diff --git a/.github/workflows/release.yaml b/.github/workflows/release.yaml index 7f27f34fa..0e2d0c416 100644 --- a/.github/workflows/release.yaml +++ b/.github/workflows/release.yaml @@ -24,9 +24,7 @@ jobs: - name: Run Keyword Replacement Script ## Replace keyword 'code' with '_code' (Microchip MCUs) - run: | - python -u scripts/keyword_replace.py "code" "_code" "thirdparty/ethernet/cyclonetcp" "cp1252" - python -u scripts/keyword_replace.py "code" "_code" "thirdparty/lvgl" "UTF-8" + run: python -u scripts/keyword_replace.py "code" "_code" "thirdparty/ethernet/cyclonetcp" "cp1252" - name: Run Package Script run: python -u scripts/package.py ${{ secrets.GITHUB_TOKEN }} ${{ github.repository }} diff --git a/bsp/board/include/boards/board_arduino_mega_2560_rev3/board.cmake b/bsp/board/include/boards/board_arduino_mega_2560_rev3/board.cmake new file mode 100644 index 000000000..ed759196a --- /dev/null +++ b/bsp/board/include/boards/board_arduino_mega_2560_rev3/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "BOARD_ARDUINO_MEGA_2560_REV3") + set(BOARD_PATH "include/boards/board_arduino_mega_2560_rev3") + set(MCU_CARD FALSE) + set(SHIELD TRUE) +endif() diff --git a/bsp/board/include/boards/board_arduino_uno_rev3/board.cmake b/bsp/board/include/boards/board_arduino_uno_rev3/board.cmake new file mode 100644 index 000000000..88e2ac335 --- /dev/null +++ b/bsp/board/include/boards/board_arduino_uno_rev3/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "BOARD_ARDUINO_UNO_REV3") + set(BOARD_PATH "include/boards/board_arduino_uno_rev3") + set(MCU_CARD FALSE) + set(SHIELD TRUE) +endif() diff --git a/bsp/board/include/boards/board_curiosity_hpc/board.cmake b/bsp/board/include/boards/board_curiosity_hpc/board.cmake new file mode 100644 index 000000000..ccbfbecc5 --- /dev/null +++ b/bsp/board/include/boards/board_curiosity_hpc/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "BOARD_CURIOSITY_HPC") + set(BOARD_PATH "include/boards/board_curiosity_hpc") + set(MCU_CARD FALSE) + set(DIP_SOCKET TRUE) +endif() diff --git a/bsp/board/include/boards/board_curiosity_nano_with_pic18f47k42/board.cmake b/bsp/board/include/boards/board_curiosity_nano_with_pic18f47k42/board.cmake new file mode 100644 index 000000000..a8f045d7b --- /dev/null +++ b/bsp/board/include/boards/board_curiosity_nano_with_pic18f47k42/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "BOARD_CURIOSITY_NANO_WITH_PIC18F47K42") + set(BOARD_PATH "include/boards/board_curiosity_nano_with_pic18f47k42") + set(MCU_CARD FALSE) + set(SHIELD TRUE) +endif() diff --git a/bsp/board/include/boards/board_curiosity_nano_with_pic18f47q10/board.cmake b/bsp/board/include/boards/board_curiosity_nano_with_pic18f47q10/board.cmake new file mode 100644 index 000000000..e335f7fe6 --- /dev/null +++ b/bsp/board/include/boards/board_curiosity_nano_with_pic18f47q10/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "BOARD_CURIOSITY_NANO_WITH_PIC18F47Q10") + set(BOARD_PATH "include/boards/board_curiosity_nano_with_pic18f47q10") + set(MCU_CARD FALSE) + set(SHIELD TRUE) +endif() diff --git a/bsp/board/include/boards/board_curiosity_nano_with_pic18f57q43/board.cmake b/bsp/board/include/boards/board_curiosity_nano_with_pic18f57q43/board.cmake new file mode 100644 index 000000000..fbacda65c --- /dev/null +++ b/bsp/board/include/boards/board_curiosity_nano_with_pic18f57q43/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "BOARD_CURIOSITY_NANO_WITH_PIC18F57Q43") + set(BOARD_PATH "include/boards/board_curiosity_nano_with_pic18f57q43") + set(MCU_CARD FALSE) + set(SHIELD TRUE) +endif() diff --git a/bsp/board/include/boards/board_curiosity_pic24fj256ga7/board.cmake b/bsp/board/include/boards/board_curiosity_pic24fj256ga7/board.cmake new file mode 100644 index 000000000..d0ff801a6 --- /dev/null +++ b/bsp/board/include/boards/board_curiosity_pic24fj256ga7/board.cmake @@ -0,0 +1,4 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "BOARD_CURIOSITY_PIC24FJ256GA7") + set(BOARD_PATH "include/boards/board_curiosity_pic24fj256ga7") + set(MCU_CARD FALSE) +endif() diff --git a/bsp/board/include/boards/board_curiosity_pic32_mz_ef/board.cmake b/bsp/board/include/boards/board_curiosity_pic32_mz_ef/board.cmake new file mode 100644 index 000000000..156548451 --- /dev/null +++ b/bsp/board/include/boards/board_curiosity_pic32_mz_ef/board.cmake @@ -0,0 +1,4 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "BOARD_CURIOSITY_PIC32MZ_EF") + set(BOARD_PATH "include/boards/board_curiosity_pic32_mz_ef") + set(MCU_CARD FALSE) +endif() diff --git a/bsp/board/include/boards/board_discovery_with_stm32f303vc/board.cmake b/bsp/board/include/boards/board_discovery_with_stm32f303vc/board.cmake new file mode 100644 index 000000000..2c4356276 --- /dev/null +++ b/bsp/board/include/boards/board_discovery_with_stm32f303vc/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "KIT_DISCOVERY_WITH_STM32F303VC_MCU") + set(BOARD_PATH "include/boards/board_discovery_with_stm32f303vc") + set(MCU_CARD FALSE) + set(SHIELD TRUE) +endif() diff --git a/bsp/board/include/boards/board_discovery_with_stm32f407vg/board.cmake b/bsp/board/include/boards/board_discovery_with_stm32f407vg/board.cmake new file mode 100644 index 000000000..35644eefc --- /dev/null +++ b/bsp/board/include/boards/board_discovery_with_stm32f407vg/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "KIT_DISCOVERY_WITH_STM32F407VG_MCU") + set(BOARD_PATH "include/boards/board_discovery_with_stm32f407vg") + set(MCU_CARD FALSE) + set(SHIELD TRUE) +endif() diff --git a/bsp/board/include/boards/board_easy24_33_v6/board.cmake b/bsp/board/include/boards/board_easy24_33_v6/board.cmake new file mode 100644 index 000000000..ea8ad3a5d --- /dev/null +++ b/bsp/board/include/boards/board_easy24_33_v6/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "EASY24_33_V6") + set(BOARD_PATH "include/boards/board_easy24_33_v6") + set(MCU_CARD FALSE) + set(DIP_SOCKET FALSE) +endif() diff --git a/bsp/board/include/boards/board_easyavr_pro_v8/board.cmake b/bsp/board/include/boards/board_easyavr_pro_v8/board.cmake new file mode 100644 index 000000000..352a44571 --- /dev/null +++ b/bsp/board/include/boards/board_easyavr_pro_v8/board.cmake @@ -0,0 +1,3 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "BOARD_EASYAVR_PRO_V8") + set(BOARD_PATH "include/boards/board_easyavr_pro_v8") +endif() diff --git a/bsp/board/include/boards/board_easyavr_v7/board.cmake b/bsp/board/include/boards/board_easyavr_v7/board.cmake new file mode 100644 index 000000000..2d2df79fb --- /dev/null +++ b/bsp/board/include/boards/board_easyavr_v7/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "BOARD_EASYAVR_V7") + set(BOARD_PATH "include/boards/board_easyavr_v7") + set(MCU_CARD FALSE) + set(DIP_SOCKET TRUE) +endif() diff --git a/bsp/board/include/boards/board_easyavr_v8/board.cmake b/bsp/board/include/boards/board_easyavr_v8/board.cmake new file mode 100644 index 000000000..f4d15df71 --- /dev/null +++ b/bsp/board/include/boards/board_easyavr_v8/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "BOARD_EASYAVR_V8") + set(BOARD_PATH "include/boards/board_easyavr_v8") + set(MCU_CARD FALSE) + set(DIP_SOCKET TRUE) +endif() diff --git a/bsp/board/include/boards/board_easyavr_v8/board.h b/bsp/board/include/boards/board_easyavr_v8/board.h new file mode 100644 index 000000000..f0bdc3c13 --- /dev/null +++ b/bsp/board/include/boards/board_easyavr_v8/board.h @@ -0,0 +1,191 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file board.h + * @brief Main board pin mapping. + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// Hardware revision number +#define BOARD_REV_MAJOR (1) +#define BOARD_REV_MINOR (01) + +#define BOARD_NAME "EasyAVR v8" + +#include "dip_socket.h" +#include "mikrobus.h" + +/// Mapping +#define MIKROBUS_1 1 +#define MIKROBUS_1_AN MIKROBUS_1_DIP_AN +#define MIKROBUS_1_RST MIKROBUS_1_DIP_RST +#define MIKROBUS_1_CS MIKROBUS_1_DIP_CS +#define MIKROBUS_1_SCK MIKROBUS_1_DIP_SCK +#define MIKROBUS_1_MISO MIKROBUS_1_DIP_MISO +#define MIKROBUS_1_MOSI MIKROBUS_1_DIP_MOSI +#define MIKROBUS_1_PWM MIKROBUS_1_DIP_PWM +#define MIKROBUS_1_INT MIKROBUS_1_DIP_INT +#define MIKROBUS_1_RX MIKROBUS_1_DIP_RX +#define MIKROBUS_1_TX MIKROBUS_1_DIP_TX +#define MIKROBUS_1_SCL MIKROBUS_1_DIP_SCL +#define MIKROBUS_1_SDA MIKROBUS_1_DIP_SDA + +#define MIKROBUS_2 2 +#define MIKROBUS_2_AN MIKROBUS_2_DIP_AN +#define MIKROBUS_2_RST MIKROBUS_2_DIP_RST +#define MIKROBUS_2_CS MIKROBUS_2_DIP_CS +#define MIKROBUS_2_SCK MIKROBUS_2_DIP_SCK +#define MIKROBUS_2_MISO MIKROBUS_2_DIP_MISO +#define MIKROBUS_2_MOSI MIKROBUS_2_DIP_MOSI +#define MIKROBUS_2_PWM MIKROBUS_2_DIP_PWM +#define MIKROBUS_2_INT MIKROBUS_2_DIP_INT +#define MIKROBUS_2_RX MIKROBUS_2_DIP_RX +#define MIKROBUS_2_TX MIKROBUS_2_DIP_TX +#define MIKROBUS_2_SCL MIKROBUS_2_DIP_SCL +#define MIKROBUS_2_SDA MIKROBUS_2_DIP_SDA + +#define MIKROBUS_3 3 +#define MIKROBUS_3_AN MIKROBUS_3_DIP_AN +#define MIKROBUS_3_RST MIKROBUS_3_DIP_RST +#define MIKROBUS_3_CS MIKROBUS_3_DIP_CS +#define MIKROBUS_3_SCK MIKROBUS_3_DIP_SCK +#define MIKROBUS_3_MISO MIKROBUS_3_DIP_MISO +#define MIKROBUS_3_MOSI MIKROBUS_3_DIP_MOSI +#define MIKROBUS_3_PWM MIKROBUS_3_DIP_PWM +#define MIKROBUS_3_INT MIKROBUS_3_DIP_INT +#define MIKROBUS_3_RX MIKROBUS_3_DIP_RX +#define MIKROBUS_3_TX MIKROBUS_3_DIP_TX +#define MIKROBUS_3_SCL MIKROBUS_3_DIP_SCL +#define MIKROBUS_3_SDA MIKROBUS_3_DIP_SDA + +#define MIKROBUS_4 4 +#define MIKROBUS_4_AN MIKROBUS_4_DIP_AN +#define MIKROBUS_4_RST MIKROBUS_4_DIP_RST +#define MIKROBUS_4_CS MIKROBUS_4_DIP_CS +#define MIKROBUS_4_SCK MIKROBUS_4_DIP_SCK +#define MIKROBUS_4_MISO MIKROBUS_4_DIP_MISO +#define MIKROBUS_4_MOSI MIKROBUS_4_DIP_MOSI +#define MIKROBUS_4_PWM MIKROBUS_4_DIP_PWM +#define MIKROBUS_4_INT MIKROBUS_4_DIP_INT +#define MIKROBUS_4_RX MIKROBUS_4_DIP_RX +#define MIKROBUS_4_TX MIKROBUS_4_DIP_TX +#define MIKROBUS_4_SCL MIKROBUS_4_DIP_SCL +#define MIKROBUS_4_SDA MIKROBUS_4_DIP_SDA + +#define MIKROBUS_5 5 +#define MIKROBUS_5_AN MIKROBUS_5_DIP_AN +#define MIKROBUS_5_RST MIKROBUS_5_DIP_RST +#define MIKROBUS_5_CS MIKROBUS_5_DIP_CS +#define MIKROBUS_5_SCK MIKROBUS_5_DIP_SCK +#define MIKROBUS_5_MISO MIKROBUS_5_DIP_MISO +#define MIKROBUS_5_MOSI MIKROBUS_5_DIP_MOSI +#define MIKROBUS_5_PWM MIKROBUS_5_DIP_PWM +#define MIKROBUS_5_INT MIKROBUS_5_DIP_INT +#define MIKROBUS_5_RX MIKROBUS_5_DIP_RX +#define MIKROBUS_5_TX MIKROBUS_5_DIP_TX +#define MIKROBUS_5_SCL MIKROBUS_5_DIP_SCL +#define MIKROBUS_5_SDA MIKROBUS_5_DIP_SDA + +#define USB_UART_TX USB_UART_DIP_TX +#define USB_UART_RX USB_UART_DIP_RX + +#define LCD_CS1 PB0 +#define LCD_CS2 PB1 +#define LCD_RS PA2 +#define LCD_E PD6 +#define LCD_D4 PC4 +#define LCD_D5 PC5 +#define LCD_D6 PC6 +#define LCD_D7 PC7 +#define LCD_BPWM PD5 + +#define TFT_CS1 PB0 +#define TFT_CS2 PB1 +#define TFT_RS PA2 +#define TFT_R_W PA3 +#define TFT_E PD6 +#define TFT_D0 PC0 +#define TFT_D1 PC1 +#define TFT_D2 PC2 +#define TFT_D3 PC3 +#define TFT_D4 PC4 +#define TFT_D5 PC5 +#define TFT_D6 PC6 +#define TFT_D7 PC7 +#define TFT_RST PD7 +#define TFT_BPWM PD5 + +#define TFT_RD TFT_CS1 +#define TFT_WR TFT_CS2 +#define TFT_CS TFT_E + +#define TP_MIKROE_XL PA1 +#define TP_MIKROE_XR PA2 +#define TP_MIKROE_YU PA3 +#define TP_MIKROE_YD PA0 + +// Default TP_MIKROE touch panel calibration values. +#define TP_MIKROE_CALIBRATION_XMIN 120 +#define TP_MIKROE_CALIBRATION_XMAX 910 +#define TP_MIKROE_CALIBRATION_YMIN 78 +#define TP_MIKROE_CALIBRATION_YMAX 945 + +#define TP_MIKROE_PRESSURE_THRESHOLD_LOWER (70) +#define TP_MIKROE_PRESSURE_THRESHOLD_UPPER (1000) + +#define TFT_8BIT_DATA_PORT_CH0 PORT_C +#define TFT_8BIT_DATA_PORT_CH0_MASK 0xFF + +#define TFT_16BIT_DATA_PORT_CH0 HAL_PORT_NC +#define TFT_16BIT_DATA_PORT_CH0_MASK 0x0000 + +#define TFT_16BIT_DATA_PORT_CH1 HAL_PORT_NC +#define TFT_16BIT_DATA_PORT_CH1_MASK 0x0000 +#ifdef __cplusplus +} +#endif + +#endif // _BOARD_H_ +// ------------------------------------------------------------------------- END diff --git a/bsp/board/include/boards/board_easyavr_v8/dip_sockets/dip14/dip_socket.h b/bsp/board/include/boards/board_easyavr_v8/dip_sockets/dip14/dip_socket.h new file mode 100644 index 000000000..58377d7f2 --- /dev/null +++ b/bsp/board/include/boards/board_easyavr_v8/dip_sockets/dip14/dip_socket.h @@ -0,0 +1,127 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file dip_socket.h + * @brief Dip socket mikrobus pin mapping. + */ + +#ifndef _DIP_SOCKET_H_ +#define _DIP_SOCKET_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_target.h" + +/// Mapping +#define MIKROBUS_1_DIP_AN PA7 +#define MIKROBUS_1_DIP_RST PA4 +#define MIKROBUS_1_DIP_CS // Pin not routed to mikroBUS. +#define MIKROBUS_1_DIP_SCK // Pin not routed to mikroBUS. +#define MIKROBUS_1_DIP_MISO // Pin not routed to mikroBUS. +#define MIKROBUS_1_DIP_MOSI // Pin not routed to mikroBUS. +#define MIKROBUS_1_DIP_PWM // Pin not routed to mikroBUS. +#define MIKROBUS_1_DIP_INT // Pin not routed to mikroBUS. +#define MIKROBUS_1_DIP_RX // Pin not routed to mikroBUS. +#define MIKROBUS_1_DIP_TX // Pin not routed to mikroBUS. +#define MIKROBUS_1_DIP_SCL // Pin not routed to mikroBUS. +#define MIKROBUS_1_DIP_SDA // Pin not routed to mikroBUS. + +#define MIKROBUS_2_DIP_AN PA3 +#define MIKROBUS_2_DIP_RST PA0 +#define MIKROBUS_2_DIP_CS PA1 +#define MIKROBUS_2_DIP_SCK // Pin not routed to mikroBUS. +#define MIKROBUS_2_DIP_MISO // Pin not routed to mikroBUS. +#define MIKROBUS_2_DIP_MOSI // Pin not routed to mikroBUS. +#define MIKROBUS_2_DIP_PWM // Pin not routed to mikroBUS. +#define MIKROBUS_2_DIP_INT // Pin not routed to mikroBUS. +#define MIKROBUS_2_DIP_RX // Pin not routed to mikroBUS. +#define MIKROBUS_2_DIP_TX // Pin not routed to mikroBUS. +#define MIKROBUS_2_DIP_SCL // Pin not routed to mikroBUS. +#define MIKROBUS_2_DIP_SDA // Pin not routed to mikroBUS. + +#define MIKROBUS_3_DIP_AN // Pin not routed to mikroBUS. +#define MIKROBUS_3_DIP_RST // Pin not routed to mikroBUS. +#define MIKROBUS_3_DIP_CS PB2 +#define MIKROBUS_3_DIP_SCK // Pin not routed to mikroBUS. +#define MIKROBUS_3_DIP_MISO PB3 +#define MIKROBUS_3_DIP_MOSI // Pin not routed to mikroBUS. +#define MIKROBUS_3_DIP_PWM // Pin not routed to mikroBUS. +#define MIKROBUS_3_DIP_INT // Pin not routed to mikroBUS. +#define MIKROBUS_3_DIP_RX // Pin not routed to mikroBUS. +#define MIKROBUS_3_DIP_TX // Pin not routed to mikroBUS. +#define MIKROBUS_3_DIP_SCL // Pin not routed to mikroBUS. +#define MIKROBUS_3_DIP_SDA // Pin not routed to mikroBUS. + +#define MIKROBUS_4_DIP_AN PA3 +#define MIKROBUS_4_DIP_RST // Pin not routed to mikroBUS. +#define MIKROBUS_4_DIP_CS PA5 +#define MIKROBUS_4_DIP_SCK PB2 +#define MIKROBUS_4_DIP_MISO PB1 +#define MIKROBUS_4_DIP_MOSI PB0 +#define MIKROBUS_4_DIP_PWM PB3 +#define MIKROBUS_4_DIP_INT // Pin not routed to mikroBUS. +#define MIKROBUS_4_DIP_RX // Pin not routed to mikroBUS. +#define MIKROBUS_4_DIP_TX // Pin not routed to mikroBUS. +#define MIKROBUS_4_DIP_SCL PA2 +#define MIKROBUS_4_DIP_SDA PA0 + +#define MIKROBUS_5_DIP_AN PB1 +#define MIKROBUS_5_DIP_RST // Pin not routed to mikroBUS. +#define MIKROBUS_5_DIP_CS PA3 +#define MIKROBUS_5_DIP_SCK PA4 +#define MIKROBUS_5_DIP_MISO PA5 +#define MIKROBUS_5_DIP_MOSI PA6 +#define MIKROBUS_5_DIP_PWM // Pin not routed to mikroBUS. +#define MIKROBUS_5_DIP_INT PB2 +#define MIKROBUS_5_DIP_RX // Pin not routed to mikroBUS. +#define MIKROBUS_5_DIP_TX // Pin not routed to mikroBUS. +#define MIKROBUS_5_DIP_SCL // Pin not routed to mikroBUS. +#define MIKROBUS_5_DIP_SDA // Pin not routed to mikroBUS. + +#define USB_UART_DIP_TX // UART not supported +#define USB_UART_DIP_RX // UART not supported + +#ifdef __cplusplus +} +#endif + +#endif // _DIP_SOCKET_H_ +// ------------------------------------------------------------------------- END diff --git a/bsp/board/include/boards/board_easyavr_v8/dip_sockets/dip20/dip_socket.h b/bsp/board/include/boards/board_easyavr_v8/dip_sockets/dip20/dip_socket.h new file mode 100644 index 000000000..82b6978a2 --- /dev/null +++ b/bsp/board/include/boards/board_easyavr_v8/dip_sockets/dip20/dip_socket.h @@ -0,0 +1,58 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file dip_socket.h + * @brief Dip socket mikrobus pin mapping. + */ + +#ifndef _DIP_SOCKET_H_ +#define _DIP_SOCKET_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "dip20b/dip_socket.h" + +#ifdef __cplusplus +} +#endif + +#endif // _DIP_SOCKET_H_ +// ------------------------------------------------------------------------- END diff --git a/bsp/board/include/boards/board_easyavr_v8/dip_sockets/dip20a/dip_socket.h b/bsp/board/include/boards/board_easyavr_v8/dip_sockets/dip20a/dip_socket.h new file mode 100644 index 000000000..79b401fbe --- /dev/null +++ b/bsp/board/include/boards/board_easyavr_v8/dip_sockets/dip20a/dip_socket.h @@ -0,0 +1,127 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file dip_socket.h + * @brief Dip socket mikrobus pin mapping. + */ + +#ifndef _DIP_SOCKET_H_ +#define _DIP_SOCKET_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_target.h" + +/// Mapping +#define MIKROBUS_1_DIP_AN // Pin not routed to mikroBUS. +#define MIKROBUS_1_DIP_RST // Pin not routed to mikroBUS. +#define MIKROBUS_1_DIP_CS PB4 +#define MIKROBUS_1_DIP_SCK PB7 +#define MIKROBUS_1_DIP_MISO PB6 +#define MIKROBUS_1_DIP_MOSI PB5 +#define MIKROBUS_1_DIP_PWM PD4 +#define MIKROBUS_1_DIP_INT PD2 +#define MIKROBUS_1_DIP_RX PD0 +#define MIKROBUS_1_DIP_TX PD1 +#define MIKROBUS_1_DIP_SCL // Pin not routed to mikroBUS. +#define MIKROBUS_1_DIP_SDA // Pin not routed to mikroBUS. + +#define MIKROBUS_2_DIP_AN // Pin not routed to mikroBUS. +#define MIKROBUS_2_DIP_RST PA0 +#define MIKROBUS_2_DIP_CS PA1 +#define MIKROBUS_2_DIP_SCK PB7 +#define MIKROBUS_2_DIP_MISO PB6 +#define MIKROBUS_2_DIP_MOSI PB5 +#define MIKROBUS_2_DIP_PWM PD5 +#define MIKROBUS_2_DIP_INT PD3 +#define MIKROBUS_2_DIP_RX PD0 +#define MIKROBUS_2_DIP_TX PD1 +#define MIKROBUS_2_DIP_SCL // Pin not routed to mikroBUS. +#define MIKROBUS_2_DIP_SDA // Pin not routed to mikroBUS. + +#define MIKROBUS_3_DIP_AN // Pin not routed to mikroBUS. +#define MIKROBUS_3_DIP_RST PD3 +#define MIKROBUS_3_DIP_CS PB2 +#define MIKROBUS_3_DIP_SCK PB5 +#define MIKROBUS_3_DIP_MISO PB4 +#define MIKROBUS_3_DIP_MOSI PB3 +#define MIKROBUS_3_DIP_PWM PD6 +#define MIKROBUS_3_DIP_INT PD2 +#define MIKROBUS_3_DIP_RX PD0 +#define MIKROBUS_3_DIP_TX PD1 +#define MIKROBUS_3_DIP_SCL // Pin not routed to mikroBUS. +#define MIKROBUS_3_DIP_SDA // Pin not routed to mikroBUS. + +#define MIKROBUS_4_DIP_AN // Pin not routed to mikroBUS. +#define MIKROBUS_4_DIP_RST PB5 +#define MIKROBUS_4_DIP_CS PA5 +#define MIKROBUS_4_DIP_SCK PB2 +#define MIKROBUS_4_DIP_MISO PB1 +#define MIKROBUS_4_DIP_MOSI PB0 +#define MIKROBUS_4_DIP_PWM PB3 +#define MIKROBUS_4_DIP_INT PB6 +#define MIKROBUS_4_DIP_RX PD2 +#define MIKROBUS_4_DIP_TX PD3 +#define MIKROBUS_4_DIP_SCL // Pin not routed to mikroBUS. +#define MIKROBUS_4_DIP_SDA // Pin not routed to mikroBUS. + +#define MIKROBUS_5_DIP_AN PB1 +#define MIKROBUS_5_DIP_RST // Pin not routed to mikroBUS. +#define MIKROBUS_5_DIP_CS // Pin not routed to mikroBUS. +#define MIKROBUS_5_DIP_SCK // Pin not routed to mikroBUS. +#define MIKROBUS_5_DIP_MISO // Pin not routed to mikroBUS. +#define MIKROBUS_5_DIP_MOSI // Pin not routed to mikroBUS. +#define MIKROBUS_5_DIP_PWM // Pin not routed to mikroBUS. +#define MIKROBUS_5_DIP_INT PB2 +#define MIKROBUS_5_DIP_RX // Pin not routed to mikroBUS. +#define MIKROBUS_5_DIP_TX // Pin not routed to mikroBUS. +#define MIKROBUS_5_DIP_SCL // Pin not routed to mikroBUS. +#define MIKROBUS_5_DIP_SDA // Pin not routed to mikroBUS. + +#define USB_UART_DIP_TX PD1 +#define USB_UART_DIP_RX PD0 + +#ifdef __cplusplus +} +#endif + +#endif // _DIP_SOCKET_H_ +// ------------------------------------------------------------------------- END diff --git a/bsp/board/include/boards/board_easyavr_v8/dip_sockets/dip20b/dip_socket.h b/bsp/board/include/boards/board_easyavr_v8/dip_sockets/dip20b/dip_socket.h new file mode 100644 index 000000000..939e51fde --- /dev/null +++ b/bsp/board/include/boards/board_easyavr_v8/dip_sockets/dip20b/dip_socket.h @@ -0,0 +1,127 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file dip_socket.h + * @brief Dip socket mikrobus pin mapping. + */ + +#ifndef _DIP_SOCKET_H_ +#define _DIP_SOCKET_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_target.h" + +/// Mapping +#define MIKROBUS_1_DIP_AN PA7 +#define MIKROBUS_1_DIP_RST PA4 +#define MIKROBUS_1_DIP_CS PB4 +#define MIKROBUS_1_DIP_SCK PB7 +#define MIKROBUS_1_DIP_MISO PB6 +#define MIKROBUS_1_DIP_MOSI PB5 +#define MIKROBUS_1_DIP_PWM // Pin not routed to mikroBUS. +#define MIKROBUS_1_DIP_INT // Pin not routed to mikroBUS. +#define MIKROBUS_1_DIP_RX // Pin not routed to mikroBUS. +#define MIKROBUS_1_DIP_TX // Pin not routed to mikroBUS. +#define MIKROBUS_1_DIP_SCL // Pin not routed to mikroBUS. +#define MIKROBUS_1_DIP_SDA // Pin not routed to mikroBUS. + +#define MIKROBUS_2_DIP_AN PA3 +#define MIKROBUS_2_DIP_RST PA0 +#define MIKROBUS_2_DIP_CS PA1 +#define MIKROBUS_2_DIP_SCK PB7 +#define MIKROBUS_2_DIP_MISO PB6 +#define MIKROBUS_2_DIP_MOSI PB5 +#define MIKROBUS_2_DIP_PWM // Pin not routed to mikroBUS. +#define MIKROBUS_2_DIP_INT // Pin not routed to mikroBUS. +#define MIKROBUS_2_DIP_RX // Pin not routed to mikroBUS. +#define MIKROBUS_2_DIP_TX // Pin not routed to mikroBUS. +#define MIKROBUS_2_DIP_SCL // Pin not routed to mikroBUS. +#define MIKROBUS_2_DIP_SDA // Pin not routed to mikroBUS. + +#define MIKROBUS_3_DIP_AN // Pin not routed to mikroBUS. +#define MIKROBUS_3_DIP_RST // Pin not routed to mikroBUS. +#define MIKROBUS_3_DIP_CS PB2 +#define MIKROBUS_3_DIP_SCK PB5 +#define MIKROBUS_3_DIP_MISO PB4 +#define MIKROBUS_3_DIP_MOSI PB3 +#define MIKROBUS_3_DIP_PWM // Pin not routed to mikroBUS. +#define MIKROBUS_3_DIP_INT // Pin not routed to mikroBUS. +#define MIKROBUS_3_DIP_RX // Pin not routed to mikroBUS. +#define MIKROBUS_3_DIP_TX // Pin not routed to mikroBUS. +#define MIKROBUS_3_DIP_SCL // Pin not routed to mikroBUS. +#define MIKROBUS_3_DIP_SDA // Pin not routed to mikroBUS. + +#define MIKROBUS_4_DIP_AN PA3 +#define MIKROBUS_4_DIP_RST PB5 +#define MIKROBUS_4_DIP_CS PA5 +#define MIKROBUS_4_DIP_SCK PB2 +#define MIKROBUS_4_DIP_MISO PB1 +#define MIKROBUS_4_DIP_MOSI PB0 +#define MIKROBUS_4_DIP_PWM PB3 +#define MIKROBUS_4_DIP_INT PB6 +#define MIKROBUS_4_DIP_RX // Pin not routed to mikroBUS. +#define MIKROBUS_4_DIP_TX // Pin not routed to mikroBUS. +#define MIKROBUS_4_DIP_SCL PA2 +#define MIKROBUS_4_DIP_SDA PA0 + +#define MIKROBUS_5_DIP_AN PB1 +#define MIKROBUS_5_DIP_RST // Pin not routed to mikroBUS. +#define MIKROBUS_5_DIP_CS PA3 +#define MIKROBUS_5_DIP_SCK PA4 +#define MIKROBUS_5_DIP_MISO PA5 +#define MIKROBUS_5_DIP_MOSI PA6 +#define MIKROBUS_5_DIP_PWM // Pin not routed to mikroBUS. +#define MIKROBUS_5_DIP_INT PB2 +#define MIKROBUS_5_DIP_RX // Pin not routed to mikroBUS. +#define MIKROBUS_5_DIP_TX // Pin not routed to mikroBUS. +#define MIKROBUS_5_DIP_SCL // Pin not routed to mikroBUS. +#define MIKROBUS_5_DIP_SDA // Pin not routed to mikroBUS. + +#define USB_UART_DIP_TX // UART not supported +#define USB_UART_DIP_RX // UART not supported + +#ifdef __cplusplus +} +#endif + +#endif // _DIP_SOCKET_H_ +// ------------------------------------------------------------------------- END diff --git a/bsp/board/include/boards/board_easyavr_v8/dip_sockets/dip28/dip_socket.h b/bsp/board/include/boards/board_easyavr_v8/dip_sockets/dip28/dip_socket.h new file mode 100644 index 000000000..2e054fcae --- /dev/null +++ b/bsp/board/include/boards/board_easyavr_v8/dip_sockets/dip28/dip_socket.h @@ -0,0 +1,58 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file dip_socket.h + * @brief Dip socket mikrobus pin mapping. + */ + +#ifndef _DIP_SOCKET_H_ +#define _DIP_SOCKET_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "dip28b/dip_socket.h" + +#ifdef __cplusplus +} +#endif + +#endif // _DIP_SOCKET_H_ +// ------------------------------------------------------------------------- END diff --git a/bsp/board/include/boards/board_easyavr_v8/dip_sockets/dip28a/dip_socket.h b/bsp/board/include/boards/board_easyavr_v8/dip_sockets/dip28a/dip_socket.h new file mode 100644 index 000000000..f373617cd --- /dev/null +++ b/bsp/board/include/boards/board_easyavr_v8/dip_sockets/dip28a/dip_socket.h @@ -0,0 +1,127 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file dip_socket.h + * @brief Dip socket mikrobus pin mapping. + */ + +#ifndef _DIP_SOCKET_H_ +#define _DIP_SOCKET_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_target.h" + +/// Mapping +#define MIKROBUS_1_DIP_AN // Pin not routed to mikroBUS. +#define MIKROBUS_1_DIP_RST // Pin not routed to mikroBUS. +#define MIKROBUS_1_DIP_CS PB4 +#define MIKROBUS_1_DIP_SCK PB7 +#define MIKROBUS_1_DIP_MISO PB6 +#define MIKROBUS_1_DIP_MOSI PB5 +#define MIKROBUS_1_DIP_PWM PD4 +#define MIKROBUS_1_DIP_INT PD2 +#define MIKROBUS_1_DIP_RX PD0 +#define MIKROBUS_1_DIP_TX PD1 +#define MIKROBUS_1_DIP_SCL PC0 +#define MIKROBUS_1_DIP_SDA PC1 + +#define MIKROBUS_2_DIP_AN // Pin not routed to mikroBUS. +#define MIKROBUS_2_DIP_RST // Pin not routed to mikroBUS. +#define MIKROBUS_2_DIP_CS // Pin not routed to mikroBUS. +#define MIKROBUS_2_DIP_SCK PB7 +#define MIKROBUS_2_DIP_MISO PB6 +#define MIKROBUS_2_DIP_MOSI PB5 +#define MIKROBUS_2_DIP_PWM PD5 +#define MIKROBUS_2_DIP_INT PD3 +#define MIKROBUS_2_DIP_RX PD0 +#define MIKROBUS_2_DIP_TX PD1 +#define MIKROBUS_2_DIP_SCL PC0 +#define MIKROBUS_2_DIP_SDA PC1 + +#define MIKROBUS_3_DIP_AN PC2 +#define MIKROBUS_3_DIP_RST PD3 +#define MIKROBUS_3_DIP_CS PB2 +#define MIKROBUS_3_DIP_SCK PB5 +#define MIKROBUS_3_DIP_MISO PB4 +#define MIKROBUS_3_DIP_MOSI PB3 +#define MIKROBUS_3_DIP_PWM PD6 +#define MIKROBUS_3_DIP_INT PD2 +#define MIKROBUS_3_DIP_RX PD0 +#define MIKROBUS_3_DIP_TX PD1 +#define MIKROBUS_3_DIP_SCL PC5 +#define MIKROBUS_3_DIP_SDA PC4 + +#define MIKROBUS_4_DIP_AN // Pin not routed to mikroBUS. +#define MIKROBUS_4_DIP_RST PB5 +#define MIKROBUS_4_DIP_CS // Pin not routed to mikroBUS. +#define MIKROBUS_4_DIP_SCK PB2 +#define MIKROBUS_4_DIP_MISO PB1 +#define MIKROBUS_4_DIP_MOSI PB0 +#define MIKROBUS_4_DIP_PWM PB3 +#define MIKROBUS_4_DIP_INT PB6 +#define MIKROBUS_4_DIP_RX PD2 +#define MIKROBUS_4_DIP_TX PD3 +#define MIKROBUS_4_DIP_SCL // Pin not routed to mikroBUS. +#define MIKROBUS_4_DIP_SDA // Pin not routed to mikroBUS. + +#define MIKROBUS_5_DIP_AN PB1 +#define MIKROBUS_5_DIP_RST PC6 +#define MIKROBUS_5_DIP_CS // Pin not routed to mikroBUS. +#define MIKROBUS_5_DIP_SCK // Pin not routed to mikroBUS. +#define MIKROBUS_5_DIP_MISO // Pin not routed to mikroBUS. +#define MIKROBUS_5_DIP_MOSI // Pin not routed to mikroBUS. +#define MIKROBUS_5_DIP_PWM PC7 +#define MIKROBUS_5_DIP_INT PB2 +#define MIKROBUS_5_DIP_RX PC1 +#define MIKROBUS_5_DIP_TX PC0 +#define MIKROBUS_5_DIP_SCL PC3 +#define MIKROBUS_5_DIP_SDA PC2 + +#define USB_UART_DIP_TX PD1 +#define USB_UART_DIP_RX PD0 + +#ifdef __cplusplus +} +#endif + +#endif // _DIP_SOCKET_H_ +// ------------------------------------------------------------------------- END diff --git a/bsp/board/include/boards/board_easyavr_v8/dip_sockets/dip28b/dip_socket.h b/bsp/board/include/boards/board_easyavr_v8/dip_sockets/dip28b/dip_socket.h new file mode 100644 index 000000000..73277bb3f --- /dev/null +++ b/bsp/board/include/boards/board_easyavr_v8/dip_sockets/dip28b/dip_socket.h @@ -0,0 +1,127 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file dip_socket.h + * @brief Dip socket mikrobus pin mapping. + */ + +#ifndef _DIP_SOCKET_H_ +#define _DIP_SOCKET_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_target.h" + +/// Mapping +#define MIKROBUS_1_DIP_AN PA7 +#define MIKROBUS_1_DIP_RST PA4 +#define MIKROBUS_1_DIP_CS // Pin not routed to mikroBUS. +#define MIKROBUS_1_DIP_SCK // Pin not routed to mikroBUS. +#define MIKROBUS_1_DIP_MISO // Pin not routed to mikroBUS. +#define MIKROBUS_1_DIP_MOSI // Pin not routed to mikroBUS. +#define MIKROBUS_1_DIP_PWM PD4 +#define MIKROBUS_1_DIP_INT PD2 +#define MIKROBUS_1_DIP_RX PD0 +#define MIKROBUS_1_DIP_TX PD1 +#define MIKROBUS_1_DIP_SCL PC0 +#define MIKROBUS_1_DIP_SDA PC1 + +#define MIKROBUS_2_DIP_AN PA3 +#define MIKROBUS_2_DIP_RST PA0 +#define MIKROBUS_2_DIP_CS PA1 +#define MIKROBUS_2_DIP_SCK // Pin not routed to mikroBUS. +#define MIKROBUS_2_DIP_MISO // Pin not routed to mikroBUS. +#define MIKROBUS_2_DIP_MOSI // Pin not routed to mikroBUS. +#define MIKROBUS_2_DIP_PWM PD5 +#define MIKROBUS_2_DIP_INT PD3 +#define MIKROBUS_2_DIP_RX PD0 +#define MIKROBUS_2_DIP_TX PD1 +#define MIKROBUS_2_DIP_SCL PC0 +#define MIKROBUS_2_DIP_SDA PC1 + +#define MIKROBUS_3_DIP_AN PC2 +#define MIKROBUS_3_DIP_RST PD3 +#define MIKROBUS_3_DIP_CS // Pin not routed to mikroBUS. +#define MIKROBUS_3_DIP_SCK // Pin not routed to mikroBUS. +#define MIKROBUS_3_DIP_MISO // Pin not routed to mikroBUS. +#define MIKROBUS_3_DIP_MOSI // Pin not routed to mikroBUS. +#define MIKROBUS_3_DIP_PWM PD6 +#define MIKROBUS_3_DIP_INT PD2 +#define MIKROBUS_3_DIP_RX PD0 +#define MIKROBUS_3_DIP_TX PD1 +#define MIKROBUS_3_DIP_SCL // Pin not routed to mikroBUS. +#define MIKROBUS_3_DIP_SDA // Pin not routed to mikroBUS. + +#define MIKROBUS_4_DIP_AN PA3 +#define MIKROBUS_4_DIP_RST // Pin not routed to mikroBUS. +#define MIKROBUS_4_DIP_CS PA5 +#define MIKROBUS_4_DIP_SCK // Pin not routed to mikroBUS. +#define MIKROBUS_4_DIP_MISO // Pin not routed to mikroBUS. +#define MIKROBUS_4_DIP_MOSI // Pin not routed to mikroBUS. +#define MIKROBUS_4_DIP_PWM // Pin not routed to mikroBUS. +#define MIKROBUS_4_DIP_INT // Pin not routed to mikroBUS. +#define MIKROBUS_4_DIP_RX PD2 +#define MIKROBUS_4_DIP_TX PD3 +#define MIKROBUS_4_DIP_SCL PA2 +#define MIKROBUS_4_DIP_SDA PA0 + +#define MIKROBUS_5_DIP_AN // Pin not routed to mikroBUS. +#define MIKROBUS_5_DIP_RST // Pin not routed to mikroBUS. +#define MIKROBUS_5_DIP_CS PA3 +#define MIKROBUS_5_DIP_SCK PA4 +#define MIKROBUS_5_DIP_MISO PA5 +#define MIKROBUS_5_DIP_MOSI PA6 +#define MIKROBUS_5_DIP_PWM // Pin not routed to mikroBUS. +#define MIKROBUS_5_DIP_INT // Pin not routed to mikroBUS. +#define MIKROBUS_5_DIP_RX PC1 +#define MIKROBUS_5_DIP_TX PC0 +#define MIKROBUS_5_DIP_SCL PC3 +#define MIKROBUS_5_DIP_SDA PC2 + +#define USB_UART_DIP_TX PC0 +#define USB_UART_DIP_RX PC1 + +#ifdef __cplusplus +} +#endif + +#endif // _DIP_SOCKET_H_ +// ------------------------------------------------------------------------- END diff --git a/bsp/board/include/boards/board_easyavr_v8/dip_sockets/dip40/dip_socket.h b/bsp/board/include/boards/board_easyavr_v8/dip_sockets/dip40/dip_socket.h new file mode 100644 index 000000000..b8a80f19f --- /dev/null +++ b/bsp/board/include/boards/board_easyavr_v8/dip_sockets/dip40/dip_socket.h @@ -0,0 +1,58 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file dip_socket.h + * @brief Dip socket mikrobus pin mapping. + */ + +#ifndef _DIP_SOCKET_H_ +#define _DIP_SOCKET_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "dip40b/dip_socket.h" + +#ifdef __cplusplus +} +#endif + +#endif // _DIP_SOCKET_H_ +// ------------------------------------------------------------------------- END diff --git a/bsp/board/include/boards/board_easyavr_v8/dip_sockets/dip40a/dip_socket.h b/bsp/board/include/boards/board_easyavr_v8/dip_sockets/dip40a/dip_socket.h new file mode 100644 index 000000000..e3fc4d74d --- /dev/null +++ b/bsp/board/include/boards/board_easyavr_v8/dip_sockets/dip40a/dip_socket.h @@ -0,0 +1,127 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file dip_socket.h + * @brief Dip socket mikrobus pin mapping. + */ + +#ifndef _DIP_SOCKET_H_ +#define _DIP_SOCKET_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_target.h" + +/// Mapping +#define MIKROBUS_1_DIP_AN PA7 +#define MIKROBUS_1_DIP_RST PA4 +#define MIKROBUS_1_DIP_CS PB4 +#define MIKROBUS_1_DIP_SCK PB7 +#define MIKROBUS_1_DIP_MISO PB6 +#define MIKROBUS_1_DIP_MOSI PB5 +#define MIKROBUS_1_DIP_PWM PD4 +#define MIKROBUS_1_DIP_INT PD2 +#define MIKROBUS_1_DIP_RX PD0 +#define MIKROBUS_1_DIP_TX PD1 +#define MIKROBUS_1_DIP_SCL PC0 +#define MIKROBUS_1_DIP_SDA PC1 + +#define MIKROBUS_2_DIP_AN PA3 +#define MIKROBUS_2_DIP_RST PA0 +#define MIKROBUS_2_DIP_CS PA1 +#define MIKROBUS_2_DIP_SCK PB7 +#define MIKROBUS_2_DIP_MISO PB6 +#define MIKROBUS_2_DIP_MOSI PB5 +#define MIKROBUS_2_DIP_PWM PD5 +#define MIKROBUS_2_DIP_INT PD3 +#define MIKROBUS_2_DIP_RX PD0 +#define MIKROBUS_2_DIP_TX PD1 +#define MIKROBUS_2_DIP_SCL PC0 +#define MIKROBUS_2_DIP_SDA PC1 + +#define MIKROBUS_3_DIP_AN PC2 +#define MIKROBUS_3_DIP_RST PD3 +#define MIKROBUS_3_DIP_CS PB2 +#define MIKROBUS_3_DIP_SCK PB5 +#define MIKROBUS_3_DIP_MISO PB4 +#define MIKROBUS_3_DIP_MOSI PB3 +#define MIKROBUS_3_DIP_PWM PD6 +#define MIKROBUS_3_DIP_INT PD2 +#define MIKROBUS_3_DIP_RX PD0 +#define MIKROBUS_3_DIP_TX PD1 +#define MIKROBUS_3_DIP_SCL PC5 +#define MIKROBUS_3_DIP_SDA PC4 + +#define MIKROBUS_4_DIP_AN PA3 +#define MIKROBUS_4_DIP_RST PB5 +#define MIKROBUS_4_DIP_CS PA5 +#define MIKROBUS_4_DIP_SCK PB2 +#define MIKROBUS_4_DIP_MISO PB1 +#define MIKROBUS_4_DIP_MOSI PB0 +#define MIKROBUS_4_DIP_PWM PB3 +#define MIKROBUS_4_DIP_INT PB6 +#define MIKROBUS_4_DIP_RX PD2 +#define MIKROBUS_4_DIP_TX PD3 +#define MIKROBUS_4_DIP_SCL PA2 +#define MIKROBUS_4_DIP_SDA PA0 + +#define MIKROBUS_5_DIP_AN PB1 +#define MIKROBUS_5_DIP_RST PC6 +#define MIKROBUS_5_DIP_CS PA3 +#define MIKROBUS_5_DIP_SCK PA4 +#define MIKROBUS_5_DIP_MISO PA5 +#define MIKROBUS_5_DIP_MOSI PA6 +#define MIKROBUS_5_DIP_PWM PC7 +#define MIKROBUS_5_DIP_INT PB2 +#define MIKROBUS_5_DIP_RX PC1 +#define MIKROBUS_5_DIP_TX PC0 +#define MIKROBUS_5_DIP_SCL PC3 +#define MIKROBUS_5_DIP_SDA PC2 + +#define USB_UART_DIP_TX PD1 +#define USB_UART_DIP_RX PD0 + +#ifdef __cplusplus +} +#endif + +#endif // _DIP_SOCKET_H_ +// ------------------------------------------------------------------------- END diff --git a/bsp/board/include/boards/board_easyavr_v8/dip_sockets/dip40b/dip_socket.h b/bsp/board/include/boards/board_easyavr_v8/dip_sockets/dip40b/dip_socket.h new file mode 100644 index 000000000..e3fc4d74d --- /dev/null +++ b/bsp/board/include/boards/board_easyavr_v8/dip_sockets/dip40b/dip_socket.h @@ -0,0 +1,127 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file dip_socket.h + * @brief Dip socket mikrobus pin mapping. + */ + +#ifndef _DIP_SOCKET_H_ +#define _DIP_SOCKET_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_target.h" + +/// Mapping +#define MIKROBUS_1_DIP_AN PA7 +#define MIKROBUS_1_DIP_RST PA4 +#define MIKROBUS_1_DIP_CS PB4 +#define MIKROBUS_1_DIP_SCK PB7 +#define MIKROBUS_1_DIP_MISO PB6 +#define MIKROBUS_1_DIP_MOSI PB5 +#define MIKROBUS_1_DIP_PWM PD4 +#define MIKROBUS_1_DIP_INT PD2 +#define MIKROBUS_1_DIP_RX PD0 +#define MIKROBUS_1_DIP_TX PD1 +#define MIKROBUS_1_DIP_SCL PC0 +#define MIKROBUS_1_DIP_SDA PC1 + +#define MIKROBUS_2_DIP_AN PA3 +#define MIKROBUS_2_DIP_RST PA0 +#define MIKROBUS_2_DIP_CS PA1 +#define MIKROBUS_2_DIP_SCK PB7 +#define MIKROBUS_2_DIP_MISO PB6 +#define MIKROBUS_2_DIP_MOSI PB5 +#define MIKROBUS_2_DIP_PWM PD5 +#define MIKROBUS_2_DIP_INT PD3 +#define MIKROBUS_2_DIP_RX PD0 +#define MIKROBUS_2_DIP_TX PD1 +#define MIKROBUS_2_DIP_SCL PC0 +#define MIKROBUS_2_DIP_SDA PC1 + +#define MIKROBUS_3_DIP_AN PC2 +#define MIKROBUS_3_DIP_RST PD3 +#define MIKROBUS_3_DIP_CS PB2 +#define MIKROBUS_3_DIP_SCK PB5 +#define MIKROBUS_3_DIP_MISO PB4 +#define MIKROBUS_3_DIP_MOSI PB3 +#define MIKROBUS_3_DIP_PWM PD6 +#define MIKROBUS_3_DIP_INT PD2 +#define MIKROBUS_3_DIP_RX PD0 +#define MIKROBUS_3_DIP_TX PD1 +#define MIKROBUS_3_DIP_SCL PC5 +#define MIKROBUS_3_DIP_SDA PC4 + +#define MIKROBUS_4_DIP_AN PA3 +#define MIKROBUS_4_DIP_RST PB5 +#define MIKROBUS_4_DIP_CS PA5 +#define MIKROBUS_4_DIP_SCK PB2 +#define MIKROBUS_4_DIP_MISO PB1 +#define MIKROBUS_4_DIP_MOSI PB0 +#define MIKROBUS_4_DIP_PWM PB3 +#define MIKROBUS_4_DIP_INT PB6 +#define MIKROBUS_4_DIP_RX PD2 +#define MIKROBUS_4_DIP_TX PD3 +#define MIKROBUS_4_DIP_SCL PA2 +#define MIKROBUS_4_DIP_SDA PA0 + +#define MIKROBUS_5_DIP_AN PB1 +#define MIKROBUS_5_DIP_RST PC6 +#define MIKROBUS_5_DIP_CS PA3 +#define MIKROBUS_5_DIP_SCK PA4 +#define MIKROBUS_5_DIP_MISO PA5 +#define MIKROBUS_5_DIP_MOSI PA6 +#define MIKROBUS_5_DIP_PWM PC7 +#define MIKROBUS_5_DIP_INT PB2 +#define MIKROBUS_5_DIP_RX PC1 +#define MIKROBUS_5_DIP_TX PC0 +#define MIKROBUS_5_DIP_SCL PC3 +#define MIKROBUS_5_DIP_SDA PC2 + +#define USB_UART_DIP_TX PD1 +#define USB_UART_DIP_RX PD0 + +#ifdef __cplusplus +} +#endif + +#endif // _DIP_SOCKET_H_ +// ------------------------------------------------------------------------- END diff --git a/bsp/board/include/boards/board_easyavr_v8/dip_sockets/dip8/dip_socket.h b/bsp/board/include/boards/board_easyavr_v8/dip_sockets/dip8/dip_socket.h new file mode 100644 index 000000000..736490e60 --- /dev/null +++ b/bsp/board/include/boards/board_easyavr_v8/dip_sockets/dip8/dip_socket.h @@ -0,0 +1,127 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file dip_socket.h + * @brief Dip socket mikrobus pin mapping. + */ + +#ifndef _DIP_SOCKET_H_ +#define _DIP_SOCKET_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_target.h" + +/// Mapping +#define MIKROBUS_1_DIP_AN // Pin not routed to mikroBUS. +#define MIKROBUS_1_DIP_RST // Pin not routed to mikroBUS. +#define MIKROBUS_1_DIP_CS PB4 +#define MIKROBUS_1_DIP_SCK // Pin not routed to mikroBUS. +#define MIKROBUS_1_DIP_MISO // Pin not routed to mikroBUS. +#define MIKROBUS_1_DIP_MOSI PB5 +#define MIKROBUS_1_DIP_PWM // Pin not routed to mikroBUS. +#define MIKROBUS_1_DIP_INT // Pin not routed to mikroBUS. +#define MIKROBUS_1_DIP_RX // Pin not routed to mikroBUS. +#define MIKROBUS_1_DIP_TX // Pin not routed to mikroBUS. +#define MIKROBUS_1_DIP_SCL // Pin not routed to mikroBUS. +#define MIKROBUS_1_DIP_SDA // Pin not routed to mikroBUS. + +#define MIKROBUS_2_DIP_AN // Pin not routed to mikroBUS. +#define MIKROBUS_2_DIP_RST // Pin not routed to mikroBUS. +#define MIKROBUS_2_DIP_CS // Pin not routed to mikroBUS. +#define MIKROBUS_2_DIP_SCK // Pin not routed to mikroBUS. +#define MIKROBUS_2_DIP_MISO // Pin not routed to mikroBUS. +#define MIKROBUS_2_DIP_MOSI PB5 +#define MIKROBUS_2_DIP_PWM // Pin not routed to mikroBUS. +#define MIKROBUS_2_DIP_INT // Pin not routed to mikroBUS. +#define MIKROBUS_2_DIP_RX // Pin not routed to mikroBUS. +#define MIKROBUS_2_DIP_TX // Pin not routed to mikroBUS. +#define MIKROBUS_2_DIP_SCL // Pin not routed to mikroBUS. +#define MIKROBUS_2_DIP_SDA // Pin not routed to mikroBUS. + +#define MIKROBUS_3_DIP_AN // Pin not routed to mikroBUS. +#define MIKROBUS_3_DIP_RST // Pin not routed to mikroBUS. +#define MIKROBUS_3_DIP_CS PB2 +#define MIKROBUS_3_DIP_SCK PB5 +#define MIKROBUS_3_DIP_MISO PB4 +#define MIKROBUS_3_DIP_MOSI PB3 +#define MIKROBUS_3_DIP_PWM // Pin not routed to mikroBUS. +#define MIKROBUS_3_DIP_INT // Pin not routed to mikroBUS. +#define MIKROBUS_3_DIP_RX // Pin not routed to mikroBUS. +#define MIKROBUS_3_DIP_TX // Pin not routed to mikroBUS. +#define MIKROBUS_3_DIP_SCL // Pin not routed to mikroBUS. +#define MIKROBUS_3_DIP_SDA // Pin not routed to mikroBUS. + +#define MIKROBUS_4_DIP_AN // Pin not routed to mikroBUS. +#define MIKROBUS_4_DIP_RST PB5 +#define MIKROBUS_4_DIP_CS // Pin not routed to mikroBUS. +#define MIKROBUS_4_DIP_SCK PB2 +#define MIKROBUS_4_DIP_MISO PB1 +#define MIKROBUS_4_DIP_MOSI PB0 +#define MIKROBUS_4_DIP_PWM PB3 +#define MIKROBUS_4_DIP_INT // Pin not routed to mikroBUS. +#define MIKROBUS_4_DIP_RX // Pin not routed to mikroBUS. +#define MIKROBUS_4_DIP_TX // Pin not routed to mikroBUS. +#define MIKROBUS_4_DIP_SCL // Pin not routed to mikroBUS. +#define MIKROBUS_4_DIP_SDA // Pin not routed to mikroBUS. + +#define MIKROBUS_5_DIP_AN PB1 +#define MIKROBUS_5_DIP_RST // Pin not routed to mikroBUS. +#define MIKROBUS_5_DIP_CS // Pin not routed to mikroBUS. +#define MIKROBUS_5_DIP_SCK // Pin not routed to mikroBUS. +#define MIKROBUS_5_DIP_MISO // Pin not routed to mikroBUS. +#define MIKROBUS_5_DIP_MOSI // Pin not routed to mikroBUS. +#define MIKROBUS_5_DIP_PWM // Pin not routed to mikroBUS. +#define MIKROBUS_5_DIP_INT PB2 +#define MIKROBUS_5_DIP_RX // Pin not routed to mikroBUS. +#define MIKROBUS_5_DIP_TX // Pin not routed to mikroBUS. +#define MIKROBUS_5_DIP_SCL // Pin not routed to mikroBUS. +#define MIKROBUS_5_DIP_SDA // Pin not routed to mikroBUS. + +#define USB_UART_DIP_TX // UART not supported +#define USB_UART_DIP_RX // UART not supported + +#ifdef __cplusplus +} +#endif + +#endif // _DIP_SOCKET_H_ +// ------------------------------------------------------------------------- END diff --git a/bsp/board/include/boards/board_easymx_pro_v7_for_stm32/board.cmake b/bsp/board/include/boards/board_easymx_pro_v7_for_stm32/board.cmake new file mode 100644 index 000000000..8e6b42bbd --- /dev/null +++ b/bsp/board/include/boards/board_easymx_pro_v7_for_stm32/board.cmake @@ -0,0 +1,3 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "BOARD_EASYMX_PRO_V7_FOR_STM32") + set(BOARD_PATH "include/boards/board_easymx_pro_v7_for_stm32") +endif() diff --git a/bsp/board/include/boards/board_easymx_pro_v7_for_tiva/board.cmake b/bsp/board/include/boards/board_easymx_pro_v7_for_tiva/board.cmake new file mode 100644 index 000000000..bbbeff70e --- /dev/null +++ b/bsp/board/include/boards/board_easymx_pro_v7_for_tiva/board.cmake @@ -0,0 +1,3 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "BOARD_EASYMX_PRO_V7_FOR_TIVA") + set(BOARD_PATH "include/boards/board_easymx_pro_v7_for_tiva") +endif() diff --git a/bsp/board/include/boards/board_easypic_fusion_v7/board.cmake b/bsp/board/include/boards/board_easypic_fusion_v7/board.cmake new file mode 100644 index 000000000..04ae9b5d5 --- /dev/null +++ b/bsp/board/include/boards/board_easypic_fusion_v7/board.cmake @@ -0,0 +1,3 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "BOARD_EASYPIC_FUSION_V7") + set(BOARD_PATH "include/boards/board_easypic_fusion_v7") +endif() diff --git a/bsp/board/include/boards/board_easypic_pro_v7/board.cmake b/bsp/board/include/boards/board_easypic_pro_v7/board.cmake new file mode 100644 index 000000000..144a36963 --- /dev/null +++ b/bsp/board/include/boards/board_easypic_pro_v7/board.cmake @@ -0,0 +1,3 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "BOARD_EASYPIC_PRO_V7") + set(BOARD_PATH "include/boards/board_easypic_pro_v7") +endif() diff --git a/bsp/board/include/boards/board_easypic_pro_v8/board.cmake b/bsp/board/include/boards/board_easypic_pro_v8/board.cmake new file mode 100644 index 000000000..0af20896e --- /dev/null +++ b/bsp/board/include/boards/board_easypic_pro_v8/board.cmake @@ -0,0 +1,3 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "BOARD_EASYPIC_PRO_V8") + set(BOARD_PATH "include/boards/board_easypic_pro_v8") +endif() diff --git a/bsp/board/include/boards/board_easypic_v7/board.cmake b/bsp/board/include/boards/board_easypic_v7/board.cmake new file mode 100644 index 000000000..cc1e607a5 --- /dev/null +++ b/bsp/board/include/boards/board_easypic_v7/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "BOARD_EASYPIC_V7") + set(BOARD_PATH "include/boards/board_easypic_v7") + set(MCU_CARD FALSE) + set(DIP_SOCKET TRUE) +endif() diff --git a/bsp/board/include/boards/board_easypic_v7_for_dspic30/board.cmake b/bsp/board/include/boards/board_easypic_v7_for_dspic30/board.cmake new file mode 100644 index 000000000..e997d2024 --- /dev/null +++ b/bsp/board/include/boards/board_easypic_v7_for_dspic30/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "BOARD_EASYPIC_V7_FOR_DSPIC30") + set(BOARD_PATH "include/boards/board_easypic_v7_for_dspic30") + set(MCU_CARD FALSE) + set(DIP_SOCKET TRUE) +endif() diff --git a/bsp/board/include/boards/board_easypic_v8/board.cmake b/bsp/board/include/boards/board_easypic_v8/board.cmake new file mode 100644 index 000000000..8011736a7 --- /dev/null +++ b/bsp/board/include/boards/board_easypic_v8/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "BOARD_EASYPIC_V8") + set(BOARD_PATH "include/boards/board_easypic_v8") + set(MCU_CARD FALSE) + set(DIP_SOCKET TRUE) +endif() diff --git a/bsp/board/include/boards/board_easypic_v8_for_dspic24_33/board.cmake b/bsp/board/include/boards/board_easypic_v8_for_dspic24_33/board.cmake new file mode 100644 index 000000000..55359eb83 --- /dev/null +++ b/bsp/board/include/boards/board_easypic_v8_for_dspic24_33/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "BOARD_EASYPIC_V8_FOR_DSPIC24_33") + set(BOARD_PATH "include/boards/board_easypic_v8_for_dspic24_33") + set(MCU_CARD FALSE) + set(DIP_SOCKET TRUE) +endif() diff --git a/bsp/board/include/boards/board_easypic_v8_for_dspic30/board.cmake b/bsp/board/include/boards/board_easypic_v8_for_dspic30/board.cmake new file mode 100644 index 000000000..30bf8edcb --- /dev/null +++ b/bsp/board/include/boards/board_easypic_v8_for_dspic30/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "BOARD_EASYPIC_V8_FOR_DSPIC30") + set(BOARD_PATH "include/boards/board_easypic_v8_for_dspic30") + set(MCU_CARD FALSE) + set(DIP_SOCKET TRUE) +endif() diff --git a/bsp/board/include/boards/board_explorer16_32/board.cmake b/bsp/board/include/boards/board_explorer16_32/board.cmake new file mode 100644 index 000000000..532941532 --- /dev/null +++ b/bsp/board/include/boards/board_explorer16_32/board.cmake @@ -0,0 +1,4 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "BOARD_EXPLORER_16_32") + set(BOARD_PATH "include/boards/board_explorer16_32") + set(PIM_SOCKET TRUE) +endif() diff --git a/bsp/board/include/boards/board_flowpaw/board.cmake b/bsp/board/include/boards/board_flowpaw/board.cmake new file mode 100644 index 000000000..27d3d34e8 --- /dev/null +++ b/bsp/board/include/boards/board_flowpaw/board.cmake @@ -0,0 +1,4 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "BOARD_FLOWPAW") + set(BOARD_PATH "include/boards/board_flowpaw") + set(MCU_CARD FALSE) +endif() diff --git a/bsp/board/include/boards/board_fusion_for_arm_v8/board.cmake b/bsp/board/include/boards/board_fusion_for_arm_v8/board.cmake new file mode 100644 index 000000000..6dbb8c313 --- /dev/null +++ b/bsp/board/include/boards/board_fusion_for_arm_v8/board.cmake @@ -0,0 +1,3 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "BOARD_FUSION_FOR_ARM_V8") + set(BOARD_PATH "include/boards/board_fusion_for_arm_v8") +endif() diff --git a/bsp/board/include/boards/board_fusion_for_kinetis_v8/board.cmake b/bsp/board/include/boards/board_fusion_for_kinetis_v8/board.cmake new file mode 100644 index 000000000..225b92ee7 --- /dev/null +++ b/bsp/board/include/boards/board_fusion_for_kinetis_v8/board.cmake @@ -0,0 +1,3 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "BOARD_FUSION_FOR_KINETIS_V8") + set(BOARD_PATH "include/boards/board_fusion_for_kinetis_v8") +endif() diff --git a/bsp/board/include/boards/board_fusion_for_pic32_v8/board.cmake b/bsp/board/include/boards/board_fusion_for_pic32_v8/board.cmake new file mode 100644 index 000000000..e8f2ab5db --- /dev/null +++ b/bsp/board/include/boards/board_fusion_for_pic32_v8/board.cmake @@ -0,0 +1,3 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "BOARD_FUSION_FOR_PIC32_V8") + set(BOARD_PATH "include/boards/board_fusion_for_pic32_v8") +endif() diff --git a/bsp/board/include/boards/board_fusion_for_pic_v8/board.cmake b/bsp/board/include/boards/board_fusion_for_pic_v8/board.cmake new file mode 100644 index 000000000..0e886c0cf --- /dev/null +++ b/bsp/board/include/boards/board_fusion_for_pic_v8/board.cmake @@ -0,0 +1,3 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "BOARD_FUSION_FOR_PIC_V8") + set(BOARD_PATH "include/boards/board_fusion_for_pic_v8") +endif() diff --git a/bsp/board/include/boards/board_fusion_for_stm32_v8/board.cmake b/bsp/board/include/boards/board_fusion_for_stm32_v8/board.cmake new file mode 100644 index 000000000..3fd528c71 --- /dev/null +++ b/bsp/board/include/boards/board_fusion_for_stm32_v8/board.cmake @@ -0,0 +1,3 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "BOARD_FUSION_FOR_STM32_V8") + set(BOARD_PATH "include/boards/board_fusion_for_stm32_v8") +endif() diff --git a/bsp/board/include/boards/board_fusion_for_tiva_v8/board.cmake b/bsp/board/include/boards/board_fusion_for_tiva_v8/board.cmake new file mode 100644 index 000000000..db7c06e60 --- /dev/null +++ b/bsp/board/include/boards/board_fusion_for_tiva_v8/board.cmake @@ -0,0 +1,3 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "BOARD_FUSION_FOR_TIVA_V8") + set(BOARD_PATH "include/boards/board_fusion_for_tiva_v8") +endif() diff --git a/bsp/board/include/boards/board_generic/board.cmake b/bsp/board/include/boards/board_generic/board.cmake new file mode 100644 index 000000000..b0778b39e --- /dev/null +++ b/bsp/board/include/boards/board_generic/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} MATCHES "GENERIC(.+)BOARD") + set(BOARD_PATH "include/boards/board_generic") + set(MCU_CARD FALSE) + set(MIKROBUS FALSE) +endif() diff --git a/bsp/board/include/boards/board_hexiwear_battery_pack/board.cmake b/bsp/board/include/boards/board_hexiwear_battery_pack/board.cmake new file mode 100644 index 000000000..072bc0450 --- /dev/null +++ b/bsp/board/include/boards/board_hexiwear_battery_pack/board.cmake @@ -0,0 +1,4 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "BOARD_HEXIWEAR_BATTERY_PACK") + set(BOARD_PATH "include/boards/board_hexiwear_battery_pack") + set(MCU_CARD FALSE) +endif() diff --git a/bsp/board/include/boards/board_hexiwear_docking_station/board.cmake b/bsp/board/include/boards/board_hexiwear_docking_station/board.cmake new file mode 100644 index 000000000..bcb4e9585 --- /dev/null +++ b/bsp/board/include/boards/board_hexiwear_docking_station/board.cmake @@ -0,0 +1,4 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "BOARD_HEXIWEAR_DOCKING_STATION") + set(BOARD_PATH "include/boards/board_hexiwear_docking_station") + set(MCU_CARD FALSE) +endif() diff --git a/bsp/board/include/boards/board_hexiwear_workstation/board.cmake b/bsp/board/include/boards/board_hexiwear_workstation/board.cmake new file mode 100644 index 000000000..832d3b14b --- /dev/null +++ b/bsp/board/include/boards/board_hexiwear_workstation/board.cmake @@ -0,0 +1,4 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "BOARD_HEXIWEAR_WORKSTATION") + set(BOARD_PATH "include/boards/board_hexiwear_workstation") + set(MCU_CARD FALSE) +endif() diff --git a/bsp/board/include/boards/board_micromod_mikrobus_carrier/board.cmake b/bsp/board/include/boards/board_micromod_mikrobus_carrier/board.cmake new file mode 100644 index 000000000..b9db01e66 --- /dev/null +++ b/bsp/board/include/boards/board_micromod_mikrobus_carrier/board.cmake @@ -0,0 +1,3 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "BOARD_MICROMOD_MIKROBUS_CARRIER") + set(BOARD_PATH "include/boards/board_micromod_mikrobus_carrier") +endif() diff --git a/bsp/board/include/boards/board_nucleo_144_with_stm32f412zg/board.cmake b/bsp/board/include/boards/board_nucleo_144_with_stm32f412zg/board.cmake new file mode 100644 index 000000000..8e2b2e779 --- /dev/null +++ b/bsp/board/include/boards/board_nucleo_144_with_stm32f412zg/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "BOARD_NUCLEO_144_WITH_STM32F412ZG") + set(BOARD_PATH "include/boards/board_nucleo_144_with_stm32f412zg") + set(MCU_CARD FALSE) + set(SHIELD TRUE) +endif() diff --git a/bsp/board/include/boards/board_nucleo_144_with_stm32f413zh/board.cmake b/bsp/board/include/boards/board_nucleo_144_with_stm32f413zh/board.cmake new file mode 100644 index 000000000..67186b551 --- /dev/null +++ b/bsp/board/include/boards/board_nucleo_144_with_stm32f413zh/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "BOARD_NUCLEO_144_WITH_STM32F413ZH") + set(BOARD_PATH "include/boards/board_nucleo_144_with_stm32f413zh") + set(MCU_CARD FALSE) + set(SHIELD TRUE) +endif() diff --git a/bsp/board/include/boards/board_nucleo_144_with_stm32f446ze/board.cmake b/bsp/board/include/boards/board_nucleo_144_with_stm32f446ze/board.cmake new file mode 100644 index 000000000..1b83b3831 --- /dev/null +++ b/bsp/board/include/boards/board_nucleo_144_with_stm32f446ze/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "BOARD_NUCLEO_144_WITH_STM32F446ZE") + set(BOARD_PATH "include/boards/board_nucleo_144_with_stm32f446ze") + set(MCU_CARD FALSE) + set(SHIELD TRUE) +endif() diff --git a/bsp/board/include/boards/board_nucleo_144_with_stm32f722ze/board.cmake b/bsp/board/include/boards/board_nucleo_144_with_stm32f722ze/board.cmake new file mode 100644 index 000000000..aa441889b --- /dev/null +++ b/bsp/board/include/boards/board_nucleo_144_with_stm32f722ze/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "BOARD_NUCLEO_144_WITH_STM32F722ZE") + set(BOARD_PATH "include/boards/board_nucleo_144_with_stm32f722ze") + set(MCU_CARD FALSE) + set(SHIELD TRUE) +endif() diff --git a/bsp/board/include/boards/board_nucleo_144_with_stm32h743zi/board.cmake b/bsp/board/include/boards/board_nucleo_144_with_stm32h743zi/board.cmake new file mode 100644 index 000000000..7b80041e6 --- /dev/null +++ b/bsp/board/include/boards/board_nucleo_144_with_stm32h743zi/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "BOARD_NUCLEO_144_WITH_STM32H743ZI") + set(BOARD_PATH "include/boards/board_nucleo_144_with_stm32h743zi") + set(MCU_CARD FALSE) + set(SHIELD TRUE) +endif() diff --git a/bsp/board/include/boards/board_nucleo_144_with_stm32l496zg/board.cmake b/bsp/board/include/boards/board_nucleo_144_with_stm32l496zg/board.cmake new file mode 100644 index 000000000..17027ee98 --- /dev/null +++ b/bsp/board/include/boards/board_nucleo_144_with_stm32l496zg/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "BOARD_NUCLEO_144_WITH_STM32L496ZG") + set(BOARD_PATH "include/boards/board_nucleo_144_with_stm32l496zg") + set(MCU_CARD FALSE) + set(SHIELD TRUE) +endif() diff --git a/bsp/board/include/boards/board_nucleo_144_with_stm32l4r5zi/board.cmake b/bsp/board/include/boards/board_nucleo_144_with_stm32l4r5zi/board.cmake new file mode 100644 index 000000000..0418502f6 --- /dev/null +++ b/bsp/board/include/boards/board_nucleo_144_with_stm32l4r5zi/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "BOARD_NUCLEO_144_WITH_STM32L4R5ZI") + set(BOARD_PATH "include/boards/board_nucleo_144_with_stm32l4r5zi") + set(MCU_CARD FALSE) + set(SHIELD TRUE) +endif() diff --git a/bsp/board/include/boards/board_nucleo_64_with_stm32f030r8/board.cmake b/bsp/board/include/boards/board_nucleo_64_with_stm32f030r8/board.cmake new file mode 100644 index 000000000..f40e422cd --- /dev/null +++ b/bsp/board/include/boards/board_nucleo_64_with_stm32f030r8/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "BOARD_NUCLEO_64_WITH_STM32F030R8") + set(BOARD_PATH "include/boards/board_nucleo_64_with_stm32f030r8") + set(MCU_CARD FALSE) + set(SHIELD TRUE) +endif() diff --git a/bsp/board/include/boards/board_nucleo_64_with_stm32f070rb/board.cmake b/bsp/board/include/boards/board_nucleo_64_with_stm32f070rb/board.cmake new file mode 100644 index 000000000..c7428771a --- /dev/null +++ b/bsp/board/include/boards/board_nucleo_64_with_stm32f070rb/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "BOARD_NUCLEO_64_WITH_STM32F070RB") + set(BOARD_PATH "include/boards/board_nucleo_64_with_stm32f070rb") + set(MCU_CARD FALSE) + set(SHIELD TRUE) +endif() diff --git a/bsp/board/include/boards/board_nucleo_64_with_stm32f091rc/board.cmake b/bsp/board/include/boards/board_nucleo_64_with_stm32f091rc/board.cmake new file mode 100644 index 000000000..6adaa9c57 --- /dev/null +++ b/bsp/board/include/boards/board_nucleo_64_with_stm32f091rc/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "BOARD_NUCLEO_64_WITH_STM32F091RC") + set(BOARD_PATH "include/boards/board_nucleo_64_with_stm32f091rc") + set(MCU_CARD FALSE) + set(SHIELD TRUE) +endif() diff --git a/bsp/board/include/boards/board_nucleo_64_with_stm32f401re/board.cmake b/bsp/board/include/boards/board_nucleo_64_with_stm32f401re/board.cmake new file mode 100644 index 000000000..5579138f4 --- /dev/null +++ b/bsp/board/include/boards/board_nucleo_64_with_stm32f401re/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "BOARD_NUCLEO_64_WITH_STM32F401RE") + set(BOARD_PATH "include/boards/board_nucleo_64_with_stm32f401re") + set(MCU_CARD FALSE) + set(SHIELD TRUE) +endif() diff --git a/bsp/board/include/boards/board_nucleo_64_with_stm32l073rz/board.cmake b/bsp/board/include/boards/board_nucleo_64_with_stm32l073rz/board.cmake new file mode 100644 index 000000000..083b0abcf --- /dev/null +++ b/bsp/board/include/boards/board_nucleo_64_with_stm32l073rz/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "BOARD_NUCLEO_64_WITH_STM32L073RZ") + set(BOARD_PATH "include/boards/board_nucleo_64_with_stm32l073rz") + set(MCU_CARD FALSE) + set(SHIELD TRUE) +endif() diff --git a/bsp/board/include/boards/board_nucleo_64_with_stm32l433rc_p/board.cmake b/bsp/board/include/boards/board_nucleo_64_with_stm32l433rc_p/board.cmake new file mode 100644 index 000000000..5b160a3eb --- /dev/null +++ b/bsp/board/include/boards/board_nucleo_64_with_stm32l433rc_p/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "BOARD_NUCLEO_64_WITH_STM32L433RC_P") + set(BOARD_PATH "include/boards/board_nucleo_64_with_stm32l433rc_p") + set(MCU_CARD FALSE) + set(SHIELD TRUE) +endif() diff --git a/bsp/board/include/boards/board_nucleo_64_with_stm32l476rg/board.cmake b/bsp/board/include/boards/board_nucleo_64_with_stm32l476rg/board.cmake new file mode 100644 index 000000000..b0037ac30 --- /dev/null +++ b/bsp/board/include/boards/board_nucleo_64_with_stm32l476rg/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "BOARD_NUCLEO_64_WITH_STM32L476RG") + set(BOARD_PATH "include/boards/board_nucleo_64_with_stm32l476rg") + set(MCU_CARD FALSE) + set(SHIELD TRUE) +endif() diff --git a/bsp/board/include/boards/board_picplc16_v7/board.cmake b/bsp/board/include/boards/board_picplc16_v7/board.cmake new file mode 100644 index 000000000..acf1790b1 --- /dev/null +++ b/bsp/board/include/boards/board_picplc16_v7/board.cmake @@ -0,0 +1,4 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "BOARD_PICPLC16_V7") + set(BOARD_PATH "include/boards/board_picplc16_v7") + set(MCU_CARD FALSE) +endif() diff --git a/bsp/board/include/boards/board_quail/board.cmake b/bsp/board/include/boards/board_quail/board.cmake new file mode 100644 index 000000000..5e85ed2ca --- /dev/null +++ b/bsp/board/include/boards/board_quail/board.cmake @@ -0,0 +1,4 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "BOARD_QUAIL") + set(BOARD_PATH "include/boards/board_quail") + set(MCU_CARD FALSE) +endif() diff --git a/bsp/board/include/boards/board_uni_ds_v8/board.cmake b/bsp/board/include/boards/board_uni_ds_v8/board.cmake new file mode 100644 index 000000000..d0bee9a11 --- /dev/null +++ b/bsp/board/include/boards/board_uni_ds_v8/board.cmake @@ -0,0 +1,3 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "BOARD_UNI_DS_V8") + set(BOARD_PATH "include/boards/board_uni_ds_v8") +endif() diff --git a/bsp/board/include/boards/clicker_2_for_dspic33/board.cmake b/bsp/board/include/boards/clicker_2_for_dspic33/board.cmake new file mode 100644 index 000000000..88c281c14 --- /dev/null +++ b/bsp/board/include/boards/clicker_2_for_dspic33/board.cmake @@ -0,0 +1,4 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "CLICKER_2_FOR_DSPIC33") + set(BOARD_PATH "include/boards/clicker_2_for_dspic33") + set(MCU_CARD FALSE) +endif() diff --git a/bsp/board/include/boards/clicker_2_for_kinetis/board.cmake b/bsp/board/include/boards/clicker_2_for_kinetis/board.cmake new file mode 100644 index 000000000..1c50162a7 --- /dev/null +++ b/bsp/board/include/boards/clicker_2_for_kinetis/board.cmake @@ -0,0 +1,4 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "CLICKER_2_FOR_KINETIS") + set(BOARD_PATH "include/boards/clicker_2_for_kinetis") + set(MCU_CARD FALSE) +endif() diff --git a/bsp/board/include/boards/clicker_2_for_pic18fj/board.cmake b/bsp/board/include/boards/clicker_2_for_pic18fj/board.cmake new file mode 100644 index 000000000..6710613ec --- /dev/null +++ b/bsp/board/include/boards/clicker_2_for_pic18fj/board.cmake @@ -0,0 +1,4 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "CLICKER_2_FOR_PIC18FJ") + set(BOARD_PATH "include/boards/clicker_2_for_pic18fj") + set(MCU_CARD FALSE) +endif() diff --git a/bsp/board/include/boards/clicker_2_for_pic18fk/board.cmake b/bsp/board/include/boards/clicker_2_for_pic18fk/board.cmake new file mode 100644 index 000000000..1f65f437f --- /dev/null +++ b/bsp/board/include/boards/clicker_2_for_pic18fk/board.cmake @@ -0,0 +1,4 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "CLICKER_2_FOR_PIC18FK") + set(BOARD_PATH "include/boards/clicker_2_for_pic18fk") + set(MCU_CARD FALSE) +endif() diff --git a/bsp/board/include/boards/clicker_2_for_pic24/board.cmake b/bsp/board/include/boards/clicker_2_for_pic24/board.cmake new file mode 100644 index 000000000..3ded10e78 --- /dev/null +++ b/bsp/board/include/boards/clicker_2_for_pic24/board.cmake @@ -0,0 +1,4 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "CLICKER_2_FOR_PIC24") + set(BOARD_PATH "include/boards/clicker_2_for_pic24") + set(MCU_CARD FALSE) +endif() diff --git a/bsp/board/include/boards/clicker_2_for_pic32mx/board.cmake b/bsp/board/include/boards/clicker_2_for_pic32mx/board.cmake new file mode 100644 index 000000000..46165e01c --- /dev/null +++ b/bsp/board/include/boards/clicker_2_for_pic32mx/board.cmake @@ -0,0 +1,4 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "CLICKER_2_FOR_PIC32MX") + set(BOARD_PATH "include/boards/clicker_2_for_pic32mx") + set(MCU_CARD FALSE) +endif() diff --git a/bsp/board/include/boards/clicker_2_for_pic32mz/board.cmake b/bsp/board/include/boards/clicker_2_for_pic32mz/board.cmake new file mode 100644 index 000000000..ee93882d5 --- /dev/null +++ b/bsp/board/include/boards/clicker_2_for_pic32mz/board.cmake @@ -0,0 +1,4 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "CLICKER_2_FOR_PIC32MZ") + set(BOARD_PATH "include/boards/clicker_2_for_pic32mz") + set(MCU_CARD FALSE) +endif() diff --git a/bsp/board/include/boards/clicker_2_for_stm32/board.cmake b/bsp/board/include/boards/clicker_2_for_stm32/board.cmake new file mode 100644 index 000000000..5c4f0e9c2 --- /dev/null +++ b/bsp/board/include/boards/clicker_2_for_stm32/board.cmake @@ -0,0 +1,4 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "CLICKER_2_FOR_STM32") + set(BOARD_PATH "include/boards/clicker_2_for_stm32") + set(MCU_CARD FALSE) +endif() diff --git a/bsp/board/include/boards/clicker_4_for_pic18f/board.cmake b/bsp/board/include/boards/clicker_4_for_pic18f/board.cmake new file mode 100644 index 000000000..fcf51412d --- /dev/null +++ b/bsp/board/include/boards/clicker_4_for_pic18f/board.cmake @@ -0,0 +1,4 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "CLICKER_4_FOR_PIC18F") + set(BOARD_PATH "include/boards/clicker_4_for_pic18f") + set(MCU_CARD FALSE) +endif() diff --git a/bsp/board/include/boards/clicker_4_for_stm32/board.cmake b/bsp/board/include/boards/clicker_4_for_stm32/board.cmake new file mode 100644 index 000000000..3b93f7754 --- /dev/null +++ b/bsp/board/include/boards/clicker_4_for_stm32/board.cmake @@ -0,0 +1,4 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "CLICKER_4_FOR_STM32") + set(BOARD_PATH "include/boards/clicker_4_for_stm32") + set(MCU_CARD FALSE) +endif() diff --git a/bsp/board/include/boards/clicker_4_for_stm32f4/board.cmake b/bsp/board/include/boards/clicker_4_for_stm32f4/board.cmake new file mode 100644 index 000000000..d5e4f7c21 --- /dev/null +++ b/bsp/board/include/boards/clicker_4_for_stm32f4/board.cmake @@ -0,0 +1,4 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "CLICKER_4_FOR_STM32F4") + set(BOARD_PATH "include/boards/clicker_4_for_stm32f4") + set(MCU_CARD FALSE) +endif() diff --git a/bsp/board/include/boards/clicker_6lowpan/board.cmake b/bsp/board/include/boards/clicker_6lowpan/board.cmake new file mode 100644 index 000000000..dda50893d --- /dev/null +++ b/bsp/board/include/boards/clicker_6lowpan/board.cmake @@ -0,0 +1,4 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "6LOWPAN_CLICKER") + set(BOARD_PATH "include/boards/clicker_6lowpan") + set(MCU_CARD FALSE) +endif() diff --git a/bsp/board/include/boards/clicker_kinetis/board.cmake b/bsp/board/include/boards/clicker_kinetis/board.cmake new file mode 100644 index 000000000..41afacdbf --- /dev/null +++ b/bsp/board/include/boards/clicker_kinetis/board.cmake @@ -0,0 +1,4 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "KINETIS_CLICKER") + set(BOARD_PATH "include/boards/clicker_kinetis") + set(MCU_CARD FALSE) +endif() diff --git a/bsp/board/include/boards/clicker_pic/board.cmake b/bsp/board/include/boards/clicker_pic/board.cmake new file mode 100644 index 000000000..d784186c7 --- /dev/null +++ b/bsp/board/include/boards/clicker_pic/board.cmake @@ -0,0 +1,4 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "PIC_CLICKER") + set(BOARD_PATH "include/boards/clicker_pic") + set(MCU_CARD FALSE) +endif() diff --git a/bsp/board/include/boards/clicker_pic32mx/board.cmake b/bsp/board/include/boards/clicker_pic32mx/board.cmake new file mode 100644 index 000000000..530a86171 --- /dev/null +++ b/bsp/board/include/boards/clicker_pic32mx/board.cmake @@ -0,0 +1,4 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "PIC32MX_CLICKER") + set(BOARD_PATH "include/boards/clicker_pic32mx") + set(MCU_CARD FALSE) +endif() diff --git a/bsp/board/include/boards/clicker_pic32mz/board.cmake b/bsp/board/include/boards/clicker_pic32mz/board.cmake new file mode 100644 index 000000000..d2700034b --- /dev/null +++ b/bsp/board/include/boards/clicker_pic32mz/board.cmake @@ -0,0 +1,4 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "PIC32MZ_CLICKER") + set(BOARD_PATH "include/boards/clicker_pic32mz") + set(MCU_CARD FALSE) +endif() diff --git a/bsp/board/include/boards/clicker_stm32_m4/board.cmake b/bsp/board/include/boards/clicker_stm32_m4/board.cmake new file mode 100644 index 000000000..858702fb1 --- /dev/null +++ b/bsp/board/include/boards/clicker_stm32_m4/board.cmake @@ -0,0 +1,4 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "STM32_M4_CLICKER") + set(BOARD_PATH "include/boards/clicker_stm32_m4") + set(MCU_CARD FALSE) +endif() diff --git a/bsp/board/include/boards/clicker_uni/board.cmake b/bsp/board/include/boards/clicker_uni/board.cmake new file mode 100644 index 000000000..1b4cd493e --- /dev/null +++ b/bsp/board/include/boards/clicker_uni/board.cmake @@ -0,0 +1,3 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "UNI_CLICKER") + set(BOARD_PATH "include/boards/clicker_uni") +endif() diff --git a/bsp/board/include/boards/flip_and_click_pic32mz/board.cmake b/bsp/board/include/boards/flip_and_click_pic32mz/board.cmake new file mode 100644 index 000000000..38200ec67 --- /dev/null +++ b/bsp/board/include/boards/flip_and_click_pic32mz/board.cmake @@ -0,0 +1,4 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "FLIP_AND_CLICK_PIC32MZ") + set(BOARD_PATH "include/boards/flip_and_click_pic32mz") + set(MCU_CARD FALSE) +endif() diff --git a/bsp/board/include/boards/kit_discovery_with_stm32l4r9ai_mcu/board.cmake b/bsp/board/include/boards/kit_discovery_with_stm32l4r9ai_mcu/board.cmake new file mode 100644 index 000000000..3a17b15aa --- /dev/null +++ b/bsp/board/include/boards/kit_discovery_with_stm32l4r9ai_mcu/board.cmake @@ -0,0 +1,4 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "KIT_DISCOVERY_WITH_STM32L4R9AI_MCU") + set(BOARD_PATH "include/boards/kit_discovery_with_stm32l4r9ai_mcu") + set(MCU_CARD FALSE) +endif() diff --git a/bsp/board/include/boards/mikromedia_3_kinetis_capacitive/board.cmake b/bsp/board/include/boards/mikromedia_3_kinetis_capacitive/board.cmake new file mode 100644 index 000000000..06311f81d --- /dev/null +++ b/bsp/board/include/boards/mikromedia_3_kinetis_capacitive/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "MIKROMEDIA3FORKINETISCAPACITIVE") + set(BOARD_PATH "include/boards/mikromedia_3_kinetis_capacitive") + set(MCU_CARD FALSE) + set(SHIELD TRUE) +endif() diff --git a/bsp/board/include/boards/mikromedia_3_kinetis_capacitive_fpi/board.cmake b/bsp/board/include/boards/mikromedia_3_kinetis_capacitive_fpi/board.cmake new file mode 100644 index 000000000..36a2aa729 --- /dev/null +++ b/bsp/board/include/boards/mikromedia_3_kinetis_capacitive_fpi/board.cmake @@ -0,0 +1,4 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "MIKROMEDIA3FORKINETISCAPACITIVEFPI") + set(BOARD_PATH "include/boards/mikromedia_3_kinetis_capacitive_fpi") + set(MCU_CARD FALSE) +endif() diff --git a/bsp/board/include/boards/mikromedia_3_kinetis_resistive/board.cmake b/bsp/board/include/boards/mikromedia_3_kinetis_resistive/board.cmake new file mode 100644 index 000000000..a5a46e67c --- /dev/null +++ b/bsp/board/include/boards/mikromedia_3_kinetis_resistive/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "MIKROMEDIA3FORKINETISRESISTIVE") + set(BOARD_PATH "include/boards/mikromedia_3_kinetis_resistive") + set(MCU_CARD FALSE) + set(SHIELD TRUE) +endif() diff --git a/bsp/board/include/boards/mikromedia_3_kinetis_resistive/board.h b/bsp/board/include/boards/mikromedia_3_kinetis_resistive/board.h new file mode 100644 index 000000000..3152944e4 --- /dev/null +++ b/bsp/board/include/boards/mikromedia_3_kinetis_resistive/board.h @@ -0,0 +1,191 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file board.h + * @brief Main board pin mapping. + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_target.h" +#include "shield.h" + +// Hardware revision number +#define BOARD_REV_MAJOR (1) +#define BOARD_REV_MINOR (01) + +#define BOARD_NAME "Mikromedia 3 for Kinetis Resistive" + +/// Mapping +#define TFT_RST PC12 +#define TFT_CS PC13 +#define TFT_D_C PC14 +#define TFT_RD PC15 +#define TFT_WR PC16 +#define TFT_TE PC17 +#define TFT_BPWM HAL_PIN_NC +#define TFT_D0 PC0 +#define TFT_D1 PC1 +#define TFT_D2 PC2 +#define TFT_D3 PC3 +#define TFT_D4 PC4 +#define TFT_D5 PC5 +#define TFT_D6 PC6 +#define TFT_D7 PC7 +#define TFT_D8 HAL_PIN_NC +#define TFT_D9 HAL_PIN_NC +#define TFT_D10 HAL_PIN_NC +#define TFT_D11 HAL_PIN_NC +#define TFT_D12 HAL_PIN_NC +#define TFT_D13 HAL_PIN_NC +#define TFT_D14 HAL_PIN_NC +#define TFT_D15 HAL_PIN_NC + +#define TFT_8BIT_DATA_PORT_CH0 PORT_C +#define TFT_8BIT_DATA_PORT_CH0_MASK 0x00FF + +#define TFT_16BIT_DATA_PORT_CH0 HAL_PORT_NC +#define TFT_16BIT_DATA_PORT_CH0_MASK 0x0000 + +#define TFT_16BIT_DATA_PORT_CH1 HAL_PORT_NC +#define TFT_16BIT_DATA_PORT_CH1_MASK 0x0000 + +#define CTP_SDA PB1 +#define CTP_SCL PB0 +#define CTP_INT PE26 +#define CTP_WAKE HAL_PIN_NC +#define CTP_RST HAL_PIN_NC + +#define USB_SW_ID PA29 +#define USB_VBUS HAL_PIN_NC +#define USB_N HAL_PIN_NC +#define USB_P HAL_PIN_NC +#define USB_PSW PB13 + +#define SDIO_DAT0 PE1 +#define SDIO_DAT1 PE0 +#define SDIO_DAT2 PE5 +#define SDIO_DAT3 PE4 +#define SDIO_CLK PE2 +#define SDIO_CMD PE3 +#define SDIO_CD PE6 + +#define FLASH_CS PD10 +#define FLASH_MISO PB17 +#define FLASH_SCK PB11 +#define FLASH_MOSI PB16 + +#define MP3_SCLK PD1 +#define MP3_SIN PD2 +#define MP3_SOUT PD3 +#define MP3_CS PA14 +#define MP3_RST PA15 +#define MP3_DREQ PA16 +#define MP3_DCS PA17 + +#define ALS_SDA PB1 +#define ALS_SCL PB0 + +#define ACCEL_SDA PB1 +#define ACCEL_SCL PB0 +#define ACCEL_INT2 PC19 +#define ACCEL_INT1 PC18 + +#define TEMP_SENS PE25 + +#define POWER_BAT_SENSE PE24 +#define POWER_STATUS PB12 +#define POWER_DC_DETECT HAL_PIN_NC + +#define USB_UART_TX HAL_PIN_NC +#define USB_UART_RX HAL_PIN_NC + +#define SHIELD_CONNECTOR_J1_PIN3 PB2 +#define SHIELD_CONNECTOR_J1_PIN4 PB3 +#define SHIELD_CONNECTOR_J1_PIN5 PB6 +#define SHIELD_CONNECTOR_J1_PIN6 PB7 +#define SHIELD_CONNECTOR_J1_PIN7 PC8 +#define SHIELD_CONNECTOR_J1_PIN8 PC9 +#define SHIELD_CONNECTOR_J1_PIN9 PB8 +#define SHIELD_CONNECTOR_J1_PIN10 PB9 +#define SHIELD_CONNECTOR_J1_PIN11 PB10 +#define SHIELD_CONNECTOR_J1_PIN12 PB11 +#define SHIELD_CONNECTOR_J1_PIN13 PB17 +#define SHIELD_CONNECTOR_J1_PIN14 PB16 +#define SHIELD_CONNECTOR_J1_PIN15 PA13 +#define SHIELD_CONNECTOR_J1_PIN16 PA12 +#define SHIELD_CONNECTOR_J1_PIN17 PD0 +#define SHIELD_CONNECTOR_J1_PIN18 PD1 +#define SHIELD_CONNECTOR_J1_PIN19 PD3 +#define SHIELD_CONNECTOR_J1_PIN20 PD2 +#define SHIELD_CONNECTOR_J1_PIN21 PD11 +#define SHIELD_CONNECTOR_J1_PIN22 PD12 +#define SHIELD_CONNECTOR_J1_PIN23 PD14 +#define SHIELD_CONNECTOR_J1_PIN24 PD13 + +#define SHIELD_CONNECTOR_J2_PIN7 PA11 +#define SHIELD_CONNECTOR_J2_PIN8 PB18 +#define SHIELD_CONNECTOR_J2_PIN9 PB19 +#define SHIELD_CONNECTOR_J2_PIN10 PD4 +#define SHIELD_CONNECTOR_J2_PIN11 PD5 +#define SHIELD_CONNECTOR_J2_PIN12 PA10 +#define SHIELD_CONNECTOR_J2_PIN13 PB20 +#define SHIELD_CONNECTOR_J2_PIN14 PB21 +#define SHIELD_CONNECTOR_J2_PIN15 PB22 +#define SHIELD_CONNECTOR_J2_PIN16 PB23 +#define SHIELD_CONNECTOR_J2_PIN17 PC10 +#define SHIELD_CONNECTOR_J2_PIN18 PC11 +#define SHIELD_CONNECTOR_J2_PIN19 PD8 +#define SHIELD_CONNECTOR_J2_PIN20 PD9 +#define SHIELD_CONNECTOR_J2_PIN21 PD6 +#define SHIELD_CONNECTOR_J2_PIN22 PD7 +#define SHIELD_CONNECTOR_J2_PIN23 PB0 +#define SHIELD_CONNECTOR_J2_PIN24 PB1 + +#ifdef __cplusplus +} +#endif + +#endif // _BOARD_H_ +// ------------------------------------------------------------------------- END diff --git a/bsp/board/include/boards/mikromedia_3_pic32mz_capacitive/board.cmake b/bsp/board/include/boards/mikromedia_3_pic32mz_capacitive/board.cmake new file mode 100644 index 000000000..21e450e9f --- /dev/null +++ b/bsp/board/include/boards/mikromedia_3_pic32mz_capacitive/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "MIKROMEDIA3FORPIC32MZCAPACITIVE") + set(BOARD_PATH "include/boards/mikromedia_3_pic32mz_capacitive") + set(MCU_CARD FALSE) + set(SHIELD TRUE) +endif() diff --git a/bsp/board/include/boards/mikromedia_3_pic32mz_capacitive_fpi/board.cmake b/bsp/board/include/boards/mikromedia_3_pic32mz_capacitive_fpi/board.cmake new file mode 100644 index 000000000..2f650d0d9 --- /dev/null +++ b/bsp/board/include/boards/mikromedia_3_pic32mz_capacitive_fpi/board.cmake @@ -0,0 +1,4 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "MIKROMEDIA3FORPIC32MZCAPACITIVEFPI") + set(BOARD_PATH "include/boards/mikromedia_3_pic32mz_capacitive_fpi") + set(MCU_CARD FALSE) +endif() diff --git a/bsp/board/include/boards/mikromedia_3_pic_capacitive/board.cmake b/bsp/board/include/boards/mikromedia_3_pic_capacitive/board.cmake new file mode 100644 index 000000000..224049f79 --- /dev/null +++ b/bsp/board/include/boards/mikromedia_3_pic_capacitive/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "MIKROMEDIA3FORPICCAPACITIVE") + set(BOARD_PATH "include/boards/mikromedia_3_pic_capacitive") + set(MCU_CARD FALSE) + set(SHIELD TRUE) +endif() diff --git a/bsp/board/include/boards/mikromedia_3_pic_capacitive_fpi/board.cmake b/bsp/board/include/boards/mikromedia_3_pic_capacitive_fpi/board.cmake new file mode 100644 index 000000000..dd0dcc85d --- /dev/null +++ b/bsp/board/include/boards/mikromedia_3_pic_capacitive_fpi/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "MIKROMEDIA3FORPICCAPACITIVEFPI") + set(BOARD_PATH "include/boards/mikromedia_3_pic_capacitive_fpi") + set(MCU_CARD FALSE) + set(SHIELD TRUE) +endif() diff --git a/bsp/board/include/boards/mikromedia_3_pic_resistive/board.cmake b/bsp/board/include/boards/mikromedia_3_pic_resistive/board.cmake new file mode 100644 index 000000000..51ce6c2b4 --- /dev/null +++ b/bsp/board/include/boards/mikromedia_3_pic_resistive/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "MIKROMEDIA3FORPICRESISTIVE") + set(BOARD_PATH "include/boards/mikromedia_3_pic_resistive") + set(MCU_CARD FALSE) + set(SHIELD TRUE) +endif() diff --git a/bsp/board/include/boards/mikromedia_3_pic_resistive_fpi/board.cmake b/bsp/board/include/boards/mikromedia_3_pic_resistive_fpi/board.cmake new file mode 100644 index 000000000..362008f43 --- /dev/null +++ b/bsp/board/include/boards/mikromedia_3_pic_resistive_fpi/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "MIKROMEDIA3FORPICRESISTIVEFPI") + set(BOARD_PATH "include/boards/mikromedia_3_pic_resistive_fpi") + set(MCU_CARD FALSE) + set(SHIELD FALSE) +endif() diff --git a/bsp/board/include/boards/mikromedia_3_stm32f2_capacitive/board.cmake b/bsp/board/include/boards/mikromedia_3_stm32f2_capacitive/board.cmake new file mode 100644 index 000000000..a2b4d9ae8 --- /dev/null +++ b/bsp/board/include/boards/mikromedia_3_stm32f2_capacitive/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "MIKROMEDIA3FORSTM32F2CAPACITIVE") + set(BOARD_PATH "include/boards/mikromedia_3_stm32f2_capacitive") + set(MCU_CARD FALSE) + set(SHIELD TRUE) +endif() diff --git a/bsp/board/include/boards/mikromedia_3_stm32f2_capacitive_fpi/board.cmake b/bsp/board/include/boards/mikromedia_3_stm32f2_capacitive_fpi/board.cmake new file mode 100644 index 000000000..f495fc9e2 --- /dev/null +++ b/bsp/board/include/boards/mikromedia_3_stm32f2_capacitive_fpi/board.cmake @@ -0,0 +1,4 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "MIKROMEDIA3FORSTM32F2CAPACITIVEFPI") + set(BOARD_PATH "include/boards/mikromedia_3_stm32f2_capacitive_fpi") + set(MCU_CARD FALSE) +endif() diff --git a/bsp/board/include/boards/mikromedia_3_stm32f2_resistive/board.cmake b/bsp/board/include/boards/mikromedia_3_stm32f2_resistive/board.cmake new file mode 100644 index 000000000..cfe2b2338 --- /dev/null +++ b/bsp/board/include/boards/mikromedia_3_stm32f2_resistive/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "MIKROMEDIA3FORSTM32F2RESISTIVE") + set(BOARD_PATH "include/boards/mikromedia_3_stm32f2_resistive") + set(MCU_CARD FALSE) + set(SHIELD TRUE) +endif() diff --git a/bsp/board/include/boards/mikromedia_3_stm32f2_resistive/board.h b/bsp/board/include/boards/mikromedia_3_stm32f2_resistive/board.h new file mode 100644 index 000000000..46158a765 --- /dev/null +++ b/bsp/board/include/boards/mikromedia_3_stm32f2_resistive/board.h @@ -0,0 +1,191 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file board.h + * @brief Main board pin mapping. + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_target.h" +#include "shield.h" + +// Hardware revision number +#define BOARD_REV_MAJOR (1) +#define BOARD_REV_MINOR (04) + +#define BOARD_NAME "Mikromedia 3 for STM32F2 Resistive" + +/// Mapping +#define TFT_RST PE14 +#define TFT_CS PE13 +#define TFT_D_C PE15 +#define TFT_RD PE12 +#define TFT_WR PE11 +#define TFT_TE PD4 +#define TFT_BPWM HAL_PIN_NC +#define TFT_D0 PE0 +#define TFT_D1 PE1 +#define TFT_D2 PE2 +#define TFT_D3 PE3 +#define TFT_D4 PE4 +#define TFT_D5 PE5 +#define TFT_D6 PE6 +#define TFT_D7 PE7 +#define TFT_D8 HAL_PIN_NC +#define TFT_D9 HAL_PIN_NC +#define TFT_D10 HAL_PIN_NC +#define TFT_D11 HAL_PIN_NC +#define TFT_D12 HAL_PIN_NC +#define TFT_D13 HAL_PIN_NC +#define TFT_D14 HAL_PIN_NC +#define TFT_D15 HAL_PIN_NC + +#define TFT_8BIT_DATA_PORT_CH0 PORT_E +#define TFT_8BIT_DATA_PORT_CH0_MASK 0x00FF + +#define TFT_16BIT_DATA_PORT_CH0 HAL_PORT_NC +#define TFT_16BIT_DATA_PORT_CH0_MASK 0x0000 + +#define TFT_16BIT_DATA_PORT_CH1 HAL_PORT_NC +#define TFT_16BIT_DATA_PORT_CH1_MASK 0x0000 + +#define CTP_SDA PB7 +#define CTP_SCL PB6 +#define CTP_INT PH1 +#define CTP_WAKE HAL_PIN_NC +#define CTP_RST HAL_PIN_NC + +#define USB_SW_ID PA10 +#define USB_VBUS PA9 +#define USB_N PA11 +#define USB_P PA12 +#define USB_PSW PD6 + +#define SDIO_DAT0 PC8 +#define SDIO_DAT1 PC9 +#define SDIO_DAT2 PC10 +#define SDIO_DAT3 PC11 +#define SDIO_CLK PC12 +#define SDIO_CMD PD2 +#define SDIO_CD PD3 + +#define FLASH_CS PE8 +#define FLASH_MISO PB14 +#define FLASH_SCK PB13 +#define FLASH_MOSI PB15 + +#define MP3_SCLK PA5 +#define MP3_SIN PA6 +#define MP3_SOUT PA7 +#define MP3_CS PD11 +#define MP3_RST PD8 +#define MP3_DREQ PD9 +#define MP3_DCS PD10 + +#define ALS_SDA PB7 +#define ALS_SCL PB6 + +#define ACCEL_SDA PB7 +#define ACCEL_SCL PB6 +#define ACCEL_INT2 PB9 +#define ACCEL_INT1 PB8 + +#define TEMP_SENS PC1 + +#define POWER_BAT_SENSE PA0 +#define POWER_STATUS PH0 +#define POWER_DC_DETECT HAL_PIN_NC + +#define USB_UART_TX HAL_PIN_NC +#define USB_UART_RX HAL_PIN_NC + +#define SHIELD_CONNECTOR_J1_PIN3 PA4 +#define SHIELD_CONNECTOR_J1_PIN4 PB0 +#define SHIELD_CONNECTOR_J1_PIN5 PB1 +#define SHIELD_CONNECTOR_J1_PIN6 PC0 +#define SHIELD_CONNECTOR_J1_PIN7 PC2 +#define SHIELD_CONNECTOR_J1_PIN8 PC3 +#define SHIELD_CONNECTOR_J1_PIN9 PA1 +#define SHIELD_CONNECTOR_J1_PIN10 PA2 +#define SHIELD_CONNECTOR_J1_PIN11 PB12 +#define SHIELD_CONNECTOR_J1_PIN12 PB13 +#define SHIELD_CONNECTOR_J1_PIN13 PB14 +#define SHIELD_CONNECTOR_J1_PIN14 PB15 +#define SHIELD_CONNECTOR_J1_PIN15 PD0 +#define SHIELD_CONNECTOR_J1_PIN16 PD1 +#define SHIELD_CONNECTOR_J1_PIN17 PA15 +#define SHIELD_CONNECTOR_J1_PIN18 PA5 +#define SHIELD_CONNECTOR_J1_PIN19 PA6 +#define SHIELD_CONNECTOR_J1_PIN20 PA7 +#define SHIELD_CONNECTOR_J1_PIN21 PC13 +#define SHIELD_CONNECTOR_J1_PIN22 PB3 +#define SHIELD_CONNECTOR_J1_PIN23 PB4 +#define SHIELD_CONNECTOR_J1_PIN24 PB5 + +#define SHIELD_CONNECTOR_J2_PIN7 PD12 +#define SHIELD_CONNECTOR_J2_PIN8 PD13 +#define SHIELD_CONNECTOR_J2_PIN9 PD14 +#define SHIELD_CONNECTOR_J2_PIN10 PD15 +#define SHIELD_CONNECTOR_J2_PIN11 PE9 +#define SHIELD_CONNECTOR_J2_PIN12 PE10 +#define SHIELD_CONNECTOR_J2_PIN13 PC4 +#define SHIELD_CONNECTOR_J2_PIN14 PC5 +#define SHIELD_CONNECTOR_J2_PIN15 PB2 +#define SHIELD_CONNECTOR_J2_PIN16 PA8 +#define SHIELD_CONNECTOR_J2_PIN17 PB10 +#define SHIELD_CONNECTOR_J2_PIN18 PB11 +#define SHIELD_CONNECTOR_J2_PIN19 PC7 +#define SHIELD_CONNECTOR_J2_PIN20 PC6 +#define SHIELD_CONNECTOR_J2_PIN21 PA3 +#define SHIELD_CONNECTOR_J2_PIN22 PD5 +#define SHIELD_CONNECTOR_J2_PIN23 PB6 +#define SHIELD_CONNECTOR_J2_PIN24 PB7 + +#ifdef __cplusplus +} +#endif + +#endif // _BOARD_H_ +// ------------------------------------------------------------------------- END diff --git a/bsp/board/include/boards/mikromedia_3_stm32f4_capacitive/board.cmake b/bsp/board/include/boards/mikromedia_3_stm32f4_capacitive/board.cmake new file mode 100644 index 000000000..2272c2956 --- /dev/null +++ b/bsp/board/include/boards/mikromedia_3_stm32f4_capacitive/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "MIKROMEDIA3FORSTM32F4CAPACITIVE") + set(BOARD_PATH "include/boards/mikromedia_3_stm32f4_capacitive") + set(MCU_CARD FALSE) + set(SHIELD TRUE) +endif() diff --git a/bsp/board/include/boards/mikromedia_3_stm32f4_capacitive_fpi/board.cmake b/bsp/board/include/boards/mikromedia_3_stm32f4_capacitive_fpi/board.cmake new file mode 100644 index 000000000..77b4b1e00 --- /dev/null +++ b/bsp/board/include/boards/mikromedia_3_stm32f4_capacitive_fpi/board.cmake @@ -0,0 +1,4 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "MIKROMEDIA3FORSTM32F4CAPACITIVEFPI") + set(BOARD_PATH "include/boards/mikromedia_3_stm32f4_capacitive_fpi") + set(MCU_CARD FALSE) +endif() diff --git a/bsp/board/include/boards/mikromedia_3_stm32f4_resistive/board.cmake b/bsp/board/include/boards/mikromedia_3_stm32f4_resistive/board.cmake new file mode 100644 index 000000000..a4de1bb31 --- /dev/null +++ b/bsp/board/include/boards/mikromedia_3_stm32f4_resistive/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "MIKROMEDIA3FORSTM32F4RESISTIVE") + set(BOARD_PATH "include/boards/mikromedia_3_stm32f4_resistive") + set(MCU_CARD FALSE) + set(SHIELD TRUE) +endif() diff --git a/bsp/board/include/boards/mikromedia_3_stm32f4_resistive/board.h b/bsp/board/include/boards/mikromedia_3_stm32f4_resistive/board.h new file mode 100644 index 000000000..e4eece200 --- /dev/null +++ b/bsp/board/include/boards/mikromedia_3_stm32f4_resistive/board.h @@ -0,0 +1,191 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file board.h + * @brief Main board pin mapping. + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_target.h" +#include "shield.h" + +// Hardware revision number +#define BOARD_REV_MAJOR (1) +#define BOARD_REV_MINOR (04) + +#define BOARD_NAME "Mikromedia 3 for STM32F4 Resistive" + +/// Mapping +#define TFT_RST PE14 +#define TFT_CS PE13 +#define TFT_D_C PE15 +#define TFT_RD PE12 +#define TFT_WR PE11 +#define TFT_TE PD4 +#define TFT_BPWM HAL_PIN_NC +#define TFT_D0 PE0 +#define TFT_D1 PE1 +#define TFT_D2 PE2 +#define TFT_D3 PE3 +#define TFT_D4 PE4 +#define TFT_D5 PE5 +#define TFT_D6 PE6 +#define TFT_D7 PE7 +#define TFT_D8 HAL_PIN_NC +#define TFT_D9 HAL_PIN_NC +#define TFT_D10 HAL_PIN_NC +#define TFT_D11 HAL_PIN_NC +#define TFT_D12 HAL_PIN_NC +#define TFT_D13 HAL_PIN_NC +#define TFT_D14 HAL_PIN_NC +#define TFT_D15 HAL_PIN_NC + +#define TFT_8BIT_DATA_PORT_CH0 PORT_E +#define TFT_8BIT_DATA_PORT_CH0_MASK 0x00FF + +#define TFT_16BIT_DATA_PORT_CH0 HAL_PORT_NC +#define TFT_16BIT_DATA_PORT_CH0_MASK 0x0000 + +#define TFT_16BIT_DATA_PORT_CH1 HAL_PORT_NC +#define TFT_16BIT_DATA_PORT_CH1_MASK 0x0000 + +#define CTP_SDA PB7 +#define CTP_SCL PB6 +#define CTP_INT PH1 +#define CTP_WAKE HAL_PIN_NC +#define CTP_RST HAL_PIN_NC + +#define USB_SW_ID PA10 +#define USB_VBUS PA9 +#define USB_N PA11 +#define USB_P PA12 +#define USB_PSW PD6 + +#define SDIO_DAT0 PC8 +#define SDIO_DAT1 PC9 +#define SDIO_DAT2 PC10 +#define SDIO_DAT3 PC11 +#define SDIO_CLK PC12 +#define SDIO_CMD PD2 +#define SDIO_CD PD3 + +#define FLASH_CS PE8 +#define FLASH_MISO PB14 +#define FLASH_SCK PB13 +#define FLASH_MOSI PB15 + +#define MP3_SCLK PA5 +#define MP3_SIN PA6 +#define MP3_SOUT PA7 +#define MP3_CS PD11 +#define MP3_RST PD8 +#define MP3_DREQ PD9 +#define MP3_DCS PD10 + +#define ALS_SDA PB7 +#define ALS_SCL PB6 + +#define ACCEL_SDA PB7 +#define ACCEL_SCL PB6 +#define ACCEL_INT2 PB9 +#define ACCEL_INT1 PB8 + +#define TEMP_SENS PC1 + +#define POWER_BAT_SENSE PA0 +#define POWER_STATUS PH0 +#define POWER_DC_DETECT HAL_PIN_NC + +#define USB_UART_TX HAL_PIN_NC +#define USB_UART_RX HAL_PIN_NC + +#define SHIELD_CONNECTOR_J1_PIN3 PA4 +#define SHIELD_CONNECTOR_J1_PIN4 PB0 +#define SHIELD_CONNECTOR_J1_PIN5 PB1 +#define SHIELD_CONNECTOR_J1_PIN6 PC0 +#define SHIELD_CONNECTOR_J1_PIN7 PC2 +#define SHIELD_CONNECTOR_J1_PIN8 PC3 +#define SHIELD_CONNECTOR_J1_PIN9 PA1 +#define SHIELD_CONNECTOR_J1_PIN10 PA2 +#define SHIELD_CONNECTOR_J1_PIN11 PB12 +#define SHIELD_CONNECTOR_J1_PIN12 PB13 +#define SHIELD_CONNECTOR_J1_PIN13 PB14 +#define SHIELD_CONNECTOR_J1_PIN14 PB15 +#define SHIELD_CONNECTOR_J1_PIN15 PD0 +#define SHIELD_CONNECTOR_J1_PIN16 PD1 +#define SHIELD_CONNECTOR_J1_PIN17 PA15 +#define SHIELD_CONNECTOR_J1_PIN18 PA5 +#define SHIELD_CONNECTOR_J1_PIN19 PA6 +#define SHIELD_CONNECTOR_J1_PIN20 PA7 +#define SHIELD_CONNECTOR_J1_PIN21 PC13 +#define SHIELD_CONNECTOR_J1_PIN22 PB3 +#define SHIELD_CONNECTOR_J1_PIN23 PB4 +#define SHIELD_CONNECTOR_J1_PIN24 PB5 + +#define SHIELD_CONNECTOR_J2_PIN7 PD12 +#define SHIELD_CONNECTOR_J2_PIN8 PD13 +#define SHIELD_CONNECTOR_J2_PIN9 PD14 +#define SHIELD_CONNECTOR_J2_PIN10 PD15 +#define SHIELD_CONNECTOR_J2_PIN11 PE9 +#define SHIELD_CONNECTOR_J2_PIN12 PE10 +#define SHIELD_CONNECTOR_J2_PIN13 PC4 +#define SHIELD_CONNECTOR_J2_PIN14 PC5 +#define SHIELD_CONNECTOR_J2_PIN15 PB2 +#define SHIELD_CONNECTOR_J2_PIN16 PA8 +#define SHIELD_CONNECTOR_J2_PIN17 PB10 +#define SHIELD_CONNECTOR_J2_PIN18 PB11 +#define SHIELD_CONNECTOR_J2_PIN19 PC7 +#define SHIELD_CONNECTOR_J2_PIN20 PC6 +#define SHIELD_CONNECTOR_J2_PIN21 PA3 +#define SHIELD_CONNECTOR_J2_PIN22 PD5 +#define SHIELD_CONNECTOR_J2_PIN23 PB6 +#define SHIELD_CONNECTOR_J2_PIN24 PB7 + +#ifdef __cplusplus +} +#endif + +#endif // _BOARD_H_ +// ------------------------------------------------------------------------- END diff --git a/bsp/board/include/boards/mikromedia_3_stm32f4_resistive_fpi/board.cmake b/bsp/board/include/boards/mikromedia_3_stm32f4_resistive_fpi/board.cmake new file mode 100644 index 000000000..5dfd45baa --- /dev/null +++ b/bsp/board/include/boards/mikromedia_3_stm32f4_resistive_fpi/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "MIKROMEDIA3FORSTM32F4RESISTIVEFPI") + set(BOARD_PATH "include/boards/mikromedia_3_stm32f4_resistive_fpi") + set(MCU_CARD FALSE) + set(SHIELD FALSE) +endif() diff --git a/bsp/board/include/boards/mikromedia_3_stm32f4_resistive_fpi/board.h b/bsp/board/include/boards/mikromedia_3_stm32f4_resistive_fpi/board.h new file mode 100644 index 000000000..ef4126b53 --- /dev/null +++ b/bsp/board/include/boards/mikromedia_3_stm32f4_resistive_fpi/board.h @@ -0,0 +1,159 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file board.h + * @brief Main board pin mapping. + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// Hardware revision number +#define BOARD_REV_MAJOR (1) +#define BOARD_REV_MINOR (02) + +#define BOARD_NAME "Mikromedia 3 for STM32F4 Resistive - FPI" + +#include "mikrobus.h" + +/// Mapping +#define MIKROBUS_1 1 +#define MIKROBUS_1_AN PC2 +#define MIKROBUS_1_RST PC3 +#define MIKROBUS_1_CS PB5 +#define MIKROBUS_1_SCK PA5 +#define MIKROBUS_1_MISO PA6 +#define MIKROBUS_1_MOSI PA7 +#define MIKROBUS_1_PWM PD15 +#define MIKROBUS_1_INT PD7 +#define MIKROBUS_1_RX PA3 +#define MIKROBUS_1_TX PD5 +#define MIKROBUS_1_SCL PB10 +#define MIKROBUS_1_SDA PB11 + +#define MIKROBUS_2 2 +#define MIKROBUS_2_AN PC1 +#define MIKROBUS_2_RST PD12 +#define MIKROBUS_2_CS PC0 +#define MIKROBUS_2_SCK PA5 +#define MIKROBUS_2_MISO PA6 +#define MIKROBUS_2_MOSI PA7 +#define MIKROBUS_2_PWM PD14 +#define MIKROBUS_2_INT PD1 +#define MIKROBUS_2_RX PC7 +#define MIKROBUS_2_TX PC6 +#define MIKROBUS_2_SCL PB10 +#define MIKROBUS_2_SDA PB11 + +#define TFT_RST PE14 +#define TFT_CS PE13 +#define TFT_D_C PE15 +#define TFT_RD PE12 +#define TFT_WR PE11 +#define TFT_TE PD4 +#define TFT_D0 PE0 +#define TFT_D1 PE1 +#define TFT_D2 PE2 +#define TFT_D3 PE3 +#define TFT_D4 PE4 +#define TFT_D5 PE5 +#define TFT_D6 PE6 +#define TFT_D7 PE7 + +#define TFT_8BIT_DATA_PORT_CH0 PORT_E +#define TFT_8BIT_DATA_PORT_CH0_MASK 0x00FF + +#define TFT_16BIT_DATA_PORT_CH0 HAL_PORT_NC +#define TFT_16BIT_DATA_PORT_CH0_MASK 0x0000 + +#define TFT_16BIT_DATA_PORT_CH1 HAL_PORT_NC +#define TFT_16BIT_DATA_PORT_CH1_MASK 0x0000 + +#define CTP_SDA PB7 +#define CTP_SCL PB6 +#define CTP_INT PH1 + +#define USB_SW_ID PA10 +#define USB_VBUS PA9 +#define USB_N PA11 +#define USB_P PA12 +#define USB_PSW PD6 + +#define SDIO_DAT0 PC8 +#define SDIO_DAT1 PC9 +#define SDIO_DAT2 PC10 +#define SDIO_DAT3 PC11 +#define SDIO_CLK PC12 +#define SDIO_CMD PD2 +#define SDIO_CD PD3 + +#define FLASH_CS PE8 +#define FLASH_MISO PB14 +#define FLASH_SCK PB13 +#define FLASH_MOSI PB15 + +#define MP3_SCLK PA5 +#define MP3_SIN PA6 +#define MP3_SOUT PA7 +#define MP3_CS PD11 +#define MP3_RST PD8 +#define MP3_DREQ PD9 +#define MP3_DCS PD10 + +#define ALS_SDA PB7 +#define ALS_SCL PB6 + +#define ACCEL_SDA PB7 +#define ACCEL_SCL PB6 +#define ACCEL_INT1 PB9 +#define ACCEL_INT2 PB8 + +#define USB_UART_TX HAL_PIN_NC +#define USB_UART_RX HAL_PIN_NC + +#ifdef __cplusplus +} +#endif + +#endif // _BOARD_H_ +// ------------------------------------------------------------------------- END diff --git a/bsp/board/include/boards/mikromedia_4_kinetis_capacitive/board.cmake b/bsp/board/include/boards/mikromedia_4_kinetis_capacitive/board.cmake new file mode 100644 index 000000000..22e66f632 --- /dev/null +++ b/bsp/board/include/boards/mikromedia_4_kinetis_capacitive/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "MIKROMEDIA4FORKINETISCAPACITIVE") + set(BOARD_PATH "include/boards/mikromedia_4_kinetis_capacitive") + set(MCU_CARD FALSE) + set(SHIELD TRUE) +endif() diff --git a/bsp/board/include/boards/mikromedia_4_kinetis_capacitive_fpi/board.cmake b/bsp/board/include/boards/mikromedia_4_kinetis_capacitive_fpi/board.cmake new file mode 100644 index 000000000..7f2c29398 --- /dev/null +++ b/bsp/board/include/boards/mikromedia_4_kinetis_capacitive_fpi/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "MIKROMEDIA4FORKINETISCAPACITIVEFPI") + set(BOARD_PATH "include/boards/mikromedia_4_kinetis_capacitive_fpi") + set(MCU_CARD FALSE) + set(MIKROBUS TRUE) +endif() diff --git a/bsp/board/include/boards/mikromedia_4_kinetis_resistive/board.cmake b/bsp/board/include/boards/mikromedia_4_kinetis_resistive/board.cmake new file mode 100644 index 000000000..dde569c09 --- /dev/null +++ b/bsp/board/include/boards/mikromedia_4_kinetis_resistive/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "MIKROMEDIA4FORKINETISRESISTIVE") + set(BOARD_PATH "include/boards/mikromedia_4_kinetis_resistive") + set(MCU_CARD FALSE) + set(SHIELD TRUE) +endif() diff --git a/bsp/board/include/boards/mikromedia_4_kinetis_resistive_fpi/board.cmake b/bsp/board/include/boards/mikromedia_4_kinetis_resistive_fpi/board.cmake new file mode 100644 index 000000000..cfb907c3f --- /dev/null +++ b/bsp/board/include/boards/mikromedia_4_kinetis_resistive_fpi/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "MIKROMEDIA4FORKINETISRESISTIVEFPI") + set(BOARD_PATH "include/boards/mikromedia_4_kinetis_resistive_fpi") + set(MCU_CARD FALSE) + set(SHIELD FALSE) +endif() diff --git a/bsp/board/include/boards/mikromedia_4_pic32mz_capacitive/board.cmake b/bsp/board/include/boards/mikromedia_4_pic32mz_capacitive/board.cmake new file mode 100644 index 000000000..02420919f --- /dev/null +++ b/bsp/board/include/boards/mikromedia_4_pic32mz_capacitive/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "MIKROMEDIA4FORPIC32MZCAPACITIVE") + set(BOARD_PATH "include/boards/mikromedia_4_pic32mz_capacitive") + set(MCU_CARD FALSE) + set(SHIELD TRUE) +endif() diff --git a/bsp/board/include/boards/mikromedia_4_pic32mz_capacitive_fpi/board.cmake b/bsp/board/include/boards/mikromedia_4_pic32mz_capacitive_fpi/board.cmake new file mode 100644 index 000000000..22473ed49 --- /dev/null +++ b/bsp/board/include/boards/mikromedia_4_pic32mz_capacitive_fpi/board.cmake @@ -0,0 +1,4 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "MIKROMEDIA4FORPIC32MZCAPACITIVEFPI") + set(BOARD_PATH "include/boards/mikromedia_4_pic32mz_capacitive_fpi") + set(MCU_CARD FALSE) +endif() diff --git a/bsp/board/include/boards/mikromedia_4_stm32f2_capacitive_fpi/board.cmake b/bsp/board/include/boards/mikromedia_4_stm32f2_capacitive_fpi/board.cmake new file mode 100644 index 000000000..a6b49f293 --- /dev/null +++ b/bsp/board/include/boards/mikromedia_4_stm32f2_capacitive_fpi/board.cmake @@ -0,0 +1,4 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "MIKROMEDIA4FORSTM32F2CAPACITIVEFPI") + set(BOARD_PATH "include/boards/mikromedia_4_stm32f2_capacitive_fpi") + set(MCU_CARD FALSE) +endif() diff --git a/bsp/board/include/boards/mikromedia_4_stm32f2_resistive_fpi/board.cmake b/bsp/board/include/boards/mikromedia_4_stm32f2_resistive_fpi/board.cmake new file mode 100644 index 000000000..71fdea286 --- /dev/null +++ b/bsp/board/include/boards/mikromedia_4_stm32f2_resistive_fpi/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "MIKROMEDIA4FORSTM32F2RESISTIVEFPI") + set(BOARD_PATH "include/boards/mikromedia_4_stm32f2_resistive_fpi") + set(MCU_CARD FALSE) + set(SHIELD FALSE) +endif() diff --git a/bsp/board/include/boards/mikromedia_4_stm32f4_capacitive/board.cmake b/bsp/board/include/boards/mikromedia_4_stm32f4_capacitive/board.cmake new file mode 100644 index 000000000..f66e7152a --- /dev/null +++ b/bsp/board/include/boards/mikromedia_4_stm32f4_capacitive/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "MIKROMEDIA4FORSTM32F4CAPACITIVE") + set(BOARD_PATH "include/boards/mikromedia_4_stm32f4_capacitive") + set(MCU_CARD FALSE) + set(SHIELD TRUE) +endif() diff --git a/bsp/board/include/boards/mikromedia_4_stm32f4_capacitive_fpi/board.cmake b/bsp/board/include/boards/mikromedia_4_stm32f4_capacitive_fpi/board.cmake new file mode 100644 index 000000000..851090cb3 --- /dev/null +++ b/bsp/board/include/boards/mikromedia_4_stm32f4_capacitive_fpi/board.cmake @@ -0,0 +1,4 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "MIKROMEDIA4FORSTM32F4CAPACITIVEFPI") + set(BOARD_PATH "include/boards/mikromedia_4_stm32f4_capacitive_fpi") + set(MCU_CARD FALSE) +endif() diff --git a/bsp/board/include/boards/mikromedia_4_stm32f4_resistive/board.cmake b/bsp/board/include/boards/mikromedia_4_stm32f4_resistive/board.cmake new file mode 100644 index 000000000..3484e0d01 --- /dev/null +++ b/bsp/board/include/boards/mikromedia_4_stm32f4_resistive/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "MIKROMEDIA4FORSTM32F4RESISTIVE") + set(BOARD_PATH "include/boards/mikromedia_4_stm32f4_resistive") + set(MCU_CARD FALSE) + set(SHIELD TRUE) +endif() diff --git a/bsp/board/include/boards/mikromedia_4_stm32f4_resistive/board.h b/bsp/board/include/boards/mikromedia_4_stm32f4_resistive/board.h new file mode 100644 index 000000000..8e9f0cc7e --- /dev/null +++ b/bsp/board/include/boards/mikromedia_4_stm32f4_resistive/board.h @@ -0,0 +1,217 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file board.h + * @brief Main board pin mapping. + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_target.h" +#include "shield.h" + +// Hardware revision number +#define BOARD_REV_MAJOR (1) +#define BOARD_REV_MINOR (03) + +#define BOARD_NAME "Mikromedia 4 for STM32F4 Resistive" + +/// Mapping +#define TFT_RST PF14 +#define TFT_CS PF13 +#define TFT_D_C PF15 +#define TFT_RD PF12 +#define TFT_WR PF11 +#define TFT_TE PD4 +#define TFT_GPIO PG5 +#define TFT_BPWM HAL_PIN_NC +#define TFT_D0 PE0 +#define TFT_D1 PE1 +#define TFT_D2 PE2 +#define TFT_D3 PE3 +#define TFT_D4 PE4 +#define TFT_D5 PE5 +#define TFT_D6 PE6 +#define TFT_D7 PE7 +#define TFT_D8 PE8 +#define TFT_D9 PE9 +#define TFT_D10 PE10 +#define TFT_D11 PE11 +#define TFT_D12 PE12 +#define TFT_D13 PE13 +#define TFT_D14 PE14 +#define TFT_D15 PE15 + +#define TFT_8BIT_DATA_PORT_CH0 PORT_E +#define TFT_8BIT_DATA_PORT_CH0_MASK 0x00FF + +#define TFT_16BIT_DATA_PORT_CH0 PORT_E +#define TFT_16BIT_DATA_PORT_CH0_MASK 0xFFFF + +#define TFT_16BIT_DATA_PORT_CH1 HAL_PORT_NC +#define TFT_16BIT_DATA_PORT_CH1_MASK 0x0000 + +#define CTP_SDA PB7 +#define CTP_SCL PB6 +#define CTP_INT PA0 +#define CTP_WAKE PF6 +#define CTP_RST HAL_PIN_NC + +#define NRF_CE PG12 +#define NRF_CS PG9 +#define NRF_SCK PB13 +#define NRF_SDI PB15 +#define NRF_SDO PB14 +#define NRF_INT PG10 + +#define ETH_RXER PB10 +#define ETH_TXD0 PG13 +#define ETH_TDD1 PG14 +#define ETH_RXD0 PC4 +#define ETH_RXD1 PC5 +#define ETH_TXEN PG11 +#define ETH_CRS_DV PA7 +#define ETH_MDIO PA2 +#define ETH_RST PG8 +#define ETH_CLKO PA1 +#define ETH_MDC PC1 +#define ETH_INT PG6 + +#define USB_SW_ID PA10 +#define USB_VBUS PA9 +#define USB_N PA11 +#define USB_P PA12 +#define USB_PSW PD6 + +#define SD_CS PC11 +#define SD_MOSI PD2 +#define SD_SCK PC12 +#define SD_MISO PC8 +#define SD_CD PD3 + +#define FLASH_CS PB11 +#define FLASH_MISO PB14 +#define FLASH_SCK PB13 +#define FLASH_MOSI PB15 + +#define MP3_SCLK PB13 +#define MP3_SIN PB15 +#define MP3_SOUT PB14 +#define MP3_CS PD11 +#define MP3_RST PD8 +#define MP3_DREQ PD9 +#define MP3_DCS PD10 + +#define ALS_SDA PB7 +#define ALS_SCL PB6 + +#define ACCEL_SDA PB7 +#define ACCEL_SCL PB6 +#define ACCEL_INT2 PF2 +#define ACCEL_INT1 PB9 + +#define BUZZER PB8 + +#define IR_TX PF10 + +#define LED_R PF7 +#define LED_G PD14 +#define LED_B PD15 + +#define TEMP_SENS PF4 + +#define CAN_RX PD0 +#define CAN_TX PD1 + +#define POWER_BAT_SENSE PF5 +#define POWER_STATUS PF3 +#define POWER_DC_DETECT PG15 + +#define USB_UART_TX HAL_PIN_NC +#define USB_UART_RX HAL_PIN_NC + +#define SHIELD_CONNECTOR_J1_PIN3 PA4 +#define SHIELD_CONNECTOR_J1_PIN4 PB0 +#define SHIELD_CONNECTOR_J1_PIN5 PB1 +#define SHIELD_CONNECTOR_J1_PIN6 PC0 +#define SHIELD_CONNECTOR_J1_PIN7 PC2 +#define SHIELD_CONNECTOR_J1_PIN8 PC3 +#define SHIELD_CONNECTOR_J1_PIN9 PG4 +#define SHIELD_CONNECTOR_J1_PIN10 PC13 +#define SHIELD_CONNECTOR_J1_PIN11 PB12 +#define SHIELD_CONNECTOR_J1_PIN12 PB13 +#define SHIELD_CONNECTOR_J1_PIN13 PB14 +#define SHIELD_CONNECTOR_J1_PIN14 PB15 +#define SHIELD_CONNECTOR_J1_PIN15 PD0 +#define SHIELD_CONNECTOR_J1_PIN16 PD1 +#define SHIELD_CONNECTOR_J1_PIN17 PA15 +#define SHIELD_CONNECTOR_J1_PIN18 PA5 +#define SHIELD_CONNECTOR_J1_PIN19 PA6 +#define SHIELD_CONNECTOR_J1_PIN20 PB5 + +#define SHIELD_CONNECTOR_J2_PIN7 PD12 +#define SHIELD_CONNECTOR_J2_PIN8 PD13 +#define SHIELD_CONNECTOR_J2_PIN9 PB3 +#define SHIELD_CONNECTOR_J2_PIN10 PB4 +#define SHIELD_CONNECTOR_J2_PIN11 PF8 +#define SHIELD_CONNECTOR_J2_PIN12 PF9 +#define SHIELD_CONNECTOR_J2_PIN13 PG0 +#define SHIELD_CONNECTOR_J2_PIN14 PG1 +#define SHIELD_CONNECTOR_J2_PIN15 PG2 +#define SHIELD_CONNECTOR_J2_PIN16 PG3 +#define SHIELD_CONNECTOR_J2_PIN17 PF1 +#define SHIELD_CONNECTOR_J2_PIN18 PF0 +#define SHIELD_CONNECTOR_J2_PIN19 PC7 +#define SHIELD_CONNECTOR_J2_PIN20 PC6 +#define SHIELD_CONNECTOR_J2_PIN21 PA3 +#define SHIELD_CONNECTOR_J2_PIN22 PD5 +#define SHIELD_CONNECTOR_J2_PIN23 PB6 +#define SHIELD_CONNECTOR_J2_PIN24 PB7 + +#ifdef __cplusplus +} +#endif + +#endif // _BOARD_H_ +// ------------------------------------------------------------------------- END diff --git a/bsp/board/include/boards/mikromedia_4_stm32f4_resistive_fpi/board.cmake b/bsp/board/include/boards/mikromedia_4_stm32f4_resistive_fpi/board.cmake new file mode 100644 index 000000000..54a04e8be --- /dev/null +++ b/bsp/board/include/boards/mikromedia_4_stm32f4_resistive_fpi/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "MIKROMEDIA4FORSTM32F4RESISTIVEFPI") + set(BOARD_PATH "include/boards/mikromedia_4_stm32f4_resistive_fpi") + set(MCU_CARD FALSE) + set(SHIELD FALSE) +endif() diff --git a/bsp/board/include/boards/mikromedia_4_stm32f7_capacitive/board.cmake b/bsp/board/include/boards/mikromedia_4_stm32f7_capacitive/board.cmake new file mode 100644 index 000000000..5776596e7 --- /dev/null +++ b/bsp/board/include/boards/mikromedia_4_stm32f7_capacitive/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "MIKROMEDIA4FORSTM32F7CAPACITIVE") + set(BOARD_PATH "include/boards/mikromedia_4_stm32f7_capacitive") + set(MCU_CARD FALSE) + set(SHIELD TRUE) +endif() diff --git a/bsp/board/include/boards/mikromedia_4_stm32f7_resistive/board.cmake b/bsp/board/include/boards/mikromedia_4_stm32f7_resistive/board.cmake new file mode 100644 index 000000000..003e74fec --- /dev/null +++ b/bsp/board/include/boards/mikromedia_4_stm32f7_resistive/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "MIKROMEDIA4FORSTM32F7RESISTIVE") + set(BOARD_PATH "include/boards/mikromedia_4_stm32f7_resistive") + set(MCU_CARD FALSE) + set(SHIELD TRUE) +endif() diff --git a/bsp/board/include/boards/mikromedia_5_kinetis_capacitive/board.cmake b/bsp/board/include/boards/mikromedia_5_kinetis_capacitive/board.cmake new file mode 100644 index 000000000..5977ebbbc --- /dev/null +++ b/bsp/board/include/boards/mikromedia_5_kinetis_capacitive/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "MIKROMEDIA5FORKINETISCAPACITIVE") + set(BOARD_PATH "include/boards/mikromedia_5_kinetis_capacitive") + set(MCU_CARD FALSE) + set(SHIELD TRUE) +endif() diff --git a/bsp/board/include/boards/mikromedia_5_kinetis_capacitive_fpi/board.cmake b/bsp/board/include/boards/mikromedia_5_kinetis_capacitive_fpi/board.cmake new file mode 100644 index 000000000..fb9f47a38 --- /dev/null +++ b/bsp/board/include/boards/mikromedia_5_kinetis_capacitive_fpi/board.cmake @@ -0,0 +1,4 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "MIKROMEDIA5FORKINETISCAPACITIVEFPI") + set(BOARD_PATH "include/boards/mikromedia_5_kinetis_capacitive_fpi") + set(MCU_CARD FALSE) +endif() diff --git a/bsp/board/include/boards/mikromedia_5_kinetis_resistive/board.cmake b/bsp/board/include/boards/mikromedia_5_kinetis_resistive/board.cmake new file mode 100644 index 000000000..fa0db9d27 --- /dev/null +++ b/bsp/board/include/boards/mikromedia_5_kinetis_resistive/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "MIKROMEDIA5FORKINETISRESISTIVE") + set(BOARD_PATH "include/boards/mikromedia_5_kinetis_resistive") + set(MCU_CARD FALSE) + set(SHIELD TRUE) +endif() diff --git a/bsp/board/include/boards/mikromedia_5_kinetis_resistive_fpi/board.cmake b/bsp/board/include/boards/mikromedia_5_kinetis_resistive_fpi/board.cmake new file mode 100644 index 000000000..6fae305e9 --- /dev/null +++ b/bsp/board/include/boards/mikromedia_5_kinetis_resistive_fpi/board.cmake @@ -0,0 +1,4 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "MIKROMEDIA5FORKINETISRESISTIVEFPI") + set(BOARD_PATH "include/boards/mikromedia_5_kinetis_resistive_fpi") + set(MCU_CARD FALSE) +endif() diff --git a/bsp/board/include/boards/mikromedia_5_pic32mz_capacitive/board.cmake b/bsp/board/include/boards/mikromedia_5_pic32mz_capacitive/board.cmake new file mode 100644 index 000000000..29d67d9dc --- /dev/null +++ b/bsp/board/include/boards/mikromedia_5_pic32mz_capacitive/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "MIKROMEDIA5FORPIC32MZCAPACITIVE") + set(BOARD_PATH "include/boards/mikromedia_5_pic32mz_capacitive") + set(MCU_CARD FALSE) + set(SHIELD TRUE) +endif() diff --git a/bsp/board/include/boards/mikromedia_5_pic32mz_capacitive_fpi/board.cmake b/bsp/board/include/boards/mikromedia_5_pic32mz_capacitive_fpi/board.cmake new file mode 100644 index 000000000..d0ac057fc --- /dev/null +++ b/bsp/board/include/boards/mikromedia_5_pic32mz_capacitive_fpi/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "MIKROMEDIA5FORPIC32MZCAPACITIVEFPI") + set(BOARD_PATH "include/boards/mikromedia_5_pic32mz_capacitive_fpi") + set(MCU_CARD FALSE) + set(MIKROBUS FALSE) +endif() diff --git a/bsp/board/include/boards/mikromedia_5_stm32f4_capacitive/board.cmake b/bsp/board/include/boards/mikromedia_5_stm32f4_capacitive/board.cmake new file mode 100644 index 000000000..28b63c113 --- /dev/null +++ b/bsp/board/include/boards/mikromedia_5_stm32f4_capacitive/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "MIKROMEDIA5FORSTM32F4CAPACITIVE") + set(BOARD_PATH "include/boards/mikromedia_5_stm32f4_capacitive") + set(MCU_CARD FALSE) + set(SHIELD TRUE) +endif() diff --git a/bsp/board/include/boards/mikromedia_5_stm32f4_capacitive_fpi/board.cmake b/bsp/board/include/boards/mikromedia_5_stm32f4_capacitive_fpi/board.cmake new file mode 100644 index 000000000..37b0843b7 --- /dev/null +++ b/bsp/board/include/boards/mikromedia_5_stm32f4_capacitive_fpi/board.cmake @@ -0,0 +1,4 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "MIKROMEDIA5FORSTM32F4CAPACITIVEFPI") + set(BOARD_PATH "include/boards/mikromedia_5_stm32f4_capacitive_fpi") + set(MCU_CARD FALSE) +endif() diff --git a/bsp/board/include/boards/mikromedia_5_stm32f4_resistive/board.cmake b/bsp/board/include/boards/mikromedia_5_stm32f4_resistive/board.cmake new file mode 100644 index 000000000..7885f8186 --- /dev/null +++ b/bsp/board/include/boards/mikromedia_5_stm32f4_resistive/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "MIKROMEDIA5FORSTM32F4RESISTIVE") + set(BOARD_PATH "include/boards/mikromedia_5_stm32f4_resistive") + set(MCU_CARD FALSE) + set(SHIELD TRUE) +endif() diff --git a/bsp/board/include/boards/mikromedia_5_stm32f4_resistive/board.h b/bsp/board/include/boards/mikromedia_5_stm32f4_resistive/board.h new file mode 100644 index 000000000..e16207abe --- /dev/null +++ b/bsp/board/include/boards/mikromedia_5_stm32f4_resistive/board.h @@ -0,0 +1,223 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file board.h + * @brief Main board pin mapping. + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_target.h" +#include "shield.h" + +// Hardware revision number +#define BOARD_REV_MAJOR (1) +#define BOARD_REV_MINOR (03) + +#define BOARD_NAME "Mikromedia 5 for STM32F4 Resistive" + +/// Mapping +#define TFT_RST PF14 +#define TFT_CS PF13 +#define TFT_D_C PF15 +#define TFT_RD PF12 +#define TFT_WR PF11 +#define TFT_TE PD4 +#define TFT_GPIO PG5 +#define TFT_BPWM HAL_PIN_NC +#define TFT_D0 PE0 +#define TFT_D1 PE1 +#define TFT_D2 PE2 +#define TFT_D3 PE3 +#define TFT_D4 PE4 +#define TFT_D5 PE5 +#define TFT_D6 PE6 +#define TFT_D7 PE7 +#define TFT_D8 PE8 +#define TFT_D9 PE9 +#define TFT_D10 PE10 +#define TFT_D11 PE11 +#define TFT_D12 PE12 +#define TFT_D13 PE13 +#define TFT_D14 PE14 +#define TFT_D15 PE15 + +#define TFT_8BIT_DATA_PORT_CH0 PORT_E +#define TFT_8BIT_DATA_PORT_CH0_MASK 0x00FF + +#define TFT_16BIT_DATA_PORT_CH0 PORT_E +#define TFT_16BIT_DATA_PORT_CH0_MASK 0xFFFF + +#define TFT_16BIT_DATA_PORT_CH1 HAL_PORT_NC +#define TFT_16BIT_DATA_PORT_CH1_MASK 0x0000 + +#define CTP_SDA PB7 +#define CTP_SCL PB6 +#define CTP_INT PA0 +#define CTP_WAKE HAL_PIN_NC +#define CTP_RST PB2 + +#define WIFI_NHIB PC11 +#define WIFI_MOSI PA5 +#define WIFI_MISO PB5 +#define WIFI_CS PA6 +#define WIFI_RESET PC12 + +#define NRF_CE PG12 +#define NRF_CS PG9 +#define NRF_SCK PB13 +#define NRF_SDI PB15 +#define NRF_SDO PB14 +#define NRF_INT PG10 + +#define ETH_RXER PB10 +#define ETH_TXD0 PG13 +#define ETH_TDD1 PG14 +#define ETH_RXD0 PC4 +#define ETH_RXD1 PC5 +#define ETH_TXEN PG11 +#define ETH_CRS_DV PA7 +#define ETH_MDIO PA2 +#define ETH_RST PG8 +#define ETH_CLKO PA1 +#define ETH_MDC PC1 +#define ETH_INT PG6 + +#define USB_SW_ID PA10 +#define USB_VBUS PA9 +#define USB_N PA11 +#define USB_P PA12 +#define USB_PSW PD6 + +#define SD_CS PD2 +#define SD_MOSI PB5 +#define SD_SCK PA5 +#define SD_MISO PA6 +#define SD_CD PD3 + +#define FLASH_CS PB11 +#define FLASH_MISO PB14 +#define FLASH_SCK PB13 +#define FLASH_MOSI PB15 + +#define MP3_SCLK PB13 +#define MP3_SIN PB15 +#define MP3_SOUT PB14 +#define MP3_CS PD11 +#define MP3_RST PD8 +#define MP3_DREQ PD9 +#define MP3_DCS PD10 + +#define ALS_SDA PB7 +#define ALS_SCL PB6 + +#define ACCEL_SDA PB7 +#define ACCEL_SCL PB6 +#define ACCEL_INT2 PF2 +#define ACCEL_INT1 PB9 + +#define BUZZER PB8 + +#define IR_TX PF10 + +#define LED_R PF7 +#define LED_G PD14 +#define LED_B PD15 + +#define TEMP_SENS PF4 + +#define CAN_RX PD0 +#define CAN_TX PD1 + +#define POWER_BAT_SENSE PF5 +#define POWER_STATUS PF3 +#define POWER_DC_DETECT PF6 + +#define USB_UART_TX HAL_PIN_NC +#define USB_UART_RX HAL_PIN_NC + +#define SHIELD_CONNECTOR_J1_PIN3 PA4 +#define SHIELD_CONNECTOR_J1_PIN4 PB0 +#define SHIELD_CONNECTOR_J1_PIN5 PB1 +#define SHIELD_CONNECTOR_J1_PIN6 PC0 +#define SHIELD_CONNECTOR_J1_PIN7 PC2 +#define SHIELD_CONNECTOR_J1_PIN8 PC3 +#define SHIELD_CONNECTOR_J1_PIN9 PC13 +#define SHIELD_CONNECTOR_J1_PIN10 PG4 +#define SHIELD_CONNECTOR_J1_PIN11 PB12 +#define SHIELD_CONNECTOR_J1_PIN12 PB13 +#define SHIELD_CONNECTOR_J1_PIN13 PB14 +#define SHIELD_CONNECTOR_J1_PIN14 PB15 +#define SHIELD_CONNECTOR_J1_PIN15 PD0 +#define SHIELD_CONNECTOR_J1_PIN16 PD1 +#define SHIELD_CONNECTOR_J1_PIN17 PA15 +#define SHIELD_CONNECTOR_J1_PIN18 PA5 +#define SHIELD_CONNECTOR_J1_PIN19 PA6 +#define SHIELD_CONNECTOR_J1_PIN20 PB5 + +#define SHIELD_CONNECTOR_J2_PIN7 PD12 +#define SHIELD_CONNECTOR_J2_PIN8 PD13 +#define SHIELD_CONNECTOR_J2_PIN9 PB3 +#define SHIELD_CONNECTOR_J2_PIN10 PB4 +#define SHIELD_CONNECTOR_J2_PIN11 PF8 +#define SHIELD_CONNECTOR_J2_PIN12 PF9 +#define SHIELD_CONNECTOR_J2_PIN13 PG0 +#define SHIELD_CONNECTOR_J2_PIN14 PG1 +#define SHIELD_CONNECTOR_J2_PIN15 PG2 +#define SHIELD_CONNECTOR_J2_PIN16 PG3 +#define SHIELD_CONNECTOR_J2_PIN17 PF1 +#define SHIELD_CONNECTOR_J2_PIN18 PF0 +#define SHIELD_CONNECTOR_J2_PIN19 PC7 +#define SHIELD_CONNECTOR_J2_PIN20 PC6 +#define SHIELD_CONNECTOR_J2_PIN21 PA3 +#define SHIELD_CONNECTOR_J2_PIN22 PD5 +#define SHIELD_CONNECTOR_J2_PIN23 PB6 +#define SHIELD_CONNECTOR_J2_PIN24 PB7 + +#ifdef __cplusplus +} +#endif + +#endif // _BOARD_H_ +// ------------------------------------------------------------------------- END diff --git a/bsp/board/include/boards/mikromedia_5_stm32f4_resistive_fpi/board.cmake b/bsp/board/include/boards/mikromedia_5_stm32f4_resistive_fpi/board.cmake new file mode 100644 index 000000000..10a6241d6 --- /dev/null +++ b/bsp/board/include/boards/mikromedia_5_stm32f4_resistive_fpi/board.cmake @@ -0,0 +1,4 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "MIKROMEDIA5FORSTM32F4RESISTIVEFPI") + set(BOARD_PATH "include/boards/mikromedia_5_stm32f4_resistive_fpi") + set(MCU_CARD FALSE) +endif() diff --git a/bsp/board/include/boards/mikromedia_5_stm32f7_capacitive/board.cmake b/bsp/board/include/boards/mikromedia_5_stm32f7_capacitive/board.cmake new file mode 100644 index 000000000..09c23fb4e --- /dev/null +++ b/bsp/board/include/boards/mikromedia_5_stm32f7_capacitive/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "MIKROMEDIA5FORSTM32F7CAPACITIVE") + set(BOARD_PATH "include/boards/mikromedia_5_stm32f7_capacitive") + set(MCU_CARD FALSE) + set(SHIELD TRUE) +endif() diff --git a/bsp/board/include/boards/mikromedia_5_stm32f7_capacitive_fpi/board.cmake b/bsp/board/include/boards/mikromedia_5_stm32f7_capacitive_fpi/board.cmake new file mode 100644 index 000000000..93b6d3759 --- /dev/null +++ b/bsp/board/include/boards/mikromedia_5_stm32f7_capacitive_fpi/board.cmake @@ -0,0 +1,4 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "MIKROMEDIA5FORSTM32F7CAPACITIVEFPI") + set(BOARD_PATH "include/boards/mikromedia_5_stm32f7_capacitive_fpi") + set(MCU_CARD FALSE) +endif() diff --git a/bsp/board/include/boards/mikromedia_5_stm32f7_resistive/board.cmake b/bsp/board/include/boards/mikromedia_5_stm32f7_resistive/board.cmake new file mode 100644 index 000000000..8f54df7bf --- /dev/null +++ b/bsp/board/include/boards/mikromedia_5_stm32f7_resistive/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "MIKROMEDIA5FORSTM32F7RESISTIVE") + set(BOARD_PATH "include/boards/mikromedia_5_stm32f7_resistive") + set(MCU_CARD FALSE) + set(SHIELD TRUE) +endif() diff --git a/bsp/board/include/boards/mikromedia_5_stm32f7_resistive_fpi/board.cmake b/bsp/board/include/boards/mikromedia_5_stm32f7_resistive_fpi/board.cmake new file mode 100644 index 000000000..c8bb3ef30 --- /dev/null +++ b/bsp/board/include/boards/mikromedia_5_stm32f7_resistive_fpi/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "MIKROMEDIA5FORSTM32F7RESISTIVEFPI") + set(BOARD_PATH "include/boards/mikromedia_5_stm32f7_resistive_fpi") + set(MCU_CARD FALSE) + set(SHIELD FALSE) +endif() diff --git a/bsp/board/include/boards/mikromedia_7_capacitive/board.cmake b/bsp/board/include/boards/mikromedia_7_capacitive/board.cmake new file mode 100644 index 000000000..22800313c --- /dev/null +++ b/bsp/board/include/boards/mikromedia_7_capacitive/board.cmake @@ -0,0 +1,4 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "MIKROMEDIA7CAPACITIVE") + set(BOARD_PATH "include/boards/mikromedia_7_capacitive") + set(SHIELD TRUE) +endif() diff --git a/bsp/board/include/boards/mikromedia_7_resistive/board.cmake b/bsp/board/include/boards/mikromedia_7_resistive/board.cmake new file mode 100644 index 000000000..07dd98d54 --- /dev/null +++ b/bsp/board/include/boards/mikromedia_7_resistive/board.cmake @@ -0,0 +1,4 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "MIKROMEDIA7RESISTIVE") + set(BOARD_PATH "include/boards/mikromedia_7_resistive") + set(SHIELD TRUE) +endif() diff --git a/bsp/board/include/boards/mikromedia_7_resistive_fpi/board.cmake b/bsp/board/include/boards/mikromedia_7_resistive_fpi/board.cmake new file mode 100644 index 000000000..fd4f6b274 --- /dev/null +++ b/bsp/board/include/boards/mikromedia_7_resistive_fpi/board.cmake @@ -0,0 +1,4 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "MIKROMEDIA7RESISTIVEFPI") + set(BOARD_PATH "include/boards/mikromedia_7_resistive_fpi") + set(SHIELD FALSE) +endif() diff --git a/bsp/board/include/boards/mikromedia_7_stm32f4/board.cmake b/bsp/board/include/boards/mikromedia_7_stm32f4/board.cmake new file mode 100644 index 000000000..0459f6001 --- /dev/null +++ b/bsp/board/include/boards/mikromedia_7_stm32f4/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "MIKROMEDIA7FORSTM32F4") + set(BOARD_PATH "include/boards/mikromedia_7_stm32f4") + set(MCU_CARD FALSE) + set(SHIELD TRUE) +endif() diff --git a/bsp/board/include/boards/mikromedia_7_stm32f7/board.cmake b/bsp/board/include/boards/mikromedia_7_stm32f7/board.cmake new file mode 100644 index 000000000..ee24064e6 --- /dev/null +++ b/bsp/board/include/boards/mikromedia_7_stm32f7/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "MIKROMEDIA7FORSTM32F7") + set(BOARD_PATH "include/boards/mikromedia_7_stm32f7") + set(MCU_CARD FALSE) + set(SHIELD TRUE) +endif() diff --git a/bsp/board/include/boards/mikromedia_for_dspic33/board.cmake b/bsp/board/include/boards/mikromedia_for_dspic33/board.cmake new file mode 100644 index 000000000..eb2406a86 --- /dev/null +++ b/bsp/board/include/boards/mikromedia_for_dspic33/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "MIKROMEDIAFORDSPIC33") + set(BOARD_PATH "include/boards/mikromedia_for_dspic33") + set(MCU_CARD FALSE) + set(SHIELD TRUE) +endif() diff --git a/bsp/board/include/boards/mikromedia_for_dspic33ep/board.cmake b/bsp/board/include/boards/mikromedia_for_dspic33ep/board.cmake new file mode 100644 index 000000000..5147b23ad --- /dev/null +++ b/bsp/board/include/boards/mikromedia_for_dspic33ep/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "MIKROMEDIAFORDSPIC33EP") + set(BOARD_PATH "include/boards/mikromedia_for_dspic33ep") + set(MCU_CARD FALSE) + set(SHIELD TRUE) +endif() diff --git a/bsp/board/include/boards/mikromedia_for_pic18fj/board.cmake b/bsp/board/include/boards/mikromedia_for_pic18fj/board.cmake new file mode 100644 index 000000000..3f0bb6013 --- /dev/null +++ b/bsp/board/include/boards/mikromedia_for_pic18fj/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "MIKROMEDIAFORPIC18FJ") + set(BOARD_PATH "include/boards/mikromedia_for_pic18fj") + set(MCU_CARD FALSE) + set(SHIELD TRUE) +endif() diff --git a/bsp/board/include/boards/mikromedia_for_pic18fk/board.cmake b/bsp/board/include/boards/mikromedia_for_pic18fk/board.cmake new file mode 100644 index 000000000..92fc0c633 --- /dev/null +++ b/bsp/board/include/boards/mikromedia_for_pic18fk/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "MIKROMEDIAFORPIC18FK") + set(BOARD_PATH "include/boards/mikromedia_for_pic18fk") + set(MCU_CARD FALSE) + set(SHIELD TRUE) +endif() diff --git a/bsp/board/include/boards/mikromedia_for_pic24/board.cmake b/bsp/board/include/boards/mikromedia_for_pic24/board.cmake new file mode 100644 index 000000000..5442ae3e1 --- /dev/null +++ b/bsp/board/include/boards/mikromedia_for_pic24/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "MIKROMEDIAFORPIC24") + set(BOARD_PATH "include/boards/mikromedia_for_pic24") + set(MCU_CARD FALSE) + set(SHIELD TRUE) +endif() diff --git a/bsp/board/include/boards/mikromedia_for_pic24ep/board.cmake b/bsp/board/include/boards/mikromedia_for_pic24ep/board.cmake new file mode 100644 index 000000000..843bf27d9 --- /dev/null +++ b/bsp/board/include/boards/mikromedia_for_pic24ep/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "MIKROMEDIAFORPIC24EP") + set(BOARD_PATH "include/boards/mikromedia_for_pic24ep") + set(MCU_CARD FALSE) + set(SHIELD TRUE) +endif() diff --git a/bsp/board/include/boards/mikromedia_for_pic32/board.cmake b/bsp/board/include/boards/mikromedia_for_pic32/board.cmake new file mode 100644 index 000000000..4a5e7456a --- /dev/null +++ b/bsp/board/include/boards/mikromedia_for_pic32/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "MIKROMEDIAFORPIC32") + set(BOARD_PATH "include/boards/mikromedia_for_pic32") + set(MCU_CARD FALSE) + set(SHIELD TRUE) +endif() diff --git a/bsp/board/include/boards/mikromedia_for_stm32_f3_f4/board.cmake b/bsp/board/include/boards/mikromedia_for_stm32_f3_f4/board.cmake new file mode 100644 index 000000000..2d27c9a8d --- /dev/null +++ b/bsp/board/include/boards/mikromedia_for_stm32_f3_f4/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "MIKROMEDIAFORSTM32F3F4") + set(BOARD_PATH "include/boards/mikromedia_for_stm32_f3_f4") + set(MCU_CARD FALSE) + set(SHIELD TRUE) +endif() diff --git a/bsp/board/include/boards/mikromedia_for_tiva/board.cmake b/bsp/board/include/boards/mikromedia_for_tiva/board.cmake new file mode 100644 index 000000000..2ad8d5ff9 --- /dev/null +++ b/bsp/board/include/boards/mikromedia_for_tiva/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "MIKROMEDIAFORTIVACSERIES") + set(BOARD_PATH "include/boards/mikromedia_for_tiva") + set(MCU_CARD FALSE) + set(SHIELD TRUE) +endif() diff --git a/bsp/board/include/boards/mikromedia_for_xmega/board.cmake b/bsp/board/include/boards/mikromedia_for_xmega/board.cmake new file mode 100644 index 000000000..db3b985cd --- /dev/null +++ b/bsp/board/include/boards/mikromedia_for_xmega/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "MIKROMEDIAFORXMEGA") + set(BOARD_PATH "include/boards/mikromedia_for_xmega") + set(MCU_CARD FALSE) + set(SHIELD TRUE) +endif() diff --git a/bsp/board/include/boards/mikromedia_plus_pic32mx7/board.cmake b/bsp/board/include/boards/mikromedia_plus_pic32mx7/board.cmake new file mode 100644 index 000000000..acb4387b0 --- /dev/null +++ b/bsp/board/include/boards/mikromedia_plus_pic32mx7/board.cmake @@ -0,0 +1,4 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "MIKROMEDIAPLUSFORPIC32MX7") + set(BOARD_PATH "include/boards/mikromedia_plus_pic32mx7") + set(MCU_CARD FALSE) +endif() diff --git a/bsp/board/include/boards/mikromedia_plus_stm32/board.cmake b/bsp/board/include/boards/mikromedia_plus_stm32/board.cmake new file mode 100644 index 000000000..457d53cc6 --- /dev/null +++ b/bsp/board/include/boards/mikromedia_plus_stm32/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "MIKROMEDIAPLUSFORSTM32") + set(BOARD_PATH "include/boards/mikromedia_plus_stm32") + set(MCU_CARD FALSE) + set(SHIELD TRUE) +endif() diff --git a/bsp/board/include/boards/mikromedia_plus_stm32f7/board.cmake b/bsp/board/include/boards/mikromedia_plus_stm32f7/board.cmake new file mode 100644 index 000000000..9bc5b2aaf --- /dev/null +++ b/bsp/board/include/boards/mikromedia_plus_stm32f7/board.cmake @@ -0,0 +1,5 @@ +if(${_MSDK_BOARD_NAME_} STREQUAL "MIKROMEDIAPLUSFORSTM32F7") + set(BOARD_PATH "include/boards/mikromedia_plus_stm32f7") + set(MCU_CARD FALSE) + set(SHIELD TRUE) +endif() diff --git a/cmake/aiUtils.cmake b/cmake/aiUtils.cmake new file mode 100644 index 000000000..3a214fb96 --- /dev/null +++ b/cmake/aiUtils.cmake @@ -0,0 +1,54 @@ +############################################################################# +## Macro to get a list of files in the provided folder and all subfolders +############################################################################# +macro(get_files_recurse search_path file_list extension) + file(GLOB_RECURSE ${file_list} ${search_path}/*.${extension}) +endmacro() + +############################################################################# +## Macro to get all subsequent directories for AI generated file and check +## if current module is supported or not. +############################################################################# +macro(check_if_module_is_generated isGenerated fileList) + ## Set variable as FALSE initially + set(${isGenerated} false) + + ## Go through all found cmake files + foreach(CMAKE_FILE ${fileList}) + ## Read the file content + file(READ ${CMAKE_FILE} CURRENT_CMAKE_FILE_CONTENT) + ## Search for current MCU in the file + string(REGEX MATCH ${MCU_NAME} CHECK_IF_SUPPORTED ${CURRENT_CMAKE_FILE_CONTENT}) + ## If the MCU is present in the file + if(CHECK_IF_SUPPORTED) + if(${CHECK_IF_SUPPORTED} STREQUAL ${MCU_NAME}) + ## Set the variable to TRUE and exit the loop + set(${isGenerated} true) + break() + endif() + endif() + endforeach() + + ## Emit a message if no files were found/generated + if(NOT ${isGenerated}) + message(STATUS ": NO CMAKE FILES FOUND FOR ${CMAKE_CURRENT_SOURCE_DIR}") + endif() +endmacro() + +############################################################################# +## Macro to get all subsequent directories for AI generated file and check +## if current module is supported or not. +############################################################################# +macro(add_module_if_generated searchPath listOut appendIt) + set(IS_MODULE_GENERATED false) + get_files_recurse(${searchPath} CMAKE_FILE_LIST cmake) + if(CMAKE_FILE_LIST) + check_if_module_is_generated(IS_MODULE_GENERATED "${CMAKE_FILE_LIST}") + endif() + if(IS_MODULE_GENERATED) + list(APPEND ${listOut} ${appendIt}) + else() + ## Emit a message if no files were found/generated + message(STATUS ": NO CMAKE FILES FOUND FOR ${CMAKE_CURRENT_SOURCE_DIR}/${appendIt}") + endif() +endmacro() diff --git a/middleware/hw/hw_eth/include/pic32/implementation_1/hw_eth.h b/middleware/hw/hw_eth/include/pic32/implementation_1/hw_eth.h new file mode 100644 index 000000000..7a2ae9bea --- /dev/null +++ b/middleware/hw/hw_eth/include/pic32/implementation_1/hw_eth.h @@ -0,0 +1,125 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hw_eth.h + * @brief Initializes ETH HW module. + * @details Sets clock, pins, etc. + */ + +#ifndef _HW_ETH_H_ +#define _HW_ETH_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "mcu.h" +#include "net.h" + +/*! + * @addtogroup middleware Middleware + * @{ + */ + +/*! + * @addtogroup ethernet MikroE ETH HW implementation. + * @brief MikroE ETH HW init library. + * + * @details This library initializes HW specific + * ethernet pins/clock etc. + * @{ + */ + +/** + * @brief Initializes ETH. + * @details Sets appropriate clock settings. + * Sets appropriate pins if necessary. + * @param None + * @note Needs to be implemented by user for current MCU. + * @return None + */ +static inline void hw_eth_init(void); + +/** + * @brief Externally linked API for ETH configuration. + */ +void pic32mxEthInitGpio(NetInterface *interface) { + hw_eth_init(); +} + +extern uint32_t timeout; // Declared in application, and updated in 1ms_timer ISR +static inline void hw_eth_init(void) { + // EMDC - RD11 - O + // EMDIO - RD8 - I/O + // ETXEN - RD6 - O + // ETXD0 - RF1 - O + // ETXD1 - RF0 - O + // nINT(ERFCLKO) - RG9 - I + // ECRS_DV - RG8 - I + // ERXD0 - RB12 - I - AN12 + AD1PCFGbits.PCFG12 = 1; + // ERXD1 - RB13 - I - AN13 + AD1PCFGbits.PCFG13 = 1; + // ERXER - RB11 - I - AN11 + AD1PCFGbits.PCFG11 = 1; + /** Note: ERXER - RB11 is not connected to PHY on MCU CARD for PIC32. + * To circumvent the problems that might arise, and to ensure proper functioning, + * RB11 must be shorted to ground!!! + */ + + // Configure PHY_RST (RG7) + TRISGbits.TRISG7 = 0; + // Reset PHY transceiver (hard reset) + LATGbits.LATG7 = 0; + timeout = 0; + while (timeout < 50); // Must be asserted at least 25ms according to LAN8720A datasheet. + LATGbits.LATG7 = 1; + timeout = 0; + while (timeout < 1); +} + +/*! @} */ // ethernet +/*! @} */ // middleware + +#ifdef __cplusplus +} +#endif + +#endif // _HW_ETH_H_ +// ------------------------------------------------------------------------- END diff --git a/middleware/hw/hw_eth/include/pic32/implementation_2/hw_eth.h b/middleware/hw/hw_eth/include/pic32/implementation_2/hw_eth.h new file mode 100644 index 000000000..14c9a7f38 --- /dev/null +++ b/middleware/hw/hw_eth/include/pic32/implementation_2/hw_eth.h @@ -0,0 +1,113 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hw_eth.h + * @brief Initializes ETH HW module. + * @details Sets clock, pins, etc. + */ + +#ifndef _HW_ETH_H_ +#define _HW_ETH_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "mcu.h" +#include "net.h" + +/*! + * @addtogroup middleware Middleware + * @{ + */ + +/*! + * @addtogroup ethernet MikroE ETH HW implementation. + * @brief MikroE ETH HW init library. + * + * @details This library initializes HW specific + * ethernet pins/clock etc. + * @{ + */ + +/** + * @brief Initializes ETH. + * @details Sets appropriate clock settings. + * Sets appropriate pins if necessary. + * @param None + * @note Needs to be implemented by user for current MCU. + * @return None + */ +static inline void hw_eth_init(void); + +/** + * @brief Externally linked API for ETH configuration. + */ +void pic32mzEthInitGpio(NetInterface *interface) { + hw_eth_init(); +} + +static inline void hw_eth_init(void) { + // EMDC - RD11 - O - RPD11 + // EMDIO - RJ1 - I/O + // ETXEN - RD6 - O -RPD6 + // ETXD0 - RJ8 - O -AN35 + // ETXD1 - RJ9 - O -AN36 + // nINT(ERFCLKO) - RJ11 - I -AN37 + // ECRS_DV - RH13 - I + // ERXD0 - RH8 - I + // ERXD1 - RH5 - I -AN41 + // ERXER - RH4 - I -AN40 + + ANSELJbits.ANSJ8 = 0; //AN35 - digital + ANSELJbits.ANSJ9 = 0; //AN36 - digital + ANSELJbits.ANSJ11 = 0; //AN37 - digital + ANSELHbits.ANSH4 = 0; //AN40 - digital + ANSELHbits.ANSH5 = 0; //AN41 - digital +} + +/*! @} */ // ethernet +/*! @} */ // middleware + +#ifdef __cplusplus +} +#endif + +#endif // _HW_ETH_H_ +// ------------------------------------------------------------------------- END diff --git a/middleware/hw/hw_usb/include/microchip/pic16/implementation_1/usb_hw.h b/middleware/hw/hw_usb/include/microchip/pic16/implementation_1/usb_hw.h new file mode 100644 index 000000000..e83b57cc9 --- /dev/null +++ b/middleware/hw/hw_usb/include/microchip/pic16/implementation_1/usb_hw.h @@ -0,0 +1,88 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file usb_hw.h + * @brief Initializes USB HW module. + * @details Sets clock, pins, etc. + */ + +#ifndef _USB_HW_H_ +#define _USB_HW_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "mcu.h" + +/*! + * @addtogroup middleware Middleware + * @{ + */ + +/*! + * @addtogroup usb MikroE USB HW implementation. + * @brief MikroE USB HW init library. + * + * @details This library initializes HW specific + * USB pins/clock etc. + * @{ + */ + +/** + * @brief Initializes USB. + * @details Sets appropriate clock settings. + * Sets appropriate pins if necessary. + * @param None + * @note Needs to implemented by user for current MCU. + * @return None + */ +static inline void usb_hw_init(void) { + // For PIC24H and dsPIC33F there is no additional initialization needed. +} + +/*! @} */ // usb +/*! @} */ // middleware + +#ifdef __cplusplus +} +#endif + +#endif // _USB_HW_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/CMakeLists.txt b/targets/arm/mikroe/CMakeLists.txt index e0a6c7af9..155f46662 100644 --- a/targets/arm/mikroe/CMakeLists.txt +++ b/targets/arm/mikroe/CMakeLists.txt @@ -1,20 +1,20 @@ -## ./targets/arm/mikroe/CMakeLists.txt -if(${MCU_NAME} MATCHES "(^STM32(.+)$)") - set(vendor_id "stm32") -elseif(${MCU_NAME} MATCHES "(^MK(.+)$)") - set(vendor_id "nxp") -elseif(${MCU_NAME} MATCHES "(^TM4C1(.+)$)") - ## TIVA has only the 71 MCUs already implemented - set(vendor_id "tiva") -else() - set(vendor_id "__implementation_error__") -endif() - -add_subdirectory(common) -add_subdirectory(core) - -if(AI_GENERATED_SDK) - add_subdirectory(ai_generated/${vendor_id}) -else() - add_subdirectory(${vendor_id}) -endif() +## ./targets/arm/mikroe/CMakeLists.txt +if(${MCU_NAME} MATCHES "(^STM32(.+)$)") + set(vendor_id "stm32") +elseif(${MCU_NAME} MATCHES "(^MK(.+)$)") + set(vendor_id "nxp") +elseif(${MCU_NAME} MATCHES "(^TM4C1(.+)$)") + ## TIVA has only the 71 MCUs already implemented + set(vendor_id "tiva") +else() + set(vendor_id "__implementation_error__") +endif() + +add_subdirectory(common) +add_subdirectory(core) + +if(AI_GENERATED_SDK) + add_subdirectory(ai_generated/${vendor_id}) +else() + add_subdirectory(${vendor_id}) +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/CMakeLists.txt b/targets/arm/mikroe/ai_generated/stm32/CMakeLists.txt new file mode 100644 index 000000000..9e7b6c0e0 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/CMakeLists.txt @@ -0,0 +1,39 @@ +## ./targets/arm/mikroe/ai_generated/stm32/CMakeLists.txt +# ALL MODULES +add_subdirectory(src/hal_ll) + +# SEPARATE MODULES +set(module_list "") +set(module_list_supported "") +set_module_support(module_list module_list_supported ${MCU_NAME} "hal_ll_layer") + +if (msdk_adc IN_LIST module_list_supported) + add_subdirectory(src/adc) +endif() +if (msdk_gpio_in IN_LIST module_list_supported) + add_subdirectory(src/gpio) +endif() +if (msdk_i2c_master IN_LIST module_list_supported) + add_subdirectory(src/i2c) +endif() +if (msdk_pwm IN_LIST module_list_supported) + add_subdirectory(src/tim) +endif() +if (msdk_spi_master IN_LIST module_list_supported) + add_subdirectory(src/spi_master) +endif() +if (msdk_uart IN_LIST module_list_supported) + add_subdirectory(src/uart) +endif() +if (msdk_onewire IN_LIST module_list_supported) + add_subdirectory(src/one_wire) +endif() +if (msdk_can IN_LIST module_list_supported) + add_subdirectory(src/can) +endif() +if (msdk_dma IN_LIST module_list_supported) + add_subdirectory(src/dma) +endif() +if (msdk_rtc IN_LIST module_list_supported) + add_subdirectory(src/rtc) +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/include/adc/hal_ll_adc.h b/targets/arm/mikroe/ai_generated/stm32/include/adc/hal_ll_adc.h new file mode 100644 index 000000000..7f2a70d50 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/adc/hal_ll_adc.h @@ -0,0 +1,227 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_adc.h + * @brief This file contains all the functions prototypes for the ADC library. + */ + +#ifndef _HAL_LL_ADC_H_ +#define _HAL_LL_ADC_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_target.h" +#include "hal_ll_rcc.h" + +#define HAL_ADC_6BIT_RES_VAL 0x003FU +#define HAL_ADC_8BIT_RES_VAL 0x00FFU +#define HAL_ADC_10BIT_RES_VAL 0x03FFU +#define HAL_ADC_12BIT_RES_VAL 0x0FFFU +#define HAL_ADC_14BIT_RES_VAL 0x3FFFU +#define HAL_ADC_16BIT_RES_VAL 0xFFFFU + +/** + * @brief ADC low level handle. + * + * The context for storing low level object handler. + * User is not to change these values or unexpected behaviour + * may occur. + */ +typedef struct +{ + handle_t *hal_ll_adc_handle; + handle_t *hal_drv_adc_handle; + bool init_ll_state; +} hal_ll_adc_handle_register_t; + +/** + * ADC VREF. + */ +typedef enum +{ + HAL_LL_ADC_VREF_EXTERNAL = 0, + HAL_LL_ADC_VREF_DEFAULT = HAL_LL_ADC_VREF_EXTERNAL +} hal_ll_adc_voltage_reference_t; + +/** + * ADC resolution. + */ +typedef enum +{ + HAL_LL_ADC_RESOLUTION_NOT_SET = 0, + HAL_LL_ADC_RESOLUTION_6_BIT, /**< 6 bit resolution */ + HAL_LL_ADC_RESOLUTION_8_BIT, /**< 8 bit resolution */ + HAL_LL_ADC_RESOLUTION_10_BIT, /**< 10 bit resolution */ + HAL_LL_ADC_RESOLUTION_12_BIT, /**< 12 bit resolution */ + HAL_LL_ADC_RESOLUTION_14_BIT, /**< 14 bit resolution */ + HAL_LL_ADC_RESOLUTION_16_BIT, /**< 16 bit resolution */ + + /*!< Default resolution. */ + HAL_LL_ADC_RESOLUTION_DEFAULT = HAL_LL_ADC_RESOLUTION_CMAKE +} hal_ll_adc_resolution_t; + +/** + * @brief ADC low level specific structure. + * + * User is not to change these values or unexpected behaviour + * may occur. + */ +typedef struct +{ + hal_ll_base_addr_t base; + uint8_t module_index; + hal_ll_pin_name_t pin; + hal_ll_adc_voltage_reference_t vref_input; + float vref_value; + uint32_t resolution; + uint8_t channel; +} hal_ll_adc_hw_specifics_map_t; + +/** + * @brief Configures specified module. + * + * Performs module configuration on the hardware + * level. + * + * @param[in] *handle HAL context object handle. + * + * @return hal_ll_err_t Module specific error. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_module_configure_adc( handle_t *handle ); + +/** + * @brief Registers handler for future use. + * + * Registers low level and hal level handlers + * for use with appropriate functions. + * + * @param[in] *handle HAL context object handle. + * @param[in] pin Analog input pin. + * @param[in] vref_input Voltage reference source. + * @param[in] resolution Analog data resolution. + * @param[in] *handle_map HAL layer local handle map. + * @param[in] *hal_module_id HAL layer module number. + + * @return hal_ll_err_t Module specific error. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_adc_register_handle(hal_ll_pin_name_t pin, hal_ll_adc_voltage_reference_t vref_input, hal_ll_adc_resolution_t resolution, hal_ll_adc_handle_register_t *handle_map, uint8_t *hal_module_id); + +/** + * @brief Sets ADC resolution. + * + * Sets specified ADC resolution for module. + * Take into consideration that the module + * will be re-initialized on the hardware level. + * + * @param[in] *handle HAL context object handle. + * @param[in] resolution ADC resolution. + * + * @return hal_ll_err_t Module specific error or success. + */ +hal_ll_err_t hal_ll_adc_set_resolution(handle_t *handle, hal_ll_adc_resolution_t resolution); + +/** + * @brief Sets ADC reference voltage source. + * + * Sets ADC reference voltage source for specified + * object. Take into consideration that the module + * will be re-initialized on the hardware level. + * + * @param[in] *handle HAL context object handle. + * @param[in] vref_input ADC reference voltage source. + * + * @return hal_ll_err_t Module specific error or success. + */ +hal_ll_err_t hal_ll_adc_set_vref_input(handle_t *handle, hal_ll_adc_voltage_reference_t vref_input); + +/** + * @brief Sets ADC reference voltage value. + * + * Sets ADC reference voltage value for specified + * object. + * + * @param[in] *handle HAL context object handle. + * @param[in] vref_input ADC reference voltage value. + * + * @return void None. + */ +void hal_ll_adc_set_vref_value(handle_t *handle, float vref_value); + +/** + * @brief Executes data read via ADC module. + * + * Function shall read raw unsigned analog value. + * + * @param handle ADC handle. + * @param *readDatabuf Data buffer where read data + * shall be placed. + * + * @return hal_ll_err_t Module specific error. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_adc_read(handle_t *handle, uint16_t *readDatabuf ); + +/** + * @brief Closes ADC HAL and HAL_LOW_LEVEL context object. + * + * De-allocates hardware resources for specific driver object and + * de-initializes the module on a hardware level. + * + * @param[in] *handle HAL context object handle. + * + * @return void None. + */ +void hal_ll_adc_close( handle_t *handle ); + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_ADC_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/adc/hal_ll_adc_pin_map/implementations/doc_ds_1/hal_ll_adc_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/adc/hal_ll_adc_pin_map/implementations/doc_ds_1/hal_ll_adc_pin_map.h new file mode 100644 index 000000000..4adc619c9 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/adc/hal_ll_adc_pin_map/implementations/doc_ds_1/hal_ll_adc_pin_map.h @@ -0,0 +1,163 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_adc_pin_map.h + * @brief Header file containing symbolic pin name definitions. + */ + +#ifndef _HAL_LL_ADC_PIN_MAP_H_ +#define _HAL_LL_ADC_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_adc_module_num(_module_num) (_module_num - 1) + +/** + * ADC channels. + */ +typedef enum +{ + HAL_LL_ADC_CHANNEL_0 = 0, + HAL_LL_ADC_CHANNEL_1, + HAL_LL_ADC_CHANNEL_2, + HAL_LL_ADC_CHANNEL_3, + HAL_LL_ADC_CHANNEL_4, + HAL_LL_ADC_CHANNEL_5, + HAL_LL_ADC_CHANNEL_6, + HAL_LL_ADC_CHANNEL_7, + HAL_LL_ADC_CHANNEL_8, + HAL_LL_ADC_CHANNEL_9, + HAL_LL_ADC_CHANNEL_10, + HAL_LL_ADC_CHANNEL_11, + HAL_LL_ADC_CHANNEL_12, + HAL_LL_ADC_CHANNEL_13, + HAL_LL_ADC_CHANNEL_14, + HAL_LL_ADC_CHANNEL_15, + HAL_LL_ADC_CHANNEL_16, + HAL_LL_ADC_CHANNEL_17, + HAL_LL_ADC_CHANNEL_18, + HAL_LL_ADC_CHANNEL_19, + HAL_LL_ADC_CHANNEL_20, + HAL_LL_ADC_CHANNEL_21, + HAL_LL_ADC_CHANNEL_22, + HAL_LL_ADC_CHANNEL_23, + HAL_LL_ADC_CHANNEL_24, + HAL_LL_ADC_CHANNEL_25, + HAL_LL_ADC_CHANNEL_26, + HAL_LL_ADC_CHANNEL_27, + HAL_LL_ADC_CHANNEL_28, + HAL_LL_ADC_CHANNEL_29, + HAL_LL_ADC_CHANNEL_30, + HAL_LL_ADC_CHANNEL_31, + + HAL_LL_ADC_CHANNEL_NC = 0xFFFF +} hal_ll_adc_channel_t; + +/*!< @brief ADC pin structure. */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + hal_ll_adc_channel_t channel; +} hal_ll_adc_pin_map_t; + +#ifdef ADC_MODULE_1 +#define ADC1_BASE_ADDRESS (0x40012400UL) +#define ADC1_BASE_ADDR ADC1_BASE_ADDRESS +#define HAL_LL_ADC1_BASE_ADDR ADC1_BASE_ADDRESS +#define HAL_LL_ADC1_BASE_ADDRESS ADC1_BASE_ADDRESS +#endif + +/*!< ADC input pins. */ +static const hal_ll_adc_pin_map_t _adc_map[] = +{ + #ifdef ADC1_PA0_CH0 + {PA0, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_0}, + #endif + #ifdef ADC1_PA11_CH11 + {PA11, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_11}, + #endif + #ifdef ADC1_PA12_CH12 + {PA12, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_12}, + #endif + #ifdef ADC1_PA13_CH13 + {PA13, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_13}, + #endif + #ifdef ADC1_PA14_CH14 + {PA14, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_14}, + #endif + #ifdef ADC1_PA1_CH1 + {PA1, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_1}, + #endif + #ifdef ADC1_PA2_CH2 + {PA2, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_2}, + #endif + #ifdef ADC1_PA3_CH3 + {PA3, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_3}, + #endif + #ifdef ADC1_PA4_CH4 + {PA4, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_4}, + #endif + #ifdef ADC1_PA5_CH5 + {PA5, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_5}, + #endif + #ifdef ADC1_PA6_CH6 + {PA6, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_6}, + #endif + #ifdef ADC1_PA7_CH7 + {PA7, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_7}, + #endif + #ifdef ADC1_PA8_CH8 + {PA8, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_8}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_CHANNEL_ERROR} +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_ADC_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/adc/hal_ll_adc_pin_map/implementations/doc_ds_160/hal_ll_adc_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/adc/hal_ll_adc_pin_map/implementations/doc_ds_160/hal_ll_adc_pin_map.h new file mode 100644 index 000000000..6303681f8 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/adc/hal_ll_adc_pin_map/implementations/doc_ds_160/hal_ll_adc_pin_map.h @@ -0,0 +1,226 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_adc_pin_map.h + * @brief Header file containing symbolic pin name definitions. + */ + +#ifndef _HAL_LL_ADC_PIN_MAP_H_ +#define _HAL_LL_ADC_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_adc_module_num(_module_num) (_module_num - 1) + +/** + * ADC channels. + */ +typedef enum +{ + HAL_LL_ADC_CHANNEL_0 = 0, + HAL_LL_ADC_CHANNEL_1, + HAL_LL_ADC_CHANNEL_2, + HAL_LL_ADC_CHANNEL_3, + HAL_LL_ADC_CHANNEL_4, + HAL_LL_ADC_CHANNEL_5, + HAL_LL_ADC_CHANNEL_6, + HAL_LL_ADC_CHANNEL_7, + HAL_LL_ADC_CHANNEL_8, + HAL_LL_ADC_CHANNEL_9, + HAL_LL_ADC_CHANNEL_10, + HAL_LL_ADC_CHANNEL_11, + HAL_LL_ADC_CHANNEL_12, + HAL_LL_ADC_CHANNEL_13, + HAL_LL_ADC_CHANNEL_14, + HAL_LL_ADC_CHANNEL_15, + HAL_LL_ADC_CHANNEL_16, + HAL_LL_ADC_CHANNEL_17, + HAL_LL_ADC_CHANNEL_18, + HAL_LL_ADC_CHANNEL_19, + HAL_LL_ADC_CHANNEL_20, + HAL_LL_ADC_CHANNEL_21, + HAL_LL_ADC_CHANNEL_22, + HAL_LL_ADC_CHANNEL_23, + HAL_LL_ADC_CHANNEL_24, + HAL_LL_ADC_CHANNEL_25, + HAL_LL_ADC_CHANNEL_26, + HAL_LL_ADC_CHANNEL_27, + HAL_LL_ADC_CHANNEL_28, + HAL_LL_ADC_CHANNEL_29, + HAL_LL_ADC_CHANNEL_30, + HAL_LL_ADC_CHANNEL_31, + + HAL_LL_ADC_CHANNEL_NC = 0xFFFF +} hal_ll_adc_channel_t; + +/*!< @brief ADC pin structure. */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + hal_ll_adc_channel_t channel; +} hal_ll_adc_pin_map_t; + +#ifdef ADC_MODULE_1 +#define ADC1_BASE_ADDRESS (0x50040000UL) +#define ADC1_BASE_ADDR ADC1_BASE_ADDRESS +#define HAL_LL_ADC1_BASE_ADDR ADC1_BASE_ADDRESS +#define HAL_LL_ADC1_BASE_ADDRESS ADC1_BASE_ADDRESS +#endif +#ifdef ADC_MODULE_2 +#define ADC2_BASE_ADDRESS (0x50040100UL) +#define ADC2_BASE_ADDR ADC2_BASE_ADDRESS +#define HAL_LL_ADC2_BASE_ADDR ADC2_BASE_ADDRESS +#define HAL_LL_ADC2_BASE_ADDRESS ADC2_BASE_ADDRESS +#endif + +/*!< ADC input pins. */ +static const hal_ll_adc_pin_map_t _adc_map[] = +{ + #ifdef ADC1_PA0_CH5 + {PA0, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_5}, + #endif + #ifdef ADC1_PA1_CH6 + {PA1, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_6}, + #endif + #ifdef ADC1_PA2_CH7 + {PA2, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_7}, + #endif + #ifdef ADC1_PA3_CH8 + {PA3, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_8}, + #endif + #ifdef ADC1_PA4_CH9 + {PA4, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_9}, + #endif + #ifdef ADC1_PA5_CH10 + {PA5, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_10}, + #endif + #ifdef ADC1_PA6_CH11 + {PA6, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_11}, + #endif + #ifdef ADC1_PA7_CH12 + {PA7, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_12}, + #endif + #ifdef ADC1_PB0_CH15 + {PB0, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_15}, + #endif + #ifdef ADC1_PB1_CH16 + {PB1, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_16}, + #endif + #ifdef ADC1_PC0_CH1 + {PC0, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_1}, + #endif + #ifdef ADC1_PC1_CH2 + {PC1, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_2}, + #endif + #ifdef ADC1_PC2_CH3 + {PC2, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_3}, + #endif + #ifdef ADC1_PC3_CH4 + {PC3, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_4}, + #endif + #ifdef ADC1_PC4_CH13 + {PC4, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_13}, + #endif + #ifdef ADC1_PC5_CH14 + {PC5, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_14}, + #endif + #ifdef ADC2_PA0_CH5 + {PA0, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_5}, + #endif + #ifdef ADC2_PA1_CH6 + {PA1, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_6}, + #endif + #ifdef ADC2_PA2_CH7 + {PA2, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_7}, + #endif + #ifdef ADC2_PA3_CH8 + {PA3, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_8}, + #endif + #ifdef ADC2_PA4_CH9 + {PA4, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_9}, + #endif + #ifdef ADC2_PA5_CH10 + {PA5, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_10}, + #endif + #ifdef ADC2_PA6_CH11 + {PA6, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_11}, + #endif + #ifdef ADC2_PA7_CH12 + {PA7, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_12}, + #endif + #ifdef ADC2_PB0_CH15 + {PB0, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_15}, + #endif + #ifdef ADC2_PB1_CH16 + {PB1, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_16}, + #endif + #ifdef ADC2_PC0_CH1 + {PC0, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_1}, + #endif + #ifdef ADC2_PC1_CH2 + {PC1, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_2}, + #endif + #ifdef ADC2_PC2_CH3 + {PC2, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_3}, + #endif + #ifdef ADC2_PC3_CH4 + {PC3, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_4}, + #endif + #ifdef ADC2_PC4_CH13 + {PC4, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_13}, + #endif + #ifdef ADC2_PC5_CH14 + {PC5, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_14}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_CHANNEL_ERROR} +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_ADC_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/adc/hal_ll_adc_pin_map/implementations/doc_ds_161/hal_ll_adc_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/adc/hal_ll_adc_pin_map/implementations/doc_ds_161/hal_ll_adc_pin_map.h new file mode 100644 index 000000000..6303681f8 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/adc/hal_ll_adc_pin_map/implementations/doc_ds_161/hal_ll_adc_pin_map.h @@ -0,0 +1,226 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_adc_pin_map.h + * @brief Header file containing symbolic pin name definitions. + */ + +#ifndef _HAL_LL_ADC_PIN_MAP_H_ +#define _HAL_LL_ADC_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_adc_module_num(_module_num) (_module_num - 1) + +/** + * ADC channels. + */ +typedef enum +{ + HAL_LL_ADC_CHANNEL_0 = 0, + HAL_LL_ADC_CHANNEL_1, + HAL_LL_ADC_CHANNEL_2, + HAL_LL_ADC_CHANNEL_3, + HAL_LL_ADC_CHANNEL_4, + HAL_LL_ADC_CHANNEL_5, + HAL_LL_ADC_CHANNEL_6, + HAL_LL_ADC_CHANNEL_7, + HAL_LL_ADC_CHANNEL_8, + HAL_LL_ADC_CHANNEL_9, + HAL_LL_ADC_CHANNEL_10, + HAL_LL_ADC_CHANNEL_11, + HAL_LL_ADC_CHANNEL_12, + HAL_LL_ADC_CHANNEL_13, + HAL_LL_ADC_CHANNEL_14, + HAL_LL_ADC_CHANNEL_15, + HAL_LL_ADC_CHANNEL_16, + HAL_LL_ADC_CHANNEL_17, + HAL_LL_ADC_CHANNEL_18, + HAL_LL_ADC_CHANNEL_19, + HAL_LL_ADC_CHANNEL_20, + HAL_LL_ADC_CHANNEL_21, + HAL_LL_ADC_CHANNEL_22, + HAL_LL_ADC_CHANNEL_23, + HAL_LL_ADC_CHANNEL_24, + HAL_LL_ADC_CHANNEL_25, + HAL_LL_ADC_CHANNEL_26, + HAL_LL_ADC_CHANNEL_27, + HAL_LL_ADC_CHANNEL_28, + HAL_LL_ADC_CHANNEL_29, + HAL_LL_ADC_CHANNEL_30, + HAL_LL_ADC_CHANNEL_31, + + HAL_LL_ADC_CHANNEL_NC = 0xFFFF +} hal_ll_adc_channel_t; + +/*!< @brief ADC pin structure. */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + hal_ll_adc_channel_t channel; +} hal_ll_adc_pin_map_t; + +#ifdef ADC_MODULE_1 +#define ADC1_BASE_ADDRESS (0x50040000UL) +#define ADC1_BASE_ADDR ADC1_BASE_ADDRESS +#define HAL_LL_ADC1_BASE_ADDR ADC1_BASE_ADDRESS +#define HAL_LL_ADC1_BASE_ADDRESS ADC1_BASE_ADDRESS +#endif +#ifdef ADC_MODULE_2 +#define ADC2_BASE_ADDRESS (0x50040100UL) +#define ADC2_BASE_ADDR ADC2_BASE_ADDRESS +#define HAL_LL_ADC2_BASE_ADDR ADC2_BASE_ADDRESS +#define HAL_LL_ADC2_BASE_ADDRESS ADC2_BASE_ADDRESS +#endif + +/*!< ADC input pins. */ +static const hal_ll_adc_pin_map_t _adc_map[] = +{ + #ifdef ADC1_PA0_CH5 + {PA0, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_5}, + #endif + #ifdef ADC1_PA1_CH6 + {PA1, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_6}, + #endif + #ifdef ADC1_PA2_CH7 + {PA2, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_7}, + #endif + #ifdef ADC1_PA3_CH8 + {PA3, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_8}, + #endif + #ifdef ADC1_PA4_CH9 + {PA4, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_9}, + #endif + #ifdef ADC1_PA5_CH10 + {PA5, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_10}, + #endif + #ifdef ADC1_PA6_CH11 + {PA6, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_11}, + #endif + #ifdef ADC1_PA7_CH12 + {PA7, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_12}, + #endif + #ifdef ADC1_PB0_CH15 + {PB0, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_15}, + #endif + #ifdef ADC1_PB1_CH16 + {PB1, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_16}, + #endif + #ifdef ADC1_PC0_CH1 + {PC0, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_1}, + #endif + #ifdef ADC1_PC1_CH2 + {PC1, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_2}, + #endif + #ifdef ADC1_PC2_CH3 + {PC2, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_3}, + #endif + #ifdef ADC1_PC3_CH4 + {PC3, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_4}, + #endif + #ifdef ADC1_PC4_CH13 + {PC4, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_13}, + #endif + #ifdef ADC1_PC5_CH14 + {PC5, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_14}, + #endif + #ifdef ADC2_PA0_CH5 + {PA0, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_5}, + #endif + #ifdef ADC2_PA1_CH6 + {PA1, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_6}, + #endif + #ifdef ADC2_PA2_CH7 + {PA2, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_7}, + #endif + #ifdef ADC2_PA3_CH8 + {PA3, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_8}, + #endif + #ifdef ADC2_PA4_CH9 + {PA4, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_9}, + #endif + #ifdef ADC2_PA5_CH10 + {PA5, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_10}, + #endif + #ifdef ADC2_PA6_CH11 + {PA6, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_11}, + #endif + #ifdef ADC2_PA7_CH12 + {PA7, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_12}, + #endif + #ifdef ADC2_PB0_CH15 + {PB0, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_15}, + #endif + #ifdef ADC2_PB1_CH16 + {PB1, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_16}, + #endif + #ifdef ADC2_PC0_CH1 + {PC0, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_1}, + #endif + #ifdef ADC2_PC1_CH2 + {PC1, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_2}, + #endif + #ifdef ADC2_PC2_CH3 + {PC2, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_3}, + #endif + #ifdef ADC2_PC3_CH4 + {PC3, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_4}, + #endif + #ifdef ADC2_PC4_CH13 + {PC4, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_13}, + #endif + #ifdef ADC2_PC5_CH14 + {PC5, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_14}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_CHANNEL_ERROR} +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_ADC_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/adc/hal_ll_adc_pin_map/implementations/doc_ds_2/hal_ll_adc_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/adc/hal_ll_adc_pin_map/implementations/doc_ds_2/hal_ll_adc_pin_map.h new file mode 100644 index 000000000..a95c4c1b8 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/adc/hal_ll_adc_pin_map/implementations/doc_ds_2/hal_ll_adc_pin_map.h @@ -0,0 +1,181 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_adc_pin_map.h + * @brief Header file containing symbolic pin name definitions. + */ + +#ifndef _HAL_LL_ADC_PIN_MAP_H_ +#define _HAL_LL_ADC_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_adc_module_num(_module_num) (_module_num - 1) + +/** + * ADC channels. + */ +typedef enum +{ + HAL_LL_ADC_CHANNEL_0 = 0, + HAL_LL_ADC_CHANNEL_1, + HAL_LL_ADC_CHANNEL_2, + HAL_LL_ADC_CHANNEL_3, + HAL_LL_ADC_CHANNEL_4, + HAL_LL_ADC_CHANNEL_5, + HAL_LL_ADC_CHANNEL_6, + HAL_LL_ADC_CHANNEL_7, + HAL_LL_ADC_CHANNEL_8, + HAL_LL_ADC_CHANNEL_9, + HAL_LL_ADC_CHANNEL_10, + HAL_LL_ADC_CHANNEL_11, + HAL_LL_ADC_CHANNEL_12, + HAL_LL_ADC_CHANNEL_13, + HAL_LL_ADC_CHANNEL_14, + HAL_LL_ADC_CHANNEL_15, + HAL_LL_ADC_CHANNEL_16, + HAL_LL_ADC_CHANNEL_17, + HAL_LL_ADC_CHANNEL_18, + HAL_LL_ADC_CHANNEL_19, + HAL_LL_ADC_CHANNEL_20, + HAL_LL_ADC_CHANNEL_21, + HAL_LL_ADC_CHANNEL_22, + HAL_LL_ADC_CHANNEL_23, + HAL_LL_ADC_CHANNEL_24, + HAL_LL_ADC_CHANNEL_25, + HAL_LL_ADC_CHANNEL_26, + HAL_LL_ADC_CHANNEL_27, + HAL_LL_ADC_CHANNEL_28, + HAL_LL_ADC_CHANNEL_29, + HAL_LL_ADC_CHANNEL_30, + HAL_LL_ADC_CHANNEL_31, + + HAL_LL_ADC_CHANNEL_NC = 0xFFFF +} hal_ll_adc_channel_t; + +/*!< @brief ADC pin structure. */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + hal_ll_adc_channel_t channel; +} hal_ll_adc_pin_map_t; + +#ifdef ADC_MODULE_1 +#define ADC1_BASE_ADDRESS (0x40012400UL) +#define ADC1_BASE_ADDR ADC1_BASE_ADDRESS +#define HAL_LL_ADC1_BASE_ADDR ADC1_BASE_ADDRESS +#define HAL_LL_ADC1_BASE_ADDRESS ADC1_BASE_ADDRESS +#endif + +/*!< ADC input pins. */ +static const hal_ll_adc_pin_map_t _adc_map[] = +{ + #ifdef ADC1_PA0_CH0 + {PA0, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_0}, + #endif + #ifdef ADC1_PA11_CH11 + {PA11, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_11}, + #endif + #ifdef ADC1_PA12_CH12 + {PA12, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_12}, + #endif + #ifdef ADC1_PA13_CH13 + {PA13, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_13}, + #endif + #ifdef ADC1_PA14_CH14 + {PA14, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_14}, + #endif + #ifdef ADC1_PA1_CH1 + {PA1, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_1}, + #endif + #ifdef ADC1_PA2_CH2 + {PA2, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_2}, + #endif + #ifdef ADC1_PA3_CH3 + {PA3, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_3}, + #endif + #ifdef ADC1_PA4_CH4 + {PA4, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_4}, + #endif + #ifdef ADC1_PA5_CH5 + {PA5, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_5}, + #endif + #ifdef ADC1_PA6_CH6 + {PA6, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_6}, + #endif + #ifdef ADC1_PA7_CH7 + {PA7, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_7}, + #endif + #ifdef ADC1_PA8_CH8 + {PA8, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_8}, + #endif + #ifdef ADC1_PB0_CH17 + {PB0, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_17}, + #endif + #ifdef ADC1_PB1_CH18 + {PB1, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_18}, + #endif + #ifdef ADC1_PB10_CH20 + {PB10, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_20}, + #endif + #ifdef ADC1_PB11_CH21 + {PB11, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_21}, + #endif + #ifdef ADC1_PB12_CH22 + {PB12, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_22}, + #endif + #ifdef ADC1_PB2_CH19 + {PB2, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_19}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_CHANNEL_ERROR} +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_ADC_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/adc/hal_ll_adc_pin_map/implementations/doc_ds_74/hal_ll_adc_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/adc/hal_ll_adc_pin_map/implementations/doc_ds_74/hal_ll_adc_pin_map.h new file mode 100644 index 000000000..e114736ba --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/adc/hal_ll_adc_pin_map/implementations/doc_ds_74/hal_ll_adc_pin_map.h @@ -0,0 +1,181 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_adc_pin_map.h + * @brief Header file containing symbolic pin name definitions. + */ + +#ifndef _HAL_LL_ADC_PIN_MAP_H_ +#define _HAL_LL_ADC_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_adc_module_num(_module_num) (_module_num - 1) + +/** + * ADC channels. + */ +typedef enum +{ + HAL_LL_ADC_CHANNEL_0 = 0, + HAL_LL_ADC_CHANNEL_1, + HAL_LL_ADC_CHANNEL_2, + HAL_LL_ADC_CHANNEL_3, + HAL_LL_ADC_CHANNEL_4, + HAL_LL_ADC_CHANNEL_5, + HAL_LL_ADC_CHANNEL_6, + HAL_LL_ADC_CHANNEL_7, + HAL_LL_ADC_CHANNEL_8, + HAL_LL_ADC_CHANNEL_9, + HAL_LL_ADC_CHANNEL_10, + HAL_LL_ADC_CHANNEL_11, + HAL_LL_ADC_CHANNEL_12, + HAL_LL_ADC_CHANNEL_13, + HAL_LL_ADC_CHANNEL_14, + HAL_LL_ADC_CHANNEL_15, + HAL_LL_ADC_CHANNEL_16, + HAL_LL_ADC_CHANNEL_17, + HAL_LL_ADC_CHANNEL_18, + HAL_LL_ADC_CHANNEL_19, + HAL_LL_ADC_CHANNEL_20, + HAL_LL_ADC_CHANNEL_21, + HAL_LL_ADC_CHANNEL_22, + HAL_LL_ADC_CHANNEL_23, + HAL_LL_ADC_CHANNEL_24, + HAL_LL_ADC_CHANNEL_25, + HAL_LL_ADC_CHANNEL_26, + HAL_LL_ADC_CHANNEL_27, + HAL_LL_ADC_CHANNEL_28, + HAL_LL_ADC_CHANNEL_29, + HAL_LL_ADC_CHANNEL_30, + HAL_LL_ADC_CHANNEL_31, + + HAL_LL_ADC_CHANNEL_NC = 0xFFFF +} hal_ll_adc_channel_t; + +/*!< @brief ADC pin structure. */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + hal_ll_adc_channel_t channel; +} hal_ll_adc_pin_map_t; + +#ifdef ADC_MODULE_1 +#define ADC1_BASE_ADDRESS (0x40012400UL) +#define ADC1_BASE_ADDR ADC1_BASE_ADDRESS +#define HAL_LL_ADC1_BASE_ADDR ADC1_BASE_ADDRESS +#define HAL_LL_ADC1_BASE_ADDRESS ADC1_BASE_ADDRESS +#endif + +/*!< ADC input pins. */ +static const hal_ll_adc_pin_map_t _adc_map[] = +{ + #ifdef ADC1_PA0_CH0 + {PA0, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_0}, + #endif + #ifdef ADC1_PA11_CH15 + {PA11, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_15}, + #endif + #ifdef ADC1_PA12_CH16 + {PA12, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_16}, + #endif + #ifdef ADC1_PA13_CH17 + {PA13, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_17}, + #endif + #ifdef ADC1_PA14_CH18 + {PA14, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_18}, + #endif + #ifdef ADC1_PA1_CH1 + {PA1, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_1}, + #endif + #ifdef ADC1_PA2_CH2 + {PA2, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_2}, + #endif + #ifdef ADC1_PA3_CH3 + {PA3, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_3}, + #endif + #ifdef ADC1_PA4_CH4 + {PA4, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_4}, + #endif + #ifdef ADC1_PA5_CH5 + {PA5, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_5}, + #endif + #ifdef ADC1_PA6_CH6 + {PA6, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_6}, + #endif + #ifdef ADC1_PA7_CH7 + {PA7, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_7}, + #endif + #ifdef ADC1_PB0_CH8 + {PB0, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_8}, + #endif + #ifdef ADC1_PB1_CH9 + {PB1, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_9}, + #endif + #ifdef ADC1_PB2_CH10 + {PB2, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_10}, + #endif + #ifdef ADC1_PB7_CH11 + {PB7, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_11}, + #endif + #ifdef ADC1_PB10_CH11 + {PB10, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_11}, + #endif + #ifdef ADC1_PB11_CH15 + {PB11, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_15}, + #endif + #ifdef ADC1_PB12_CH16 + {PB12, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_16}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_CHANNEL_ERROR} +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_ADC_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/adc/hal_ll_adc_pin_map/implementations/doc_ds_75/hal_ll_adc_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/adc/hal_ll_adc_pin_map/implementations/doc_ds_75/hal_ll_adc_pin_map.h new file mode 100644 index 000000000..e114736ba --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/adc/hal_ll_adc_pin_map/implementations/doc_ds_75/hal_ll_adc_pin_map.h @@ -0,0 +1,181 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_adc_pin_map.h + * @brief Header file containing symbolic pin name definitions. + */ + +#ifndef _HAL_LL_ADC_PIN_MAP_H_ +#define _HAL_LL_ADC_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_adc_module_num(_module_num) (_module_num - 1) + +/** + * ADC channels. + */ +typedef enum +{ + HAL_LL_ADC_CHANNEL_0 = 0, + HAL_LL_ADC_CHANNEL_1, + HAL_LL_ADC_CHANNEL_2, + HAL_LL_ADC_CHANNEL_3, + HAL_LL_ADC_CHANNEL_4, + HAL_LL_ADC_CHANNEL_5, + HAL_LL_ADC_CHANNEL_6, + HAL_LL_ADC_CHANNEL_7, + HAL_LL_ADC_CHANNEL_8, + HAL_LL_ADC_CHANNEL_9, + HAL_LL_ADC_CHANNEL_10, + HAL_LL_ADC_CHANNEL_11, + HAL_LL_ADC_CHANNEL_12, + HAL_LL_ADC_CHANNEL_13, + HAL_LL_ADC_CHANNEL_14, + HAL_LL_ADC_CHANNEL_15, + HAL_LL_ADC_CHANNEL_16, + HAL_LL_ADC_CHANNEL_17, + HAL_LL_ADC_CHANNEL_18, + HAL_LL_ADC_CHANNEL_19, + HAL_LL_ADC_CHANNEL_20, + HAL_LL_ADC_CHANNEL_21, + HAL_LL_ADC_CHANNEL_22, + HAL_LL_ADC_CHANNEL_23, + HAL_LL_ADC_CHANNEL_24, + HAL_LL_ADC_CHANNEL_25, + HAL_LL_ADC_CHANNEL_26, + HAL_LL_ADC_CHANNEL_27, + HAL_LL_ADC_CHANNEL_28, + HAL_LL_ADC_CHANNEL_29, + HAL_LL_ADC_CHANNEL_30, + HAL_LL_ADC_CHANNEL_31, + + HAL_LL_ADC_CHANNEL_NC = 0xFFFF +} hal_ll_adc_channel_t; + +/*!< @brief ADC pin structure. */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + hal_ll_adc_channel_t channel; +} hal_ll_adc_pin_map_t; + +#ifdef ADC_MODULE_1 +#define ADC1_BASE_ADDRESS (0x40012400UL) +#define ADC1_BASE_ADDR ADC1_BASE_ADDRESS +#define HAL_LL_ADC1_BASE_ADDR ADC1_BASE_ADDRESS +#define HAL_LL_ADC1_BASE_ADDRESS ADC1_BASE_ADDRESS +#endif + +/*!< ADC input pins. */ +static const hal_ll_adc_pin_map_t _adc_map[] = +{ + #ifdef ADC1_PA0_CH0 + {PA0, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_0}, + #endif + #ifdef ADC1_PA11_CH15 + {PA11, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_15}, + #endif + #ifdef ADC1_PA12_CH16 + {PA12, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_16}, + #endif + #ifdef ADC1_PA13_CH17 + {PA13, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_17}, + #endif + #ifdef ADC1_PA14_CH18 + {PA14, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_18}, + #endif + #ifdef ADC1_PA1_CH1 + {PA1, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_1}, + #endif + #ifdef ADC1_PA2_CH2 + {PA2, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_2}, + #endif + #ifdef ADC1_PA3_CH3 + {PA3, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_3}, + #endif + #ifdef ADC1_PA4_CH4 + {PA4, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_4}, + #endif + #ifdef ADC1_PA5_CH5 + {PA5, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_5}, + #endif + #ifdef ADC1_PA6_CH6 + {PA6, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_6}, + #endif + #ifdef ADC1_PA7_CH7 + {PA7, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_7}, + #endif + #ifdef ADC1_PB0_CH8 + {PB0, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_8}, + #endif + #ifdef ADC1_PB1_CH9 + {PB1, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_9}, + #endif + #ifdef ADC1_PB2_CH10 + {PB2, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_10}, + #endif + #ifdef ADC1_PB7_CH11 + {PB7, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_11}, + #endif + #ifdef ADC1_PB10_CH11 + {PB10, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_11}, + #endif + #ifdef ADC1_PB11_CH15 + {PB11, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_15}, + #endif + #ifdef ADC1_PB12_CH16 + {PB12, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_16}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_CHANNEL_ERROR} +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_ADC_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/adc/hal_ll_adc_pin_map/implementations/doc_ds_80/hal_ll_adc_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/adc/hal_ll_adc_pin_map/implementations/doc_ds_80/hal_ll_adc_pin_map.h new file mode 100644 index 000000000..d81796da5 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/adc/hal_ll_adc_pin_map/implementations/doc_ds_80/hal_ll_adc_pin_map.h @@ -0,0 +1,172 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_adc_pin_map.h + * @brief Header file containing symbolic pin name definitions. + */ + +#ifndef _HAL_LL_ADC_PIN_MAP_H_ +#define _HAL_LL_ADC_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_adc_module_num(_module_num) (_module_num - 1) + +/** + * ADC channels. + */ +typedef enum +{ + HAL_LL_ADC_CHANNEL_0 = 0, + HAL_LL_ADC_CHANNEL_1, + HAL_LL_ADC_CHANNEL_2, + HAL_LL_ADC_CHANNEL_3, + HAL_LL_ADC_CHANNEL_4, + HAL_LL_ADC_CHANNEL_5, + HAL_LL_ADC_CHANNEL_6, + HAL_LL_ADC_CHANNEL_7, + HAL_LL_ADC_CHANNEL_8, + HAL_LL_ADC_CHANNEL_9, + HAL_LL_ADC_CHANNEL_10, + HAL_LL_ADC_CHANNEL_11, + HAL_LL_ADC_CHANNEL_12, + HAL_LL_ADC_CHANNEL_13, + HAL_LL_ADC_CHANNEL_14, + HAL_LL_ADC_CHANNEL_15, + HAL_LL_ADC_CHANNEL_16, + HAL_LL_ADC_CHANNEL_17, + HAL_LL_ADC_CHANNEL_18, + HAL_LL_ADC_CHANNEL_19, + HAL_LL_ADC_CHANNEL_20, + HAL_LL_ADC_CHANNEL_21, + HAL_LL_ADC_CHANNEL_22, + HAL_LL_ADC_CHANNEL_23, + HAL_LL_ADC_CHANNEL_24, + HAL_LL_ADC_CHANNEL_25, + HAL_LL_ADC_CHANNEL_26, + HAL_LL_ADC_CHANNEL_27, + HAL_LL_ADC_CHANNEL_28, + HAL_LL_ADC_CHANNEL_29, + HAL_LL_ADC_CHANNEL_30, + HAL_LL_ADC_CHANNEL_31, + + HAL_LL_ADC_CHANNEL_NC = 0xFFFF +} hal_ll_adc_channel_t; + +/*!< @brief ADC pin structure. */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + hal_ll_adc_channel_t channel; +} hal_ll_adc_pin_map_t; + +#ifdef ADC_MODULE_1 +#define ADC1_BASE_ADDRESS (0x40012400UL) +#define ADC1_BASE_ADDR ADC1_BASE_ADDRESS +#define HAL_LL_ADC1_BASE_ADDR ADC1_BASE_ADDRESS +#define HAL_LL_ADC1_BASE_ADDRESS ADC1_BASE_ADDRESS +#endif + +/*!< ADC input pins. */ +static const hal_ll_adc_pin_map_t _adc_map[] = +{ + #ifdef ADC1_PA0_CH0 + {PA0, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_0}, + #endif + #ifdef ADC1_PA1_CH1 + {PA1, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_1}, + #endif + #ifdef ADC1_PA2_CH2 + {PA2, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_2}, + #endif + #ifdef ADC1_PA3_CH3 + {PA3, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_3}, + #endif + #ifdef ADC1_PA4_CH4 + {PA4, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_4}, + #endif + #ifdef ADC1_PA5_CH5 + {PA5, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_5}, + #endif + #ifdef ADC1_PA6_CH6 + {PA6, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_6}, + #endif + #ifdef ADC1_PA7_CH7 + {PA7, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_7}, + #endif + #ifdef ADC1_PB0_CH8 + {PB0, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_8}, + #endif + #ifdef ADC1_PB10_CH11 + {PB10, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_11}, + #endif + #ifdef ADC1_PB11_CH15 + {PB11, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_15}, + #endif + #ifdef ADC1_PB12_CH16 + {PB12, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_16}, + #endif + #ifdef ADC1_PB1_CH9 + {PB1, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_9}, + #endif + #ifdef ADC1_PB2_CH10 + {PB2, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_10}, + #endif + #ifdef ADC1_PC4_CH17 + {PC4, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_17}, + #endif + #ifdef ADC1_PC5_CH18 + {PC5, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_18}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_CHANNEL_ERROR} +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_ADC_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/adc/hal_ll_adc_pin_map/implementations/doc_ds_81/hal_ll_adc_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/adc/hal_ll_adc_pin_map/implementations/doc_ds_81/hal_ll_adc_pin_map.h new file mode 100644 index 000000000..d81796da5 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/adc/hal_ll_adc_pin_map/implementations/doc_ds_81/hal_ll_adc_pin_map.h @@ -0,0 +1,172 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_adc_pin_map.h + * @brief Header file containing symbolic pin name definitions. + */ + +#ifndef _HAL_LL_ADC_PIN_MAP_H_ +#define _HAL_LL_ADC_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_adc_module_num(_module_num) (_module_num - 1) + +/** + * ADC channels. + */ +typedef enum +{ + HAL_LL_ADC_CHANNEL_0 = 0, + HAL_LL_ADC_CHANNEL_1, + HAL_LL_ADC_CHANNEL_2, + HAL_LL_ADC_CHANNEL_3, + HAL_LL_ADC_CHANNEL_4, + HAL_LL_ADC_CHANNEL_5, + HAL_LL_ADC_CHANNEL_6, + HAL_LL_ADC_CHANNEL_7, + HAL_LL_ADC_CHANNEL_8, + HAL_LL_ADC_CHANNEL_9, + HAL_LL_ADC_CHANNEL_10, + HAL_LL_ADC_CHANNEL_11, + HAL_LL_ADC_CHANNEL_12, + HAL_LL_ADC_CHANNEL_13, + HAL_LL_ADC_CHANNEL_14, + HAL_LL_ADC_CHANNEL_15, + HAL_LL_ADC_CHANNEL_16, + HAL_LL_ADC_CHANNEL_17, + HAL_LL_ADC_CHANNEL_18, + HAL_LL_ADC_CHANNEL_19, + HAL_LL_ADC_CHANNEL_20, + HAL_LL_ADC_CHANNEL_21, + HAL_LL_ADC_CHANNEL_22, + HAL_LL_ADC_CHANNEL_23, + HAL_LL_ADC_CHANNEL_24, + HAL_LL_ADC_CHANNEL_25, + HAL_LL_ADC_CHANNEL_26, + HAL_LL_ADC_CHANNEL_27, + HAL_LL_ADC_CHANNEL_28, + HAL_LL_ADC_CHANNEL_29, + HAL_LL_ADC_CHANNEL_30, + HAL_LL_ADC_CHANNEL_31, + + HAL_LL_ADC_CHANNEL_NC = 0xFFFF +} hal_ll_adc_channel_t; + +/*!< @brief ADC pin structure. */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + hal_ll_adc_channel_t channel; +} hal_ll_adc_pin_map_t; + +#ifdef ADC_MODULE_1 +#define ADC1_BASE_ADDRESS (0x40012400UL) +#define ADC1_BASE_ADDR ADC1_BASE_ADDRESS +#define HAL_LL_ADC1_BASE_ADDR ADC1_BASE_ADDRESS +#define HAL_LL_ADC1_BASE_ADDRESS ADC1_BASE_ADDRESS +#endif + +/*!< ADC input pins. */ +static const hal_ll_adc_pin_map_t _adc_map[] = +{ + #ifdef ADC1_PA0_CH0 + {PA0, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_0}, + #endif + #ifdef ADC1_PA1_CH1 + {PA1, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_1}, + #endif + #ifdef ADC1_PA2_CH2 + {PA2, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_2}, + #endif + #ifdef ADC1_PA3_CH3 + {PA3, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_3}, + #endif + #ifdef ADC1_PA4_CH4 + {PA4, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_4}, + #endif + #ifdef ADC1_PA5_CH5 + {PA5, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_5}, + #endif + #ifdef ADC1_PA6_CH6 + {PA6, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_6}, + #endif + #ifdef ADC1_PA7_CH7 + {PA7, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_7}, + #endif + #ifdef ADC1_PB0_CH8 + {PB0, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_8}, + #endif + #ifdef ADC1_PB10_CH11 + {PB10, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_11}, + #endif + #ifdef ADC1_PB11_CH15 + {PB11, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_15}, + #endif + #ifdef ADC1_PB12_CH16 + {PB12, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_16}, + #endif + #ifdef ADC1_PB1_CH9 + {PB1, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_9}, + #endif + #ifdef ADC1_PB2_CH10 + {PB2, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_10}, + #endif + #ifdef ADC1_PC4_CH17 + {PC4, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_17}, + #endif + #ifdef ADC1_PC5_CH18 + {PC5, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_18}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_CHANNEL_ERROR} +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_ADC_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/adc/hal_ll_adc_pin_map/implementations/doc_ds_82/hal_ll_adc_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/adc/hal_ll_adc_pin_map/implementations/doc_ds_82/hal_ll_adc_pin_map.h new file mode 100644 index 000000000..72f672290 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/adc/hal_ll_adc_pin_map/implementations/doc_ds_82/hal_ll_adc_pin_map.h @@ -0,0 +1,220 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_adc_pin_map.h + * @brief Header file containing symbolic pin name definitions. + */ + +#ifndef _HAL_LL_ADC_PIN_MAP_H_ +#define _HAL_LL_ADC_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_adc_module_num(_module_num) (_module_num - 1) + +/** + * ADC channels. + */ +typedef enum +{ + HAL_LL_ADC_CHANNEL_0 = 0, + HAL_LL_ADC_CHANNEL_1, + HAL_LL_ADC_CHANNEL_2, + HAL_LL_ADC_CHANNEL_3, + HAL_LL_ADC_CHANNEL_4, + HAL_LL_ADC_CHANNEL_5, + HAL_LL_ADC_CHANNEL_6, + HAL_LL_ADC_CHANNEL_7, + HAL_LL_ADC_CHANNEL_8, + HAL_LL_ADC_CHANNEL_9, + HAL_LL_ADC_CHANNEL_10, + HAL_LL_ADC_CHANNEL_11, + HAL_LL_ADC_CHANNEL_12, + HAL_LL_ADC_CHANNEL_13, + HAL_LL_ADC_CHANNEL_14, + HAL_LL_ADC_CHANNEL_15, + HAL_LL_ADC_CHANNEL_16, + HAL_LL_ADC_CHANNEL_17, + HAL_LL_ADC_CHANNEL_18, + HAL_LL_ADC_CHANNEL_19, + HAL_LL_ADC_CHANNEL_20, + HAL_LL_ADC_CHANNEL_21, + HAL_LL_ADC_CHANNEL_22, + HAL_LL_ADC_CHANNEL_23, + HAL_LL_ADC_CHANNEL_24, + HAL_LL_ADC_CHANNEL_25, + HAL_LL_ADC_CHANNEL_26, + HAL_LL_ADC_CHANNEL_27, + HAL_LL_ADC_CHANNEL_28, + HAL_LL_ADC_CHANNEL_29, + HAL_LL_ADC_CHANNEL_30, + HAL_LL_ADC_CHANNEL_31, + + HAL_LL_ADC_CHANNEL_NC = 0xFFFF +} hal_ll_adc_channel_t; + +/*!< @brief ADC pin structure. */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + hal_ll_adc_channel_t channel; +} hal_ll_adc_pin_map_t; + +#ifdef ADC_MODULE_1 +#define ADC1_BASE_ADDRESS (0x50000000UL) +#define ADC1_BASE_ADDR ADC1_BASE_ADDRESS +#define HAL_LL_ADC1_BASE_ADDR ADC1_BASE_ADDRESS +#define HAL_LL_ADC1_BASE_ADDRESS ADC1_BASE_ADDRESS +#endif +#ifdef ADC_MODULE_2 +#define ADC2_BASE_ADDRESS (0x50000100UL) +#define ADC2_BASE_ADDR ADC2_BASE_ADDRESS +#define HAL_LL_ADC2_BASE_ADDR ADC2_BASE_ADDRESS +#define HAL_LL_ADC2_BASE_ADDRESS ADC2_BASE_ADDRESS +#endif + +/*!< ADC input pins. */ +static const hal_ll_adc_pin_map_t _adc_map[] = +{ + #ifdef ADC1_PA0_CH1 + {PA0, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_1}, + #endif + #ifdef ADC1_PA1_CH2 + {PA1, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_2}, + #endif + #ifdef ADC1_PA2_CH3 + {PA2, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_3}, + #endif + #ifdef ADC1_PA3_CH4 + {PA3, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_4}, + #endif + #ifdef ADC1_PB0_CH15 + {PB0, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_15}, + #endif + #ifdef ADC1_PF0_CH10 + {PF0, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_10}, + #endif + #ifdef ADC2_PA0_CH1 + {PA0, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_1}, + #endif + #ifdef ADC2_PA1_CH2 + {PA1, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_2}, + #endif + #ifdef ADC2_PA4_CH17 + {PA4, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_17}, + #endif + #ifdef ADC2_PA5_CH13 + {PA5, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_13}, + #endif + #ifdef ADC2_PA6_CH3 + {PA6, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_3}, + #endif + #ifdef ADC2_PA7_CH4 + {PA7, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_4}, + #endif + #ifdef ADC2_PF1_CH10 + {PF1, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_10}, + #endif + #ifdef ADC1_PB11_CH14 + {PB11, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_14}, + #endif + #ifdef ADC1_PB12_CH11 + {PB12, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_11}, + #endif + #ifdef ADC1_PB14_CH5 + {PB14, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_5}, + #endif + #ifdef ADC1_PB1_CH12 + {PB1, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_12}, + #endif + #ifdef ADC1_PC0_CH6 + {PC0, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_6}, + #endif + #ifdef ADC1_PC1_CH7 + {PC1, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_7}, + #endif + #ifdef ADC1_PC2_CH8 + {PC2, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_8}, + #endif + #ifdef ADC1_PC3_CH9 + {PC3, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_9}, + #endif + #ifdef ADC2_PB11_CH14 + {PB11, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_14}, + #endif + #ifdef ADC2_PB15_CH15 + {PB15, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_15}, + #endif + #ifdef ADC2_PB2_CH12 + {PB2, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_12}, + #endif + #ifdef ADC2_PC0_CH6 + {PC0, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_6}, + #endif + #ifdef ADC2_PC1_CH7 + {PC1, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_7}, + #endif + #ifdef ADC2_PC2_CH8 + {PC2, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_8}, + #endif + #ifdef ADC2_PC3_CH9 + {PC3, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_9}, + #endif + #ifdef ADC2_PC4_CH5 + {PC4, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_5}, + #endif + #ifdef ADC2_PC5_CH11 + {PC5, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_11}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_CHANNEL_ERROR} +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_ADC_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/adc/hal_ll_adc_pin_map/implementations/doc_ds_83/hal_ll_adc_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/adc/hal_ll_adc_pin_map/implementations/doc_ds_83/hal_ll_adc_pin_map.h new file mode 100644 index 000000000..421fbfffd --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/adc/hal_ll_adc_pin_map/implementations/doc_ds_83/hal_ll_adc_pin_map.h @@ -0,0 +1,220 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_adc_pin_map.h + * @brief Header file containing symbolic pin name definitions. + */ + +#ifndef _HAL_LL_ADC_PIN_MAP_H_ +#define _HAL_LL_ADC_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_adc_module_num(_module_num) (_module_num - 1) + +/** + * ADC channels. + */ +typedef enum +{ + HAL_LL_ADC_CHANNEL_0 = 0, + HAL_LL_ADC_CHANNEL_1, + HAL_LL_ADC_CHANNEL_2, + HAL_LL_ADC_CHANNEL_3, + HAL_LL_ADC_CHANNEL_4, + HAL_LL_ADC_CHANNEL_5, + HAL_LL_ADC_CHANNEL_6, + HAL_LL_ADC_CHANNEL_7, + HAL_LL_ADC_CHANNEL_8, + HAL_LL_ADC_CHANNEL_9, + HAL_LL_ADC_CHANNEL_10, + HAL_LL_ADC_CHANNEL_11, + HAL_LL_ADC_CHANNEL_12, + HAL_LL_ADC_CHANNEL_13, + HAL_LL_ADC_CHANNEL_14, + HAL_LL_ADC_CHANNEL_15, + HAL_LL_ADC_CHANNEL_16, + HAL_LL_ADC_CHANNEL_17, + HAL_LL_ADC_CHANNEL_18, + HAL_LL_ADC_CHANNEL_19, + HAL_LL_ADC_CHANNEL_20, + HAL_LL_ADC_CHANNEL_21, + HAL_LL_ADC_CHANNEL_22, + HAL_LL_ADC_CHANNEL_23, + HAL_LL_ADC_CHANNEL_24, + HAL_LL_ADC_CHANNEL_25, + HAL_LL_ADC_CHANNEL_26, + HAL_LL_ADC_CHANNEL_27, + HAL_LL_ADC_CHANNEL_28, + HAL_LL_ADC_CHANNEL_29, + HAL_LL_ADC_CHANNEL_30, + HAL_LL_ADC_CHANNEL_31, + + HAL_LL_ADC_CHANNEL_NC = 0xFFFF +} hal_ll_adc_channel_t; + +/*!< @brief ADC pin structure. */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + hal_ll_adc_channel_t channel; +} hal_ll_adc_pin_map_t; + +#ifdef ADC_MODULE_1 +#define ADC1_BASE_ADDRESS (0x50000000UL) +#define ADC1_BASE_ADDR ADC1_BASE_ADDRESS +#define HAL_LL_ADC1_BASE_ADDR ADC1_BASE_ADDRESS +#define HAL_LL_ADC1_BASE_ADDRESS ADC1_BASE_ADDRESS +#endif +#ifdef ADC_MODULE_2 +#define ADC2_BASE_ADDRESS (0x50000100UL) +#define ADC2_BASE_ADDR ADC2_BASE_ADDRESS +#define HAL_LL_ADC2_BASE_ADDR ADC2_BASE_ADDRESS +#define HAL_LL_ADC2_BASE_ADDRESS ADC2_BASE_ADDRESS +#endif + +/*!< ADC input pins. */ +static const hal_ll_adc_pin_map_t _adc_map[] = +{ + #ifdef ADC1_PA0_CH1 + {PA0, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_1}, + #endif + #ifdef ADC1_PA1_CH2 + {PA1, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_2}, + #endif + #ifdef ADC1_PA2_CH3 + {PA2, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_3}, + #endif + #ifdef ADC1_PA3_CH4 + {PA3, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_4}, + #endif + #ifdef ADC1_PB0_CH15 + {PB0, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_15}, + #endif + #ifdef ADC1_PB11_CH14 + {PB11, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_14}, + #endif + #ifdef ADC1_PB12_CH11 + {PB12, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_11}, + #endif + #ifdef ADC1_PB14_CH5 + {PB14, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_5}, + #endif + #ifdef ADC1_PB1_CH12 + {PB1, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_12}, + #endif + #ifdef ADC1_PC0_CH6 + {PC0, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_6}, + #endif + #ifdef ADC1_PC1_CH7 + {PC1, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_7}, + #endif + #ifdef ADC1_PC2_CH8 + {PC2, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_8}, + #endif + #ifdef ADC1_PC3_CH9 + {PC3, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_9}, + #endif + #ifdef ADC1_PF0_CH10 + {PF0, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_10}, + #endif + #ifdef ADC2_PA0_CH1 + {PA0, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_1}, + #endif + #ifdef ADC2_PA1_CH2 + {PA1, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_2}, + #endif + #ifdef ADC2_PA4_CH17 + {PA4, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_17}, + #endif + #ifdef ADC2_PA5_CH13 + {PA5, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_13}, + #endif + #ifdef ADC2_PA6_CH3 + {PA6, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_3}, + #endif + #ifdef ADC2_PA7_CH4 + {PA7, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_4}, + #endif + #ifdef ADC2_PB11_CH14 + {PB11, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_14}, + #endif + #ifdef ADC2_PB15_CH15 + {PB15, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_15}, + #endif + #ifdef ADC2_PB2_CH12 + {PB2, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_12}, + #endif + #ifdef ADC2_PC0_CH6 + {PC0, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_6}, + #endif + #ifdef ADC2_PC1_CH7 + {PC1, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_7}, + #endif + #ifdef ADC2_PC2_CH8 + {PC2, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_8}, + #endif + #ifdef ADC2_PC3_CH9 + {PC3, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_9}, + #endif + #ifdef ADC2_PC4_CH5 + {PC4, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_5}, + #endif + #ifdef ADC2_PC5_CH11 + {PC5, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_11}, + #endif + #ifdef ADC2_PF1_CH10 + {PF1, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_10}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_CHANNEL_ERROR} +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_ADC_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/adc/hal_ll_adc_pin_map/implementations/doc_ds_84/hal_ll_adc_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/adc/hal_ll_adc_pin_map/implementations/doc_ds_84/hal_ll_adc_pin_map.h new file mode 100644 index 000000000..eec4370b9 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/adc/hal_ll_adc_pin_map/implementations/doc_ds_84/hal_ll_adc_pin_map.h @@ -0,0 +1,370 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_adc_pin_map.h + * @brief Header file containing symbolic pin name definitions. + */ + +#ifndef _HAL_LL_ADC_PIN_MAP_H_ +#define _HAL_LL_ADC_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_adc_module_num(_module_num) (_module_num - 1) + +/** + * ADC channels. + */ +typedef enum +{ + HAL_LL_ADC_CHANNEL_0 = 0, + HAL_LL_ADC_CHANNEL_1, + HAL_LL_ADC_CHANNEL_2, + HAL_LL_ADC_CHANNEL_3, + HAL_LL_ADC_CHANNEL_4, + HAL_LL_ADC_CHANNEL_5, + HAL_LL_ADC_CHANNEL_6, + HAL_LL_ADC_CHANNEL_7, + HAL_LL_ADC_CHANNEL_8, + HAL_LL_ADC_CHANNEL_9, + HAL_LL_ADC_CHANNEL_10, + HAL_LL_ADC_CHANNEL_11, + HAL_LL_ADC_CHANNEL_12, + HAL_LL_ADC_CHANNEL_13, + HAL_LL_ADC_CHANNEL_14, + HAL_LL_ADC_CHANNEL_15, + HAL_LL_ADC_CHANNEL_16, + HAL_LL_ADC_CHANNEL_17, + HAL_LL_ADC_CHANNEL_18, + HAL_LL_ADC_CHANNEL_19, + HAL_LL_ADC_CHANNEL_20, + HAL_LL_ADC_CHANNEL_21, + HAL_LL_ADC_CHANNEL_22, + HAL_LL_ADC_CHANNEL_23, + HAL_LL_ADC_CHANNEL_24, + HAL_LL_ADC_CHANNEL_25, + HAL_LL_ADC_CHANNEL_26, + HAL_LL_ADC_CHANNEL_27, + HAL_LL_ADC_CHANNEL_28, + HAL_LL_ADC_CHANNEL_29, + HAL_LL_ADC_CHANNEL_30, + HAL_LL_ADC_CHANNEL_31, + + HAL_LL_ADC_CHANNEL_NC = 0xFFFF +} hal_ll_adc_channel_t; + +/*!< @brief ADC pin structure. */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + hal_ll_adc_channel_t channel; +} hal_ll_adc_pin_map_t; + +#ifdef ADC_MODULE_1 +#define ADC1_BASE_ADDRESS (0x50000000UL) +#define ADC1_BASE_ADDR ADC1_BASE_ADDRESS +#define HAL_LL_ADC1_BASE_ADDR ADC1_BASE_ADDRESS +#define HAL_LL_ADC1_BASE_ADDRESS ADC1_BASE_ADDRESS +#endif +#ifdef ADC_MODULE_2 +#define ADC2_BASE_ADDRESS (0x50000100UL) +#define ADC2_BASE_ADDR ADC2_BASE_ADDRESS +#define HAL_LL_ADC2_BASE_ADDR ADC2_BASE_ADDRESS +#define HAL_LL_ADC2_BASE_ADDRESS ADC2_BASE_ADDRESS +#endif +#ifdef ADC_MODULE_3 +#define ADC3_BASE_ADDRESS (0x50000400UL) +#define ADC3_BASE_ADDR ADC3_BASE_ADDRESS +#define HAL_LL_ADC3_BASE_ADDR ADC3_BASE_ADDRESS +#define HAL_LL_ADC3_BASE_ADDRESS ADC3_BASE_ADDRESS +#endif +#ifdef ADC_MODULE_4 +#define ADC4_BASE_ADDRESS (0x50000500UL) +#define ADC4_BASE_ADDR ADC4_BASE_ADDRESS +#define HAL_LL_ADC4_BASE_ADDR ADC4_BASE_ADDRESS +#define HAL_LL_ADC4_BASE_ADDRESS ADC4_BASE_ADDRESS +#endif +#ifdef ADC_MODULE_5 +#define ADC5_BASE_ADDRESS (0x50000600UL) +#define ADC5_BASE_ADDR ADC5_BASE_ADDRESS +#define HAL_LL_ADC5_BASE_ADDR ADC5_BASE_ADDRESS +#define HAL_LL_ADC5_BASE_ADDRESS ADC5_BASE_ADDRESS +#endif + +/*!< ADC input pins. */ +static const hal_ll_adc_pin_map_t _adc_map[] = +{ + #ifdef ADC1_PA0_CH1 + {PA0, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_1}, + #endif + #ifdef ADC1_PA1_CH2 + {PA1, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_2}, + #endif + #ifdef ADC1_PA2_CH3 + {PA2, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_3}, + #endif + #ifdef ADC1_PA3_CH4 + {PA3, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_4}, + #endif + #ifdef ADC1_PB0_CH15 + {PB0, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_15}, + #endif + #ifdef ADC1_PB11_CH14 + {PB11, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_14}, + #endif + #ifdef ADC1_PB12_CH11 + {PB12, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_11}, + #endif + #ifdef ADC1_PB14_CH5 + {PB14, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_5}, + #endif + #ifdef ADC1_PB1_CH12 + {PB1, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_12}, + #endif + #ifdef ADC1_PC0_CH6 + {PC0, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_6}, + #endif + #ifdef ADC1_PC1_CH7 + {PC1, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_7}, + #endif + #ifdef ADC1_PC2_CH8 + {PC2, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_8}, + #endif + #ifdef ADC1_PC3_CH9 + {PC3, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_9}, + #endif + #ifdef ADC1_PF0_CH10 + {PF0, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_10}, + #endif + #ifdef ADC2_PA0_CH1 + {PA0, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_1}, + #endif + #ifdef ADC2_PA1_CH2 + {PA1, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_2}, + #endif + #ifdef ADC2_PA4_CH17 + {PA4, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_17}, + #endif + #ifdef ADC2_PA5_CH13 + {PA5, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_13}, + #endif + #ifdef ADC2_PA6_CH3 + {PA6, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_3}, + #endif + #ifdef ADC2_PA7_CH4 + {PA7, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_4}, + #endif + #ifdef ADC2_PB11_CH14 + {PB11, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_14}, + #endif + #ifdef ADC2_PB15_CH15 + {PB15, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_15}, + #endif + #ifdef ADC2_PB2_CH12 + {PB2, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_12}, + #endif + #ifdef ADC2_PC0_CH6 + {PC0, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_6}, + #endif + #ifdef ADC2_PC1_CH7 + {PC1, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_7}, + #endif + #ifdef ADC2_PC2_CH8 + {PC2, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_8}, + #endif + #ifdef ADC2_PC3_CH9 + {PC3, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_9}, + #endif + #ifdef ADC2_PC4_CH5 + {PC4, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_5}, + #endif + #ifdef ADC2_PC5_CH11 + {PC5, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_11}, + #endif + #ifdef ADC2_PF1_CH10 + {PF1, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_10}, + #endif + #ifdef ADC3_PB0_CH12 + {PB0, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_12}, + #endif + #ifdef ADC3_PB13_CH5 + {PB13, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_5}, + #endif + #ifdef ADC3_PB1_CH1 + {PB1, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_1}, + #endif + #ifdef ADC3_PD10_CH7 + {PD10, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_7}, + #endif + #ifdef ADC3_PD11_CH8 + {PD11, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_8}, + #endif + #ifdef ADC3_PD12_CH9 + {PD12, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_9}, + #endif + #ifdef ADC3_PD13_CH10 + {PD13, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_10}, + #endif + #ifdef ADC3_PD14_CH11 + {PD14, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_11}, + #endif + #ifdef ADC3_PE10_CH14 + {PE10, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_14}, + #endif + #ifdef ADC3_PE11_CH15 + {PE11, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_15}, + #endif + #ifdef ADC3_PE12_CH16 + {PE12, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_16}, + #endif + #ifdef ADC3_PE13_CH3 + {PE13, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_3}, + #endif + #ifdef ADC3_PE7_CH4 + {PE7, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_4}, + #endif + #ifdef ADC3_PE8_CH6 + {PE8, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_6}, + #endif + #ifdef ADC3_PE9_CH2 + {PE9, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_2}, + #endif + #ifdef ADC4_PB12_CH3 + {PB12, ADC4_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_4), HAL_LL_ADC_CHANNEL_3}, + #endif + #ifdef ADC4_PB14_CH4 + {PB14, ADC4_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_4), HAL_LL_ADC_CHANNEL_4}, + #endif + #ifdef ADC4_PB15_CH5 + {PB15, ADC4_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_4), HAL_LL_ADC_CHANNEL_5}, + #endif + #ifdef ADC4_PD10_CH7 + {PD10, ADC4_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_4), HAL_LL_ADC_CHANNEL_7}, + #endif + #ifdef ADC4_PD11_CH8 + {PD11, ADC4_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_4), HAL_LL_ADC_CHANNEL_8}, + #endif + #ifdef ADC4_PD12_CH9 + {PD12, ADC4_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_4), HAL_LL_ADC_CHANNEL_9}, + #endif + #ifdef ADC4_PD13_CH10 + {PD13, ADC4_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_4), HAL_LL_ADC_CHANNEL_10}, + #endif + #ifdef ADC4_PD14_CH11 + {PD14, ADC4_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_4), HAL_LL_ADC_CHANNEL_11}, + #endif + #ifdef ADC4_PD8_CH12 + {PD8, ADC4_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_4), HAL_LL_ADC_CHANNEL_12}, + #endif + #ifdef ADC4_PD9_CH13 + {PD9, ADC4_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_4), HAL_LL_ADC_CHANNEL_13}, + #endif + #ifdef ADC4_PE10_CH14 + {PE10, ADC4_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_4), HAL_LL_ADC_CHANNEL_14}, + #endif + #ifdef ADC4_PE11_CH15 + {PE11, ADC4_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_4), HAL_LL_ADC_CHANNEL_15}, + #endif + #ifdef ADC4_PE12_CH16 + {PE12, ADC4_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_4), HAL_LL_ADC_CHANNEL_16}, + #endif + #ifdef ADC4_PE14_CH1 + {PE14, ADC4_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_4), HAL_LL_ADC_CHANNEL_1}, + #endif + #ifdef ADC4_PE15_CH2 + {PE15, ADC4_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_4), HAL_LL_ADC_CHANNEL_2}, + #endif + #ifdef ADC4_PE8_CH6 + {PE8, ADC4_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_4), HAL_LL_ADC_CHANNEL_6}, + #endif + #ifdef ADC5_PA8_CH1 + {PA8, ADC5_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_5), HAL_LL_ADC_CHANNEL_1}, + #endif + #ifdef ADC5_PA9_CH2 + {PA9, ADC5_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_5), HAL_LL_ADC_CHANNEL_2}, + #endif + #ifdef ADC5_PD10_CH7 + {PD10, ADC5_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_5), HAL_LL_ADC_CHANNEL_7}, + #endif + #ifdef ADC5_PD11_CH8 + {PD11, ADC5_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_5), HAL_LL_ADC_CHANNEL_8}, + #endif + #ifdef ADC5_PD12_CH9 + {PD12, ADC5_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_5), HAL_LL_ADC_CHANNEL_9}, + #endif + #ifdef ADC5_PD13_CH10 + {PD13, ADC5_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_5), HAL_LL_ADC_CHANNEL_10}, + #endif + #ifdef ADC5_PD14_CH11 + {PD14, ADC5_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_5), HAL_LL_ADC_CHANNEL_11}, + #endif + #ifdef ADC5_PD8_CH12 + {PD8, ADC5_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_5), HAL_LL_ADC_CHANNEL_12}, + #endif + #ifdef ADC5_PD9_CH13 + {PD9, ADC5_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_5), HAL_LL_ADC_CHANNEL_13}, + #endif + #ifdef ADC5_PE10_CH14 + {PE10, ADC5_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_5), HAL_LL_ADC_CHANNEL_14}, + #endif + #ifdef ADC5_PE11_CH15 + {PE11, ADC5_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_5), HAL_LL_ADC_CHANNEL_15}, + #endif + #ifdef ADC5_PE12_CH16 + {PE12, ADC5_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_5), HAL_LL_ADC_CHANNEL_16}, + #endif + #ifdef ADC5_PE8_CH6 + {PE8, ADC5_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_5), HAL_LL_ADC_CHANNEL_6}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_CHANNEL_ERROR} +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_ADC_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/adc/hal_ll_adc_pin_map/implementations/doc_ds_85/hal_ll_adc_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/adc/hal_ll_adc_pin_map/implementations/doc_ds_85/hal_ll_adc_pin_map.h new file mode 100644 index 000000000..e38321e0d --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/adc/hal_ll_adc_pin_map/implementations/doc_ds_85/hal_ll_adc_pin_map.h @@ -0,0 +1,370 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_adc_pin_map.h + * @brief Header file containing symbolic pin name definitions. + */ + +#ifndef _HAL_LL_ADC_PIN_MAP_H_ +#define _HAL_LL_ADC_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_adc_module_num(_module_num) (_module_num - 1) + +/** + * ADC channels. + */ +typedef enum +{ + HAL_LL_ADC_CHANNEL_0 = 0, + HAL_LL_ADC_CHANNEL_1, + HAL_LL_ADC_CHANNEL_2, + HAL_LL_ADC_CHANNEL_3, + HAL_LL_ADC_CHANNEL_4, + HAL_LL_ADC_CHANNEL_5, + HAL_LL_ADC_CHANNEL_6, + HAL_LL_ADC_CHANNEL_7, + HAL_LL_ADC_CHANNEL_8, + HAL_LL_ADC_CHANNEL_9, + HAL_LL_ADC_CHANNEL_10, + HAL_LL_ADC_CHANNEL_11, + HAL_LL_ADC_CHANNEL_12, + HAL_LL_ADC_CHANNEL_13, + HAL_LL_ADC_CHANNEL_14, + HAL_LL_ADC_CHANNEL_15, + HAL_LL_ADC_CHANNEL_16, + HAL_LL_ADC_CHANNEL_17, + HAL_LL_ADC_CHANNEL_18, + HAL_LL_ADC_CHANNEL_19, + HAL_LL_ADC_CHANNEL_20, + HAL_LL_ADC_CHANNEL_21, + HAL_LL_ADC_CHANNEL_22, + HAL_LL_ADC_CHANNEL_23, + HAL_LL_ADC_CHANNEL_24, + HAL_LL_ADC_CHANNEL_25, + HAL_LL_ADC_CHANNEL_26, + HAL_LL_ADC_CHANNEL_27, + HAL_LL_ADC_CHANNEL_28, + HAL_LL_ADC_CHANNEL_29, + HAL_LL_ADC_CHANNEL_30, + HAL_LL_ADC_CHANNEL_31, + + HAL_LL_ADC_CHANNEL_NC = 0xFFFF +} hal_ll_adc_channel_t; + +/*!< @brief ADC pin structure. */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + hal_ll_adc_channel_t channel; +} hal_ll_adc_pin_map_t; + +#ifdef ADC_MODULE_1 +#define ADC1_BASE_ADDRESS (0x50000000UL) +#define ADC1_BASE_ADDR ADC1_BASE_ADDRESS +#define HAL_LL_ADC1_BASE_ADDR ADC1_BASE_ADDRESS +#define HAL_LL_ADC1_BASE_ADDRESS ADC1_BASE_ADDRESS +#endif +#ifdef ADC_MODULE_2 +#define ADC2_BASE_ADDRESS (0x50000100UL) +#define ADC2_BASE_ADDR ADC2_BASE_ADDRESS +#define HAL_LL_ADC2_BASE_ADDR ADC2_BASE_ADDRESS +#define HAL_LL_ADC2_BASE_ADDRESS ADC2_BASE_ADDRESS +#endif +#ifdef ADC_MODULE_3 +#define ADC3_BASE_ADDRESS (0x50000400UL) +#define ADC3_BASE_ADDR ADC3_BASE_ADDRESS +#define HAL_LL_ADC3_BASE_ADDR ADC3_BASE_ADDRESS +#define HAL_LL_ADC3_BASE_ADDRESS ADC3_BASE_ADDRESS +#endif +#ifdef ADC_MODULE_4 +#define ADC4_BASE_ADDRESS (0x50000500UL) +#define ADC4_BASE_ADDR ADC4_BASE_ADDRESS +#define HAL_LL_ADC4_BASE_ADDR ADC4_BASE_ADDRESS +#define HAL_LL_ADC4_BASE_ADDRESS ADC4_BASE_ADDRESS +#endif +#ifdef ADC_MODULE_5 +#define ADC5_BASE_ADDRESS (0x50000600UL) +#define ADC5_BASE_ADDR ADC5_BASE_ADDRESS +#define HAL_LL_ADC5_BASE_ADDR ADC5_BASE_ADDRESS +#define HAL_LL_ADC5_BASE_ADDRESS ADC5_BASE_ADDRESS +#endif + +/*!< ADC input pins. */ +static const hal_ll_adc_pin_map_t _adc_map[] = +{ + #ifdef ADC1_PA0_CH1 + {PA0, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_1}, + #endif + #ifdef ADC1_PA1_CH2 + {PA1, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_2}, + #endif + #ifdef ADC1_PA2_CH3 + {PA2, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_3}, + #endif + #ifdef ADC1_PA3_CH4 + {PA3, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_4}, + #endif + #ifdef ADC1_PB0_CH15 + {PB0, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_15}, + #endif + #ifdef ADC1_PB11_CH14 + {PB11, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_14}, + #endif + #ifdef ADC1_PB12_CH11 + {PB12, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_11}, + #endif + #ifdef ADC1_PB14_CH5 + {PB14, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_5}, + #endif + #ifdef ADC1_PB1_CH12 + {PB1, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_12}, + #endif + #ifdef ADC1_PF0_CH10 + {PF0, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_10}, + #endif + #ifdef ADC2_PA0_CH1 + {PA0, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_1}, + #endif + #ifdef ADC2_PA1_CH2 + {PA1, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_2}, + #endif + #ifdef ADC2_PA4_CH17 + {PA4, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_17}, + #endif + #ifdef ADC2_PA5_CH13 + {PA5, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_13}, + #endif + #ifdef ADC2_PA6_CH3 + {PA6, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_3}, + #endif + #ifdef ADC2_PA7_CH4 + {PA7, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_4}, + #endif + #ifdef ADC2_PB11_CH14 + {PB11, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_14}, + #endif + #ifdef ADC2_PB15_CH15 + {PB15, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_15}, + #endif + #ifdef ADC2_PB2_CH12 + {PB2, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_12}, + #endif + #ifdef ADC2_PC4_CH5 + {PC4, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_5}, + #endif + #ifdef ADC2_PF1_CH10 + {PF1, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_10}, + #endif + #ifdef ADC3_PB0_CH12 + {PB0, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_12}, + #endif + #ifdef ADC3_PB13_CH5 + {PB13, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_5}, + #endif + #ifdef ADC3_PB1_CH1 + {PB1, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_1}, + #endif + #ifdef ADC4_PB12_CH3 + {PB12, ADC4_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_4), HAL_LL_ADC_CHANNEL_3}, + #endif + #ifdef ADC4_PB14_CH4 + {PB14, ADC4_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_4), HAL_LL_ADC_CHANNEL_4}, + #endif + #ifdef ADC4_PB15_CH5 + {PB15, ADC4_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_4), HAL_LL_ADC_CHANNEL_5}, + #endif + #ifdef ADC5_PA8_CH1 + {PA8, ADC5_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_5), HAL_LL_ADC_CHANNEL_1}, + #endif + #ifdef ADC5_PA9_CH2 + {PA9, ADC5_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_5), HAL_LL_ADC_CHANNEL_2}, + #endif + #ifdef ADC1_PC0_CH6 + {PC0, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_6}, + #endif + #ifdef ADC1_PC1_CH7 + {PC1, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_7}, + #endif + #ifdef ADC1_PC2_CH8 + {PC2, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_8}, + #endif + #ifdef ADC1_PC3_CH9 + {PC3, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_9}, + #endif + #ifdef ADC2_PC0_CH6 + {PC0, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_6}, + #endif + #ifdef ADC2_PC1_CH7 + {PC1, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_7}, + #endif + #ifdef ADC2_PC2_CH8 + {PC2, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_8}, + #endif + #ifdef ADC2_PC3_CH9 + {PC3, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_9}, + #endif + #ifdef ADC2_PC5_CH11 + {PC5, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_11}, + #endif + #ifdef ADC3_PD10_CH7 + {PD10, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_7}, + #endif + #ifdef ADC3_PD11_CH8 + {PD11, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_8}, + #endif + #ifdef ADC3_PD12_CH9 + {PD12, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_9}, + #endif + #ifdef ADC3_PD13_CH10 + {PD13, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_10}, + #endif + #ifdef ADC3_PD14_CH11 + {PD14, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_11}, + #endif + #ifdef ADC3_PE10_CH14 + {PE10, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_14}, + #endif + #ifdef ADC3_PE11_CH15 + {PE11, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_15}, + #endif + #ifdef ADC3_PE12_CH16 + {PE12, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_16}, + #endif + #ifdef ADC3_PE13_CH3 + {PE13, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_3}, + #endif + #ifdef ADC3_PE7_CH4 + {PE7, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_4}, + #endif + #ifdef ADC3_PE8_CH6 + {PE8, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_6}, + #endif + #ifdef ADC3_PE9_CH2 + {PE9, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_2}, + #endif + #ifdef ADC4_PD10_CH7 + {PD10, ADC4_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_4), HAL_LL_ADC_CHANNEL_7}, + #endif + #ifdef ADC4_PD11_CH8 + {PD11, ADC4_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_4), HAL_LL_ADC_CHANNEL_8}, + #endif + #ifdef ADC4_PD12_CH9 + {PD12, ADC4_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_4), HAL_LL_ADC_CHANNEL_9}, + #endif + #ifdef ADC4_PD13_CH10 + {PD13, ADC4_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_4), HAL_LL_ADC_CHANNEL_10}, + #endif + #ifdef ADC4_PD14_CH11 + {PD14, ADC4_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_4), HAL_LL_ADC_CHANNEL_11}, + #endif + #ifdef ADC4_PD8_CH12 + {PD8, ADC4_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_4), HAL_LL_ADC_CHANNEL_12}, + #endif + #ifdef ADC4_PD9_CH13 + {PD9, ADC4_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_4), HAL_LL_ADC_CHANNEL_13}, + #endif + #ifdef ADC4_PE10_CH14 + {PE10, ADC4_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_4), HAL_LL_ADC_CHANNEL_14}, + #endif + #ifdef ADC4_PE11_CH15 + {PE11, ADC4_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_4), HAL_LL_ADC_CHANNEL_15}, + #endif + #ifdef ADC4_PE12_CH16 + {PE12, ADC4_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_4), HAL_LL_ADC_CHANNEL_16}, + #endif + #ifdef ADC4_PE14_CH1 + {PE14, ADC4_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_4), HAL_LL_ADC_CHANNEL_1}, + #endif + #ifdef ADC4_PE15_CH2 + {PE15, ADC4_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_4), HAL_LL_ADC_CHANNEL_2}, + #endif + #ifdef ADC4_PE8_CH6 + {PE8, ADC4_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_4), HAL_LL_ADC_CHANNEL_6}, + #endif + #ifdef ADC5_PD10_CH7 + {PD10, ADC5_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_5), HAL_LL_ADC_CHANNEL_7}, + #endif + #ifdef ADC5_PD11_CH8 + {PD11, ADC5_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_5), HAL_LL_ADC_CHANNEL_8}, + #endif + #ifdef ADC5_PD12_CH9 + {PD12, ADC5_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_5), HAL_LL_ADC_CHANNEL_9}, + #endif + #ifdef ADC5_PD13_CH10 + {PD13, ADC5_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_5), HAL_LL_ADC_CHANNEL_10}, + #endif + #ifdef ADC5_PD14_CH11 + {PD14, ADC5_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_5), HAL_LL_ADC_CHANNEL_11}, + #endif + #ifdef ADC5_PD8_CH12 + {PD8, ADC5_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_5), HAL_LL_ADC_CHANNEL_12}, + #endif + #ifdef ADC5_PD9_CH13 + {PD9, ADC5_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_5), HAL_LL_ADC_CHANNEL_13}, + #endif + #ifdef ADC5_PE10_CH14 + {PE10, ADC5_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_5), HAL_LL_ADC_CHANNEL_14}, + #endif + #ifdef ADC5_PE11_CH15 + {PE11, ADC5_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_5), HAL_LL_ADC_CHANNEL_15}, + #endif + #ifdef ADC5_PE12_CH16 + {PE12, ADC5_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_5), HAL_LL_ADC_CHANNEL_16}, + #endif + #ifdef ADC5_PE8_CH6 + {PE8, ADC5_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_5), HAL_LL_ADC_CHANNEL_6}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_CHANNEL_ERROR} +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_ADC_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/adc/hal_ll_adc_pin_map/implementations/doc_ds_86/hal_ll_adc_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/adc/hal_ll_adc_pin_map/implementations/doc_ds_86/hal_ll_adc_pin_map.h new file mode 100644 index 000000000..eec4370b9 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/adc/hal_ll_adc_pin_map/implementations/doc_ds_86/hal_ll_adc_pin_map.h @@ -0,0 +1,370 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_adc_pin_map.h + * @brief Header file containing symbolic pin name definitions. + */ + +#ifndef _HAL_LL_ADC_PIN_MAP_H_ +#define _HAL_LL_ADC_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_adc_module_num(_module_num) (_module_num - 1) + +/** + * ADC channels. + */ +typedef enum +{ + HAL_LL_ADC_CHANNEL_0 = 0, + HAL_LL_ADC_CHANNEL_1, + HAL_LL_ADC_CHANNEL_2, + HAL_LL_ADC_CHANNEL_3, + HAL_LL_ADC_CHANNEL_4, + HAL_LL_ADC_CHANNEL_5, + HAL_LL_ADC_CHANNEL_6, + HAL_LL_ADC_CHANNEL_7, + HAL_LL_ADC_CHANNEL_8, + HAL_LL_ADC_CHANNEL_9, + HAL_LL_ADC_CHANNEL_10, + HAL_LL_ADC_CHANNEL_11, + HAL_LL_ADC_CHANNEL_12, + HAL_LL_ADC_CHANNEL_13, + HAL_LL_ADC_CHANNEL_14, + HAL_LL_ADC_CHANNEL_15, + HAL_LL_ADC_CHANNEL_16, + HAL_LL_ADC_CHANNEL_17, + HAL_LL_ADC_CHANNEL_18, + HAL_LL_ADC_CHANNEL_19, + HAL_LL_ADC_CHANNEL_20, + HAL_LL_ADC_CHANNEL_21, + HAL_LL_ADC_CHANNEL_22, + HAL_LL_ADC_CHANNEL_23, + HAL_LL_ADC_CHANNEL_24, + HAL_LL_ADC_CHANNEL_25, + HAL_LL_ADC_CHANNEL_26, + HAL_LL_ADC_CHANNEL_27, + HAL_LL_ADC_CHANNEL_28, + HAL_LL_ADC_CHANNEL_29, + HAL_LL_ADC_CHANNEL_30, + HAL_LL_ADC_CHANNEL_31, + + HAL_LL_ADC_CHANNEL_NC = 0xFFFF +} hal_ll_adc_channel_t; + +/*!< @brief ADC pin structure. */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + hal_ll_adc_channel_t channel; +} hal_ll_adc_pin_map_t; + +#ifdef ADC_MODULE_1 +#define ADC1_BASE_ADDRESS (0x50000000UL) +#define ADC1_BASE_ADDR ADC1_BASE_ADDRESS +#define HAL_LL_ADC1_BASE_ADDR ADC1_BASE_ADDRESS +#define HAL_LL_ADC1_BASE_ADDRESS ADC1_BASE_ADDRESS +#endif +#ifdef ADC_MODULE_2 +#define ADC2_BASE_ADDRESS (0x50000100UL) +#define ADC2_BASE_ADDR ADC2_BASE_ADDRESS +#define HAL_LL_ADC2_BASE_ADDR ADC2_BASE_ADDRESS +#define HAL_LL_ADC2_BASE_ADDRESS ADC2_BASE_ADDRESS +#endif +#ifdef ADC_MODULE_3 +#define ADC3_BASE_ADDRESS (0x50000400UL) +#define ADC3_BASE_ADDR ADC3_BASE_ADDRESS +#define HAL_LL_ADC3_BASE_ADDR ADC3_BASE_ADDRESS +#define HAL_LL_ADC3_BASE_ADDRESS ADC3_BASE_ADDRESS +#endif +#ifdef ADC_MODULE_4 +#define ADC4_BASE_ADDRESS (0x50000500UL) +#define ADC4_BASE_ADDR ADC4_BASE_ADDRESS +#define HAL_LL_ADC4_BASE_ADDR ADC4_BASE_ADDRESS +#define HAL_LL_ADC4_BASE_ADDRESS ADC4_BASE_ADDRESS +#endif +#ifdef ADC_MODULE_5 +#define ADC5_BASE_ADDRESS (0x50000600UL) +#define ADC5_BASE_ADDR ADC5_BASE_ADDRESS +#define HAL_LL_ADC5_BASE_ADDR ADC5_BASE_ADDRESS +#define HAL_LL_ADC5_BASE_ADDRESS ADC5_BASE_ADDRESS +#endif + +/*!< ADC input pins. */ +static const hal_ll_adc_pin_map_t _adc_map[] = +{ + #ifdef ADC1_PA0_CH1 + {PA0, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_1}, + #endif + #ifdef ADC1_PA1_CH2 + {PA1, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_2}, + #endif + #ifdef ADC1_PA2_CH3 + {PA2, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_3}, + #endif + #ifdef ADC1_PA3_CH4 + {PA3, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_4}, + #endif + #ifdef ADC1_PB0_CH15 + {PB0, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_15}, + #endif + #ifdef ADC1_PB11_CH14 + {PB11, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_14}, + #endif + #ifdef ADC1_PB12_CH11 + {PB12, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_11}, + #endif + #ifdef ADC1_PB14_CH5 + {PB14, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_5}, + #endif + #ifdef ADC1_PB1_CH12 + {PB1, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_12}, + #endif + #ifdef ADC1_PC0_CH6 + {PC0, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_6}, + #endif + #ifdef ADC1_PC1_CH7 + {PC1, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_7}, + #endif + #ifdef ADC1_PC2_CH8 + {PC2, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_8}, + #endif + #ifdef ADC1_PC3_CH9 + {PC3, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_9}, + #endif + #ifdef ADC1_PF0_CH10 + {PF0, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_10}, + #endif + #ifdef ADC2_PA0_CH1 + {PA0, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_1}, + #endif + #ifdef ADC2_PA1_CH2 + {PA1, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_2}, + #endif + #ifdef ADC2_PA4_CH17 + {PA4, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_17}, + #endif + #ifdef ADC2_PA5_CH13 + {PA5, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_13}, + #endif + #ifdef ADC2_PA6_CH3 + {PA6, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_3}, + #endif + #ifdef ADC2_PA7_CH4 + {PA7, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_4}, + #endif + #ifdef ADC2_PB11_CH14 + {PB11, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_14}, + #endif + #ifdef ADC2_PB15_CH15 + {PB15, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_15}, + #endif + #ifdef ADC2_PB2_CH12 + {PB2, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_12}, + #endif + #ifdef ADC2_PC0_CH6 + {PC0, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_6}, + #endif + #ifdef ADC2_PC1_CH7 + {PC1, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_7}, + #endif + #ifdef ADC2_PC2_CH8 + {PC2, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_8}, + #endif + #ifdef ADC2_PC3_CH9 + {PC3, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_9}, + #endif + #ifdef ADC2_PC4_CH5 + {PC4, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_5}, + #endif + #ifdef ADC2_PC5_CH11 + {PC5, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_11}, + #endif + #ifdef ADC2_PF1_CH10 + {PF1, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_10}, + #endif + #ifdef ADC3_PB0_CH12 + {PB0, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_12}, + #endif + #ifdef ADC3_PB13_CH5 + {PB13, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_5}, + #endif + #ifdef ADC3_PB1_CH1 + {PB1, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_1}, + #endif + #ifdef ADC3_PD10_CH7 + {PD10, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_7}, + #endif + #ifdef ADC3_PD11_CH8 + {PD11, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_8}, + #endif + #ifdef ADC3_PD12_CH9 + {PD12, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_9}, + #endif + #ifdef ADC3_PD13_CH10 + {PD13, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_10}, + #endif + #ifdef ADC3_PD14_CH11 + {PD14, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_11}, + #endif + #ifdef ADC3_PE10_CH14 + {PE10, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_14}, + #endif + #ifdef ADC3_PE11_CH15 + {PE11, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_15}, + #endif + #ifdef ADC3_PE12_CH16 + {PE12, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_16}, + #endif + #ifdef ADC3_PE13_CH3 + {PE13, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_3}, + #endif + #ifdef ADC3_PE7_CH4 + {PE7, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_4}, + #endif + #ifdef ADC3_PE8_CH6 + {PE8, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_6}, + #endif + #ifdef ADC3_PE9_CH2 + {PE9, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_2}, + #endif + #ifdef ADC4_PB12_CH3 + {PB12, ADC4_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_4), HAL_LL_ADC_CHANNEL_3}, + #endif + #ifdef ADC4_PB14_CH4 + {PB14, ADC4_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_4), HAL_LL_ADC_CHANNEL_4}, + #endif + #ifdef ADC4_PB15_CH5 + {PB15, ADC4_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_4), HAL_LL_ADC_CHANNEL_5}, + #endif + #ifdef ADC4_PD10_CH7 + {PD10, ADC4_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_4), HAL_LL_ADC_CHANNEL_7}, + #endif + #ifdef ADC4_PD11_CH8 + {PD11, ADC4_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_4), HAL_LL_ADC_CHANNEL_8}, + #endif + #ifdef ADC4_PD12_CH9 + {PD12, ADC4_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_4), HAL_LL_ADC_CHANNEL_9}, + #endif + #ifdef ADC4_PD13_CH10 + {PD13, ADC4_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_4), HAL_LL_ADC_CHANNEL_10}, + #endif + #ifdef ADC4_PD14_CH11 + {PD14, ADC4_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_4), HAL_LL_ADC_CHANNEL_11}, + #endif + #ifdef ADC4_PD8_CH12 + {PD8, ADC4_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_4), HAL_LL_ADC_CHANNEL_12}, + #endif + #ifdef ADC4_PD9_CH13 + {PD9, ADC4_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_4), HAL_LL_ADC_CHANNEL_13}, + #endif + #ifdef ADC4_PE10_CH14 + {PE10, ADC4_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_4), HAL_LL_ADC_CHANNEL_14}, + #endif + #ifdef ADC4_PE11_CH15 + {PE11, ADC4_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_4), HAL_LL_ADC_CHANNEL_15}, + #endif + #ifdef ADC4_PE12_CH16 + {PE12, ADC4_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_4), HAL_LL_ADC_CHANNEL_16}, + #endif + #ifdef ADC4_PE14_CH1 + {PE14, ADC4_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_4), HAL_LL_ADC_CHANNEL_1}, + #endif + #ifdef ADC4_PE15_CH2 + {PE15, ADC4_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_4), HAL_LL_ADC_CHANNEL_2}, + #endif + #ifdef ADC4_PE8_CH6 + {PE8, ADC4_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_4), HAL_LL_ADC_CHANNEL_6}, + #endif + #ifdef ADC5_PA8_CH1 + {PA8, ADC5_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_5), HAL_LL_ADC_CHANNEL_1}, + #endif + #ifdef ADC5_PA9_CH2 + {PA9, ADC5_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_5), HAL_LL_ADC_CHANNEL_2}, + #endif + #ifdef ADC5_PD10_CH7 + {PD10, ADC5_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_5), HAL_LL_ADC_CHANNEL_7}, + #endif + #ifdef ADC5_PD11_CH8 + {PD11, ADC5_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_5), HAL_LL_ADC_CHANNEL_8}, + #endif + #ifdef ADC5_PD12_CH9 + {PD12, ADC5_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_5), HAL_LL_ADC_CHANNEL_9}, + #endif + #ifdef ADC5_PD13_CH10 + {PD13, ADC5_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_5), HAL_LL_ADC_CHANNEL_10}, + #endif + #ifdef ADC5_PD14_CH11 + {PD14, ADC5_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_5), HAL_LL_ADC_CHANNEL_11}, + #endif + #ifdef ADC5_PD8_CH12 + {PD8, ADC5_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_5), HAL_LL_ADC_CHANNEL_12}, + #endif + #ifdef ADC5_PD9_CH13 + {PD9, ADC5_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_5), HAL_LL_ADC_CHANNEL_13}, + #endif + #ifdef ADC5_PE10_CH14 + {PE10, ADC5_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_5), HAL_LL_ADC_CHANNEL_14}, + #endif + #ifdef ADC5_PE11_CH15 + {PE11, ADC5_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_5), HAL_LL_ADC_CHANNEL_15}, + #endif + #ifdef ADC5_PE12_CH16 + {PE12, ADC5_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_5), HAL_LL_ADC_CHANNEL_16}, + #endif + #ifdef ADC5_PE8_CH6 + {PE8, ADC5_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_5), HAL_LL_ADC_CHANNEL_6}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_CHANNEL_ERROR} +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_ADC_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/adc/hal_ll_adc_pin_map/implementations/doc_ds_87/hal_ll_adc_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/adc/hal_ll_adc_pin_map/implementations/doc_ds_87/hal_ll_adc_pin_map.h new file mode 100644 index 000000000..eec4370b9 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/adc/hal_ll_adc_pin_map/implementations/doc_ds_87/hal_ll_adc_pin_map.h @@ -0,0 +1,370 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_adc_pin_map.h + * @brief Header file containing symbolic pin name definitions. + */ + +#ifndef _HAL_LL_ADC_PIN_MAP_H_ +#define _HAL_LL_ADC_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_adc_module_num(_module_num) (_module_num - 1) + +/** + * ADC channels. + */ +typedef enum +{ + HAL_LL_ADC_CHANNEL_0 = 0, + HAL_LL_ADC_CHANNEL_1, + HAL_LL_ADC_CHANNEL_2, + HAL_LL_ADC_CHANNEL_3, + HAL_LL_ADC_CHANNEL_4, + HAL_LL_ADC_CHANNEL_5, + HAL_LL_ADC_CHANNEL_6, + HAL_LL_ADC_CHANNEL_7, + HAL_LL_ADC_CHANNEL_8, + HAL_LL_ADC_CHANNEL_9, + HAL_LL_ADC_CHANNEL_10, + HAL_LL_ADC_CHANNEL_11, + HAL_LL_ADC_CHANNEL_12, + HAL_LL_ADC_CHANNEL_13, + HAL_LL_ADC_CHANNEL_14, + HAL_LL_ADC_CHANNEL_15, + HAL_LL_ADC_CHANNEL_16, + HAL_LL_ADC_CHANNEL_17, + HAL_LL_ADC_CHANNEL_18, + HAL_LL_ADC_CHANNEL_19, + HAL_LL_ADC_CHANNEL_20, + HAL_LL_ADC_CHANNEL_21, + HAL_LL_ADC_CHANNEL_22, + HAL_LL_ADC_CHANNEL_23, + HAL_LL_ADC_CHANNEL_24, + HAL_LL_ADC_CHANNEL_25, + HAL_LL_ADC_CHANNEL_26, + HAL_LL_ADC_CHANNEL_27, + HAL_LL_ADC_CHANNEL_28, + HAL_LL_ADC_CHANNEL_29, + HAL_LL_ADC_CHANNEL_30, + HAL_LL_ADC_CHANNEL_31, + + HAL_LL_ADC_CHANNEL_NC = 0xFFFF +} hal_ll_adc_channel_t; + +/*!< @brief ADC pin structure. */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + hal_ll_adc_channel_t channel; +} hal_ll_adc_pin_map_t; + +#ifdef ADC_MODULE_1 +#define ADC1_BASE_ADDRESS (0x50000000UL) +#define ADC1_BASE_ADDR ADC1_BASE_ADDRESS +#define HAL_LL_ADC1_BASE_ADDR ADC1_BASE_ADDRESS +#define HAL_LL_ADC1_BASE_ADDRESS ADC1_BASE_ADDRESS +#endif +#ifdef ADC_MODULE_2 +#define ADC2_BASE_ADDRESS (0x50000100UL) +#define ADC2_BASE_ADDR ADC2_BASE_ADDRESS +#define HAL_LL_ADC2_BASE_ADDR ADC2_BASE_ADDRESS +#define HAL_LL_ADC2_BASE_ADDRESS ADC2_BASE_ADDRESS +#endif +#ifdef ADC_MODULE_3 +#define ADC3_BASE_ADDRESS (0x50000400UL) +#define ADC3_BASE_ADDR ADC3_BASE_ADDRESS +#define HAL_LL_ADC3_BASE_ADDR ADC3_BASE_ADDRESS +#define HAL_LL_ADC3_BASE_ADDRESS ADC3_BASE_ADDRESS +#endif +#ifdef ADC_MODULE_4 +#define ADC4_BASE_ADDRESS (0x50000500UL) +#define ADC4_BASE_ADDR ADC4_BASE_ADDRESS +#define HAL_LL_ADC4_BASE_ADDR ADC4_BASE_ADDRESS +#define HAL_LL_ADC4_BASE_ADDRESS ADC4_BASE_ADDRESS +#endif +#ifdef ADC_MODULE_5 +#define ADC5_BASE_ADDRESS (0x50000600UL) +#define ADC5_BASE_ADDR ADC5_BASE_ADDRESS +#define HAL_LL_ADC5_BASE_ADDR ADC5_BASE_ADDRESS +#define HAL_LL_ADC5_BASE_ADDRESS ADC5_BASE_ADDRESS +#endif + +/*!< ADC input pins. */ +static const hal_ll_adc_pin_map_t _adc_map[] = +{ + #ifdef ADC1_PA0_CH1 + {PA0, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_1}, + #endif + #ifdef ADC1_PA1_CH2 + {PA1, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_2}, + #endif + #ifdef ADC1_PA2_CH3 + {PA2, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_3}, + #endif + #ifdef ADC1_PA3_CH4 + {PA3, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_4}, + #endif + #ifdef ADC1_PB0_CH15 + {PB0, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_15}, + #endif + #ifdef ADC1_PB11_CH14 + {PB11, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_14}, + #endif + #ifdef ADC1_PB12_CH11 + {PB12, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_11}, + #endif + #ifdef ADC1_PB14_CH5 + {PB14, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_5}, + #endif + #ifdef ADC1_PB1_CH12 + {PB1, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_12}, + #endif + #ifdef ADC1_PC0_CH6 + {PC0, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_6}, + #endif + #ifdef ADC1_PC1_CH7 + {PC1, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_7}, + #endif + #ifdef ADC1_PC2_CH8 + {PC2, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_8}, + #endif + #ifdef ADC1_PC3_CH9 + {PC3, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_9}, + #endif + #ifdef ADC1_PF0_CH10 + {PF0, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_10}, + #endif + #ifdef ADC2_PA0_CH1 + {PA0, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_1}, + #endif + #ifdef ADC2_PA1_CH2 + {PA1, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_2}, + #endif + #ifdef ADC2_PA4_CH17 + {PA4, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_17}, + #endif + #ifdef ADC2_PA5_CH13 + {PA5, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_13}, + #endif + #ifdef ADC2_PA6_CH3 + {PA6, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_3}, + #endif + #ifdef ADC2_PA7_CH4 + {PA7, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_4}, + #endif + #ifdef ADC2_PB11_CH14 + {PB11, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_14}, + #endif + #ifdef ADC2_PB15_CH15 + {PB15, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_15}, + #endif + #ifdef ADC2_PB2_CH12 + {PB2, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_12}, + #endif + #ifdef ADC2_PC0_CH6 + {PC0, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_6}, + #endif + #ifdef ADC2_PC1_CH7 + {PC1, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_7}, + #endif + #ifdef ADC2_PC2_CH8 + {PC2, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_8}, + #endif + #ifdef ADC2_PC3_CH9 + {PC3, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_9}, + #endif + #ifdef ADC2_PC4_CH5 + {PC4, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_5}, + #endif + #ifdef ADC2_PC5_CH11 + {PC5, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_11}, + #endif + #ifdef ADC2_PF1_CH10 + {PF1, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_10}, + #endif + #ifdef ADC3_PB0_CH12 + {PB0, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_12}, + #endif + #ifdef ADC3_PB13_CH5 + {PB13, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_5}, + #endif + #ifdef ADC3_PB1_CH1 + {PB1, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_1}, + #endif + #ifdef ADC3_PD10_CH7 + {PD10, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_7}, + #endif + #ifdef ADC3_PD11_CH8 + {PD11, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_8}, + #endif + #ifdef ADC3_PD12_CH9 + {PD12, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_9}, + #endif + #ifdef ADC3_PD13_CH10 + {PD13, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_10}, + #endif + #ifdef ADC3_PD14_CH11 + {PD14, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_11}, + #endif + #ifdef ADC3_PE10_CH14 + {PE10, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_14}, + #endif + #ifdef ADC3_PE11_CH15 + {PE11, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_15}, + #endif + #ifdef ADC3_PE12_CH16 + {PE12, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_16}, + #endif + #ifdef ADC3_PE13_CH3 + {PE13, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_3}, + #endif + #ifdef ADC3_PE7_CH4 + {PE7, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_4}, + #endif + #ifdef ADC3_PE8_CH6 + {PE8, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_6}, + #endif + #ifdef ADC3_PE9_CH2 + {PE9, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_2}, + #endif + #ifdef ADC4_PB12_CH3 + {PB12, ADC4_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_4), HAL_LL_ADC_CHANNEL_3}, + #endif + #ifdef ADC4_PB14_CH4 + {PB14, ADC4_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_4), HAL_LL_ADC_CHANNEL_4}, + #endif + #ifdef ADC4_PB15_CH5 + {PB15, ADC4_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_4), HAL_LL_ADC_CHANNEL_5}, + #endif + #ifdef ADC4_PD10_CH7 + {PD10, ADC4_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_4), HAL_LL_ADC_CHANNEL_7}, + #endif + #ifdef ADC4_PD11_CH8 + {PD11, ADC4_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_4), HAL_LL_ADC_CHANNEL_8}, + #endif + #ifdef ADC4_PD12_CH9 + {PD12, ADC4_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_4), HAL_LL_ADC_CHANNEL_9}, + #endif + #ifdef ADC4_PD13_CH10 + {PD13, ADC4_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_4), HAL_LL_ADC_CHANNEL_10}, + #endif + #ifdef ADC4_PD14_CH11 + {PD14, ADC4_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_4), HAL_LL_ADC_CHANNEL_11}, + #endif + #ifdef ADC4_PD8_CH12 + {PD8, ADC4_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_4), HAL_LL_ADC_CHANNEL_12}, + #endif + #ifdef ADC4_PD9_CH13 + {PD9, ADC4_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_4), HAL_LL_ADC_CHANNEL_13}, + #endif + #ifdef ADC4_PE10_CH14 + {PE10, ADC4_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_4), HAL_LL_ADC_CHANNEL_14}, + #endif + #ifdef ADC4_PE11_CH15 + {PE11, ADC4_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_4), HAL_LL_ADC_CHANNEL_15}, + #endif + #ifdef ADC4_PE12_CH16 + {PE12, ADC4_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_4), HAL_LL_ADC_CHANNEL_16}, + #endif + #ifdef ADC4_PE14_CH1 + {PE14, ADC4_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_4), HAL_LL_ADC_CHANNEL_1}, + #endif + #ifdef ADC4_PE15_CH2 + {PE15, ADC4_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_4), HAL_LL_ADC_CHANNEL_2}, + #endif + #ifdef ADC4_PE8_CH6 + {PE8, ADC4_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_4), HAL_LL_ADC_CHANNEL_6}, + #endif + #ifdef ADC5_PA8_CH1 + {PA8, ADC5_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_5), HAL_LL_ADC_CHANNEL_1}, + #endif + #ifdef ADC5_PA9_CH2 + {PA9, ADC5_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_5), HAL_LL_ADC_CHANNEL_2}, + #endif + #ifdef ADC5_PD10_CH7 + {PD10, ADC5_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_5), HAL_LL_ADC_CHANNEL_7}, + #endif + #ifdef ADC5_PD11_CH8 + {PD11, ADC5_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_5), HAL_LL_ADC_CHANNEL_8}, + #endif + #ifdef ADC5_PD12_CH9 + {PD12, ADC5_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_5), HAL_LL_ADC_CHANNEL_9}, + #endif + #ifdef ADC5_PD13_CH10 + {PD13, ADC5_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_5), HAL_LL_ADC_CHANNEL_10}, + #endif + #ifdef ADC5_PD14_CH11 + {PD14, ADC5_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_5), HAL_LL_ADC_CHANNEL_11}, + #endif + #ifdef ADC5_PD8_CH12 + {PD8, ADC5_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_5), HAL_LL_ADC_CHANNEL_12}, + #endif + #ifdef ADC5_PD9_CH13 + {PD9, ADC5_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_5), HAL_LL_ADC_CHANNEL_13}, + #endif + #ifdef ADC5_PE10_CH14 + {PE10, ADC5_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_5), HAL_LL_ADC_CHANNEL_14}, + #endif + #ifdef ADC5_PE11_CH15 + {PE11, ADC5_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_5), HAL_LL_ADC_CHANNEL_15}, + #endif + #ifdef ADC5_PE12_CH16 + {PE12, ADC5_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_5), HAL_LL_ADC_CHANNEL_16}, + #endif + #ifdef ADC5_PE8_CH6 + {PE8, ADC5_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_5), HAL_LL_ADC_CHANNEL_6}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_CHANNEL_ERROR} +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_ADC_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/adc/hal_ll_adc_pin_map/implementations/doc_ds_88/hal_ll_adc_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/adc/hal_ll_adc_pin_map/implementations/doc_ds_88/hal_ll_adc_pin_map.h new file mode 100644 index 000000000..0216711aa --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/adc/hal_ll_adc_pin_map/implementations/doc_ds_88/hal_ll_adc_pin_map.h @@ -0,0 +1,271 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_adc_pin_map.h + * @brief Header file containing symbolic pin name definitions. + */ + +#ifndef _HAL_LL_ADC_PIN_MAP_H_ +#define _HAL_LL_ADC_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_adc_module_num(_module_num) (_module_num - 1) + +/** + * ADC channels. + */ +typedef enum +{ + HAL_LL_ADC_CHANNEL_0 = 0, + HAL_LL_ADC_CHANNEL_1, + HAL_LL_ADC_CHANNEL_2, + HAL_LL_ADC_CHANNEL_3, + HAL_LL_ADC_CHANNEL_4, + HAL_LL_ADC_CHANNEL_5, + HAL_LL_ADC_CHANNEL_6, + HAL_LL_ADC_CHANNEL_7, + HAL_LL_ADC_CHANNEL_8, + HAL_LL_ADC_CHANNEL_9, + HAL_LL_ADC_CHANNEL_10, + HAL_LL_ADC_CHANNEL_11, + HAL_LL_ADC_CHANNEL_12, + HAL_LL_ADC_CHANNEL_13, + HAL_LL_ADC_CHANNEL_14, + HAL_LL_ADC_CHANNEL_15, + HAL_LL_ADC_CHANNEL_16, + HAL_LL_ADC_CHANNEL_17, + HAL_LL_ADC_CHANNEL_18, + HAL_LL_ADC_CHANNEL_19, + HAL_LL_ADC_CHANNEL_20, + HAL_LL_ADC_CHANNEL_21, + HAL_LL_ADC_CHANNEL_22, + HAL_LL_ADC_CHANNEL_23, + HAL_LL_ADC_CHANNEL_24, + HAL_LL_ADC_CHANNEL_25, + HAL_LL_ADC_CHANNEL_26, + HAL_LL_ADC_CHANNEL_27, + HAL_LL_ADC_CHANNEL_28, + HAL_LL_ADC_CHANNEL_29, + HAL_LL_ADC_CHANNEL_30, + HAL_LL_ADC_CHANNEL_31, + + HAL_LL_ADC_CHANNEL_NC = 0xFFFF +} hal_ll_adc_channel_t; + +/*!< @brief ADC pin structure. */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + hal_ll_adc_channel_t channel; +} hal_ll_adc_pin_map_t; + +#ifdef ADC_MODULE_1 +#define ADC1_BASE_ADDRESS (0x50000000UL) +#define ADC1_BASE_ADDR ADC1_BASE_ADDRESS +#define HAL_LL_ADC1_BASE_ADDR ADC1_BASE_ADDRESS +#define HAL_LL_ADC1_BASE_ADDRESS ADC1_BASE_ADDRESS +#endif +#ifdef ADC_MODULE_2 +#define ADC2_BASE_ADDRESS (0x50000100UL) +#define ADC2_BASE_ADDR ADC2_BASE_ADDRESS +#define HAL_LL_ADC2_BASE_ADDR ADC2_BASE_ADDRESS +#define HAL_LL_ADC2_BASE_ADDRESS ADC2_BASE_ADDRESS +#endif +#ifdef ADC_MODULE_3 +#define ADC3_BASE_ADDRESS (0x50000400UL) +#define ADC3_BASE_ADDR ADC3_BASE_ADDRESS +#define HAL_LL_ADC3_BASE_ADDR ADC3_BASE_ADDRESS +#define HAL_LL_ADC3_BASE_ADDRESS ADC3_BASE_ADDRESS +#endif + +/*!< ADC input pins. */ +static const hal_ll_adc_pin_map_t _adc_map[] = +{ + #ifdef ADC1_PA0_CH1 + {PA0, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_1}, + #endif + #ifdef ADC1_PA1_CH2 + {PA1, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_2}, + #endif + #ifdef ADC1_PA2_CH3 + {PA2, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_3}, + #endif + #ifdef ADC1_PA3_CH4 + {PA3, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_4}, + #endif + #ifdef ADC1_PB0_CH15 + {PB0, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_15}, + #endif + #ifdef ADC1_PF0_CH10 + {PF0, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_10}, + #endif + #ifdef ADC2_PA0_CH1 + {PA0, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_1}, + #endif + #ifdef ADC2_PA1_CH2 + {PA1, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_2}, + #endif + #ifdef ADC2_PA4_CH17 + {PA4, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_17}, + #endif + #ifdef ADC2_PA5_CH13 + {PA5, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_13}, + #endif + #ifdef ADC2_PA6_CH3 + {PA6, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_3}, + #endif + #ifdef ADC2_PA7_CH4 + {PA7, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_4}, + #endif + #ifdef ADC2_PF1_CH10 + {PF1, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_10}, + #endif + #ifdef ADC3_PB0_CH12 + {PB0, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_12}, + #endif + #ifdef ADC1_PB11_CH14 + {PB11, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_14}, + #endif + #ifdef ADC1_PB12_CH11 + {PB12, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_11}, + #endif + #ifdef ADC1_PB14_CH5 + {PB14, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_5}, + #endif + #ifdef ADC1_PB1_CH12 + {PB1, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_12}, + #endif + #ifdef ADC1_PC0_CH6 + {PC0, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_6}, + #endif + #ifdef ADC1_PC1_CH7 + {PC1, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_7}, + #endif + #ifdef ADC1_PC2_CH8 + {PC2, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_8}, + #endif + #ifdef ADC1_PC3_CH9 + {PC3, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_9}, + #endif + #ifdef ADC2_PB11_CH14 + {PB11, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_14}, + #endif + #ifdef ADC2_PB15_CH15 + {PB15, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_15}, + #endif + #ifdef ADC2_PB2_CH12 + {PB2, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_12}, + #endif + #ifdef ADC2_PC0_CH6 + {PC0, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_6}, + #endif + #ifdef ADC2_PC1_CH7 + {PC1, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_7}, + #endif + #ifdef ADC2_PC2_CH8 + {PC2, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_8}, + #endif + #ifdef ADC2_PC3_CH9 + {PC3, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_9}, + #endif + #ifdef ADC2_PC4_CH5 + {PC4, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_5}, + #endif + #ifdef ADC2_PC5_CH11 + {PC5, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_11}, + #endif + #ifdef ADC3_PB13_CH5 + {PB13, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_5}, + #endif + #ifdef ADC3_PB1_CH1 + {PB1, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_1}, + #endif + #ifdef ADC3_PD10_CH7 + {PD10, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_7}, + #endif + #ifdef ADC3_PE10_CH14 + {PE10, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_14}, + #endif + #ifdef ADC3_PE11_CH15 + {PE11, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_15}, + #endif + #ifdef ADC3_PE12_CH16 + {PE12, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_16}, + #endif + #ifdef ADC3_PE13_CH3 + {PE13, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_3}, + #endif + #ifdef ADC3_PE7_CH4 + {PE7, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_4}, + #endif + #ifdef ADC3_PE8_CH6 + {PE8, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_6}, + #endif + #ifdef ADC3_PE9_CH2 + {PE9, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_2}, + #endif + #ifdef ADC3_PD11_CH8 + {PD11, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_8}, + #endif + #ifdef ADC3_PD12_CH9 + {PD12, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_9}, + #endif + #ifdef ADC3_PD13_CH10 + {PD13, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_10}, + #endif + #ifdef ADC3_PD14_CH11 + {PD14, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_11}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_CHANNEL_ERROR} +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_ADC_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/adc/hal_ll_adc_pin_map/implementations/doc_ds_89/hal_ll_adc_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/adc/hal_ll_adc_pin_map/implementations/doc_ds_89/hal_ll_adc_pin_map.h new file mode 100644 index 000000000..d98428706 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/adc/hal_ll_adc_pin_map/implementations/doc_ds_89/hal_ll_adc_pin_map.h @@ -0,0 +1,271 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_adc_pin_map.h + * @brief Header file containing symbolic pin name definitions. + */ + +#ifndef _HAL_LL_ADC_PIN_MAP_H_ +#define _HAL_LL_ADC_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_adc_module_num(_module_num) (_module_num - 1) + +/** + * ADC channels. + */ +typedef enum +{ + HAL_LL_ADC_CHANNEL_0 = 0, + HAL_LL_ADC_CHANNEL_1, + HAL_LL_ADC_CHANNEL_2, + HAL_LL_ADC_CHANNEL_3, + HAL_LL_ADC_CHANNEL_4, + HAL_LL_ADC_CHANNEL_5, + HAL_LL_ADC_CHANNEL_6, + HAL_LL_ADC_CHANNEL_7, + HAL_LL_ADC_CHANNEL_8, + HAL_LL_ADC_CHANNEL_9, + HAL_LL_ADC_CHANNEL_10, + HAL_LL_ADC_CHANNEL_11, + HAL_LL_ADC_CHANNEL_12, + HAL_LL_ADC_CHANNEL_13, + HAL_LL_ADC_CHANNEL_14, + HAL_LL_ADC_CHANNEL_15, + HAL_LL_ADC_CHANNEL_16, + HAL_LL_ADC_CHANNEL_17, + HAL_LL_ADC_CHANNEL_18, + HAL_LL_ADC_CHANNEL_19, + HAL_LL_ADC_CHANNEL_20, + HAL_LL_ADC_CHANNEL_21, + HAL_LL_ADC_CHANNEL_22, + HAL_LL_ADC_CHANNEL_23, + HAL_LL_ADC_CHANNEL_24, + HAL_LL_ADC_CHANNEL_25, + HAL_LL_ADC_CHANNEL_26, + HAL_LL_ADC_CHANNEL_27, + HAL_LL_ADC_CHANNEL_28, + HAL_LL_ADC_CHANNEL_29, + HAL_LL_ADC_CHANNEL_30, + HAL_LL_ADC_CHANNEL_31, + + HAL_LL_ADC_CHANNEL_NC = 0xFFFF +} hal_ll_adc_channel_t; + +/*!< @brief ADC pin structure. */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + hal_ll_adc_channel_t channel; +} hal_ll_adc_pin_map_t; + +#ifdef ADC_MODULE_1 +#define ADC1_BASE_ADDRESS (0x50000000UL) +#define ADC1_BASE_ADDR ADC1_BASE_ADDRESS +#define HAL_LL_ADC1_BASE_ADDR ADC1_BASE_ADDRESS +#define HAL_LL_ADC1_BASE_ADDRESS ADC1_BASE_ADDRESS +#endif +#ifdef ADC_MODULE_2 +#define ADC2_BASE_ADDRESS (0x50000100UL) +#define ADC2_BASE_ADDR ADC2_BASE_ADDRESS +#define HAL_LL_ADC2_BASE_ADDR ADC2_BASE_ADDRESS +#define HAL_LL_ADC2_BASE_ADDRESS ADC2_BASE_ADDRESS +#endif +#ifdef ADC_MODULE_3 +#define ADC3_BASE_ADDRESS (0x50000400UL) +#define ADC3_BASE_ADDR ADC3_BASE_ADDRESS +#define HAL_LL_ADC3_BASE_ADDR ADC3_BASE_ADDRESS +#define HAL_LL_ADC3_BASE_ADDRESS ADC3_BASE_ADDRESS +#endif + +/*!< ADC input pins. */ +static const hal_ll_adc_pin_map_t _adc_map[] = +{ + #ifdef ADC1_PA0_CH1 + {PA0, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_1}, + #endif + #ifdef ADC1_PA1_CH2 + {PA1, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_2}, + #endif + #ifdef ADC1_PA2_CH3 + {PA2, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_3}, + #endif + #ifdef ADC1_PA3_CH4 + {PA3, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_4}, + #endif + #ifdef ADC1_PB0_CH15 + {PB0, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_15}, + #endif + #ifdef ADC1_PB11_CH14 + {PB11, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_14}, + #endif + #ifdef ADC1_PB12_CH11 + {PB12, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_11}, + #endif + #ifdef ADC1_PB14_CH5 + {PB14, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_5}, + #endif + #ifdef ADC1_PB1_CH12 + {PB1, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_12}, + #endif + #ifdef ADC1_PC0_CH6 + {PC0, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_6}, + #endif + #ifdef ADC1_PC1_CH7 + {PC1, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_7}, + #endif + #ifdef ADC1_PC2_CH8 + {PC2, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_8}, + #endif + #ifdef ADC1_PC3_CH9 + {PC3, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_9}, + #endif + #ifdef ADC1_PF0_CH10 + {PF0, ADC1_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_10}, + #endif + #ifdef ADC2_PA0_CH1 + {PA0, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_1}, + #endif + #ifdef ADC2_PA1_CH2 + {PA1, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_2}, + #endif + #ifdef ADC2_PA4_CH17 + {PA4, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_17}, + #endif + #ifdef ADC2_PA5_CH13 + {PA5, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_13}, + #endif + #ifdef ADC2_PA6_CH3 + {PA6, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_3}, + #endif + #ifdef ADC2_PA7_CH4 + {PA7, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_4}, + #endif + #ifdef ADC2_PB11_CH14 + {PB11, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_14}, + #endif + #ifdef ADC2_PB15_CH15 + {PB15, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_15}, + #endif + #ifdef ADC2_PB2_CH12 + {PB2, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_12}, + #endif + #ifdef ADC2_PC0_CH6 + {PC0, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_6}, + #endif + #ifdef ADC2_PC1_CH7 + {PC1, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_7}, + #endif + #ifdef ADC2_PC2_CH8 + {PC2, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_8}, + #endif + #ifdef ADC2_PC3_CH9 + {PC3, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_9}, + #endif + #ifdef ADC2_PC4_CH5 + {PC4, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_5}, + #endif + #ifdef ADC2_PC5_CH11 + {PC5, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_11}, + #endif + #ifdef ADC2_PF1_CH10 + {PF1, ADC2_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_ADC_CHANNEL_10}, + #endif + #ifdef ADC3_PB0_CH12 + {PB0, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_12}, + #endif + #ifdef ADC3_PB13_CH5 + {PB13, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_5}, + #endif + #ifdef ADC3_PB1_CH1 + {PB1, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_1}, + #endif + #ifdef ADC3_PD10_CH7 + {PD10, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_7}, + #endif + #ifdef ADC3_PE10_CH14 + {PE10, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_14}, + #endif + #ifdef ADC3_PE11_CH15 + {PE11, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_15}, + #endif + #ifdef ADC3_PE12_CH16 + {PE12, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_16}, + #endif + #ifdef ADC3_PE13_CH3 + {PE13, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_3}, + #endif + #ifdef ADC3_PE7_CH4 + {PE7, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_4}, + #endif + #ifdef ADC3_PE8_CH6 + {PE8, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_6}, + #endif + #ifdef ADC3_PE9_CH2 + {PE9, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_2}, + #endif + #ifdef ADC3_PD11_CH8 + {PD11, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_8}, + #endif + #ifdef ADC3_PD12_CH9 + {PD12, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_9}, + #endif + #ifdef ADC3_PD13_CH10 + {PD13, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_10}, + #endif + #ifdef ADC3_PD14_CH11 + {PD14, ADC3_BASE_ADDRESS, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_ADC_CHANNEL_11}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_CHANNEL_ERROR} +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_ADC_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/can/hal_ll_can.h b/targets/arm/mikroe/ai_generated/stm32/include/can/hal_ll_can.h new file mode 100644 index 000000000..f277c0d38 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/can/hal_ll_can.h @@ -0,0 +1,420 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_can.h + * @brief API for CAN HAL LOW LEVEL layer. + */ + +#ifndef _HAL_LL_CAN_H_ +#define _HAL_LL_CAN_H_ + +#include "hal_ll_target.h" + +#ifdef __cplusplus +extern "C"{ +#endif + +/** + * @brief CAN low level pins config structure. + * + * The context structure for storing low level pin configuration + * for both TX and RX pins. + * + */ +typedef struct +{ + hal_ll_pin_af_t tx_pin; /*!< TX CAN pin. */ + hal_ll_pin_af_t rx_pin; /*!< RX CAN pin. */ +} hal_ll_can_pins_t; + +/** + * @details CAN modes. + */ +typedef enum +{ + /* Universal Modes. */ + HAL_LL_CAN_MODE_NORMAL = 0, /*!< Mode for normal operation. */ + HAL_LL_CAN_MODE_LOOPBACK, /*!< Mode for testing communication internally with sending TX data frames to other nodes. */ + HAL_LL_CAN_MODE_DISABLE, /*!< Mode for ignoring TX and RX data frames. */ + /* STM32 and RISC-V Modes. */ + HAL_LL_CAN_MODE_SILENT, /*!< Mode for only receiving messages. */ + HAL_LL_CAN_MODE_LOOPBACK_SILENT, /*!< Mode for testing communication internally without sending TX data frames to other nodes. */ + /* NXP Modes. */ + HAL_LL_CAN_MODE_LISTENONLY, /*!< Mode for only receiving messages. */ + HAL_LL_CAN_MODE_DOZE, /*!< Mode for acknowledging system low-power mode. */ + HAL_LL_CAN_MODE_STOP, /*!< Mode for acknowledging system clock stop. */ + HAL_LL_CAN_MODE_FREEZE, /*!< Mode for ignoring TX and RX data frames. */ + /* dsPIC Modes. */ + HAL_LL_CAN_MODE_LISTENALL /*!< Mode for receiving data frames without filter configs. */ +} hal_ll_can_mode_t; + +/** + * @details CAN data frame formats. + */ +typedef enum +{ + HAL_LL_CAN_FRAME_FORMAT_STANDARD_11BITS = 0, /*!< Standard format identifier. */ + HAL_LL_CAN_FRAME_FORMAT_EXTENDED_29BITS /*!< Extended format identifier. */ +} hal_ll_can_frame_format_t; + +/** + * @details CAN data frame types. + */ +typedef enum +{ + HAL_LL_CAN_FRAME_TYPE_DATA = 0, /*!< Data frame. */ + HAL_LL_CAN_FRAME_TYPE_RTR /*!< Remote frame. */ +} hal_ll_can_frame_type_t; + +/** + * @details CAN filter mode. + */ +typedef enum +{ + HAL_LL_CAN_FILTER_MODE_IDMASK = 0, /*!< Identifier mask mode. */ + HAL_LL_CAN_FILTER_MODE_IDLIST /*!< Identifier list mode. */ +} hal_ll_can_filter_mode_t; + +/** + * @details CAN filter scale. + */ +typedef enum +{ + HAL_LL_CAN_FILTER_SCALE_16BIT = 0, /*!< Two 16-bit filters. */ + HAL_LL_CAN_FILTER_SCALE_32BIT /*!< One 32-bit filter. */ +} hal_ll_can_filter_scale_t; + +/** + * @details CAN filter FIFO. + */ +typedef enum +{ + HAL_LL_CAN_FILTER_FIFO0 = 0, /*!< Filter mapped to FIFO0. */ + HAL_LL_CAN_FILTER_FIFO1, /*!< Filter mapped to FIFO1. */ + HAL_LL_CAN_FILTER_FIFO2, /*!< Filter mapped to FIFO2. */ + HAL_LL_CAN_FILTER_FIFO3, /*!< Filter mapped to FIFO3. */ + HAL_LL_CAN_FILTER_FIFO4, /*!< Filter mapped to FIFO4. */ + HAL_LL_CAN_FILTER_FIFO5, /*!< Filter mapped to FIFO5. */ + HAL_LL_CAN_FILTER_FIFO6, /*!< Filter mapped to FIFO6. */ + HAL_LL_CAN_FILTER_FIFO7, /*!< Filter mapped to FIFO7. */ + HAL_LL_CAN_FILTER_FIFO8, /*!< Filter mapped to FIFO8. */ + HAL_LL_CAN_FILTER_FIFO9, /*!< Filter mapped to FIFO9. */ + HAL_LL_CAN_FILTER_FIFO10, /*!< Filter mapped to FIFO10. */ + HAL_LL_CAN_FILTER_FIFO11, /*!< Filter mapped to FIFO11. */ + HAL_LL_CAN_FILTER_FIFO12, /*!< Filter mapped to FIFO12. */ + HAL_LL_CAN_FILTER_FIFO13, /*!< Filter mapped to FIFO13. */ + HAL_LL_CAN_FILTER_FIFO14, /*!< Filter mapped to FIFO14. */ + HAL_LL_CAN_FILTER_FIFO15, /*!< Filter mapped to FIFO15. */ + HAL_LL_CAN_FILTER_FIFO16, /*!< Filter mapped to FIFO16. */ + HAL_LL_CAN_FILTER_FIFO17, /*!< Filter mapped to FIFO17. */ + HAL_LL_CAN_FILTER_FIFO18, /*!< Filter mapped to FIFO18. */ + HAL_LL_CAN_FILTER_FIFO19, /*!< Filter mapped to FIFO19. */ + HAL_LL_CAN_FILTER_FIFO20, /*!< Filter mapped to FIFO20. */ + HAL_LL_CAN_FILTER_FIFO21, /*!< Filter mapped to FIFO21. */ + HAL_LL_CAN_FILTER_FIFO22, /*!< Filter mapped to FIFO22. */ + HAL_LL_CAN_FILTER_FIFO23, /*!< Filter mapped to FIFO23. */ + HAL_LL_CAN_FILTER_FIFO24, /*!< Filter mapped to FIFO24. */ + HAL_LL_CAN_FILTER_FIFO25, /*!< Filter mapped to FIFO25. */ + HAL_LL_CAN_FILTER_FIFO26, /*!< Filter mapped to FIFO26. */ + HAL_LL_CAN_FILTER_FIFO27, /*!< Filter mapped to FIFO27. */ + HAL_LL_CAN_FILTER_FIFO28, /*!< Filter mapped to FIFO28. */ + HAL_LL_CAN_FILTER_FIFO29, /*!< Filter mapped to FIFO29. */ + HAL_LL_CAN_FILTER_FIFO30, /*!< Filter mapped to FIFO30. */ + HAL_LL_CAN_FILTER_FIFO31 /*!< Filter mapped to FIFO31. */ +} hal_ll_can_filter_fifo_t; + +/** + * @details CAN filter activation. + */ +typedef enum +{ + HAL_LL_CAN_FILTER_DISABLE = 0, /*!< CAN filter disable. */ + HAL_LL_CAN_FILTER_ENABLE /*!< CAN filter enable. */ +} hal_ll_can_filter_activation_t; + +/** + * @details CAN filter config structure. + */ +typedef struct +{ + union { + struct { + uint16_t can_filter_id_low; /*!< 16-bit Filter ID. */ + uint16_t can_filter_id_high; /*!< 16-bit Filter ID. */ + }; + uint32_t can_filter_id; /*!< 32-bit Filter ID. */ + }; + union { + struct { + uint16_t can_filter_mask_id_low; /*!< 16-bit Filter ID or Filter Mask. */ + uint16_t can_filter_mask_id_high; /*!< 16-bit Filter ID or Filter Mask. */ + }; + uint32_t can_filter_mask_id; /*!< 32-bit Filter ID or Filter Mask. */ + }; + uint8_t can_filter_bank; /*!< Filter bank. */ + hal_ll_can_frame_type_t can_filter_frame_type[4]; /*!< Type of frame, data or remote. */ + hal_ll_can_filter_activation_t can_filter_enable; /*!< Filter activation status. */ + hal_ll_can_filter_mode_t can_filter_mode; /*!< Filter mode. */ + hal_ll_can_filter_scale_t can_filter_scale; /*!< Filter scale. */ + hal_ll_can_filter_fifo_t can_filter_fifo; /*!< Filter-to-FIFO mapping. */ +} hal_ll_can_filter_config_t; + +/** + * @details CAN module config structure. + */ +typedef struct +{ + hal_ll_pin_name_t tx_pin; /*!< Tx pin. */ + hal_ll_pin_name_t rx_pin; /*!< Rx pin. */ + hal_ll_can_mode_t mode; /*!< CAN mode. */ + uint32_t frequency; /*!< CAN frequency. */ +} hal_ll_can_config_t; + +/** + * @details Message structure. + */ +typedef struct +{ + union { + struct { + uint16_t std_id; /*!< Standard format frame identifier. */ + uint16_t ext_id; /*!< Extended format frame identifier. */ + }; + uint32_t id; + }; + hal_ll_can_frame_format_t frame_format; /*!< Format of frame, standard or extended format. */ + hal_ll_can_frame_type_t frame_type; /*!< Type of frame, data or remote. */ + uint8_t data_len; /*!< Data length. */ + uint8_t message_data[8]; /*!< Data. */ +} hal_ll_can_message_t; + +/** + * @details CAN HAL low level transmit message structure. + */ +typedef struct +{ + hal_ll_can_message_t message; /* CAN message structure. */ +} hal_ll_can_transmit_message_struct; + +/** + * @details CAN HAL low level receive message structure. + */ +typedef struct +{ + hal_ll_can_message_t message; /* CAN message structure. */ + uint8_t rx_fifo_number; /* Receive FIFO number. */ +} hal_ll_can_receive_message_struct; + +/** + * @brief CAN low level handle. + * + * The context for storing low level object handler. + * User is not to change these values or unexpected behaviour + * may occur. + */ +typedef struct +{ + handle_t *hal_ll_can_handle; /*!< CAN HAL low level handle */ + handle_t *hal_drv_can_handle; /*!< CAN DRV level handle */ + bool init_ll_state; /*!< CAN HAL low level object init state */ +} hal_ll_can_handle_register_t; + +/** + * @brief Registers handler for future use. + * + * Registers low level and hal level handlers + * for use with appropriate functions. + * + * @param[in] tx_pin CAN TX pin. + * @param[in] rx_pin CAN RX pin. + * @param[in] *handle_map HAL layer local handle map. + * @param[in] *hal_module_id HAL layer module number. + + * @return hal_ll_err_t Module specific error. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_can_register_handle( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, + hal_ll_can_handle_register_t *handle_map, uint8_t *hal_module_id ); + +/** + * @brief Initializes specified module. + * + * Performs module configuration on the hardware + * level. Enables module specific clock gate and + * sets adequate alternate function values. + * + * @param[in] handle HAL context object handle. + * @param[in] config HAL low level config structure. + * @param[in] filter_config HAL low level filter config structure. + * + * @return hal_ll_err_t Module specific error. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_can_init( handle_t *handle, hal_ll_can_config_t *config, + hal_ll_can_filter_config_t *filter_config ); + +/** + * @brief Sets filter parameters. + * + * Initializes module with specified filter parameters. + * + * @param[in] handle HAL context object handle. + * @param[in] config HAL low level config structure. + * @param[in] filter_config HAL low level filter config structure. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_can_set_filter( handle_t *handle, hal_ll_can_config_t *config, + hal_ll_can_filter_config_t *filter_config ); + +/** + * @brief Sets adequate bit timing parameters for desired frequency. + * + * @note: Setting parameters that result in a baud rate that + * differs from the desired value is not acceptable. + * If two devices communicate over CAN, their baud + * rates need to be exactly the same. + * + * @param[in] handle HAL context object handle. + * @param[in] config HAL low level config structure. + * @param[in] filter_config HAL low level filter config structure. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_can_set_frequency( handle_t *handle, hal_ll_can_config_t *config, + hal_ll_can_filter_config_t *filter_config ); + +/** + * @brief Gets CAN frequency. + * + * Gets the currently configured CAN frequency. + * + * @param[in] handle HAL context object handle. + * + * Returns CAN frequency. + */ +hal_ll_err_t hal_ll_can_get_frequency( handle_t *handle ); + +/** + * @brief Sets desired CAN operating mode. + * + * Initializes module with specified CAN mode. + * + * @param[in] handle HAL context object handle. + * @param[in] config HAL low level config structure. + * @param[in] filter_config HAL low level filter config structure. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_can_set_mode( handle_t *handle, hal_ll_can_config_t *config, + hal_ll_can_filter_config_t *filter_config ); + +/** + * @brief Gets CAN mode. + * + * Gets the currently configured CAN mode. + * + * @param[in] handle HAL context object handle. + * + * Returns CAN mode. + */ +hal_ll_err_t hal_ll_can_get_mode( handle_t *handle ); + +/** + * @brief Performs transmit operation. + * + * Accesses hardware transmit registers and + * writes parameters and data directly to them. + * + * @param[in] handle HAL context object handle. + * @param[in] transmit_message Transmit message structure. + * + * @return one of pre-defined values. + */ +hal_ll_err_t hal_ll_can_transmit( handle_t *handle, hal_ll_can_transmit_message_struct *transmit_message ); + +/** + * @brief Stops transmit operation. + * + * Accesses hardware transmit registers and stops data transmission. + * + * @param[in] handle HAL context object handle. + * + * @return void None. + */ +void hal_ll_can_transmission_stop( handle_t *handle ); + +/** + * @brief Performs receive operation. + * + * Accesses hardware receive registers and + * reads parameters and data directly from them. + * + * @param[in] handle HAL context object handle. + * @param[in] receive_message Receive message structure. + * + * Returns one of pre-defined values. + */ +hal_ll_err_t hal_ll_can_receive( handle_t *handle, hal_ll_can_receive_message_struct *receive_message ); + +/** + * @brief Closes CAN HAL and HAL_LOW_LEVEL context object. + * + * De-allocates hardware resources for specific driver object and + * de-initializes the module on a hardware level. + * + * @param[in] *handle HAL context object handle. + * + * Returns one of pre-defined values. + */ +hal_ll_err_t hal_ll_can_close( handle_t *handle ); + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_CAN_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/can/hal_ll_can_pin_map/implementations/.gitkeep b/targets/arm/mikroe/ai_generated/stm32/include/can/hal_ll_can_pin_map/implementations/.gitkeep new file mode 100644 index 000000000..e69de29bb diff --git a/targets/arm/mikroe/ai_generated/stm32/include/can/hal_ll_can_pin_map/implementations/doc_ds_160/hal_ll_can_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/can/hal_ll_can_pin_map/implementations/doc_ds_160/hal_ll_can_pin_map.h new file mode 100644 index 000000000..860dbb77f --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/can/hal_ll_can_pin_map/implementations/doc_ds_160/hal_ll_can_pin_map.h @@ -0,0 +1,114 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_can_pin_map.h + * @brief CAN HAL LOW LEVEL PIN MAPS. + */ + +#ifndef _HAL_LL_CAN_PIN_MAP_H_ +#define _HAL_LL_CAN_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_can_module_num(_module_num) (_module_num - 1) +#define hal_ll_fdcan_module_num(_module_num) hal_ll_can_module_num(_module_num) + +/*!< @brief Pin structure */ +typedef struct +{ + uint8_t module_index; + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + uint32_t af; +} hal_ll_can_pin_map_t; + +#ifdef CAN_MODULE_1 +#define CAN1_BASE_ADDRESS (0x40006400UL) +#define CAN1_BASE_ADDR CAN1_BASE_ADDRESS +#define HAL_LL_CAN1_BASE_ADDR CAN1_BASE_ADDRESS +#define HAL_LL_CAN1_BASE_ADDRESS CAN1_BASE_ADDRESS +#endif + +/*!< @brief CAN RX pins */ +static const hal_ll_can_pin_map_t hal_ll_can_rx_map[] = +{ + #ifdef CAN1_RX_PA11_AF9 + {hal_ll_can_module_num(CAN_MODULE_1), PA11, CAN1_BASE_ADDRESS, 9}, + #endif + #ifdef CAN1_RX_PB8_AF9 + {hal_ll_can_module_num(CAN_MODULE_1), PB8, CAN1_BASE_ADDRESS, 9}, + #endif + #ifdef CAN1_RX_PD0_AF9 + {hal_ll_can_module_num(CAN_MODULE_1), PD0, CAN1_BASE_ADDRESS, 9}, + #endif + #ifdef CAN1_RX_PI9_AF9 + {hal_ll_can_module_num(CAN_MODULE_1), PI9, CAN1_BASE_ADDRESS, 9}, + #endif + {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} +}; + +/*!< @brief CAN TX pins */ +static const hal_ll_can_pin_map_t hal_ll_can_tx_map[] = +{ + #ifdef CAN1_TX_PA12_AF9 + {hal_ll_can_module_num(CAN_MODULE_1), PA12, CAN1_BASE_ADDRESS, 9}, + #endif + #ifdef CAN1_TX_PB9_AF9 + {hal_ll_can_module_num(CAN_MODULE_1), PB9, CAN1_BASE_ADDRESS, 9}, + #endif + #ifdef CAN1_TX_PD1_AF9 + {hal_ll_can_module_num(CAN_MODULE_1), PD1, CAN1_BASE_ADDRESS, 9}, + #endif + #ifdef CAN1_TX_PH13_AF9 + {hal_ll_can_module_num(CAN_MODULE_1), PH13, CAN1_BASE_ADDRESS, 9}, + #endif + {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_CAN_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/can/hal_ll_can_pin_map/implementations/doc_ds_161/hal_ll_can_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/can/hal_ll_can_pin_map/implementations/doc_ds_161/hal_ll_can_pin_map.h new file mode 100644 index 000000000..860dbb77f --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/can/hal_ll_can_pin_map/implementations/doc_ds_161/hal_ll_can_pin_map.h @@ -0,0 +1,114 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_can_pin_map.h + * @brief CAN HAL LOW LEVEL PIN MAPS. + */ + +#ifndef _HAL_LL_CAN_PIN_MAP_H_ +#define _HAL_LL_CAN_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_can_module_num(_module_num) (_module_num - 1) +#define hal_ll_fdcan_module_num(_module_num) hal_ll_can_module_num(_module_num) + +/*!< @brief Pin structure */ +typedef struct +{ + uint8_t module_index; + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + uint32_t af; +} hal_ll_can_pin_map_t; + +#ifdef CAN_MODULE_1 +#define CAN1_BASE_ADDRESS (0x40006400UL) +#define CAN1_BASE_ADDR CAN1_BASE_ADDRESS +#define HAL_LL_CAN1_BASE_ADDR CAN1_BASE_ADDRESS +#define HAL_LL_CAN1_BASE_ADDRESS CAN1_BASE_ADDRESS +#endif + +/*!< @brief CAN RX pins */ +static const hal_ll_can_pin_map_t hal_ll_can_rx_map[] = +{ + #ifdef CAN1_RX_PA11_AF9 + {hal_ll_can_module_num(CAN_MODULE_1), PA11, CAN1_BASE_ADDRESS, 9}, + #endif + #ifdef CAN1_RX_PB8_AF9 + {hal_ll_can_module_num(CAN_MODULE_1), PB8, CAN1_BASE_ADDRESS, 9}, + #endif + #ifdef CAN1_RX_PD0_AF9 + {hal_ll_can_module_num(CAN_MODULE_1), PD0, CAN1_BASE_ADDRESS, 9}, + #endif + #ifdef CAN1_RX_PI9_AF9 + {hal_ll_can_module_num(CAN_MODULE_1), PI9, CAN1_BASE_ADDRESS, 9}, + #endif + {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} +}; + +/*!< @brief CAN TX pins */ +static const hal_ll_can_pin_map_t hal_ll_can_tx_map[] = +{ + #ifdef CAN1_TX_PA12_AF9 + {hal_ll_can_module_num(CAN_MODULE_1), PA12, CAN1_BASE_ADDRESS, 9}, + #endif + #ifdef CAN1_TX_PB9_AF9 + {hal_ll_can_module_num(CAN_MODULE_1), PB9, CAN1_BASE_ADDRESS, 9}, + #endif + #ifdef CAN1_TX_PD1_AF9 + {hal_ll_can_module_num(CAN_MODULE_1), PD1, CAN1_BASE_ADDRESS, 9}, + #endif + #ifdef CAN1_TX_PH13_AF9 + {hal_ll_can_module_num(CAN_MODULE_1), PH13, CAN1_BASE_ADDRESS, 9}, + #endif + {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_CAN_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/can/hal_ll_can_pin_map/implementations/doc_ds_80/hal_ll_can_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/can/hal_ll_can_pin_map/implementations/doc_ds_80/hal_ll_can_pin_map.h new file mode 100644 index 000000000..2624ea593 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/can/hal_ll_can_pin_map/implementations/doc_ds_80/hal_ll_can_pin_map.h @@ -0,0 +1,145 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_can_pin_map.h + * @brief CAN HAL LOW LEVEL PIN MAPS. + */ + +#ifndef _HAL_LL_CAN_PIN_MAP_H_ +#define _HAL_LL_CAN_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_can_module_num(_module_num) (_module_num - 1) +#define hal_ll_fdcan_module_num(_module_num) hal_ll_can_module_num(_module_num) + +/*!< @brief Pin structure */ +typedef struct +{ + uint8_t module_index; + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + uint32_t af; +} hal_ll_can_pin_map_t; + +REPLACE_MODULE_MACROS + +/*!< @brief CAN RX pins */ +static const hal_ll_can_pin_map_t hal_ll_can_rx_map[] = +{ + #ifdef FDCAN1_RX_PA11_AF3 + {hal_ll_fdcan_module_num(FDCAN_MODULE_1), PA11, FDCAN1_BASE_ADDRESS, 3}, + #endif + #ifdef FDCAN1_RX_PB8_AF3 + {hal_ll_fdcan_module_num(FDCAN_MODULE_1), PB8, FDCAN1_BASE_ADDRESS, 3}, + #endif + #ifdef FDCAN1_RX_PC4_AF3 + {hal_ll_fdcan_module_num(FDCAN_MODULE_1), PC4, FDCAN1_BASE_ADDRESS, 3}, + #endif + #ifdef FDCAN1_RX_PD0_AF3 + {hal_ll_fdcan_module_num(FDCAN_MODULE_1), PD0, FDCAN1_BASE_ADDRESS, 3}, + #endif + #ifdef FDCAN1_RX_PD12_AF3 + {hal_ll_fdcan_module_num(FDCAN_MODULE_1), PD12, FDCAN1_BASE_ADDRESS, 3}, + #endif + #ifdef FDCAN2_RX_PB0_AF3 + {hal_ll_fdcan_module_num(FDCAN_MODULE_2), PB0, FDCAN2_BASE_ADDRESS, 3}, + #endif + #ifdef FDCAN2_RX_PB12_AF3 + {hal_ll_fdcan_module_num(FDCAN_MODULE_2), PB12, FDCAN2_BASE_ADDRESS, 3}, + #endif + #ifdef FDCAN2_RX_PB5_AF3 + {hal_ll_fdcan_module_num(FDCAN_MODULE_2), PB5, FDCAN2_BASE_ADDRESS, 3}, + #endif + #ifdef FDCAN2_RX_PC2_AF3 + {hal_ll_fdcan_module_num(FDCAN_MODULE_2), PC2, FDCAN2_BASE_ADDRESS, 3}, + #endif + #ifdef FDCAN2_RX_PD14_AF3 + {hal_ll_fdcan_module_num(FDCAN_MODULE_2), PD14, FDCAN2_BASE_ADDRESS, 3}, + #endif + {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} +}; + +/*!< @brief CAN TX pins */ +static const hal_ll_can_pin_map_t hal_ll_can_tx_map[] = +{ + #ifdef FDCAN1_TX_PA12_AF3 + {hal_ll_fdcan_module_num(FDCAN_MODULE_1), PA12, FDCAN1_BASE_ADDRESS, 3}, + #endif + #ifdef FDCAN1_TX_PB9_AF3 + {hal_ll_fdcan_module_num(FDCAN_MODULE_1), PB9, FDCAN1_BASE_ADDRESS, 3}, + #endif + #ifdef FDCAN1_TX_PC5_AF3 + {hal_ll_fdcan_module_num(FDCAN_MODULE_1), PC5, FDCAN1_BASE_ADDRESS, 3}, + #endif + #ifdef FDCAN1_TX_PD13_AF3 + {hal_ll_fdcan_module_num(FDCAN_MODULE_1), PD13, FDCAN1_BASE_ADDRESS, 3}, + #endif + #ifdef FDCAN1_TX_PD1_AF3 + {hal_ll_fdcan_module_num(FDCAN_MODULE_1), PD1, FDCAN1_BASE_ADDRESS, 3}, + #endif + #ifdef FDCAN2_TX_PB13_AF3 + {hal_ll_fdcan_module_num(FDCAN_MODULE_2), PB13, FDCAN2_BASE_ADDRESS, 3}, + #endif + #ifdef FDCAN2_TX_PB1_AF3 + {hal_ll_fdcan_module_num(FDCAN_MODULE_2), PB1, FDCAN2_BASE_ADDRESS, 3}, + #endif + #ifdef FDCAN2_TX_PB6_AF3 + {hal_ll_fdcan_module_num(FDCAN_MODULE_2), PB6, FDCAN2_BASE_ADDRESS, 3}, + #endif + #ifdef FDCAN2_TX_PC3_AF3 + {hal_ll_fdcan_module_num(FDCAN_MODULE_2), PC3, FDCAN2_BASE_ADDRESS, 3}, + #endif + #ifdef FDCAN2_TX_PD15_AF3 + {hal_ll_fdcan_module_num(FDCAN_MODULE_2), PD15, FDCAN2_BASE_ADDRESS, 3}, + #endif + {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_CAN_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/can/hal_ll_can_pin_map/implementations/doc_ds_81/hal_ll_can_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/can/hal_ll_can_pin_map/implementations/doc_ds_81/hal_ll_can_pin_map.h new file mode 100644 index 000000000..69b307d2b --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/can/hal_ll_can_pin_map/implementations/doc_ds_81/hal_ll_can_pin_map.h @@ -0,0 +1,145 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_can_pin_map.h + * @brief CAN HAL LOW LEVEL PIN MAPS. + */ + +#ifndef _HAL_LL_CAN_PIN_MAP_H_ +#define _HAL_LL_CAN_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_can_module_num(_module_num) (_module_num - 1) +#define hal_ll_fdcan_module_num(_module_num) hal_ll_can_module_num(_module_num) + +/*!< @brief Pin structure */ +typedef struct +{ + uint8_t module_index; + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + uint32_t af; +} hal_ll_can_pin_map_t; + +REPLACE_MODULE_MACROS + +/*!< @brief CAN RX pins */ +static const hal_ll_can_pin_map_t hal_ll_can_rx_map[] = +{ + #ifdef FDCAN1_RX_PA11_AF3 + {hal_ll_fdcan_module_num(FDCAN_MODULE_1), PA11, FDCAN1_BASE_ADDRESS, 3}, + #endif + #ifdef FDCAN1_RX_PB8_AF3 + {hal_ll_fdcan_module_num(FDCAN_MODULE_1), PB8, FDCAN1_BASE_ADDRESS, 3}, + #endif + #ifdef FDCAN1_RX_PD0_AF3 + {hal_ll_fdcan_module_num(FDCAN_MODULE_1), PD0, FDCAN1_BASE_ADDRESS, 3}, + #endif + #ifdef FDCAN2_RX_PB0_AF3 + {hal_ll_fdcan_module_num(FDCAN_MODULE_2), PB0, FDCAN2_BASE_ADDRESS, 3}, + #endif + #ifdef FDCAN2_RX_PB12_AF3 + {hal_ll_fdcan_module_num(FDCAN_MODULE_2), PB12, FDCAN2_BASE_ADDRESS, 3}, + #endif + #ifdef FDCAN2_RX_PB5_AF3 + {hal_ll_fdcan_module_num(FDCAN_MODULE_2), PB5, FDCAN2_BASE_ADDRESS, 3}, + #endif + #ifdef FDCAN1_RX_PC4_AF3 + {hal_ll_fdcan_module_num(FDCAN_MODULE_1), PC4, FDCAN1_BASE_ADDRESS, 3}, + #endif + #ifdef FDCAN2_RX_PC2_AF3 + {hal_ll_fdcan_module_num(FDCAN_MODULE_2), PC2, FDCAN2_BASE_ADDRESS, 3}, + #endif + #ifdef FDCAN1_RX_PD12_AF3 + {hal_ll_fdcan_module_num(FDCAN_MODULE_1), PD12, FDCAN1_BASE_ADDRESS, 3}, + #endif + #ifdef FDCAN2_RX_PD14_AF3 + {hal_ll_fdcan_module_num(FDCAN_MODULE_2), PD14, FDCAN2_BASE_ADDRESS, 3}, + #endif + {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} +}; + +/*!< @brief CAN TX pins */ +static const hal_ll_can_pin_map_t hal_ll_can_tx_map[] = +{ + #ifdef FDCAN1_TX_PA12_AF3 + {hal_ll_fdcan_module_num(FDCAN_MODULE_1), PA12, FDCAN1_BASE_ADDRESS, 3}, + #endif + #ifdef FDCAN1_TX_PB9_AF3 + {hal_ll_fdcan_module_num(FDCAN_MODULE_1), PB9, FDCAN1_BASE_ADDRESS, 3}, + #endif + #ifdef FDCAN1_TX_PD1_AF3 + {hal_ll_fdcan_module_num(FDCAN_MODULE_1), PD1, FDCAN1_BASE_ADDRESS, 3}, + #endif + #ifdef FDCAN2_TX_PB13_AF3 + {hal_ll_fdcan_module_num(FDCAN_MODULE_2), PB13, FDCAN2_BASE_ADDRESS, 3}, + #endif + #ifdef FDCAN2_TX_PB1_AF3 + {hal_ll_fdcan_module_num(FDCAN_MODULE_2), PB1, FDCAN2_BASE_ADDRESS, 3}, + #endif + #ifdef FDCAN2_TX_PB6_AF3 + {hal_ll_fdcan_module_num(FDCAN_MODULE_2), PB6, FDCAN2_BASE_ADDRESS, 3}, + #endif + #ifdef FDCAN1_TX_PC5_AF3 + {hal_ll_fdcan_module_num(FDCAN_MODULE_1), PC5, FDCAN1_BASE_ADDRESS, 3}, + #endif + #ifdef FDCAN2_TX_PC3_AF3 + {hal_ll_fdcan_module_num(FDCAN_MODULE_2), PC3, FDCAN2_BASE_ADDRESS, 3}, + #endif + #ifdef FDCAN1_TX_PD13_AF3 + {hal_ll_fdcan_module_num(FDCAN_MODULE_1), PD13, FDCAN1_BASE_ADDRESS, 3}, + #endif + #ifdef FDCAN2_TX_PD15_AF3 + {hal_ll_fdcan_module_num(FDCAN_MODULE_2), PD15, FDCAN2_BASE_ADDRESS, 3}, + #endif + {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_CAN_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/can/hal_ll_can_pin_map/implementations/doc_ds_82/hal_ll_can_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/can/hal_ll_can_pin_map/implementations/doc_ds_82/hal_ll_can_pin_map.h new file mode 100644 index 000000000..b01304f01 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/can/hal_ll_can_pin_map/implementations/doc_ds_82/hal_ll_can_pin_map.h @@ -0,0 +1,103 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_can_pin_map.h + * @brief CAN HAL LOW LEVEL PIN MAPS. + */ + +#ifndef _HAL_LL_CAN_PIN_MAP_H_ +#define _HAL_LL_CAN_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_can_module_num(_module_num) (_module_num - 1) +#define hal_ll_fdcan_module_num(_module_num) hal_ll_can_module_num(_module_num) + +/*!< @brief Pin structure */ +typedef struct +{ + uint8_t module_index; + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + uint32_t af; +} hal_ll_can_pin_map_t; + +REPLACE_MODULE_MACROS + +/*!< @brief CAN RX pins */ +static const hal_ll_can_pin_map_t hal_ll_can_rx_map[] = +{ + #ifdef FDCAN1_RX_PA11_AF9 + {hal_ll_fdcan_module_num(FDCAN_MODULE_1), PA11, FDCAN1_BASE_ADDRESS, 9}, + #endif + #ifdef FDCAN1_RX_PB8_AF9 + {hal_ll_fdcan_module_num(FDCAN_MODULE_1), PB8, FDCAN1_BASE_ADDRESS, 9}, + #endif + #ifdef FDCAN1_RX_PD0_AF9 + {hal_ll_fdcan_module_num(FDCAN_MODULE_1), PD0, FDCAN1_BASE_ADDRESS, 9}, + #endif + {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} +}; + +/*!< @brief CAN TX pins */ +static const hal_ll_can_pin_map_t hal_ll_can_tx_map[] = +{ + #ifdef FDCAN1_TX_PA12_AF9 + {hal_ll_fdcan_module_num(FDCAN_MODULE_1), PA12, FDCAN1_BASE_ADDRESS, 9}, + #endif + #ifdef FDCAN1_TX_PB9_AF9 + {hal_ll_fdcan_module_num(FDCAN_MODULE_1), PB9, FDCAN1_BASE_ADDRESS, 9}, + #endif + #ifdef FDCAN1_TX_PD1_AF9 + {hal_ll_fdcan_module_num(FDCAN_MODULE_1), PD1, FDCAN1_BASE_ADDRESS, 9}, + #endif + {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_CAN_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/can/hal_ll_can_pin_map/implementations/doc_ds_83/hal_ll_can_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/can/hal_ll_can_pin_map/implementations/doc_ds_83/hal_ll_can_pin_map.h new file mode 100644 index 000000000..b01304f01 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/can/hal_ll_can_pin_map/implementations/doc_ds_83/hal_ll_can_pin_map.h @@ -0,0 +1,103 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_can_pin_map.h + * @brief CAN HAL LOW LEVEL PIN MAPS. + */ + +#ifndef _HAL_LL_CAN_PIN_MAP_H_ +#define _HAL_LL_CAN_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_can_module_num(_module_num) (_module_num - 1) +#define hal_ll_fdcan_module_num(_module_num) hal_ll_can_module_num(_module_num) + +/*!< @brief Pin structure */ +typedef struct +{ + uint8_t module_index; + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + uint32_t af; +} hal_ll_can_pin_map_t; + +REPLACE_MODULE_MACROS + +/*!< @brief CAN RX pins */ +static const hal_ll_can_pin_map_t hal_ll_can_rx_map[] = +{ + #ifdef FDCAN1_RX_PA11_AF9 + {hal_ll_fdcan_module_num(FDCAN_MODULE_1), PA11, FDCAN1_BASE_ADDRESS, 9}, + #endif + #ifdef FDCAN1_RX_PB8_AF9 + {hal_ll_fdcan_module_num(FDCAN_MODULE_1), PB8, FDCAN1_BASE_ADDRESS, 9}, + #endif + #ifdef FDCAN1_RX_PD0_AF9 + {hal_ll_fdcan_module_num(FDCAN_MODULE_1), PD0, FDCAN1_BASE_ADDRESS, 9}, + #endif + {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} +}; + +/*!< @brief CAN TX pins */ +static const hal_ll_can_pin_map_t hal_ll_can_tx_map[] = +{ + #ifdef FDCAN1_TX_PA12_AF9 + {hal_ll_fdcan_module_num(FDCAN_MODULE_1), PA12, FDCAN1_BASE_ADDRESS, 9}, + #endif + #ifdef FDCAN1_TX_PB9_AF9 + {hal_ll_fdcan_module_num(FDCAN_MODULE_1), PB9, FDCAN1_BASE_ADDRESS, 9}, + #endif + #ifdef FDCAN1_TX_PD1_AF9 + {hal_ll_fdcan_module_num(FDCAN_MODULE_1), PD1, FDCAN1_BASE_ADDRESS, 9}, + #endif + {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_CAN_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/can/hal_ll_can_pin_map/implementations/doc_ds_84/hal_ll_can_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/can/hal_ll_can_pin_map/implementations/doc_ds_84/hal_ll_can_pin_map.h new file mode 100644 index 000000000..da707f72a --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/can/hal_ll_can_pin_map/implementations/doc_ds_84/hal_ll_can_pin_map.h @@ -0,0 +1,127 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_can_pin_map.h + * @brief CAN HAL LOW LEVEL PIN MAPS. + */ + +#ifndef _HAL_LL_CAN_PIN_MAP_H_ +#define _HAL_LL_CAN_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_can_module_num(_module_num) (_module_num - 1) +#define hal_ll_fdcan_module_num(_module_num) hal_ll_can_module_num(_module_num) + +/*!< @brief Pin structure */ +typedef struct +{ + uint8_t module_index; + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + uint32_t af; +} hal_ll_can_pin_map_t; + +REPLACE_MODULE_MACROS + +/*!< @brief CAN RX pins */ +static const hal_ll_can_pin_map_t hal_ll_can_rx_map[] = +{ + #ifdef FDCAN1_RX_PA11_AF9 + {hal_ll_fdcan_module_num(FDCAN_MODULE_1), PA11, FDCAN1_BASE_ADDRESS, 9}, + #endif + #ifdef FDCAN1_RX_PB8_AF9 + {hal_ll_fdcan_module_num(FDCAN_MODULE_1), PB8, FDCAN1_BASE_ADDRESS, 9}, + #endif + #ifdef FDCAN1_RX_PD0_AF9 + {hal_ll_fdcan_module_num(FDCAN_MODULE_1), PD0, FDCAN1_BASE_ADDRESS, 9}, + #endif + #ifdef FDCAN2_RX_PB12_AF9 + {hal_ll_fdcan_module_num(FDCAN_MODULE_2), PB12, FDCAN2_BASE_ADDRESS, 9}, + #endif + #ifdef FDCAN2_RX_PB5_AF9 + {hal_ll_fdcan_module_num(FDCAN_MODULE_2), PB5, FDCAN2_BASE_ADDRESS, 9}, + #endif + #ifdef FDCAN3_RX_PA8_AF11 + {hal_ll_fdcan_module_num(FDCAN_MODULE_3), PA8, FDCAN3_BASE_ADDRESS, 11}, + #endif + #ifdef FDCAN3_RX_PB3_AF11 + {hal_ll_fdcan_module_num(FDCAN_MODULE_3), PB3, FDCAN3_BASE_ADDRESS, 11}, + #endif + {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} +}; + +/*!< @brief CAN TX pins */ +static const hal_ll_can_pin_map_t hal_ll_can_tx_map[] = +{ + #ifdef FDCAN1_TX_PA12_AF9 + {hal_ll_fdcan_module_num(FDCAN_MODULE_1), PA12, FDCAN1_BASE_ADDRESS, 9}, + #endif + #ifdef FDCAN1_TX_PB9_AF9 + {hal_ll_fdcan_module_num(FDCAN_MODULE_1), PB9, FDCAN1_BASE_ADDRESS, 9}, + #endif + #ifdef FDCAN1_TX_PD1_AF9 + {hal_ll_fdcan_module_num(FDCAN_MODULE_1), PD1, FDCAN1_BASE_ADDRESS, 9}, + #endif + #ifdef FDCAN2_TX_PB13_AF9 + {hal_ll_fdcan_module_num(FDCAN_MODULE_2), PB13, FDCAN2_BASE_ADDRESS, 9}, + #endif + #ifdef FDCAN2_TX_PB6_AF9 + {hal_ll_fdcan_module_num(FDCAN_MODULE_2), PB6, FDCAN2_BASE_ADDRESS, 9}, + #endif + #ifdef FDCAN3_TX_PA15_AF11 + {hal_ll_fdcan_module_num(FDCAN_MODULE_3), PA15, FDCAN3_BASE_ADDRESS, 11}, + #endif + #ifdef FDCAN3_TX_PB4_AF11 + {hal_ll_fdcan_module_num(FDCAN_MODULE_3), PB4, FDCAN3_BASE_ADDRESS, 11}, + #endif + {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_CAN_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/can/hal_ll_can_pin_map/implementations/doc_ds_85/hal_ll_can_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/can/hal_ll_can_pin_map/implementations/doc_ds_85/hal_ll_can_pin_map.h new file mode 100644 index 000000000..03454cadd --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/can/hal_ll_can_pin_map/implementations/doc_ds_85/hal_ll_can_pin_map.h @@ -0,0 +1,127 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_can_pin_map.h + * @brief CAN HAL LOW LEVEL PIN MAPS. + */ + +#ifndef _HAL_LL_CAN_PIN_MAP_H_ +#define _HAL_LL_CAN_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_can_module_num(_module_num) (_module_num - 1) +#define hal_ll_fdcan_module_num(_module_num) hal_ll_can_module_num(_module_num) + +/*!< @brief Pin structure */ +typedef struct +{ + uint8_t module_index; + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + uint32_t af; +} hal_ll_can_pin_map_t; + +REPLACE_MODULE_MACROS + +/*!< @brief CAN RX pins */ +static const hal_ll_can_pin_map_t hal_ll_can_rx_map[] = +{ + #ifdef FDCAN1_RX_PA11_AF9 + {hal_ll_fdcan_module_num(FDCAN_MODULE_1), PA11, FDCAN1_BASE_ADDRESS, 9}, + #endif + #ifdef FDCAN1_RX_PB8_AF9 + {hal_ll_fdcan_module_num(FDCAN_MODULE_1), PB8, FDCAN1_BASE_ADDRESS, 9}, + #endif + #ifdef FDCAN2_RX_PB12_AF9 + {hal_ll_fdcan_module_num(FDCAN_MODULE_2), PB12, FDCAN2_BASE_ADDRESS, 9}, + #endif + #ifdef FDCAN2_RX_PB5_AF9 + {hal_ll_fdcan_module_num(FDCAN_MODULE_2), PB5, FDCAN2_BASE_ADDRESS, 9}, + #endif + #ifdef FDCAN3_RX_PA8_AF11 + {hal_ll_fdcan_module_num(FDCAN_MODULE_3), PA8, FDCAN3_BASE_ADDRESS, 11}, + #endif + #ifdef FDCAN3_RX_PB3_AF11 + {hal_ll_fdcan_module_num(FDCAN_MODULE_3), PB3, FDCAN3_BASE_ADDRESS, 11}, + #endif + #ifdef FDCAN1_RX_PD0_AF9 + {hal_ll_fdcan_module_num(FDCAN_MODULE_1), PD0, FDCAN1_BASE_ADDRESS, 9}, + #endif + {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} +}; + +/*!< @brief CAN TX pins */ +static const hal_ll_can_pin_map_t hal_ll_can_tx_map[] = +{ + #ifdef FDCAN1_TX_PA12_AF9 + {hal_ll_fdcan_module_num(FDCAN_MODULE_1), PA12, FDCAN1_BASE_ADDRESS, 9}, + #endif + #ifdef FDCAN1_TX_PB9_AF9 + {hal_ll_fdcan_module_num(FDCAN_MODULE_1), PB9, FDCAN1_BASE_ADDRESS, 9}, + #endif + #ifdef FDCAN2_TX_PB13_AF9 + {hal_ll_fdcan_module_num(FDCAN_MODULE_2), PB13, FDCAN2_BASE_ADDRESS, 9}, + #endif + #ifdef FDCAN2_TX_PB6_AF9 + {hal_ll_fdcan_module_num(FDCAN_MODULE_2), PB6, FDCAN2_BASE_ADDRESS, 9}, + #endif + #ifdef FDCAN3_TX_PA15_AF11 + {hal_ll_fdcan_module_num(FDCAN_MODULE_3), PA15, FDCAN3_BASE_ADDRESS, 11}, + #endif + #ifdef FDCAN3_TX_PB4_AF11 + {hal_ll_fdcan_module_num(FDCAN_MODULE_3), PB4, FDCAN3_BASE_ADDRESS, 11}, + #endif + #ifdef FDCAN1_TX_PD1_AF9 + {hal_ll_fdcan_module_num(FDCAN_MODULE_1), PD1, FDCAN1_BASE_ADDRESS, 9}, + #endif + {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_CAN_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/can/hal_ll_can_pin_map/implementations/doc_ds_86/hal_ll_can_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/can/hal_ll_can_pin_map/implementations/doc_ds_86/hal_ll_can_pin_map.h new file mode 100644 index 000000000..da707f72a --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/can/hal_ll_can_pin_map/implementations/doc_ds_86/hal_ll_can_pin_map.h @@ -0,0 +1,127 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_can_pin_map.h + * @brief CAN HAL LOW LEVEL PIN MAPS. + */ + +#ifndef _HAL_LL_CAN_PIN_MAP_H_ +#define _HAL_LL_CAN_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_can_module_num(_module_num) (_module_num - 1) +#define hal_ll_fdcan_module_num(_module_num) hal_ll_can_module_num(_module_num) + +/*!< @brief Pin structure */ +typedef struct +{ + uint8_t module_index; + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + uint32_t af; +} hal_ll_can_pin_map_t; + +REPLACE_MODULE_MACROS + +/*!< @brief CAN RX pins */ +static const hal_ll_can_pin_map_t hal_ll_can_rx_map[] = +{ + #ifdef FDCAN1_RX_PA11_AF9 + {hal_ll_fdcan_module_num(FDCAN_MODULE_1), PA11, FDCAN1_BASE_ADDRESS, 9}, + #endif + #ifdef FDCAN1_RX_PB8_AF9 + {hal_ll_fdcan_module_num(FDCAN_MODULE_1), PB8, FDCAN1_BASE_ADDRESS, 9}, + #endif + #ifdef FDCAN1_RX_PD0_AF9 + {hal_ll_fdcan_module_num(FDCAN_MODULE_1), PD0, FDCAN1_BASE_ADDRESS, 9}, + #endif + #ifdef FDCAN2_RX_PB12_AF9 + {hal_ll_fdcan_module_num(FDCAN_MODULE_2), PB12, FDCAN2_BASE_ADDRESS, 9}, + #endif + #ifdef FDCAN2_RX_PB5_AF9 + {hal_ll_fdcan_module_num(FDCAN_MODULE_2), PB5, FDCAN2_BASE_ADDRESS, 9}, + #endif + #ifdef FDCAN3_RX_PA8_AF11 + {hal_ll_fdcan_module_num(FDCAN_MODULE_3), PA8, FDCAN3_BASE_ADDRESS, 11}, + #endif + #ifdef FDCAN3_RX_PB3_AF11 + {hal_ll_fdcan_module_num(FDCAN_MODULE_3), PB3, FDCAN3_BASE_ADDRESS, 11}, + #endif + {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} +}; + +/*!< @brief CAN TX pins */ +static const hal_ll_can_pin_map_t hal_ll_can_tx_map[] = +{ + #ifdef FDCAN1_TX_PA12_AF9 + {hal_ll_fdcan_module_num(FDCAN_MODULE_1), PA12, FDCAN1_BASE_ADDRESS, 9}, + #endif + #ifdef FDCAN1_TX_PB9_AF9 + {hal_ll_fdcan_module_num(FDCAN_MODULE_1), PB9, FDCAN1_BASE_ADDRESS, 9}, + #endif + #ifdef FDCAN1_TX_PD1_AF9 + {hal_ll_fdcan_module_num(FDCAN_MODULE_1), PD1, FDCAN1_BASE_ADDRESS, 9}, + #endif + #ifdef FDCAN2_TX_PB13_AF9 + {hal_ll_fdcan_module_num(FDCAN_MODULE_2), PB13, FDCAN2_BASE_ADDRESS, 9}, + #endif + #ifdef FDCAN2_TX_PB6_AF9 + {hal_ll_fdcan_module_num(FDCAN_MODULE_2), PB6, FDCAN2_BASE_ADDRESS, 9}, + #endif + #ifdef FDCAN3_TX_PA15_AF11 + {hal_ll_fdcan_module_num(FDCAN_MODULE_3), PA15, FDCAN3_BASE_ADDRESS, 11}, + #endif + #ifdef FDCAN3_TX_PB4_AF11 + {hal_ll_fdcan_module_num(FDCAN_MODULE_3), PB4, FDCAN3_BASE_ADDRESS, 11}, + #endif + {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_CAN_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/can/hal_ll_can_pin_map/implementations/doc_ds_87/hal_ll_can_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/can/hal_ll_can_pin_map/implementations/doc_ds_87/hal_ll_can_pin_map.h new file mode 100644 index 000000000..da707f72a --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/can/hal_ll_can_pin_map/implementations/doc_ds_87/hal_ll_can_pin_map.h @@ -0,0 +1,127 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_can_pin_map.h + * @brief CAN HAL LOW LEVEL PIN MAPS. + */ + +#ifndef _HAL_LL_CAN_PIN_MAP_H_ +#define _HAL_LL_CAN_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_can_module_num(_module_num) (_module_num - 1) +#define hal_ll_fdcan_module_num(_module_num) hal_ll_can_module_num(_module_num) + +/*!< @brief Pin structure */ +typedef struct +{ + uint8_t module_index; + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + uint32_t af; +} hal_ll_can_pin_map_t; + +REPLACE_MODULE_MACROS + +/*!< @brief CAN RX pins */ +static const hal_ll_can_pin_map_t hal_ll_can_rx_map[] = +{ + #ifdef FDCAN1_RX_PA11_AF9 + {hal_ll_fdcan_module_num(FDCAN_MODULE_1), PA11, FDCAN1_BASE_ADDRESS, 9}, + #endif + #ifdef FDCAN1_RX_PB8_AF9 + {hal_ll_fdcan_module_num(FDCAN_MODULE_1), PB8, FDCAN1_BASE_ADDRESS, 9}, + #endif + #ifdef FDCAN1_RX_PD0_AF9 + {hal_ll_fdcan_module_num(FDCAN_MODULE_1), PD0, FDCAN1_BASE_ADDRESS, 9}, + #endif + #ifdef FDCAN2_RX_PB12_AF9 + {hal_ll_fdcan_module_num(FDCAN_MODULE_2), PB12, FDCAN2_BASE_ADDRESS, 9}, + #endif + #ifdef FDCAN2_RX_PB5_AF9 + {hal_ll_fdcan_module_num(FDCAN_MODULE_2), PB5, FDCAN2_BASE_ADDRESS, 9}, + #endif + #ifdef FDCAN3_RX_PA8_AF11 + {hal_ll_fdcan_module_num(FDCAN_MODULE_3), PA8, FDCAN3_BASE_ADDRESS, 11}, + #endif + #ifdef FDCAN3_RX_PB3_AF11 + {hal_ll_fdcan_module_num(FDCAN_MODULE_3), PB3, FDCAN3_BASE_ADDRESS, 11}, + #endif + {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} +}; + +/*!< @brief CAN TX pins */ +static const hal_ll_can_pin_map_t hal_ll_can_tx_map[] = +{ + #ifdef FDCAN1_TX_PA12_AF9 + {hal_ll_fdcan_module_num(FDCAN_MODULE_1), PA12, FDCAN1_BASE_ADDRESS, 9}, + #endif + #ifdef FDCAN1_TX_PB9_AF9 + {hal_ll_fdcan_module_num(FDCAN_MODULE_1), PB9, FDCAN1_BASE_ADDRESS, 9}, + #endif + #ifdef FDCAN1_TX_PD1_AF9 + {hal_ll_fdcan_module_num(FDCAN_MODULE_1), PD1, FDCAN1_BASE_ADDRESS, 9}, + #endif + #ifdef FDCAN2_TX_PB13_AF9 + {hal_ll_fdcan_module_num(FDCAN_MODULE_2), PB13, FDCAN2_BASE_ADDRESS, 9}, + #endif + #ifdef FDCAN2_TX_PB6_AF9 + {hal_ll_fdcan_module_num(FDCAN_MODULE_2), PB6, FDCAN2_BASE_ADDRESS, 9}, + #endif + #ifdef FDCAN3_TX_PA15_AF11 + {hal_ll_fdcan_module_num(FDCAN_MODULE_3), PA15, FDCAN3_BASE_ADDRESS, 11}, + #endif + #ifdef FDCAN3_TX_PB4_AF11 + {hal_ll_fdcan_module_num(FDCAN_MODULE_3), PB4, FDCAN3_BASE_ADDRESS, 11}, + #endif + {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_CAN_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/can/hal_ll_can_pin_map/implementations/doc_ds_88/hal_ll_can_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/can/hal_ll_can_pin_map/implementations/doc_ds_88/hal_ll_can_pin_map.h new file mode 100644 index 000000000..5fc652bc5 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/can/hal_ll_can_pin_map/implementations/doc_ds_88/hal_ll_can_pin_map.h @@ -0,0 +1,115 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_can_pin_map.h + * @brief CAN HAL LOW LEVEL PIN MAPS. + */ + +#ifndef _HAL_LL_CAN_PIN_MAP_H_ +#define _HAL_LL_CAN_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_can_module_num(_module_num) (_module_num - 1) +#define hal_ll_fdcan_module_num(_module_num) hal_ll_can_module_num(_module_num) + +/*!< @brief Pin structure */ +typedef struct +{ + uint8_t module_index; + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + uint32_t af; +} hal_ll_can_pin_map_t; + +REPLACE_MODULE_MACROS + +/*!< @brief CAN RX pins */ +static const hal_ll_can_pin_map_t hal_ll_can_rx_map[] = +{ + #ifdef FDCAN1_RX_PA11_AF9 + {hal_ll_fdcan_module_num(FDCAN_MODULE_1), PA11, FDCAN1_BASE_ADDRESS, 9}, + #endif + #ifdef FDCAN1_RX_PB8_AF9 + {hal_ll_fdcan_module_num(FDCAN_MODULE_1), PB8, FDCAN1_BASE_ADDRESS, 9}, + #endif + #ifdef FDCAN2_RX_PB5_AF9 + {hal_ll_fdcan_module_num(FDCAN_MODULE_2), PB5, FDCAN2_BASE_ADDRESS, 9}, + #endif + #ifdef FDCAN1_RX_PD0_AF9 + {hal_ll_fdcan_module_num(FDCAN_MODULE_1), PD0, FDCAN1_BASE_ADDRESS, 9}, + #endif + #ifdef FDCAN2_RX_PB12_AF9 + {hal_ll_fdcan_module_num(FDCAN_MODULE_2), PB12, FDCAN2_BASE_ADDRESS, 9}, + #endif + {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} +}; + +/*!< @brief CAN TX pins */ +static const hal_ll_can_pin_map_t hal_ll_can_tx_map[] = +{ + #ifdef FDCAN1_TX_PA12_AF9 + {hal_ll_fdcan_module_num(FDCAN_MODULE_1), PA12, FDCAN1_BASE_ADDRESS, 9}, + #endif + #ifdef FDCAN2_TX_PB6_AF9 + {hal_ll_fdcan_module_num(FDCAN_MODULE_2), PB6, FDCAN2_BASE_ADDRESS, 9}, + #endif + #ifdef FDCAN1_TX_PB9_AF9 + {hal_ll_fdcan_module_num(FDCAN_MODULE_1), PB9, FDCAN1_BASE_ADDRESS, 9}, + #endif + #ifdef FDCAN1_TX_PD1_AF9 + {hal_ll_fdcan_module_num(FDCAN_MODULE_1), PD1, FDCAN1_BASE_ADDRESS, 9}, + #endif + #ifdef FDCAN2_TX_PB13_AF9 + {hal_ll_fdcan_module_num(FDCAN_MODULE_2), PB13, FDCAN2_BASE_ADDRESS, 9}, + #endif + {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_CAN_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/can/hal_ll_can_pin_map/implementations/doc_ds_89/hal_ll_can_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/can/hal_ll_can_pin_map/implementations/doc_ds_89/hal_ll_can_pin_map.h new file mode 100644 index 000000000..67c912376 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/can/hal_ll_can_pin_map/implementations/doc_ds_89/hal_ll_can_pin_map.h @@ -0,0 +1,115 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_can_pin_map.h + * @brief CAN HAL LOW LEVEL PIN MAPS. + */ + +#ifndef _HAL_LL_CAN_PIN_MAP_H_ +#define _HAL_LL_CAN_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_can_module_num(_module_num) (_module_num - 1) +#define hal_ll_fdcan_module_num(_module_num) hal_ll_can_module_num(_module_num) + +/*!< @brief Pin structure */ +typedef struct +{ + uint8_t module_index; + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + uint32_t af; +} hal_ll_can_pin_map_t; + +REPLACE_MODULE_MACROS + +/*!< @brief CAN RX pins */ +static const hal_ll_can_pin_map_t hal_ll_can_rx_map[] = +{ + #ifdef FDCAN1_RX_PA11_AF9 + {hal_ll_fdcan_module_num(FDCAN_MODULE_1), PA11, FDCAN1_BASE_ADDRESS, 9}, + #endif + #ifdef FDCAN1_RX_PB8_AF9 + {hal_ll_fdcan_module_num(FDCAN_MODULE_1), PB8, FDCAN1_BASE_ADDRESS, 9}, + #endif + #ifdef FDCAN1_RX_PD0_AF9 + {hal_ll_fdcan_module_num(FDCAN_MODULE_1), PD0, FDCAN1_BASE_ADDRESS, 9}, + #endif + #ifdef FDCAN2_RX_PB12_AF9 + {hal_ll_fdcan_module_num(FDCAN_MODULE_2), PB12, FDCAN2_BASE_ADDRESS, 9}, + #endif + #ifdef FDCAN2_RX_PB5_AF9 + {hal_ll_fdcan_module_num(FDCAN_MODULE_2), PB5, FDCAN2_BASE_ADDRESS, 9}, + #endif + {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} +}; + +/*!< @brief CAN TX pins */ +static const hal_ll_can_pin_map_t hal_ll_can_tx_map[] = +{ + #ifdef FDCAN1_TX_PA12_AF9 + {hal_ll_fdcan_module_num(FDCAN_MODULE_1), PA12, FDCAN1_BASE_ADDRESS, 9}, + #endif + #ifdef FDCAN1_TX_PB9_AF9 + {hal_ll_fdcan_module_num(FDCAN_MODULE_1), PB9, FDCAN1_BASE_ADDRESS, 9}, + #endif + #ifdef FDCAN1_TX_PD1_AF9 + {hal_ll_fdcan_module_num(FDCAN_MODULE_1), PD1, FDCAN1_BASE_ADDRESS, 9}, + #endif + #ifdef FDCAN2_TX_PB13_AF9 + {hal_ll_fdcan_module_num(FDCAN_MODULE_2), PB13, FDCAN2_BASE_ADDRESS, 9}, + #endif + #ifdef FDCAN2_TX_PB6_AF9 + {hal_ll_fdcan_module_num(FDCAN_MODULE_2), PB6, FDCAN2_BASE_ADDRESS, 9}, + #endif + {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_CAN_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/dma/hal_ll_dma.h b/targets/arm/mikroe/ai_generated/stm32/include/dma/hal_ll_dma.h new file mode 100644 index 000000000..af2275b11 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/dma/hal_ll_dma.h @@ -0,0 +1,311 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_dma.h + * @brief API for DMA HAL LOW LEVEL layer. + */ + +#ifndef _HAL_LL_DMA_H_ +#define _HAL_LL_DMA_H_ + +#include "hal_ll_target.h" + +#ifdef __cplusplus +extern "C"{ +#endif + +/** + * @details Return values. + */ +typedef enum +{ + HAL_LL_DMA_SUCCESS = 0, /*!< Success. */ + HAL_LL_DMA_ERROR = (-1) /*!< Error. */ +} hal_ll_dma_err_t; + +/** + * @details Module state values. + */ +typedef enum +{ + HAL_LL_DMA_STATE_FREE = 0, /*!< DMA object is free for use. */ + HAL_LL_DMA_STATE_ALLOCATED /*!< DMA object has been allocated - not free for use. */ +} hal_ll_dma_state_t; + +/** + * @details Source address memory region. + */ +typedef enum +{ + HAL_LL_DMA_SOURCE_MEMORY_REGION_RAM = 0, /*!< DMA source address is in RAM section. */ + HAL_LL_DMA_SOURCE_MEMORY_REGION_PFM = 1, /*!< DMA source address is in Program Flash Memory section. */ + HAL_LL_DMA_SOURCE_MEMORY_REGION_DEEPROM = 2 /*!< DMA source address is in Data EEPROM section. */ +} hal_ll_dma_source_memory_region_t; + +/** + * @details Module direction values. + */ +typedef enum +{ + HAL_LL_DMA_DIRECTION_MEMORY_TO_MEMORY = 0, /*!< M2M */ + HAL_LL_DMA_DIRECTION_MEMORY_TO_PERIPH, /*!< M2P */ + HAL_LL_DMA_DIRECTION_PERIPH_TO_MEMORY, /*!< P2M */ + HAL_LL_DMA_DIRECTION_PERIPH_TO_PERIPH, /*!< P2P */ + + HAL_LL_DMA_DIRECTION_DEFAULT = HAL_LL_DMA_DIRECTION_MEMORY_TO_MEMORY /*!< Default value is M2M. */ +} hal_ll_dma_direction_t; + +/** + * @details Module data alignment values. + */ +typedef enum +{ + HAL_LL_DMA_DATA_ALIGN_BYTES_1 = 0, /*!< Align data to byte (uint8_t). */ + HAL_LL_DMA_DATA_ALIGN_BYTES_2, /*!< Align data to half word (uint16_t). */ + HAL_LL_DMA_DATA_ALIGN_BYTES_3, /*!< Align data to 3 bytes (uint24_t). */ + HAL_LL_DMA_DATA_ALIGN_BYTES_4, /*!< Align data to word (uint32_t). */ + + HAL_LL_DMA_DATA_ALIGN_DEFAULT = HAL_LL_DMA_DATA_ALIGN_BYTES_1 /*!< Default data alignment of byte (uint8_t). */ +} hal_ll_dma_data_align_t; + +/** + * @details Module mode values. + */ +typedef enum +{ + HAL_LL_DMA_MODE_NORMAL = 0, /*!< Normal mode. */ + HAL_LL_DMA_MODE_CIRCULAR, /*!< Circular mode. */ + + HAL_LL_DMA_MODE_DEFAULT = HAL_LL_DMA_MODE_NORMAL /*!< Default mode set to normal. */ +} hal_ll_dma_mode_t; + +/** + * @details Module priority levels. + */ +typedef enum +{ + HAL_LL_DMA_PRIORITY_LOW = 0, /*!< Sets priority level to low. */ + HAL_LL_DMA_PRIORITY_MEDIUM, /*!< Sets priority level to medium. */ + HAL_LL_DMA_PRIORITY_HIGH, /*!< Sets priority level to high. */ + HAL_LL_DMA_PRIORITY_VERY_HIGH, /*!< Sets priority level to very high. */ + + HAL_LL_DMA_PRIORITY_DEFAULT = HAL_LL_DMA_PRIORITY_MEDIUM /*!< Default priority level set to medium. */ +} hal_ll_dma_priority_t; + +/** + * @details Module burst increment size. + */ +typedef enum +{ + HAL_LL_DMA_BURST_SIZE_INCREMENT_1 = 0, /*!< Dma module burst increment size set to 1 byte. */ + HAL_LL_DMA_BURST_SIZE_INCREMENT_2, /*!< Dma module burst increment size set to 2 bytes. */ + HAL_LL_DMA_BURST_SIZE_INCREMENT_4, /*!< Dma module burst increment size set to 4 bytes. */ + HAL_LL_DMA_BURST_SIZE_INCREMENT_8, /*!< Dma module burst increment size set to 8 bytes. */ + HAL_LL_DMA_BURST_SIZE_INCREMENT_16, /*!< Dma module burst increment size set to 16 bytes. */ + HAL_LL_DMA_BURST_SIZE_INCREMENT_32, /*!< Dma module burst increment size set to 32 bytes. */ + + HAL_LL_DMA_BURST_SIZE_INCREMENT_DEFAULT = HAL_LL_DMA_BURST_SIZE_INCREMENT_1 /*!< Default burst increment size set to 1 byte. */ +} hal_ll_dma_burst_size_t; + +/** + * @brief HAL LL DMA Configuration Structure prototype. + */ +typedef struct +{ + uint8_t module; /*!< Specifies the module. */ + uint8_t stream; /*!< Specifies the stream. */ + uint8_t channel; /*!< Specifies the channel used for the specified stream. */ + hal_ll_dma_direction_t direction; /*!< Specifies if the data will be transferred from memory to peripheral, + from memory to memory, from peripheral to memory, or from + peripheral to peripheral. + This parameter can be a value of @ref hal_ll_dma_direction_t */ + hal_ll_dma_mode_t mode; /*!< Specifies the operation mode of the DMA Stream. + This parameter can be a value of @ref hal_ll_dma_mode_t */ + bool src_inc; /*!< Specifies whether the Source address register should be incremented or not. */ + hal_ll_dma_data_align_t data_align_source; /*!< Specifies the Source data width. + This parameter can be a value of @ref hal_ll_dma_data_align_t */ + hal_ll_dma_burst_size_t burst_size_source; /*!< Specifies the Burst transfer configuration for the source transfers. + It specifies the amount of data to be transferred in a single non interruptable + transaction. + This parameter can be a value of @ref hal_ll_dma_burst_size_t + @note The burst mode is possible only if the address increment mode is enabled. */ + bool dst_inc; /*!< Specifies whether the Destination address register should be incremented or not. */ + hal_ll_dma_data_align_t data_align_destination; /*!< Specifies the Destination data width. + This parameter can be a value of @ref hal_ll_dma_data_align_t */ + hal_ll_dma_burst_size_t burst_size_destination; /*!< Specifies the Burst transfer configuration for the destination transfers. + It specifies the amount of data to be transferred in a single non interruptable + transaction. + This parameter can be a value of @ref hal_ll_dma_burst_size_t + @note The burst mode is possible only if the address increment mode is enabled. */ + hal_ll_dma_priority_t priority; /*!< Specifies the software priority for the DMA Stream. + This parameter can be a value of @ref hal_ll_dma_priority_t */ + uint32_t addr_src; /*!< Address to transfer from. */ + uint32_t addr_dst; /*!< Address to transfer to. */ + size_t transfer_length; /*!< Number of bytes to transfer. */ +} hal_ll_dma_config_t; + +/** + * @brief HAL DMA Handle prototype. + * @details DMA hal context structure, used by every other function later on. + */ +typedef struct +{ + handle_t handle; /*!< DMA HAL LL handle. */ + hal_ll_dma_config_t config; /*!< DMA HAL LL configuration structure. */ + uint8_t module; /*!< Specifies the module. */ + uint8_t stream; /*!< Specifies the stream. */ + uint8_t channel; /*!< Specifies the channel used for the specified stream. */ + hal_ll_dma_state_t allocated; /*!< Is the object allocated or not? */ + bool initialized; /*!< Is the object initialized or not? */ +} hal_ll_dma_t; + +/** + * @brief Initializes the DMA module. + * @details Enables module clock and initializes to values set in + * @b hal_ll_dma_t->hal_ll_dma_config_t + * @param[in,out] obj DMA HAL LL object. + * See #hal_ll_dma_t structure definition for detailed explanation. + * @return The function can return one of the values defined by + * hal_ll_err_t, which is dependant on the architecture and ported low level layer. + * @note It is recommended to check return value for error. + */ +hal_ll_err_t hal_ll_dma_init( hal_ll_dma_t *obj ); + +/** + * @brief Set the DMA mode. + * @details Sets DMA mode to be used by the DMA HAL LL. + * @param[in,out] obj DMA HAL LL object. + * See #hal_ll_dma_t structure definition for detailed explanation. + * @param[in] mode DMA mode. + * See #hal_ll_dma_mode_t for valid values. + * @return The function can return one of the values defined by + * hal_ll_err_t, which is dependant on the architecture and ported low level layer. + * @note It is recommended to check return value for error. + */ +hal_ll_err_t hal_ll_dma_set_mode( hal_ll_dma_t *obj, hal_ll_dma_mode_t mode ); + +/** + * @brief Set the DMA direction. + * @details Sets DMA direction to be used by the DMA HAL LL. + * @param[in,out] obj DMA HAL LL object. + * See #hal_ll_dma_t structure definition for detailed explanation. + * @param[in] direction DMA direction. + * See #hal_ll_dma_direction_t for valid values. + * @return The function can return one of the values defined by + * hal_ll_err_t, which is dependant on the architecture and ported low level layer. + * @note It is recommended to check return value for error. + */ +hal_ll_err_t hal_ll_dma_set_direction( hal_ll_dma_t *obj, hal_ll_dma_direction_t direction ); + +/** + * @brief Set the DMA priority. + * @details Sets DMA priority level to be used by the DMA HAL LL. + * @param[in,out] obj DMA HAL LL object. + * See #hal_ll_dma_t structure definition for detailed explanation. + * @param[in] priority DMA priority level. + * See #hal_ll_dma_priority_t for valid values. + * @return The function can return one of the values defined by + * hal_ll_err_t, which is dependant on the architecture and ported low level layer. + * @note It is recommended to check return value for error. + */ +hal_ll_err_t hal_ll_dma_set_priority( hal_ll_dma_t *obj, hal_ll_dma_priority_t priority ); + +/** + * @brief Configure the DMA transfer. + * @details Configures initialized DMA stream for transfer. + * @param[in,out] obj DMA HAL LL object. + * See #hal_dma_t structure definition for detailed explanation. + * @param[in] addr_src Source address for transfer. + * @param[in] addr_dst Destination address for transfer. + * @param[in] transfer_size Number of bytes to transfer. + * @param[in] src_mem_type Source address memory region. + * @return Nothing. + */ +hal_ll_err_t hal_ll_dma_set_parameters( hal_ll_dma_t *obj, uint32_t addr_src, uint32_t addr_dst, size_t transfer_size, hal_ll_dma_source_memory_region_t src_mem_type ); + +/** + * @brief Initializes the DMA transfer. + * @details Starts previously configured DMA transfer by enabling stream. + * @param[in,out] obj DMA HAL LL object. + * See #hal_ll_dma_t structure definition for detailed explanation. + * @return The function can return one of the values defined by + * hal_ll_err_t, which is dependant on the architecture and ported low level layer. + * @note It is recommended to check return value for error. + */ +hal_ll_err_t hal_ll_dma_transfer_start( hal_ll_dma_t *obj ); + +/** + * @brief Stops the DMA transfer. + * @details Stops an active DMA transfer by disabling stream. + * @param[in,out] obj DMA HAL LL object. + * See #hal_ll_dma_t structure definition for detailed explanation. + * @return The function can return one of the values defined by + * hal_ll_err_t, which is dependant on the architecture and ported low level layer. + * @note It is recommended to check return value for error. + */ +hal_ll_err_t hal_ll_dma_transfer_stop( hal_ll_dma_t *obj ); + +/** + * @brief Aborts a DMA transfer. + * @details Aborts any ongoing DMA transfers and disables stream. + * @param[in,out] obj DMA HAL LL object. + * See #hal_ll_dma_t structure definition for detailed explanation. + * @return The function can return one of the values defined by + * hal_ll_err_t, which is dependant on the architecture and ported low level layer. + * @note It is recommended to check return value for error. + */ +hal_ll_err_t hal_ll_dma_transfer_abort( hal_ll_dma_t *obj ); + +/** + * @brief De-initializes the DMA module. + * @details Disables module clock and de-initializes module. + * @param[in,out] obj DMA HAL LL object. + * See #hal_ll_dma_t structure definition for detailed explanation. + * @return The function can return one of the values defined by + * hal_ll_err_t, which is dependant on the architecture and ported low level layer. + * @note It is recommended to check return value for error. + */ +hal_ll_err_t hal_ll_dma_deinit( hal_ll_dma_t *dma_obj ); + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_DMA_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/gpio/hal_ll_gpio.h b/targets/arm/mikroe/ai_generated/stm32/include/gpio/hal_ll_gpio.h new file mode 100644 index 000000000..bf11dfdea --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/gpio/hal_ll_gpio.h @@ -0,0 +1,278 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_gpio.h + * @brief This file contains all the functions prototypes for the GPIO library. + */ + +#ifndef _HAL_LL_GPIO_H_ +#define _HAL_LL_GPIO_H_ + +#include "hal_ll_gpio_port.h" + +#ifdef __cplusplus +extern "C"{ +#endif + +/** + * @brief Function configures pin. + * + * Configures pin to digital output or digital input. + * Sets only the pin defined by pin mask in + * hal_ll_gpio_pin_t structure. + * + * @param *pin Pin object context. + * Configured during this functions process. + * @param name Pin name -- PA0, PA1... + * @param direction Pin direction. + * HAL_LL_GPIO_DIGITAL_INPUT + * HAL_LL_GPIO_DIGITAL_OUTPUT + * + * @return None. + */ +void hal_ll_gpio_configure_pin(hal_ll_gpio_pin_t *pin, hal_ll_pin_name_t name, hal_ll_gpio_direction_t direction); + +/** + * @brief Read pin input. + * + * Checks pin data input register value and + * returns logical state. + * + * @param *pin Pin object context. + * Configured during hal_ll_gpio_configure_pin. + * + * @return uint8_t Pin logical state. + * 1/true -- pin high state -- 1.8V or more detected + * 0/false -- pin low state -- 1.8V or less detected + */ +#if defined(FLATTEN_ME) && (FLATTEN_ME_LEVEL >= FLATTEN_ME_LEVEL_LOW) +#define hal_ll_gpio_read_pin_input(_handle) ((((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base) == 0) ? \ + (0) : (((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base)->idr & ((hal_ll_gpio_pin_t *)_handle)->mask) ? \ + (1) : (0)) +#else +uint8_t hal_ll_gpio_read_pin_input(hal_ll_gpio_pin_t *pin); +#endif + +/** + * @brief Read pin output. + * + * Checks pin data output register value and + * returns logical state. + * + * @param *pin Pin object context. + * Configured during hal_ll_gpio_configure_pin. + * + * @return uint8_t Pin logical state. + * 1/true -- pin high state -- 1.8V or more detected + * 0/false -- pin low state -- 1.8V or less detected + */ +#if defined(FLATTEN_ME) && (FLATTEN_ME_LEVEL >= FLATTEN_ME_LEVEL_LOW) +#define hal_ll_gpio_read_pin_output(_handle) ((((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base) == 0) ? \ + (0) : (((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base)->odr & ((hal_ll_gpio_pin_t *)_handle)->mask) ? \ + (1) : (0)) +#else +uint8_t hal_ll_gpio_read_pin_output(hal_ll_gpio_pin_t *pin); +#endif + +/** + * @brief Writes pin output state. + * + * Sets single pin logical state. + * + * @param *pin Pin object context. + * Configured during hal_ll_gpio_configure_pin. + * @param value Pin logical state. + * 1/true -- sets pin high state -- over 1.8V + * 0/false -- sets pin low state -- less than 1.8V + * + * @return None + */ +#if defined(FLATTEN_ME) && (FLATTEN_ME_LEVEL >= FLATTEN_ME_LEVEL_LOW) +#define hal_ll_gpio_write_pin_output(_handle,_value) ((((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base) != NULL) ? \ + ((_value > 0) ? \ + (((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base)->bsrr = ((hal_ll_gpio_pin_t *)_handle)->mask) : \ + (((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base)->bsrr = ((uint32_t)((hal_ll_gpio_pin_t *)_handle)->mask << RESET_PINS_OFFSET))) : \ + (0)) +#else +void hal_ll_gpio_write_pin_output(hal_ll_gpio_pin_t *pin, uint8_t value); +#endif + +/** + * @brief Toggles pin logical state. + * + * Checks current state of pin + * and toggles it. + * + * @param *pin Pin object context. + * Configured during hal_ll_gpio_configure_pin. + * + * @return None + */ +#if defined(FLATTEN_ME) && (FLATTEN_ME_LEVEL >= FLATTEN_ME_LEVEL_LOW) +#define hal_ll_gpio_toggle_pin_output(_handle) ((((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base) != NULL) ? \ + ((((((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base)->odr & ((hal_ll_gpio_pin_t *)_handle)->mask))) ? \ + (((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base)->bsrr = ((uint32_t)((hal_ll_gpio_pin_t *)_handle)->mask << RESET_PINS_OFFSET)) : \ + (((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base)->bsrr = ((hal_ll_gpio_pin_t *)_handle)->mask)) : \ + (0)) +#else +void hal_ll_gpio_toggle_pin_output(hal_ll_gpio_pin_t *pin); +#endif + +/** + * @brief Sets pin logical state. + * + * Sets pin logical state to high. + * + * @param *pin Pin object context. + * Configured during hal_ll_gpio_configure_pin. + * + * @return None + */ +#if defined(FLATTEN_ME) && (FLATTEN_ME_LEVEL >= FLATTEN_ME_LEVEL_LOW) +#define hal_ll_gpio_set_pin_output(_handle) ((((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base) != NULL) ? \ + (((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base)->bsrr = ((hal_ll_gpio_pin_t *)_handle)->mask) : \ + (0)) +#else +void hal_ll_gpio_set_pin_output(hal_ll_gpio_pin_t *pin); +#endif + +/** + * @brief Sets pin logical state. + * + * Sets pin logical state to low. + * + * @param *pin Pin object context. + * Configured during hal_ll_gpio_configure_pin. + * + * @return None + */ +#if defined(FLATTEN_ME) && (FLATTEN_ME_LEVEL >= FLATTEN_ME_LEVEL_LOW) +#define hal_ll_gpio_clear_pin_output(_handle) ((((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base) != NULL) ? \ + (((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base)->bsrr = ((uint32_t)((hal_ll_gpio_pin_t *)_handle)->mask << RESET_PINS_OFFSET)) : \ + (0)) +#else +void hal_ll_gpio_clear_pin_output(hal_ll_gpio_pin_t *pin); +#endif + +/** + * @brief Configures port. + * + * Configures port according to specified + * direction. Takes into consideration only + * pins defined by mask. + * + * @param *port Port object context. + * Configured during this functions process. + * @param name Port name. + * @param mask Port pin mask. + * @param direction Port pin direction. + * HAL_LL_GPIO_DIGITAL_INPUT + * HAL_LL_GPIO_DIGITAL_OUTPUT + * + * @return None + */ +void hal_ll_gpio_configure_port(hal_ll_gpio_port_t *port, hal_ll_port_name_t name, hal_ll_gpio_mask_t mask, hal_ll_gpio_direction_t direction); + +/** + * @brief Read port input value. + * + * Checks port data input register value and + * returns it. + * + * @param *port Port object context. + * Configured during hal_ll_gpio_configure_port. + * + * @return hal_ll_port_size_t Port input data register value. + */ +#if defined(FLATTEN_ME) && (FLATTEN_ME_LEVEL >= FLATTEN_ME_LEVEL_LOW) +#define hal_ll_gpio_read_port_input(_handle) ((((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_port_t *)_handle)->base) != NULL) ? \ + ((hal_ll_port_size_t)((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_port_t *)_handle)->base)->idr & ((hal_ll_gpio_port_t *)_handle)->mask) : \ + (0)) +#else +hal_ll_port_size_t hal_ll_gpio_read_port_input(hal_ll_gpio_port_t *port); +#endif + +/** + * @brief Read port output value. + * + * Checks port data output register value and + * returns it. + * + * @param *port Port object context. + * Configured during hal_ll_gpio_configure_port. + * @return hal_ll_port_size_t Port output data register value. + */ +#if defined(FLATTEN_ME) && (FLATTEN_ME_LEVEL >= FLATTEN_ME_LEVEL_LOW) +#define hal_ll_gpio_read_port_output(_handle) ((((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_port_t *)_handle)->base) != NULL) ? \ + ((hal_ll_port_size_t)(((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_port_t *)_handle)->base)->odr) & (((hal_ll_gpio_port_t *)_handle)->mask)) : \ + (0)) +#else +hal_ll_port_size_t hal_ll_gpio_read_port_output(hal_ll_gpio_port_t *port); +#endif + +/** + * @brief Set port state. + * + * Sets port output state. + * Will take into consideration only + * port pins defined by mask in + * port object context. + * + * @param *port Port object context. + * Configured during hal_ll_gpio_configure_port. + * @param value Port output value + * + * @return None + */ +#if defined(FLATTEN_ME) && (FLATTEN_ME_LEVEL >= FLATTEN_ME_LEVEL_LOW) +#define hal_ll_gpio_write_port_output(_handle,_value) ((((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_port_t *)_handle)->base) != NULL) ? \ + (((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_port_t *)_handle)->base)->bsrr = \ + ((hal_ll_port_size_t)_value & ((hal_ll_gpio_port_t *)_handle)->mask) | \ + ((uint32_t)(~(hal_ll_port_size_t)_value & ((hal_ll_gpio_port_t *)_handle)->mask) << RESET_PINS_OFFSET)) : \ + (0)) +#else +void hal_ll_gpio_write_port_output(hal_ll_gpio_port_t *port, hal_ll_port_size_t value); +#endif + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_GPIO_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/gpio/hal_ll_gpio_port.h b/targets/arm/mikroe/ai_generated/stm32/include/gpio/hal_ll_gpio_port.h new file mode 100644 index 000000000..16da9e85d --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/gpio/hal_ll_gpio_port.h @@ -0,0 +1,160 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_gpio.h + * @brief This file contains all the functions prototypes for the GPIO library. + */ + +#ifndef _HAL_LL_GPIO_PORT_H_ +#define _HAL_LL_GPIO_PORT_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_target.h" +#include "hal_ll_gpio_constants.h" +#include "hal_ll_gpio_struct_type.h" + +#define RESET_PINS_OFFSET 16 + +/** + * Helper macros for GPIO HAL + */ +#define GPIO_MODULE_STRUCT_END -1 +#define GPIO_AF_OFFSET 8 +#define VALUE(pin, func) (pin | (func << GPIO_AF_OFFSET)) + +/** + * GPIO module struct defining pins and proprietary functions + */ +typedef struct +{ + uint32_t pins[13]; + uint32_t configs[13]; + uint32_t gpio_remap; +} module_struct; + +/** + * Handle and mask types. + */ +typedef handle_t hal_ll_gpio_base_t; + +/** + * Enum used for pin direction selection. + */ +typedef enum +{ + HAL_LL_GPIO_DIGITAL_INPUT = 0, + HAL_LL_GPIO_DIGITAL_OUTPUT = 1 +} hal_ll_gpio_direction_t; + +/** + * Enum used for pin direction selection. + */ +typedef struct hal_ll_gpio_t +{ + hal_ll_gpio_base_t base; + hal_ll_gpio_mask_t mask; +}; + +/** + * Pin and port data types. + */ +typedef struct hal_ll_gpio_t hal_ll_gpio_pin_t; +typedef struct hal_ll_gpio_t hal_ll_gpio_port_t; + +/** + * @brief Get pins port index within a list of available ports + * @param name - desired pin + * @return uint8_t value from 0 to PORT_COUNT-1 + */ +uint8_t hal_ll_gpio_port_index( hal_ll_pin_name_t name ); + +/** + * @brief Get pin mask of provided pin within proprietery port + * @param name - desired pin + * @return uint32_t + */ +uint32_t hal_ll_gpio_pin_mask( hal_ll_pin_name_t name ); + +/** + * @brief Get base address of ports registers + * @param name - desired port + * @return uint32_t address of first regsiter + */ +uint32_t hal_ll_gpio_port_base( hal_ll_port_name_t name ); + +/** + * @brief Set pin as analog input + * @param port - port base address acquired from hal_gpio_ll_port_base + * @param pin_mask - pin mask acquired from hal_gpio_ll_pin_mask + * @return none + */ +void hal_ll_gpio_analog_input( uint32_t *port, uint16_t pin_mask ); + +/** + * @brief Set pin as digital input + * @param port - port base address acquired from hal_gpio_ll_port_base + * @param pin_mask - pin mask acquired from hal_gpio_ll_pin_mask + * @return none + */ +void hal_ll_gpio_digital_input( uint32_t *port, uint16_t pin_mask ); + +/** + * @brief Set pin as digital output + * @param port - port base address acquired from hal_gpio_ll_port_base + * @param pin_mask - pin mask acquired from hal_gpio_ll_pin_mask + * @return none + */ +void hal_ll_gpio_digital_output( uint32_t *port, uint16_t pin_mask ); + +/** + * @brief Initialize structure of pins associated to specific peripheral + * @param module - desired module pins structure + * @return none + */ +void hal_ll_gpio_module_struct_init( module_struct const *module, bool state ); + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_GPIO_PORT_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_1/hal_ll_gpio_constants.h b/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_1/hal_ll_gpio_constants.h new file mode 100644 index 000000000..ac120aad7 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_1/hal_ll_gpio_constants.h @@ -0,0 +1,153 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_gpio_constants.h + * @brief GPIO HAL LL macros. + */ + +#ifndef _HAL_LL_GPIO_CONSTANTS_H_ +#define _HAL_LL_GPIO_CONSTANTS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// Define any specific macros here +// REPLACE_MACROS // + +// Predefined macros if missing +#ifndef GPIO_OSPEEDER_OSPEEDR0 +#define GPIO_OSPEEDER_OSPEEDR0 ( uint32_t )0x03 +#endif +#ifndef GPIO_MODER_MODER0 +#define GPIO_MODER_MODER0 ( uint32_t )0x03 +#endif +#ifndef GPIO_OTYPER_OT_0 +#define GPIO_OTYPER_OT_0 ( uint32_t )0x01 +#endif +#ifndef GPIO_PUPDR_PUPDR0 +#define GPIO_PUPDR_PUPDR0 ( uint32_t )0x03 +#endif + +#ifndef GPIO_PIN_MASK_LOW +#define GPIO_PIN_MASK_LOW ( uint32_t )0x00FF +#endif +#ifndef GPIO_PIN_MASK_HIGH +#define GPIO_PIN_MASK_HIGH ( uint32_t )0xFF00 +#endif +#ifndef GPIO_PIN_MASK_ALL +#define GPIO_PIN_MASK_ALL ( uint32_t )0xFFFF +#endif + +#ifndef GPIO_AF_CONFIG_OFFSET +#define GPIO_AF_CONFIG_OFFSET ( uint32_t )20 +#endif +#ifndef GPIO_AF_MASK +#define GPIO_AF_MASK ( 0x0F ) +#endif +#ifndef GPIO_PIN_NAME_MASK +#define GPIO_PIN_NAME_MASK ( ( uint32_t )0xFF ) +#endif +#ifndef GPIO_AF_CONFIG_MASK +#define GPIO_AF_CONFIG_MASK ( ( uint32_t )0x0F << GPIO_AF_CONFIG_OFFSET ) +#endif + +#ifndef GPIO_CFG_MODE_ANALOG +#define GPIO_CFG_MODE_ANALOG ( uint32_t )0x1 +#endif +#ifndef GPIO_CFG_MODE_INPUT +#define GPIO_CFG_MODE_INPUT ( uint32_t )0x2 +#endif +#ifndef GPIO_CFG_MODE_OUTPUT +#define GPIO_CFG_MODE_OUTPUT ( uint32_t )0x4 +#endif +#ifndef GPIO_CFG_MODE_ALT_FUNCTION +#define GPIO_CFG_MODE_ALT_FUNCTION ( uint32_t )0x8 +#endif +#ifndef GPIO_CFG_OTYPE_PP +#define GPIO_CFG_OTYPE_PP ( uint32_t )0x10 +#endif +#ifndef GPIO_CFG_OTYPE_OD +#define GPIO_CFG_OTYPE_OD ( uint32_t )0x20 +#endif +#ifndef GPIO_CFG_PULL_NO +#define GPIO_CFG_PULL_NO ( uint32_t )0x40 +#endif +#ifndef GPIO_CFG_PULL_UP +#define GPIO_CFG_PULL_UP ( uint32_t )0x80 +#endif +#ifndef GPIO_CFG_PULL_DOWN +#define GPIO_CFG_PULL_DOWN ( uint32_t )0x100 +#endif +#ifndef GPIO_CFG_SPEED_LOW +#define GPIO_CFG_SPEED_LOW ( uint32_t )0x0 +#endif +#ifndef GPIO_CFG_SPEED_MEDIUM +#define GPIO_CFG_SPEED_MEDIUM ( uint32_t )0x200 +#endif +#ifndef GPIO_CFG_SPEED_HIGH +#define GPIO_CFG_SPEED_HIGH ( uint32_t )0x400 +#endif +#ifndef GPIO_CFG_SPEED_VERY_HIGH +#define GPIO_CFG_SPEED_VERY_HIGH ( uint32_t )0x800 +#endif +#ifndef GPIO_CFG_SPEED_MAX +#define GPIO_CFG_SPEED_MAX ( uint32_t )0x80000 +#endif + +#ifndef GPIO_AHB_SHIFT +#define GPIO_AHB_SHIFT 17 +#endif + +#ifndef GPIO_CFG_DIGITAL_OUTPUT +#define GPIO_CFG_DIGITAL_OUTPUT ( GPIO_CFG_MODE_OUTPUT | GPIO_CFG_SPEED_MAX | GPIO_CFG_OTYPE_PP ) +#endif +#ifndef GPIO_CFG_DIGITAL_INPUT +#define GPIO_CFG_DIGITAL_INPUT ( GPIO_CFG_MODE_INPUT | GPIO_CFG_PULL_NO ) +#endif +#ifndef GPIO_CFG_ANALOG_INPUT +#define GPIO_CFG_ANALOG_INPUT ( GPIO_CFG_MODE_ANALOG | GPIO_CFG_PULL_NO ) +#endif + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_GPIO_CONSTANTS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_1/hal_ll_gpio_struct_type.h b/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_1/hal_ll_gpio_struct_type.h new file mode 100644 index 000000000..0baa9dc5e --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_1/hal_ll_gpio_struct_type.h @@ -0,0 +1,76 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_gpio_struct_type.h + * @brief GPIO HAL LL register structure typedef. + */ + +#ifndef _HAL_LL_GPIO_STRUCT_TYPE_H_ +#define _HAL_LL_GPIO_STRUCT_TYPE_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include + +/** + * GPIO module registers access structure + */ +typedef struct hal_ll_gpio_base_handle +{ + uint32_t moder; + uint32_t otyper; + uint32_t ospeedr; + uint32_t pupdr; + uint32_t idr; + uint32_t odr; + uint32_t bsrr; + uint32_t lckr; + uint32_t afrl; + uint32_t afrh; + uint32_t brr; +} hal_ll_gpio_base_handle_t; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_GPIO_STRUCT_TYPE_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_160/hal_ll_gpio_constants.h b/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_160/hal_ll_gpio_constants.h new file mode 100644 index 000000000..ac120aad7 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_160/hal_ll_gpio_constants.h @@ -0,0 +1,153 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_gpio_constants.h + * @brief GPIO HAL LL macros. + */ + +#ifndef _HAL_LL_GPIO_CONSTANTS_H_ +#define _HAL_LL_GPIO_CONSTANTS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// Define any specific macros here +// REPLACE_MACROS // + +// Predefined macros if missing +#ifndef GPIO_OSPEEDER_OSPEEDR0 +#define GPIO_OSPEEDER_OSPEEDR0 ( uint32_t )0x03 +#endif +#ifndef GPIO_MODER_MODER0 +#define GPIO_MODER_MODER0 ( uint32_t )0x03 +#endif +#ifndef GPIO_OTYPER_OT_0 +#define GPIO_OTYPER_OT_0 ( uint32_t )0x01 +#endif +#ifndef GPIO_PUPDR_PUPDR0 +#define GPIO_PUPDR_PUPDR0 ( uint32_t )0x03 +#endif + +#ifndef GPIO_PIN_MASK_LOW +#define GPIO_PIN_MASK_LOW ( uint32_t )0x00FF +#endif +#ifndef GPIO_PIN_MASK_HIGH +#define GPIO_PIN_MASK_HIGH ( uint32_t )0xFF00 +#endif +#ifndef GPIO_PIN_MASK_ALL +#define GPIO_PIN_MASK_ALL ( uint32_t )0xFFFF +#endif + +#ifndef GPIO_AF_CONFIG_OFFSET +#define GPIO_AF_CONFIG_OFFSET ( uint32_t )20 +#endif +#ifndef GPIO_AF_MASK +#define GPIO_AF_MASK ( 0x0F ) +#endif +#ifndef GPIO_PIN_NAME_MASK +#define GPIO_PIN_NAME_MASK ( ( uint32_t )0xFF ) +#endif +#ifndef GPIO_AF_CONFIG_MASK +#define GPIO_AF_CONFIG_MASK ( ( uint32_t )0x0F << GPIO_AF_CONFIG_OFFSET ) +#endif + +#ifndef GPIO_CFG_MODE_ANALOG +#define GPIO_CFG_MODE_ANALOG ( uint32_t )0x1 +#endif +#ifndef GPIO_CFG_MODE_INPUT +#define GPIO_CFG_MODE_INPUT ( uint32_t )0x2 +#endif +#ifndef GPIO_CFG_MODE_OUTPUT +#define GPIO_CFG_MODE_OUTPUT ( uint32_t )0x4 +#endif +#ifndef GPIO_CFG_MODE_ALT_FUNCTION +#define GPIO_CFG_MODE_ALT_FUNCTION ( uint32_t )0x8 +#endif +#ifndef GPIO_CFG_OTYPE_PP +#define GPIO_CFG_OTYPE_PP ( uint32_t )0x10 +#endif +#ifndef GPIO_CFG_OTYPE_OD +#define GPIO_CFG_OTYPE_OD ( uint32_t )0x20 +#endif +#ifndef GPIO_CFG_PULL_NO +#define GPIO_CFG_PULL_NO ( uint32_t )0x40 +#endif +#ifndef GPIO_CFG_PULL_UP +#define GPIO_CFG_PULL_UP ( uint32_t )0x80 +#endif +#ifndef GPIO_CFG_PULL_DOWN +#define GPIO_CFG_PULL_DOWN ( uint32_t )0x100 +#endif +#ifndef GPIO_CFG_SPEED_LOW +#define GPIO_CFG_SPEED_LOW ( uint32_t )0x0 +#endif +#ifndef GPIO_CFG_SPEED_MEDIUM +#define GPIO_CFG_SPEED_MEDIUM ( uint32_t )0x200 +#endif +#ifndef GPIO_CFG_SPEED_HIGH +#define GPIO_CFG_SPEED_HIGH ( uint32_t )0x400 +#endif +#ifndef GPIO_CFG_SPEED_VERY_HIGH +#define GPIO_CFG_SPEED_VERY_HIGH ( uint32_t )0x800 +#endif +#ifndef GPIO_CFG_SPEED_MAX +#define GPIO_CFG_SPEED_MAX ( uint32_t )0x80000 +#endif + +#ifndef GPIO_AHB_SHIFT +#define GPIO_AHB_SHIFT 17 +#endif + +#ifndef GPIO_CFG_DIGITAL_OUTPUT +#define GPIO_CFG_DIGITAL_OUTPUT ( GPIO_CFG_MODE_OUTPUT | GPIO_CFG_SPEED_MAX | GPIO_CFG_OTYPE_PP ) +#endif +#ifndef GPIO_CFG_DIGITAL_INPUT +#define GPIO_CFG_DIGITAL_INPUT ( GPIO_CFG_MODE_INPUT | GPIO_CFG_PULL_NO ) +#endif +#ifndef GPIO_CFG_ANALOG_INPUT +#define GPIO_CFG_ANALOG_INPUT ( GPIO_CFG_MODE_ANALOG | GPIO_CFG_PULL_NO ) +#endif + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_GPIO_CONSTANTS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_160/hal_ll_gpio_struct_type.h b/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_160/hal_ll_gpio_struct_type.h new file mode 100644 index 000000000..0baa9dc5e --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_160/hal_ll_gpio_struct_type.h @@ -0,0 +1,76 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_gpio_struct_type.h + * @brief GPIO HAL LL register structure typedef. + */ + +#ifndef _HAL_LL_GPIO_STRUCT_TYPE_H_ +#define _HAL_LL_GPIO_STRUCT_TYPE_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include + +/** + * GPIO module registers access structure + */ +typedef struct hal_ll_gpio_base_handle +{ + uint32_t moder; + uint32_t otyper; + uint32_t ospeedr; + uint32_t pupdr; + uint32_t idr; + uint32_t odr; + uint32_t bsrr; + uint32_t lckr; + uint32_t afrl; + uint32_t afrh; + uint32_t brr; +} hal_ll_gpio_base_handle_t; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_GPIO_STRUCT_TYPE_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_161/hal_ll_gpio_constants.h b/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_161/hal_ll_gpio_constants.h new file mode 100644 index 000000000..ac120aad7 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_161/hal_ll_gpio_constants.h @@ -0,0 +1,153 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_gpio_constants.h + * @brief GPIO HAL LL macros. + */ + +#ifndef _HAL_LL_GPIO_CONSTANTS_H_ +#define _HAL_LL_GPIO_CONSTANTS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// Define any specific macros here +// REPLACE_MACROS // + +// Predefined macros if missing +#ifndef GPIO_OSPEEDER_OSPEEDR0 +#define GPIO_OSPEEDER_OSPEEDR0 ( uint32_t )0x03 +#endif +#ifndef GPIO_MODER_MODER0 +#define GPIO_MODER_MODER0 ( uint32_t )0x03 +#endif +#ifndef GPIO_OTYPER_OT_0 +#define GPIO_OTYPER_OT_0 ( uint32_t )0x01 +#endif +#ifndef GPIO_PUPDR_PUPDR0 +#define GPIO_PUPDR_PUPDR0 ( uint32_t )0x03 +#endif + +#ifndef GPIO_PIN_MASK_LOW +#define GPIO_PIN_MASK_LOW ( uint32_t )0x00FF +#endif +#ifndef GPIO_PIN_MASK_HIGH +#define GPIO_PIN_MASK_HIGH ( uint32_t )0xFF00 +#endif +#ifndef GPIO_PIN_MASK_ALL +#define GPIO_PIN_MASK_ALL ( uint32_t )0xFFFF +#endif + +#ifndef GPIO_AF_CONFIG_OFFSET +#define GPIO_AF_CONFIG_OFFSET ( uint32_t )20 +#endif +#ifndef GPIO_AF_MASK +#define GPIO_AF_MASK ( 0x0F ) +#endif +#ifndef GPIO_PIN_NAME_MASK +#define GPIO_PIN_NAME_MASK ( ( uint32_t )0xFF ) +#endif +#ifndef GPIO_AF_CONFIG_MASK +#define GPIO_AF_CONFIG_MASK ( ( uint32_t )0x0F << GPIO_AF_CONFIG_OFFSET ) +#endif + +#ifndef GPIO_CFG_MODE_ANALOG +#define GPIO_CFG_MODE_ANALOG ( uint32_t )0x1 +#endif +#ifndef GPIO_CFG_MODE_INPUT +#define GPIO_CFG_MODE_INPUT ( uint32_t )0x2 +#endif +#ifndef GPIO_CFG_MODE_OUTPUT +#define GPIO_CFG_MODE_OUTPUT ( uint32_t )0x4 +#endif +#ifndef GPIO_CFG_MODE_ALT_FUNCTION +#define GPIO_CFG_MODE_ALT_FUNCTION ( uint32_t )0x8 +#endif +#ifndef GPIO_CFG_OTYPE_PP +#define GPIO_CFG_OTYPE_PP ( uint32_t )0x10 +#endif +#ifndef GPIO_CFG_OTYPE_OD +#define GPIO_CFG_OTYPE_OD ( uint32_t )0x20 +#endif +#ifndef GPIO_CFG_PULL_NO +#define GPIO_CFG_PULL_NO ( uint32_t )0x40 +#endif +#ifndef GPIO_CFG_PULL_UP +#define GPIO_CFG_PULL_UP ( uint32_t )0x80 +#endif +#ifndef GPIO_CFG_PULL_DOWN +#define GPIO_CFG_PULL_DOWN ( uint32_t )0x100 +#endif +#ifndef GPIO_CFG_SPEED_LOW +#define GPIO_CFG_SPEED_LOW ( uint32_t )0x0 +#endif +#ifndef GPIO_CFG_SPEED_MEDIUM +#define GPIO_CFG_SPEED_MEDIUM ( uint32_t )0x200 +#endif +#ifndef GPIO_CFG_SPEED_HIGH +#define GPIO_CFG_SPEED_HIGH ( uint32_t )0x400 +#endif +#ifndef GPIO_CFG_SPEED_VERY_HIGH +#define GPIO_CFG_SPEED_VERY_HIGH ( uint32_t )0x800 +#endif +#ifndef GPIO_CFG_SPEED_MAX +#define GPIO_CFG_SPEED_MAX ( uint32_t )0x80000 +#endif + +#ifndef GPIO_AHB_SHIFT +#define GPIO_AHB_SHIFT 17 +#endif + +#ifndef GPIO_CFG_DIGITAL_OUTPUT +#define GPIO_CFG_DIGITAL_OUTPUT ( GPIO_CFG_MODE_OUTPUT | GPIO_CFG_SPEED_MAX | GPIO_CFG_OTYPE_PP ) +#endif +#ifndef GPIO_CFG_DIGITAL_INPUT +#define GPIO_CFG_DIGITAL_INPUT ( GPIO_CFG_MODE_INPUT | GPIO_CFG_PULL_NO ) +#endif +#ifndef GPIO_CFG_ANALOG_INPUT +#define GPIO_CFG_ANALOG_INPUT ( GPIO_CFG_MODE_ANALOG | GPIO_CFG_PULL_NO ) +#endif + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_GPIO_CONSTANTS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_161/hal_ll_gpio_struct_type.h b/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_161/hal_ll_gpio_struct_type.h new file mode 100644 index 000000000..0baa9dc5e --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_161/hal_ll_gpio_struct_type.h @@ -0,0 +1,76 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_gpio_struct_type.h + * @brief GPIO HAL LL register structure typedef. + */ + +#ifndef _HAL_LL_GPIO_STRUCT_TYPE_H_ +#define _HAL_LL_GPIO_STRUCT_TYPE_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include + +/** + * GPIO module registers access structure + */ +typedef struct hal_ll_gpio_base_handle +{ + uint32_t moder; + uint32_t otyper; + uint32_t ospeedr; + uint32_t pupdr; + uint32_t idr; + uint32_t odr; + uint32_t bsrr; + uint32_t lckr; + uint32_t afrl; + uint32_t afrh; + uint32_t brr; +} hal_ll_gpio_base_handle_t; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_GPIO_STRUCT_TYPE_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_2/hal_ll_gpio_constants.h b/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_2/hal_ll_gpio_constants.h new file mode 100644 index 000000000..ac120aad7 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_2/hal_ll_gpio_constants.h @@ -0,0 +1,153 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_gpio_constants.h + * @brief GPIO HAL LL macros. + */ + +#ifndef _HAL_LL_GPIO_CONSTANTS_H_ +#define _HAL_LL_GPIO_CONSTANTS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// Define any specific macros here +// REPLACE_MACROS // + +// Predefined macros if missing +#ifndef GPIO_OSPEEDER_OSPEEDR0 +#define GPIO_OSPEEDER_OSPEEDR0 ( uint32_t )0x03 +#endif +#ifndef GPIO_MODER_MODER0 +#define GPIO_MODER_MODER0 ( uint32_t )0x03 +#endif +#ifndef GPIO_OTYPER_OT_0 +#define GPIO_OTYPER_OT_0 ( uint32_t )0x01 +#endif +#ifndef GPIO_PUPDR_PUPDR0 +#define GPIO_PUPDR_PUPDR0 ( uint32_t )0x03 +#endif + +#ifndef GPIO_PIN_MASK_LOW +#define GPIO_PIN_MASK_LOW ( uint32_t )0x00FF +#endif +#ifndef GPIO_PIN_MASK_HIGH +#define GPIO_PIN_MASK_HIGH ( uint32_t )0xFF00 +#endif +#ifndef GPIO_PIN_MASK_ALL +#define GPIO_PIN_MASK_ALL ( uint32_t )0xFFFF +#endif + +#ifndef GPIO_AF_CONFIG_OFFSET +#define GPIO_AF_CONFIG_OFFSET ( uint32_t )20 +#endif +#ifndef GPIO_AF_MASK +#define GPIO_AF_MASK ( 0x0F ) +#endif +#ifndef GPIO_PIN_NAME_MASK +#define GPIO_PIN_NAME_MASK ( ( uint32_t )0xFF ) +#endif +#ifndef GPIO_AF_CONFIG_MASK +#define GPIO_AF_CONFIG_MASK ( ( uint32_t )0x0F << GPIO_AF_CONFIG_OFFSET ) +#endif + +#ifndef GPIO_CFG_MODE_ANALOG +#define GPIO_CFG_MODE_ANALOG ( uint32_t )0x1 +#endif +#ifndef GPIO_CFG_MODE_INPUT +#define GPIO_CFG_MODE_INPUT ( uint32_t )0x2 +#endif +#ifndef GPIO_CFG_MODE_OUTPUT +#define GPIO_CFG_MODE_OUTPUT ( uint32_t )0x4 +#endif +#ifndef GPIO_CFG_MODE_ALT_FUNCTION +#define GPIO_CFG_MODE_ALT_FUNCTION ( uint32_t )0x8 +#endif +#ifndef GPIO_CFG_OTYPE_PP +#define GPIO_CFG_OTYPE_PP ( uint32_t )0x10 +#endif +#ifndef GPIO_CFG_OTYPE_OD +#define GPIO_CFG_OTYPE_OD ( uint32_t )0x20 +#endif +#ifndef GPIO_CFG_PULL_NO +#define GPIO_CFG_PULL_NO ( uint32_t )0x40 +#endif +#ifndef GPIO_CFG_PULL_UP +#define GPIO_CFG_PULL_UP ( uint32_t )0x80 +#endif +#ifndef GPIO_CFG_PULL_DOWN +#define GPIO_CFG_PULL_DOWN ( uint32_t )0x100 +#endif +#ifndef GPIO_CFG_SPEED_LOW +#define GPIO_CFG_SPEED_LOW ( uint32_t )0x0 +#endif +#ifndef GPIO_CFG_SPEED_MEDIUM +#define GPIO_CFG_SPEED_MEDIUM ( uint32_t )0x200 +#endif +#ifndef GPIO_CFG_SPEED_HIGH +#define GPIO_CFG_SPEED_HIGH ( uint32_t )0x400 +#endif +#ifndef GPIO_CFG_SPEED_VERY_HIGH +#define GPIO_CFG_SPEED_VERY_HIGH ( uint32_t )0x800 +#endif +#ifndef GPIO_CFG_SPEED_MAX +#define GPIO_CFG_SPEED_MAX ( uint32_t )0x80000 +#endif + +#ifndef GPIO_AHB_SHIFT +#define GPIO_AHB_SHIFT 17 +#endif + +#ifndef GPIO_CFG_DIGITAL_OUTPUT +#define GPIO_CFG_DIGITAL_OUTPUT ( GPIO_CFG_MODE_OUTPUT | GPIO_CFG_SPEED_MAX | GPIO_CFG_OTYPE_PP ) +#endif +#ifndef GPIO_CFG_DIGITAL_INPUT +#define GPIO_CFG_DIGITAL_INPUT ( GPIO_CFG_MODE_INPUT | GPIO_CFG_PULL_NO ) +#endif +#ifndef GPIO_CFG_ANALOG_INPUT +#define GPIO_CFG_ANALOG_INPUT ( GPIO_CFG_MODE_ANALOG | GPIO_CFG_PULL_NO ) +#endif + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_GPIO_CONSTANTS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_2/hal_ll_gpio_struct_type.h b/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_2/hal_ll_gpio_struct_type.h new file mode 100644 index 000000000..0baa9dc5e --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_2/hal_ll_gpio_struct_type.h @@ -0,0 +1,76 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_gpio_struct_type.h + * @brief GPIO HAL LL register structure typedef. + */ + +#ifndef _HAL_LL_GPIO_STRUCT_TYPE_H_ +#define _HAL_LL_GPIO_STRUCT_TYPE_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include + +/** + * GPIO module registers access structure + */ +typedef struct hal_ll_gpio_base_handle +{ + uint32_t moder; + uint32_t otyper; + uint32_t ospeedr; + uint32_t pupdr; + uint32_t idr; + uint32_t odr; + uint32_t bsrr; + uint32_t lckr; + uint32_t afrl; + uint32_t afrh; + uint32_t brr; +} hal_ll_gpio_base_handle_t; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_GPIO_STRUCT_TYPE_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_74/hal_ll_gpio_constants.h b/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_74/hal_ll_gpio_constants.h new file mode 100644 index 000000000..ac120aad7 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_74/hal_ll_gpio_constants.h @@ -0,0 +1,153 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_gpio_constants.h + * @brief GPIO HAL LL macros. + */ + +#ifndef _HAL_LL_GPIO_CONSTANTS_H_ +#define _HAL_LL_GPIO_CONSTANTS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// Define any specific macros here +// REPLACE_MACROS // + +// Predefined macros if missing +#ifndef GPIO_OSPEEDER_OSPEEDR0 +#define GPIO_OSPEEDER_OSPEEDR0 ( uint32_t )0x03 +#endif +#ifndef GPIO_MODER_MODER0 +#define GPIO_MODER_MODER0 ( uint32_t )0x03 +#endif +#ifndef GPIO_OTYPER_OT_0 +#define GPIO_OTYPER_OT_0 ( uint32_t )0x01 +#endif +#ifndef GPIO_PUPDR_PUPDR0 +#define GPIO_PUPDR_PUPDR0 ( uint32_t )0x03 +#endif + +#ifndef GPIO_PIN_MASK_LOW +#define GPIO_PIN_MASK_LOW ( uint32_t )0x00FF +#endif +#ifndef GPIO_PIN_MASK_HIGH +#define GPIO_PIN_MASK_HIGH ( uint32_t )0xFF00 +#endif +#ifndef GPIO_PIN_MASK_ALL +#define GPIO_PIN_MASK_ALL ( uint32_t )0xFFFF +#endif + +#ifndef GPIO_AF_CONFIG_OFFSET +#define GPIO_AF_CONFIG_OFFSET ( uint32_t )20 +#endif +#ifndef GPIO_AF_MASK +#define GPIO_AF_MASK ( 0x0F ) +#endif +#ifndef GPIO_PIN_NAME_MASK +#define GPIO_PIN_NAME_MASK ( ( uint32_t )0xFF ) +#endif +#ifndef GPIO_AF_CONFIG_MASK +#define GPIO_AF_CONFIG_MASK ( ( uint32_t )0x0F << GPIO_AF_CONFIG_OFFSET ) +#endif + +#ifndef GPIO_CFG_MODE_ANALOG +#define GPIO_CFG_MODE_ANALOG ( uint32_t )0x1 +#endif +#ifndef GPIO_CFG_MODE_INPUT +#define GPIO_CFG_MODE_INPUT ( uint32_t )0x2 +#endif +#ifndef GPIO_CFG_MODE_OUTPUT +#define GPIO_CFG_MODE_OUTPUT ( uint32_t )0x4 +#endif +#ifndef GPIO_CFG_MODE_ALT_FUNCTION +#define GPIO_CFG_MODE_ALT_FUNCTION ( uint32_t )0x8 +#endif +#ifndef GPIO_CFG_OTYPE_PP +#define GPIO_CFG_OTYPE_PP ( uint32_t )0x10 +#endif +#ifndef GPIO_CFG_OTYPE_OD +#define GPIO_CFG_OTYPE_OD ( uint32_t )0x20 +#endif +#ifndef GPIO_CFG_PULL_NO +#define GPIO_CFG_PULL_NO ( uint32_t )0x40 +#endif +#ifndef GPIO_CFG_PULL_UP +#define GPIO_CFG_PULL_UP ( uint32_t )0x80 +#endif +#ifndef GPIO_CFG_PULL_DOWN +#define GPIO_CFG_PULL_DOWN ( uint32_t )0x100 +#endif +#ifndef GPIO_CFG_SPEED_LOW +#define GPIO_CFG_SPEED_LOW ( uint32_t )0x0 +#endif +#ifndef GPIO_CFG_SPEED_MEDIUM +#define GPIO_CFG_SPEED_MEDIUM ( uint32_t )0x200 +#endif +#ifndef GPIO_CFG_SPEED_HIGH +#define GPIO_CFG_SPEED_HIGH ( uint32_t )0x400 +#endif +#ifndef GPIO_CFG_SPEED_VERY_HIGH +#define GPIO_CFG_SPEED_VERY_HIGH ( uint32_t )0x800 +#endif +#ifndef GPIO_CFG_SPEED_MAX +#define GPIO_CFG_SPEED_MAX ( uint32_t )0x80000 +#endif + +#ifndef GPIO_AHB_SHIFT +#define GPIO_AHB_SHIFT 17 +#endif + +#ifndef GPIO_CFG_DIGITAL_OUTPUT +#define GPIO_CFG_DIGITAL_OUTPUT ( GPIO_CFG_MODE_OUTPUT | GPIO_CFG_SPEED_MAX | GPIO_CFG_OTYPE_PP ) +#endif +#ifndef GPIO_CFG_DIGITAL_INPUT +#define GPIO_CFG_DIGITAL_INPUT ( GPIO_CFG_MODE_INPUT | GPIO_CFG_PULL_NO ) +#endif +#ifndef GPIO_CFG_ANALOG_INPUT +#define GPIO_CFG_ANALOG_INPUT ( GPIO_CFG_MODE_ANALOG | GPIO_CFG_PULL_NO ) +#endif + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_GPIO_CONSTANTS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_74/hal_ll_gpio_struct_type.h b/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_74/hal_ll_gpio_struct_type.h new file mode 100644 index 000000000..0baa9dc5e --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_74/hal_ll_gpio_struct_type.h @@ -0,0 +1,76 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_gpio_struct_type.h + * @brief GPIO HAL LL register structure typedef. + */ + +#ifndef _HAL_LL_GPIO_STRUCT_TYPE_H_ +#define _HAL_LL_GPIO_STRUCT_TYPE_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include + +/** + * GPIO module registers access structure + */ +typedef struct hal_ll_gpio_base_handle +{ + uint32_t moder; + uint32_t otyper; + uint32_t ospeedr; + uint32_t pupdr; + uint32_t idr; + uint32_t odr; + uint32_t bsrr; + uint32_t lckr; + uint32_t afrl; + uint32_t afrh; + uint32_t brr; +} hal_ll_gpio_base_handle_t; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_GPIO_STRUCT_TYPE_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_75/hal_ll_gpio_constants.h b/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_75/hal_ll_gpio_constants.h new file mode 100644 index 000000000..ac120aad7 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_75/hal_ll_gpio_constants.h @@ -0,0 +1,153 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_gpio_constants.h + * @brief GPIO HAL LL macros. + */ + +#ifndef _HAL_LL_GPIO_CONSTANTS_H_ +#define _HAL_LL_GPIO_CONSTANTS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// Define any specific macros here +// REPLACE_MACROS // + +// Predefined macros if missing +#ifndef GPIO_OSPEEDER_OSPEEDR0 +#define GPIO_OSPEEDER_OSPEEDR0 ( uint32_t )0x03 +#endif +#ifndef GPIO_MODER_MODER0 +#define GPIO_MODER_MODER0 ( uint32_t )0x03 +#endif +#ifndef GPIO_OTYPER_OT_0 +#define GPIO_OTYPER_OT_0 ( uint32_t )0x01 +#endif +#ifndef GPIO_PUPDR_PUPDR0 +#define GPIO_PUPDR_PUPDR0 ( uint32_t )0x03 +#endif + +#ifndef GPIO_PIN_MASK_LOW +#define GPIO_PIN_MASK_LOW ( uint32_t )0x00FF +#endif +#ifndef GPIO_PIN_MASK_HIGH +#define GPIO_PIN_MASK_HIGH ( uint32_t )0xFF00 +#endif +#ifndef GPIO_PIN_MASK_ALL +#define GPIO_PIN_MASK_ALL ( uint32_t )0xFFFF +#endif + +#ifndef GPIO_AF_CONFIG_OFFSET +#define GPIO_AF_CONFIG_OFFSET ( uint32_t )20 +#endif +#ifndef GPIO_AF_MASK +#define GPIO_AF_MASK ( 0x0F ) +#endif +#ifndef GPIO_PIN_NAME_MASK +#define GPIO_PIN_NAME_MASK ( ( uint32_t )0xFF ) +#endif +#ifndef GPIO_AF_CONFIG_MASK +#define GPIO_AF_CONFIG_MASK ( ( uint32_t )0x0F << GPIO_AF_CONFIG_OFFSET ) +#endif + +#ifndef GPIO_CFG_MODE_ANALOG +#define GPIO_CFG_MODE_ANALOG ( uint32_t )0x1 +#endif +#ifndef GPIO_CFG_MODE_INPUT +#define GPIO_CFG_MODE_INPUT ( uint32_t )0x2 +#endif +#ifndef GPIO_CFG_MODE_OUTPUT +#define GPIO_CFG_MODE_OUTPUT ( uint32_t )0x4 +#endif +#ifndef GPIO_CFG_MODE_ALT_FUNCTION +#define GPIO_CFG_MODE_ALT_FUNCTION ( uint32_t )0x8 +#endif +#ifndef GPIO_CFG_OTYPE_PP +#define GPIO_CFG_OTYPE_PP ( uint32_t )0x10 +#endif +#ifndef GPIO_CFG_OTYPE_OD +#define GPIO_CFG_OTYPE_OD ( uint32_t )0x20 +#endif +#ifndef GPIO_CFG_PULL_NO +#define GPIO_CFG_PULL_NO ( uint32_t )0x40 +#endif +#ifndef GPIO_CFG_PULL_UP +#define GPIO_CFG_PULL_UP ( uint32_t )0x80 +#endif +#ifndef GPIO_CFG_PULL_DOWN +#define GPIO_CFG_PULL_DOWN ( uint32_t )0x100 +#endif +#ifndef GPIO_CFG_SPEED_LOW +#define GPIO_CFG_SPEED_LOW ( uint32_t )0x0 +#endif +#ifndef GPIO_CFG_SPEED_MEDIUM +#define GPIO_CFG_SPEED_MEDIUM ( uint32_t )0x200 +#endif +#ifndef GPIO_CFG_SPEED_HIGH +#define GPIO_CFG_SPEED_HIGH ( uint32_t )0x400 +#endif +#ifndef GPIO_CFG_SPEED_VERY_HIGH +#define GPIO_CFG_SPEED_VERY_HIGH ( uint32_t )0x800 +#endif +#ifndef GPIO_CFG_SPEED_MAX +#define GPIO_CFG_SPEED_MAX ( uint32_t )0x80000 +#endif + +#ifndef GPIO_AHB_SHIFT +#define GPIO_AHB_SHIFT 17 +#endif + +#ifndef GPIO_CFG_DIGITAL_OUTPUT +#define GPIO_CFG_DIGITAL_OUTPUT ( GPIO_CFG_MODE_OUTPUT | GPIO_CFG_SPEED_MAX | GPIO_CFG_OTYPE_PP ) +#endif +#ifndef GPIO_CFG_DIGITAL_INPUT +#define GPIO_CFG_DIGITAL_INPUT ( GPIO_CFG_MODE_INPUT | GPIO_CFG_PULL_NO ) +#endif +#ifndef GPIO_CFG_ANALOG_INPUT +#define GPIO_CFG_ANALOG_INPUT ( GPIO_CFG_MODE_ANALOG | GPIO_CFG_PULL_NO ) +#endif + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_GPIO_CONSTANTS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_75/hal_ll_gpio_struct_type.h b/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_75/hal_ll_gpio_struct_type.h new file mode 100644 index 000000000..0baa9dc5e --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_75/hal_ll_gpio_struct_type.h @@ -0,0 +1,76 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_gpio_struct_type.h + * @brief GPIO HAL LL register structure typedef. + */ + +#ifndef _HAL_LL_GPIO_STRUCT_TYPE_H_ +#define _HAL_LL_GPIO_STRUCT_TYPE_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include + +/** + * GPIO module registers access structure + */ +typedef struct hal_ll_gpio_base_handle +{ + uint32_t moder; + uint32_t otyper; + uint32_t ospeedr; + uint32_t pupdr; + uint32_t idr; + uint32_t odr; + uint32_t bsrr; + uint32_t lckr; + uint32_t afrl; + uint32_t afrh; + uint32_t brr; +} hal_ll_gpio_base_handle_t; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_GPIO_STRUCT_TYPE_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_80/hal_ll_gpio_constants.h b/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_80/hal_ll_gpio_constants.h new file mode 100644 index 000000000..ac120aad7 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_80/hal_ll_gpio_constants.h @@ -0,0 +1,153 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_gpio_constants.h + * @brief GPIO HAL LL macros. + */ + +#ifndef _HAL_LL_GPIO_CONSTANTS_H_ +#define _HAL_LL_GPIO_CONSTANTS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// Define any specific macros here +// REPLACE_MACROS // + +// Predefined macros if missing +#ifndef GPIO_OSPEEDER_OSPEEDR0 +#define GPIO_OSPEEDER_OSPEEDR0 ( uint32_t )0x03 +#endif +#ifndef GPIO_MODER_MODER0 +#define GPIO_MODER_MODER0 ( uint32_t )0x03 +#endif +#ifndef GPIO_OTYPER_OT_0 +#define GPIO_OTYPER_OT_0 ( uint32_t )0x01 +#endif +#ifndef GPIO_PUPDR_PUPDR0 +#define GPIO_PUPDR_PUPDR0 ( uint32_t )0x03 +#endif + +#ifndef GPIO_PIN_MASK_LOW +#define GPIO_PIN_MASK_LOW ( uint32_t )0x00FF +#endif +#ifndef GPIO_PIN_MASK_HIGH +#define GPIO_PIN_MASK_HIGH ( uint32_t )0xFF00 +#endif +#ifndef GPIO_PIN_MASK_ALL +#define GPIO_PIN_MASK_ALL ( uint32_t )0xFFFF +#endif + +#ifndef GPIO_AF_CONFIG_OFFSET +#define GPIO_AF_CONFIG_OFFSET ( uint32_t )20 +#endif +#ifndef GPIO_AF_MASK +#define GPIO_AF_MASK ( 0x0F ) +#endif +#ifndef GPIO_PIN_NAME_MASK +#define GPIO_PIN_NAME_MASK ( ( uint32_t )0xFF ) +#endif +#ifndef GPIO_AF_CONFIG_MASK +#define GPIO_AF_CONFIG_MASK ( ( uint32_t )0x0F << GPIO_AF_CONFIG_OFFSET ) +#endif + +#ifndef GPIO_CFG_MODE_ANALOG +#define GPIO_CFG_MODE_ANALOG ( uint32_t )0x1 +#endif +#ifndef GPIO_CFG_MODE_INPUT +#define GPIO_CFG_MODE_INPUT ( uint32_t )0x2 +#endif +#ifndef GPIO_CFG_MODE_OUTPUT +#define GPIO_CFG_MODE_OUTPUT ( uint32_t )0x4 +#endif +#ifndef GPIO_CFG_MODE_ALT_FUNCTION +#define GPIO_CFG_MODE_ALT_FUNCTION ( uint32_t )0x8 +#endif +#ifndef GPIO_CFG_OTYPE_PP +#define GPIO_CFG_OTYPE_PP ( uint32_t )0x10 +#endif +#ifndef GPIO_CFG_OTYPE_OD +#define GPIO_CFG_OTYPE_OD ( uint32_t )0x20 +#endif +#ifndef GPIO_CFG_PULL_NO +#define GPIO_CFG_PULL_NO ( uint32_t )0x40 +#endif +#ifndef GPIO_CFG_PULL_UP +#define GPIO_CFG_PULL_UP ( uint32_t )0x80 +#endif +#ifndef GPIO_CFG_PULL_DOWN +#define GPIO_CFG_PULL_DOWN ( uint32_t )0x100 +#endif +#ifndef GPIO_CFG_SPEED_LOW +#define GPIO_CFG_SPEED_LOW ( uint32_t )0x0 +#endif +#ifndef GPIO_CFG_SPEED_MEDIUM +#define GPIO_CFG_SPEED_MEDIUM ( uint32_t )0x200 +#endif +#ifndef GPIO_CFG_SPEED_HIGH +#define GPIO_CFG_SPEED_HIGH ( uint32_t )0x400 +#endif +#ifndef GPIO_CFG_SPEED_VERY_HIGH +#define GPIO_CFG_SPEED_VERY_HIGH ( uint32_t )0x800 +#endif +#ifndef GPIO_CFG_SPEED_MAX +#define GPIO_CFG_SPEED_MAX ( uint32_t )0x80000 +#endif + +#ifndef GPIO_AHB_SHIFT +#define GPIO_AHB_SHIFT 17 +#endif + +#ifndef GPIO_CFG_DIGITAL_OUTPUT +#define GPIO_CFG_DIGITAL_OUTPUT ( GPIO_CFG_MODE_OUTPUT | GPIO_CFG_SPEED_MAX | GPIO_CFG_OTYPE_PP ) +#endif +#ifndef GPIO_CFG_DIGITAL_INPUT +#define GPIO_CFG_DIGITAL_INPUT ( GPIO_CFG_MODE_INPUT | GPIO_CFG_PULL_NO ) +#endif +#ifndef GPIO_CFG_ANALOG_INPUT +#define GPIO_CFG_ANALOG_INPUT ( GPIO_CFG_MODE_ANALOG | GPIO_CFG_PULL_NO ) +#endif + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_GPIO_CONSTANTS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_80/hal_ll_gpio_struct_type.h b/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_80/hal_ll_gpio_struct_type.h new file mode 100644 index 000000000..0baa9dc5e --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_80/hal_ll_gpio_struct_type.h @@ -0,0 +1,76 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_gpio_struct_type.h + * @brief GPIO HAL LL register structure typedef. + */ + +#ifndef _HAL_LL_GPIO_STRUCT_TYPE_H_ +#define _HAL_LL_GPIO_STRUCT_TYPE_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include + +/** + * GPIO module registers access structure + */ +typedef struct hal_ll_gpio_base_handle +{ + uint32_t moder; + uint32_t otyper; + uint32_t ospeedr; + uint32_t pupdr; + uint32_t idr; + uint32_t odr; + uint32_t bsrr; + uint32_t lckr; + uint32_t afrl; + uint32_t afrh; + uint32_t brr; +} hal_ll_gpio_base_handle_t; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_GPIO_STRUCT_TYPE_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_81/hal_ll_gpio_constants.h b/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_81/hal_ll_gpio_constants.h new file mode 100644 index 000000000..ac120aad7 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_81/hal_ll_gpio_constants.h @@ -0,0 +1,153 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_gpio_constants.h + * @brief GPIO HAL LL macros. + */ + +#ifndef _HAL_LL_GPIO_CONSTANTS_H_ +#define _HAL_LL_GPIO_CONSTANTS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// Define any specific macros here +// REPLACE_MACROS // + +// Predefined macros if missing +#ifndef GPIO_OSPEEDER_OSPEEDR0 +#define GPIO_OSPEEDER_OSPEEDR0 ( uint32_t )0x03 +#endif +#ifndef GPIO_MODER_MODER0 +#define GPIO_MODER_MODER0 ( uint32_t )0x03 +#endif +#ifndef GPIO_OTYPER_OT_0 +#define GPIO_OTYPER_OT_0 ( uint32_t )0x01 +#endif +#ifndef GPIO_PUPDR_PUPDR0 +#define GPIO_PUPDR_PUPDR0 ( uint32_t )0x03 +#endif + +#ifndef GPIO_PIN_MASK_LOW +#define GPIO_PIN_MASK_LOW ( uint32_t )0x00FF +#endif +#ifndef GPIO_PIN_MASK_HIGH +#define GPIO_PIN_MASK_HIGH ( uint32_t )0xFF00 +#endif +#ifndef GPIO_PIN_MASK_ALL +#define GPIO_PIN_MASK_ALL ( uint32_t )0xFFFF +#endif + +#ifndef GPIO_AF_CONFIG_OFFSET +#define GPIO_AF_CONFIG_OFFSET ( uint32_t )20 +#endif +#ifndef GPIO_AF_MASK +#define GPIO_AF_MASK ( 0x0F ) +#endif +#ifndef GPIO_PIN_NAME_MASK +#define GPIO_PIN_NAME_MASK ( ( uint32_t )0xFF ) +#endif +#ifndef GPIO_AF_CONFIG_MASK +#define GPIO_AF_CONFIG_MASK ( ( uint32_t )0x0F << GPIO_AF_CONFIG_OFFSET ) +#endif + +#ifndef GPIO_CFG_MODE_ANALOG +#define GPIO_CFG_MODE_ANALOG ( uint32_t )0x1 +#endif +#ifndef GPIO_CFG_MODE_INPUT +#define GPIO_CFG_MODE_INPUT ( uint32_t )0x2 +#endif +#ifndef GPIO_CFG_MODE_OUTPUT +#define GPIO_CFG_MODE_OUTPUT ( uint32_t )0x4 +#endif +#ifndef GPIO_CFG_MODE_ALT_FUNCTION +#define GPIO_CFG_MODE_ALT_FUNCTION ( uint32_t )0x8 +#endif +#ifndef GPIO_CFG_OTYPE_PP +#define GPIO_CFG_OTYPE_PP ( uint32_t )0x10 +#endif +#ifndef GPIO_CFG_OTYPE_OD +#define GPIO_CFG_OTYPE_OD ( uint32_t )0x20 +#endif +#ifndef GPIO_CFG_PULL_NO +#define GPIO_CFG_PULL_NO ( uint32_t )0x40 +#endif +#ifndef GPIO_CFG_PULL_UP +#define GPIO_CFG_PULL_UP ( uint32_t )0x80 +#endif +#ifndef GPIO_CFG_PULL_DOWN +#define GPIO_CFG_PULL_DOWN ( uint32_t )0x100 +#endif +#ifndef GPIO_CFG_SPEED_LOW +#define GPIO_CFG_SPEED_LOW ( uint32_t )0x0 +#endif +#ifndef GPIO_CFG_SPEED_MEDIUM +#define GPIO_CFG_SPEED_MEDIUM ( uint32_t )0x200 +#endif +#ifndef GPIO_CFG_SPEED_HIGH +#define GPIO_CFG_SPEED_HIGH ( uint32_t )0x400 +#endif +#ifndef GPIO_CFG_SPEED_VERY_HIGH +#define GPIO_CFG_SPEED_VERY_HIGH ( uint32_t )0x800 +#endif +#ifndef GPIO_CFG_SPEED_MAX +#define GPIO_CFG_SPEED_MAX ( uint32_t )0x80000 +#endif + +#ifndef GPIO_AHB_SHIFT +#define GPIO_AHB_SHIFT 17 +#endif + +#ifndef GPIO_CFG_DIGITAL_OUTPUT +#define GPIO_CFG_DIGITAL_OUTPUT ( GPIO_CFG_MODE_OUTPUT | GPIO_CFG_SPEED_MAX | GPIO_CFG_OTYPE_PP ) +#endif +#ifndef GPIO_CFG_DIGITAL_INPUT +#define GPIO_CFG_DIGITAL_INPUT ( GPIO_CFG_MODE_INPUT | GPIO_CFG_PULL_NO ) +#endif +#ifndef GPIO_CFG_ANALOG_INPUT +#define GPIO_CFG_ANALOG_INPUT ( GPIO_CFG_MODE_ANALOG | GPIO_CFG_PULL_NO ) +#endif + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_GPIO_CONSTANTS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_81/hal_ll_gpio_struct_type.h b/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_81/hal_ll_gpio_struct_type.h new file mode 100644 index 000000000..0baa9dc5e --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_81/hal_ll_gpio_struct_type.h @@ -0,0 +1,76 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_gpio_struct_type.h + * @brief GPIO HAL LL register structure typedef. + */ + +#ifndef _HAL_LL_GPIO_STRUCT_TYPE_H_ +#define _HAL_LL_GPIO_STRUCT_TYPE_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include + +/** + * GPIO module registers access structure + */ +typedef struct hal_ll_gpio_base_handle +{ + uint32_t moder; + uint32_t otyper; + uint32_t ospeedr; + uint32_t pupdr; + uint32_t idr; + uint32_t odr; + uint32_t bsrr; + uint32_t lckr; + uint32_t afrl; + uint32_t afrh; + uint32_t brr; +} hal_ll_gpio_base_handle_t; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_GPIO_STRUCT_TYPE_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_82/hal_ll_gpio_constants.h b/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_82/hal_ll_gpio_constants.h new file mode 100644 index 000000000..ac120aad7 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_82/hal_ll_gpio_constants.h @@ -0,0 +1,153 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_gpio_constants.h + * @brief GPIO HAL LL macros. + */ + +#ifndef _HAL_LL_GPIO_CONSTANTS_H_ +#define _HAL_LL_GPIO_CONSTANTS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// Define any specific macros here +// REPLACE_MACROS // + +// Predefined macros if missing +#ifndef GPIO_OSPEEDER_OSPEEDR0 +#define GPIO_OSPEEDER_OSPEEDR0 ( uint32_t )0x03 +#endif +#ifndef GPIO_MODER_MODER0 +#define GPIO_MODER_MODER0 ( uint32_t )0x03 +#endif +#ifndef GPIO_OTYPER_OT_0 +#define GPIO_OTYPER_OT_0 ( uint32_t )0x01 +#endif +#ifndef GPIO_PUPDR_PUPDR0 +#define GPIO_PUPDR_PUPDR0 ( uint32_t )0x03 +#endif + +#ifndef GPIO_PIN_MASK_LOW +#define GPIO_PIN_MASK_LOW ( uint32_t )0x00FF +#endif +#ifndef GPIO_PIN_MASK_HIGH +#define GPIO_PIN_MASK_HIGH ( uint32_t )0xFF00 +#endif +#ifndef GPIO_PIN_MASK_ALL +#define GPIO_PIN_MASK_ALL ( uint32_t )0xFFFF +#endif + +#ifndef GPIO_AF_CONFIG_OFFSET +#define GPIO_AF_CONFIG_OFFSET ( uint32_t )20 +#endif +#ifndef GPIO_AF_MASK +#define GPIO_AF_MASK ( 0x0F ) +#endif +#ifndef GPIO_PIN_NAME_MASK +#define GPIO_PIN_NAME_MASK ( ( uint32_t )0xFF ) +#endif +#ifndef GPIO_AF_CONFIG_MASK +#define GPIO_AF_CONFIG_MASK ( ( uint32_t )0x0F << GPIO_AF_CONFIG_OFFSET ) +#endif + +#ifndef GPIO_CFG_MODE_ANALOG +#define GPIO_CFG_MODE_ANALOG ( uint32_t )0x1 +#endif +#ifndef GPIO_CFG_MODE_INPUT +#define GPIO_CFG_MODE_INPUT ( uint32_t )0x2 +#endif +#ifndef GPIO_CFG_MODE_OUTPUT +#define GPIO_CFG_MODE_OUTPUT ( uint32_t )0x4 +#endif +#ifndef GPIO_CFG_MODE_ALT_FUNCTION +#define GPIO_CFG_MODE_ALT_FUNCTION ( uint32_t )0x8 +#endif +#ifndef GPIO_CFG_OTYPE_PP +#define GPIO_CFG_OTYPE_PP ( uint32_t )0x10 +#endif +#ifndef GPIO_CFG_OTYPE_OD +#define GPIO_CFG_OTYPE_OD ( uint32_t )0x20 +#endif +#ifndef GPIO_CFG_PULL_NO +#define GPIO_CFG_PULL_NO ( uint32_t )0x40 +#endif +#ifndef GPIO_CFG_PULL_UP +#define GPIO_CFG_PULL_UP ( uint32_t )0x80 +#endif +#ifndef GPIO_CFG_PULL_DOWN +#define GPIO_CFG_PULL_DOWN ( uint32_t )0x100 +#endif +#ifndef GPIO_CFG_SPEED_LOW +#define GPIO_CFG_SPEED_LOW ( uint32_t )0x0 +#endif +#ifndef GPIO_CFG_SPEED_MEDIUM +#define GPIO_CFG_SPEED_MEDIUM ( uint32_t )0x200 +#endif +#ifndef GPIO_CFG_SPEED_HIGH +#define GPIO_CFG_SPEED_HIGH ( uint32_t )0x400 +#endif +#ifndef GPIO_CFG_SPEED_VERY_HIGH +#define GPIO_CFG_SPEED_VERY_HIGH ( uint32_t )0x800 +#endif +#ifndef GPIO_CFG_SPEED_MAX +#define GPIO_CFG_SPEED_MAX ( uint32_t )0x80000 +#endif + +#ifndef GPIO_AHB_SHIFT +#define GPIO_AHB_SHIFT 17 +#endif + +#ifndef GPIO_CFG_DIGITAL_OUTPUT +#define GPIO_CFG_DIGITAL_OUTPUT ( GPIO_CFG_MODE_OUTPUT | GPIO_CFG_SPEED_MAX | GPIO_CFG_OTYPE_PP ) +#endif +#ifndef GPIO_CFG_DIGITAL_INPUT +#define GPIO_CFG_DIGITAL_INPUT ( GPIO_CFG_MODE_INPUT | GPIO_CFG_PULL_NO ) +#endif +#ifndef GPIO_CFG_ANALOG_INPUT +#define GPIO_CFG_ANALOG_INPUT ( GPIO_CFG_MODE_ANALOG | GPIO_CFG_PULL_NO ) +#endif + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_GPIO_CONSTANTS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_82/hal_ll_gpio_struct_type.h b/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_82/hal_ll_gpio_struct_type.h new file mode 100644 index 000000000..0baa9dc5e --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_82/hal_ll_gpio_struct_type.h @@ -0,0 +1,76 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_gpio_struct_type.h + * @brief GPIO HAL LL register structure typedef. + */ + +#ifndef _HAL_LL_GPIO_STRUCT_TYPE_H_ +#define _HAL_LL_GPIO_STRUCT_TYPE_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include + +/** + * GPIO module registers access structure + */ +typedef struct hal_ll_gpio_base_handle +{ + uint32_t moder; + uint32_t otyper; + uint32_t ospeedr; + uint32_t pupdr; + uint32_t idr; + uint32_t odr; + uint32_t bsrr; + uint32_t lckr; + uint32_t afrl; + uint32_t afrh; + uint32_t brr; +} hal_ll_gpio_base_handle_t; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_GPIO_STRUCT_TYPE_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_83/hal_ll_gpio_constants.h b/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_83/hal_ll_gpio_constants.h new file mode 100644 index 000000000..ac120aad7 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_83/hal_ll_gpio_constants.h @@ -0,0 +1,153 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_gpio_constants.h + * @brief GPIO HAL LL macros. + */ + +#ifndef _HAL_LL_GPIO_CONSTANTS_H_ +#define _HAL_LL_GPIO_CONSTANTS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// Define any specific macros here +// REPLACE_MACROS // + +// Predefined macros if missing +#ifndef GPIO_OSPEEDER_OSPEEDR0 +#define GPIO_OSPEEDER_OSPEEDR0 ( uint32_t )0x03 +#endif +#ifndef GPIO_MODER_MODER0 +#define GPIO_MODER_MODER0 ( uint32_t )0x03 +#endif +#ifndef GPIO_OTYPER_OT_0 +#define GPIO_OTYPER_OT_0 ( uint32_t )0x01 +#endif +#ifndef GPIO_PUPDR_PUPDR0 +#define GPIO_PUPDR_PUPDR0 ( uint32_t )0x03 +#endif + +#ifndef GPIO_PIN_MASK_LOW +#define GPIO_PIN_MASK_LOW ( uint32_t )0x00FF +#endif +#ifndef GPIO_PIN_MASK_HIGH +#define GPIO_PIN_MASK_HIGH ( uint32_t )0xFF00 +#endif +#ifndef GPIO_PIN_MASK_ALL +#define GPIO_PIN_MASK_ALL ( uint32_t )0xFFFF +#endif + +#ifndef GPIO_AF_CONFIG_OFFSET +#define GPIO_AF_CONFIG_OFFSET ( uint32_t )20 +#endif +#ifndef GPIO_AF_MASK +#define GPIO_AF_MASK ( 0x0F ) +#endif +#ifndef GPIO_PIN_NAME_MASK +#define GPIO_PIN_NAME_MASK ( ( uint32_t )0xFF ) +#endif +#ifndef GPIO_AF_CONFIG_MASK +#define GPIO_AF_CONFIG_MASK ( ( uint32_t )0x0F << GPIO_AF_CONFIG_OFFSET ) +#endif + +#ifndef GPIO_CFG_MODE_ANALOG +#define GPIO_CFG_MODE_ANALOG ( uint32_t )0x1 +#endif +#ifndef GPIO_CFG_MODE_INPUT +#define GPIO_CFG_MODE_INPUT ( uint32_t )0x2 +#endif +#ifndef GPIO_CFG_MODE_OUTPUT +#define GPIO_CFG_MODE_OUTPUT ( uint32_t )0x4 +#endif +#ifndef GPIO_CFG_MODE_ALT_FUNCTION +#define GPIO_CFG_MODE_ALT_FUNCTION ( uint32_t )0x8 +#endif +#ifndef GPIO_CFG_OTYPE_PP +#define GPIO_CFG_OTYPE_PP ( uint32_t )0x10 +#endif +#ifndef GPIO_CFG_OTYPE_OD +#define GPIO_CFG_OTYPE_OD ( uint32_t )0x20 +#endif +#ifndef GPIO_CFG_PULL_NO +#define GPIO_CFG_PULL_NO ( uint32_t )0x40 +#endif +#ifndef GPIO_CFG_PULL_UP +#define GPIO_CFG_PULL_UP ( uint32_t )0x80 +#endif +#ifndef GPIO_CFG_PULL_DOWN +#define GPIO_CFG_PULL_DOWN ( uint32_t )0x100 +#endif +#ifndef GPIO_CFG_SPEED_LOW +#define GPIO_CFG_SPEED_LOW ( uint32_t )0x0 +#endif +#ifndef GPIO_CFG_SPEED_MEDIUM +#define GPIO_CFG_SPEED_MEDIUM ( uint32_t )0x200 +#endif +#ifndef GPIO_CFG_SPEED_HIGH +#define GPIO_CFG_SPEED_HIGH ( uint32_t )0x400 +#endif +#ifndef GPIO_CFG_SPEED_VERY_HIGH +#define GPIO_CFG_SPEED_VERY_HIGH ( uint32_t )0x800 +#endif +#ifndef GPIO_CFG_SPEED_MAX +#define GPIO_CFG_SPEED_MAX ( uint32_t )0x80000 +#endif + +#ifndef GPIO_AHB_SHIFT +#define GPIO_AHB_SHIFT 17 +#endif + +#ifndef GPIO_CFG_DIGITAL_OUTPUT +#define GPIO_CFG_DIGITAL_OUTPUT ( GPIO_CFG_MODE_OUTPUT | GPIO_CFG_SPEED_MAX | GPIO_CFG_OTYPE_PP ) +#endif +#ifndef GPIO_CFG_DIGITAL_INPUT +#define GPIO_CFG_DIGITAL_INPUT ( GPIO_CFG_MODE_INPUT | GPIO_CFG_PULL_NO ) +#endif +#ifndef GPIO_CFG_ANALOG_INPUT +#define GPIO_CFG_ANALOG_INPUT ( GPIO_CFG_MODE_ANALOG | GPIO_CFG_PULL_NO ) +#endif + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_GPIO_CONSTANTS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_83/hal_ll_gpio_struct_type.h b/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_83/hal_ll_gpio_struct_type.h new file mode 100644 index 000000000..0baa9dc5e --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_83/hal_ll_gpio_struct_type.h @@ -0,0 +1,76 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_gpio_struct_type.h + * @brief GPIO HAL LL register structure typedef. + */ + +#ifndef _HAL_LL_GPIO_STRUCT_TYPE_H_ +#define _HAL_LL_GPIO_STRUCT_TYPE_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include + +/** + * GPIO module registers access structure + */ +typedef struct hal_ll_gpio_base_handle +{ + uint32_t moder; + uint32_t otyper; + uint32_t ospeedr; + uint32_t pupdr; + uint32_t idr; + uint32_t odr; + uint32_t bsrr; + uint32_t lckr; + uint32_t afrl; + uint32_t afrh; + uint32_t brr; +} hal_ll_gpio_base_handle_t; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_GPIO_STRUCT_TYPE_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_84/hal_ll_gpio_constants.h b/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_84/hal_ll_gpio_constants.h new file mode 100644 index 000000000..ac120aad7 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_84/hal_ll_gpio_constants.h @@ -0,0 +1,153 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_gpio_constants.h + * @brief GPIO HAL LL macros. + */ + +#ifndef _HAL_LL_GPIO_CONSTANTS_H_ +#define _HAL_LL_GPIO_CONSTANTS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// Define any specific macros here +// REPLACE_MACROS // + +// Predefined macros if missing +#ifndef GPIO_OSPEEDER_OSPEEDR0 +#define GPIO_OSPEEDER_OSPEEDR0 ( uint32_t )0x03 +#endif +#ifndef GPIO_MODER_MODER0 +#define GPIO_MODER_MODER0 ( uint32_t )0x03 +#endif +#ifndef GPIO_OTYPER_OT_0 +#define GPIO_OTYPER_OT_0 ( uint32_t )0x01 +#endif +#ifndef GPIO_PUPDR_PUPDR0 +#define GPIO_PUPDR_PUPDR0 ( uint32_t )0x03 +#endif + +#ifndef GPIO_PIN_MASK_LOW +#define GPIO_PIN_MASK_LOW ( uint32_t )0x00FF +#endif +#ifndef GPIO_PIN_MASK_HIGH +#define GPIO_PIN_MASK_HIGH ( uint32_t )0xFF00 +#endif +#ifndef GPIO_PIN_MASK_ALL +#define GPIO_PIN_MASK_ALL ( uint32_t )0xFFFF +#endif + +#ifndef GPIO_AF_CONFIG_OFFSET +#define GPIO_AF_CONFIG_OFFSET ( uint32_t )20 +#endif +#ifndef GPIO_AF_MASK +#define GPIO_AF_MASK ( 0x0F ) +#endif +#ifndef GPIO_PIN_NAME_MASK +#define GPIO_PIN_NAME_MASK ( ( uint32_t )0xFF ) +#endif +#ifndef GPIO_AF_CONFIG_MASK +#define GPIO_AF_CONFIG_MASK ( ( uint32_t )0x0F << GPIO_AF_CONFIG_OFFSET ) +#endif + +#ifndef GPIO_CFG_MODE_ANALOG +#define GPIO_CFG_MODE_ANALOG ( uint32_t )0x1 +#endif +#ifndef GPIO_CFG_MODE_INPUT +#define GPIO_CFG_MODE_INPUT ( uint32_t )0x2 +#endif +#ifndef GPIO_CFG_MODE_OUTPUT +#define GPIO_CFG_MODE_OUTPUT ( uint32_t )0x4 +#endif +#ifndef GPIO_CFG_MODE_ALT_FUNCTION +#define GPIO_CFG_MODE_ALT_FUNCTION ( uint32_t )0x8 +#endif +#ifndef GPIO_CFG_OTYPE_PP +#define GPIO_CFG_OTYPE_PP ( uint32_t )0x10 +#endif +#ifndef GPIO_CFG_OTYPE_OD +#define GPIO_CFG_OTYPE_OD ( uint32_t )0x20 +#endif +#ifndef GPIO_CFG_PULL_NO +#define GPIO_CFG_PULL_NO ( uint32_t )0x40 +#endif +#ifndef GPIO_CFG_PULL_UP +#define GPIO_CFG_PULL_UP ( uint32_t )0x80 +#endif +#ifndef GPIO_CFG_PULL_DOWN +#define GPIO_CFG_PULL_DOWN ( uint32_t )0x100 +#endif +#ifndef GPIO_CFG_SPEED_LOW +#define GPIO_CFG_SPEED_LOW ( uint32_t )0x0 +#endif +#ifndef GPIO_CFG_SPEED_MEDIUM +#define GPIO_CFG_SPEED_MEDIUM ( uint32_t )0x200 +#endif +#ifndef GPIO_CFG_SPEED_HIGH +#define GPIO_CFG_SPEED_HIGH ( uint32_t )0x400 +#endif +#ifndef GPIO_CFG_SPEED_VERY_HIGH +#define GPIO_CFG_SPEED_VERY_HIGH ( uint32_t )0x800 +#endif +#ifndef GPIO_CFG_SPEED_MAX +#define GPIO_CFG_SPEED_MAX ( uint32_t )0x80000 +#endif + +#ifndef GPIO_AHB_SHIFT +#define GPIO_AHB_SHIFT 17 +#endif + +#ifndef GPIO_CFG_DIGITAL_OUTPUT +#define GPIO_CFG_DIGITAL_OUTPUT ( GPIO_CFG_MODE_OUTPUT | GPIO_CFG_SPEED_MAX | GPIO_CFG_OTYPE_PP ) +#endif +#ifndef GPIO_CFG_DIGITAL_INPUT +#define GPIO_CFG_DIGITAL_INPUT ( GPIO_CFG_MODE_INPUT | GPIO_CFG_PULL_NO ) +#endif +#ifndef GPIO_CFG_ANALOG_INPUT +#define GPIO_CFG_ANALOG_INPUT ( GPIO_CFG_MODE_ANALOG | GPIO_CFG_PULL_NO ) +#endif + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_GPIO_CONSTANTS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_84/hal_ll_gpio_struct_type.h b/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_84/hal_ll_gpio_struct_type.h new file mode 100644 index 000000000..0baa9dc5e --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_84/hal_ll_gpio_struct_type.h @@ -0,0 +1,76 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_gpio_struct_type.h + * @brief GPIO HAL LL register structure typedef. + */ + +#ifndef _HAL_LL_GPIO_STRUCT_TYPE_H_ +#define _HAL_LL_GPIO_STRUCT_TYPE_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include + +/** + * GPIO module registers access structure + */ +typedef struct hal_ll_gpio_base_handle +{ + uint32_t moder; + uint32_t otyper; + uint32_t ospeedr; + uint32_t pupdr; + uint32_t idr; + uint32_t odr; + uint32_t bsrr; + uint32_t lckr; + uint32_t afrl; + uint32_t afrh; + uint32_t brr; +} hal_ll_gpio_base_handle_t; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_GPIO_STRUCT_TYPE_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_85/hal_ll_gpio_constants.h b/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_85/hal_ll_gpio_constants.h new file mode 100644 index 000000000..ac120aad7 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_85/hal_ll_gpio_constants.h @@ -0,0 +1,153 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_gpio_constants.h + * @brief GPIO HAL LL macros. + */ + +#ifndef _HAL_LL_GPIO_CONSTANTS_H_ +#define _HAL_LL_GPIO_CONSTANTS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// Define any specific macros here +// REPLACE_MACROS // + +// Predefined macros if missing +#ifndef GPIO_OSPEEDER_OSPEEDR0 +#define GPIO_OSPEEDER_OSPEEDR0 ( uint32_t )0x03 +#endif +#ifndef GPIO_MODER_MODER0 +#define GPIO_MODER_MODER0 ( uint32_t )0x03 +#endif +#ifndef GPIO_OTYPER_OT_0 +#define GPIO_OTYPER_OT_0 ( uint32_t )0x01 +#endif +#ifndef GPIO_PUPDR_PUPDR0 +#define GPIO_PUPDR_PUPDR0 ( uint32_t )0x03 +#endif + +#ifndef GPIO_PIN_MASK_LOW +#define GPIO_PIN_MASK_LOW ( uint32_t )0x00FF +#endif +#ifndef GPIO_PIN_MASK_HIGH +#define GPIO_PIN_MASK_HIGH ( uint32_t )0xFF00 +#endif +#ifndef GPIO_PIN_MASK_ALL +#define GPIO_PIN_MASK_ALL ( uint32_t )0xFFFF +#endif + +#ifndef GPIO_AF_CONFIG_OFFSET +#define GPIO_AF_CONFIG_OFFSET ( uint32_t )20 +#endif +#ifndef GPIO_AF_MASK +#define GPIO_AF_MASK ( 0x0F ) +#endif +#ifndef GPIO_PIN_NAME_MASK +#define GPIO_PIN_NAME_MASK ( ( uint32_t )0xFF ) +#endif +#ifndef GPIO_AF_CONFIG_MASK +#define GPIO_AF_CONFIG_MASK ( ( uint32_t )0x0F << GPIO_AF_CONFIG_OFFSET ) +#endif + +#ifndef GPIO_CFG_MODE_ANALOG +#define GPIO_CFG_MODE_ANALOG ( uint32_t )0x1 +#endif +#ifndef GPIO_CFG_MODE_INPUT +#define GPIO_CFG_MODE_INPUT ( uint32_t )0x2 +#endif +#ifndef GPIO_CFG_MODE_OUTPUT +#define GPIO_CFG_MODE_OUTPUT ( uint32_t )0x4 +#endif +#ifndef GPIO_CFG_MODE_ALT_FUNCTION +#define GPIO_CFG_MODE_ALT_FUNCTION ( uint32_t )0x8 +#endif +#ifndef GPIO_CFG_OTYPE_PP +#define GPIO_CFG_OTYPE_PP ( uint32_t )0x10 +#endif +#ifndef GPIO_CFG_OTYPE_OD +#define GPIO_CFG_OTYPE_OD ( uint32_t )0x20 +#endif +#ifndef GPIO_CFG_PULL_NO +#define GPIO_CFG_PULL_NO ( uint32_t )0x40 +#endif +#ifndef GPIO_CFG_PULL_UP +#define GPIO_CFG_PULL_UP ( uint32_t )0x80 +#endif +#ifndef GPIO_CFG_PULL_DOWN +#define GPIO_CFG_PULL_DOWN ( uint32_t )0x100 +#endif +#ifndef GPIO_CFG_SPEED_LOW +#define GPIO_CFG_SPEED_LOW ( uint32_t )0x0 +#endif +#ifndef GPIO_CFG_SPEED_MEDIUM +#define GPIO_CFG_SPEED_MEDIUM ( uint32_t )0x200 +#endif +#ifndef GPIO_CFG_SPEED_HIGH +#define GPIO_CFG_SPEED_HIGH ( uint32_t )0x400 +#endif +#ifndef GPIO_CFG_SPEED_VERY_HIGH +#define GPIO_CFG_SPEED_VERY_HIGH ( uint32_t )0x800 +#endif +#ifndef GPIO_CFG_SPEED_MAX +#define GPIO_CFG_SPEED_MAX ( uint32_t )0x80000 +#endif + +#ifndef GPIO_AHB_SHIFT +#define GPIO_AHB_SHIFT 17 +#endif + +#ifndef GPIO_CFG_DIGITAL_OUTPUT +#define GPIO_CFG_DIGITAL_OUTPUT ( GPIO_CFG_MODE_OUTPUT | GPIO_CFG_SPEED_MAX | GPIO_CFG_OTYPE_PP ) +#endif +#ifndef GPIO_CFG_DIGITAL_INPUT +#define GPIO_CFG_DIGITAL_INPUT ( GPIO_CFG_MODE_INPUT | GPIO_CFG_PULL_NO ) +#endif +#ifndef GPIO_CFG_ANALOG_INPUT +#define GPIO_CFG_ANALOG_INPUT ( GPIO_CFG_MODE_ANALOG | GPIO_CFG_PULL_NO ) +#endif + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_GPIO_CONSTANTS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_85/hal_ll_gpio_struct_type.h b/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_85/hal_ll_gpio_struct_type.h new file mode 100644 index 000000000..0baa9dc5e --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_85/hal_ll_gpio_struct_type.h @@ -0,0 +1,76 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_gpio_struct_type.h + * @brief GPIO HAL LL register structure typedef. + */ + +#ifndef _HAL_LL_GPIO_STRUCT_TYPE_H_ +#define _HAL_LL_GPIO_STRUCT_TYPE_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include + +/** + * GPIO module registers access structure + */ +typedef struct hal_ll_gpio_base_handle +{ + uint32_t moder; + uint32_t otyper; + uint32_t ospeedr; + uint32_t pupdr; + uint32_t idr; + uint32_t odr; + uint32_t bsrr; + uint32_t lckr; + uint32_t afrl; + uint32_t afrh; + uint32_t brr; +} hal_ll_gpio_base_handle_t; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_GPIO_STRUCT_TYPE_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_86/hal_ll_gpio_constants.h b/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_86/hal_ll_gpio_constants.h new file mode 100644 index 000000000..ac120aad7 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_86/hal_ll_gpio_constants.h @@ -0,0 +1,153 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_gpio_constants.h + * @brief GPIO HAL LL macros. + */ + +#ifndef _HAL_LL_GPIO_CONSTANTS_H_ +#define _HAL_LL_GPIO_CONSTANTS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// Define any specific macros here +// REPLACE_MACROS // + +// Predefined macros if missing +#ifndef GPIO_OSPEEDER_OSPEEDR0 +#define GPIO_OSPEEDER_OSPEEDR0 ( uint32_t )0x03 +#endif +#ifndef GPIO_MODER_MODER0 +#define GPIO_MODER_MODER0 ( uint32_t )0x03 +#endif +#ifndef GPIO_OTYPER_OT_0 +#define GPIO_OTYPER_OT_0 ( uint32_t )0x01 +#endif +#ifndef GPIO_PUPDR_PUPDR0 +#define GPIO_PUPDR_PUPDR0 ( uint32_t )0x03 +#endif + +#ifndef GPIO_PIN_MASK_LOW +#define GPIO_PIN_MASK_LOW ( uint32_t )0x00FF +#endif +#ifndef GPIO_PIN_MASK_HIGH +#define GPIO_PIN_MASK_HIGH ( uint32_t )0xFF00 +#endif +#ifndef GPIO_PIN_MASK_ALL +#define GPIO_PIN_MASK_ALL ( uint32_t )0xFFFF +#endif + +#ifndef GPIO_AF_CONFIG_OFFSET +#define GPIO_AF_CONFIG_OFFSET ( uint32_t )20 +#endif +#ifndef GPIO_AF_MASK +#define GPIO_AF_MASK ( 0x0F ) +#endif +#ifndef GPIO_PIN_NAME_MASK +#define GPIO_PIN_NAME_MASK ( ( uint32_t )0xFF ) +#endif +#ifndef GPIO_AF_CONFIG_MASK +#define GPIO_AF_CONFIG_MASK ( ( uint32_t )0x0F << GPIO_AF_CONFIG_OFFSET ) +#endif + +#ifndef GPIO_CFG_MODE_ANALOG +#define GPIO_CFG_MODE_ANALOG ( uint32_t )0x1 +#endif +#ifndef GPIO_CFG_MODE_INPUT +#define GPIO_CFG_MODE_INPUT ( uint32_t )0x2 +#endif +#ifndef GPIO_CFG_MODE_OUTPUT +#define GPIO_CFG_MODE_OUTPUT ( uint32_t )0x4 +#endif +#ifndef GPIO_CFG_MODE_ALT_FUNCTION +#define GPIO_CFG_MODE_ALT_FUNCTION ( uint32_t )0x8 +#endif +#ifndef GPIO_CFG_OTYPE_PP +#define GPIO_CFG_OTYPE_PP ( uint32_t )0x10 +#endif +#ifndef GPIO_CFG_OTYPE_OD +#define GPIO_CFG_OTYPE_OD ( uint32_t )0x20 +#endif +#ifndef GPIO_CFG_PULL_NO +#define GPIO_CFG_PULL_NO ( uint32_t )0x40 +#endif +#ifndef GPIO_CFG_PULL_UP +#define GPIO_CFG_PULL_UP ( uint32_t )0x80 +#endif +#ifndef GPIO_CFG_PULL_DOWN +#define GPIO_CFG_PULL_DOWN ( uint32_t )0x100 +#endif +#ifndef GPIO_CFG_SPEED_LOW +#define GPIO_CFG_SPEED_LOW ( uint32_t )0x0 +#endif +#ifndef GPIO_CFG_SPEED_MEDIUM +#define GPIO_CFG_SPEED_MEDIUM ( uint32_t )0x200 +#endif +#ifndef GPIO_CFG_SPEED_HIGH +#define GPIO_CFG_SPEED_HIGH ( uint32_t )0x400 +#endif +#ifndef GPIO_CFG_SPEED_VERY_HIGH +#define GPIO_CFG_SPEED_VERY_HIGH ( uint32_t )0x800 +#endif +#ifndef GPIO_CFG_SPEED_MAX +#define GPIO_CFG_SPEED_MAX ( uint32_t )0x80000 +#endif + +#ifndef GPIO_AHB_SHIFT +#define GPIO_AHB_SHIFT 17 +#endif + +#ifndef GPIO_CFG_DIGITAL_OUTPUT +#define GPIO_CFG_DIGITAL_OUTPUT ( GPIO_CFG_MODE_OUTPUT | GPIO_CFG_SPEED_MAX | GPIO_CFG_OTYPE_PP ) +#endif +#ifndef GPIO_CFG_DIGITAL_INPUT +#define GPIO_CFG_DIGITAL_INPUT ( GPIO_CFG_MODE_INPUT | GPIO_CFG_PULL_NO ) +#endif +#ifndef GPIO_CFG_ANALOG_INPUT +#define GPIO_CFG_ANALOG_INPUT ( GPIO_CFG_MODE_ANALOG | GPIO_CFG_PULL_NO ) +#endif + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_GPIO_CONSTANTS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_86/hal_ll_gpio_struct_type.h b/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_86/hal_ll_gpio_struct_type.h new file mode 100644 index 000000000..0baa9dc5e --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_86/hal_ll_gpio_struct_type.h @@ -0,0 +1,76 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_gpio_struct_type.h + * @brief GPIO HAL LL register structure typedef. + */ + +#ifndef _HAL_LL_GPIO_STRUCT_TYPE_H_ +#define _HAL_LL_GPIO_STRUCT_TYPE_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include + +/** + * GPIO module registers access structure + */ +typedef struct hal_ll_gpio_base_handle +{ + uint32_t moder; + uint32_t otyper; + uint32_t ospeedr; + uint32_t pupdr; + uint32_t idr; + uint32_t odr; + uint32_t bsrr; + uint32_t lckr; + uint32_t afrl; + uint32_t afrh; + uint32_t brr; +} hal_ll_gpio_base_handle_t; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_GPIO_STRUCT_TYPE_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_87/hal_ll_gpio_constants.h b/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_87/hal_ll_gpio_constants.h new file mode 100644 index 000000000..ac120aad7 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_87/hal_ll_gpio_constants.h @@ -0,0 +1,153 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_gpio_constants.h + * @brief GPIO HAL LL macros. + */ + +#ifndef _HAL_LL_GPIO_CONSTANTS_H_ +#define _HAL_LL_GPIO_CONSTANTS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// Define any specific macros here +// REPLACE_MACROS // + +// Predefined macros if missing +#ifndef GPIO_OSPEEDER_OSPEEDR0 +#define GPIO_OSPEEDER_OSPEEDR0 ( uint32_t )0x03 +#endif +#ifndef GPIO_MODER_MODER0 +#define GPIO_MODER_MODER0 ( uint32_t )0x03 +#endif +#ifndef GPIO_OTYPER_OT_0 +#define GPIO_OTYPER_OT_0 ( uint32_t )0x01 +#endif +#ifndef GPIO_PUPDR_PUPDR0 +#define GPIO_PUPDR_PUPDR0 ( uint32_t )0x03 +#endif + +#ifndef GPIO_PIN_MASK_LOW +#define GPIO_PIN_MASK_LOW ( uint32_t )0x00FF +#endif +#ifndef GPIO_PIN_MASK_HIGH +#define GPIO_PIN_MASK_HIGH ( uint32_t )0xFF00 +#endif +#ifndef GPIO_PIN_MASK_ALL +#define GPIO_PIN_MASK_ALL ( uint32_t )0xFFFF +#endif + +#ifndef GPIO_AF_CONFIG_OFFSET +#define GPIO_AF_CONFIG_OFFSET ( uint32_t )20 +#endif +#ifndef GPIO_AF_MASK +#define GPIO_AF_MASK ( 0x0F ) +#endif +#ifndef GPIO_PIN_NAME_MASK +#define GPIO_PIN_NAME_MASK ( ( uint32_t )0xFF ) +#endif +#ifndef GPIO_AF_CONFIG_MASK +#define GPIO_AF_CONFIG_MASK ( ( uint32_t )0x0F << GPIO_AF_CONFIG_OFFSET ) +#endif + +#ifndef GPIO_CFG_MODE_ANALOG +#define GPIO_CFG_MODE_ANALOG ( uint32_t )0x1 +#endif +#ifndef GPIO_CFG_MODE_INPUT +#define GPIO_CFG_MODE_INPUT ( uint32_t )0x2 +#endif +#ifndef GPIO_CFG_MODE_OUTPUT +#define GPIO_CFG_MODE_OUTPUT ( uint32_t )0x4 +#endif +#ifndef GPIO_CFG_MODE_ALT_FUNCTION +#define GPIO_CFG_MODE_ALT_FUNCTION ( uint32_t )0x8 +#endif +#ifndef GPIO_CFG_OTYPE_PP +#define GPIO_CFG_OTYPE_PP ( uint32_t )0x10 +#endif +#ifndef GPIO_CFG_OTYPE_OD +#define GPIO_CFG_OTYPE_OD ( uint32_t )0x20 +#endif +#ifndef GPIO_CFG_PULL_NO +#define GPIO_CFG_PULL_NO ( uint32_t )0x40 +#endif +#ifndef GPIO_CFG_PULL_UP +#define GPIO_CFG_PULL_UP ( uint32_t )0x80 +#endif +#ifndef GPIO_CFG_PULL_DOWN +#define GPIO_CFG_PULL_DOWN ( uint32_t )0x100 +#endif +#ifndef GPIO_CFG_SPEED_LOW +#define GPIO_CFG_SPEED_LOW ( uint32_t )0x0 +#endif +#ifndef GPIO_CFG_SPEED_MEDIUM +#define GPIO_CFG_SPEED_MEDIUM ( uint32_t )0x200 +#endif +#ifndef GPIO_CFG_SPEED_HIGH +#define GPIO_CFG_SPEED_HIGH ( uint32_t )0x400 +#endif +#ifndef GPIO_CFG_SPEED_VERY_HIGH +#define GPIO_CFG_SPEED_VERY_HIGH ( uint32_t )0x800 +#endif +#ifndef GPIO_CFG_SPEED_MAX +#define GPIO_CFG_SPEED_MAX ( uint32_t )0x80000 +#endif + +#ifndef GPIO_AHB_SHIFT +#define GPIO_AHB_SHIFT 17 +#endif + +#ifndef GPIO_CFG_DIGITAL_OUTPUT +#define GPIO_CFG_DIGITAL_OUTPUT ( GPIO_CFG_MODE_OUTPUT | GPIO_CFG_SPEED_MAX | GPIO_CFG_OTYPE_PP ) +#endif +#ifndef GPIO_CFG_DIGITAL_INPUT +#define GPIO_CFG_DIGITAL_INPUT ( GPIO_CFG_MODE_INPUT | GPIO_CFG_PULL_NO ) +#endif +#ifndef GPIO_CFG_ANALOG_INPUT +#define GPIO_CFG_ANALOG_INPUT ( GPIO_CFG_MODE_ANALOG | GPIO_CFG_PULL_NO ) +#endif + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_GPIO_CONSTANTS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_87/hal_ll_gpio_struct_type.h b/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_87/hal_ll_gpio_struct_type.h new file mode 100644 index 000000000..0baa9dc5e --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_87/hal_ll_gpio_struct_type.h @@ -0,0 +1,76 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_gpio_struct_type.h + * @brief GPIO HAL LL register structure typedef. + */ + +#ifndef _HAL_LL_GPIO_STRUCT_TYPE_H_ +#define _HAL_LL_GPIO_STRUCT_TYPE_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include + +/** + * GPIO module registers access structure + */ +typedef struct hal_ll_gpio_base_handle +{ + uint32_t moder; + uint32_t otyper; + uint32_t ospeedr; + uint32_t pupdr; + uint32_t idr; + uint32_t odr; + uint32_t bsrr; + uint32_t lckr; + uint32_t afrl; + uint32_t afrh; + uint32_t brr; +} hal_ll_gpio_base_handle_t; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_GPIO_STRUCT_TYPE_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_88/hal_ll_gpio_constants.h b/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_88/hal_ll_gpio_constants.h new file mode 100644 index 000000000..ac120aad7 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_88/hal_ll_gpio_constants.h @@ -0,0 +1,153 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_gpio_constants.h + * @brief GPIO HAL LL macros. + */ + +#ifndef _HAL_LL_GPIO_CONSTANTS_H_ +#define _HAL_LL_GPIO_CONSTANTS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// Define any specific macros here +// REPLACE_MACROS // + +// Predefined macros if missing +#ifndef GPIO_OSPEEDER_OSPEEDR0 +#define GPIO_OSPEEDER_OSPEEDR0 ( uint32_t )0x03 +#endif +#ifndef GPIO_MODER_MODER0 +#define GPIO_MODER_MODER0 ( uint32_t )0x03 +#endif +#ifndef GPIO_OTYPER_OT_0 +#define GPIO_OTYPER_OT_0 ( uint32_t )0x01 +#endif +#ifndef GPIO_PUPDR_PUPDR0 +#define GPIO_PUPDR_PUPDR0 ( uint32_t )0x03 +#endif + +#ifndef GPIO_PIN_MASK_LOW +#define GPIO_PIN_MASK_LOW ( uint32_t )0x00FF +#endif +#ifndef GPIO_PIN_MASK_HIGH +#define GPIO_PIN_MASK_HIGH ( uint32_t )0xFF00 +#endif +#ifndef GPIO_PIN_MASK_ALL +#define GPIO_PIN_MASK_ALL ( uint32_t )0xFFFF +#endif + +#ifndef GPIO_AF_CONFIG_OFFSET +#define GPIO_AF_CONFIG_OFFSET ( uint32_t )20 +#endif +#ifndef GPIO_AF_MASK +#define GPIO_AF_MASK ( 0x0F ) +#endif +#ifndef GPIO_PIN_NAME_MASK +#define GPIO_PIN_NAME_MASK ( ( uint32_t )0xFF ) +#endif +#ifndef GPIO_AF_CONFIG_MASK +#define GPIO_AF_CONFIG_MASK ( ( uint32_t )0x0F << GPIO_AF_CONFIG_OFFSET ) +#endif + +#ifndef GPIO_CFG_MODE_ANALOG +#define GPIO_CFG_MODE_ANALOG ( uint32_t )0x1 +#endif +#ifndef GPIO_CFG_MODE_INPUT +#define GPIO_CFG_MODE_INPUT ( uint32_t )0x2 +#endif +#ifndef GPIO_CFG_MODE_OUTPUT +#define GPIO_CFG_MODE_OUTPUT ( uint32_t )0x4 +#endif +#ifndef GPIO_CFG_MODE_ALT_FUNCTION +#define GPIO_CFG_MODE_ALT_FUNCTION ( uint32_t )0x8 +#endif +#ifndef GPIO_CFG_OTYPE_PP +#define GPIO_CFG_OTYPE_PP ( uint32_t )0x10 +#endif +#ifndef GPIO_CFG_OTYPE_OD +#define GPIO_CFG_OTYPE_OD ( uint32_t )0x20 +#endif +#ifndef GPIO_CFG_PULL_NO +#define GPIO_CFG_PULL_NO ( uint32_t )0x40 +#endif +#ifndef GPIO_CFG_PULL_UP +#define GPIO_CFG_PULL_UP ( uint32_t )0x80 +#endif +#ifndef GPIO_CFG_PULL_DOWN +#define GPIO_CFG_PULL_DOWN ( uint32_t )0x100 +#endif +#ifndef GPIO_CFG_SPEED_LOW +#define GPIO_CFG_SPEED_LOW ( uint32_t )0x0 +#endif +#ifndef GPIO_CFG_SPEED_MEDIUM +#define GPIO_CFG_SPEED_MEDIUM ( uint32_t )0x200 +#endif +#ifndef GPIO_CFG_SPEED_HIGH +#define GPIO_CFG_SPEED_HIGH ( uint32_t )0x400 +#endif +#ifndef GPIO_CFG_SPEED_VERY_HIGH +#define GPIO_CFG_SPEED_VERY_HIGH ( uint32_t )0x800 +#endif +#ifndef GPIO_CFG_SPEED_MAX +#define GPIO_CFG_SPEED_MAX ( uint32_t )0x80000 +#endif + +#ifndef GPIO_AHB_SHIFT +#define GPIO_AHB_SHIFT 17 +#endif + +#ifndef GPIO_CFG_DIGITAL_OUTPUT +#define GPIO_CFG_DIGITAL_OUTPUT ( GPIO_CFG_MODE_OUTPUT | GPIO_CFG_SPEED_MAX | GPIO_CFG_OTYPE_PP ) +#endif +#ifndef GPIO_CFG_DIGITAL_INPUT +#define GPIO_CFG_DIGITAL_INPUT ( GPIO_CFG_MODE_INPUT | GPIO_CFG_PULL_NO ) +#endif +#ifndef GPIO_CFG_ANALOG_INPUT +#define GPIO_CFG_ANALOG_INPUT ( GPIO_CFG_MODE_ANALOG | GPIO_CFG_PULL_NO ) +#endif + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_GPIO_CONSTANTS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_88/hal_ll_gpio_struct_type.h b/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_88/hal_ll_gpio_struct_type.h new file mode 100644 index 000000000..0baa9dc5e --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_88/hal_ll_gpio_struct_type.h @@ -0,0 +1,76 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_gpio_struct_type.h + * @brief GPIO HAL LL register structure typedef. + */ + +#ifndef _HAL_LL_GPIO_STRUCT_TYPE_H_ +#define _HAL_LL_GPIO_STRUCT_TYPE_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include + +/** + * GPIO module registers access structure + */ +typedef struct hal_ll_gpio_base_handle +{ + uint32_t moder; + uint32_t otyper; + uint32_t ospeedr; + uint32_t pupdr; + uint32_t idr; + uint32_t odr; + uint32_t bsrr; + uint32_t lckr; + uint32_t afrl; + uint32_t afrh; + uint32_t brr; +} hal_ll_gpio_base_handle_t; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_GPIO_STRUCT_TYPE_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_89/hal_ll_gpio_constants.h b/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_89/hal_ll_gpio_constants.h new file mode 100644 index 000000000..ac120aad7 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_89/hal_ll_gpio_constants.h @@ -0,0 +1,153 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_gpio_constants.h + * @brief GPIO HAL LL macros. + */ + +#ifndef _HAL_LL_GPIO_CONSTANTS_H_ +#define _HAL_LL_GPIO_CONSTANTS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// Define any specific macros here +// REPLACE_MACROS // + +// Predefined macros if missing +#ifndef GPIO_OSPEEDER_OSPEEDR0 +#define GPIO_OSPEEDER_OSPEEDR0 ( uint32_t )0x03 +#endif +#ifndef GPIO_MODER_MODER0 +#define GPIO_MODER_MODER0 ( uint32_t )0x03 +#endif +#ifndef GPIO_OTYPER_OT_0 +#define GPIO_OTYPER_OT_0 ( uint32_t )0x01 +#endif +#ifndef GPIO_PUPDR_PUPDR0 +#define GPIO_PUPDR_PUPDR0 ( uint32_t )0x03 +#endif + +#ifndef GPIO_PIN_MASK_LOW +#define GPIO_PIN_MASK_LOW ( uint32_t )0x00FF +#endif +#ifndef GPIO_PIN_MASK_HIGH +#define GPIO_PIN_MASK_HIGH ( uint32_t )0xFF00 +#endif +#ifndef GPIO_PIN_MASK_ALL +#define GPIO_PIN_MASK_ALL ( uint32_t )0xFFFF +#endif + +#ifndef GPIO_AF_CONFIG_OFFSET +#define GPIO_AF_CONFIG_OFFSET ( uint32_t )20 +#endif +#ifndef GPIO_AF_MASK +#define GPIO_AF_MASK ( 0x0F ) +#endif +#ifndef GPIO_PIN_NAME_MASK +#define GPIO_PIN_NAME_MASK ( ( uint32_t )0xFF ) +#endif +#ifndef GPIO_AF_CONFIG_MASK +#define GPIO_AF_CONFIG_MASK ( ( uint32_t )0x0F << GPIO_AF_CONFIG_OFFSET ) +#endif + +#ifndef GPIO_CFG_MODE_ANALOG +#define GPIO_CFG_MODE_ANALOG ( uint32_t )0x1 +#endif +#ifndef GPIO_CFG_MODE_INPUT +#define GPIO_CFG_MODE_INPUT ( uint32_t )0x2 +#endif +#ifndef GPIO_CFG_MODE_OUTPUT +#define GPIO_CFG_MODE_OUTPUT ( uint32_t )0x4 +#endif +#ifndef GPIO_CFG_MODE_ALT_FUNCTION +#define GPIO_CFG_MODE_ALT_FUNCTION ( uint32_t )0x8 +#endif +#ifndef GPIO_CFG_OTYPE_PP +#define GPIO_CFG_OTYPE_PP ( uint32_t )0x10 +#endif +#ifndef GPIO_CFG_OTYPE_OD +#define GPIO_CFG_OTYPE_OD ( uint32_t )0x20 +#endif +#ifndef GPIO_CFG_PULL_NO +#define GPIO_CFG_PULL_NO ( uint32_t )0x40 +#endif +#ifndef GPIO_CFG_PULL_UP +#define GPIO_CFG_PULL_UP ( uint32_t )0x80 +#endif +#ifndef GPIO_CFG_PULL_DOWN +#define GPIO_CFG_PULL_DOWN ( uint32_t )0x100 +#endif +#ifndef GPIO_CFG_SPEED_LOW +#define GPIO_CFG_SPEED_LOW ( uint32_t )0x0 +#endif +#ifndef GPIO_CFG_SPEED_MEDIUM +#define GPIO_CFG_SPEED_MEDIUM ( uint32_t )0x200 +#endif +#ifndef GPIO_CFG_SPEED_HIGH +#define GPIO_CFG_SPEED_HIGH ( uint32_t )0x400 +#endif +#ifndef GPIO_CFG_SPEED_VERY_HIGH +#define GPIO_CFG_SPEED_VERY_HIGH ( uint32_t )0x800 +#endif +#ifndef GPIO_CFG_SPEED_MAX +#define GPIO_CFG_SPEED_MAX ( uint32_t )0x80000 +#endif + +#ifndef GPIO_AHB_SHIFT +#define GPIO_AHB_SHIFT 17 +#endif + +#ifndef GPIO_CFG_DIGITAL_OUTPUT +#define GPIO_CFG_DIGITAL_OUTPUT ( GPIO_CFG_MODE_OUTPUT | GPIO_CFG_SPEED_MAX | GPIO_CFG_OTYPE_PP ) +#endif +#ifndef GPIO_CFG_DIGITAL_INPUT +#define GPIO_CFG_DIGITAL_INPUT ( GPIO_CFG_MODE_INPUT | GPIO_CFG_PULL_NO ) +#endif +#ifndef GPIO_CFG_ANALOG_INPUT +#define GPIO_CFG_ANALOG_INPUT ( GPIO_CFG_MODE_ANALOG | GPIO_CFG_PULL_NO ) +#endif + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_GPIO_CONSTANTS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_89/hal_ll_gpio_struct_type.h b/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_89/hal_ll_gpio_struct_type.h new file mode 100644 index 000000000..0baa9dc5e --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/gpio/implementations/doc_ds_89/hal_ll_gpio_struct_type.h @@ -0,0 +1,76 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_gpio_struct_type.h + * @brief GPIO HAL LL register structure typedef. + */ + +#ifndef _HAL_LL_GPIO_STRUCT_TYPE_H_ +#define _HAL_LL_GPIO_STRUCT_TYPE_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include + +/** + * GPIO module registers access structure + */ +typedef struct hal_ll_gpio_base_handle +{ + uint32_t moder; + uint32_t otyper; + uint32_t ospeedr; + uint32_t pupdr; + uint32_t idr; + uint32_t odr; + uint32_t bsrr; + uint32_t lckr; + uint32_t afrl; + uint32_t afrh; + uint32_t brr; +} hal_ll_gpio_base_handle_t; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_GPIO_STRUCT_TYPE_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/hal_ll_pin_names.h b/targets/arm/mikroe/ai_generated/stm32/include/hal_ll_pin_names.h new file mode 100644 index 000000000..992316af7 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/hal_ll_pin_names.h @@ -0,0 +1,685 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_pin_names.h + * @brief Header file containing symbolic pin name definitions. + */ + +#ifndef _HAL_LL_PIN_NAMES_H_ +#define _HAL_LL_PIN_NAMES_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "mcu_definitions.h" +#include "hal_ll_target_names.h" + +#define GPIO_FEATURE_16BIT_PORT + +#ifdef __PORT_A_CN +#define GPIO_FEATURE_GROUP_1 +#endif +#ifdef __PORT_B_CN +#define GPIO_FEATURE_GROUP_2 +#endif +#ifdef __PORT_C_CN +#define GPIO_FEATURE_GROUP_3 +#endif +#ifdef __PORT_D_CN +#define GPIO_FEATURE_GROUP_4 +#endif +#ifdef __PORT_E_CN +#define GPIO_FEATURE_GROUP_5 +#endif +#ifdef __PORT_F_CN +#define GPIO_FEATURE_GROUP_6 +#endif +#ifdef __PORT_G_CN +#define GPIO_FEATURE_GROUP_7 +#endif +#ifdef __PORT_H_CN +#define GPIO_FEATURE_GROUP_8 +#endif +#ifdef __PORT_I_CN +#define GPIO_FEATURE_GROUP_9 +#endif +#ifdef __PORT_J_CN +#define GPIO_FEATURE_GROUP_10 +#endif +#ifdef __PORT_K_CN +#define GPIO_FEATURE_GROUP_11 +#endif + +#ifdef __PA0_CN +#define PA0 (0x00) +#endif +#ifdef __PA1_CN +#define PA1 (0x01) +#endif +#ifdef __PA2_CN +#define PA2 (0x02) +#endif +#ifdef __PA3_CN +#define PA3 (0x03) +#endif +#ifdef __PA4_CN +#define PA4 (0x04) +#endif +#ifdef __PA5_CN +#define PA5 (0x05) +#endif +#ifdef __PA6_CN +#define PA6 (0x06) +#endif +#ifdef __PA7_CN +#define PA7 (0x07) +#endif +#ifdef __PA8_CN +#define PA8 (0x08) +#endif +#ifdef __PA9_CN +#define PA9 (0x09) +#endif +#ifdef __PA10_CN +#define PA10 (0x0A) +#endif +#ifdef __PA11_CN +#define PA11 (0x0B) +#endif +#ifdef __PA12_CN +#define PA12 (0x0C) +#endif +#ifdef __PA13_CN +#define PA13 (0x0D) +#endif +#ifdef __PA14_CN +#define PA14 (0x0E) +#endif +#ifdef __PA15_CN +#define PA15 (0x0F) +#endif + +#ifdef __PB0_CN +#define PB0 (0x10) +#endif +#ifdef __PB1_CN +#define PB1 (0x11) +#endif +#ifdef __PB2_CN +#define PB2 (0x12) +#endif +#ifdef __PB3_CN +#define PB3 (0x13) +#endif +#ifdef __PB4_CN +#define PB4 (0x14) +#endif +#ifdef __PB5_CN +#define PB5 (0x15) +#endif +#ifdef __PB6_CN +#define PB6 (0x16) +#endif +#ifdef __PB7_CN +#define PB7 (0x17) +#endif +#ifdef __PB8_CN +#define PB8 (0x18) +#endif +#ifdef __PB9_CN +#define PB9 (0x19) +#endif +#ifdef __PB10_CN +#define PB10 (0x1A) +#endif +#ifdef __PB11_CN +#define PB11 (0x1B) +#endif +#ifdef __PB12_CN +#define PB12 (0x1C) +#endif +#ifdef __PB13_CN +#define PB13 (0x1D) +#endif +#ifdef __PB14_CN +#define PB14 (0x1E) +#endif +#ifdef __PB15_CN +#define PB15 (0x1F) +#endif + +#ifdef __PC0_CN +#define PC0 (0x20) +#endif +#ifdef __PC1_CN +#define PC1 (0x21) +#endif +#ifdef __PC2_CN +#define PC2 (0x22) +#endif +#ifdef __PC3_CN +#define PC3 (0x23) +#endif +#ifdef __PC4_CN +#define PC4 (0x24) +#endif +#ifdef __PC5_CN +#define PC5 (0x25) +#endif +#ifdef __PC6_CN +#define PC6 (0x26) +#endif +#ifdef __PC7_CN +#define PC7 (0x27) +#endif +#ifdef __PC8_CN +#define PC8 (0x28) +#endif +#ifdef __PC9_CN +#define PC9 (0x29) +#endif +#ifdef __PC10_CN +#define PC10 (0x2A) +#endif +#ifdef __PC11_CN +#define PC11 (0x2B) +#endif +#ifdef __PC12_CN +#define PC12 (0x2C) +#endif +#ifdef __PC13_CN +#define PC13 (0x2D) +#endif +#ifdef __PC14_CN +#define PC14 (0x2E) +#endif +#ifdef __PC15_CN +#define PC15 (0x2F) +#endif + +#ifdef __PD0_CN +#define PD0 (0x30) +#endif +#ifdef __PD1_CN +#define PD1 (0x31) +#endif +#ifdef __PD2_CN +#define PD2 (0x32) +#endif +#ifdef __PD3_CN +#define PD3 (0x33) +#endif +#ifdef __PD4_CN +#define PD4 (0x34) +#endif +#ifdef __PD5_CN +#define PD5 (0x35) +#endif +#ifdef __PD6_CN +#define PD6 (0x36) +#endif +#ifdef __PD7_CN +#define PD7 (0x37) +#endif +#ifdef __PD8_CN +#define PD8 (0x38) +#endif +#ifdef __PD9_CN +#define PD9 (0x39) +#endif +#ifdef __PD10_CN +#define PD10 (0x3A) +#endif +#ifdef __PD11_CN +#define PD11 (0x3B) +#endif +#ifdef __PD12_CN +#define PD12 (0x3C) +#endif +#ifdef __PD13_CN +#define PD13 (0x3D) +#endif +#ifdef __PD14_CN +#define PD14 (0x3E) +#endif +#ifdef __PD15_CN +#define PD15 (0x3F) +#endif + +#ifdef __PE0_CN +#define PE0 (0x40) +#endif +#ifdef __PE1_CN +#define PE1 (0x41) +#endif +#ifdef __PE2_CN +#define PE2 (0x42) +#endif +#ifdef __PE3_CN +#define PE3 (0x43) +#endif +#ifdef __PE4_CN +#define PE4 (0x44) +#endif +#ifdef __PE5_CN +#define PE5 (0x45) +#endif +#ifdef __PE6_CN +#define PE6 (0x46) +#endif +#ifdef __PE7_CN +#define PE7 (0x47) +#endif +#ifdef __PE8_CN +#define PE8 (0x48) +#endif +#ifdef __PE9_CN +#define PE9 (0x49) +#endif +#ifdef __PE10_CN +#define PE10 (0x4A) +#endif +#ifdef __PE11_CN +#define PE11 (0x4B) +#endif +#ifdef __PE12_CN +#define PE12 (0x4C) +#endif +#ifdef __PE13_CN +#define PE13 (0x4D) +#endif +#ifdef __PE14_CN +#define PE14 (0x4E) +#endif +#ifdef __PE15_CN +#define PE15 (0x4F) +#endif + +#ifdef __PF0_CN +#define PF0 (0x50) +#endif +#ifdef __PF1_CN +#define PF1 (0x51) +#endif +#ifdef __PF2_CN +#define PF2 (0x52) +#endif +#ifdef __PF3_CN +#define PF3 (0x53) +#endif +#ifdef __PF4_CN +#define PF4 (0x54) +#endif +#ifdef __PF5_CN +#define PF5 (0x55) +#endif +#ifdef __PF6_CN +#define PF6 (0x56) +#endif +#ifdef __PF7_CN +#define PF7 (0x57) +#endif +#ifdef __PF8_CN +#define PF8 (0x58) +#endif +#ifdef __PF9_CN +#define PF9 (0x59) +#endif +#ifdef __PF10_CN +#define PF10 (0x5A) +#endif +#ifdef __PF11_CN +#define PF11 (0x5B) +#endif +#ifdef __PF12_CN +#define PF12 (0x5C) +#endif +#ifdef __PF13_CN +#define PF13 (0x5D) +#endif +#ifdef __PF14_CN +#define PF14 (0x5E) +#endif +#ifdef __PF15_CN +#define PF15 (0x5F) +#endif + +#ifdef __PG0_CN +#define PG0 (0x60) +#endif +#ifdef __PG1_CN +#define PG1 (0x61) +#endif +#ifdef __PG2_CN +#define PG2 (0x62) +#endif +#ifdef __PG3_CN +#define PG3 (0x63) +#endif +#ifdef __PG4_CN +#define PG4 (0x64) +#endif +#ifdef __PG5_CN +#define PG5 (0x65) +#endif +#ifdef __PG6_CN +#define PG6 (0x66) +#endif +#ifdef __PG7_CN +#define PG7 (0x67) +#endif +#ifdef __PG8_CN +#define PG8 (0x68) +#endif +#ifdef __PG9_CN +#define PG9 (0x69) +#endif +#ifdef __PG10_CN +#define PG10 (0x6A) +#endif +#ifdef __PG11_CN +#define PG11 (0x6B) +#endif +#ifdef __PG12_CN +#define PG12 (0x6C) +#endif +#ifdef __PG13_CN +#define PG13 (0x6D) +#endif +#ifdef __PG14_CN +#define PG14 (0x6E) +#endif +#ifdef __PG15_CN +#define PG15 (0x6F) +#endif + +#ifdef __PH0_CN +#define PH0 (0x70) +#endif +#ifdef __PH1_CN +#define PH1 (0x71) +#endif +#ifdef __PH2_CN +#define PH2 (0x72) +#endif +#ifdef __PH3_CN +#define PH3 (0x73) +#endif +#ifdef __PH4_CN +#define PH4 (0x74) +#endif +#ifdef __PH5_CN +#define PH5 (0x75) +#endif +#ifdef __PH6_CN +#define PH6 (0x76) +#endif +#ifdef __PH7_CN +#define PH7 (0x77) +#endif +#ifdef __PH8_CN +#define PH8 (0x78) +#endif +#ifdef __PH9_CN +#define PH9 (0x79) +#endif +#ifdef __PH10_CN +#define PH10 (0x7A) +#endif +#ifdef __PH11_CN +#define PH11 (0x7B) +#endif +#ifdef __PH12_CN +#define PH12 (0x7C) +#endif +#ifdef __PH13_CN +#define PH13 (0x7D) +#endif +#ifdef __PH14_CN +#define PH14 (0x7E) +#endif +#ifdef __PH15_CN +#define PH15 (0x7F) +#endif + +#ifdef __PI0_CN +#define PI0 (0x80) +#endif +#ifdef __PI1_CN +#define PI1 (0x81) +#endif +#ifdef __PI2_CN +#define PI2 (0x82) +#endif +#ifdef __PI3_CN +#define PI3 (0x83) +#endif +#ifdef __PI4_CN +#define PI4 (0x84) +#endif +#ifdef __PI5_CN +#define PI5 (0x85) +#endif +#ifdef __PI6_CN +#define PI6 (0x86) +#endif +#ifdef __PI7_CN +#define PI7 (0x87) +#endif +#ifdef __PI8_CN +#define PI8 (0x88) +#endif +#ifdef __PI9_CN +#define PI9 (0x89) +#endif +#ifdef __PI10_CN +#define PI10 (0x8A) +#endif +#ifdef __PI11_CN +#define PI11 (0x8B) +#endif +#ifdef __PI12_CN +#define PI12 (0x8C) +#endif +#ifdef __PI13_CN +#define PI13 (0x8D) +#endif +#ifdef __PI14_CN +#define PI14 (0x8E) +#endif +#ifdef __PI15_CN +#define PI15 (0x8F) +#endif + +#ifdef __PJ0_CN +#define PJ0 (0x90) +#endif +#ifdef __PJ1_CN +#define PJ1 (0x91) +#endif +#ifdef __PJ2_CN +#define PJ2 (0x92) +#endif +#ifdef __PJ3_CN +#define PJ3 (0x93) +#endif +#ifdef __PJ4_CN +#define PJ4 (0x94) +#endif +#ifdef __PJ5_CN +#define PJ5 (0x95) +#endif +#ifdef __PJ6_CN +#define PJ6 (0x96) +#endif +#ifdef __PJ7_CN +#define PJ7 (0x97) +#endif +#ifdef __PJ8_CN +#define PJ8 (0x98) +#endif +#ifdef __PJ9_CN +#define PJ9 (0x99) +#endif +#ifdef __PJ10_CN +#define PJ10 (0x9A) +#endif +#ifdef __PJ11_CN +#define PJ11 (0x9B) +#endif +#ifdef __PJ12_CN +#define PJ12 (0x9C) +#endif +#ifdef __PJ13_CN +#define PJ13 (0x9D) +#endif +#ifdef __PJ14_CN +#define PJ14 (0x9E) +#endif +#ifdef __PJ15_CN +#define PJ15 (0x9F) +#endif + +#ifdef __PK0_CN +#define PK0 (0xA0) +#endif +#ifdef __PK1_CN +#define PK1 (0xA1) +#endif +#ifdef __PK2_CN +#define PK2 (0xA2) +#endif +#ifdef __PK3_CN +#define PK3 (0xA3) +#endif +#ifdef __PK4_CN +#define PK4 (0xA4) +#endif +#ifdef __PK5_CN +#define PK5 (0xA5) +#endif +#ifdef __PK6_CN +#define PK6 (0xA6) +#endif +#ifdef __PK7_CN +#define PK7 (0xA7) +#endif +#ifdef __PK8_CN +#define PK8 (0xA8) +#endif +#ifdef __PK9_CN +#define PK9 (0xA9) +#endif +#ifdef __PK10_CN +#define PK10 (0xAA) +#endif +#ifdef __PK11_CN +#define PK11 (0xAB) +#endif +#ifdef __PK12_CN +#define PK12 (0xAC) +#endif +#ifdef __PK13_CN +#define PK13 (0xAD) +#endif +#ifdef __PK14_CN +#define PK14 (0xAE) +#endif +#ifdef __PK15_CN +#define PK15 (0xAF) +#endif + +#define PIN_0 (0x00) +#define PIN_1 (0x01) +#define PIN_2 (0x02) +#define PIN_3 (0x03) +#define PIN_4 (0x04) +#define PIN_5 (0x05) +#define PIN_6 (0x06) +#define PIN_7 (0x07) +#define PIN_8 (0x08) +#define PIN_9 (0x09) +#define PIN_10 (0x0A) +#define PIN_11 (0x0B) +#define PIN_12 (0x0C) +#define PIN_13 (0x0D) +#define PIN_14 (0x0E) +#define PIN_15 (0x0F) + +#ifdef __PORT_A_CN +#define PORT_A (0x00) +#endif +#ifdef __PORT_B_CN +#define PORT_B (0x01) +#endif +#ifdef __PORT_C_CN +#define PORT_C (0x02) +#endif +#ifdef __PORT_D_CN +#define PORT_D (0x03) +#endif +#ifdef __PORT_E_CN +#define PORT_E (0x04) +#endif +#ifdef __PORT_F_CN +#define PORT_F (0x05) +#endif +#ifdef __PORT_G_CN +#define PORT_G (0x06) +#endif +#ifdef __PORT_H_CN +#define PORT_H (0x07) +#endif +#ifdef __PORT_I_CN +#define PORT_I (0x08) +#endif +#ifdef __PORT_J_CN +#define PORT_J (0x09) +#endif +#ifdef __PORT_K_CN +#define PORT_K (0x0A) +#endif + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_PIN_NAMES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/hal_ll_target.h b/targets/arm/mikroe/ai_generated/stm32/include/hal_ll_target.h new file mode 100644 index 000000000..ba2b047b5 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/hal_ll_target.h @@ -0,0 +1,67 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_target.h + * @brief Header file containing symbolic pin name definitions. + */ + +#ifndef _HAL_LL_TARGET_H_ +#define _HAL_LL_TARGET_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" +#include "hal_ll_bit_control.h" +#include "assembly.h" +#include "common_macros.h" +#include "common_types.h" + +#define HAL_LL_MODULE_ERROR (hal_ll_base_addr_t)(0xFFFFFFFF) +#define HAL_LL_CHANNEL_ERROR (hal_ll_base_addr_t)(0xFFFFFF) +#define HAL_LL_PIN_NC (hal_ll_pin_name_t)(0xFFFF) +#define HAL_LL_PORT_NC (hal_ll_port_name_t)(0xFF) + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_TARGET_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/hal_ll_target_names.h b/targets/arm/mikroe/ai_generated/stm32/include/hal_ll_target_names.h new file mode 100644 index 000000000..658ce4559 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/hal_ll_target_names.h @@ -0,0 +1,72 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_target_names.h + * @brief Header file containing symbolic pin name definitions. + */ + +#ifndef _HAL_LL_TARGET_NAMES_H_ +#define _HAL_LL_TARGET_NAMES_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include +#include +#include +#include +#include + +typedef uintptr_t handle_t; +typedef uint16_t hal_ll_gpio_mask_t; +typedef uint16_t hal_ll_pin_name_t; +typedef uint8_t hal_ll_port_name_t; +typedef uint16_t hal_ll_port_size_t; +typedef uint32_t hal_ll_base_addr_t; +typedef uint8_t hal_ll_channel_t; + +typedef int32_t hal_ll_err_t; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_TARGET_NAMES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/i2c/hal_ll_i2c_master.h b/targets/arm/mikroe/ai_generated/stm32/include/i2c/hal_ll_i2c_master.h new file mode 100644 index 000000000..46376d50a --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/i2c/hal_ll_i2c_master.h @@ -0,0 +1,241 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_i2c_master.h + * @brief API for I2C master HAL LOW LEVEL layer. + */ + +#ifndef _HAL_LL_I2C_MASTER_H_ +#define _HAL_LL_I2C_MASTER_H_ + +#include "hal_ll_target.h" + +#ifdef __cplusplus +extern "C"{ +#endif + +/** + * @brief I2C master low level pins config structure. + * + * The context structure for storing low level pin configuration + * for both SCL and SDA pins. + * + */ +typedef struct +{ + hal_ll_pin_af_t pin_scl; + hal_ll_pin_af_t pin_sda; +} hal_ll_i2c_pins_t; + +/** + * @brief I2C master low level handle. + * + * The context for storing low level object handler. + * User is not to change these values or unexpected behaviour + * may occur. + */ +typedef struct +{ + handle_t *hal_ll_i2c_master_handle; + handle_t *hal_drv_i2c_master_handle; + bool init_ll_state; +} hal_ll_i2c_master_handle_register_t; + +/** + * @brief Registers handler for future use. + * + * Registers low level and hal level handlers + * for use with appropriate functions. + * + * @param[in] scl I2C SCL pin. + * @param[in] sda I2C SDA pin. + * @param[in] *handle_map HAL layer local handle map. + * @param[in] *hal_module_id HAL layer module number. + + * @return hal_ll_err_t Module specific error. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_i2c_master_register_handle( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_master_handle_register_t *handle_map, uint8_t *hal_module_id ); + +/** + * @brief Configures specified module. + * + * Performs module configuration on the hardware + * level. Enables module specific clock gate and + * sets adequate alternate function values. + * + * @param[in] *handle HAL context object handle. + * + * @return hal_ll_err_t Module specific error. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_module_configure_i2c( handle_t *handle ); + +/** + * @brief Sets I2C slave address. + * + * Registers I2C slave address for specified + * object. + * + * @param[in] *handle HAL context object handle. + * @param[in] addr I2C slave address. + * + * @return void None. + */ +void hal_ll_i2c_master_set_slave_address( handle_t *handle, uint8_t addr ); + +/** + * @brief Sets I2C module speed. + * + * Sets specified speed for module. + * Take into consideration that the module + * will be re-initialized on the hardware level. + * + * @param[in] *handle HAL context object handle. + * @param[in] speed Desired speed value. + * + * @return hal_ll_err_t Module specific error. + * + * Returns value of speed the module was + * initialized to, or module specific error if + * initialization failed. + * When using from low level directly, + * speed can be set to any desired value, + * but take into consideration that not all values + * will work, as this is chip specific. + * Speed value is declared in kbit/s. + */ +hal_ll_err_t hal_ll_i2c_master_set_speed( handle_t *handle, uint32_t speed ); + +/** + * @brief Sets I2C timeout value. + * + * Registers I2C timeout value in number of retries. + * Module shall retry any given operation + * `timeout` number of times before aborting operation. + * + * @param[in] *handle HAL context object handle. + * @param[in] timeout I2C timeout value. + * + * @return void None. + */ +void hal_ll_i2c_master_set_timeout( handle_t *handle, uint16_t timeout ); + +/** + * @brief Executes low level data read on I2C bus. + * + * Function shall generate a START signal, + * followed by lenReadData number of reads + * on the bus. Ends with a STOP signal. + * + * @param handle I2C handle. + * @param *readDatabuf Data buffer where read data + * shall be placed. + * @param lenReadData Number of bytes to read. + * + * @return hal_ll_err_t Module specific error. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_i2c_master_read( handle_t *handle, uint8_t *read_data_buf, size_t len_read_data ); + +/** + * @brief Executes low level data write on I2C bus. + * + * Function shall generate a START signal, + * followed by lenWriteData number of writes + * on the bus. Ends with a STOP signal. + * + * @param handle I2C handle. + * @param *WriteDatabuf Data buffer where data to + * be written is located. + * @param lenWriteData Number of bytes to send. + * + * @return hal_ll_err_t Module specific error. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_i2c_master_write( handle_t *handle, uint8_t *write_data_buf, size_t len_write_data ); + +/** + * @brief Perform a low level write followed by a low level read on the I2C bus. + * + * Initializes I2C module on hardware level, if not initialized beforehand + * and continues to perform a write operation followed by a + * read operation on the bus. + * The operation consists of a start signal followed by lenWriteData number + * of write operations, a restart signal followed by lenReadData number + * of read operations finishing with a stop signal. + * + * @param handle I2C handle. + * @param[in] *writeDatabuf - Pointer to write data buffer. + * @param[in] lenWriteData - Number of data to be written. + * @param[in] *readDatabuf - Pointer to read data buffer. + * @param[in] lenReadData - Number of data to be read. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_i2c_master_write_then_read( handle_t *handle, uint8_t *write_data_buf, size_t len_write_data, uint8_t *read_data_buf, size_t len_read_data ); + +/** + * @brief Closes I2C master HAL and HAL_LOW_LEVEL context object. + * + * De-allocates hardware resources for specific driver object and + * de-initializes the module on a hardware level. + * + * @param[in] *handle HAL context object handle. + * + * @return void None. + */ +void hal_ll_i2c_master_close( handle_t *handle ); + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_I2C_MASTER_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/i2c/hal_ll_i2c_pin_map/implementations/doc_ds_1/hal_ll_i2c_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/i2c/hal_ll_i2c_pin_map/implementations/doc_ds_1/hal_ll_i2c_pin_map.h new file mode 100644 index 000000000..11db420b6 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/i2c/hal_ll_i2c_pin_map/implementations/doc_ds_1/hal_ll_i2c_pin_map.h @@ -0,0 +1,109 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_i2c_pin_map.h + * @brief I2C HAL LOW LEVEL PIN MAP. + */ + +#ifndef _HAL_LL_I2C_PIN_MAP_H_ +#define _HAL_LL_I2C_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_i2c_module_num(_module_num) (_module_num - 1) + +/*!< @brief Pin function structure */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + uint8_t af; +} hal_ll_i2c_pin_map_t; + +#ifdef I2C_MODULE_1 +#define I2C1_BASE_ADDRESS (0x40005400UL) +#define I2C1_BASE_ADDR I2C1_BASE_ADDRESS +#define HAL_LL_I2C1_BASE_ADDR I2C1_BASE_ADDRESS +#define HAL_LL_I2C1_BASE_ADDRESS I2C1_BASE_ADDRESS +#endif + +/*!< @brief I2C SCL pins */ +static const hal_ll_i2c_pin_map_t hal_ll_i2c_scl_map[] = +{ + #ifdef I2C1_SCL_PA9_AF6 + {PA9, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 6}, + #endif + #ifdef I2C1_SCL_PB6_AF6 + {PB6, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 6}, + #endif + #ifdef I2C1_SCL_PB7_AF14 + {PB7, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 14}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} + //------------ END SCL +}; + +/*!< @brief I2C SDA pins */ +static const hal_ll_i2c_pin_map_t hal_ll_i2c_sda_map[] = +{ + #ifdef I2C1_SDA_PA10_AF6 + {PA10, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 6}, + #endif + #ifdef I2C1_SDA_PB7_AF6 + {PB7, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 6}, + #endif + #ifdef I2C1_SDA_PC14_AF14 + {PC14, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 14}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} + //------------ END SDA +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_I2C_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/i2c/hal_ll_i2c_pin_map/implementations/doc_ds_160/hal_ll_i2c_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/i2c/hal_ll_i2c_pin_map/implementations/doc_ds_160/hal_ll_i2c_pin_map.h new file mode 100644 index 000000000..5d01b5211 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/i2c/hal_ll_i2c_pin_map/implementations/doc_ds_160/hal_ll_i2c_pin_map.h @@ -0,0 +1,202 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_i2c_pin_map.h + * @brief I2C HAL LOW LEVEL PIN MAP. + */ + +#ifndef _HAL_LL_I2C_PIN_MAP_H_ +#define _HAL_LL_I2C_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_i2c_module_num(_module_num) (_module_num - 1) + +/*!< @brief Pin function structure */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + uint8_t af; +} hal_ll_i2c_pin_map_t; + +#ifdef I2C_MODULE_1 +#define I2C1_BASE_ADDRESS (0x40005400UL) +#define I2C1_BASE_ADDR I2C1_BASE_ADDRESS +#define HAL_LL_I2C1_BASE_ADDR I2C1_BASE_ADDRESS +#define HAL_LL_I2C1_BASE_ADDRESS I2C1_BASE_ADDRESS +#endif +#ifdef I2C_MODULE_2 +#define I2C2_BASE_ADDRESS (0x40005800UL) +#define I2C2_BASE_ADDR I2C2_BASE_ADDRESS +#define HAL_LL_I2C2_BASE_ADDR I2C2_BASE_ADDRESS +#define HAL_LL_I2C2_BASE_ADDRESS I2C2_BASE_ADDRESS +#endif +#ifdef I2C_MODULE_3 +#define I2C3_BASE_ADDRESS (0x40005C00UL) +#define I2C3_BASE_ADDR I2C3_BASE_ADDRESS +#define HAL_LL_I2C3_BASE_ADDR I2C3_BASE_ADDRESS +#define HAL_LL_I2C3_BASE_ADDRESS I2C3_BASE_ADDRESS +#endif +#ifdef I2C_MODULE_4 +#define I2C4_BASE_ADDRESS (0x40008400UL) +#define I2C4_BASE_ADDR I2C4_BASE_ADDRESS +#define HAL_LL_I2C4_BASE_ADDR I2C4_BASE_ADDRESS +#define HAL_LL_I2C4_BASE_ADDRESS I2C4_BASE_ADDRESS +#endif + +/*!< @brief I2C SCL pins */ +static const hal_ll_i2c_pin_map_t hal_ll_i2c_scl_map[] = +{ + #ifdef I2C1_SCL_PB6_AF4 + {PB6, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 4}, + #endif + #ifdef I2C1_SCL_PB8_AF4 + {PB8, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 4}, + #endif + #ifdef I2C1_SCL_PG14_AF4 + {PG14, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 4}, + #endif + #ifdef I2C2_SCL_PB10_AF4 + {PB10, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 4}, + #endif + #ifdef I2C2_SCL_PB13_AF4 + {PB13, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 4}, + #endif + #ifdef I2C2_SCL_PF1_AF4 + {PF1, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 4}, + #endif + #ifdef I2C3_SCL_PA7_AF4 + {PA7, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 4}, + #endif + #ifdef I2C3_SCL_PC0_AF4 + {PC0, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 4}, + #endif + #ifdef I2C3_SCL_PG7_AF4 + {PG7, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 4}, + #endif + #ifdef I2C4_SCL_PB10_AF3 + {PB10, I2C4_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_4), 3}, + #endif + #ifdef I2C4_SCL_PB6_AF5 + {PB6, I2C4_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_4), 5}, + #endif + #ifdef I2C4_SCL_PD12_AF4 + {PD12, I2C4_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_4), 4}, + #endif + #ifdef I2C4_SCL_PF14_AF4 + {PF14, I2C4_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_4), 4}, + #endif + #ifdef I2C2_SCL_PH4_AF4 + {PH4, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 4}, + #endif + #ifdef I2C3_SCL_PH7_AF4 + {PH7, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 4}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} + //------------ END SCL +}; + +/*!< @brief I2C SDA pins */ +static const hal_ll_i2c_pin_map_t hal_ll_i2c_sda_map[] = +{ + #ifdef I2C1_SDA_PB7_AF4 + {PB7, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 4}, + #endif + #ifdef I2C1_SDA_PB9_AF4 + {PB9, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 4}, + #endif + #ifdef I2C1_SDA_PG13_AF4 + {PG13, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 4}, + #endif + #ifdef I2C2_SDA_PB11_AF4 + {PB11, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 4}, + #endif + #ifdef I2C2_SDA_PB14_AF4 + {PB14, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 4}, + #endif + #ifdef I2C2_SDA_PF0_AF4 + {PF0, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 4}, + #endif + #ifdef I2C3_SDA_PB4_AF4 + {PB4, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 4}, + #endif + #ifdef I2C3_SDA_PC1_AF4 + {PC1, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 4}, + #endif + #ifdef I2C3_SDA_PC9_AF6 + {PC9, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 6}, + #endif + #ifdef I2C3_SDA_PG8_AF4 + {PG8, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 4}, + #endif + #ifdef I2C4_SDA_PB11_AF3 + {PB11, I2C4_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_4), 3}, + #endif + #ifdef I2C4_SDA_PB7_AF5 + {PB7, I2C4_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_4), 5}, + #endif + #ifdef I2C4_SDA_PD13_AF4 + {PD13, I2C4_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_4), 4}, + #endif + #ifdef I2C4_SDA_PF15_AF4 + {PF15, I2C4_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_4), 4}, + #endif + #ifdef I2C2_SDA_PH5_AF4 + {PH5, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 4}, + #endif + #ifdef I2C3_SDA_PH8_AF4 + {PH8, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 4}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} + //------------ END SDA +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_I2C_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/i2c/hal_ll_i2c_pin_map/implementations/doc_ds_161/hal_ll_i2c_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/i2c/hal_ll_i2c_pin_map/implementations/doc_ds_161/hal_ll_i2c_pin_map.h new file mode 100644 index 000000000..5d01b5211 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/i2c/hal_ll_i2c_pin_map/implementations/doc_ds_161/hal_ll_i2c_pin_map.h @@ -0,0 +1,202 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_i2c_pin_map.h + * @brief I2C HAL LOW LEVEL PIN MAP. + */ + +#ifndef _HAL_LL_I2C_PIN_MAP_H_ +#define _HAL_LL_I2C_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_i2c_module_num(_module_num) (_module_num - 1) + +/*!< @brief Pin function structure */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + uint8_t af; +} hal_ll_i2c_pin_map_t; + +#ifdef I2C_MODULE_1 +#define I2C1_BASE_ADDRESS (0x40005400UL) +#define I2C1_BASE_ADDR I2C1_BASE_ADDRESS +#define HAL_LL_I2C1_BASE_ADDR I2C1_BASE_ADDRESS +#define HAL_LL_I2C1_BASE_ADDRESS I2C1_BASE_ADDRESS +#endif +#ifdef I2C_MODULE_2 +#define I2C2_BASE_ADDRESS (0x40005800UL) +#define I2C2_BASE_ADDR I2C2_BASE_ADDRESS +#define HAL_LL_I2C2_BASE_ADDR I2C2_BASE_ADDRESS +#define HAL_LL_I2C2_BASE_ADDRESS I2C2_BASE_ADDRESS +#endif +#ifdef I2C_MODULE_3 +#define I2C3_BASE_ADDRESS (0x40005C00UL) +#define I2C3_BASE_ADDR I2C3_BASE_ADDRESS +#define HAL_LL_I2C3_BASE_ADDR I2C3_BASE_ADDRESS +#define HAL_LL_I2C3_BASE_ADDRESS I2C3_BASE_ADDRESS +#endif +#ifdef I2C_MODULE_4 +#define I2C4_BASE_ADDRESS (0x40008400UL) +#define I2C4_BASE_ADDR I2C4_BASE_ADDRESS +#define HAL_LL_I2C4_BASE_ADDR I2C4_BASE_ADDRESS +#define HAL_LL_I2C4_BASE_ADDRESS I2C4_BASE_ADDRESS +#endif + +/*!< @brief I2C SCL pins */ +static const hal_ll_i2c_pin_map_t hal_ll_i2c_scl_map[] = +{ + #ifdef I2C1_SCL_PB6_AF4 + {PB6, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 4}, + #endif + #ifdef I2C1_SCL_PB8_AF4 + {PB8, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 4}, + #endif + #ifdef I2C1_SCL_PG14_AF4 + {PG14, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 4}, + #endif + #ifdef I2C2_SCL_PB10_AF4 + {PB10, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 4}, + #endif + #ifdef I2C2_SCL_PB13_AF4 + {PB13, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 4}, + #endif + #ifdef I2C2_SCL_PF1_AF4 + {PF1, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 4}, + #endif + #ifdef I2C3_SCL_PA7_AF4 + {PA7, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 4}, + #endif + #ifdef I2C3_SCL_PC0_AF4 + {PC0, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 4}, + #endif + #ifdef I2C3_SCL_PG7_AF4 + {PG7, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 4}, + #endif + #ifdef I2C4_SCL_PB10_AF3 + {PB10, I2C4_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_4), 3}, + #endif + #ifdef I2C4_SCL_PB6_AF5 + {PB6, I2C4_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_4), 5}, + #endif + #ifdef I2C4_SCL_PD12_AF4 + {PD12, I2C4_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_4), 4}, + #endif + #ifdef I2C4_SCL_PF14_AF4 + {PF14, I2C4_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_4), 4}, + #endif + #ifdef I2C2_SCL_PH4_AF4 + {PH4, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 4}, + #endif + #ifdef I2C3_SCL_PH7_AF4 + {PH7, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 4}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} + //------------ END SCL +}; + +/*!< @brief I2C SDA pins */ +static const hal_ll_i2c_pin_map_t hal_ll_i2c_sda_map[] = +{ + #ifdef I2C1_SDA_PB7_AF4 + {PB7, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 4}, + #endif + #ifdef I2C1_SDA_PB9_AF4 + {PB9, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 4}, + #endif + #ifdef I2C1_SDA_PG13_AF4 + {PG13, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 4}, + #endif + #ifdef I2C2_SDA_PB11_AF4 + {PB11, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 4}, + #endif + #ifdef I2C2_SDA_PB14_AF4 + {PB14, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 4}, + #endif + #ifdef I2C2_SDA_PF0_AF4 + {PF0, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 4}, + #endif + #ifdef I2C3_SDA_PB4_AF4 + {PB4, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 4}, + #endif + #ifdef I2C3_SDA_PC1_AF4 + {PC1, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 4}, + #endif + #ifdef I2C3_SDA_PC9_AF6 + {PC9, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 6}, + #endif + #ifdef I2C3_SDA_PG8_AF4 + {PG8, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 4}, + #endif + #ifdef I2C4_SDA_PB11_AF3 + {PB11, I2C4_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_4), 3}, + #endif + #ifdef I2C4_SDA_PB7_AF5 + {PB7, I2C4_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_4), 5}, + #endif + #ifdef I2C4_SDA_PD13_AF4 + {PD13, I2C4_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_4), 4}, + #endif + #ifdef I2C4_SDA_PF15_AF4 + {PF15, I2C4_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_4), 4}, + #endif + #ifdef I2C2_SDA_PH5_AF4 + {PH5, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 4}, + #endif + #ifdef I2C3_SDA_PH8_AF4 + {PH8, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 4}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} + //------------ END SDA +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_I2C_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/i2c/hal_ll_i2c_pin_map/implementations/doc_ds_2/hal_ll_i2c_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/i2c/hal_ll_i2c_pin_map/implementations/doc_ds_2/hal_ll_i2c_pin_map.h new file mode 100644 index 000000000..7ace8c472 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/i2c/hal_ll_i2c_pin_map/implementations/doc_ds_2/hal_ll_i2c_pin_map.h @@ -0,0 +1,115 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_i2c_pin_map.h + * @brief I2C HAL LOW LEVEL PIN MAP. + */ + +#ifndef _HAL_LL_I2C_PIN_MAP_H_ +#define _HAL_LL_I2C_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_i2c_module_num(_module_num) (_module_num - 1) + +/*!< @brief Pin function structure */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + uint8_t af; +} hal_ll_i2c_pin_map_t; + +#ifdef I2C_MODULE_1 +#define I2C1_BASE_ADDRESS (0x40005400UL) +#define I2C1_BASE_ADDR I2C1_BASE_ADDRESS +#define HAL_LL_I2C1_BASE_ADDR I2C1_BASE_ADDRESS +#define HAL_LL_I2C1_BASE_ADDRESS I2C1_BASE_ADDRESS +#endif + +/*!< @brief I2C SCL pins */ +static const hal_ll_i2c_pin_map_t hal_ll_i2c_scl_map[] = +{ + #ifdef I2C1_SCL_PB6_AF6 + {PB6, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 6}, + #endif + #ifdef I2C1_SCL_PB7_AF14 + {PB7, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 14}, + #endif + #ifdef I2C1_SCL_PB8_AF6 + {PB8, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 6}, + #endif + #ifdef I2C1_SCL_PA9_AF6 + {PA9, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 6}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} + //------------ END SCL +}; + +/*!< @brief I2C SDA pins */ +static const hal_ll_i2c_pin_map_t hal_ll_i2c_sda_map[] = +{ + #ifdef I2C1_SDA_PB7_AF6 + {PB7, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 6}, + #endif + #ifdef I2C1_SDA_PC14_AF14 + {PC14, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 14}, + #endif + #ifdef I2C1_SDA_PA10_AF6 + {PA10, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 6}, + #endif + #ifdef I2C1_SDA_PB9_AF6 + {PB9, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 6}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} + //------------ END SDA +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_I2C_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/i2c/hal_ll_i2c_pin_map/implementations/doc_ds_74/hal_ll_i2c_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/i2c/hal_ll_i2c_pin_map/implementations/doc_ds_74/hal_ll_i2c_pin_map.h new file mode 100644 index 000000000..6469c66f7 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/i2c/hal_ll_i2c_pin_map/implementations/doc_ds_74/hal_ll_i2c_pin_map.h @@ -0,0 +1,133 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_i2c_pin_map.h + * @brief I2C HAL LOW LEVEL PIN MAP. + */ + +#ifndef _HAL_LL_I2C_PIN_MAP_H_ +#define _HAL_LL_I2C_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_i2c_module_num(_module_num) (_module_num - 1) + +/*!< @brief Pin function structure */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + uint8_t af; +} hal_ll_i2c_pin_map_t; + +#ifdef I2C_MODULE_1 +#define I2C1_BASE_ADDRESS (0x40005400UL) +#define I2C1_BASE_ADDR I2C1_BASE_ADDRESS +#define HAL_LL_I2C1_BASE_ADDR I2C1_BASE_ADDRESS +#define HAL_LL_I2C1_BASE_ADDRESS I2C1_BASE_ADDRESS +#endif +#ifdef I2C_MODULE_2 +#define I2C2_BASE_ADDRESS (0x40005800UL) +#define I2C2_BASE_ADDR I2C2_BASE_ADDRESS +#define HAL_LL_I2C2_BASE_ADDR I2C2_BASE_ADDRESS +#define HAL_LL_I2C2_BASE_ADDRESS I2C2_BASE_ADDRESS +#endif + +/*!< @brief I2C SCL pins */ +static const hal_ll_i2c_pin_map_t hal_ll_i2c_scl_map[] = +{ + #ifdef I2C1_SCL_PA9_AF6 + {PA9, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 6}, + #endif + #ifdef I2C1_SCL_PB6_AF6 + {PB6, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 6}, + #endif + #ifdef I2C1_SCL_PB8_AF6 + {PB8, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 6}, + #endif + #ifdef I2C2_SCL_PA11_AF6 + {PA11, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 6}, + #endif + #ifdef I2C2_SCL_PB10_AF6 + {PB10, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 6}, + #endif + #ifdef I2C2_SCL_PB13_AF6 + {PB13, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 6}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} + //------------ END SCL +}; + +/*!< @brief I2C SDA pins */ +static const hal_ll_i2c_pin_map_t hal_ll_i2c_sda_map[] = +{ + #ifdef I2C1_SDA_PA10_AF6 + {PA10, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 6}, + #endif + #ifdef I2C1_SDA_PB7_AF6 + {PB7, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 6}, + #endif + #ifdef I2C1_SDA_PB9_AF6 + {PB9, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 6}, + #endif + #ifdef I2C2_SDA_PA12_AF6 + {PA12, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 6}, + #endif + #ifdef I2C2_SDA_PB11_AF6 + {PB11, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 6}, + #endif + #ifdef I2C2_SDA_PB14_AF6 + {PB14, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 6}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} + //------------ END SDA +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_I2C_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/i2c/hal_ll_i2c_pin_map/implementations/doc_ds_75/hal_ll_i2c_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/i2c/hal_ll_i2c_pin_map/implementations/doc_ds_75/hal_ll_i2c_pin_map.h new file mode 100644 index 000000000..6469c66f7 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/i2c/hal_ll_i2c_pin_map/implementations/doc_ds_75/hal_ll_i2c_pin_map.h @@ -0,0 +1,133 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_i2c_pin_map.h + * @brief I2C HAL LOW LEVEL PIN MAP. + */ + +#ifndef _HAL_LL_I2C_PIN_MAP_H_ +#define _HAL_LL_I2C_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_i2c_module_num(_module_num) (_module_num - 1) + +/*!< @brief Pin function structure */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + uint8_t af; +} hal_ll_i2c_pin_map_t; + +#ifdef I2C_MODULE_1 +#define I2C1_BASE_ADDRESS (0x40005400UL) +#define I2C1_BASE_ADDR I2C1_BASE_ADDRESS +#define HAL_LL_I2C1_BASE_ADDR I2C1_BASE_ADDRESS +#define HAL_LL_I2C1_BASE_ADDRESS I2C1_BASE_ADDRESS +#endif +#ifdef I2C_MODULE_2 +#define I2C2_BASE_ADDRESS (0x40005800UL) +#define I2C2_BASE_ADDR I2C2_BASE_ADDRESS +#define HAL_LL_I2C2_BASE_ADDR I2C2_BASE_ADDRESS +#define HAL_LL_I2C2_BASE_ADDRESS I2C2_BASE_ADDRESS +#endif + +/*!< @brief I2C SCL pins */ +static const hal_ll_i2c_pin_map_t hal_ll_i2c_scl_map[] = +{ + #ifdef I2C1_SCL_PA9_AF6 + {PA9, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 6}, + #endif + #ifdef I2C1_SCL_PB6_AF6 + {PB6, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 6}, + #endif + #ifdef I2C1_SCL_PB8_AF6 + {PB8, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 6}, + #endif + #ifdef I2C2_SCL_PA11_AF6 + {PA11, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 6}, + #endif + #ifdef I2C2_SCL_PB10_AF6 + {PB10, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 6}, + #endif + #ifdef I2C2_SCL_PB13_AF6 + {PB13, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 6}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} + //------------ END SCL +}; + +/*!< @brief I2C SDA pins */ +static const hal_ll_i2c_pin_map_t hal_ll_i2c_sda_map[] = +{ + #ifdef I2C1_SDA_PA10_AF6 + {PA10, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 6}, + #endif + #ifdef I2C1_SDA_PB7_AF6 + {PB7, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 6}, + #endif + #ifdef I2C1_SDA_PB9_AF6 + {PB9, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 6}, + #endif + #ifdef I2C2_SDA_PA12_AF6 + {PA12, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 6}, + #endif + #ifdef I2C2_SDA_PB11_AF6 + {PB11, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 6}, + #endif + #ifdef I2C2_SDA_PB14_AF6 + {PB14, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 6}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} + //------------ END SDA +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_I2C_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/i2c/hal_ll_i2c_pin_map/implementations/doc_ds_80/hal_ll_i2c_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/i2c/hal_ll_i2c_pin_map/implementations/doc_ds_80/hal_ll_i2c_pin_map.h new file mode 100644 index 000000000..50b32d491 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/i2c/hal_ll_i2c_pin_map/implementations/doc_ds_80/hal_ll_i2c_pin_map.h @@ -0,0 +1,175 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_i2c_pin_map.h + * @brief I2C HAL LOW LEVEL PIN MAP. + */ + +#ifndef _HAL_LL_I2C_PIN_MAP_H_ +#define _HAL_LL_I2C_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_i2c_module_num(_module_num) (_module_num - 1) + +/*!< @brief Pin function structure */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + uint8_t af; +} hal_ll_i2c_pin_map_t; + +#ifdef I2C_MODULE_1 +#define I2C1_BASE_ADDRESS (0x40005400UL) +#define I2C1_BASE_ADDR I2C1_BASE_ADDRESS +#define HAL_LL_I2C1_BASE_ADDR I2C1_BASE_ADDRESS +#define HAL_LL_I2C1_BASE_ADDRESS I2C1_BASE_ADDRESS +#endif +#ifdef I2C_MODULE_2 +#define I2C2_BASE_ADDRESS (0x40005800UL) +#define I2C2_BASE_ADDR I2C2_BASE_ADDRESS +#define HAL_LL_I2C2_BASE_ADDR I2C2_BASE_ADDRESS +#define HAL_LL_I2C2_BASE_ADDRESS I2C2_BASE_ADDRESS +#endif +#ifdef I2C_MODULE_3 +#define I2C3_BASE_ADDRESS (0x40008800UL) +#define I2C3_BASE_ADDR I2C3_BASE_ADDRESS +#define HAL_LL_I2C3_BASE_ADDR I2C3_BASE_ADDRESS +#define HAL_LL_I2C3_BASE_ADDRESS I2C3_BASE_ADDRESS +#endif + +/*!< @brief I2C SCL pins */ +static const hal_ll_i2c_pin_map_t hal_ll_i2c_scl_map[] = +{ + #ifdef I2C1_SCL_PA9_AF6 + {PA9, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 6}, + #endif + #ifdef I2C1_SCL_PB6_AF6 + {PB6, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 6}, + #endif + #ifdef I2C1_SCL_PB8_AF6 + {PB8, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 6}, + #endif + #ifdef I2C2_SCL_PA11_AF6 + {PA11, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 6}, + #endif + #ifdef I2C2_SCL_PA7_AF8 + {PA7, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 8}, + #endif + #ifdef I2C2_SCL_PA9_AF8 + {PA9, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 8}, + #endif + #ifdef I2C2_SCL_PB10_AF6 + {PB10, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 6}, + #endif + #ifdef I2C2_SCL_PB13_AF6 + {PB13, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 6}, + #endif + #ifdef I2C2_SCL_PB3_AF8 + {PB3, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 8}, + #endif + #ifdef I2C3_SCL_PA7_AF9 + {PA7, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 9}, + #endif + #ifdef I2C3_SCL_PB3_AF6 + {PB3, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 6}, + #endif + #ifdef I2C3_SCL_PC0_AF6 + {PC0, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 6}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} + //------------ END SCL +}; + +/*!< @brief I2C SDA pins */ +static const hal_ll_i2c_pin_map_t hal_ll_i2c_sda_map[] = +{ + #ifdef I2C1_SDA_PA10_AF6 + {PA10, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 6}, + #endif + #ifdef I2C1_SDA_PB7_AF6 + {PB7, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 6}, + #endif + #ifdef I2C1_SDA_PB9_AF6 + {PB9, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 6}, + #endif + #ifdef I2C2_SDA_PA10_AF8 + {PA10, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 8}, + #endif + #ifdef I2C2_SDA_PA12_AF6 + {PA12, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 6}, + #endif + #ifdef I2C2_SDA_PA6_AF8 + {PA6, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 8}, + #endif + #ifdef I2C2_SDA_PB11_AF6 + {PB11, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 6}, + #endif + #ifdef I2C2_SDA_PB14_AF6 + {PB14, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 6}, + #endif + #ifdef I2C2_SDA_PB4_AF8 + {PB4, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 8}, + #endif + #ifdef I2C3_SDA_PA6_AF9 + {PA6, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 9}, + #endif + #ifdef I2C3_SDA_PB4_AF6 + {PB4, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 6}, + #endif + #ifdef I2C3_SDA_PC1_AF6 + {PC1, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 6}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} + //------------ END SDA +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_I2C_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/i2c/hal_ll_i2c_pin_map/implementations/doc_ds_81/hal_ll_i2c_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/i2c/hal_ll_i2c_pin_map/implementations/doc_ds_81/hal_ll_i2c_pin_map.h new file mode 100644 index 000000000..50b32d491 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/i2c/hal_ll_i2c_pin_map/implementations/doc_ds_81/hal_ll_i2c_pin_map.h @@ -0,0 +1,175 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_i2c_pin_map.h + * @brief I2C HAL LOW LEVEL PIN MAP. + */ + +#ifndef _HAL_LL_I2C_PIN_MAP_H_ +#define _HAL_LL_I2C_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_i2c_module_num(_module_num) (_module_num - 1) + +/*!< @brief Pin function structure */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + uint8_t af; +} hal_ll_i2c_pin_map_t; + +#ifdef I2C_MODULE_1 +#define I2C1_BASE_ADDRESS (0x40005400UL) +#define I2C1_BASE_ADDR I2C1_BASE_ADDRESS +#define HAL_LL_I2C1_BASE_ADDR I2C1_BASE_ADDRESS +#define HAL_LL_I2C1_BASE_ADDRESS I2C1_BASE_ADDRESS +#endif +#ifdef I2C_MODULE_2 +#define I2C2_BASE_ADDRESS (0x40005800UL) +#define I2C2_BASE_ADDR I2C2_BASE_ADDRESS +#define HAL_LL_I2C2_BASE_ADDR I2C2_BASE_ADDRESS +#define HAL_LL_I2C2_BASE_ADDRESS I2C2_BASE_ADDRESS +#endif +#ifdef I2C_MODULE_3 +#define I2C3_BASE_ADDRESS (0x40008800UL) +#define I2C3_BASE_ADDR I2C3_BASE_ADDRESS +#define HAL_LL_I2C3_BASE_ADDR I2C3_BASE_ADDRESS +#define HAL_LL_I2C3_BASE_ADDRESS I2C3_BASE_ADDRESS +#endif + +/*!< @brief I2C SCL pins */ +static const hal_ll_i2c_pin_map_t hal_ll_i2c_scl_map[] = +{ + #ifdef I2C1_SCL_PA9_AF6 + {PA9, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 6}, + #endif + #ifdef I2C1_SCL_PB6_AF6 + {PB6, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 6}, + #endif + #ifdef I2C1_SCL_PB8_AF6 + {PB8, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 6}, + #endif + #ifdef I2C2_SCL_PA11_AF6 + {PA11, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 6}, + #endif + #ifdef I2C2_SCL_PA7_AF8 + {PA7, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 8}, + #endif + #ifdef I2C2_SCL_PA9_AF8 + {PA9, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 8}, + #endif + #ifdef I2C2_SCL_PB10_AF6 + {PB10, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 6}, + #endif + #ifdef I2C2_SCL_PB13_AF6 + {PB13, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 6}, + #endif + #ifdef I2C2_SCL_PB3_AF8 + {PB3, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 8}, + #endif + #ifdef I2C3_SCL_PA7_AF9 + {PA7, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 9}, + #endif + #ifdef I2C3_SCL_PB3_AF6 + {PB3, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 6}, + #endif + #ifdef I2C3_SCL_PC0_AF6 + {PC0, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 6}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} + //------------ END SCL +}; + +/*!< @brief I2C SDA pins */ +static const hal_ll_i2c_pin_map_t hal_ll_i2c_sda_map[] = +{ + #ifdef I2C1_SDA_PA10_AF6 + {PA10, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 6}, + #endif + #ifdef I2C1_SDA_PB7_AF6 + {PB7, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 6}, + #endif + #ifdef I2C1_SDA_PB9_AF6 + {PB9, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 6}, + #endif + #ifdef I2C2_SDA_PA10_AF8 + {PA10, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 8}, + #endif + #ifdef I2C2_SDA_PA12_AF6 + {PA12, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 6}, + #endif + #ifdef I2C2_SDA_PA6_AF8 + {PA6, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 8}, + #endif + #ifdef I2C2_SDA_PB11_AF6 + {PB11, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 6}, + #endif + #ifdef I2C2_SDA_PB14_AF6 + {PB14, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 6}, + #endif + #ifdef I2C2_SDA_PB4_AF8 + {PB4, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 8}, + #endif + #ifdef I2C3_SDA_PA6_AF9 + {PA6, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 9}, + #endif + #ifdef I2C3_SDA_PB4_AF6 + {PB4, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 6}, + #endif + #ifdef I2C3_SDA_PC1_AF6 + {PC1, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 6}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} + //------------ END SDA +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_I2C_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/i2c/hal_ll_i2c_pin_map/implementations/doc_ds_82/hal_ll_i2c_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/i2c/hal_ll_i2c_pin_map/implementations/doc_ds_82/hal_ll_i2c_pin_map.h new file mode 100644 index 000000000..5ea83a7b0 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/i2c/hal_ll_i2c_pin_map/implementations/doc_ds_82/hal_ll_i2c_pin_map.h @@ -0,0 +1,148 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_i2c_pin_map.h + * @brief I2C HAL LOW LEVEL PIN MAP. + */ + +#ifndef _HAL_LL_I2C_PIN_MAP_H_ +#define _HAL_LL_I2C_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_i2c_module_num(_module_num) (_module_num - 1) + +/*!< @brief Pin function structure */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + uint8_t af; +} hal_ll_i2c_pin_map_t; + +#ifdef I2C_MODULE_1 +#define I2C1_BASE_ADDRESS (0x40005400UL) +#define I2C1_BASE_ADDR I2C1_BASE_ADDRESS +#define HAL_LL_I2C1_BASE_ADDR I2C1_BASE_ADDRESS +#define HAL_LL_I2C1_BASE_ADDRESS I2C1_BASE_ADDRESS +#endif +#ifdef I2C_MODULE_2 +#define I2C2_BASE_ADDRESS (0x40005800UL) +#define I2C2_BASE_ADDR I2C2_BASE_ADDRESS +#define HAL_LL_I2C2_BASE_ADDR I2C2_BASE_ADDRESS +#define HAL_LL_I2C2_BASE_ADDRESS I2C2_BASE_ADDRESS +#endif +#ifdef I2C_MODULE_3 +#define I2C3_BASE_ADDRESS (0x40007800UL) +#define I2C3_BASE_ADDR I2C3_BASE_ADDRESS +#define HAL_LL_I2C3_BASE_ADDR I2C3_BASE_ADDRESS +#define HAL_LL_I2C3_BASE_ADDRESS I2C3_BASE_ADDRESS +#endif + +/*!< @brief I2C SCL pins */ +static const hal_ll_i2c_pin_map_t hal_ll_i2c_scl_map[] = +{ + #ifdef I2C1_SCL_PA13_AF4 + {PA13, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 4}, + #endif + #ifdef I2C1_SCL_PA15_AF4 + {PA15, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 4}, + #endif + #ifdef I2C1_SCL_PB8_AF4 + {PB8, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 4}, + #endif + #ifdef I2C2_SCL_PA9_AF4 + {PA9, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 4}, + #endif + #ifdef I2C3_SCL_PA8_AF2 + {PA8, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 2}, + #endif + #ifdef I2C2_SCL_PC4_AF4 + {PC4, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 4}, + #endif + #ifdef I2C3_SCL_PC8_AF8 + {PC8, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 8}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} + //------------ END SCL +}; + +/*!< @brief I2C SDA pins */ +static const hal_ll_i2c_pin_map_t hal_ll_i2c_sda_map[] = +{ + #ifdef I2C1_SDA_PA14_AF4 + {PA14, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 4}, + #endif + #ifdef I2C1_SDA_PB7_AF4 + {PB7, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 4}, + #endif + #ifdef I2C2_SDA_PA8_AF4 + {PA8, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 4}, + #endif + #ifdef I2C2_SDA_PF0_AF4 + {PF0, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 4}, + #endif + #ifdef I2C3_SDA_PB5_AF8 + {PB5, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 8}, + #endif + #ifdef I2C1_SDA_PB9_AF4 + {PB9, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 4}, + #endif + #ifdef I2C3_SDA_PC11_AF8 + {PC11, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 8}, + #endif + #ifdef I2C3_SDA_PC9_AF8 + {PC9, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 8}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} + //------------ END SDA +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_I2C_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/i2c/hal_ll_i2c_pin_map/implementations/doc_ds_83/hal_ll_i2c_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/i2c/hal_ll_i2c_pin_map/implementations/doc_ds_83/hal_ll_i2c_pin_map.h new file mode 100644 index 000000000..21fbad421 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/i2c/hal_ll_i2c_pin_map/implementations/doc_ds_83/hal_ll_i2c_pin_map.h @@ -0,0 +1,148 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_i2c_pin_map.h + * @brief I2C HAL LOW LEVEL PIN MAP. + */ + +#ifndef _HAL_LL_I2C_PIN_MAP_H_ +#define _HAL_LL_I2C_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_i2c_module_num(_module_num) (_module_num - 1) + +/*!< @brief Pin function structure */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + uint8_t af; +} hal_ll_i2c_pin_map_t; + +#ifdef I2C_MODULE_1 +#define I2C1_BASE_ADDRESS (0x40005400UL) +#define I2C1_BASE_ADDR I2C1_BASE_ADDRESS +#define HAL_LL_I2C1_BASE_ADDR I2C1_BASE_ADDRESS +#define HAL_LL_I2C1_BASE_ADDRESS I2C1_BASE_ADDRESS +#endif +#ifdef I2C_MODULE_2 +#define I2C2_BASE_ADDRESS (0x40005800UL) +#define I2C2_BASE_ADDR I2C2_BASE_ADDRESS +#define HAL_LL_I2C2_BASE_ADDR I2C2_BASE_ADDRESS +#define HAL_LL_I2C2_BASE_ADDRESS I2C2_BASE_ADDRESS +#endif +#ifdef I2C_MODULE_3 +#define I2C3_BASE_ADDRESS (0x40007800UL) +#define I2C3_BASE_ADDR I2C3_BASE_ADDRESS +#define HAL_LL_I2C3_BASE_ADDR I2C3_BASE_ADDRESS +#define HAL_LL_I2C3_BASE_ADDRESS I2C3_BASE_ADDRESS +#endif + +/*!< @brief I2C SCL pins */ +static const hal_ll_i2c_pin_map_t hal_ll_i2c_scl_map[] = +{ + #ifdef I2C1_SCL_PA13_AF4 + {PA13, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 4}, + #endif + #ifdef I2C1_SCL_PA15_AF4 + {PA15, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 4}, + #endif + #ifdef I2C1_SCL_PB8_AF4 + {PB8, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 4}, + #endif + #ifdef I2C2_SCL_PA9_AF4 + {PA9, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 4}, + #endif + #ifdef I2C2_SCL_PC4_AF4 + {PC4, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 4}, + #endif + #ifdef I2C3_SCL_PA8_AF2 + {PA8, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 2}, + #endif + #ifdef I2C3_SCL_PC8_AF8 + {PC8, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 8}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} + //------------ END SCL +}; + +/*!< @brief I2C SDA pins */ +static const hal_ll_i2c_pin_map_t hal_ll_i2c_sda_map[] = +{ + #ifdef I2C1_SDA_PA14_AF4 + {PA14, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 4}, + #endif + #ifdef I2C1_SDA_PB7_AF4 + {PB7, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 4}, + #endif + #ifdef I2C1_SDA_PB9_AF4 + {PB9, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 4}, + #endif + #ifdef I2C2_SDA_PA8_AF4 + {PA8, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 4}, + #endif + #ifdef I2C2_SDA_PF0_AF4 + {PF0, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 4}, + #endif + #ifdef I2C3_SDA_PB5_AF8 + {PB5, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 8}, + #endif + #ifdef I2C3_SDA_PC11_AF8 + {PC11, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 8}, + #endif + #ifdef I2C3_SDA_PC9_AF8 + {PC9, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 8}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} + //------------ END SDA +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_I2C_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/i2c/hal_ll_i2c_pin_map/implementations/doc_ds_84/hal_ll_i2c_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/i2c/hal_ll_i2c_pin_map/implementations/doc_ds_84/hal_ll_i2c_pin_map.h new file mode 100644 index 000000000..8c69de998 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/i2c/hal_ll_i2c_pin_map/implementations/doc_ds_84/hal_ll_i2c_pin_map.h @@ -0,0 +1,193 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_i2c_pin_map.h + * @brief I2C HAL LOW LEVEL PIN MAP. + */ + +#ifndef _HAL_LL_I2C_PIN_MAP_H_ +#define _HAL_LL_I2C_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_i2c_module_num(_module_num) (_module_num - 1) + +/*!< @brief Pin function structure */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + uint8_t af; +} hal_ll_i2c_pin_map_t; + +#ifdef I2C_MODULE_1 +#define I2C1_BASE_ADDRESS (0x40005400UL) +#define I2C1_BASE_ADDR I2C1_BASE_ADDRESS +#define HAL_LL_I2C1_BASE_ADDR I2C1_BASE_ADDRESS +#define HAL_LL_I2C1_BASE_ADDRESS I2C1_BASE_ADDRESS +#endif +#ifdef I2C_MODULE_2 +#define I2C2_BASE_ADDRESS (0x40005800UL) +#define I2C2_BASE_ADDR I2C2_BASE_ADDRESS +#define HAL_LL_I2C2_BASE_ADDR I2C2_BASE_ADDRESS +#define HAL_LL_I2C2_BASE_ADDRESS I2C2_BASE_ADDRESS +#endif +#ifdef I2C_MODULE_3 +#define I2C3_BASE_ADDRESS (0x40007800UL) +#define I2C3_BASE_ADDR I2C3_BASE_ADDRESS +#define HAL_LL_I2C3_BASE_ADDR I2C3_BASE_ADDRESS +#define HAL_LL_I2C3_BASE_ADDRESS I2C3_BASE_ADDRESS +#endif +#ifdef I2C_MODULE_4 +#define I2C4_BASE_ADDRESS (0x40008400UL) +#define I2C4_BASE_ADDR I2C4_BASE_ADDRESS +#define HAL_LL_I2C4_BASE_ADDR I2C4_BASE_ADDRESS +#define HAL_LL_I2C4_BASE_ADDRESS I2C4_BASE_ADDRESS +#endif + +/*!< @brief I2C SCL pins */ +static const hal_ll_i2c_pin_map_t hal_ll_i2c_scl_map[] = +{ + #ifdef I2C1_SCL_PA13_AF4 + {PA13, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 4}, + #endif + #ifdef I2C1_SCL_PA15_AF4 + {PA15, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 4}, + #endif + #ifdef I2C1_SCL_PB8_AF4 + {PB8, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 4}, + #endif + #ifdef I2C2_SCL_PA9_AF4 + {PA9, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 4}, + #endif + #ifdef I2C2_SCL_PC4_AF4 + {PC4, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 4}, + #endif + #ifdef I2C2_SCL_PF6_AF4 + {PF6, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 4}, + #endif + #ifdef I2C3_SCL_PA8_AF2 + {PA8, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 2}, + #endif + #ifdef I2C3_SCL_PC8_AF8 + {PC8, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 8}, + #endif + #ifdef I2C3_SCL_PF3_AF4 + {PF3, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 4}, + #endif + #ifdef I2C4_SCL_PA13_AF3 + {PA13, I2C4_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_4), 3}, + #endif + #ifdef I2C4_SCL_PC6_AF8 + {PC6, I2C4_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_4), 8}, + #endif + #ifdef I2C4_SCL_PF14_AF4 + {PF14, I2C4_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_4), 4}, + #endif + #ifdef I2C4_SCL_PG3_AF4 + {PG3, I2C4_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_4), 4}, + #endif + #ifdef I2C3_SCL_PG7_AF4 + {PG7, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 4}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} + //------------ END SCL +}; + +/*!< @brief I2C SDA pins */ +static const hal_ll_i2c_pin_map_t hal_ll_i2c_sda_map[] = +{ + #ifdef I2C1_SDA_PA14_AF4 + {PA14, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 4}, + #endif + #ifdef I2C1_SDA_PB7_AF4 + {PB7, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 4}, + #endif + #ifdef I2C1_SDA_PB9_AF4 + {PB9, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 4}, + #endif + #ifdef I2C2_SDA_PA8_AF4 + {PA8, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 4}, + #endif + #ifdef I2C2_SDA_PF0_AF4 + {PF0, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 4}, + #endif + #ifdef I2C3_SDA_PB5_AF8 + {PB5, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 8}, + #endif + #ifdef I2C3_SDA_PC11_AF8 + {PC11, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 8}, + #endif + #ifdef I2C3_SDA_PC9_AF8 + {PC9, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 8}, + #endif + #ifdef I2C3_SDA_PF4_AF4 + {PF4, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 4}, + #endif + #ifdef I2C4_SDA_PB7_AF3 + {PB7, I2C4_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_4), 3}, + #endif + #ifdef I2C4_SDA_PC7_AF8 + {PC7, I2C4_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_4), 8}, + #endif + #ifdef I2C4_SDA_PF15_AF4 + {PF15, I2C4_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_4), 4}, + #endif + #ifdef I2C4_SDA_PG4_AF4 + {PG4, I2C4_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_4), 4}, + #endif + #ifdef I2C3_SDA_PG8_AF4 + {PG8, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 4}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} + //------------ END SDA +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_I2C_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/i2c/hal_ll_i2c_pin_map/implementations/doc_ds_85/hal_ll_i2c_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/i2c/hal_ll_i2c_pin_map/implementations/doc_ds_85/hal_ll_i2c_pin_map.h new file mode 100644 index 000000000..7cefe92d8 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/i2c/hal_ll_i2c_pin_map/implementations/doc_ds_85/hal_ll_i2c_pin_map.h @@ -0,0 +1,193 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_i2c_pin_map.h + * @brief I2C HAL LOW LEVEL PIN MAP. + */ + +#ifndef _HAL_LL_I2C_PIN_MAP_H_ +#define _HAL_LL_I2C_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_i2c_module_num(_module_num) (_module_num - 1) + +/*!< @brief Pin function structure */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + uint8_t af; +} hal_ll_i2c_pin_map_t; + +#ifdef I2C_MODULE_1 +#define I2C1_BASE_ADDRESS (0x40005400UL) +#define I2C1_BASE_ADDR I2C1_BASE_ADDRESS +#define HAL_LL_I2C1_BASE_ADDR I2C1_BASE_ADDRESS +#define HAL_LL_I2C1_BASE_ADDRESS I2C1_BASE_ADDRESS +#endif +#ifdef I2C_MODULE_2 +#define I2C2_BASE_ADDRESS (0x40005800UL) +#define I2C2_BASE_ADDR I2C2_BASE_ADDRESS +#define HAL_LL_I2C2_BASE_ADDR I2C2_BASE_ADDRESS +#define HAL_LL_I2C2_BASE_ADDRESS I2C2_BASE_ADDRESS +#endif +#ifdef I2C_MODULE_3 +#define I2C3_BASE_ADDRESS (0x40007800UL) +#define I2C3_BASE_ADDR I2C3_BASE_ADDRESS +#define HAL_LL_I2C3_BASE_ADDR I2C3_BASE_ADDRESS +#define HAL_LL_I2C3_BASE_ADDRESS I2C3_BASE_ADDRESS +#endif +#ifdef I2C_MODULE_4 +#define I2C4_BASE_ADDRESS (0x40008400UL) +#define I2C4_BASE_ADDR I2C4_BASE_ADDRESS +#define HAL_LL_I2C4_BASE_ADDR I2C4_BASE_ADDRESS +#define HAL_LL_I2C4_BASE_ADDRESS I2C4_BASE_ADDRESS +#endif + +/*!< @brief I2C SCL pins */ +static const hal_ll_i2c_pin_map_t hal_ll_i2c_scl_map[] = +{ + #ifdef I2C1_SCL_PA13_AF4 + {PA13, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 4}, + #endif + #ifdef I2C1_SCL_PA15_AF4 + {PA15, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 4}, + #endif + #ifdef I2C1_SCL_PB8_AF4 + {PB8, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 4}, + #endif + #ifdef I2C2_SCL_PA9_AF4 + {PA9, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 4}, + #endif + #ifdef I2C2_SCL_PC4_AF4 + {PC4, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 4}, + #endif + #ifdef I2C3_SCL_PA8_AF2 + {PA8, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 2}, + #endif + #ifdef I2C4_SCL_PA13_AF3 + {PA13, I2C4_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_4), 3}, + #endif + #ifdef I2C4_SCL_PC6_AF8 + {PC6, I2C4_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_4), 8}, + #endif + #ifdef I2C3_SCL_PC8_AF8 + {PC8, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 8}, + #endif + #ifdef I2C2_SCL_PF6_AF4 + {PF6, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 4}, + #endif + #ifdef I2C3_SCL_PF3_AF4 + {PF3, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 4}, + #endif + #ifdef I2C4_SCL_PF14_AF4 + {PF14, I2C4_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_4), 4}, + #endif + #ifdef I2C4_SCL_PG3_AF4 + {PG3, I2C4_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_4), 4}, + #endif + #ifdef I2C3_SCL_PG7_AF4 + {PG7, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 4}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} + //------------ END SCL +}; + +/*!< @brief I2C SDA pins */ +static const hal_ll_i2c_pin_map_t hal_ll_i2c_sda_map[] = +{ + #ifdef I2C1_SDA_PA14_AF4 + {PA14, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 4}, + #endif + #ifdef I2C1_SDA_PB7_AF4 + {PB7, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 4}, + #endif + #ifdef I2C1_SDA_PB9_AF4 + {PB9, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 4}, + #endif + #ifdef I2C2_SDA_PA8_AF4 + {PA8, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 4}, + #endif + #ifdef I2C2_SDA_PF0_AF4 + {PF0, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 4}, + #endif + #ifdef I2C3_SDA_PB5_AF8 + {PB5, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 8}, + #endif + #ifdef I2C3_SDA_PC11_AF8 + {PC11, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 8}, + #endif + #ifdef I2C4_SDA_PB7_AF3 + {PB7, I2C4_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_4), 3}, + #endif + #ifdef I2C3_SDA_PC9_AF8 + {PC9, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 8}, + #endif + #ifdef I2C4_SDA_PC7_AF8 + {PC7, I2C4_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_4), 8}, + #endif + #ifdef I2C3_SDA_PF4_AF4 + {PF4, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 4}, + #endif + #ifdef I2C4_SDA_PF15_AF4 + {PF15, I2C4_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_4), 4}, + #endif + #ifdef I2C4_SDA_PG4_AF4 + {PG4, I2C4_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_4), 4}, + #endif + #ifdef I2C3_SDA_PG8_AF4 + {PG8, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 4}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} + //------------ END SDA +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_I2C_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/i2c/hal_ll_i2c_pin_map/implementations/doc_ds_86/hal_ll_i2c_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/i2c/hal_ll_i2c_pin_map/implementations/doc_ds_86/hal_ll_i2c_pin_map.h new file mode 100644 index 000000000..58470920f --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/i2c/hal_ll_i2c_pin_map/implementations/doc_ds_86/hal_ll_i2c_pin_map.h @@ -0,0 +1,193 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_i2c_pin_map.h + * @brief I2C HAL LOW LEVEL PIN MAP. + */ + +#ifndef _HAL_LL_I2C_PIN_MAP_H_ +#define _HAL_LL_I2C_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_i2c_module_num(_module_num) (_module_num - 1) + +/*!< @brief Pin function structure */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + uint8_t af; +} hal_ll_i2c_pin_map_t; + +#ifdef I2C_MODULE_1 +#define I2C1_BASE_ADDRESS (0x40005400UL) +#define I2C1_BASE_ADDR I2C1_BASE_ADDRESS +#define HAL_LL_I2C1_BASE_ADDR I2C1_BASE_ADDRESS +#define HAL_LL_I2C1_BASE_ADDRESS I2C1_BASE_ADDRESS +#endif +#ifdef I2C_MODULE_2 +#define I2C2_BASE_ADDRESS (0x40005800UL) +#define I2C2_BASE_ADDR I2C2_BASE_ADDRESS +#define HAL_LL_I2C2_BASE_ADDR I2C2_BASE_ADDRESS +#define HAL_LL_I2C2_BASE_ADDRESS I2C2_BASE_ADDRESS +#endif +#ifdef I2C_MODULE_3 +#define I2C3_BASE_ADDRESS (0x40007800UL) +#define I2C3_BASE_ADDR I2C3_BASE_ADDRESS +#define HAL_LL_I2C3_BASE_ADDR I2C3_BASE_ADDRESS +#define HAL_LL_I2C3_BASE_ADDRESS I2C3_BASE_ADDRESS +#endif +#ifdef I2C_MODULE_4 +#define I2C4_BASE_ADDRESS (0x40008400UL) +#define I2C4_BASE_ADDR I2C4_BASE_ADDRESS +#define HAL_LL_I2C4_BASE_ADDR I2C4_BASE_ADDRESS +#define HAL_LL_I2C4_BASE_ADDRESS I2C4_BASE_ADDRESS +#endif + +/*!< @brief I2C SCL pins */ +static const hal_ll_i2c_pin_map_t hal_ll_i2c_scl_map[] = +{ + #ifdef I2C1_SCL_PA13_AF4 + {PA13, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 4}, + #endif + #ifdef I2C1_SCL_PA15_AF4 + {PA15, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 4}, + #endif + #ifdef I2C1_SCL_PB8_AF4 + {PB8, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 4}, + #endif + #ifdef I2C2_SCL_PA9_AF4 + {PA9, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 4}, + #endif + #ifdef I2C2_SCL_PC4_AF4 + {PC4, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 4}, + #endif + #ifdef I2C2_SCL_PF6_AF4 + {PF6, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 4}, + #endif + #ifdef I2C3_SCL_PA8_AF2 + {PA8, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 2}, + #endif + #ifdef I2C3_SCL_PC8_AF8 + {PC8, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 8}, + #endif + #ifdef I2C3_SCL_PF3_AF4 + {PF3, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 4}, + #endif + #ifdef I2C3_SCL_PG7_AF4 + {PG7, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 4}, + #endif + #ifdef I2C4_SCL_PA13_AF3 + {PA13, I2C4_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_4), 3}, + #endif + #ifdef I2C4_SCL_PC6_AF8 + {PC6, I2C4_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_4), 8}, + #endif + #ifdef I2C4_SCL_PF14_AF4 + {PF14, I2C4_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_4), 4}, + #endif + #ifdef I2C4_SCL_PG3_AF4 + {PG3, I2C4_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_4), 4}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} + //------------ END SCL +}; + +/*!< @brief I2C SDA pins */ +static const hal_ll_i2c_pin_map_t hal_ll_i2c_sda_map[] = +{ + #ifdef I2C1_SDA_PA14_AF4 + {PA14, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 4}, + #endif + #ifdef I2C1_SDA_PB7_AF4 + {PB7, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 4}, + #endif + #ifdef I2C1_SDA_PB9_AF4 + {PB9, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 4}, + #endif + #ifdef I2C2_SDA_PA8_AF4 + {PA8, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 4}, + #endif + #ifdef I2C2_SDA_PF0_AF4 + {PF0, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 4}, + #endif + #ifdef I2C3_SDA_PB5_AF8 + {PB5, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 8}, + #endif + #ifdef I2C3_SDA_PC11_AF8 + {PC11, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 8}, + #endif + #ifdef I2C3_SDA_PC9_AF8 + {PC9, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 8}, + #endif + #ifdef I2C3_SDA_PF4_AF4 + {PF4, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 4}, + #endif + #ifdef I2C3_SDA_PG8_AF4 + {PG8, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 4}, + #endif + #ifdef I2C4_SDA_PB7_AF3 + {PB7, I2C4_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_4), 3}, + #endif + #ifdef I2C4_SDA_PC7_AF8 + {PC7, I2C4_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_4), 8}, + #endif + #ifdef I2C4_SDA_PF15_AF4 + {PF15, I2C4_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_4), 4}, + #endif + #ifdef I2C4_SDA_PG4_AF4 + {PG4, I2C4_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_4), 4}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} + //------------ END SDA +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_I2C_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/i2c/hal_ll_i2c_pin_map/implementations/doc_ds_87/hal_ll_i2c_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/i2c/hal_ll_i2c_pin_map/implementations/doc_ds_87/hal_ll_i2c_pin_map.h new file mode 100644 index 000000000..58470920f --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/i2c/hal_ll_i2c_pin_map/implementations/doc_ds_87/hal_ll_i2c_pin_map.h @@ -0,0 +1,193 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_i2c_pin_map.h + * @brief I2C HAL LOW LEVEL PIN MAP. + */ + +#ifndef _HAL_LL_I2C_PIN_MAP_H_ +#define _HAL_LL_I2C_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_i2c_module_num(_module_num) (_module_num - 1) + +/*!< @brief Pin function structure */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + uint8_t af; +} hal_ll_i2c_pin_map_t; + +#ifdef I2C_MODULE_1 +#define I2C1_BASE_ADDRESS (0x40005400UL) +#define I2C1_BASE_ADDR I2C1_BASE_ADDRESS +#define HAL_LL_I2C1_BASE_ADDR I2C1_BASE_ADDRESS +#define HAL_LL_I2C1_BASE_ADDRESS I2C1_BASE_ADDRESS +#endif +#ifdef I2C_MODULE_2 +#define I2C2_BASE_ADDRESS (0x40005800UL) +#define I2C2_BASE_ADDR I2C2_BASE_ADDRESS +#define HAL_LL_I2C2_BASE_ADDR I2C2_BASE_ADDRESS +#define HAL_LL_I2C2_BASE_ADDRESS I2C2_BASE_ADDRESS +#endif +#ifdef I2C_MODULE_3 +#define I2C3_BASE_ADDRESS (0x40007800UL) +#define I2C3_BASE_ADDR I2C3_BASE_ADDRESS +#define HAL_LL_I2C3_BASE_ADDR I2C3_BASE_ADDRESS +#define HAL_LL_I2C3_BASE_ADDRESS I2C3_BASE_ADDRESS +#endif +#ifdef I2C_MODULE_4 +#define I2C4_BASE_ADDRESS (0x40008400UL) +#define I2C4_BASE_ADDR I2C4_BASE_ADDRESS +#define HAL_LL_I2C4_BASE_ADDR I2C4_BASE_ADDRESS +#define HAL_LL_I2C4_BASE_ADDRESS I2C4_BASE_ADDRESS +#endif + +/*!< @brief I2C SCL pins */ +static const hal_ll_i2c_pin_map_t hal_ll_i2c_scl_map[] = +{ + #ifdef I2C1_SCL_PA13_AF4 + {PA13, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 4}, + #endif + #ifdef I2C1_SCL_PA15_AF4 + {PA15, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 4}, + #endif + #ifdef I2C1_SCL_PB8_AF4 + {PB8, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 4}, + #endif + #ifdef I2C2_SCL_PA9_AF4 + {PA9, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 4}, + #endif + #ifdef I2C2_SCL_PC4_AF4 + {PC4, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 4}, + #endif + #ifdef I2C2_SCL_PF6_AF4 + {PF6, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 4}, + #endif + #ifdef I2C3_SCL_PA8_AF2 + {PA8, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 2}, + #endif + #ifdef I2C3_SCL_PC8_AF8 + {PC8, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 8}, + #endif + #ifdef I2C3_SCL_PF3_AF4 + {PF3, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 4}, + #endif + #ifdef I2C3_SCL_PG7_AF4 + {PG7, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 4}, + #endif + #ifdef I2C4_SCL_PA13_AF3 + {PA13, I2C4_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_4), 3}, + #endif + #ifdef I2C4_SCL_PC6_AF8 + {PC6, I2C4_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_4), 8}, + #endif + #ifdef I2C4_SCL_PF14_AF4 + {PF14, I2C4_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_4), 4}, + #endif + #ifdef I2C4_SCL_PG3_AF4 + {PG3, I2C4_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_4), 4}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} + //------------ END SCL +}; + +/*!< @brief I2C SDA pins */ +static const hal_ll_i2c_pin_map_t hal_ll_i2c_sda_map[] = +{ + #ifdef I2C1_SDA_PA14_AF4 + {PA14, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 4}, + #endif + #ifdef I2C1_SDA_PB7_AF4 + {PB7, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 4}, + #endif + #ifdef I2C1_SDA_PB9_AF4 + {PB9, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 4}, + #endif + #ifdef I2C2_SDA_PA8_AF4 + {PA8, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 4}, + #endif + #ifdef I2C2_SDA_PF0_AF4 + {PF0, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 4}, + #endif + #ifdef I2C3_SDA_PB5_AF8 + {PB5, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 8}, + #endif + #ifdef I2C3_SDA_PC11_AF8 + {PC11, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 8}, + #endif + #ifdef I2C3_SDA_PC9_AF8 + {PC9, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 8}, + #endif + #ifdef I2C3_SDA_PF4_AF4 + {PF4, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 4}, + #endif + #ifdef I2C3_SDA_PG8_AF4 + {PG8, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 4}, + #endif + #ifdef I2C4_SDA_PB7_AF3 + {PB7, I2C4_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_4), 3}, + #endif + #ifdef I2C4_SDA_PC7_AF8 + {PC7, I2C4_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_4), 8}, + #endif + #ifdef I2C4_SDA_PF15_AF4 + {PF15, I2C4_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_4), 4}, + #endif + #ifdef I2C4_SDA_PG4_AF4 + {PG4, I2C4_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_4), 4}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} + //------------ END SDA +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_I2C_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/i2c/hal_ll_i2c_pin_map/implementations/doc_ds_88/hal_ll_i2c_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/i2c/hal_ll_i2c_pin_map/implementations/doc_ds_88/hal_ll_i2c_pin_map.h new file mode 100644 index 000000000..5ea83a7b0 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/i2c/hal_ll_i2c_pin_map/implementations/doc_ds_88/hal_ll_i2c_pin_map.h @@ -0,0 +1,148 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_i2c_pin_map.h + * @brief I2C HAL LOW LEVEL PIN MAP. + */ + +#ifndef _HAL_LL_I2C_PIN_MAP_H_ +#define _HAL_LL_I2C_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_i2c_module_num(_module_num) (_module_num - 1) + +/*!< @brief Pin function structure */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + uint8_t af; +} hal_ll_i2c_pin_map_t; + +#ifdef I2C_MODULE_1 +#define I2C1_BASE_ADDRESS (0x40005400UL) +#define I2C1_BASE_ADDR I2C1_BASE_ADDRESS +#define HAL_LL_I2C1_BASE_ADDR I2C1_BASE_ADDRESS +#define HAL_LL_I2C1_BASE_ADDRESS I2C1_BASE_ADDRESS +#endif +#ifdef I2C_MODULE_2 +#define I2C2_BASE_ADDRESS (0x40005800UL) +#define I2C2_BASE_ADDR I2C2_BASE_ADDRESS +#define HAL_LL_I2C2_BASE_ADDR I2C2_BASE_ADDRESS +#define HAL_LL_I2C2_BASE_ADDRESS I2C2_BASE_ADDRESS +#endif +#ifdef I2C_MODULE_3 +#define I2C3_BASE_ADDRESS (0x40007800UL) +#define I2C3_BASE_ADDR I2C3_BASE_ADDRESS +#define HAL_LL_I2C3_BASE_ADDR I2C3_BASE_ADDRESS +#define HAL_LL_I2C3_BASE_ADDRESS I2C3_BASE_ADDRESS +#endif + +/*!< @brief I2C SCL pins */ +static const hal_ll_i2c_pin_map_t hal_ll_i2c_scl_map[] = +{ + #ifdef I2C1_SCL_PA13_AF4 + {PA13, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 4}, + #endif + #ifdef I2C1_SCL_PA15_AF4 + {PA15, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 4}, + #endif + #ifdef I2C1_SCL_PB8_AF4 + {PB8, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 4}, + #endif + #ifdef I2C2_SCL_PA9_AF4 + {PA9, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 4}, + #endif + #ifdef I2C3_SCL_PA8_AF2 + {PA8, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 2}, + #endif + #ifdef I2C2_SCL_PC4_AF4 + {PC4, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 4}, + #endif + #ifdef I2C3_SCL_PC8_AF8 + {PC8, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 8}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} + //------------ END SCL +}; + +/*!< @brief I2C SDA pins */ +static const hal_ll_i2c_pin_map_t hal_ll_i2c_sda_map[] = +{ + #ifdef I2C1_SDA_PA14_AF4 + {PA14, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 4}, + #endif + #ifdef I2C1_SDA_PB7_AF4 + {PB7, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 4}, + #endif + #ifdef I2C2_SDA_PA8_AF4 + {PA8, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 4}, + #endif + #ifdef I2C2_SDA_PF0_AF4 + {PF0, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 4}, + #endif + #ifdef I2C3_SDA_PB5_AF8 + {PB5, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 8}, + #endif + #ifdef I2C1_SDA_PB9_AF4 + {PB9, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 4}, + #endif + #ifdef I2C3_SDA_PC11_AF8 + {PC11, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 8}, + #endif + #ifdef I2C3_SDA_PC9_AF8 + {PC9, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 8}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} + //------------ END SDA +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_I2C_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/i2c/hal_ll_i2c_pin_map/implementations/doc_ds_89/hal_ll_i2c_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/i2c/hal_ll_i2c_pin_map/implementations/doc_ds_89/hal_ll_i2c_pin_map.h new file mode 100644 index 000000000..21fbad421 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/i2c/hal_ll_i2c_pin_map/implementations/doc_ds_89/hal_ll_i2c_pin_map.h @@ -0,0 +1,148 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_i2c_pin_map.h + * @brief I2C HAL LOW LEVEL PIN MAP. + */ + +#ifndef _HAL_LL_I2C_PIN_MAP_H_ +#define _HAL_LL_I2C_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_i2c_module_num(_module_num) (_module_num - 1) + +/*!< @brief Pin function structure */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + uint8_t af; +} hal_ll_i2c_pin_map_t; + +#ifdef I2C_MODULE_1 +#define I2C1_BASE_ADDRESS (0x40005400UL) +#define I2C1_BASE_ADDR I2C1_BASE_ADDRESS +#define HAL_LL_I2C1_BASE_ADDR I2C1_BASE_ADDRESS +#define HAL_LL_I2C1_BASE_ADDRESS I2C1_BASE_ADDRESS +#endif +#ifdef I2C_MODULE_2 +#define I2C2_BASE_ADDRESS (0x40005800UL) +#define I2C2_BASE_ADDR I2C2_BASE_ADDRESS +#define HAL_LL_I2C2_BASE_ADDR I2C2_BASE_ADDRESS +#define HAL_LL_I2C2_BASE_ADDRESS I2C2_BASE_ADDRESS +#endif +#ifdef I2C_MODULE_3 +#define I2C3_BASE_ADDRESS (0x40007800UL) +#define I2C3_BASE_ADDR I2C3_BASE_ADDRESS +#define HAL_LL_I2C3_BASE_ADDR I2C3_BASE_ADDRESS +#define HAL_LL_I2C3_BASE_ADDRESS I2C3_BASE_ADDRESS +#endif + +/*!< @brief I2C SCL pins */ +static const hal_ll_i2c_pin_map_t hal_ll_i2c_scl_map[] = +{ + #ifdef I2C1_SCL_PA13_AF4 + {PA13, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 4}, + #endif + #ifdef I2C1_SCL_PA15_AF4 + {PA15, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 4}, + #endif + #ifdef I2C1_SCL_PB8_AF4 + {PB8, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 4}, + #endif + #ifdef I2C2_SCL_PA9_AF4 + {PA9, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 4}, + #endif + #ifdef I2C2_SCL_PC4_AF4 + {PC4, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 4}, + #endif + #ifdef I2C3_SCL_PA8_AF2 + {PA8, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 2}, + #endif + #ifdef I2C3_SCL_PC8_AF8 + {PC8, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 8}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} + //------------ END SCL +}; + +/*!< @brief I2C SDA pins */ +static const hal_ll_i2c_pin_map_t hal_ll_i2c_sda_map[] = +{ + #ifdef I2C1_SDA_PA14_AF4 + {PA14, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 4}, + #endif + #ifdef I2C1_SDA_PB7_AF4 + {PB7, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 4}, + #endif + #ifdef I2C1_SDA_PB9_AF4 + {PB9, I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 4}, + #endif + #ifdef I2C2_SDA_PA8_AF4 + {PA8, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 4}, + #endif + #ifdef I2C2_SDA_PF0_AF4 + {PF0, I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 4}, + #endif + #ifdef I2C3_SDA_PB5_AF8 + {PB5, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 8}, + #endif + #ifdef I2C3_SDA_PC11_AF8 + {PC11, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 8}, + #endif + #ifdef I2C3_SDA_PC9_AF8 + {PC9, I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_3), 8}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} + //------------ END SDA +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_I2C_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/one_wire/hal_ll_one_wire.h b/targets/arm/mikroe/ai_generated/stm32/include/one_wire/hal_ll_one_wire.h new file mode 100644 index 000000000..9d290c603 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/one_wire/hal_ll_one_wire.h @@ -0,0 +1,243 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_one_wire.h + * @brief API for One Wire HAL LOW LEVEL layer. + */ + +#ifndef _HAL_LL_ONE_WIRE_H_ +#define _HAL_LL_ONE_WIRE_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_gpio.h" + +/** + * @brief Structure for storing One Wire device address. + * @details Unique One Wire address used for device addressing. + */ +typedef struct { + uint8_t address[8]; /*!< One Wire address buffer. */ +} hal_ll_one_wire_rom_address_t; + +/** + * @brief One Wire HAL Low Level context structure. + * @details The context structure for storing driver internal state. The contents of the + * context structure are used by the module and must not be altered. Reading or + * writing data directly from a control structure by user should be avoided. + */ +#if defined(__hal_ll_gpio_subset_1__) +typedef struct { + hal_ll_pin_name_t data_pin; // One Wire data pin. + volatile uint32_t moder; // Register for altering GPIO pin direction. + volatile uint32_t moder_set; // Variable for configuring pin as General purpose output. + volatile uint32_t moder_clear; // Variable for configuring pin as General purpose input (reset state). + volatile uint32_t bsrr; // Register for GPIO port bit set/reset. + volatile uint32_t idr; // Register for reading current GPIO pin state. +} hal_ll_one_wire_local_t; +#elif defined(__hal_ll_gpio_subset_2__) +typedef struct { + hal_ll_pin_name_t data_pin; // One Wire data pin. + volatile uint32_t crl; // Register for altering GPIO pin direction (lower eight pins). + volatile uint32_t crh; // Register for altering GPIO pin direction (higher eight pins). + volatile uint32_t crx_set; // Variable for configuring pin as General purpose output. + volatile uint32_t crx_clear; // Variable for configuring pin as General purpose input (reset state). + volatile uint32_t bsrr; // Register for GPIO port bit set/reset. + volatile uint32_t idr; // Register for reading current GPIO pin state. +} hal_ll_one_wire_local_t; +#endif +/** + * @brief One Wire HAL Low Level initialization configuration structure. + * + * @details + * - data_pin value - to be configured as desired. + * - state value - NOTE must not be altered (it is supposed to be set automatically in Low Level Layer). + */ +typedef struct { + hal_ll_pin_name_t data_pin; /*!< One Wire pin - user is to configure it as desired. */ + bool state; /*!< State of a pin. NOTE must not be altered. */ +} hal_ll_one_wire_t; + +/** + * @details Enum containing predefined module return values. + */ +typedef enum { + HAL_LL_ONE_WIRE_SUCCESS = 0, /*!< Success. */ + HAL_LL_ONE_WIRE_ERROR = (-1) /*!< Error. */ +} hal_ll_one_wire_err_t; + +/** + * @brief Opens One Wire HAL Low Level object. + * @details Opens One Wire HAL Low Level object on selected pin. + * Enables appropriate PORT clock, configures pin to have digital output functionality, + * makes sure that HIGH voltage state is applied on pin before any One Wire actions. + * @param[in,out] *obj One Wire HAL Low Level object. + * See #hal_ll_one_wire_t structure definition for detailed explanation. + * @return None. + * @pre Make sure that \p LowLevel structure has been adequately + * populated beforehand. + * @note It is recommended to check return value for error. + */ +void hal_ll_one_wire_open( hal_ll_one_wire_t *obj ); + +/** + * @brief Reset One Wire bus. + * @details Host shall send reset sequence and devices shall go into reset state. + * @param[in,out] *handle One Wire HAL Low Level object. + * See #hal_one_wire_t structure definition for detailed explanation. + * @return The function can return one of the values defined by + * #hal_ll_one_wire_err_t, which is size dependant on the architecture. + * @pre Before calling this function, + * the user is expected to call #hal_ll_one_wire_open function. + */ +hal_ll_err_t hal_ll_one_wire_reset( hal_ll_one_wire_t *obj ); + +/** + * @brief Reads device's ROM information. + * @details Allows the host to read eight-bit family code, + * 48-bit serial number, and eight-bit CRC. + * + * @important THIS FUNCTION IS TO BE ISSUED ONLY IF WE ARE DEALING WITH + * ONE DEVICE ONLY. THIS FUNCTION AUTOMATICALLY RESETS ONE WIRE BUS. + * @param[in] *obj One Wire HAL Low Level object. + * See #hal_one_wire_t structure definition for detailed explanation. + * @param[out] *device_rom_address Buffer for One Wire device ROM information. + * @return The function can return one of the values defined by + * #hal_ll_one_wire_err_t, which is size dependant on the architecture. + */ +hal_ll_err_t hal_ll_one_wire_read_rom( hal_ll_one_wire_t *obj, hal_ll_one_wire_rom_address_t *device_rom_address ); + +/** + * @brief Access device's level functions without transmitting ROM information. + * @details Allows the host to access device functions without + * providing the 64-bit ROM identification number. + * + * @important THIS FUNCTION IS TO BE ISSUED ONLY IF WE ARE DEALING WITH + * ONE DEVICE ONLY. THIS FUNCTION AUTOMATICALLY RESETS ONE WIRE BUS. + * @param[in] *obj One Wire HAL Low Level object. + * See #hal_one_wire_t structure definition for detailed explanation. + * @return The function can return one of the values defined by + * #hal_ll_one_wire_err_t, which is size dependant on the architecture. + */ +hal_ll_err_t hal_ll_one_wire_skip_rom( hal_ll_one_wire_t *obj ); + +/** + * @brief Selects a specific One Wire capable device on bus. + * @details Select a One Wire device with specific ID. + * + * @param[in] *obj One Wire HAL Low Level object. + * See #hal_ll_one_wire_t structure definition for detailed explanation. + * @param[in] device_rom_address Buffer for One Wire device ROM information. + * @return The function can return one of the values defined by + * #hal_ll_one_wire_err_t, which is size dependant on the architecture. + * @pre Before calling this function, + * the user is expected to call #hal_one_wire_open function. + */ +hal_ll_err_t hal_ll_one_wire_match_rom( hal_ll_one_wire_t *obj, hal_ll_one_wire_rom_address_t *device_rom_address ); + +/** + * @brief Search One Wire capable device on bus. + * @details Search and list 1st device that is One Wire capable. + * + * @param[in] *obj One Wire HAL Low Level object. + * See #hal_ll_one_wire_t structure definition for detailed explanation. + * @param[out] *one_wire_device_list Buffer for One Wire device ROM information. + * @return The function can return one of the values defined by + * #hal_ll_one_wire_err_t, which is size dependant on the architecture. + * @pre Before calling this function, + * the user is expected to call #hal_ll_one_wire_open function. + */ +hal_ll_err_t hal_ll_one_wire_search_first_device( hal_ll_one_wire_t *obj, hal_ll_one_wire_rom_address_t *one_wire_device_list ); + +/** + * @brief Search One Wire capable devices on bus. + * @details Search devices that is One Wire capable. + * + * @param[in] *obj One Wire HAL Low Level object. + * See #hal_ll_one_wire_t structure definition for detailed explanation. + * @param[out] *one_wire_device_list Buffer for One Wire device ROM information. + * @return The function can return one of the values defined by + * #hal_ll_one_wire_err_t, which is size dependant on the architecture. + * @pre Before calling this function, + * the user is expected to call #hal_ll_one_wire_open function. + */ +hal_ll_err_t hal_ll_one_wire_search_next_device( hal_ll_one_wire_t *obj, hal_ll_one_wire_rom_address_t *one_wire_device_list ); + +/** + * @brief Writes byte to One Wire bus. + * @details Writes byte to One Wire bus. + * @param[in] *write_data_buffer Data transmit buffer. + * @param[in] write_data_length Number of bytes to write from data transmit buffer. + * @return None. + * @pre Before calling this function, + * the user is expected to call #hal_ll_one_wire_open function. + */ +void hal_ll_one_wire_write_byte( uint8_t *write_data_buffer, size_t write_data_length ); + +/** + * @brief Reads byte from One Wire bus. + * @details Reads byte from One Wire bus. + * @param[out] *read_data_buffer Data receive buffer. + * @param[in] read_data_length Number of bytes to be read. + * @return None. + * @pre Before calling this function, + * the user is expected to call #hal_ll_one_wire_open function. + */ +void hal_ll_one_wire_read_byte( uint8_t *read_data_buffer, size_t read_data_length ); + +/** + * @brief Reconfigures One Wire pin settings. + * @details Enables appropriate PORT clock, configures pin to have digital output functionality, + * makes sure that HIGH voltage state is applied on pin before any One Wire actions. + * @param[in] *obj One Wire HAL Low Level object. + * See #hal_ll_one_wire_t structure definition for detailed explanation. + * @return None. + * @pre Before calling this function, + * the user is expected to call #hal_one_wire_open function. + */ +void hal_ll_one_wire_reconfigure( hal_ll_one_wire_t *obj ); + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_ONE_WIRE_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/one_wire/implementations/.gitkeep b/targets/arm/mikroe/ai_generated/stm32/include/one_wire/implementations/.gitkeep new file mode 100644 index 000000000..e69de29bb diff --git a/targets/arm/mikroe/ai_generated/stm32/include/rcc/implementations/doc_ds_1/hal_ll_rcc.h b/targets/arm/mikroe/ai_generated/stm32/include/rcc/implementations/doc_ds_1/hal_ll_rcc.h new file mode 100644 index 000000000..cc47f254d --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/rcc/implementations/doc_ds_1/hal_ll_rcc.h @@ -0,0 +1,104 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_rcc.h + * @brief Reset and Clock control defines necessary for HAL. + */ + +#ifndef _HAL_LL_RCC_H_ +#define _HAL_LL_RCC_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include + +/** + * Core register addresses used in source + */ +#define _RCC_BASE (0x40021000UL) +#define _RCC_CR ((uint32_t *)(_RCC_BASE + 0x0)) +#define _RCC_ICSCR ((uint32_t *)(_RCC_BASE + 0x4)) +#define _RCC_CFGR ((uint32_t *)(_RCC_BASE + 0x8)) +#define _RCC_CIER ((uint32_t *)(_RCC_BASE + 0x18)) +#define _RCC_CIFR ((uint32_t *)(_RCC_BASE + 0x1C)) +#define _RCC_CICR ((uint32_t *)(_RCC_BASE + 0x20)) +#define _RCC_IOPRSTR ((uint32_t *)(_RCC_BASE + 0x24)) +#define _RCC_AHBRSTR ((uint32_t *)(_RCC_BASE + 0x28)) +#define _RCC_APBRSTR1 ((uint32_t *)(_RCC_BASE + 0x2C)) +#define _RCC_APBRSTR2 ((uint32_t *)(_RCC_BASE + 0x30)) +#define _RCC_IOPENR ((uint32_t *)(_RCC_BASE + 0x34)) +#define _RCC_AHBENR ((uint32_t *)(_RCC_BASE + 0x38)) +#define _RCC_APBENR1 ((uint32_t *)(_RCC_BASE + 0x3C)) +#define _RCC_APBENR2 ((uint32_t *)(_RCC_BASE + 0x40)) +#define _RCC_IOPSMENR ((uint32_t *)(_RCC_BASE + 0x44)) +#define _RCC_AHBSMENR ((uint32_t *)(_RCC_BASE + 0x48)) +#define _RCC_APBSMENR1 ((uint32_t *)(_RCC_BASE + 0x4C)) +#define _RCC_APBSMENR2 ((uint32_t *)(_RCC_BASE + 0x50)) +#define _RCC_CCIPR ((uint32_t *)(_RCC_BASE + 0x54)) +#define _RCC_CSR1 ((uint32_t *)(_RCC_BASE + 0x5C)) +#define _RCC_CSR2 ((uint32_t *)(_RCC_BASE + 0x60)) + +/** + * RCC Structs used in source + */ +typedef struct rcc_clocks +{ + uint32_t sysclk; // SYSCLK clock frequency in Hz + uint32_t hclk; // HCLK clock frequency in Hz + uint32_t pclk; // PCLK clock frequency in Hz + uint32_t tpclk; // TPCLK clock frequency in Hz +} rcc_clocks_t; + +/** + * @brief Gets clock values. + * + * @param rcc_clocks_t[OUT] RCC clocks structure. + * + * @return *rcc_clocks_t Structure containing clock values. + */ +void RCC_GetClocksFrequency(rcc_clocks_t *RCC_Clocks); + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_RCC_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/rcc/implementations/doc_ds_160/hal_ll_rcc.h b/targets/arm/mikroe/ai_generated/stm32/include/rcc/implementations/doc_ds_160/hal_ll_rcc.h new file mode 100644 index 000000000..c2f431b45 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/rcc/implementations/doc_ds_160/hal_ll_rcc.h @@ -0,0 +1,118 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_rcc.h + * @brief Reset and Clock control defines necessary for HAL. + */ + +#ifndef _HAL_LL_RCC_H_ +#define _HAL_LL_RCC_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include + +/** + * Core register addresses used in source + */ +#define _RCC_BASE (0x40021000UL) +#define _RCC_CR ((uint32_t *)(_RCC_BASE + 0x0)) +#define _RCC_ICSCR ((uint32_t *)(_RCC_BASE + 0x4)) +#define _RCC_CFGR ((uint32_t *)(_RCC_BASE + 0x8)) +#define _RCC_PLLCFGR ((uint32_t *)(_RCC_BASE + 0xC)) +#define _RCC_PLLSAI1CFGR ((uint32_t *)(_RCC_BASE + 0x10)) +#define _RCC_PLLSAI2CFGR ((uint32_t *)(_RCC_BASE + 0x14)) +#define _RCC_CIER ((uint32_t *)(_RCC_BASE + 0x18)) +#define _RCC_CIFR ((uint32_t *)(_RCC_BASE + 0x1C)) +#define _RCC_CICR ((uint32_t *)(_RCC_BASE + 0x20)) +#define _RCC_AHB1RSTR ((uint32_t *)(_RCC_BASE + 0x28)) +#define _RCC_AHB2RSTR ((uint32_t *)(_RCC_BASE + 0x2C)) +#define _RCC_AHB3RSTR ((uint32_t *)(_RCC_BASE + 0x30)) +#define _RCC_APB1RSTR1 ((uint32_t *)(_RCC_BASE + 0x38)) +#define _RCC_APB1RSTR2 ((uint32_t *)(_RCC_BASE + 0x3C)) +#define _RCC_APB2RSTR ((uint32_t *)(_RCC_BASE + 0x40)) +#define _RCC_AHB1ENR ((uint32_t *)(_RCC_BASE + 0x48)) +#define _RCC_AHB2ENR ((uint32_t *)(_RCC_BASE + 0x4C)) +#define _RCC_AHB3ENR ((uint32_t *)(_RCC_BASE + 0x50)) +#define _RCC_APB1ENR1 ((uint32_t *)(_RCC_BASE + 0x58)) +#define _RCC_APB1ENR2 ((uint32_t *)(_RCC_BASE + 0x5C)) +#define _RCC_APB2ENR ((uint32_t *)(_RCC_BASE + 0x60)) +#define _RCC_AHB1SMENR ((uint32_t *)(_RCC_BASE + 0x68)) +#define _RCC_AHB2SMENR ((uint32_t *)(_RCC_BASE + 0x6C)) +#define _RCC_AHB3SMENR ((uint32_t *)(_RCC_BASE + 0x70)) +#define _RCC_APB1SMENR1 ((uint32_t *)(_RCC_BASE + 0x78)) +#define _RCC_APB1SMENR2 ((uint32_t *)(_RCC_BASE + 0x7C)) +#define _RCC_APB2SMENR ((uint32_t *)(_RCC_BASE + 0x80)) +#define _RCC_CCIPR ((uint32_t *)(_RCC_BASE + 0x88)) +#define _RCC_BDCR ((uint32_t *)(_RCC_BASE + 0x90)) +#define _RCC_CSR ((uint32_t *)(_RCC_BASE + 0x94)) +#define _RCC_CRRCR ((uint32_t *)(_RCC_BASE + 0x98)) +#define _RCC_CCIPR2 ((uint32_t *)(_RCC_BASE + 0x9C)) +#define _RCC_DLYCFGR ((uint32_t *)(_RCC_BASE + 0xA4)) + +/** + * RCC Structs used in source + */ +typedef struct rcc_clocks +{ + uint32_t sysclk; // SYSCLK clock frequency in Hz + uint32_t hclk; // HCLK clock frequency in Hz + uint32_t pclk1; // PCLK1 clock frequency in Hz + uint32_t pclk2; // PCLK2 clock frequency in Hz + uint32_t tpclk1; // TPCLK1 clock frequency in Hz + uint32_t tpclk2; // TPCLK2 clock frequency in Hz +} rcc_clocks_t; + +/** + * @brief Gets clock values. + * + * @param rcc_clocks_t[OUT] RCC clocks structure. + * + * @return *rcc_clocks_t Structure containing clock values. + */ +void RCC_GetClocksFrequency(rcc_clocks_t *RCC_Clocks); + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_RCC_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/rcc/implementations/doc_ds_161/hal_ll_rcc.h b/targets/arm/mikroe/ai_generated/stm32/include/rcc/implementations/doc_ds_161/hal_ll_rcc.h new file mode 100644 index 000000000..c2f431b45 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/rcc/implementations/doc_ds_161/hal_ll_rcc.h @@ -0,0 +1,118 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_rcc.h + * @brief Reset and Clock control defines necessary for HAL. + */ + +#ifndef _HAL_LL_RCC_H_ +#define _HAL_LL_RCC_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include + +/** + * Core register addresses used in source + */ +#define _RCC_BASE (0x40021000UL) +#define _RCC_CR ((uint32_t *)(_RCC_BASE + 0x0)) +#define _RCC_ICSCR ((uint32_t *)(_RCC_BASE + 0x4)) +#define _RCC_CFGR ((uint32_t *)(_RCC_BASE + 0x8)) +#define _RCC_PLLCFGR ((uint32_t *)(_RCC_BASE + 0xC)) +#define _RCC_PLLSAI1CFGR ((uint32_t *)(_RCC_BASE + 0x10)) +#define _RCC_PLLSAI2CFGR ((uint32_t *)(_RCC_BASE + 0x14)) +#define _RCC_CIER ((uint32_t *)(_RCC_BASE + 0x18)) +#define _RCC_CIFR ((uint32_t *)(_RCC_BASE + 0x1C)) +#define _RCC_CICR ((uint32_t *)(_RCC_BASE + 0x20)) +#define _RCC_AHB1RSTR ((uint32_t *)(_RCC_BASE + 0x28)) +#define _RCC_AHB2RSTR ((uint32_t *)(_RCC_BASE + 0x2C)) +#define _RCC_AHB3RSTR ((uint32_t *)(_RCC_BASE + 0x30)) +#define _RCC_APB1RSTR1 ((uint32_t *)(_RCC_BASE + 0x38)) +#define _RCC_APB1RSTR2 ((uint32_t *)(_RCC_BASE + 0x3C)) +#define _RCC_APB2RSTR ((uint32_t *)(_RCC_BASE + 0x40)) +#define _RCC_AHB1ENR ((uint32_t *)(_RCC_BASE + 0x48)) +#define _RCC_AHB2ENR ((uint32_t *)(_RCC_BASE + 0x4C)) +#define _RCC_AHB3ENR ((uint32_t *)(_RCC_BASE + 0x50)) +#define _RCC_APB1ENR1 ((uint32_t *)(_RCC_BASE + 0x58)) +#define _RCC_APB1ENR2 ((uint32_t *)(_RCC_BASE + 0x5C)) +#define _RCC_APB2ENR ((uint32_t *)(_RCC_BASE + 0x60)) +#define _RCC_AHB1SMENR ((uint32_t *)(_RCC_BASE + 0x68)) +#define _RCC_AHB2SMENR ((uint32_t *)(_RCC_BASE + 0x6C)) +#define _RCC_AHB3SMENR ((uint32_t *)(_RCC_BASE + 0x70)) +#define _RCC_APB1SMENR1 ((uint32_t *)(_RCC_BASE + 0x78)) +#define _RCC_APB1SMENR2 ((uint32_t *)(_RCC_BASE + 0x7C)) +#define _RCC_APB2SMENR ((uint32_t *)(_RCC_BASE + 0x80)) +#define _RCC_CCIPR ((uint32_t *)(_RCC_BASE + 0x88)) +#define _RCC_BDCR ((uint32_t *)(_RCC_BASE + 0x90)) +#define _RCC_CSR ((uint32_t *)(_RCC_BASE + 0x94)) +#define _RCC_CRRCR ((uint32_t *)(_RCC_BASE + 0x98)) +#define _RCC_CCIPR2 ((uint32_t *)(_RCC_BASE + 0x9C)) +#define _RCC_DLYCFGR ((uint32_t *)(_RCC_BASE + 0xA4)) + +/** + * RCC Structs used in source + */ +typedef struct rcc_clocks +{ + uint32_t sysclk; // SYSCLK clock frequency in Hz + uint32_t hclk; // HCLK clock frequency in Hz + uint32_t pclk1; // PCLK1 clock frequency in Hz + uint32_t pclk2; // PCLK2 clock frequency in Hz + uint32_t tpclk1; // TPCLK1 clock frequency in Hz + uint32_t tpclk2; // TPCLK2 clock frequency in Hz +} rcc_clocks_t; + +/** + * @brief Gets clock values. + * + * @param rcc_clocks_t[OUT] RCC clocks structure. + * + * @return *rcc_clocks_t Structure containing clock values. + */ +void RCC_GetClocksFrequency(rcc_clocks_t *RCC_Clocks); + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_RCC_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/rcc/implementations/doc_ds_2/hal_ll_rcc.h b/targets/arm/mikroe/ai_generated/stm32/include/rcc/implementations/doc_ds_2/hal_ll_rcc.h new file mode 100644 index 000000000..cc47f254d --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/rcc/implementations/doc_ds_2/hal_ll_rcc.h @@ -0,0 +1,104 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_rcc.h + * @brief Reset and Clock control defines necessary for HAL. + */ + +#ifndef _HAL_LL_RCC_H_ +#define _HAL_LL_RCC_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include + +/** + * Core register addresses used in source + */ +#define _RCC_BASE (0x40021000UL) +#define _RCC_CR ((uint32_t *)(_RCC_BASE + 0x0)) +#define _RCC_ICSCR ((uint32_t *)(_RCC_BASE + 0x4)) +#define _RCC_CFGR ((uint32_t *)(_RCC_BASE + 0x8)) +#define _RCC_CIER ((uint32_t *)(_RCC_BASE + 0x18)) +#define _RCC_CIFR ((uint32_t *)(_RCC_BASE + 0x1C)) +#define _RCC_CICR ((uint32_t *)(_RCC_BASE + 0x20)) +#define _RCC_IOPRSTR ((uint32_t *)(_RCC_BASE + 0x24)) +#define _RCC_AHBRSTR ((uint32_t *)(_RCC_BASE + 0x28)) +#define _RCC_APBRSTR1 ((uint32_t *)(_RCC_BASE + 0x2C)) +#define _RCC_APBRSTR2 ((uint32_t *)(_RCC_BASE + 0x30)) +#define _RCC_IOPENR ((uint32_t *)(_RCC_BASE + 0x34)) +#define _RCC_AHBENR ((uint32_t *)(_RCC_BASE + 0x38)) +#define _RCC_APBENR1 ((uint32_t *)(_RCC_BASE + 0x3C)) +#define _RCC_APBENR2 ((uint32_t *)(_RCC_BASE + 0x40)) +#define _RCC_IOPSMENR ((uint32_t *)(_RCC_BASE + 0x44)) +#define _RCC_AHBSMENR ((uint32_t *)(_RCC_BASE + 0x48)) +#define _RCC_APBSMENR1 ((uint32_t *)(_RCC_BASE + 0x4C)) +#define _RCC_APBSMENR2 ((uint32_t *)(_RCC_BASE + 0x50)) +#define _RCC_CCIPR ((uint32_t *)(_RCC_BASE + 0x54)) +#define _RCC_CSR1 ((uint32_t *)(_RCC_BASE + 0x5C)) +#define _RCC_CSR2 ((uint32_t *)(_RCC_BASE + 0x60)) + +/** + * RCC Structs used in source + */ +typedef struct rcc_clocks +{ + uint32_t sysclk; // SYSCLK clock frequency in Hz + uint32_t hclk; // HCLK clock frequency in Hz + uint32_t pclk; // PCLK clock frequency in Hz + uint32_t tpclk; // TPCLK clock frequency in Hz +} rcc_clocks_t; + +/** + * @brief Gets clock values. + * + * @param rcc_clocks_t[OUT] RCC clocks structure. + * + * @return *rcc_clocks_t Structure containing clock values. + */ +void RCC_GetClocksFrequency(rcc_clocks_t *RCC_Clocks); + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_RCC_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/rcc/implementations/doc_ds_74/hal_ll_rcc.h b/targets/arm/mikroe/ai_generated/stm32/include/rcc/implementations/doc_ds_74/hal_ll_rcc.h new file mode 100644 index 000000000..576826899 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/rcc/implementations/doc_ds_74/hal_ll_rcc.h @@ -0,0 +1,105 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_rcc.h + * @brief Reset and Clock control defines necessary for HAL. + */ + +#ifndef _HAL_LL_RCC_H_ +#define _HAL_LL_RCC_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include + +/** + * Core register addresses used in source + */ +#define _RCC_BASE (0x40021000UL) +#define _RCC_CR ((uint32_t *)(_RCC_BASE + 0x0)) +#define _RCC_ICSCR ((uint32_t *)(_RCC_BASE + 0x4)) +#define _RCC_CFGR ((uint32_t *)(_RCC_BASE + 0x8)) +#define _RCC_PLLCFGR ((uint32_t *)(_RCC_BASE + 0xC)) +#define _RCC_CIER ((uint32_t *)(_RCC_BASE + 0x18)) +#define _RCC_CIFR ((uint32_t *)(_RCC_BASE + 0x1C)) +#define _RCC_CICR ((uint32_t *)(_RCC_BASE + 0x20)) +#define _RCC_IOPRSTR ((uint32_t *)(_RCC_BASE + 0x24)) +#define _RCC_AHBRSTR ((uint32_t *)(_RCC_BASE + 0x28)) +#define _RCC_APBRSTR1 ((uint32_t *)(_RCC_BASE + 0x2C)) +#define _RCC_APBRSTR2 ((uint32_t *)(_RCC_BASE + 0x30)) +#define _RCC_IOPENR ((uint32_t *)(_RCC_BASE + 0x34)) +#define _RCC_AHBENR ((uint32_t *)(_RCC_BASE + 0x38)) +#define _RCC_APBENR1 ((uint32_t *)(_RCC_BASE + 0x3C)) +#define _RCC_APBENR2 ((uint32_t *)(_RCC_BASE + 0x40)) +#define _RCC_IOPSMENR ((uint32_t *)(_RCC_BASE + 0x44)) +#define _RCC_AHBSMENR ((uint32_t *)(_RCC_BASE + 0x48)) +#define _RCC_APBSMENR1 ((uint32_t *)(_RCC_BASE + 0x4C)) +#define _RCC_APBSMENR2 ((uint32_t *)(_RCC_BASE + 0x50)) +#define _RCC_CCIPR ((uint32_t *)(_RCC_BASE + 0x54)) +#define _RCC_BDCR ((uint32_t *)(_RCC_BASE + 0x5C)) +#define _RCC_CSR ((uint32_t *)(_RCC_BASE + 0x60)) + +/** + * RCC Structs used in source + */ +typedef struct rcc_clocks +{ + uint32_t sysclk; // SYSCLK clock frequency in Hz + uint32_t hclk; // HCLK clock frequency in Hz + uint32_t pclk; // PCLK clock frequency in Hz + uint32_t tpclk; // TPCLK clock frequency in Hz +} rcc_clocks_t; + +/** + * @brief Gets clock values. + * + * @param rcc_clocks_t[OUT] RCC clocks structure. + * + * @return *rcc_clocks_t Structure containing clock values. + */ +void RCC_GetClocksFrequency(rcc_clocks_t *RCC_Clocks); + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_RCC_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/rcc/implementations/doc_ds_75/hal_ll_rcc.h b/targets/arm/mikroe/ai_generated/stm32/include/rcc/implementations/doc_ds_75/hal_ll_rcc.h new file mode 100644 index 000000000..576826899 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/rcc/implementations/doc_ds_75/hal_ll_rcc.h @@ -0,0 +1,105 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_rcc.h + * @brief Reset and Clock control defines necessary for HAL. + */ + +#ifndef _HAL_LL_RCC_H_ +#define _HAL_LL_RCC_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include + +/** + * Core register addresses used in source + */ +#define _RCC_BASE (0x40021000UL) +#define _RCC_CR ((uint32_t *)(_RCC_BASE + 0x0)) +#define _RCC_ICSCR ((uint32_t *)(_RCC_BASE + 0x4)) +#define _RCC_CFGR ((uint32_t *)(_RCC_BASE + 0x8)) +#define _RCC_PLLCFGR ((uint32_t *)(_RCC_BASE + 0xC)) +#define _RCC_CIER ((uint32_t *)(_RCC_BASE + 0x18)) +#define _RCC_CIFR ((uint32_t *)(_RCC_BASE + 0x1C)) +#define _RCC_CICR ((uint32_t *)(_RCC_BASE + 0x20)) +#define _RCC_IOPRSTR ((uint32_t *)(_RCC_BASE + 0x24)) +#define _RCC_AHBRSTR ((uint32_t *)(_RCC_BASE + 0x28)) +#define _RCC_APBRSTR1 ((uint32_t *)(_RCC_BASE + 0x2C)) +#define _RCC_APBRSTR2 ((uint32_t *)(_RCC_BASE + 0x30)) +#define _RCC_IOPENR ((uint32_t *)(_RCC_BASE + 0x34)) +#define _RCC_AHBENR ((uint32_t *)(_RCC_BASE + 0x38)) +#define _RCC_APBENR1 ((uint32_t *)(_RCC_BASE + 0x3C)) +#define _RCC_APBENR2 ((uint32_t *)(_RCC_BASE + 0x40)) +#define _RCC_IOPSMENR ((uint32_t *)(_RCC_BASE + 0x44)) +#define _RCC_AHBSMENR ((uint32_t *)(_RCC_BASE + 0x48)) +#define _RCC_APBSMENR1 ((uint32_t *)(_RCC_BASE + 0x4C)) +#define _RCC_APBSMENR2 ((uint32_t *)(_RCC_BASE + 0x50)) +#define _RCC_CCIPR ((uint32_t *)(_RCC_BASE + 0x54)) +#define _RCC_BDCR ((uint32_t *)(_RCC_BASE + 0x5C)) +#define _RCC_CSR ((uint32_t *)(_RCC_BASE + 0x60)) + +/** + * RCC Structs used in source + */ +typedef struct rcc_clocks +{ + uint32_t sysclk; // SYSCLK clock frequency in Hz + uint32_t hclk; // HCLK clock frequency in Hz + uint32_t pclk; // PCLK clock frequency in Hz + uint32_t tpclk; // TPCLK clock frequency in Hz +} rcc_clocks_t; + +/** + * @brief Gets clock values. + * + * @param rcc_clocks_t[OUT] RCC clocks structure. + * + * @return *rcc_clocks_t Structure containing clock values. + */ +void RCC_GetClocksFrequency(rcc_clocks_t *RCC_Clocks); + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_RCC_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/rcc/implementations/doc_ds_80/hal_ll_rcc.h b/targets/arm/mikroe/ai_generated/stm32/include/rcc/implementations/doc_ds_80/hal_ll_rcc.h new file mode 100644 index 000000000..c5a1b045d --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/rcc/implementations/doc_ds_80/hal_ll_rcc.h @@ -0,0 +1,108 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_rcc.h + * @brief Reset and Clock control defines necessary for HAL. + */ + +#ifndef _HAL_LL_RCC_H_ +#define _HAL_LL_RCC_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include + +/** + * Core register addresses used in source + */ +#define _RCC_BASE (0x40021000UL) +#define _RCC_CR ((uint32_t *)(_RCC_BASE + 0x0)) +#define _RCC_ICSCR ((uint32_t *)(_RCC_BASE + 0x4)) +#define _RCC_CFGR ((uint32_t *)(_RCC_BASE + 0x8)) +#define _RCC_PLLCFGR ((uint32_t *)(_RCC_BASE + 0xC)) +#define _RCC_CRRCR ((uint32_t *)(_RCC_BASE + 0x14)) +#define _RCC_CIER ((uint32_t *)(_RCC_BASE + 0x18)) +#define _RCC_CIFR ((uint32_t *)(_RCC_BASE + 0x1C)) +#define _RCC_CICR ((uint32_t *)(_RCC_BASE + 0x20)) +#define _RCC_IOPRSTR ((uint32_t *)(_RCC_BASE + 0x24)) +#define _RCC_AHBRSTR ((uint32_t *)(_RCC_BASE + 0x28)) +#define _RCC_APBRSTR1 ((uint32_t *)(_RCC_BASE + 0x2C)) +#define _RCC_APBRSTR2 ((uint32_t *)(_RCC_BASE + 0x30)) +#define _RCC_IOPENR ((uint32_t *)(_RCC_BASE + 0x34)) +#define _RCC_AHBENR ((uint32_t *)(_RCC_BASE + 0x38)) +#define _RCC_APBENR1 ((uint32_t *)(_RCC_BASE + 0x3C)) +#define _RCC_APBENR2 ((uint32_t *)(_RCC_BASE + 0x40)) +#define _RCC_IOPSMENR ((uint32_t *)(_RCC_BASE + 0x44)) +#define _RCC_AHBSMENR ((uint32_t *)(_RCC_BASE + 0x48)) +#define _RCC_APBSMENR1 ((uint32_t *)(_RCC_BASE + 0x4C)) +#define _RCC_APBSMENR2 ((uint32_t *)(_RCC_BASE + 0x50)) +#define _RCC_CCIPR ((uint32_t *)(_RCC_BASE + 0x54)) +#define _RCC_CCIPR2 ((uint32_t *)(_RCC_BASE + 0x58)) +#define _RCC_BDCR ((uint32_t *)(_RCC_BASE + 0x5C)) +#define _RCC_CSR ((uint32_t *)(_RCC_BASE + 0x60)) + +/** + * RCC Structs used in source + */ +typedef struct rcc_clocks +{ + uint32_t sysclk; // SYSCLK clock frequency in Hz + uint32_t hclk; // HCLK clock frequency in Hz + uint32_t hclk8; // HCLK8 clock frequency in Hz + uint32_t pclk; // PCLK clock frequency in Hz + uint32_t tpclk; // TPCLK clock frequency in Hz +} rcc_clocks_t; + +/** + * @brief Gets clock values. + * + * @param rcc_clocks_t[OUT] RCC clocks structure. + * + * @return *rcc_clocks_t Structure containing clock values. + */ +void RCC_GetClocksFrequency(rcc_clocks_t *RCC_Clocks); + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_RCC_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/rcc/implementations/doc_ds_81/hal_ll_rcc.h b/targets/arm/mikroe/ai_generated/stm32/include/rcc/implementations/doc_ds_81/hal_ll_rcc.h new file mode 100644 index 000000000..a73f11b09 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/rcc/implementations/doc_ds_81/hal_ll_rcc.h @@ -0,0 +1,107 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_rcc.h + * @brief Reset and Clock control defines necessary for HAL. + */ + +#ifndef _HAL_LL_RCC_H_ +#define _HAL_LL_RCC_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include + +/** + * Core register addresses used in source + */ +#define _RCC_BASE (0x40021000UL) +#define _RCC_CR ((uint32_t *)(_RCC_BASE + 0x0)) +#define _RCC_ICSCR ((uint32_t *)(_RCC_BASE + 0x4)) +#define _RCC_CFGR ((uint32_t *)(_RCC_BASE + 0x8)) +#define _RCC_PLLCFGR ((uint32_t *)(_RCC_BASE + 0xC)) +#define _RCC_CRRCR ((uint32_t *)(_RCC_BASE + 0x14)) +#define _RCC_CIER ((uint32_t *)(_RCC_BASE + 0x18)) +#define _RCC_CIFR ((uint32_t *)(_RCC_BASE + 0x1C)) +#define _RCC_CICR ((uint32_t *)(_RCC_BASE + 0x20)) +#define _RCC_IOPRSTR ((uint32_t *)(_RCC_BASE + 0x24)) +#define _RCC_AHBRSTR ((uint32_t *)(_RCC_BASE + 0x28)) +#define _RCC_APBRSTR1 ((uint32_t *)(_RCC_BASE + 0x2C)) +#define _RCC_APBRSTR2 ((uint32_t *)(_RCC_BASE + 0x30)) +#define _RCC_IOPENR ((uint32_t *)(_RCC_BASE + 0x34)) +#define _RCC_AHBENR ((uint32_t *)(_RCC_BASE + 0x38)) +#define _RCC_APBENR1 ((uint32_t *)(_RCC_BASE + 0x3C)) +#define _RCC_APBENR2 ((uint32_t *)(_RCC_BASE + 0x40)) +#define _RCC_IOPSMENR ((uint32_t *)(_RCC_BASE + 0x44)) +#define _RCC_AHBSMENR ((uint32_t *)(_RCC_BASE + 0x48)) +#define _RCC_APBSMENR1 ((uint32_t *)(_RCC_BASE + 0x4C)) +#define _RCC_APBSMENR2 ((uint32_t *)(_RCC_BASE + 0x50)) +#define _RCC_CCIPR ((uint32_t *)(_RCC_BASE + 0x54)) +#define _RCC_CCIPR2 ((uint32_t *)(_RCC_BASE + 0x58)) +#define _RCC_BDCR ((uint32_t *)(_RCC_BASE + 0x5C)) +#define _RCC_CSR ((uint32_t *)(_RCC_BASE + 0x60)) + +/** + * RCC Structs used in source + */ +typedef struct rcc_clocks +{ + uint32_t sysclk; // SYSCLK clock frequency in Hz + uint32_t hclk; // HCLK clock frequency in Hz + uint32_t pclk; // PCLK clock frequency in Hz + uint32_t tpclk; // TPCLK clock frequency in Hz +} rcc_clocks_t; + +/** + * @brief Gets clock values. + * + * @param rcc_clocks_t[OUT] RCC clocks structure. + * + * @return *rcc_clocks_t Structure containing clock values. + */ +void RCC_GetClocksFrequency(rcc_clocks_t *RCC_Clocks); + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_RCC_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/rcc/implementations/doc_ds_82/hal_ll_rcc.h b/targets/arm/mikroe/ai_generated/stm32/include/rcc/implementations/doc_ds_82/hal_ll_rcc.h new file mode 100644 index 000000000..b89ffff31 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/rcc/implementations/doc_ds_82/hal_ll_rcc.h @@ -0,0 +1,114 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_rcc.h + * @brief Reset and Clock control defines necessary for HAL. + */ + +#ifndef _HAL_LL_RCC_H_ +#define _HAL_LL_RCC_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include + +/** + * Core register addresses used in source + */ +#define _RCC_BASE (0x40021000UL) +#define _RCC_CR ((uint32_t *)(_RCC_BASE + 0x0)) +#define _RCC_ICSCR ((uint32_t *)(_RCC_BASE + 0x4)) +#define _RCC_CFGR ((uint32_t *)(_RCC_BASE + 0x8)) +#define _RCC_PLLCFGR ((uint32_t *)(_RCC_BASE + 0xC)) +#define _RCC_CIER ((uint32_t *)(_RCC_BASE + 0x18)) +#define _RCC_CIFR ((uint32_t *)(_RCC_BASE + 0x1C)) +#define _RCC_CICR ((uint32_t *)(_RCC_BASE + 0x20)) +#define _RCC_AHB1RSTR ((uint32_t *)(_RCC_BASE + 0x28)) +#define _RCC_AHB2RSTR ((uint32_t *)(_RCC_BASE + 0x2C)) +#define _RCC_AHB3RSTR ((uint32_t *)(_RCC_BASE + 0x30)) +#define _RCC_APB1RSTR1 ((uint32_t *)(_RCC_BASE + 0x38)) +#define _RCC_APB1RSTR2 ((uint32_t *)(_RCC_BASE + 0x3C)) +#define _RCC_APB2RSTR ((uint32_t *)(_RCC_BASE + 0x40)) +#define _RCC_AHB1ENR ((uint32_t *)(_RCC_BASE + 0x48)) +#define _RCC_AHB2ENR ((uint32_t *)(_RCC_BASE + 0x4C)) +#define _RCC_AHB3ENR ((uint32_t *)(_RCC_BASE + 0x50)) +#define _RCC_APB1ENR1 ((uint32_t *)(_RCC_BASE + 0x58)) +#define _RCC_APB1ENR2 ((uint32_t *)(_RCC_BASE + 0x5C)) +#define _RCC_APB2ENR ((uint32_t *)(_RCC_BASE + 0x60)) +#define _RCC_AHB1SMENR ((uint32_t *)(_RCC_BASE + 0x68)) +#define _RCC_AHB2SMENR ((uint32_t *)(_RCC_BASE + 0x6C)) +#define _RCC_AHB3SMENR ((uint32_t *)(_RCC_BASE + 0x70)) +#define _RCC_APB1SMENR1 ((uint32_t *)(_RCC_BASE + 0x78)) +#define _RCC_APB1SMENR2 ((uint32_t *)(_RCC_BASE + 0x7C)) +#define _RCC_APB2SMENR ((uint32_t *)(_RCC_BASE + 0x80)) +#define _RCC_CCIPR ((uint32_t *)(_RCC_BASE + 0x88)) +#define _RCC_BDCR ((uint32_t *)(_RCC_BASE + 0x90)) +#define _RCC_CSR ((uint32_t *)(_RCC_BASE + 0x94)) +#define _RCC_CRRCR ((uint32_t *)(_RCC_BASE + 0x98)) +#define _RCC_CCIPR2 ((uint32_t *)(_RCC_BASE + 0x9C)) + +/** + * RCC Structs used in source + */ +typedef struct rcc_clocks +{ + uint32_t sysclk; // SYSCLK clock frequency in Hz + uint32_t hclk; // HCLK clock frequency in Hz + uint32_t pclk1; // PCLK1 clock frequency in Hz + uint32_t pclk2; // PCLK2 clock frequency in Hz + uint32_t tpclk; // TPCLK clock frequency in Hz +} rcc_clocks_t; + +/** + * @brief Gets clock values. + * + * @param rcc_clocks_t[OUT] RCC clocks structure. + * + * @return *rcc_clocks_t Structure containing clock values. + */ +void RCC_GetClocksFrequency(rcc_clocks_t *RCC_Clocks); + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_RCC_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/rcc/implementations/doc_ds_83/hal_ll_rcc.h b/targets/arm/mikroe/ai_generated/stm32/include/rcc/implementations/doc_ds_83/hal_ll_rcc.h new file mode 100644 index 000000000..b89ffff31 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/rcc/implementations/doc_ds_83/hal_ll_rcc.h @@ -0,0 +1,114 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_rcc.h + * @brief Reset and Clock control defines necessary for HAL. + */ + +#ifndef _HAL_LL_RCC_H_ +#define _HAL_LL_RCC_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include + +/** + * Core register addresses used in source + */ +#define _RCC_BASE (0x40021000UL) +#define _RCC_CR ((uint32_t *)(_RCC_BASE + 0x0)) +#define _RCC_ICSCR ((uint32_t *)(_RCC_BASE + 0x4)) +#define _RCC_CFGR ((uint32_t *)(_RCC_BASE + 0x8)) +#define _RCC_PLLCFGR ((uint32_t *)(_RCC_BASE + 0xC)) +#define _RCC_CIER ((uint32_t *)(_RCC_BASE + 0x18)) +#define _RCC_CIFR ((uint32_t *)(_RCC_BASE + 0x1C)) +#define _RCC_CICR ((uint32_t *)(_RCC_BASE + 0x20)) +#define _RCC_AHB1RSTR ((uint32_t *)(_RCC_BASE + 0x28)) +#define _RCC_AHB2RSTR ((uint32_t *)(_RCC_BASE + 0x2C)) +#define _RCC_AHB3RSTR ((uint32_t *)(_RCC_BASE + 0x30)) +#define _RCC_APB1RSTR1 ((uint32_t *)(_RCC_BASE + 0x38)) +#define _RCC_APB1RSTR2 ((uint32_t *)(_RCC_BASE + 0x3C)) +#define _RCC_APB2RSTR ((uint32_t *)(_RCC_BASE + 0x40)) +#define _RCC_AHB1ENR ((uint32_t *)(_RCC_BASE + 0x48)) +#define _RCC_AHB2ENR ((uint32_t *)(_RCC_BASE + 0x4C)) +#define _RCC_AHB3ENR ((uint32_t *)(_RCC_BASE + 0x50)) +#define _RCC_APB1ENR1 ((uint32_t *)(_RCC_BASE + 0x58)) +#define _RCC_APB1ENR2 ((uint32_t *)(_RCC_BASE + 0x5C)) +#define _RCC_APB2ENR ((uint32_t *)(_RCC_BASE + 0x60)) +#define _RCC_AHB1SMENR ((uint32_t *)(_RCC_BASE + 0x68)) +#define _RCC_AHB2SMENR ((uint32_t *)(_RCC_BASE + 0x6C)) +#define _RCC_AHB3SMENR ((uint32_t *)(_RCC_BASE + 0x70)) +#define _RCC_APB1SMENR1 ((uint32_t *)(_RCC_BASE + 0x78)) +#define _RCC_APB1SMENR2 ((uint32_t *)(_RCC_BASE + 0x7C)) +#define _RCC_APB2SMENR ((uint32_t *)(_RCC_BASE + 0x80)) +#define _RCC_CCIPR ((uint32_t *)(_RCC_BASE + 0x88)) +#define _RCC_BDCR ((uint32_t *)(_RCC_BASE + 0x90)) +#define _RCC_CSR ((uint32_t *)(_RCC_BASE + 0x94)) +#define _RCC_CRRCR ((uint32_t *)(_RCC_BASE + 0x98)) +#define _RCC_CCIPR2 ((uint32_t *)(_RCC_BASE + 0x9C)) + +/** + * RCC Structs used in source + */ +typedef struct rcc_clocks +{ + uint32_t sysclk; // SYSCLK clock frequency in Hz + uint32_t hclk; // HCLK clock frequency in Hz + uint32_t pclk1; // PCLK1 clock frequency in Hz + uint32_t pclk2; // PCLK2 clock frequency in Hz + uint32_t tpclk; // TPCLK clock frequency in Hz +} rcc_clocks_t; + +/** + * @brief Gets clock values. + * + * @param rcc_clocks_t[OUT] RCC clocks structure. + * + * @return *rcc_clocks_t Structure containing clock values. + */ +void RCC_GetClocksFrequency(rcc_clocks_t *RCC_Clocks); + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_RCC_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/rcc/implementations/doc_ds_84/hal_ll_rcc.h b/targets/arm/mikroe/ai_generated/stm32/include/rcc/implementations/doc_ds_84/hal_ll_rcc.h new file mode 100644 index 000000000..b89ffff31 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/rcc/implementations/doc_ds_84/hal_ll_rcc.h @@ -0,0 +1,114 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_rcc.h + * @brief Reset and Clock control defines necessary for HAL. + */ + +#ifndef _HAL_LL_RCC_H_ +#define _HAL_LL_RCC_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include + +/** + * Core register addresses used in source + */ +#define _RCC_BASE (0x40021000UL) +#define _RCC_CR ((uint32_t *)(_RCC_BASE + 0x0)) +#define _RCC_ICSCR ((uint32_t *)(_RCC_BASE + 0x4)) +#define _RCC_CFGR ((uint32_t *)(_RCC_BASE + 0x8)) +#define _RCC_PLLCFGR ((uint32_t *)(_RCC_BASE + 0xC)) +#define _RCC_CIER ((uint32_t *)(_RCC_BASE + 0x18)) +#define _RCC_CIFR ((uint32_t *)(_RCC_BASE + 0x1C)) +#define _RCC_CICR ((uint32_t *)(_RCC_BASE + 0x20)) +#define _RCC_AHB1RSTR ((uint32_t *)(_RCC_BASE + 0x28)) +#define _RCC_AHB2RSTR ((uint32_t *)(_RCC_BASE + 0x2C)) +#define _RCC_AHB3RSTR ((uint32_t *)(_RCC_BASE + 0x30)) +#define _RCC_APB1RSTR1 ((uint32_t *)(_RCC_BASE + 0x38)) +#define _RCC_APB1RSTR2 ((uint32_t *)(_RCC_BASE + 0x3C)) +#define _RCC_APB2RSTR ((uint32_t *)(_RCC_BASE + 0x40)) +#define _RCC_AHB1ENR ((uint32_t *)(_RCC_BASE + 0x48)) +#define _RCC_AHB2ENR ((uint32_t *)(_RCC_BASE + 0x4C)) +#define _RCC_AHB3ENR ((uint32_t *)(_RCC_BASE + 0x50)) +#define _RCC_APB1ENR1 ((uint32_t *)(_RCC_BASE + 0x58)) +#define _RCC_APB1ENR2 ((uint32_t *)(_RCC_BASE + 0x5C)) +#define _RCC_APB2ENR ((uint32_t *)(_RCC_BASE + 0x60)) +#define _RCC_AHB1SMENR ((uint32_t *)(_RCC_BASE + 0x68)) +#define _RCC_AHB2SMENR ((uint32_t *)(_RCC_BASE + 0x6C)) +#define _RCC_AHB3SMENR ((uint32_t *)(_RCC_BASE + 0x70)) +#define _RCC_APB1SMENR1 ((uint32_t *)(_RCC_BASE + 0x78)) +#define _RCC_APB1SMENR2 ((uint32_t *)(_RCC_BASE + 0x7C)) +#define _RCC_APB2SMENR ((uint32_t *)(_RCC_BASE + 0x80)) +#define _RCC_CCIPR ((uint32_t *)(_RCC_BASE + 0x88)) +#define _RCC_BDCR ((uint32_t *)(_RCC_BASE + 0x90)) +#define _RCC_CSR ((uint32_t *)(_RCC_BASE + 0x94)) +#define _RCC_CRRCR ((uint32_t *)(_RCC_BASE + 0x98)) +#define _RCC_CCIPR2 ((uint32_t *)(_RCC_BASE + 0x9C)) + +/** + * RCC Structs used in source + */ +typedef struct rcc_clocks +{ + uint32_t sysclk; // SYSCLK clock frequency in Hz + uint32_t hclk; // HCLK clock frequency in Hz + uint32_t pclk1; // PCLK1 clock frequency in Hz + uint32_t pclk2; // PCLK2 clock frequency in Hz + uint32_t tpclk; // TPCLK clock frequency in Hz +} rcc_clocks_t; + +/** + * @brief Gets clock values. + * + * @param rcc_clocks_t[OUT] RCC clocks structure. + * + * @return *rcc_clocks_t Structure containing clock values. + */ +void RCC_GetClocksFrequency(rcc_clocks_t *RCC_Clocks); + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_RCC_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/rcc/implementations/doc_ds_85/hal_ll_rcc.h b/targets/arm/mikroe/ai_generated/stm32/include/rcc/implementations/doc_ds_85/hal_ll_rcc.h new file mode 100644 index 000000000..b89ffff31 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/rcc/implementations/doc_ds_85/hal_ll_rcc.h @@ -0,0 +1,114 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_rcc.h + * @brief Reset and Clock control defines necessary for HAL. + */ + +#ifndef _HAL_LL_RCC_H_ +#define _HAL_LL_RCC_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include + +/** + * Core register addresses used in source + */ +#define _RCC_BASE (0x40021000UL) +#define _RCC_CR ((uint32_t *)(_RCC_BASE + 0x0)) +#define _RCC_ICSCR ((uint32_t *)(_RCC_BASE + 0x4)) +#define _RCC_CFGR ((uint32_t *)(_RCC_BASE + 0x8)) +#define _RCC_PLLCFGR ((uint32_t *)(_RCC_BASE + 0xC)) +#define _RCC_CIER ((uint32_t *)(_RCC_BASE + 0x18)) +#define _RCC_CIFR ((uint32_t *)(_RCC_BASE + 0x1C)) +#define _RCC_CICR ((uint32_t *)(_RCC_BASE + 0x20)) +#define _RCC_AHB1RSTR ((uint32_t *)(_RCC_BASE + 0x28)) +#define _RCC_AHB2RSTR ((uint32_t *)(_RCC_BASE + 0x2C)) +#define _RCC_AHB3RSTR ((uint32_t *)(_RCC_BASE + 0x30)) +#define _RCC_APB1RSTR1 ((uint32_t *)(_RCC_BASE + 0x38)) +#define _RCC_APB1RSTR2 ((uint32_t *)(_RCC_BASE + 0x3C)) +#define _RCC_APB2RSTR ((uint32_t *)(_RCC_BASE + 0x40)) +#define _RCC_AHB1ENR ((uint32_t *)(_RCC_BASE + 0x48)) +#define _RCC_AHB2ENR ((uint32_t *)(_RCC_BASE + 0x4C)) +#define _RCC_AHB3ENR ((uint32_t *)(_RCC_BASE + 0x50)) +#define _RCC_APB1ENR1 ((uint32_t *)(_RCC_BASE + 0x58)) +#define _RCC_APB1ENR2 ((uint32_t *)(_RCC_BASE + 0x5C)) +#define _RCC_APB2ENR ((uint32_t *)(_RCC_BASE + 0x60)) +#define _RCC_AHB1SMENR ((uint32_t *)(_RCC_BASE + 0x68)) +#define _RCC_AHB2SMENR ((uint32_t *)(_RCC_BASE + 0x6C)) +#define _RCC_AHB3SMENR ((uint32_t *)(_RCC_BASE + 0x70)) +#define _RCC_APB1SMENR1 ((uint32_t *)(_RCC_BASE + 0x78)) +#define _RCC_APB1SMENR2 ((uint32_t *)(_RCC_BASE + 0x7C)) +#define _RCC_APB2SMENR ((uint32_t *)(_RCC_BASE + 0x80)) +#define _RCC_CCIPR ((uint32_t *)(_RCC_BASE + 0x88)) +#define _RCC_BDCR ((uint32_t *)(_RCC_BASE + 0x90)) +#define _RCC_CSR ((uint32_t *)(_RCC_BASE + 0x94)) +#define _RCC_CRRCR ((uint32_t *)(_RCC_BASE + 0x98)) +#define _RCC_CCIPR2 ((uint32_t *)(_RCC_BASE + 0x9C)) + +/** + * RCC Structs used in source + */ +typedef struct rcc_clocks +{ + uint32_t sysclk; // SYSCLK clock frequency in Hz + uint32_t hclk; // HCLK clock frequency in Hz + uint32_t pclk1; // PCLK1 clock frequency in Hz + uint32_t pclk2; // PCLK2 clock frequency in Hz + uint32_t tpclk; // TPCLK clock frequency in Hz +} rcc_clocks_t; + +/** + * @brief Gets clock values. + * + * @param rcc_clocks_t[OUT] RCC clocks structure. + * + * @return *rcc_clocks_t Structure containing clock values. + */ +void RCC_GetClocksFrequency(rcc_clocks_t *RCC_Clocks); + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_RCC_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/rcc/implementations/doc_ds_86/hal_ll_rcc.h b/targets/arm/mikroe/ai_generated/stm32/include/rcc/implementations/doc_ds_86/hal_ll_rcc.h new file mode 100644 index 000000000..b89ffff31 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/rcc/implementations/doc_ds_86/hal_ll_rcc.h @@ -0,0 +1,114 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_rcc.h + * @brief Reset and Clock control defines necessary for HAL. + */ + +#ifndef _HAL_LL_RCC_H_ +#define _HAL_LL_RCC_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include + +/** + * Core register addresses used in source + */ +#define _RCC_BASE (0x40021000UL) +#define _RCC_CR ((uint32_t *)(_RCC_BASE + 0x0)) +#define _RCC_ICSCR ((uint32_t *)(_RCC_BASE + 0x4)) +#define _RCC_CFGR ((uint32_t *)(_RCC_BASE + 0x8)) +#define _RCC_PLLCFGR ((uint32_t *)(_RCC_BASE + 0xC)) +#define _RCC_CIER ((uint32_t *)(_RCC_BASE + 0x18)) +#define _RCC_CIFR ((uint32_t *)(_RCC_BASE + 0x1C)) +#define _RCC_CICR ((uint32_t *)(_RCC_BASE + 0x20)) +#define _RCC_AHB1RSTR ((uint32_t *)(_RCC_BASE + 0x28)) +#define _RCC_AHB2RSTR ((uint32_t *)(_RCC_BASE + 0x2C)) +#define _RCC_AHB3RSTR ((uint32_t *)(_RCC_BASE + 0x30)) +#define _RCC_APB1RSTR1 ((uint32_t *)(_RCC_BASE + 0x38)) +#define _RCC_APB1RSTR2 ((uint32_t *)(_RCC_BASE + 0x3C)) +#define _RCC_APB2RSTR ((uint32_t *)(_RCC_BASE + 0x40)) +#define _RCC_AHB1ENR ((uint32_t *)(_RCC_BASE + 0x48)) +#define _RCC_AHB2ENR ((uint32_t *)(_RCC_BASE + 0x4C)) +#define _RCC_AHB3ENR ((uint32_t *)(_RCC_BASE + 0x50)) +#define _RCC_APB1ENR1 ((uint32_t *)(_RCC_BASE + 0x58)) +#define _RCC_APB1ENR2 ((uint32_t *)(_RCC_BASE + 0x5C)) +#define _RCC_APB2ENR ((uint32_t *)(_RCC_BASE + 0x60)) +#define _RCC_AHB1SMENR ((uint32_t *)(_RCC_BASE + 0x68)) +#define _RCC_AHB2SMENR ((uint32_t *)(_RCC_BASE + 0x6C)) +#define _RCC_AHB3SMENR ((uint32_t *)(_RCC_BASE + 0x70)) +#define _RCC_APB1SMENR1 ((uint32_t *)(_RCC_BASE + 0x78)) +#define _RCC_APB1SMENR2 ((uint32_t *)(_RCC_BASE + 0x7C)) +#define _RCC_APB2SMENR ((uint32_t *)(_RCC_BASE + 0x80)) +#define _RCC_CCIPR ((uint32_t *)(_RCC_BASE + 0x88)) +#define _RCC_BDCR ((uint32_t *)(_RCC_BASE + 0x90)) +#define _RCC_CSR ((uint32_t *)(_RCC_BASE + 0x94)) +#define _RCC_CRRCR ((uint32_t *)(_RCC_BASE + 0x98)) +#define _RCC_CCIPR2 ((uint32_t *)(_RCC_BASE + 0x9C)) + +/** + * RCC Structs used in source + */ +typedef struct rcc_clocks +{ + uint32_t sysclk; // SYSCLK clock frequency in Hz + uint32_t hclk; // HCLK clock frequency in Hz + uint32_t pclk1; // PCLK1 clock frequency in Hz + uint32_t pclk2; // PCLK2 clock frequency in Hz + uint32_t tpclk; // TPCLK clock frequency in Hz +} rcc_clocks_t; + +/** + * @brief Gets clock values. + * + * @param rcc_clocks_t[OUT] RCC clocks structure. + * + * @return *rcc_clocks_t Structure containing clock values. + */ +void RCC_GetClocksFrequency(rcc_clocks_t *RCC_Clocks); + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_RCC_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/rcc/implementations/doc_ds_87/hal_ll_rcc.h b/targets/arm/mikroe/ai_generated/stm32/include/rcc/implementations/doc_ds_87/hal_ll_rcc.h new file mode 100644 index 000000000..b89ffff31 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/rcc/implementations/doc_ds_87/hal_ll_rcc.h @@ -0,0 +1,114 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_rcc.h + * @brief Reset and Clock control defines necessary for HAL. + */ + +#ifndef _HAL_LL_RCC_H_ +#define _HAL_LL_RCC_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include + +/** + * Core register addresses used in source + */ +#define _RCC_BASE (0x40021000UL) +#define _RCC_CR ((uint32_t *)(_RCC_BASE + 0x0)) +#define _RCC_ICSCR ((uint32_t *)(_RCC_BASE + 0x4)) +#define _RCC_CFGR ((uint32_t *)(_RCC_BASE + 0x8)) +#define _RCC_PLLCFGR ((uint32_t *)(_RCC_BASE + 0xC)) +#define _RCC_CIER ((uint32_t *)(_RCC_BASE + 0x18)) +#define _RCC_CIFR ((uint32_t *)(_RCC_BASE + 0x1C)) +#define _RCC_CICR ((uint32_t *)(_RCC_BASE + 0x20)) +#define _RCC_AHB1RSTR ((uint32_t *)(_RCC_BASE + 0x28)) +#define _RCC_AHB2RSTR ((uint32_t *)(_RCC_BASE + 0x2C)) +#define _RCC_AHB3RSTR ((uint32_t *)(_RCC_BASE + 0x30)) +#define _RCC_APB1RSTR1 ((uint32_t *)(_RCC_BASE + 0x38)) +#define _RCC_APB1RSTR2 ((uint32_t *)(_RCC_BASE + 0x3C)) +#define _RCC_APB2RSTR ((uint32_t *)(_RCC_BASE + 0x40)) +#define _RCC_AHB1ENR ((uint32_t *)(_RCC_BASE + 0x48)) +#define _RCC_AHB2ENR ((uint32_t *)(_RCC_BASE + 0x4C)) +#define _RCC_AHB3ENR ((uint32_t *)(_RCC_BASE + 0x50)) +#define _RCC_APB1ENR1 ((uint32_t *)(_RCC_BASE + 0x58)) +#define _RCC_APB1ENR2 ((uint32_t *)(_RCC_BASE + 0x5C)) +#define _RCC_APB2ENR ((uint32_t *)(_RCC_BASE + 0x60)) +#define _RCC_AHB1SMENR ((uint32_t *)(_RCC_BASE + 0x68)) +#define _RCC_AHB2SMENR ((uint32_t *)(_RCC_BASE + 0x6C)) +#define _RCC_AHB3SMENR ((uint32_t *)(_RCC_BASE + 0x70)) +#define _RCC_APB1SMENR1 ((uint32_t *)(_RCC_BASE + 0x78)) +#define _RCC_APB1SMENR2 ((uint32_t *)(_RCC_BASE + 0x7C)) +#define _RCC_APB2SMENR ((uint32_t *)(_RCC_BASE + 0x80)) +#define _RCC_CCIPR ((uint32_t *)(_RCC_BASE + 0x88)) +#define _RCC_BDCR ((uint32_t *)(_RCC_BASE + 0x90)) +#define _RCC_CSR ((uint32_t *)(_RCC_BASE + 0x94)) +#define _RCC_CRRCR ((uint32_t *)(_RCC_BASE + 0x98)) +#define _RCC_CCIPR2 ((uint32_t *)(_RCC_BASE + 0x9C)) + +/** + * RCC Structs used in source + */ +typedef struct rcc_clocks +{ + uint32_t sysclk; // SYSCLK clock frequency in Hz + uint32_t hclk; // HCLK clock frequency in Hz + uint32_t pclk1; // PCLK1 clock frequency in Hz + uint32_t pclk2; // PCLK2 clock frequency in Hz + uint32_t tpclk; // TPCLK clock frequency in Hz +} rcc_clocks_t; + +/** + * @brief Gets clock values. + * + * @param rcc_clocks_t[OUT] RCC clocks structure. + * + * @return *rcc_clocks_t Structure containing clock values. + */ +void RCC_GetClocksFrequency(rcc_clocks_t *RCC_Clocks); + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_RCC_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/rcc/implementations/doc_ds_88/hal_ll_rcc.h b/targets/arm/mikroe/ai_generated/stm32/include/rcc/implementations/doc_ds_88/hal_ll_rcc.h new file mode 100644 index 000000000..b89ffff31 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/rcc/implementations/doc_ds_88/hal_ll_rcc.h @@ -0,0 +1,114 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_rcc.h + * @brief Reset and Clock control defines necessary for HAL. + */ + +#ifndef _HAL_LL_RCC_H_ +#define _HAL_LL_RCC_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include + +/** + * Core register addresses used in source + */ +#define _RCC_BASE (0x40021000UL) +#define _RCC_CR ((uint32_t *)(_RCC_BASE + 0x0)) +#define _RCC_ICSCR ((uint32_t *)(_RCC_BASE + 0x4)) +#define _RCC_CFGR ((uint32_t *)(_RCC_BASE + 0x8)) +#define _RCC_PLLCFGR ((uint32_t *)(_RCC_BASE + 0xC)) +#define _RCC_CIER ((uint32_t *)(_RCC_BASE + 0x18)) +#define _RCC_CIFR ((uint32_t *)(_RCC_BASE + 0x1C)) +#define _RCC_CICR ((uint32_t *)(_RCC_BASE + 0x20)) +#define _RCC_AHB1RSTR ((uint32_t *)(_RCC_BASE + 0x28)) +#define _RCC_AHB2RSTR ((uint32_t *)(_RCC_BASE + 0x2C)) +#define _RCC_AHB3RSTR ((uint32_t *)(_RCC_BASE + 0x30)) +#define _RCC_APB1RSTR1 ((uint32_t *)(_RCC_BASE + 0x38)) +#define _RCC_APB1RSTR2 ((uint32_t *)(_RCC_BASE + 0x3C)) +#define _RCC_APB2RSTR ((uint32_t *)(_RCC_BASE + 0x40)) +#define _RCC_AHB1ENR ((uint32_t *)(_RCC_BASE + 0x48)) +#define _RCC_AHB2ENR ((uint32_t *)(_RCC_BASE + 0x4C)) +#define _RCC_AHB3ENR ((uint32_t *)(_RCC_BASE + 0x50)) +#define _RCC_APB1ENR1 ((uint32_t *)(_RCC_BASE + 0x58)) +#define _RCC_APB1ENR2 ((uint32_t *)(_RCC_BASE + 0x5C)) +#define _RCC_APB2ENR ((uint32_t *)(_RCC_BASE + 0x60)) +#define _RCC_AHB1SMENR ((uint32_t *)(_RCC_BASE + 0x68)) +#define _RCC_AHB2SMENR ((uint32_t *)(_RCC_BASE + 0x6C)) +#define _RCC_AHB3SMENR ((uint32_t *)(_RCC_BASE + 0x70)) +#define _RCC_APB1SMENR1 ((uint32_t *)(_RCC_BASE + 0x78)) +#define _RCC_APB1SMENR2 ((uint32_t *)(_RCC_BASE + 0x7C)) +#define _RCC_APB2SMENR ((uint32_t *)(_RCC_BASE + 0x80)) +#define _RCC_CCIPR ((uint32_t *)(_RCC_BASE + 0x88)) +#define _RCC_BDCR ((uint32_t *)(_RCC_BASE + 0x90)) +#define _RCC_CSR ((uint32_t *)(_RCC_BASE + 0x94)) +#define _RCC_CRRCR ((uint32_t *)(_RCC_BASE + 0x98)) +#define _RCC_CCIPR2 ((uint32_t *)(_RCC_BASE + 0x9C)) + +/** + * RCC Structs used in source + */ +typedef struct rcc_clocks +{ + uint32_t sysclk; // SYSCLK clock frequency in Hz + uint32_t hclk; // HCLK clock frequency in Hz + uint32_t pclk1; // PCLK1 clock frequency in Hz + uint32_t pclk2; // PCLK2 clock frequency in Hz + uint32_t tpclk; // TPCLK clock frequency in Hz +} rcc_clocks_t; + +/** + * @brief Gets clock values. + * + * @param rcc_clocks_t[OUT] RCC clocks structure. + * + * @return *rcc_clocks_t Structure containing clock values. + */ +void RCC_GetClocksFrequency(rcc_clocks_t *RCC_Clocks); + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_RCC_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/rcc/implementations/doc_ds_89/hal_ll_rcc.h b/targets/arm/mikroe/ai_generated/stm32/include/rcc/implementations/doc_ds_89/hal_ll_rcc.h new file mode 100644 index 000000000..b89ffff31 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/rcc/implementations/doc_ds_89/hal_ll_rcc.h @@ -0,0 +1,114 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_rcc.h + * @brief Reset and Clock control defines necessary for HAL. + */ + +#ifndef _HAL_LL_RCC_H_ +#define _HAL_LL_RCC_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include + +/** + * Core register addresses used in source + */ +#define _RCC_BASE (0x40021000UL) +#define _RCC_CR ((uint32_t *)(_RCC_BASE + 0x0)) +#define _RCC_ICSCR ((uint32_t *)(_RCC_BASE + 0x4)) +#define _RCC_CFGR ((uint32_t *)(_RCC_BASE + 0x8)) +#define _RCC_PLLCFGR ((uint32_t *)(_RCC_BASE + 0xC)) +#define _RCC_CIER ((uint32_t *)(_RCC_BASE + 0x18)) +#define _RCC_CIFR ((uint32_t *)(_RCC_BASE + 0x1C)) +#define _RCC_CICR ((uint32_t *)(_RCC_BASE + 0x20)) +#define _RCC_AHB1RSTR ((uint32_t *)(_RCC_BASE + 0x28)) +#define _RCC_AHB2RSTR ((uint32_t *)(_RCC_BASE + 0x2C)) +#define _RCC_AHB3RSTR ((uint32_t *)(_RCC_BASE + 0x30)) +#define _RCC_APB1RSTR1 ((uint32_t *)(_RCC_BASE + 0x38)) +#define _RCC_APB1RSTR2 ((uint32_t *)(_RCC_BASE + 0x3C)) +#define _RCC_APB2RSTR ((uint32_t *)(_RCC_BASE + 0x40)) +#define _RCC_AHB1ENR ((uint32_t *)(_RCC_BASE + 0x48)) +#define _RCC_AHB2ENR ((uint32_t *)(_RCC_BASE + 0x4C)) +#define _RCC_AHB3ENR ((uint32_t *)(_RCC_BASE + 0x50)) +#define _RCC_APB1ENR1 ((uint32_t *)(_RCC_BASE + 0x58)) +#define _RCC_APB1ENR2 ((uint32_t *)(_RCC_BASE + 0x5C)) +#define _RCC_APB2ENR ((uint32_t *)(_RCC_BASE + 0x60)) +#define _RCC_AHB1SMENR ((uint32_t *)(_RCC_BASE + 0x68)) +#define _RCC_AHB2SMENR ((uint32_t *)(_RCC_BASE + 0x6C)) +#define _RCC_AHB3SMENR ((uint32_t *)(_RCC_BASE + 0x70)) +#define _RCC_APB1SMENR1 ((uint32_t *)(_RCC_BASE + 0x78)) +#define _RCC_APB1SMENR2 ((uint32_t *)(_RCC_BASE + 0x7C)) +#define _RCC_APB2SMENR ((uint32_t *)(_RCC_BASE + 0x80)) +#define _RCC_CCIPR ((uint32_t *)(_RCC_BASE + 0x88)) +#define _RCC_BDCR ((uint32_t *)(_RCC_BASE + 0x90)) +#define _RCC_CSR ((uint32_t *)(_RCC_BASE + 0x94)) +#define _RCC_CRRCR ((uint32_t *)(_RCC_BASE + 0x98)) +#define _RCC_CCIPR2 ((uint32_t *)(_RCC_BASE + 0x9C)) + +/** + * RCC Structs used in source + */ +typedef struct rcc_clocks +{ + uint32_t sysclk; // SYSCLK clock frequency in Hz + uint32_t hclk; // HCLK clock frequency in Hz + uint32_t pclk1; // PCLK1 clock frequency in Hz + uint32_t pclk2; // PCLK2 clock frequency in Hz + uint32_t tpclk; // TPCLK clock frequency in Hz +} rcc_clocks_t; + +/** + * @brief Gets clock values. + * + * @param rcc_clocks_t[OUT] RCC clocks structure. + * + * @return *rcc_clocks_t Structure containing clock values. + */ +void RCC_GetClocksFrequency(rcc_clocks_t *RCC_Clocks); + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_RCC_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/rtc/hal_ll_rtc.h b/targets/arm/mikroe/ai_generated/stm32/include/rtc/hal_ll_rtc.h new file mode 100644 index 000000000..905925792 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/rtc/hal_ll_rtc.h @@ -0,0 +1,152 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_rtc.h + * @brief API for RTC HAL LOW level layer. + */ + +#ifndef _HAL_LL_RTC_H +#define _HAL_LL_RTC_H + +#ifdef __cplusplus +extern "C"{ +#endif + +#ifdef __GNUC__ +#include "mcu.h" +#endif + +#include "hal_target.h" +#include "hal_ll_bit_control.h" + +/** + * @brief Structure representing the RTC time. + * @details This structure is used to hold the real-time clock information, including + * hour, minute, second and it follows a 24-hour format. + * @note Take into consideration that any value can be changed explicitly by the user. + */ +typedef struct +{ + uint8_t hour; // 2-digit format - supports values from 00 to 23 + uint8_t minute; // 2-digit format - supports values from 00 to 59 + uint8_t second; // 2-digit format - supports values from 00 to 59 +} hal_ll_rtc_time_t; + +/** + * @brief Initialize the RTC module. + * @details Initialize the RTC module. + * @param None. + */ +void hal_ll_rtc_init(); + +/** + * @brief Start the RTC module. + * @details Continue the RTC module count from the stored value in the count register. + * @param None. + * @return The function can return one of the values defined by + * hal_ll_rtc_err_t structure, which is size dependant on the architecture. + * @note It is recommended to check return value for error. + * @pre Before calling this function, the user is expected + * to have initialized RTC by using hal_ll_rtc_init() and have the RTC not counting. + */ +err_t hal_ll_rtc_start(); + +/** + * @brief Stop the RTC module. + * @details Stop the RTC module count. + * @param None. + * @return The function can return one of the values defined by + * hal_ll_rtc_err_t structure, which is size dependant on the architecture. + * @note It is recommended to check return value for error. + * @pre Before calling this function, the user is expected + * to have the RTC started. + */ +err_t hal_ll_rtc_stop(); + +/** + * @brief Reset the RTC module. + * @details Reset the RTC counter to the default values of 0h:0m:0s. + * @param None. + * @return The function can return one of the values defined by + * hal_ll_rtc_err_t structure, which is size dependant on the architecture. + * @note It is recommended to check return value for error. + * @pre Before calling this function, the user is expected + * to have the RTC started. + */ +err_t hal_ll_rtc_reset(); + +/** + * @brief Configure time of RTC module. + * @details Configure time registers with the values from hal_ll_rtc_time_t structure. + * @param time hal_ll_rtc_time_t structure. + * @return The function can return one of the values defined by + * hal_ll_rtc_err_t structure, which is size dependant on the architecture. + * @note It is recommended to check return value for error. + * @pre Before calling this function, the user is expected + * to have the RTC enabled. + */ +err_t hal_ll_rtc_set_time( hal_ll_rtc_time_t *time ); + +/** + * @brief Get time from RTC module. + * @details Configure hal_ll_rtc_time_t structure with the values from time registers. + * @param time hal_ll_rtc_time_t structure. + * @return The function can return one of the values defined by + * hal_ll_rtc_err_t structure, which is size dependant on the architecture. + * @note It is recommended to check return value for error. + * @pre Before calling this function, the user is expected + * to have the RTC enabled. + */ +err_t hal_ll_rtc_get_time( hal_ll_rtc_time_t *time ); + +/** + * @brief Preforms system reset. + * @details Resets the core and all on-chip peripherals except the Debug + * interface. + * @param None. + * @warning System reset affects core and periferals, + * depending on the architecture you will need to reconfigure opened modules. + */ +void hal_ll_rtc_system_reset(); + +#ifdef __cplusplus +} +#endif + +#endif // HAL_LL_RTC_H diff --git a/targets/arm/mikroe/ai_generated/stm32/include/rtc/implementations/.gitkeep b/targets/arm/mikroe/ai_generated/stm32/include/rtc/implementations/.gitkeep new file mode 100644 index 000000000..e69de29bb diff --git a/targets/arm/mikroe/ai_generated/stm32/include/spi_master/hal_ll_spi_master.h b/targets/arm/mikroe/ai_generated/stm32/include/spi_master/hal_ll_spi_master.h new file mode 100644 index 000000000..f2035088b --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/spi_master/hal_ll_spi_master.h @@ -0,0 +1,232 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_spi_master.h + * @brief API for SPI master HAL LOW LEVEL layer. + */ + +#ifndef _HAL_LL_SPI_MASTER_H_ +#define _HAL_LL_SPI_MASTER_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_target.h" +#include "hal_ll_gpio.h" + +/** + * @brief SPI configuration pins structure. + */ +typedef struct +{ + hal_ll_pin_af_t sck; + hal_ll_pin_af_t miso; + hal_ll_pin_af_t mosi; +} hal_ll_spi_master_pins_t; + +/** + * @brief SPI master HAL low lever configuration structure. + */ +typedef struct +{ + uint8_t default_write_data; + hal_ll_pin_name_t sck; + hal_ll_pin_name_t miso; + hal_ll_pin_name_t mosi; + uint32_t speed; +} hal_ll_spi_master_config_t; + +/** + * @brief Enum containing predefined module mode values. + * + * Enum values: + * + * HAL_LL_SPI_MASTER_MODE_0 -- CPOL = 0, CPHA = 0 + * HAL_LL_SPI_MASTER_MODE_1 -- CPOL = 0, CPHA = 1 + * HAL_LL_SPI_MASTER_MODE_2 -- CPOL = 1, CPHA = 0 + * HAL_LL_SPI_MASTER_MODE_3 -- CPOL = 1, CPHA = 1 + */ +typedef enum +{ + HAL_LL_SPI_MASTER_MODE_0 = 0, + HAL_LL_SPI_MASTER_MODE_1, + HAL_LL_SPI_MASTER_MODE_2, + HAL_LL_SPI_MASTER_MODE_3, + + HAL_LL_SPI_MASTER_MODE_DEFAULT = HAL_LL_SPI_MASTER_MODE_0 +} hal_ll_spi_master_mode_t; + +/** + * @brief SPI master HAL low lever handle register. + */ +typedef struct +{ + handle_t *hal_ll_spi_master_handle; + handle_t *hal_drv_spi_master_handle; + bool init_ll_state; +} hal_ll_spi_master_handle_register_t; + +/** + * @brief Registers handler for future use. + * + * Registers low level and hal level handlers + * for use with appropriate functions. + * + * @param[in] *handle HAL context object handle. + * @param[in] sck SPI sck pin. + * @param[in] miso SPI miso pin. + * @param[in] mosi SPI mosi pin. + * @param[in] *handle_map HAL layer local handle map. + * @param[in] *hal_module_id HAL layer module number. + + * @return hal_ll_err_t Module specific error. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_spi_master_register_handle( hal_ll_pin_name_t sck, hal_ll_pin_name_t miso, + hal_ll_pin_name_t mosi, hal_ll_spi_master_handle_register_t *handle_map, uint8_t *hal_module_id ); + +/** + * @brief Configures specified module. + * + * Performs module configuration on the hardware + * level. Enables module specific clock gate and + * sets adequate alternate function values. + * + * @param[in] *handle HAL context object handle. + * + * @return hal_ll_err_t Module specific error. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_module_configure_spi( handle_t *handle ); + +/** + * @brief Sets SPI Master configuration dummy data. + * @param config[IN] SPI Master module configuration. + * @param config[IN] user-defined dummy data. + */ +void hal_ll_spi_master_set_default_write_data( handle_t *handle, uint8_t dummy_data ); + +/** + * @brief Sets SPI Master configuration dummy data. + * @param config[IN] SPI Master module configuration. + * @param config[IN] user-defined SPI Master baud rate value. + */ +uint32_t hal_ll_spi_master_set_speed( handle_t *handle, uint32_t speed ); + +/** + * @brief Sets SPI Master configuration dummy data. + * @param[in] *handle HAL context object handle. + * @param[in] mode SPI Master de-facto mode selection. + */ +hal_ll_err_t hal_ll_spi_master_set_mode( handle_t *handle, hal_ll_spi_master_mode_t mode ); + +/** + * @brief Executes low level data write on SPI bus. + * + * Function shall generate a START signal, + * followed by write_data_buffer number of writes + * on the bus. + * + * @param *handle HAL context object handle. + * @param *write_data_buffer Data buffer where data to be written is located. + * @param length_data Number of bytes to send. + * + * @return hal_ll_err_t Module specific error. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_spi_master_write( handle_t *handle, uint8_t *write_data_buffer, size_t length_data); + +/** + * @brief Executes low level data read on SPI bus. + * + * @param handle I2C handle. + * @param *read_data_buffer Data buffer where read data shall be placed. + * @param length_data Number of bytes to read. + * + * @return hal_ll_err_t Module specific error. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_spi_master_read( handle_t *handle, uint8_t *read_data_buffer, size_t length_data); + +/** + * @brief Perform a low level write followed by a low level read on the SPI bus. + * + * Initializes SPI Master module on hardware level, if not initialized beforehand + * and continues to perform a write operation followed by a + * read operation on the bus. + * + * @param[in] *handle - Object specific context handler. + * @param[in] *write_data_buffer - Pointer to write data buffer. + * @param[in] length_write_data - Number of data to be written. + * @param[in] *read_data_buffer - Pointer to read data buffer. + * @param[in] length_read_data - Number of data to be read. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_spi_master_write_then_read( handle_t *handle, uint8_t *write_data_buffer, size_t length_write_data, uint8_t *read_data_buffer, size_t length_read_data ); + +/** + * @brief Closes SPI Master HAL and HAL_LOW_LEVEL context object. + * + * De-allocates hardware resources for specific driver object and + * de-initializes the module on a hardware level. + * + * @param[in] *handle HAL context object handle. + * + * @return void None. + */ +void hal_ll_spi_master_close( handle_t *handle ); + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_SPI_MASTER_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/spi_master/hal_ll_spi_master_pin_map/implementations/doc_ds_1/hal_ll_spi_master_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/spi_master/hal_ll_spi_master_pin_map/implementations/doc_ds_1/hal_ll_spi_master_pin_map.h new file mode 100644 index 000000000..907291bdd --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/spi_master/hal_ll_spi_master_pin_map/implementations/doc_ds_1/hal_ll_spi_master_pin_map.h @@ -0,0 +1,126 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_spi_master_pin_map.h + * @brief SPI HAL LOW LEVEL MASTER PIN MAP. + */ + +#ifndef _HAL_LL_SPI_MASTER_PIN_MAP_H_ +#define _HAL_LL_SPI_MASTER_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_spi_master_module_num(_module_num) (_module_num - 1) +#define hal_ll_spi_module_num(_module_num) hal_ll_spi_master_module_num(_module_num) + +/*!< @brief Pin function structure. */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + uint8_t module_index; + uint32_t af; +} hal_ll_spi_master_pin_map_t; + +#ifdef SPI_MODULE_1 +#define SPI1_BASE_ADDRESS (0x40013000UL) +#define SPI1_BASE_ADDR SPI1_BASE_ADDRESS +#define HAL_LL_SPI1_BASE_ADDR SPI1_BASE_ADDRESS +#define HAL_LL_SPI1_BASE_ADDRESS SPI1_BASE_ADDRESS +#endif + +/*!< @brief SPI SCK pins. */ +static const hal_ll_spi_master_pin_map_t _spi_sck_map[] = +{ + #ifdef SPI1_SCK_PA1_AF0 + {PA1, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 0}, + #endif + #ifdef SPI1_SCK_PA5_AF0 + {PA5, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 0}, + #endif + #ifdef SPI1_SCK_PB6_AF10 + {PB6, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 10}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} +}; + +/*!< @brief SPI MISO pins. */ +static const hal_ll_spi_master_pin_map_t _spi_miso_map[] = +{ + #ifdef SPI1_MISO_PA11_AF0 + {PA11, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 0}, + #endif + #ifdef SPI1_MISO_PA6_AF0 + {PA6, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 0}, + #endif + #ifdef SPI1_MISO_PB6_AF9 + {PB6, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 9}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} +}; + +/*!< @brief SPI MOSI pins. */ +static const hal_ll_spi_master_pin_map_t _spi_mosi_map[] = +{ + #ifdef SPI1_MOSI_PA12_AF0 + {PA12, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 0}, + #endif + #ifdef SPI1_MOSI_PA2_AF0 + {PA2, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 0}, + #endif + #ifdef SPI1_MOSI_PA7_AF0 + {PA7, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 0}, + #endif + #ifdef SPI1_MOSI_PB6_AF8 + {PB6, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 8}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_SPI_MASTER_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/spi_master/hal_ll_spi_master_pin_map/implementations/doc_ds_160/hal_ll_spi_master_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/spi_master/hal_ll_spi_master_pin_map/implementations/doc_ds_160/hal_ll_spi_master_pin_map.h new file mode 100644 index 000000000..168187e96 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/spi_master/hal_ll_spi_master_pin_map/implementations/doc_ds_160/hal_ll_spi_master_pin_map.h @@ -0,0 +1,228 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_spi_master_pin_map.h + * @brief SPI HAL LOW LEVEL MASTER PIN MAP. + */ + +#ifndef _HAL_LL_SPI_MASTER_PIN_MAP_H_ +#define _HAL_LL_SPI_MASTER_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_spi_master_module_num(_module_num) (_module_num - 1) +#define hal_ll_spi_module_num(_module_num) hal_ll_spi_master_module_num(_module_num) + +/*!< @brief Pin function structure. */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + uint8_t module_index; + uint32_t af; +} hal_ll_spi_master_pin_map_t; + +#ifdef SPI_MODULE_1 +#define SPI1_BASE_ADDRESS (0x40013000UL) +#define SPI1_BASE_ADDR SPI1_BASE_ADDRESS +#define HAL_LL_SPI1_BASE_ADDR SPI1_BASE_ADDRESS +#define HAL_LL_SPI1_BASE_ADDRESS SPI1_BASE_ADDRESS +#endif +#ifdef SPI_MODULE_2 +#define SPI2_BASE_ADDRESS (0x40003800UL) +#define SPI2_BASE_ADDR SPI2_BASE_ADDRESS +#define HAL_LL_SPI2_BASE_ADDR SPI2_BASE_ADDRESS +#define HAL_LL_SPI2_BASE_ADDRESS SPI2_BASE_ADDRESS +#endif +#ifdef SPI_MODULE_3 +#define SPI3_BASE_ADDRESS (0x40003C00UL) +#define SPI3_BASE_ADDR SPI3_BASE_ADDRESS +#define HAL_LL_SPI3_BASE_ADDR SPI3_BASE_ADDRESS +#define HAL_LL_SPI3_BASE_ADDRESS SPI3_BASE_ADDRESS +#endif + +/*!< @brief SPI SCK pins. */ +static const hal_ll_spi_master_pin_map_t _spi_sck_map[] = +{ + #ifdef SPI1_SCK_PA1_AF5 + {PA1, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI1_SCK_PA5_AF5 + {PA5, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI1_SCK_PB3_AF5 + {PB3, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI1_SCK_PE13_AF5 + {PE13, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI1_SCK_PG2_AF5 + {PG2, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI2_SCK_PA9_AF3 + {PA9, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 3}, + #endif + #ifdef SPI2_SCK_PB10_AF5 + {PB10, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI2_SCK_PB13_AF5 + {PB13, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI2_SCK_PD1_AF5 + {PD1, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI2_SCK_PD3_AF3 + {PD3, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 3}, + #endif + #ifdef SPI3_SCK_PB3_AF6 + {PB3, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 6}, + #endif + #ifdef SPI3_SCK_PC10_AF6 + {PC10, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 6}, + #endif + #ifdef SPI3_SCK_PG9_AF6 + {PG9, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 6}, + #endif + #ifdef SPI2_SCK_PI1_AF5 + {PI1, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} +}; + +/*!< @brief SPI MISO pins. */ +static const hal_ll_spi_master_pin_map_t _spi_miso_map[] = +{ + #ifdef SPI1_MISO_PA11_AF5 + {PA11, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI1_MISO_PA6_AF5 + {PA6, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI1_MISO_PB4_AF5 + {PB4, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI1_MISO_PE14_AF5 + {PE14, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI1_MISO_PG3_AF5 + {PG3, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI2_MISO_PB14_AF5 + {PB14, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI2_MISO_PC2_AF5 + {PC2, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI2_MISO_PD3_AF5 + {PD3, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI3_MISO_PB4_AF6 + {PB4, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 6}, + #endif + #ifdef SPI3_MISO_PC11_AF6 + {PC11, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 6}, + #endif + #ifdef SPI3_MISO_PG10_AF6 + {PG10, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 6}, + #endif + #ifdef SPI2_MISO_PI2_AF5 + {PI2, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} +}; + +/*!< @brief SPI MOSI pins. */ +static const hal_ll_spi_master_pin_map_t _spi_mosi_map[] = +{ + #ifdef SPI1_MOSI_PA12_AF5 + {PA12, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI1_MOSI_PA7_AF5 + {PA7, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI1_MOSI_PB5_AF5 + {PB5, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI1_MOSI_PE15_AF5 + {PE15, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI1_MOSI_PG4_AF5 + {PG4, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI2_MOSI_PB15_AF5 + {PB15, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI2_MOSI_PC1_AF3 + {PC1, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 3}, + #endif + #ifdef SPI2_MOSI_PC3_AF5 + {PC3, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI2_MOSI_PD4_AF5 + {PD4, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI3_MOSI_PB5_AF6 + {PB5, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 6}, + #endif + #ifdef SPI3_MOSI_PC12_AF6 + {PC12, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 6}, + #endif + #ifdef SPI3_MOSI_PD6_AF5 + {PD6, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 5}, + #endif + #ifdef SPI3_MOSI_PG11_AF6 + {PG11, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 6}, + #endif + #ifdef SPI2_MOSI_PI3_AF5 + {PI3, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_SPI_MASTER_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/spi_master/hal_ll_spi_master_pin_map/implementations/doc_ds_161/hal_ll_spi_master_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/spi_master/hal_ll_spi_master_pin_map/implementations/doc_ds_161/hal_ll_spi_master_pin_map.h new file mode 100644 index 000000000..168187e96 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/spi_master/hal_ll_spi_master_pin_map/implementations/doc_ds_161/hal_ll_spi_master_pin_map.h @@ -0,0 +1,228 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_spi_master_pin_map.h + * @brief SPI HAL LOW LEVEL MASTER PIN MAP. + */ + +#ifndef _HAL_LL_SPI_MASTER_PIN_MAP_H_ +#define _HAL_LL_SPI_MASTER_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_spi_master_module_num(_module_num) (_module_num - 1) +#define hal_ll_spi_module_num(_module_num) hal_ll_spi_master_module_num(_module_num) + +/*!< @brief Pin function structure. */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + uint8_t module_index; + uint32_t af; +} hal_ll_spi_master_pin_map_t; + +#ifdef SPI_MODULE_1 +#define SPI1_BASE_ADDRESS (0x40013000UL) +#define SPI1_BASE_ADDR SPI1_BASE_ADDRESS +#define HAL_LL_SPI1_BASE_ADDR SPI1_BASE_ADDRESS +#define HAL_LL_SPI1_BASE_ADDRESS SPI1_BASE_ADDRESS +#endif +#ifdef SPI_MODULE_2 +#define SPI2_BASE_ADDRESS (0x40003800UL) +#define SPI2_BASE_ADDR SPI2_BASE_ADDRESS +#define HAL_LL_SPI2_BASE_ADDR SPI2_BASE_ADDRESS +#define HAL_LL_SPI2_BASE_ADDRESS SPI2_BASE_ADDRESS +#endif +#ifdef SPI_MODULE_3 +#define SPI3_BASE_ADDRESS (0x40003C00UL) +#define SPI3_BASE_ADDR SPI3_BASE_ADDRESS +#define HAL_LL_SPI3_BASE_ADDR SPI3_BASE_ADDRESS +#define HAL_LL_SPI3_BASE_ADDRESS SPI3_BASE_ADDRESS +#endif + +/*!< @brief SPI SCK pins. */ +static const hal_ll_spi_master_pin_map_t _spi_sck_map[] = +{ + #ifdef SPI1_SCK_PA1_AF5 + {PA1, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI1_SCK_PA5_AF5 + {PA5, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI1_SCK_PB3_AF5 + {PB3, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI1_SCK_PE13_AF5 + {PE13, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI1_SCK_PG2_AF5 + {PG2, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI2_SCK_PA9_AF3 + {PA9, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 3}, + #endif + #ifdef SPI2_SCK_PB10_AF5 + {PB10, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI2_SCK_PB13_AF5 + {PB13, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI2_SCK_PD1_AF5 + {PD1, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI2_SCK_PD3_AF3 + {PD3, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 3}, + #endif + #ifdef SPI3_SCK_PB3_AF6 + {PB3, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 6}, + #endif + #ifdef SPI3_SCK_PC10_AF6 + {PC10, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 6}, + #endif + #ifdef SPI3_SCK_PG9_AF6 + {PG9, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 6}, + #endif + #ifdef SPI2_SCK_PI1_AF5 + {PI1, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} +}; + +/*!< @brief SPI MISO pins. */ +static const hal_ll_spi_master_pin_map_t _spi_miso_map[] = +{ + #ifdef SPI1_MISO_PA11_AF5 + {PA11, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI1_MISO_PA6_AF5 + {PA6, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI1_MISO_PB4_AF5 + {PB4, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI1_MISO_PE14_AF5 + {PE14, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI1_MISO_PG3_AF5 + {PG3, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI2_MISO_PB14_AF5 + {PB14, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI2_MISO_PC2_AF5 + {PC2, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI2_MISO_PD3_AF5 + {PD3, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI3_MISO_PB4_AF6 + {PB4, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 6}, + #endif + #ifdef SPI3_MISO_PC11_AF6 + {PC11, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 6}, + #endif + #ifdef SPI3_MISO_PG10_AF6 + {PG10, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 6}, + #endif + #ifdef SPI2_MISO_PI2_AF5 + {PI2, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} +}; + +/*!< @brief SPI MOSI pins. */ +static const hal_ll_spi_master_pin_map_t _spi_mosi_map[] = +{ + #ifdef SPI1_MOSI_PA12_AF5 + {PA12, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI1_MOSI_PA7_AF5 + {PA7, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI1_MOSI_PB5_AF5 + {PB5, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI1_MOSI_PE15_AF5 + {PE15, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI1_MOSI_PG4_AF5 + {PG4, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI2_MOSI_PB15_AF5 + {PB15, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI2_MOSI_PC1_AF3 + {PC1, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 3}, + #endif + #ifdef SPI2_MOSI_PC3_AF5 + {PC3, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI2_MOSI_PD4_AF5 + {PD4, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI3_MOSI_PB5_AF6 + {PB5, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 6}, + #endif + #ifdef SPI3_MOSI_PC12_AF6 + {PC12, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 6}, + #endif + #ifdef SPI3_MOSI_PD6_AF5 + {PD6, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 5}, + #endif + #ifdef SPI3_MOSI_PG11_AF6 + {PG11, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 6}, + #endif + #ifdef SPI2_MOSI_PI3_AF5 + {PI3, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_SPI_MASTER_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/spi_master/hal_ll_spi_master_pin_map/implementations/doc_ds_2/hal_ll_spi_master_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/spi_master/hal_ll_spi_master_pin_map/implementations/doc_ds_2/hal_ll_spi_master_pin_map.h new file mode 100644 index 000000000..8a64a9cee --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/spi_master/hal_ll_spi_master_pin_map/implementations/doc_ds_2/hal_ll_spi_master_pin_map.h @@ -0,0 +1,135 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_spi_master_pin_map.h + * @brief SPI HAL LOW LEVEL MASTER PIN MAP. + */ + +#ifndef _HAL_LL_SPI_MASTER_PIN_MAP_H_ +#define _HAL_LL_SPI_MASTER_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_spi_master_module_num(_module_num) (_module_num - 1) +#define hal_ll_spi_module_num(_module_num) hal_ll_spi_master_module_num(_module_num) + +/*!< @brief Pin function structure. */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + uint8_t module_index; + uint32_t af; +} hal_ll_spi_master_pin_map_t; + +#ifdef SPI_MODULE_1 +#define SPI1_BASE_ADDRESS (0x40013000UL) +#define SPI1_BASE_ADDR SPI1_BASE_ADDRESS +#define HAL_LL_SPI1_BASE_ADDR SPI1_BASE_ADDRESS +#define HAL_LL_SPI1_BASE_ADDRESS SPI1_BASE_ADDRESS +#endif + +/*!< @brief SPI SCK pins. */ +static const hal_ll_spi_master_pin_map_t _spi_sck_map[] = +{ + #ifdef SPI1_SCK_PA1_AF0 + {PA1, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 0}, + #endif + #ifdef SPI1_SCK_PA5_AF0 + {PA5, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 0}, + #endif + #ifdef SPI1_SCK_PB3_AF0 + {PB3, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 0}, + #endif + #ifdef SPI1_SCK_PB6_AF10 + {PB6, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 10}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} +}; + +/*!< @brief SPI MISO pins. */ +static const hal_ll_spi_master_pin_map_t _spi_miso_map[] = +{ + #ifdef SPI1_MISO_PA11_AF0 + {PA11, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 0}, + #endif + #ifdef SPI1_MISO_PA6_AF0 + {PA6, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 0}, + #endif + #ifdef SPI1_MISO_PB4_AF0 + {PB4, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 0}, + #endif + #ifdef SPI1_MISO_PB6_AF9 + {PB6, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 9}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} +}; + +/*!< @brief SPI MOSI pins. */ +static const hal_ll_spi_master_pin_map_t _spi_mosi_map[] = +{ + #ifdef SPI1_MOSI_PA12_AF0 + {PA12, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 0}, + #endif + #ifdef SPI1_MOSI_PA2_AF0 + {PA2, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 0}, + #endif + #ifdef SPI1_MOSI_PA7_AF0 + {PA7, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 0}, + #endif + #ifdef SPI1_MOSI_PB5_AF0 + {PB5, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 0}, + #endif + #ifdef SPI1_MOSI_PB6_AF8 + {PB6, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 8}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_SPI_MASTER_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/spi_master/hal_ll_spi_master_pin_map/implementations/doc_ds_74/hal_ll_spi_master_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/spi_master/hal_ll_spi_master_pin_map/implementations/doc_ds_74/hal_ll_spi_master_pin_map.h new file mode 100644 index 000000000..12ecee404 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/spi_master/hal_ll_spi_master_pin_map/implementations/doc_ds_74/hal_ll_spi_master_pin_map.h @@ -0,0 +1,180 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_spi_master_pin_map.h + * @brief SPI HAL LOW LEVEL MASTER PIN MAP. + */ + +#ifndef _HAL_LL_SPI_MASTER_PIN_MAP_H_ +#define _HAL_LL_SPI_MASTER_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_spi_master_module_num(_module_num) (_module_num - 1) +#define hal_ll_spi_module_num(_module_num) hal_ll_spi_master_module_num(_module_num) + +/*!< @brief Pin function structure. */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + uint8_t module_index; + uint32_t af; +} hal_ll_spi_master_pin_map_t; + +#ifdef SPI_MODULE_1 +#define SPI1_BASE_ADDRESS (0x40013000UL) +#define SPI1_BASE_ADDR SPI1_BASE_ADDRESS +#define HAL_LL_SPI1_BASE_ADDR SPI1_BASE_ADDRESS +#define HAL_LL_SPI1_BASE_ADDRESS SPI1_BASE_ADDRESS +#endif +#ifdef SPI_MODULE_2 +#define SPI2_BASE_ADDRESS (0x40003800UL) +#define SPI2_BASE_ADDR SPI2_BASE_ADDRESS +#define HAL_LL_SPI2_BASE_ADDR SPI2_BASE_ADDRESS +#define HAL_LL_SPI2_BASE_ADDRESS SPI2_BASE_ADDRESS +#endif + +/*!< @brief SPI SCK pins. */ +static const hal_ll_spi_master_pin_map_t _spi_sck_map[] = +{ + #ifdef SPI1_SCK_PA1_AF0 + {PA1, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 0}, + #endif + #ifdef SPI1_SCK_PA5_AF0 + {PA5, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 0}, + #endif + #ifdef SPI1_SCK_PB3_AF0 + {PB3, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 0}, + #endif + #ifdef SPI2_SCK_PA0_AF0 + {PA0, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 0}, + #endif + #ifdef SPI2_SCK_PB8_AF1 + {PB8, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 1}, + #endif + #ifdef SPI2_SCK_PB10_AF5 + {PB10, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI2_SCK_PB13_AF0 + {PB13, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 0}, + #endif + #ifdef SPI2_SCK_PD1_AF1 + {PD1, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 1}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} +}; + +/*!< @brief SPI MISO pins. */ +static const hal_ll_spi_master_pin_map_t _spi_miso_map[] = +{ + #ifdef SPI1_MISO_PA11_AF0 + {PA11, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 0}, + #endif + #ifdef SPI1_MISO_PA6_AF0 + {PA6, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 0}, + #endif + #ifdef SPI1_MISO_PB4_AF0 + {PB4, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 0}, + #endif + #ifdef SPI2_MISO_PA3_AF0 + {PA3, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 0}, + #endif + #ifdef SPI2_MISO_PA9_AF4 + {PA9, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 4}, + #endif + #ifdef SPI2_MISO_PB2_AF1 + {PB2, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 1}, + #endif + #ifdef SPI2_MISO_PB6_AF4 + {PB6, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 4}, + #endif + #ifdef SPI2_MISO_PB14_AF0 + {PB14, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 0}, + #endif + #ifdef SPI2_MISO_PD3_AF1 + {PD3, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 1}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} +}; + +/*!< @brief SPI MOSI pins. */ +static const hal_ll_spi_master_pin_map_t _spi_mosi_map[] = +{ + #ifdef SPI1_MOSI_PA12_AF0 + {PA12, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 0}, + #endif + #ifdef SPI1_MOSI_PA2_AF0 + {PA2, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 0}, + #endif + #ifdef SPI1_MOSI_PA7_AF0 + {PA7, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 0}, + #endif + #ifdef SPI1_MOSI_PB5_AF0 + {PB5, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 0}, + #endif + #ifdef SPI2_MOSI_PA10_AF0 + {PA10, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 0}, + #endif + #ifdef SPI2_MOSI_PA4_AF1 + {PA4, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 1}, + #endif + #ifdef SPI2_MOSI_PB7_AF1 + {PB7, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 1}, + #endif + #ifdef SPI2_MOSI_PB11_AF0 + {PB11, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 0}, + #endif + #ifdef SPI2_MOSI_PB15_AF0 + {PB15, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 0}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_SPI_MASTER_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/spi_master/hal_ll_spi_master_pin_map/implementations/doc_ds_75/hal_ll_spi_master_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/spi_master/hal_ll_spi_master_pin_map/implementations/doc_ds_75/hal_ll_spi_master_pin_map.h new file mode 100644 index 000000000..12ecee404 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/spi_master/hal_ll_spi_master_pin_map/implementations/doc_ds_75/hal_ll_spi_master_pin_map.h @@ -0,0 +1,180 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_spi_master_pin_map.h + * @brief SPI HAL LOW LEVEL MASTER PIN MAP. + */ + +#ifndef _HAL_LL_SPI_MASTER_PIN_MAP_H_ +#define _HAL_LL_SPI_MASTER_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_spi_master_module_num(_module_num) (_module_num - 1) +#define hal_ll_spi_module_num(_module_num) hal_ll_spi_master_module_num(_module_num) + +/*!< @brief Pin function structure. */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + uint8_t module_index; + uint32_t af; +} hal_ll_spi_master_pin_map_t; + +#ifdef SPI_MODULE_1 +#define SPI1_BASE_ADDRESS (0x40013000UL) +#define SPI1_BASE_ADDR SPI1_BASE_ADDRESS +#define HAL_LL_SPI1_BASE_ADDR SPI1_BASE_ADDRESS +#define HAL_LL_SPI1_BASE_ADDRESS SPI1_BASE_ADDRESS +#endif +#ifdef SPI_MODULE_2 +#define SPI2_BASE_ADDRESS (0x40003800UL) +#define SPI2_BASE_ADDR SPI2_BASE_ADDRESS +#define HAL_LL_SPI2_BASE_ADDR SPI2_BASE_ADDRESS +#define HAL_LL_SPI2_BASE_ADDRESS SPI2_BASE_ADDRESS +#endif + +/*!< @brief SPI SCK pins. */ +static const hal_ll_spi_master_pin_map_t _spi_sck_map[] = +{ + #ifdef SPI1_SCK_PA1_AF0 + {PA1, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 0}, + #endif + #ifdef SPI1_SCK_PA5_AF0 + {PA5, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 0}, + #endif + #ifdef SPI1_SCK_PB3_AF0 + {PB3, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 0}, + #endif + #ifdef SPI2_SCK_PA0_AF0 + {PA0, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 0}, + #endif + #ifdef SPI2_SCK_PB8_AF1 + {PB8, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 1}, + #endif + #ifdef SPI2_SCK_PB10_AF5 + {PB10, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI2_SCK_PB13_AF0 + {PB13, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 0}, + #endif + #ifdef SPI2_SCK_PD1_AF1 + {PD1, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 1}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} +}; + +/*!< @brief SPI MISO pins. */ +static const hal_ll_spi_master_pin_map_t _spi_miso_map[] = +{ + #ifdef SPI1_MISO_PA11_AF0 + {PA11, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 0}, + #endif + #ifdef SPI1_MISO_PA6_AF0 + {PA6, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 0}, + #endif + #ifdef SPI1_MISO_PB4_AF0 + {PB4, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 0}, + #endif + #ifdef SPI2_MISO_PA3_AF0 + {PA3, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 0}, + #endif + #ifdef SPI2_MISO_PA9_AF4 + {PA9, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 4}, + #endif + #ifdef SPI2_MISO_PB2_AF1 + {PB2, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 1}, + #endif + #ifdef SPI2_MISO_PB6_AF4 + {PB6, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 4}, + #endif + #ifdef SPI2_MISO_PB14_AF0 + {PB14, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 0}, + #endif + #ifdef SPI2_MISO_PD3_AF1 + {PD3, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 1}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} +}; + +/*!< @brief SPI MOSI pins. */ +static const hal_ll_spi_master_pin_map_t _spi_mosi_map[] = +{ + #ifdef SPI1_MOSI_PA12_AF0 + {PA12, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 0}, + #endif + #ifdef SPI1_MOSI_PA2_AF0 + {PA2, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 0}, + #endif + #ifdef SPI1_MOSI_PA7_AF0 + {PA7, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 0}, + #endif + #ifdef SPI1_MOSI_PB5_AF0 + {PB5, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 0}, + #endif + #ifdef SPI2_MOSI_PA10_AF0 + {PA10, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 0}, + #endif + #ifdef SPI2_MOSI_PA4_AF1 + {PA4, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 1}, + #endif + #ifdef SPI2_MOSI_PB7_AF1 + {PB7, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 1}, + #endif + #ifdef SPI2_MOSI_PB11_AF0 + {PB11, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 0}, + #endif + #ifdef SPI2_MOSI_PB15_AF0 + {PB15, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 0}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_SPI_MASTER_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/spi_master/hal_ll_spi_master_pin_map/implementations/doc_ds_80/hal_ll_spi_master_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/spi_master/hal_ll_spi_master_pin_map/implementations/doc_ds_80/hal_ll_spi_master_pin_map.h new file mode 100644 index 000000000..dd38d9441 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/spi_master/hal_ll_spi_master_pin_map/implementations/doc_ds_80/hal_ll_spi_master_pin_map.h @@ -0,0 +1,231 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_spi_master_pin_map.h + * @brief SPI HAL LOW LEVEL MASTER PIN MAP. + */ + +#ifndef _HAL_LL_SPI_MASTER_PIN_MAP_H_ +#define _HAL_LL_SPI_MASTER_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_spi_master_module_num(_module_num) (_module_num - 1) +#define hal_ll_spi_module_num(_module_num) hal_ll_spi_master_module_num(_module_num) + +/*!< @brief Pin function structure. */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + uint8_t module_index; + uint32_t af; +} hal_ll_spi_master_pin_map_t; + +#ifdef SPI_MODULE_1 +#define SPI1_BASE_ADDRESS (0x40013000UL) +#define SPI1_BASE_ADDR SPI1_BASE_ADDRESS +#define HAL_LL_SPI1_BASE_ADDR SPI1_BASE_ADDRESS +#define HAL_LL_SPI1_BASE_ADDRESS SPI1_BASE_ADDRESS +#endif +#ifdef SPI_MODULE_2 +#define SPI2_BASE_ADDRESS (0x40003800UL) +#define SPI2_BASE_ADDR SPI2_BASE_ADDRESS +#define HAL_LL_SPI2_BASE_ADDR SPI2_BASE_ADDRESS +#define HAL_LL_SPI2_BASE_ADDRESS SPI2_BASE_ADDRESS +#endif +#ifdef SPI_MODULE_3 +#define SPI3_BASE_ADDRESS (0x40003C00UL) +#define SPI3_BASE_ADDR SPI3_BASE_ADDRESS +#define HAL_LL_SPI3_BASE_ADDR SPI3_BASE_ADDRESS +#define HAL_LL_SPI3_BASE_ADDRESS SPI3_BASE_ADDRESS +#endif + +/*!< @brief SPI SCK pins. */ +static const hal_ll_spi_master_pin_map_t _spi_sck_map[] = +{ + #ifdef SPI1_SCK_PA1_AF0 + {PA1, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 0}, + #endif + #ifdef SPI1_SCK_PA5_AF0 + {PA5, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 0}, + #endif + #ifdef SPI1_SCK_PB3_AF0 + {PB3, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 0}, + #endif + #ifdef SPI1_SCK_PD8_AF1 + {PD8, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 1}, + #endif + #ifdef SPI2_SCK_PA0_AF0 + {PA0, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 0}, + #endif + #ifdef SPI2_SCK_PB10_AF5 + {PB10, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI2_SCK_PB13_AF0 + {PB13, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 0}, + #endif + #ifdef SPI2_SCK_PB8_AF1 + {PB8, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 1}, + #endif + #ifdef SPI2_SCK_PD1_AF1 + {PD1, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 1}, + #endif + #ifdef SPI3_SCK_PB3_AF9 + {PB3, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 9}, + #endif + #ifdef SPI3_SCK_PC10_AF4 + {PC10, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 4}, + #endif + #ifdef SPI1_SCK_PE13_AF0 + {PE13, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 0}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} +}; + +/*!< @brief SPI MISO pins. */ +static const hal_ll_spi_master_pin_map_t _spi_miso_map[] = +{ + #ifdef SPI1_MISO_PA11_AF0 + {PA11, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 0}, + #endif + #ifdef SPI1_MISO_PA6_AF0 + {PA6, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 0}, + #endif + #ifdef SPI1_MISO_PB4_AF0 + {PB4, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 0}, + #endif + #ifdef SPI1_MISO_PD5_AF1 + {PD5, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 1}, + #endif + #ifdef SPI2_MISO_PA3_AF0 + {PA3, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 0}, + #endif + #ifdef SPI2_MISO_PA9_AF4 + {PA9, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 4}, + #endif + #ifdef SPI2_MISO_PB14_AF0 + {PB14, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 0}, + #endif + #ifdef SPI2_MISO_PB2_AF1 + {PB2, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 1}, + #endif + #ifdef SPI2_MISO_PB6_AF4 + {PB6, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 4}, + #endif + #ifdef SPI2_MISO_PC2_AF1 + {PC2, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 1}, + #endif + #ifdef SPI2_MISO_PD3_AF1 + {PD3, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 1}, + #endif + #ifdef SPI3_MISO_PB4_AF9 + {PB4, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 9}, + #endif + #ifdef SPI3_MISO_PC11_AF4 + {PC11, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 4}, + #endif + #ifdef SPI1_MISO_PE14_AF0 + {PE14, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 0}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} +}; + +/*!< @brief SPI MOSI pins. */ +static const hal_ll_spi_master_pin_map_t _spi_mosi_map[] = +{ + #ifdef SPI1_MOSI_PA12_AF0 + {PA12, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 0}, + #endif + #ifdef SPI1_MOSI_PA2_AF0 + {PA2, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 0}, + #endif + #ifdef SPI1_MOSI_PA7_AF0 + {PA7, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 0}, + #endif + #ifdef SPI1_MOSI_PB5_AF0 + {PB5, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 0}, + #endif + #ifdef SPI1_MOSI_PD6_AF1 + {PD6, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 1}, + #endif + #ifdef SPI2_MOSI_PA10_AF0 + {PA10, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 0}, + #endif + #ifdef SPI2_MOSI_PA4_AF1 + {PA4, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 1}, + #endif + #ifdef SPI2_MOSI_PB11_AF0 + {PB11, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 0}, + #endif + #ifdef SPI2_MOSI_PB15_AF0 + {PB15, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 0}, + #endif + #ifdef SPI2_MOSI_PB7_AF1 + {PB7, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 1}, + #endif + #ifdef SPI2_MOSI_PC3_AF1 + {PC3, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 1}, + #endif + #ifdef SPI2_MOSI_PD4_AF1 + {PD4, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 1}, + #endif + #ifdef SPI3_MOSI_PB5_AF9 + {PB5, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 9}, + #endif + #ifdef SPI3_MOSI_PC12_AF4 + {PC12, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 4}, + #endif + #ifdef SPI1_MOSI_PE15_AF0 + {PE15, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 0}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_SPI_MASTER_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/spi_master/hal_ll_spi_master_pin_map/implementations/doc_ds_81/hal_ll_spi_master_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/spi_master/hal_ll_spi_master_pin_map/implementations/doc_ds_81/hal_ll_spi_master_pin_map.h new file mode 100644 index 000000000..338392482 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/spi_master/hal_ll_spi_master_pin_map/implementations/doc_ds_81/hal_ll_spi_master_pin_map.h @@ -0,0 +1,231 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_spi_master_pin_map.h + * @brief SPI HAL LOW LEVEL MASTER PIN MAP. + */ + +#ifndef _HAL_LL_SPI_MASTER_PIN_MAP_H_ +#define _HAL_LL_SPI_MASTER_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_spi_master_module_num(_module_num) (_module_num - 1) +#define hal_ll_spi_module_num(_module_num) hal_ll_spi_master_module_num(_module_num) + +/*!< @brief Pin function structure. */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + uint8_t module_index; + uint32_t af; +} hal_ll_spi_master_pin_map_t; + +#ifdef SPI_MODULE_1 +#define SPI1_BASE_ADDRESS (0x40013000UL) +#define SPI1_BASE_ADDR SPI1_BASE_ADDRESS +#define HAL_LL_SPI1_BASE_ADDR SPI1_BASE_ADDRESS +#define HAL_LL_SPI1_BASE_ADDRESS SPI1_BASE_ADDRESS +#endif +#ifdef SPI_MODULE_2 +#define SPI2_BASE_ADDRESS (0x40003800UL) +#define SPI2_BASE_ADDR SPI2_BASE_ADDRESS +#define HAL_LL_SPI2_BASE_ADDR SPI2_BASE_ADDRESS +#define HAL_LL_SPI2_BASE_ADDRESS SPI2_BASE_ADDRESS +#endif +#ifdef SPI_MODULE_3 +#define SPI3_BASE_ADDRESS (0x40003C00UL) +#define SPI3_BASE_ADDR SPI3_BASE_ADDRESS +#define HAL_LL_SPI3_BASE_ADDR SPI3_BASE_ADDRESS +#define HAL_LL_SPI3_BASE_ADDRESS SPI3_BASE_ADDRESS +#endif + +/*!< @brief SPI SCK pins. */ +static const hal_ll_spi_master_pin_map_t _spi_sck_map[] = +{ + #ifdef SPI1_SCK_PA1_AF0 + {PA1, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 0}, + #endif + #ifdef SPI1_SCK_PA5_AF0 + {PA5, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 0}, + #endif + #ifdef SPI1_SCK_PB3_AF0 + {PB3, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 0}, + #endif + #ifdef SPI2_SCK_PA0_AF0 + {PA0, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 0}, + #endif + #ifdef SPI2_SCK_PB10_AF5 + {PB10, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI2_SCK_PB13_AF0 + {PB13, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 0}, + #endif + #ifdef SPI2_SCK_PB8_AF1 + {PB8, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 1}, + #endif + #ifdef SPI2_SCK_PD1_AF1 + {PD1, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 1}, + #endif + #ifdef SPI3_SCK_PB3_AF9 + {PB3, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 9}, + #endif + #ifdef SPI1_SCK_PD8_AF1 + {PD8, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 1}, + #endif + #ifdef SPI3_SCK_PC10_AF4 + {PC10, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 4}, + #endif + #ifdef SPI1_SCK_PE13_AF0 + {PE13, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 0}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} +}; + +/*!< @brief SPI MISO pins. */ +static const hal_ll_spi_master_pin_map_t _spi_miso_map[] = +{ + #ifdef SPI1_MISO_PA11_AF0 + {PA11, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 0}, + #endif + #ifdef SPI1_MISO_PA6_AF0 + {PA6, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 0}, + #endif + #ifdef SPI1_MISO_PB4_AF0 + {PB4, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 0}, + #endif + #ifdef SPI2_MISO_PA3_AF0 + {PA3, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 0}, + #endif + #ifdef SPI2_MISO_PA9_AF4 + {PA9, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 4}, + #endif + #ifdef SPI2_MISO_PB14_AF0 + {PB14, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 0}, + #endif + #ifdef SPI2_MISO_PB2_AF1 + {PB2, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 1}, + #endif + #ifdef SPI2_MISO_PB6_AF4 + {PB6, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 4}, + #endif + #ifdef SPI2_MISO_PD3_AF1 + {PD3, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 1}, + #endif + #ifdef SPI3_MISO_PB4_AF9 + {PB4, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 9}, + #endif + #ifdef SPI1_MISO_PD5_AF1 + {PD5, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 1}, + #endif + #ifdef SPI2_MISO_PC2_AF1 + {PC2, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 1}, + #endif + #ifdef SPI3_MISO_PC11_AF4 + {PC11, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 4}, + #endif + #ifdef SPI1_MISO_PE14_AF0 + {PE14, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 0}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} +}; + +/*!< @brief SPI MOSI pins. */ +static const hal_ll_spi_master_pin_map_t _spi_mosi_map[] = +{ + #ifdef SPI1_MOSI_PA12_AF0 + {PA12, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 0}, + #endif + #ifdef SPI1_MOSI_PA2_AF0 + {PA2, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 0}, + #endif + #ifdef SPI1_MOSI_PA7_AF0 + {PA7, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 0}, + #endif + #ifdef SPI1_MOSI_PB5_AF0 + {PB5, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 0}, + #endif + #ifdef SPI2_MOSI_PA10_AF0 + {PA10, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 0}, + #endif + #ifdef SPI2_MOSI_PA4_AF1 + {PA4, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 1}, + #endif + #ifdef SPI2_MOSI_PB11_AF0 + {PB11, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 0}, + #endif + #ifdef SPI2_MOSI_PB15_AF0 + {PB15, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 0}, + #endif + #ifdef SPI2_MOSI_PB7_AF1 + {PB7, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 1}, + #endif + #ifdef SPI3_MOSI_PB5_AF9 + {PB5, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 9}, + #endif + #ifdef SPI1_MOSI_PD6_AF1 + {PD6, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 1}, + #endif + #ifdef SPI2_MOSI_PC3_AF1 + {PC3, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 1}, + #endif + #ifdef SPI2_MOSI_PD4_AF1 + {PD4, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 1}, + #endif + #ifdef SPI3_MOSI_PC12_AF4 + {PC12, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 4}, + #endif + #ifdef SPI1_MOSI_PE15_AF0 + {PE15, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 0}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_SPI_MASTER_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/spi_master/hal_ll_spi_master_pin_map/implementations/doc_ds_82/hal_ll_spi_master_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/spi_master/hal_ll_spi_master_pin_map/implementations/doc_ds_82/hal_ll_spi_master_pin_map.h new file mode 100644 index 000000000..fd3a0d8db --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/spi_master/hal_ll_spi_master_pin_map/implementations/doc_ds_82/hal_ll_spi_master_pin_map.h @@ -0,0 +1,168 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_spi_master_pin_map.h + * @brief SPI HAL LOW LEVEL MASTER PIN MAP. + */ + +#ifndef _HAL_LL_SPI_MASTER_PIN_MAP_H_ +#define _HAL_LL_SPI_MASTER_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_spi_master_module_num(_module_num) (_module_num - 1) +#define hal_ll_spi_module_num(_module_num) hal_ll_spi_master_module_num(_module_num) + +/*!< @brief Pin function structure. */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + uint8_t module_index; + uint32_t af; +} hal_ll_spi_master_pin_map_t; + +#ifdef SPI_MODULE_1 +#define SPI1_BASE_ADDRESS (0x40013000UL) +#define SPI1_BASE_ADDR SPI1_BASE_ADDRESS +#define HAL_LL_SPI1_BASE_ADDR SPI1_BASE_ADDRESS +#define HAL_LL_SPI1_BASE_ADDRESS SPI1_BASE_ADDRESS +#endif +#ifdef SPI_MODULE_2 +#define SPI2_BASE_ADDRESS (0x40003800UL) +#define SPI2_BASE_ADDR SPI2_BASE_ADDRESS +#define HAL_LL_SPI2_BASE_ADDR SPI2_BASE_ADDRESS +#define HAL_LL_SPI2_BASE_ADDRESS SPI2_BASE_ADDRESS +#endif +#ifdef SPI_MODULE_3 +#define SPI3_BASE_ADDRESS (0x40003C00UL) +#define SPI3_BASE_ADDR SPI3_BASE_ADDRESS +#define HAL_LL_SPI3_BASE_ADDR SPI3_BASE_ADDRESS +#define HAL_LL_SPI3_BASE_ADDRESS SPI3_BASE_ADDRESS +#endif + +/*!< @brief SPI SCK pins. */ +static const hal_ll_spi_master_pin_map_t _spi_sck_map[] = +{ + #ifdef SPI1_SCK_PA5_AF5 + {PA5, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI1_SCK_PB3_AF5 + {PB3, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI2_SCK_PF1_AF5 + {PF1, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI3_SCK_PB3_AF6 + {PB3, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 6}, + #endif + #ifdef SPI2_SCK_PB13_AF5 + {PB13, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI3_SCK_PC10_AF6 + {PC10, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 6}, + #endif + #ifdef SPI2_SCK_PF10_AF5 + {PF10, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI2_SCK_PF9_AF5 + {PF9, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} +}; + +/*!< @brief SPI MISO pins. */ +static const hal_ll_spi_master_pin_map_t _spi_miso_map[] = +{ + #ifdef SPI1_MISO_PA6_AF5 + {PA6, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI1_MISO_PB4_AF5 + {PB4, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI2_MISO_PA10_AF5 + {PA10, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI3_MISO_PB4_AF6 + {PB4, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 6}, + #endif + #ifdef SPI2_MISO_PB14_AF5 + {PB14, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI3_MISO_PC11_AF6 + {PC11, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 6}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} +}; + +/*!< @brief SPI MOSI pins. */ +static const hal_ll_spi_master_pin_map_t _spi_mosi_map[] = +{ + #ifdef SPI1_MOSI_PA7_AF5 + {PA7, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI1_MOSI_PB5_AF5 + {PB5, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI2_MOSI_PA11_AF5 + {PA11, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI3_MOSI_PB5_AF6 + {PB5, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 6}, + #endif + #ifdef SPI2_MOSI_PB15_AF5 + {PB15, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI3_MOSI_PC12_AF6 + {PC12, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 6}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_SPI_MASTER_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/spi_master/hal_ll_spi_master_pin_map/implementations/doc_ds_83/hal_ll_spi_master_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/spi_master/hal_ll_spi_master_pin_map/implementations/doc_ds_83/hal_ll_spi_master_pin_map.h new file mode 100644 index 000000000..1d440f1dc --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/spi_master/hal_ll_spi_master_pin_map/implementations/doc_ds_83/hal_ll_spi_master_pin_map.h @@ -0,0 +1,168 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_spi_master_pin_map.h + * @brief SPI HAL LOW LEVEL MASTER PIN MAP. + */ + +#ifndef _HAL_LL_SPI_MASTER_PIN_MAP_H_ +#define _HAL_LL_SPI_MASTER_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_spi_master_module_num(_module_num) (_module_num - 1) +#define hal_ll_spi_module_num(_module_num) hal_ll_spi_master_module_num(_module_num) + +/*!< @brief Pin function structure. */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + uint8_t module_index; + uint32_t af; +} hal_ll_spi_master_pin_map_t; + +#ifdef SPI_MODULE_1 +#define SPI1_BASE_ADDRESS (0x40013000UL) +#define SPI1_BASE_ADDR SPI1_BASE_ADDRESS +#define HAL_LL_SPI1_BASE_ADDR SPI1_BASE_ADDRESS +#define HAL_LL_SPI1_BASE_ADDRESS SPI1_BASE_ADDRESS +#endif +#ifdef SPI_MODULE_2 +#define SPI2_BASE_ADDRESS (0x40003800UL) +#define SPI2_BASE_ADDR SPI2_BASE_ADDRESS +#define HAL_LL_SPI2_BASE_ADDR SPI2_BASE_ADDRESS +#define HAL_LL_SPI2_BASE_ADDRESS SPI2_BASE_ADDRESS +#endif +#ifdef SPI_MODULE_3 +#define SPI3_BASE_ADDRESS (0x40003C00UL) +#define SPI3_BASE_ADDR SPI3_BASE_ADDRESS +#define HAL_LL_SPI3_BASE_ADDR SPI3_BASE_ADDRESS +#define HAL_LL_SPI3_BASE_ADDRESS SPI3_BASE_ADDRESS +#endif + +/*!< @brief SPI SCK pins. */ +static const hal_ll_spi_master_pin_map_t _spi_sck_map[] = +{ + #ifdef SPI1_SCK_PA5_AF5 + {PA5, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI1_SCK_PB3_AF5 + {PB3, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI2_SCK_PB13_AF5 + {PB13, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI2_SCK_PF1_AF5 + {PF1, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI3_SCK_PB3_AF6 + {PB3, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 6}, + #endif + #ifdef SPI3_SCK_PC10_AF6 + {PC10, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 6}, + #endif + #ifdef SPI2_SCK_PF10_AF5 + {PF10, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI2_SCK_PF9_AF5 + {PF9, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} +}; + +/*!< @brief SPI MISO pins. */ +static const hal_ll_spi_master_pin_map_t _spi_miso_map[] = +{ + #ifdef SPI1_MISO_PA6_AF5 + {PA6, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI1_MISO_PB4_AF5 + {PB4, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI2_MISO_PA10_AF5 + {PA10, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI2_MISO_PB14_AF5 + {PB14, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI3_MISO_PB4_AF6 + {PB4, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 6}, + #endif + #ifdef SPI3_MISO_PC11_AF6 + {PC11, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 6}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} +}; + +/*!< @brief SPI MOSI pins. */ +static const hal_ll_spi_master_pin_map_t _spi_mosi_map[] = +{ + #ifdef SPI1_MOSI_PA7_AF5 + {PA7, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI1_MOSI_PB5_AF5 + {PB5, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI2_MOSI_PA11_AF5 + {PA11, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI2_MOSI_PB15_AF5 + {PB15, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI3_MOSI_PB5_AF6 + {PB5, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 6}, + #endif + #ifdef SPI3_MOSI_PC12_AF6 + {PC12, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 6}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_SPI_MASTER_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/spi_master/hal_ll_spi_master_pin_map/implementations/doc_ds_84/hal_ll_spi_master_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/spi_master/hal_ll_spi_master_pin_map/implementations/doc_ds_84/hal_ll_spi_master_pin_map.h new file mode 100644 index 000000000..02e44bec3 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/spi_master/hal_ll_spi_master_pin_map/implementations/doc_ds_84/hal_ll_spi_master_pin_map.h @@ -0,0 +1,204 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_spi_master_pin_map.h + * @brief SPI HAL LOW LEVEL MASTER PIN MAP. + */ + +#ifndef _HAL_LL_SPI_MASTER_PIN_MAP_H_ +#define _HAL_LL_SPI_MASTER_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_spi_master_module_num(_module_num) (_module_num - 1) +#define hal_ll_spi_module_num(_module_num) hal_ll_spi_master_module_num(_module_num) + +/*!< @brief Pin function structure. */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + uint8_t module_index; + uint32_t af; +} hal_ll_spi_master_pin_map_t; + +#ifdef SPI_MODULE_1 +#define SPI1_BASE_ADDRESS (0x40013000UL) +#define SPI1_BASE_ADDR SPI1_BASE_ADDRESS +#define HAL_LL_SPI1_BASE_ADDR SPI1_BASE_ADDRESS +#define HAL_LL_SPI1_BASE_ADDRESS SPI1_BASE_ADDRESS +#endif +#ifdef SPI_MODULE_2 +#define SPI2_BASE_ADDRESS (0x40003800UL) +#define SPI2_BASE_ADDR SPI2_BASE_ADDRESS +#define HAL_LL_SPI2_BASE_ADDR SPI2_BASE_ADDRESS +#define HAL_LL_SPI2_BASE_ADDRESS SPI2_BASE_ADDRESS +#endif +#ifdef SPI_MODULE_3 +#define SPI3_BASE_ADDRESS (0x40003C00UL) +#define SPI3_BASE_ADDR SPI3_BASE_ADDRESS +#define HAL_LL_SPI3_BASE_ADDR SPI3_BASE_ADDRESS +#define HAL_LL_SPI3_BASE_ADDRESS SPI3_BASE_ADDRESS +#endif +#ifdef SPI_MODULE_4 +#define SPI4_BASE_ADDRESS (0x40013C00UL) +#define SPI4_BASE_ADDR SPI4_BASE_ADDRESS +#define HAL_LL_SPI4_BASE_ADDR SPI4_BASE_ADDRESS +#define HAL_LL_SPI4_BASE_ADDRESS SPI4_BASE_ADDRESS +#endif + +/*!< @brief SPI SCK pins. */ +static const hal_ll_spi_master_pin_map_t _spi_sck_map[] = +{ + #ifdef SPI1_SCK_PA5_AF5 + {PA5, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI1_SCK_PB3_AF5 + {PB3, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI1_SCK_PG2_AF5 + {PG2, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI2_SCK_PB13_AF5 + {PB13, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI2_SCK_PF10_AF5 + {PF10, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI2_SCK_PF1_AF5 + {PF1, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI2_SCK_PF9_AF5 + {PF9, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI3_SCK_PB3_AF6 + {PB3, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 6}, + #endif + #ifdef SPI3_SCK_PC10_AF6 + {PC10, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 6}, + #endif + #ifdef SPI4_SCK_PE12_AF5 + {PE12, SPI4_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_4), 5}, + #endif + #ifdef SPI4_SCK_PE2_AF5 + {PE2, SPI4_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_4), 5}, + #endif + #ifdef SPI3_SCK_PG9_AF6 + {PG9, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 6}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} +}; + +/*!< @brief SPI MISO pins. */ +static const hal_ll_spi_master_pin_map_t _spi_miso_map[] = +{ + #ifdef SPI1_MISO_PA6_AF5 + {PA6, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI1_MISO_PB4_AF5 + {PB4, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI1_MISO_PG3_AF5 + {PG3, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI2_MISO_PA10_AF5 + {PA10, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI2_MISO_PB14_AF5 + {PB14, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI3_MISO_PB4_AF6 + {PB4, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 6}, + #endif + #ifdef SPI3_MISO_PC11_AF6 + {PC11, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 6}, + #endif + #ifdef SPI4_MISO_PE13_AF5 + {PE13, SPI4_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_4), 5}, + #endif + #ifdef SPI4_MISO_PE5_AF5 + {PE5, SPI4_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_4), 5}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} +}; + +/*!< @brief SPI MOSI pins. */ +static const hal_ll_spi_master_pin_map_t _spi_mosi_map[] = +{ + #ifdef SPI1_MOSI_PA7_AF5 + {PA7, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI1_MOSI_PB5_AF5 + {PB5, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI1_MOSI_PG4_AF5 + {PG4, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI2_MOSI_PA11_AF5 + {PA11, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI2_MOSI_PB15_AF5 + {PB15, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI3_MOSI_PB5_AF6 + {PB5, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 6}, + #endif + #ifdef SPI3_MOSI_PC12_AF6 + {PC12, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 6}, + #endif + #ifdef SPI4_MOSI_PE14_AF5 + {PE14, SPI4_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_4), 5}, + #endif + #ifdef SPI4_MOSI_PE6_AF5 + {PE6, SPI4_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_4), 5}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_SPI_MASTER_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/spi_master/hal_ll_spi_master_pin_map/implementations/doc_ds_85/hal_ll_spi_master_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/spi_master/hal_ll_spi_master_pin_map/implementations/doc_ds_85/hal_ll_spi_master_pin_map.h new file mode 100644 index 000000000..0dd93c91b --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/spi_master/hal_ll_spi_master_pin_map/implementations/doc_ds_85/hal_ll_spi_master_pin_map.h @@ -0,0 +1,204 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_spi_master_pin_map.h + * @brief SPI HAL LOW LEVEL MASTER PIN MAP. + */ + +#ifndef _HAL_LL_SPI_MASTER_PIN_MAP_H_ +#define _HAL_LL_SPI_MASTER_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_spi_master_module_num(_module_num) (_module_num - 1) +#define hal_ll_spi_module_num(_module_num) hal_ll_spi_master_module_num(_module_num) + +/*!< @brief Pin function structure. */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + uint8_t module_index; + uint32_t af; +} hal_ll_spi_master_pin_map_t; + +#ifdef SPI_MODULE_1 +#define SPI1_BASE_ADDRESS (0x40013000UL) +#define SPI1_BASE_ADDR SPI1_BASE_ADDRESS +#define HAL_LL_SPI1_BASE_ADDR SPI1_BASE_ADDRESS +#define HAL_LL_SPI1_BASE_ADDRESS SPI1_BASE_ADDRESS +#endif +#ifdef SPI_MODULE_2 +#define SPI2_BASE_ADDRESS (0x40003800UL) +#define SPI2_BASE_ADDR SPI2_BASE_ADDRESS +#define HAL_LL_SPI2_BASE_ADDR SPI2_BASE_ADDRESS +#define HAL_LL_SPI2_BASE_ADDRESS SPI2_BASE_ADDRESS +#endif +#ifdef SPI_MODULE_3 +#define SPI3_BASE_ADDRESS (0x40003C00UL) +#define SPI3_BASE_ADDR SPI3_BASE_ADDRESS +#define HAL_LL_SPI3_BASE_ADDR SPI3_BASE_ADDRESS +#define HAL_LL_SPI3_BASE_ADDRESS SPI3_BASE_ADDRESS +#endif +#ifdef SPI_MODULE_4 +#define SPI4_BASE_ADDRESS (0x40013C00UL) +#define SPI4_BASE_ADDR SPI4_BASE_ADDRESS +#define HAL_LL_SPI4_BASE_ADDR SPI4_BASE_ADDRESS +#define HAL_LL_SPI4_BASE_ADDRESS SPI4_BASE_ADDRESS +#endif + +/*!< @brief SPI SCK pins. */ +static const hal_ll_spi_master_pin_map_t _spi_sck_map[] = +{ + #ifdef SPI1_SCK_PA5_AF5 + {PA5, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI1_SCK_PB3_AF5 + {PB3, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI2_SCK_PB13_AF5 + {PB13, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI2_SCK_PF1_AF5 + {PF1, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI3_SCK_PB3_AF6 + {PB3, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 6}, + #endif + #ifdef SPI3_SCK_PC10_AF6 + {PC10, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 6}, + #endif + #ifdef SPI2_SCK_PF10_AF5 + {PF10, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI2_SCK_PF9_AF5 + {PF9, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI4_SCK_PE12_AF5 + {PE12, SPI4_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_4), 5}, + #endif + #ifdef SPI4_SCK_PE2_AF5 + {PE2, SPI4_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_4), 5}, + #endif + #ifdef SPI1_SCK_PG2_AF5 + {PG2, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI3_SCK_PG9_AF6 + {PG9, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 6}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} +}; + +/*!< @brief SPI MISO pins. */ +static const hal_ll_spi_master_pin_map_t _spi_miso_map[] = +{ + #ifdef SPI1_MISO_PA6_AF5 + {PA6, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI1_MISO_PB4_AF5 + {PB4, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI2_MISO_PA10_AF5 + {PA10, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI2_MISO_PB14_AF5 + {PB14, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI3_MISO_PB4_AF6 + {PB4, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 6}, + #endif + #ifdef SPI3_MISO_PC11_AF6 + {PC11, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 6}, + #endif + #ifdef SPI4_MISO_PE13_AF5 + {PE13, SPI4_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_4), 5}, + #endif + #ifdef SPI4_MISO_PE5_AF5 + {PE5, SPI4_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_4), 5}, + #endif + #ifdef SPI1_MISO_PG3_AF5 + {PG3, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} +}; + +/*!< @brief SPI MOSI pins. */ +static const hal_ll_spi_master_pin_map_t _spi_mosi_map[] = +{ + #ifdef SPI1_MOSI_PA7_AF5 + {PA7, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI1_MOSI_PB5_AF5 + {PB5, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI2_MOSI_PA11_AF5 + {PA11, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI2_MOSI_PB15_AF5 + {PB15, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI3_MOSI_PB5_AF6 + {PB5, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 6}, + #endif + #ifdef SPI3_MOSI_PC12_AF6 + {PC12, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 6}, + #endif + #ifdef SPI4_MOSI_PE14_AF5 + {PE14, SPI4_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_4), 5}, + #endif + #ifdef SPI4_MOSI_PE6_AF5 + {PE6, SPI4_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_4), 5}, + #endif + #ifdef SPI1_MOSI_PG4_AF5 + {PG4, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_SPI_MASTER_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/spi_master/hal_ll_spi_master_pin_map/implementations/doc_ds_86/hal_ll_spi_master_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/spi_master/hal_ll_spi_master_pin_map/implementations/doc_ds_86/hal_ll_spi_master_pin_map.h new file mode 100644 index 000000000..0532f49bd --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/spi_master/hal_ll_spi_master_pin_map/implementations/doc_ds_86/hal_ll_spi_master_pin_map.h @@ -0,0 +1,204 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_spi_master_pin_map.h + * @brief SPI HAL LOW LEVEL MASTER PIN MAP. + */ + +#ifndef _HAL_LL_SPI_MASTER_PIN_MAP_H_ +#define _HAL_LL_SPI_MASTER_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_spi_master_module_num(_module_num) (_module_num - 1) +#define hal_ll_spi_module_num(_module_num) hal_ll_spi_master_module_num(_module_num) + +/*!< @brief Pin function structure. */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + uint8_t module_index; + uint32_t af; +} hal_ll_spi_master_pin_map_t; + +#ifdef SPI_MODULE_1 +#define SPI1_BASE_ADDRESS (0x40013000UL) +#define SPI1_BASE_ADDR SPI1_BASE_ADDRESS +#define HAL_LL_SPI1_BASE_ADDR SPI1_BASE_ADDRESS +#define HAL_LL_SPI1_BASE_ADDRESS SPI1_BASE_ADDRESS +#endif +#ifdef SPI_MODULE_2 +#define SPI2_BASE_ADDRESS (0x40003800UL) +#define SPI2_BASE_ADDR SPI2_BASE_ADDRESS +#define HAL_LL_SPI2_BASE_ADDR SPI2_BASE_ADDRESS +#define HAL_LL_SPI2_BASE_ADDRESS SPI2_BASE_ADDRESS +#endif +#ifdef SPI_MODULE_3 +#define SPI3_BASE_ADDRESS (0x40003C00UL) +#define SPI3_BASE_ADDR SPI3_BASE_ADDRESS +#define HAL_LL_SPI3_BASE_ADDR SPI3_BASE_ADDRESS +#define HAL_LL_SPI3_BASE_ADDRESS SPI3_BASE_ADDRESS +#endif +#ifdef SPI_MODULE_4 +#define SPI4_BASE_ADDRESS (0x40013C00UL) +#define SPI4_BASE_ADDR SPI4_BASE_ADDRESS +#define HAL_LL_SPI4_BASE_ADDR SPI4_BASE_ADDRESS +#define HAL_LL_SPI4_BASE_ADDRESS SPI4_BASE_ADDRESS +#endif + +/*!< @brief SPI SCK pins. */ +static const hal_ll_spi_master_pin_map_t _spi_sck_map[] = +{ + #ifdef SPI1_SCK_PA5_AF5 + {PA5, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI1_SCK_PB3_AF5 + {PB3, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI1_SCK_PG2_AF5 + {PG2, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI2_SCK_PB13_AF5 + {PB13, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI2_SCK_PF10_AF5 + {PF10, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI2_SCK_PF1_AF5 + {PF1, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI2_SCK_PF9_AF5 + {PF9, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI3_SCK_PB3_AF6 + {PB3, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 6}, + #endif + #ifdef SPI3_SCK_PC10_AF6 + {PC10, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 6}, + #endif + #ifdef SPI3_SCK_PG9_AF6 + {PG9, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 6}, + #endif + #ifdef SPI4_SCK_PE12_AF5 + {PE12, SPI4_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_4), 5}, + #endif + #ifdef SPI4_SCK_PE2_AF5 + {PE2, SPI4_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_4), 5}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} +}; + +/*!< @brief SPI MISO pins. */ +static const hal_ll_spi_master_pin_map_t _spi_miso_map[] = +{ + #ifdef SPI1_MISO_PA6_AF5 + {PA6, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI1_MISO_PB4_AF5 + {PB4, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI1_MISO_PG3_AF5 + {PG3, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI2_MISO_PA10_AF5 + {PA10, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI2_MISO_PB14_AF5 + {PB14, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI3_MISO_PB4_AF6 + {PB4, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 6}, + #endif + #ifdef SPI3_MISO_PC11_AF6 + {PC11, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 6}, + #endif + #ifdef SPI4_MISO_PE13_AF5 + {PE13, SPI4_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_4), 5}, + #endif + #ifdef SPI4_MISO_PE5_AF5 + {PE5, SPI4_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_4), 5}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} +}; + +/*!< @brief SPI MOSI pins. */ +static const hal_ll_spi_master_pin_map_t _spi_mosi_map[] = +{ + #ifdef SPI1_MOSI_PA7_AF5 + {PA7, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI1_MOSI_PB5_AF5 + {PB5, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI1_MOSI_PG4_AF5 + {PG4, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI2_MOSI_PA11_AF5 + {PA11, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI2_MOSI_PB15_AF5 + {PB15, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI3_MOSI_PB5_AF6 + {PB5, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 6}, + #endif + #ifdef SPI3_MOSI_PC12_AF6 + {PC12, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 6}, + #endif + #ifdef SPI4_MOSI_PE14_AF5 + {PE14, SPI4_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_4), 5}, + #endif + #ifdef SPI4_MOSI_PE6_AF5 + {PE6, SPI4_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_4), 5}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_SPI_MASTER_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/spi_master/hal_ll_spi_master_pin_map/implementations/doc_ds_87/hal_ll_spi_master_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/spi_master/hal_ll_spi_master_pin_map/implementations/doc_ds_87/hal_ll_spi_master_pin_map.h new file mode 100644 index 000000000..0532f49bd --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/spi_master/hal_ll_spi_master_pin_map/implementations/doc_ds_87/hal_ll_spi_master_pin_map.h @@ -0,0 +1,204 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_spi_master_pin_map.h + * @brief SPI HAL LOW LEVEL MASTER PIN MAP. + */ + +#ifndef _HAL_LL_SPI_MASTER_PIN_MAP_H_ +#define _HAL_LL_SPI_MASTER_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_spi_master_module_num(_module_num) (_module_num - 1) +#define hal_ll_spi_module_num(_module_num) hal_ll_spi_master_module_num(_module_num) + +/*!< @brief Pin function structure. */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + uint8_t module_index; + uint32_t af; +} hal_ll_spi_master_pin_map_t; + +#ifdef SPI_MODULE_1 +#define SPI1_BASE_ADDRESS (0x40013000UL) +#define SPI1_BASE_ADDR SPI1_BASE_ADDRESS +#define HAL_LL_SPI1_BASE_ADDR SPI1_BASE_ADDRESS +#define HAL_LL_SPI1_BASE_ADDRESS SPI1_BASE_ADDRESS +#endif +#ifdef SPI_MODULE_2 +#define SPI2_BASE_ADDRESS (0x40003800UL) +#define SPI2_BASE_ADDR SPI2_BASE_ADDRESS +#define HAL_LL_SPI2_BASE_ADDR SPI2_BASE_ADDRESS +#define HAL_LL_SPI2_BASE_ADDRESS SPI2_BASE_ADDRESS +#endif +#ifdef SPI_MODULE_3 +#define SPI3_BASE_ADDRESS (0x40003C00UL) +#define SPI3_BASE_ADDR SPI3_BASE_ADDRESS +#define HAL_LL_SPI3_BASE_ADDR SPI3_BASE_ADDRESS +#define HAL_LL_SPI3_BASE_ADDRESS SPI3_BASE_ADDRESS +#endif +#ifdef SPI_MODULE_4 +#define SPI4_BASE_ADDRESS (0x40013C00UL) +#define SPI4_BASE_ADDR SPI4_BASE_ADDRESS +#define HAL_LL_SPI4_BASE_ADDR SPI4_BASE_ADDRESS +#define HAL_LL_SPI4_BASE_ADDRESS SPI4_BASE_ADDRESS +#endif + +/*!< @brief SPI SCK pins. */ +static const hal_ll_spi_master_pin_map_t _spi_sck_map[] = +{ + #ifdef SPI1_SCK_PA5_AF5 + {PA5, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI1_SCK_PB3_AF5 + {PB3, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI1_SCK_PG2_AF5 + {PG2, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI2_SCK_PB13_AF5 + {PB13, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI2_SCK_PF10_AF5 + {PF10, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI2_SCK_PF1_AF5 + {PF1, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI2_SCK_PF9_AF5 + {PF9, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI3_SCK_PB3_AF6 + {PB3, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 6}, + #endif + #ifdef SPI3_SCK_PC10_AF6 + {PC10, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 6}, + #endif + #ifdef SPI3_SCK_PG9_AF6 + {PG9, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 6}, + #endif + #ifdef SPI4_SCK_PE12_AF5 + {PE12, SPI4_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_4), 5}, + #endif + #ifdef SPI4_SCK_PE2_AF5 + {PE2, SPI4_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_4), 5}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} +}; + +/*!< @brief SPI MISO pins. */ +static const hal_ll_spi_master_pin_map_t _spi_miso_map[] = +{ + #ifdef SPI1_MISO_PA6_AF5 + {PA6, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI1_MISO_PB4_AF5 + {PB4, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI1_MISO_PG3_AF5 + {PG3, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI2_MISO_PA10_AF5 + {PA10, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI2_MISO_PB14_AF5 + {PB14, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI3_MISO_PB4_AF6 + {PB4, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 6}, + #endif + #ifdef SPI3_MISO_PC11_AF6 + {PC11, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 6}, + #endif + #ifdef SPI4_MISO_PE13_AF5 + {PE13, SPI4_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_4), 5}, + #endif + #ifdef SPI4_MISO_PE5_AF5 + {PE5, SPI4_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_4), 5}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} +}; + +/*!< @brief SPI MOSI pins. */ +static const hal_ll_spi_master_pin_map_t _spi_mosi_map[] = +{ + #ifdef SPI1_MOSI_PA7_AF5 + {PA7, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI1_MOSI_PB5_AF5 + {PB5, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI1_MOSI_PG4_AF5 + {PG4, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI2_MOSI_PA11_AF5 + {PA11, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI2_MOSI_PB15_AF5 + {PB15, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI3_MOSI_PB5_AF6 + {PB5, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 6}, + #endif + #ifdef SPI3_MOSI_PC12_AF6 + {PC12, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 6}, + #endif + #ifdef SPI4_MOSI_PE14_AF5 + {PE14, SPI4_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_4), 5}, + #endif + #ifdef SPI4_MOSI_PE6_AF5 + {PE6, SPI4_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_4), 5}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_SPI_MASTER_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/spi_master/hal_ll_spi_master_pin_map/implementations/doc_ds_88/hal_ll_spi_master_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/spi_master/hal_ll_spi_master_pin_map/implementations/doc_ds_88/hal_ll_spi_master_pin_map.h new file mode 100644 index 000000000..fd3a0d8db --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/spi_master/hal_ll_spi_master_pin_map/implementations/doc_ds_88/hal_ll_spi_master_pin_map.h @@ -0,0 +1,168 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_spi_master_pin_map.h + * @brief SPI HAL LOW LEVEL MASTER PIN MAP. + */ + +#ifndef _HAL_LL_SPI_MASTER_PIN_MAP_H_ +#define _HAL_LL_SPI_MASTER_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_spi_master_module_num(_module_num) (_module_num - 1) +#define hal_ll_spi_module_num(_module_num) hal_ll_spi_master_module_num(_module_num) + +/*!< @brief Pin function structure. */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + uint8_t module_index; + uint32_t af; +} hal_ll_spi_master_pin_map_t; + +#ifdef SPI_MODULE_1 +#define SPI1_BASE_ADDRESS (0x40013000UL) +#define SPI1_BASE_ADDR SPI1_BASE_ADDRESS +#define HAL_LL_SPI1_BASE_ADDR SPI1_BASE_ADDRESS +#define HAL_LL_SPI1_BASE_ADDRESS SPI1_BASE_ADDRESS +#endif +#ifdef SPI_MODULE_2 +#define SPI2_BASE_ADDRESS (0x40003800UL) +#define SPI2_BASE_ADDR SPI2_BASE_ADDRESS +#define HAL_LL_SPI2_BASE_ADDR SPI2_BASE_ADDRESS +#define HAL_LL_SPI2_BASE_ADDRESS SPI2_BASE_ADDRESS +#endif +#ifdef SPI_MODULE_3 +#define SPI3_BASE_ADDRESS (0x40003C00UL) +#define SPI3_BASE_ADDR SPI3_BASE_ADDRESS +#define HAL_LL_SPI3_BASE_ADDR SPI3_BASE_ADDRESS +#define HAL_LL_SPI3_BASE_ADDRESS SPI3_BASE_ADDRESS +#endif + +/*!< @brief SPI SCK pins. */ +static const hal_ll_spi_master_pin_map_t _spi_sck_map[] = +{ + #ifdef SPI1_SCK_PA5_AF5 + {PA5, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI1_SCK_PB3_AF5 + {PB3, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI2_SCK_PF1_AF5 + {PF1, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI3_SCK_PB3_AF6 + {PB3, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 6}, + #endif + #ifdef SPI2_SCK_PB13_AF5 + {PB13, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI3_SCK_PC10_AF6 + {PC10, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 6}, + #endif + #ifdef SPI2_SCK_PF10_AF5 + {PF10, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI2_SCK_PF9_AF5 + {PF9, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} +}; + +/*!< @brief SPI MISO pins. */ +static const hal_ll_spi_master_pin_map_t _spi_miso_map[] = +{ + #ifdef SPI1_MISO_PA6_AF5 + {PA6, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI1_MISO_PB4_AF5 + {PB4, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI2_MISO_PA10_AF5 + {PA10, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI3_MISO_PB4_AF6 + {PB4, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 6}, + #endif + #ifdef SPI2_MISO_PB14_AF5 + {PB14, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI3_MISO_PC11_AF6 + {PC11, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 6}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} +}; + +/*!< @brief SPI MOSI pins. */ +static const hal_ll_spi_master_pin_map_t _spi_mosi_map[] = +{ + #ifdef SPI1_MOSI_PA7_AF5 + {PA7, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI1_MOSI_PB5_AF5 + {PB5, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI2_MOSI_PA11_AF5 + {PA11, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI3_MOSI_PB5_AF6 + {PB5, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 6}, + #endif + #ifdef SPI2_MOSI_PB15_AF5 + {PB15, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI3_MOSI_PC12_AF6 + {PC12, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 6}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_SPI_MASTER_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/spi_master/hal_ll_spi_master_pin_map/implementations/doc_ds_89/hal_ll_spi_master_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/spi_master/hal_ll_spi_master_pin_map/implementations/doc_ds_89/hal_ll_spi_master_pin_map.h new file mode 100644 index 000000000..1d440f1dc --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/spi_master/hal_ll_spi_master_pin_map/implementations/doc_ds_89/hal_ll_spi_master_pin_map.h @@ -0,0 +1,168 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_spi_master_pin_map.h + * @brief SPI HAL LOW LEVEL MASTER PIN MAP. + */ + +#ifndef _HAL_LL_SPI_MASTER_PIN_MAP_H_ +#define _HAL_LL_SPI_MASTER_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_spi_master_module_num(_module_num) (_module_num - 1) +#define hal_ll_spi_module_num(_module_num) hal_ll_spi_master_module_num(_module_num) + +/*!< @brief Pin function structure. */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + uint8_t module_index; + uint32_t af; +} hal_ll_spi_master_pin_map_t; + +#ifdef SPI_MODULE_1 +#define SPI1_BASE_ADDRESS (0x40013000UL) +#define SPI1_BASE_ADDR SPI1_BASE_ADDRESS +#define HAL_LL_SPI1_BASE_ADDR SPI1_BASE_ADDRESS +#define HAL_LL_SPI1_BASE_ADDRESS SPI1_BASE_ADDRESS +#endif +#ifdef SPI_MODULE_2 +#define SPI2_BASE_ADDRESS (0x40003800UL) +#define SPI2_BASE_ADDR SPI2_BASE_ADDRESS +#define HAL_LL_SPI2_BASE_ADDR SPI2_BASE_ADDRESS +#define HAL_LL_SPI2_BASE_ADDRESS SPI2_BASE_ADDRESS +#endif +#ifdef SPI_MODULE_3 +#define SPI3_BASE_ADDRESS (0x40003C00UL) +#define SPI3_BASE_ADDR SPI3_BASE_ADDRESS +#define HAL_LL_SPI3_BASE_ADDR SPI3_BASE_ADDRESS +#define HAL_LL_SPI3_BASE_ADDRESS SPI3_BASE_ADDRESS +#endif + +/*!< @brief SPI SCK pins. */ +static const hal_ll_spi_master_pin_map_t _spi_sck_map[] = +{ + #ifdef SPI1_SCK_PA5_AF5 + {PA5, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI1_SCK_PB3_AF5 + {PB3, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI2_SCK_PB13_AF5 + {PB13, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI2_SCK_PF1_AF5 + {PF1, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI3_SCK_PB3_AF6 + {PB3, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 6}, + #endif + #ifdef SPI3_SCK_PC10_AF6 + {PC10, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 6}, + #endif + #ifdef SPI2_SCK_PF10_AF5 + {PF10, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI2_SCK_PF9_AF5 + {PF9, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} +}; + +/*!< @brief SPI MISO pins. */ +static const hal_ll_spi_master_pin_map_t _spi_miso_map[] = +{ + #ifdef SPI1_MISO_PA6_AF5 + {PA6, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI1_MISO_PB4_AF5 + {PB4, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI2_MISO_PA10_AF5 + {PA10, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI2_MISO_PB14_AF5 + {PB14, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI3_MISO_PB4_AF6 + {PB4, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 6}, + #endif + #ifdef SPI3_MISO_PC11_AF6 + {PC11, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 6}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} +}; + +/*!< @brief SPI MOSI pins. */ +static const hal_ll_spi_master_pin_map_t _spi_mosi_map[] = +{ + #ifdef SPI1_MOSI_PA7_AF5 + {PA7, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI1_MOSI_PB5_AF5 + {PB5, SPI1_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_1), 5}, + #endif + #ifdef SPI2_MOSI_PA11_AF5 + {PA11, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI2_MOSI_PB15_AF5 + {PB15, SPI2_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_2), 5}, + #endif + #ifdef SPI3_MOSI_PB5_AF6 + {PB5, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 6}, + #endif + #ifdef SPI3_MOSI_PC12_AF6 + {PC12, SPI3_BASE_ADDRESS, hal_ll_spi_module_num(SPI_MODULE_3), 6}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_SPI_MASTER_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/tim/hal_ll_tim.h b/targets/arm/mikroe/ai_generated/stm32/include/tim/hal_ll_tim.h new file mode 100644 index 000000000..a5b601151 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/tim/hal_ll_tim.h @@ -0,0 +1,253 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_tim.h + * @brief Brief file description. + */ + +#ifndef _HAL_LL_TIM_H_ +#define _HAL_LL_TIM_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_target.h" + +/** + * TIM modules + */ +typedef enum +{ + HAL_LL_TIM_MODULE_DEFAULT = 0xFF, + #if defined(TIM_MODULE_1) + HAL_LL_TIM_MODULE_1 = 1, + #endif + #if defined(TIM_MODULE_2) + HAL_LL_TIM_MODULE_2 = 2, + #endif + #if defined(TIM_MODULE_3) + HAL_LL_TIM_MODULE_3 = 3, + #endif + #if defined(TIM_MODULE_4) + HAL_LL_TIM_MODULE_4 = 4, + #endif + #if defined(TIM_MODULE_5) + HAL_LL_TIM_MODULE_5 = 5, + #endif + #if defined(TIM_MODULE_6) + HAL_LL_TIM_MODULE_6 = 6, + #endif + #if defined(TIM_MODULE_7) + HAL_LL_TIM_MODULE_7 = 7, + #endif + #if defined(TIM_MODULE_8) + HAL_LL_TIM_MODULE_8 = 8, + #endif + #if defined(TIM_MODULE_9) + HAL_LL_TIM_MODULE_9 = 9, + #endif + #if defined(TIM_MODULE_10) + HAL_LL_TIM_MODULE_10 = 10, + #endif + #if defined(TIM_MODULE_11) + HAL_LL_TIM_MODULE_11 = 11, + #endif + #if defined(TIM_MODULE_12) + HAL_LL_TIM_MODULE_12 = 12, + #endif + #if defined(TIM_MODULE_13) + HAL_LL_TIM_MODULE_13 = 13, + #endif + #if defined(TIM_MODULE_14) + HAL_LL_TIM_MODULE_14 = 14, + #endif + #if defined(TIM_MODULE_15) + HAL_LL_TIM_MODULE_15 = 15, + #endif + #if defined(TIM_MODULE_16) + HAL_LL_TIM_MODULE_16 = 16, + #endif + #if defined(TIM_MODULE_17) + HAL_LL_TIM_MODULE_17 = 17, + #endif + #if defined(TIM_MODULE_18) + HAL_LL_TIM_MODULE_18 = 18, + #endif + #if defined(TIM_MODULE_19) + HAL_LL_TIM_MODULE_19 = 19, + #endif + #if defined(TIM_MODULE_20) + HAL_LL_TIM_MODULE_20 = 20, + #endif + #if defined(TIM_MODULE_21) + HAL_LL_TIM_MODULE_21 = 21, + #endif + #if defined(TIM_MODULE_22) + HAL_LL_TIM_MODULE_22 = 22, + #endif + + HAL_LL_TIM_MODULE_NONE +} hal_ll_tim_module_number_t; + +typedef struct +{ + handle_t *hal_ll_tim_handle; + handle_t *hal_drv_tim_handle; + bool init_ll_state; +} hal_ll_tim_handle_register_t; + +/** + * @brief Registers handler for future use. + * + * Registers low level and hal level handlers + * for use with appropriate functions. + * + * @param pin TIM pin. + * @param handle_map HAL layer local handle map. + * @param hal_module_id HAL layer module number. + + * @return hal_ll_err_t Module specific error. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_tim_register_handle( hal_ll_pin_name_t pin, + hal_ll_tim_handle_register_t *handle_map, uint8_t *hal_module_id ); + +/** + * @brief Configures specified module. + * + * Performs module configuration on the hardware + * level. Enables module specific clock gate and + * sets adequate alternate function values. + * + * @param[in] *handle HAL context object handle. + * + * @return hal_ll_err_t Module specific error. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_module_configure_tim( handle_t *handle ); + +/** + * @brief Enables counter for TIM module. + * + * Initializes TIM module on hardware level, if not already initialized and + * starts TIM module. + * + * @param handle TIM handle. + * + * @return hal_ll_err_t Module specific error. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_tim_start( handle_t *handle ); + +/** + * @brief Stops counter for TIM module. + * + * The TIM Module needs to be initialized so that + * the stop can be done. + * + * @param handle TIM handle. + * + * @return hal_ll_err_t Module specific error. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_tim_stop( handle_t *handle ); + +/** + * @brief Set TIM frequency in Hertz. + * + * This function is used to set the TIM frequency, it + * stops TIM module and sets duty_cycle on 0. + * Take into consideration that the module + * will be re-initialized on the hardware level. + * + * @param handle TIM handle. + * @param freq_hz TIM frequency in hz. + * + * @return This function returns the frequency value in hz, + * to which the PWM module is set. + * + * @note If the frequency value is less than allowed, + * the frequency will be set to the lowest possible value for the specified TIM. + */ +uint32_t hal_ll_tim_set_freq( handle_t *handle, uint32_t freq_hz ); + +/** + * @brief Set TIM duty cycle in percentages. + * + * The user should enter the duty_ratio in percentages. + * The dut_ratio value should be between 0 and 1 + * (where 0 represents 0% and 1 represents 100%). + * + * @param handle TIM handle. + * @param duty_ratio TIM duty ratio in percentages. + * + * @return hal_ll_err_t Module specific error. + * + * @note Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_tim_set_duty( handle_t *handle, float duty_ratio ); + +/** + * @brief Closes TIM master HAL and HAL_LOW_LEVEL context object. + * + * De-allocates hardware resources for specific driver object and + * de-initializes the module on a hardware level. + * + * @param handle TIM handle. + * + * @return void None. + */ +void hal_ll_tim_close( handle_t *handle ); + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_TIM_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/tim/hal_ll_tim_pin_map/implementations/doc_ds_1/hal_ll_tim_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/tim/hal_ll_tim_pin_map/implementations/doc_ds_1/hal_ll_tim_pin_map.h new file mode 100644 index 000000000..952cf7fdb --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/tim/hal_ll_tim_pin_map/implementations/doc_ds_1/hal_ll_tim_pin_map.h @@ -0,0 +1,288 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_tim_pin_map.h + * @brief TIM HAL LOW LEVEL PIN MAP. + */ + +#ifndef _HAL_LL_TIM_PIN_MAP_H_ +#define _HAL_LL_TIM_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_tim_module_num(_module_num) (_module_num - 1) + +/*!< @brief Alternate pin function structure. */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + hal_ll_channel_t channel; + uint32_t af; + hal_ll_pin_name_t module_index; +} hal_ll_tim_pin_map_t; + +typedef enum +{ + HAL_LL_TIM_CHANNEL_0 = 0, + HAL_LL_TIM_CHANNEL_1, + HAL_LL_TIM_CHANNEL_2, + HAL_LL_TIM_CHANNEL_3, + HAL_LL_TIM_CHANNEL_4, + HAL_LL_TIM_CHANNEL_1N, + HAL_LL_TIM_CHANNEL_2N, + HAL_LL_TIM_CHANNEL_3N, + HAL_LL_TIM_CHANNEL_4N +} hal_ll_tim_channel_t; + +#ifdef TIM_MODULE_1 +#define TIM1_BASE_ADDRESS (0x40012C00UL) +#define TIM1_BASE_ADDR TIM1_BASE_ADDRESS +#define HAL_LL_TIM1_BASE_ADDR TIM1_BASE_ADDRESS +#define HAL_LL_TIM1_BASE_ADDRESS TIM1_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_3 +#define TIM3_BASE_ADDRESS (0x40000400UL) +#define TIM3_BASE_ADDR TIM3_BASE_ADDRESS +#define HAL_LL_TIM3_BASE_ADDR TIM3_BASE_ADDRESS +#define HAL_LL_TIM3_BASE_ADDRESS TIM3_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_14 +#define TIM14_BASE_ADDRESS (0x40002000UL) +#define TIM14_BASE_ADDR TIM14_BASE_ADDRESS +#define HAL_LL_TIM14_BASE_ADDR TIM14_BASE_ADDRESS +#define HAL_LL_TIM14_BASE_ADDRESS TIM14_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_16 +#define TIM16_BASE_ADDRESS (0x40014400UL) +#define TIM16_BASE_ADDR TIM16_BASE_ADDRESS +#define HAL_LL_TIM16_BASE_ADDR TIM16_BASE_ADDRESS +#define HAL_LL_TIM16_BASE_ADDRESS TIM16_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_17 +#define TIM17_BASE_ADDRESS (0x40014800UL) +#define TIM17_BASE_ADDR TIM17_BASE_ADDRESS +#define HAL_LL_TIM17_BASE_ADDR TIM17_BASE_ADDRESS +#define HAL_LL_TIM17_BASE_ADDRESS TIM17_BASE_ADDRESS +#endif + +/*!< @brief TIM pins. */ +static const hal_ll_tim_pin_map_t _tim_map[] = { + #ifdef TIM14_CH1_PA4_AF4 + {PA4, TIM14_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 4, hal_ll_tim_module_num(TIM_MODULE_14)}, + #endif + #ifdef TIM14_CH1_PA7_AF4 + {PA7, TIM14_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 4, hal_ll_tim_module_num(TIM_MODULE_14)}, + #endif + #ifdef TIM14_CH1_PA8_AF13 + {PA8, TIM14_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 13, hal_ll_tim_module_num(TIM_MODULE_14)}, + #endif + #ifdef TIM16_BKIN_PB6_AF14 + // {PB6, TIM16_BASE_ADDRESS, 0, 14, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1N_PA2_AF2 + {PA2, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 2, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1N_PB6_AF2 + {PB6, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 2, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1_PA0_AF2 + {PA0, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1_PA6_AF5 + {PA6, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 5, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1_PB7_AF10 + {PB7, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 10, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM17_BKIN_PA10_AF5 + // {PA10, TIM17_BASE_ADDRESS, 0, 5, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_BKIN_PB6_AF15 + // {PB6, TIM17_BASE_ADDRESS, 0, 15, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_CH1N_PA4_AF5 + {PA4, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 5, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_CH1N_PB7_AF2 + {PB7, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 2, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_CH1_PA1_AF2 + {PA1, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_CH1_PA7_AF5 + {PA7, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 5, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_CH1_PC14_AF10 + {PC14, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 10, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM1_BKIN2_PA11_AF5 + // {PA11, TIM1_BASE_ADDRESS, 0, 5, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN2_PC14_AF2 + // {PC14, TIM1_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN_PA6_AF2 + // {PA6, TIM1_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1N_PA3_AF2 + {PA3, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1N_PA7_AF2 + {PA7, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1_PA0_AF5 + {PA0, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 5, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1_PA14_AF10 + {PA14, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 10, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1_PA5_AF5 + {PA5, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 5, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1_PA8_AF2 + {PA8, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2N_PA4_AF2 + {PA4, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2N_PA8_AF9 + {PA8, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 9, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2_PA1_AF5 + {PA1, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 5, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2_PA9_AF2 + {PA9, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2_PB6_AF11 + {PB6, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 11, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3N_PA5_AF2 + {PA5, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3N_PA8_AF10 + {PA8, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 10, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3_PA10_AF2 + {PA10, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3_PA2_AF5 + {PA2, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 5, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3_PB6_AF1 + {PB6, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 1, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH4_PA11_AF2 + {PA11, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH4_PA3_AF5 + {PA3, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 5, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH4_PB7_AF1 + {PB7, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 1, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH4_PF2_AF1 + {PF2, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 1, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_ETR_PA12_AF2 + // {PA12, TIM1_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_ETR_PC14_AF1 + // {PC14, TIM1_BASE_ADDRESS, 0, 1, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_ETR_PC15_AF2 + // {PC15, TIM1_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM3_CH1_PA6_AF1 + {PA6, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH1_PB6_AF12 + {PB6, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 12, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH1_PB7_AF11 + {PB7, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 11, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH2_PA7_AF1 + {PA7, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 1, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH2_PB6_AF13 + {PB6, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 13, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH2_PC14_AF11 + {PC14, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 11, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH3_PA8_AF11 + {PA8, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 11, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH3_PB6_AF3 + {PB6, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 3, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH3_PC15_AF3 + {PC15, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 3, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH4_PA8_AF12 + {PA8, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 12, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH4_PB7_AF3 + {PB7, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 3, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_ETR_PA13_AF3 + // {PA13, TIM3_BASE_ADDRESS, 0, 3, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_ETR_PA2_AF3 + // {PA2, TIM3_BASE_ADDRESS, 0, 3, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_ETR_PA9_AF3 + // {PA9, TIM3_BASE_ADDRESS, 0, 3, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + { HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_CHANNEL_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC } +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_TIM_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/tim/hal_ll_tim_pin_map/implementations/doc_ds_160/hal_ll_tim_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/tim/hal_ll_tim_pin_map/implementations/doc_ds_160/hal_ll_tim_pin_map.h new file mode 100644 index 000000000..c9e32d792 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/tim/hal_ll_tim_pin_map/implementations/doc_ds_160/hal_ll_tim_pin_map.h @@ -0,0 +1,528 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_tim_pin_map.h + * @brief TIM HAL LOW LEVEL PIN MAP. + */ + +#ifndef _HAL_LL_TIM_PIN_MAP_H_ +#define _HAL_LL_TIM_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_tim_module_num(_module_num) (_module_num - 1) + +/*!< @brief Alternate pin function structure. */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + hal_ll_channel_t channel; + uint32_t af; + hal_ll_pin_name_t module_index; +} hal_ll_tim_pin_map_t; + +typedef enum +{ + HAL_LL_TIM_CHANNEL_0 = 0, + HAL_LL_TIM_CHANNEL_1, + HAL_LL_TIM_CHANNEL_2, + HAL_LL_TIM_CHANNEL_3, + HAL_LL_TIM_CHANNEL_4, + HAL_LL_TIM_CHANNEL_1N, + HAL_LL_TIM_CHANNEL_2N, + HAL_LL_TIM_CHANNEL_3N, + HAL_LL_TIM_CHANNEL_4N +} hal_ll_tim_channel_t; + +#ifdef TIM_MODULE_1 +#define TIM1_BASE_ADDRESS (0x40012C00UL) +#define TIM1_BASE_ADDR TIM1_BASE_ADDRESS +#define HAL_LL_TIM1_BASE_ADDR TIM1_BASE_ADDRESS +#define HAL_LL_TIM1_BASE_ADDRESS TIM1_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_2 +#define TIM2_BASE_ADDRESS (0x40000000UL) +#define TIM2_BASE_ADDR TIM2_BASE_ADDRESS +#define HAL_LL_TIM2_BASE_ADDR TIM2_BASE_ADDRESS +#define HAL_LL_TIM2_BASE_ADDRESS TIM2_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_3 +#define TIM3_BASE_ADDRESS (0x40000400UL) +#define TIM3_BASE_ADDR TIM3_BASE_ADDRESS +#define HAL_LL_TIM3_BASE_ADDR TIM3_BASE_ADDRESS +#define HAL_LL_TIM3_BASE_ADDRESS TIM3_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_4 +#define TIM4_BASE_ADDRESS (0x40000800UL) +#define TIM4_BASE_ADDR TIM4_BASE_ADDRESS +#define HAL_LL_TIM4_BASE_ADDR TIM4_BASE_ADDRESS +#define HAL_LL_TIM4_BASE_ADDRESS TIM4_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_5 +#define TIM5_BASE_ADDRESS (0x40000C00UL) +#define TIM5_BASE_ADDR TIM5_BASE_ADDRESS +#define HAL_LL_TIM5_BASE_ADDR TIM5_BASE_ADDRESS +#define HAL_LL_TIM5_BASE_ADDRESS TIM5_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_8 +#define TIM8_BASE_ADDRESS (0x40013400UL) +#define TIM8_BASE_ADDR TIM8_BASE_ADDRESS +#define HAL_LL_TIM8_BASE_ADDR TIM8_BASE_ADDRESS +#define HAL_LL_TIM8_BASE_ADDRESS TIM8_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_15 +#define TIM15_BASE_ADDRESS (0x40014000UL) +#define TIM15_BASE_ADDR TIM15_BASE_ADDRESS +#define HAL_LL_TIM15_BASE_ADDR TIM15_BASE_ADDRESS +#define HAL_LL_TIM15_BASE_ADDRESS TIM15_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_16 +#define TIM16_BASE_ADDRESS (0x40014400UL) +#define TIM16_BASE_ADDR TIM16_BASE_ADDRESS +#define HAL_LL_TIM16_BASE_ADDR TIM16_BASE_ADDRESS +#define HAL_LL_TIM16_BASE_ADDRESS TIM16_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_17 +#define TIM17_BASE_ADDRESS (0x40014800UL) +#define TIM17_BASE_ADDR TIM17_BASE_ADDRESS +#define HAL_LL_TIM17_BASE_ADDR TIM17_BASE_ADDRESS +#define HAL_LL_TIM17_BASE_ADDRESS TIM17_BASE_ADDRESS +#endif + +/*!< @brief TIM pins. */ +static const hal_ll_tim_pin_map_t _tim_map[] = { + #ifdef LPTIM1_ETR_PB6_AF1 + // {PB6, LPTIM1_BASE_ADDRESS, 0, 1, hal_ll_lptim_module_num(LPTIM_MODULE_1)}, + #endif + #ifdef LPTIM1_ETR_PC3_AF1 + // {PC3, LPTIM1_BASE_ADDRESS, 0, 1, hal_ll_lptim_module_num(LPTIM_MODULE_1)}, + #endif + #ifdef LPTIM1_ETR_PG12_AF1 + // {PG12, LPTIM1_BASE_ADDRESS, 0, 1, hal_ll_lptim_module_num(LPTIM_MODULE_1)}, + #endif + #ifdef LPTIM2_ETR_PA5_AF14 + // {PA5, LPTIM2_BASE_ADDRESS, 0, 14, hal_ll_lptim_module_num(LPTIM_MODULE_2)}, + #endif + #ifdef LPTIM2_ETR_PC3_AF14 + // {PC3, LPTIM2_BASE_ADDRESS, 0, 14, hal_ll_lptim_module_num(LPTIM_MODULE_2)}, + #endif + #ifdef LPTIM2_ETR_PD11_AF14 + // {PD11, LPTIM2_BASE_ADDRESS, 0, 14, hal_ll_lptim_module_num(LPTIM_MODULE_2)}, + #endif + #ifdef TIM15_BKIN_PA9_AF14 + // {PA9, TIM15_BASE_ADDRESS, 0, 14, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_BKIN_PB12_AF14 + // {PB12, TIM15_BASE_ADDRESS, 0, 14, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH1N_PA1_AF14 + {PA1, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 14, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH1N_PB13_AF14 + {PB13, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 14, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH1N_PG9_AF14 + {PG9, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 14, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH1_PA2_AF14 + {PA2, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 14, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH1_PB14_AF14 + {PB14, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 14, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH1_PF9_AF14 + {PF9, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 14, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH1_PG10_AF14 + {PG10, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 14, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH2_PA3_AF14 + {PA3, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 14, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH2_PB15_AF14 + {PB15, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 14, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH2_PF10_AF14 + {PF10, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 14, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH2_PG11_AF14 + {PG11, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 14, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM16_BKIN_PB5_AF14 + // {PB5, TIM16_BASE_ADDRESS, 0, 14, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1N_PB6_AF14 + {PB6, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 14, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1_PA6_AF14 + {PA6, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 14, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1_PB8_AF14 + {PB8, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 14, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1_PE0_AF14 + {PE0, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 14, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM17_BKIN_PA10_AF14 + // {PA10, TIM17_BASE_ADDRESS, 0, 14, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_BKIN_PB4_AF14 + // {PB4, TIM17_BASE_ADDRESS, 0, 14, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_CH1N_PB7_AF14 + {PB7, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 14, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_CH1_PA7_AF14 + {PA7, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 14, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_CH1_PB9_AF14 + {PB9, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 14, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_CH1_PE1_AF14 + {PE1, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 14, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM1_BKIN2_PA11_AF12 + // {PA11, TIM1_BASE_ADDRESS, 0, 12, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN2_PE14_AF3 + // {PE14, TIM1_BASE_ADDRESS, 0, 3, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN_PA6_AF12 + // {PA6, TIM1_BASE_ADDRESS, 0, 12, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN_PB12_AF3 + // {PB12, TIM1_BASE_ADDRESS, 0, 3, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN_PE15_AF3 + // {PE15, TIM1_BASE_ADDRESS, 0, 3, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1N_PA7_AF1 + {PA7, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 1, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1N_PB13_AF1 + {PB13, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 1, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1N_PE8_AF1 + {PE8, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 1, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1_PA8_AF1 + {PA8, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1_PE9_AF1 + {PE9, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2N_PB0_AF1 + {PB0, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 1, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2N_PB14_AF1 + {PB14, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 1, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2N_PE10_AF1 + {PE10, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 1, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2_PA9_AF1 + {PA9, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 1, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2_PE11_AF1 + {PE11, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 1, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3N_PB15_AF1 + {PB15, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 1, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3N_PB1_AF1 + {PB1, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 1, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3N_PE12_AF1 + {PE12, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 1, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3_PA10_AF1 + {PA10, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 1, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3_PE13_AF1 + {PE13, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 1, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH4_PA11_AF1 + {PA11, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 1, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH4_PE14_AF1 + {PE14, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 1, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_ETR_PA12_AF1 + // {PA12, TIM1_BASE_ADDRESS, 0, 1, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_ETR_PE7_AF1 + // {PE7, TIM1_BASE_ADDRESS, 0, 1, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM2_CH1_PA0_AF1 + {PA0, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH1_PA15_AF1 + {PA15, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH1_PA5_AF1 + {PA5, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH2_PA1_AF1 + {PA1, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH2_PB3_AF1 + {PB3, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH3_PA2_AF1 + {PA2, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH3_PB10_AF1 + {PB10, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH4_PA3_AF1 + {PA3, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH4_PB11_AF1 + {PB11, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_ETR_PA0_AF14 + // {PA0, TIM2_BASE_ADDRESS, 0, 14, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_ETR_PA15_AF2 + // {PA15, TIM2_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_ETR_PA5_AF2 + // {PA5, TIM2_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM3_CH1_PA6_AF2 + {PA6, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH1_PB4_AF2 + {PB4, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH1_PC6_AF2 + {PC6, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH1_PE3_AF2 + {PE3, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH2_PA7_AF2 + {PA7, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH2_PB5_AF2 + {PB5, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH2_PC7_AF2 + {PC7, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH2_PE4_AF2 + {PE4, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH3_PB0_AF2 + {PB0, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH3_PC8_AF2 + {PC8, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH3_PE5_AF2 + {PE5, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH4_PB1_AF2 + {PB1, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH4_PC9_AF2 + {PC9, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH4_PE6_AF2 + {PE6, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_ETR_PD2_AF2 + // {PD2, TIM3_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_ETR_PE2_AF2 + // {PE2, TIM3_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM4_CH1_PB6_AF2 + {PB6, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH1_PD12_AF2 + {PD12, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH2_PB7_AF2 + {PB7, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH2_PD13_AF2 + {PD13, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH3_PB8_AF2 + {PB8, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH3_PD14_AF2 + {PD14, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH4_PB9_AF2 + {PB9, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH4_PD15_AF2 + {PD15, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_ETR_PE0_AF2 + // {PE0, TIM4_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM5_CH1_PA0_AF2 + {PA0, TIM5_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_CH1_PF6_AF2 + {PF6, TIM5_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_CH2_PA1_AF2 + {PA1, TIM5_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_CH2_PF7_AF2 + {PF7, TIM5_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_CH3_PA2_AF2 + {PA2, TIM5_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_CH3_PF8_AF2 + {PF8, TIM5_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_CH4_PA3_AF2 + {PA3, TIM5_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_CH4_PF9_AF2 + {PF9, TIM5_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_ETR_PF6_AF1 + // {PF6, TIM5_BASE_ADDRESS, 0, 1, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM8_BKIN2_PB6_AF12 + // {PB6, TIM8_BASE_ADDRESS, 0, 12, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_BKIN2_PC9_AF14 + // {PC9, TIM8_BASE_ADDRESS, 0, 14, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_BKIN_PA6_AF13 + // {PA6, TIM8_BASE_ADDRESS, 0, 13, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_BKIN_PB7_AF13 + // {PB7, TIM8_BASE_ADDRESS, 0, 13, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH1N_PA5_AF3 + {PA5, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 3, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH1N_PA7_AF3 + {PA7, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 3, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH1_PC6_AF3 + {PC6, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 3, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH2N_PB0_AF3 + {PB0, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 3, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH2N_PB14_AF3 + {PB14, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 3, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH2_PC7_AF3 + {PC7, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 3, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH3N_PB15_AF3 + {PB15, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 3, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH3N_PB1_AF3 + {PB1, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 3, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH3_PC8_AF3 + {PC8, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 3, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH4_PC9_AF3 + {PC9, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 3, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_ETR_PA0_AF3 + // {PA0, TIM8_BASE_ADDRESS, 0, 3, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM5_CH1_PH10_AF2 + {PH10, TIM5_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_CH2_PH11_AF2 + {PH11, TIM5_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_CH3_PH12_AF2 + {PH12, TIM5_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_CH4_PI0_AF2 + {PI0, TIM5_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM8_BKIN_PI4_AF3 + // {PI4, TIM8_BASE_ADDRESS, 0, 3, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH1N_PH13_AF3 + {PH13, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 3, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH1_PI5_AF3 + {PI5, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 3, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH2N_PH14_AF3 + {PH14, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 3, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH2_PI6_AF3 + {PI6, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 3, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH3N_PH15_AF3 + {PH15, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 3, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH3_PI7_AF3 + {PI7, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 3, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH4_PI2_AF3 + {PI2, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 3, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_ETR_PI3_AF3 + // {PI3, TIM8_BASE_ADDRESS, 0, 3, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + { HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_CHANNEL_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC } +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_TIM_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/tim/hal_ll_tim_pin_map/implementations/doc_ds_161/hal_ll_tim_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/tim/hal_ll_tim_pin_map/implementations/doc_ds_161/hal_ll_tim_pin_map.h new file mode 100644 index 000000000..c755c027e --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/tim/hal_ll_tim_pin_map/implementations/doc_ds_161/hal_ll_tim_pin_map.h @@ -0,0 +1,528 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_tim_pin_map.h + * @brief TIM HAL LOW LEVEL PIN MAP. + */ + +#ifndef _HAL_LL_TIM_PIN_MAP_H_ +#define _HAL_LL_TIM_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_tim_module_num(_module_num) (_module_num - 1) + +/*!< @brief Alternate pin function structure. */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + hal_ll_channel_t channel; + uint32_t af; + hal_ll_pin_name_t module_index; +} hal_ll_tim_pin_map_t; + +typedef enum +{ + HAL_LL_TIM_CHANNEL_0 = 0, + HAL_LL_TIM_CHANNEL_1, + HAL_LL_TIM_CHANNEL_2, + HAL_LL_TIM_CHANNEL_3, + HAL_LL_TIM_CHANNEL_4, + HAL_LL_TIM_CHANNEL_1N, + HAL_LL_TIM_CHANNEL_2N, + HAL_LL_TIM_CHANNEL_3N, + HAL_LL_TIM_CHANNEL_4N +} hal_ll_tim_channel_t; + +#ifdef TIM_MODULE_1 +#define TIM1_BASE_ADDRESS (0x40012C00UL) +#define TIM1_BASE_ADDR TIM1_BASE_ADDRESS +#define HAL_LL_TIM1_BASE_ADDR TIM1_BASE_ADDRESS +#define HAL_LL_TIM1_BASE_ADDRESS TIM1_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_2 +#define TIM2_BASE_ADDRESS (0x40000000UL) +#define TIM2_BASE_ADDR TIM2_BASE_ADDRESS +#define HAL_LL_TIM2_BASE_ADDR TIM2_BASE_ADDRESS +#define HAL_LL_TIM2_BASE_ADDRESS TIM2_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_3 +#define TIM3_BASE_ADDRESS (0x40000400UL) +#define TIM3_BASE_ADDR TIM3_BASE_ADDRESS +#define HAL_LL_TIM3_BASE_ADDR TIM3_BASE_ADDRESS +#define HAL_LL_TIM3_BASE_ADDRESS TIM3_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_4 +#define TIM4_BASE_ADDRESS (0x40000800UL) +#define TIM4_BASE_ADDR TIM4_BASE_ADDRESS +#define HAL_LL_TIM4_BASE_ADDR TIM4_BASE_ADDRESS +#define HAL_LL_TIM4_BASE_ADDRESS TIM4_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_5 +#define TIM5_BASE_ADDRESS (0x40000C00UL) +#define TIM5_BASE_ADDR TIM5_BASE_ADDRESS +#define HAL_LL_TIM5_BASE_ADDR TIM5_BASE_ADDRESS +#define HAL_LL_TIM5_BASE_ADDRESS TIM5_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_8 +#define TIM8_BASE_ADDRESS (0x40013400UL) +#define TIM8_BASE_ADDR TIM8_BASE_ADDRESS +#define HAL_LL_TIM8_BASE_ADDR TIM8_BASE_ADDRESS +#define HAL_LL_TIM8_BASE_ADDRESS TIM8_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_15 +#define TIM15_BASE_ADDRESS (0x40014000UL) +#define TIM15_BASE_ADDR TIM15_BASE_ADDRESS +#define HAL_LL_TIM15_BASE_ADDR TIM15_BASE_ADDRESS +#define HAL_LL_TIM15_BASE_ADDRESS TIM15_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_16 +#define TIM16_BASE_ADDRESS (0x40014400UL) +#define TIM16_BASE_ADDR TIM16_BASE_ADDRESS +#define HAL_LL_TIM16_BASE_ADDR TIM16_BASE_ADDRESS +#define HAL_LL_TIM16_BASE_ADDRESS TIM16_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_17 +#define TIM17_BASE_ADDRESS (0x40014800UL) +#define TIM17_BASE_ADDR TIM17_BASE_ADDRESS +#define HAL_LL_TIM17_BASE_ADDR TIM17_BASE_ADDRESS +#define HAL_LL_TIM17_BASE_ADDRESS TIM17_BASE_ADDRESS +#endif + +/*!< @brief TIM pins. */ +static const hal_ll_tim_pin_map_t _tim_map[] = { + #ifdef LPTIM1_ETR_PB6_AF1 + // {PB6, LPTIM1_BASE_ADDRESS, 0, 1, hal_ll_lptim_module_num(LPTIM_MODULE_1)}, + #endif + #ifdef LPTIM1_ETR_PC3_AF1 + // {PC3, LPTIM1_BASE_ADDRESS, 0, 1, hal_ll_lptim_module_num(LPTIM_MODULE_1)}, + #endif + #ifdef LPTIM1_ETR_PG12_AF1 + // {PG12, LPTIM1_BASE_ADDRESS, 0, 1, hal_ll_lptim_module_num(LPTIM_MODULE_1)}, + #endif + #ifdef LPTIM2_ETR_PA5_AF14 + // {PA5, LPTIM2_BASE_ADDRESS, 0, 14, hal_ll_lptim_module_num(LPTIM_MODULE_2)}, + #endif + #ifdef LPTIM2_ETR_PC3_AF14 + // {PC3, LPTIM2_BASE_ADDRESS, 0, 14, hal_ll_lptim_module_num(LPTIM_MODULE_2)}, + #endif + #ifdef LPTIM2_ETR_PD11_AF14 + // {PD11, LPTIM2_BASE_ADDRESS, 0, 14, hal_ll_lptim_module_num(LPTIM_MODULE_2)}, + #endif + #ifdef TIM15_BKIN_PA9_AF14 + // {PA9, TIM15_BASE_ADDRESS, 0, 14, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_BKIN_PB12_AF14 + // {PB12, TIM15_BASE_ADDRESS, 0, 14, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH1N_PA1_AF14 + {PA1, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 14, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH1N_PB13_AF14 + {PB13, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 14, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH1N_PG9_AF14 + {PG9, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 14, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH1_PA2_AF14 + {PA2, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 14, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH1_PB14_AF14 + {PB14, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 14, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH1_PG10_AF14 + {PG10, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 14, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH2_PA3_AF14 + {PA3, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 14, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH2_PB15_AF14 + {PB15, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 14, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH2_PG11_AF14 + {PG11, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 14, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM16_BKIN_PB5_AF14 + // {PB5, TIM16_BASE_ADDRESS, 0, 14, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1N_PB6_AF14 + {PB6, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 14, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1_PA6_AF14 + {PA6, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 14, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1_PB8_AF14 + {PB8, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 14, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1_PE0_AF14 + {PE0, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 14, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM17_BKIN_PA10_AF14 + // {PA10, TIM17_BASE_ADDRESS, 0, 14, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_BKIN_PB4_AF14 + // {PB4, TIM17_BASE_ADDRESS, 0, 14, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_CH1N_PB7_AF14 + {PB7, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 14, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_CH1_PA7_AF14 + {PA7, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 14, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_CH1_PB9_AF14 + {PB9, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 14, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_CH1_PE1_AF14 + {PE1, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 14, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM1_BKIN2_PA11_AF12 + // {PA11, TIM1_BASE_ADDRESS, 0, 12, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN2_PE14_AF3 + // {PE14, TIM1_BASE_ADDRESS, 0, 3, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN_PA6_AF12 + // {PA6, TIM1_BASE_ADDRESS, 0, 12, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN_PB12_AF3 + // {PB12, TIM1_BASE_ADDRESS, 0, 3, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN_PE15_AF3 + // {PE15, TIM1_BASE_ADDRESS, 0, 3, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1N_PA7_AF1 + {PA7, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 1, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1N_PB13_AF1 + {PB13, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 1, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1N_PE8_AF1 + {PE8, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 1, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1_PA8_AF1 + {PA8, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1_PE9_AF1 + {PE9, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2N_PB0_AF1 + {PB0, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 1, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2N_PB14_AF1 + {PB14, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 1, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2N_PE10_AF1 + {PE10, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 1, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2_PA9_AF1 + {PA9, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 1, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2_PE11_AF1 + {PE11, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 1, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3N_PB15_AF1 + {PB15, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 1, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3N_PB1_AF1 + {PB1, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 1, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3N_PE12_AF1 + {PE12, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 1, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3_PA10_AF1 + {PA10, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 1, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3_PE13_AF1 + {PE13, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 1, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH4_PA11_AF1 + {PA11, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 1, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH4_PE14_AF1 + {PE14, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 1, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_ETR_PA12_AF1 + // {PA12, TIM1_BASE_ADDRESS, 0, 1, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_ETR_PE7_AF1 + // {PE7, TIM1_BASE_ADDRESS, 0, 1, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM2_CH1_PA0_AF1 + {PA0, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH1_PA15_AF1 + {PA15, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH1_PA5_AF1 + {PA5, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH2_PA1_AF1 + {PA1, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH2_PB3_AF1 + {PB3, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH3_PA2_AF1 + {PA2, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH3_PB10_AF1 + {PB10, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH4_PA3_AF1 + {PA3, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH4_PB11_AF1 + {PB11, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_ETR_PA0_AF14 + // {PA0, TIM2_BASE_ADDRESS, 0, 14, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_ETR_PA15_AF2 + // {PA15, TIM2_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_ETR_PA5_AF2 + // {PA5, TIM2_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM3_CH1_PA6_AF2 + {PA6, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH1_PB4_AF2 + {PB4, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH1_PC6_AF2 + {PC6, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH1_PE3_AF2 + {PE3, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH2_PA7_AF2 + {PA7, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH2_PB5_AF2 + {PB5, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH2_PC7_AF2 + {PC7, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH2_PE4_AF2 + {PE4, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH3_PB0_AF2 + {PB0, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH3_PC8_AF2 + {PC8, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH3_PE5_AF2 + {PE5, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH4_PB1_AF2 + {PB1, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH4_PC9_AF2 + {PC9, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH4_PE6_AF2 + {PE6, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_ETR_PD2_AF2 + // {PD2, TIM3_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_ETR_PE2_AF2 + // {PE2, TIM3_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM4_CH1_PB6_AF2 + {PB6, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH1_PD12_AF2 + {PD12, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH2_PB7_AF2 + {PB7, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH2_PD13_AF2 + {PD13, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH3_PB8_AF2 + {PB8, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH3_PD14_AF2 + {PD14, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH4_PB9_AF2 + {PB9, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH4_PD15_AF2 + {PD15, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_ETR_PE0_AF2 + // {PE0, TIM4_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM5_CH1_PA0_AF2 + {PA0, TIM5_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_CH2_PA1_AF2 + {PA1, TIM5_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_CH3_PA2_AF2 + {PA2, TIM5_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_CH4_PA3_AF2 + {PA3, TIM5_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM8_BKIN2_PB6_AF12 + // {PB6, TIM8_BASE_ADDRESS, 0, 12, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_BKIN2_PC9_AF14 + // {PC9, TIM8_BASE_ADDRESS, 0, 14, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_BKIN_PA6_AF13 + // {PA6, TIM8_BASE_ADDRESS, 0, 13, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_BKIN_PB7_AF13 + // {PB7, TIM8_BASE_ADDRESS, 0, 13, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH1N_PA5_AF3 + {PA5, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 3, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH1N_PA7_AF3 + {PA7, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 3, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH1_PC6_AF3 + {PC6, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 3, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH2N_PB0_AF3 + {PB0, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 3, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH2N_PB14_AF3 + {PB14, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 3, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH2_PC7_AF3 + {PC7, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 3, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH3N_PB15_AF3 + {PB15, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 3, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH3N_PB1_AF3 + {PB1, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 3, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH3_PC8_AF3 + {PC8, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 3, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH4_PC9_AF3 + {PC9, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 3, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_ETR_PA0_AF3 + // {PA0, TIM8_BASE_ADDRESS, 0, 3, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM15_CH1_PF9_AF14 + {PF9, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 14, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH2_PF10_AF14 + {PF10, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 14, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM5_CH1_PF6_AF2 + {PF6, TIM5_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_CH2_PF7_AF2 + {PF7, TIM5_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_CH3_PF8_AF2 + {PF8, TIM5_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_CH4_PF9_AF2 + {PF9, TIM5_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_ETR_PF6_AF1 + // {PF6, TIM5_BASE_ADDRESS, 0, 1, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_CH1_PH10_AF2 + {PH10, TIM5_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_CH2_PH11_AF2 + {PH11, TIM5_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_CH3_PH12_AF2 + {PH12, TIM5_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_CH4_PI0_AF2 + {PI0, TIM5_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM8_BKIN_PI4_AF3 + // {PI4, TIM8_BASE_ADDRESS, 0, 3, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH1N_PH13_AF3 + {PH13, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 3, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH1_PI5_AF3 + {PI5, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 3, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH2N_PH14_AF3 + {PH14, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 3, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH2_PI6_AF3 + {PI6, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 3, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH3N_PH15_AF3 + {PH15, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 3, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH3_PI7_AF3 + {PI7, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 3, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH4_PI2_AF3 + {PI2, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 3, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_ETR_PI3_AF3 + // {PI3, TIM8_BASE_ADDRESS, 0, 3, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + { HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_CHANNEL_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC } +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_TIM_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/tim/hal_ll_tim_pin_map/implementations/doc_ds_2/hal_ll_tim_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/tim/hal_ll_tim_pin_map/implementations/doc_ds_2/hal_ll_tim_pin_map.h new file mode 100644 index 000000000..8c8b3ebd4 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/tim/hal_ll_tim_pin_map/implementations/doc_ds_2/hal_ll_tim_pin_map.h @@ -0,0 +1,387 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_tim_pin_map.h + * @brief TIM HAL LOW LEVEL PIN MAP. + */ + +#ifndef _HAL_LL_TIM_PIN_MAP_H_ +#define _HAL_LL_TIM_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_tim_module_num(_module_num) (_module_num - 1) + +/*!< @brief Alternate pin function structure. */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + hal_ll_channel_t channel; + uint32_t af; + hal_ll_pin_name_t module_index; +} hal_ll_tim_pin_map_t; + +typedef enum +{ + HAL_LL_TIM_CHANNEL_0 = 0, + HAL_LL_TIM_CHANNEL_1, + HAL_LL_TIM_CHANNEL_2, + HAL_LL_TIM_CHANNEL_3, + HAL_LL_TIM_CHANNEL_4, + HAL_LL_TIM_CHANNEL_1N, + HAL_LL_TIM_CHANNEL_2N, + HAL_LL_TIM_CHANNEL_3N, + HAL_LL_TIM_CHANNEL_4N +} hal_ll_tim_channel_t; + +#ifdef TIM_MODULE_1 +#define TIM1_BASE_ADDRESS (0x40012C00UL) +#define TIM1_BASE_ADDR TIM1_BASE_ADDRESS +#define HAL_LL_TIM1_BASE_ADDR TIM1_BASE_ADDRESS +#define HAL_LL_TIM1_BASE_ADDRESS TIM1_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_3 +#define TIM3_BASE_ADDRESS (0x40000400UL) +#define TIM3_BASE_ADDR TIM3_BASE_ADDRESS +#define HAL_LL_TIM3_BASE_ADDR TIM3_BASE_ADDRESS +#define HAL_LL_TIM3_BASE_ADDRESS TIM3_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_14 +#define TIM14_BASE_ADDRESS (0x40002000UL) +#define TIM14_BASE_ADDR TIM14_BASE_ADDRESS +#define HAL_LL_TIM14_BASE_ADDR TIM14_BASE_ADDRESS +#define HAL_LL_TIM14_BASE_ADDRESS TIM14_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_16 +#define TIM16_BASE_ADDRESS (0x40014400UL) +#define TIM16_BASE_ADDR TIM16_BASE_ADDRESS +#define HAL_LL_TIM16_BASE_ADDR TIM16_BASE_ADDRESS +#define HAL_LL_TIM16_BASE_ADDRESS TIM16_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_17 +#define TIM17_BASE_ADDRESS (0x40014800UL) +#define TIM17_BASE_ADDR TIM17_BASE_ADDRESS +#define HAL_LL_TIM17_BASE_ADDR TIM17_BASE_ADDRESS +#define HAL_LL_TIM17_BASE_ADDRESS TIM17_BASE_ADDRESS +#endif + +/*!< @brief TIM pins. */ +static const hal_ll_tim_pin_map_t _tim_map[] = { + #ifdef TIM14_CH1_PA4_AF4 + {PA4, TIM14_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 4, hal_ll_tim_module_num(TIM_MODULE_14)}, + #endif + #ifdef TIM14_CH1_PA7_AF4 + {PA7, TIM14_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 4, hal_ll_tim_module_num(TIM_MODULE_14)}, + #endif + #ifdef TIM14_CH1_PA8_AF13 + {PA8, TIM14_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 13, hal_ll_tim_module_num(TIM_MODULE_14)}, + #endif + #ifdef TIM14_CH1_PB1_AF0 + {PB1, TIM14_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 0, hal_ll_tim_module_num(TIM_MODULE_14)}, + #endif + #ifdef TIM16_BKIN_PB5_AF2 + // {PB5, TIM16_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_BKIN_PB6_AF14 + // {PB6, TIM16_BASE_ADDRESS, 0, 14, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1N_PA2_AF2 + {PA2, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 2, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1N_PB6_AF2 + {PB6, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 2, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1_PA0_AF2 + {PA0, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1_PA6_AF5 + {PA6, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 5, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1_PB7_AF10 + {PB7, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 10, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1_PB8_AF2 + {PB8, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM17_BKIN_PB4_AF5 + // {PB4, TIM17_BASE_ADDRESS, 0, 5, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_BKIN_PB6_AF15 + // {PB6, TIM17_BASE_ADDRESS, 0, 15, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_CH1N_PA4_AF5 + {PA4, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 5, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_CH1N_PB7_AF2 + {PB7, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 2, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_CH1_PA1_AF2 + {PA1, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_CH1_PA7_AF5 + {PA7, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 5, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_CH1_PC14_AF10 + {PC14, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 10, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM1_BKIN2_PA11_AF5 + // {PA11, TIM1_BASE_ADDRESS, 0, 5, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN2_PC14_AF2 + // {PC14, TIM1_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN_PA6_AF2 + // {PA6, TIM1_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1N_PA3_AF2 + {PA3, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1N_PA7_AF2 + {PA7, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1_PA0_AF5 + {PA0, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 5, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1_PA14_AF10 + {PA14, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 10, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1_PA15_AF2 + {PA15, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1_PA5_AF5 + {PA5, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 5, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1_PA8_AF2 + {PA8, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2N_PA4_AF2 + {PA4, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2N_PA8_AF9 + {PA8, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 9, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2N_PB0_AF2 + {PB0, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2N_PB1_AF5 + {PB1, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 5, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2_PA1_AF5 + {PA1, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 5, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2_PB3_AF1 + {PB3, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 1, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2_PB6_AF11 + {PB6, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 11, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3N_PA5_AF2 + {PA5, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3N_PA8_AF10 + {PA8, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 10, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3N_PB1_AF2 + {PB1, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3_PA2_AF5 + {PA2, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 5, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3_PB6_AF1 + {PB6, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 1, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH4_PA11_AF2 + {PA11, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH4_PA3_AF5 + {PA3, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 5, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH4_PB7_AF1 + {PB7, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 1, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH4_PF2_AF1 + {PF2, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 1, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_ETR_PA12_AF2 + // {PA12, TIM1_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_ETR_PC14_AF1 + // {PC14, TIM1_BASE_ADDRESS, 0, 1, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_ETR_PC15_AF2 + // {PC15, TIM1_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM3_CH1_PA6_AF1 + {PA6, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH1_PB4_AF1 + {PB4, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH1_PB6_AF12 + {PB6, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 12, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH1_PB7_AF11 + {PB7, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 11, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH1_PB8_AF3 + {PB8, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 3, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH1_PC6_AF1 + {PC6, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH2_PA7_AF1 + {PA7, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 1, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH2_PB3_AF3 + {PB3, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 3, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH2_PB5_AF1 + {PB5, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 1, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH2_PB6_AF13 + {PB6, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 13, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH2_PC14_AF11 + {PC14, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 11, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH3_PA8_AF11 + {PA8, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 11, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH3_PB0_AF1 + {PB0, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 1, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH3_PB5_AF3 + {PB5, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 3, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH3_PB6_AF3 + {PB6, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 3, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH3_PC15_AF3 + {PC15, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 3, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH4_PA8_AF12 + {PA8, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 12, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH4_PB1_AF1 + {PB1, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 1, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH4_PB7_AF3 + {PB7, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 3, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_ETR_PA13_AF3 + // {PA13, TIM3_BASE_ADDRESS, 0, 3, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_ETR_PA2_AF3 + // {PA2, TIM3_BASE_ADDRESS, 0, 3, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM17_BKIN_PA10_AF5 + // {PA10, TIM17_BASE_ADDRESS, 0, 5, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM1_CH2_PA9_AF2 + {PA9, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3_PA10_AF2 + {PA10, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM3_ETR_PA9_AF3 + // {PA9, TIM3_BASE_ADDRESS, 0, 3, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM14_CH1_PF0_AF2 + {PF0, TIM14_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_14)}, + #endif + #ifdef TIM16_CH1_PD0_AF2 + {PD0, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM17_CH1_PB9_AF2 + {PB9, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_CH1_PD1_AF2 + {PD1, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM1_BKIN2_PB12_AF1 + // {PB12, TIM1_BASE_ADDRESS, 0, 1, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN_PB12_AF2 + // {PB12, TIM1_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN_PC13_AF2 + // {PC13, TIM1_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1N_PB13_AF2 + {PB13, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1N_PD2_AF2 + {PD2, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2N_PB14_AF2 + {PB14, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2N_PD3_AF2 + {PD3, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3N_PB15_AF2 + {PB15, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_ETR_PC13_AF1 + // {PC13, TIM1_BASE_ADDRESS, 0, 1, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM3_CH2_PB9_AF3 + {PB9, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 3, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH2_PC7_AF1 + {PC7, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 1, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_ETR_PD2_AF1 + // {PD2, TIM3_BASE_ADDRESS, 0, 1, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + { HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_CHANNEL_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC } +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_TIM_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/tim/hal_ll_tim_pin_map/implementations/doc_ds_74/hal_ll_tim_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/tim/hal_ll_tim_pin_map/implementations/doc_ds_74/hal_ll_tim_pin_map.h new file mode 100644 index 000000000..3faa3718d --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/tim/hal_ll_tim_pin_map/implementations/doc_ds_74/hal_ll_tim_pin_map.h @@ -0,0 +1,312 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_tim_pin_map.h + * @brief TIM HAL LOW LEVEL PIN MAP. + */ + +#ifndef _HAL_LL_TIM_PIN_MAP_H_ +#define _HAL_LL_TIM_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_tim_module_num(_module_num) (_module_num - 1) + +/*!< @brief Alternate pin function structure. */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + hal_ll_channel_t channel; + uint32_t af; + hal_ll_pin_name_t module_index; +} hal_ll_tim_pin_map_t; + +typedef enum +{ + HAL_LL_TIM_CHANNEL_0 = 0, + HAL_LL_TIM_CHANNEL_1, + HAL_LL_TIM_CHANNEL_2, + HAL_LL_TIM_CHANNEL_3, + HAL_LL_TIM_CHANNEL_4, + HAL_LL_TIM_CHANNEL_1N, + HAL_LL_TIM_CHANNEL_2N, + HAL_LL_TIM_CHANNEL_3N, + HAL_LL_TIM_CHANNEL_4N +} hal_ll_tim_channel_t; + +#ifdef TIM_MODULE_1 +#define TIM1_BASE_ADDRESS (0x40012C00UL) +#define TIM1_BASE_ADDR TIM1_BASE_ADDRESS +#define HAL_LL_TIM1_BASE_ADDR TIM1_BASE_ADDRESS +#define HAL_LL_TIM1_BASE_ADDRESS TIM1_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_2 +#define TIM2_BASE_ADDRESS (0x40000000UL) +#define TIM2_BASE_ADDR TIM2_BASE_ADDRESS +#define HAL_LL_TIM2_BASE_ADDR TIM2_BASE_ADDRESS +#define HAL_LL_TIM2_BASE_ADDRESS TIM2_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_3 +#define TIM3_BASE_ADDRESS (0x40000400UL) +#define TIM3_BASE_ADDR TIM3_BASE_ADDRESS +#define HAL_LL_TIM3_BASE_ADDR TIM3_BASE_ADDRESS +#define HAL_LL_TIM3_BASE_ADDRESS TIM3_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_14 +#define TIM14_BASE_ADDRESS (0x40002000UL) +#define TIM14_BASE_ADDR TIM14_BASE_ADDRESS +#define HAL_LL_TIM14_BASE_ADDR TIM14_BASE_ADDRESS +#define HAL_LL_TIM14_BASE_ADDRESS TIM14_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_15 +#define TIM15_BASE_ADDRESS (0x40014000UL) +#define TIM15_BASE_ADDR TIM15_BASE_ADDRESS +#define HAL_LL_TIM15_BASE_ADDR TIM15_BASE_ADDRESS +#define HAL_LL_TIM15_BASE_ADDRESS TIM15_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_16 +#define TIM16_BASE_ADDRESS (0x40014400UL) +#define TIM16_BASE_ADDR TIM16_BASE_ADDRESS +#define HAL_LL_TIM16_BASE_ADDR TIM16_BASE_ADDRESS +#define HAL_LL_TIM16_BASE_ADDRESS TIM16_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_17 +#define TIM17_BASE_ADDRESS (0x40014800UL) +#define TIM17_BASE_ADDR TIM17_BASE_ADDRESS +#define HAL_LL_TIM17_BASE_ADDR TIM17_BASE_ADDRESS +#define HAL_LL_TIM17_BASE_ADDRESS TIM17_BASE_ADDRESS +#endif + +/*!< @brief TIM pins. */ +static const hal_ll_tim_pin_map_t _tim_map[] = { + #ifdef LPTIM1_ETR_PB6_AF5 + // {PB6, LPTIM1_BASE_ADDRESS, 0, 5, hal_ll_lptim_module_num(LPTIM_MODULE_1)}, + #endif + #ifdef LPTIM2_ETR_PA5_AF5 + // {PA5, LPTIM2_BASE_ADDRESS, 0, 5, hal_ll_lptim_module_num(LPTIM_MODULE_2)}, + #endif + #ifdef TIM14_CH1_PA4_AF4 + {PA4, TIM14_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 4, hal_ll_tim_module_num(TIM_MODULE_14)}, + #endif + #ifdef TIM14_CH1_PA7_AF4 + {PA7, TIM14_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 4, hal_ll_tim_module_num(TIM_MODULE_14)}, + #endif + #ifdef TIM14_CH1_PB1_AF0 + {PB1, TIM14_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 0, hal_ll_tim_module_num(TIM_MODULE_14)}, + #endif + #ifdef TIM15_CH1N_PA1_AF5 + {PA1, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 5, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH1_PA2_AF5 + {PA2, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 5, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH2_PA3_AF5 + {PA3, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 5, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM16_CH1N_PB6_AF2 + {PB6, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 2, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1_PA6_AF5 + {PA6, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 5, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1_PB8_AF2 + {PB8, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM17_CH1N_PB7_AF2 + {PB7, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 2, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_CH1_PA7_AF5 + {PA7, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 5, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_CH1_PB9_AF2 + {PB9, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM1_CH1N_PA7_AF2 + {PA7, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1_PA8_AF2 + {PA8, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2N_PB0_AF2 + {PB0, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2_PA9_AF2 + {PA9, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2_PB3_AF1 + {PB3, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 1, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3N_PB1_AF2 + {PB1, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3_PA10_AF2 + {PA10, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3_PB6_AF1 + {PB6, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 1, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH4_PA11_AF2 + {PA11, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_ETR_PA12_AF2 + // {PA12, TIM1_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM2_CH1_PA0_AF2 + {PA0, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH1_PA15_AF2 + {PA15, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH1_PA5_AF2 + {PA5, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH2_PA1_AF2 + {PA1, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH2_PB3_AF2 + {PB3, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH3_PA2_AF2 + {PA2, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH4_PA3_AF2 + {PA3, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_ETR_PA0_AF2 + // {PA0, TIM2_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_ETR_PA15_AF2 + // {PA15, TIM2_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_ETR_PA5_AF2 + // {PA5, TIM2_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM3_CH1_PA6_AF1 + {PA6, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH1_PB4_AF1 + {PB4, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH2_PA7_AF1 + {PA7, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 1, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH2_PB5_AF1 + {PB5, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 1, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH3_PB0_AF1 + {PB0, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 1, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH4_PB1_AF1 + {PB1, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 1, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM2_CH3_PC6_AF2 + {PC6, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM3_CH1_PC6_AF1 + {PC6, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM14_CH1_PF0_AF2 + {PF0, TIM14_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_14)}, + #endif + #ifdef TIM15_CH1N_PB13_AF5 + {PB13, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 5, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH1N_PB15_AF4 + {PB15, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 4, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH1N_PF1_AF2 + {PF1, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 2, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH1_PB14_AF5 + {PB14, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 5, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH2_PB15_AF5 + {PB15, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 5, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM16_CH1_PD0_AF2 + {PD0, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM17_CH1_PD1_AF2 + {PD1, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM1_CH1N_PB13_AF2 + {PB13, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1N_PD2_AF2 + {PD2, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2N_PB14_AF2 + {PB14, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2N_PD3_AF2 + {PD3, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3N_PB15_AF2 + {PB15, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM2_CH3_PB10_AF2 + {PB10, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH4_PB11_AF2 + {PB11, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH4_PC7_AF2 + {PC7, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM3_CH2_PC7_AF1 + {PC7, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 1, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_ETR_PD2_AF1 + // {PD2, TIM3_BASE_ADDRESS, 0, 1, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + { HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_CHANNEL_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC } +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_TIM_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/tim/hal_ll_tim_pin_map/implementations/doc_ds_75/hal_ll_tim_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/tim/hal_ll_tim_pin_map/implementations/doc_ds_75/hal_ll_tim_pin_map.h new file mode 100644 index 000000000..f640337b4 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/tim/hal_ll_tim_pin_map/implementations/doc_ds_75/hal_ll_tim_pin_map.h @@ -0,0 +1,312 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_tim_pin_map.h + * @brief TIM HAL LOW LEVEL PIN MAP. + */ + +#ifndef _HAL_LL_TIM_PIN_MAP_H_ +#define _HAL_LL_TIM_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_tim_module_num(_module_num) (_module_num - 1) + +/*!< @brief Alternate pin function structure. */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + hal_ll_channel_t channel; + uint32_t af; + hal_ll_pin_name_t module_index; +} hal_ll_tim_pin_map_t; + +typedef enum +{ + HAL_LL_TIM_CHANNEL_0 = 0, + HAL_LL_TIM_CHANNEL_1, + HAL_LL_TIM_CHANNEL_2, + HAL_LL_TIM_CHANNEL_3, + HAL_LL_TIM_CHANNEL_4, + HAL_LL_TIM_CHANNEL_1N, + HAL_LL_TIM_CHANNEL_2N, + HAL_LL_TIM_CHANNEL_3N, + HAL_LL_TIM_CHANNEL_4N +} hal_ll_tim_channel_t; + +#ifdef TIM_MODULE_1 +#define TIM1_BASE_ADDRESS (0x40012C00UL) +#define TIM1_BASE_ADDR TIM1_BASE_ADDRESS +#define HAL_LL_TIM1_BASE_ADDR TIM1_BASE_ADDRESS +#define HAL_LL_TIM1_BASE_ADDRESS TIM1_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_2 +#define TIM2_BASE_ADDRESS (0x40000000UL) +#define TIM2_BASE_ADDR TIM2_BASE_ADDRESS +#define HAL_LL_TIM2_BASE_ADDR TIM2_BASE_ADDRESS +#define HAL_LL_TIM2_BASE_ADDRESS TIM2_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_3 +#define TIM3_BASE_ADDRESS (0x40000400UL) +#define TIM3_BASE_ADDR TIM3_BASE_ADDRESS +#define HAL_LL_TIM3_BASE_ADDR TIM3_BASE_ADDRESS +#define HAL_LL_TIM3_BASE_ADDRESS TIM3_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_14 +#define TIM14_BASE_ADDRESS (0x40002000UL) +#define TIM14_BASE_ADDR TIM14_BASE_ADDRESS +#define HAL_LL_TIM14_BASE_ADDR TIM14_BASE_ADDRESS +#define HAL_LL_TIM14_BASE_ADDRESS TIM14_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_15 +#define TIM15_BASE_ADDRESS (0x40014000UL) +#define TIM15_BASE_ADDR TIM15_BASE_ADDRESS +#define HAL_LL_TIM15_BASE_ADDR TIM15_BASE_ADDRESS +#define HAL_LL_TIM15_BASE_ADDRESS TIM15_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_16 +#define TIM16_BASE_ADDRESS (0x40014400UL) +#define TIM16_BASE_ADDR TIM16_BASE_ADDRESS +#define HAL_LL_TIM16_BASE_ADDR TIM16_BASE_ADDRESS +#define HAL_LL_TIM16_BASE_ADDRESS TIM16_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_17 +#define TIM17_BASE_ADDRESS (0x40014800UL) +#define TIM17_BASE_ADDR TIM17_BASE_ADDRESS +#define HAL_LL_TIM17_BASE_ADDR TIM17_BASE_ADDRESS +#define HAL_LL_TIM17_BASE_ADDRESS TIM17_BASE_ADDRESS +#endif + +/*!< @brief TIM pins. */ +static const hal_ll_tim_pin_map_t _tim_map[] = { + #ifdef LPTIM1_ETR_PB6_AF5 + // {PB6, LPTIM1_BASE_ADDRESS, 0, 5, hal_ll_lptim_module_num(LPTIM_MODULE_1)}, + #endif + #ifdef LPTIM2_ETR_PA5_AF5 + // {PA5, LPTIM2_BASE_ADDRESS, 0, 5, hal_ll_lptim_module_num(LPTIM_MODULE_2)}, + #endif + #ifdef TIM14_CH1_PA4_AF4 + {PA4, TIM14_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 4, hal_ll_tim_module_num(TIM_MODULE_14)}, + #endif + #ifdef TIM14_CH1_PA7_AF4 + {PA7, TIM14_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 4, hal_ll_tim_module_num(TIM_MODULE_14)}, + #endif + #ifdef TIM14_CH1_PB1_AF0 + {PB1, TIM14_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 0, hal_ll_tim_module_num(TIM_MODULE_14)}, + #endif + #ifdef TIM15_CH1N_PA1_AF5 + {PA1, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 5, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH1_PA2_AF5 + {PA2, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 5, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH2_PA3_AF5 + {PA3, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 5, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM16_CH1N_PB6_AF2 + {PB6, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 2, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1_PA6_AF5 + {PA6, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 5, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1_PB8_AF2 + {PB8, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM17_CH1N_PB7_AF2 + {PB7, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 2, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_CH1_PA7_AF5 + {PA7, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 5, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_CH1_PB9_AF2 + {PB9, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM1_CH1N_PA7_AF2 + {PA7, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1_PA8_AF2 + {PA8, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2N_PB0_AF2 + {PB0, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2_PA9_AF2 + {PA9, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2_PB3_AF1 + {PB3, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 1, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3N_PB1_AF2 + {PB1, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3_PA10_AF2 + {PA10, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3_PB6_AF1 + {PB6, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 1, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH4_PA11_AF2 + {PA11, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_ETR_PA12_AF2 + // {PA12, TIM1_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM2_CH1_PA0_AF2 + {PA0, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH1_PA15_AF2 + {PA15, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH1_PA5_AF2 + {PA5, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH2_PA1_AF2 + {PA1, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH2_PB3_AF2 + {PB3, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH3_PA2_AF2 + {PA2, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH3_PC6_AF2 + {PC6, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH4_PA3_AF2 + {PA3, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_ETR_PA0_AF2 + // {PA0, TIM2_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_ETR_PA15_AF2 + // {PA15, TIM2_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_ETR_PA5_AF2 + // {PA5, TIM2_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM3_CH1_PA6_AF1 + {PA6, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH1_PB4_AF1 + {PB4, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH1_PC6_AF1 + {PC6, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH2_PA7_AF1 + {PA7, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 1, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH2_PB5_AF1 + {PB5, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 1, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH3_PB0_AF1 + {PB0, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 1, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH4_PB1_AF1 + {PB1, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 1, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM14_CH1_PF0_AF2 + {PF0, TIM14_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_14)}, + #endif + #ifdef TIM15_CH1N_PB13_AF5 + {PB13, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 5, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH1N_PB15_AF4 + {PB15, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 4, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH1N_PF1_AF2 + {PF1, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 2, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH1_PB14_AF5 + {PB14, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 5, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH2_PB15_AF5 + {PB15, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 5, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM16_CH1_PD0_AF2 + {PD0, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM17_CH1_PD1_AF2 + {PD1, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM1_CH1N_PB13_AF2 + {PB13, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1N_PD2_AF2 + {PD2, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2N_PB14_AF2 + {PB14, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2N_PD3_AF2 + {PD3, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3N_PB15_AF2 + {PB15, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM2_CH3_PB10_AF2 + {PB10, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH4_PB11_AF2 + {PB11, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH4_PC7_AF2 + {PC7, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM3_CH2_PC7_AF1 + {PC7, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 1, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_ETR_PD2_AF1 + // {PD2, TIM3_BASE_ADDRESS, 0, 1, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + { HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_CHANNEL_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC } +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_TIM_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/tim/hal_ll_tim_pin_map/implementations/doc_ds_80/hal_ll_tim_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/tim/hal_ll_tim_pin_map/implementations/doc_ds_80/hal_ll_tim_pin_map.h new file mode 100644 index 000000000..826883e4d --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/tim/hal_ll_tim_pin_map/implementations/doc_ds_80/hal_ll_tim_pin_map.h @@ -0,0 +1,444 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_tim_pin_map.h + * @brief TIM HAL LOW LEVEL PIN MAP. + */ + +#ifndef _HAL_LL_TIM_PIN_MAP_H_ +#define _HAL_LL_TIM_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_tim_module_num(_module_num) (_module_num - 1) + +/*!< @brief Alternate pin function structure. */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + hal_ll_channel_t channel; + uint32_t af; + hal_ll_pin_name_t module_index; +} hal_ll_tim_pin_map_t; + +typedef enum +{ + HAL_LL_TIM_CHANNEL_0 = 0, + HAL_LL_TIM_CHANNEL_1, + HAL_LL_TIM_CHANNEL_2, + HAL_LL_TIM_CHANNEL_3, + HAL_LL_TIM_CHANNEL_4, + HAL_LL_TIM_CHANNEL_1N, + HAL_LL_TIM_CHANNEL_2N, + HAL_LL_TIM_CHANNEL_3N, + HAL_LL_TIM_CHANNEL_4N +} hal_ll_tim_channel_t; + +#ifdef TIM_MODULE_1 +#define TIM1_BASE_ADDRESS (0x40012C00UL) +#define TIM1_BASE_ADDR TIM1_BASE_ADDRESS +#define HAL_LL_TIM1_BASE_ADDR TIM1_BASE_ADDRESS +#define HAL_LL_TIM1_BASE_ADDRESS TIM1_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_2 +#define TIM2_BASE_ADDRESS (0x40000000UL) +#define TIM2_BASE_ADDR TIM2_BASE_ADDRESS +#define HAL_LL_TIM2_BASE_ADDR TIM2_BASE_ADDRESS +#define HAL_LL_TIM2_BASE_ADDRESS TIM2_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_3 +#define TIM3_BASE_ADDRESS (0x40000400UL) +#define TIM3_BASE_ADDR TIM3_BASE_ADDRESS +#define HAL_LL_TIM3_BASE_ADDR TIM3_BASE_ADDRESS +#define HAL_LL_TIM3_BASE_ADDRESS TIM3_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_4 +#define TIM4_BASE_ADDRESS (0x40000800UL) +#define TIM4_BASE_ADDR TIM4_BASE_ADDRESS +#define HAL_LL_TIM4_BASE_ADDR TIM4_BASE_ADDRESS +#define HAL_LL_TIM4_BASE_ADDRESS TIM4_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_14 +#define TIM14_BASE_ADDRESS (0x40002000UL) +#define TIM14_BASE_ADDR TIM14_BASE_ADDRESS +#define HAL_LL_TIM14_BASE_ADDR TIM14_BASE_ADDRESS +#define HAL_LL_TIM14_BASE_ADDRESS TIM14_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_15 +#define TIM15_BASE_ADDRESS (0x40014000UL) +#define TIM15_BASE_ADDR TIM15_BASE_ADDRESS +#define HAL_LL_TIM15_BASE_ADDR TIM15_BASE_ADDRESS +#define HAL_LL_TIM15_BASE_ADDRESS TIM15_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_16 +#define TIM16_BASE_ADDRESS (0x40014400UL) +#define TIM16_BASE_ADDR TIM16_BASE_ADDRESS +#define HAL_LL_TIM16_BASE_ADDR TIM16_BASE_ADDRESS +#define HAL_LL_TIM16_BASE_ADDRESS TIM16_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_17 +#define TIM17_BASE_ADDRESS (0x40014800UL) +#define TIM17_BASE_ADDR TIM17_BASE_ADDRESS +#define HAL_LL_TIM17_BASE_ADDR TIM17_BASE_ADDRESS +#define HAL_LL_TIM17_BASE_ADDRESS TIM17_BASE_ADDRESS +#endif + +/*!< @brief TIM pins. */ +static const hal_ll_tim_pin_map_t _tim_map[] = { + #ifdef LPTIM1_ETR_PB6_AF5 + // {PB6, LPTIM1_BASE_ADDRESS, 0, 5, hal_ll_lptim_module_num(LPTIM_MODULE_1)}, + #endif + #ifdef LPTIM1_ETR_PC3_AF0 + // {PC3, LPTIM1_BASE_ADDRESS, 0, 0, hal_ll_lptim_module_num(LPTIM_MODULE_1)}, + #endif + #ifdef LPTIM2_ETR_PA5_AF5 + // {PA5, LPTIM2_BASE_ADDRESS, 0, 5, hal_ll_lptim_module_num(LPTIM_MODULE_2)}, + #endif + #ifdef LPTIM2_ETR_PC3_AF2 + // {PC3, LPTIM2_BASE_ADDRESS, 0, 2, hal_ll_lptim_module_num(LPTIM_MODULE_2)}, + #endif + #ifdef LPTIM2_ETR_PD11_AF1 + // {PD11, LPTIM2_BASE_ADDRESS, 0, 1, hal_ll_lptim_module_num(LPTIM_MODULE_2)}, + #endif + #ifdef TIM14_CH1_PA4_AF4 + {PA4, TIM14_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 4, hal_ll_tim_module_num(TIM_MODULE_14)}, + #endif + #ifdef TIM14_CH1_PA7_AF4 + {PA7, TIM14_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 4, hal_ll_tim_module_num(TIM_MODULE_14)}, + #endif + #ifdef TIM14_CH1_PB1_AF0 + {PB1, TIM14_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 0, hal_ll_tim_module_num(TIM_MODULE_14)}, + #endif + #ifdef TIM14_CH1_PC12_AF2 + {PC12, TIM14_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_14)}, + #endif + #ifdef TIM14_CH1_PF0_AF2 + {PF0, TIM14_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_14)}, + #endif + #ifdef TIM15_CH1N_PA1_AF5 + {PA1, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 5, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH1N_PB13_AF5 + {PB13, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 5, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH1N_PB15_AF4 + {PB15, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 4, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH1N_PF1_AF2 + {PF1, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 2, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH1_PA2_AF5 + {PA2, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 5, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH1_PB14_AF5 + {PB14, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 5, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH1_PC1_AF2 + {PC1, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH2_PA3_AF5 + {PA3, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 5, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH2_PB15_AF5 + {PB15, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 5, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH2_PC2_AF2 + {PC2, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM16_CH1N_PB6_AF2 + {PB6, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 2, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1_PA6_AF5 + {PA6, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 5, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1_PB8_AF2 + {PB8, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1_PD0_AF2 + {PD0, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1_PE0_AF0 + {PE0, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 0, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM17_CH1N_PB7_AF2 + {PB7, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 2, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_CH1_PA7_AF5 + {PA7, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 5, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_CH1_PB9_AF2 + {PB9, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_CH1_PD1_AF2 + {PD1, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_CH1_PE1_AF0 + {PE1, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 0, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM1_CH1N_PA7_AF2 + {PA7, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1N_PB13_AF2 + {PB13, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1N_PD2_AF2 + {PD2, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1N_PE8_AF1 + {PE8, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 1, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1_PA8_AF2 + {PA8, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1_PC8_AF2 + {PC8, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1_PE9_AF1 + {PE9, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2N_PB0_AF2 + {PB0, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2N_PB14_AF2 + {PB14, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2N_PD3_AF2 + {PD3, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2N_PE10_AF1 + {PE10, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 1, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2_PA9_AF2 + {PA9, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2_PB3_AF1 + {PB3, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 1, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2_PC9_AF2 + {PC9, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3N_PB15_AF2 + {PB15, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3N_PB1_AF2 + {PB1, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3N_PD4_AF2 + {PD4, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3_PA10_AF2 + {PA10, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3_PB6_AF1 + {PB6, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 1, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3_PC10_AF2 + {PC10, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH4_PA11_AF2 + {PA11, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH4_PC11_AF2 + {PC11, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_ETR_PA12_AF2 + // {PA12, TIM1_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_ETR_PE7_AF1 + // {PE7, TIM1_BASE_ADDRESS, 0, 1, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM2_CH1_PA0_AF2 + {PA0, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH1_PA15_AF2 + {PA15, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH1_PA5_AF2 + {PA5, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH1_PC4_AF2 + {PC4, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH2_PA1_AF2 + {PA1, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH2_PB3_AF2 + {PB3, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH2_PC5_AF2 + {PC5, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH3_PA2_AF2 + {PA2, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH3_PB10_AF2 + {PB10, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH3_PC6_AF2 + {PC6, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH4_PA3_AF2 + {PA3, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH4_PB11_AF2 + {PB11, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH4_PC7_AF2 + {PC7, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_ETR_PA0_AF2 + // {PA0, TIM2_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_ETR_PA15_AF2 + // {PA15, TIM2_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_ETR_PA5_AF2 + // {PA5, TIM2_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_ETR_PC4_AF2 + // {PC4, TIM2_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM3_CH1_PA6_AF1 + {PA6, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH1_PB4_AF1 + {PB4, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH1_PC6_AF1 + {PC6, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH1_PE3_AF1 + {PE3, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH2_PA7_AF1 + {PA7, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 1, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH2_PB5_AF1 + {PB5, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 1, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH2_PC7_AF1 + {PC7, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 1, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH3_PB0_AF1 + {PB0, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 1, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH3_PC8_AF1 + {PC8, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 1, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH4_PB1_AF1 + {PB1, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 1, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH4_PC9_AF1 + {PC9, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 1, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_ETR_PD2_AF1 + // {PD2, TIM3_BASE_ADDRESS, 0, 1, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM4_CH1_PB6_AF9 + {PB6, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 9, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH1_PD12_AF2 + {PD12, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH2_PB7_AF9 + {PB7, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 9, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH2_PD13_AF2 + {PD13, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH3_PB8_AF9 + {PB8, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 9, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH3_PD14_AF2 + {PD14, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH4_PB9_AF9 + {PB9, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 9, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH4_PD15_AF2 + {PD15, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_ETR_PE0_AF2 + // {PE0, TIM4_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM15_CH1_PF12_AF0 + {PF12, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 0, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH2_PF13_AF0 + {PF13, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 0, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM1_CH2_PE11_AF1 + {PE11, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 1, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3N_PE12_AF1 + {PE12, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 1, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3_PE13_AF1 + {PE13, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 1, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH4_PE14_AF1 + {PE14, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 1, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM3_CH2_PE4_AF1 + {PE4, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 1, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH3_PE5_AF1 + {PE5, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 1, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH4_PE6_AF1 + {PE6, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 1, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_ETR_PE2_AF1 + // {PE2, TIM3_BASE_ADDRESS, 0, 1, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + { HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_CHANNEL_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC } +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_TIM_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/tim/hal_ll_tim_pin_map/implementations/doc_ds_81/hal_ll_tim_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/tim/hal_ll_tim_pin_map/implementations/doc_ds_81/hal_ll_tim_pin_map.h new file mode 100644 index 000000000..ad78ac35e --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/tim/hal_ll_tim_pin_map/implementations/doc_ds_81/hal_ll_tim_pin_map.h @@ -0,0 +1,444 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_tim_pin_map.h + * @brief TIM HAL LOW LEVEL PIN MAP. + */ + +#ifndef _HAL_LL_TIM_PIN_MAP_H_ +#define _HAL_LL_TIM_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_tim_module_num(_module_num) (_module_num - 1) + +/*!< @brief Alternate pin function structure. */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + hal_ll_channel_t channel; + uint32_t af; + hal_ll_pin_name_t module_index; +} hal_ll_tim_pin_map_t; + +typedef enum +{ + HAL_LL_TIM_CHANNEL_0 = 0, + HAL_LL_TIM_CHANNEL_1, + HAL_LL_TIM_CHANNEL_2, + HAL_LL_TIM_CHANNEL_3, + HAL_LL_TIM_CHANNEL_4, + HAL_LL_TIM_CHANNEL_1N, + HAL_LL_TIM_CHANNEL_2N, + HAL_LL_TIM_CHANNEL_3N, + HAL_LL_TIM_CHANNEL_4N +} hal_ll_tim_channel_t; + +#ifdef TIM_MODULE_1 +#define TIM1_BASE_ADDRESS (0x40012C00UL) +#define TIM1_BASE_ADDR TIM1_BASE_ADDRESS +#define HAL_LL_TIM1_BASE_ADDR TIM1_BASE_ADDRESS +#define HAL_LL_TIM1_BASE_ADDRESS TIM1_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_2 +#define TIM2_BASE_ADDRESS (0x40000000UL) +#define TIM2_BASE_ADDR TIM2_BASE_ADDRESS +#define HAL_LL_TIM2_BASE_ADDR TIM2_BASE_ADDRESS +#define HAL_LL_TIM2_BASE_ADDRESS TIM2_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_3 +#define TIM3_BASE_ADDRESS (0x40000400UL) +#define TIM3_BASE_ADDR TIM3_BASE_ADDRESS +#define HAL_LL_TIM3_BASE_ADDR TIM3_BASE_ADDRESS +#define HAL_LL_TIM3_BASE_ADDRESS TIM3_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_4 +#define TIM4_BASE_ADDRESS (0x40000800UL) +#define TIM4_BASE_ADDR TIM4_BASE_ADDRESS +#define HAL_LL_TIM4_BASE_ADDR TIM4_BASE_ADDRESS +#define HAL_LL_TIM4_BASE_ADDRESS TIM4_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_14 +#define TIM14_BASE_ADDRESS (0x40002000UL) +#define TIM14_BASE_ADDR TIM14_BASE_ADDRESS +#define HAL_LL_TIM14_BASE_ADDR TIM14_BASE_ADDRESS +#define HAL_LL_TIM14_BASE_ADDRESS TIM14_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_15 +#define TIM15_BASE_ADDRESS (0x40014000UL) +#define TIM15_BASE_ADDR TIM15_BASE_ADDRESS +#define HAL_LL_TIM15_BASE_ADDR TIM15_BASE_ADDRESS +#define HAL_LL_TIM15_BASE_ADDRESS TIM15_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_16 +#define TIM16_BASE_ADDRESS (0x40014400UL) +#define TIM16_BASE_ADDR TIM16_BASE_ADDRESS +#define HAL_LL_TIM16_BASE_ADDR TIM16_BASE_ADDRESS +#define HAL_LL_TIM16_BASE_ADDRESS TIM16_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_17 +#define TIM17_BASE_ADDRESS (0x40014800UL) +#define TIM17_BASE_ADDR TIM17_BASE_ADDRESS +#define HAL_LL_TIM17_BASE_ADDR TIM17_BASE_ADDRESS +#define HAL_LL_TIM17_BASE_ADDRESS TIM17_BASE_ADDRESS +#endif + +/*!< @brief TIM pins. */ +static const hal_ll_tim_pin_map_t _tim_map[] = { + #ifdef LPTIM1_ETR_PB6_AF5 + // {PB6, LPTIM1_BASE_ADDRESS, 0, 5, hal_ll_lptim_module_num(LPTIM_MODULE_1)}, + #endif + #ifdef LPTIM2_ETR_PA5_AF5 + // {PA5, LPTIM2_BASE_ADDRESS, 0, 5, hal_ll_lptim_module_num(LPTIM_MODULE_2)}, + #endif + #ifdef TIM14_CH1_PA4_AF4 + {PA4, TIM14_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 4, hal_ll_tim_module_num(TIM_MODULE_14)}, + #endif + #ifdef TIM14_CH1_PA7_AF4 + {PA7, TIM14_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 4, hal_ll_tim_module_num(TIM_MODULE_14)}, + #endif + #ifdef TIM14_CH1_PB1_AF0 + {PB1, TIM14_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 0, hal_ll_tim_module_num(TIM_MODULE_14)}, + #endif + #ifdef TIM14_CH1_PF0_AF2 + {PF0, TIM14_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_14)}, + #endif + #ifdef TIM15_CH1N_PA1_AF5 + {PA1, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 5, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH1N_PB13_AF5 + {PB13, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 5, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH1N_PB15_AF4 + {PB15, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 4, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH1N_PF1_AF2 + {PF1, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 2, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH1_PA2_AF5 + {PA2, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 5, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH1_PB14_AF5 + {PB14, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 5, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH2_PA3_AF5 + {PA3, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 5, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH2_PB15_AF5 + {PB15, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 5, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM16_CH1N_PB6_AF2 + {PB6, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 2, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1_PA6_AF5 + {PA6, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 5, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1_PB8_AF2 + {PB8, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1_PD0_AF2 + {PD0, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM17_CH1N_PB7_AF2 + {PB7, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 2, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_CH1_PA7_AF5 + {PA7, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 5, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_CH1_PB9_AF2 + {PB9, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_CH1_PD1_AF2 + {PD1, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM1_CH1N_PA7_AF2 + {PA7, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1N_PB13_AF2 + {PB13, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1N_PD2_AF2 + {PD2, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1_PA8_AF2 + {PA8, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2N_PB0_AF2 + {PB0, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2N_PB14_AF2 + {PB14, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2N_PD3_AF2 + {PD3, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2_PA9_AF2 + {PA9, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2_PB3_AF1 + {PB3, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 1, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3N_PB15_AF2 + {PB15, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3N_PB1_AF2 + {PB1, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3_PA10_AF2 + {PA10, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3_PB6_AF1 + {PB6, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 1, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH4_PA11_AF2 + {PA11, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_ETR_PA12_AF2 + // {PA12, TIM1_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM2_CH1_PA0_AF2 + {PA0, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH1_PA15_AF2 + {PA15, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH1_PA5_AF2 + {PA5, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH2_PA1_AF2 + {PA1, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH2_PB3_AF2 + {PB3, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH3_PA2_AF2 + {PA2, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH3_PB10_AF2 + {PB10, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH3_PC6_AF2 + {PC6, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH4_PA3_AF2 + {PA3, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH4_PB11_AF2 + {PB11, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH4_PC7_AF2 + {PC7, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_ETR_PA0_AF2 + // {PA0, TIM2_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_ETR_PA15_AF2 + // {PA15, TIM2_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_ETR_PA5_AF2 + // {PA5, TIM2_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM3_CH1_PA6_AF1 + {PA6, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH1_PB4_AF1 + {PB4, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH1_PC6_AF1 + {PC6, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH2_PA7_AF1 + {PA7, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 1, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH2_PB5_AF1 + {PB5, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 1, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH2_PC7_AF1 + {PC7, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 1, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH3_PB0_AF1 + {PB0, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 1, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH4_PB1_AF1 + {PB1, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 1, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_ETR_PD2_AF1 + // {PD2, TIM3_BASE_ADDRESS, 0, 1, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM4_CH1_PB6_AF9 + {PB6, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 9, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH2_PB7_AF9 + {PB7, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 9, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH3_PB8_AF9 + {PB8, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 9, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH4_PB9_AF9 + {PB9, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 9, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef LPTIM1_ETR_PC3_AF0 + // {PC3, LPTIM1_BASE_ADDRESS, 0, 0, hal_ll_lptim_module_num(LPTIM_MODULE_1)}, + #endif + #ifdef LPTIM2_ETR_PC3_AF2 + // {PC3, LPTIM2_BASE_ADDRESS, 0, 2, hal_ll_lptim_module_num(LPTIM_MODULE_2)}, + #endif + #ifdef TIM14_CH1_PC12_AF2 + {PC12, TIM14_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_14)}, + #endif + #ifdef TIM15_CH1_PC1_AF2 + {PC1, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH2_PC2_AF2 + {PC2, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM1_CH1_PC8_AF2 + {PC8, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2_PC9_AF2 + {PC9, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3N_PD4_AF2 + {PD4, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3_PC10_AF2 + {PC10, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH4_PC11_AF2 + {PC11, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM2_CH1_PC4_AF2 + {PC4, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH2_PC5_AF2 + {PC5, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_ETR_PC4_AF2 + // {PC4, TIM2_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM3_CH3_PC8_AF1 + {PC8, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 1, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH4_PC9_AF1 + {PC9, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 1, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef LPTIM2_ETR_PD11_AF1 + // {PD11, LPTIM2_BASE_ADDRESS, 0, 1, hal_ll_lptim_module_num(LPTIM_MODULE_2)}, + #endif + #ifdef TIM16_CH1_PE0_AF0 + {PE0, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 0, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM17_CH1_PE1_AF0 + {PE1, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 0, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM1_CH1N_PE8_AF1 + {PE8, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 1, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1_PE9_AF1 + {PE9, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2N_PE10_AF1 + {PE10, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 1, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_ETR_PE7_AF1 + // {PE7, TIM1_BASE_ADDRESS, 0, 1, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM3_CH1_PE3_AF1 + {PE3, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM4_CH1_PD12_AF2 + {PD12, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH2_PD13_AF2 + {PD13, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH3_PD14_AF2 + {PD14, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH4_PD15_AF2 + {PD15, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_ETR_PE0_AF2 + // {PE0, TIM4_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM15_CH1_PF12_AF0 + {PF12, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 0, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH2_PF13_AF0 + {PF13, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 0, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM1_CH2_PE11_AF1 + {PE11, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 1, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3N_PE12_AF1 + {PE12, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 1, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3_PE13_AF1 + {PE13, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 1, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH4_PE14_AF1 + {PE14, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 1, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM3_CH2_PE4_AF1 + {PE4, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 1, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH3_PE5_AF1 + {PE5, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 1, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH4_PE6_AF1 + {PE6, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 1, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_ETR_PE2_AF1 + // {PE2, TIM3_BASE_ADDRESS, 0, 1, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + { HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_CHANNEL_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC } +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_TIM_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/tim/hal_ll_tim_pin_map/implementations/doc_ds_82/hal_ll_tim_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/tim/hal_ll_tim_pin_map/implementations/doc_ds_82/hal_ll_tim_pin_map.h new file mode 100644 index 000000000..072fd9003 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/tim/hal_ll_tim_pin_map/implementations/doc_ds_82/hal_ll_tim_pin_map.h @@ -0,0 +1,591 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_tim_pin_map.h + * @brief TIM HAL LOW LEVEL PIN MAP. + */ + +#ifndef _HAL_LL_TIM_PIN_MAP_H_ +#define _HAL_LL_TIM_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_tim_module_num(_module_num) (_module_num - 1) + +/*!< @brief Alternate pin function structure. */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + hal_ll_channel_t channel; + uint32_t af; + hal_ll_pin_name_t module_index; +} hal_ll_tim_pin_map_t; + +typedef enum +{ + HAL_LL_TIM_CHANNEL_0 = 0, + HAL_LL_TIM_CHANNEL_1, + HAL_LL_TIM_CHANNEL_2, + HAL_LL_TIM_CHANNEL_3, + HAL_LL_TIM_CHANNEL_4, + HAL_LL_TIM_CHANNEL_1N, + HAL_LL_TIM_CHANNEL_2N, + HAL_LL_TIM_CHANNEL_3N, + HAL_LL_TIM_CHANNEL_4N +} hal_ll_tim_channel_t; + +#ifdef TIM_MODULE_1 +#define TIM1_BASE_ADDRESS (0x40012C00UL) +#define TIM1_BASE_ADDR TIM1_BASE_ADDRESS +#define HAL_LL_TIM1_BASE_ADDR TIM1_BASE_ADDRESS +#define HAL_LL_TIM1_BASE_ADDRESS TIM1_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_2 +#define TIM2_BASE_ADDRESS (0x40000000UL) +#define TIM2_BASE_ADDR TIM2_BASE_ADDRESS +#define HAL_LL_TIM2_BASE_ADDR TIM2_BASE_ADDRESS +#define HAL_LL_TIM2_BASE_ADDRESS TIM2_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_3 +#define TIM3_BASE_ADDRESS (0x40000400UL) +#define TIM3_BASE_ADDR TIM3_BASE_ADDRESS +#define HAL_LL_TIM3_BASE_ADDR TIM3_BASE_ADDRESS +#define HAL_LL_TIM3_BASE_ADDRESS TIM3_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_4 +#define TIM4_BASE_ADDRESS (0x40000800UL) +#define TIM4_BASE_ADDR TIM4_BASE_ADDRESS +#define HAL_LL_TIM4_BASE_ADDR TIM4_BASE_ADDRESS +#define HAL_LL_TIM4_BASE_ADDRESS TIM4_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_8 +#define TIM8_BASE_ADDRESS (0x40013400UL) +#define TIM8_BASE_ADDR TIM8_BASE_ADDRESS +#define HAL_LL_TIM8_BASE_ADDR TIM8_BASE_ADDRESS +#define HAL_LL_TIM8_BASE_ADDRESS TIM8_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_15 +#define TIM15_BASE_ADDRESS (0x40014000UL) +#define TIM15_BASE_ADDR TIM15_BASE_ADDRESS +#define HAL_LL_TIM15_BASE_ADDR TIM15_BASE_ADDRESS +#define HAL_LL_TIM15_BASE_ADDRESS TIM15_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_16 +#define TIM16_BASE_ADDRESS (0x40014400UL) +#define TIM16_BASE_ADDR TIM16_BASE_ADDRESS +#define HAL_LL_TIM16_BASE_ADDR TIM16_BASE_ADDRESS +#define HAL_LL_TIM16_BASE_ADDRESS TIM16_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_17 +#define TIM17_BASE_ADDRESS (0x40014800UL) +#define TIM17_BASE_ADDR TIM17_BASE_ADDRESS +#define HAL_LL_TIM17_BASE_ADDR TIM17_BASE_ADDRESS +#define HAL_LL_TIM17_BASE_ADDRESS TIM17_BASE_ADDRESS +#endif + +/*!< @brief TIM pins. */ +static const hal_ll_tim_pin_map_t _tim_map[] = { + #ifdef LPTIM1_ETR_PB6_AF11 + // {PB6, LPTIM1_BASE_ADDRESS, 0, 11, hal_ll_lptim_module_num(LPTIM_MODULE_1)}, + #endif + #ifdef TIM15_BKIN_PA9_AF9 + // {PA9, TIM15_BASE_ADDRESS, 0, 9, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH1N_PA1_AF9 + {PA1, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 9, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH1_PA2_AF9 + {PA2, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 9, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH2_PA3_AF9 + {PA3, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 9, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM16_BKIN_PB5_AF1 + // {PB5, TIM16_BASE_ADDRESS, 0, 1, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1N_PA13_AF1 + {PA13, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 1, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1N_PB6_AF1 + {PB6, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 1, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1_PA12_AF1 + {PA12, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1_PA6_AF1 + {PA6, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1_PB4_AF1 + {PB4, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1_PB8_AF1 + {PB8, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM17_BKIN_PA10_AF1 + // {PA10, TIM17_BASE_ADDRESS, 0, 1, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_BKIN_PB4_AF10 + // {PB4, TIM17_BASE_ADDRESS, 0, 10, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_CH1N_PB7_AF1 + {PB7, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 1, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_CH1_PA7_AF1 + {PA7, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_CH1_PB5_AF10 + {PB5, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 10, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM1_BKIN2_PA11_AF12 + // {PA11, TIM1_BASE_ADDRESS, 0, 12, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN_PA14_AF6 + // {PA14, TIM1_BASE_ADDRESS, 0, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN_PA15_AF9 + // {PA15, TIM1_BASE_ADDRESS, 0, 9, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN_PA6_AF6 + // {PA6, TIM1_BASE_ADDRESS, 0, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN_PB8_AF12 + // {PB8, TIM1_BASE_ADDRESS, 0, 12, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1N_PA11_AF6 + {PA11, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1N_PA7_AF6 + {PA7, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1_PA8_AF6 + {PA8, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2N_PA12_AF6 + {PA12, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2N_PB0_AF6 + {PB0, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2_PA9_AF6 + {PA9, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3N_PF0_AF6 + {PF0, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3_PA10_AF6 + {PA10, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH4_PA11_AF11 + {PA11, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 11, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_ETR_PA12_AF11 + // {PA12, TIM1_BASE_ADDRESS, 0, 11, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM2_CH1_PA0_AF1 + {PA0, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH1_PA15_AF1 + {PA15, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH1_PA5_AF1 + {PA5, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH2_PA1_AF1 + {PA1, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH2_PB3_AF1 + {PB3, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH3_PA2_AF1 + {PA2, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH3_PA9_AF10 + {PA9, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 10, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH4_PA10_AF10 + {PA10, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 10, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH4_PA3_AF1 + {PA3, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_ETR_PA0_AF14 + // {PA0, TIM2_BASE_ADDRESS, 0, 14, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_ETR_PA15_AF14 + // {PA15, TIM2_BASE_ADDRESS, 0, 14, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_ETR_PA5_AF2 + // {PA5, TIM2_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM3_CH1_PA6_AF2 + {PA6, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH1_PB4_AF2 + {PB4, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH2_PA4_AF2 + {PA4, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH2_PA7_AF2 + {PA7, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH2_PB5_AF2 + {PB5, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH3_PB0_AF2 + {PB0, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH4_PB7_AF10 + {PB7, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 10, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_ETR_PB3_AF10 + // {PB3, TIM3_BASE_ADDRESS, 0, 10, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM4_CH1_PA11_AF10 + {PA11, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 10, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH1_PB6_AF2 + {PB6, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH2_PA12_AF10 + {PA12, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 10, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH2_PB7_AF2 + {PB7, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH3_PA13_AF10 + {PA13, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 10, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH3_PB8_AF2 + {PB8, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_ETR_PA8_AF10 + // {PA8, TIM4_BASE_ADDRESS, 0, 10, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_ETR_PB3_AF2 + // {PB3, TIM4_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM8_BKIN2_PB6_AF10 + // {PB6, TIM8_BASE_ADDRESS, 0, 10, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_BKIN_PA0_AF9 + // {PA0, TIM8_BASE_ADDRESS, 0, 9, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_BKIN_PA10_AF11 + // {PA10, TIM8_BASE_ADDRESS, 0, 11, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_BKIN_PA6_AF4 + // {PA6, TIM8_BASE_ADDRESS, 0, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_BKIN_PB7_AF5 + // {PB7, TIM8_BASE_ADDRESS, 0, 5, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH1N_PA7_AF4 + {PA7, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH1N_PB3_AF4 + {PB3, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH1_PA15_AF2 + {PA15, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH1_PB6_AF5 + {PB6, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 5, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH2N_PB0_AF4 + {PB0, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH2N_PB4_AF4 + {PB4, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH2_PA14_AF5 + {PA14, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 5, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH2_PB8_AF10 + {PB8, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 10, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH3N_PB5_AF3 + {PB5, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 3, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_ETR_PA0_AF10 + // {PA0, TIM8_BASE_ADDRESS, 0, 10, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_ETR_PB6_AF6 + // {PB6, TIM8_BASE_ADDRESS, 0, 6, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef LPTIM1_ETR_PC3_AF1 + // {PC3, LPTIM1_BASE_ADDRESS, 0, 1, hal_ll_lptim_module_num(LPTIM_MODULE_1)}, + #endif + #ifdef TIM15_BKIN_PC5_AF2 + // {PC5, TIM15_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH1N_PB15_AF2 + {PB15, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 2, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH1_PB14_AF1 + {PB14, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH2_PB15_AF1 + {PB15, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 1, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM17_CH1_PB9_AF1 + {PB9, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM1_BKIN2_PC3_AF6 + // {PC3, TIM1_BASE_ADDRESS, 0, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN2_PE14_AF6 + // {PE14, TIM1_BASE_ADDRESS, 0, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN_PB10_AF12 + // {PB10, TIM1_BASE_ADDRESS, 0, 12, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN_PB12_AF6 + // {PB12, TIM1_BASE_ADDRESS, 0, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN_PC13_AF2 + // {PC13, TIM1_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN_PE15_AF2 + // {PE15, TIM1_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1N_PB13_AF6 + {PB13, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1N_PC13_AF4 + {PC13, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 4, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1N_PE8_AF2 + {PE8, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1_PC0_AF2 + {PC0, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1_PE9_AF2 + {PE9, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2N_PB14_AF6 + {PB14, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2N_PE10_AF2 + {PE10, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2_PC1_AF2 + {PC1, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2_PE11_AF2 + {PE11, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3N_PB15_AF4 + {PB15, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 4, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3N_PB1_AF6 + {PB1, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3N_PB9_AF12 + {PB9, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 12, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3N_PE12_AF2 + {PE12, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3_PC2_AF2 + {PC2, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3_PE13_AF2 + {PE13, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH4N_PC5_AF6 + {PC5, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH4N_PE15_AF6 + {PE15, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH4_PC3_AF2 + {PC3, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH4_PE14_AF2 + {PE14, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_ETR_PC4_AF2 + // {PC4, TIM1_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_ETR_PE7_AF2 + // {PE7, TIM1_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM2_CH3_PB10_AF1 + {PB10, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH4_PB11_AF1 + {PB11, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM3_CH1_PC6_AF2 + {PC6, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH2_PC7_AF2 + {PC7, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH3_PC8_AF2 + {PC8, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH4_PB1_AF2 + {PB1, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH4_PC9_AF2 + {PC9, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_ETR_PD2_AF2 + // {PD2, TIM3_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM4_CH4_PB9_AF2 + {PB9, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM8_BKIN2_PC9_AF6 + // {PC9, TIM8_BASE_ADDRESS, 0, 6, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_BKIN2_PD1_AF6 + // {PD1, TIM8_BASE_ADDRESS, 0, 6, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_BKIN_PD2_AF4 + // {PD2, TIM8_BASE_ADDRESS, 0, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH1N_PC10_AF4 + {PC10, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH1_PC6_AF4 + {PC6, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH2N_PC11_AF4 + {PC11, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH2_PC7_AF4 + {PC7, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH3N_PB1_AF4 + {PB1, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH3N_PC12_AF4 + {PC12, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH3_PB9_AF10 + {PB9, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 10, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH3_PC8_AF4 + {PC8, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH4N_PC13_AF6 + {PC13, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4N, 6, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH4N_PD0_AF6 + {PD0, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4N, 6, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH4_PC9_AF4 + {PC9, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH4_PD1_AF4 + {PD1, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM15_CH1_PF9_AF3 + {PF9, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 3, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH2_PF10_AF3 + {PF10, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 3, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM16_CH1_PE0_AF4 + {PE0, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 4, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM17_CH1_PE1_AF4 + {PE1, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 4, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM2_CH1_PD3_AF2 + {PD3, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH2_PD4_AF2 + {PD4, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH3_PD7_AF2 + {PD7, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH4_PD6_AF2 + {PD6, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_ETR_PD3_AF2 + // {PD3, TIM2_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM3_CH1_PE2_AF2 + {PE2, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH2_PE3_AF2 + {PE3, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH3_PE4_AF2 + {PE4, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH4_PE5_AF2 + {PE5, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM4_CH1_PD12_AF2 + {PD12, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH2_PD13_AF2 + {PD13, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH3_PD14_AF2 + {PD14, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH4_PD15_AF2 + {PD15, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_ETR_PE0_AF2 + // {PE0, TIM4_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + { HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_CHANNEL_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC } +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_TIM_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/tim/hal_ll_tim_pin_map/implementations/doc_ds_83/hal_ll_tim_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/tim/hal_ll_tim_pin_map/implementations/doc_ds_83/hal_ll_tim_pin_map.h new file mode 100644 index 000000000..077e35423 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/tim/hal_ll_tim_pin_map/implementations/doc_ds_83/hal_ll_tim_pin_map.h @@ -0,0 +1,591 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_tim_pin_map.h + * @brief TIM HAL LOW LEVEL PIN MAP. + */ + +#ifndef _HAL_LL_TIM_PIN_MAP_H_ +#define _HAL_LL_TIM_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_tim_module_num(_module_num) (_module_num - 1) + +/*!< @brief Alternate pin function structure. */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + hal_ll_channel_t channel; + uint32_t af; + hal_ll_pin_name_t module_index; +} hal_ll_tim_pin_map_t; + +typedef enum +{ + HAL_LL_TIM_CHANNEL_0 = 0, + HAL_LL_TIM_CHANNEL_1, + HAL_LL_TIM_CHANNEL_2, + HAL_LL_TIM_CHANNEL_3, + HAL_LL_TIM_CHANNEL_4, + HAL_LL_TIM_CHANNEL_1N, + HAL_LL_TIM_CHANNEL_2N, + HAL_LL_TIM_CHANNEL_3N, + HAL_LL_TIM_CHANNEL_4N +} hal_ll_tim_channel_t; + +#ifdef TIM_MODULE_1 +#define TIM1_BASE_ADDRESS (0x40012C00UL) +#define TIM1_BASE_ADDR TIM1_BASE_ADDRESS +#define HAL_LL_TIM1_BASE_ADDR TIM1_BASE_ADDRESS +#define HAL_LL_TIM1_BASE_ADDRESS TIM1_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_2 +#define TIM2_BASE_ADDRESS (0x40000000UL) +#define TIM2_BASE_ADDR TIM2_BASE_ADDRESS +#define HAL_LL_TIM2_BASE_ADDR TIM2_BASE_ADDRESS +#define HAL_LL_TIM2_BASE_ADDRESS TIM2_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_3 +#define TIM3_BASE_ADDRESS (0x40000400UL) +#define TIM3_BASE_ADDR TIM3_BASE_ADDRESS +#define HAL_LL_TIM3_BASE_ADDR TIM3_BASE_ADDRESS +#define HAL_LL_TIM3_BASE_ADDRESS TIM3_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_4 +#define TIM4_BASE_ADDRESS (0x40000800UL) +#define TIM4_BASE_ADDR TIM4_BASE_ADDRESS +#define HAL_LL_TIM4_BASE_ADDR TIM4_BASE_ADDRESS +#define HAL_LL_TIM4_BASE_ADDRESS TIM4_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_8 +#define TIM8_BASE_ADDRESS (0x40013400UL) +#define TIM8_BASE_ADDR TIM8_BASE_ADDRESS +#define HAL_LL_TIM8_BASE_ADDR TIM8_BASE_ADDRESS +#define HAL_LL_TIM8_BASE_ADDRESS TIM8_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_15 +#define TIM15_BASE_ADDRESS (0x40014000UL) +#define TIM15_BASE_ADDR TIM15_BASE_ADDRESS +#define HAL_LL_TIM15_BASE_ADDR TIM15_BASE_ADDRESS +#define HAL_LL_TIM15_BASE_ADDRESS TIM15_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_16 +#define TIM16_BASE_ADDRESS (0x40014400UL) +#define TIM16_BASE_ADDR TIM16_BASE_ADDRESS +#define HAL_LL_TIM16_BASE_ADDR TIM16_BASE_ADDRESS +#define HAL_LL_TIM16_BASE_ADDRESS TIM16_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_17 +#define TIM17_BASE_ADDRESS (0x40014800UL) +#define TIM17_BASE_ADDR TIM17_BASE_ADDRESS +#define HAL_LL_TIM17_BASE_ADDR TIM17_BASE_ADDRESS +#define HAL_LL_TIM17_BASE_ADDRESS TIM17_BASE_ADDRESS +#endif + +/*!< @brief TIM pins. */ +static const hal_ll_tim_pin_map_t _tim_map[] = { + #ifdef LPTIM1_ETR_PB6_AF11 + // {PB6, LPTIM1_BASE_ADDRESS, 0, 11, hal_ll_lptim_module_num(LPTIM_MODULE_1)}, + #endif + #ifdef LPTIM1_ETR_PC3_AF1 + // {PC3, LPTIM1_BASE_ADDRESS, 0, 1, hal_ll_lptim_module_num(LPTIM_MODULE_1)}, + #endif + #ifdef TIM15_BKIN_PA9_AF9 + // {PA9, TIM15_BASE_ADDRESS, 0, 9, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_BKIN_PC5_AF2 + // {PC5, TIM15_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH1N_PA1_AF9 + {PA1, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 9, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH1N_PB15_AF2 + {PB15, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 2, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH1_PA2_AF9 + {PA2, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 9, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH1_PB14_AF1 + {PB14, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH2_PA3_AF9 + {PA3, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 9, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH2_PB15_AF1 + {PB15, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 1, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM16_BKIN_PB5_AF1 + // {PB5, TIM16_BASE_ADDRESS, 0, 1, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1N_PA13_AF1 + {PA13, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 1, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1N_PB6_AF1 + {PB6, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 1, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1_PA12_AF1 + {PA12, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1_PA6_AF1 + {PA6, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1_PB4_AF1 + {PB4, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1_PB8_AF1 + {PB8, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM17_BKIN_PA10_AF1 + // {PA10, TIM17_BASE_ADDRESS, 0, 1, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_BKIN_PB4_AF10 + // {PB4, TIM17_BASE_ADDRESS, 0, 10, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_CH1N_PB7_AF1 + {PB7, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 1, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_CH1_PA7_AF1 + {PA7, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_CH1_PB5_AF10 + {PB5, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 10, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_CH1_PB9_AF1 + {PB9, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM1_BKIN2_PA11_AF12 + // {PA11, TIM1_BASE_ADDRESS, 0, 12, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN2_PC3_AF6 + // {PC3, TIM1_BASE_ADDRESS, 0, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN_PA14_AF6 + // {PA14, TIM1_BASE_ADDRESS, 0, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN_PA15_AF9 + // {PA15, TIM1_BASE_ADDRESS, 0, 9, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN_PA6_AF6 + // {PA6, TIM1_BASE_ADDRESS, 0, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN_PB10_AF12 + // {PB10, TIM1_BASE_ADDRESS, 0, 12, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN_PB12_AF6 + // {PB12, TIM1_BASE_ADDRESS, 0, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN_PB8_AF12 + // {PB8, TIM1_BASE_ADDRESS, 0, 12, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN_PC13_AF2 + // {PC13, TIM1_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1N_PA11_AF6 + {PA11, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1N_PA7_AF6 + {PA7, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1N_PB13_AF6 + {PB13, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1N_PC13_AF4 + {PC13, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 4, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1_PA8_AF6 + {PA8, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1_PC0_AF2 + {PC0, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2N_PA12_AF6 + {PA12, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2N_PB0_AF6 + {PB0, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2N_PB14_AF6 + {PB14, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2_PA9_AF6 + {PA9, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2_PC1_AF2 + {PC1, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3N_PB15_AF4 + {PB15, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 4, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3N_PB1_AF6 + {PB1, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3N_PB9_AF12 + {PB9, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 12, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3N_PF0_AF6 + {PF0, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3_PA10_AF6 + {PA10, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3_PC2_AF2 + {PC2, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH4N_PC5_AF6 + {PC5, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH4_PA11_AF11 + {PA11, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 11, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH4_PC3_AF2 + {PC3, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_ETR_PA12_AF11 + // {PA12, TIM1_BASE_ADDRESS, 0, 11, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_ETR_PC4_AF2 + // {PC4, TIM1_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM2_CH1_PA0_AF1 + {PA0, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH1_PA15_AF1 + {PA15, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH1_PA5_AF1 + {PA5, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH2_PA1_AF1 + {PA1, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH2_PB3_AF1 + {PB3, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH3_PA2_AF1 + {PA2, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH3_PA9_AF10 + {PA9, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 10, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH3_PB10_AF1 + {PB10, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH4_PA10_AF10 + {PA10, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 10, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH4_PA3_AF1 + {PA3, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH4_PB11_AF1 + {PB11, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_ETR_PA0_AF14 + // {PA0, TIM2_BASE_ADDRESS, 0, 14, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_ETR_PA15_AF14 + // {PA15, TIM2_BASE_ADDRESS, 0, 14, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_ETR_PA5_AF2 + // {PA5, TIM2_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM3_CH1_PA6_AF2 + {PA6, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH1_PB4_AF2 + {PB4, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH1_PC6_AF2 + {PC6, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH2_PA4_AF2 + {PA4, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH2_PA7_AF2 + {PA7, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH2_PB5_AF2 + {PB5, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH2_PC7_AF2 + {PC7, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH3_PB0_AF2 + {PB0, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH3_PC8_AF2 + {PC8, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH4_PB1_AF2 + {PB1, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH4_PB7_AF10 + {PB7, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 10, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH4_PC9_AF2 + {PC9, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_ETR_PB3_AF10 + // {PB3, TIM3_BASE_ADDRESS, 0, 10, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_ETR_PD2_AF2 + // {PD2, TIM3_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM4_CH1_PA11_AF10 + {PA11, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 10, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH1_PB6_AF2 + {PB6, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH2_PA12_AF10 + {PA12, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 10, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH2_PB7_AF2 + {PB7, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH3_PA13_AF10 + {PA13, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 10, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH3_PB8_AF2 + {PB8, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH4_PB9_AF2 + {PB9, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_ETR_PA8_AF10 + // {PA8, TIM4_BASE_ADDRESS, 0, 10, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_ETR_PB3_AF2 + // {PB3, TIM4_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM8_BKIN2_PB6_AF10 + // {PB6, TIM8_BASE_ADDRESS, 0, 10, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_BKIN2_PC9_AF6 + // {PC9, TIM8_BASE_ADDRESS, 0, 6, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_BKIN_PA0_AF9 + // {PA0, TIM8_BASE_ADDRESS, 0, 9, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_BKIN_PA10_AF11 + // {PA10, TIM8_BASE_ADDRESS, 0, 11, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_BKIN_PA6_AF4 + // {PA6, TIM8_BASE_ADDRESS, 0, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_BKIN_PB7_AF5 + // {PB7, TIM8_BASE_ADDRESS, 0, 5, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_BKIN_PD2_AF4 + // {PD2, TIM8_BASE_ADDRESS, 0, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH1N_PA7_AF4 + {PA7, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH1N_PB3_AF4 + {PB3, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH1N_PC10_AF4 + {PC10, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH1_PA15_AF2 + {PA15, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH1_PB6_AF5 + {PB6, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 5, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH1_PC6_AF4 + {PC6, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH2N_PB0_AF4 + {PB0, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH2N_PB4_AF4 + {PB4, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH2N_PC11_AF4 + {PC11, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH2_PA14_AF5 + {PA14, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 5, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH2_PB8_AF10 + {PB8, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 10, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH2_PC7_AF4 + {PC7, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH3N_PB1_AF4 + {PB1, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH3N_PB5_AF3 + {PB5, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 3, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH3N_PC12_AF4 + {PC12, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH3_PB9_AF10 + {PB9, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 10, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH3_PC8_AF4 + {PC8, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH4N_PC13_AF6 + {PC13, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4N, 6, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH4_PC9_AF4 + {PC9, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_ETR_PA0_AF10 + // {PA0, TIM8_BASE_ADDRESS, 0, 10, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_ETR_PB6_AF6 + // {PB6, TIM8_BASE_ADDRESS, 0, 6, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM1_BKIN2_PE14_AF6 + // {PE14, TIM1_BASE_ADDRESS, 0, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN_PE15_AF2 + // {PE15, TIM1_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1N_PE8_AF2 + {PE8, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1_PE9_AF2 + {PE9, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2N_PE10_AF2 + {PE10, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2_PE11_AF2 + {PE11, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3N_PE12_AF2 + {PE12, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3_PE13_AF2 + {PE13, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH4N_PE15_AF6 + {PE15, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH4_PE14_AF2 + {PE14, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_ETR_PE7_AF2 + // {PE7, TIM1_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM8_BKIN2_PD1_AF6 + // {PD1, TIM8_BASE_ADDRESS, 0, 6, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH4N_PD0_AF6 + {PD0, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4N, 6, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH4_PD1_AF4 + {PD1, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM15_CH1_PF9_AF3 + {PF9, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 3, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH2_PF10_AF3 + {PF10, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 3, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM16_CH1_PE0_AF4 + {PE0, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 4, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM17_CH1_PE1_AF4 + {PE1, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 4, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM2_CH1_PD3_AF2 + {PD3, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH2_PD4_AF2 + {PD4, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH3_PD7_AF2 + {PD7, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH4_PD6_AF2 + {PD6, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_ETR_PD3_AF2 + // {PD3, TIM2_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM3_CH1_PE2_AF2 + {PE2, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH2_PE3_AF2 + {PE3, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH3_PE4_AF2 + {PE4, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH4_PE5_AF2 + {PE5, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM4_CH1_PD12_AF2 + {PD12, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH2_PD13_AF2 + {PD13, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH3_PD14_AF2 + {PD14, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH4_PD15_AF2 + {PD15, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_ETR_PE0_AF2 + // {PE0, TIM4_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + { HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_CHANNEL_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC } +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_TIM_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/tim/hal_ll_tim_pin_map/implementations/doc_ds_84/hal_ll_tim_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/tim/hal_ll_tim_pin_map/implementations/doc_ds_84/hal_ll_tim_pin_map.h new file mode 100644 index 000000000..155b37acb --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/tim/hal_ll_tim_pin_map/implementations/doc_ds_84/hal_ll_tim_pin_map.h @@ -0,0 +1,750 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_tim_pin_map.h + * @brief TIM HAL LOW LEVEL PIN MAP. + */ + +#ifndef _HAL_LL_TIM_PIN_MAP_H_ +#define _HAL_LL_TIM_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_tim_module_num(_module_num) (_module_num - 1) + +/*!< @brief Alternate pin function structure. */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + hal_ll_channel_t channel; + uint32_t af; + hal_ll_pin_name_t module_index; +} hal_ll_tim_pin_map_t; + +typedef enum +{ + HAL_LL_TIM_CHANNEL_0 = 0, + HAL_LL_TIM_CHANNEL_1, + HAL_LL_TIM_CHANNEL_2, + HAL_LL_TIM_CHANNEL_3, + HAL_LL_TIM_CHANNEL_4, + HAL_LL_TIM_CHANNEL_1N, + HAL_LL_TIM_CHANNEL_2N, + HAL_LL_TIM_CHANNEL_3N, + HAL_LL_TIM_CHANNEL_4N +} hal_ll_tim_channel_t; + +#ifdef TIM_MODULE_1 +#define TIM1_BASE_ADDRESS (0x40012C00UL) +#define TIM1_BASE_ADDR TIM1_BASE_ADDRESS +#define HAL_LL_TIM1_BASE_ADDR TIM1_BASE_ADDRESS +#define HAL_LL_TIM1_BASE_ADDRESS TIM1_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_2 +#define TIM2_BASE_ADDRESS (0x40000000UL) +#define TIM2_BASE_ADDR TIM2_BASE_ADDRESS +#define HAL_LL_TIM2_BASE_ADDR TIM2_BASE_ADDRESS +#define HAL_LL_TIM2_BASE_ADDRESS TIM2_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_3 +#define TIM3_BASE_ADDRESS (0x40000400UL) +#define TIM3_BASE_ADDR TIM3_BASE_ADDRESS +#define HAL_LL_TIM3_BASE_ADDR TIM3_BASE_ADDRESS +#define HAL_LL_TIM3_BASE_ADDRESS TIM3_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_4 +#define TIM4_BASE_ADDRESS (0x40000800UL) +#define TIM4_BASE_ADDR TIM4_BASE_ADDRESS +#define HAL_LL_TIM4_BASE_ADDR TIM4_BASE_ADDRESS +#define HAL_LL_TIM4_BASE_ADDRESS TIM4_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_5 +#define TIM5_BASE_ADDRESS (0x40000C00UL) +#define TIM5_BASE_ADDR TIM5_BASE_ADDRESS +#define HAL_LL_TIM5_BASE_ADDR TIM5_BASE_ADDRESS +#define HAL_LL_TIM5_BASE_ADDRESS TIM5_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_8 +#define TIM8_BASE_ADDRESS (0x40013400UL) +#define TIM8_BASE_ADDR TIM8_BASE_ADDRESS +#define HAL_LL_TIM8_BASE_ADDR TIM8_BASE_ADDRESS +#define HAL_LL_TIM8_BASE_ADDRESS TIM8_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_15 +#define TIM15_BASE_ADDRESS (0x40014000UL) +#define TIM15_BASE_ADDR TIM15_BASE_ADDRESS +#define HAL_LL_TIM15_BASE_ADDR TIM15_BASE_ADDRESS +#define HAL_LL_TIM15_BASE_ADDRESS TIM15_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_16 +#define TIM16_BASE_ADDRESS (0x40014400UL) +#define TIM16_BASE_ADDR TIM16_BASE_ADDRESS +#define HAL_LL_TIM16_BASE_ADDR TIM16_BASE_ADDRESS +#define HAL_LL_TIM16_BASE_ADDRESS TIM16_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_17 +#define TIM17_BASE_ADDRESS (0x40014800UL) +#define TIM17_BASE_ADDR TIM17_BASE_ADDRESS +#define HAL_LL_TIM17_BASE_ADDR TIM17_BASE_ADDRESS +#define HAL_LL_TIM17_BASE_ADDRESS TIM17_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_20 +#define TIM20_BASE_ADDRESS (0x40015000UL) +#define TIM20_BASE_ADDR TIM20_BASE_ADDRESS +#define HAL_LL_TIM20_BASE_ADDR TIM20_BASE_ADDRESS +#define HAL_LL_TIM20_BASE_ADDRESS TIM20_BASE_ADDRESS +#endif + +/*!< @brief TIM pins. */ +static const hal_ll_tim_pin_map_t _tim_map[] = { + #ifdef LPTIM1_ETR_PB6_AF11 + // {PB6, LPTIM1_BASE_ADDRESS, 0, 11, hal_ll_lptim_module_num(LPTIM_MODULE_1)}, + #endif + #ifdef LPTIM1_ETR_PC3_AF1 + // {PC3, LPTIM1_BASE_ADDRESS, 0, 1, hal_ll_lptim_module_num(LPTIM_MODULE_1)}, + #endif + #ifdef TIM15_BKIN_PA9_AF9 + // {PA9, TIM15_BASE_ADDRESS, 0, 9, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_BKIN_PC5_AF2 + // {PC5, TIM15_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH1N_PA1_AF9 + {PA1, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 9, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH1N_PB15_AF2 + {PB15, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 2, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH1_PA2_AF9 + {PA2, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 9, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH1_PB14_AF1 + {PB14, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH1_PF9_AF3 + {PF9, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 3, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH2_PA3_AF9 + {PA3, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 9, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH2_PB15_AF1 + {PB15, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 1, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH2_PF10_AF3 + {PF10, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 3, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM16_BKIN_PB5_AF1 + // {PB5, TIM16_BASE_ADDRESS, 0, 1, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1N_PA13_AF1 + {PA13, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 1, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1N_PB6_AF1 + {PB6, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 1, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1_PA12_AF1 + {PA12, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1_PA6_AF1 + {PA6, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1_PB4_AF1 + {PB4, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1_PB8_AF1 + {PB8, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1_PE0_AF4 + {PE0, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 4, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM17_BKIN_PA10_AF1 + // {PA10, TIM17_BASE_ADDRESS, 0, 1, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_BKIN_PB4_AF10 + // {PB4, TIM17_BASE_ADDRESS, 0, 10, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_CH1N_PB7_AF1 + {PB7, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 1, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_CH1_PA7_AF1 + {PA7, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_CH1_PB5_AF10 + {PB5, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 10, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_CH1_PB9_AF1 + {PB9, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_CH1_PE1_AF4 + {PE1, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 4, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM1_BKIN2_PA11_AF12 + // {PA11, TIM1_BASE_ADDRESS, 0, 12, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN2_PC3_AF6 + // {PC3, TIM1_BASE_ADDRESS, 0, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN2_PE14_AF6 + // {PE14, TIM1_BASE_ADDRESS, 0, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN_PA14_AF6 + // {PA14, TIM1_BASE_ADDRESS, 0, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN_PA15_AF9 + // {PA15, TIM1_BASE_ADDRESS, 0, 9, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN_PA6_AF6 + // {PA6, TIM1_BASE_ADDRESS, 0, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN_PB10_AF12 + // {PB10, TIM1_BASE_ADDRESS, 0, 12, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN_PB12_AF6 + // {PB12, TIM1_BASE_ADDRESS, 0, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN_PB8_AF12 + // {PB8, TIM1_BASE_ADDRESS, 0, 12, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN_PC13_AF2 + // {PC13, TIM1_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN_PE15_AF2 + // {PE15, TIM1_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1N_PA11_AF6 + {PA11, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1N_PA7_AF6 + {PA7, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1N_PB13_AF6 + {PB13, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1N_PC13_AF4 + {PC13, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 4, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1N_PE8_AF2 + {PE8, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1_PA8_AF6 + {PA8, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1_PC0_AF2 + {PC0, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1_PE9_AF2 + {PE9, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2N_PA12_AF6 + {PA12, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2N_PB0_AF6 + {PB0, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2N_PB14_AF6 + {PB14, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2N_PE10_AF2 + {PE10, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2_PA9_AF6 + {PA9, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2_PC1_AF2 + {PC1, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2_PE11_AF2 + {PE11, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3N_PB15_AF4 + {PB15, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 4, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3N_PB1_AF6 + {PB1, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3N_PB9_AF12 + {PB9, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 12, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3N_PE12_AF2 + {PE12, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3N_PF0_AF6 + {PF0, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3_PA10_AF6 + {PA10, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3_PC2_AF2 + {PC2, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3_PE13_AF2 + {PE13, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH4N_PC5_AF6 + {PC5, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH4N_PE15_AF6 + {PE15, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH4_PA11_AF11 + {PA11, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 11, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH4_PC3_AF2 + {PC3, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH4_PE14_AF2 + {PE14, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_ETR_PA12_AF11 + // {PA12, TIM1_BASE_ADDRESS, 0, 11, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_ETR_PC4_AF2 + // {PC4, TIM1_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_ETR_PE7_AF2 + // {PE7, TIM1_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM20_BKIN2_PF10_AF2 + // {PF10, TIM20_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_BKIN2_PF8_AF2 + // {PF8, TIM20_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_BKIN2_PG4_AF2 + // {PG4, TIM20_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_BKIN_PF7_AF2 + // {PF7, TIM20_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_BKIN_PF9_AF2 + // {PF9, TIM20_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_BKIN_PG3_AF2 + // {PG3, TIM20_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH1N_PE4_AF6 + {PE4, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 6, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH1N_PF4_AF3 + {PF4, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 3, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH1N_PG0_AF2 + {PG0, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH1_PB2_AF3 + {PB2, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 3, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH1_PE2_AF6 + {PE2, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 6, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH1_PF12_AF2 + {PF12, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH2N_PE5_AF6 + {PE5, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 6, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH2N_PF5_AF2 + {PF5, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH2N_PG1_AF2 + {PG1, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH2_PC2_AF6 + {PC2, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 6, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH2_PE3_AF6 + {PE3, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 6, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH2_PF13_AF2 + {PF13, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH3N_PE6_AF6 + {PE6, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 6, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH3N_PG2_AF2 + {PG2, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH3_PC8_AF6 + {PC8, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 6, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH3_PF14_AF2 + {PF14, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH3_PF2_AF2 + {PF2, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH4N_PE0_AF3 + {PE0, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4N, 3, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH4N_PG3_AF6 + {PG3, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4N, 6, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH4_PE1_AF6 + {PE1, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 6, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH4_PF15_AF2 + {PF15, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH4_PF3_AF2 + {PF3, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_ETR_PE0_AF6 + // {PE0, TIM20_BASE_ADDRESS, 0, 6, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_ETR_PF11_AF2 + // {PF11, TIM20_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM2_CH1_PA0_AF1 + {PA0, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH1_PA15_AF1 + {PA15, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH1_PA5_AF1 + {PA5, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH1_PD3_AF2 + {PD3, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH2_PA1_AF1 + {PA1, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH2_PB3_AF1 + {PB3, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH2_PD4_AF2 + {PD4, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH3_PA2_AF1 + {PA2, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH3_PA9_AF10 + {PA9, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 10, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH3_PB10_AF1 + {PB10, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH3_PD7_AF2 + {PD7, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH4_PA10_AF10 + {PA10, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 10, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH4_PA3_AF1 + {PA3, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH4_PB11_AF1 + {PB11, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH4_PD6_AF2 + {PD6, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_ETR_PA0_AF14 + // {PA0, TIM2_BASE_ADDRESS, 0, 14, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_ETR_PA15_AF14 + // {PA15, TIM2_BASE_ADDRESS, 0, 14, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_ETR_PA5_AF2 + // {PA5, TIM2_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_ETR_PD3_AF2 + // {PD3, TIM2_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM3_CH1_PA6_AF2 + {PA6, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH1_PB4_AF2 + {PB4, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH1_PC6_AF2 + {PC6, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH1_PE2_AF2 + {PE2, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH2_PA4_AF2 + {PA4, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH2_PA7_AF2 + {PA7, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH2_PB5_AF2 + {PB5, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH2_PC7_AF2 + {PC7, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH2_PE3_AF2 + {PE3, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH3_PB0_AF2 + {PB0, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH3_PC8_AF2 + {PC8, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH3_PE4_AF2 + {PE4, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH4_PB1_AF2 + {PB1, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH4_PB7_AF10 + {PB7, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 10, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH4_PC9_AF2 + {PC9, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH4_PE5_AF2 + {PE5, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_ETR_PB3_AF10 + // {PB3, TIM3_BASE_ADDRESS, 0, 10, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_ETR_PD2_AF2 + // {PD2, TIM3_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM4_CH1_PA11_AF10 + {PA11, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 10, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH1_PB6_AF2 + {PB6, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH1_PD12_AF2 + {PD12, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH2_PA12_AF10 + {PA12, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 10, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH2_PB7_AF2 + {PB7, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH2_PD13_AF2 + {PD13, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH3_PA13_AF10 + {PA13, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 10, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH3_PB8_AF2 + {PB8, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH3_PD14_AF2 + {PD14, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH4_PB9_AF2 + {PB9, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH4_PD15_AF2 + {PD15, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH4_PF6_AF2 + {PF6, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_ETR_PA8_AF10 + // {PA8, TIM4_BASE_ADDRESS, 0, 10, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_ETR_PB3_AF2 + // {PB3, TIM4_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_ETR_PE0_AF2 + // {PE0, TIM4_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM5_CH1_PA0_AF2 + {PA0, TIM5_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_CH1_PB2_AF2 + {PB2, TIM5_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_CH1_PF6_AF6 + {PF6, TIM5_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 6, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_CH2_PA1_AF2 + {PA1, TIM5_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_CH2_PC12_AF1 + {PC12, TIM5_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 1, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_CH2_PF7_AF6 + {PF7, TIM5_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 6, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_CH3_PA2_AF2 + {PA2, TIM5_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_CH3_PE8_AF1 + {PE8, TIM5_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 1, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_CH3_PF8_AF6 + {PF8, TIM5_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 6, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_CH4_PA3_AF2 + {PA3, TIM5_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_CH4_PE9_AF1 + {PE9, TIM5_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 1, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_CH4_PF9_AF6 + {PF9, TIM5_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 6, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_ETR_PB12_AF2 + // {PB12, TIM5_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_ETR_PD11_AF1 + // {PD11, TIM5_BASE_ADDRESS, 0, 1, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_ETR_PF6_AF1 + // {PF6, TIM5_BASE_ADDRESS, 0, 1, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM8_BKIN2_PB6_AF10 + // {PB6, TIM8_BASE_ADDRESS, 0, 10, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_BKIN2_PC9_AF6 + // {PC9, TIM8_BASE_ADDRESS, 0, 6, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_BKIN2_PD1_AF6 + // {PD1, TIM8_BASE_ADDRESS, 0, 6, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_BKIN_PA0_AF9 + // {PA0, TIM8_BASE_ADDRESS, 0, 9, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_BKIN_PA10_AF11 + // {PA10, TIM8_BASE_ADDRESS, 0, 11, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_BKIN_PA6_AF4 + // {PA6, TIM8_BASE_ADDRESS, 0, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_BKIN_PB7_AF5 + // {PB7, TIM8_BASE_ADDRESS, 0, 5, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_BKIN_PD2_AF4 + // {PD2, TIM8_BASE_ADDRESS, 0, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH1N_PA7_AF4 + {PA7, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH1N_PB3_AF4 + {PB3, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH1N_PC10_AF4 + {PC10, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH1_PA15_AF2 + {PA15, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH1_PB6_AF5 + {PB6, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 5, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH1_PC6_AF4 + {PC6, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH2N_PB0_AF4 + {PB0, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH2N_PB4_AF4 + {PB4, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH2N_PC11_AF4 + {PC11, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH2_PA14_AF5 + {PA14, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 5, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH2_PB8_AF10 + {PB8, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 10, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH2_PC7_AF4 + {PC7, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH3N_PB1_AF4 + {PB1, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH3N_PB5_AF3 + {PB5, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 3, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH3N_PC12_AF4 + {PC12, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH3_PB9_AF10 + {PB9, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 10, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH3_PC8_AF4 + {PC8, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH4N_PC13_AF6 + {PC13, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4N, 6, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH4N_PD0_AF6 + {PD0, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4N, 6, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH4_PC9_AF4 + {PC9, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH4_PD1_AF4 + {PD1, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_ETR_PA0_AF10 + // {PA0, TIM8_BASE_ADDRESS, 0, 10, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_ETR_PB6_AF6 + // {PB6, TIM8_BASE_ADDRESS, 0, 6, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM15_CH1N_PG9_AF14 + {PG9, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 14, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM20_BKIN_PG6_AF2 + // {PG6, TIM20_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_ETR_PG5_AF2 + // {PG5, TIM20_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + { HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_CHANNEL_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC } +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_TIM_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/tim/hal_ll_tim_pin_map/implementations/doc_ds_85/hal_ll_tim_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/tim/hal_ll_tim_pin_map/implementations/doc_ds_85/hal_ll_tim_pin_map.h new file mode 100644 index 000000000..bc06f169d --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/tim/hal_ll_tim_pin_map/implementations/doc_ds_85/hal_ll_tim_pin_map.h @@ -0,0 +1,786 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_tim_pin_map.h + * @brief TIM HAL LOW LEVEL PIN MAP. + */ + +#ifndef _HAL_LL_TIM_PIN_MAP_H_ +#define _HAL_LL_TIM_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_tim_module_num(_module_num) (_module_num - 1) + +/*!< @brief Alternate pin function structure. */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + hal_ll_channel_t channel; + uint32_t af; + hal_ll_pin_name_t module_index; +} hal_ll_tim_pin_map_t; + +typedef enum +{ + HAL_LL_TIM_CHANNEL_0 = 0, + HAL_LL_TIM_CHANNEL_1, + HAL_LL_TIM_CHANNEL_2, + HAL_LL_TIM_CHANNEL_3, + HAL_LL_TIM_CHANNEL_4, + HAL_LL_TIM_CHANNEL_1N, + HAL_LL_TIM_CHANNEL_2N, + HAL_LL_TIM_CHANNEL_3N, + HAL_LL_TIM_CHANNEL_4N +} hal_ll_tim_channel_t; + +#ifdef TIM_MODULE_1 +#define TIM1_BASE_ADDRESS (0x40012C00UL) +#define TIM1_BASE_ADDR TIM1_BASE_ADDRESS +#define HAL_LL_TIM1_BASE_ADDR TIM1_BASE_ADDRESS +#define HAL_LL_TIM1_BASE_ADDRESS TIM1_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_2 +#define TIM2_BASE_ADDRESS (0x40000000UL) +#define TIM2_BASE_ADDR TIM2_BASE_ADDRESS +#define HAL_LL_TIM2_BASE_ADDR TIM2_BASE_ADDRESS +#define HAL_LL_TIM2_BASE_ADDRESS TIM2_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_3 +#define TIM3_BASE_ADDRESS (0x40000400UL) +#define TIM3_BASE_ADDR TIM3_BASE_ADDRESS +#define HAL_LL_TIM3_BASE_ADDR TIM3_BASE_ADDRESS +#define HAL_LL_TIM3_BASE_ADDRESS TIM3_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_4 +#define TIM4_BASE_ADDRESS (0x40000800UL) +#define TIM4_BASE_ADDR TIM4_BASE_ADDRESS +#define HAL_LL_TIM4_BASE_ADDR TIM4_BASE_ADDRESS +#define HAL_LL_TIM4_BASE_ADDRESS TIM4_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_5 +#define TIM5_BASE_ADDRESS (0x40000C00UL) +#define TIM5_BASE_ADDR TIM5_BASE_ADDRESS +#define HAL_LL_TIM5_BASE_ADDR TIM5_BASE_ADDRESS +#define HAL_LL_TIM5_BASE_ADDRESS TIM5_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_8 +#define TIM8_BASE_ADDRESS (0x40013400UL) +#define TIM8_BASE_ADDR TIM8_BASE_ADDRESS +#define HAL_LL_TIM8_BASE_ADDR TIM8_BASE_ADDRESS +#define HAL_LL_TIM8_BASE_ADDRESS TIM8_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_15 +#define TIM15_BASE_ADDRESS (0x40014000UL) +#define TIM15_BASE_ADDR TIM15_BASE_ADDRESS +#define HAL_LL_TIM15_BASE_ADDR TIM15_BASE_ADDRESS +#define HAL_LL_TIM15_BASE_ADDRESS TIM15_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_16 +#define TIM16_BASE_ADDRESS (0x40014400UL) +#define TIM16_BASE_ADDR TIM16_BASE_ADDRESS +#define HAL_LL_TIM16_BASE_ADDR TIM16_BASE_ADDRESS +#define HAL_LL_TIM16_BASE_ADDRESS TIM16_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_17 +#define TIM17_BASE_ADDRESS (0x40014800UL) +#define TIM17_BASE_ADDR TIM17_BASE_ADDRESS +#define HAL_LL_TIM17_BASE_ADDR TIM17_BASE_ADDRESS +#define HAL_LL_TIM17_BASE_ADDRESS TIM17_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_20 +#define TIM20_BASE_ADDRESS (0x40015000UL) +#define TIM20_BASE_ADDR TIM20_BASE_ADDRESS +#define HAL_LL_TIM20_BASE_ADDR TIM20_BASE_ADDRESS +#define HAL_LL_TIM20_BASE_ADDRESS TIM20_BASE_ADDRESS +#endif + +/*!< @brief TIM pins. */ +static const hal_ll_tim_pin_map_t _tim_map[] = { + #ifdef HRTIM1_CHA1_PA8_AF13 + // {PA8, HRTIM1_BASE_ADDRESS, 0, 13, hal_ll_hrtim_module_num(HRTIM_MODULE_1)}, + #endif + #ifdef HRTIM1_CHA2_PA9_AF13 + // {PA9, HRTIM1_BASE_ADDRESS, 0, 13, hal_ll_hrtim_module_num(HRTIM_MODULE_1)}, + #endif + #ifdef HRTIM1_CHB1_PA10_AF13 + // {PA10, HRTIM1_BASE_ADDRESS, 0, 13, hal_ll_hrtim_module_num(HRTIM_MODULE_1)}, + #endif + #ifdef HRTIM1_CHB2_PA11_AF13 + // {PA11, HRTIM1_BASE_ADDRESS, 0, 13, hal_ll_hrtim_module_num(HRTIM_MODULE_1)}, + #endif + #ifdef HRTIM1_CHC1_PB12_AF13 + // {PB12, HRTIM1_BASE_ADDRESS, 0, 13, hal_ll_hrtim_module_num(HRTIM_MODULE_1)}, + #endif + #ifdef HRTIM1_CHC2_PB13_AF13 + // {PB13, HRTIM1_BASE_ADDRESS, 0, 13, hal_ll_hrtim_module_num(HRTIM_MODULE_1)}, + #endif + #ifdef HRTIM1_CHD1_PB14_AF13 + // {PB14, HRTIM1_BASE_ADDRESS, 0, 13, hal_ll_hrtim_module_num(HRTIM_MODULE_1)}, + #endif + #ifdef HRTIM1_CHD2_PB15_AF13 + // {PB15, HRTIM1_BASE_ADDRESS, 0, 13, hal_ll_hrtim_module_num(HRTIM_MODULE_1)}, + #endif + #ifdef HRTIM1_CHF1_PC6_AF13 + // {PC6, HRTIM1_BASE_ADDRESS, 0, 13, hal_ll_hrtim_module_num(HRTIM_MODULE_1)}, + #endif + #ifdef LPTIM1_ETR_PB6_AF11 + // {PB6, LPTIM1_BASE_ADDRESS, 0, 11, hal_ll_lptim_module_num(LPTIM_MODULE_1)}, + #endif + #ifdef TIM15_BKIN_PA9_AF9 + // {PA9, TIM15_BASE_ADDRESS, 0, 9, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH1N_PA1_AF9 + {PA1, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 9, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH1N_PB15_AF2 + {PB15, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 2, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH1_PA2_AF9 + {PA2, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 9, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH1_PB14_AF1 + {PB14, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH2_PA3_AF9 + {PA3, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 9, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH2_PB15_AF1 + {PB15, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 1, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM16_BKIN_PB5_AF1 + // {PB5, TIM16_BASE_ADDRESS, 0, 1, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1N_PA13_AF1 + {PA13, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 1, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1N_PB6_AF1 + {PB6, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 1, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1_PA12_AF1 + {PA12, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1_PA6_AF1 + {PA6, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1_PB4_AF1 + {PB4, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1_PB8_AF1 + {PB8, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM17_BKIN_PA10_AF1 + // {PA10, TIM17_BASE_ADDRESS, 0, 1, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_BKIN_PB4_AF10 + // {PB4, TIM17_BASE_ADDRESS, 0, 10, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_CH1N_PB7_AF1 + {PB7, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 1, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_CH1_PA7_AF1 + {PA7, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_CH1_PB5_AF10 + {PB5, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 10, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_CH1_PB9_AF1 + {PB9, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM1_BKIN2_PA11_AF12 + // {PA11, TIM1_BASE_ADDRESS, 0, 12, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN_PA14_AF6 + // {PA14, TIM1_BASE_ADDRESS, 0, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN_PA15_AF9 + // {PA15, TIM1_BASE_ADDRESS, 0, 9, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN_PA6_AF6 + // {PA6, TIM1_BASE_ADDRESS, 0, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN_PB10_AF12 + // {PB10, TIM1_BASE_ADDRESS, 0, 12, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN_PB12_AF6 + // {PB12, TIM1_BASE_ADDRESS, 0, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN_PB8_AF12 + // {PB8, TIM1_BASE_ADDRESS, 0, 12, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN_PC13_AF2 + // {PC13, TIM1_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1N_PA11_AF6 + {PA11, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1N_PA7_AF6 + {PA7, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1N_PB13_AF6 + {PB13, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1N_PC13_AF4 + {PC13, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 4, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1_PA8_AF6 + {PA8, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2N_PA12_AF6 + {PA12, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2N_PB0_AF6 + {PB0, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2N_PB14_AF6 + {PB14, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2_PA9_AF6 + {PA9, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3N_PB15_AF4 + {PB15, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 4, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3N_PB1_AF6 + {PB1, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3N_PB9_AF12 + {PB9, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 12, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3N_PF0_AF6 + {PF0, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3_PA10_AF6 + {PA10, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH4_PA11_AF11 + {PA11, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 11, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_ETR_PA12_AF11 + // {PA12, TIM1_BASE_ADDRESS, 0, 11, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_ETR_PC4_AF2 + // {PC4, TIM1_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM20_CH1_PB2_AF3 + {PB2, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 3, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM2_CH1_PA0_AF1 + {PA0, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH1_PA15_AF1 + {PA15, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH1_PA5_AF1 + {PA5, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH2_PA1_AF1 + {PA1, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH2_PB3_AF1 + {PB3, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH3_PA2_AF1 + {PA2, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH3_PA9_AF10 + {PA9, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 10, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH3_PB10_AF1 + {PB10, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH4_PA10_AF10 + {PA10, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 10, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH4_PA3_AF1 + {PA3, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH4_PB11_AF1 + {PB11, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_ETR_PA0_AF14 + // {PA0, TIM2_BASE_ADDRESS, 0, 14, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_ETR_PA15_AF14 + // {PA15, TIM2_BASE_ADDRESS, 0, 14, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_ETR_PA5_AF2 + // {PA5, TIM2_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM3_CH1_PA6_AF2 + {PA6, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH1_PB4_AF2 + {PB4, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH1_PC6_AF2 + {PC6, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH2_PA4_AF2 + {PA4, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH2_PA7_AF2 + {PA7, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH2_PB5_AF2 + {PB5, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH3_PB0_AF2 + {PB0, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH4_PB1_AF2 + {PB1, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH4_PB7_AF10 + {PB7, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 10, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_ETR_PB3_AF10 + // {PB3, TIM3_BASE_ADDRESS, 0, 10, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM4_CH1_PA11_AF10 + {PA11, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 10, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH1_PB6_AF2 + {PB6, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH2_PA12_AF10 + {PA12, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 10, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH2_PB7_AF2 + {PB7, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH3_PA13_AF10 + {PA13, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 10, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH3_PB8_AF2 + {PB8, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH4_PB9_AF2 + {PB9, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_ETR_PA8_AF10 + // {PA8, TIM4_BASE_ADDRESS, 0, 10, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_ETR_PB3_AF2 + // {PB3, TIM4_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM5_CH1_PA0_AF2 + {PA0, TIM5_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_CH1_PB2_AF2 + {PB2, TIM5_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_CH2_PA1_AF2 + {PA1, TIM5_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_CH3_PA2_AF2 + {PA2, TIM5_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_CH4_PA3_AF2 + {PA3, TIM5_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_ETR_PB12_AF2 + // {PB12, TIM5_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM8_BKIN2_PB6_AF10 + // {PB6, TIM8_BASE_ADDRESS, 0, 10, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_BKIN_PA0_AF9 + // {PA0, TIM8_BASE_ADDRESS, 0, 9, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_BKIN_PA10_AF11 + // {PA10, TIM8_BASE_ADDRESS, 0, 11, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_BKIN_PA6_AF4 + // {PA6, TIM8_BASE_ADDRESS, 0, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_BKIN_PB7_AF5 + // {PB7, TIM8_BASE_ADDRESS, 0, 5, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH1N_PA7_AF4 + {PA7, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH1N_PB3_AF4 + {PB3, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH1N_PC10_AF4 + {PC10, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH1_PA15_AF2 + {PA15, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH1_PB6_AF5 + {PB6, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 5, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH1_PC6_AF4 + {PC6, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH2N_PB0_AF4 + {PB0, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH2N_PB4_AF4 + {PB4, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH2N_PC11_AF4 + {PC11, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH2_PA14_AF5 + {PA14, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 5, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH2_PB8_AF10 + {PB8, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 10, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH3N_PB1_AF4 + {PB1, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH3N_PB5_AF3 + {PB5, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 3, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH3_PB9_AF10 + {PB9, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 10, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH4N_PC13_AF6 + {PC13, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4N, 6, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_ETR_PA0_AF10 + // {PA0, TIM8_BASE_ADDRESS, 0, 10, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_ETR_PB6_AF6 + // {PB6, TIM8_BASE_ADDRESS, 0, 6, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef HRTIM1_CHE1_PC8_AF3 + // {PC8, HRTIM1_BASE_ADDRESS, 0, 3, hal_ll_hrtim_module_num(HRTIM_MODULE_1)}, + #endif + #ifdef HRTIM1_CHE2_PC9_AF3 + // {PC9, HRTIM1_BASE_ADDRESS, 0, 3, hal_ll_hrtim_module_num(HRTIM_MODULE_1)}, + #endif + #ifdef HRTIM1_CHF2_PC7_AF13 + // {PC7, HRTIM1_BASE_ADDRESS, 0, 13, hal_ll_hrtim_module_num(HRTIM_MODULE_1)}, + #endif + #ifdef LPTIM1_ETR_PC3_AF1 + // {PC3, LPTIM1_BASE_ADDRESS, 0, 1, hal_ll_lptim_module_num(LPTIM_MODULE_1)}, + #endif + #ifdef TIM15_BKIN_PC5_AF2 + // {PC5, TIM15_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM1_BKIN2_PC3_AF6 + // {PC3, TIM1_BASE_ADDRESS, 0, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1_PC0_AF2 + {PC0, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2_PC1_AF2 + {PC1, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3_PC2_AF2 + {PC2, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH4N_PC5_AF6 + {PC5, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH4_PC3_AF2 + {PC3, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM20_CH2_PC2_AF6 + {PC2, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 6, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH3_PC8_AF6 + {PC8, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 6, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM3_CH2_PC7_AF2 + {PC7, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH3_PC8_AF2 + {PC8, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH4_PC9_AF2 + {PC9, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_ETR_PD2_AF2 + // {PD2, TIM3_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM5_CH2_PC12_AF1 + {PC12, TIM5_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 1, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM8_BKIN2_PC9_AF6 + // {PC9, TIM8_BASE_ADDRESS, 0, 6, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_BKIN_PD2_AF4 + // {PD2, TIM8_BASE_ADDRESS, 0, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH2_PC7_AF4 + {PC7, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH3N_PC12_AF4 + {PC12, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH3_PC8_AF4 + {PC8, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH4_PC9_AF4 + {PC9, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM15_CH1_PF9_AF3 + {PF9, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 3, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH2_PF10_AF3 + {PF10, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 3, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM16_CH1_PE0_AF4 + {PE0, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 4, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM17_CH1_PE1_AF4 + {PE1, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 4, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM1_BKIN2_PE14_AF6 + // {PE14, TIM1_BASE_ADDRESS, 0, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN_PE15_AF2 + // {PE15, TIM1_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1N_PE8_AF2 + {PE8, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1_PE9_AF2 + {PE9, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2N_PE10_AF2 + {PE10, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2_PE11_AF2 + {PE11, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3N_PE12_AF2 + {PE12, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3_PE13_AF2 + {PE13, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH4N_PE15_AF6 + {PE15, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH4_PE14_AF2 + {PE14, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_ETR_PE7_AF2 + // {PE7, TIM1_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM20_BKIN2_PF10_AF2 + // {PF10, TIM20_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_BKIN_PF9_AF2 + // {PF9, TIM20_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH1N_PE4_AF6 + {PE4, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 6, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH1_PE2_AF6 + {PE2, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 6, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH2N_PE5_AF6 + {PE5, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 6, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH2_PE3_AF6 + {PE3, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 6, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH3N_PE6_AF6 + {PE6, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 6, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH3_PF2_AF2 + {PF2, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH4N_PE0_AF3 + {PE0, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4N, 3, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH4_PE1_AF6 + {PE1, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 6, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_ETR_PE0_AF6 + // {PE0, TIM20_BASE_ADDRESS, 0, 6, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM2_CH1_PD3_AF2 + {PD3, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH2_PD4_AF2 + {PD4, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH3_PD7_AF2 + {PD7, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH4_PD6_AF2 + {PD6, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_ETR_PD3_AF2 + // {PD3, TIM2_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM3_CH1_PE2_AF2 + {PE2, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH2_PE3_AF2 + {PE3, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH3_PE4_AF2 + {PE4, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH4_PE5_AF2 + {PE5, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM4_CH1_PD12_AF2 + {PD12, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH2_PD13_AF2 + {PD13, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH3_PD14_AF2 + {PD14, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH4_PD15_AF2 + {PD15, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_ETR_PE0_AF2 + // {PE0, TIM4_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM5_CH3_PE8_AF1 + {PE8, TIM5_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 1, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_CH4_PE9_AF1 + {PE9, TIM5_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 1, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_CH4_PF9_AF6 + {PF9, TIM5_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 6, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_ETR_PD11_AF1 + // {PD11, TIM5_BASE_ADDRESS, 0, 1, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM8_BKIN2_PD1_AF6 + // {PD1, TIM8_BASE_ADDRESS, 0, 6, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH4N_PD0_AF6 + {PD0, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4N, 6, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH4_PD1_AF4 + {PD1, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM20_BKIN2_PF8_AF2 + // {PF8, TIM20_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_BKIN2_PG4_AF2 + // {PG4, TIM20_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_BKIN_PF7_AF2 + // {PF7, TIM20_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_BKIN_PG3_AF2 + // {PG3, TIM20_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH1N_PF4_AF3 + {PF4, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 3, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH1N_PG0_AF2 + {PG0, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH1_PF12_AF2 + {PF12, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH2N_PF5_AF2 + {PF5, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH2N_PG1_AF2 + {PG1, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH2_PF13_AF2 + {PF13, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH3N_PG2_AF2 + {PG2, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH3_PF14_AF2 + {PF14, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH4N_PG3_AF6 + {PG3, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4N, 6, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH4_PF15_AF2 + {PF15, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH4_PF3_AF2 + {PF3, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_ETR_PF11_AF2 + // {PF11, TIM20_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM4_CH4_PF6_AF2 + {PF6, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM5_CH1_PF6_AF6 + {PF6, TIM5_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 6, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_CH2_PF7_AF6 + {PF7, TIM5_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 6, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_CH3_PF8_AF6 + {PF8, TIM5_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 6, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_ETR_PF6_AF1 + // {PF6, TIM5_BASE_ADDRESS, 0, 1, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM15_CH1N_PG9_AF14 + {PG9, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 14, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM20_BKIN_PG6_AF2 + // {PG6, TIM20_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_ETR_PG5_AF2 + // {PG5, TIM20_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + { HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_CHANNEL_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC } +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_TIM_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/tim/hal_ll_tim_pin_map/implementations/doc_ds_86/hal_ll_tim_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/tim/hal_ll_tim_pin_map/implementations/doc_ds_86/hal_ll_tim_pin_map.h new file mode 100644 index 000000000..d833c1aab --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/tim/hal_ll_tim_pin_map/implementations/doc_ds_86/hal_ll_tim_pin_map.h @@ -0,0 +1,750 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_tim_pin_map.h + * @brief TIM HAL LOW LEVEL PIN MAP. + */ + +#ifndef _HAL_LL_TIM_PIN_MAP_H_ +#define _HAL_LL_TIM_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_tim_module_num(_module_num) (_module_num - 1) + +/*!< @brief Alternate pin function structure. */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + hal_ll_channel_t channel; + uint32_t af; + hal_ll_pin_name_t module_index; +} hal_ll_tim_pin_map_t; + +typedef enum +{ + HAL_LL_TIM_CHANNEL_0 = 0, + HAL_LL_TIM_CHANNEL_1, + HAL_LL_TIM_CHANNEL_2, + HAL_LL_TIM_CHANNEL_3, + HAL_LL_TIM_CHANNEL_4, + HAL_LL_TIM_CHANNEL_1N, + HAL_LL_TIM_CHANNEL_2N, + HAL_LL_TIM_CHANNEL_3N, + HAL_LL_TIM_CHANNEL_4N +} hal_ll_tim_channel_t; + +#ifdef TIM_MODULE_1 +#define TIM1_BASE_ADDRESS (0x40012C00UL) +#define TIM1_BASE_ADDR TIM1_BASE_ADDRESS +#define HAL_LL_TIM1_BASE_ADDR TIM1_BASE_ADDRESS +#define HAL_LL_TIM1_BASE_ADDRESS TIM1_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_2 +#define TIM2_BASE_ADDRESS (0x40000000UL) +#define TIM2_BASE_ADDR TIM2_BASE_ADDRESS +#define HAL_LL_TIM2_BASE_ADDR TIM2_BASE_ADDRESS +#define HAL_LL_TIM2_BASE_ADDRESS TIM2_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_3 +#define TIM3_BASE_ADDRESS (0x40000400UL) +#define TIM3_BASE_ADDR TIM3_BASE_ADDRESS +#define HAL_LL_TIM3_BASE_ADDR TIM3_BASE_ADDRESS +#define HAL_LL_TIM3_BASE_ADDRESS TIM3_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_4 +#define TIM4_BASE_ADDRESS (0x40000800UL) +#define TIM4_BASE_ADDR TIM4_BASE_ADDRESS +#define HAL_LL_TIM4_BASE_ADDR TIM4_BASE_ADDRESS +#define HAL_LL_TIM4_BASE_ADDRESS TIM4_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_5 +#define TIM5_BASE_ADDRESS (0x40000C00UL) +#define TIM5_BASE_ADDR TIM5_BASE_ADDRESS +#define HAL_LL_TIM5_BASE_ADDR TIM5_BASE_ADDRESS +#define HAL_LL_TIM5_BASE_ADDRESS TIM5_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_8 +#define TIM8_BASE_ADDRESS (0x40013400UL) +#define TIM8_BASE_ADDR TIM8_BASE_ADDRESS +#define HAL_LL_TIM8_BASE_ADDR TIM8_BASE_ADDRESS +#define HAL_LL_TIM8_BASE_ADDRESS TIM8_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_15 +#define TIM15_BASE_ADDRESS (0x40014000UL) +#define TIM15_BASE_ADDR TIM15_BASE_ADDRESS +#define HAL_LL_TIM15_BASE_ADDR TIM15_BASE_ADDRESS +#define HAL_LL_TIM15_BASE_ADDRESS TIM15_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_16 +#define TIM16_BASE_ADDRESS (0x40014400UL) +#define TIM16_BASE_ADDR TIM16_BASE_ADDRESS +#define HAL_LL_TIM16_BASE_ADDR TIM16_BASE_ADDRESS +#define HAL_LL_TIM16_BASE_ADDRESS TIM16_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_17 +#define TIM17_BASE_ADDRESS (0x40014800UL) +#define TIM17_BASE_ADDR TIM17_BASE_ADDRESS +#define HAL_LL_TIM17_BASE_ADDR TIM17_BASE_ADDRESS +#define HAL_LL_TIM17_BASE_ADDRESS TIM17_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_20 +#define TIM20_BASE_ADDRESS (0x40015000UL) +#define TIM20_BASE_ADDR TIM20_BASE_ADDRESS +#define HAL_LL_TIM20_BASE_ADDR TIM20_BASE_ADDRESS +#define HAL_LL_TIM20_BASE_ADDRESS TIM20_BASE_ADDRESS +#endif + +/*!< @brief TIM pins. */ +static const hal_ll_tim_pin_map_t _tim_map[] = { + #ifdef LPTIM1_ETR_PB6_AF11 + // {PB6, LPTIM1_BASE_ADDRESS, 0, 11, hal_ll_lptim_module_num(LPTIM_MODULE_1)}, + #endif + #ifdef LPTIM1_ETR_PC3_AF1 + // {PC3, LPTIM1_BASE_ADDRESS, 0, 1, hal_ll_lptim_module_num(LPTIM_MODULE_1)}, + #endif + #ifdef TIM15_BKIN_PA9_AF9 + // {PA9, TIM15_BASE_ADDRESS, 0, 9, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_BKIN_PC5_AF2 + // {PC5, TIM15_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH1N_PA1_AF9 + {PA1, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 9, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH1N_PB15_AF2 + {PB15, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 2, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH1N_PG9_AF14 + {PG9, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 14, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH1_PA2_AF9 + {PA2, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 9, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH1_PB14_AF1 + {PB14, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH1_PF9_AF3 + {PF9, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 3, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH2_PA3_AF9 + {PA3, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 9, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH2_PB15_AF1 + {PB15, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 1, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH2_PF10_AF3 + {PF10, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 3, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM16_BKIN_PB5_AF1 + // {PB5, TIM16_BASE_ADDRESS, 0, 1, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1N_PA13_AF1 + {PA13, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 1, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1N_PB6_AF1 + {PB6, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 1, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1_PA12_AF1 + {PA12, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1_PA6_AF1 + {PA6, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1_PB4_AF1 + {PB4, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1_PB8_AF1 + {PB8, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1_PE0_AF4 + {PE0, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 4, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM17_BKIN_PA10_AF1 + // {PA10, TIM17_BASE_ADDRESS, 0, 1, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_BKIN_PB4_AF10 + // {PB4, TIM17_BASE_ADDRESS, 0, 10, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_CH1N_PB7_AF1 + {PB7, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 1, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_CH1_PA7_AF1 + {PA7, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_CH1_PB5_AF10 + {PB5, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 10, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_CH1_PB9_AF1 + {PB9, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_CH1_PE1_AF4 + {PE1, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 4, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM1_BKIN2_PA11_AF12 + // {PA11, TIM1_BASE_ADDRESS, 0, 12, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN2_PC3_AF6 + // {PC3, TIM1_BASE_ADDRESS, 0, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN2_PE14_AF6 + // {PE14, TIM1_BASE_ADDRESS, 0, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN_PA14_AF6 + // {PA14, TIM1_BASE_ADDRESS, 0, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN_PA15_AF9 + // {PA15, TIM1_BASE_ADDRESS, 0, 9, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN_PA6_AF6 + // {PA6, TIM1_BASE_ADDRESS, 0, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN_PB10_AF12 + // {PB10, TIM1_BASE_ADDRESS, 0, 12, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN_PB12_AF6 + // {PB12, TIM1_BASE_ADDRESS, 0, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN_PB8_AF12 + // {PB8, TIM1_BASE_ADDRESS, 0, 12, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN_PC13_AF2 + // {PC13, TIM1_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN_PE15_AF2 + // {PE15, TIM1_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1N_PA11_AF6 + {PA11, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1N_PA7_AF6 + {PA7, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1N_PB13_AF6 + {PB13, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1N_PC13_AF4 + {PC13, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 4, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1N_PE8_AF2 + {PE8, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1_PA8_AF6 + {PA8, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1_PC0_AF2 + {PC0, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1_PE9_AF2 + {PE9, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2N_PA12_AF6 + {PA12, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2N_PB0_AF6 + {PB0, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2N_PB14_AF6 + {PB14, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2N_PE10_AF2 + {PE10, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2_PA9_AF6 + {PA9, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2_PC1_AF2 + {PC1, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2_PE11_AF2 + {PE11, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3N_PB15_AF4 + {PB15, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 4, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3N_PB1_AF6 + {PB1, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3N_PB9_AF12 + {PB9, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 12, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3N_PE12_AF2 + {PE12, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3N_PF0_AF6 + {PF0, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3_PA10_AF6 + {PA10, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3_PC2_AF2 + {PC2, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3_PE13_AF2 + {PE13, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH4N_PC5_AF6 + {PC5, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH4N_PE15_AF6 + {PE15, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH4_PA11_AF11 + {PA11, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 11, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH4_PC3_AF2 + {PC3, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH4_PE14_AF2 + {PE14, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_ETR_PA12_AF11 + // {PA12, TIM1_BASE_ADDRESS, 0, 11, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_ETR_PC4_AF2 + // {PC4, TIM1_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_ETR_PE7_AF2 + // {PE7, TIM1_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM20_BKIN2_PF10_AF2 + // {PF10, TIM20_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_BKIN2_PF8_AF2 + // {PF8, TIM20_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_BKIN2_PG4_AF2 + // {PG4, TIM20_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_BKIN_PF7_AF2 + // {PF7, TIM20_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_BKIN_PF9_AF2 + // {PF9, TIM20_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_BKIN_PG3_AF2 + // {PG3, TIM20_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_BKIN_PG6_AF2 + // {PG6, TIM20_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH1N_PE4_AF6 + {PE4, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 6, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH1N_PF4_AF3 + {PF4, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 3, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH1N_PG0_AF2 + {PG0, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH1_PB2_AF3 + {PB2, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 3, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH1_PE2_AF6 + {PE2, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 6, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH1_PF12_AF2 + {PF12, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH2N_PE5_AF6 + {PE5, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 6, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH2N_PF5_AF2 + {PF5, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH2N_PG1_AF2 + {PG1, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH2_PC2_AF6 + {PC2, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 6, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH2_PE3_AF6 + {PE3, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 6, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH2_PF13_AF2 + {PF13, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH3N_PE6_AF6 + {PE6, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 6, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH3N_PG2_AF2 + {PG2, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH3_PC8_AF6 + {PC8, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 6, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH3_PF14_AF2 + {PF14, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH3_PF2_AF2 + {PF2, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH4N_PE0_AF3 + {PE0, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4N, 3, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH4N_PG3_AF6 + {PG3, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4N, 6, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH4_PE1_AF6 + {PE1, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 6, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH4_PF15_AF2 + {PF15, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH4_PF3_AF2 + {PF3, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_ETR_PE0_AF6 + // {PE0, TIM20_BASE_ADDRESS, 0, 6, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_ETR_PF11_AF2 + // {PF11, TIM20_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_ETR_PG5_AF2 + // {PG5, TIM20_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM2_CH1_PA0_AF1 + {PA0, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH1_PA15_AF1 + {PA15, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH1_PA5_AF1 + {PA5, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH1_PD3_AF2 + {PD3, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH2_PA1_AF1 + {PA1, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH2_PB3_AF1 + {PB3, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH2_PD4_AF2 + {PD4, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH3_PA2_AF1 + {PA2, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH3_PA9_AF10 + {PA9, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 10, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH3_PB10_AF1 + {PB10, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH3_PD7_AF2 + {PD7, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH4_PA10_AF10 + {PA10, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 10, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH4_PA3_AF1 + {PA3, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH4_PB11_AF1 + {PB11, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH4_PD6_AF2 + {PD6, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_ETR_PA0_AF14 + // {PA0, TIM2_BASE_ADDRESS, 0, 14, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_ETR_PA15_AF14 + // {PA15, TIM2_BASE_ADDRESS, 0, 14, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_ETR_PA5_AF2 + // {PA5, TIM2_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_ETR_PD3_AF2 + // {PD3, TIM2_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM3_CH1_PA6_AF2 + {PA6, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH1_PB4_AF2 + {PB4, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH1_PC6_AF2 + {PC6, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH1_PE2_AF2 + {PE2, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH2_PA4_AF2 + {PA4, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH2_PA7_AF2 + {PA7, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH2_PB5_AF2 + {PB5, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH2_PC7_AF2 + {PC7, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH2_PE3_AF2 + {PE3, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH3_PB0_AF2 + {PB0, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH3_PC8_AF2 + {PC8, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH3_PE4_AF2 + {PE4, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH4_PB1_AF2 + {PB1, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH4_PB7_AF10 + {PB7, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 10, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH4_PC9_AF2 + {PC9, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH4_PE5_AF2 + {PE5, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_ETR_PB3_AF10 + // {PB3, TIM3_BASE_ADDRESS, 0, 10, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_ETR_PD2_AF2 + // {PD2, TIM3_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM4_CH1_PA11_AF10 + {PA11, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 10, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH1_PB6_AF2 + {PB6, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH1_PD12_AF2 + {PD12, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH2_PA12_AF10 + {PA12, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 10, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH2_PB7_AF2 + {PB7, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH2_PD13_AF2 + {PD13, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH3_PA13_AF10 + {PA13, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 10, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH3_PB8_AF2 + {PB8, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH3_PD14_AF2 + {PD14, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH4_PB9_AF2 + {PB9, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH4_PD15_AF2 + {PD15, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH4_PF6_AF2 + {PF6, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_ETR_PA8_AF10 + // {PA8, TIM4_BASE_ADDRESS, 0, 10, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_ETR_PB3_AF2 + // {PB3, TIM4_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_ETR_PE0_AF2 + // {PE0, TIM4_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM5_CH1_PA0_AF2 + {PA0, TIM5_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_CH1_PB2_AF2 + {PB2, TIM5_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_CH1_PF6_AF6 + {PF6, TIM5_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 6, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_CH2_PA1_AF2 + {PA1, TIM5_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_CH2_PC12_AF1 + {PC12, TIM5_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 1, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_CH2_PF7_AF6 + {PF7, TIM5_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 6, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_CH3_PA2_AF2 + {PA2, TIM5_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_CH3_PE8_AF1 + {PE8, TIM5_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 1, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_CH3_PF8_AF6 + {PF8, TIM5_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 6, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_CH4_PA3_AF2 + {PA3, TIM5_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_CH4_PE9_AF1 + {PE9, TIM5_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 1, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_CH4_PF9_AF6 + {PF9, TIM5_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 6, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_ETR_PB12_AF2 + // {PB12, TIM5_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_ETR_PD11_AF1 + // {PD11, TIM5_BASE_ADDRESS, 0, 1, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_ETR_PF6_AF1 + // {PF6, TIM5_BASE_ADDRESS, 0, 1, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM8_BKIN2_PB6_AF10 + // {PB6, TIM8_BASE_ADDRESS, 0, 10, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_BKIN2_PC9_AF6 + // {PC9, TIM8_BASE_ADDRESS, 0, 6, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_BKIN2_PD1_AF6 + // {PD1, TIM8_BASE_ADDRESS, 0, 6, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_BKIN_PA0_AF9 + // {PA0, TIM8_BASE_ADDRESS, 0, 9, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_BKIN_PA10_AF11 + // {PA10, TIM8_BASE_ADDRESS, 0, 11, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_BKIN_PA6_AF4 + // {PA6, TIM8_BASE_ADDRESS, 0, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_BKIN_PB7_AF5 + // {PB7, TIM8_BASE_ADDRESS, 0, 5, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_BKIN_PD2_AF4 + // {PD2, TIM8_BASE_ADDRESS, 0, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH1N_PA7_AF4 + {PA7, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH1N_PB3_AF4 + {PB3, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH1N_PC10_AF4 + {PC10, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH1_PA15_AF2 + {PA15, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH1_PB6_AF5 + {PB6, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 5, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH1_PC6_AF4 + {PC6, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH2N_PB0_AF4 + {PB0, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH2N_PB4_AF4 + {PB4, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH2N_PC11_AF4 + {PC11, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH2_PA14_AF5 + {PA14, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 5, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH2_PB8_AF10 + {PB8, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 10, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH2_PC7_AF4 + {PC7, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH3N_PB1_AF4 + {PB1, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH3N_PB5_AF3 + {PB5, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 3, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH3N_PC12_AF4 + {PC12, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH3_PB9_AF10 + {PB9, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 10, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH3_PC8_AF4 + {PC8, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH4N_PC13_AF6 + {PC13, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4N, 6, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH4N_PD0_AF6 + {PD0, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4N, 6, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH4_PC9_AF4 + {PC9, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH4_PD1_AF4 + {PD1, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_ETR_PA0_AF10 + // {PA0, TIM8_BASE_ADDRESS, 0, 10, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_ETR_PB6_AF6 + // {PB6, TIM8_BASE_ADDRESS, 0, 6, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + { HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_CHANNEL_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC } +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_TIM_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/tim/hal_ll_tim_pin_map/implementations/doc_ds_87/hal_ll_tim_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/tim/hal_ll_tim_pin_map/implementations/doc_ds_87/hal_ll_tim_pin_map.h new file mode 100644 index 000000000..912cc8e41 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/tim/hal_ll_tim_pin_map/implementations/doc_ds_87/hal_ll_tim_pin_map.h @@ -0,0 +1,786 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_tim_pin_map.h + * @brief TIM HAL LOW LEVEL PIN MAP. + */ + +#ifndef _HAL_LL_TIM_PIN_MAP_H_ +#define _HAL_LL_TIM_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_tim_module_num(_module_num) (_module_num - 1) + +/*!< @brief Alternate pin function structure. */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + hal_ll_channel_t channel; + uint32_t af; + hal_ll_pin_name_t module_index; +} hal_ll_tim_pin_map_t; + +typedef enum +{ + HAL_LL_TIM_CHANNEL_0 = 0, + HAL_LL_TIM_CHANNEL_1, + HAL_LL_TIM_CHANNEL_2, + HAL_LL_TIM_CHANNEL_3, + HAL_LL_TIM_CHANNEL_4, + HAL_LL_TIM_CHANNEL_1N, + HAL_LL_TIM_CHANNEL_2N, + HAL_LL_TIM_CHANNEL_3N, + HAL_LL_TIM_CHANNEL_4N +} hal_ll_tim_channel_t; + +#ifdef TIM_MODULE_1 +#define TIM1_BASE_ADDRESS (0x40012C00UL) +#define TIM1_BASE_ADDR TIM1_BASE_ADDRESS +#define HAL_LL_TIM1_BASE_ADDR TIM1_BASE_ADDRESS +#define HAL_LL_TIM1_BASE_ADDRESS TIM1_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_2 +#define TIM2_BASE_ADDRESS (0x40000000UL) +#define TIM2_BASE_ADDR TIM2_BASE_ADDRESS +#define HAL_LL_TIM2_BASE_ADDR TIM2_BASE_ADDRESS +#define HAL_LL_TIM2_BASE_ADDRESS TIM2_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_3 +#define TIM3_BASE_ADDRESS (0x40000400UL) +#define TIM3_BASE_ADDR TIM3_BASE_ADDRESS +#define HAL_LL_TIM3_BASE_ADDR TIM3_BASE_ADDRESS +#define HAL_LL_TIM3_BASE_ADDRESS TIM3_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_4 +#define TIM4_BASE_ADDRESS (0x40000800UL) +#define TIM4_BASE_ADDR TIM4_BASE_ADDRESS +#define HAL_LL_TIM4_BASE_ADDR TIM4_BASE_ADDRESS +#define HAL_LL_TIM4_BASE_ADDRESS TIM4_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_5 +#define TIM5_BASE_ADDRESS (0x40000C00UL) +#define TIM5_BASE_ADDR TIM5_BASE_ADDRESS +#define HAL_LL_TIM5_BASE_ADDR TIM5_BASE_ADDRESS +#define HAL_LL_TIM5_BASE_ADDRESS TIM5_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_8 +#define TIM8_BASE_ADDRESS (0x40013400UL) +#define TIM8_BASE_ADDR TIM8_BASE_ADDRESS +#define HAL_LL_TIM8_BASE_ADDR TIM8_BASE_ADDRESS +#define HAL_LL_TIM8_BASE_ADDRESS TIM8_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_15 +#define TIM15_BASE_ADDRESS (0x40014000UL) +#define TIM15_BASE_ADDR TIM15_BASE_ADDRESS +#define HAL_LL_TIM15_BASE_ADDR TIM15_BASE_ADDRESS +#define HAL_LL_TIM15_BASE_ADDRESS TIM15_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_16 +#define TIM16_BASE_ADDRESS (0x40014400UL) +#define TIM16_BASE_ADDR TIM16_BASE_ADDRESS +#define HAL_LL_TIM16_BASE_ADDR TIM16_BASE_ADDRESS +#define HAL_LL_TIM16_BASE_ADDRESS TIM16_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_17 +#define TIM17_BASE_ADDRESS (0x40014800UL) +#define TIM17_BASE_ADDR TIM17_BASE_ADDRESS +#define HAL_LL_TIM17_BASE_ADDR TIM17_BASE_ADDRESS +#define HAL_LL_TIM17_BASE_ADDRESS TIM17_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_20 +#define TIM20_BASE_ADDRESS (0x40015000UL) +#define TIM20_BASE_ADDR TIM20_BASE_ADDRESS +#define HAL_LL_TIM20_BASE_ADDR TIM20_BASE_ADDRESS +#define HAL_LL_TIM20_BASE_ADDRESS TIM20_BASE_ADDRESS +#endif + +/*!< @brief TIM pins. */ +static const hal_ll_tim_pin_map_t _tim_map[] = { + #ifdef HRTIM1_CHA1_PA8_AF13 + // {PA8, HRTIM1_BASE_ADDRESS, 0, 13, hal_ll_hrtim_module_num(HRTIM_MODULE_1)}, + #endif + #ifdef HRTIM1_CHA2_PA9_AF13 + // {PA9, HRTIM1_BASE_ADDRESS, 0, 13, hal_ll_hrtim_module_num(HRTIM_MODULE_1)}, + #endif + #ifdef HRTIM1_CHB1_PA10_AF13 + // {PA10, HRTIM1_BASE_ADDRESS, 0, 13, hal_ll_hrtim_module_num(HRTIM_MODULE_1)}, + #endif + #ifdef HRTIM1_CHB2_PA11_AF13 + // {PA11, HRTIM1_BASE_ADDRESS, 0, 13, hal_ll_hrtim_module_num(HRTIM_MODULE_1)}, + #endif + #ifdef HRTIM1_CHC1_PB12_AF13 + // {PB12, HRTIM1_BASE_ADDRESS, 0, 13, hal_ll_hrtim_module_num(HRTIM_MODULE_1)}, + #endif + #ifdef HRTIM1_CHC2_PB13_AF13 + // {PB13, HRTIM1_BASE_ADDRESS, 0, 13, hal_ll_hrtim_module_num(HRTIM_MODULE_1)}, + #endif + #ifdef HRTIM1_CHD1_PB14_AF13 + // {PB14, HRTIM1_BASE_ADDRESS, 0, 13, hal_ll_hrtim_module_num(HRTIM_MODULE_1)}, + #endif + #ifdef HRTIM1_CHD2_PB15_AF13 + // {PB15, HRTIM1_BASE_ADDRESS, 0, 13, hal_ll_hrtim_module_num(HRTIM_MODULE_1)}, + #endif + #ifdef HRTIM1_CHE1_PC8_AF3 + // {PC8, HRTIM1_BASE_ADDRESS, 0, 3, hal_ll_hrtim_module_num(HRTIM_MODULE_1)}, + #endif + #ifdef HRTIM1_CHE2_PC9_AF3 + // {PC9, HRTIM1_BASE_ADDRESS, 0, 3, hal_ll_hrtim_module_num(HRTIM_MODULE_1)}, + #endif + #ifdef HRTIM1_CHF1_PC6_AF13 + // {PC6, HRTIM1_BASE_ADDRESS, 0, 13, hal_ll_hrtim_module_num(HRTIM_MODULE_1)}, + #endif + #ifdef HRTIM1_CHF2_PC7_AF13 + // {PC7, HRTIM1_BASE_ADDRESS, 0, 13, hal_ll_hrtim_module_num(HRTIM_MODULE_1)}, + #endif + #ifdef LPTIM1_ETR_PB6_AF11 + // {PB6, LPTIM1_BASE_ADDRESS, 0, 11, hal_ll_lptim_module_num(LPTIM_MODULE_1)}, + #endif + #ifdef LPTIM1_ETR_PC3_AF1 + // {PC3, LPTIM1_BASE_ADDRESS, 0, 1, hal_ll_lptim_module_num(LPTIM_MODULE_1)}, + #endif + #ifdef TIM15_BKIN_PA9_AF9 + // {PA9, TIM15_BASE_ADDRESS, 0, 9, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_BKIN_PC5_AF2 + // {PC5, TIM15_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH1N_PA1_AF9 + {PA1, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 9, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH1N_PB15_AF2 + {PB15, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 2, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH1N_PG9_AF14 + {PG9, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 14, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH1_PA2_AF9 + {PA2, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 9, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH1_PB14_AF1 + {PB14, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH1_PF9_AF3 + {PF9, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 3, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH2_PA3_AF9 + {PA3, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 9, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH2_PB15_AF1 + {PB15, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 1, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH2_PF10_AF3 + {PF10, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 3, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM16_BKIN_PB5_AF1 + // {PB5, TIM16_BASE_ADDRESS, 0, 1, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1N_PA13_AF1 + {PA13, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 1, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1N_PB6_AF1 + {PB6, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 1, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1_PA12_AF1 + {PA12, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1_PA6_AF1 + {PA6, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1_PB4_AF1 + {PB4, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1_PB8_AF1 + {PB8, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1_PE0_AF4 + {PE0, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 4, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM17_BKIN_PA10_AF1 + // {PA10, TIM17_BASE_ADDRESS, 0, 1, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_BKIN_PB4_AF10 + // {PB4, TIM17_BASE_ADDRESS, 0, 10, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_CH1N_PB7_AF1 + {PB7, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 1, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_CH1_PA7_AF1 + {PA7, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_CH1_PB5_AF10 + {PB5, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 10, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_CH1_PB9_AF1 + {PB9, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_CH1_PE1_AF4 + {PE1, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 4, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM1_BKIN2_PA11_AF12 + // {PA11, TIM1_BASE_ADDRESS, 0, 12, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN2_PC3_AF6 + // {PC3, TIM1_BASE_ADDRESS, 0, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN2_PE14_AF6 + // {PE14, TIM1_BASE_ADDRESS, 0, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN_PA14_AF6 + // {PA14, TIM1_BASE_ADDRESS, 0, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN_PA15_AF9 + // {PA15, TIM1_BASE_ADDRESS, 0, 9, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN_PA6_AF6 + // {PA6, TIM1_BASE_ADDRESS, 0, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN_PB10_AF12 + // {PB10, TIM1_BASE_ADDRESS, 0, 12, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN_PB12_AF6 + // {PB12, TIM1_BASE_ADDRESS, 0, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN_PB8_AF12 + // {PB8, TIM1_BASE_ADDRESS, 0, 12, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN_PC13_AF2 + // {PC13, TIM1_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN_PE15_AF2 + // {PE15, TIM1_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1N_PA11_AF6 + {PA11, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1N_PA7_AF6 + {PA7, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1N_PB13_AF6 + {PB13, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1N_PC13_AF4 + {PC13, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 4, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1N_PE8_AF2 + {PE8, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1_PA8_AF6 + {PA8, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1_PC0_AF2 + {PC0, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1_PE9_AF2 + {PE9, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2N_PA12_AF6 + {PA12, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2N_PB0_AF6 + {PB0, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2N_PB14_AF6 + {PB14, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2N_PE10_AF2 + {PE10, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2_PA9_AF6 + {PA9, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2_PC1_AF2 + {PC1, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2_PE11_AF2 + {PE11, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3N_PB15_AF4 + {PB15, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 4, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3N_PB1_AF6 + {PB1, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3N_PB9_AF12 + {PB9, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 12, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3N_PE12_AF2 + {PE12, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3N_PF0_AF6 + {PF0, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3_PA10_AF6 + {PA10, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3_PC2_AF2 + {PC2, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3_PE13_AF2 + {PE13, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH4N_PC5_AF6 + {PC5, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH4N_PE15_AF6 + {PE15, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH4_PA11_AF11 + {PA11, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 11, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH4_PC3_AF2 + {PC3, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH4_PE14_AF2 + {PE14, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_ETR_PA12_AF11 + // {PA12, TIM1_BASE_ADDRESS, 0, 11, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_ETR_PC4_AF2 + // {PC4, TIM1_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_ETR_PE7_AF2 + // {PE7, TIM1_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM20_BKIN2_PF10_AF2 + // {PF10, TIM20_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_BKIN2_PF8_AF2 + // {PF8, TIM20_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_BKIN2_PG4_AF2 + // {PG4, TIM20_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_BKIN_PF7_AF2 + // {PF7, TIM20_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_BKIN_PF9_AF2 + // {PF9, TIM20_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_BKIN_PG3_AF2 + // {PG3, TIM20_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_BKIN_PG6_AF2 + // {PG6, TIM20_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH1N_PE4_AF6 + {PE4, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 6, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH1N_PF4_AF3 + {PF4, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 3, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH1N_PG0_AF2 + {PG0, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH1_PB2_AF3 + {PB2, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 3, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH1_PE2_AF6 + {PE2, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 6, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH1_PF12_AF2 + {PF12, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH2N_PE5_AF6 + {PE5, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 6, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH2N_PF5_AF2 + {PF5, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH2N_PG1_AF2 + {PG1, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH2_PC2_AF6 + {PC2, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 6, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH2_PE3_AF6 + {PE3, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 6, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH2_PF13_AF2 + {PF13, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH3N_PE6_AF6 + {PE6, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 6, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH3N_PG2_AF2 + {PG2, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH3_PC8_AF6 + {PC8, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 6, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH3_PF14_AF2 + {PF14, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH3_PF2_AF2 + {PF2, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH4N_PE0_AF3 + {PE0, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4N, 3, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH4N_PG3_AF6 + {PG3, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4N, 6, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH4_PE1_AF6 + {PE1, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 6, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH4_PF15_AF2 + {PF15, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH4_PF3_AF2 + {PF3, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_ETR_PE0_AF6 + // {PE0, TIM20_BASE_ADDRESS, 0, 6, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_ETR_PF11_AF2 + // {PF11, TIM20_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_ETR_PG5_AF2 + // {PG5, TIM20_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM2_CH1_PA0_AF1 + {PA0, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH1_PA15_AF1 + {PA15, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH1_PA5_AF1 + {PA5, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH1_PD3_AF2 + {PD3, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH2_PA1_AF1 + {PA1, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH2_PB3_AF1 + {PB3, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH2_PD4_AF2 + {PD4, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH3_PA2_AF1 + {PA2, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH3_PA9_AF10 + {PA9, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 10, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH3_PB10_AF1 + {PB10, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH3_PD7_AF2 + {PD7, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH4_PA10_AF10 + {PA10, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 10, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH4_PA3_AF1 + {PA3, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH4_PB11_AF1 + {PB11, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH4_PD6_AF2 + {PD6, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_ETR_PA0_AF14 + // {PA0, TIM2_BASE_ADDRESS, 0, 14, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_ETR_PA15_AF14 + // {PA15, TIM2_BASE_ADDRESS, 0, 14, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_ETR_PA5_AF2 + // {PA5, TIM2_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_ETR_PD3_AF2 + // {PD3, TIM2_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM3_CH1_PA6_AF2 + {PA6, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH1_PB4_AF2 + {PB4, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH1_PC6_AF2 + {PC6, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH1_PE2_AF2 + {PE2, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH2_PA4_AF2 + {PA4, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH2_PA7_AF2 + {PA7, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH2_PB5_AF2 + {PB5, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH2_PC7_AF2 + {PC7, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH2_PE3_AF2 + {PE3, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH3_PB0_AF2 + {PB0, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH3_PC8_AF2 + {PC8, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH3_PE4_AF2 + {PE4, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH4_PB1_AF2 + {PB1, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH4_PB7_AF10 + {PB7, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 10, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH4_PC9_AF2 + {PC9, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH4_PE5_AF2 + {PE5, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_ETR_PB3_AF10 + // {PB3, TIM3_BASE_ADDRESS, 0, 10, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_ETR_PD2_AF2 + // {PD2, TIM3_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM4_CH1_PA11_AF10 + {PA11, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 10, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH1_PB6_AF2 + {PB6, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH1_PD12_AF2 + {PD12, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH2_PA12_AF10 + {PA12, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 10, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH2_PB7_AF2 + {PB7, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH2_PD13_AF2 + {PD13, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH3_PA13_AF10 + {PA13, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 10, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH3_PB8_AF2 + {PB8, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH3_PD14_AF2 + {PD14, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH4_PB9_AF2 + {PB9, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH4_PD15_AF2 + {PD15, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH4_PF6_AF2 + {PF6, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_ETR_PA8_AF10 + // {PA8, TIM4_BASE_ADDRESS, 0, 10, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_ETR_PB3_AF2 + // {PB3, TIM4_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_ETR_PE0_AF2 + // {PE0, TIM4_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM5_CH1_PA0_AF2 + {PA0, TIM5_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_CH1_PB2_AF2 + {PB2, TIM5_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_CH1_PF6_AF6 + {PF6, TIM5_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 6, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_CH2_PA1_AF2 + {PA1, TIM5_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_CH2_PC12_AF1 + {PC12, TIM5_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 1, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_CH2_PF7_AF6 + {PF7, TIM5_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 6, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_CH3_PA2_AF2 + {PA2, TIM5_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_CH3_PE8_AF1 + {PE8, TIM5_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 1, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_CH3_PF8_AF6 + {PF8, TIM5_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 6, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_CH4_PA3_AF2 + {PA3, TIM5_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_CH4_PE9_AF1 + {PE9, TIM5_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 1, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_CH4_PF9_AF6 + {PF9, TIM5_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 6, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_ETR_PB12_AF2 + // {PB12, TIM5_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_ETR_PD11_AF1 + // {PD11, TIM5_BASE_ADDRESS, 0, 1, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM5_ETR_PF6_AF1 + // {PF6, TIM5_BASE_ADDRESS, 0, 1, hal_ll_tim_module_num(TIM_MODULE_5)}, + #endif + #ifdef TIM8_BKIN2_PB6_AF10 + // {PB6, TIM8_BASE_ADDRESS, 0, 10, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_BKIN2_PC9_AF6 + // {PC9, TIM8_BASE_ADDRESS, 0, 6, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_BKIN2_PD1_AF6 + // {PD1, TIM8_BASE_ADDRESS, 0, 6, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_BKIN_PA0_AF9 + // {PA0, TIM8_BASE_ADDRESS, 0, 9, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_BKIN_PA10_AF11 + // {PA10, TIM8_BASE_ADDRESS, 0, 11, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_BKIN_PA6_AF4 + // {PA6, TIM8_BASE_ADDRESS, 0, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_BKIN_PB7_AF5 + // {PB7, TIM8_BASE_ADDRESS, 0, 5, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_BKIN_PD2_AF4 + // {PD2, TIM8_BASE_ADDRESS, 0, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH1N_PA7_AF4 + {PA7, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH1N_PB3_AF4 + {PB3, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH1N_PC10_AF4 + {PC10, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH1_PA15_AF2 + {PA15, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH1_PB6_AF5 + {PB6, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 5, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH1_PC6_AF4 + {PC6, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH2N_PB0_AF4 + {PB0, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH2N_PB4_AF4 + {PB4, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH2N_PC11_AF4 + {PC11, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH2_PA14_AF5 + {PA14, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 5, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH2_PB8_AF10 + {PB8, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 10, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH2_PC7_AF4 + {PC7, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH3N_PB1_AF4 + {PB1, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH3N_PB5_AF3 + {PB5, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 3, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH3N_PC12_AF4 + {PC12, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH3_PB9_AF10 + {PB9, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 10, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH3_PC8_AF4 + {PC8, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH4N_PC13_AF6 + {PC13, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4N, 6, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH4N_PD0_AF6 + {PD0, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4N, 6, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH4_PC9_AF4 + {PC9, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH4_PD1_AF4 + {PD1, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_ETR_PA0_AF10 + // {PA0, TIM8_BASE_ADDRESS, 0, 10, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_ETR_PB6_AF6 + // {PB6, TIM8_BASE_ADDRESS, 0, 6, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + { HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_CHANNEL_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC } +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_TIM_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/tim/hal_ll_tim_pin_map/implementations/doc_ds_88/hal_ll_tim_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/tim/hal_ll_tim_pin_map/implementations/doc_ds_88/hal_ll_tim_pin_map.h new file mode 100644 index 000000000..9d3c2d7bd --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/tim/hal_ll_tim_pin_map/implementations/doc_ds_88/hal_ll_tim_pin_map.h @@ -0,0 +1,642 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_tim_pin_map.h + * @brief TIM HAL LOW LEVEL PIN MAP. + */ + +#ifndef _HAL_LL_TIM_PIN_MAP_H_ +#define _HAL_LL_TIM_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_tim_module_num(_module_num) (_module_num - 1) + +/*!< @brief Alternate pin function structure. */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + hal_ll_channel_t channel; + uint32_t af; + hal_ll_pin_name_t module_index; +} hal_ll_tim_pin_map_t; + +typedef enum +{ + HAL_LL_TIM_CHANNEL_0 = 0, + HAL_LL_TIM_CHANNEL_1, + HAL_LL_TIM_CHANNEL_2, + HAL_LL_TIM_CHANNEL_3, + HAL_LL_TIM_CHANNEL_4, + HAL_LL_TIM_CHANNEL_1N, + HAL_LL_TIM_CHANNEL_2N, + HAL_LL_TIM_CHANNEL_3N, + HAL_LL_TIM_CHANNEL_4N +} hal_ll_tim_channel_t; + +#ifdef TIM_MODULE_1 +#define TIM1_BASE_ADDRESS (0x40012C00UL) +#define TIM1_BASE_ADDR TIM1_BASE_ADDRESS +#define HAL_LL_TIM1_BASE_ADDR TIM1_BASE_ADDRESS +#define HAL_LL_TIM1_BASE_ADDRESS TIM1_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_2 +#define TIM2_BASE_ADDRESS (0x40000000UL) +#define TIM2_BASE_ADDR TIM2_BASE_ADDRESS +#define HAL_LL_TIM2_BASE_ADDR TIM2_BASE_ADDRESS +#define HAL_LL_TIM2_BASE_ADDRESS TIM2_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_3 +#define TIM3_BASE_ADDRESS (0x40000400UL) +#define TIM3_BASE_ADDR TIM3_BASE_ADDRESS +#define HAL_LL_TIM3_BASE_ADDR TIM3_BASE_ADDRESS +#define HAL_LL_TIM3_BASE_ADDRESS TIM3_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_4 +#define TIM4_BASE_ADDRESS (0x40000800UL) +#define TIM4_BASE_ADDR TIM4_BASE_ADDRESS +#define HAL_LL_TIM4_BASE_ADDR TIM4_BASE_ADDRESS +#define HAL_LL_TIM4_BASE_ADDRESS TIM4_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_8 +#define TIM8_BASE_ADDRESS (0x40013400UL) +#define TIM8_BASE_ADDR TIM8_BASE_ADDRESS +#define HAL_LL_TIM8_BASE_ADDR TIM8_BASE_ADDRESS +#define HAL_LL_TIM8_BASE_ADDRESS TIM8_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_15 +#define TIM15_BASE_ADDRESS (0x40014000UL) +#define TIM15_BASE_ADDR TIM15_BASE_ADDRESS +#define HAL_LL_TIM15_BASE_ADDR TIM15_BASE_ADDRESS +#define HAL_LL_TIM15_BASE_ADDRESS TIM15_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_16 +#define TIM16_BASE_ADDRESS (0x40014400UL) +#define TIM16_BASE_ADDR TIM16_BASE_ADDRESS +#define HAL_LL_TIM16_BASE_ADDR TIM16_BASE_ADDRESS +#define HAL_LL_TIM16_BASE_ADDRESS TIM16_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_17 +#define TIM17_BASE_ADDRESS (0x40014800UL) +#define TIM17_BASE_ADDR TIM17_BASE_ADDRESS +#define HAL_LL_TIM17_BASE_ADDR TIM17_BASE_ADDRESS +#define HAL_LL_TIM17_BASE_ADDRESS TIM17_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_20 +#define TIM20_BASE_ADDRESS (0x40015000UL) +#define TIM20_BASE_ADDR TIM20_BASE_ADDRESS +#define HAL_LL_TIM20_BASE_ADDR TIM20_BASE_ADDRESS +#define HAL_LL_TIM20_BASE_ADDRESS TIM20_BASE_ADDRESS +#endif + +/*!< @brief TIM pins. */ +static const hal_ll_tim_pin_map_t _tim_map[] = { + #ifdef LPTIM1_ETR_PB6_AF11 + // {PB6, LPTIM1_BASE_ADDRESS, 0, 11, hal_ll_lptim_module_num(LPTIM_MODULE_1)}, + #endif + #ifdef TIM15_BKIN_PA9_AF9 + // {PA9, TIM15_BASE_ADDRESS, 0, 9, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH1N_PA1_AF9 + {PA1, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 9, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH1_PA2_AF9 + {PA2, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 9, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH2_PA3_AF9 + {PA3, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 9, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM16_BKIN_PB5_AF1 + // {PB5, TIM16_BASE_ADDRESS, 0, 1, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1N_PA13_AF1 + {PA13, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 1, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1N_PB6_AF1 + {PB6, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 1, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1_PA12_AF1 + {PA12, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1_PA6_AF1 + {PA6, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1_PB4_AF1 + {PB4, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1_PB8_AF1 + {PB8, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM17_BKIN_PA10_AF1 + // {PA10, TIM17_BASE_ADDRESS, 0, 1, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_BKIN_PB4_AF10 + // {PB4, TIM17_BASE_ADDRESS, 0, 10, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_CH1N_PB7_AF1 + {PB7, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 1, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_CH1_PA7_AF1 + {PA7, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_CH1_PB5_AF10 + {PB5, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 10, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM1_BKIN2_PA11_AF12 + // {PA11, TIM1_BASE_ADDRESS, 0, 12, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN_PA14_AF6 + // {PA14, TIM1_BASE_ADDRESS, 0, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN_PA15_AF9 + // {PA15, TIM1_BASE_ADDRESS, 0, 9, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN_PA6_AF6 + // {PA6, TIM1_BASE_ADDRESS, 0, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN_PB8_AF12 + // {PB8, TIM1_BASE_ADDRESS, 0, 12, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1N_PA11_AF6 + {PA11, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1N_PA7_AF6 + {PA7, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1_PA8_AF6 + {PA8, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2N_PA12_AF6 + {PA12, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2N_PB0_AF6 + {PB0, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2_PA9_AF6 + {PA9, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3N_PF0_AF6 + {PF0, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3_PA10_AF6 + {PA10, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH4_PA11_AF11 + {PA11, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 11, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_ETR_PA12_AF11 + // {PA12, TIM1_BASE_ADDRESS, 0, 11, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM20_ETR_PA15_AF3 + // {PA15, TIM20_BASE_ADDRESS, 0, 3, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM2_CH1_PA0_AF1 + {PA0, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH1_PA15_AF1 + {PA15, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH1_PA5_AF1 + {PA5, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH2_PA1_AF1 + {PA1, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH2_PB3_AF1 + {PB3, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH3_PA2_AF1 + {PA2, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH3_PA9_AF10 + {PA9, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 10, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH4_PA10_AF10 + {PA10, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 10, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH4_PA3_AF1 + {PA3, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_ETR_PA0_AF14 + // {PA0, TIM2_BASE_ADDRESS, 0, 14, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_ETR_PA15_AF14 + // {PA15, TIM2_BASE_ADDRESS, 0, 14, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_ETR_PA5_AF2 + // {PA5, TIM2_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM3_CH1_PA6_AF2 + {PA6, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH1_PB4_AF2 + {PB4, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH2_PA4_AF2 + {PA4, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH2_PA7_AF2 + {PA7, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH2_PB5_AF2 + {PB5, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH3_PB0_AF2 + {PB0, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH4_PB7_AF10 + {PB7, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 10, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_ETR_PB3_AF10 + // {PB3, TIM3_BASE_ADDRESS, 0, 10, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM4_CH1_PA11_AF10 + {PA11, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 10, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH1_PB6_AF2 + {PB6, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH2_PA12_AF10 + {PA12, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 10, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH2_PB7_AF2 + {PB7, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH3_PA13_AF10 + {PA13, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 10, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH3_PB8_AF2 + {PB8, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_ETR_PA8_AF10 + // {PA8, TIM4_BASE_ADDRESS, 0, 10, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_ETR_PB3_AF2 + // {PB3, TIM4_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM8_BKIN2_PB6_AF10 + // {PB6, TIM8_BASE_ADDRESS, 0, 10, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_BKIN_PA0_AF9 + // {PA0, TIM8_BASE_ADDRESS, 0, 9, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_BKIN_PA10_AF11 + // {PA10, TIM8_BASE_ADDRESS, 0, 11, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_BKIN_PA6_AF4 + // {PA6, TIM8_BASE_ADDRESS, 0, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_BKIN_PB7_AF5 + // {PB7, TIM8_BASE_ADDRESS, 0, 5, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH1N_PA7_AF4 + {PA7, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH1N_PB3_AF4 + {PB3, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH1_PA15_AF2 + {PA15, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH1_PB6_AF5 + {PB6, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 5, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH2N_PB0_AF4 + {PB0, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH2N_PB4_AF4 + {PB4, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH2_PA14_AF5 + {PA14, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 5, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH2_PB8_AF10 + {PB8, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 10, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH3N_PB5_AF3 + {PB5, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 3, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_ETR_PA0_AF10 + // {PA0, TIM8_BASE_ADDRESS, 0, 10, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_ETR_PB6_AF6 + // {PB6, TIM8_BASE_ADDRESS, 0, 6, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef LPTIM1_ETR_PC3_AF1 + // {PC3, LPTIM1_BASE_ADDRESS, 0, 1, hal_ll_lptim_module_num(LPTIM_MODULE_1)}, + #endif + #ifdef TIM15_BKIN_PC5_AF2 + // {PC5, TIM15_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH1N_PB15_AF2 + {PB15, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 2, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH1_PB14_AF1 + {PB14, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH2_PB15_AF1 + {PB15, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 1, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM17_CH1_PB9_AF1 + {PB9, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM1_BKIN2_PC3_AF6 + // {PC3, TIM1_BASE_ADDRESS, 0, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN2_PE14_AF6 + // {PE14, TIM1_BASE_ADDRESS, 0, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN_PB10_AF12 + // {PB10, TIM1_BASE_ADDRESS, 0, 12, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN_PB12_AF6 + // {PB12, TIM1_BASE_ADDRESS, 0, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN_PC13_AF2 + // {PC13, TIM1_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN_PE15_AF2 + // {PE15, TIM1_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1N_PB13_AF6 + {PB13, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1N_PC13_AF4 + {PC13, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 4, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1N_PE8_AF2 + {PE8, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1_PC0_AF2 + {PC0, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1_PE9_AF2 + {PE9, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2N_PB14_AF6 + {PB14, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2N_PE10_AF2 + {PE10, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2_PC1_AF2 + {PC1, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2_PE11_AF2 + {PE11, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3N_PB15_AF4 + {PB15, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 4, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3N_PB1_AF6 + {PB1, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3N_PB9_AF12 + {PB9, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 12, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3N_PE12_AF2 + {PE12, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3_PC2_AF2 + {PC2, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3_PE13_AF2 + {PE13, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH4N_PC5_AF6 + {PC5, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH4N_PE15_AF6 + {PE15, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH4_PC3_AF2 + {PC3, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH4_PE14_AF2 + {PE14, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_ETR_PC4_AF2 + // {PC4, TIM1_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_ETR_PE7_AF2 + // {PE7, TIM1_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM20_CH1_PB2_AF3 + {PB2, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 3, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH2_PC2_AF6 + {PC2, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 6, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH3_PC8_AF6 + {PC8, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 6, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM2_CH3_PB10_AF1 + {PB10, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH4_PB11_AF1 + {PB11, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM3_CH1_PC6_AF2 + {PC6, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH2_PC7_AF2 + {PC7, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH3_PC8_AF2 + {PC8, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH4_PB1_AF2 + {PB1, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH4_PC9_AF2 + {PC9, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_ETR_PD2_AF2 + // {PD2, TIM3_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM4_CH4_PB9_AF2 + {PB9, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM8_BKIN2_PC9_AF6 + // {PC9, TIM8_BASE_ADDRESS, 0, 6, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_BKIN2_PD1_AF6 + // {PD1, TIM8_BASE_ADDRESS, 0, 6, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_BKIN_PD2_AF4 + // {PD2, TIM8_BASE_ADDRESS, 0, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH1N_PC10_AF4 + {PC10, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH1_PC6_AF4 + {PC6, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH2N_PC11_AF4 + {PC11, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH2_PC7_AF4 + {PC7, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH3N_PB1_AF4 + {PB1, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH3N_PC12_AF4 + {PC12, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH3_PB9_AF10 + {PB9, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 10, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH3_PC8_AF4 + {PC8, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH4N_PC13_AF6 + {PC13, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4N, 6, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH4N_PD0_AF6 + {PD0, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4N, 6, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH4_PC9_AF4 + {PC9, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH4_PD1_AF4 + {PD1, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM15_CH1_PF9_AF3 + {PF9, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 3, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH2_PF10_AF3 + {PF10, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 3, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM16_CH1_PE0_AF4 + {PE0, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 4, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM17_CH1_PE1_AF4 + {PE1, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 4, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM20_BKIN2_PF10_AF2 + // {PF10, TIM20_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_BKIN_PF9_AF2 + // {PF9, TIM20_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH1N_PE4_AF6 + {PE4, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 6, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH1_PE2_AF6 + {PE2, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 6, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH2N_PE5_AF6 + {PE5, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 6, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH2_PE3_AF6 + {PE3, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 6, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH3N_PE6_AF6 + {PE6, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 6, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH3_PF2_AF2 + {PF2, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH4N_PE0_AF3 + {PE0, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4N, 3, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH4_PE1_AF6 + {PE1, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 6, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_ETR_PE0_AF6 + // {PE0, TIM20_BASE_ADDRESS, 0, 6, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM2_CH1_PD3_AF2 + {PD3, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH2_PD4_AF2 + {PD4, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH3_PD7_AF2 + {PD7, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH4_PD6_AF2 + {PD6, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_ETR_PD3_AF2 + // {PD3, TIM2_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM3_CH1_PE2_AF2 + {PE2, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH2_PE3_AF2 + {PE3, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH3_PE4_AF2 + {PE4, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH4_PE5_AF2 + {PE5, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM4_CH1_PD12_AF2 + {PD12, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH2_PD13_AF2 + {PD13, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH3_PD14_AF2 + {PD14, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH4_PD15_AF2 + {PD15, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_ETR_PE0_AF2 + // {PE0, TIM4_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + { HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_CHANNEL_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC } +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_TIM_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/tim/hal_ll_tim_pin_map/implementations/doc_ds_89/hal_ll_tim_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/tim/hal_ll_tim_pin_map/implementations/doc_ds_89/hal_ll_tim_pin_map.h new file mode 100644 index 000000000..a441653b1 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/tim/hal_ll_tim_pin_map/implementations/doc_ds_89/hal_ll_tim_pin_map.h @@ -0,0 +1,642 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_tim_pin_map.h + * @brief TIM HAL LOW LEVEL PIN MAP. + */ + +#ifndef _HAL_LL_TIM_PIN_MAP_H_ +#define _HAL_LL_TIM_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_tim_module_num(_module_num) (_module_num - 1) + +/*!< @brief Alternate pin function structure. */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + hal_ll_channel_t channel; + uint32_t af; + hal_ll_pin_name_t module_index; +} hal_ll_tim_pin_map_t; + +typedef enum +{ + HAL_LL_TIM_CHANNEL_0 = 0, + HAL_LL_TIM_CHANNEL_1, + HAL_LL_TIM_CHANNEL_2, + HAL_LL_TIM_CHANNEL_3, + HAL_LL_TIM_CHANNEL_4, + HAL_LL_TIM_CHANNEL_1N, + HAL_LL_TIM_CHANNEL_2N, + HAL_LL_TIM_CHANNEL_3N, + HAL_LL_TIM_CHANNEL_4N +} hal_ll_tim_channel_t; + +#ifdef TIM_MODULE_1 +#define TIM1_BASE_ADDRESS (0x40012C00UL) +#define TIM1_BASE_ADDR TIM1_BASE_ADDRESS +#define HAL_LL_TIM1_BASE_ADDR TIM1_BASE_ADDRESS +#define HAL_LL_TIM1_BASE_ADDRESS TIM1_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_2 +#define TIM2_BASE_ADDRESS (0x40000000UL) +#define TIM2_BASE_ADDR TIM2_BASE_ADDRESS +#define HAL_LL_TIM2_BASE_ADDR TIM2_BASE_ADDRESS +#define HAL_LL_TIM2_BASE_ADDRESS TIM2_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_3 +#define TIM3_BASE_ADDRESS (0x40000400UL) +#define TIM3_BASE_ADDR TIM3_BASE_ADDRESS +#define HAL_LL_TIM3_BASE_ADDR TIM3_BASE_ADDRESS +#define HAL_LL_TIM3_BASE_ADDRESS TIM3_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_4 +#define TIM4_BASE_ADDRESS (0x40000800UL) +#define TIM4_BASE_ADDR TIM4_BASE_ADDRESS +#define HAL_LL_TIM4_BASE_ADDR TIM4_BASE_ADDRESS +#define HAL_LL_TIM4_BASE_ADDRESS TIM4_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_8 +#define TIM8_BASE_ADDRESS (0x40013400UL) +#define TIM8_BASE_ADDR TIM8_BASE_ADDRESS +#define HAL_LL_TIM8_BASE_ADDR TIM8_BASE_ADDRESS +#define HAL_LL_TIM8_BASE_ADDRESS TIM8_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_15 +#define TIM15_BASE_ADDRESS (0x40014000UL) +#define TIM15_BASE_ADDR TIM15_BASE_ADDRESS +#define HAL_LL_TIM15_BASE_ADDR TIM15_BASE_ADDRESS +#define HAL_LL_TIM15_BASE_ADDRESS TIM15_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_16 +#define TIM16_BASE_ADDRESS (0x40014400UL) +#define TIM16_BASE_ADDR TIM16_BASE_ADDRESS +#define HAL_LL_TIM16_BASE_ADDR TIM16_BASE_ADDRESS +#define HAL_LL_TIM16_BASE_ADDRESS TIM16_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_17 +#define TIM17_BASE_ADDRESS (0x40014800UL) +#define TIM17_BASE_ADDR TIM17_BASE_ADDRESS +#define HAL_LL_TIM17_BASE_ADDR TIM17_BASE_ADDRESS +#define HAL_LL_TIM17_BASE_ADDRESS TIM17_BASE_ADDRESS +#endif +#ifdef TIM_MODULE_20 +#define TIM20_BASE_ADDRESS (0x40015000UL) +#define TIM20_BASE_ADDR TIM20_BASE_ADDRESS +#define HAL_LL_TIM20_BASE_ADDR TIM20_BASE_ADDRESS +#define HAL_LL_TIM20_BASE_ADDRESS TIM20_BASE_ADDRESS +#endif + +/*!< @brief TIM pins. */ +static const hal_ll_tim_pin_map_t _tim_map[] = { + #ifdef LPTIM1_ETR_PB6_AF11 + // {PB6, LPTIM1_BASE_ADDRESS, 0, 11, hal_ll_lptim_module_num(LPTIM_MODULE_1)}, + #endif + #ifdef LPTIM1_ETR_PC3_AF1 + // {PC3, LPTIM1_BASE_ADDRESS, 0, 1, hal_ll_lptim_module_num(LPTIM_MODULE_1)}, + #endif + #ifdef TIM15_BKIN_PA9_AF9 + // {PA9, TIM15_BASE_ADDRESS, 0, 9, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_BKIN_PC5_AF2 + // {PC5, TIM15_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH1N_PA1_AF9 + {PA1, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 9, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH1N_PB15_AF2 + {PB15, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 2, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH1_PA2_AF9 + {PA2, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 9, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH1_PB14_AF1 + {PB14, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH2_PA3_AF9 + {PA3, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 9, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH2_PB15_AF1 + {PB15, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 1, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM16_BKIN_PB5_AF1 + // {PB5, TIM16_BASE_ADDRESS, 0, 1, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1N_PA13_AF1 + {PA13, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 1, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1N_PB6_AF1 + {PB6, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 1, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1_PA12_AF1 + {PA12, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1_PA6_AF1 + {PA6, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1_PB4_AF1 + {PB4, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM16_CH1_PB8_AF1 + {PB8, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM17_BKIN_PA10_AF1 + // {PA10, TIM17_BASE_ADDRESS, 0, 1, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_BKIN_PB4_AF10 + // {PB4, TIM17_BASE_ADDRESS, 0, 10, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_CH1N_PB7_AF1 + {PB7, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 1, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_CH1_PA7_AF1 + {PA7, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_CH1_PB5_AF10 + {PB5, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 10, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM17_CH1_PB9_AF1 + {PB9, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM1_BKIN2_PA11_AF12 + // {PA11, TIM1_BASE_ADDRESS, 0, 12, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN2_PC3_AF6 + // {PC3, TIM1_BASE_ADDRESS, 0, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN2_PE14_AF6 + // {PE14, TIM1_BASE_ADDRESS, 0, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN_PA14_AF6 + // {PA14, TIM1_BASE_ADDRESS, 0, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN_PA15_AF9 + // {PA15, TIM1_BASE_ADDRESS, 0, 9, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN_PA6_AF6 + // {PA6, TIM1_BASE_ADDRESS, 0, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN_PB10_AF12 + // {PB10, TIM1_BASE_ADDRESS, 0, 12, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN_PB12_AF6 + // {PB12, TIM1_BASE_ADDRESS, 0, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN_PB8_AF12 + // {PB8, TIM1_BASE_ADDRESS, 0, 12, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN_PC13_AF2 + // {PC13, TIM1_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_BKIN_PE15_AF2 + // {PE15, TIM1_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1N_PA11_AF6 + {PA11, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1N_PA7_AF6 + {PA7, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1N_PB13_AF6 + {PB13, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1N_PC13_AF4 + {PC13, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 4, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1N_PE8_AF2 + {PE8, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1_PA8_AF6 + {PA8, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1_PC0_AF2 + {PC0, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1_PE9_AF2 + {PE9, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2N_PA12_AF6 + {PA12, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2N_PB0_AF6 + {PB0, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2N_PB14_AF6 + {PB14, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2N_PE10_AF2 + {PE10, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2_PA9_AF6 + {PA9, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2_PC1_AF2 + {PC1, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2_PE11_AF2 + {PE11, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3N_PB15_AF4 + {PB15, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 4, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3N_PB1_AF6 + {PB1, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3N_PB9_AF12 + {PB9, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 12, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3N_PE12_AF2 + {PE12, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3N_PF0_AF6 + {PF0, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3_PA10_AF6 + {PA10, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3_PC2_AF2 + {PC2, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH3_PE13_AF2 + {PE13, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH4N_PC5_AF6 + {PC5, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH4N_PE15_AF6 + {PE15, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4N, 6, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH4_PA11_AF11 + {PA11, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 11, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH4_PC3_AF2 + {PC3, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH4_PE14_AF2 + {PE14, TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_ETR_PA12_AF11 + // {PA12, TIM1_BASE_ADDRESS, 0, 11, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_ETR_PC4_AF2 + // {PC4, TIM1_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_ETR_PE7_AF2 + // {PE7, TIM1_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM20_CH1_PB2_AF3 + {PB2, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 3, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH2_PC2_AF6 + {PC2, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 6, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH3_PC8_AF6 + {PC8, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 6, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_ETR_PA15_AF3 + // {PA15, TIM20_BASE_ADDRESS, 0, 3, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM2_CH1_PA0_AF1 + {PA0, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH1_PA15_AF1 + {PA15, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH1_PA5_AF1 + {PA5, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH2_PA1_AF1 + {PA1, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH2_PB3_AF1 + {PB3, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH3_PA2_AF1 + {PA2, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH3_PA9_AF10 + {PA9, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 10, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH3_PB10_AF1 + {PB10, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH4_PA10_AF10 + {PA10, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 10, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH4_PA3_AF1 + {PA3, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH4_PB11_AF1 + {PB11, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 1, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_ETR_PA0_AF14 + // {PA0, TIM2_BASE_ADDRESS, 0, 14, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_ETR_PA15_AF14 + // {PA15, TIM2_BASE_ADDRESS, 0, 14, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_ETR_PA5_AF2 + // {PA5, TIM2_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM3_CH1_PA6_AF2 + {PA6, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH1_PB4_AF2 + {PB4, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH1_PC6_AF2 + {PC6, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH2_PA4_AF2 + {PA4, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH2_PA7_AF2 + {PA7, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH2_PB5_AF2 + {PB5, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH2_PC7_AF2 + {PC7, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH3_PB0_AF2 + {PB0, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH3_PC8_AF2 + {PC8, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH4_PB1_AF2 + {PB1, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH4_PB7_AF10 + {PB7, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 10, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH4_PC9_AF2 + {PC9, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_ETR_PB3_AF10 + // {PB3, TIM3_BASE_ADDRESS, 0, 10, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_ETR_PD2_AF2 + // {PD2, TIM3_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM4_CH1_PA11_AF10 + {PA11, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 10, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH1_PB6_AF2 + {PB6, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH2_PA12_AF10 + {PA12, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 10, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH2_PB7_AF2 + {PB7, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH3_PA13_AF10 + {PA13, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 10, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH3_PB8_AF2 + {PB8, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH4_PB9_AF2 + {PB9, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_ETR_PA8_AF10 + // {PA8, TIM4_BASE_ADDRESS, 0, 10, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_ETR_PB3_AF2 + // {PB3, TIM4_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM8_BKIN2_PB6_AF10 + // {PB6, TIM8_BASE_ADDRESS, 0, 10, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_BKIN2_PC9_AF6 + // {PC9, TIM8_BASE_ADDRESS, 0, 6, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_BKIN2_PD1_AF6 + // {PD1, TIM8_BASE_ADDRESS, 0, 6, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_BKIN_PA0_AF9 + // {PA0, TIM8_BASE_ADDRESS, 0, 9, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_BKIN_PA10_AF11 + // {PA10, TIM8_BASE_ADDRESS, 0, 11, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_BKIN_PA6_AF4 + // {PA6, TIM8_BASE_ADDRESS, 0, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_BKIN_PB7_AF5 + // {PB7, TIM8_BASE_ADDRESS, 0, 5, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_BKIN_PD2_AF4 + // {PD2, TIM8_BASE_ADDRESS, 0, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH1N_PA7_AF4 + {PA7, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH1N_PB3_AF4 + {PB3, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH1N_PC10_AF4 + {PC10, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH1_PA15_AF2 + {PA15, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH1_PB6_AF5 + {PB6, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 5, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH1_PC6_AF4 + {PC6, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH2N_PB0_AF4 + {PB0, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH2N_PB4_AF4 + {PB4, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH2N_PC11_AF4 + {PC11, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH2_PA14_AF5 + {PA14, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 5, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH2_PB8_AF10 + {PB8, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 10, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH2_PC7_AF4 + {PC7, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH3N_PB1_AF4 + {PB1, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH3N_PB5_AF3 + {PB5, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 3, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH3N_PC12_AF4 + {PC12, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH3_PB9_AF10 + {PB9, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 10, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH3_PC8_AF4 + {PC8, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH4N_PC13_AF6 + {PC13, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4N, 6, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH4N_PD0_AF6 + {PD0, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4N, 6, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH4_PC9_AF4 + {PC9, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_CH4_PD1_AF4 + {PD1, TIM8_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 4, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_ETR_PA0_AF10 + // {PA0, TIM8_BASE_ADDRESS, 0, 10, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM8_ETR_PB6_AF6 + // {PB6, TIM8_BASE_ADDRESS, 0, 6, hal_ll_tim_module_num(TIM_MODULE_8)}, + #endif + #ifdef TIM15_CH1_PF9_AF3 + {PF9, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 3, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM15_CH2_PF10_AF3 + {PF10, TIM15_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 3, hal_ll_tim_module_num(TIM_MODULE_15)}, + #endif + #ifdef TIM16_CH1_PE0_AF4 + {PE0, TIM16_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 4, hal_ll_tim_module_num(TIM_MODULE_16)}, + #endif + #ifdef TIM17_CH1_PE1_AF4 + {PE1, TIM17_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 4, hal_ll_tim_module_num(TIM_MODULE_17)}, + #endif + #ifdef TIM20_BKIN2_PF10_AF2 + // {PF10, TIM20_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_BKIN_PF9_AF2 + // {PF9, TIM20_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH1N_PE4_AF6 + {PE4, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1N, 6, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH1_PE2_AF6 + {PE2, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 6, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH2N_PE5_AF6 + {PE5, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2N, 6, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH2_PE3_AF6 + {PE3, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 6, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH3N_PE6_AF6 + {PE6, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3N, 6, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH3_PF2_AF2 + {PF2, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH4N_PE0_AF3 + {PE0, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4N, 3, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_CH4_PE1_AF6 + {PE1, TIM20_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 6, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM20_ETR_PE0_AF6 + // {PE0, TIM20_BASE_ADDRESS, 0, 6, hal_ll_tim_module_num(TIM_MODULE_20)}, + #endif + #ifdef TIM2_CH1_PD3_AF2 + {PD3, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH2_PD4_AF2 + {PD4, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH3_PD7_AF2 + {PD7, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH4_PD6_AF2 + {PD6, TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_ETR_PD3_AF2 + // {PD3, TIM2_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM3_CH1_PE2_AF2 + {PE2, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH2_PE3_AF2 + {PE3, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH3_PE4_AF2 + {PE4, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH4_PE5_AF2 + {PE5, TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM4_CH1_PD12_AF2 + {PD12, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH2_PD13_AF2 + {PD13, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH3_PD14_AF2 + {PD14, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_3, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_CH4_PD15_AF2 + {PD15, TIM4_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_4, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + #ifdef TIM4_ETR_PE0_AF2 + // {PE0, TIM4_BASE_ADDRESS, 0, 2, hal_ll_tim_module_num(TIM_MODULE_4)}, + #endif + { HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_CHANNEL_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC } +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_TIM_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/uart/hal_ll_uart.h b/targets/arm/mikroe/ai_generated/stm32/include/uart/hal_ll_uart.h new file mode 100644 index 000000000..9abb7a870 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/uart/hal_ll_uart.h @@ -0,0 +1,300 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_uart.h + * @brief API for UART HAL LOW LEVEL layer. + */ + +#ifndef _HAL_LL_UART_H_ +#define _HAL_LL_UART_H_ + +#include "hal_ll_target.h" + +#ifdef __cplusplus +extern "C"{ +#endif + +/** + * @brief Interrupt request type enum. + */ +typedef enum +{ + HAL_LL_UART_IRQ_RX, /**< RX INT */ + HAL_LL_UART_IRQ_TX /**< TX INT */ +} hal_ll_uart_irq_t; + +/** + * @brief Pointer to interrupt handler function. + */ +typedef void ( *hal_ll_uart_isr_t )( handle_t handle, hal_ll_uart_irq_t event ); + +/** + * @brief Predefined enum values for parity selection. + */ +typedef enum +{ + HAL_LL_UART_PARITY_NONE = 0, + HAL_LL_UART_PARITY_EVEN, + HAL_LL_UART_PARITY_ODD, + + HAL_LL_UART_PARITY_DEFAULT = HAL_LL_UART_PARITY_NONE +} hal_ll_uart_parity_t; + +/** + * @brief Predefined enum values for stop bit selection. + */ +typedef enum +{ + HAL_LL_UART_STOP_BITS_HALF = 0, + HAL_LL_UART_STOP_BITS_ONE, + HAL_LL_UART_STOP_BITS_ONE_AND_A_HALF, + HAL_LL_UART_STOP_BITS_TWO, + + HAL_LL_UART_STOP_BITS_DEFAULT = HAL_LL_UART_STOP_BITS_ONE +} hal_ll_uart_stop_bits_t; + +/** + * @brief Predefined enum values for data bit selection. + */ +typedef enum +{ + HAL_LL_UART_DATA_BITS_7 = 0, + HAL_LL_UART_DATA_BITS_8, + HAL_LL_UART_DATA_BITS_9, + + HAL_LL_UART_DATA_BITS_DEFAULT = HAL_LL_UART_DATA_BITS_8 +} hal_ll_uart_data_bits_t; + +/** + * @brief I2C master low level pins config structure. + * + * The context structure for storing low level pin configuration + * for both SCL and SDA pins. + * + */ +typedef struct +{ + hal_ll_pin_af_t tx_pin; + hal_ll_pin_af_t rx_pin; +} hal_ll_uart_pins_t; + +/** + * @brief I2C master low level handle. + * + * The context for storing low level object handler. + * User is not to change these values or unexpected behaviour + * may occur. + */ +typedef struct +{ + handle_t *hal_ll_uart_handle; + handle_t *hal_drv_uart_handle; + bool init_ll_state; +} hal_ll_uart_handle_register_t; + +/** + * @brief Registers handler for future use. + * + * Registers low level and hal level handlers + * for use with appropriate functions. + * + * @param[in] tx_pin UART TX pin. + * @param[in] rx_pin UART RX pin. + * @param[in] *handle_map HAL layer local handle map. + * @param[in] *hal_module_id HAL layer module number. + + * @return hal_ll_err_t Module specific error. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_uart_register_handle( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_uart_handle_register_t *handle_map, uint8_t *hal_module_id ); + +/** + * @brief Configures specified module. + * + * Performs module configuration on the hardware + * level. Enables module specific clock gate and + * sets adequate alternate function values. + * + * @param[in] *handle HAL context object handle. + * + * @return hal_ll_err_t Module specific error. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_module_configure_uart( handle_t *handle ); + +/** + * @brief Registers interrupt handlers for future use. + * + * Registers low level interrupt handlers + * for use with appropriate functions. + * + * @param[in] handle HAL context object handle. + * @param[in] handler Predefined pointer function. + * @param[in] obj HAL context handle address. + + * @return None. + */ +void hal_ll_uart_register_irq_handler( handle_t *handle, hal_ll_uart_isr_t handler, handle_t obj ); + +/** + * @brief Sets desired baud rate. + * + * Initializes module with specified baud rate value. + * Take into consideration that if the difference + * between desired baud rate and actual baud + * rate the hw was initialized to is greater than + * 1%, baud rate shall not be set. + * If this occurs, return value shall be + * the error percentage. + * + * @param[in] handle HAL context object handle. + * @param[in] baud Desired baud rate value in Bits/s. + * + * @return Actual baud rate value the hw module was initialized to, + * or module specific error value if init failed. + */ +hal_ll_err_t hal_ll_uart_set_baud( handle_t *handle, uint32_t baud ); + +/** + * @brief Sets desired parity. + * + * Initializes module with specified parity value. + * + * @param[in] handle HAL context object handle. + * @param[in] parity One of pre-defined values. + * + * @return Re-init module state. If neccessary. + */ +hal_ll_err_t hal_ll_uart_set_parity( handle_t *handle, hal_ll_uart_parity_t parity ); + +/** + * @brief Sets desired stop bits. + * + * Initializes module with specified stop bits value. + * + * @param[in] handle HAL context object handle. + * @param[in] stop_bit One of pre-defined values. + * + * @return Re-init module state. If neccessary. + */ +hal_ll_err_t hal_ll_uart_set_stop_bits( handle_t *handle, hal_ll_uart_stop_bits_t stop_bit ); + +/** + * @brief Sets desired data bits. + * + * Initializes module with specified data bits value. + * + * @param[in] handle HAL context object handle. + * @param[in] data_bit One of pre-defined values. + * + * @return Re-init module state. If neccessary. + */ +hal_ll_err_t hal_ll_uart_set_data_bits( handle_t *handle, hal_ll_uart_data_bits_t data_bit ); + +/** + * @brief Enables module specific interrupt. + * + * Enables module specific interrupt and registers + * interrupt on hardware level and enables it. + * + * @param[in] handle HAL context object handle. + * @param[in] irq Chip interrupt IRQ value. + * + * @return void None. + */ +void hal_ll_uart_irq_enable( handle_t *handle, hal_ll_uart_irq_t irq ); + +/** + * @brief Disables module specific interrupt. + * + * Disables module specific interrupt. + * + * @param[in] handle HAL context object handle. + * @param[in] irq Chip interrupt IRQ value. + * + * @return void None. + */ +void hal_ll_uart_irq_disable( handle_t *handle, hal_ll_uart_irq_t irq ); + +/** + * @brief Performs read operation. + * + * Reads one byte on a hardware level. + * + * @param[in] handle HAL context object handle. + * + * @return uint8_t Data read from hw register. + */ +uint8_t hal_ll_uart_read( handle_t *handle ); + +/** + * @brief Performs write operation. + * + * Accesses hardware data registers and + * writes data directly to it. + * + * @param[in] handle HAL context object handle. + * @param[in] wr_data Data to be written. + * + * @return void None. + */ +void hal_ll_uart_write( handle_t *handle, uint8_t wr_data); + +/** + * @brief Closes UART HAL and HAL_LOW_LEVEL context object. + * + * De-allocates hardware resources for specific driver object and + * de-initializes the module on a hardware level. + * + * @param[in] *handle HAL context object handle. + * + * @return void None. + */ +void hal_ll_uart_close( handle_t *handle ); + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_UART_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/uart/hal_ll_uart_pin_map/implementations/doc_ds_1/hal_ll_uart_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/uart/hal_ll_uart_pin_map/implementations/doc_ds_1/hal_ll_uart_pin_map.h new file mode 100644 index 000000000..7bb8db72a --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/uart/hal_ll_uart_pin_map/implementations/doc_ds_1/hal_ll_uart_pin_map.h @@ -0,0 +1,157 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_uart_pin_map.h + * @brief UART HAL LOW LEVEL PIN MAPS. + */ + +#ifndef _HAL_LL_UART_PIN_MAP_H_ +#define _HAL_LL_UART_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_uart_module_num(_module_num) (_module_num - 1) +#define hal_ll_usart_module_num(_module_num) hal_ll_uart_module_num(_module_num) +#define hal_ll_lpuart_module_num(_module_num) hal_ll_uart_module_num(_module_num) + +/*!< @brief Pin structure */ +typedef struct +{ + uint8_t module_index; + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + uint32_t af; +} hal_ll_uart_pin_map_t; + +#ifdef UART_MODULE_1 +#define USART_MODULE_1 UART_MODULE_1 +#define UART1_BASE_ADDRESS (0x40013800UL) +#define UART1_BASE_ADDR UART1_BASE_ADDRESS +#define USART1_BASE_ADDR UART1_BASE_ADDRESS +#define USART1_BASE_ADDRESS UART1_BASE_ADDRESS +#define HAL_LL_UART1_BASE_ADDR UART1_BASE_ADDRESS +#define HAL_LL_USART1_BASE_ADDR UART1_BASE_ADDRESS +#define HAL_LL_UART1_BASE_ADDRESS UART1_BASE_ADDRESS +#define HAL_LL_USART1_BASE_ADDRESS UART1_BASE_ADDRESS +#endif +#ifdef UART_MODULE_2 +#define USART_MODULE_2 UART_MODULE_2 +#define UART2_BASE_ADDRESS (0x40004400UL) +#define UART2_BASE_ADDR UART2_BASE_ADDRESS +#define USART2_BASE_ADDR UART2_BASE_ADDRESS +#define USART2_BASE_ADDRESS UART2_BASE_ADDRESS +#define HAL_LL_UART2_BASE_ADDR UART2_BASE_ADDRESS +#define HAL_LL_USART2_BASE_ADDR UART2_BASE_ADDRESS +#define HAL_LL_UART2_BASE_ADDRESS UART2_BASE_ADDRESS +#define HAL_LL_USART2_BASE_ADDRESS UART2_BASE_ADDRESS +#endif + +/*!< @brief UART TX pins */ +static const hal_ll_uart_pin_map_t hal_ll_uart_tx_map[] = +{ + #ifdef USART1_TX_PA0_AF4 + {hal_ll_usart_module_num(USART_MODULE_1), PA0, USART1_BASE_ADDRESS, 4}, + #endif + #ifdef USART1_TX_PA9_AF1 + {hal_ll_usart_module_num(USART_MODULE_1), PA9, USART1_BASE_ADDRESS, 1}, + #endif + #ifdef USART1_TX_PB6_AF0 + {hal_ll_usart_module_num(USART_MODULE_1), PB6, USART1_BASE_ADDRESS, 0}, + #endif + #ifdef USART1_TX_PC14_AF0 + {hal_ll_usart_module_num(USART_MODULE_1), PC14, USART1_BASE_ADDRESS, 0}, + #endif + #ifdef USART2_TX_PA14_AF1 + {hal_ll_usart_module_num(USART_MODULE_2), PA14, USART2_BASE_ADDRESS, 1}, + #endif + #ifdef USART2_TX_PA2_AF1 + {hal_ll_usart_module_num(USART_MODULE_2), PA2, USART2_BASE_ADDRESS, 1}, + #endif + #ifdef USART2_TX_PA4_AF1 + {hal_ll_usart_module_num(USART_MODULE_2), PA4, USART2_BASE_ADDRESS, 1}, + #endif + #ifdef USART2_TX_PA8_AF1 + {hal_ll_usart_module_num(USART_MODULE_2), PA8, USART2_BASE_ADDRESS, 1}, + #endif + {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} + //------------ END TX +}; + +/*!< @brief UART RX pins */ +static const hal_ll_uart_pin_map_t hal_ll_uart_rx_map[] = +{ + #ifdef USART1_RX_PA10_AF1 + {hal_ll_usart_module_num(USART_MODULE_1), PA10, USART1_BASE_ADDRESS, 1}, + #endif + #ifdef USART1_RX_PA1_AF4 + {hal_ll_usart_module_num(USART_MODULE_1), PA1, USART1_BASE_ADDRESS, 4}, + #endif + #ifdef USART1_RX_PA8_AF14 + {hal_ll_usart_module_num(USART_MODULE_1), PA8, USART1_BASE_ADDRESS, 14}, + #endif + #ifdef USART1_RX_PB7_AF0 + {hal_ll_usart_module_num(USART_MODULE_1), PB7, USART1_BASE_ADDRESS, 0}, + #endif + #ifdef USART2_RX_PA13_AF4 + {hal_ll_usart_module_num(USART_MODULE_2), PA13, USART2_BASE_ADDRESS, 4}, + #endif + #ifdef USART2_RX_PA14_AF9 + {hal_ll_usart_module_num(USART_MODULE_2), PA14, USART2_BASE_ADDRESS, 9}, + #endif + #ifdef USART2_RX_PA3_AF1 + {hal_ll_usart_module_num(USART_MODULE_2), PA3, USART2_BASE_ADDRESS, 1}, + #endif + #ifdef USART2_RX_PA5_AF1 + {hal_ll_usart_module_num(USART_MODULE_2), PA5, USART2_BASE_ADDRESS, 1}, + #endif + {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} + //------------ END RX +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_UART_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/uart/hal_ll_uart_pin_map/implementations/doc_ds_160/hal_ll_uart_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/uart/hal_ll_uart_pin_map/implementations/doc_ds_160/hal_ll_uart_pin_map.h new file mode 100644 index 000000000..726c3bdab --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/uart/hal_ll_uart_pin_map/implementations/doc_ds_160/hal_ll_uart_pin_map.h @@ -0,0 +1,217 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_uart_pin_map.h + * @brief UART HAL LOW LEVEL PIN MAPS. + */ + +#ifndef _HAL_LL_UART_PIN_MAP_H_ +#define _HAL_LL_UART_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_uart_module_num(_module_num) (_module_num - 1) +#define hal_ll_usart_module_num(_module_num) hal_ll_uart_module_num(_module_num) +#define hal_ll_lpuart_module_num(_module_num) hal_ll_uart_module_num(_module_num) + +/*!< @brief Pin structure */ +typedef struct +{ + uint8_t module_index; + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + uint32_t af; +} hal_ll_uart_pin_map_t; + +#ifdef UART_MODULE_1 +#define USART_MODULE_1 UART_MODULE_1 +#define UART1_BASE_ADDRESS (0x40013800UL) +#define UART1_BASE_ADDR UART1_BASE_ADDRESS +#define USART1_BASE_ADDR UART1_BASE_ADDRESS +#define USART1_BASE_ADDRESS UART1_BASE_ADDRESS +#define HAL_LL_UART1_BASE_ADDR UART1_BASE_ADDRESS +#define HAL_LL_USART1_BASE_ADDR UART1_BASE_ADDRESS +#define HAL_LL_UART1_BASE_ADDRESS UART1_BASE_ADDRESS +#define HAL_LL_USART1_BASE_ADDRESS UART1_BASE_ADDRESS +#endif +#ifdef UART_MODULE_2 +#define USART_MODULE_2 UART_MODULE_2 +#define UART2_BASE_ADDRESS (0x40004400UL) +#define UART2_BASE_ADDR UART2_BASE_ADDRESS +#define USART2_BASE_ADDR UART2_BASE_ADDRESS +#define USART2_BASE_ADDRESS UART2_BASE_ADDRESS +#define HAL_LL_UART2_BASE_ADDR UART2_BASE_ADDRESS +#define HAL_LL_USART2_BASE_ADDR UART2_BASE_ADDRESS +#define HAL_LL_UART2_BASE_ADDRESS UART2_BASE_ADDRESS +#define HAL_LL_USART2_BASE_ADDRESS UART2_BASE_ADDRESS +#endif +#ifdef UART_MODULE_3 +#define USART_MODULE_3 UART_MODULE_3 +#define UART3_BASE_ADDRESS (0x40004800UL) +#define UART3_BASE_ADDR UART3_BASE_ADDRESS +#define USART3_BASE_ADDR UART3_BASE_ADDRESS +#define USART3_BASE_ADDRESS UART3_BASE_ADDRESS +#define HAL_LL_UART3_BASE_ADDR UART3_BASE_ADDRESS +#define HAL_LL_USART3_BASE_ADDR UART3_BASE_ADDRESS +#define HAL_LL_UART3_BASE_ADDRESS UART3_BASE_ADDRESS +#define HAL_LL_USART3_BASE_ADDRESS UART3_BASE_ADDRESS +#endif +#ifdef UART_MODULE_4 +#define USART_MODULE_4 UART_MODULE_4 +#define UART4_BASE_ADDRESS (0x40004C00UL) +#define UART4_BASE_ADDR UART4_BASE_ADDRESS +#define USART4_BASE_ADDR UART4_BASE_ADDRESS +#define USART4_BASE_ADDRESS UART4_BASE_ADDRESS +#define HAL_LL_UART4_BASE_ADDR UART4_BASE_ADDRESS +#define HAL_LL_USART4_BASE_ADDR UART4_BASE_ADDRESS +#define HAL_LL_UART4_BASE_ADDRESS UART4_BASE_ADDRESS +#define HAL_LL_USART4_BASE_ADDRESS UART4_BASE_ADDRESS +#endif +#ifdef UART_MODULE_5 +#define USART_MODULE_5 UART_MODULE_5 +#define UART5_BASE_ADDRESS (0x40005000UL) +#define UART5_BASE_ADDR UART5_BASE_ADDRESS +#define USART5_BASE_ADDR UART5_BASE_ADDRESS +#define USART5_BASE_ADDRESS UART5_BASE_ADDRESS +#define HAL_LL_UART5_BASE_ADDR UART5_BASE_ADDRESS +#define HAL_LL_USART5_BASE_ADDR UART5_BASE_ADDRESS +#define HAL_LL_UART5_BASE_ADDRESS UART5_BASE_ADDRESS +#define HAL_LL_USART5_BASE_ADDRESS UART5_BASE_ADDRESS +#endif + +/*!< @brief UART TX pins */ +static const hal_ll_uart_pin_map_t hal_ll_uart_tx_map[] = +{ + #ifdef UART4_TX_PA0_AF8 + {hal_ll_uart_module_num(UART_MODULE_4), PA0, UART4_BASE_ADDRESS, 8}, + #endif + #ifdef UART4_TX_PC10_AF8 + {hal_ll_uart_module_num(UART_MODULE_4), PC10, UART4_BASE_ADDRESS, 8}, + #endif + #ifdef UART5_TX_PC12_AF8 + {hal_ll_uart_module_num(UART_MODULE_5), PC12, UART5_BASE_ADDRESS, 8}, + #endif + #ifdef USART1_TX_PA9_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PA9, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART1_TX_PB6_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PB6, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART1_TX_PG9_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PG9, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART2_TX_PA2_AF7 + {hal_ll_usart_module_num(USART_MODULE_2), PA2, USART2_BASE_ADDRESS, 7}, + #endif + #ifdef USART2_TX_PD5_AF7 + {hal_ll_usart_module_num(USART_MODULE_2), PD5, USART2_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_TX_PB10_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PB10, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_TX_PC10_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PC10, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_TX_PC4_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PC4, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_TX_PD8_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PD8, USART3_BASE_ADDRESS, 7}, + #endif + {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} + //------------ END TX +}; + +/*!< @brief UART RX pins */ +static const hal_ll_uart_pin_map_t hal_ll_uart_rx_map[] = +{ + #ifdef UART4_RX_PA1_AF8 + {hal_ll_uart_module_num(UART_MODULE_4), PA1, UART4_BASE_ADDRESS, 8}, + #endif + #ifdef UART4_RX_PC11_AF8 + {hal_ll_uart_module_num(UART_MODULE_4), PC11, UART4_BASE_ADDRESS, 8}, + #endif + #ifdef UART5_RX_PD2_AF8 + {hal_ll_uart_module_num(UART_MODULE_5), PD2, UART5_BASE_ADDRESS, 8}, + #endif + #ifdef USART1_RX_PA10_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PA10, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART1_RX_PB7_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PB7, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART1_RX_PG10_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PG10, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART2_RX_PA15_AF3 + {hal_ll_usart_module_num(USART_MODULE_2), PA15, USART2_BASE_ADDRESS, 3}, + #endif + #ifdef USART2_RX_PA3_AF7 + {hal_ll_usart_module_num(USART_MODULE_2), PA3, USART2_BASE_ADDRESS, 7}, + #endif + #ifdef USART2_RX_PD6_AF7 + {hal_ll_usart_module_num(USART_MODULE_2), PD6, USART2_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_RX_PB11_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PB11, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_RX_PC11_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PC11, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_RX_PC5_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PC5, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_RX_PD9_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PD9, USART3_BASE_ADDRESS, 7}, + #endif + {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} + //------------ END RX +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_UART_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/uart/hal_ll_uart_pin_map/implementations/doc_ds_161/hal_ll_uart_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/uart/hal_ll_uart_pin_map/implementations/doc_ds_161/hal_ll_uart_pin_map.h new file mode 100644 index 000000000..726c3bdab --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/uart/hal_ll_uart_pin_map/implementations/doc_ds_161/hal_ll_uart_pin_map.h @@ -0,0 +1,217 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_uart_pin_map.h + * @brief UART HAL LOW LEVEL PIN MAPS. + */ + +#ifndef _HAL_LL_UART_PIN_MAP_H_ +#define _HAL_LL_UART_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_uart_module_num(_module_num) (_module_num - 1) +#define hal_ll_usart_module_num(_module_num) hal_ll_uart_module_num(_module_num) +#define hal_ll_lpuart_module_num(_module_num) hal_ll_uart_module_num(_module_num) + +/*!< @brief Pin structure */ +typedef struct +{ + uint8_t module_index; + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + uint32_t af; +} hal_ll_uart_pin_map_t; + +#ifdef UART_MODULE_1 +#define USART_MODULE_1 UART_MODULE_1 +#define UART1_BASE_ADDRESS (0x40013800UL) +#define UART1_BASE_ADDR UART1_BASE_ADDRESS +#define USART1_BASE_ADDR UART1_BASE_ADDRESS +#define USART1_BASE_ADDRESS UART1_BASE_ADDRESS +#define HAL_LL_UART1_BASE_ADDR UART1_BASE_ADDRESS +#define HAL_LL_USART1_BASE_ADDR UART1_BASE_ADDRESS +#define HAL_LL_UART1_BASE_ADDRESS UART1_BASE_ADDRESS +#define HAL_LL_USART1_BASE_ADDRESS UART1_BASE_ADDRESS +#endif +#ifdef UART_MODULE_2 +#define USART_MODULE_2 UART_MODULE_2 +#define UART2_BASE_ADDRESS (0x40004400UL) +#define UART2_BASE_ADDR UART2_BASE_ADDRESS +#define USART2_BASE_ADDR UART2_BASE_ADDRESS +#define USART2_BASE_ADDRESS UART2_BASE_ADDRESS +#define HAL_LL_UART2_BASE_ADDR UART2_BASE_ADDRESS +#define HAL_LL_USART2_BASE_ADDR UART2_BASE_ADDRESS +#define HAL_LL_UART2_BASE_ADDRESS UART2_BASE_ADDRESS +#define HAL_LL_USART2_BASE_ADDRESS UART2_BASE_ADDRESS +#endif +#ifdef UART_MODULE_3 +#define USART_MODULE_3 UART_MODULE_3 +#define UART3_BASE_ADDRESS (0x40004800UL) +#define UART3_BASE_ADDR UART3_BASE_ADDRESS +#define USART3_BASE_ADDR UART3_BASE_ADDRESS +#define USART3_BASE_ADDRESS UART3_BASE_ADDRESS +#define HAL_LL_UART3_BASE_ADDR UART3_BASE_ADDRESS +#define HAL_LL_USART3_BASE_ADDR UART3_BASE_ADDRESS +#define HAL_LL_UART3_BASE_ADDRESS UART3_BASE_ADDRESS +#define HAL_LL_USART3_BASE_ADDRESS UART3_BASE_ADDRESS +#endif +#ifdef UART_MODULE_4 +#define USART_MODULE_4 UART_MODULE_4 +#define UART4_BASE_ADDRESS (0x40004C00UL) +#define UART4_BASE_ADDR UART4_BASE_ADDRESS +#define USART4_BASE_ADDR UART4_BASE_ADDRESS +#define USART4_BASE_ADDRESS UART4_BASE_ADDRESS +#define HAL_LL_UART4_BASE_ADDR UART4_BASE_ADDRESS +#define HAL_LL_USART4_BASE_ADDR UART4_BASE_ADDRESS +#define HAL_LL_UART4_BASE_ADDRESS UART4_BASE_ADDRESS +#define HAL_LL_USART4_BASE_ADDRESS UART4_BASE_ADDRESS +#endif +#ifdef UART_MODULE_5 +#define USART_MODULE_5 UART_MODULE_5 +#define UART5_BASE_ADDRESS (0x40005000UL) +#define UART5_BASE_ADDR UART5_BASE_ADDRESS +#define USART5_BASE_ADDR UART5_BASE_ADDRESS +#define USART5_BASE_ADDRESS UART5_BASE_ADDRESS +#define HAL_LL_UART5_BASE_ADDR UART5_BASE_ADDRESS +#define HAL_LL_USART5_BASE_ADDR UART5_BASE_ADDRESS +#define HAL_LL_UART5_BASE_ADDRESS UART5_BASE_ADDRESS +#define HAL_LL_USART5_BASE_ADDRESS UART5_BASE_ADDRESS +#endif + +/*!< @brief UART TX pins */ +static const hal_ll_uart_pin_map_t hal_ll_uart_tx_map[] = +{ + #ifdef UART4_TX_PA0_AF8 + {hal_ll_uart_module_num(UART_MODULE_4), PA0, UART4_BASE_ADDRESS, 8}, + #endif + #ifdef UART4_TX_PC10_AF8 + {hal_ll_uart_module_num(UART_MODULE_4), PC10, UART4_BASE_ADDRESS, 8}, + #endif + #ifdef UART5_TX_PC12_AF8 + {hal_ll_uart_module_num(UART_MODULE_5), PC12, UART5_BASE_ADDRESS, 8}, + #endif + #ifdef USART1_TX_PA9_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PA9, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART1_TX_PB6_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PB6, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART1_TX_PG9_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PG9, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART2_TX_PA2_AF7 + {hal_ll_usart_module_num(USART_MODULE_2), PA2, USART2_BASE_ADDRESS, 7}, + #endif + #ifdef USART2_TX_PD5_AF7 + {hal_ll_usart_module_num(USART_MODULE_2), PD5, USART2_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_TX_PB10_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PB10, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_TX_PC10_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PC10, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_TX_PC4_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PC4, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_TX_PD8_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PD8, USART3_BASE_ADDRESS, 7}, + #endif + {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} + //------------ END TX +}; + +/*!< @brief UART RX pins */ +static const hal_ll_uart_pin_map_t hal_ll_uart_rx_map[] = +{ + #ifdef UART4_RX_PA1_AF8 + {hal_ll_uart_module_num(UART_MODULE_4), PA1, UART4_BASE_ADDRESS, 8}, + #endif + #ifdef UART4_RX_PC11_AF8 + {hal_ll_uart_module_num(UART_MODULE_4), PC11, UART4_BASE_ADDRESS, 8}, + #endif + #ifdef UART5_RX_PD2_AF8 + {hal_ll_uart_module_num(UART_MODULE_5), PD2, UART5_BASE_ADDRESS, 8}, + #endif + #ifdef USART1_RX_PA10_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PA10, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART1_RX_PB7_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PB7, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART1_RX_PG10_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PG10, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART2_RX_PA15_AF3 + {hal_ll_usart_module_num(USART_MODULE_2), PA15, USART2_BASE_ADDRESS, 3}, + #endif + #ifdef USART2_RX_PA3_AF7 + {hal_ll_usart_module_num(USART_MODULE_2), PA3, USART2_BASE_ADDRESS, 7}, + #endif + #ifdef USART2_RX_PD6_AF7 + {hal_ll_usart_module_num(USART_MODULE_2), PD6, USART2_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_RX_PB11_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PB11, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_RX_PC11_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PC11, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_RX_PC5_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PC5, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_RX_PD9_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PD9, USART3_BASE_ADDRESS, 7}, + #endif + {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} + //------------ END RX +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_UART_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/uart/hal_ll_uart_pin_map/implementations/doc_ds_2/hal_ll_uart_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/uart/hal_ll_uart_pin_map/implementations/doc_ds_2/hal_ll_uart_pin_map.h new file mode 100644 index 000000000..f16528dc6 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/uart/hal_ll_uart_pin_map/implementations/doc_ds_2/hal_ll_uart_pin_map.h @@ -0,0 +1,163 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_uart_pin_map.h + * @brief UART HAL LOW LEVEL PIN MAPS. + */ + +#ifndef _HAL_LL_UART_PIN_MAP_H_ +#define _HAL_LL_UART_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_uart_module_num(_module_num) (_module_num - 1) +#define hal_ll_usart_module_num(_module_num) hal_ll_uart_module_num(_module_num) +#define hal_ll_lpuart_module_num(_module_num) hal_ll_uart_module_num(_module_num) + +/*!< @brief Pin structure */ +typedef struct +{ + uint8_t module_index; + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + uint32_t af; +} hal_ll_uart_pin_map_t; + +#ifdef UART_MODULE_1 +#define USART_MODULE_1 UART_MODULE_1 +#define UART1_BASE_ADDRESS (0x40013800UL) +#define UART1_BASE_ADDR UART1_BASE_ADDRESS +#define USART1_BASE_ADDR UART1_BASE_ADDRESS +#define USART1_BASE_ADDRESS UART1_BASE_ADDRESS +#define HAL_LL_UART1_BASE_ADDR UART1_BASE_ADDRESS +#define HAL_LL_USART1_BASE_ADDR UART1_BASE_ADDRESS +#define HAL_LL_UART1_BASE_ADDRESS UART1_BASE_ADDRESS +#define HAL_LL_USART1_BASE_ADDRESS UART1_BASE_ADDRESS +#endif +#ifdef UART_MODULE_2 +#define USART_MODULE_2 UART_MODULE_2 +#define UART2_BASE_ADDRESS (0x40004400UL) +#define UART2_BASE_ADDR UART2_BASE_ADDRESS +#define USART2_BASE_ADDR UART2_BASE_ADDRESS +#define USART2_BASE_ADDRESS UART2_BASE_ADDRESS +#define HAL_LL_UART2_BASE_ADDR UART2_BASE_ADDRESS +#define HAL_LL_USART2_BASE_ADDR UART2_BASE_ADDRESS +#define HAL_LL_UART2_BASE_ADDRESS UART2_BASE_ADDRESS +#define HAL_LL_USART2_BASE_ADDRESS UART2_BASE_ADDRESS +#endif + +/*!< @brief UART TX pins */ +static const hal_ll_uart_pin_map_t hal_ll_uart_tx_map[] = +{ + #ifdef USART1_TX_PA0_AF4 + {hal_ll_usart_module_num(USART_MODULE_1), PA0, USART1_BASE_ADDRESS, 4}, + #endif + #ifdef USART1_TX_PB6_AF0 + {hal_ll_usart_module_num(USART_MODULE_1), PB6, USART1_BASE_ADDRESS, 0}, + #endif + #ifdef USART1_TX_PC14_AF0 + {hal_ll_usart_module_num(USART_MODULE_1), PC14, USART1_BASE_ADDRESS, 0}, + #endif + #ifdef USART2_TX_PA14_AF1 + {hal_ll_usart_module_num(USART_MODULE_2), PA14, USART2_BASE_ADDRESS, 1}, + #endif + #ifdef USART2_TX_PA2_AF1 + {hal_ll_usart_module_num(USART_MODULE_2), PA2, USART2_BASE_ADDRESS, 1}, + #endif + #ifdef USART2_TX_PA4_AF1 + {hal_ll_usart_module_num(USART_MODULE_2), PA4, USART2_BASE_ADDRESS, 1}, + #endif + #ifdef USART2_TX_PA8_AF1 + {hal_ll_usart_module_num(USART_MODULE_2), PA8, USART2_BASE_ADDRESS, 1}, + #endif + #ifdef USART1_TX_PA9_AF1 + {hal_ll_usart_module_num(USART_MODULE_1), PA9, USART1_BASE_ADDRESS, 1}, + #endif + {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} + //------------ END TX +}; + +/*!< @brief UART RX pins */ +static const hal_ll_uart_pin_map_t hal_ll_uart_rx_map[] = +{ + #ifdef USART1_RX_PA1_AF4 + {hal_ll_usart_module_num(USART_MODULE_1), PA1, USART1_BASE_ADDRESS, 4}, + #endif + #ifdef USART1_RX_PA8_AF14 + {hal_ll_usart_module_num(USART_MODULE_1), PA8, USART1_BASE_ADDRESS, 14}, + #endif + #ifdef USART1_RX_PB7_AF0 + {hal_ll_usart_module_num(USART_MODULE_1), PB7, USART1_BASE_ADDRESS, 0}, + #endif + #ifdef USART2_RX_PA13_AF4 + {hal_ll_usart_module_num(USART_MODULE_2), PA13, USART2_BASE_ADDRESS, 4}, + #endif + #ifdef USART2_RX_PA14_AF9 + {hal_ll_usart_module_num(USART_MODULE_2), PA14, USART2_BASE_ADDRESS, 9}, + #endif + #ifdef USART2_RX_PA15_AF1 + {hal_ll_usart_module_num(USART_MODULE_2), PA15, USART2_BASE_ADDRESS, 1}, + #endif + #ifdef USART2_RX_PA3_AF1 + {hal_ll_usart_module_num(USART_MODULE_2), PA3, USART2_BASE_ADDRESS, 1}, + #endif + #ifdef USART2_RX_PA5_AF1 + {hal_ll_usart_module_num(USART_MODULE_2), PA5, USART2_BASE_ADDRESS, 1}, + #endif + #ifdef USART1_RX_PA10_AF1 + {hal_ll_usart_module_num(USART_MODULE_1), PA10, USART1_BASE_ADDRESS, 1}, + #endif + #ifdef USART1_RX_PB2_AF0 + {hal_ll_usart_module_num(USART_MODULE_1), PB2, USART1_BASE_ADDRESS, 0}, + #endif + {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} + //------------ END RX +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_UART_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/uart/hal_ll_uart_pin_map/implementations/doc_ds_74/hal_ll_uart_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/uart/hal_ll_uart_pin_map/implementations/doc_ds_74/hal_ll_uart_pin_map.h new file mode 100644 index 000000000..2dee4aa73 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/uart/hal_ll_uart_pin_map/implementations/doc_ds_74/hal_ll_uart_pin_map.h @@ -0,0 +1,133 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_uart_pin_map.h + * @brief UART HAL LOW LEVEL PIN MAPS. + */ + +#ifndef _HAL_LL_UART_PIN_MAP_H_ +#define _HAL_LL_UART_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_uart_module_num(_module_num) (_module_num - 1) +#define hal_ll_usart_module_num(_module_num) hal_ll_uart_module_num(_module_num) +#define hal_ll_lpuart_module_num(_module_num) hal_ll_uart_module_num(_module_num) + +/*!< @brief Pin structure */ +typedef struct +{ + uint8_t module_index; + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + uint32_t af; +} hal_ll_uart_pin_map_t; + +#ifdef UART_MODULE_1 +#define USART_MODULE_1 UART_MODULE_1 +#define UART1_BASE_ADDRESS (0x40013800UL) +#define UART1_BASE_ADDR UART1_BASE_ADDRESS +#define USART1_BASE_ADDR UART1_BASE_ADDRESS +#define USART1_BASE_ADDRESS UART1_BASE_ADDRESS +#define HAL_LL_UART1_BASE_ADDR UART1_BASE_ADDRESS +#define HAL_LL_USART1_BASE_ADDR UART1_BASE_ADDRESS +#define HAL_LL_UART1_BASE_ADDRESS UART1_BASE_ADDRESS +#define HAL_LL_USART1_BASE_ADDRESS UART1_BASE_ADDRESS +#endif +#ifdef UART_MODULE_2 +#define USART_MODULE_2 UART_MODULE_2 +#define UART2_BASE_ADDRESS (0x40004400UL) +#define UART2_BASE_ADDR UART2_BASE_ADDRESS +#define USART2_BASE_ADDR UART2_BASE_ADDRESS +#define USART2_BASE_ADDRESS UART2_BASE_ADDRESS +#define HAL_LL_UART2_BASE_ADDR UART2_BASE_ADDRESS +#define HAL_LL_USART2_BASE_ADDR UART2_BASE_ADDRESS +#define HAL_LL_UART2_BASE_ADDRESS UART2_BASE_ADDRESS +#define HAL_LL_USART2_BASE_ADDRESS UART2_BASE_ADDRESS +#endif + +/*!< @brief UART TX pins */ +static const hal_ll_uart_pin_map_t hal_ll_uart_tx_map[] = +{ + #ifdef USART1_TX_PA9_AF1 + {hal_ll_usart_module_num(USART_MODULE_1), PA9, USART1_BASE_ADDRESS, 1}, + #endif + #ifdef USART1_TX_PB6_AF0 + {hal_ll_usart_module_num(USART_MODULE_1), PB6, USART1_BASE_ADDRESS, 0}, + #endif + #ifdef USART2_TX_PA14_AF1 + {hal_ll_usart_module_num(USART_MODULE_2), PA14, USART2_BASE_ADDRESS, 1}, + #endif + #ifdef USART2_TX_PA2_AF1 + {hal_ll_usart_module_num(USART_MODULE_2), PA2, USART2_BASE_ADDRESS, 1}, + #endif + {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} + //------------ END TX +}; + +/*!< @brief UART RX pins */ +static const hal_ll_uart_pin_map_t hal_ll_uart_rx_map[] = +{ + #ifdef USART1_RX_PA10_AF1 + {hal_ll_usart_module_num(USART_MODULE_1), PA10, USART1_BASE_ADDRESS, 1}, + #endif + #ifdef USART1_RX_PB7_AF0 + {hal_ll_usart_module_num(USART_MODULE_1), PB7, USART1_BASE_ADDRESS, 0}, + #endif + #ifdef USART2_RX_PA15_AF1 + {hal_ll_usart_module_num(USART_MODULE_2), PA15, USART2_BASE_ADDRESS, 1}, + #endif + #ifdef USART2_RX_PA3_AF1 + {hal_ll_usart_module_num(USART_MODULE_2), PA3, USART2_BASE_ADDRESS, 1}, + #endif + {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} + //------------ END RX +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_UART_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/uart/hal_ll_uart_pin_map/implementations/doc_ds_75/hal_ll_uart_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/uart/hal_ll_uart_pin_map/implementations/doc_ds_75/hal_ll_uart_pin_map.h new file mode 100644 index 000000000..2dee4aa73 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/uart/hal_ll_uart_pin_map/implementations/doc_ds_75/hal_ll_uart_pin_map.h @@ -0,0 +1,133 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_uart_pin_map.h + * @brief UART HAL LOW LEVEL PIN MAPS. + */ + +#ifndef _HAL_LL_UART_PIN_MAP_H_ +#define _HAL_LL_UART_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_uart_module_num(_module_num) (_module_num - 1) +#define hal_ll_usart_module_num(_module_num) hal_ll_uart_module_num(_module_num) +#define hal_ll_lpuart_module_num(_module_num) hal_ll_uart_module_num(_module_num) + +/*!< @brief Pin structure */ +typedef struct +{ + uint8_t module_index; + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + uint32_t af; +} hal_ll_uart_pin_map_t; + +#ifdef UART_MODULE_1 +#define USART_MODULE_1 UART_MODULE_1 +#define UART1_BASE_ADDRESS (0x40013800UL) +#define UART1_BASE_ADDR UART1_BASE_ADDRESS +#define USART1_BASE_ADDR UART1_BASE_ADDRESS +#define USART1_BASE_ADDRESS UART1_BASE_ADDRESS +#define HAL_LL_UART1_BASE_ADDR UART1_BASE_ADDRESS +#define HAL_LL_USART1_BASE_ADDR UART1_BASE_ADDRESS +#define HAL_LL_UART1_BASE_ADDRESS UART1_BASE_ADDRESS +#define HAL_LL_USART1_BASE_ADDRESS UART1_BASE_ADDRESS +#endif +#ifdef UART_MODULE_2 +#define USART_MODULE_2 UART_MODULE_2 +#define UART2_BASE_ADDRESS (0x40004400UL) +#define UART2_BASE_ADDR UART2_BASE_ADDRESS +#define USART2_BASE_ADDR UART2_BASE_ADDRESS +#define USART2_BASE_ADDRESS UART2_BASE_ADDRESS +#define HAL_LL_UART2_BASE_ADDR UART2_BASE_ADDRESS +#define HAL_LL_USART2_BASE_ADDR UART2_BASE_ADDRESS +#define HAL_LL_UART2_BASE_ADDRESS UART2_BASE_ADDRESS +#define HAL_LL_USART2_BASE_ADDRESS UART2_BASE_ADDRESS +#endif + +/*!< @brief UART TX pins */ +static const hal_ll_uart_pin_map_t hal_ll_uart_tx_map[] = +{ + #ifdef USART1_TX_PA9_AF1 + {hal_ll_usart_module_num(USART_MODULE_1), PA9, USART1_BASE_ADDRESS, 1}, + #endif + #ifdef USART1_TX_PB6_AF0 + {hal_ll_usart_module_num(USART_MODULE_1), PB6, USART1_BASE_ADDRESS, 0}, + #endif + #ifdef USART2_TX_PA14_AF1 + {hal_ll_usart_module_num(USART_MODULE_2), PA14, USART2_BASE_ADDRESS, 1}, + #endif + #ifdef USART2_TX_PA2_AF1 + {hal_ll_usart_module_num(USART_MODULE_2), PA2, USART2_BASE_ADDRESS, 1}, + #endif + {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} + //------------ END TX +}; + +/*!< @brief UART RX pins */ +static const hal_ll_uart_pin_map_t hal_ll_uart_rx_map[] = +{ + #ifdef USART1_RX_PA10_AF1 + {hal_ll_usart_module_num(USART_MODULE_1), PA10, USART1_BASE_ADDRESS, 1}, + #endif + #ifdef USART1_RX_PB7_AF0 + {hal_ll_usart_module_num(USART_MODULE_1), PB7, USART1_BASE_ADDRESS, 0}, + #endif + #ifdef USART2_RX_PA15_AF1 + {hal_ll_usart_module_num(USART_MODULE_2), PA15, USART2_BASE_ADDRESS, 1}, + #endif + #ifdef USART2_RX_PA3_AF1 + {hal_ll_usart_module_num(USART_MODULE_2), PA3, USART2_BASE_ADDRESS, 1}, + #endif + {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} + //------------ END RX +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_UART_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/uart/hal_ll_uart_pin_map/implementations/doc_ds_80/hal_ll_uart_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/uart/hal_ll_uart_pin_map/implementations/doc_ds_80/hal_ll_uart_pin_map.h new file mode 100644 index 000000000..3f8309782 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/uart/hal_ll_uart_pin_map/implementations/doc_ds_80/hal_ll_uart_pin_map.h @@ -0,0 +1,297 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_uart_pin_map.h + * @brief UART HAL LOW LEVEL PIN MAPS. + */ + +#ifndef _HAL_LL_UART_PIN_MAP_H_ +#define _HAL_LL_UART_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_uart_module_num(_module_num) (_module_num - 1) +#define hal_ll_usart_module_num(_module_num) hal_ll_uart_module_num(_module_num) +#define hal_ll_lpuart_module_num(_module_num) hal_ll_uart_module_num(_module_num) + +/*!< @brief Pin structure */ +typedef struct +{ + uint8_t module_index; + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + uint32_t af; +} hal_ll_uart_pin_map_t; + +#ifdef UART_MODULE_1 +#define USART_MODULE_1 UART_MODULE_1 +#define UART1_BASE_ADDRESS (0x40013800UL) +#define UART1_BASE_ADDR UART1_BASE_ADDRESS +#define USART1_BASE_ADDR UART1_BASE_ADDRESS +#define USART1_BASE_ADDRESS UART1_BASE_ADDRESS +#define HAL_LL_UART1_BASE_ADDR UART1_BASE_ADDRESS +#define HAL_LL_USART1_BASE_ADDR UART1_BASE_ADDRESS +#define HAL_LL_UART1_BASE_ADDRESS UART1_BASE_ADDRESS +#define HAL_LL_USART1_BASE_ADDRESS UART1_BASE_ADDRESS +#endif +#ifdef UART_MODULE_2 +#define USART_MODULE_2 UART_MODULE_2 +#define UART2_BASE_ADDRESS (0x40004400UL) +#define UART2_BASE_ADDR UART2_BASE_ADDRESS +#define USART2_BASE_ADDR UART2_BASE_ADDRESS +#define USART2_BASE_ADDRESS UART2_BASE_ADDRESS +#define HAL_LL_UART2_BASE_ADDR UART2_BASE_ADDRESS +#define HAL_LL_USART2_BASE_ADDR UART2_BASE_ADDRESS +#define HAL_LL_UART2_BASE_ADDRESS UART2_BASE_ADDRESS +#define HAL_LL_USART2_BASE_ADDRESS UART2_BASE_ADDRESS +#endif +#ifdef UART_MODULE_3 +#define USART_MODULE_3 UART_MODULE_3 +#define UART3_BASE_ADDRESS (0x40004800UL) +#define UART3_BASE_ADDR UART3_BASE_ADDRESS +#define USART3_BASE_ADDR UART3_BASE_ADDRESS +#define USART3_BASE_ADDRESS UART3_BASE_ADDRESS +#define HAL_LL_UART3_BASE_ADDR UART3_BASE_ADDRESS +#define HAL_LL_USART3_BASE_ADDR UART3_BASE_ADDRESS +#define HAL_LL_UART3_BASE_ADDRESS UART3_BASE_ADDRESS +#define HAL_LL_USART3_BASE_ADDRESS UART3_BASE_ADDRESS +#endif +#ifdef UART_MODULE_4 +#define USART_MODULE_4 UART_MODULE_4 +#define UART4_BASE_ADDRESS (0x40004C00UL) +#define UART4_BASE_ADDR UART4_BASE_ADDRESS +#define USART4_BASE_ADDR UART4_BASE_ADDRESS +#define USART4_BASE_ADDRESS UART4_BASE_ADDRESS +#define HAL_LL_UART4_BASE_ADDR UART4_BASE_ADDRESS +#define HAL_LL_USART4_BASE_ADDR UART4_BASE_ADDRESS +#define HAL_LL_UART4_BASE_ADDRESS UART4_BASE_ADDRESS +#define HAL_LL_USART4_BASE_ADDRESS UART4_BASE_ADDRESS +#endif +#ifdef UART_MODULE_5 +#define USART_MODULE_5 UART_MODULE_5 +#define UART5_BASE_ADDRESS (0x40005000UL) +#define UART5_BASE_ADDR UART5_BASE_ADDRESS +#define USART5_BASE_ADDR UART5_BASE_ADDRESS +#define USART5_BASE_ADDRESS UART5_BASE_ADDRESS +#define HAL_LL_UART5_BASE_ADDR UART5_BASE_ADDRESS +#define HAL_LL_USART5_BASE_ADDR UART5_BASE_ADDRESS +#define HAL_LL_UART5_BASE_ADDRESS UART5_BASE_ADDRESS +#define HAL_LL_USART5_BASE_ADDRESS UART5_BASE_ADDRESS +#endif +#ifdef UART_MODULE_6 +#define USART_MODULE_6 UART_MODULE_6 +#define UART6_BASE_ADDRESS (0x40013C00UL) +#define UART6_BASE_ADDR UART6_BASE_ADDRESS +#define USART6_BASE_ADDR UART6_BASE_ADDRESS +#define USART6_BASE_ADDRESS UART6_BASE_ADDRESS +#define HAL_LL_UART6_BASE_ADDR UART6_BASE_ADDRESS +#define HAL_LL_USART6_BASE_ADDR UART6_BASE_ADDRESS +#define HAL_LL_UART6_BASE_ADDRESS UART6_BASE_ADDRESS +#define HAL_LL_USART6_BASE_ADDRESS UART6_BASE_ADDRESS +#endif + +/*!< @brief UART TX pins */ +static const hal_ll_uart_pin_map_t hal_ll_uart_tx_map[] = +{ + #ifdef USART1_TX_PA9_AF1 + {hal_ll_usart_module_num(USART_MODULE_1), PA9, USART1_BASE_ADDRESS, 1}, + #endif + #ifdef USART1_TX_PB6_AF0 + {hal_ll_usart_module_num(USART_MODULE_1), PB6, USART1_BASE_ADDRESS, 0}, + #endif + #ifdef USART1_TX_PC4_AF1 + {hal_ll_usart_module_num(USART_MODULE_1), PC4, USART1_BASE_ADDRESS, 1}, + #endif + #ifdef USART2_TX_PA14_AF1 + {hal_ll_usart_module_num(USART_MODULE_2), PA14, USART2_BASE_ADDRESS, 1}, + #endif + #ifdef USART2_TX_PA2_AF1 + {hal_ll_usart_module_num(USART_MODULE_2), PA2, USART2_BASE_ADDRESS, 1}, + #endif + #ifdef USART2_TX_PD5_AF0 + {hal_ll_usart_module_num(USART_MODULE_2), PD5, USART2_BASE_ADDRESS, 0}, + #endif + #ifdef USART3_TX_PA5_AF4 + {hal_ll_usart_module_num(USART_MODULE_3), PA5, USART3_BASE_ADDRESS, 4}, + #endif + #ifdef USART3_TX_PB10_AF4 + {hal_ll_usart_module_num(USART_MODULE_3), PB10, USART3_BASE_ADDRESS, 4}, + #endif + #ifdef USART3_TX_PB2_AF4 + {hal_ll_usart_module_num(USART_MODULE_3), PB2, USART3_BASE_ADDRESS, 4}, + #endif + #ifdef USART3_TX_PB8_AF4 + {hal_ll_usart_module_num(USART_MODULE_3), PB8, USART3_BASE_ADDRESS, 4}, + #endif + #ifdef USART3_TX_PC10_AF0 + {hal_ll_usart_module_num(USART_MODULE_3), PC10, USART3_BASE_ADDRESS, 0}, + #endif + #ifdef USART3_TX_PC4_AF0 + {hal_ll_usart_module_num(USART_MODULE_3), PC4, USART3_BASE_ADDRESS, 0}, + #endif + #ifdef USART3_TX_PD8_AF0 + {hal_ll_usart_module_num(USART_MODULE_3), PD8, USART3_BASE_ADDRESS, 0}, + #endif + #ifdef USART4_TX_PA0_AF4 + {hal_ll_usart_module_num(USART_MODULE_4), PA0, USART4_BASE_ADDRESS, 4}, + #endif + #ifdef USART4_TX_PC10_AF1 + {hal_ll_usart_module_num(USART_MODULE_4), PC10, USART4_BASE_ADDRESS, 1}, + #endif + #ifdef USART4_TX_PE8_AF0 + {hal_ll_usart_module_num(USART_MODULE_4), PE8, USART4_BASE_ADDRESS, 0}, + #endif + #ifdef USART5_TX_PB0_AF8 + {hal_ll_usart_module_num(USART_MODULE_5), PB0, USART5_BASE_ADDRESS, 8}, + #endif + #ifdef USART5_TX_PB3_AF3 + {hal_ll_usart_module_num(USART_MODULE_5), PB3, USART5_BASE_ADDRESS, 3}, + #endif + #ifdef USART5_TX_PC12_AF3 + {hal_ll_usart_module_num(USART_MODULE_5), PC12, USART5_BASE_ADDRESS, 3}, + #endif + #ifdef USART5_TX_PD3_AF3 + {hal_ll_usart_module_num(USART_MODULE_5), PD3, USART5_BASE_ADDRESS, 3}, + #endif + #ifdef USART5_TX_PE10_AF3 + {hal_ll_usart_module_num(USART_MODULE_5), PE10, USART5_BASE_ADDRESS, 3}, + #endif + #ifdef USART6_TX_PA4_AF3 + {hal_ll_usart_module_num(USART_MODULE_6), PA4, USART6_BASE_ADDRESS, 3}, + #endif + #ifdef USART6_TX_PB8_AF8 + {hal_ll_usart_module_num(USART_MODULE_6), PB8, USART6_BASE_ADDRESS, 8}, + #endif + #ifdef USART6_TX_PC0_AF4 + {hal_ll_usart_module_num(USART_MODULE_6), PC0, USART6_BASE_ADDRESS, 4}, + #endif + #ifdef USART6_TX_PF9_AF3 + {hal_ll_usart_module_num(USART_MODULE_6), PF9, USART6_BASE_ADDRESS, 3}, + #endif + {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} + //------------ END TX +}; + +/*!< @brief UART RX pins */ +static const hal_ll_uart_pin_map_t hal_ll_uart_rx_map[] = +{ + #ifdef USART1_RX_PA10_AF1 + {hal_ll_usart_module_num(USART_MODULE_1), PA10, USART1_BASE_ADDRESS, 1}, + #endif + #ifdef USART1_RX_PB7_AF0 + {hal_ll_usart_module_num(USART_MODULE_1), PB7, USART1_BASE_ADDRESS, 0}, + #endif + #ifdef USART1_RX_PC5_AF1 + {hal_ll_usart_module_num(USART_MODULE_1), PC5, USART1_BASE_ADDRESS, 1}, + #endif + #ifdef USART2_RX_PA15_AF1 + {hal_ll_usart_module_num(USART_MODULE_2), PA15, USART2_BASE_ADDRESS, 1}, + #endif + #ifdef USART2_RX_PA3_AF1 + {hal_ll_usart_module_num(USART_MODULE_2), PA3, USART2_BASE_ADDRESS, 1}, + #endif + #ifdef USART2_RX_PD6_AF0 + {hal_ll_usart_module_num(USART_MODULE_2), PD6, USART2_BASE_ADDRESS, 0}, + #endif + #ifdef USART3_RX_PB0_AF4 + {hal_ll_usart_module_num(USART_MODULE_3), PB0, USART3_BASE_ADDRESS, 4}, + #endif + #ifdef USART3_RX_PB11_AF4 + {hal_ll_usart_module_num(USART_MODULE_3), PB11, USART3_BASE_ADDRESS, 4}, + #endif + #ifdef USART3_RX_PB9_AF4 + {hal_ll_usart_module_num(USART_MODULE_3), PB9, USART3_BASE_ADDRESS, 4}, + #endif + #ifdef USART3_RX_PC11_AF0 + {hal_ll_usart_module_num(USART_MODULE_3), PC11, USART3_BASE_ADDRESS, 0}, + #endif + #ifdef USART3_RX_PC5_AF0 + {hal_ll_usart_module_num(USART_MODULE_3), PC5, USART3_BASE_ADDRESS, 0}, + #endif + #ifdef USART3_RX_PD9_AF0 + {hal_ll_usart_module_num(USART_MODULE_3), PD9, USART3_BASE_ADDRESS, 0}, + #endif + #ifdef USART4_RX_PA1_AF4 + {hal_ll_usart_module_num(USART_MODULE_4), PA1, USART4_BASE_ADDRESS, 4}, + #endif + #ifdef USART4_RX_PC11_AF1 + {hal_ll_usart_module_num(USART_MODULE_4), PC11, USART4_BASE_ADDRESS, 1}, + #endif + #ifdef USART4_RX_PE9_AF0 + {hal_ll_usart_module_num(USART_MODULE_4), PE9, USART4_BASE_ADDRESS, 0}, + #endif + #ifdef USART5_RX_PB1_AF8 + {hal_ll_usart_module_num(USART_MODULE_5), PB1, USART5_BASE_ADDRESS, 8}, + #endif + #ifdef USART5_RX_PB4_AF3 + {hal_ll_usart_module_num(USART_MODULE_5), PB4, USART5_BASE_ADDRESS, 3}, + #endif + #ifdef USART5_RX_PD2_AF3 + {hal_ll_usart_module_num(USART_MODULE_5), PD2, USART5_BASE_ADDRESS, 3}, + #endif + #ifdef USART6_RX_PA5_AF3 + {hal_ll_usart_module_num(USART_MODULE_6), PA5, USART6_BASE_ADDRESS, 3}, + #endif + #ifdef USART6_RX_PB9_AF8 + {hal_ll_usart_module_num(USART_MODULE_6), PB9, USART6_BASE_ADDRESS, 8}, + #endif + #ifdef USART6_RX_PC1_AF4 + {hal_ll_usart_module_num(USART_MODULE_6), PC1, USART6_BASE_ADDRESS, 4}, + #endif + #ifdef USART5_RX_PE11_AF3 + {hal_ll_usart_module_num(USART_MODULE_5), PE11, USART5_BASE_ADDRESS, 3}, + #endif + #ifdef USART6_RX_PF10_AF3 + {hal_ll_usart_module_num(USART_MODULE_6), PF10, USART6_BASE_ADDRESS, 3}, + #endif + {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} + //------------ END RX +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_UART_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/uart/hal_ll_uart_pin_map/implementations/doc_ds_81/hal_ll_uart_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/uart/hal_ll_uart_pin_map/implementations/doc_ds_81/hal_ll_uart_pin_map.h new file mode 100644 index 000000000..a0b3464e3 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/uart/hal_ll_uart_pin_map/implementations/doc_ds_81/hal_ll_uart_pin_map.h @@ -0,0 +1,297 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_uart_pin_map.h + * @brief UART HAL LOW LEVEL PIN MAPS. + */ + +#ifndef _HAL_LL_UART_PIN_MAP_H_ +#define _HAL_LL_UART_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_uart_module_num(_module_num) (_module_num - 1) +#define hal_ll_usart_module_num(_module_num) hal_ll_uart_module_num(_module_num) +#define hal_ll_lpuart_module_num(_module_num) hal_ll_uart_module_num(_module_num) + +/*!< @brief Pin structure */ +typedef struct +{ + uint8_t module_index; + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + uint32_t af; +} hal_ll_uart_pin_map_t; + +#ifdef UART_MODULE_1 +#define USART_MODULE_1 UART_MODULE_1 +#define UART1_BASE_ADDRESS (0x40013800UL) +#define UART1_BASE_ADDR UART1_BASE_ADDRESS +#define USART1_BASE_ADDR UART1_BASE_ADDRESS +#define USART1_BASE_ADDRESS UART1_BASE_ADDRESS +#define HAL_LL_UART1_BASE_ADDR UART1_BASE_ADDRESS +#define HAL_LL_USART1_BASE_ADDR UART1_BASE_ADDRESS +#define HAL_LL_UART1_BASE_ADDRESS UART1_BASE_ADDRESS +#define HAL_LL_USART1_BASE_ADDRESS UART1_BASE_ADDRESS +#endif +#ifdef UART_MODULE_2 +#define USART_MODULE_2 UART_MODULE_2 +#define UART2_BASE_ADDRESS (0x40004400UL) +#define UART2_BASE_ADDR UART2_BASE_ADDRESS +#define USART2_BASE_ADDR UART2_BASE_ADDRESS +#define USART2_BASE_ADDRESS UART2_BASE_ADDRESS +#define HAL_LL_UART2_BASE_ADDR UART2_BASE_ADDRESS +#define HAL_LL_USART2_BASE_ADDR UART2_BASE_ADDRESS +#define HAL_LL_UART2_BASE_ADDRESS UART2_BASE_ADDRESS +#define HAL_LL_USART2_BASE_ADDRESS UART2_BASE_ADDRESS +#endif +#ifdef UART_MODULE_3 +#define USART_MODULE_3 UART_MODULE_3 +#define UART3_BASE_ADDRESS (0x40004800UL) +#define UART3_BASE_ADDR UART3_BASE_ADDRESS +#define USART3_BASE_ADDR UART3_BASE_ADDRESS +#define USART3_BASE_ADDRESS UART3_BASE_ADDRESS +#define HAL_LL_UART3_BASE_ADDR UART3_BASE_ADDRESS +#define HAL_LL_USART3_BASE_ADDR UART3_BASE_ADDRESS +#define HAL_LL_UART3_BASE_ADDRESS UART3_BASE_ADDRESS +#define HAL_LL_USART3_BASE_ADDRESS UART3_BASE_ADDRESS +#endif +#ifdef UART_MODULE_4 +#define USART_MODULE_4 UART_MODULE_4 +#define UART4_BASE_ADDRESS (0x40004C00UL) +#define UART4_BASE_ADDR UART4_BASE_ADDRESS +#define USART4_BASE_ADDR UART4_BASE_ADDRESS +#define USART4_BASE_ADDRESS UART4_BASE_ADDRESS +#define HAL_LL_UART4_BASE_ADDR UART4_BASE_ADDRESS +#define HAL_LL_USART4_BASE_ADDR UART4_BASE_ADDRESS +#define HAL_LL_UART4_BASE_ADDRESS UART4_BASE_ADDRESS +#define HAL_LL_USART4_BASE_ADDRESS UART4_BASE_ADDRESS +#endif +#ifdef UART_MODULE_5 +#define USART_MODULE_5 UART_MODULE_5 +#define UART5_BASE_ADDRESS (0x40005000UL) +#define UART5_BASE_ADDR UART5_BASE_ADDRESS +#define USART5_BASE_ADDR UART5_BASE_ADDRESS +#define USART5_BASE_ADDRESS UART5_BASE_ADDRESS +#define HAL_LL_UART5_BASE_ADDR UART5_BASE_ADDRESS +#define HAL_LL_USART5_BASE_ADDR UART5_BASE_ADDRESS +#define HAL_LL_UART5_BASE_ADDRESS UART5_BASE_ADDRESS +#define HAL_LL_USART5_BASE_ADDRESS UART5_BASE_ADDRESS +#endif +#ifdef UART_MODULE_6 +#define USART_MODULE_6 UART_MODULE_6 +#define UART6_BASE_ADDRESS (0x40013C00UL) +#define UART6_BASE_ADDR UART6_BASE_ADDRESS +#define USART6_BASE_ADDR UART6_BASE_ADDRESS +#define USART6_BASE_ADDRESS UART6_BASE_ADDRESS +#define HAL_LL_UART6_BASE_ADDR UART6_BASE_ADDRESS +#define HAL_LL_USART6_BASE_ADDR UART6_BASE_ADDRESS +#define HAL_LL_UART6_BASE_ADDRESS UART6_BASE_ADDRESS +#define HAL_LL_USART6_BASE_ADDRESS UART6_BASE_ADDRESS +#endif + +/*!< @brief UART TX pins */ +static const hal_ll_uart_pin_map_t hal_ll_uart_tx_map[] = +{ + #ifdef USART1_TX_PA9_AF1 + {hal_ll_usart_module_num(USART_MODULE_1), PA9, USART1_BASE_ADDRESS, 1}, + #endif + #ifdef USART1_TX_PB6_AF0 + {hal_ll_usart_module_num(USART_MODULE_1), PB6, USART1_BASE_ADDRESS, 0}, + #endif + #ifdef USART2_TX_PA14_AF1 + {hal_ll_usart_module_num(USART_MODULE_2), PA14, USART2_BASE_ADDRESS, 1}, + #endif + #ifdef USART2_TX_PA2_AF1 + {hal_ll_usart_module_num(USART_MODULE_2), PA2, USART2_BASE_ADDRESS, 1}, + #endif + #ifdef USART3_TX_PA5_AF4 + {hal_ll_usart_module_num(USART_MODULE_3), PA5, USART3_BASE_ADDRESS, 4}, + #endif + #ifdef USART3_TX_PB10_AF4 + {hal_ll_usart_module_num(USART_MODULE_3), PB10, USART3_BASE_ADDRESS, 4}, + #endif + #ifdef USART3_TX_PB2_AF4 + {hal_ll_usart_module_num(USART_MODULE_3), PB2, USART3_BASE_ADDRESS, 4}, + #endif + #ifdef USART3_TX_PB8_AF4 + {hal_ll_usart_module_num(USART_MODULE_3), PB8, USART3_BASE_ADDRESS, 4}, + #endif + #ifdef USART4_TX_PA0_AF4 + {hal_ll_usart_module_num(USART_MODULE_4), PA0, USART4_BASE_ADDRESS, 4}, + #endif + #ifdef USART5_TX_PB0_AF8 + {hal_ll_usart_module_num(USART_MODULE_5), PB0, USART5_BASE_ADDRESS, 8}, + #endif + #ifdef USART5_TX_PB3_AF3 + {hal_ll_usart_module_num(USART_MODULE_5), PB3, USART5_BASE_ADDRESS, 3}, + #endif + #ifdef USART5_TX_PD3_AF3 + {hal_ll_usart_module_num(USART_MODULE_5), PD3, USART5_BASE_ADDRESS, 3}, + #endif + #ifdef USART6_TX_PA4_AF3 + {hal_ll_usart_module_num(USART_MODULE_6), PA4, USART6_BASE_ADDRESS, 3}, + #endif + #ifdef USART6_TX_PB8_AF8 + {hal_ll_usart_module_num(USART_MODULE_6), PB8, USART6_BASE_ADDRESS, 8}, + #endif + #ifdef USART1_TX_PC4_AF1 + {hal_ll_usart_module_num(USART_MODULE_1), PC4, USART1_BASE_ADDRESS, 1}, + #endif + #ifdef USART2_TX_PD5_AF0 + {hal_ll_usart_module_num(USART_MODULE_2), PD5, USART2_BASE_ADDRESS, 0}, + #endif + #ifdef USART3_TX_PC10_AF0 + {hal_ll_usart_module_num(USART_MODULE_3), PC10, USART3_BASE_ADDRESS, 0}, + #endif + #ifdef USART3_TX_PC4_AF0 + {hal_ll_usart_module_num(USART_MODULE_3), PC4, USART3_BASE_ADDRESS, 0}, + #endif + #ifdef USART3_TX_PD8_AF0 + {hal_ll_usart_module_num(USART_MODULE_3), PD8, USART3_BASE_ADDRESS, 0}, + #endif + #ifdef USART4_TX_PC10_AF1 + {hal_ll_usart_module_num(USART_MODULE_4), PC10, USART4_BASE_ADDRESS, 1}, + #endif + #ifdef USART5_TX_PC12_AF3 + {hal_ll_usart_module_num(USART_MODULE_5), PC12, USART5_BASE_ADDRESS, 3}, + #endif + #ifdef USART6_TX_PC0_AF4 + {hal_ll_usart_module_num(USART_MODULE_6), PC0, USART6_BASE_ADDRESS, 4}, + #endif + #ifdef USART4_TX_PE8_AF0 + {hal_ll_usart_module_num(USART_MODULE_4), PE8, USART4_BASE_ADDRESS, 0}, + #endif + #ifdef USART5_TX_PE10_AF3 + {hal_ll_usart_module_num(USART_MODULE_5), PE10, USART5_BASE_ADDRESS, 3}, + #endif + #ifdef USART6_TX_PF9_AF3 + {hal_ll_usart_module_num(USART_MODULE_6), PF9, USART6_BASE_ADDRESS, 3}, + #endif + {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} + //------------ END TX +}; + +/*!< @brief UART RX pins */ +static const hal_ll_uart_pin_map_t hal_ll_uart_rx_map[] = +{ + #ifdef USART1_RX_PA10_AF1 + {hal_ll_usart_module_num(USART_MODULE_1), PA10, USART1_BASE_ADDRESS, 1}, + #endif + #ifdef USART1_RX_PB7_AF0 + {hal_ll_usart_module_num(USART_MODULE_1), PB7, USART1_BASE_ADDRESS, 0}, + #endif + #ifdef USART2_RX_PA15_AF1 + {hal_ll_usart_module_num(USART_MODULE_2), PA15, USART2_BASE_ADDRESS, 1}, + #endif + #ifdef USART2_RX_PA3_AF1 + {hal_ll_usart_module_num(USART_MODULE_2), PA3, USART2_BASE_ADDRESS, 1}, + #endif + #ifdef USART3_RX_PB0_AF4 + {hal_ll_usart_module_num(USART_MODULE_3), PB0, USART3_BASE_ADDRESS, 4}, + #endif + #ifdef USART3_RX_PB11_AF4 + {hal_ll_usart_module_num(USART_MODULE_3), PB11, USART3_BASE_ADDRESS, 4}, + #endif + #ifdef USART3_RX_PB9_AF4 + {hal_ll_usart_module_num(USART_MODULE_3), PB9, USART3_BASE_ADDRESS, 4}, + #endif + #ifdef USART4_RX_PA1_AF4 + {hal_ll_usart_module_num(USART_MODULE_4), PA1, USART4_BASE_ADDRESS, 4}, + #endif + #ifdef USART5_RX_PB1_AF8 + {hal_ll_usart_module_num(USART_MODULE_5), PB1, USART5_BASE_ADDRESS, 8}, + #endif + #ifdef USART5_RX_PB4_AF3 + {hal_ll_usart_module_num(USART_MODULE_5), PB4, USART5_BASE_ADDRESS, 3}, + #endif + #ifdef USART5_RX_PD2_AF3 + {hal_ll_usart_module_num(USART_MODULE_5), PD2, USART5_BASE_ADDRESS, 3}, + #endif + #ifdef USART6_RX_PA5_AF3 + {hal_ll_usart_module_num(USART_MODULE_6), PA5, USART6_BASE_ADDRESS, 3}, + #endif + #ifdef USART6_RX_PB9_AF8 + {hal_ll_usart_module_num(USART_MODULE_6), PB9, USART6_BASE_ADDRESS, 8}, + #endif + #ifdef USART1_RX_PC5_AF1 + {hal_ll_usart_module_num(USART_MODULE_1), PC5, USART1_BASE_ADDRESS, 1}, + #endif + #ifdef USART2_RX_PD6_AF0 + {hal_ll_usart_module_num(USART_MODULE_2), PD6, USART2_BASE_ADDRESS, 0}, + #endif + #ifdef USART3_RX_PC11_AF0 + {hal_ll_usart_module_num(USART_MODULE_3), PC11, USART3_BASE_ADDRESS, 0}, + #endif + #ifdef USART3_RX_PC5_AF0 + {hal_ll_usart_module_num(USART_MODULE_3), PC5, USART3_BASE_ADDRESS, 0}, + #endif + #ifdef USART3_RX_PD9_AF0 + {hal_ll_usart_module_num(USART_MODULE_3), PD9, USART3_BASE_ADDRESS, 0}, + #endif + #ifdef USART4_RX_PC11_AF1 + {hal_ll_usart_module_num(USART_MODULE_4), PC11, USART4_BASE_ADDRESS, 1}, + #endif + #ifdef USART6_RX_PC1_AF4 + {hal_ll_usart_module_num(USART_MODULE_6), PC1, USART6_BASE_ADDRESS, 4}, + #endif + #ifdef USART4_RX_PE9_AF0 + {hal_ll_usart_module_num(USART_MODULE_4), PE9, USART4_BASE_ADDRESS, 0}, + #endif + #ifdef USART5_RX_PE11_AF3 + {hal_ll_usart_module_num(USART_MODULE_5), PE11, USART5_BASE_ADDRESS, 3}, + #endif + #ifdef USART6_RX_PF10_AF3 + {hal_ll_usart_module_num(USART_MODULE_6), PF10, USART6_BASE_ADDRESS, 3}, + #endif + {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} + //------------ END RX +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_UART_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/uart/hal_ll_uart_pin_map/implementations/doc_ds_82/hal_ll_uart_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/uart/hal_ll_uart_pin_map/implementations/doc_ds_82/hal_ll_uart_pin_map.h new file mode 100644 index 000000000..3b57c66ea --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/uart/hal_ll_uart_pin_map/implementations/doc_ds_82/hal_ll_uart_pin_map.h @@ -0,0 +1,212 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_uart_pin_map.h + * @brief UART HAL LOW LEVEL PIN MAPS. + */ + +#ifndef _HAL_LL_UART_PIN_MAP_H_ +#define _HAL_LL_UART_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_uart_module_num(_module_num) (_module_num - 1) +#define hal_ll_usart_module_num(_module_num) hal_ll_uart_module_num(_module_num) +#define hal_ll_lpuart_module_num(_module_num) hal_ll_uart_module_num(_module_num) + +/*!< @brief Pin structure */ +typedef struct +{ + uint8_t module_index; + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + uint32_t af; +} hal_ll_uart_pin_map_t; + +#ifdef UART_MODULE_1 +#define USART_MODULE_1 UART_MODULE_1 +#define UART1_BASE_ADDRESS (0x40013800UL) +#define UART1_BASE_ADDR UART1_BASE_ADDRESS +#define USART1_BASE_ADDR UART1_BASE_ADDRESS +#define USART1_BASE_ADDRESS UART1_BASE_ADDRESS +#define HAL_LL_UART1_BASE_ADDR UART1_BASE_ADDRESS +#define HAL_LL_USART1_BASE_ADDR UART1_BASE_ADDRESS +#define HAL_LL_UART1_BASE_ADDRESS UART1_BASE_ADDRESS +#define HAL_LL_USART1_BASE_ADDRESS UART1_BASE_ADDRESS +#endif +#ifdef UART_MODULE_2 +#define USART_MODULE_2 UART_MODULE_2 +#define UART2_BASE_ADDRESS (0x40004400UL) +#define UART2_BASE_ADDR UART2_BASE_ADDRESS +#define USART2_BASE_ADDR UART2_BASE_ADDRESS +#define USART2_BASE_ADDRESS UART2_BASE_ADDRESS +#define HAL_LL_UART2_BASE_ADDR UART2_BASE_ADDRESS +#define HAL_LL_USART2_BASE_ADDR UART2_BASE_ADDRESS +#define HAL_LL_UART2_BASE_ADDRESS UART2_BASE_ADDRESS +#define HAL_LL_USART2_BASE_ADDRESS UART2_BASE_ADDRESS +#endif +#ifdef UART_MODULE_3 +#define USART_MODULE_3 UART_MODULE_3 +#define UART3_BASE_ADDRESS (0x40004800UL) +#define UART3_BASE_ADDR UART3_BASE_ADDRESS +#define USART3_BASE_ADDR UART3_BASE_ADDRESS +#define USART3_BASE_ADDRESS UART3_BASE_ADDRESS +#define HAL_LL_UART3_BASE_ADDR UART3_BASE_ADDRESS +#define HAL_LL_USART3_BASE_ADDR UART3_BASE_ADDRESS +#define HAL_LL_UART3_BASE_ADDRESS UART3_BASE_ADDRESS +#define HAL_LL_USART3_BASE_ADDRESS UART3_BASE_ADDRESS +#endif +#ifdef UART_MODULE_4 +#define USART_MODULE_4 UART_MODULE_4 +#define UART4_BASE_ADDRESS (0x40004C00UL) +#define UART4_BASE_ADDR UART4_BASE_ADDRESS +#define USART4_BASE_ADDR UART4_BASE_ADDRESS +#define USART4_BASE_ADDRESS UART4_BASE_ADDRESS +#define HAL_LL_UART4_BASE_ADDR UART4_BASE_ADDRESS +#define HAL_LL_USART4_BASE_ADDR UART4_BASE_ADDRESS +#define HAL_LL_UART4_BASE_ADDRESS UART4_BASE_ADDRESS +#define HAL_LL_USART4_BASE_ADDRESS UART4_BASE_ADDRESS +#endif + +/*!< @brief UART TX pins */ +static const hal_ll_uart_pin_map_t hal_ll_uart_tx_map[] = +{ + #ifdef USART1_TX_PA9_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PA9, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART1_TX_PB6_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PB6, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART2_TX_PA14_AF7 + {hal_ll_usart_module_num(USART_MODULE_2), PA14, USART2_BASE_ADDRESS, 7}, + #endif + #ifdef USART2_TX_PA2_AF7 + {hal_ll_usart_module_num(USART_MODULE_2), PA2, USART2_BASE_ADDRESS, 7}, + #endif + #ifdef USART2_TX_PB3_AF7 + {hal_ll_usart_module_num(USART_MODULE_2), PB3, USART2_BASE_ADDRESS, 7}, + #endif + #ifdef UART4_TX_PC10_AF5 + {hal_ll_uart_module_num(UART_MODULE_4), PC10, UART4_BASE_ADDRESS, 5}, + #endif + #ifdef USART1_TX_PC4_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PC4, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_TX_PB10_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PB10, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_TX_PB9_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PB9, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_TX_PC10_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PC10, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_TX_PD8_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PD8, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART1_TX_PE0_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PE0, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART2_TX_PD5_AF7 + {hal_ll_usart_module_num(USART_MODULE_2), PD5, USART2_BASE_ADDRESS, 7}, + #endif + {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} + //------------ END TX +}; + +/*!< @brief UART RX pins */ +static const hal_ll_uart_pin_map_t hal_ll_uart_rx_map[] = +{ + #ifdef USART1_RX_PA10_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PA10, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART1_RX_PB7_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PB7, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART2_RX_PA15_AF7 + {hal_ll_usart_module_num(USART_MODULE_2), PA15, USART2_BASE_ADDRESS, 7}, + #endif + #ifdef USART2_RX_PA3_AF7 + {hal_ll_usart_module_num(USART_MODULE_2), PA3, USART2_BASE_ADDRESS, 7}, + #endif + #ifdef USART2_RX_PB4_AF7 + {hal_ll_usart_module_num(USART_MODULE_2), PB4, USART2_BASE_ADDRESS, 7}, + #endif + #ifdef UART4_RX_PC11_AF5 + {hal_ll_uart_module_num(UART_MODULE_4), PC11, UART4_BASE_ADDRESS, 5}, + #endif + #ifdef USART1_RX_PC5_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PC5, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_RX_PB11_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PB11, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_RX_PB8_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PB8, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_RX_PC11_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PC11, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_RX_PD9_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PD9, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_RX_PE15_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PE15, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART1_RX_PE1_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PE1, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART2_RX_PD6_AF7 + {hal_ll_usart_module_num(USART_MODULE_2), PD6, USART2_BASE_ADDRESS, 7}, + #endif + {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} + //------------ END RX +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_UART_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/uart/hal_ll_uart_pin_map/implementations/doc_ds_83/hal_ll_uart_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/uart/hal_ll_uart_pin_map/implementations/doc_ds_83/hal_ll_uart_pin_map.h new file mode 100644 index 000000000..6493ff6f2 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/uart/hal_ll_uart_pin_map/implementations/doc_ds_83/hal_ll_uart_pin_map.h @@ -0,0 +1,212 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_uart_pin_map.h + * @brief UART HAL LOW LEVEL PIN MAPS. + */ + +#ifndef _HAL_LL_UART_PIN_MAP_H_ +#define _HAL_LL_UART_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_uart_module_num(_module_num) (_module_num - 1) +#define hal_ll_usart_module_num(_module_num) hal_ll_uart_module_num(_module_num) +#define hal_ll_lpuart_module_num(_module_num) hal_ll_uart_module_num(_module_num) + +/*!< @brief Pin structure */ +typedef struct +{ + uint8_t module_index; + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + uint32_t af; +} hal_ll_uart_pin_map_t; + +#ifdef UART_MODULE_1 +#define USART_MODULE_1 UART_MODULE_1 +#define UART1_BASE_ADDRESS (0x40013800UL) +#define UART1_BASE_ADDR UART1_BASE_ADDRESS +#define USART1_BASE_ADDR UART1_BASE_ADDRESS +#define USART1_BASE_ADDRESS UART1_BASE_ADDRESS +#define HAL_LL_UART1_BASE_ADDR UART1_BASE_ADDRESS +#define HAL_LL_USART1_BASE_ADDR UART1_BASE_ADDRESS +#define HAL_LL_UART1_BASE_ADDRESS UART1_BASE_ADDRESS +#define HAL_LL_USART1_BASE_ADDRESS UART1_BASE_ADDRESS +#endif +#ifdef UART_MODULE_2 +#define USART_MODULE_2 UART_MODULE_2 +#define UART2_BASE_ADDRESS (0x40004400UL) +#define UART2_BASE_ADDR UART2_BASE_ADDRESS +#define USART2_BASE_ADDR UART2_BASE_ADDRESS +#define USART2_BASE_ADDRESS UART2_BASE_ADDRESS +#define HAL_LL_UART2_BASE_ADDR UART2_BASE_ADDRESS +#define HAL_LL_USART2_BASE_ADDR UART2_BASE_ADDRESS +#define HAL_LL_UART2_BASE_ADDRESS UART2_BASE_ADDRESS +#define HAL_LL_USART2_BASE_ADDRESS UART2_BASE_ADDRESS +#endif +#ifdef UART_MODULE_3 +#define USART_MODULE_3 UART_MODULE_3 +#define UART3_BASE_ADDRESS (0x40004800UL) +#define UART3_BASE_ADDR UART3_BASE_ADDRESS +#define USART3_BASE_ADDR UART3_BASE_ADDRESS +#define USART3_BASE_ADDRESS UART3_BASE_ADDRESS +#define HAL_LL_UART3_BASE_ADDR UART3_BASE_ADDRESS +#define HAL_LL_USART3_BASE_ADDR UART3_BASE_ADDRESS +#define HAL_LL_UART3_BASE_ADDRESS UART3_BASE_ADDRESS +#define HAL_LL_USART3_BASE_ADDRESS UART3_BASE_ADDRESS +#endif +#ifdef UART_MODULE_4 +#define USART_MODULE_4 UART_MODULE_4 +#define UART4_BASE_ADDRESS (0x40004C00UL) +#define UART4_BASE_ADDR UART4_BASE_ADDRESS +#define USART4_BASE_ADDR UART4_BASE_ADDRESS +#define USART4_BASE_ADDRESS UART4_BASE_ADDRESS +#define HAL_LL_UART4_BASE_ADDR UART4_BASE_ADDRESS +#define HAL_LL_USART4_BASE_ADDR UART4_BASE_ADDRESS +#define HAL_LL_UART4_BASE_ADDRESS UART4_BASE_ADDRESS +#define HAL_LL_USART4_BASE_ADDRESS UART4_BASE_ADDRESS +#endif + +/*!< @brief UART TX pins */ +static const hal_ll_uart_pin_map_t hal_ll_uart_tx_map[] = +{ + #ifdef UART4_TX_PC10_AF5 + {hal_ll_uart_module_num(UART_MODULE_4), PC10, UART4_BASE_ADDRESS, 5}, + #endif + #ifdef USART1_TX_PA9_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PA9, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART1_TX_PB6_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PB6, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART1_TX_PC4_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PC4, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART2_TX_PA14_AF7 + {hal_ll_usart_module_num(USART_MODULE_2), PA14, USART2_BASE_ADDRESS, 7}, + #endif + #ifdef USART2_TX_PA2_AF7 + {hal_ll_usart_module_num(USART_MODULE_2), PA2, USART2_BASE_ADDRESS, 7}, + #endif + #ifdef USART2_TX_PB3_AF7 + {hal_ll_usart_module_num(USART_MODULE_2), PB3, USART2_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_TX_PB10_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PB10, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_TX_PB9_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PB9, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_TX_PC10_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PC10, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_TX_PD8_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PD8, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART1_TX_PE0_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PE0, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART2_TX_PD5_AF7 + {hal_ll_usart_module_num(USART_MODULE_2), PD5, USART2_BASE_ADDRESS, 7}, + #endif + {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} + //------------ END TX +}; + +/*!< @brief UART RX pins */ +static const hal_ll_uart_pin_map_t hal_ll_uart_rx_map[] = +{ + #ifdef UART4_RX_PC11_AF5 + {hal_ll_uart_module_num(UART_MODULE_4), PC11, UART4_BASE_ADDRESS, 5}, + #endif + #ifdef USART1_RX_PA10_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PA10, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART1_RX_PB7_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PB7, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART1_RX_PC5_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PC5, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART2_RX_PA15_AF7 + {hal_ll_usart_module_num(USART_MODULE_2), PA15, USART2_BASE_ADDRESS, 7}, + #endif + #ifdef USART2_RX_PA3_AF7 + {hal_ll_usart_module_num(USART_MODULE_2), PA3, USART2_BASE_ADDRESS, 7}, + #endif + #ifdef USART2_RX_PB4_AF7 + {hal_ll_usart_module_num(USART_MODULE_2), PB4, USART2_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_RX_PB11_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PB11, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_RX_PB8_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PB8, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_RX_PC11_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PC11, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_RX_PD9_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PD9, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_RX_PE15_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PE15, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART1_RX_PE1_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PE1, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART2_RX_PD6_AF7 + {hal_ll_usart_module_num(USART_MODULE_2), PD6, USART2_BASE_ADDRESS, 7}, + #endif + {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} + //------------ END RX +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_UART_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/uart/hal_ll_uart_pin_map/implementations/doc_ds_84/hal_ll_uart_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/uart/hal_ll_uart_pin_map/implementations/doc_ds_84/hal_ll_uart_pin_map.h new file mode 100644 index 000000000..f9894e3bc --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/uart/hal_ll_uart_pin_map/implementations/doc_ds_84/hal_ll_uart_pin_map.h @@ -0,0 +1,232 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_uart_pin_map.h + * @brief UART HAL LOW LEVEL PIN MAPS. + */ + +#ifndef _HAL_LL_UART_PIN_MAP_H_ +#define _HAL_LL_UART_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_uart_module_num(_module_num) (_module_num - 1) +#define hal_ll_usart_module_num(_module_num) hal_ll_uart_module_num(_module_num) +#define hal_ll_lpuart_module_num(_module_num) hal_ll_uart_module_num(_module_num) + +/*!< @brief Pin structure */ +typedef struct +{ + uint8_t module_index; + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + uint32_t af; +} hal_ll_uart_pin_map_t; + +#ifdef UART_MODULE_1 +#define USART_MODULE_1 UART_MODULE_1 +#define UART1_BASE_ADDRESS (0x40013800UL) +#define UART1_BASE_ADDR UART1_BASE_ADDRESS +#define USART1_BASE_ADDR UART1_BASE_ADDRESS +#define USART1_BASE_ADDRESS UART1_BASE_ADDRESS +#define HAL_LL_UART1_BASE_ADDR UART1_BASE_ADDRESS +#define HAL_LL_USART1_BASE_ADDR UART1_BASE_ADDRESS +#define HAL_LL_UART1_BASE_ADDRESS UART1_BASE_ADDRESS +#define HAL_LL_USART1_BASE_ADDRESS UART1_BASE_ADDRESS +#endif +#ifdef UART_MODULE_2 +#define USART_MODULE_2 UART_MODULE_2 +#define UART2_BASE_ADDRESS (0x40004400UL) +#define UART2_BASE_ADDR UART2_BASE_ADDRESS +#define USART2_BASE_ADDR UART2_BASE_ADDRESS +#define USART2_BASE_ADDRESS UART2_BASE_ADDRESS +#define HAL_LL_UART2_BASE_ADDR UART2_BASE_ADDRESS +#define HAL_LL_USART2_BASE_ADDR UART2_BASE_ADDRESS +#define HAL_LL_UART2_BASE_ADDRESS UART2_BASE_ADDRESS +#define HAL_LL_USART2_BASE_ADDRESS UART2_BASE_ADDRESS +#endif +#ifdef UART_MODULE_3 +#define USART_MODULE_3 UART_MODULE_3 +#define UART3_BASE_ADDRESS (0x40004800UL) +#define UART3_BASE_ADDR UART3_BASE_ADDRESS +#define USART3_BASE_ADDR UART3_BASE_ADDRESS +#define USART3_BASE_ADDRESS UART3_BASE_ADDRESS +#define HAL_LL_UART3_BASE_ADDR UART3_BASE_ADDRESS +#define HAL_LL_USART3_BASE_ADDR UART3_BASE_ADDRESS +#define HAL_LL_UART3_BASE_ADDRESS UART3_BASE_ADDRESS +#define HAL_LL_USART3_BASE_ADDRESS UART3_BASE_ADDRESS +#endif +#ifdef UART_MODULE_4 +#define USART_MODULE_4 UART_MODULE_4 +#define UART4_BASE_ADDRESS (0x40004C00UL) +#define UART4_BASE_ADDR UART4_BASE_ADDRESS +#define USART4_BASE_ADDR UART4_BASE_ADDRESS +#define USART4_BASE_ADDRESS UART4_BASE_ADDRESS +#define HAL_LL_UART4_BASE_ADDR UART4_BASE_ADDRESS +#define HAL_LL_USART4_BASE_ADDR UART4_BASE_ADDRESS +#define HAL_LL_UART4_BASE_ADDRESS UART4_BASE_ADDRESS +#define HAL_LL_USART4_BASE_ADDRESS UART4_BASE_ADDRESS +#endif +#ifdef UART_MODULE_5 +#define USART_MODULE_5 UART_MODULE_5 +#define UART5_BASE_ADDRESS (0x40005000UL) +#define UART5_BASE_ADDR UART5_BASE_ADDRESS +#define USART5_BASE_ADDR UART5_BASE_ADDRESS +#define USART5_BASE_ADDRESS UART5_BASE_ADDRESS +#define HAL_LL_UART5_BASE_ADDR UART5_BASE_ADDRESS +#define HAL_LL_USART5_BASE_ADDR UART5_BASE_ADDRESS +#define HAL_LL_UART5_BASE_ADDRESS UART5_BASE_ADDRESS +#define HAL_LL_USART5_BASE_ADDRESS UART5_BASE_ADDRESS +#endif + +/*!< @brief UART TX pins */ +static const hal_ll_uart_pin_map_t hal_ll_uart_tx_map[] = +{ + #ifdef UART4_TX_PC10_AF5 + {hal_ll_uart_module_num(UART_MODULE_4), PC10, UART4_BASE_ADDRESS, 5}, + #endif + #ifdef UART5_TX_PC12_AF5 + {hal_ll_uart_module_num(UART_MODULE_5), PC12, UART5_BASE_ADDRESS, 5}, + #endif + #ifdef USART1_TX_PA9_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PA9, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART1_TX_PB6_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PB6, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART1_TX_PC4_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PC4, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART1_TX_PE0_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PE0, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART2_TX_PA14_AF7 + {hal_ll_usart_module_num(USART_MODULE_2), PA14, USART2_BASE_ADDRESS, 7}, + #endif + #ifdef USART2_TX_PA2_AF7 + {hal_ll_usart_module_num(USART_MODULE_2), PA2, USART2_BASE_ADDRESS, 7}, + #endif + #ifdef USART2_TX_PB3_AF7 + {hal_ll_usart_module_num(USART_MODULE_2), PB3, USART2_BASE_ADDRESS, 7}, + #endif + #ifdef USART2_TX_PD5_AF7 + {hal_ll_usart_module_num(USART_MODULE_2), PD5, USART2_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_TX_PB10_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PB10, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_TX_PB9_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PB9, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_TX_PC10_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PC10, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_TX_PD8_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PD8, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART1_TX_PG9_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PG9, USART1_BASE_ADDRESS, 7}, + #endif + {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} + //------------ END TX +}; + +/*!< @brief UART RX pins */ +static const hal_ll_uart_pin_map_t hal_ll_uart_rx_map[] = +{ + #ifdef UART4_RX_PC11_AF5 + {hal_ll_uart_module_num(UART_MODULE_4), PC11, UART4_BASE_ADDRESS, 5}, + #endif + #ifdef UART5_RX_PD2_AF5 + {hal_ll_uart_module_num(UART_MODULE_5), PD2, UART5_BASE_ADDRESS, 5}, + #endif + #ifdef USART1_RX_PA10_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PA10, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART1_RX_PB7_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PB7, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART1_RX_PC5_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PC5, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART1_RX_PE1_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PE1, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART2_RX_PA15_AF7 + {hal_ll_usart_module_num(USART_MODULE_2), PA15, USART2_BASE_ADDRESS, 7}, + #endif + #ifdef USART2_RX_PA3_AF7 + {hal_ll_usart_module_num(USART_MODULE_2), PA3, USART2_BASE_ADDRESS, 7}, + #endif + #ifdef USART2_RX_PB4_AF7 + {hal_ll_usart_module_num(USART_MODULE_2), PB4, USART2_BASE_ADDRESS, 7}, + #endif + #ifdef USART2_RX_PD6_AF7 + {hal_ll_usart_module_num(USART_MODULE_2), PD6, USART2_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_RX_PB11_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PB11, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_RX_PB8_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PB8, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_RX_PC11_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PC11, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_RX_PD9_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PD9, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_RX_PE15_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PE15, USART3_BASE_ADDRESS, 7}, + #endif + {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} + //------------ END RX +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_UART_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/uart/hal_ll_uart_pin_map/implementations/doc_ds_85/hal_ll_uart_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/uart/hal_ll_uart_pin_map/implementations/doc_ds_85/hal_ll_uart_pin_map.h new file mode 100644 index 000000000..285555360 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/uart/hal_ll_uart_pin_map/implementations/doc_ds_85/hal_ll_uart_pin_map.h @@ -0,0 +1,232 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_uart_pin_map.h + * @brief UART HAL LOW LEVEL PIN MAPS. + */ + +#ifndef _HAL_LL_UART_PIN_MAP_H_ +#define _HAL_LL_UART_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_uart_module_num(_module_num) (_module_num - 1) +#define hal_ll_usart_module_num(_module_num) hal_ll_uart_module_num(_module_num) +#define hal_ll_lpuart_module_num(_module_num) hal_ll_uart_module_num(_module_num) + +/*!< @brief Pin structure */ +typedef struct +{ + uint8_t module_index; + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + uint32_t af; +} hal_ll_uart_pin_map_t; + +#ifdef UART_MODULE_1 +#define USART_MODULE_1 UART_MODULE_1 +#define UART1_BASE_ADDRESS (0x40013800UL) +#define UART1_BASE_ADDR UART1_BASE_ADDRESS +#define USART1_BASE_ADDR UART1_BASE_ADDRESS +#define USART1_BASE_ADDRESS UART1_BASE_ADDRESS +#define HAL_LL_UART1_BASE_ADDR UART1_BASE_ADDRESS +#define HAL_LL_USART1_BASE_ADDR UART1_BASE_ADDRESS +#define HAL_LL_UART1_BASE_ADDRESS UART1_BASE_ADDRESS +#define HAL_LL_USART1_BASE_ADDRESS UART1_BASE_ADDRESS +#endif +#ifdef UART_MODULE_2 +#define USART_MODULE_2 UART_MODULE_2 +#define UART2_BASE_ADDRESS (0x40004400UL) +#define UART2_BASE_ADDR UART2_BASE_ADDRESS +#define USART2_BASE_ADDR UART2_BASE_ADDRESS +#define USART2_BASE_ADDRESS UART2_BASE_ADDRESS +#define HAL_LL_UART2_BASE_ADDR UART2_BASE_ADDRESS +#define HAL_LL_USART2_BASE_ADDR UART2_BASE_ADDRESS +#define HAL_LL_UART2_BASE_ADDRESS UART2_BASE_ADDRESS +#define HAL_LL_USART2_BASE_ADDRESS UART2_BASE_ADDRESS +#endif +#ifdef UART_MODULE_3 +#define USART_MODULE_3 UART_MODULE_3 +#define UART3_BASE_ADDRESS (0x40004800UL) +#define UART3_BASE_ADDR UART3_BASE_ADDRESS +#define USART3_BASE_ADDR UART3_BASE_ADDRESS +#define USART3_BASE_ADDRESS UART3_BASE_ADDRESS +#define HAL_LL_UART3_BASE_ADDR UART3_BASE_ADDRESS +#define HAL_LL_USART3_BASE_ADDR UART3_BASE_ADDRESS +#define HAL_LL_UART3_BASE_ADDRESS UART3_BASE_ADDRESS +#define HAL_LL_USART3_BASE_ADDRESS UART3_BASE_ADDRESS +#endif +#ifdef UART_MODULE_4 +#define USART_MODULE_4 UART_MODULE_4 +#define UART4_BASE_ADDRESS (0x40004C00UL) +#define UART4_BASE_ADDR UART4_BASE_ADDRESS +#define USART4_BASE_ADDR UART4_BASE_ADDRESS +#define USART4_BASE_ADDRESS UART4_BASE_ADDRESS +#define HAL_LL_UART4_BASE_ADDR UART4_BASE_ADDRESS +#define HAL_LL_USART4_BASE_ADDR UART4_BASE_ADDRESS +#define HAL_LL_UART4_BASE_ADDRESS UART4_BASE_ADDRESS +#define HAL_LL_USART4_BASE_ADDRESS UART4_BASE_ADDRESS +#endif +#ifdef UART_MODULE_5 +#define USART_MODULE_5 UART_MODULE_5 +#define UART5_BASE_ADDRESS (0x40005000UL) +#define UART5_BASE_ADDR UART5_BASE_ADDRESS +#define USART5_BASE_ADDR UART5_BASE_ADDRESS +#define USART5_BASE_ADDRESS UART5_BASE_ADDRESS +#define HAL_LL_UART5_BASE_ADDR UART5_BASE_ADDRESS +#define HAL_LL_USART5_BASE_ADDR UART5_BASE_ADDRESS +#define HAL_LL_UART5_BASE_ADDRESS UART5_BASE_ADDRESS +#define HAL_LL_USART5_BASE_ADDRESS UART5_BASE_ADDRESS +#endif + +/*!< @brief UART TX pins */ +static const hal_ll_uart_pin_map_t hal_ll_uart_tx_map[] = +{ + #ifdef UART4_TX_PC10_AF5 + {hal_ll_uart_module_num(UART_MODULE_4), PC10, UART4_BASE_ADDRESS, 5}, + #endif + #ifdef USART1_TX_PA9_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PA9, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART1_TX_PB6_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PB6, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART1_TX_PC4_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PC4, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART2_TX_PA14_AF7 + {hal_ll_usart_module_num(USART_MODULE_2), PA14, USART2_BASE_ADDRESS, 7}, + #endif + #ifdef USART2_TX_PA2_AF7 + {hal_ll_usart_module_num(USART_MODULE_2), PA2, USART2_BASE_ADDRESS, 7}, + #endif + #ifdef USART2_TX_PB3_AF7 + {hal_ll_usart_module_num(USART_MODULE_2), PB3, USART2_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_TX_PB10_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PB10, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_TX_PB9_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PB9, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_TX_PC10_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PC10, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef UART5_TX_PC12_AF5 + {hal_ll_uart_module_num(UART_MODULE_5), PC12, UART5_BASE_ADDRESS, 5}, + #endif + #ifdef USART1_TX_PE0_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PE0, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART2_TX_PD5_AF7 + {hal_ll_usart_module_num(USART_MODULE_2), PD5, USART2_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_TX_PD8_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PD8, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART1_TX_PG9_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PG9, USART1_BASE_ADDRESS, 7}, + #endif + {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} + //------------ END TX +}; + +/*!< @brief UART RX pins */ +static const hal_ll_uart_pin_map_t hal_ll_uart_rx_map[] = +{ + #ifdef UART4_RX_PC11_AF5 + {hal_ll_uart_module_num(UART_MODULE_4), PC11, UART4_BASE_ADDRESS, 5}, + #endif + #ifdef USART1_RX_PA10_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PA10, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART1_RX_PB7_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PB7, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART2_RX_PA15_AF7 + {hal_ll_usart_module_num(USART_MODULE_2), PA15, USART2_BASE_ADDRESS, 7}, + #endif + #ifdef USART2_RX_PA3_AF7 + {hal_ll_usart_module_num(USART_MODULE_2), PA3, USART2_BASE_ADDRESS, 7}, + #endif + #ifdef USART2_RX_PB4_AF7 + {hal_ll_usart_module_num(USART_MODULE_2), PB4, USART2_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_RX_PB11_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PB11, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_RX_PB8_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PB8, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_RX_PC11_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PC11, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef UART5_RX_PD2_AF5 + {hal_ll_uart_module_num(UART_MODULE_5), PD2, UART5_BASE_ADDRESS, 5}, + #endif + #ifdef USART1_RX_PC5_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PC5, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART1_RX_PE1_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PE1, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART2_RX_PD6_AF7 + {hal_ll_usart_module_num(USART_MODULE_2), PD6, USART2_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_RX_PD9_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PD9, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_RX_PE15_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PE15, USART3_BASE_ADDRESS, 7}, + #endif + {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} + //------------ END RX +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_UART_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/uart/hal_ll_uart_pin_map/implementations/doc_ds_86/hal_ll_uart_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/uart/hal_ll_uart_pin_map/implementations/doc_ds_86/hal_ll_uart_pin_map.h new file mode 100644 index 000000000..9f76f6bd3 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/uart/hal_ll_uart_pin_map/implementations/doc_ds_86/hal_ll_uart_pin_map.h @@ -0,0 +1,232 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_uart_pin_map.h + * @brief UART HAL LOW LEVEL PIN MAPS. + */ + +#ifndef _HAL_LL_UART_PIN_MAP_H_ +#define _HAL_LL_UART_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_uart_module_num(_module_num) (_module_num - 1) +#define hal_ll_usart_module_num(_module_num) hal_ll_uart_module_num(_module_num) +#define hal_ll_lpuart_module_num(_module_num) hal_ll_uart_module_num(_module_num) + +/*!< @brief Pin structure */ +typedef struct +{ + uint8_t module_index; + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + uint32_t af; +} hal_ll_uart_pin_map_t; + +#ifdef UART_MODULE_1 +#define USART_MODULE_1 UART_MODULE_1 +#define UART1_BASE_ADDRESS (0x40013800UL) +#define UART1_BASE_ADDR UART1_BASE_ADDRESS +#define USART1_BASE_ADDR UART1_BASE_ADDRESS +#define USART1_BASE_ADDRESS UART1_BASE_ADDRESS +#define HAL_LL_UART1_BASE_ADDR UART1_BASE_ADDRESS +#define HAL_LL_USART1_BASE_ADDR UART1_BASE_ADDRESS +#define HAL_LL_UART1_BASE_ADDRESS UART1_BASE_ADDRESS +#define HAL_LL_USART1_BASE_ADDRESS UART1_BASE_ADDRESS +#endif +#ifdef UART_MODULE_2 +#define USART_MODULE_2 UART_MODULE_2 +#define UART2_BASE_ADDRESS (0x40004400UL) +#define UART2_BASE_ADDR UART2_BASE_ADDRESS +#define USART2_BASE_ADDR UART2_BASE_ADDRESS +#define USART2_BASE_ADDRESS UART2_BASE_ADDRESS +#define HAL_LL_UART2_BASE_ADDR UART2_BASE_ADDRESS +#define HAL_LL_USART2_BASE_ADDR UART2_BASE_ADDRESS +#define HAL_LL_UART2_BASE_ADDRESS UART2_BASE_ADDRESS +#define HAL_LL_USART2_BASE_ADDRESS UART2_BASE_ADDRESS +#endif +#ifdef UART_MODULE_3 +#define USART_MODULE_3 UART_MODULE_3 +#define UART3_BASE_ADDRESS (0x40004800UL) +#define UART3_BASE_ADDR UART3_BASE_ADDRESS +#define USART3_BASE_ADDR UART3_BASE_ADDRESS +#define USART3_BASE_ADDRESS UART3_BASE_ADDRESS +#define HAL_LL_UART3_BASE_ADDR UART3_BASE_ADDRESS +#define HAL_LL_USART3_BASE_ADDR UART3_BASE_ADDRESS +#define HAL_LL_UART3_BASE_ADDRESS UART3_BASE_ADDRESS +#define HAL_LL_USART3_BASE_ADDRESS UART3_BASE_ADDRESS +#endif +#ifdef UART_MODULE_4 +#define USART_MODULE_4 UART_MODULE_4 +#define UART4_BASE_ADDRESS (0x40004C00UL) +#define UART4_BASE_ADDR UART4_BASE_ADDRESS +#define USART4_BASE_ADDR UART4_BASE_ADDRESS +#define USART4_BASE_ADDRESS UART4_BASE_ADDRESS +#define HAL_LL_UART4_BASE_ADDR UART4_BASE_ADDRESS +#define HAL_LL_USART4_BASE_ADDR UART4_BASE_ADDRESS +#define HAL_LL_UART4_BASE_ADDRESS UART4_BASE_ADDRESS +#define HAL_LL_USART4_BASE_ADDRESS UART4_BASE_ADDRESS +#endif +#ifdef UART_MODULE_5 +#define USART_MODULE_5 UART_MODULE_5 +#define UART5_BASE_ADDRESS (0x40005000UL) +#define UART5_BASE_ADDR UART5_BASE_ADDRESS +#define USART5_BASE_ADDR UART5_BASE_ADDRESS +#define USART5_BASE_ADDRESS UART5_BASE_ADDRESS +#define HAL_LL_UART5_BASE_ADDR UART5_BASE_ADDRESS +#define HAL_LL_USART5_BASE_ADDR UART5_BASE_ADDRESS +#define HAL_LL_UART5_BASE_ADDRESS UART5_BASE_ADDRESS +#define HAL_LL_USART5_BASE_ADDRESS UART5_BASE_ADDRESS +#endif + +/*!< @brief UART TX pins */ +static const hal_ll_uart_pin_map_t hal_ll_uart_tx_map[] = +{ + #ifdef UART4_TX_PC10_AF5 + {hal_ll_uart_module_num(UART_MODULE_4), PC10, UART4_BASE_ADDRESS, 5}, + #endif + #ifdef UART5_TX_PC12_AF5 + {hal_ll_uart_module_num(UART_MODULE_5), PC12, UART5_BASE_ADDRESS, 5}, + #endif + #ifdef USART1_TX_PA9_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PA9, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART1_TX_PB6_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PB6, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART1_TX_PC4_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PC4, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART1_TX_PE0_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PE0, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART1_TX_PG9_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PG9, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART2_TX_PA14_AF7 + {hal_ll_usart_module_num(USART_MODULE_2), PA14, USART2_BASE_ADDRESS, 7}, + #endif + #ifdef USART2_TX_PA2_AF7 + {hal_ll_usart_module_num(USART_MODULE_2), PA2, USART2_BASE_ADDRESS, 7}, + #endif + #ifdef USART2_TX_PB3_AF7 + {hal_ll_usart_module_num(USART_MODULE_2), PB3, USART2_BASE_ADDRESS, 7}, + #endif + #ifdef USART2_TX_PD5_AF7 + {hal_ll_usart_module_num(USART_MODULE_2), PD5, USART2_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_TX_PB10_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PB10, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_TX_PB9_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PB9, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_TX_PC10_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PC10, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_TX_PD8_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PD8, USART3_BASE_ADDRESS, 7}, + #endif + {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} + //------------ END TX +}; + +/*!< @brief UART RX pins */ +static const hal_ll_uart_pin_map_t hal_ll_uart_rx_map[] = +{ + #ifdef UART4_RX_PC11_AF5 + {hal_ll_uart_module_num(UART_MODULE_4), PC11, UART4_BASE_ADDRESS, 5}, + #endif + #ifdef UART5_RX_PD2_AF5 + {hal_ll_uart_module_num(UART_MODULE_5), PD2, UART5_BASE_ADDRESS, 5}, + #endif + #ifdef USART1_RX_PA10_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PA10, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART1_RX_PB7_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PB7, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART1_RX_PC5_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PC5, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART1_RX_PE1_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PE1, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART2_RX_PA15_AF7 + {hal_ll_usart_module_num(USART_MODULE_2), PA15, USART2_BASE_ADDRESS, 7}, + #endif + #ifdef USART2_RX_PA3_AF7 + {hal_ll_usart_module_num(USART_MODULE_2), PA3, USART2_BASE_ADDRESS, 7}, + #endif + #ifdef USART2_RX_PB4_AF7 + {hal_ll_usart_module_num(USART_MODULE_2), PB4, USART2_BASE_ADDRESS, 7}, + #endif + #ifdef USART2_RX_PD6_AF7 + {hal_ll_usart_module_num(USART_MODULE_2), PD6, USART2_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_RX_PB11_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PB11, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_RX_PB8_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PB8, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_RX_PC11_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PC11, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_RX_PD9_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PD9, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_RX_PE15_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PE15, USART3_BASE_ADDRESS, 7}, + #endif + {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} + //------------ END RX +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_UART_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/uart/hal_ll_uart_pin_map/implementations/doc_ds_87/hal_ll_uart_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/uart/hal_ll_uart_pin_map/implementations/doc_ds_87/hal_ll_uart_pin_map.h new file mode 100644 index 000000000..9f76f6bd3 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/uart/hal_ll_uart_pin_map/implementations/doc_ds_87/hal_ll_uart_pin_map.h @@ -0,0 +1,232 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_uart_pin_map.h + * @brief UART HAL LOW LEVEL PIN MAPS. + */ + +#ifndef _HAL_LL_UART_PIN_MAP_H_ +#define _HAL_LL_UART_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_uart_module_num(_module_num) (_module_num - 1) +#define hal_ll_usart_module_num(_module_num) hal_ll_uart_module_num(_module_num) +#define hal_ll_lpuart_module_num(_module_num) hal_ll_uart_module_num(_module_num) + +/*!< @brief Pin structure */ +typedef struct +{ + uint8_t module_index; + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + uint32_t af; +} hal_ll_uart_pin_map_t; + +#ifdef UART_MODULE_1 +#define USART_MODULE_1 UART_MODULE_1 +#define UART1_BASE_ADDRESS (0x40013800UL) +#define UART1_BASE_ADDR UART1_BASE_ADDRESS +#define USART1_BASE_ADDR UART1_BASE_ADDRESS +#define USART1_BASE_ADDRESS UART1_BASE_ADDRESS +#define HAL_LL_UART1_BASE_ADDR UART1_BASE_ADDRESS +#define HAL_LL_USART1_BASE_ADDR UART1_BASE_ADDRESS +#define HAL_LL_UART1_BASE_ADDRESS UART1_BASE_ADDRESS +#define HAL_LL_USART1_BASE_ADDRESS UART1_BASE_ADDRESS +#endif +#ifdef UART_MODULE_2 +#define USART_MODULE_2 UART_MODULE_2 +#define UART2_BASE_ADDRESS (0x40004400UL) +#define UART2_BASE_ADDR UART2_BASE_ADDRESS +#define USART2_BASE_ADDR UART2_BASE_ADDRESS +#define USART2_BASE_ADDRESS UART2_BASE_ADDRESS +#define HAL_LL_UART2_BASE_ADDR UART2_BASE_ADDRESS +#define HAL_LL_USART2_BASE_ADDR UART2_BASE_ADDRESS +#define HAL_LL_UART2_BASE_ADDRESS UART2_BASE_ADDRESS +#define HAL_LL_USART2_BASE_ADDRESS UART2_BASE_ADDRESS +#endif +#ifdef UART_MODULE_3 +#define USART_MODULE_3 UART_MODULE_3 +#define UART3_BASE_ADDRESS (0x40004800UL) +#define UART3_BASE_ADDR UART3_BASE_ADDRESS +#define USART3_BASE_ADDR UART3_BASE_ADDRESS +#define USART3_BASE_ADDRESS UART3_BASE_ADDRESS +#define HAL_LL_UART3_BASE_ADDR UART3_BASE_ADDRESS +#define HAL_LL_USART3_BASE_ADDR UART3_BASE_ADDRESS +#define HAL_LL_UART3_BASE_ADDRESS UART3_BASE_ADDRESS +#define HAL_LL_USART3_BASE_ADDRESS UART3_BASE_ADDRESS +#endif +#ifdef UART_MODULE_4 +#define USART_MODULE_4 UART_MODULE_4 +#define UART4_BASE_ADDRESS (0x40004C00UL) +#define UART4_BASE_ADDR UART4_BASE_ADDRESS +#define USART4_BASE_ADDR UART4_BASE_ADDRESS +#define USART4_BASE_ADDRESS UART4_BASE_ADDRESS +#define HAL_LL_UART4_BASE_ADDR UART4_BASE_ADDRESS +#define HAL_LL_USART4_BASE_ADDR UART4_BASE_ADDRESS +#define HAL_LL_UART4_BASE_ADDRESS UART4_BASE_ADDRESS +#define HAL_LL_USART4_BASE_ADDRESS UART4_BASE_ADDRESS +#endif +#ifdef UART_MODULE_5 +#define USART_MODULE_5 UART_MODULE_5 +#define UART5_BASE_ADDRESS (0x40005000UL) +#define UART5_BASE_ADDR UART5_BASE_ADDRESS +#define USART5_BASE_ADDR UART5_BASE_ADDRESS +#define USART5_BASE_ADDRESS UART5_BASE_ADDRESS +#define HAL_LL_UART5_BASE_ADDR UART5_BASE_ADDRESS +#define HAL_LL_USART5_BASE_ADDR UART5_BASE_ADDRESS +#define HAL_LL_UART5_BASE_ADDRESS UART5_BASE_ADDRESS +#define HAL_LL_USART5_BASE_ADDRESS UART5_BASE_ADDRESS +#endif + +/*!< @brief UART TX pins */ +static const hal_ll_uart_pin_map_t hal_ll_uart_tx_map[] = +{ + #ifdef UART4_TX_PC10_AF5 + {hal_ll_uart_module_num(UART_MODULE_4), PC10, UART4_BASE_ADDRESS, 5}, + #endif + #ifdef UART5_TX_PC12_AF5 + {hal_ll_uart_module_num(UART_MODULE_5), PC12, UART5_BASE_ADDRESS, 5}, + #endif + #ifdef USART1_TX_PA9_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PA9, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART1_TX_PB6_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PB6, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART1_TX_PC4_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PC4, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART1_TX_PE0_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PE0, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART1_TX_PG9_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PG9, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART2_TX_PA14_AF7 + {hal_ll_usart_module_num(USART_MODULE_2), PA14, USART2_BASE_ADDRESS, 7}, + #endif + #ifdef USART2_TX_PA2_AF7 + {hal_ll_usart_module_num(USART_MODULE_2), PA2, USART2_BASE_ADDRESS, 7}, + #endif + #ifdef USART2_TX_PB3_AF7 + {hal_ll_usart_module_num(USART_MODULE_2), PB3, USART2_BASE_ADDRESS, 7}, + #endif + #ifdef USART2_TX_PD5_AF7 + {hal_ll_usart_module_num(USART_MODULE_2), PD5, USART2_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_TX_PB10_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PB10, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_TX_PB9_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PB9, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_TX_PC10_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PC10, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_TX_PD8_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PD8, USART3_BASE_ADDRESS, 7}, + #endif + {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} + //------------ END TX +}; + +/*!< @brief UART RX pins */ +static const hal_ll_uart_pin_map_t hal_ll_uart_rx_map[] = +{ + #ifdef UART4_RX_PC11_AF5 + {hal_ll_uart_module_num(UART_MODULE_4), PC11, UART4_BASE_ADDRESS, 5}, + #endif + #ifdef UART5_RX_PD2_AF5 + {hal_ll_uart_module_num(UART_MODULE_5), PD2, UART5_BASE_ADDRESS, 5}, + #endif + #ifdef USART1_RX_PA10_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PA10, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART1_RX_PB7_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PB7, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART1_RX_PC5_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PC5, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART1_RX_PE1_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PE1, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART2_RX_PA15_AF7 + {hal_ll_usart_module_num(USART_MODULE_2), PA15, USART2_BASE_ADDRESS, 7}, + #endif + #ifdef USART2_RX_PA3_AF7 + {hal_ll_usart_module_num(USART_MODULE_2), PA3, USART2_BASE_ADDRESS, 7}, + #endif + #ifdef USART2_RX_PB4_AF7 + {hal_ll_usart_module_num(USART_MODULE_2), PB4, USART2_BASE_ADDRESS, 7}, + #endif + #ifdef USART2_RX_PD6_AF7 + {hal_ll_usart_module_num(USART_MODULE_2), PD6, USART2_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_RX_PB11_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PB11, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_RX_PB8_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PB8, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_RX_PC11_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PC11, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_RX_PD9_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PD9, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_RX_PE15_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PE15, USART3_BASE_ADDRESS, 7}, + #endif + {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} + //------------ END RX +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_UART_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/uart/hal_ll_uart_pin_map/implementations/doc_ds_88/hal_ll_uart_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/uart/hal_ll_uart_pin_map/implementations/doc_ds_88/hal_ll_uart_pin_map.h new file mode 100644 index 000000000..91d29282a --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/uart/hal_ll_uart_pin_map/implementations/doc_ds_88/hal_ll_uart_pin_map.h @@ -0,0 +1,229 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_uart_pin_map.h + * @brief UART HAL LOW LEVEL PIN MAPS. + */ + +#ifndef _HAL_LL_UART_PIN_MAP_H_ +#define _HAL_LL_UART_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_uart_module_num(_module_num) (_module_num - 1) +#define hal_ll_usart_module_num(_module_num) hal_ll_uart_module_num(_module_num) +#define hal_ll_lpuart_module_num(_module_num) hal_ll_uart_module_num(_module_num) + +/*!< @brief Pin structure */ +typedef struct +{ + uint8_t module_index; + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + uint32_t af; +} hal_ll_uart_pin_map_t; + +#ifdef UART_MODULE_1 +#define USART_MODULE_1 UART_MODULE_1 +#define UART1_BASE_ADDRESS (0x40013800UL) +#define UART1_BASE_ADDR UART1_BASE_ADDRESS +#define USART1_BASE_ADDR UART1_BASE_ADDRESS +#define USART1_BASE_ADDRESS UART1_BASE_ADDRESS +#define HAL_LL_UART1_BASE_ADDR UART1_BASE_ADDRESS +#define HAL_LL_USART1_BASE_ADDR UART1_BASE_ADDRESS +#define HAL_LL_UART1_BASE_ADDRESS UART1_BASE_ADDRESS +#define HAL_LL_USART1_BASE_ADDRESS UART1_BASE_ADDRESS +#endif +#ifdef UART_MODULE_2 +#define USART_MODULE_2 UART_MODULE_2 +#define UART2_BASE_ADDRESS (0x40004400UL) +#define UART2_BASE_ADDR UART2_BASE_ADDRESS +#define USART2_BASE_ADDR UART2_BASE_ADDRESS +#define USART2_BASE_ADDRESS UART2_BASE_ADDRESS +#define HAL_LL_UART2_BASE_ADDR UART2_BASE_ADDRESS +#define HAL_LL_USART2_BASE_ADDR UART2_BASE_ADDRESS +#define HAL_LL_UART2_BASE_ADDRESS UART2_BASE_ADDRESS +#define HAL_LL_USART2_BASE_ADDRESS UART2_BASE_ADDRESS +#endif +#ifdef UART_MODULE_3 +#define USART_MODULE_3 UART_MODULE_3 +#define UART3_BASE_ADDRESS (0x40004800UL) +#define UART3_BASE_ADDR UART3_BASE_ADDRESS +#define USART3_BASE_ADDR UART3_BASE_ADDRESS +#define USART3_BASE_ADDRESS UART3_BASE_ADDRESS +#define HAL_LL_UART3_BASE_ADDR UART3_BASE_ADDRESS +#define HAL_LL_USART3_BASE_ADDR UART3_BASE_ADDRESS +#define HAL_LL_UART3_BASE_ADDRESS UART3_BASE_ADDRESS +#define HAL_LL_USART3_BASE_ADDRESS UART3_BASE_ADDRESS +#endif +#ifdef UART_MODULE_4 +#define USART_MODULE_4 UART_MODULE_4 +#define UART4_BASE_ADDRESS (0x40004C00UL) +#define UART4_BASE_ADDR UART4_BASE_ADDRESS +#define USART4_BASE_ADDR UART4_BASE_ADDRESS +#define USART4_BASE_ADDRESS UART4_BASE_ADDRESS +#define HAL_LL_UART4_BASE_ADDR UART4_BASE_ADDRESS +#define HAL_LL_USART4_BASE_ADDR UART4_BASE_ADDRESS +#define HAL_LL_UART4_BASE_ADDRESS UART4_BASE_ADDRESS +#define HAL_LL_USART4_BASE_ADDRESS UART4_BASE_ADDRESS +#endif +#ifdef UART_MODULE_5 +#define USART_MODULE_5 UART_MODULE_5 +#define UART5_BASE_ADDRESS (0x40005000UL) +#define UART5_BASE_ADDR UART5_BASE_ADDRESS +#define USART5_BASE_ADDR UART5_BASE_ADDRESS +#define USART5_BASE_ADDRESS UART5_BASE_ADDRESS +#define HAL_LL_UART5_BASE_ADDR UART5_BASE_ADDRESS +#define HAL_LL_USART5_BASE_ADDR UART5_BASE_ADDRESS +#define HAL_LL_UART5_BASE_ADDRESS UART5_BASE_ADDRESS +#define HAL_LL_USART5_BASE_ADDRESS UART5_BASE_ADDRESS +#endif + +/*!< @brief UART TX pins */ +static const hal_ll_uart_pin_map_t hal_ll_uart_tx_map[] = +{ + #ifdef USART1_TX_PA9_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PA9, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART1_TX_PB6_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PB6, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART2_TX_PA14_AF7 + {hal_ll_usart_module_num(USART_MODULE_2), PA14, USART2_BASE_ADDRESS, 7}, + #endif + #ifdef USART2_TX_PA2_AF7 + {hal_ll_usart_module_num(USART_MODULE_2), PA2, USART2_BASE_ADDRESS, 7}, + #endif + #ifdef USART2_TX_PB3_AF7 + {hal_ll_usart_module_num(USART_MODULE_2), PB3, USART2_BASE_ADDRESS, 7}, + #endif + #ifdef UART4_TX_PC10_AF5 + {hal_ll_uart_module_num(UART_MODULE_4), PC10, UART4_BASE_ADDRESS, 5}, + #endif + #ifdef UART5_TX_PC12_AF5 + {hal_ll_uart_module_num(UART_MODULE_5), PC12, UART5_BASE_ADDRESS, 5}, + #endif + #ifdef USART1_TX_PC4_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PC4, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_TX_PB10_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PB10, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_TX_PB9_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PB9, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_TX_PC10_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PC10, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_TX_PD8_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PD8, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART1_TX_PE0_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PE0, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART2_TX_PD5_AF7 + {hal_ll_usart_module_num(USART_MODULE_2), PD5, USART2_BASE_ADDRESS, 7}, + #endif + {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} + //------------ END TX +}; + +/*!< @brief UART RX pins */ +static const hal_ll_uart_pin_map_t hal_ll_uart_rx_map[] = +{ + #ifdef USART1_RX_PA10_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PA10, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART1_RX_PB7_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PB7, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART2_RX_PA15_AF7 + {hal_ll_usart_module_num(USART_MODULE_2), PA15, USART2_BASE_ADDRESS, 7}, + #endif + #ifdef USART2_RX_PA3_AF7 + {hal_ll_usart_module_num(USART_MODULE_2), PA3, USART2_BASE_ADDRESS, 7}, + #endif + #ifdef USART2_RX_PB4_AF7 + {hal_ll_usart_module_num(USART_MODULE_2), PB4, USART2_BASE_ADDRESS, 7}, + #endif + #ifdef UART4_RX_PC11_AF5 + {hal_ll_uart_module_num(UART_MODULE_4), PC11, UART4_BASE_ADDRESS, 5}, + #endif + #ifdef UART5_RX_PD2_AF5 + {hal_ll_uart_module_num(UART_MODULE_5), PD2, UART5_BASE_ADDRESS, 5}, + #endif + #ifdef USART1_RX_PC5_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PC5, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_RX_PB11_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PB11, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_RX_PB8_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PB8, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_RX_PC11_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PC11, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_RX_PD9_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PD9, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_RX_PE15_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PE15, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART1_RX_PE1_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PE1, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART2_RX_PD6_AF7 + {hal_ll_usart_module_num(USART_MODULE_2), PD6, USART2_BASE_ADDRESS, 7}, + #endif + {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} + //------------ END RX +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_UART_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/include/uart/hal_ll_uart_pin_map/implementations/doc_ds_89/hal_ll_uart_pin_map.h b/targets/arm/mikroe/ai_generated/stm32/include/uart/hal_ll_uart_pin_map/implementations/doc_ds_89/hal_ll_uart_pin_map.h new file mode 100644 index 000000000..8c839bd79 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/include/uart/hal_ll_uart_pin_map/implementations/doc_ds_89/hal_ll_uart_pin_map.h @@ -0,0 +1,229 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_uart_pin_map.h + * @brief UART HAL LOW LEVEL PIN MAPS. + */ + +#ifndef _HAL_LL_UART_PIN_MAP_H_ +#define _HAL_LL_UART_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_uart_module_num(_module_num) (_module_num - 1) +#define hal_ll_usart_module_num(_module_num) hal_ll_uart_module_num(_module_num) +#define hal_ll_lpuart_module_num(_module_num) hal_ll_uart_module_num(_module_num) + +/*!< @brief Pin structure */ +typedef struct +{ + uint8_t module_index; + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + uint32_t af; +} hal_ll_uart_pin_map_t; + +#ifdef UART_MODULE_1 +#define USART_MODULE_1 UART_MODULE_1 +#define UART1_BASE_ADDRESS (0x40013800UL) +#define UART1_BASE_ADDR UART1_BASE_ADDRESS +#define USART1_BASE_ADDR UART1_BASE_ADDRESS +#define USART1_BASE_ADDRESS UART1_BASE_ADDRESS +#define HAL_LL_UART1_BASE_ADDR UART1_BASE_ADDRESS +#define HAL_LL_USART1_BASE_ADDR UART1_BASE_ADDRESS +#define HAL_LL_UART1_BASE_ADDRESS UART1_BASE_ADDRESS +#define HAL_LL_USART1_BASE_ADDRESS UART1_BASE_ADDRESS +#endif +#ifdef UART_MODULE_2 +#define USART_MODULE_2 UART_MODULE_2 +#define UART2_BASE_ADDRESS (0x40004400UL) +#define UART2_BASE_ADDR UART2_BASE_ADDRESS +#define USART2_BASE_ADDR UART2_BASE_ADDRESS +#define USART2_BASE_ADDRESS UART2_BASE_ADDRESS +#define HAL_LL_UART2_BASE_ADDR UART2_BASE_ADDRESS +#define HAL_LL_USART2_BASE_ADDR UART2_BASE_ADDRESS +#define HAL_LL_UART2_BASE_ADDRESS UART2_BASE_ADDRESS +#define HAL_LL_USART2_BASE_ADDRESS UART2_BASE_ADDRESS +#endif +#ifdef UART_MODULE_3 +#define USART_MODULE_3 UART_MODULE_3 +#define UART3_BASE_ADDRESS (0x40004800UL) +#define UART3_BASE_ADDR UART3_BASE_ADDRESS +#define USART3_BASE_ADDR UART3_BASE_ADDRESS +#define USART3_BASE_ADDRESS UART3_BASE_ADDRESS +#define HAL_LL_UART3_BASE_ADDR UART3_BASE_ADDRESS +#define HAL_LL_USART3_BASE_ADDR UART3_BASE_ADDRESS +#define HAL_LL_UART3_BASE_ADDRESS UART3_BASE_ADDRESS +#define HAL_LL_USART3_BASE_ADDRESS UART3_BASE_ADDRESS +#endif +#ifdef UART_MODULE_4 +#define USART_MODULE_4 UART_MODULE_4 +#define UART4_BASE_ADDRESS (0x40004C00UL) +#define UART4_BASE_ADDR UART4_BASE_ADDRESS +#define USART4_BASE_ADDR UART4_BASE_ADDRESS +#define USART4_BASE_ADDRESS UART4_BASE_ADDRESS +#define HAL_LL_UART4_BASE_ADDR UART4_BASE_ADDRESS +#define HAL_LL_USART4_BASE_ADDR UART4_BASE_ADDRESS +#define HAL_LL_UART4_BASE_ADDRESS UART4_BASE_ADDRESS +#define HAL_LL_USART4_BASE_ADDRESS UART4_BASE_ADDRESS +#endif +#ifdef UART_MODULE_5 +#define USART_MODULE_5 UART_MODULE_5 +#define UART5_BASE_ADDRESS (0x40005000UL) +#define UART5_BASE_ADDR UART5_BASE_ADDRESS +#define USART5_BASE_ADDR UART5_BASE_ADDRESS +#define USART5_BASE_ADDRESS UART5_BASE_ADDRESS +#define HAL_LL_UART5_BASE_ADDR UART5_BASE_ADDRESS +#define HAL_LL_USART5_BASE_ADDR UART5_BASE_ADDRESS +#define HAL_LL_UART5_BASE_ADDRESS UART5_BASE_ADDRESS +#define HAL_LL_USART5_BASE_ADDRESS UART5_BASE_ADDRESS +#endif + +/*!< @brief UART TX pins */ +static const hal_ll_uart_pin_map_t hal_ll_uart_tx_map[] = +{ + #ifdef UART4_TX_PC10_AF5 + {hal_ll_uart_module_num(UART_MODULE_4), PC10, UART4_BASE_ADDRESS, 5}, + #endif + #ifdef UART5_TX_PC12_AF5 + {hal_ll_uart_module_num(UART_MODULE_5), PC12, UART5_BASE_ADDRESS, 5}, + #endif + #ifdef USART1_TX_PA9_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PA9, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART1_TX_PB6_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PB6, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART1_TX_PC4_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PC4, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART2_TX_PA14_AF7 + {hal_ll_usart_module_num(USART_MODULE_2), PA14, USART2_BASE_ADDRESS, 7}, + #endif + #ifdef USART2_TX_PA2_AF7 + {hal_ll_usart_module_num(USART_MODULE_2), PA2, USART2_BASE_ADDRESS, 7}, + #endif + #ifdef USART2_TX_PB3_AF7 + {hal_ll_usart_module_num(USART_MODULE_2), PB3, USART2_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_TX_PB10_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PB10, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_TX_PB9_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PB9, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_TX_PC10_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PC10, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_TX_PD8_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PD8, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART1_TX_PE0_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PE0, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART2_TX_PD5_AF7 + {hal_ll_usart_module_num(USART_MODULE_2), PD5, USART2_BASE_ADDRESS, 7}, + #endif + {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} + //------------ END TX +}; + +/*!< @brief UART RX pins */ +static const hal_ll_uart_pin_map_t hal_ll_uart_rx_map[] = +{ + #ifdef UART4_RX_PC11_AF5 + {hal_ll_uart_module_num(UART_MODULE_4), PC11, UART4_BASE_ADDRESS, 5}, + #endif + #ifdef UART5_RX_PD2_AF5 + {hal_ll_uart_module_num(UART_MODULE_5), PD2, UART5_BASE_ADDRESS, 5}, + #endif + #ifdef USART1_RX_PA10_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PA10, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART1_RX_PB7_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PB7, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART1_RX_PC5_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PC5, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART2_RX_PA15_AF7 + {hal_ll_usart_module_num(USART_MODULE_2), PA15, USART2_BASE_ADDRESS, 7}, + #endif + #ifdef USART2_RX_PA3_AF7 + {hal_ll_usart_module_num(USART_MODULE_2), PA3, USART2_BASE_ADDRESS, 7}, + #endif + #ifdef USART2_RX_PB4_AF7 + {hal_ll_usart_module_num(USART_MODULE_2), PB4, USART2_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_RX_PB11_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PB11, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_RX_PB8_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PB8, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_RX_PC11_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PC11, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_RX_PD9_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PD9, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART3_RX_PE15_AF7 + {hal_ll_usart_module_num(USART_MODULE_3), PE15, USART3_BASE_ADDRESS, 7}, + #endif + #ifdef USART1_RX_PE1_AF7 + {hal_ll_usart_module_num(USART_MODULE_1), PE1, USART1_BASE_ADDRESS, 7}, + #endif + #ifdef USART2_RX_PD6_AF7 + {hal_ll_usart_module_num(USART_MODULE_2), PD6, USART2_BASE_ADDRESS, 7}, + #endif + {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} + //------------ END RX +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_UART_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/src/adc/CMakeLists.txt b/targets/arm/mikroe/ai_generated/stm32/src/adc/CMakeLists.txt new file mode 100644 index 000000000..ad6df5c22 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/adc/CMakeLists.txt @@ -0,0 +1,76 @@ +## ./targets/arm/mikroe/ai_generated/stm32/src/adc/CMakeLists.txt + +## Check if current module is generated or not +set(MODULE_IS_GENERATED false) +get_files_recurse(${CMAKE_CURRENT_LIST_DIR}/implementations CMAKE_FILES cmake) +check_if_module_is_generated(MODULE_IS_GENERATED "${CMAKE_FILES}") + +## If current MCU has this module, add it +if(MODULE_IS_GENERATED) + set(hal_ll_def_list "") + set(mcu_header_path "") + + find_cortex(hal_ll_def_list) + list(APPEND hal_ll_def_list ${MCU_NAME}) + set(mcu_header_path ${MCU_NAME}_${_MSDK_PACKAGE_ID_}) + + ## BEGIN ADC + list(APPEND hal_ll_def_list "MACRO_USAGE_ADC") + + ## i.e "if (${MCU_NAME} MATCHES "^STM32C011F6$|^STM32C011C6$")" + ## List all MCUs and or them in the regex + foreach(cmakeFile ${CMAKE_FILES}) + include(${cmakeFile}) + endforeach() + ## END ADC + + mikrosdk_add_library(lib_hal_ll_adc MikroSDK.HalLowLevel.ADC + ${rcc_subimplementation}/hal_ll_rcc.h + ../../include/hal_ll_target.h + # BEGIN ADC + ${adc_subimplementation} + ../../include/adc/hal_ll_adc.h + ${adc_pin_map}/hal_ll_adc_pin_map.h + # END ADC + ) + + target_compile_definitions(lib_hal_ll_adc PUBLIC + ${hal_ll_def_list} + ) + + target_link_libraries(lib_hal_ll_adc PUBLIC + MikroC.Core + MikroSDK.HalLowLevelCore + MikroSDK.HalLowLevelCommon + ) + + string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) + target_include_directories(lib_hal_ll_adc + PRIVATE + ../../include + ../../include/gpio + ${gpio_subimplementation_include_dir} + # BEGIN ADC + ../../include/adc + ${adc_pin_map} + # END ADC + # BEGIN RCC + ${rcc_subimplementation} + # END RCC + INTERFACE + # BUILD + $ + $ + $ + $ + $ + $ + # INSTALL + $ + $ + ) + + mikrosdk_install(MikroSDK.HalLowLevel.ADC) + + install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.ADC ../../include/adc/hal_ll_adc.h) +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_1/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_1/CMakeLists.cmake new file mode 100644 index 000000000..413e82b3b --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_1/CMakeLists.cmake @@ -0,0 +1,10 @@ +if(${MCU_NAME} MATCHES "^STM32C011F4$|^STM32C011J4$|^STM32C011F6$|^STM32C011J6$|^STM32C011D6$") + set(adc_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_adc.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_1") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_1") + list(APPEND hal_ll_def_list "STM32C0xx") + list(APPEND hal_ll_def_list "STM32C01xx") + list(APPEND hal_ll_def_list "STM32C011xx") + set(adc_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/adc/hal_ll_adc_pin_map/implementations/doc_ds_1") + list(APPEND hal_ll_def_list "HAL_LL_ADC_RESOLUTION_CMAKE=HAL_LL_ADC_RESOLUTION_12_BIT") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_1/hal_ll_adc.c b/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_1/hal_ll_adc.c new file mode 100644 index 000000000..6d1349d70 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_1/hal_ll_adc.c @@ -0,0 +1,547 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_adc.c + * @brief Low level HAL ADC source file. + */ + +#include "hal_ll_adc.h" +#include "hal_ll_gpio.h" +#include "hal_ll_adc_pin_map.h" +#include "mcu.h" + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_adc_get_module_state_address ((hal_ll_adc_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_adc_get_handle (hal_ll_adc_handle_register_t *)hal_ll_adc_get_module_state_address->hal_ll_adc_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_adc_get_base_struct(_handle) ((hal_ll_adc_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_adc_get_base_from_hal_handle ((hal_ll_adc_hw_specifics_map_t *)((hal_ll_adc_handle_register_t *)\ + (((hal_ll_adc_handle_register_t *)(handle))->hal_ll_adc_handle))->hal_ll_adc_handle)->base +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_adc_module_num(_module_num) (_module_num - 1) + +#define HAL_LL_ADC_ISR_OFFSET ( 0x0 / 4 ) +#define HAL_LL_ADC_IER_OFFSET ( 0x4 / 4 ) +#define HAL_LL_ADC_CR_OFFSET ( 0x8 / 4 ) +#define HAL_LL_ADC_CFGR1_OFFSET ( 0xC / 4 ) +#define HAL_LL_ADC_CFGR2_OFFSET ( 0x10 / 4 ) +#define HAL_LL_ADC_SMPR_OFFSET ( 0x14 / 4 ) + +#define HAL_LL_ADC_CHSELR_OFFSET ( 0x28 / 4 ) +#define HAL_LL_ADC_DR_OFFSET ( 0x40 / 4 ) +#define HAL_LL_ADC_CCR_OFFSET ( 0x308 / 4 ) + +#define HAL_LL_ADC_ADEN_BIT 0 +#define HAL_LL_ADC_ADRDY_BIT 0 +#define HAL_LL_ADC_ADDIS_BIT 1 +#define HAL_LL_ADC_ADSTART_BIT 2 +#define HAL_LL_ADC_EOC_BIT 2 +#define HAL_LL_ADC_SCANDIR_BIT 2 +#define HAL_LL_ADC_ADSTP_BIT 4 +#define HAL_LL_ADC_ALIGN_BIT 5 +#define HAL_LL_ADC_CONT_BIT 13 +#define HAL_LL_ADC_ADCAL_BIT 31 +#define HAL_LL_ADC_ADVREGEN_BIT 28 + +#define HAL_LL_ADC1_ENABLE_CLOCK 20 + +#define HAL_LL_ADC_CKMODE0_BIT 30 +#define HAL_LL_ADC_CKMODE1_BIT 31 +#define HAL_LL_ADC_8MHZ 8000000ul +#define HAL_LL_ADC_16MHZ 16000000ul + +#define HAL_LL_ADC_12BIT_RES 0x00000000ul +#define HAL_LL_ADC_10BIT_RES 0x00000008ul +#define HAL_LL_ADC_8BIT_RES 0x00000010ul +#define HAL_LL_ADC_6BIT_RES 0x00000018ul + +#define HAL_LL_ADC_SMPR 0xFFFFFFF8ul +#define HAL_LL_ADC_EXTEN 0xFFFFF3FFul +#define HAL_LL_ADC_CR_WAIT 0x80000017ul + +#define HAL_LL_ADC_RESOLUTION_MASK 0xFFFFFFE7ul + +#define HAL_LL_MODULE_INDEX_ERROR 0xFFFFFFFFul + +// -------------------------------------------------------------- PRIVATE TYPES +/*!< @brief Local handle list */ +static hal_ll_adc_handle_register_t hal_ll_module_state[ADC_MODULE_COUNT] = { (handle_t *) NULL, (handle_t *) NULL, false }; + +/*!< Abbreviations used in source. */ +typedef uint32_t hal_ll_adc_base_handle_t; + +/*!< @brief ADC hw specific module values */ +typedef struct +{ + uint16_t pin_an[ADC_MODULE_COUNT]; +} hal_ll_adc_pin_id; + +/** + * Return values + */ +typedef enum +{ + HAL_LL_ADC_SUCCESS = 0, + HAL_LL_ADC_WRONG_PIN, + + HAL_LL_ADC_UNSUPPORTED_RESOLUTION = 1100, + HAL_LL_ADC_UNSUPPORTED_VREF, + HAL_LL_ADC_WRONG_CHANNEL, + HAL_LL_ADC_ERROR = (-1) +} hal_ll_adc_err_t; + +static hal_ll_adc_hw_specifics_map_t hal_ll_adc_hw_specifics_map[] = +{ + #ifdef ADC_MODULE_1 + {ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF}, + #endif + + + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF} +}; + +// ------------------------------------------------------------------ VARIABLES + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_adc_handle_register_t *low_level_handle; +static volatile hal_ll_adc_hw_specifics_map_t *hal_ll_adc_hw_specifics_map_local; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS + +/** + * @brief Enable ADC module 1 clock. + * @param none + * @return none + */ +static inline void adc1_enable_clock(); + +/** + * @brief Initialize ADC module. + * @param *map - ADC module local map. + * @return None + */ +static void hal_ll_adc_init( hal_ll_adc_hw_specifics_map_t *map ); + +/** + * @brief Check if pins are adequate. + * + * Checks analog pin the user has passed with pre-defined + * pins in ADC pin map. + * + * @param[in] pin - ADC pre-defined pin name. + * @param[in] *index - ADC map index value. + * @return hal_ll_pin_name_t Module index based on pin. + * + * Returns pre-defined module index from pin maps, if pin + * is adequate. + */ +static hal_ll_pin_name_t hal_ll_adc_check_pins( hal_ll_pin_name_t pin, hal_ll_adc_pin_id *index, hal_ll_adc_handle_register_t *handle_map ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_adc_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_adc_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_adc_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and channel values for ADC pin + * + * @param[in] module_index ADC HW module index -- 0,1,2... + * @param[in] *index ADC map index value + * + * @return None + */ +static void hal_ll_adc_map_pin( uint8_t module_index, hal_ll_adc_pin_id *index ); + +/** + * @brief Enable ADC module gate clock. + * @param base - ADC module base address. + * @return None + */ +static void _hal_ll_adc_enable_clock( uint8_t base ); + +/** + * @brief Initialize ADC module. + * @param *base - ADC module base address. + * @param resolution - ADC module resolution. + * @return None + */ +static void _hal_ll_adc_hw_init( hal_ll_adc_base_handle_t *base, uint32_t resolution ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_adc_register_handle(hal_ll_pin_name_t pin, hal_ll_adc_voltage_reference_t vref_input, hal_ll_adc_resolution_t resolution, hal_ll_adc_handle_register_t *handle_map, uint8_t *hal_module_id) +{ + uint16_t pin_check_result; + hal_ll_adc_pin_id index = {HAL_LL_PIN_NC}; + + if ( (pin_check_result = hal_ll_adc_check_pins( pin, &index, handle_map )) == HAL_LL_PIN_NC ) { + return HAL_LL_ADC_WRONG_PIN; + }; + + switch ( resolution ) + { + case HAL_LL_ADC_RESOLUTION_12_BIT: + hal_ll_adc_hw_specifics_map[pin_check_result].resolution = HAL_LL_ADC_12BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_10_BIT: + hal_ll_adc_hw_specifics_map[pin_check_result].resolution = HAL_LL_ADC_10BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_8_BIT: + hal_ll_adc_hw_specifics_map[pin_check_result].resolution = HAL_LL_ADC_8BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_6_BIT: + hal_ll_adc_hw_specifics_map[pin_check_result].resolution = HAL_LL_ADC_6BIT_RES; + break; + + default: + return HAL_LL_ADC_UNSUPPORTED_RESOLUTION; + } + + switch ( vref_input ) + { + case HAL_LL_ADC_VREF_EXTERNAL: + break; + + default: + return HAL_LL_ADC_UNSUPPORTED_VREF; + } + + if ( hal_ll_adc_hw_specifics_map[pin_check_result].pin != pin ) + { + hal_ll_adc_map_pin( pin_check_result, &index ); + + handle_map[pin_check_result].init_ll_state = false; + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[pin_check_result].hal_ll_adc_handle = (handle_t *)&hal_ll_adc_hw_specifics_map[pin_check_result].base; + + handle_map[pin_check_result].hal_ll_adc_handle = (handle_t *)&hal_ll_module_state[pin_check_result].hal_ll_adc_handle; + + return HAL_LL_ADC_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_adc( handle_t *handle ) +{ + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + hal_ll_adc_handle_register_t *hal_handle = (hal_ll_adc_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_adc_hw_specifics_map_local->module_index; + + hal_ll_adc_init( hal_ll_adc_hw_specifics_map_local ); + + hal_ll_module_state[pin_check_result].hal_ll_adc_handle = (handle_t *)&hal_ll_adc_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_ADC_SUCCESS; +} + +hal_ll_err_t hal_ll_adc_set_resolution(handle_t *handle, hal_ll_adc_resolution_t resolution) +{ + low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + + low_level_handle->init_ll_state = false; + + switch( resolution ) { + case HAL_LL_ADC_RESOLUTION_12_BIT: + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_12BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_10_BIT: + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_10BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_8_BIT: + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_8BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_6_BIT: + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_6BIT_RES; + break; + + default: + return HAL_LL_ADC_UNSUPPORTED_RESOLUTION; + } + + hal_ll_adc_init( hal_ll_adc_hw_specifics_map_local ); + + low_level_handle->init_ll_state = true; + + return HAL_LL_ADC_SUCCESS; +} + +hal_ll_err_t hal_ll_adc_set_vref_input(handle_t *handle, hal_ll_adc_voltage_reference_t vref_input) +{ + low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + + low_level_handle->init_ll_state = false; + + switch( vref_input ) { + case HAL_LL_ADC_VREF_EXTERNAL: + break; + + default: + return HAL_LL_ADC_UNSUPPORTED_RESOLUTION; + } + + hal_ll_adc_init( hal_ll_adc_hw_specifics_map_local ); + + low_level_handle->init_ll_state = true; + + return HAL_LL_ADC_SUCCESS; +} + +void hal_ll_adc_set_vref_value(handle_t *handle, float vref_value) +{ + low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + + hal_ll_adc_hw_specifics_map_local->vref_value = vref_value; +} + +hal_ll_err_t hal_ll_adc_read( handle_t *handle, uint16_t *readDatabuf ) +{ + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_base_handle_t *base = ( hal_ll_adc_base_handle_t * )hal_ll_adc_hw_specifics_map_local->base ; + + *(base + HAL_LL_ADC_CHSELR_OFFSET) = 1ul << hal_ll_adc_hw_specifics_map_local->channel; + set_reg_bit( ( base + HAL_LL_ADC_CR_OFFSET ), HAL_LL_ADC_ADSTART_BIT ); + + Delay_1us(); + while( !(check_reg_bit( ( base + HAL_LL_ADC_ISR_OFFSET ), HAL_LL_ADC_EOC_BIT ) ) ); + + *readDatabuf = ( *(base + HAL_LL_ADC_DR_OFFSET) ); + + return HAL_LL_ADC_SUCCESS; +} + +void hal_ll_adc_close( handle_t *handle ) +{ + hal_ll_adc_hw_specifics_map_t *hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + low_level_handle = hal_ll_adc_get_handle; + + if( hal_ll_adc_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + + hal_ll_adc_hw_specifics_map_local->vref_input = HAL_LL_ADC_VREF_DEFAULT; + hal_ll_adc_hw_specifics_map_local->vref_value = 0; + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_RESOLUTION_12_BIT; + + low_level_handle->hal_ll_adc_handle = NULL; + low_level_handle->hal_drv_adc_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_adc_hw_specifics_map_local->pin = HAL_LL_PIN_NC; + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static hal_ll_pin_name_t hal_ll_adc_check_pins( hal_ll_pin_name_t pin, hal_ll_adc_pin_id *index, hal_ll_adc_handle_register_t *handle_map ) +{ + static const uint16_t adc_map_size = ( sizeof( _adc_map ) / sizeof( hal_ll_adc_pin_map_t ) ); + uint16_t pin_index = 0; + uint8_t index_counter = 0; + uint8_t hal_ll_module_id = 0; + + if ( HAL_LL_PIN_NC == pin ) { + return HAL_LL_PIN_NC; + } + + for ( pin_index = 0; pin_index < adc_map_size; pin_index++ ) + { + if ( pin == _adc_map[pin_index].pin ) + { + // Get module number + hal_ll_module_id = _adc_map[pin_index].module_index; + // Map pin name + index->pin_an[hal_ll_module_id] = pin_index; + + // Check if module is taken + if ( NULL == handle_map[ hal_ll_module_id ].hal_drv_adc_handle ) { + return hal_ll_module_id; + } else if ( ADC_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static void hal_ll_adc_map_pin( uint8_t module_index, hal_ll_adc_pin_id *index ) { + // Map new pins + hal_ll_adc_hw_specifics_map[module_index].pin = _adc_map[ index->pin_an[module_index] ].pin; + hal_ll_adc_hw_specifics_map[module_index].channel = _adc_map[ index->pin_an[module_index] ].channel; +} + +static hal_ll_adc_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof(hal_ll_adc_handle_register_t)); + static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof(hal_ll_adc_handle_register_t)); + + while( hal_ll_module_count-- ) { + if (hal_ll_adc_get_base_from_hal_handle == hal_ll_adc_hw_specifics_map[hal_ll_module_count].base) { + return &hal_ll_adc_hw_specifics_map[hal_ll_module_count]; + } + } + + return &hal_ll_adc_hw_specifics_map[hal_ll_module_error]; +} + + +static inline void adc1_enable_clock() +{ + set_reg_bit( _RCC_APBENR2, HAL_LL_ADC1_ENABLE_CLOCK ); +} +static void _hal_ll_adc_enable_clock( uint8_t base ) +{ + switch ( base ) + { + #ifdef ADC_MODULE_1 + case ( hal_ll_adc_module_num(ADC_MODULE_1) ): + adc1_enable_clock(); + break; + #endif + + } +} + +static void _hal_ll_adc_hw_init( hal_ll_adc_base_handle_t *base, uint32_t resolution ) +{ + rcc_clocks_t rcc_clocks; + static uint32_t *reg; + /* ADC clock + The ADC features two clock schemes: + Clock for the analog circuitry: ADCCLK, common to all ADCs + This clock is generated from the APB2 clock divided by a programmable prescaler that + allows the ADC to work at fPCLK2/2, /4, /6 or /8. ADCCLK maximum value is 30 MHz + when the APB2 clock is at 60 MHz. */ + RCC_GetClocksFrequency( &rcc_clocks ); + + // Turn off ADC module. + if ( check_reg_bit( ( base + HAL_LL_ADC_CR_OFFSET ), HAL_LL_ADC_ADEN_BIT ) ) + { + while( check_reg_bit( ( base + HAL_LL_ADC_CR_OFFSET ), HAL_LL_ADC_ADSTART_BIT ) ); + set_reg_bit( ( base + HAL_LL_ADC_CR_OFFSET ), HAL_LL_ADC_ADDIS_BIT ); + while( check_reg_bit( ( base + HAL_LL_ADC_CR_OFFSET ), HAL_LL_ADC_ADDIS_BIT )); + } + + if ( rcc_clocks.pclk < HAL_LL_ADC_8MHZ ) // Set clock and prescaler. + { + // If less than 8MHz, prescaler is set to 1 (read caution on pg. 252 in the reference manual). + set_reg_bit( ( base + HAL_LL_ADC_CFGR2_OFFSET ), HAL_LL_ADC_CKMODE0_BIT ); + set_reg_bit( ( base + HAL_LL_ADC_CFGR2_OFFSET ), HAL_LL_ADC_CKMODE1_BIT ); + } + else if ( rcc_clocks.pclk < HAL_LL_ADC_16MHZ ) // Set clock and prescaler. + { + // Above 8 Mhz, prescaler is set to 2. + set_reg_bit( ( base + HAL_LL_ADC_CFGR2_OFFSET ), HAL_LL_ADC_CKMODE0_BIT ); + clear_reg_bit( ( base + HAL_LL_ADC_CFGR2_OFFSET ), HAL_LL_ADC_CKMODE1_BIT ); + }else + { + // Above 16 Mhz, prescaler is set to 4. + clear_reg_bit( ( base + HAL_LL_ADC_CFGR2_OFFSET ), HAL_LL_ADC_CKMODE0_BIT ); + set_reg_bit( ( base + HAL_LL_ADC_CFGR2_OFFSET ), HAL_LL_ADC_CKMODE1_BIT ); + } + + // Wait for ADEN to go down. + while( check_reg_bit( ( base + HAL_LL_ADC_CR_OFFSET ), HAL_LL_ADC_ADEN_BIT ) ); + + // Start calibration. + set_reg_bit( ( base + HAL_LL_ADC_CR_OFFSET ), HAL_LL_ADC_ADVREGEN_BIT ); + Delay_us(30); + set_reg_bit( ( base + HAL_LL_ADC_CR_OFFSET ), HAL_LL_ADC_ADCAL_BIT ); + while( check_reg_bit( ( base + HAL_LL_ADC_CR_OFFSET ), HAL_LL_ADC_ADCAL_BIT ) ); + + // Set sampling time - 1.5 ADC clock. + *( base + HAL_LL_ADC_SMPR_OFFSET ) &= HAL_LL_ADC_SMPR; + + // Set resolution. + reg = ( base + HAL_LL_ADC_CFGR1_OFFSET ); + *reg &= HAL_LL_ADC_RESOLUTION_MASK; + *reg |= resolution; + + // Wait for hardware to clear ADC_CR register. + while( ( *( base + HAL_LL_ADC_CR_OFFSET ) & HAL_LL_ADC_CR_WAIT ) != 0 ); + + // Scan sequence upward. + clear_reg_bit( ( base + HAL_LL_ADC_CFGR1_OFFSET ), HAL_LL_ADC_SCANDIR_BIT ); + + // Data alignment - right. + clear_reg_bit( ( base + HAL_LL_ADC_CFGR1_OFFSET ), HAL_LL_ADC_ALIGN_BIT ); + + // Single conversion mode. + clear_reg_bit( ( base + HAL_LL_ADC_CFGR1_OFFSET ), HAL_LL_ADC_CONT_BIT ); + + // External trigger disable. + *( base + HAL_LL_ADC_CFGR1_OFFSET ) &= HAL_LL_ADC_EXTEN; + + // Turn on ADC module. + set_reg_bit( ( base + HAL_LL_ADC_CR_OFFSET ), HAL_LL_ADC_ADEN_BIT ); + while( !( check_reg_bit( ( base + HAL_LL_ADC_ISR_OFFSET ), HAL_LL_ADC_ADRDY_BIT ) ) ); +} + +static void hal_ll_adc_init( hal_ll_adc_hw_specifics_map_t *map ) { + + hal_ll_gpio_analog_input( hal_ll_gpio_port_base( hal_ll_gpio_port_index( map->pin ) ), + hal_ll_gpio_pin_mask( map->pin ) ); + + _hal_ll_adc_enable_clock( map->module_index ); + + _hal_ll_adc_hw_init((hal_ll_adc_base_handle_t *)map->base, map->resolution); + +} +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_160/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_160/CMakeLists.cmake new file mode 100644 index 000000000..e77bbdb53 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_160/CMakeLists.cmake @@ -0,0 +1,10 @@ +if(${MCU_NAME} MATCHES "^STM32L4P5AE$|^STM32L4P5AG$|^STM32L4P5CE$|^STM32L4P5CG$|^STM32L4P5QE$|^STM32L4P5QG$|^STM32L4P5RE$|^STM32L4P5RG$|^STM32L4P5VE$|^STM32L4P5VG$|^STM32L4P5ZE$|^STM32L4P5ZG$") + set(adc_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_adc.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_160") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_160") + list(APPEND hal_ll_def_list "STM32L4xx") + list(APPEND hal_ll_def_list "STM32L4Pxx") + list(APPEND hal_ll_def_list "STM32L4P5xx") + set(adc_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/adc/hal_ll_adc_pin_map/implementations/doc_ds_160") + list(APPEND hal_ll_def_list "HAL_LL_ADC_RESOLUTION_CMAKE=HAL_LL_ADC_RESOLUTION_12_BIT") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_160/hal_ll_adc.c b/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_160/hal_ll_adc.c new file mode 100644 index 000000000..03b370fd1 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_160/hal_ll_adc.c @@ -0,0 +1,628 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_adc.c + * @brief Low level HAL ADC source file. + */ + +#include "hal_ll_adc.h" +#include "hal_ll_gpio.h" +#include "hal_ll_adc_pin_map.h" + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_adc_get_module_state_address ((hal_ll_adc_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_adc_get_handle (hal_ll_adc_handle_register_t *)hal_ll_adc_get_module_state_address->hal_ll_adc_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_adc_get_base_struct(_handle) ((hal_ll_adc_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_adc_get_base_from_hal_handle ((hal_ll_adc_hw_specifics_map_t *)((hal_ll_adc_handle_register_t *)\ + (((hal_ll_adc_handle_register_t *)(handle))->hal_ll_adc_handle))->hal_ll_adc_handle)->base +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_adc_module_num(_module_num) (_module_num - 1) + +// ADC common registers. + +#define hal_ll_adc_module_num(_module_num) (_module_num - 1) + +#define HAL_LL_ADC_CSR_OFFSET ( 0x300 / 4 ) +#define HAL_LL_ADC_CCR_OFFSET ( 0x308 / 4 ) +#define HAL_LL_ADC_CDR_OFFSET ( 0x30C / 4 ) + +#define HAL_LL_ADC_APB2ENR_SYSCFGEN 0 +#define HAL_LL_ADC_VREF_ENVR 0 +#define HAL_LL_ADC_ADRDYIE_BIT 0 +#define HAL_LL_ADC_ADEN_BIT 0 +#define HAL_LL_ADC_ADRDY_BIT 0 +#define HAL_LL_ADC_ADDIS_BIT 1 +#define HAL_LL_ADC_EOC_BIT 2 +#define HAL_LL_ADC_ADSTART_BIT 2 +#define HAL_LL_ADC_RESOLUTION_BIT0 3 +#define HAL_LL_ADC_RESOLUTION_BIT1 4 +#define HAL_LL_ADC_VREF_VRR 3 +#define HAL_LL_ADC_ALIGN_BIT 5 + +#define HAL_LL_ADC1_ENABLE_CLOCK 13 +#define HAL_LL_ADC2_ENABLE_CLOCK 13 + +#define HAL_LL_ADC_CONT_BIT 13 +#define HAL_LL_ADC_DISCEN_BIT 16 +#define HAL_LL_ADC_ADVREGEN_BIT 28 +#define HAL_LL_ADC_DEEPPWD_BIT 29 +#define HAL_LL_ADC_ADCALDIF_BIT 30 +#define HAL_LL_ADC_ADCAL_BIT 31 +#define HAL_LL_ADC_PIN_MASK 0xF + +#define HAL_LL_ADC_12BIT_RES 0x00000000ul +#define HAL_LL_ADC_10BIT_RES 0x00000008ul +#define HAL_LL_ADC_8BIT_RES 0x00000010ul +#define HAL_LL_ADC_6BIT_RES 0x00000018ul + +#define ADC_CAL_SINGLE 0x00000000ul +#define ADC_CAL_DIF 0x00000001ul +#define HAL_LL_ADC_CLK_SRC 0x30000000ul +#define HAL_LL_ADC_VOLTAGE 0xCFFFFFFFul +#define HAL_LL_ADC_CCR 0x50040308ul +#define HAL_LL_ADC_CKMODE_MASK 0x00000000ul +#define HAL_LL_ADC_VREFEN_MASK 0x00400000ul +#define HAL_LL_ADC_CCIPR 0x40021088ul +#define HAL_LL_ADC_PRESCALER 0xFFC3FFFFul +#define HAL_LL_ADC_CONVERSION 0xFFFFFFF0ul +#define HAL_LL_ADC_VREF_CSR 0x40010030ul +#define HAL_LL_ADC_CONVERSION_ONE 0x000007C0ul + +#define HAL_LL_MODULE_INDEX_ERROR 0xFFFFFFFFul + +#define HAL_LL_RESOLUTION_MASK 0xFFFFFFE7ul + +#define HAL_LL_ADC_DEFAULT_BASE_ADDRESS 0xFF + +// -------------------------------------------------------------- PRIVATE TYPES +/*!< @brief Local handle list */ +static hal_ll_adc_handle_register_t hal_ll_module_state[ADC_MODULE_COUNT] = { (handle_t *) NULL, (handle_t *) NULL, false }; + +/** + * Return values + */ +typedef enum +{ + HAL_LL_ADC_SUCCESS = 0, + HAL_LL_ADC_WRONG_PIN, + + HAL_LL_ADC_UNSUPPORTED_RESOLUTION = 1100, + HAL_LL_ADC_UNSUPPORTED_VREF, + HAL_LL_ADC_WRONG_CHANNEL, + HAL_LL_ADC_ERROR = (-1) +} hal_ll_adc_err_t; + +/*!< @brief ADC register structure. */ +typedef struct +{ + uint32_t isr; /* ADC interrupt and status register (ADC_ISR) */ + uint32_t ier; /* ADC interrupt enable register (ADC_IER) */ + uint32_t cr; /* ADC control register (ADC_CR) */ + uint32_t cfgr; /* ADC configuration register (ADC_CFGR) */ + uint32_t cfgr2; /* ADC configuration register (ADC_CFGR) */ + uint32_t smpr1; /* ADC sample time register 1 (ADC_SMPR1) */ + uint32_t smpr2; /* ADC sample time register 1 (ADC_SMPR1) */ + uint32_t __unused1[1]; /* */ + uint32_t tr1; /* ADC watchdog threshold register 1 (ADC_TR1) */ + uint32_t tr2; /* ADC watchdog threshold register 1 (ADC_TR1) */ + uint32_t tr3; /* ADC watchdog threshold register 1 (ADC_TR1) */ + uint32_t __unused2[1]; /* */ + uint32_t sqr1; /* ADC regular sequence register 1 (ADC_SQR1) */ + uint32_t sqr2; /* ADC regular sequence register 1 (ADC_SQR1) */ + uint32_t sqr3; /* ADC regular sequence register 1 (ADC_SQR1) */ + uint32_t sqr4; /* ADC regular sequence register 1 (ADC_SQR1) */ + uint32_t dr; /* ADC regular data register (ADC_DR) */ + uint32_t __unused3[2]; /* */ + uint32_t jsqr; /* ADC injected sequence register (ADC_JSQR) */ + uint32_t __unused4[4]; /* */ + uint32_t ofr1; /* ADC offset y register (ADC_OFRy) */ + uint32_t ofr2; /* ADC offset y register (ADC_OFRy) */ + uint32_t ofr3; /* ADC offset y register (ADC_OFRy) */ + uint32_t ofr4; /* ADC offset y register (ADC_OFRy) */ + uint32_t __unused5[4]; /* */ + uint32_t jdr1; /* ADC injected channel y data register (ADC_JDRy) */ + uint32_t jdr2; /* ADC injected channel y data register (ADC_JDRy) */ + uint32_t jdr3; /* ADC injected channel y data register (ADC_JDRy) */ + uint32_t jdr4; /* ADC injected channel y data register (ADC_JDRy) */ + uint32_t __unused6[4]; /* */ + uint32_t awd2cr; /* ADC analog watchdog 2 configuration register (ADC_AWD2CR) */ + uint32_t awd3cr; /* ADC analog watchdog 2 configuration register (ADC_AWD2CR) */ + uint32_t __unused7[2]; /* */ + uint32_t difsel; /* ADC differential mode selection register (ADC_DIFSEL) */ + uint32_t calfact; /* ADC calibration factors (ADC_CALFACT) */ + uint32_t csr; /* ADC common status register (ADC_CSR) */ + uint32_t __unused8[1]; /* */ + uint32_t ccr; /* ADC common control register (ADC_CCR) */ + uint32_t cdr; /* ADC common regular data register for dual mode (ADC_CDR) */ +} hal_ll_adc_base_handle_t; + +/*!< @brief ADC hw specific module values */ +typedef struct +{ + uint16_t pin_an[ADC_MODULE_COUNT]; +} hal_ll_adc_pin_id; + +static hal_ll_adc_hw_specifics_map_t hal_ll_adc_hw_specifics_map[] = +{ + #ifdef ADC_MODULE_1 + {ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF}, + #endif + #ifdef ADC_MODULE_2 + {ADC2_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF}, + #endif + + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF} +}; + +// ------------------------------------------------------------------ VARIABLES + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_adc_handle_register_t *low_level_handle; +static volatile hal_ll_adc_hw_specifics_map_t *hal_ll_adc_hw_specifics_map_local; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Enable ADC module 1 clock. + * @param none + * @return none + */ +static inline void adc1_enable_clock(); +/** + * @brief Enable ADC module 2 clock. + * @param none + * @return none + */ +static inline void adc2_enable_clock(); + + +/** + * @brief Initialize ADC module. + * @param *map - ADC module local map. + * @return None + */ +static void hal_ll_adc_init( hal_ll_adc_hw_specifics_map_t *map ); + +/** + * @brief Check if pins are adequate. + * + * Checks analog pin the user has passed with pre-defined + * pins in ADC pin map. + * + * @param[in] pin - ADC pre-defined pin name. + * @param[in] *index - ADC map index value. + * @return hal_ll_pin_name_t Module index based on pin. + * + * Returns pre-defined module index from pin maps, if pin + * is adequate. + */ +static hal_ll_pin_name_t hal_ll_adc_check_pins( hal_ll_pin_name_t pin, hal_ll_adc_pin_id *index, hal_ll_adc_handle_register_t *handle_map ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and channel values for ADC pin + * + * @param[in] module_index ADC HW module index -- 0,1,2... + * @param[in] *index ADC map index value + * + * @return None + */ +static void hal_ll_adc_map_pin( uint8_t module_index, hal_ll_adc_pin_id *index ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_adc_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_adc_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_adc_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Enable ADC module gate clock. + * @param base - ADC module base address. + * @return None + */ +static void _hal_ll_adc_enable_clock( uint8_t base ); + +/** + * @brief Initialize ADC module. + * @param *base - ADC module base address. + * @param resolution - ADC module resolution. + * @return None + */ +static void _hal_ll_adc_hw_init( hal_ll_adc_base_handle_t *base, uint32_t resolution ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_adc_register_handle(hal_ll_pin_name_t pin, hal_ll_adc_voltage_reference_t vref_input, hal_ll_adc_resolution_t resolution, hal_ll_adc_handle_register_t *handle_map, uint8_t *hal_module_id) +{ + uint16_t pin_check_result; + hal_ll_adc_pin_id index = {HAL_LL_PIN_NC}; + + if ( (pin_check_result = hal_ll_adc_check_pins( pin, &index, handle_map )) == HAL_LL_PIN_NC ) { + return HAL_LL_ADC_WRONG_PIN; + }; + + switch ( resolution ) + { + case HAL_LL_ADC_RESOLUTION_12_BIT: + hal_ll_adc_hw_specifics_map[pin_check_result].resolution = HAL_LL_ADC_12BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_10_BIT: + hal_ll_adc_hw_specifics_map[pin_check_result].resolution = HAL_LL_ADC_10BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_8_BIT: + hal_ll_adc_hw_specifics_map[pin_check_result].resolution = HAL_LL_ADC_8BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_6_BIT: + hal_ll_adc_hw_specifics_map[pin_check_result].resolution = HAL_LL_ADC_6BIT_RES; + break; + default: + return HAL_LL_ADC_UNSUPPORTED_RESOLUTION; + } + + switch ( vref_input ) + { + case HAL_LL_ADC_VREF_EXTERNAL: + break; + + default: + return HAL_LL_ADC_UNSUPPORTED_VREF; + } + + if ( hal_ll_adc_hw_specifics_map[pin_check_result].pin != pin ) + { + hal_ll_adc_map_pin( pin_check_result, &index ); + + handle_map[pin_check_result].init_ll_state = false; + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[pin_check_result].hal_ll_adc_handle = (handle_t *)&hal_ll_adc_hw_specifics_map[pin_check_result].base; + + handle_map[pin_check_result].hal_ll_adc_handle = (handle_t *)&hal_ll_module_state[pin_check_result].hal_ll_adc_handle; + + return HAL_LL_ADC_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_adc( handle_t *handle ) +{ + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + hal_ll_adc_handle_register_t *hal_handle = (hal_ll_adc_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_adc_hw_specifics_map_local->module_index; + + hal_ll_adc_init( hal_ll_adc_hw_specifics_map_local ); + + hal_ll_module_state[pin_check_result].hal_ll_adc_handle = (handle_t *)&hal_ll_adc_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_ADC_SUCCESS; +} + +hal_ll_err_t hal_ll_adc_set_resolution(handle_t *handle, hal_ll_adc_resolution_t resolution) +{ + low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + + low_level_handle->init_ll_state = false; + + switch( resolution ) { + case HAL_LL_ADC_RESOLUTION_12_BIT: + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_12BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_10_BIT: + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_10BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_8_BIT: + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_8BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_6_BIT: + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_6BIT_RES; + break; + + default: + return HAL_LL_ADC_UNSUPPORTED_RESOLUTION; + } + + hal_ll_adc_init( hal_ll_adc_hw_specifics_map_local ); + + low_level_handle->init_ll_state = true; + + return HAL_LL_ADC_SUCCESS; +} + +hal_ll_err_t hal_ll_adc_set_vref_input(handle_t *handle, hal_ll_adc_voltage_reference_t vref_input) +{ + low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + + low_level_handle->init_ll_state = false; + + switch( vref_input ) { + case HAL_LL_ADC_VREF_EXTERNAL: + break; + + default: + return HAL_LL_ADC_UNSUPPORTED_VREF; + } + + hal_ll_adc_init( hal_ll_adc_hw_specifics_map_local ); + + low_level_handle->init_ll_state = true; + + return HAL_LL_ADC_SUCCESS; +} + +void hal_ll_adc_set_vref_value(handle_t *handle, float vref_value) +{ + low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + + hal_ll_adc_hw_specifics_map_local->vref_value = vref_value; +} + +hal_ll_err_t hal_ll_adc_read( handle_t *handle, uint16_t *readDatabuf ) +{ + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_base_handle_t *base = ( hal_ll_adc_base_handle_t * )hal_ll_adc_hw_specifics_map_local->base ; + + while( ( check_reg_bit( &( base->cr ), HAL_LL_ADC_ADSTART_BIT ) ) ); + base->sqr1 &= ~HAL_LL_ADC_CONVERSION_ONE; + base->sqr1 |= ( ( hal_ll_adc_hw_specifics_map_local->channel << 6 ) ); + + Delay_1us(); + + // Start the conversion. + set_reg_bit( &( base->cr ), HAL_LL_ADC_ADSTART_BIT ); + + while ( !( check_reg_bit( &( base->isr ), HAL_LL_ADC_EOC_BIT ) ) ); + // Conversion result from SS3. + *readDatabuf = base->dr; + + return HAL_LL_ADC_SUCCESS; +} + +void hal_ll_adc_close( handle_t *handle ) +{ + hal_ll_adc_hw_specifics_map_t *hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + low_level_handle = hal_ll_adc_get_handle; + + if( hal_ll_adc_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + + hal_ll_adc_hw_specifics_map_local->vref_input = HAL_LL_ADC_VREF_DEFAULT; + hal_ll_adc_hw_specifics_map_local->vref_value = 0; + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_RESOLUTION_12_BIT; + + low_level_handle->hal_ll_adc_handle = NULL; + low_level_handle->hal_drv_adc_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_adc_hw_specifics_map_local->pin = HAL_LL_PIN_NC; + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static hal_ll_pin_name_t hal_ll_adc_check_pins( hal_ll_pin_name_t pin, hal_ll_adc_pin_id *index, hal_ll_adc_handle_register_t *handle_map ) +{ + static const uint16_t adc_map_size = ( sizeof( _adc_map ) / sizeof( hal_ll_adc_pin_map_t ) ); + uint16_t pin_index = 0; + uint8_t index_counter = 0; + uint8_t hal_ll_module_id = 0; + + if ( HAL_LL_PIN_NC == pin ) { + return HAL_LL_PIN_NC; + } + + for ( pin_index = 0; pin_index < adc_map_size; pin_index++ ) + { + if ( pin == _adc_map[pin_index].pin ) + { + // Get module number + hal_ll_module_id = _adc_map[pin_index].module_index; + // Map pin name + index->pin_an[hal_ll_module_id] = pin_index; + + // Check if module is taken + if ( NULL == handle_map[ hal_ll_module_id ].hal_drv_adc_handle ) { + return hal_ll_module_id; + } else if ( ADC_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static void hal_ll_adc_map_pin( uint8_t module_index, hal_ll_adc_pin_id *index ) { + // Map new pins + hal_ll_adc_hw_specifics_map[module_index].pin = _adc_map[ index->pin_an[module_index] ].pin; + hal_ll_adc_hw_specifics_map[module_index].channel = _adc_map[ index->pin_an[module_index] ].channel; +} + +static hal_ll_adc_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof(hal_ll_adc_handle_register_t)); + static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof(hal_ll_adc_handle_register_t)); + + while( hal_ll_module_count-- ) { + if (hal_ll_adc_get_base_from_hal_handle == hal_ll_adc_hw_specifics_map[hal_ll_module_count].base) { + return &hal_ll_adc_hw_specifics_map[hal_ll_module_count]; + } + } + + return &hal_ll_adc_hw_specifics_map[hal_ll_module_error]; +} + +static inline void adc1_enable_clock() +{ + set_reg_bit( _RCC_AHB2ENR, HAL_LL_ADC1_ENABLE_CLOCK ); +} + +static inline void adc2_enable_clock() +{ + set_reg_bit( _RCC_AHB2ENR, HAL_LL_ADC2_ENABLE_CLOCK ); +} + +static void _hal_ll_adc_enable_clock( uint8_t base ) +{ + switch ( base ) + { + #ifdef ADC_MODULE_1 + case ( hal_ll_adc_module_num(ADC_MODULE_1) ): + adc1_enable_clock(); + break; + #endif + #ifdef ADC_MODULE_2 + case ( hal_ll_adc_module_num(ADC_MODULE_2) ): + adc2_enable_clock(); + break; + #endif + } +} +static void _hal_ll_adc_hw_init( hal_ll_adc_base_handle_t *base, uint32_t resolution ) +{ + static uint32_t wait_loop_index = 0; + static uint32_t *reg; + reg = HAL_LL_ADC_CCIPR; + + // Select ADC clock source. + *reg |= HAL_LL_ADC_CLK_SRC; + + // Exit from deep power down mode. + if ( check_reg_bit( &( base->cr ), HAL_LL_ADC_DEEPPWD_BIT ) ) + { + clear_reg_bit( &( base->cr ), HAL_LL_ADC_DEEPPWD_BIT ); + } + + // Enable voltage regulator. + base->cr &= HAL_LL_ADC_VOLTAGE; + + if ( !( check_reg_bit( &( base->cr ), HAL_LL_ADC_ADVREGEN_BIT ) ) ) + { + set_reg_bit( &( base->cr ), HAL_LL_ADC_ADVREGEN_BIT ); + } + + // Enable ADC interrupts. + set_reg_bit( &( base->ier ), HAL_LL_ADC_ADRDYIE_BIT ); + + // Disable ADC + if ( check_reg_bit( &( base->cr ), HAL_LL_ADC_ADEN_BIT ) ) + { + set_reg_bit( &( base->cr ), HAL_LL_ADC_ADDIS_BIT ); + } + + // Voltage reference enable, ckmode SYSCLK. + reg = HAL_LL_ADC_CCR; + *reg |= (HAL_LL_ADC_CKMODE_MASK | HAL_LL_ADC_VREFEN_MASK); + + // Select calibration mode. + clear_reg_bit( &( base->cr ), HAL_LL_ADC_ADCALDIF_BIT ); + + // Start ADC calibration. + set_reg_bit( &( base->cr ), HAL_LL_ADC_ADCAL_BIT ); + + // Wait for calibration. + while ( check_reg_bit( &( base->cr ), HAL_LL_ADC_ADCAL_BIT ) ); + + // Prescaler. + *reg &= HAL_LL_ADC_PRESCALER; + + // Clear ADRDY bit ADC_ISR by writting 1. + set_reg_bit( &( base->isr ), HAL_LL_ADC_ADRDY_BIT ); + + // Set delay for voltage regulator to be initialized correctly. + wait_loop_index = 10 * ( Get_Fosc_kHz() / 1000 ); + while( wait_loop_index != 0 ) + { + wait_loop_index--; + } + + // Enable ADC. + set_reg_bit( &( base->cr ), HAL_LL_ADC_ADEN_BIT ); + + // ADRDY bit. + while ( !( check_reg_bit( &( base->cr ), HAL_LL_ADC_ADRDY_BIT ) ) ); + + // Resolution. + base->cfgr &= HAL_LL_RESOLUTION_MASK; + base->cfgr |= resolution; + + // Data alignment. + clear_reg_bit( &( base->cfgr ), HAL_LL_ADC_ALIGN_BIT ); + + // Discontinuos mode disabled. + clear_reg_bit( &( base->cfgr ), HAL_LL_ADC_DISCEN_BIT ); + + // Continuos conversion mode. + clear_reg_bit( &( base->cfgr ), HAL_LL_ADC_CONT_BIT ); + + // Regular channel sequence length. + base->sqr1 &= HAL_LL_ADC_CONVERSION; +} + +static void hal_ll_adc_init( hal_ll_adc_hw_specifics_map_t *map ) { + + + hal_ll_gpio_analog_input( hal_ll_gpio_port_base( hal_ll_gpio_port_index( map->pin ) ), + hal_ll_gpio_pin_mask( map->pin ) ); + + _hal_ll_adc_enable_clock( map->module_index ); + + _hal_ll_adc_hw_init((hal_ll_adc_base_handle_t *)map->base, map->resolution); + +} + +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_161/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_161/CMakeLists.cmake new file mode 100644 index 000000000..22273204d --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_161/CMakeLists.cmake @@ -0,0 +1,10 @@ +if(${MCU_NAME} MATCHES "^STM32L4Q5AG$|^STM32L4Q5CG$|^STM32L4Q5QG$|^STM32L4Q5RG$|^STM32L4Q5VG$|^STM32L4Q5ZG$") + set(adc_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_adc.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_161") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_161") + list(APPEND hal_ll_def_list "STM32L4xx") + list(APPEND hal_ll_def_list "STM32L4Qxx") + list(APPEND hal_ll_def_list "STM32L4Q5xx") + set(adc_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/adc/hal_ll_adc_pin_map/implementations/doc_ds_161") + list(APPEND hal_ll_def_list "HAL_LL_ADC_RESOLUTION_CMAKE=HAL_LL_ADC_RESOLUTION_12_BIT") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_161/hal_ll_adc.c b/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_161/hal_ll_adc.c new file mode 100644 index 000000000..11d830aac --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_161/hal_ll_adc.c @@ -0,0 +1,634 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_adc.c + * @brief Low level HAL ADC source file. + */ + +#include "hal_ll_adc.h" +#include "hal_ll_gpio.h" +#include "hal_ll_adc_pin_map.h" + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_adc_get_module_state_address ((hal_ll_adc_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_adc_get_handle (hal_ll_adc_handle_register_t *)hal_ll_adc_get_module_state_address->hal_ll_adc_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_adc_get_base_struct(_handle) ((hal_ll_adc_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_adc_get_base_from_hal_handle ((hal_ll_adc_hw_specifics_map_t *)((hal_ll_adc_handle_register_t *)\ + (((hal_ll_adc_handle_register_t *)(handle))->hal_ll_adc_handle))->hal_ll_adc_handle)->base +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_adc_module_num(_module_num) (_module_num - 1) + +// ADC common registers. + +#define hal_ll_adc_module_num(_module_num) (_module_num - 1) + +#define HAL_LL_ADC_CSR_OFFSET ( 0x300 / 4 ) +#define HAL_LL_ADC_CCR_OFFSET ( 0x308 / 4 ) +#define HAL_LL_ADC_CDR_OFFSET ( 0x30C / 4 ) + + +#define HAL_LL_ADC_APB2ENR_SYSCFGEN 0 +#define HAL_LL_ADC_VREF_ENVR 0 +#define HAL_LL_ADC_ADRDYIE_BIT 0 +#define HAL_LL_ADC_ADEN_BIT 0 +#define HAL_LL_ADC_ADRDY_BIT 0 +#define HAL_LL_ADC_ADDIS_BIT 1 +#define HAL_LL_ADC_EOC_BIT 2 +#define HAL_LL_ADC_ADSTART_BIT 2 +#define HAL_LL_ADC_RESOLUTION_BIT0 3 +#define HAL_LL_ADC_RESOLUTION_BIT1 4 +#define HAL_LL_ADC_VREF_VRR 3 +#define HAL_LL_ADC_ALIGN_BIT 5 + +#define HAL_LL_ADC1_ENABLE_CLOCK 13 +#define HAL_LL_ADC2_ENABLE_CLOCK 13 + +#define HAL_LL_ADC_CONT_BIT 13 +#define HAL_LL_ADC_DISCEN_BIT 16 +#define HAL_LL_ADC_ADVREGEN_BIT 28 +#define HAL_LL_ADC_DEEPPWD_BIT 29 +#define HAL_LL_ADC_ADCALDIF_BIT 30 +#define HAL_LL_ADC_ADCAL_BIT 31 +#define HAL_LL_ADC_PIN_MASK 0xF + +#define HAL_LL_ADC_12BIT_RES 0x00000000ul +#define HAL_LL_ADC_10BIT_RES 0x00000008ul +#define HAL_LL_ADC_8BIT_RES 0x00000010ul +#define HAL_LL_ADC_6BIT_RES 0x00000018ul + +#define ADC_CAL_SINGLE 0x00000000ul +#define ADC_CAL_DIF 0x00000001ul +#define HAL_LL_ADC_CLK_SRC 0x30000000ul +#define HAL_LL_ADC_VOLTAGE 0xCFFFFFFFul +#define HAL_LL_ADC_CCR 0x50040308ul +#define HAL_LL_ADC_CKMODE_MASK 0x00000000ul +#define HAL_LL_ADC_VREFEN_MASK 0x00400000ul +#define HAL_LL_ADC_CCIPR 0x40021088ul +#define HAL_LL_ADC_PRESCALER 0xFFC3FFFFul +#define HAL_LL_ADC_CONVERSION 0xFFFFFFF0ul +#define HAL_LL_ADC_VREF_CSR 0x40010030ul +#define HAL_LL_ADC_CONVERSION_ONE 0x000007C0ul + +#define HAL_LL_MODULE_INDEX_ERROR 0xFFFFFFFFul + +#define HAL_LL_RESOLUTION_MASK 0xFFFFFFE7ul + +#define HAL_LL_ADC_DEFAULT_BASE_ADDRESS 0xFF + + +// -------------------------------------------------------------- PRIVATE TYPES +/*!< @brief Local handle list */ +static hal_ll_adc_handle_register_t hal_ll_module_state[ADC_MODULE_COUNT] = { (handle_t *) NULL, (handle_t *) NULL, false }; + +/** + * Return values + */ +typedef enum +{ + HAL_LL_ADC_SUCCESS = 0, + HAL_LL_ADC_WRONG_PIN, + + HAL_LL_ADC_UNSUPPORTED_RESOLUTION = 1100, + HAL_LL_ADC_UNSUPPORTED_VREF, + HAL_LL_ADC_WRONG_CHANNEL, + HAL_LL_ADC_ERROR = (-1) +} hal_ll_adc_err_t; + +/*!< @brief ADC register structure. */ +typedef struct +{ + uint32_t isr; /* ADC interrupt and status register (ADC_ISR) */ + uint32_t ier; /* ADC interrupt enable register (ADC_IER) */ + uint32_t cr; /* ADC control register (ADC_CR) */ + uint32_t cfgr; /* ADC configuration register (ADC_CFGR) */ + uint32_t cfgr2; /* ADC configuration register (ADC_CFGR) */ + uint32_t smpr1; /* ADC sample time register 1 (ADC_SMPR1) */ + uint32_t smpr2; /* ADC sample time register 1 (ADC_SMPR1) */ + uint32_t __unused1[1]; /* */ + uint32_t tr1; /* ADC watchdog threshold register 1 (ADC_TR1) */ + uint32_t tr2; /* ADC watchdog threshold register 1 (ADC_TR1) */ + uint32_t tr3; /* ADC watchdog threshold register 1 (ADC_TR1) */ + uint32_t __unused2[1]; /* */ + uint32_t sqr1; /* ADC regular sequence register 1 (ADC_SQR1) */ + uint32_t sqr2; /* ADC regular sequence register 1 (ADC_SQR1) */ + uint32_t sqr3; /* ADC regular sequence register 1 (ADC_SQR1) */ + uint32_t sqr4; /* ADC regular sequence register 1 (ADC_SQR1) */ + uint32_t dr; /* ADC regular data register (ADC_DR) */ + uint32_t __unused3[2]; /* */ + uint32_t jsqr; /* ADC injected sequence register (ADC_JSQR) */ + uint32_t __unused4[4]; /* */ + uint32_t ofr1; /* ADC offset y register (ADC_OFRy) */ + uint32_t ofr2; /* ADC offset y register (ADC_OFRy) */ + uint32_t ofr3; /* ADC offset y register (ADC_OFRy) */ + uint32_t ofr4; /* ADC offset y register (ADC_OFRy) */ + uint32_t __unused5[4]; /* */ + uint32_t jdr1; /* ADC injected channel y data register (ADC_JDRy) */ + uint32_t jdr2; /* ADC injected channel y data register (ADC_JDRy) */ + uint32_t jdr3; /* ADC injected channel y data register (ADC_JDRy) */ + uint32_t jdr4; /* ADC injected channel y data register (ADC_JDRy) */ + uint32_t __unused6[4]; /* */ + uint32_t awd2cr; /* ADC analog watchdog 2 configuration register (ADC_AWD2CR) */ + uint32_t awd3cr; /* ADC analog watchdog 2 configuration register (ADC_AWD2CR) */ + uint32_t __unused7[2]; /* */ + uint32_t difsel; /* ADC differential mode selection register (ADC_DIFSEL) */ + uint32_t calfact; /* ADC calibration factors (ADC_CALFACT) */ + uint32_t csr; /* ADC common status register (ADC_CSR) */ + uint32_t __unused8[1]; /* */ + uint32_t ccr; /* ADC common control register (ADC_CCR) */ + uint32_t cdr; /* ADC common regular data register for dual mode (ADC_CDR) */ + +} hal_ll_adc_base_handle_t; + +/*!< @brief ADC hw specific module values */ +typedef struct +{ + uint16_t pin_an[ADC_MODULE_COUNT]; +} hal_ll_adc_pin_id; + +static hal_ll_adc_hw_specifics_map_t hal_ll_adc_hw_specifics_map[] = +{ + #ifdef ADC_MODULE_1 + {ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF}, + #endif + #ifdef ADC_MODULE_2 + {ADC2_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF}, + #endif + + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF} +}; + +// ------------------------------------------------------------------ VARIABLES + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_adc_handle_register_t *low_level_handle; +static volatile hal_ll_adc_hw_specifics_map_t *hal_ll_adc_hw_specifics_map_local; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Enable ADC module 1 clock. + * @param none + * @return none + */ +static inline void adc1_enable_clock(); +/** + * @brief Enable ADC module 2 clock. + * @param none + * @return none + */ +static inline void adc2_enable_clock(); + + +/** + * @brief Initialize ADC module. + * @param *map - ADC module local map. + * @return None + */ +static void hal_ll_adc_init( hal_ll_adc_hw_specifics_map_t *map ); + +/** + * @brief Check if pins are adequate. + * + * Checks analog pin the user has passed with pre-defined + * pins in ADC pin map. + * + * @param[in] pin - ADC pre-defined pin name. + * @param[in] *index - ADC map index value. + * @return hal_ll_pin_name_t Module index based on pin. + * + * Returns pre-defined module index from pin maps, if pin + * is adequate. + */ +static hal_ll_pin_name_t hal_ll_adc_check_pins( hal_ll_pin_name_t pin, hal_ll_adc_pin_id *index, hal_ll_adc_handle_register_t *handle_map ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and channel values for ADC pin + * + * @param[in] module_index ADC HW module index -- 0,1,2... + * @param[in] *index ADC map index value + * + * @return None + */ +static void hal_ll_adc_map_pin( uint8_t module_index, hal_ll_adc_pin_id *index ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_adc_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_adc_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_adc_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Enable ADC module gate clock. + * @param base - ADC module base address. + * @return None + */ +static void _hal_ll_adc_enable_clock( uint8_t base ); + +/** + * @brief Initialize ADC module. + * @param *base - ADC module base address. + * @param resolution - ADC module resolution. + * @return None + */ +static void _hal_ll_adc_hw_init( hal_ll_adc_base_handle_t *base, uint32_t resolution ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_adc_register_handle(hal_ll_pin_name_t pin, hal_ll_adc_voltage_reference_t vref_input, hal_ll_adc_resolution_t resolution, hal_ll_adc_handle_register_t *handle_map, uint8_t *hal_module_id) +{ + uint16_t pin_check_result; + hal_ll_adc_pin_id index = {HAL_LL_PIN_NC}; + + if ( (pin_check_result = hal_ll_adc_check_pins( pin, &index, handle_map )) == HAL_LL_PIN_NC ) { + return HAL_LL_ADC_WRONG_PIN; + }; + + switch ( resolution ) + { + case HAL_LL_ADC_RESOLUTION_12_BIT: + hal_ll_adc_hw_specifics_map[pin_check_result].resolution = HAL_LL_ADC_12BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_10_BIT: + hal_ll_adc_hw_specifics_map[pin_check_result].resolution = HAL_LL_ADC_10BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_8_BIT: + hal_ll_adc_hw_specifics_map[pin_check_result].resolution = HAL_LL_ADC_8BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_6_BIT: + hal_ll_adc_hw_specifics_map[pin_check_result].resolution = HAL_LL_ADC_6BIT_RES; + break; + default: + return HAL_LL_ADC_UNSUPPORTED_RESOLUTION; + } + + switch ( vref_input ) + { + case HAL_LL_ADC_VREF_EXTERNAL: + break; + + default: + return HAL_LL_ADC_UNSUPPORTED_VREF; + } + + if ( hal_ll_adc_hw_specifics_map[pin_check_result].pin != pin ) + { + hal_ll_adc_map_pin( pin_check_result, &index ); + + handle_map[pin_check_result].init_ll_state = false; + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[pin_check_result].hal_ll_adc_handle = (handle_t *)&hal_ll_adc_hw_specifics_map[pin_check_result].base; + + handle_map[pin_check_result].hal_ll_adc_handle = (handle_t *)&hal_ll_module_state[pin_check_result].hal_ll_adc_handle; + + return HAL_LL_ADC_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_adc( handle_t *handle ) +{ + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + hal_ll_adc_handle_register_t *hal_handle = (hal_ll_adc_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_adc_hw_specifics_map_local->module_index; + + hal_ll_adc_init( hal_ll_adc_hw_specifics_map_local ); + + hal_ll_module_state[pin_check_result].hal_ll_adc_handle = (handle_t *)&hal_ll_adc_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_ADC_SUCCESS; +} + +hal_ll_err_t hal_ll_adc_set_resolution(handle_t *handle, hal_ll_adc_resolution_t resolution) +{ + low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + + low_level_handle->init_ll_state = false; + + switch( resolution ) { + case HAL_LL_ADC_RESOLUTION_12_BIT: + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_12BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_10_BIT: + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_10BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_8_BIT: + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_8BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_6_BIT: + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_6BIT_RES; + break; + + default: + return HAL_LL_ADC_UNSUPPORTED_RESOLUTION; + } + + hal_ll_adc_init( hal_ll_adc_hw_specifics_map_local ); + + low_level_handle->init_ll_state = true; + + return HAL_LL_ADC_SUCCESS; +} + +hal_ll_err_t hal_ll_adc_set_vref_input(handle_t *handle, hal_ll_adc_voltage_reference_t vref_input) +{ + low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + + low_level_handle->init_ll_state = false; + + switch( vref_input ) { + case HAL_LL_ADC_VREF_EXTERNAL: + break; + + default: + return HAL_LL_ADC_UNSUPPORTED_VREF; + } + + hal_ll_adc_init( hal_ll_adc_hw_specifics_map_local ); + + low_level_handle->init_ll_state = true; + + return HAL_LL_ADC_SUCCESS; +} + +void hal_ll_adc_set_vref_value(handle_t *handle, float vref_value) +{ + low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + + hal_ll_adc_hw_specifics_map_local->vref_value = vref_value; +} + +hal_ll_err_t hal_ll_adc_read( handle_t *handle, uint16_t *readDatabuf ) +{ + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_base_handle_t *base = ( hal_ll_adc_base_handle_t * )hal_ll_adc_hw_specifics_map_local->base ; + + while( ( check_reg_bit( &( base->cr ), HAL_LL_ADC_ADSTART_BIT ) ) ); + base->sqr1 &= ~HAL_LL_ADC_CONVERSION_ONE; + base->sqr1 |= ( ( hal_ll_adc_hw_specifics_map_local->channel << 6 ) ); + + Delay_1us(); + + // Start the conversion. + set_reg_bit( &( base->cr ), HAL_LL_ADC_ADSTART_BIT ); + + while ( !( check_reg_bit( &( base->isr ), HAL_LL_ADC_EOC_BIT ) ) ); + // Conversion result from SS3. + *readDatabuf = base->dr; + + return HAL_LL_ADC_SUCCESS; +} + +void hal_ll_adc_close( handle_t *handle ) +{ + hal_ll_adc_hw_specifics_map_t *hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + low_level_handle = hal_ll_adc_get_handle; + + if( hal_ll_adc_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + + hal_ll_adc_hw_specifics_map_local->vref_input = HAL_LL_ADC_VREF_DEFAULT; + hal_ll_adc_hw_specifics_map_local->vref_value = 0; + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_RESOLUTION_12_BIT; + + low_level_handle->hal_ll_adc_handle = NULL; + low_level_handle->hal_drv_adc_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_adc_hw_specifics_map_local->pin = HAL_LL_PIN_NC; + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static hal_ll_pin_name_t hal_ll_adc_check_pins( hal_ll_pin_name_t pin, hal_ll_adc_pin_id *index, hal_ll_adc_handle_register_t *handle_map ) +{ + static const uint16_t adc_map_size = ( sizeof( _adc_map ) / sizeof( hal_ll_adc_pin_map_t ) ); + uint16_t pin_index = 0; + uint8_t index_counter = 0; + uint8_t hal_ll_module_id = 0; + + if ( HAL_LL_PIN_NC == pin ) { + return HAL_LL_PIN_NC; + } + + for ( pin_index = 0; pin_index < adc_map_size; pin_index++ ) + { + if ( pin == _adc_map[pin_index].pin ) + { + // Get module number + hal_ll_module_id = _adc_map[pin_index].module_index; + // Map pin name + index->pin_an[hal_ll_module_id] = pin_index; + + // Check if module is taken + if ( NULL == handle_map[ hal_ll_module_id ].hal_drv_adc_handle ) { + return hal_ll_module_id; + } else if ( ADC_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static void hal_ll_adc_map_pin( uint8_t module_index, hal_ll_adc_pin_id *index ) { + // Map new pins + hal_ll_adc_hw_specifics_map[module_index].pin = _adc_map[ index->pin_an[module_index] ].pin; + hal_ll_adc_hw_specifics_map[module_index].channel = _adc_map[ index->pin_an[module_index] ].channel; +} + +static hal_ll_adc_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof(hal_ll_adc_handle_register_t)); + static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof(hal_ll_adc_handle_register_t)); + + while( hal_ll_module_count-- ) { + if (hal_ll_adc_get_base_from_hal_handle == hal_ll_adc_hw_specifics_map[hal_ll_module_count].base) { + return &hal_ll_adc_hw_specifics_map[hal_ll_module_count]; + } + } + + return &hal_ll_adc_hw_specifics_map[hal_ll_module_error]; +} +static inline void adc1_enable_clock() +{ + set_reg_bit( _RCC_AHB2ENR, HAL_LL_ADC1_ENABLE_CLOCK ); +} +static inline void adc2_enable_clock() +{ + set_reg_bit( _RCC_AHB2ENR, HAL_LL_ADC2_ENABLE_CLOCK ); +} + +static void _hal_ll_adc_enable_clock( uint8_t base ) +{ + switch ( base ) + { + #ifdef ADC_MODULE_1 + case ( hal_ll_adc_module_num(ADC_MODULE_1) ): + adc1_enable_clock(); + break; + #endif + #ifdef ADC_MODULE_2 + case ( hal_ll_adc_module_num(ADC_MODULE_2) ): + adc2_enable_clock(); + break; + #endif + } +} +static void _hal_ll_adc_hw_init( hal_ll_adc_base_handle_t *base, uint32_t resolution ) +{ + static uint32_t wait_loop_index = 0; + static uint32_t *reg; + reg = HAL_LL_ADC_CCIPR; + + // Select ADC clock source. + *reg |= HAL_LL_ADC_CLK_SRC; + + // Exit from deep power down mode. + if ( check_reg_bit( &( base->cr ), HAL_LL_ADC_DEEPPWD_BIT ) ) + { + clear_reg_bit( &( base->cr ), HAL_LL_ADC_DEEPPWD_BIT ); + } + + // Enable voltage regulator. + base->cr &= HAL_LL_ADC_VOLTAGE; + + if ( !( check_reg_bit( &( base->cr ), HAL_LL_ADC_ADVREGEN_BIT ) ) ) + { + set_reg_bit( &( base->cr ), HAL_LL_ADC_ADVREGEN_BIT ); + } + + // Enable ADC interrupts. + set_reg_bit( &( base->ier ), HAL_LL_ADC_ADRDYIE_BIT ); + + // Disable ADC + if ( check_reg_bit( &( base->cr ), HAL_LL_ADC_ADEN_BIT ) ) + { + set_reg_bit( &( base->cr ), HAL_LL_ADC_ADDIS_BIT ); + } + + // Voltage reference enable, ckmode SYSCLK. + reg = HAL_LL_ADC_CCR; + *reg |= (HAL_LL_ADC_CKMODE_MASK | HAL_LL_ADC_VREFEN_MASK); + + // Select calibration mode. + clear_reg_bit( &( base->cr ), HAL_LL_ADC_ADCALDIF_BIT ); + + // Start ADC calibration. + set_reg_bit( &( base->cr ), HAL_LL_ADC_ADCAL_BIT ); + + // Wait for calibration. + while ( check_reg_bit( &( base->cr ), HAL_LL_ADC_ADCAL_BIT ) ); + + // Prescaler. + *reg &= HAL_LL_ADC_PRESCALER; + + // Clear ADRDY bit ADC_ISR by writting 1. + set_reg_bit( &( base->isr ), HAL_LL_ADC_ADRDY_BIT ); + + // Set delay for voltage regulator to be initialized correctly. + wait_loop_index = 10 * ( Get_Fosc_kHz() / 1000 ); + while( wait_loop_index != 0 ) + { + wait_loop_index--; + } + + // Enable ADC. + set_reg_bit( &( base->cr ), HAL_LL_ADC_ADEN_BIT ); + + // ADRDY bit. + while ( !( check_reg_bit( &( base->cr ), HAL_LL_ADC_ADRDY_BIT ) ) ); + + // Resolution. + base->cfgr &= HAL_LL_RESOLUTION_MASK; + base->cfgr |= resolution; + + // Data alignment. + clear_reg_bit( &( base->cfgr ), HAL_LL_ADC_ALIGN_BIT ); + + // Discontinuos mode disabled. + clear_reg_bit( &( base->cfgr ), HAL_LL_ADC_DISCEN_BIT ); + + // Continuos conversion mode. + clear_reg_bit( &( base->cfgr ), HAL_LL_ADC_CONT_BIT ); + + // Regular channel sequence length. + base->sqr1 &= HAL_LL_ADC_CONVERSION; +} + +static void hal_ll_adc_init( hal_ll_adc_hw_specifics_map_t *map ) { + + + hal_ll_gpio_analog_input( hal_ll_gpio_port_base( hal_ll_gpio_port_index( map->pin ) ), + hal_ll_gpio_pin_mask( map->pin ) ); + + _hal_ll_adc_enable_clock( map->module_index ); + + _hal_ll_adc_hw_init((hal_ll_adc_base_handle_t *)map->base, map->resolution); + +} + + +// ------------------------------------------------------------------------- END + + + + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_2/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_2/CMakeLists.cmake new file mode 100644 index 000000000..afe07c38a --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_2/CMakeLists.cmake @@ -0,0 +1,10 @@ +if(${MCU_NAME} MATCHES "^STM32C031C4$|^STM32C031F4$|^STM32C031G4$|^STM32C031K4$|^STM32C031C6$|^STM32C031F6$|^STM32C031G6$|^STM32C031K6$") + set(adc_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_adc.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_2") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_2") + list(APPEND hal_ll_def_list "STM32C0xx") + list(APPEND hal_ll_def_list "STM32C03xx") + list(APPEND hal_ll_def_list "STM32C031xx") + set(adc_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/adc/hal_ll_adc_pin_map/implementations/doc_ds_2") + list(APPEND hal_ll_def_list "HAL_LL_ADC_RESOLUTION_CMAKE=HAL_LL_ADC_RESOLUTION_12_BIT") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_2/hal_ll_adc.c b/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_2/hal_ll_adc.c new file mode 100644 index 000000000..6d1349d70 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_2/hal_ll_adc.c @@ -0,0 +1,547 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_adc.c + * @brief Low level HAL ADC source file. + */ + +#include "hal_ll_adc.h" +#include "hal_ll_gpio.h" +#include "hal_ll_adc_pin_map.h" +#include "mcu.h" + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_adc_get_module_state_address ((hal_ll_adc_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_adc_get_handle (hal_ll_adc_handle_register_t *)hal_ll_adc_get_module_state_address->hal_ll_adc_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_adc_get_base_struct(_handle) ((hal_ll_adc_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_adc_get_base_from_hal_handle ((hal_ll_adc_hw_specifics_map_t *)((hal_ll_adc_handle_register_t *)\ + (((hal_ll_adc_handle_register_t *)(handle))->hal_ll_adc_handle))->hal_ll_adc_handle)->base +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_adc_module_num(_module_num) (_module_num - 1) + +#define HAL_LL_ADC_ISR_OFFSET ( 0x0 / 4 ) +#define HAL_LL_ADC_IER_OFFSET ( 0x4 / 4 ) +#define HAL_LL_ADC_CR_OFFSET ( 0x8 / 4 ) +#define HAL_LL_ADC_CFGR1_OFFSET ( 0xC / 4 ) +#define HAL_LL_ADC_CFGR2_OFFSET ( 0x10 / 4 ) +#define HAL_LL_ADC_SMPR_OFFSET ( 0x14 / 4 ) + +#define HAL_LL_ADC_CHSELR_OFFSET ( 0x28 / 4 ) +#define HAL_LL_ADC_DR_OFFSET ( 0x40 / 4 ) +#define HAL_LL_ADC_CCR_OFFSET ( 0x308 / 4 ) + +#define HAL_LL_ADC_ADEN_BIT 0 +#define HAL_LL_ADC_ADRDY_BIT 0 +#define HAL_LL_ADC_ADDIS_BIT 1 +#define HAL_LL_ADC_ADSTART_BIT 2 +#define HAL_LL_ADC_EOC_BIT 2 +#define HAL_LL_ADC_SCANDIR_BIT 2 +#define HAL_LL_ADC_ADSTP_BIT 4 +#define HAL_LL_ADC_ALIGN_BIT 5 +#define HAL_LL_ADC_CONT_BIT 13 +#define HAL_LL_ADC_ADCAL_BIT 31 +#define HAL_LL_ADC_ADVREGEN_BIT 28 + +#define HAL_LL_ADC1_ENABLE_CLOCK 20 + +#define HAL_LL_ADC_CKMODE0_BIT 30 +#define HAL_LL_ADC_CKMODE1_BIT 31 +#define HAL_LL_ADC_8MHZ 8000000ul +#define HAL_LL_ADC_16MHZ 16000000ul + +#define HAL_LL_ADC_12BIT_RES 0x00000000ul +#define HAL_LL_ADC_10BIT_RES 0x00000008ul +#define HAL_LL_ADC_8BIT_RES 0x00000010ul +#define HAL_LL_ADC_6BIT_RES 0x00000018ul + +#define HAL_LL_ADC_SMPR 0xFFFFFFF8ul +#define HAL_LL_ADC_EXTEN 0xFFFFF3FFul +#define HAL_LL_ADC_CR_WAIT 0x80000017ul + +#define HAL_LL_ADC_RESOLUTION_MASK 0xFFFFFFE7ul + +#define HAL_LL_MODULE_INDEX_ERROR 0xFFFFFFFFul + +// -------------------------------------------------------------- PRIVATE TYPES +/*!< @brief Local handle list */ +static hal_ll_adc_handle_register_t hal_ll_module_state[ADC_MODULE_COUNT] = { (handle_t *) NULL, (handle_t *) NULL, false }; + +/*!< Abbreviations used in source. */ +typedef uint32_t hal_ll_adc_base_handle_t; + +/*!< @brief ADC hw specific module values */ +typedef struct +{ + uint16_t pin_an[ADC_MODULE_COUNT]; +} hal_ll_adc_pin_id; + +/** + * Return values + */ +typedef enum +{ + HAL_LL_ADC_SUCCESS = 0, + HAL_LL_ADC_WRONG_PIN, + + HAL_LL_ADC_UNSUPPORTED_RESOLUTION = 1100, + HAL_LL_ADC_UNSUPPORTED_VREF, + HAL_LL_ADC_WRONG_CHANNEL, + HAL_LL_ADC_ERROR = (-1) +} hal_ll_adc_err_t; + +static hal_ll_adc_hw_specifics_map_t hal_ll_adc_hw_specifics_map[] = +{ + #ifdef ADC_MODULE_1 + {ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF}, + #endif + + + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF} +}; + +// ------------------------------------------------------------------ VARIABLES + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_adc_handle_register_t *low_level_handle; +static volatile hal_ll_adc_hw_specifics_map_t *hal_ll_adc_hw_specifics_map_local; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS + +/** + * @brief Enable ADC module 1 clock. + * @param none + * @return none + */ +static inline void adc1_enable_clock(); + +/** + * @brief Initialize ADC module. + * @param *map - ADC module local map. + * @return None + */ +static void hal_ll_adc_init( hal_ll_adc_hw_specifics_map_t *map ); + +/** + * @brief Check if pins are adequate. + * + * Checks analog pin the user has passed with pre-defined + * pins in ADC pin map. + * + * @param[in] pin - ADC pre-defined pin name. + * @param[in] *index - ADC map index value. + * @return hal_ll_pin_name_t Module index based on pin. + * + * Returns pre-defined module index from pin maps, if pin + * is adequate. + */ +static hal_ll_pin_name_t hal_ll_adc_check_pins( hal_ll_pin_name_t pin, hal_ll_adc_pin_id *index, hal_ll_adc_handle_register_t *handle_map ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_adc_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_adc_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_adc_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and channel values for ADC pin + * + * @param[in] module_index ADC HW module index -- 0,1,2... + * @param[in] *index ADC map index value + * + * @return None + */ +static void hal_ll_adc_map_pin( uint8_t module_index, hal_ll_adc_pin_id *index ); + +/** + * @brief Enable ADC module gate clock. + * @param base - ADC module base address. + * @return None + */ +static void _hal_ll_adc_enable_clock( uint8_t base ); + +/** + * @brief Initialize ADC module. + * @param *base - ADC module base address. + * @param resolution - ADC module resolution. + * @return None + */ +static void _hal_ll_adc_hw_init( hal_ll_adc_base_handle_t *base, uint32_t resolution ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_adc_register_handle(hal_ll_pin_name_t pin, hal_ll_adc_voltage_reference_t vref_input, hal_ll_adc_resolution_t resolution, hal_ll_adc_handle_register_t *handle_map, uint8_t *hal_module_id) +{ + uint16_t pin_check_result; + hal_ll_adc_pin_id index = {HAL_LL_PIN_NC}; + + if ( (pin_check_result = hal_ll_adc_check_pins( pin, &index, handle_map )) == HAL_LL_PIN_NC ) { + return HAL_LL_ADC_WRONG_PIN; + }; + + switch ( resolution ) + { + case HAL_LL_ADC_RESOLUTION_12_BIT: + hal_ll_adc_hw_specifics_map[pin_check_result].resolution = HAL_LL_ADC_12BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_10_BIT: + hal_ll_adc_hw_specifics_map[pin_check_result].resolution = HAL_LL_ADC_10BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_8_BIT: + hal_ll_adc_hw_specifics_map[pin_check_result].resolution = HAL_LL_ADC_8BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_6_BIT: + hal_ll_adc_hw_specifics_map[pin_check_result].resolution = HAL_LL_ADC_6BIT_RES; + break; + + default: + return HAL_LL_ADC_UNSUPPORTED_RESOLUTION; + } + + switch ( vref_input ) + { + case HAL_LL_ADC_VREF_EXTERNAL: + break; + + default: + return HAL_LL_ADC_UNSUPPORTED_VREF; + } + + if ( hal_ll_adc_hw_specifics_map[pin_check_result].pin != pin ) + { + hal_ll_adc_map_pin( pin_check_result, &index ); + + handle_map[pin_check_result].init_ll_state = false; + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[pin_check_result].hal_ll_adc_handle = (handle_t *)&hal_ll_adc_hw_specifics_map[pin_check_result].base; + + handle_map[pin_check_result].hal_ll_adc_handle = (handle_t *)&hal_ll_module_state[pin_check_result].hal_ll_adc_handle; + + return HAL_LL_ADC_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_adc( handle_t *handle ) +{ + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + hal_ll_adc_handle_register_t *hal_handle = (hal_ll_adc_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_adc_hw_specifics_map_local->module_index; + + hal_ll_adc_init( hal_ll_adc_hw_specifics_map_local ); + + hal_ll_module_state[pin_check_result].hal_ll_adc_handle = (handle_t *)&hal_ll_adc_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_ADC_SUCCESS; +} + +hal_ll_err_t hal_ll_adc_set_resolution(handle_t *handle, hal_ll_adc_resolution_t resolution) +{ + low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + + low_level_handle->init_ll_state = false; + + switch( resolution ) { + case HAL_LL_ADC_RESOLUTION_12_BIT: + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_12BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_10_BIT: + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_10BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_8_BIT: + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_8BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_6_BIT: + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_6BIT_RES; + break; + + default: + return HAL_LL_ADC_UNSUPPORTED_RESOLUTION; + } + + hal_ll_adc_init( hal_ll_adc_hw_specifics_map_local ); + + low_level_handle->init_ll_state = true; + + return HAL_LL_ADC_SUCCESS; +} + +hal_ll_err_t hal_ll_adc_set_vref_input(handle_t *handle, hal_ll_adc_voltage_reference_t vref_input) +{ + low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + + low_level_handle->init_ll_state = false; + + switch( vref_input ) { + case HAL_LL_ADC_VREF_EXTERNAL: + break; + + default: + return HAL_LL_ADC_UNSUPPORTED_RESOLUTION; + } + + hal_ll_adc_init( hal_ll_adc_hw_specifics_map_local ); + + low_level_handle->init_ll_state = true; + + return HAL_LL_ADC_SUCCESS; +} + +void hal_ll_adc_set_vref_value(handle_t *handle, float vref_value) +{ + low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + + hal_ll_adc_hw_specifics_map_local->vref_value = vref_value; +} + +hal_ll_err_t hal_ll_adc_read( handle_t *handle, uint16_t *readDatabuf ) +{ + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_base_handle_t *base = ( hal_ll_adc_base_handle_t * )hal_ll_adc_hw_specifics_map_local->base ; + + *(base + HAL_LL_ADC_CHSELR_OFFSET) = 1ul << hal_ll_adc_hw_specifics_map_local->channel; + set_reg_bit( ( base + HAL_LL_ADC_CR_OFFSET ), HAL_LL_ADC_ADSTART_BIT ); + + Delay_1us(); + while( !(check_reg_bit( ( base + HAL_LL_ADC_ISR_OFFSET ), HAL_LL_ADC_EOC_BIT ) ) ); + + *readDatabuf = ( *(base + HAL_LL_ADC_DR_OFFSET) ); + + return HAL_LL_ADC_SUCCESS; +} + +void hal_ll_adc_close( handle_t *handle ) +{ + hal_ll_adc_hw_specifics_map_t *hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + low_level_handle = hal_ll_adc_get_handle; + + if( hal_ll_adc_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + + hal_ll_adc_hw_specifics_map_local->vref_input = HAL_LL_ADC_VREF_DEFAULT; + hal_ll_adc_hw_specifics_map_local->vref_value = 0; + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_RESOLUTION_12_BIT; + + low_level_handle->hal_ll_adc_handle = NULL; + low_level_handle->hal_drv_adc_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_adc_hw_specifics_map_local->pin = HAL_LL_PIN_NC; + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static hal_ll_pin_name_t hal_ll_adc_check_pins( hal_ll_pin_name_t pin, hal_ll_adc_pin_id *index, hal_ll_adc_handle_register_t *handle_map ) +{ + static const uint16_t adc_map_size = ( sizeof( _adc_map ) / sizeof( hal_ll_adc_pin_map_t ) ); + uint16_t pin_index = 0; + uint8_t index_counter = 0; + uint8_t hal_ll_module_id = 0; + + if ( HAL_LL_PIN_NC == pin ) { + return HAL_LL_PIN_NC; + } + + for ( pin_index = 0; pin_index < adc_map_size; pin_index++ ) + { + if ( pin == _adc_map[pin_index].pin ) + { + // Get module number + hal_ll_module_id = _adc_map[pin_index].module_index; + // Map pin name + index->pin_an[hal_ll_module_id] = pin_index; + + // Check if module is taken + if ( NULL == handle_map[ hal_ll_module_id ].hal_drv_adc_handle ) { + return hal_ll_module_id; + } else if ( ADC_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static void hal_ll_adc_map_pin( uint8_t module_index, hal_ll_adc_pin_id *index ) { + // Map new pins + hal_ll_adc_hw_specifics_map[module_index].pin = _adc_map[ index->pin_an[module_index] ].pin; + hal_ll_adc_hw_specifics_map[module_index].channel = _adc_map[ index->pin_an[module_index] ].channel; +} + +static hal_ll_adc_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof(hal_ll_adc_handle_register_t)); + static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof(hal_ll_adc_handle_register_t)); + + while( hal_ll_module_count-- ) { + if (hal_ll_adc_get_base_from_hal_handle == hal_ll_adc_hw_specifics_map[hal_ll_module_count].base) { + return &hal_ll_adc_hw_specifics_map[hal_ll_module_count]; + } + } + + return &hal_ll_adc_hw_specifics_map[hal_ll_module_error]; +} + + +static inline void adc1_enable_clock() +{ + set_reg_bit( _RCC_APBENR2, HAL_LL_ADC1_ENABLE_CLOCK ); +} +static void _hal_ll_adc_enable_clock( uint8_t base ) +{ + switch ( base ) + { + #ifdef ADC_MODULE_1 + case ( hal_ll_adc_module_num(ADC_MODULE_1) ): + adc1_enable_clock(); + break; + #endif + + } +} + +static void _hal_ll_adc_hw_init( hal_ll_adc_base_handle_t *base, uint32_t resolution ) +{ + rcc_clocks_t rcc_clocks; + static uint32_t *reg; + /* ADC clock + The ADC features two clock schemes: + Clock for the analog circuitry: ADCCLK, common to all ADCs + This clock is generated from the APB2 clock divided by a programmable prescaler that + allows the ADC to work at fPCLK2/2, /4, /6 or /8. ADCCLK maximum value is 30 MHz + when the APB2 clock is at 60 MHz. */ + RCC_GetClocksFrequency( &rcc_clocks ); + + // Turn off ADC module. + if ( check_reg_bit( ( base + HAL_LL_ADC_CR_OFFSET ), HAL_LL_ADC_ADEN_BIT ) ) + { + while( check_reg_bit( ( base + HAL_LL_ADC_CR_OFFSET ), HAL_LL_ADC_ADSTART_BIT ) ); + set_reg_bit( ( base + HAL_LL_ADC_CR_OFFSET ), HAL_LL_ADC_ADDIS_BIT ); + while( check_reg_bit( ( base + HAL_LL_ADC_CR_OFFSET ), HAL_LL_ADC_ADDIS_BIT )); + } + + if ( rcc_clocks.pclk < HAL_LL_ADC_8MHZ ) // Set clock and prescaler. + { + // If less than 8MHz, prescaler is set to 1 (read caution on pg. 252 in the reference manual). + set_reg_bit( ( base + HAL_LL_ADC_CFGR2_OFFSET ), HAL_LL_ADC_CKMODE0_BIT ); + set_reg_bit( ( base + HAL_LL_ADC_CFGR2_OFFSET ), HAL_LL_ADC_CKMODE1_BIT ); + } + else if ( rcc_clocks.pclk < HAL_LL_ADC_16MHZ ) // Set clock and prescaler. + { + // Above 8 Mhz, prescaler is set to 2. + set_reg_bit( ( base + HAL_LL_ADC_CFGR2_OFFSET ), HAL_LL_ADC_CKMODE0_BIT ); + clear_reg_bit( ( base + HAL_LL_ADC_CFGR2_OFFSET ), HAL_LL_ADC_CKMODE1_BIT ); + }else + { + // Above 16 Mhz, prescaler is set to 4. + clear_reg_bit( ( base + HAL_LL_ADC_CFGR2_OFFSET ), HAL_LL_ADC_CKMODE0_BIT ); + set_reg_bit( ( base + HAL_LL_ADC_CFGR2_OFFSET ), HAL_LL_ADC_CKMODE1_BIT ); + } + + // Wait for ADEN to go down. + while( check_reg_bit( ( base + HAL_LL_ADC_CR_OFFSET ), HAL_LL_ADC_ADEN_BIT ) ); + + // Start calibration. + set_reg_bit( ( base + HAL_LL_ADC_CR_OFFSET ), HAL_LL_ADC_ADVREGEN_BIT ); + Delay_us(30); + set_reg_bit( ( base + HAL_LL_ADC_CR_OFFSET ), HAL_LL_ADC_ADCAL_BIT ); + while( check_reg_bit( ( base + HAL_LL_ADC_CR_OFFSET ), HAL_LL_ADC_ADCAL_BIT ) ); + + // Set sampling time - 1.5 ADC clock. + *( base + HAL_LL_ADC_SMPR_OFFSET ) &= HAL_LL_ADC_SMPR; + + // Set resolution. + reg = ( base + HAL_LL_ADC_CFGR1_OFFSET ); + *reg &= HAL_LL_ADC_RESOLUTION_MASK; + *reg |= resolution; + + // Wait for hardware to clear ADC_CR register. + while( ( *( base + HAL_LL_ADC_CR_OFFSET ) & HAL_LL_ADC_CR_WAIT ) != 0 ); + + // Scan sequence upward. + clear_reg_bit( ( base + HAL_LL_ADC_CFGR1_OFFSET ), HAL_LL_ADC_SCANDIR_BIT ); + + // Data alignment - right. + clear_reg_bit( ( base + HAL_LL_ADC_CFGR1_OFFSET ), HAL_LL_ADC_ALIGN_BIT ); + + // Single conversion mode. + clear_reg_bit( ( base + HAL_LL_ADC_CFGR1_OFFSET ), HAL_LL_ADC_CONT_BIT ); + + // External trigger disable. + *( base + HAL_LL_ADC_CFGR1_OFFSET ) &= HAL_LL_ADC_EXTEN; + + // Turn on ADC module. + set_reg_bit( ( base + HAL_LL_ADC_CR_OFFSET ), HAL_LL_ADC_ADEN_BIT ); + while( !( check_reg_bit( ( base + HAL_LL_ADC_ISR_OFFSET ), HAL_LL_ADC_ADRDY_BIT ) ) ); +} + +static void hal_ll_adc_init( hal_ll_adc_hw_specifics_map_t *map ) { + + hal_ll_gpio_analog_input( hal_ll_gpio_port_base( hal_ll_gpio_port_index( map->pin ) ), + hal_ll_gpio_pin_mask( map->pin ) ); + + _hal_ll_adc_enable_clock( map->module_index ); + + _hal_ll_adc_hw_init((hal_ll_adc_base_handle_t *)map->base, map->resolution); + +} +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_74/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_74/CMakeLists.cmake new file mode 100644 index 000000000..c9065cb56 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_74/CMakeLists.cmake @@ -0,0 +1,10 @@ +if(${MCU_NAME} MATCHES "^STM32G051C6$|^STM32G051F6$|^STM32G051G6$|^STM32G051K6$|^STM32G051C8$|^STM32G051F8$|^STM32G051G8$|^STM32G051K8$") + set(adc_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_adc.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_74") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_74") + list(APPEND hal_ll_def_list "STM32G0xx") + list(APPEND hal_ll_def_list "STM32G05xx") + list(APPEND hal_ll_def_list "STM32G051xx") + set(adc_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/adc/hal_ll_adc_pin_map/implementations/doc_ds_74") + list(APPEND hal_ll_def_list "HAL_LL_ADC_RESOLUTION_CMAKE=HAL_LL_ADC_RESOLUTION_12_BIT") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_74/hal_ll_adc.c b/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_74/hal_ll_adc.c new file mode 100644 index 000000000..2eadb29aa --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_74/hal_ll_adc.c @@ -0,0 +1,592 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_adc.c + * @brief Low level HAL ADC source file. + */ + +#include "hal_ll_adc.h" +#include "hal_ll_gpio.h" +#include "hal_ll_adc_pin_map.h" +#include "mcu.h" + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_adc_get_module_state_address ((hal_ll_adc_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_adc_get_handle (hal_ll_adc_handle_register_t *)hal_ll_adc_get_module_state_address->hal_ll_adc_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_adc_get_base_struct(_handle) ((hal_ll_adc_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_adc_get_base_from_hal_handle ((hal_ll_adc_hw_specifics_map_t *)((hal_ll_adc_handle_register_t *)\ + (((hal_ll_adc_handle_register_t *)(handle))->hal_ll_adc_handle))->hal_ll_adc_handle)->base +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_adc_module_num(_module_num) (_module_num - 1) + +#define HAL_LL_ADC_ISR_OFFSET ( 0x0 / 4 ) +#define HAL_LL_ADC_IER_OFFSET ( 0x4 / 4 ) +#define HAL_LL_ADC_CR_OFFSET ( 0x8 / 4 ) +#define HAL_LL_ADC_CFGR1_OFFSET ( 0xC / 4 ) +#define HAL_LL_ADC_CFGR2_OFFSET ( 0x10 / 4 ) +#define HAL_LL_ADC_SMPR_OFFSET ( 0x14 / 4 ) + +#define HAL_LL_ADC_CHSELR_OFFSET ( 0x28 / 4 ) +#define HAL_LL_ADC_DR_OFFSET ( 0x40 / 4 ) +#define HAL_LL_ADC_CCR_OFFSET ( 0x308 / 4 ) + +#define HAL_LL_ADC_ADEN_BIT 0 +#define HAL_LL_ADC_ADRDY_BIT 0 +#define HAL_LL_ADC_ADDIS_BIT 1 +#define HAL_LL_ADC_ADSTART_BIT 2 +#define HAL_LL_ADC_EOC_BIT 2 +#define HAL_LL_ADC_SCANDIR_BIT 2 +#define HAL_LL_ADC_ADSTP_BIT 4 +#define HAL_LL_ADC_ALIGN_BIT 5 +#define HAL_LL_ADC_CONT_BIT 13 +#define HAL_LL_ADC_ADCAL_BIT 31 +#define HAL_LL_ADC_ADVREGEN_BIT 28 + +#define HAL_LL_ADC1_ENABLE_CLOCK 20 + +#define HAL_LL_ADC_CKMODE0_BIT 30 +#define HAL_LL_ADC_CKMODE1_BIT 31 +#define HAL_LL_ADC_CCIPR 30 + +#define HAL_LL_ADC_2M8HZ 2800000ul +#define HAL_LL_ADC_8MHZ 8000000ul +#define HAL_LL_ADC_16MHZ 16000000ul + + +#define HAL_LL_ADC_12BIT_RES 0x00000000ul +#define HAL_LL_ADC_10BIT_RES 0x00000008ul +#define HAL_LL_ADC_8BIT_RES 0x00000010ul +#define HAL_LL_ADC_6BIT_RES 0x00000018ul + +#define HAL_LL_ADC_SMPR 0xFFFFFFF8ul +#define HAL_LL_ADC_EXTEN 0xFFFFF3FFul +#define HAL_LL_ADC_CR_WAIT 0x80000017ul + +#define HAL_LL_ADC_RESOLUTION_MASK 0xFFFFFFE7ul + +#define HAL_LL_MODULE_INDEX_ERROR 0xFFFFFFFFul + +// -------------------------------------------------------------- PRIVATE TYPES +/*!< @brief Local handle list */ +static hal_ll_adc_handle_register_t hal_ll_module_state[ADC_MODULE_COUNT] = { (handle_t *) NULL, (handle_t *) NULL, false }; + +/*!< Abbreviations used in source. */ +typedef uint32_t hal_ll_adc_base_handle_t; + +/*!< @brief ADC hw specific module values */ +typedef struct +{ + uint16_t pin_an[ADC_MODULE_COUNT]; +} hal_ll_adc_pin_id; + +/** + * Return values + */ +typedef enum +{ + HAL_LL_ADC_SUCCESS = 0, + HAL_LL_ADC_WRONG_PIN, + + HAL_LL_ADC_UNSUPPORTED_RESOLUTION = 1100, + HAL_LL_ADC_UNSUPPORTED_VREF, + HAL_LL_ADC_WRONG_CHANNEL, + HAL_LL_ADC_ERROR = (-1) +} hal_ll_adc_err_t; + +static hal_ll_adc_hw_specifics_map_t hal_ll_adc_hw_specifics_map[] = +{ + #ifdef ADC_MODULE_1 + {ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF}, + #endif + + + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF} +}; + +// ------------------------------------------------------------------ VARIABLES + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_adc_handle_register_t *low_level_handle; +static volatile hal_ll_adc_hw_specifics_map_t *hal_ll_adc_hw_specifics_map_local; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS + +/** + * @brief Enable ADC module 1 clock. + * @param none + * @return none + */ +static inline void adc1_enable_clock(); + +/** + * @brief Initialize ADC module. + * @param *map - ADC module local map. + * @return None + */ +static void hal_ll_adc_init( hal_ll_adc_hw_specifics_map_t *map ); + +/** + * @brief Check if pins are adequate. + * + * Checks analog pin the user has passed with pre-defined + * pins in ADC pin map. + * + * @param[in] pin - ADC pre-defined pin name. + * @param[in] *index - ADC map index value. + * @return hal_ll_pin_name_t Module index based on pin. + * + * Returns pre-defined module index from pin maps, if pin + * is adequate. + */ +static hal_ll_pin_name_t hal_ll_adc_check_pins( hal_ll_pin_name_t pin, hal_ll_adc_pin_id *index, hal_ll_adc_handle_register_t *handle_map ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_adc_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_adc_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_adc_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and channel values for ADC pin + * + * @param[in] module_index ADC HW module index -- 0,1,2... + * @param[in] *index ADC map index value + * + * @return None + */ +static void hal_ll_adc_map_pin( uint8_t module_index, hal_ll_adc_pin_id *index ); + +/** + * @brief Enable ADC module gate clock. + * @param base - ADC module base address. + * @return None + */ +static void _hal_ll_adc_enable_clock( uint8_t base ); + +/** + * @brief Initialize ADC module. + * @param *base - ADC module base address. + * @param resolution - ADC module resolution. + * @return None + */ +static void _hal_ll_adc_hw_init( hal_ll_adc_base_handle_t *base, uint32_t resolution ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_adc_register_handle(hal_ll_pin_name_t pin, hal_ll_adc_voltage_reference_t vref_input, hal_ll_adc_resolution_t resolution, hal_ll_adc_handle_register_t *handle_map, uint8_t *hal_module_id) +{ + uint16_t pin_check_result; + hal_ll_adc_pin_id index = {HAL_LL_PIN_NC}; + + if ( (pin_check_result = hal_ll_adc_check_pins( pin, &index, handle_map )) == HAL_LL_PIN_NC ) { + return HAL_LL_ADC_WRONG_PIN; + }; + + switch ( resolution ) + { + case HAL_LL_ADC_RESOLUTION_12_BIT: + hal_ll_adc_hw_specifics_map[pin_check_result].resolution = HAL_LL_ADC_12BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_10_BIT: + hal_ll_adc_hw_specifics_map[pin_check_result].resolution = HAL_LL_ADC_10BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_8_BIT: + hal_ll_adc_hw_specifics_map[pin_check_result].resolution = HAL_LL_ADC_8BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_6_BIT: + hal_ll_adc_hw_specifics_map[pin_check_result].resolution = HAL_LL_ADC_6BIT_RES; + break; + + default: + return HAL_LL_ADC_UNSUPPORTED_RESOLUTION; + } + + switch ( vref_input ) + { + case HAL_LL_ADC_VREF_EXTERNAL: + break; + + default: + return HAL_LL_ADC_UNSUPPORTED_VREF; + } + + if ( hal_ll_adc_hw_specifics_map[pin_check_result].pin != pin ) + { + hal_ll_adc_map_pin( pin_check_result, &index ); + + handle_map[pin_check_result].init_ll_state = false; + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[pin_check_result].hal_ll_adc_handle = (handle_t *)&hal_ll_adc_hw_specifics_map[pin_check_result].base; + + handle_map[pin_check_result].hal_ll_adc_handle = (handle_t *)&hal_ll_module_state[pin_check_result].hal_ll_adc_handle; + + return HAL_LL_ADC_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_adc( handle_t *handle ) +{ + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + hal_ll_adc_handle_register_t *hal_handle = (hal_ll_adc_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_adc_hw_specifics_map_local->module_index; + + hal_ll_adc_init( hal_ll_adc_hw_specifics_map_local ); + + hal_ll_module_state[pin_check_result].hal_ll_adc_handle = (handle_t *)&hal_ll_adc_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_ADC_SUCCESS; +} + +hal_ll_err_t hal_ll_adc_set_resolution(handle_t *handle, hal_ll_adc_resolution_t resolution) +{ + low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + + low_level_handle->init_ll_state = false; + + switch( resolution ) { + case HAL_LL_ADC_RESOLUTION_12_BIT: + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_12BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_10_BIT: + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_10BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_8_BIT: + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_8BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_6_BIT: + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_6BIT_RES; + break; + + default: + return HAL_LL_ADC_UNSUPPORTED_RESOLUTION; + } + + hal_ll_adc_init( hal_ll_adc_hw_specifics_map_local ); + + low_level_handle->init_ll_state = true; + + return HAL_LL_ADC_SUCCESS; +} + +hal_ll_err_t hal_ll_adc_set_vref_input(handle_t *handle, hal_ll_adc_voltage_reference_t vref_input) +{ + low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + + low_level_handle->init_ll_state = false; + + switch( vref_input ) { + case HAL_LL_ADC_VREF_EXTERNAL: + break; + + default: + return HAL_LL_ADC_UNSUPPORTED_RESOLUTION; + } + + hal_ll_adc_init( hal_ll_adc_hw_specifics_map_local ); + + low_level_handle->init_ll_state = true; + + return HAL_LL_ADC_SUCCESS; +} + +void hal_ll_adc_set_vref_value(handle_t *handle, float vref_value) +{ + low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + + hal_ll_adc_hw_specifics_map_local->vref_value = vref_value; +} + +hal_ll_err_t hal_ll_adc_read( handle_t *handle, uint16_t *readDatabuf ) +{ + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_base_handle_t *base = ( hal_ll_adc_base_handle_t * )hal_ll_adc_hw_specifics_map_local->base ; + + *(base + HAL_LL_ADC_CHSELR_OFFSET) = 1ul << hal_ll_adc_hw_specifics_map_local->channel; + set_reg_bit( ( base + HAL_LL_ADC_CR_OFFSET ), HAL_LL_ADC_ADSTART_BIT ); + + Delay_1us(); + while( !(check_reg_bit( ( base + HAL_LL_ADC_ISR_OFFSET ), HAL_LL_ADC_EOC_BIT ) ) ); + + *readDatabuf = ( *(base + HAL_LL_ADC_DR_OFFSET) ); + + return HAL_LL_ADC_SUCCESS; +} + +void hal_ll_adc_close( handle_t *handle ) +{ + hal_ll_adc_hw_specifics_map_t *hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + low_level_handle = hal_ll_adc_get_handle; + + if( hal_ll_adc_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + + hal_ll_adc_hw_specifics_map_local->vref_input = HAL_LL_ADC_VREF_DEFAULT; + hal_ll_adc_hw_specifics_map_local->vref_value = 0; + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_RESOLUTION_12_BIT; + + low_level_handle->hal_ll_adc_handle = NULL; + low_level_handle->hal_drv_adc_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_adc_hw_specifics_map_local->pin = HAL_LL_PIN_NC; + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static hal_ll_pin_name_t hal_ll_adc_check_pins( hal_ll_pin_name_t pin, hal_ll_adc_pin_id *index, hal_ll_adc_handle_register_t *handle_map ) +{ + static const uint16_t adc_map_size = ( sizeof( _adc_map ) / sizeof( hal_ll_adc_pin_map_t ) ); + uint16_t pin_index = 0; + uint8_t index_counter = 0; + uint8_t hal_ll_module_id = 0; + + if ( HAL_LL_PIN_NC == pin ) { + return HAL_LL_PIN_NC; + } + + for ( pin_index = 0; pin_index < adc_map_size; pin_index++ ) + { + if ( pin == _adc_map[pin_index].pin ) + { + // Get module number + hal_ll_module_id = _adc_map[pin_index].module_index; + // Map pin name + index->pin_an[hal_ll_module_id] = pin_index; + + // Check if module is taken + if ( NULL == handle_map[ hal_ll_module_id ].hal_drv_adc_handle ) { + return hal_ll_module_id; + } else if ( ADC_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static void hal_ll_adc_map_pin( uint8_t module_index, hal_ll_adc_pin_id *index ) { + // Map new pins + hal_ll_adc_hw_specifics_map[module_index].pin = _adc_map[ index->pin_an[module_index] ].pin; + hal_ll_adc_hw_specifics_map[module_index].channel = _adc_map[ index->pin_an[module_index] ].channel; +} + +static hal_ll_adc_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof(hal_ll_adc_handle_register_t)); + static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof(hal_ll_adc_handle_register_t)); + + while( hal_ll_module_count-- ) { + if (hal_ll_adc_get_base_from_hal_handle == hal_ll_adc_hw_specifics_map[hal_ll_module_count].base) { + return &hal_ll_adc_hw_specifics_map[hal_ll_module_count]; + } + } + + return &hal_ll_adc_hw_specifics_map[hal_ll_module_error]; +} + +static void adc_clock_mode( uint32_t clock_value, hal_ll_adc_base_handle_t *base ) +{ + if (clock_value < HAL_LL_ADC_8MHZ) // Set clock and prescaler. + { + // If less than 8MHz, prescaler is set to 1 (read caution on pg. 252 in the reference manual). + set_reg_bit( ( base + HAL_LL_ADC_CFGR2_OFFSET ), HAL_LL_ADC_CKMODE0_BIT ); + set_reg_bit( ( base + HAL_LL_ADC_CFGR2_OFFSET ), HAL_LL_ADC_CKMODE1_BIT ); + } + else if ( clock_value < HAL_LL_ADC_16MHZ ) + { + // Above 8 Mhz, prescaler is set to 2. + set_reg_bit( ( base + HAL_LL_ADC_CFGR2_OFFSET ), HAL_LL_ADC_CKMODE0_BIT ); + clear_reg_bit( ( base + HAL_LL_ADC_CFGR2_OFFSET ), HAL_LL_ADC_CKMODE1_BIT ); + } + else + { + // Above 16 Mhz, prescaler is set to 4. + clear_reg_bit( ( base + HAL_LL_ADC_CFGR2_OFFSET ), HAL_LL_ADC_CKMODE0_BIT ); + set_reg_bit( ( base + HAL_LL_ADC_CFGR2_OFFSET ), HAL_LL_ADC_CKMODE1_BIT ); + } +} + + +static inline void adc1_enable_clock() +{ + set_reg_bit( _RCC_APBENR2, HAL_LL_ADC1_ENABLE_CLOCK ); +} +static void _hal_ll_adc_enable_clock( uint8_t base ) +{ + switch ( base ) + { + #ifdef ADC_MODULE_1 + case ( hal_ll_adc_module_num(ADC_MODULE_1) ): + adc1_enable_clock(); + break; + #endif + + } +} + +static void _hal_ll_adc_hw_init( hal_ll_adc_base_handle_t *base, uint32_t resolution ) +{ + rcc_clocks_t rcc_clocks; + static uint32_t *reg; + static uint32_t temp_reg; + static uint32_t adc_clk; + + /* ADC clock + The ADC features two clock schemes: + Clock for the analog circuitry: ADCCLK, common to all ADCs + This clock is generated from the APB2 clock divided by a programmable prescaler that + allows the ADC to work at fPCLK2/2, /4, /6 or /8. ADCCLK maximum value is 30 MHz + when the APB2 clock is at 60 MHz. */ + RCC_GetClocksFrequency( &rcc_clocks ); + +// Turn off ADC module. + if ( check_reg_bit( ( base + HAL_LL_ADC_CR_OFFSET ), HAL_LL_ADC_ADEN_BIT ) ) + { + while( check_reg_bit( ( base + HAL_LL_ADC_CR_OFFSET ), HAL_LL_ADC_ADSTART_BIT ) ); + set_reg_bit( ( base + HAL_LL_ADC_CR_OFFSET ), HAL_LL_ADC_ADDIS_BIT ); + while( check_reg_bit( ( base + HAL_LL_ADC_CR_OFFSET ), HAL_LL_ADC_ADDIS_BIT )); + } + + + if ( check_reg_bit( ( base + HAL_LL_ADC_CR_OFFSET ), HAL_LL_ADC_ADDIS_BIT ) ) + { + set_reg_bit( ( base + HAL_LL_ADC_CR_OFFSET ), HAL_LL_ADC_ADSTP_BIT ); + } + + + // Select the correct ADC clock source. + temp_reg = _RCC_CCIPR; + temp_reg >>= HAL_LL_ADC_CCIPR; + + switch ( temp_reg ) + { + // If system clock selected as source. + case 0 : + adc_clk = rcc_clocks.sysclk; + break; + // If nothing of the above use PCLK as default clock. + default: + adc_clk = rcc_clocks.pclk; + break; + } + + adc_clock_mode( adc_clk, base ); + + + + // Wait for ADEN to go down. + while( check_reg_bit( ( base + HAL_LL_ADC_CR_OFFSET ), HAL_LL_ADC_ADEN_BIT ) ); + + // Start calibration. + set_reg_bit( ( base + HAL_LL_ADC_CR_OFFSET ), HAL_LL_ADC_ADVREGEN_BIT ); + Delay_us(30); + set_reg_bit( ( base + HAL_LL_ADC_CR_OFFSET ), HAL_LL_ADC_ADCAL_BIT ); + while( check_reg_bit( ( base + HAL_LL_ADC_CR_OFFSET ), HAL_LL_ADC_ADCAL_BIT ) ); + + + + // Set sampling time - 1.5 ADC clock. + *( base + HAL_LL_ADC_SMPR_OFFSET ) &= HAL_LL_ADC_SMPR; + + // Set resolution. + reg = ( base + HAL_LL_ADC_CFGR1_OFFSET ); + *reg &= HAL_LL_ADC_RESOLUTION_MASK; + *reg |= resolution; + + // Wait for hardware to clear ADC_CR register. + while( ( *( base + HAL_LL_ADC_CR_OFFSET ) & HAL_LL_ADC_CR_WAIT ) != 0 ); + + // Scan sequence upward. +// *( base + HAL_LL_ADC_CFGR1_OFFSET ) &= 0xFFFFFFFF; + clear_reg_bit( ( base + HAL_LL_ADC_CFGR1_OFFSET ), HAL_LL_ADC_SCANDIR_BIT ); + + // Data alignment - right. + clear_reg_bit( ( base + HAL_LL_ADC_CFGR1_OFFSET ), HAL_LL_ADC_ALIGN_BIT ); + + // Single conversion mode. + clear_reg_bit( ( base + HAL_LL_ADC_CFGR1_OFFSET ), HAL_LL_ADC_CONT_BIT ); + + // External trigger disable. + *( base + HAL_LL_ADC_CFGR1_OFFSET ) &= HAL_LL_ADC_EXTEN; + + // Turn on ADC module. + set_reg_bit( ( base + HAL_LL_ADC_CR_OFFSET ), HAL_LL_ADC_ADEN_BIT ); + while( !( check_reg_bit( ( base + HAL_LL_ADC_ISR_OFFSET ), HAL_LL_ADC_ADRDY_BIT ) ) ); +} + +static void hal_ll_adc_init( hal_ll_adc_hw_specifics_map_t *map ) { + + hal_ll_gpio_analog_input( hal_ll_gpio_port_base( hal_ll_gpio_port_index( map->pin ) ), + hal_ll_gpio_pin_mask( map->pin ) ); + + _hal_ll_adc_enable_clock( map->module_index ); + + _hal_ll_adc_hw_init((hal_ll_adc_base_handle_t *)map->base, map->resolution); + +} +// ------------------------------------------------------------------------- END + + + + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_75/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_75/CMakeLists.cmake new file mode 100644 index 000000000..59913d165 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_75/CMakeLists.cmake @@ -0,0 +1,10 @@ +if(${MCU_NAME} MATCHES "^STM32G061C6$|^STM32G061F6$|^STM32G061G6$|^STM32G061K6$|^STM32G061C8$|^STM32G061F8$|^STM32G061G8$|^STM32G061K8$") + set(adc_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_adc.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_75") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_75") + list(APPEND hal_ll_def_list "STM32G0xx") + list(APPEND hal_ll_def_list "STM32G06xx") + list(APPEND hal_ll_def_list "STM32G061xx") + set(adc_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/adc/hal_ll_adc_pin_map/implementations/doc_ds_75") + list(APPEND hal_ll_def_list "HAL_LL_ADC_RESOLUTION_CMAKE=HAL_LL_ADC_RESOLUTION_12_BIT") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_75/hal_ll_adc.c b/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_75/hal_ll_adc.c new file mode 100644 index 000000000..2eadb29aa --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_75/hal_ll_adc.c @@ -0,0 +1,592 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_adc.c + * @brief Low level HAL ADC source file. + */ + +#include "hal_ll_adc.h" +#include "hal_ll_gpio.h" +#include "hal_ll_adc_pin_map.h" +#include "mcu.h" + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_adc_get_module_state_address ((hal_ll_adc_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_adc_get_handle (hal_ll_adc_handle_register_t *)hal_ll_adc_get_module_state_address->hal_ll_adc_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_adc_get_base_struct(_handle) ((hal_ll_adc_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_adc_get_base_from_hal_handle ((hal_ll_adc_hw_specifics_map_t *)((hal_ll_adc_handle_register_t *)\ + (((hal_ll_adc_handle_register_t *)(handle))->hal_ll_adc_handle))->hal_ll_adc_handle)->base +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_adc_module_num(_module_num) (_module_num - 1) + +#define HAL_LL_ADC_ISR_OFFSET ( 0x0 / 4 ) +#define HAL_LL_ADC_IER_OFFSET ( 0x4 / 4 ) +#define HAL_LL_ADC_CR_OFFSET ( 0x8 / 4 ) +#define HAL_LL_ADC_CFGR1_OFFSET ( 0xC / 4 ) +#define HAL_LL_ADC_CFGR2_OFFSET ( 0x10 / 4 ) +#define HAL_LL_ADC_SMPR_OFFSET ( 0x14 / 4 ) + +#define HAL_LL_ADC_CHSELR_OFFSET ( 0x28 / 4 ) +#define HAL_LL_ADC_DR_OFFSET ( 0x40 / 4 ) +#define HAL_LL_ADC_CCR_OFFSET ( 0x308 / 4 ) + +#define HAL_LL_ADC_ADEN_BIT 0 +#define HAL_LL_ADC_ADRDY_BIT 0 +#define HAL_LL_ADC_ADDIS_BIT 1 +#define HAL_LL_ADC_ADSTART_BIT 2 +#define HAL_LL_ADC_EOC_BIT 2 +#define HAL_LL_ADC_SCANDIR_BIT 2 +#define HAL_LL_ADC_ADSTP_BIT 4 +#define HAL_LL_ADC_ALIGN_BIT 5 +#define HAL_LL_ADC_CONT_BIT 13 +#define HAL_LL_ADC_ADCAL_BIT 31 +#define HAL_LL_ADC_ADVREGEN_BIT 28 + +#define HAL_LL_ADC1_ENABLE_CLOCK 20 + +#define HAL_LL_ADC_CKMODE0_BIT 30 +#define HAL_LL_ADC_CKMODE1_BIT 31 +#define HAL_LL_ADC_CCIPR 30 + +#define HAL_LL_ADC_2M8HZ 2800000ul +#define HAL_LL_ADC_8MHZ 8000000ul +#define HAL_LL_ADC_16MHZ 16000000ul + + +#define HAL_LL_ADC_12BIT_RES 0x00000000ul +#define HAL_LL_ADC_10BIT_RES 0x00000008ul +#define HAL_LL_ADC_8BIT_RES 0x00000010ul +#define HAL_LL_ADC_6BIT_RES 0x00000018ul + +#define HAL_LL_ADC_SMPR 0xFFFFFFF8ul +#define HAL_LL_ADC_EXTEN 0xFFFFF3FFul +#define HAL_LL_ADC_CR_WAIT 0x80000017ul + +#define HAL_LL_ADC_RESOLUTION_MASK 0xFFFFFFE7ul + +#define HAL_LL_MODULE_INDEX_ERROR 0xFFFFFFFFul + +// -------------------------------------------------------------- PRIVATE TYPES +/*!< @brief Local handle list */ +static hal_ll_adc_handle_register_t hal_ll_module_state[ADC_MODULE_COUNT] = { (handle_t *) NULL, (handle_t *) NULL, false }; + +/*!< Abbreviations used in source. */ +typedef uint32_t hal_ll_adc_base_handle_t; + +/*!< @brief ADC hw specific module values */ +typedef struct +{ + uint16_t pin_an[ADC_MODULE_COUNT]; +} hal_ll_adc_pin_id; + +/** + * Return values + */ +typedef enum +{ + HAL_LL_ADC_SUCCESS = 0, + HAL_LL_ADC_WRONG_PIN, + + HAL_LL_ADC_UNSUPPORTED_RESOLUTION = 1100, + HAL_LL_ADC_UNSUPPORTED_VREF, + HAL_LL_ADC_WRONG_CHANNEL, + HAL_LL_ADC_ERROR = (-1) +} hal_ll_adc_err_t; + +static hal_ll_adc_hw_specifics_map_t hal_ll_adc_hw_specifics_map[] = +{ + #ifdef ADC_MODULE_1 + {ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF}, + #endif + + + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF} +}; + +// ------------------------------------------------------------------ VARIABLES + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_adc_handle_register_t *low_level_handle; +static volatile hal_ll_adc_hw_specifics_map_t *hal_ll_adc_hw_specifics_map_local; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS + +/** + * @brief Enable ADC module 1 clock. + * @param none + * @return none + */ +static inline void adc1_enable_clock(); + +/** + * @brief Initialize ADC module. + * @param *map - ADC module local map. + * @return None + */ +static void hal_ll_adc_init( hal_ll_adc_hw_specifics_map_t *map ); + +/** + * @brief Check if pins are adequate. + * + * Checks analog pin the user has passed with pre-defined + * pins in ADC pin map. + * + * @param[in] pin - ADC pre-defined pin name. + * @param[in] *index - ADC map index value. + * @return hal_ll_pin_name_t Module index based on pin. + * + * Returns pre-defined module index from pin maps, if pin + * is adequate. + */ +static hal_ll_pin_name_t hal_ll_adc_check_pins( hal_ll_pin_name_t pin, hal_ll_adc_pin_id *index, hal_ll_adc_handle_register_t *handle_map ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_adc_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_adc_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_adc_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and channel values for ADC pin + * + * @param[in] module_index ADC HW module index -- 0,1,2... + * @param[in] *index ADC map index value + * + * @return None + */ +static void hal_ll_adc_map_pin( uint8_t module_index, hal_ll_adc_pin_id *index ); + +/** + * @brief Enable ADC module gate clock. + * @param base - ADC module base address. + * @return None + */ +static void _hal_ll_adc_enable_clock( uint8_t base ); + +/** + * @brief Initialize ADC module. + * @param *base - ADC module base address. + * @param resolution - ADC module resolution. + * @return None + */ +static void _hal_ll_adc_hw_init( hal_ll_adc_base_handle_t *base, uint32_t resolution ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_adc_register_handle(hal_ll_pin_name_t pin, hal_ll_adc_voltage_reference_t vref_input, hal_ll_adc_resolution_t resolution, hal_ll_adc_handle_register_t *handle_map, uint8_t *hal_module_id) +{ + uint16_t pin_check_result; + hal_ll_adc_pin_id index = {HAL_LL_PIN_NC}; + + if ( (pin_check_result = hal_ll_adc_check_pins( pin, &index, handle_map )) == HAL_LL_PIN_NC ) { + return HAL_LL_ADC_WRONG_PIN; + }; + + switch ( resolution ) + { + case HAL_LL_ADC_RESOLUTION_12_BIT: + hal_ll_adc_hw_specifics_map[pin_check_result].resolution = HAL_LL_ADC_12BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_10_BIT: + hal_ll_adc_hw_specifics_map[pin_check_result].resolution = HAL_LL_ADC_10BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_8_BIT: + hal_ll_adc_hw_specifics_map[pin_check_result].resolution = HAL_LL_ADC_8BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_6_BIT: + hal_ll_adc_hw_specifics_map[pin_check_result].resolution = HAL_LL_ADC_6BIT_RES; + break; + + default: + return HAL_LL_ADC_UNSUPPORTED_RESOLUTION; + } + + switch ( vref_input ) + { + case HAL_LL_ADC_VREF_EXTERNAL: + break; + + default: + return HAL_LL_ADC_UNSUPPORTED_VREF; + } + + if ( hal_ll_adc_hw_specifics_map[pin_check_result].pin != pin ) + { + hal_ll_adc_map_pin( pin_check_result, &index ); + + handle_map[pin_check_result].init_ll_state = false; + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[pin_check_result].hal_ll_adc_handle = (handle_t *)&hal_ll_adc_hw_specifics_map[pin_check_result].base; + + handle_map[pin_check_result].hal_ll_adc_handle = (handle_t *)&hal_ll_module_state[pin_check_result].hal_ll_adc_handle; + + return HAL_LL_ADC_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_adc( handle_t *handle ) +{ + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + hal_ll_adc_handle_register_t *hal_handle = (hal_ll_adc_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_adc_hw_specifics_map_local->module_index; + + hal_ll_adc_init( hal_ll_adc_hw_specifics_map_local ); + + hal_ll_module_state[pin_check_result].hal_ll_adc_handle = (handle_t *)&hal_ll_adc_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_ADC_SUCCESS; +} + +hal_ll_err_t hal_ll_adc_set_resolution(handle_t *handle, hal_ll_adc_resolution_t resolution) +{ + low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + + low_level_handle->init_ll_state = false; + + switch( resolution ) { + case HAL_LL_ADC_RESOLUTION_12_BIT: + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_12BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_10_BIT: + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_10BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_8_BIT: + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_8BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_6_BIT: + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_6BIT_RES; + break; + + default: + return HAL_LL_ADC_UNSUPPORTED_RESOLUTION; + } + + hal_ll_adc_init( hal_ll_adc_hw_specifics_map_local ); + + low_level_handle->init_ll_state = true; + + return HAL_LL_ADC_SUCCESS; +} + +hal_ll_err_t hal_ll_adc_set_vref_input(handle_t *handle, hal_ll_adc_voltage_reference_t vref_input) +{ + low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + + low_level_handle->init_ll_state = false; + + switch( vref_input ) { + case HAL_LL_ADC_VREF_EXTERNAL: + break; + + default: + return HAL_LL_ADC_UNSUPPORTED_RESOLUTION; + } + + hal_ll_adc_init( hal_ll_adc_hw_specifics_map_local ); + + low_level_handle->init_ll_state = true; + + return HAL_LL_ADC_SUCCESS; +} + +void hal_ll_adc_set_vref_value(handle_t *handle, float vref_value) +{ + low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + + hal_ll_adc_hw_specifics_map_local->vref_value = vref_value; +} + +hal_ll_err_t hal_ll_adc_read( handle_t *handle, uint16_t *readDatabuf ) +{ + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_base_handle_t *base = ( hal_ll_adc_base_handle_t * )hal_ll_adc_hw_specifics_map_local->base ; + + *(base + HAL_LL_ADC_CHSELR_OFFSET) = 1ul << hal_ll_adc_hw_specifics_map_local->channel; + set_reg_bit( ( base + HAL_LL_ADC_CR_OFFSET ), HAL_LL_ADC_ADSTART_BIT ); + + Delay_1us(); + while( !(check_reg_bit( ( base + HAL_LL_ADC_ISR_OFFSET ), HAL_LL_ADC_EOC_BIT ) ) ); + + *readDatabuf = ( *(base + HAL_LL_ADC_DR_OFFSET) ); + + return HAL_LL_ADC_SUCCESS; +} + +void hal_ll_adc_close( handle_t *handle ) +{ + hal_ll_adc_hw_specifics_map_t *hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + low_level_handle = hal_ll_adc_get_handle; + + if( hal_ll_adc_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + + hal_ll_adc_hw_specifics_map_local->vref_input = HAL_LL_ADC_VREF_DEFAULT; + hal_ll_adc_hw_specifics_map_local->vref_value = 0; + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_RESOLUTION_12_BIT; + + low_level_handle->hal_ll_adc_handle = NULL; + low_level_handle->hal_drv_adc_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_adc_hw_specifics_map_local->pin = HAL_LL_PIN_NC; + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static hal_ll_pin_name_t hal_ll_adc_check_pins( hal_ll_pin_name_t pin, hal_ll_adc_pin_id *index, hal_ll_adc_handle_register_t *handle_map ) +{ + static const uint16_t adc_map_size = ( sizeof( _adc_map ) / sizeof( hal_ll_adc_pin_map_t ) ); + uint16_t pin_index = 0; + uint8_t index_counter = 0; + uint8_t hal_ll_module_id = 0; + + if ( HAL_LL_PIN_NC == pin ) { + return HAL_LL_PIN_NC; + } + + for ( pin_index = 0; pin_index < adc_map_size; pin_index++ ) + { + if ( pin == _adc_map[pin_index].pin ) + { + // Get module number + hal_ll_module_id = _adc_map[pin_index].module_index; + // Map pin name + index->pin_an[hal_ll_module_id] = pin_index; + + // Check if module is taken + if ( NULL == handle_map[ hal_ll_module_id ].hal_drv_adc_handle ) { + return hal_ll_module_id; + } else if ( ADC_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static void hal_ll_adc_map_pin( uint8_t module_index, hal_ll_adc_pin_id *index ) { + // Map new pins + hal_ll_adc_hw_specifics_map[module_index].pin = _adc_map[ index->pin_an[module_index] ].pin; + hal_ll_adc_hw_specifics_map[module_index].channel = _adc_map[ index->pin_an[module_index] ].channel; +} + +static hal_ll_adc_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof(hal_ll_adc_handle_register_t)); + static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof(hal_ll_adc_handle_register_t)); + + while( hal_ll_module_count-- ) { + if (hal_ll_adc_get_base_from_hal_handle == hal_ll_adc_hw_specifics_map[hal_ll_module_count].base) { + return &hal_ll_adc_hw_specifics_map[hal_ll_module_count]; + } + } + + return &hal_ll_adc_hw_specifics_map[hal_ll_module_error]; +} + +static void adc_clock_mode( uint32_t clock_value, hal_ll_adc_base_handle_t *base ) +{ + if (clock_value < HAL_LL_ADC_8MHZ) // Set clock and prescaler. + { + // If less than 8MHz, prescaler is set to 1 (read caution on pg. 252 in the reference manual). + set_reg_bit( ( base + HAL_LL_ADC_CFGR2_OFFSET ), HAL_LL_ADC_CKMODE0_BIT ); + set_reg_bit( ( base + HAL_LL_ADC_CFGR2_OFFSET ), HAL_LL_ADC_CKMODE1_BIT ); + } + else if ( clock_value < HAL_LL_ADC_16MHZ ) + { + // Above 8 Mhz, prescaler is set to 2. + set_reg_bit( ( base + HAL_LL_ADC_CFGR2_OFFSET ), HAL_LL_ADC_CKMODE0_BIT ); + clear_reg_bit( ( base + HAL_LL_ADC_CFGR2_OFFSET ), HAL_LL_ADC_CKMODE1_BIT ); + } + else + { + // Above 16 Mhz, prescaler is set to 4. + clear_reg_bit( ( base + HAL_LL_ADC_CFGR2_OFFSET ), HAL_LL_ADC_CKMODE0_BIT ); + set_reg_bit( ( base + HAL_LL_ADC_CFGR2_OFFSET ), HAL_LL_ADC_CKMODE1_BIT ); + } +} + + +static inline void adc1_enable_clock() +{ + set_reg_bit( _RCC_APBENR2, HAL_LL_ADC1_ENABLE_CLOCK ); +} +static void _hal_ll_adc_enable_clock( uint8_t base ) +{ + switch ( base ) + { + #ifdef ADC_MODULE_1 + case ( hal_ll_adc_module_num(ADC_MODULE_1) ): + adc1_enable_clock(); + break; + #endif + + } +} + +static void _hal_ll_adc_hw_init( hal_ll_adc_base_handle_t *base, uint32_t resolution ) +{ + rcc_clocks_t rcc_clocks; + static uint32_t *reg; + static uint32_t temp_reg; + static uint32_t adc_clk; + + /* ADC clock + The ADC features two clock schemes: + Clock for the analog circuitry: ADCCLK, common to all ADCs + This clock is generated from the APB2 clock divided by a programmable prescaler that + allows the ADC to work at fPCLK2/2, /4, /6 or /8. ADCCLK maximum value is 30 MHz + when the APB2 clock is at 60 MHz. */ + RCC_GetClocksFrequency( &rcc_clocks ); + +// Turn off ADC module. + if ( check_reg_bit( ( base + HAL_LL_ADC_CR_OFFSET ), HAL_LL_ADC_ADEN_BIT ) ) + { + while( check_reg_bit( ( base + HAL_LL_ADC_CR_OFFSET ), HAL_LL_ADC_ADSTART_BIT ) ); + set_reg_bit( ( base + HAL_LL_ADC_CR_OFFSET ), HAL_LL_ADC_ADDIS_BIT ); + while( check_reg_bit( ( base + HAL_LL_ADC_CR_OFFSET ), HAL_LL_ADC_ADDIS_BIT )); + } + + + if ( check_reg_bit( ( base + HAL_LL_ADC_CR_OFFSET ), HAL_LL_ADC_ADDIS_BIT ) ) + { + set_reg_bit( ( base + HAL_LL_ADC_CR_OFFSET ), HAL_LL_ADC_ADSTP_BIT ); + } + + + // Select the correct ADC clock source. + temp_reg = _RCC_CCIPR; + temp_reg >>= HAL_LL_ADC_CCIPR; + + switch ( temp_reg ) + { + // If system clock selected as source. + case 0 : + adc_clk = rcc_clocks.sysclk; + break; + // If nothing of the above use PCLK as default clock. + default: + adc_clk = rcc_clocks.pclk; + break; + } + + adc_clock_mode( adc_clk, base ); + + + + // Wait for ADEN to go down. + while( check_reg_bit( ( base + HAL_LL_ADC_CR_OFFSET ), HAL_LL_ADC_ADEN_BIT ) ); + + // Start calibration. + set_reg_bit( ( base + HAL_LL_ADC_CR_OFFSET ), HAL_LL_ADC_ADVREGEN_BIT ); + Delay_us(30); + set_reg_bit( ( base + HAL_LL_ADC_CR_OFFSET ), HAL_LL_ADC_ADCAL_BIT ); + while( check_reg_bit( ( base + HAL_LL_ADC_CR_OFFSET ), HAL_LL_ADC_ADCAL_BIT ) ); + + + + // Set sampling time - 1.5 ADC clock. + *( base + HAL_LL_ADC_SMPR_OFFSET ) &= HAL_LL_ADC_SMPR; + + // Set resolution. + reg = ( base + HAL_LL_ADC_CFGR1_OFFSET ); + *reg &= HAL_LL_ADC_RESOLUTION_MASK; + *reg |= resolution; + + // Wait for hardware to clear ADC_CR register. + while( ( *( base + HAL_LL_ADC_CR_OFFSET ) & HAL_LL_ADC_CR_WAIT ) != 0 ); + + // Scan sequence upward. +// *( base + HAL_LL_ADC_CFGR1_OFFSET ) &= 0xFFFFFFFF; + clear_reg_bit( ( base + HAL_LL_ADC_CFGR1_OFFSET ), HAL_LL_ADC_SCANDIR_BIT ); + + // Data alignment - right. + clear_reg_bit( ( base + HAL_LL_ADC_CFGR1_OFFSET ), HAL_LL_ADC_ALIGN_BIT ); + + // Single conversion mode. + clear_reg_bit( ( base + HAL_LL_ADC_CFGR1_OFFSET ), HAL_LL_ADC_CONT_BIT ); + + // External trigger disable. + *( base + HAL_LL_ADC_CFGR1_OFFSET ) &= HAL_LL_ADC_EXTEN; + + // Turn on ADC module. + set_reg_bit( ( base + HAL_LL_ADC_CR_OFFSET ), HAL_LL_ADC_ADEN_BIT ); + while( !( check_reg_bit( ( base + HAL_LL_ADC_ISR_OFFSET ), HAL_LL_ADC_ADRDY_BIT ) ) ); +} + +static void hal_ll_adc_init( hal_ll_adc_hw_specifics_map_t *map ) { + + hal_ll_gpio_analog_input( hal_ll_gpio_port_base( hal_ll_gpio_port_index( map->pin ) ), + hal_ll_gpio_pin_mask( map->pin ) ); + + _hal_ll_adc_enable_clock( map->module_index ); + + _hal_ll_adc_hw_init((hal_ll_adc_base_handle_t *)map->base, map->resolution); + +} +// ------------------------------------------------------------------------- END + + + + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_80/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_80/CMakeLists.cmake new file mode 100644 index 000000000..94ab821c4 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_80/CMakeLists.cmake @@ -0,0 +1,10 @@ +if(${MCU_NAME} MATCHES "^STM32G0B1CB$|^STM32G0B1KB$|^STM32G0B1MB$|^STM32G0B1RB$|^STM32G0B1VB$|^STM32G0B1CC$|^STM32G0B1KC$|^STM32G0B1MC$|^STM32G0B1RC$|^STM32G0B1VC$|^STM32G0B1CE$|^STM32G0B1KE$|^STM32G0B1ME$|^STM32G0B1NE$|^STM32G0B1RE$|^STM32G0B1VE$") + set(adc_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_adc.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_80") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_80") + list(APPEND hal_ll_def_list "STM32G0xx") + list(APPEND hal_ll_def_list "STM32G0Bxx") + list(APPEND hal_ll_def_list "STM32G0B1xx") + set(adc_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/adc/hal_ll_adc_pin_map/implementations/doc_ds_80") + list(APPEND hal_ll_def_list "HAL_LL_ADC_RESOLUTION_CMAKE=HAL_LL_ADC_RESOLUTION_12_BIT") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_80/hal_ll_adc.c b/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_80/hal_ll_adc.c new file mode 100644 index 000000000..278c6c2e1 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_80/hal_ll_adc.c @@ -0,0 +1,583 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_adc.c + * @brief Low level HAL ADC source file. + */ + +#include "hal_ll_adc.h" +#include "hal_ll_gpio.h" +#include "hal_ll_adc_pin_map.h" +#include "mcu.h" + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_adc_get_module_state_address ((hal_ll_adc_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_adc_get_handle (hal_ll_adc_handle_register_t *)hal_ll_adc_get_module_state_address->hal_ll_adc_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_adc_get_base_struct(_handle) ((hal_ll_adc_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_adc_get_base_from_hal_handle ((hal_ll_adc_hw_specifics_map_t *)((hal_ll_adc_handle_register_t *)\ + (((hal_ll_adc_handle_register_t *)(handle))->hal_ll_adc_handle))->hal_ll_adc_handle)->base +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_adc_module_num(_module_num) (_module_num - 1) + +#define HAL_LL_ADC_ISR_OFFSET ( 0x0 / 4 ) +#define HAL_LL_ADC_IER_OFFSET ( 0x4 / 4 ) +#define HAL_LL_ADC_CR_OFFSET ( 0x8 / 4 ) +#define HAL_LL_ADC_CFGR1_OFFSET ( 0xC / 4 ) +#define HAL_LL_ADC_CFGR2_OFFSET ( 0x10 / 4 ) +#define HAL_LL_ADC_SMPR_OFFSET ( 0x14 / 4 ) +#define HAL_LL_ADC_CHSELR_OFFSET ( 0x28 / 4 ) +#define HAL_LL_ADC_DR_OFFSET ( 0x40 / 4 ) +#define HAL_LL_ADC_CCR_OFFSET ( 0x308 / 4 ) + +#define HAL_LL_ADC_ADEN_BIT 0 +#define HAL_LL_ADC_ADRDY_BIT 0 +#define HAL_LL_ADC_ADDIS_BIT 1 +#define HAL_LL_ADC_ADSTART_BIT 2 +#define HAL_LL_ADC_EOC_BIT 2 +#define HAL_LL_ADC_SCANDIR_BIT 2 +#define HAL_LL_ADC_ADSTP_BIT 4 +#define HAL_LL_ADC_ALIGN_BIT 5 +#define HAL_LL_ADC_CONT_BIT 13 +#define HAL_LL_ADC_ADCAL_BIT 31 +#define HAL_LL_ADC_ADVREGEN_BIT 28 + +#define HAL_LL_ADC1_ENABLE_CLOCK 20 + +#define HAL_LL_ADC_CKMODE0_BIT 30 +#define HAL_LL_ADC_CKMODE1_BIT 31 +#define HAL_LL_ADC_CCIPR 30 + +#define HAL_LL_ADC_2M8HZ 2800000ul +#define HAL_LL_ADC_8MHZ 8000000ul +#define HAL_LL_ADC_16MHZ 16000000ul + + +#define HAL_LL_ADC_12BIT_RES 0x00000000ul +#define HAL_LL_ADC_10BIT_RES 0x00000008ul +#define HAL_LL_ADC_8BIT_RES 0x00000010ul +#define HAL_LL_ADC_6BIT_RES 0x00000018ul + +#define HAL_LL_ADC_SMPR 0xFFFFFFF8ul +#define HAL_LL_ADC_EXTEN 0xFFFFF3FFul +#define HAL_LL_ADC_CR_WAIT 0x80000017ul + +#define HAL_LL_ADC_RESOLUTION_MASK 0xFFFFFFE7ul + +#define HAL_LL_MODULE_INDEX_ERROR 0xFFFFFFFFul + +// -------------------------------------------------------------- PRIVATE TYPES +/*!< @brief Local handle list */ +static hal_ll_adc_handle_register_t hal_ll_module_state[ADC_MODULE_COUNT] = { (handle_t *) NULL, (handle_t *) NULL, false }; + +/*!< Abbreviations used in source. */ +typedef uint32_t hal_ll_adc_base_handle_t; + +/*!< @brief ADC hw specific module values */ +typedef struct +{ + uint16_t pin_an[ADC_MODULE_COUNT]; +} hal_ll_adc_pin_id; + +/** + * Return values + */ +typedef enum +{ + HAL_LL_ADC_SUCCESS = 0, + HAL_LL_ADC_WRONG_PIN, + + HAL_LL_ADC_UNSUPPORTED_RESOLUTION = 1100, + HAL_LL_ADC_UNSUPPORTED_VREF, + HAL_LL_ADC_WRONG_CHANNEL, + HAL_LL_ADC_ERROR = (-1) +} hal_ll_adc_err_t; + +static hal_ll_adc_hw_specifics_map_t hal_ll_adc_hw_specifics_map[] = +{ + #ifdef ADC_MODULE_1 + {ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF}, + #endif + + + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF} +}; + +// ------------------------------------------------------------------ VARIABLES + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_adc_handle_register_t *low_level_handle; +static volatile hal_ll_adc_hw_specifics_map_t *hal_ll_adc_hw_specifics_map_local; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS + +/** + * @brief Enable ADC module 1 clock. + * @param none + * @return none + */ +static inline void adc1_enable_clock(); + +/** + * @brief Initialize ADC module. + * @param *map - ADC module local map. + * @return None + */ +static void hal_ll_adc_init( hal_ll_adc_hw_specifics_map_t *map ); + +/** + * @brief Check if pins are adequate. + * + * Checks analog pin the user has passed with pre-defined + * pins in ADC pin map. + * + * @param[in] pin - ADC pre-defined pin name. + * @param[in] *index - ADC map index value. + * @return hal_ll_pin_name_t Module index based on pin. + * + * Returns pre-defined module index from pin maps, if pin + * is adequate. + */ +static hal_ll_pin_name_t hal_ll_adc_check_pins( hal_ll_pin_name_t pin, hal_ll_adc_pin_id *index, hal_ll_adc_handle_register_t *handle_map ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_adc_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_adc_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_adc_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and channel values for ADC pin + * + * @param[in] module_index ADC HW module index -- 0,1,2... + * @param[in] *index ADC map index value + * + * @return None + */ +static void hal_ll_adc_map_pin( uint8_t module_index, hal_ll_adc_pin_id *index ); + +/** + * @brief Enable ADC module gate clock. + * @param base - ADC module base address. + * @return None + */ +static void _hal_ll_adc_enable_clock( uint8_t base ); + +/** + * @brief Initialize ADC module. + * @param *base - ADC module base address. + * @param resolution - ADC module resolution. + * @return None + */ +static void _hal_ll_adc_hw_init( hal_ll_adc_base_handle_t *base, uint32_t resolution ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_adc_register_handle(hal_ll_pin_name_t pin, hal_ll_adc_voltage_reference_t vref_input, hal_ll_adc_resolution_t resolution, hal_ll_adc_handle_register_t *handle_map, uint8_t *hal_module_id) +{ + uint16_t pin_check_result; + hal_ll_adc_pin_id index = {HAL_LL_PIN_NC}; + + if ( (pin_check_result = hal_ll_adc_check_pins( pin, &index, handle_map )) == HAL_LL_PIN_NC ) { + return HAL_LL_ADC_WRONG_PIN; + }; + + switch ( resolution ) + { + case HAL_LL_ADC_RESOLUTION_12_BIT: + hal_ll_adc_hw_specifics_map[pin_check_result].resolution = HAL_LL_ADC_12BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_10_BIT: + hal_ll_adc_hw_specifics_map[pin_check_result].resolution = HAL_LL_ADC_10BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_8_BIT: + hal_ll_adc_hw_specifics_map[pin_check_result].resolution = HAL_LL_ADC_8BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_6_BIT: + hal_ll_adc_hw_specifics_map[pin_check_result].resolution = HAL_LL_ADC_6BIT_RES; + break; + + default: + return HAL_LL_ADC_UNSUPPORTED_RESOLUTION; + } + + switch ( vref_input ) + { + case HAL_LL_ADC_VREF_EXTERNAL: + break; + + default: + return HAL_LL_ADC_UNSUPPORTED_VREF; + } + + if ( hal_ll_adc_hw_specifics_map[pin_check_result].pin != pin ) + { + hal_ll_adc_map_pin( pin_check_result, &index ); + + handle_map[pin_check_result].init_ll_state = false; + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[pin_check_result].hal_ll_adc_handle = (handle_t *)&hal_ll_adc_hw_specifics_map[pin_check_result].base; + + handle_map[pin_check_result].hal_ll_adc_handle = (handle_t *)&hal_ll_module_state[pin_check_result].hal_ll_adc_handle; + + return HAL_LL_ADC_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_adc( handle_t *handle ) +{ + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + hal_ll_adc_handle_register_t *hal_handle = (hal_ll_adc_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_adc_hw_specifics_map_local->module_index; + + hal_ll_adc_init( hal_ll_adc_hw_specifics_map_local ); + + hal_ll_module_state[pin_check_result].hal_ll_adc_handle = (handle_t *)&hal_ll_adc_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_ADC_SUCCESS; +} + +hal_ll_err_t hal_ll_adc_set_resolution(handle_t *handle, hal_ll_adc_resolution_t resolution) +{ + low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + + low_level_handle->init_ll_state = false; + + switch( resolution ) { + case HAL_LL_ADC_RESOLUTION_12_BIT: + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_12BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_10_BIT: + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_10BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_8_BIT: + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_8BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_6_BIT: + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_6BIT_RES; + break; + + default: + return HAL_LL_ADC_UNSUPPORTED_RESOLUTION; + } + + hal_ll_adc_init( hal_ll_adc_hw_specifics_map_local ); + + low_level_handle->init_ll_state = true; + + return HAL_LL_ADC_SUCCESS; +} + +hal_ll_err_t hal_ll_adc_set_vref_input(handle_t *handle, hal_ll_adc_voltage_reference_t vref_input) +{ + low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + + low_level_handle->init_ll_state = false; + + switch( vref_input ) { + case HAL_LL_ADC_VREF_EXTERNAL: + break; + + default: + return HAL_LL_ADC_UNSUPPORTED_RESOLUTION; + } + + hal_ll_adc_init( hal_ll_adc_hw_specifics_map_local ); + + low_level_handle->init_ll_state = true; + + return HAL_LL_ADC_SUCCESS; +} + +void hal_ll_adc_set_vref_value(handle_t *handle, float vref_value) +{ + low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + + hal_ll_adc_hw_specifics_map_local->vref_value = vref_value; +} + +hal_ll_err_t hal_ll_adc_read( handle_t *handle, uint16_t *readDatabuf ) +{ + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_base_handle_t *base = ( hal_ll_adc_base_handle_t * )hal_ll_adc_hw_specifics_map_local->base ; + + *(base + HAL_LL_ADC_CHSELR_OFFSET) = 1ul << hal_ll_adc_hw_specifics_map_local->channel; + set_reg_bit( ( base + HAL_LL_ADC_CR_OFFSET ), HAL_LL_ADC_ADSTART_BIT ); + + Delay_1us(); + while( !(check_reg_bit( ( base + HAL_LL_ADC_ISR_OFFSET ), HAL_LL_ADC_EOC_BIT ) ) ); + + *readDatabuf = ( *(base + HAL_LL_ADC_DR_OFFSET) ); + + return HAL_LL_ADC_SUCCESS; +} + +void hal_ll_adc_close( handle_t *handle ) +{ + hal_ll_adc_hw_specifics_map_t *hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + low_level_handle = hal_ll_adc_get_handle; + + if( hal_ll_adc_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + + hal_ll_adc_hw_specifics_map_local->vref_input = HAL_LL_ADC_VREF_DEFAULT; + hal_ll_adc_hw_specifics_map_local->vref_value = 0; + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_RESOLUTION_12_BIT; + + low_level_handle->hal_ll_adc_handle = NULL; + low_level_handle->hal_drv_adc_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_adc_hw_specifics_map_local->pin = HAL_LL_PIN_NC; + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static hal_ll_pin_name_t hal_ll_adc_check_pins( hal_ll_pin_name_t pin, hal_ll_adc_pin_id *index, hal_ll_adc_handle_register_t *handle_map ) +{ + static const uint16_t adc_map_size = ( sizeof( _adc_map ) / sizeof( hal_ll_adc_pin_map_t ) ); + uint16_t pin_index = 0; + uint8_t index_counter = 0; + uint8_t hal_ll_module_id = 0; + + if ( HAL_LL_PIN_NC == pin ) { + return HAL_LL_PIN_NC; + } + + for ( pin_index = 0; pin_index < adc_map_size; pin_index++ ) + { + if ( pin == _adc_map[pin_index].pin ) + { + // Get module number + hal_ll_module_id = _adc_map[pin_index].module_index; + // Map pin name + index->pin_an[hal_ll_module_id] = pin_index; + + // Check if module is taken + if ( NULL == handle_map[ hal_ll_module_id ].hal_drv_adc_handle ) { + return hal_ll_module_id; + } else if ( ADC_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static void hal_ll_adc_map_pin( uint8_t module_index, hal_ll_adc_pin_id *index ) { + // Map new pins + hal_ll_adc_hw_specifics_map[module_index].pin = _adc_map[ index->pin_an[module_index] ].pin; + hal_ll_adc_hw_specifics_map[module_index].channel = _adc_map[ index->pin_an[module_index] ].channel; +} + +static hal_ll_adc_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof(hal_ll_adc_handle_register_t)); + static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof(hal_ll_adc_handle_register_t)); + + while( hal_ll_module_count-- ) { + if (hal_ll_adc_get_base_from_hal_handle == hal_ll_adc_hw_specifics_map[hal_ll_module_count].base) { + return &hal_ll_adc_hw_specifics_map[hal_ll_module_count]; + } + } + + return &hal_ll_adc_hw_specifics_map[hal_ll_module_error]; +} + +static void adc_clock_mode( uint32_t clock_value, hal_ll_adc_base_handle_t *base ) +{ + if (clock_value < HAL_LL_ADC_8MHZ) // Set clock and prescaler. + { + // If less than 8MHz, prescaler is set to 1 (read caution on pg. 252 in the reference manual). + set_reg_bit( ( base + HAL_LL_ADC_CFGR2_OFFSET ), HAL_LL_ADC_CKMODE0_BIT ); + set_reg_bit( ( base + HAL_LL_ADC_CFGR2_OFFSET ), HAL_LL_ADC_CKMODE1_BIT ); + } + else if ( clock_value < HAL_LL_ADC_16MHZ ) + { + // Above 8 Mhz, prescaler is set to 2. + set_reg_bit( ( base + HAL_LL_ADC_CFGR2_OFFSET ), HAL_LL_ADC_CKMODE0_BIT ); + clear_reg_bit( ( base + HAL_LL_ADC_CFGR2_OFFSET ), HAL_LL_ADC_CKMODE1_BIT ); + } + else + { + // Above 16 Mhz, prescaler is set to 4. + clear_reg_bit( ( base + HAL_LL_ADC_CFGR2_OFFSET ), HAL_LL_ADC_CKMODE0_BIT ); + set_reg_bit( ( base + HAL_LL_ADC_CFGR2_OFFSET ), HAL_LL_ADC_CKMODE1_BIT ); + } +} + +static inline void adc1_enable_clock() +{ + set_reg_bit( _RCC_APBENR2, HAL_LL_ADC1_ENABLE_CLOCK ); +} + +static void _hal_ll_adc_enable_clock( uint8_t base ) +{ + switch ( base ) + { + #ifdef ADC_MODULE_1 + case ( hal_ll_adc_module_num(ADC_MODULE_1) ): + adc1_enable_clock(); + break; + #endif + + } +} + +static void _hal_ll_adc_hw_init( hal_ll_adc_base_handle_t *base, uint32_t resolution ) +{ + rcc_clocks_t rcc_clocks; + static uint32_t *reg; + static uint32_t temp_reg; + static uint32_t adc_clk; + + /* ADC clock + The ADC features two clock schemes: + Clock for the analog circuitry: ADCCLK, common to all ADCs + This clock is generated from the APB2 clock divided by a programmable prescaler that + allows the ADC to work at fPCLK2/2, /4, /6 or /8. ADCCLK maximum value is 30 MHz + when the APB2 clock is at 60 MHz. */ + RCC_GetClocksFrequency( &rcc_clocks ); + + // Turn off ADC module. + if ( check_reg_bit( ( base + HAL_LL_ADC_CR_OFFSET ), HAL_LL_ADC_ADEN_BIT ) ) + { + while( check_reg_bit( ( base + HAL_LL_ADC_CR_OFFSET ), HAL_LL_ADC_ADSTART_BIT ) ); + set_reg_bit( ( base + HAL_LL_ADC_CR_OFFSET ), HAL_LL_ADC_ADDIS_BIT ); + while( check_reg_bit( ( base + HAL_LL_ADC_CR_OFFSET ), HAL_LL_ADC_ADDIS_BIT )); + } + + + if ( check_reg_bit( ( base + HAL_LL_ADC_CR_OFFSET ), HAL_LL_ADC_ADDIS_BIT ) ) + { + set_reg_bit( ( base + HAL_LL_ADC_CR_OFFSET ), HAL_LL_ADC_ADSTP_BIT ); + } + + + // Select the correct ADC clock source. + temp_reg = _RCC_CCIPR; + temp_reg >>= HAL_LL_ADC_CCIPR; + + switch ( temp_reg ) + { + // If system clock selected as source. + case 0 : + adc_clk = rcc_clocks.sysclk; + break; + // If nothing of the above use PCLK as default clock. + default: + adc_clk = rcc_clocks.pclk; + break; + } + + adc_clock_mode( adc_clk, base ); + + + // Wait for ADEN to go down. + while( check_reg_bit( ( base + HAL_LL_ADC_CR_OFFSET ), HAL_LL_ADC_ADEN_BIT ) ); + + // Start calibration. + set_reg_bit( ( base + HAL_LL_ADC_CR_OFFSET ), HAL_LL_ADC_ADVREGEN_BIT ); + Delay_us(30); + set_reg_bit( ( base + HAL_LL_ADC_CR_OFFSET ), HAL_LL_ADC_ADCAL_BIT ); + while( check_reg_bit( ( base + HAL_LL_ADC_CR_OFFSET ), HAL_LL_ADC_ADCAL_BIT ) ); + + // Set sampling time - 1.5 ADC clock. + *( base + HAL_LL_ADC_SMPR_OFFSET ) &= HAL_LL_ADC_SMPR; + + // Set resolution. + reg = ( base + HAL_LL_ADC_CFGR1_OFFSET ); + *reg &= HAL_LL_ADC_RESOLUTION_MASK; + *reg |= resolution; + + // Wait for hardware to clear ADC_CR register. + while( ( *( base + HAL_LL_ADC_CR_OFFSET ) & HAL_LL_ADC_CR_WAIT ) != 0 ); + + // Scan sequence upward. + clear_reg_bit( ( base + HAL_LL_ADC_CFGR1_OFFSET ), HAL_LL_ADC_SCANDIR_BIT ); + + // Data alignment - right. + clear_reg_bit( ( base + HAL_LL_ADC_CFGR1_OFFSET ), HAL_LL_ADC_ALIGN_BIT ); + + // Single conversion mode. + clear_reg_bit( ( base + HAL_LL_ADC_CFGR1_OFFSET ), HAL_LL_ADC_CONT_BIT ); + + // External trigger disable. + *( base + HAL_LL_ADC_CFGR1_OFFSET ) &= HAL_LL_ADC_EXTEN; + + // Turn on ADC module. + set_reg_bit( ( base + HAL_LL_ADC_CR_OFFSET ), HAL_LL_ADC_ADEN_BIT ); + while( !( check_reg_bit( ( base + HAL_LL_ADC_ISR_OFFSET ), HAL_LL_ADC_ADRDY_BIT ) ) ); +} + +static void hal_ll_adc_init( hal_ll_adc_hw_specifics_map_t *map ) { + + hal_ll_gpio_analog_input( hal_ll_gpio_port_base( hal_ll_gpio_port_index( map->pin ) ), + hal_ll_gpio_pin_mask( map->pin ) ); + + _hal_ll_adc_enable_clock( map->module_index ); + + _hal_ll_adc_hw_init((hal_ll_adc_base_handle_t *)map->base, map->resolution); + +} +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_81/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_81/CMakeLists.cmake new file mode 100644 index 000000000..ad171e151 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_81/CMakeLists.cmake @@ -0,0 +1,10 @@ +if(${MCU_NAME} MATCHES "^STM32G0C1CC$|^STM32G0C1KC$|^STM32G0C1MC$|^STM32G0C1RC$|^STM32G0C1VC$|^STM32G0C1CE$|^STM32G0C1KE$|^STM32G0C1ME$|^STM32G0C1NE$|^STM32G0C1RE$|^STM32G0C1VE$") + set(adc_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_adc.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_81") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_81") + list(APPEND hal_ll_def_list "STM32G0xx") + list(APPEND hal_ll_def_list "STM32G0Cxx") + list(APPEND hal_ll_def_list "STM32G0C1xx") + set(adc_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/adc/hal_ll_adc_pin_map/implementations/doc_ds_81") + list(APPEND hal_ll_def_list "HAL_LL_ADC_RESOLUTION_CMAKE=HAL_LL_ADC_RESOLUTION_12_BIT") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_81/hal_ll_adc.c b/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_81/hal_ll_adc.c new file mode 100644 index 000000000..2eadb29aa --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_81/hal_ll_adc.c @@ -0,0 +1,592 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_adc.c + * @brief Low level HAL ADC source file. + */ + +#include "hal_ll_adc.h" +#include "hal_ll_gpio.h" +#include "hal_ll_adc_pin_map.h" +#include "mcu.h" + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_adc_get_module_state_address ((hal_ll_adc_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_adc_get_handle (hal_ll_adc_handle_register_t *)hal_ll_adc_get_module_state_address->hal_ll_adc_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_adc_get_base_struct(_handle) ((hal_ll_adc_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_adc_get_base_from_hal_handle ((hal_ll_adc_hw_specifics_map_t *)((hal_ll_adc_handle_register_t *)\ + (((hal_ll_adc_handle_register_t *)(handle))->hal_ll_adc_handle))->hal_ll_adc_handle)->base +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_adc_module_num(_module_num) (_module_num - 1) + +#define HAL_LL_ADC_ISR_OFFSET ( 0x0 / 4 ) +#define HAL_LL_ADC_IER_OFFSET ( 0x4 / 4 ) +#define HAL_LL_ADC_CR_OFFSET ( 0x8 / 4 ) +#define HAL_LL_ADC_CFGR1_OFFSET ( 0xC / 4 ) +#define HAL_LL_ADC_CFGR2_OFFSET ( 0x10 / 4 ) +#define HAL_LL_ADC_SMPR_OFFSET ( 0x14 / 4 ) + +#define HAL_LL_ADC_CHSELR_OFFSET ( 0x28 / 4 ) +#define HAL_LL_ADC_DR_OFFSET ( 0x40 / 4 ) +#define HAL_LL_ADC_CCR_OFFSET ( 0x308 / 4 ) + +#define HAL_LL_ADC_ADEN_BIT 0 +#define HAL_LL_ADC_ADRDY_BIT 0 +#define HAL_LL_ADC_ADDIS_BIT 1 +#define HAL_LL_ADC_ADSTART_BIT 2 +#define HAL_LL_ADC_EOC_BIT 2 +#define HAL_LL_ADC_SCANDIR_BIT 2 +#define HAL_LL_ADC_ADSTP_BIT 4 +#define HAL_LL_ADC_ALIGN_BIT 5 +#define HAL_LL_ADC_CONT_BIT 13 +#define HAL_LL_ADC_ADCAL_BIT 31 +#define HAL_LL_ADC_ADVREGEN_BIT 28 + +#define HAL_LL_ADC1_ENABLE_CLOCK 20 + +#define HAL_LL_ADC_CKMODE0_BIT 30 +#define HAL_LL_ADC_CKMODE1_BIT 31 +#define HAL_LL_ADC_CCIPR 30 + +#define HAL_LL_ADC_2M8HZ 2800000ul +#define HAL_LL_ADC_8MHZ 8000000ul +#define HAL_LL_ADC_16MHZ 16000000ul + + +#define HAL_LL_ADC_12BIT_RES 0x00000000ul +#define HAL_LL_ADC_10BIT_RES 0x00000008ul +#define HAL_LL_ADC_8BIT_RES 0x00000010ul +#define HAL_LL_ADC_6BIT_RES 0x00000018ul + +#define HAL_LL_ADC_SMPR 0xFFFFFFF8ul +#define HAL_LL_ADC_EXTEN 0xFFFFF3FFul +#define HAL_LL_ADC_CR_WAIT 0x80000017ul + +#define HAL_LL_ADC_RESOLUTION_MASK 0xFFFFFFE7ul + +#define HAL_LL_MODULE_INDEX_ERROR 0xFFFFFFFFul + +// -------------------------------------------------------------- PRIVATE TYPES +/*!< @brief Local handle list */ +static hal_ll_adc_handle_register_t hal_ll_module_state[ADC_MODULE_COUNT] = { (handle_t *) NULL, (handle_t *) NULL, false }; + +/*!< Abbreviations used in source. */ +typedef uint32_t hal_ll_adc_base_handle_t; + +/*!< @brief ADC hw specific module values */ +typedef struct +{ + uint16_t pin_an[ADC_MODULE_COUNT]; +} hal_ll_adc_pin_id; + +/** + * Return values + */ +typedef enum +{ + HAL_LL_ADC_SUCCESS = 0, + HAL_LL_ADC_WRONG_PIN, + + HAL_LL_ADC_UNSUPPORTED_RESOLUTION = 1100, + HAL_LL_ADC_UNSUPPORTED_VREF, + HAL_LL_ADC_WRONG_CHANNEL, + HAL_LL_ADC_ERROR = (-1) +} hal_ll_adc_err_t; + +static hal_ll_adc_hw_specifics_map_t hal_ll_adc_hw_specifics_map[] = +{ + #ifdef ADC_MODULE_1 + {ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF}, + #endif + + + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF} +}; + +// ------------------------------------------------------------------ VARIABLES + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_adc_handle_register_t *low_level_handle; +static volatile hal_ll_adc_hw_specifics_map_t *hal_ll_adc_hw_specifics_map_local; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS + +/** + * @brief Enable ADC module 1 clock. + * @param none + * @return none + */ +static inline void adc1_enable_clock(); + +/** + * @brief Initialize ADC module. + * @param *map - ADC module local map. + * @return None + */ +static void hal_ll_adc_init( hal_ll_adc_hw_specifics_map_t *map ); + +/** + * @brief Check if pins are adequate. + * + * Checks analog pin the user has passed with pre-defined + * pins in ADC pin map. + * + * @param[in] pin - ADC pre-defined pin name. + * @param[in] *index - ADC map index value. + * @return hal_ll_pin_name_t Module index based on pin. + * + * Returns pre-defined module index from pin maps, if pin + * is adequate. + */ +static hal_ll_pin_name_t hal_ll_adc_check_pins( hal_ll_pin_name_t pin, hal_ll_adc_pin_id *index, hal_ll_adc_handle_register_t *handle_map ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_adc_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_adc_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_adc_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and channel values for ADC pin + * + * @param[in] module_index ADC HW module index -- 0,1,2... + * @param[in] *index ADC map index value + * + * @return None + */ +static void hal_ll_adc_map_pin( uint8_t module_index, hal_ll_adc_pin_id *index ); + +/** + * @brief Enable ADC module gate clock. + * @param base - ADC module base address. + * @return None + */ +static void _hal_ll_adc_enable_clock( uint8_t base ); + +/** + * @brief Initialize ADC module. + * @param *base - ADC module base address. + * @param resolution - ADC module resolution. + * @return None + */ +static void _hal_ll_adc_hw_init( hal_ll_adc_base_handle_t *base, uint32_t resolution ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_adc_register_handle(hal_ll_pin_name_t pin, hal_ll_adc_voltage_reference_t vref_input, hal_ll_adc_resolution_t resolution, hal_ll_adc_handle_register_t *handle_map, uint8_t *hal_module_id) +{ + uint16_t pin_check_result; + hal_ll_adc_pin_id index = {HAL_LL_PIN_NC}; + + if ( (pin_check_result = hal_ll_adc_check_pins( pin, &index, handle_map )) == HAL_LL_PIN_NC ) { + return HAL_LL_ADC_WRONG_PIN; + }; + + switch ( resolution ) + { + case HAL_LL_ADC_RESOLUTION_12_BIT: + hal_ll_adc_hw_specifics_map[pin_check_result].resolution = HAL_LL_ADC_12BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_10_BIT: + hal_ll_adc_hw_specifics_map[pin_check_result].resolution = HAL_LL_ADC_10BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_8_BIT: + hal_ll_adc_hw_specifics_map[pin_check_result].resolution = HAL_LL_ADC_8BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_6_BIT: + hal_ll_adc_hw_specifics_map[pin_check_result].resolution = HAL_LL_ADC_6BIT_RES; + break; + + default: + return HAL_LL_ADC_UNSUPPORTED_RESOLUTION; + } + + switch ( vref_input ) + { + case HAL_LL_ADC_VREF_EXTERNAL: + break; + + default: + return HAL_LL_ADC_UNSUPPORTED_VREF; + } + + if ( hal_ll_adc_hw_specifics_map[pin_check_result].pin != pin ) + { + hal_ll_adc_map_pin( pin_check_result, &index ); + + handle_map[pin_check_result].init_ll_state = false; + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[pin_check_result].hal_ll_adc_handle = (handle_t *)&hal_ll_adc_hw_specifics_map[pin_check_result].base; + + handle_map[pin_check_result].hal_ll_adc_handle = (handle_t *)&hal_ll_module_state[pin_check_result].hal_ll_adc_handle; + + return HAL_LL_ADC_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_adc( handle_t *handle ) +{ + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + hal_ll_adc_handle_register_t *hal_handle = (hal_ll_adc_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_adc_hw_specifics_map_local->module_index; + + hal_ll_adc_init( hal_ll_adc_hw_specifics_map_local ); + + hal_ll_module_state[pin_check_result].hal_ll_adc_handle = (handle_t *)&hal_ll_adc_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_ADC_SUCCESS; +} + +hal_ll_err_t hal_ll_adc_set_resolution(handle_t *handle, hal_ll_adc_resolution_t resolution) +{ + low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + + low_level_handle->init_ll_state = false; + + switch( resolution ) { + case HAL_LL_ADC_RESOLUTION_12_BIT: + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_12BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_10_BIT: + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_10BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_8_BIT: + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_8BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_6_BIT: + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_6BIT_RES; + break; + + default: + return HAL_LL_ADC_UNSUPPORTED_RESOLUTION; + } + + hal_ll_adc_init( hal_ll_adc_hw_specifics_map_local ); + + low_level_handle->init_ll_state = true; + + return HAL_LL_ADC_SUCCESS; +} + +hal_ll_err_t hal_ll_adc_set_vref_input(handle_t *handle, hal_ll_adc_voltage_reference_t vref_input) +{ + low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + + low_level_handle->init_ll_state = false; + + switch( vref_input ) { + case HAL_LL_ADC_VREF_EXTERNAL: + break; + + default: + return HAL_LL_ADC_UNSUPPORTED_RESOLUTION; + } + + hal_ll_adc_init( hal_ll_adc_hw_specifics_map_local ); + + low_level_handle->init_ll_state = true; + + return HAL_LL_ADC_SUCCESS; +} + +void hal_ll_adc_set_vref_value(handle_t *handle, float vref_value) +{ + low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + + hal_ll_adc_hw_specifics_map_local->vref_value = vref_value; +} + +hal_ll_err_t hal_ll_adc_read( handle_t *handle, uint16_t *readDatabuf ) +{ + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_base_handle_t *base = ( hal_ll_adc_base_handle_t * )hal_ll_adc_hw_specifics_map_local->base ; + + *(base + HAL_LL_ADC_CHSELR_OFFSET) = 1ul << hal_ll_adc_hw_specifics_map_local->channel; + set_reg_bit( ( base + HAL_LL_ADC_CR_OFFSET ), HAL_LL_ADC_ADSTART_BIT ); + + Delay_1us(); + while( !(check_reg_bit( ( base + HAL_LL_ADC_ISR_OFFSET ), HAL_LL_ADC_EOC_BIT ) ) ); + + *readDatabuf = ( *(base + HAL_LL_ADC_DR_OFFSET) ); + + return HAL_LL_ADC_SUCCESS; +} + +void hal_ll_adc_close( handle_t *handle ) +{ + hal_ll_adc_hw_specifics_map_t *hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + low_level_handle = hal_ll_adc_get_handle; + + if( hal_ll_adc_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + + hal_ll_adc_hw_specifics_map_local->vref_input = HAL_LL_ADC_VREF_DEFAULT; + hal_ll_adc_hw_specifics_map_local->vref_value = 0; + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_RESOLUTION_12_BIT; + + low_level_handle->hal_ll_adc_handle = NULL; + low_level_handle->hal_drv_adc_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_adc_hw_specifics_map_local->pin = HAL_LL_PIN_NC; + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static hal_ll_pin_name_t hal_ll_adc_check_pins( hal_ll_pin_name_t pin, hal_ll_adc_pin_id *index, hal_ll_adc_handle_register_t *handle_map ) +{ + static const uint16_t adc_map_size = ( sizeof( _adc_map ) / sizeof( hal_ll_adc_pin_map_t ) ); + uint16_t pin_index = 0; + uint8_t index_counter = 0; + uint8_t hal_ll_module_id = 0; + + if ( HAL_LL_PIN_NC == pin ) { + return HAL_LL_PIN_NC; + } + + for ( pin_index = 0; pin_index < adc_map_size; pin_index++ ) + { + if ( pin == _adc_map[pin_index].pin ) + { + // Get module number + hal_ll_module_id = _adc_map[pin_index].module_index; + // Map pin name + index->pin_an[hal_ll_module_id] = pin_index; + + // Check if module is taken + if ( NULL == handle_map[ hal_ll_module_id ].hal_drv_adc_handle ) { + return hal_ll_module_id; + } else if ( ADC_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static void hal_ll_adc_map_pin( uint8_t module_index, hal_ll_adc_pin_id *index ) { + // Map new pins + hal_ll_adc_hw_specifics_map[module_index].pin = _adc_map[ index->pin_an[module_index] ].pin; + hal_ll_adc_hw_specifics_map[module_index].channel = _adc_map[ index->pin_an[module_index] ].channel; +} + +static hal_ll_adc_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof(hal_ll_adc_handle_register_t)); + static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof(hal_ll_adc_handle_register_t)); + + while( hal_ll_module_count-- ) { + if (hal_ll_adc_get_base_from_hal_handle == hal_ll_adc_hw_specifics_map[hal_ll_module_count].base) { + return &hal_ll_adc_hw_specifics_map[hal_ll_module_count]; + } + } + + return &hal_ll_adc_hw_specifics_map[hal_ll_module_error]; +} + +static void adc_clock_mode( uint32_t clock_value, hal_ll_adc_base_handle_t *base ) +{ + if (clock_value < HAL_LL_ADC_8MHZ) // Set clock and prescaler. + { + // If less than 8MHz, prescaler is set to 1 (read caution on pg. 252 in the reference manual). + set_reg_bit( ( base + HAL_LL_ADC_CFGR2_OFFSET ), HAL_LL_ADC_CKMODE0_BIT ); + set_reg_bit( ( base + HAL_LL_ADC_CFGR2_OFFSET ), HAL_LL_ADC_CKMODE1_BIT ); + } + else if ( clock_value < HAL_LL_ADC_16MHZ ) + { + // Above 8 Mhz, prescaler is set to 2. + set_reg_bit( ( base + HAL_LL_ADC_CFGR2_OFFSET ), HAL_LL_ADC_CKMODE0_BIT ); + clear_reg_bit( ( base + HAL_LL_ADC_CFGR2_OFFSET ), HAL_LL_ADC_CKMODE1_BIT ); + } + else + { + // Above 16 Mhz, prescaler is set to 4. + clear_reg_bit( ( base + HAL_LL_ADC_CFGR2_OFFSET ), HAL_LL_ADC_CKMODE0_BIT ); + set_reg_bit( ( base + HAL_LL_ADC_CFGR2_OFFSET ), HAL_LL_ADC_CKMODE1_BIT ); + } +} + + +static inline void adc1_enable_clock() +{ + set_reg_bit( _RCC_APBENR2, HAL_LL_ADC1_ENABLE_CLOCK ); +} +static void _hal_ll_adc_enable_clock( uint8_t base ) +{ + switch ( base ) + { + #ifdef ADC_MODULE_1 + case ( hal_ll_adc_module_num(ADC_MODULE_1) ): + adc1_enable_clock(); + break; + #endif + + } +} + +static void _hal_ll_adc_hw_init( hal_ll_adc_base_handle_t *base, uint32_t resolution ) +{ + rcc_clocks_t rcc_clocks; + static uint32_t *reg; + static uint32_t temp_reg; + static uint32_t adc_clk; + + /* ADC clock + The ADC features two clock schemes: + Clock for the analog circuitry: ADCCLK, common to all ADCs + This clock is generated from the APB2 clock divided by a programmable prescaler that + allows the ADC to work at fPCLK2/2, /4, /6 or /8. ADCCLK maximum value is 30 MHz + when the APB2 clock is at 60 MHz. */ + RCC_GetClocksFrequency( &rcc_clocks ); + +// Turn off ADC module. + if ( check_reg_bit( ( base + HAL_LL_ADC_CR_OFFSET ), HAL_LL_ADC_ADEN_BIT ) ) + { + while( check_reg_bit( ( base + HAL_LL_ADC_CR_OFFSET ), HAL_LL_ADC_ADSTART_BIT ) ); + set_reg_bit( ( base + HAL_LL_ADC_CR_OFFSET ), HAL_LL_ADC_ADDIS_BIT ); + while( check_reg_bit( ( base + HAL_LL_ADC_CR_OFFSET ), HAL_LL_ADC_ADDIS_BIT )); + } + + + if ( check_reg_bit( ( base + HAL_LL_ADC_CR_OFFSET ), HAL_LL_ADC_ADDIS_BIT ) ) + { + set_reg_bit( ( base + HAL_LL_ADC_CR_OFFSET ), HAL_LL_ADC_ADSTP_BIT ); + } + + + // Select the correct ADC clock source. + temp_reg = _RCC_CCIPR; + temp_reg >>= HAL_LL_ADC_CCIPR; + + switch ( temp_reg ) + { + // If system clock selected as source. + case 0 : + adc_clk = rcc_clocks.sysclk; + break; + // If nothing of the above use PCLK as default clock. + default: + adc_clk = rcc_clocks.pclk; + break; + } + + adc_clock_mode( adc_clk, base ); + + + + // Wait for ADEN to go down. + while( check_reg_bit( ( base + HAL_LL_ADC_CR_OFFSET ), HAL_LL_ADC_ADEN_BIT ) ); + + // Start calibration. + set_reg_bit( ( base + HAL_LL_ADC_CR_OFFSET ), HAL_LL_ADC_ADVREGEN_BIT ); + Delay_us(30); + set_reg_bit( ( base + HAL_LL_ADC_CR_OFFSET ), HAL_LL_ADC_ADCAL_BIT ); + while( check_reg_bit( ( base + HAL_LL_ADC_CR_OFFSET ), HAL_LL_ADC_ADCAL_BIT ) ); + + + + // Set sampling time - 1.5 ADC clock. + *( base + HAL_LL_ADC_SMPR_OFFSET ) &= HAL_LL_ADC_SMPR; + + // Set resolution. + reg = ( base + HAL_LL_ADC_CFGR1_OFFSET ); + *reg &= HAL_LL_ADC_RESOLUTION_MASK; + *reg |= resolution; + + // Wait for hardware to clear ADC_CR register. + while( ( *( base + HAL_LL_ADC_CR_OFFSET ) & HAL_LL_ADC_CR_WAIT ) != 0 ); + + // Scan sequence upward. +// *( base + HAL_LL_ADC_CFGR1_OFFSET ) &= 0xFFFFFFFF; + clear_reg_bit( ( base + HAL_LL_ADC_CFGR1_OFFSET ), HAL_LL_ADC_SCANDIR_BIT ); + + // Data alignment - right. + clear_reg_bit( ( base + HAL_LL_ADC_CFGR1_OFFSET ), HAL_LL_ADC_ALIGN_BIT ); + + // Single conversion mode. + clear_reg_bit( ( base + HAL_LL_ADC_CFGR1_OFFSET ), HAL_LL_ADC_CONT_BIT ); + + // External trigger disable. + *( base + HAL_LL_ADC_CFGR1_OFFSET ) &= HAL_LL_ADC_EXTEN; + + // Turn on ADC module. + set_reg_bit( ( base + HAL_LL_ADC_CR_OFFSET ), HAL_LL_ADC_ADEN_BIT ); + while( !( check_reg_bit( ( base + HAL_LL_ADC_ISR_OFFSET ), HAL_LL_ADC_ADRDY_BIT ) ) ); +} + +static void hal_ll_adc_init( hal_ll_adc_hw_specifics_map_t *map ) { + + hal_ll_gpio_analog_input( hal_ll_gpio_port_base( hal_ll_gpio_port_index( map->pin ) ), + hal_ll_gpio_pin_mask( map->pin ) ); + + _hal_ll_adc_enable_clock( map->module_index ); + + _hal_ll_adc_hw_init((hal_ll_adc_base_handle_t *)map->base, map->resolution); + +} +// ------------------------------------------------------------------------- END + + + + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_82/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_82/CMakeLists.cmake new file mode 100644 index 000000000..ef9b10c0a --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_82/CMakeLists.cmake @@ -0,0 +1,10 @@ +if(${MCU_NAME} MATCHES "^STM32G431C6$|^STM32G431K6$|^STM32G431R6$|^STM32G431V6$|^STM32G431M6$|^STM32G431C8$|^STM32G431K8$|^STM32G431R8$|^STM32G431V8$|^STM32G431M8$|^STM32G431CB$|^STM32G431KB$|^STM32G431RB$|^STM32G431VB$|^STM32G431MB$") + set(adc_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_adc.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_82") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_82") + list(APPEND hal_ll_def_list "STM32G4xx") + list(APPEND hal_ll_def_list "STM32G43xx") + list(APPEND hal_ll_def_list "STM32G431xx") + set(adc_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/adc/hal_ll_adc_pin_map/implementations/doc_ds_82") + list(APPEND hal_ll_def_list "HAL_LL_ADC_RESOLUTION_CMAKE=HAL_LL_ADC_RESOLUTION_12_BIT") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_82/hal_ll_adc.c b/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_82/hal_ll_adc.c new file mode 100644 index 000000000..b413ad922 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_82/hal_ll_adc.c @@ -0,0 +1,629 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_adc.c + * @brief Low level HAL ADC source file. + */ + +#include "hal_ll_adc.h" +#include "hal_ll_gpio.h" +#include "hal_ll_adc_pin_map.h" + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_adc_get_module_state_address ((hal_ll_adc_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_adc_get_handle (hal_ll_adc_handle_register_t *)hal_ll_adc_get_module_state_address->hal_ll_adc_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_adc_get_base_struct(_handle) ((hal_ll_adc_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_adc_get_base_from_hal_handle ((hal_ll_adc_hw_specifics_map_t *)((hal_ll_adc_handle_register_t *)\ + (((hal_ll_adc_handle_register_t *)(handle))->hal_ll_adc_handle))->hal_ll_adc_handle)->base +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_adc_module_num(_module_num) (_module_num - 1) + +// ADC common registers. + +#define hal_ll_adc_module_num(_module_num) (_module_num - 1) + +#define HAL_LL_ADC_CSR_OFFSET ( 0x300 / 4 ) +#define HAL_LL_ADC_CCR_OFFSET ( 0x308 / 4 ) +#define HAL_LL_ADC_CDR_OFFSET ( 0x30C / 4 ) + +#define HAL_LL_ADC_APB2ENR_SYSCFGEN 0 +#define HAL_LL_ADC_VREF_ENVR 0 +#define HAL_LL_ADC_ADRDYIE_BIT 0 +#define HAL_LL_ADC_ADEN_BIT 0 +#define HAL_LL_ADC_ADRDY_BIT 0 +#define HAL_LL_ADC_ADDIS_BIT 1 +#define HAL_LL_ADC_EOC_BIT 2 +#define HAL_LL_ADC_ADSTART_BIT 2 +#define HAL_LL_ADC_RESOLUTION_BIT0 3 +#define HAL_LL_ADC_RESOLUTION_BIT1 4 +#define HAL_LL_ADC_VREF_VRR 3 +#define HAL_LL_ADC_ALIGN_BIT 15 + +#define HAL_LL_ADC1_ENABLE_CLOCK 13 +#define HAL_LL_ADC2_ENABLE_CLOCK 13 + +#define HAL_LL_ADC_CONT_BIT 13 +#define HAL_LL_ADC_DISCEN_BIT 16 +#define HAL_LL_ADC_ADVREGEN_BIT 28 +#define HAL_LL_ADC_DEEPPWD_BIT 29 +#define HAL_LL_ADC_ADCALDIF_BIT 30 +#define HAL_LL_ADC_ADCAL_BIT 31 +#define HAL_LL_ADC_PIN_MASK 0xF + +#define HAL_LL_ADC_12BIT_RES 0x00000000ul +#define HAL_LL_ADC_10BIT_RES 0x00000008ul +#define HAL_LL_ADC_8BIT_RES 0x00000010ul +#define HAL_LL_ADC_6BIT_RES 0x00000018ul + +#define ADC_CAL_SINGLE 0x00000000ul +#define ADC_CAL_DIF 0x00000001ul +#define HAL_LL_ADC_CLK_SRC 0xF0000000ul +#define HAL_LL_ADC_VOLTAGE 0xCFFFFFFFul +#define HAL_LL_ADC_CCR 0x50000308ul +#define HAL_LL_ADC_CKMODE_MASK 0x00000000ul +#define HAL_LL_ADC_VREFEN_MASK 0x00400000ul +#define HAL_LL_ADC_CCIPR 0x40021088ul +#define HAL_LL_ADC_PRESCALER 0xFFC3FFFFul +#define HAL_LL_ADC_CONVERSION 0xFFFFFFF0ul +#define HAL_LL_ADC_CONVERSION_ONE 0x000007C0ul + +#define HAL_LL_MODULE_INDEX_ERROR 0xFFFFFFFFul + +#define HAL_LL_RESOLUTION_MASK 0xFFFFFFE7ul + +#define HAL_LL_ADC_DEFAULT_BASE_ADDRESS 0xFF + +// -------------------------------------------------------------- PRIVATE TYPES +/*!< @brief Local handle list */ +static hal_ll_adc_handle_register_t hal_ll_module_state[ADC_MODULE_COUNT] = { (handle_t *) NULL, (handle_t *) NULL, false }; + +/** + * Return values + */ +typedef enum +{ + HAL_LL_ADC_SUCCESS = 0, + HAL_LL_ADC_WRONG_PIN, + + HAL_LL_ADC_UNSUPPORTED_RESOLUTION = 1100, + HAL_LL_ADC_UNSUPPORTED_VREF, + HAL_LL_ADC_WRONG_CHANNEL, + HAL_LL_ADC_ERROR = (-1) +} hal_ll_adc_err_t; + +/*!< @brief ADC register structure. */ +typedef struct +{ + uint32_t isr; /* ADC interrupt and status register (ADC_ISR) */ + uint32_t ier; /* ADC interrupt enable register (ADC_IER) */ + uint32_t cr; /* ADC control register (ADC_CR) */ + uint32_t cfgr; /* ADC configuration register (ADC_CFGR) */ + uint32_t cfgr2; /* ADC configuration register (ADC_CFGR) */ + uint32_t smpr1; /* ADC sample time register 1 (ADC_SMPR1) */ + uint32_t smpr2; /* ADC sample time register 1 (ADC_SMPR1) */ + uint32_t __unused1[1]; /* */ + uint32_t tr1; /* ADC watchdog threshold register 1 (ADC_TR1) */ + uint32_t tr2; /* ADC watchdog threshold register 1 (ADC_TR1) */ + uint32_t tr3; /* ADC watchdog threshold register 1 (ADC_TR1) */ + uint32_t __unused2[1]; /* */ + uint32_t sqr1; /* ADC regular sequence register 1 (ADC_SQR1) */ + uint32_t sqr2; /* ADC regular sequence register 1 (ADC_SQR1) */ + uint32_t sqr3; /* ADC regular sequence register 1 (ADC_SQR1) */ + uint32_t sqr4; /* ADC regular sequence register 1 (ADC_SQR1) */ + uint32_t dr; /* ADC regular data register (ADC_DR) */ + uint32_t __unused3[2]; /* */ + uint32_t jsqr; /* ADC injected sequence register (ADC_JSQR) */ + uint32_t __unused4[4]; /* */ + uint32_t ofr1; /* ADC offset y register (ADC_OFRy) */ + uint32_t ofr2; /* ADC offset y register (ADC_OFRy) */ + uint32_t ofr3; /* ADC offset y register (ADC_OFRy) */ + uint32_t ofr4; /* ADC offset y register (ADC_OFRy) */ + uint32_t __unused5[4]; /* */ + uint32_t jdr1; /* ADC injected channel y data register (ADC_JDRy) */ + uint32_t jdr2; /* ADC injected channel y data register (ADC_JDRy) */ + uint32_t jdr3; /* ADC injected channel y data register (ADC_JDRy) */ + uint32_t jdr4; /* ADC injected channel y data register (ADC_JDRy) */ + uint32_t __unused6[4]; /* */ + uint32_t awd2cr; /* ADC analog watchdog 2 configuration register (ADC_AWD2CR) */ + uint32_t awd3cr; /* ADC analog watchdog 2 configuration register (ADC_AWD2CR) */ + uint32_t __unused7[2]; /* */ + uint32_t difsel; /* ADC differential mode selection register (ADC_DIFSEL) */ + uint32_t calfact; /* ADC calibration factors (ADC_CALFACT) */ + uint32_t __unused8[2]; /* */ + uint32_t gcomp; /* ADC Gain compensation Register (ADC_GCOMP) */ + uint32_t csr; /* ADCx common status register (ADCx_CSR) (x = 12 or 345) */ + uint32_t __unused9[1]; /* */ + uint32_t ccr; /* ADCx common control register (ADCx_CCR) (x = 12 or 345) */ + uint32_t __unused10[192]; /* */ + uint32_t cdr; /* ADCx common regular data register for dual mode (ADCx_CDR) (x = 12 or 345) */ +} hal_ll_adc_base_handle_t; + +/*!< @brief ADC hw specific module values */ +typedef struct +{ + uint16_t pin_an[ADC_MODULE_COUNT]; +} hal_ll_adc_pin_id; + +static hal_ll_adc_hw_specifics_map_t hal_ll_adc_hw_specifics_map[] = +{ + #ifdef ADC_MODULE_1 + {ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF}, + #endif + #ifdef ADC_MODULE_2 + {ADC2_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF}, + #endif + + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF} +}; + +// ------------------------------------------------------------------ VARIABLES + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_adc_handle_register_t *low_level_handle; +static volatile hal_ll_adc_hw_specifics_map_t *hal_ll_adc_hw_specifics_map_local; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Enable ADC module 1 clock. + * @param none + * @return none + */ +static inline void adc1_enable_clock(); +/** + * @brief Enable ADC module 2 clock. + * @param none + * @return none + */ +static inline void adc2_enable_clock(); + +/** + * @brief Initialize ADC module. + * @param *map - ADC module local map. + * @return None + */ +static void hal_ll_adc_init( hal_ll_adc_hw_specifics_map_t *map ); + +/** + * @brief Check if pins are adequate. + * + * Checks analog pin the user has passed with pre-defined + * pins in ADC pin map. + * + * @param[in] pin - ADC pre-defined pin name. + * @param[in] *index - ADC map index value. + * @return hal_ll_pin_name_t Module index based on pin. + * + * Returns pre-defined module index from pin maps, if pin + * is adequate. + */ +static hal_ll_pin_name_t hal_ll_adc_check_pins( hal_ll_pin_name_t pin, hal_ll_adc_pin_id *index, hal_ll_adc_handle_register_t *handle_map ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and channel values for ADC pin + * + * @param[in] module_index ADC HW module index -- 0,1,2... + * @param[in] *index ADC map index value + * + * @return None + */ +static void hal_ll_adc_map_pin( uint8_t module_index, hal_ll_adc_pin_id *index ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_adc_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_adc_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_adc_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Enable ADC module gate clock. + * @param base - ADC module base address. + * @return None + */ +static void _hal_ll_adc_enable_clock( uint8_t base ); + +/** + * @brief Initialize ADC module. + * @param *base - ADC module base address. + * @param resolution - ADC module resolution. + * @return None + */ +static void _hal_ll_adc_hw_init( hal_ll_adc_base_handle_t *base, uint32_t resolution ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_adc_register_handle(hal_ll_pin_name_t pin, hal_ll_adc_voltage_reference_t vref_input, hal_ll_adc_resolution_t resolution, hal_ll_adc_handle_register_t *handle_map, uint8_t *hal_module_id) +{ + uint16_t pin_check_result; + hal_ll_adc_pin_id index = {HAL_LL_PIN_NC}; + + if ( (pin_check_result = hal_ll_adc_check_pins( pin, &index, handle_map )) == HAL_LL_PIN_NC ) { + return HAL_LL_ADC_WRONG_PIN; + }; + + switch ( resolution ) + { + case HAL_LL_ADC_RESOLUTION_12_BIT: + hal_ll_adc_hw_specifics_map[pin_check_result].resolution = HAL_LL_ADC_12BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_10_BIT: + hal_ll_adc_hw_specifics_map[pin_check_result].resolution = HAL_LL_ADC_10BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_8_BIT: + hal_ll_adc_hw_specifics_map[pin_check_result].resolution = HAL_LL_ADC_8BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_6_BIT: + hal_ll_adc_hw_specifics_map[pin_check_result].resolution = HAL_LL_ADC_6BIT_RES; + break; + default: + return HAL_LL_ADC_UNSUPPORTED_RESOLUTION; + } + + switch ( vref_input ) + { + case HAL_LL_ADC_VREF_EXTERNAL: + break; + + default: + return HAL_LL_ADC_UNSUPPORTED_VREF; + } + + if ( hal_ll_adc_hw_specifics_map[pin_check_result].pin != pin ) + { + hal_ll_adc_map_pin( pin_check_result, &index ); + + handle_map[pin_check_result].init_ll_state = false; + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[pin_check_result].hal_ll_adc_handle = (handle_t *)&hal_ll_adc_hw_specifics_map[pin_check_result].base; + + handle_map[pin_check_result].hal_ll_adc_handle = (handle_t *)&hal_ll_module_state[pin_check_result].hal_ll_adc_handle; + + return HAL_LL_ADC_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_adc( handle_t *handle ) +{ + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + hal_ll_adc_handle_register_t *hal_handle = (hal_ll_adc_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_adc_hw_specifics_map_local->module_index; + + hal_ll_adc_init( hal_ll_adc_hw_specifics_map_local ); + + hal_ll_module_state[pin_check_result].hal_ll_adc_handle = (handle_t *)&hal_ll_adc_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_ADC_SUCCESS; +} + +hal_ll_err_t hal_ll_adc_set_resolution(handle_t *handle, hal_ll_adc_resolution_t resolution) +{ + low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + + low_level_handle->init_ll_state = false; + + switch( resolution ) { + case HAL_LL_ADC_RESOLUTION_12_BIT: + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_12BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_10_BIT: + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_10BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_8_BIT: + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_8BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_6_BIT: + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_6BIT_RES; + break; + + default: + return HAL_LL_ADC_UNSUPPORTED_RESOLUTION; + } + + hal_ll_adc_init( hal_ll_adc_hw_specifics_map_local ); + + low_level_handle->init_ll_state = true; + + return HAL_LL_ADC_SUCCESS; +} + +hal_ll_err_t hal_ll_adc_set_vref_input(handle_t *handle, hal_ll_adc_voltage_reference_t vref_input) +{ + low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + + low_level_handle->init_ll_state = false; + + switch( vref_input ) { + case HAL_LL_ADC_VREF_EXTERNAL: + break; + + default: + return HAL_LL_ADC_UNSUPPORTED_VREF; + } + + hal_ll_adc_init( hal_ll_adc_hw_specifics_map_local ); + + low_level_handle->init_ll_state = true; + + return HAL_LL_ADC_SUCCESS; +} + +void hal_ll_adc_set_vref_value(handle_t *handle, float vref_value) +{ + low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + + hal_ll_adc_hw_specifics_map_local->vref_value = vref_value; +} + +hal_ll_err_t hal_ll_adc_read( handle_t *handle, uint16_t *readDatabuf ) +{ + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_base_handle_t *base = ( hal_ll_adc_base_handle_t * )hal_ll_adc_hw_specifics_map_local->base ; + + while( ( check_reg_bit( &( base->cr ), HAL_LL_ADC_ADSTART_BIT ) ) ); + base->sqr1 &= ~HAL_LL_ADC_CONVERSION_ONE; + base->sqr1 |= ( ( hal_ll_adc_hw_specifics_map_local->channel << 6 ) ); + + Delay_1us(); + + // Start the conversion. + set_reg_bit( &( base->cr ), HAL_LL_ADC_ADSTART_BIT ); + + while ( !( check_reg_bit( &( base->isr ), HAL_LL_ADC_EOC_BIT ) ) ); + // Conversion result from SS3. + *readDatabuf = base->dr; + + return HAL_LL_ADC_SUCCESS; +} + +void hal_ll_adc_close( handle_t *handle ) +{ + hal_ll_adc_hw_specifics_map_t *hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + low_level_handle = hal_ll_adc_get_handle; + + if( hal_ll_adc_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + + hal_ll_adc_hw_specifics_map_local->vref_input = HAL_LL_ADC_VREF_DEFAULT; + hal_ll_adc_hw_specifics_map_local->vref_value = 0; + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_RESOLUTION_12_BIT; + + low_level_handle->hal_ll_adc_handle = NULL; + low_level_handle->hal_drv_adc_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_adc_hw_specifics_map_local->pin = HAL_LL_PIN_NC; + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static hal_ll_pin_name_t hal_ll_adc_check_pins( hal_ll_pin_name_t pin, hal_ll_adc_pin_id *index, hal_ll_adc_handle_register_t *handle_map ) +{ + static const uint16_t adc_map_size = ( sizeof( _adc_map ) / sizeof( hal_ll_adc_pin_map_t ) ); + uint16_t pin_index = 0; + uint8_t index_counter = 0; + uint8_t hal_ll_module_id = 0; + + if ( HAL_LL_PIN_NC == pin ) { + return HAL_LL_PIN_NC; + } + + for ( pin_index = 0; pin_index < adc_map_size; pin_index++ ) + { + if ( pin == _adc_map[pin_index].pin ) + { + // Get module number + hal_ll_module_id = _adc_map[pin_index].module_index; + // Map pin name + index->pin_an[hal_ll_module_id] = pin_index; + + // Check if module is taken + if ( NULL == handle_map[ hal_ll_module_id ].hal_drv_adc_handle ) { + return hal_ll_module_id; + } else if ( ADC_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static void hal_ll_adc_map_pin( uint8_t module_index, hal_ll_adc_pin_id *index ) { + // Map new pins + hal_ll_adc_hw_specifics_map[module_index].pin = _adc_map[ index->pin_an[module_index] ].pin; + hal_ll_adc_hw_specifics_map[module_index].channel = _adc_map[ index->pin_an[module_index] ].channel; +} + +static hal_ll_adc_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof(hal_ll_adc_handle_register_t)); + static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof(hal_ll_adc_handle_register_t)); + + while( hal_ll_module_count-- ) { + if (hal_ll_adc_get_base_from_hal_handle == hal_ll_adc_hw_specifics_map[hal_ll_module_count].base) { + return &hal_ll_adc_hw_specifics_map[hal_ll_module_count]; + } + } + + return &hal_ll_adc_hw_specifics_map[hal_ll_module_error]; +} + +static inline void adc1_enable_clock() +{ + set_reg_bit( _RCC_AHB2ENR, HAL_LL_ADC1_ENABLE_CLOCK ); +} + +static inline void adc2_enable_clock() +{ + set_reg_bit( _RCC_AHB2ENR, HAL_LL_ADC2_ENABLE_CLOCK ); +} + +static void _hal_ll_adc_enable_clock( uint8_t base ) +{ + switch ( base ) + { + #ifdef ADC_MODULE_1 + case ( hal_ll_adc_module_num(ADC_MODULE_1) ): + adc1_enable_clock(); + break; + #endif + #ifdef ADC_MODULE_2 + case ( hal_ll_adc_module_num(ADC_MODULE_2) ): + adc2_enable_clock(); + break; + #endif + } +} +static void _hal_ll_adc_hw_init( hal_ll_adc_base_handle_t *base, uint32_t resolution ) +{ + static uint32_t wait_loop_index = 0; + static uint32_t *reg; + reg = HAL_LL_ADC_CCIPR; + + // Select ADC clock source. + *reg |= HAL_LL_ADC_CLK_SRC; + + // Exit from deep power down mode. + if ( check_reg_bit( &( base->cr ), HAL_LL_ADC_DEEPPWD_BIT ) ) + { + clear_reg_bit( &( base->cr ), HAL_LL_ADC_DEEPPWD_BIT ); + } + + // Enable voltage regulator. + base->cr &= HAL_LL_ADC_VOLTAGE; + + if ( !( check_reg_bit( &( base->cr ), HAL_LL_ADC_ADVREGEN_BIT ) ) ) + { + set_reg_bit( &( base->cr ), HAL_LL_ADC_ADVREGEN_BIT ); + } + + // Enable ADC interrupts. + set_reg_bit( &( base->ier ), HAL_LL_ADC_ADRDYIE_BIT ); + + // Disable ADC + if ( check_reg_bit( &( base->cr ), HAL_LL_ADC_ADEN_BIT ) ) + { + set_reg_bit( &( base->cr ), HAL_LL_ADC_ADDIS_BIT ); + } + + // Voltage reference enable, ckmode SYSCLK. + reg = HAL_LL_ADC_CCR; + *reg |= (HAL_LL_ADC_CKMODE_MASK | HAL_LL_ADC_VREFEN_MASK); + + // Select calibration mode. + clear_reg_bit( &( base->cr ), HAL_LL_ADC_ADCALDIF_BIT ); + + // Start ADC calibration. + set_reg_bit( &( base->cr ), HAL_LL_ADC_ADCAL_BIT ); + + // Wait for calibration. + while ( check_reg_bit( &( base->cr ), HAL_LL_ADC_ADCAL_BIT ) ); + + // Prescaler. + *reg &= HAL_LL_ADC_PRESCALER; + + // Clear ADRDY bit ADC_ISR by writting 1. + set_reg_bit( &( base->isr ), HAL_LL_ADC_ADRDY_BIT ); + + // Set delay for voltage regulator to be initialized correctly. + wait_loop_index = 10 * ( Get_Fosc_kHz() / 1000 ); + while( wait_loop_index != 0 ) + { + wait_loop_index--; + } + + // Enable ADC. + set_reg_bit( &( base->cr ), HAL_LL_ADC_ADEN_BIT ); + + // ADRDY bit. + while ( !( check_reg_bit( &( base->cr ), HAL_LL_ADC_ADRDY_BIT ) ) ); + + // Resolution. + base->cfgr &= HAL_LL_RESOLUTION_MASK; + base->cfgr |= resolution; + + // Data alignment. + clear_reg_bit( &( base->cfgr ), HAL_LL_ADC_ALIGN_BIT ); + + // Discontinuos mode disabled. + clear_reg_bit( &( base->cfgr ), HAL_LL_ADC_DISCEN_BIT ); + + // Continuos conversion mode. + clear_reg_bit( &( base->cfgr ), HAL_LL_ADC_CONT_BIT ); + + // Regular channel sequence length. + base->sqr1 &= HAL_LL_ADC_CONVERSION; +} + +static void hal_ll_adc_init( hal_ll_adc_hw_specifics_map_t *map ) { + + + hal_ll_gpio_analog_input( hal_ll_gpio_port_base( hal_ll_gpio_port_index( map->pin ) ), + hal_ll_gpio_pin_mask( map->pin ) ); + + _hal_ll_adc_enable_clock( map->module_index ); + + _hal_ll_adc_hw_init((hal_ll_adc_base_handle_t *)map->base, map->resolution); + +} + +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_83/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_83/CMakeLists.cmake new file mode 100644 index 000000000..1e86e51bf --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_83/CMakeLists.cmake @@ -0,0 +1,10 @@ +if(${MCU_NAME} MATCHES "^STM32G441CB$|^STM32G441KB$|^STM32G441RB$|^STM32G441MB$|^STM32G441VB$") + set(adc_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_adc.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_83") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_83") + list(APPEND hal_ll_def_list "STM32G4xx") + list(APPEND hal_ll_def_list "STM32G44xx") + list(APPEND hal_ll_def_list "STM32G441xx") + set(adc_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/adc/hal_ll_adc_pin_map/implementations/doc_ds_83") + list(APPEND hal_ll_def_list "HAL_LL_ADC_RESOLUTION_CMAKE=HAL_LL_ADC_RESOLUTION_12_BIT") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_83/hal_ll_adc.c b/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_83/hal_ll_adc.c new file mode 100644 index 000000000..0c8db6604 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_83/hal_ll_adc.c @@ -0,0 +1,633 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_adc.c + * @brief Low level HAL ADC source file. + */ + +#include "hal_ll_adc.h" +#include "hal_ll_gpio.h" +#include "hal_ll_adc_pin_map.h" + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_adc_get_module_state_address ((hal_ll_adc_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_adc_get_handle (hal_ll_adc_handle_register_t *)hal_ll_adc_get_module_state_address->hal_ll_adc_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_adc_get_base_struct(_handle) ((hal_ll_adc_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_adc_get_base_from_hal_handle ((hal_ll_adc_hw_specifics_map_t *)((hal_ll_adc_handle_register_t *)\ + (((hal_ll_adc_handle_register_t *)(handle))->hal_ll_adc_handle))->hal_ll_adc_handle)->base +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_adc_module_num(_module_num) (_module_num - 1) + +// ADC common registers. + +#define hal_ll_adc_module_num(_module_num) (_module_num - 1) + +#define HAL_LL_ADC_CSR_OFFSET ( 0x300 / 4 ) +#define HAL_LL_ADC_CCR_OFFSET ( 0x308 / 4 ) +#define HAL_LL_ADC_CDR_OFFSET ( 0x30C / 4 ) + + +#define HAL_LL_ADC_APB2ENR_SYSCFGEN 0 +#define HAL_LL_ADC_VREF_ENVR 0 +#define HAL_LL_ADC_ADRDYIE_BIT 0 +#define HAL_LL_ADC_ADEN_BIT 0 +#define HAL_LL_ADC_ADRDY_BIT 0 +#define HAL_LL_ADC_ADDIS_BIT 1 +#define HAL_LL_ADC_EOC_BIT 2 +#define HAL_LL_ADC_ADSTART_BIT 2 +#define HAL_LL_ADC_RESOLUTION_BIT0 3 +#define HAL_LL_ADC_RESOLUTION_BIT1 4 +#define HAL_LL_ADC_VREF_VRR 3 +#define HAL_LL_ADC_ALIGN_BIT 15 + +#define HAL_LL_ADC1_ENABLE_CLOCK 13 +#define HAL_LL_ADC2_ENABLE_CLOCK 13 + +#define HAL_LL_ADC_CONT_BIT 13 +#define HAL_LL_ADC_DISCEN_BIT 16 +#define HAL_LL_ADC_ADVREGEN_BIT 28 +#define HAL_LL_ADC_DEEPPWD_BIT 29 +#define HAL_LL_ADC_ADCALDIF_BIT 30 +#define HAL_LL_ADC_ADCAL_BIT 31 +#define HAL_LL_ADC_PIN_MASK 0xF + +#define HAL_LL_ADC_12BIT_RES 0x00000000ul +#define HAL_LL_ADC_10BIT_RES 0x00000008ul +#define HAL_LL_ADC_8BIT_RES 0x00000010ul +#define HAL_LL_ADC_6BIT_RES 0x00000018ul + +#define ADC_CAL_SINGLE 0x00000000ul +#define ADC_CAL_DIF 0x00000001ul +#define HAL_LL_ADC_CLK_SRC 0xF0000000ul +#define HAL_LL_ADC_VOLTAGE 0xCFFFFFFFul +#define HAL_LL_ADC_CCR 0x50000308ul +#define HAL_LL_ADC_CKMODE_MASK 0x00000000ul +#define HAL_LL_ADC_VREFEN_MASK 0x00400000ul +#define HAL_LL_ADC_CCIPR 0x40021088ul +#define HAL_LL_ADC_PRESCALER 0xFFC3FFFFul +#define HAL_LL_ADC_CONVERSION 0xFFFFFFF0ul + +#define HAL_LL_ADC_CONVERSION_ONE 0x000007C0ul + +#define HAL_LL_MODULE_INDEX_ERROR 0xFFFFFFFFul + +#define HAL_LL_RESOLUTION_MASK 0xFFFFFFE7ul + +#define HAL_LL_ADC_DEFAULT_BASE_ADDRESS 0xFF + + +// -------------------------------------------------------------- PRIVATE TYPES +/*!< @brief Local handle list */ +static hal_ll_adc_handle_register_t hal_ll_module_state[ADC_MODULE_COUNT] = { (handle_t *) NULL, (handle_t *) NULL, false }; + +/** + * Return values + */ +typedef enum +{ + HAL_LL_ADC_SUCCESS = 0, + HAL_LL_ADC_WRONG_PIN, + + HAL_LL_ADC_UNSUPPORTED_RESOLUTION = 1100, + HAL_LL_ADC_UNSUPPORTED_VREF, + HAL_LL_ADC_WRONG_CHANNEL, + HAL_LL_ADC_ERROR = (-1) +} hal_ll_adc_err_t; + +/*!< @brief ADC register structure. */ +typedef struct +{ + uint32_t isr; /* ADC interrupt and status register (ADC_ISR) */ + uint32_t ier; /* ADC interrupt enable register (ADC_IER) */ + uint32_t cr; /* ADC control register (ADC_CR) */ + uint32_t cfgr; /* ADC configuration register (ADC_CFGR) */ + uint32_t cfgr2; /* ADC configuration register (ADC_CFGR) */ + uint32_t smpr1; /* ADC sample time register 1 (ADC_SMPR1) */ + uint32_t smpr2; /* ADC sample time register 1 (ADC_SMPR1) */ + uint32_t __unused1[1]; /* */ + uint32_t tr1; /* ADC watchdog threshold register 1 (ADC_TR1) */ + uint32_t tr2; /* ADC watchdog threshold register 1 (ADC_TR1) */ + uint32_t tr3; /* ADC watchdog threshold register 1 (ADC_TR1) */ + uint32_t __unused2[1]; /* */ + uint32_t sqr1; /* ADC regular sequence register 1 (ADC_SQR1) */ + uint32_t sqr2; /* ADC regular sequence register 1 (ADC_SQR1) */ + uint32_t sqr3; /* ADC regular sequence register 1 (ADC_SQR1) */ + uint32_t sqr4; /* ADC regular sequence register 1 (ADC_SQR1) */ + uint32_t dr; /* ADC regular data register (ADC_DR) */ + uint32_t __unused3[2]; /* */ + uint32_t jsqr; /* ADC injected sequence register (ADC_JSQR) */ + uint32_t __unused4[4]; /* */ + uint32_t ofr1; /* ADC offset y register (ADC_OFRy) */ + uint32_t ofr2; /* ADC offset y register (ADC_OFRy) */ + uint32_t ofr3; /* ADC offset y register (ADC_OFRy) */ + uint32_t ofr4; /* ADC offset y register (ADC_OFRy) */ + uint32_t __unused5[4]; /* */ + uint32_t jdr1; /* ADC injected channel y data register (ADC_JDRy) */ + uint32_t jdr2; /* ADC injected channel y data register (ADC_JDRy) */ + uint32_t jdr3; /* ADC injected channel y data register (ADC_JDRy) */ + uint32_t jdr4; /* ADC injected channel y data register (ADC_JDRy) */ + uint32_t __unused6[4]; /* */ + uint32_t awd2cr; /* ADC analog watchdog 2 configuration register (ADC_AWD2CR) */ + uint32_t awd3cr; /* ADC analog watchdog 2 configuration register (ADC_AWD2CR) */ + uint32_t __unused7[2]; /* */ + uint32_t difsel; /* ADC differential mode selection register (ADC_DIFSEL) */ + uint32_t calfact; /* ADC calibration factors (ADC_CALFACT) */ + uint32_t __unused8[2]; /* */ + uint32_t gcomp; /* ADC Gain compensation Register (ADC_GCOMP) */ + uint32_t csr; /* ADCx common status register (ADCx_CSR) (x = 12 or 345) */ + uint32_t __unused9[1]; /* */ + uint32_t ccr; /* ADCx common control register (ADCx_CCR) (x = 12 or 345) */ + uint32_t __unused10[192]; /* */ + uint32_t cdr; /* ADCx common regular data register for dual mode (ADCx_CDR) (x = 12 or 345) */ + +} hal_ll_adc_base_handle_t; + +/*!< @brief ADC hw specific module values */ +typedef struct +{ + uint16_t pin_an[ADC_MODULE_COUNT]; +} hal_ll_adc_pin_id; + +static hal_ll_adc_hw_specifics_map_t hal_ll_adc_hw_specifics_map[] = +{ + #ifdef ADC_MODULE_1 + {ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF}, + #endif + #ifdef ADC_MODULE_2 + {ADC2_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF}, + #endif + + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF} +}; + +// ------------------------------------------------------------------ VARIABLES + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_adc_handle_register_t *low_level_handle; +static volatile hal_ll_adc_hw_specifics_map_t *hal_ll_adc_hw_specifics_map_local; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Enable ADC module 1 clock. + * @param none + * @return none + */ +static inline void adc1_enable_clock(); +/** + * @brief Enable ADC module 2 clock. + * @param none + * @return none + */ +static inline void adc2_enable_clock(); + + +/** + * @brief Initialize ADC module. + * @param *map - ADC module local map. + * @return None + */ +static void hal_ll_adc_init( hal_ll_adc_hw_specifics_map_t *map ); + +/** + * @brief Check if pins are adequate. + * + * Checks analog pin the user has passed with pre-defined + * pins in ADC pin map. + * + * @param[in] pin - ADC pre-defined pin name. + * @param[in] *index - ADC map index value. + * @return hal_ll_pin_name_t Module index based on pin. + * + * Returns pre-defined module index from pin maps, if pin + * is adequate. + */ +static hal_ll_pin_name_t hal_ll_adc_check_pins( hal_ll_pin_name_t pin, hal_ll_adc_pin_id *index, hal_ll_adc_handle_register_t *handle_map ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and channel values for ADC pin + * + * @param[in] module_index ADC HW module index -- 0,1,2... + * @param[in] *index ADC map index value + * + * @return None + */ +static void hal_ll_adc_map_pin( uint8_t module_index, hal_ll_adc_pin_id *index ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_adc_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_adc_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_adc_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Enable ADC module gate clock. + * @param base - ADC module base address. + * @return None + */ +static void _hal_ll_adc_enable_clock( uint8_t base ); + +/** + * @brief Initialize ADC module. + * @param *base - ADC module base address. + * @param resolution - ADC module resolution. + * @return None + */ +static void _hal_ll_adc_hw_init( hal_ll_adc_base_handle_t *base, uint32_t resolution ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_adc_register_handle(hal_ll_pin_name_t pin, hal_ll_adc_voltage_reference_t vref_input, hal_ll_adc_resolution_t resolution, hal_ll_adc_handle_register_t *handle_map, uint8_t *hal_module_id) +{ + uint16_t pin_check_result; + hal_ll_adc_pin_id index = {HAL_LL_PIN_NC}; + + if ( (pin_check_result = hal_ll_adc_check_pins( pin, &index, handle_map )) == HAL_LL_PIN_NC ) { + return HAL_LL_ADC_WRONG_PIN; + }; + + switch ( resolution ) + { + case HAL_LL_ADC_RESOLUTION_12_BIT: + hal_ll_adc_hw_specifics_map[pin_check_result].resolution = HAL_LL_ADC_12BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_10_BIT: + hal_ll_adc_hw_specifics_map[pin_check_result].resolution = HAL_LL_ADC_10BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_8_BIT: + hal_ll_adc_hw_specifics_map[pin_check_result].resolution = HAL_LL_ADC_8BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_6_BIT: + hal_ll_adc_hw_specifics_map[pin_check_result].resolution = HAL_LL_ADC_6BIT_RES; + break; + default: + return HAL_LL_ADC_UNSUPPORTED_RESOLUTION; + } + + switch ( vref_input ) + { + case HAL_LL_ADC_VREF_EXTERNAL: + break; + + default: + return HAL_LL_ADC_UNSUPPORTED_VREF; + } + + if ( hal_ll_adc_hw_specifics_map[pin_check_result].pin != pin ) + { + hal_ll_adc_map_pin( pin_check_result, &index ); + + handle_map[pin_check_result].init_ll_state = false; + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[pin_check_result].hal_ll_adc_handle = (handle_t *)&hal_ll_adc_hw_specifics_map[pin_check_result].base; + + handle_map[pin_check_result].hal_ll_adc_handle = (handle_t *)&hal_ll_module_state[pin_check_result].hal_ll_adc_handle; + + return HAL_LL_ADC_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_adc( handle_t *handle ) +{ + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + hal_ll_adc_handle_register_t *hal_handle = (hal_ll_adc_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_adc_hw_specifics_map_local->module_index; + + hal_ll_adc_init( hal_ll_adc_hw_specifics_map_local ); + + hal_ll_module_state[pin_check_result].hal_ll_adc_handle = (handle_t *)&hal_ll_adc_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_ADC_SUCCESS; +} + +hal_ll_err_t hal_ll_adc_set_resolution(handle_t *handle, hal_ll_adc_resolution_t resolution) +{ + low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + + low_level_handle->init_ll_state = false; + + switch( resolution ) { + case HAL_LL_ADC_RESOLUTION_12_BIT: + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_12BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_10_BIT: + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_10BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_8_BIT: + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_8BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_6_BIT: + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_6BIT_RES; + break; + + default: + return HAL_LL_ADC_UNSUPPORTED_RESOLUTION; + } + + hal_ll_adc_init( hal_ll_adc_hw_specifics_map_local ); + + low_level_handle->init_ll_state = true; + + return HAL_LL_ADC_SUCCESS; +} + +hal_ll_err_t hal_ll_adc_set_vref_input(handle_t *handle, hal_ll_adc_voltage_reference_t vref_input) +{ + low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + + low_level_handle->init_ll_state = false; + + switch( vref_input ) { + case HAL_LL_ADC_VREF_EXTERNAL: + break; + + default: + return HAL_LL_ADC_UNSUPPORTED_VREF; + } + + hal_ll_adc_init( hal_ll_adc_hw_specifics_map_local ); + + low_level_handle->init_ll_state = true; + + return HAL_LL_ADC_SUCCESS; +} + +void hal_ll_adc_set_vref_value(handle_t *handle, float vref_value) +{ + low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + + hal_ll_adc_hw_specifics_map_local->vref_value = vref_value; +} + +hal_ll_err_t hal_ll_adc_read( handle_t *handle, uint16_t *readDatabuf ) +{ + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_base_handle_t *base = ( hal_ll_adc_base_handle_t * )hal_ll_adc_hw_specifics_map_local->base ; + + while( ( check_reg_bit( &( base->cr ), HAL_LL_ADC_ADSTART_BIT ) ) ); + base->sqr1 &= ~HAL_LL_ADC_CONVERSION_ONE; + base->sqr1 |= ( ( hal_ll_adc_hw_specifics_map_local->channel << 6 ) ); + + Delay_1us(); + + // Start the conversion. + set_reg_bit( &( base->cr ), HAL_LL_ADC_ADSTART_BIT ); + + while ( !( check_reg_bit( &( base->isr ), HAL_LL_ADC_EOC_BIT ) ) ); + // Conversion result from SS3. + *readDatabuf = base->dr; + + return HAL_LL_ADC_SUCCESS; +} + +void hal_ll_adc_close( handle_t *handle ) +{ + hal_ll_adc_hw_specifics_map_t *hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + low_level_handle = hal_ll_adc_get_handle; + + if( hal_ll_adc_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + + hal_ll_adc_hw_specifics_map_local->vref_input = HAL_LL_ADC_VREF_DEFAULT; + hal_ll_adc_hw_specifics_map_local->vref_value = 0; + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_RESOLUTION_12_BIT; + + low_level_handle->hal_ll_adc_handle = NULL; + low_level_handle->hal_drv_adc_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_adc_hw_specifics_map_local->pin = HAL_LL_PIN_NC; + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static hal_ll_pin_name_t hal_ll_adc_check_pins( hal_ll_pin_name_t pin, hal_ll_adc_pin_id *index, hal_ll_adc_handle_register_t *handle_map ) +{ + static const uint16_t adc_map_size = ( sizeof( _adc_map ) / sizeof( hal_ll_adc_pin_map_t ) ); + uint16_t pin_index = 0; + uint8_t index_counter = 0; + uint8_t hal_ll_module_id = 0; + + if ( HAL_LL_PIN_NC == pin ) { + return HAL_LL_PIN_NC; + } + + for ( pin_index = 0; pin_index < adc_map_size; pin_index++ ) + { + if ( pin == _adc_map[pin_index].pin ) + { + // Get module number + hal_ll_module_id = _adc_map[pin_index].module_index; + // Map pin name + index->pin_an[hal_ll_module_id] = pin_index; + + // Check if module is taken + if ( NULL == handle_map[ hal_ll_module_id ].hal_drv_adc_handle ) { + return hal_ll_module_id; + } else if ( ADC_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static void hal_ll_adc_map_pin( uint8_t module_index, hal_ll_adc_pin_id *index ) { + // Map new pins + hal_ll_adc_hw_specifics_map[module_index].pin = _adc_map[ index->pin_an[module_index] ].pin; + hal_ll_adc_hw_specifics_map[module_index].channel = _adc_map[ index->pin_an[module_index] ].channel; +} + +static hal_ll_adc_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof(hal_ll_adc_handle_register_t)); + static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof(hal_ll_adc_handle_register_t)); + + while( hal_ll_module_count-- ) { + if (hal_ll_adc_get_base_from_hal_handle == hal_ll_adc_hw_specifics_map[hal_ll_module_count].base) { + return &hal_ll_adc_hw_specifics_map[hal_ll_module_count]; + } + } + + return &hal_ll_adc_hw_specifics_map[hal_ll_module_error]; +} +static inline void adc1_enable_clock() +{ + set_reg_bit( _RCC_AHB2ENR, HAL_LL_ADC1_ENABLE_CLOCK ); +} +static inline void adc2_enable_clock() +{ + set_reg_bit( _RCC_AHB2ENR, HAL_LL_ADC2_ENABLE_CLOCK ); +} + +static void _hal_ll_adc_enable_clock( uint8_t base ) +{ + switch ( base ) + { + #ifdef ADC_MODULE_1 + case ( hal_ll_adc_module_num(ADC_MODULE_1) ): + adc1_enable_clock(); + break; + #endif + #ifdef ADC_MODULE_2 + case ( hal_ll_adc_module_num(ADC_MODULE_2) ): + adc2_enable_clock(); + break; + #endif + } +} +static void _hal_ll_adc_hw_init( hal_ll_adc_base_handle_t *base, uint32_t resolution ) +{ + static uint32_t wait_loop_index = 0; + static uint32_t *reg; + reg = HAL_LL_ADC_CCIPR; + + // Select ADC clock source. + *reg |= HAL_LL_ADC_CLK_SRC; + + // Exit from deep power down mode. + if ( check_reg_bit( &( base->cr ), HAL_LL_ADC_DEEPPWD_BIT ) ) + { + clear_reg_bit( &( base->cr ), HAL_LL_ADC_DEEPPWD_BIT ); + } + + // Enable voltage regulator. + base->cr &= HAL_LL_ADC_VOLTAGE; + + if ( !( check_reg_bit( &( base->cr ), HAL_LL_ADC_ADVREGEN_BIT ) ) ) + { + set_reg_bit( &( base->cr ), HAL_LL_ADC_ADVREGEN_BIT ); + } + + // Enable ADC interrupts. + set_reg_bit( &( base->ier ), HAL_LL_ADC_ADRDYIE_BIT ); + + // Disable ADC + if ( check_reg_bit( &( base->cr ), HAL_LL_ADC_ADEN_BIT ) ) + { + set_reg_bit( &( base->cr ), HAL_LL_ADC_ADDIS_BIT ); + } + + // Voltage reference enable, ckmode SYSCLK. + reg = HAL_LL_ADC_CCR; + *reg |= (HAL_LL_ADC_CKMODE_MASK | HAL_LL_ADC_VREFEN_MASK); + + // Select calibration mode. + clear_reg_bit( &( base->cr ), HAL_LL_ADC_ADCALDIF_BIT ); + + // Start ADC calibration. + set_reg_bit( &( base->cr ), HAL_LL_ADC_ADCAL_BIT ); + + // Wait for calibration. + while ( check_reg_bit( &( base->cr ), HAL_LL_ADC_ADCAL_BIT ) ); + + // Prescaler. + *reg &= HAL_LL_ADC_PRESCALER; + + // Clear ADRDY bit ADC_ISR by writting 1. + set_reg_bit( &( base->isr ), HAL_LL_ADC_ADRDY_BIT ); + + // Set delay for voltage regulator to be initialized correctly. + wait_loop_index = 10 * ( Get_Fosc_kHz() / 1000 ); + while( wait_loop_index != 0 ) + { + wait_loop_index--; + } + + // Enable ADC. + set_reg_bit( &( base->cr ), HAL_LL_ADC_ADEN_BIT ); + + // ADRDY bit. + while ( !( check_reg_bit( &( base->cr ), HAL_LL_ADC_ADRDY_BIT ) ) ); + + // Resolution. + base->cfgr &= HAL_LL_RESOLUTION_MASK; + base->cfgr |= resolution; + + // Data alignment. + clear_reg_bit( &( base->cfgr ), HAL_LL_ADC_ALIGN_BIT ); + + // Discontinuos mode disabled. + clear_reg_bit( &( base->cfgr ), HAL_LL_ADC_DISCEN_BIT ); + + // Continuos conversion mode. + clear_reg_bit( &( base->cfgr ), HAL_LL_ADC_CONT_BIT ); + + // Regular channel sequence length. + base->sqr1 &= HAL_LL_ADC_CONVERSION; +} + +static void hal_ll_adc_init( hal_ll_adc_hw_specifics_map_t *map ) { + + + hal_ll_gpio_analog_input( hal_ll_gpio_port_base( hal_ll_gpio_port_index( map->pin ) ), + hal_ll_gpio_pin_mask( map->pin ) ); + + _hal_ll_adc_enable_clock( map->module_index ); + + _hal_ll_adc_hw_init((hal_ll_adc_base_handle_t *)map->base, map->resolution); + +} + + +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_84/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_84/CMakeLists.cmake new file mode 100644 index 000000000..2fcf90a23 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_84/CMakeLists.cmake @@ -0,0 +1,10 @@ +if(${MCU_NAME} MATCHES "^STM32G473CB$|^STM32G473MB$|^STM32G473PB$|^STM32G473RB$|^STM32G473VB$|^STM32G473QB$|^STM32G473CC$|^STM32G473MC$|^STM32G473PC$|^STM32G473RC$|^STM32G473VC$|^STM32G473QC$|^STM32G473CE$|^STM32G473ME$|^STM32G473PE$|^STM32G473RE$|^STM32G473VE$|^STM32G473QE$") + set(adc_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_adc.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_84") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_84") + list(APPEND hal_ll_def_list "STM32G4xx") + list(APPEND hal_ll_def_list "STM32G47xx") + list(APPEND hal_ll_def_list "STM32G473xx") + set(adc_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/adc/hal_ll_adc_pin_map/implementations/doc_ds_84") + list(APPEND hal_ll_def_list "HAL_LL_ADC_RESOLUTION_CMAKE=HAL_LL_ADC_RESOLUTION_12_BIT") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_84/hal_ll_adc.c b/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_84/hal_ll_adc.c new file mode 100644 index 000000000..616f145a8 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_84/hal_ll_adc.c @@ -0,0 +1,694 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_adc.c + * @brief Low level HAL ADC source file. + */ + +#include "hal_ll_adc.h" +#include "hal_ll_gpio.h" +#include "hal_ll_adc_pin_map.h" + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_adc_get_module_state_address ((hal_ll_adc_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_adc_get_handle (hal_ll_adc_handle_register_t *)hal_ll_adc_get_module_state_address->hal_ll_adc_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_adc_get_base_struct(_handle) ((hal_ll_adc_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_adc_get_base_from_hal_handle ((hal_ll_adc_hw_specifics_map_t *)((hal_ll_adc_handle_register_t *)\ + (((hal_ll_adc_handle_register_t *)(handle))->hal_ll_adc_handle))->hal_ll_adc_handle)->base +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_adc_module_num(_module_num) (_module_num - 1) + +// ADC common registers. + +#define hal_ll_adc_module_num(_module_num) (_module_num - 1) + +#define HAL_LL_ADC_CSR_OFFSET ( 0x300 / 4 ) +#define HAL_LL_ADC_CCR_OFFSET ( 0x308 / 4 ) +#define HAL_LL_ADC_CDR_OFFSET ( 0x30C / 4 ) + + +#define HAL_LL_ADC_APB2ENR_SYSCFGEN 0 +#define HAL_LL_ADC_VREF_ENVR 0 +#define HAL_LL_ADC_ADRDYIE_BIT 0 +#define HAL_LL_ADC_ADEN_BIT 0 +#define HAL_LL_ADC_ADRDY_BIT 0 +#define HAL_LL_ADC_ADDIS_BIT 1 +#define HAL_LL_ADC_EOC_BIT 2 +#define HAL_LL_ADC_ADSTART_BIT 2 +#define HAL_LL_ADC_RESOLUTION_BIT0 3 +#define HAL_LL_ADC_RESOLUTION_BIT1 4 +#define HAL_LL_ADC_VREF_VRR 3 +#define HAL_LL_ADC_ALIGN_BIT 15 + +#define HAL_LL_ADC1_ENABLE_CLOCK 13 +#define HAL_LL_ADC2_ENABLE_CLOCK 13 +#define HAL_LL_ADC3_ENABLE_CLOCK 14 +#define HAL_LL_ADC4_ENABLE_CLOCK 14 +#define HAL_LL_ADC5_ENABLE_CLOCK 14 + +#define HAL_LL_ADC_CONT_BIT 13 +#define HAL_LL_ADC_DISCEN_BIT 16 +#define HAL_LL_ADC_ADVREGEN_BIT 28 +#define HAL_LL_ADC_DEEPPWD_BIT 29 +#define HAL_LL_ADC_ADCALDIF_BIT 30 +#define HAL_LL_ADC_ADCAL_BIT 31 +#define HAL_LL_ADC_PIN_MASK 0xF + +#define HAL_LL_ADC_12BIT_RES 0x00000000ul +#define HAL_LL_ADC_10BIT_RES 0x00000008ul +#define HAL_LL_ADC_8BIT_RES 0x00000010ul +#define HAL_LL_ADC_6BIT_RES 0x00000018ul + +#define ADC_CAL_SINGLE 0x00000000ul +#define ADC_CAL_DIF 0x00000001ul +#define HAL_LL_ADC_CLK_SRC 0xF0000000ul +#define HAL_LL_ADC_VOLTAGE 0xCFFFFFFFul +#define HAL_LL_ADC_CCR 0x50000308ul +#define HAL_LL_ADC_CKMODE_MASK 0x00000000ul +#define HAL_LL_ADC_VREFEN_MASK 0x00400000ul +#define HAL_LL_ADC_CCIPR 0x40021088ul +#define HAL_LL_ADC_PRESCALER 0xFFC3FFFFul +#define HAL_LL_ADC_CONVERSION 0xFFFFFFF0ul + +#define HAL_LL_ADC_CONVERSION_ONE 0x000007C0ul + +#define HAL_LL_MODULE_INDEX_ERROR 0xFFFFFFFFul + +#define HAL_LL_RESOLUTION_MASK 0xFFFFFFE7ul + +#define HAL_LL_ADC_DEFAULT_BASE_ADDRESS 0xFF + + +// -------------------------------------------------------------- PRIVATE TYPES +/*!< @brief Local handle list */ +static hal_ll_adc_handle_register_t hal_ll_module_state[ADC_MODULE_COUNT] = { (handle_t *) NULL, (handle_t *) NULL, false }; + +/** + * Return values + */ +typedef enum +{ + HAL_LL_ADC_SUCCESS = 0, + HAL_LL_ADC_WRONG_PIN, + + HAL_LL_ADC_UNSUPPORTED_RESOLUTION = 1100, + HAL_LL_ADC_UNSUPPORTED_VREF, + HAL_LL_ADC_WRONG_CHANNEL, + HAL_LL_ADC_ERROR = (-1) +} hal_ll_adc_err_t; + +/*!< @brief ADC register structure. */ +typedef struct +{ + uint32_t isr; /* ADC interrupt and status register (ADC_ISR) */ + uint32_t ier; /* ADC interrupt enable register (ADC_IER) */ + uint32_t cr; /* ADC control register (ADC_CR) */ + uint32_t cfgr; /* ADC configuration register (ADC_CFGR) */ + uint32_t cfgr2; /* ADC configuration register (ADC_CFGR) */ + uint32_t smpr1; /* ADC sample time register 1 (ADC_SMPR1) */ + uint32_t smpr2; /* ADC sample time register 1 (ADC_SMPR1) */ + uint32_t __unused1[1]; /* */ + uint32_t tr1; /* ADC watchdog threshold register 1 (ADC_TR1) */ + uint32_t tr2; /* ADC watchdog threshold register 1 (ADC_TR1) */ + uint32_t tr3; /* ADC watchdog threshold register 1 (ADC_TR1) */ + uint32_t __unused2[1]; /* */ + uint32_t sqr1; /* ADC regular sequence register 1 (ADC_SQR1) */ + uint32_t sqr2; /* ADC regular sequence register 1 (ADC_SQR1) */ + uint32_t sqr3; /* ADC regular sequence register 1 (ADC_SQR1) */ + uint32_t sqr4; /* ADC regular sequence register 1 (ADC_SQR1) */ + uint32_t dr; /* ADC regular data register (ADC_DR) */ + uint32_t __unused3[2]; /* */ + uint32_t jsqr; /* ADC injected sequence register (ADC_JSQR) */ + uint32_t __unused4[4]; /* */ + uint32_t ofr1; /* ADC offset y register (ADC_OFRy) */ + uint32_t ofr2; /* ADC offset y register (ADC_OFRy) */ + uint32_t ofr3; /* ADC offset y register (ADC_OFRy) */ + uint32_t ofr4; /* ADC offset y register (ADC_OFRy) */ + uint32_t __unused5[4]; /* */ + uint32_t jdr1; /* ADC injected channel y data register (ADC_JDRy) */ + uint32_t jdr2; /* ADC injected channel y data register (ADC_JDRy) */ + uint32_t jdr3; /* ADC injected channel y data register (ADC_JDRy) */ + uint32_t jdr4; /* ADC injected channel y data register (ADC_JDRy) */ + uint32_t __unused6[4]; /* */ + uint32_t awd2cr; /* ADC analog watchdog 2 configuration register (ADC_AWD2CR) */ + uint32_t awd3cr; /* ADC analog watchdog 2 configuration register (ADC_AWD2CR) */ + uint32_t __unused7[2]; /* */ + uint32_t difsel; /* ADC differential mode selection register (ADC_DIFSEL) */ + uint32_t calfact; /* ADC calibration factors (ADC_CALFACT) */ + uint32_t __unused8[2]; /* */ + uint32_t gcomp; /* ADC Gain compensation Register (ADC_GCOMP) */ + uint32_t csr; /* ADCx common status register (ADCx_CSR) (x = 12 or 345) */ + uint32_t __unused9[1]; /* */ + uint32_t ccr; /* ADCx common control register (ADCx_CCR) (x = 12 or 345) */ + uint32_t __unused10[192]; /* */ + uint32_t cdr; /* ADCx common regular data register for dual mode (ADCx_CDR) (x = 12 or 345) */ + +} hal_ll_adc_base_handle_t; + +/*!< @brief ADC hw specific module values */ +typedef struct +{ + uint16_t pin_an[ADC_MODULE_COUNT]; +} hal_ll_adc_pin_id; + +static hal_ll_adc_hw_specifics_map_t hal_ll_adc_hw_specifics_map[] = +{ + #ifdef ADC_MODULE_1 + {ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF}, + #endif + #ifdef ADC_MODULE_2 + {ADC2_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF}, + #endif + #ifdef ADC_MODULE_3 + {ADC3_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF}, + #endif + #ifdef ADC_MODULE_4 + {ADC4_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_4), HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF}, + #endif + #ifdef ADC_MODULE_5 + {ADC5_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_5), HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF}, + #endif + + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF} +}; + +// ------------------------------------------------------------------ VARIABLES + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_adc_handle_register_t *low_level_handle; +static volatile hal_ll_adc_hw_specifics_map_t *hal_ll_adc_hw_specifics_map_local; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Enable ADC module 1 clock. + * @param none + * @return none + */ +static inline void adc1_enable_clock(); +/** + * @brief Enable ADC module 2 clock. + * @param none + * @return none + */ +static inline void adc2_enable_clock(); +/** + * @brief Enable ADC module 3 clock. + * @param none + * @return none + */ +static inline void adc3_enable_clock(); +/** + * @brief Enable ADC module 4 clock. + * @param none + * @return none + */ +static inline void adc4_enable_clock(); +/** + * @brief Enable ADC module 5 clock. + * @param none + * @return none + */ +static inline void adc5_enable_clock(); + + +/** + * @brief Initialize ADC module. + * @param *map - ADC module local map. + * @return None + */ +static void hal_ll_adc_init( hal_ll_adc_hw_specifics_map_t *map ); + +/** + * @brief Check if pins are adequate. + * + * Checks analog pin the user has passed with pre-defined + * pins in ADC pin map. + * + * @param[in] pin - ADC pre-defined pin name. + * @param[in] *index - ADC map index value. + * @return hal_ll_pin_name_t Module index based on pin. + * + * Returns pre-defined module index from pin maps, if pin + * is adequate. + */ +static hal_ll_pin_name_t hal_ll_adc_check_pins( hal_ll_pin_name_t pin, hal_ll_adc_pin_id *index, hal_ll_adc_handle_register_t *handle_map ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and channel values for ADC pin + * + * @param[in] module_index ADC HW module index -- 0,1,2... + * @param[in] *index ADC map index value + * + * @return None + */ +static void hal_ll_adc_map_pin( uint8_t module_index, hal_ll_adc_pin_id *index ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_adc_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_adc_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_adc_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Enable ADC module gate clock. + * @param base - ADC module base address. + * @return None + */ +static void _hal_ll_adc_enable_clock( uint8_t base ); + +/** + * @brief Initialize ADC module. + * @param *base - ADC module base address. + * @param resolution - ADC module resolution. + * @return None + */ +static void _hal_ll_adc_hw_init( hal_ll_adc_base_handle_t *base, uint32_t resolution ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_adc_register_handle(hal_ll_pin_name_t pin, hal_ll_adc_voltage_reference_t vref_input, hal_ll_adc_resolution_t resolution, hal_ll_adc_handle_register_t *handle_map, uint8_t *hal_module_id) +{ + uint16_t pin_check_result; + hal_ll_adc_pin_id index = {HAL_LL_PIN_NC}; + + if ( (pin_check_result = hal_ll_adc_check_pins( pin, &index, handle_map )) == HAL_LL_PIN_NC ) { + return HAL_LL_ADC_WRONG_PIN; + }; + + switch ( resolution ) + { + case HAL_LL_ADC_RESOLUTION_12_BIT: + hal_ll_adc_hw_specifics_map[pin_check_result].resolution = HAL_LL_ADC_12BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_10_BIT: + hal_ll_adc_hw_specifics_map[pin_check_result].resolution = HAL_LL_ADC_10BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_8_BIT: + hal_ll_adc_hw_specifics_map[pin_check_result].resolution = HAL_LL_ADC_8BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_6_BIT: + hal_ll_adc_hw_specifics_map[pin_check_result].resolution = HAL_LL_ADC_6BIT_RES; + break; + default: + return HAL_LL_ADC_UNSUPPORTED_RESOLUTION; + } + + switch ( vref_input ) + { + case HAL_LL_ADC_VREF_EXTERNAL: + break; + + default: + return HAL_LL_ADC_UNSUPPORTED_VREF; + } + + if ( hal_ll_adc_hw_specifics_map[pin_check_result].pin != pin ) + { + hal_ll_adc_map_pin( pin_check_result, &index ); + + handle_map[pin_check_result].init_ll_state = false; + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[pin_check_result].hal_ll_adc_handle = (handle_t *)&hal_ll_adc_hw_specifics_map[pin_check_result].base; + + handle_map[pin_check_result].hal_ll_adc_handle = (handle_t *)&hal_ll_module_state[pin_check_result].hal_ll_adc_handle; + + return HAL_LL_ADC_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_adc( handle_t *handle ) +{ + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + hal_ll_adc_handle_register_t *hal_handle = (hal_ll_adc_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_adc_hw_specifics_map_local->module_index; + + hal_ll_adc_init( hal_ll_adc_hw_specifics_map_local ); + + hal_ll_module_state[pin_check_result].hal_ll_adc_handle = (handle_t *)&hal_ll_adc_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_ADC_SUCCESS; +} + +hal_ll_err_t hal_ll_adc_set_resolution(handle_t *handle, hal_ll_adc_resolution_t resolution) +{ + low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + + low_level_handle->init_ll_state = false; + + switch( resolution ) { + case HAL_LL_ADC_RESOLUTION_12_BIT: + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_12BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_10_BIT: + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_10BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_8_BIT: + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_8BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_6_BIT: + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_6BIT_RES; + break; + + default: + return HAL_LL_ADC_UNSUPPORTED_RESOLUTION; + } + + hal_ll_adc_init( hal_ll_adc_hw_specifics_map_local ); + + low_level_handle->init_ll_state = true; + + return HAL_LL_ADC_SUCCESS; +} + +hal_ll_err_t hal_ll_adc_set_vref_input(handle_t *handle, hal_ll_adc_voltage_reference_t vref_input) +{ + low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + + low_level_handle->init_ll_state = false; + + switch( vref_input ) { + case HAL_LL_ADC_VREF_EXTERNAL: + break; + + default: + return HAL_LL_ADC_UNSUPPORTED_VREF; + } + + hal_ll_adc_init( hal_ll_adc_hw_specifics_map_local ); + + low_level_handle->init_ll_state = true; + + return HAL_LL_ADC_SUCCESS; +} + +void hal_ll_adc_set_vref_value(handle_t *handle, float vref_value) +{ + low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + + hal_ll_adc_hw_specifics_map_local->vref_value = vref_value; +} + +hal_ll_err_t hal_ll_adc_read( handle_t *handle, uint16_t *readDatabuf ) +{ + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_base_handle_t *base = ( hal_ll_adc_base_handle_t * )hal_ll_adc_hw_specifics_map_local->base ; + + while( ( check_reg_bit( &( base->cr ), HAL_LL_ADC_ADSTART_BIT ) ) ); + base->sqr1 &= ~HAL_LL_ADC_CONVERSION_ONE; + base->sqr1 |= ( ( hal_ll_adc_hw_specifics_map_local->channel << 6 ) ); + + Delay_1us(); + + // Start the conversion. + set_reg_bit( &( base->cr ), HAL_LL_ADC_ADSTART_BIT ); + + while ( !( check_reg_bit( &( base->isr ), HAL_LL_ADC_EOC_BIT ) ) ); + // Conversion result from SS3. + *readDatabuf = base->dr; + + return HAL_LL_ADC_SUCCESS; +} + +void hal_ll_adc_close( handle_t *handle ) +{ + hal_ll_adc_hw_specifics_map_t *hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + low_level_handle = hal_ll_adc_get_handle; + + if( hal_ll_adc_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + + hal_ll_adc_hw_specifics_map_local->vref_input = HAL_LL_ADC_VREF_DEFAULT; + hal_ll_adc_hw_specifics_map_local->vref_value = 0; + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_RESOLUTION_12_BIT; + + low_level_handle->hal_ll_adc_handle = NULL; + low_level_handle->hal_drv_adc_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_adc_hw_specifics_map_local->pin = HAL_LL_PIN_NC; + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static hal_ll_pin_name_t hal_ll_adc_check_pins( hal_ll_pin_name_t pin, hal_ll_adc_pin_id *index, hal_ll_adc_handle_register_t *handle_map ) +{ + static const uint16_t adc_map_size = ( sizeof( _adc_map ) / sizeof( hal_ll_adc_pin_map_t ) ); + uint16_t pin_index = 0; + uint8_t index_counter = 0; + uint8_t hal_ll_module_id = 0; + + if ( HAL_LL_PIN_NC == pin ) { + return HAL_LL_PIN_NC; + } + + for ( pin_index = 0; pin_index < adc_map_size; pin_index++ ) + { + if ( pin == _adc_map[pin_index].pin ) + { + // Get module number + hal_ll_module_id = _adc_map[pin_index].module_index; + // Map pin name + index->pin_an[hal_ll_module_id] = pin_index; + + // Check if module is taken + if ( NULL == handle_map[ hal_ll_module_id ].hal_drv_adc_handle ) { + return hal_ll_module_id; + } else if ( ADC_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static void hal_ll_adc_map_pin( uint8_t module_index, hal_ll_adc_pin_id *index ) { + // Map new pins + hal_ll_adc_hw_specifics_map[module_index].pin = _adc_map[ index->pin_an[module_index] ].pin; + hal_ll_adc_hw_specifics_map[module_index].channel = _adc_map[ index->pin_an[module_index] ].channel; +} + +static hal_ll_adc_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof(hal_ll_adc_handle_register_t)); + static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof(hal_ll_adc_handle_register_t)); + + while( hal_ll_module_count-- ) { + if (hal_ll_adc_get_base_from_hal_handle == hal_ll_adc_hw_specifics_map[hal_ll_module_count].base) { + return &hal_ll_adc_hw_specifics_map[hal_ll_module_count]; + } + } + + return &hal_ll_adc_hw_specifics_map[hal_ll_module_error]; +} +static inline void adc1_enable_clock() +{ + set_reg_bit( _RCC_AHB2ENR, HAL_LL_ADC1_ENABLE_CLOCK ); +} +static inline void adc2_enable_clock() +{ + set_reg_bit( _RCC_AHB2ENR, HAL_LL_ADC2_ENABLE_CLOCK ); +} +static inline void adc3_enable_clock() +{ + set_reg_bit( _RCC_AHB2ENR, HAL_LL_ADC3_ENABLE_CLOCK ); +} +static inline void adc4_enable_clock() +{ + set_reg_bit( _RCC_AHB2ENR, HAL_LL_ADC4_ENABLE_CLOCK ); +} +static inline void adc5_enable_clock() +{ + set_reg_bit( _RCC_AHB2ENR, HAL_LL_ADC5_ENABLE_CLOCK ); +} + +static void _hal_ll_adc_enable_clock( uint8_t base ) +{ + switch ( base ) + { + #ifdef ADC_MODULE_1 + case ( hal_ll_adc_module_num(ADC_MODULE_1) ): + adc1_enable_clock(); + break; + #endif + #ifdef ADC_MODULE_2 + case ( hal_ll_adc_module_num(ADC_MODULE_2) ): + adc2_enable_clock(); + break; + #endif + #ifdef ADC_MODULE_3 + case ( hal_ll_adc_module_num(ADC_MODULE_3) ): + adc3_enable_clock(); + break; + #endif + #ifdef ADC_MODULE_4 + case ( hal_ll_adc_module_num(ADC_MODULE_4) ): + adc4_enable_clock(); + break; + #endif + #ifdef ADC_MODULE_5 + case ( hal_ll_adc_module_num(ADC_MODULE_5) ): + adc5_enable_clock(); + break; + #endif + } +} +static void _hal_ll_adc_hw_init( hal_ll_adc_base_handle_t *base, uint32_t resolution ) +{ + static uint32_t wait_loop_index = 0; + static uint32_t *reg; + reg = HAL_LL_ADC_CCIPR; + + // Select ADC clock source. + *reg |= HAL_LL_ADC_CLK_SRC; + + // Exit from deep power down mode. + if ( check_reg_bit( &( base->cr ), HAL_LL_ADC_DEEPPWD_BIT ) ) + { + clear_reg_bit( &( base->cr ), HAL_LL_ADC_DEEPPWD_BIT ); + } + + // Enable voltage regulator. + base->cr &= HAL_LL_ADC_VOLTAGE; + + if ( !( check_reg_bit( &( base->cr ), HAL_LL_ADC_ADVREGEN_BIT ) ) ) + { + set_reg_bit( &( base->cr ), HAL_LL_ADC_ADVREGEN_BIT ); + } + + // Enable ADC interrupts. + set_reg_bit( &( base->ier ), HAL_LL_ADC_ADRDYIE_BIT ); + + // Disable ADC + if ( check_reg_bit( &( base->cr ), HAL_LL_ADC_ADEN_BIT ) ) + { + set_reg_bit( &( base->cr ), HAL_LL_ADC_ADDIS_BIT ); + } + + // Voltage reference enable, ckmode SYSCLK. + reg = HAL_LL_ADC_CCR; + *reg |= (HAL_LL_ADC_CKMODE_MASK | HAL_LL_ADC_VREFEN_MASK); + + // Select calibration mode. + clear_reg_bit( &( base->cr ), HAL_LL_ADC_ADCALDIF_BIT ); + + // Start ADC calibration. + set_reg_bit( &( base->cr ), HAL_LL_ADC_ADCAL_BIT ); + + // Wait for calibration. + while ( check_reg_bit( &( base->cr ), HAL_LL_ADC_ADCAL_BIT ) ); + + // Prescaler. + *reg &= HAL_LL_ADC_PRESCALER; + + // Clear ADRDY bit ADC_ISR by writting 1. + set_reg_bit( &( base->isr ), HAL_LL_ADC_ADRDY_BIT ); + + // Set delay for voltage regulator to be initialized correctly. + wait_loop_index = 10 * ( Get_Fosc_kHz() / 1000 ); + while( wait_loop_index != 0 ) + { + wait_loop_index--; + } + + // Enable ADC. + set_reg_bit( &( base->cr ), HAL_LL_ADC_ADEN_BIT ); + + // ADRDY bit. + while ( !( check_reg_bit( &( base->cr ), HAL_LL_ADC_ADRDY_BIT ) ) ); + + // Resolution. + base->cfgr &= HAL_LL_RESOLUTION_MASK; + base->cfgr |= resolution; + + // Data alignment. + clear_reg_bit( &( base->cfgr ), HAL_LL_ADC_ALIGN_BIT ); + + // Discontinuos mode disabled. + clear_reg_bit( &( base->cfgr ), HAL_LL_ADC_DISCEN_BIT ); + + // Continuos conversion mode. + clear_reg_bit( &( base->cfgr ), HAL_LL_ADC_CONT_BIT ); + + // Regular channel sequence length. + base->sqr1 &= HAL_LL_ADC_CONVERSION; +} + +static void hal_ll_adc_init( hal_ll_adc_hw_specifics_map_t *map ) { + + + hal_ll_gpio_analog_input( hal_ll_gpio_port_base( hal_ll_gpio_port_index( map->pin ) ), + hal_ll_gpio_pin_mask( map->pin ) ); + + _hal_ll_adc_enable_clock( map->module_index ); + + _hal_ll_adc_hw_init((hal_ll_adc_base_handle_t *)map->base, map->resolution); + +} + + +// ------------------------------------------------------------------------- END + + + + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_85/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_85/CMakeLists.cmake new file mode 100644 index 000000000..e0070500b --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_85/CMakeLists.cmake @@ -0,0 +1,10 @@ +if(${MCU_NAME} MATCHES "^STM32G474CB$|^STM32G474MB$|^STM32G474RB$|^STM32G474VB$|^STM32G474QB$|^STM32G474PB$|^STM32G474CC$|^STM32G474MC$|^STM32G474RC$|^STM32G474VC$|^STM32G474QC$|^STM32G474PC$|^STM32G474CE$|^STM32G474ME$|^STM32G474RE$|^STM32G474VE$|^STM32G474QE$|^STM32G474PE$") + set(adc_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_adc.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_85") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_85") + list(APPEND hal_ll_def_list "STM32G4xx") + list(APPEND hal_ll_def_list "STM32G47xx") + list(APPEND hal_ll_def_list "STM32G474xx") + set(adc_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/adc/hal_ll_adc_pin_map/implementations/doc_ds_85") + list(APPEND hal_ll_def_list "HAL_LL_ADC_RESOLUTION_CMAKE=HAL_LL_ADC_RESOLUTION_12_BIT") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_85/hal_ll_adc.c b/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_85/hal_ll_adc.c new file mode 100644 index 000000000..616f145a8 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_85/hal_ll_adc.c @@ -0,0 +1,694 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_adc.c + * @brief Low level HAL ADC source file. + */ + +#include "hal_ll_adc.h" +#include "hal_ll_gpio.h" +#include "hal_ll_adc_pin_map.h" + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_adc_get_module_state_address ((hal_ll_adc_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_adc_get_handle (hal_ll_adc_handle_register_t *)hal_ll_adc_get_module_state_address->hal_ll_adc_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_adc_get_base_struct(_handle) ((hal_ll_adc_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_adc_get_base_from_hal_handle ((hal_ll_adc_hw_specifics_map_t *)((hal_ll_adc_handle_register_t *)\ + (((hal_ll_adc_handle_register_t *)(handle))->hal_ll_adc_handle))->hal_ll_adc_handle)->base +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_adc_module_num(_module_num) (_module_num - 1) + +// ADC common registers. + +#define hal_ll_adc_module_num(_module_num) (_module_num - 1) + +#define HAL_LL_ADC_CSR_OFFSET ( 0x300 / 4 ) +#define HAL_LL_ADC_CCR_OFFSET ( 0x308 / 4 ) +#define HAL_LL_ADC_CDR_OFFSET ( 0x30C / 4 ) + + +#define HAL_LL_ADC_APB2ENR_SYSCFGEN 0 +#define HAL_LL_ADC_VREF_ENVR 0 +#define HAL_LL_ADC_ADRDYIE_BIT 0 +#define HAL_LL_ADC_ADEN_BIT 0 +#define HAL_LL_ADC_ADRDY_BIT 0 +#define HAL_LL_ADC_ADDIS_BIT 1 +#define HAL_LL_ADC_EOC_BIT 2 +#define HAL_LL_ADC_ADSTART_BIT 2 +#define HAL_LL_ADC_RESOLUTION_BIT0 3 +#define HAL_LL_ADC_RESOLUTION_BIT1 4 +#define HAL_LL_ADC_VREF_VRR 3 +#define HAL_LL_ADC_ALIGN_BIT 15 + +#define HAL_LL_ADC1_ENABLE_CLOCK 13 +#define HAL_LL_ADC2_ENABLE_CLOCK 13 +#define HAL_LL_ADC3_ENABLE_CLOCK 14 +#define HAL_LL_ADC4_ENABLE_CLOCK 14 +#define HAL_LL_ADC5_ENABLE_CLOCK 14 + +#define HAL_LL_ADC_CONT_BIT 13 +#define HAL_LL_ADC_DISCEN_BIT 16 +#define HAL_LL_ADC_ADVREGEN_BIT 28 +#define HAL_LL_ADC_DEEPPWD_BIT 29 +#define HAL_LL_ADC_ADCALDIF_BIT 30 +#define HAL_LL_ADC_ADCAL_BIT 31 +#define HAL_LL_ADC_PIN_MASK 0xF + +#define HAL_LL_ADC_12BIT_RES 0x00000000ul +#define HAL_LL_ADC_10BIT_RES 0x00000008ul +#define HAL_LL_ADC_8BIT_RES 0x00000010ul +#define HAL_LL_ADC_6BIT_RES 0x00000018ul + +#define ADC_CAL_SINGLE 0x00000000ul +#define ADC_CAL_DIF 0x00000001ul +#define HAL_LL_ADC_CLK_SRC 0xF0000000ul +#define HAL_LL_ADC_VOLTAGE 0xCFFFFFFFul +#define HAL_LL_ADC_CCR 0x50000308ul +#define HAL_LL_ADC_CKMODE_MASK 0x00000000ul +#define HAL_LL_ADC_VREFEN_MASK 0x00400000ul +#define HAL_LL_ADC_CCIPR 0x40021088ul +#define HAL_LL_ADC_PRESCALER 0xFFC3FFFFul +#define HAL_LL_ADC_CONVERSION 0xFFFFFFF0ul + +#define HAL_LL_ADC_CONVERSION_ONE 0x000007C0ul + +#define HAL_LL_MODULE_INDEX_ERROR 0xFFFFFFFFul + +#define HAL_LL_RESOLUTION_MASK 0xFFFFFFE7ul + +#define HAL_LL_ADC_DEFAULT_BASE_ADDRESS 0xFF + + +// -------------------------------------------------------------- PRIVATE TYPES +/*!< @brief Local handle list */ +static hal_ll_adc_handle_register_t hal_ll_module_state[ADC_MODULE_COUNT] = { (handle_t *) NULL, (handle_t *) NULL, false }; + +/** + * Return values + */ +typedef enum +{ + HAL_LL_ADC_SUCCESS = 0, + HAL_LL_ADC_WRONG_PIN, + + HAL_LL_ADC_UNSUPPORTED_RESOLUTION = 1100, + HAL_LL_ADC_UNSUPPORTED_VREF, + HAL_LL_ADC_WRONG_CHANNEL, + HAL_LL_ADC_ERROR = (-1) +} hal_ll_adc_err_t; + +/*!< @brief ADC register structure. */ +typedef struct +{ + uint32_t isr; /* ADC interrupt and status register (ADC_ISR) */ + uint32_t ier; /* ADC interrupt enable register (ADC_IER) */ + uint32_t cr; /* ADC control register (ADC_CR) */ + uint32_t cfgr; /* ADC configuration register (ADC_CFGR) */ + uint32_t cfgr2; /* ADC configuration register (ADC_CFGR) */ + uint32_t smpr1; /* ADC sample time register 1 (ADC_SMPR1) */ + uint32_t smpr2; /* ADC sample time register 1 (ADC_SMPR1) */ + uint32_t __unused1[1]; /* */ + uint32_t tr1; /* ADC watchdog threshold register 1 (ADC_TR1) */ + uint32_t tr2; /* ADC watchdog threshold register 1 (ADC_TR1) */ + uint32_t tr3; /* ADC watchdog threshold register 1 (ADC_TR1) */ + uint32_t __unused2[1]; /* */ + uint32_t sqr1; /* ADC regular sequence register 1 (ADC_SQR1) */ + uint32_t sqr2; /* ADC regular sequence register 1 (ADC_SQR1) */ + uint32_t sqr3; /* ADC regular sequence register 1 (ADC_SQR1) */ + uint32_t sqr4; /* ADC regular sequence register 1 (ADC_SQR1) */ + uint32_t dr; /* ADC regular data register (ADC_DR) */ + uint32_t __unused3[2]; /* */ + uint32_t jsqr; /* ADC injected sequence register (ADC_JSQR) */ + uint32_t __unused4[4]; /* */ + uint32_t ofr1; /* ADC offset y register (ADC_OFRy) */ + uint32_t ofr2; /* ADC offset y register (ADC_OFRy) */ + uint32_t ofr3; /* ADC offset y register (ADC_OFRy) */ + uint32_t ofr4; /* ADC offset y register (ADC_OFRy) */ + uint32_t __unused5[4]; /* */ + uint32_t jdr1; /* ADC injected channel y data register (ADC_JDRy) */ + uint32_t jdr2; /* ADC injected channel y data register (ADC_JDRy) */ + uint32_t jdr3; /* ADC injected channel y data register (ADC_JDRy) */ + uint32_t jdr4; /* ADC injected channel y data register (ADC_JDRy) */ + uint32_t __unused6[4]; /* */ + uint32_t awd2cr; /* ADC analog watchdog 2 configuration register (ADC_AWD2CR) */ + uint32_t awd3cr; /* ADC analog watchdog 2 configuration register (ADC_AWD2CR) */ + uint32_t __unused7[2]; /* */ + uint32_t difsel; /* ADC differential mode selection register (ADC_DIFSEL) */ + uint32_t calfact; /* ADC calibration factors (ADC_CALFACT) */ + uint32_t __unused8[2]; /* */ + uint32_t gcomp; /* ADC Gain compensation Register (ADC_GCOMP) */ + uint32_t csr; /* ADCx common status register (ADCx_CSR) (x = 12 or 345) */ + uint32_t __unused9[1]; /* */ + uint32_t ccr; /* ADCx common control register (ADCx_CCR) (x = 12 or 345) */ + uint32_t __unused10[192]; /* */ + uint32_t cdr; /* ADCx common regular data register for dual mode (ADCx_CDR) (x = 12 or 345) */ + +} hal_ll_adc_base_handle_t; + +/*!< @brief ADC hw specific module values */ +typedef struct +{ + uint16_t pin_an[ADC_MODULE_COUNT]; +} hal_ll_adc_pin_id; + +static hal_ll_adc_hw_specifics_map_t hal_ll_adc_hw_specifics_map[] = +{ + #ifdef ADC_MODULE_1 + {ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF}, + #endif + #ifdef ADC_MODULE_2 + {ADC2_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF}, + #endif + #ifdef ADC_MODULE_3 + {ADC3_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF}, + #endif + #ifdef ADC_MODULE_4 + {ADC4_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_4), HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF}, + #endif + #ifdef ADC_MODULE_5 + {ADC5_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_5), HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF}, + #endif + + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF} +}; + +// ------------------------------------------------------------------ VARIABLES + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_adc_handle_register_t *low_level_handle; +static volatile hal_ll_adc_hw_specifics_map_t *hal_ll_adc_hw_specifics_map_local; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Enable ADC module 1 clock. + * @param none + * @return none + */ +static inline void adc1_enable_clock(); +/** + * @brief Enable ADC module 2 clock. + * @param none + * @return none + */ +static inline void adc2_enable_clock(); +/** + * @brief Enable ADC module 3 clock. + * @param none + * @return none + */ +static inline void adc3_enable_clock(); +/** + * @brief Enable ADC module 4 clock. + * @param none + * @return none + */ +static inline void adc4_enable_clock(); +/** + * @brief Enable ADC module 5 clock. + * @param none + * @return none + */ +static inline void adc5_enable_clock(); + + +/** + * @brief Initialize ADC module. + * @param *map - ADC module local map. + * @return None + */ +static void hal_ll_adc_init( hal_ll_adc_hw_specifics_map_t *map ); + +/** + * @brief Check if pins are adequate. + * + * Checks analog pin the user has passed with pre-defined + * pins in ADC pin map. + * + * @param[in] pin - ADC pre-defined pin name. + * @param[in] *index - ADC map index value. + * @return hal_ll_pin_name_t Module index based on pin. + * + * Returns pre-defined module index from pin maps, if pin + * is adequate. + */ +static hal_ll_pin_name_t hal_ll_adc_check_pins( hal_ll_pin_name_t pin, hal_ll_adc_pin_id *index, hal_ll_adc_handle_register_t *handle_map ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and channel values for ADC pin + * + * @param[in] module_index ADC HW module index -- 0,1,2... + * @param[in] *index ADC map index value + * + * @return None + */ +static void hal_ll_adc_map_pin( uint8_t module_index, hal_ll_adc_pin_id *index ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_adc_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_adc_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_adc_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Enable ADC module gate clock. + * @param base - ADC module base address. + * @return None + */ +static void _hal_ll_adc_enable_clock( uint8_t base ); + +/** + * @brief Initialize ADC module. + * @param *base - ADC module base address. + * @param resolution - ADC module resolution. + * @return None + */ +static void _hal_ll_adc_hw_init( hal_ll_adc_base_handle_t *base, uint32_t resolution ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_adc_register_handle(hal_ll_pin_name_t pin, hal_ll_adc_voltage_reference_t vref_input, hal_ll_adc_resolution_t resolution, hal_ll_adc_handle_register_t *handle_map, uint8_t *hal_module_id) +{ + uint16_t pin_check_result; + hal_ll_adc_pin_id index = {HAL_LL_PIN_NC}; + + if ( (pin_check_result = hal_ll_adc_check_pins( pin, &index, handle_map )) == HAL_LL_PIN_NC ) { + return HAL_LL_ADC_WRONG_PIN; + }; + + switch ( resolution ) + { + case HAL_LL_ADC_RESOLUTION_12_BIT: + hal_ll_adc_hw_specifics_map[pin_check_result].resolution = HAL_LL_ADC_12BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_10_BIT: + hal_ll_adc_hw_specifics_map[pin_check_result].resolution = HAL_LL_ADC_10BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_8_BIT: + hal_ll_adc_hw_specifics_map[pin_check_result].resolution = HAL_LL_ADC_8BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_6_BIT: + hal_ll_adc_hw_specifics_map[pin_check_result].resolution = HAL_LL_ADC_6BIT_RES; + break; + default: + return HAL_LL_ADC_UNSUPPORTED_RESOLUTION; + } + + switch ( vref_input ) + { + case HAL_LL_ADC_VREF_EXTERNAL: + break; + + default: + return HAL_LL_ADC_UNSUPPORTED_VREF; + } + + if ( hal_ll_adc_hw_specifics_map[pin_check_result].pin != pin ) + { + hal_ll_adc_map_pin( pin_check_result, &index ); + + handle_map[pin_check_result].init_ll_state = false; + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[pin_check_result].hal_ll_adc_handle = (handle_t *)&hal_ll_adc_hw_specifics_map[pin_check_result].base; + + handle_map[pin_check_result].hal_ll_adc_handle = (handle_t *)&hal_ll_module_state[pin_check_result].hal_ll_adc_handle; + + return HAL_LL_ADC_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_adc( handle_t *handle ) +{ + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + hal_ll_adc_handle_register_t *hal_handle = (hal_ll_adc_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_adc_hw_specifics_map_local->module_index; + + hal_ll_adc_init( hal_ll_adc_hw_specifics_map_local ); + + hal_ll_module_state[pin_check_result].hal_ll_adc_handle = (handle_t *)&hal_ll_adc_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_ADC_SUCCESS; +} + +hal_ll_err_t hal_ll_adc_set_resolution(handle_t *handle, hal_ll_adc_resolution_t resolution) +{ + low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + + low_level_handle->init_ll_state = false; + + switch( resolution ) { + case HAL_LL_ADC_RESOLUTION_12_BIT: + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_12BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_10_BIT: + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_10BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_8_BIT: + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_8BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_6_BIT: + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_6BIT_RES; + break; + + default: + return HAL_LL_ADC_UNSUPPORTED_RESOLUTION; + } + + hal_ll_adc_init( hal_ll_adc_hw_specifics_map_local ); + + low_level_handle->init_ll_state = true; + + return HAL_LL_ADC_SUCCESS; +} + +hal_ll_err_t hal_ll_adc_set_vref_input(handle_t *handle, hal_ll_adc_voltage_reference_t vref_input) +{ + low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + + low_level_handle->init_ll_state = false; + + switch( vref_input ) { + case HAL_LL_ADC_VREF_EXTERNAL: + break; + + default: + return HAL_LL_ADC_UNSUPPORTED_VREF; + } + + hal_ll_adc_init( hal_ll_adc_hw_specifics_map_local ); + + low_level_handle->init_ll_state = true; + + return HAL_LL_ADC_SUCCESS; +} + +void hal_ll_adc_set_vref_value(handle_t *handle, float vref_value) +{ + low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + + hal_ll_adc_hw_specifics_map_local->vref_value = vref_value; +} + +hal_ll_err_t hal_ll_adc_read( handle_t *handle, uint16_t *readDatabuf ) +{ + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_base_handle_t *base = ( hal_ll_adc_base_handle_t * )hal_ll_adc_hw_specifics_map_local->base ; + + while( ( check_reg_bit( &( base->cr ), HAL_LL_ADC_ADSTART_BIT ) ) ); + base->sqr1 &= ~HAL_LL_ADC_CONVERSION_ONE; + base->sqr1 |= ( ( hal_ll_adc_hw_specifics_map_local->channel << 6 ) ); + + Delay_1us(); + + // Start the conversion. + set_reg_bit( &( base->cr ), HAL_LL_ADC_ADSTART_BIT ); + + while ( !( check_reg_bit( &( base->isr ), HAL_LL_ADC_EOC_BIT ) ) ); + // Conversion result from SS3. + *readDatabuf = base->dr; + + return HAL_LL_ADC_SUCCESS; +} + +void hal_ll_adc_close( handle_t *handle ) +{ + hal_ll_adc_hw_specifics_map_t *hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + low_level_handle = hal_ll_adc_get_handle; + + if( hal_ll_adc_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + + hal_ll_adc_hw_specifics_map_local->vref_input = HAL_LL_ADC_VREF_DEFAULT; + hal_ll_adc_hw_specifics_map_local->vref_value = 0; + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_RESOLUTION_12_BIT; + + low_level_handle->hal_ll_adc_handle = NULL; + low_level_handle->hal_drv_adc_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_adc_hw_specifics_map_local->pin = HAL_LL_PIN_NC; + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static hal_ll_pin_name_t hal_ll_adc_check_pins( hal_ll_pin_name_t pin, hal_ll_adc_pin_id *index, hal_ll_adc_handle_register_t *handle_map ) +{ + static const uint16_t adc_map_size = ( sizeof( _adc_map ) / sizeof( hal_ll_adc_pin_map_t ) ); + uint16_t pin_index = 0; + uint8_t index_counter = 0; + uint8_t hal_ll_module_id = 0; + + if ( HAL_LL_PIN_NC == pin ) { + return HAL_LL_PIN_NC; + } + + for ( pin_index = 0; pin_index < adc_map_size; pin_index++ ) + { + if ( pin == _adc_map[pin_index].pin ) + { + // Get module number + hal_ll_module_id = _adc_map[pin_index].module_index; + // Map pin name + index->pin_an[hal_ll_module_id] = pin_index; + + // Check if module is taken + if ( NULL == handle_map[ hal_ll_module_id ].hal_drv_adc_handle ) { + return hal_ll_module_id; + } else if ( ADC_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static void hal_ll_adc_map_pin( uint8_t module_index, hal_ll_adc_pin_id *index ) { + // Map new pins + hal_ll_adc_hw_specifics_map[module_index].pin = _adc_map[ index->pin_an[module_index] ].pin; + hal_ll_adc_hw_specifics_map[module_index].channel = _adc_map[ index->pin_an[module_index] ].channel; +} + +static hal_ll_adc_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof(hal_ll_adc_handle_register_t)); + static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof(hal_ll_adc_handle_register_t)); + + while( hal_ll_module_count-- ) { + if (hal_ll_adc_get_base_from_hal_handle == hal_ll_adc_hw_specifics_map[hal_ll_module_count].base) { + return &hal_ll_adc_hw_specifics_map[hal_ll_module_count]; + } + } + + return &hal_ll_adc_hw_specifics_map[hal_ll_module_error]; +} +static inline void adc1_enable_clock() +{ + set_reg_bit( _RCC_AHB2ENR, HAL_LL_ADC1_ENABLE_CLOCK ); +} +static inline void adc2_enable_clock() +{ + set_reg_bit( _RCC_AHB2ENR, HAL_LL_ADC2_ENABLE_CLOCK ); +} +static inline void adc3_enable_clock() +{ + set_reg_bit( _RCC_AHB2ENR, HAL_LL_ADC3_ENABLE_CLOCK ); +} +static inline void adc4_enable_clock() +{ + set_reg_bit( _RCC_AHB2ENR, HAL_LL_ADC4_ENABLE_CLOCK ); +} +static inline void adc5_enable_clock() +{ + set_reg_bit( _RCC_AHB2ENR, HAL_LL_ADC5_ENABLE_CLOCK ); +} + +static void _hal_ll_adc_enable_clock( uint8_t base ) +{ + switch ( base ) + { + #ifdef ADC_MODULE_1 + case ( hal_ll_adc_module_num(ADC_MODULE_1) ): + adc1_enable_clock(); + break; + #endif + #ifdef ADC_MODULE_2 + case ( hal_ll_adc_module_num(ADC_MODULE_2) ): + adc2_enable_clock(); + break; + #endif + #ifdef ADC_MODULE_3 + case ( hal_ll_adc_module_num(ADC_MODULE_3) ): + adc3_enable_clock(); + break; + #endif + #ifdef ADC_MODULE_4 + case ( hal_ll_adc_module_num(ADC_MODULE_4) ): + adc4_enable_clock(); + break; + #endif + #ifdef ADC_MODULE_5 + case ( hal_ll_adc_module_num(ADC_MODULE_5) ): + adc5_enable_clock(); + break; + #endif + } +} +static void _hal_ll_adc_hw_init( hal_ll_adc_base_handle_t *base, uint32_t resolution ) +{ + static uint32_t wait_loop_index = 0; + static uint32_t *reg; + reg = HAL_LL_ADC_CCIPR; + + // Select ADC clock source. + *reg |= HAL_LL_ADC_CLK_SRC; + + // Exit from deep power down mode. + if ( check_reg_bit( &( base->cr ), HAL_LL_ADC_DEEPPWD_BIT ) ) + { + clear_reg_bit( &( base->cr ), HAL_LL_ADC_DEEPPWD_BIT ); + } + + // Enable voltage regulator. + base->cr &= HAL_LL_ADC_VOLTAGE; + + if ( !( check_reg_bit( &( base->cr ), HAL_LL_ADC_ADVREGEN_BIT ) ) ) + { + set_reg_bit( &( base->cr ), HAL_LL_ADC_ADVREGEN_BIT ); + } + + // Enable ADC interrupts. + set_reg_bit( &( base->ier ), HAL_LL_ADC_ADRDYIE_BIT ); + + // Disable ADC + if ( check_reg_bit( &( base->cr ), HAL_LL_ADC_ADEN_BIT ) ) + { + set_reg_bit( &( base->cr ), HAL_LL_ADC_ADDIS_BIT ); + } + + // Voltage reference enable, ckmode SYSCLK. + reg = HAL_LL_ADC_CCR; + *reg |= (HAL_LL_ADC_CKMODE_MASK | HAL_LL_ADC_VREFEN_MASK); + + // Select calibration mode. + clear_reg_bit( &( base->cr ), HAL_LL_ADC_ADCALDIF_BIT ); + + // Start ADC calibration. + set_reg_bit( &( base->cr ), HAL_LL_ADC_ADCAL_BIT ); + + // Wait for calibration. + while ( check_reg_bit( &( base->cr ), HAL_LL_ADC_ADCAL_BIT ) ); + + // Prescaler. + *reg &= HAL_LL_ADC_PRESCALER; + + // Clear ADRDY bit ADC_ISR by writting 1. + set_reg_bit( &( base->isr ), HAL_LL_ADC_ADRDY_BIT ); + + // Set delay for voltage regulator to be initialized correctly. + wait_loop_index = 10 * ( Get_Fosc_kHz() / 1000 ); + while( wait_loop_index != 0 ) + { + wait_loop_index--; + } + + // Enable ADC. + set_reg_bit( &( base->cr ), HAL_LL_ADC_ADEN_BIT ); + + // ADRDY bit. + while ( !( check_reg_bit( &( base->cr ), HAL_LL_ADC_ADRDY_BIT ) ) ); + + // Resolution. + base->cfgr &= HAL_LL_RESOLUTION_MASK; + base->cfgr |= resolution; + + // Data alignment. + clear_reg_bit( &( base->cfgr ), HAL_LL_ADC_ALIGN_BIT ); + + // Discontinuos mode disabled. + clear_reg_bit( &( base->cfgr ), HAL_LL_ADC_DISCEN_BIT ); + + // Continuos conversion mode. + clear_reg_bit( &( base->cfgr ), HAL_LL_ADC_CONT_BIT ); + + // Regular channel sequence length. + base->sqr1 &= HAL_LL_ADC_CONVERSION; +} + +static void hal_ll_adc_init( hal_ll_adc_hw_specifics_map_t *map ) { + + + hal_ll_gpio_analog_input( hal_ll_gpio_port_base( hal_ll_gpio_port_index( map->pin ) ), + hal_ll_gpio_pin_mask( map->pin ) ); + + _hal_ll_adc_enable_clock( map->module_index ); + + _hal_ll_adc_hw_init((hal_ll_adc_base_handle_t *)map->base, map->resolution); + +} + + +// ------------------------------------------------------------------------- END + + + + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_86/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_86/CMakeLists.cmake new file mode 100644 index 000000000..885db324c --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_86/CMakeLists.cmake @@ -0,0 +1,10 @@ +if(${MCU_NAME} MATCHES "^STM32G483CE$|^STM32G483RE$|^STM32G483ME$|^STM32G483PE$|^STM32G483VE$|^STM32G483QE$") + set(adc_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_adc.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_86") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_86") + list(APPEND hal_ll_def_list "STM32G4xx") + list(APPEND hal_ll_def_list "STM32G48xx") + list(APPEND hal_ll_def_list "STM32G483xx") + set(adc_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/adc/hal_ll_adc_pin_map/implementations/doc_ds_86") + list(APPEND hal_ll_def_list "HAL_LL_ADC_RESOLUTION_CMAKE=HAL_LL_ADC_RESOLUTION_12_BIT") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_86/hal_ll_adc.c b/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_86/hal_ll_adc.c new file mode 100644 index 000000000..616f145a8 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_86/hal_ll_adc.c @@ -0,0 +1,694 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_adc.c + * @brief Low level HAL ADC source file. + */ + +#include "hal_ll_adc.h" +#include "hal_ll_gpio.h" +#include "hal_ll_adc_pin_map.h" + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_adc_get_module_state_address ((hal_ll_adc_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_adc_get_handle (hal_ll_adc_handle_register_t *)hal_ll_adc_get_module_state_address->hal_ll_adc_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_adc_get_base_struct(_handle) ((hal_ll_adc_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_adc_get_base_from_hal_handle ((hal_ll_adc_hw_specifics_map_t *)((hal_ll_adc_handle_register_t *)\ + (((hal_ll_adc_handle_register_t *)(handle))->hal_ll_adc_handle))->hal_ll_adc_handle)->base +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_adc_module_num(_module_num) (_module_num - 1) + +// ADC common registers. + +#define hal_ll_adc_module_num(_module_num) (_module_num - 1) + +#define HAL_LL_ADC_CSR_OFFSET ( 0x300 / 4 ) +#define HAL_LL_ADC_CCR_OFFSET ( 0x308 / 4 ) +#define HAL_LL_ADC_CDR_OFFSET ( 0x30C / 4 ) + + +#define HAL_LL_ADC_APB2ENR_SYSCFGEN 0 +#define HAL_LL_ADC_VREF_ENVR 0 +#define HAL_LL_ADC_ADRDYIE_BIT 0 +#define HAL_LL_ADC_ADEN_BIT 0 +#define HAL_LL_ADC_ADRDY_BIT 0 +#define HAL_LL_ADC_ADDIS_BIT 1 +#define HAL_LL_ADC_EOC_BIT 2 +#define HAL_LL_ADC_ADSTART_BIT 2 +#define HAL_LL_ADC_RESOLUTION_BIT0 3 +#define HAL_LL_ADC_RESOLUTION_BIT1 4 +#define HAL_LL_ADC_VREF_VRR 3 +#define HAL_LL_ADC_ALIGN_BIT 15 + +#define HAL_LL_ADC1_ENABLE_CLOCK 13 +#define HAL_LL_ADC2_ENABLE_CLOCK 13 +#define HAL_LL_ADC3_ENABLE_CLOCK 14 +#define HAL_LL_ADC4_ENABLE_CLOCK 14 +#define HAL_LL_ADC5_ENABLE_CLOCK 14 + +#define HAL_LL_ADC_CONT_BIT 13 +#define HAL_LL_ADC_DISCEN_BIT 16 +#define HAL_LL_ADC_ADVREGEN_BIT 28 +#define HAL_LL_ADC_DEEPPWD_BIT 29 +#define HAL_LL_ADC_ADCALDIF_BIT 30 +#define HAL_LL_ADC_ADCAL_BIT 31 +#define HAL_LL_ADC_PIN_MASK 0xF + +#define HAL_LL_ADC_12BIT_RES 0x00000000ul +#define HAL_LL_ADC_10BIT_RES 0x00000008ul +#define HAL_LL_ADC_8BIT_RES 0x00000010ul +#define HAL_LL_ADC_6BIT_RES 0x00000018ul + +#define ADC_CAL_SINGLE 0x00000000ul +#define ADC_CAL_DIF 0x00000001ul +#define HAL_LL_ADC_CLK_SRC 0xF0000000ul +#define HAL_LL_ADC_VOLTAGE 0xCFFFFFFFul +#define HAL_LL_ADC_CCR 0x50000308ul +#define HAL_LL_ADC_CKMODE_MASK 0x00000000ul +#define HAL_LL_ADC_VREFEN_MASK 0x00400000ul +#define HAL_LL_ADC_CCIPR 0x40021088ul +#define HAL_LL_ADC_PRESCALER 0xFFC3FFFFul +#define HAL_LL_ADC_CONVERSION 0xFFFFFFF0ul + +#define HAL_LL_ADC_CONVERSION_ONE 0x000007C0ul + +#define HAL_LL_MODULE_INDEX_ERROR 0xFFFFFFFFul + +#define HAL_LL_RESOLUTION_MASK 0xFFFFFFE7ul + +#define HAL_LL_ADC_DEFAULT_BASE_ADDRESS 0xFF + + +// -------------------------------------------------------------- PRIVATE TYPES +/*!< @brief Local handle list */ +static hal_ll_adc_handle_register_t hal_ll_module_state[ADC_MODULE_COUNT] = { (handle_t *) NULL, (handle_t *) NULL, false }; + +/** + * Return values + */ +typedef enum +{ + HAL_LL_ADC_SUCCESS = 0, + HAL_LL_ADC_WRONG_PIN, + + HAL_LL_ADC_UNSUPPORTED_RESOLUTION = 1100, + HAL_LL_ADC_UNSUPPORTED_VREF, + HAL_LL_ADC_WRONG_CHANNEL, + HAL_LL_ADC_ERROR = (-1) +} hal_ll_adc_err_t; + +/*!< @brief ADC register structure. */ +typedef struct +{ + uint32_t isr; /* ADC interrupt and status register (ADC_ISR) */ + uint32_t ier; /* ADC interrupt enable register (ADC_IER) */ + uint32_t cr; /* ADC control register (ADC_CR) */ + uint32_t cfgr; /* ADC configuration register (ADC_CFGR) */ + uint32_t cfgr2; /* ADC configuration register (ADC_CFGR) */ + uint32_t smpr1; /* ADC sample time register 1 (ADC_SMPR1) */ + uint32_t smpr2; /* ADC sample time register 1 (ADC_SMPR1) */ + uint32_t __unused1[1]; /* */ + uint32_t tr1; /* ADC watchdog threshold register 1 (ADC_TR1) */ + uint32_t tr2; /* ADC watchdog threshold register 1 (ADC_TR1) */ + uint32_t tr3; /* ADC watchdog threshold register 1 (ADC_TR1) */ + uint32_t __unused2[1]; /* */ + uint32_t sqr1; /* ADC regular sequence register 1 (ADC_SQR1) */ + uint32_t sqr2; /* ADC regular sequence register 1 (ADC_SQR1) */ + uint32_t sqr3; /* ADC regular sequence register 1 (ADC_SQR1) */ + uint32_t sqr4; /* ADC regular sequence register 1 (ADC_SQR1) */ + uint32_t dr; /* ADC regular data register (ADC_DR) */ + uint32_t __unused3[2]; /* */ + uint32_t jsqr; /* ADC injected sequence register (ADC_JSQR) */ + uint32_t __unused4[4]; /* */ + uint32_t ofr1; /* ADC offset y register (ADC_OFRy) */ + uint32_t ofr2; /* ADC offset y register (ADC_OFRy) */ + uint32_t ofr3; /* ADC offset y register (ADC_OFRy) */ + uint32_t ofr4; /* ADC offset y register (ADC_OFRy) */ + uint32_t __unused5[4]; /* */ + uint32_t jdr1; /* ADC injected channel y data register (ADC_JDRy) */ + uint32_t jdr2; /* ADC injected channel y data register (ADC_JDRy) */ + uint32_t jdr3; /* ADC injected channel y data register (ADC_JDRy) */ + uint32_t jdr4; /* ADC injected channel y data register (ADC_JDRy) */ + uint32_t __unused6[4]; /* */ + uint32_t awd2cr; /* ADC analog watchdog 2 configuration register (ADC_AWD2CR) */ + uint32_t awd3cr; /* ADC analog watchdog 2 configuration register (ADC_AWD2CR) */ + uint32_t __unused7[2]; /* */ + uint32_t difsel; /* ADC differential mode selection register (ADC_DIFSEL) */ + uint32_t calfact; /* ADC calibration factors (ADC_CALFACT) */ + uint32_t __unused8[2]; /* */ + uint32_t gcomp; /* ADC Gain compensation Register (ADC_GCOMP) */ + uint32_t csr; /* ADCx common status register (ADCx_CSR) (x = 12 or 345) */ + uint32_t __unused9[1]; /* */ + uint32_t ccr; /* ADCx common control register (ADCx_CCR) (x = 12 or 345) */ + uint32_t __unused10[192]; /* */ + uint32_t cdr; /* ADCx common regular data register for dual mode (ADCx_CDR) (x = 12 or 345) */ + +} hal_ll_adc_base_handle_t; + +/*!< @brief ADC hw specific module values */ +typedef struct +{ + uint16_t pin_an[ADC_MODULE_COUNT]; +} hal_ll_adc_pin_id; + +static hal_ll_adc_hw_specifics_map_t hal_ll_adc_hw_specifics_map[] = +{ + #ifdef ADC_MODULE_1 + {ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF}, + #endif + #ifdef ADC_MODULE_2 + {ADC2_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF}, + #endif + #ifdef ADC_MODULE_3 + {ADC3_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF}, + #endif + #ifdef ADC_MODULE_4 + {ADC4_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_4), HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF}, + #endif + #ifdef ADC_MODULE_5 + {ADC5_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_5), HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF}, + #endif + + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF} +}; + +// ------------------------------------------------------------------ VARIABLES + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_adc_handle_register_t *low_level_handle; +static volatile hal_ll_adc_hw_specifics_map_t *hal_ll_adc_hw_specifics_map_local; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Enable ADC module 1 clock. + * @param none + * @return none + */ +static inline void adc1_enable_clock(); +/** + * @brief Enable ADC module 2 clock. + * @param none + * @return none + */ +static inline void adc2_enable_clock(); +/** + * @brief Enable ADC module 3 clock. + * @param none + * @return none + */ +static inline void adc3_enable_clock(); +/** + * @brief Enable ADC module 4 clock. + * @param none + * @return none + */ +static inline void adc4_enable_clock(); +/** + * @brief Enable ADC module 5 clock. + * @param none + * @return none + */ +static inline void adc5_enable_clock(); + + +/** + * @brief Initialize ADC module. + * @param *map - ADC module local map. + * @return None + */ +static void hal_ll_adc_init( hal_ll_adc_hw_specifics_map_t *map ); + +/** + * @brief Check if pins are adequate. + * + * Checks analog pin the user has passed with pre-defined + * pins in ADC pin map. + * + * @param[in] pin - ADC pre-defined pin name. + * @param[in] *index - ADC map index value. + * @return hal_ll_pin_name_t Module index based on pin. + * + * Returns pre-defined module index from pin maps, if pin + * is adequate. + */ +static hal_ll_pin_name_t hal_ll_adc_check_pins( hal_ll_pin_name_t pin, hal_ll_adc_pin_id *index, hal_ll_adc_handle_register_t *handle_map ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and channel values for ADC pin + * + * @param[in] module_index ADC HW module index -- 0,1,2... + * @param[in] *index ADC map index value + * + * @return None + */ +static void hal_ll_adc_map_pin( uint8_t module_index, hal_ll_adc_pin_id *index ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_adc_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_adc_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_adc_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Enable ADC module gate clock. + * @param base - ADC module base address. + * @return None + */ +static void _hal_ll_adc_enable_clock( uint8_t base ); + +/** + * @brief Initialize ADC module. + * @param *base - ADC module base address. + * @param resolution - ADC module resolution. + * @return None + */ +static void _hal_ll_adc_hw_init( hal_ll_adc_base_handle_t *base, uint32_t resolution ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_adc_register_handle(hal_ll_pin_name_t pin, hal_ll_adc_voltage_reference_t vref_input, hal_ll_adc_resolution_t resolution, hal_ll_adc_handle_register_t *handle_map, uint8_t *hal_module_id) +{ + uint16_t pin_check_result; + hal_ll_adc_pin_id index = {HAL_LL_PIN_NC}; + + if ( (pin_check_result = hal_ll_adc_check_pins( pin, &index, handle_map )) == HAL_LL_PIN_NC ) { + return HAL_LL_ADC_WRONG_PIN; + }; + + switch ( resolution ) + { + case HAL_LL_ADC_RESOLUTION_12_BIT: + hal_ll_adc_hw_specifics_map[pin_check_result].resolution = HAL_LL_ADC_12BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_10_BIT: + hal_ll_adc_hw_specifics_map[pin_check_result].resolution = HAL_LL_ADC_10BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_8_BIT: + hal_ll_adc_hw_specifics_map[pin_check_result].resolution = HAL_LL_ADC_8BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_6_BIT: + hal_ll_adc_hw_specifics_map[pin_check_result].resolution = HAL_LL_ADC_6BIT_RES; + break; + default: + return HAL_LL_ADC_UNSUPPORTED_RESOLUTION; + } + + switch ( vref_input ) + { + case HAL_LL_ADC_VREF_EXTERNAL: + break; + + default: + return HAL_LL_ADC_UNSUPPORTED_VREF; + } + + if ( hal_ll_adc_hw_specifics_map[pin_check_result].pin != pin ) + { + hal_ll_adc_map_pin( pin_check_result, &index ); + + handle_map[pin_check_result].init_ll_state = false; + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[pin_check_result].hal_ll_adc_handle = (handle_t *)&hal_ll_adc_hw_specifics_map[pin_check_result].base; + + handle_map[pin_check_result].hal_ll_adc_handle = (handle_t *)&hal_ll_module_state[pin_check_result].hal_ll_adc_handle; + + return HAL_LL_ADC_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_adc( handle_t *handle ) +{ + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + hal_ll_adc_handle_register_t *hal_handle = (hal_ll_adc_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_adc_hw_specifics_map_local->module_index; + + hal_ll_adc_init( hal_ll_adc_hw_specifics_map_local ); + + hal_ll_module_state[pin_check_result].hal_ll_adc_handle = (handle_t *)&hal_ll_adc_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_ADC_SUCCESS; +} + +hal_ll_err_t hal_ll_adc_set_resolution(handle_t *handle, hal_ll_adc_resolution_t resolution) +{ + low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + + low_level_handle->init_ll_state = false; + + switch( resolution ) { + case HAL_LL_ADC_RESOLUTION_12_BIT: + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_12BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_10_BIT: + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_10BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_8_BIT: + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_8BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_6_BIT: + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_6BIT_RES; + break; + + default: + return HAL_LL_ADC_UNSUPPORTED_RESOLUTION; + } + + hal_ll_adc_init( hal_ll_adc_hw_specifics_map_local ); + + low_level_handle->init_ll_state = true; + + return HAL_LL_ADC_SUCCESS; +} + +hal_ll_err_t hal_ll_adc_set_vref_input(handle_t *handle, hal_ll_adc_voltage_reference_t vref_input) +{ + low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + + low_level_handle->init_ll_state = false; + + switch( vref_input ) { + case HAL_LL_ADC_VREF_EXTERNAL: + break; + + default: + return HAL_LL_ADC_UNSUPPORTED_VREF; + } + + hal_ll_adc_init( hal_ll_adc_hw_specifics_map_local ); + + low_level_handle->init_ll_state = true; + + return HAL_LL_ADC_SUCCESS; +} + +void hal_ll_adc_set_vref_value(handle_t *handle, float vref_value) +{ + low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + + hal_ll_adc_hw_specifics_map_local->vref_value = vref_value; +} + +hal_ll_err_t hal_ll_adc_read( handle_t *handle, uint16_t *readDatabuf ) +{ + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_base_handle_t *base = ( hal_ll_adc_base_handle_t * )hal_ll_adc_hw_specifics_map_local->base ; + + while( ( check_reg_bit( &( base->cr ), HAL_LL_ADC_ADSTART_BIT ) ) ); + base->sqr1 &= ~HAL_LL_ADC_CONVERSION_ONE; + base->sqr1 |= ( ( hal_ll_adc_hw_specifics_map_local->channel << 6 ) ); + + Delay_1us(); + + // Start the conversion. + set_reg_bit( &( base->cr ), HAL_LL_ADC_ADSTART_BIT ); + + while ( !( check_reg_bit( &( base->isr ), HAL_LL_ADC_EOC_BIT ) ) ); + // Conversion result from SS3. + *readDatabuf = base->dr; + + return HAL_LL_ADC_SUCCESS; +} + +void hal_ll_adc_close( handle_t *handle ) +{ + hal_ll_adc_hw_specifics_map_t *hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + low_level_handle = hal_ll_adc_get_handle; + + if( hal_ll_adc_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + + hal_ll_adc_hw_specifics_map_local->vref_input = HAL_LL_ADC_VREF_DEFAULT; + hal_ll_adc_hw_specifics_map_local->vref_value = 0; + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_RESOLUTION_12_BIT; + + low_level_handle->hal_ll_adc_handle = NULL; + low_level_handle->hal_drv_adc_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_adc_hw_specifics_map_local->pin = HAL_LL_PIN_NC; + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static hal_ll_pin_name_t hal_ll_adc_check_pins( hal_ll_pin_name_t pin, hal_ll_adc_pin_id *index, hal_ll_adc_handle_register_t *handle_map ) +{ + static const uint16_t adc_map_size = ( sizeof( _adc_map ) / sizeof( hal_ll_adc_pin_map_t ) ); + uint16_t pin_index = 0; + uint8_t index_counter = 0; + uint8_t hal_ll_module_id = 0; + + if ( HAL_LL_PIN_NC == pin ) { + return HAL_LL_PIN_NC; + } + + for ( pin_index = 0; pin_index < adc_map_size; pin_index++ ) + { + if ( pin == _adc_map[pin_index].pin ) + { + // Get module number + hal_ll_module_id = _adc_map[pin_index].module_index; + // Map pin name + index->pin_an[hal_ll_module_id] = pin_index; + + // Check if module is taken + if ( NULL == handle_map[ hal_ll_module_id ].hal_drv_adc_handle ) { + return hal_ll_module_id; + } else if ( ADC_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static void hal_ll_adc_map_pin( uint8_t module_index, hal_ll_adc_pin_id *index ) { + // Map new pins + hal_ll_adc_hw_specifics_map[module_index].pin = _adc_map[ index->pin_an[module_index] ].pin; + hal_ll_adc_hw_specifics_map[module_index].channel = _adc_map[ index->pin_an[module_index] ].channel; +} + +static hal_ll_adc_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof(hal_ll_adc_handle_register_t)); + static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof(hal_ll_adc_handle_register_t)); + + while( hal_ll_module_count-- ) { + if (hal_ll_adc_get_base_from_hal_handle == hal_ll_adc_hw_specifics_map[hal_ll_module_count].base) { + return &hal_ll_adc_hw_specifics_map[hal_ll_module_count]; + } + } + + return &hal_ll_adc_hw_specifics_map[hal_ll_module_error]; +} +static inline void adc1_enable_clock() +{ + set_reg_bit( _RCC_AHB2ENR, HAL_LL_ADC1_ENABLE_CLOCK ); +} +static inline void adc2_enable_clock() +{ + set_reg_bit( _RCC_AHB2ENR, HAL_LL_ADC2_ENABLE_CLOCK ); +} +static inline void adc3_enable_clock() +{ + set_reg_bit( _RCC_AHB2ENR, HAL_LL_ADC3_ENABLE_CLOCK ); +} +static inline void adc4_enable_clock() +{ + set_reg_bit( _RCC_AHB2ENR, HAL_LL_ADC4_ENABLE_CLOCK ); +} +static inline void adc5_enable_clock() +{ + set_reg_bit( _RCC_AHB2ENR, HAL_LL_ADC5_ENABLE_CLOCK ); +} + +static void _hal_ll_adc_enable_clock( uint8_t base ) +{ + switch ( base ) + { + #ifdef ADC_MODULE_1 + case ( hal_ll_adc_module_num(ADC_MODULE_1) ): + adc1_enable_clock(); + break; + #endif + #ifdef ADC_MODULE_2 + case ( hal_ll_adc_module_num(ADC_MODULE_2) ): + adc2_enable_clock(); + break; + #endif + #ifdef ADC_MODULE_3 + case ( hal_ll_adc_module_num(ADC_MODULE_3) ): + adc3_enable_clock(); + break; + #endif + #ifdef ADC_MODULE_4 + case ( hal_ll_adc_module_num(ADC_MODULE_4) ): + adc4_enable_clock(); + break; + #endif + #ifdef ADC_MODULE_5 + case ( hal_ll_adc_module_num(ADC_MODULE_5) ): + adc5_enable_clock(); + break; + #endif + } +} +static void _hal_ll_adc_hw_init( hal_ll_adc_base_handle_t *base, uint32_t resolution ) +{ + static uint32_t wait_loop_index = 0; + static uint32_t *reg; + reg = HAL_LL_ADC_CCIPR; + + // Select ADC clock source. + *reg |= HAL_LL_ADC_CLK_SRC; + + // Exit from deep power down mode. + if ( check_reg_bit( &( base->cr ), HAL_LL_ADC_DEEPPWD_BIT ) ) + { + clear_reg_bit( &( base->cr ), HAL_LL_ADC_DEEPPWD_BIT ); + } + + // Enable voltage regulator. + base->cr &= HAL_LL_ADC_VOLTAGE; + + if ( !( check_reg_bit( &( base->cr ), HAL_LL_ADC_ADVREGEN_BIT ) ) ) + { + set_reg_bit( &( base->cr ), HAL_LL_ADC_ADVREGEN_BIT ); + } + + // Enable ADC interrupts. + set_reg_bit( &( base->ier ), HAL_LL_ADC_ADRDYIE_BIT ); + + // Disable ADC + if ( check_reg_bit( &( base->cr ), HAL_LL_ADC_ADEN_BIT ) ) + { + set_reg_bit( &( base->cr ), HAL_LL_ADC_ADDIS_BIT ); + } + + // Voltage reference enable, ckmode SYSCLK. + reg = HAL_LL_ADC_CCR; + *reg |= (HAL_LL_ADC_CKMODE_MASK | HAL_LL_ADC_VREFEN_MASK); + + // Select calibration mode. + clear_reg_bit( &( base->cr ), HAL_LL_ADC_ADCALDIF_BIT ); + + // Start ADC calibration. + set_reg_bit( &( base->cr ), HAL_LL_ADC_ADCAL_BIT ); + + // Wait for calibration. + while ( check_reg_bit( &( base->cr ), HAL_LL_ADC_ADCAL_BIT ) ); + + // Prescaler. + *reg &= HAL_LL_ADC_PRESCALER; + + // Clear ADRDY bit ADC_ISR by writting 1. + set_reg_bit( &( base->isr ), HAL_LL_ADC_ADRDY_BIT ); + + // Set delay for voltage regulator to be initialized correctly. + wait_loop_index = 10 * ( Get_Fosc_kHz() / 1000 ); + while( wait_loop_index != 0 ) + { + wait_loop_index--; + } + + // Enable ADC. + set_reg_bit( &( base->cr ), HAL_LL_ADC_ADEN_BIT ); + + // ADRDY bit. + while ( !( check_reg_bit( &( base->cr ), HAL_LL_ADC_ADRDY_BIT ) ) ); + + // Resolution. + base->cfgr &= HAL_LL_RESOLUTION_MASK; + base->cfgr |= resolution; + + // Data alignment. + clear_reg_bit( &( base->cfgr ), HAL_LL_ADC_ALIGN_BIT ); + + // Discontinuos mode disabled. + clear_reg_bit( &( base->cfgr ), HAL_LL_ADC_DISCEN_BIT ); + + // Continuos conversion mode. + clear_reg_bit( &( base->cfgr ), HAL_LL_ADC_CONT_BIT ); + + // Regular channel sequence length. + base->sqr1 &= HAL_LL_ADC_CONVERSION; +} + +static void hal_ll_adc_init( hal_ll_adc_hw_specifics_map_t *map ) { + + + hal_ll_gpio_analog_input( hal_ll_gpio_port_base( hal_ll_gpio_port_index( map->pin ) ), + hal_ll_gpio_pin_mask( map->pin ) ); + + _hal_ll_adc_enable_clock( map->module_index ); + + _hal_ll_adc_hw_init((hal_ll_adc_base_handle_t *)map->base, map->resolution); + +} + + +// ------------------------------------------------------------------------- END + + + + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_87/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_87/CMakeLists.cmake new file mode 100644 index 000000000..581eb5740 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_87/CMakeLists.cmake @@ -0,0 +1,10 @@ +if(${MCU_NAME} MATCHES "^STM32G484CE$|^STM32G484ME$|^STM32G484PE$|^STM32G484RE$|^STM32G484QE$|^STM32G484VE$") + set(adc_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_adc.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_87") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_87") + list(APPEND hal_ll_def_list "STM32G4xx") + list(APPEND hal_ll_def_list "STM32G48xx") + list(APPEND hal_ll_def_list "STM32G484xx") + set(adc_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/adc/hal_ll_adc_pin_map/implementations/doc_ds_87") + list(APPEND hal_ll_def_list "HAL_LL_ADC_RESOLUTION_CMAKE=HAL_LL_ADC_RESOLUTION_12_BIT") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_87/hal_ll_adc.c b/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_87/hal_ll_adc.c new file mode 100644 index 000000000..616f145a8 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_87/hal_ll_adc.c @@ -0,0 +1,694 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_adc.c + * @brief Low level HAL ADC source file. + */ + +#include "hal_ll_adc.h" +#include "hal_ll_gpio.h" +#include "hal_ll_adc_pin_map.h" + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_adc_get_module_state_address ((hal_ll_adc_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_adc_get_handle (hal_ll_adc_handle_register_t *)hal_ll_adc_get_module_state_address->hal_ll_adc_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_adc_get_base_struct(_handle) ((hal_ll_adc_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_adc_get_base_from_hal_handle ((hal_ll_adc_hw_specifics_map_t *)((hal_ll_adc_handle_register_t *)\ + (((hal_ll_adc_handle_register_t *)(handle))->hal_ll_adc_handle))->hal_ll_adc_handle)->base +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_adc_module_num(_module_num) (_module_num - 1) + +// ADC common registers. + +#define hal_ll_adc_module_num(_module_num) (_module_num - 1) + +#define HAL_LL_ADC_CSR_OFFSET ( 0x300 / 4 ) +#define HAL_LL_ADC_CCR_OFFSET ( 0x308 / 4 ) +#define HAL_LL_ADC_CDR_OFFSET ( 0x30C / 4 ) + + +#define HAL_LL_ADC_APB2ENR_SYSCFGEN 0 +#define HAL_LL_ADC_VREF_ENVR 0 +#define HAL_LL_ADC_ADRDYIE_BIT 0 +#define HAL_LL_ADC_ADEN_BIT 0 +#define HAL_LL_ADC_ADRDY_BIT 0 +#define HAL_LL_ADC_ADDIS_BIT 1 +#define HAL_LL_ADC_EOC_BIT 2 +#define HAL_LL_ADC_ADSTART_BIT 2 +#define HAL_LL_ADC_RESOLUTION_BIT0 3 +#define HAL_LL_ADC_RESOLUTION_BIT1 4 +#define HAL_LL_ADC_VREF_VRR 3 +#define HAL_LL_ADC_ALIGN_BIT 15 + +#define HAL_LL_ADC1_ENABLE_CLOCK 13 +#define HAL_LL_ADC2_ENABLE_CLOCK 13 +#define HAL_LL_ADC3_ENABLE_CLOCK 14 +#define HAL_LL_ADC4_ENABLE_CLOCK 14 +#define HAL_LL_ADC5_ENABLE_CLOCK 14 + +#define HAL_LL_ADC_CONT_BIT 13 +#define HAL_LL_ADC_DISCEN_BIT 16 +#define HAL_LL_ADC_ADVREGEN_BIT 28 +#define HAL_LL_ADC_DEEPPWD_BIT 29 +#define HAL_LL_ADC_ADCALDIF_BIT 30 +#define HAL_LL_ADC_ADCAL_BIT 31 +#define HAL_LL_ADC_PIN_MASK 0xF + +#define HAL_LL_ADC_12BIT_RES 0x00000000ul +#define HAL_LL_ADC_10BIT_RES 0x00000008ul +#define HAL_LL_ADC_8BIT_RES 0x00000010ul +#define HAL_LL_ADC_6BIT_RES 0x00000018ul + +#define ADC_CAL_SINGLE 0x00000000ul +#define ADC_CAL_DIF 0x00000001ul +#define HAL_LL_ADC_CLK_SRC 0xF0000000ul +#define HAL_LL_ADC_VOLTAGE 0xCFFFFFFFul +#define HAL_LL_ADC_CCR 0x50000308ul +#define HAL_LL_ADC_CKMODE_MASK 0x00000000ul +#define HAL_LL_ADC_VREFEN_MASK 0x00400000ul +#define HAL_LL_ADC_CCIPR 0x40021088ul +#define HAL_LL_ADC_PRESCALER 0xFFC3FFFFul +#define HAL_LL_ADC_CONVERSION 0xFFFFFFF0ul + +#define HAL_LL_ADC_CONVERSION_ONE 0x000007C0ul + +#define HAL_LL_MODULE_INDEX_ERROR 0xFFFFFFFFul + +#define HAL_LL_RESOLUTION_MASK 0xFFFFFFE7ul + +#define HAL_LL_ADC_DEFAULT_BASE_ADDRESS 0xFF + + +// -------------------------------------------------------------- PRIVATE TYPES +/*!< @brief Local handle list */ +static hal_ll_adc_handle_register_t hal_ll_module_state[ADC_MODULE_COUNT] = { (handle_t *) NULL, (handle_t *) NULL, false }; + +/** + * Return values + */ +typedef enum +{ + HAL_LL_ADC_SUCCESS = 0, + HAL_LL_ADC_WRONG_PIN, + + HAL_LL_ADC_UNSUPPORTED_RESOLUTION = 1100, + HAL_LL_ADC_UNSUPPORTED_VREF, + HAL_LL_ADC_WRONG_CHANNEL, + HAL_LL_ADC_ERROR = (-1) +} hal_ll_adc_err_t; + +/*!< @brief ADC register structure. */ +typedef struct +{ + uint32_t isr; /* ADC interrupt and status register (ADC_ISR) */ + uint32_t ier; /* ADC interrupt enable register (ADC_IER) */ + uint32_t cr; /* ADC control register (ADC_CR) */ + uint32_t cfgr; /* ADC configuration register (ADC_CFGR) */ + uint32_t cfgr2; /* ADC configuration register (ADC_CFGR) */ + uint32_t smpr1; /* ADC sample time register 1 (ADC_SMPR1) */ + uint32_t smpr2; /* ADC sample time register 1 (ADC_SMPR1) */ + uint32_t __unused1[1]; /* */ + uint32_t tr1; /* ADC watchdog threshold register 1 (ADC_TR1) */ + uint32_t tr2; /* ADC watchdog threshold register 1 (ADC_TR1) */ + uint32_t tr3; /* ADC watchdog threshold register 1 (ADC_TR1) */ + uint32_t __unused2[1]; /* */ + uint32_t sqr1; /* ADC regular sequence register 1 (ADC_SQR1) */ + uint32_t sqr2; /* ADC regular sequence register 1 (ADC_SQR1) */ + uint32_t sqr3; /* ADC regular sequence register 1 (ADC_SQR1) */ + uint32_t sqr4; /* ADC regular sequence register 1 (ADC_SQR1) */ + uint32_t dr; /* ADC regular data register (ADC_DR) */ + uint32_t __unused3[2]; /* */ + uint32_t jsqr; /* ADC injected sequence register (ADC_JSQR) */ + uint32_t __unused4[4]; /* */ + uint32_t ofr1; /* ADC offset y register (ADC_OFRy) */ + uint32_t ofr2; /* ADC offset y register (ADC_OFRy) */ + uint32_t ofr3; /* ADC offset y register (ADC_OFRy) */ + uint32_t ofr4; /* ADC offset y register (ADC_OFRy) */ + uint32_t __unused5[4]; /* */ + uint32_t jdr1; /* ADC injected channel y data register (ADC_JDRy) */ + uint32_t jdr2; /* ADC injected channel y data register (ADC_JDRy) */ + uint32_t jdr3; /* ADC injected channel y data register (ADC_JDRy) */ + uint32_t jdr4; /* ADC injected channel y data register (ADC_JDRy) */ + uint32_t __unused6[4]; /* */ + uint32_t awd2cr; /* ADC analog watchdog 2 configuration register (ADC_AWD2CR) */ + uint32_t awd3cr; /* ADC analog watchdog 2 configuration register (ADC_AWD2CR) */ + uint32_t __unused7[2]; /* */ + uint32_t difsel; /* ADC differential mode selection register (ADC_DIFSEL) */ + uint32_t calfact; /* ADC calibration factors (ADC_CALFACT) */ + uint32_t __unused8[2]; /* */ + uint32_t gcomp; /* ADC Gain compensation Register (ADC_GCOMP) */ + uint32_t csr; /* ADCx common status register (ADCx_CSR) (x = 12 or 345) */ + uint32_t __unused9[1]; /* */ + uint32_t ccr; /* ADCx common control register (ADCx_CCR) (x = 12 or 345) */ + uint32_t __unused10[192]; /* */ + uint32_t cdr; /* ADCx common regular data register for dual mode (ADCx_CDR) (x = 12 or 345) */ + +} hal_ll_adc_base_handle_t; + +/*!< @brief ADC hw specific module values */ +typedef struct +{ + uint16_t pin_an[ADC_MODULE_COUNT]; +} hal_ll_adc_pin_id; + +static hal_ll_adc_hw_specifics_map_t hal_ll_adc_hw_specifics_map[] = +{ + #ifdef ADC_MODULE_1 + {ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF}, + #endif + #ifdef ADC_MODULE_2 + {ADC2_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF}, + #endif + #ifdef ADC_MODULE_3 + {ADC3_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF}, + #endif + #ifdef ADC_MODULE_4 + {ADC4_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_4), HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF}, + #endif + #ifdef ADC_MODULE_5 + {ADC5_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_5), HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF}, + #endif + + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF} +}; + +// ------------------------------------------------------------------ VARIABLES + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_adc_handle_register_t *low_level_handle; +static volatile hal_ll_adc_hw_specifics_map_t *hal_ll_adc_hw_specifics_map_local; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Enable ADC module 1 clock. + * @param none + * @return none + */ +static inline void adc1_enable_clock(); +/** + * @brief Enable ADC module 2 clock. + * @param none + * @return none + */ +static inline void adc2_enable_clock(); +/** + * @brief Enable ADC module 3 clock. + * @param none + * @return none + */ +static inline void adc3_enable_clock(); +/** + * @brief Enable ADC module 4 clock. + * @param none + * @return none + */ +static inline void adc4_enable_clock(); +/** + * @brief Enable ADC module 5 clock. + * @param none + * @return none + */ +static inline void adc5_enable_clock(); + + +/** + * @brief Initialize ADC module. + * @param *map - ADC module local map. + * @return None + */ +static void hal_ll_adc_init( hal_ll_adc_hw_specifics_map_t *map ); + +/** + * @brief Check if pins are adequate. + * + * Checks analog pin the user has passed with pre-defined + * pins in ADC pin map. + * + * @param[in] pin - ADC pre-defined pin name. + * @param[in] *index - ADC map index value. + * @return hal_ll_pin_name_t Module index based on pin. + * + * Returns pre-defined module index from pin maps, if pin + * is adequate. + */ +static hal_ll_pin_name_t hal_ll_adc_check_pins( hal_ll_pin_name_t pin, hal_ll_adc_pin_id *index, hal_ll_adc_handle_register_t *handle_map ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and channel values for ADC pin + * + * @param[in] module_index ADC HW module index -- 0,1,2... + * @param[in] *index ADC map index value + * + * @return None + */ +static void hal_ll_adc_map_pin( uint8_t module_index, hal_ll_adc_pin_id *index ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_adc_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_adc_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_adc_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Enable ADC module gate clock. + * @param base - ADC module base address. + * @return None + */ +static void _hal_ll_adc_enable_clock( uint8_t base ); + +/** + * @brief Initialize ADC module. + * @param *base - ADC module base address. + * @param resolution - ADC module resolution. + * @return None + */ +static void _hal_ll_adc_hw_init( hal_ll_adc_base_handle_t *base, uint32_t resolution ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_adc_register_handle(hal_ll_pin_name_t pin, hal_ll_adc_voltage_reference_t vref_input, hal_ll_adc_resolution_t resolution, hal_ll_adc_handle_register_t *handle_map, uint8_t *hal_module_id) +{ + uint16_t pin_check_result; + hal_ll_adc_pin_id index = {HAL_LL_PIN_NC}; + + if ( (pin_check_result = hal_ll_adc_check_pins( pin, &index, handle_map )) == HAL_LL_PIN_NC ) { + return HAL_LL_ADC_WRONG_PIN; + }; + + switch ( resolution ) + { + case HAL_LL_ADC_RESOLUTION_12_BIT: + hal_ll_adc_hw_specifics_map[pin_check_result].resolution = HAL_LL_ADC_12BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_10_BIT: + hal_ll_adc_hw_specifics_map[pin_check_result].resolution = HAL_LL_ADC_10BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_8_BIT: + hal_ll_adc_hw_specifics_map[pin_check_result].resolution = HAL_LL_ADC_8BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_6_BIT: + hal_ll_adc_hw_specifics_map[pin_check_result].resolution = HAL_LL_ADC_6BIT_RES; + break; + default: + return HAL_LL_ADC_UNSUPPORTED_RESOLUTION; + } + + switch ( vref_input ) + { + case HAL_LL_ADC_VREF_EXTERNAL: + break; + + default: + return HAL_LL_ADC_UNSUPPORTED_VREF; + } + + if ( hal_ll_adc_hw_specifics_map[pin_check_result].pin != pin ) + { + hal_ll_adc_map_pin( pin_check_result, &index ); + + handle_map[pin_check_result].init_ll_state = false; + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[pin_check_result].hal_ll_adc_handle = (handle_t *)&hal_ll_adc_hw_specifics_map[pin_check_result].base; + + handle_map[pin_check_result].hal_ll_adc_handle = (handle_t *)&hal_ll_module_state[pin_check_result].hal_ll_adc_handle; + + return HAL_LL_ADC_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_adc( handle_t *handle ) +{ + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + hal_ll_adc_handle_register_t *hal_handle = (hal_ll_adc_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_adc_hw_specifics_map_local->module_index; + + hal_ll_adc_init( hal_ll_adc_hw_specifics_map_local ); + + hal_ll_module_state[pin_check_result].hal_ll_adc_handle = (handle_t *)&hal_ll_adc_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_ADC_SUCCESS; +} + +hal_ll_err_t hal_ll_adc_set_resolution(handle_t *handle, hal_ll_adc_resolution_t resolution) +{ + low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + + low_level_handle->init_ll_state = false; + + switch( resolution ) { + case HAL_LL_ADC_RESOLUTION_12_BIT: + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_12BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_10_BIT: + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_10BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_8_BIT: + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_8BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_6_BIT: + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_6BIT_RES; + break; + + default: + return HAL_LL_ADC_UNSUPPORTED_RESOLUTION; + } + + hal_ll_adc_init( hal_ll_adc_hw_specifics_map_local ); + + low_level_handle->init_ll_state = true; + + return HAL_LL_ADC_SUCCESS; +} + +hal_ll_err_t hal_ll_adc_set_vref_input(handle_t *handle, hal_ll_adc_voltage_reference_t vref_input) +{ + low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + + low_level_handle->init_ll_state = false; + + switch( vref_input ) { + case HAL_LL_ADC_VREF_EXTERNAL: + break; + + default: + return HAL_LL_ADC_UNSUPPORTED_VREF; + } + + hal_ll_adc_init( hal_ll_adc_hw_specifics_map_local ); + + low_level_handle->init_ll_state = true; + + return HAL_LL_ADC_SUCCESS; +} + +void hal_ll_adc_set_vref_value(handle_t *handle, float vref_value) +{ + low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + + hal_ll_adc_hw_specifics_map_local->vref_value = vref_value; +} + +hal_ll_err_t hal_ll_adc_read( handle_t *handle, uint16_t *readDatabuf ) +{ + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_base_handle_t *base = ( hal_ll_adc_base_handle_t * )hal_ll_adc_hw_specifics_map_local->base ; + + while( ( check_reg_bit( &( base->cr ), HAL_LL_ADC_ADSTART_BIT ) ) ); + base->sqr1 &= ~HAL_LL_ADC_CONVERSION_ONE; + base->sqr1 |= ( ( hal_ll_adc_hw_specifics_map_local->channel << 6 ) ); + + Delay_1us(); + + // Start the conversion. + set_reg_bit( &( base->cr ), HAL_LL_ADC_ADSTART_BIT ); + + while ( !( check_reg_bit( &( base->isr ), HAL_LL_ADC_EOC_BIT ) ) ); + // Conversion result from SS3. + *readDatabuf = base->dr; + + return HAL_LL_ADC_SUCCESS; +} + +void hal_ll_adc_close( handle_t *handle ) +{ + hal_ll_adc_hw_specifics_map_t *hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + low_level_handle = hal_ll_adc_get_handle; + + if( hal_ll_adc_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + + hal_ll_adc_hw_specifics_map_local->vref_input = HAL_LL_ADC_VREF_DEFAULT; + hal_ll_adc_hw_specifics_map_local->vref_value = 0; + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_RESOLUTION_12_BIT; + + low_level_handle->hal_ll_adc_handle = NULL; + low_level_handle->hal_drv_adc_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_adc_hw_specifics_map_local->pin = HAL_LL_PIN_NC; + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static hal_ll_pin_name_t hal_ll_adc_check_pins( hal_ll_pin_name_t pin, hal_ll_adc_pin_id *index, hal_ll_adc_handle_register_t *handle_map ) +{ + static const uint16_t adc_map_size = ( sizeof( _adc_map ) / sizeof( hal_ll_adc_pin_map_t ) ); + uint16_t pin_index = 0; + uint8_t index_counter = 0; + uint8_t hal_ll_module_id = 0; + + if ( HAL_LL_PIN_NC == pin ) { + return HAL_LL_PIN_NC; + } + + for ( pin_index = 0; pin_index < adc_map_size; pin_index++ ) + { + if ( pin == _adc_map[pin_index].pin ) + { + // Get module number + hal_ll_module_id = _adc_map[pin_index].module_index; + // Map pin name + index->pin_an[hal_ll_module_id] = pin_index; + + // Check if module is taken + if ( NULL == handle_map[ hal_ll_module_id ].hal_drv_adc_handle ) { + return hal_ll_module_id; + } else if ( ADC_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static void hal_ll_adc_map_pin( uint8_t module_index, hal_ll_adc_pin_id *index ) { + // Map new pins + hal_ll_adc_hw_specifics_map[module_index].pin = _adc_map[ index->pin_an[module_index] ].pin; + hal_ll_adc_hw_specifics_map[module_index].channel = _adc_map[ index->pin_an[module_index] ].channel; +} + +static hal_ll_adc_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof(hal_ll_adc_handle_register_t)); + static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof(hal_ll_adc_handle_register_t)); + + while( hal_ll_module_count-- ) { + if (hal_ll_adc_get_base_from_hal_handle == hal_ll_adc_hw_specifics_map[hal_ll_module_count].base) { + return &hal_ll_adc_hw_specifics_map[hal_ll_module_count]; + } + } + + return &hal_ll_adc_hw_specifics_map[hal_ll_module_error]; +} +static inline void adc1_enable_clock() +{ + set_reg_bit( _RCC_AHB2ENR, HAL_LL_ADC1_ENABLE_CLOCK ); +} +static inline void adc2_enable_clock() +{ + set_reg_bit( _RCC_AHB2ENR, HAL_LL_ADC2_ENABLE_CLOCK ); +} +static inline void adc3_enable_clock() +{ + set_reg_bit( _RCC_AHB2ENR, HAL_LL_ADC3_ENABLE_CLOCK ); +} +static inline void adc4_enable_clock() +{ + set_reg_bit( _RCC_AHB2ENR, HAL_LL_ADC4_ENABLE_CLOCK ); +} +static inline void adc5_enable_clock() +{ + set_reg_bit( _RCC_AHB2ENR, HAL_LL_ADC5_ENABLE_CLOCK ); +} + +static void _hal_ll_adc_enable_clock( uint8_t base ) +{ + switch ( base ) + { + #ifdef ADC_MODULE_1 + case ( hal_ll_adc_module_num(ADC_MODULE_1) ): + adc1_enable_clock(); + break; + #endif + #ifdef ADC_MODULE_2 + case ( hal_ll_adc_module_num(ADC_MODULE_2) ): + adc2_enable_clock(); + break; + #endif + #ifdef ADC_MODULE_3 + case ( hal_ll_adc_module_num(ADC_MODULE_3) ): + adc3_enable_clock(); + break; + #endif + #ifdef ADC_MODULE_4 + case ( hal_ll_adc_module_num(ADC_MODULE_4) ): + adc4_enable_clock(); + break; + #endif + #ifdef ADC_MODULE_5 + case ( hal_ll_adc_module_num(ADC_MODULE_5) ): + adc5_enable_clock(); + break; + #endif + } +} +static void _hal_ll_adc_hw_init( hal_ll_adc_base_handle_t *base, uint32_t resolution ) +{ + static uint32_t wait_loop_index = 0; + static uint32_t *reg; + reg = HAL_LL_ADC_CCIPR; + + // Select ADC clock source. + *reg |= HAL_LL_ADC_CLK_SRC; + + // Exit from deep power down mode. + if ( check_reg_bit( &( base->cr ), HAL_LL_ADC_DEEPPWD_BIT ) ) + { + clear_reg_bit( &( base->cr ), HAL_LL_ADC_DEEPPWD_BIT ); + } + + // Enable voltage regulator. + base->cr &= HAL_LL_ADC_VOLTAGE; + + if ( !( check_reg_bit( &( base->cr ), HAL_LL_ADC_ADVREGEN_BIT ) ) ) + { + set_reg_bit( &( base->cr ), HAL_LL_ADC_ADVREGEN_BIT ); + } + + // Enable ADC interrupts. + set_reg_bit( &( base->ier ), HAL_LL_ADC_ADRDYIE_BIT ); + + // Disable ADC + if ( check_reg_bit( &( base->cr ), HAL_LL_ADC_ADEN_BIT ) ) + { + set_reg_bit( &( base->cr ), HAL_LL_ADC_ADDIS_BIT ); + } + + // Voltage reference enable, ckmode SYSCLK. + reg = HAL_LL_ADC_CCR; + *reg |= (HAL_LL_ADC_CKMODE_MASK | HAL_LL_ADC_VREFEN_MASK); + + // Select calibration mode. + clear_reg_bit( &( base->cr ), HAL_LL_ADC_ADCALDIF_BIT ); + + // Start ADC calibration. + set_reg_bit( &( base->cr ), HAL_LL_ADC_ADCAL_BIT ); + + // Wait for calibration. + while ( check_reg_bit( &( base->cr ), HAL_LL_ADC_ADCAL_BIT ) ); + + // Prescaler. + *reg &= HAL_LL_ADC_PRESCALER; + + // Clear ADRDY bit ADC_ISR by writting 1. + set_reg_bit( &( base->isr ), HAL_LL_ADC_ADRDY_BIT ); + + // Set delay for voltage regulator to be initialized correctly. + wait_loop_index = 10 * ( Get_Fosc_kHz() / 1000 ); + while( wait_loop_index != 0 ) + { + wait_loop_index--; + } + + // Enable ADC. + set_reg_bit( &( base->cr ), HAL_LL_ADC_ADEN_BIT ); + + // ADRDY bit. + while ( !( check_reg_bit( &( base->cr ), HAL_LL_ADC_ADRDY_BIT ) ) ); + + // Resolution. + base->cfgr &= HAL_LL_RESOLUTION_MASK; + base->cfgr |= resolution; + + // Data alignment. + clear_reg_bit( &( base->cfgr ), HAL_LL_ADC_ALIGN_BIT ); + + // Discontinuos mode disabled. + clear_reg_bit( &( base->cfgr ), HAL_LL_ADC_DISCEN_BIT ); + + // Continuos conversion mode. + clear_reg_bit( &( base->cfgr ), HAL_LL_ADC_CONT_BIT ); + + // Regular channel sequence length. + base->sqr1 &= HAL_LL_ADC_CONVERSION; +} + +static void hal_ll_adc_init( hal_ll_adc_hw_specifics_map_t *map ) { + + + hal_ll_gpio_analog_input( hal_ll_gpio_port_base( hal_ll_gpio_port_index( map->pin ) ), + hal_ll_gpio_pin_mask( map->pin ) ); + + _hal_ll_adc_enable_clock( map->module_index ); + + _hal_ll_adc_hw_init((hal_ll_adc_base_handle_t *)map->base, map->resolution); + +} + + +// ------------------------------------------------------------------------- END + + + + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_88/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_88/CMakeLists.cmake new file mode 100644 index 000000000..32e12ff47 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_88/CMakeLists.cmake @@ -0,0 +1,10 @@ +if(${MCU_NAME} MATCHES "^STM32G491CC$|^STM32G491KC$|^STM32G491RC$|^STM32G491VC$|^STM32G491MC$|^STM32G491CE$|^STM32G491KE$|^STM32G491RE$|^STM32G491VE$|^STM32G491ME$") + set(adc_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_adc.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_88") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_88") + list(APPEND hal_ll_def_list "STM32G4xx") + list(APPEND hal_ll_def_list "STM32G49xx") + list(APPEND hal_ll_def_list "STM32G491xx") + set(adc_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/adc/hal_ll_adc_pin_map/implementations/doc_ds_88") + list(APPEND hal_ll_def_list "HAL_LL_ADC_RESOLUTION_CMAKE=HAL_LL_ADC_RESOLUTION_12_BIT") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_88/hal_ll_adc.c b/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_88/hal_ll_adc.c new file mode 100644 index 000000000..753410cc5 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_88/hal_ll_adc.c @@ -0,0 +1,652 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_adc.c + * @brief Low level HAL ADC source file. + */ + +#include "hal_ll_adc.h" +#include "hal_ll_gpio.h" +#include "hal_ll_adc_pin_map.h" + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_adc_get_module_state_address ((hal_ll_adc_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_adc_get_handle (hal_ll_adc_handle_register_t *)hal_ll_adc_get_module_state_address->hal_ll_adc_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_adc_get_base_struct(_handle) ((hal_ll_adc_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_adc_get_base_from_hal_handle ((hal_ll_adc_hw_specifics_map_t *)((hal_ll_adc_handle_register_t *)\ + (((hal_ll_adc_handle_register_t *)(handle))->hal_ll_adc_handle))->hal_ll_adc_handle)->base +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_adc_module_num(_module_num) (_module_num - 1) + +// ADC common registers. + +#define hal_ll_adc_module_num(_module_num) (_module_num - 1) + +#define HAL_LL_ADC_CSR_OFFSET ( 0x300 / 4 ) +#define HAL_LL_ADC_CCR_OFFSET ( 0x308 / 4 ) +#define HAL_LL_ADC_CDR_OFFSET ( 0x30C / 4 ) + + +#define HAL_LL_ADC_APB2ENR_SYSCFGEN 0 +#define HAL_LL_ADC_VREF_ENVR 0 +#define HAL_LL_ADC_ADRDYIE_BIT 0 +#define HAL_LL_ADC_ADEN_BIT 0 +#define HAL_LL_ADC_ADRDY_BIT 0 +#define HAL_LL_ADC_ADDIS_BIT 1 +#define HAL_LL_ADC_EOC_BIT 2 +#define HAL_LL_ADC_ADSTART_BIT 2 +#define HAL_LL_ADC_RESOLUTION_BIT0 3 +#define HAL_LL_ADC_RESOLUTION_BIT1 4 +#define HAL_LL_ADC_VREF_VRR 3 +#define HAL_LL_ADC_ALIGN_BIT 15 + +#define HAL_LL_ADC1_ENABLE_CLOCK 13 +#define HAL_LL_ADC2_ENABLE_CLOCK 13 +#define HAL_LL_ADC3_ENABLE_CLOCK 14 + +#define HAL_LL_ADC_CONT_BIT 13 +#define HAL_LL_ADC_DISCEN_BIT 16 +#define HAL_LL_ADC_ADVREGEN_BIT 28 +#define HAL_LL_ADC_DEEPPWD_BIT 29 +#define HAL_LL_ADC_ADCALDIF_BIT 30 +#define HAL_LL_ADC_ADCAL_BIT 31 +#define HAL_LL_ADC_PIN_MASK 0xF + +#define HAL_LL_ADC_12BIT_RES 0x00000000ul +#define HAL_LL_ADC_10BIT_RES 0x00000008ul +#define HAL_LL_ADC_8BIT_RES 0x00000010ul +#define HAL_LL_ADC_6BIT_RES 0x00000018ul + +#define ADC_CAL_SINGLE 0x00000000ul +#define ADC_CAL_DIF 0x00000001ul +#define HAL_LL_ADC_CLK_SRC 0xF0000000ul +#define HAL_LL_ADC_VOLTAGE 0xCFFFFFFFul +#define HAL_LL_ADC_CCR 0x50000308ul +#define HAL_LL_ADC_CKMODE_MASK 0x00000000ul +#define HAL_LL_ADC_VREFEN_MASK 0x00400000ul +#define HAL_LL_ADC_CCIPR 0x40021088ul +#define HAL_LL_ADC_PRESCALER 0xFFC3FFFFul +#define HAL_LL_ADC_CONVERSION 0xFFFFFFF0ul + +#define HAL_LL_ADC_CONVERSION_ONE 0x000007C0ul + +#define HAL_LL_MODULE_INDEX_ERROR 0xFFFFFFFFul + +#define HAL_LL_RESOLUTION_MASK 0xFFFFFFE7ul + +#define HAL_LL_ADC_DEFAULT_BASE_ADDRESS 0xFF + + +// -------------------------------------------------------------- PRIVATE TYPES +/*!< @brief Local handle list */ +static hal_ll_adc_handle_register_t hal_ll_module_state[ADC_MODULE_COUNT] = { (handle_t *) NULL, (handle_t *) NULL, false }; + +/** + * Return values + */ +typedef enum +{ + HAL_LL_ADC_SUCCESS = 0, + HAL_LL_ADC_WRONG_PIN, + + HAL_LL_ADC_UNSUPPORTED_RESOLUTION = 1100, + HAL_LL_ADC_UNSUPPORTED_VREF, + HAL_LL_ADC_WRONG_CHANNEL, + HAL_LL_ADC_ERROR = (-1) +} hal_ll_adc_err_t; + +/*!< @brief ADC register structure. */ +typedef struct +{ + uint32_t isr; /* ADC interrupt and status register (ADC_ISR) */ + uint32_t ier; /* ADC interrupt enable register (ADC_IER) */ + uint32_t cr; /* ADC control register (ADC_CR) */ + uint32_t cfgr; /* ADC configuration register (ADC_CFGR) */ + uint32_t cfgr2; /* ADC configuration register (ADC_CFGR) */ + uint32_t smpr1; /* ADC sample time register 1 (ADC_SMPR1) */ + uint32_t smpr2; /* ADC sample time register 1 (ADC_SMPR1) */ + uint32_t __unused1[1]; /* */ + uint32_t tr1; /* ADC watchdog threshold register 1 (ADC_TR1) */ + uint32_t tr2; /* ADC watchdog threshold register 1 (ADC_TR1) */ + uint32_t tr3; /* ADC watchdog threshold register 1 (ADC_TR1) */ + uint32_t __unused2[1]; /* */ + uint32_t sqr1; /* ADC regular sequence register 1 (ADC_SQR1) */ + uint32_t sqr2; /* ADC regular sequence register 1 (ADC_SQR1) */ + uint32_t sqr3; /* ADC regular sequence register 1 (ADC_SQR1) */ + uint32_t sqr4; /* ADC regular sequence register 1 (ADC_SQR1) */ + uint32_t dr; /* ADC regular data register (ADC_DR) */ + uint32_t __unused3[2]; /* */ + uint32_t jsqr; /* ADC injected sequence register (ADC_JSQR) */ + uint32_t __unused4[4]; /* */ + uint32_t ofr1; /* ADC offset y register (ADC_OFRy) */ + uint32_t ofr2; /* ADC offset y register (ADC_OFRy) */ + uint32_t ofr3; /* ADC offset y register (ADC_OFRy) */ + uint32_t ofr4; /* ADC offset y register (ADC_OFRy) */ + uint32_t __unused5[4]; /* */ + uint32_t jdr1; /* ADC injected channel y data register (ADC_JDRy) */ + uint32_t jdr2; /* ADC injected channel y data register (ADC_JDRy) */ + uint32_t jdr3; /* ADC injected channel y data register (ADC_JDRy) */ + uint32_t jdr4; /* ADC injected channel y data register (ADC_JDRy) */ + uint32_t __unused6[4]; /* */ + uint32_t awd2cr; /* ADC analog watchdog 2 configuration register (ADC_AWD2CR) */ + uint32_t awd3cr; /* ADC analog watchdog 2 configuration register (ADC_AWD2CR) */ + uint32_t __unused7[2]; /* */ + uint32_t difsel; /* ADC differential mode selection register (ADC_DIFSEL) */ + uint32_t calfact; /* ADC calibration factors (ADC_CALFACT) */ + uint32_t __unused8[2]; /* */ + uint32_t gcomp; /* ADC Gain compensation Register (ADC_GCOMP) */ + uint32_t csr; /* ADCx common status register (ADCx_CSR) (x = 12 or 345) */ + uint32_t __unused9[1]; /* */ + uint32_t ccr; /* ADCx common control register (ADCx_CCR) (x = 12 or 345) */ + uint32_t __unused10[192]; /* */ + uint32_t cdr; /* ADCx common regular data register for dual mode (ADCx_CDR) (x = 12 or 345) */ + +} hal_ll_adc_base_handle_t; + +/*!< @brief ADC hw specific module values */ +typedef struct +{ + uint16_t pin_an[ADC_MODULE_COUNT]; +} hal_ll_adc_pin_id; + +static hal_ll_adc_hw_specifics_map_t hal_ll_adc_hw_specifics_map[] = +{ + #ifdef ADC_MODULE_1 + {ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF}, + #endif + #ifdef ADC_MODULE_2 + {ADC2_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF}, + #endif + #ifdef ADC_MODULE_3 + {ADC3_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF}, + #endif + + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF} +}; + +// ------------------------------------------------------------------ VARIABLES + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_adc_handle_register_t *low_level_handle; +static volatile hal_ll_adc_hw_specifics_map_t *hal_ll_adc_hw_specifics_map_local; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Enable ADC module 1 clock. + * @param none + * @return none + */ +static inline void adc1_enable_clock(); +/** + * @brief Enable ADC module 2 clock. + * @param none + * @return none + */ +static inline void adc2_enable_clock(); +/** + * @brief Enable ADC module 3 clock. + * @param none + * @return none + */ +static inline void adc3_enable_clock(); + + +/** + * @brief Initialize ADC module. + * @param *map - ADC module local map. + * @return None + */ +static void hal_ll_adc_init( hal_ll_adc_hw_specifics_map_t *map ); + +/** + * @brief Check if pins are adequate. + * + * Checks analog pin the user has passed with pre-defined + * pins in ADC pin map. + * + * @param[in] pin - ADC pre-defined pin name. + * @param[in] *index - ADC map index value. + * @return hal_ll_pin_name_t Module index based on pin. + * + * Returns pre-defined module index from pin maps, if pin + * is adequate. + */ +static hal_ll_pin_name_t hal_ll_adc_check_pins( hal_ll_pin_name_t pin, hal_ll_adc_pin_id *index, hal_ll_adc_handle_register_t *handle_map ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and channel values for ADC pin + * + * @param[in] module_index ADC HW module index -- 0,1,2... + * @param[in] *index ADC map index value + * + * @return None + */ +static void hal_ll_adc_map_pin( uint8_t module_index, hal_ll_adc_pin_id *index ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_adc_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_adc_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_adc_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Enable ADC module gate clock. + * @param base - ADC module base address. + * @return None + */ +static void _hal_ll_adc_enable_clock( uint8_t base ); + +/** + * @brief Initialize ADC module. + * @param *base - ADC module base address. + * @param resolution - ADC module resolution. + * @return None + */ +static void _hal_ll_adc_hw_init( hal_ll_adc_base_handle_t *base, uint32_t resolution ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_adc_register_handle(hal_ll_pin_name_t pin, hal_ll_adc_voltage_reference_t vref_input, hal_ll_adc_resolution_t resolution, hal_ll_adc_handle_register_t *handle_map, uint8_t *hal_module_id) +{ + uint16_t pin_check_result; + hal_ll_adc_pin_id index = {HAL_LL_PIN_NC}; + + if ( (pin_check_result = hal_ll_adc_check_pins( pin, &index, handle_map )) == HAL_LL_PIN_NC ) { + return HAL_LL_ADC_WRONG_PIN; + }; + + switch ( resolution ) + { + case HAL_LL_ADC_RESOLUTION_12_BIT: + hal_ll_adc_hw_specifics_map[pin_check_result].resolution = HAL_LL_ADC_12BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_10_BIT: + hal_ll_adc_hw_specifics_map[pin_check_result].resolution = HAL_LL_ADC_10BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_8_BIT: + hal_ll_adc_hw_specifics_map[pin_check_result].resolution = HAL_LL_ADC_8BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_6_BIT: + hal_ll_adc_hw_specifics_map[pin_check_result].resolution = HAL_LL_ADC_6BIT_RES; + break; + default: + return HAL_LL_ADC_UNSUPPORTED_RESOLUTION; + } + + switch ( vref_input ) + { + case HAL_LL_ADC_VREF_EXTERNAL: + break; + + default: + return HAL_LL_ADC_UNSUPPORTED_VREF; + } + + if ( hal_ll_adc_hw_specifics_map[pin_check_result].pin != pin ) + { + hal_ll_adc_map_pin( pin_check_result, &index ); + + handle_map[pin_check_result].init_ll_state = false; + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[pin_check_result].hal_ll_adc_handle = (handle_t *)&hal_ll_adc_hw_specifics_map[pin_check_result].base; + + handle_map[pin_check_result].hal_ll_adc_handle = (handle_t *)&hal_ll_module_state[pin_check_result].hal_ll_adc_handle; + + return HAL_LL_ADC_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_adc( handle_t *handle ) +{ + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + hal_ll_adc_handle_register_t *hal_handle = (hal_ll_adc_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_adc_hw_specifics_map_local->module_index; + + hal_ll_adc_init( hal_ll_adc_hw_specifics_map_local ); + + hal_ll_module_state[pin_check_result].hal_ll_adc_handle = (handle_t *)&hal_ll_adc_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_ADC_SUCCESS; +} + +hal_ll_err_t hal_ll_adc_set_resolution(handle_t *handle, hal_ll_adc_resolution_t resolution) +{ + low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + + low_level_handle->init_ll_state = false; + + switch( resolution ) { + case HAL_LL_ADC_RESOLUTION_12_BIT: + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_12BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_10_BIT: + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_10BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_8_BIT: + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_8BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_6_BIT: + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_6BIT_RES; + break; + + default: + return HAL_LL_ADC_UNSUPPORTED_RESOLUTION; + } + + hal_ll_adc_init( hal_ll_adc_hw_specifics_map_local ); + + low_level_handle->init_ll_state = true; + + return HAL_LL_ADC_SUCCESS; +} + +hal_ll_err_t hal_ll_adc_set_vref_input(handle_t *handle, hal_ll_adc_voltage_reference_t vref_input) +{ + low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + + low_level_handle->init_ll_state = false; + + switch( vref_input ) { + case HAL_LL_ADC_VREF_EXTERNAL: + break; + + default: + return HAL_LL_ADC_UNSUPPORTED_VREF; + } + + hal_ll_adc_init( hal_ll_adc_hw_specifics_map_local ); + + low_level_handle->init_ll_state = true; + + return HAL_LL_ADC_SUCCESS; +} + +void hal_ll_adc_set_vref_value(handle_t *handle, float vref_value) +{ + low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + + hal_ll_adc_hw_specifics_map_local->vref_value = vref_value; +} + +hal_ll_err_t hal_ll_adc_read( handle_t *handle, uint16_t *readDatabuf ) +{ + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_base_handle_t *base = ( hal_ll_adc_base_handle_t * )hal_ll_adc_hw_specifics_map_local->base ; + + while( ( check_reg_bit( &( base->cr ), HAL_LL_ADC_ADSTART_BIT ) ) ); + base->sqr1 &= ~HAL_LL_ADC_CONVERSION_ONE; + base->sqr1 |= ( ( hal_ll_adc_hw_specifics_map_local->channel << 6 ) ); + + Delay_1us(); + + // Start the conversion. + set_reg_bit( &( base->cr ), HAL_LL_ADC_ADSTART_BIT ); + + while ( !( check_reg_bit( &( base->isr ), HAL_LL_ADC_EOC_BIT ) ) ); + // Conversion result from SS3. + *readDatabuf = base->dr; + + return HAL_LL_ADC_SUCCESS; +} + +void hal_ll_adc_close( handle_t *handle ) +{ + hal_ll_adc_hw_specifics_map_t *hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + low_level_handle = hal_ll_adc_get_handle; + + if( hal_ll_adc_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + + hal_ll_adc_hw_specifics_map_local->vref_input = HAL_LL_ADC_VREF_DEFAULT; + hal_ll_adc_hw_specifics_map_local->vref_value = 0; + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_RESOLUTION_12_BIT; + + low_level_handle->hal_ll_adc_handle = NULL; + low_level_handle->hal_drv_adc_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_adc_hw_specifics_map_local->pin = HAL_LL_PIN_NC; + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static hal_ll_pin_name_t hal_ll_adc_check_pins( hal_ll_pin_name_t pin, hal_ll_adc_pin_id *index, hal_ll_adc_handle_register_t *handle_map ) +{ + static const uint16_t adc_map_size = ( sizeof( _adc_map ) / sizeof( hal_ll_adc_pin_map_t ) ); + uint16_t pin_index = 0; + uint8_t index_counter = 0; + uint8_t hal_ll_module_id = 0; + + if ( HAL_LL_PIN_NC == pin ) { + return HAL_LL_PIN_NC; + } + + for ( pin_index = 0; pin_index < adc_map_size; pin_index++ ) + { + if ( pin == _adc_map[pin_index].pin ) + { + // Get module number + hal_ll_module_id = _adc_map[pin_index].module_index; + // Map pin name + index->pin_an[hal_ll_module_id] = pin_index; + + // Check if module is taken + if ( NULL == handle_map[ hal_ll_module_id ].hal_drv_adc_handle ) { + return hal_ll_module_id; + } else if ( ADC_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static void hal_ll_adc_map_pin( uint8_t module_index, hal_ll_adc_pin_id *index ) { + // Map new pins + hal_ll_adc_hw_specifics_map[module_index].pin = _adc_map[ index->pin_an[module_index] ].pin; + hal_ll_adc_hw_specifics_map[module_index].channel = _adc_map[ index->pin_an[module_index] ].channel; +} + +static hal_ll_adc_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof(hal_ll_adc_handle_register_t)); + static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof(hal_ll_adc_handle_register_t)); + + while( hal_ll_module_count-- ) { + if (hal_ll_adc_get_base_from_hal_handle == hal_ll_adc_hw_specifics_map[hal_ll_module_count].base) { + return &hal_ll_adc_hw_specifics_map[hal_ll_module_count]; + } + } + + return &hal_ll_adc_hw_specifics_map[hal_ll_module_error]; +} +static inline void adc1_enable_clock() +{ + set_reg_bit( _RCC_AHB2ENR, HAL_LL_ADC1_ENABLE_CLOCK ); +} +static inline void adc2_enable_clock() +{ + set_reg_bit( _RCC_AHB2ENR, HAL_LL_ADC2_ENABLE_CLOCK ); +} +static inline void adc3_enable_clock() +{ + set_reg_bit( _RCC_AHB2ENR, HAL_LL_ADC3_ENABLE_CLOCK ); +} + +static void _hal_ll_adc_enable_clock( uint8_t base ) +{ + switch ( base ) + { + #ifdef ADC_MODULE_1 + case ( hal_ll_adc_module_num(ADC_MODULE_1) ): + adc1_enable_clock(); + break; + #endif + #ifdef ADC_MODULE_2 + case ( hal_ll_adc_module_num(ADC_MODULE_2) ): + adc2_enable_clock(); + break; + #endif + #ifdef ADC_MODULE_3 + case ( hal_ll_adc_module_num(ADC_MODULE_3) ): + adc3_enable_clock(); + break; + #endif + } +} +static void _hal_ll_adc_hw_init( hal_ll_adc_base_handle_t *base, uint32_t resolution ) +{ + static uint32_t wait_loop_index = 0; + static uint32_t *reg; + reg = HAL_LL_ADC_CCIPR; + + // Select ADC clock source. + *reg |= HAL_LL_ADC_CLK_SRC; + + // Exit from deep power down mode. + if ( check_reg_bit( &( base->cr ), HAL_LL_ADC_DEEPPWD_BIT ) ) + { + clear_reg_bit( &( base->cr ), HAL_LL_ADC_DEEPPWD_BIT ); + } + + // Enable voltage regulator. + base->cr &= HAL_LL_ADC_VOLTAGE; + + if ( !( check_reg_bit( &( base->cr ), HAL_LL_ADC_ADVREGEN_BIT ) ) ) + { + set_reg_bit( &( base->cr ), HAL_LL_ADC_ADVREGEN_BIT ); + } + + // Enable ADC interrupts. + set_reg_bit( &( base->ier ), HAL_LL_ADC_ADRDYIE_BIT ); + + // Disable ADC + if ( check_reg_bit( &( base->cr ), HAL_LL_ADC_ADEN_BIT ) ) + { + set_reg_bit( &( base->cr ), HAL_LL_ADC_ADDIS_BIT ); + } + + // Voltage reference enable, ckmode SYSCLK. + reg = HAL_LL_ADC_CCR; + *reg |= (HAL_LL_ADC_CKMODE_MASK | HAL_LL_ADC_VREFEN_MASK); + + // Select calibration mode. + clear_reg_bit( &( base->cr ), HAL_LL_ADC_ADCALDIF_BIT ); + + // Start ADC calibration. + set_reg_bit( &( base->cr ), HAL_LL_ADC_ADCAL_BIT ); + + // Wait for calibration. + while ( check_reg_bit( &( base->cr ), HAL_LL_ADC_ADCAL_BIT ) ); + + // Prescaler. + *reg &= HAL_LL_ADC_PRESCALER; + + // Clear ADRDY bit ADC_ISR by writting 1. + set_reg_bit( &( base->isr ), HAL_LL_ADC_ADRDY_BIT ); + + // Set delay for voltage regulator to be initialized correctly. + wait_loop_index = 10 * ( Get_Fosc_kHz() / 1000 ); + while( wait_loop_index != 0 ) + { + wait_loop_index--; + } + + // Enable ADC. + set_reg_bit( &( base->cr ), HAL_LL_ADC_ADEN_BIT ); + + // ADRDY bit. + while ( !( check_reg_bit( &( base->cr ), HAL_LL_ADC_ADRDY_BIT ) ) ); + + // Resolution. + base->cfgr &= HAL_LL_RESOLUTION_MASK; + base->cfgr |= resolution; + + // Data alignment. + clear_reg_bit( &( base->cfgr ), HAL_LL_ADC_ALIGN_BIT ); + + // Discontinuos mode disabled. + clear_reg_bit( &( base->cfgr ), HAL_LL_ADC_DISCEN_BIT ); + + // Continuos conversion mode. + clear_reg_bit( &( base->cfgr ), HAL_LL_ADC_CONT_BIT ); + + // Regular channel sequence length. + base->sqr1 &= HAL_LL_ADC_CONVERSION; +} + +static void hal_ll_adc_init( hal_ll_adc_hw_specifics_map_t *map ) { + + + hal_ll_gpio_analog_input( hal_ll_gpio_port_base( hal_ll_gpio_port_index( map->pin ) ), + hal_ll_gpio_pin_mask( map->pin ) ); + + _hal_ll_adc_enable_clock( map->module_index ); + + _hal_ll_adc_hw_init((hal_ll_adc_base_handle_t *)map->base, map->resolution); + +} + + +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_89/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_89/CMakeLists.cmake new file mode 100644 index 000000000..3a45da179 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_89/CMakeLists.cmake @@ -0,0 +1,10 @@ +if(${MCU_NAME} MATCHES "^STM32G4A1CE$|^STM32G4A1KE$|^STM32G4A1ME$|^STM32G4A1RE$|^STM32G4A1VE$") + set(adc_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_adc.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_89") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_89") + list(APPEND hal_ll_def_list "STM32G4xx") + list(APPEND hal_ll_def_list "STM32G4Axx") + list(APPEND hal_ll_def_list "STM32G4A1xx") + set(adc_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/adc/hal_ll_adc_pin_map/implementations/doc_ds_89") + list(APPEND hal_ll_def_list "HAL_LL_ADC_RESOLUTION_CMAKE=HAL_LL_ADC_RESOLUTION_12_BIT") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_89/hal_ll_adc.c b/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_89/hal_ll_adc.c new file mode 100644 index 000000000..753410cc5 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/adc/implementations/doc_ds_89/hal_ll_adc.c @@ -0,0 +1,652 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_adc.c + * @brief Low level HAL ADC source file. + */ + +#include "hal_ll_adc.h" +#include "hal_ll_gpio.h" +#include "hal_ll_adc_pin_map.h" + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_adc_get_module_state_address ((hal_ll_adc_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_adc_get_handle (hal_ll_adc_handle_register_t *)hal_ll_adc_get_module_state_address->hal_ll_adc_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_adc_get_base_struct(_handle) ((hal_ll_adc_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_adc_get_base_from_hal_handle ((hal_ll_adc_hw_specifics_map_t *)((hal_ll_adc_handle_register_t *)\ + (((hal_ll_adc_handle_register_t *)(handle))->hal_ll_adc_handle))->hal_ll_adc_handle)->base +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_adc_module_num(_module_num) (_module_num - 1) + +// ADC common registers. + +#define hal_ll_adc_module_num(_module_num) (_module_num - 1) + +#define HAL_LL_ADC_CSR_OFFSET ( 0x300 / 4 ) +#define HAL_LL_ADC_CCR_OFFSET ( 0x308 / 4 ) +#define HAL_LL_ADC_CDR_OFFSET ( 0x30C / 4 ) + + +#define HAL_LL_ADC_APB2ENR_SYSCFGEN 0 +#define HAL_LL_ADC_VREF_ENVR 0 +#define HAL_LL_ADC_ADRDYIE_BIT 0 +#define HAL_LL_ADC_ADEN_BIT 0 +#define HAL_LL_ADC_ADRDY_BIT 0 +#define HAL_LL_ADC_ADDIS_BIT 1 +#define HAL_LL_ADC_EOC_BIT 2 +#define HAL_LL_ADC_ADSTART_BIT 2 +#define HAL_LL_ADC_RESOLUTION_BIT0 3 +#define HAL_LL_ADC_RESOLUTION_BIT1 4 +#define HAL_LL_ADC_VREF_VRR 3 +#define HAL_LL_ADC_ALIGN_BIT 15 + +#define HAL_LL_ADC1_ENABLE_CLOCK 13 +#define HAL_LL_ADC2_ENABLE_CLOCK 13 +#define HAL_LL_ADC3_ENABLE_CLOCK 14 + +#define HAL_LL_ADC_CONT_BIT 13 +#define HAL_LL_ADC_DISCEN_BIT 16 +#define HAL_LL_ADC_ADVREGEN_BIT 28 +#define HAL_LL_ADC_DEEPPWD_BIT 29 +#define HAL_LL_ADC_ADCALDIF_BIT 30 +#define HAL_LL_ADC_ADCAL_BIT 31 +#define HAL_LL_ADC_PIN_MASK 0xF + +#define HAL_LL_ADC_12BIT_RES 0x00000000ul +#define HAL_LL_ADC_10BIT_RES 0x00000008ul +#define HAL_LL_ADC_8BIT_RES 0x00000010ul +#define HAL_LL_ADC_6BIT_RES 0x00000018ul + +#define ADC_CAL_SINGLE 0x00000000ul +#define ADC_CAL_DIF 0x00000001ul +#define HAL_LL_ADC_CLK_SRC 0xF0000000ul +#define HAL_LL_ADC_VOLTAGE 0xCFFFFFFFul +#define HAL_LL_ADC_CCR 0x50000308ul +#define HAL_LL_ADC_CKMODE_MASK 0x00000000ul +#define HAL_LL_ADC_VREFEN_MASK 0x00400000ul +#define HAL_LL_ADC_CCIPR 0x40021088ul +#define HAL_LL_ADC_PRESCALER 0xFFC3FFFFul +#define HAL_LL_ADC_CONVERSION 0xFFFFFFF0ul + +#define HAL_LL_ADC_CONVERSION_ONE 0x000007C0ul + +#define HAL_LL_MODULE_INDEX_ERROR 0xFFFFFFFFul + +#define HAL_LL_RESOLUTION_MASK 0xFFFFFFE7ul + +#define HAL_LL_ADC_DEFAULT_BASE_ADDRESS 0xFF + + +// -------------------------------------------------------------- PRIVATE TYPES +/*!< @brief Local handle list */ +static hal_ll_adc_handle_register_t hal_ll_module_state[ADC_MODULE_COUNT] = { (handle_t *) NULL, (handle_t *) NULL, false }; + +/** + * Return values + */ +typedef enum +{ + HAL_LL_ADC_SUCCESS = 0, + HAL_LL_ADC_WRONG_PIN, + + HAL_LL_ADC_UNSUPPORTED_RESOLUTION = 1100, + HAL_LL_ADC_UNSUPPORTED_VREF, + HAL_LL_ADC_WRONG_CHANNEL, + HAL_LL_ADC_ERROR = (-1) +} hal_ll_adc_err_t; + +/*!< @brief ADC register structure. */ +typedef struct +{ + uint32_t isr; /* ADC interrupt and status register (ADC_ISR) */ + uint32_t ier; /* ADC interrupt enable register (ADC_IER) */ + uint32_t cr; /* ADC control register (ADC_CR) */ + uint32_t cfgr; /* ADC configuration register (ADC_CFGR) */ + uint32_t cfgr2; /* ADC configuration register (ADC_CFGR) */ + uint32_t smpr1; /* ADC sample time register 1 (ADC_SMPR1) */ + uint32_t smpr2; /* ADC sample time register 1 (ADC_SMPR1) */ + uint32_t __unused1[1]; /* */ + uint32_t tr1; /* ADC watchdog threshold register 1 (ADC_TR1) */ + uint32_t tr2; /* ADC watchdog threshold register 1 (ADC_TR1) */ + uint32_t tr3; /* ADC watchdog threshold register 1 (ADC_TR1) */ + uint32_t __unused2[1]; /* */ + uint32_t sqr1; /* ADC regular sequence register 1 (ADC_SQR1) */ + uint32_t sqr2; /* ADC regular sequence register 1 (ADC_SQR1) */ + uint32_t sqr3; /* ADC regular sequence register 1 (ADC_SQR1) */ + uint32_t sqr4; /* ADC regular sequence register 1 (ADC_SQR1) */ + uint32_t dr; /* ADC regular data register (ADC_DR) */ + uint32_t __unused3[2]; /* */ + uint32_t jsqr; /* ADC injected sequence register (ADC_JSQR) */ + uint32_t __unused4[4]; /* */ + uint32_t ofr1; /* ADC offset y register (ADC_OFRy) */ + uint32_t ofr2; /* ADC offset y register (ADC_OFRy) */ + uint32_t ofr3; /* ADC offset y register (ADC_OFRy) */ + uint32_t ofr4; /* ADC offset y register (ADC_OFRy) */ + uint32_t __unused5[4]; /* */ + uint32_t jdr1; /* ADC injected channel y data register (ADC_JDRy) */ + uint32_t jdr2; /* ADC injected channel y data register (ADC_JDRy) */ + uint32_t jdr3; /* ADC injected channel y data register (ADC_JDRy) */ + uint32_t jdr4; /* ADC injected channel y data register (ADC_JDRy) */ + uint32_t __unused6[4]; /* */ + uint32_t awd2cr; /* ADC analog watchdog 2 configuration register (ADC_AWD2CR) */ + uint32_t awd3cr; /* ADC analog watchdog 2 configuration register (ADC_AWD2CR) */ + uint32_t __unused7[2]; /* */ + uint32_t difsel; /* ADC differential mode selection register (ADC_DIFSEL) */ + uint32_t calfact; /* ADC calibration factors (ADC_CALFACT) */ + uint32_t __unused8[2]; /* */ + uint32_t gcomp; /* ADC Gain compensation Register (ADC_GCOMP) */ + uint32_t csr; /* ADCx common status register (ADCx_CSR) (x = 12 or 345) */ + uint32_t __unused9[1]; /* */ + uint32_t ccr; /* ADCx common control register (ADCx_CCR) (x = 12 or 345) */ + uint32_t __unused10[192]; /* */ + uint32_t cdr; /* ADCx common regular data register for dual mode (ADCx_CDR) (x = 12 or 345) */ + +} hal_ll_adc_base_handle_t; + +/*!< @brief ADC hw specific module values */ +typedef struct +{ + uint16_t pin_an[ADC_MODULE_COUNT]; +} hal_ll_adc_pin_id; + +static hal_ll_adc_hw_specifics_map_t hal_ll_adc_hw_specifics_map[] = +{ + #ifdef ADC_MODULE_1 + {ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF}, + #endif + #ifdef ADC_MODULE_2 + {ADC2_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF}, + #endif + #ifdef ADC_MODULE_3 + {ADC3_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF}, + #endif + + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF} +}; + +// ------------------------------------------------------------------ VARIABLES + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_adc_handle_register_t *low_level_handle; +static volatile hal_ll_adc_hw_specifics_map_t *hal_ll_adc_hw_specifics_map_local; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Enable ADC module 1 clock. + * @param none + * @return none + */ +static inline void adc1_enable_clock(); +/** + * @brief Enable ADC module 2 clock. + * @param none + * @return none + */ +static inline void adc2_enable_clock(); +/** + * @brief Enable ADC module 3 clock. + * @param none + * @return none + */ +static inline void adc3_enable_clock(); + + +/** + * @brief Initialize ADC module. + * @param *map - ADC module local map. + * @return None + */ +static void hal_ll_adc_init( hal_ll_adc_hw_specifics_map_t *map ); + +/** + * @brief Check if pins are adequate. + * + * Checks analog pin the user has passed with pre-defined + * pins in ADC pin map. + * + * @param[in] pin - ADC pre-defined pin name. + * @param[in] *index - ADC map index value. + * @return hal_ll_pin_name_t Module index based on pin. + * + * Returns pre-defined module index from pin maps, if pin + * is adequate. + */ +static hal_ll_pin_name_t hal_ll_adc_check_pins( hal_ll_pin_name_t pin, hal_ll_adc_pin_id *index, hal_ll_adc_handle_register_t *handle_map ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and channel values for ADC pin + * + * @param[in] module_index ADC HW module index -- 0,1,2... + * @param[in] *index ADC map index value + * + * @return None + */ +static void hal_ll_adc_map_pin( uint8_t module_index, hal_ll_adc_pin_id *index ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_adc_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_adc_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_adc_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Enable ADC module gate clock. + * @param base - ADC module base address. + * @return None + */ +static void _hal_ll_adc_enable_clock( uint8_t base ); + +/** + * @brief Initialize ADC module. + * @param *base - ADC module base address. + * @param resolution - ADC module resolution. + * @return None + */ +static void _hal_ll_adc_hw_init( hal_ll_adc_base_handle_t *base, uint32_t resolution ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_adc_register_handle(hal_ll_pin_name_t pin, hal_ll_adc_voltage_reference_t vref_input, hal_ll_adc_resolution_t resolution, hal_ll_adc_handle_register_t *handle_map, uint8_t *hal_module_id) +{ + uint16_t pin_check_result; + hal_ll_adc_pin_id index = {HAL_LL_PIN_NC}; + + if ( (pin_check_result = hal_ll_adc_check_pins( pin, &index, handle_map )) == HAL_LL_PIN_NC ) { + return HAL_LL_ADC_WRONG_PIN; + }; + + switch ( resolution ) + { + case HAL_LL_ADC_RESOLUTION_12_BIT: + hal_ll_adc_hw_specifics_map[pin_check_result].resolution = HAL_LL_ADC_12BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_10_BIT: + hal_ll_adc_hw_specifics_map[pin_check_result].resolution = HAL_LL_ADC_10BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_8_BIT: + hal_ll_adc_hw_specifics_map[pin_check_result].resolution = HAL_LL_ADC_8BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_6_BIT: + hal_ll_adc_hw_specifics_map[pin_check_result].resolution = HAL_LL_ADC_6BIT_RES; + break; + default: + return HAL_LL_ADC_UNSUPPORTED_RESOLUTION; + } + + switch ( vref_input ) + { + case HAL_LL_ADC_VREF_EXTERNAL: + break; + + default: + return HAL_LL_ADC_UNSUPPORTED_VREF; + } + + if ( hal_ll_adc_hw_specifics_map[pin_check_result].pin != pin ) + { + hal_ll_adc_map_pin( pin_check_result, &index ); + + handle_map[pin_check_result].init_ll_state = false; + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[pin_check_result].hal_ll_adc_handle = (handle_t *)&hal_ll_adc_hw_specifics_map[pin_check_result].base; + + handle_map[pin_check_result].hal_ll_adc_handle = (handle_t *)&hal_ll_module_state[pin_check_result].hal_ll_adc_handle; + + return HAL_LL_ADC_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_adc( handle_t *handle ) +{ + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + hal_ll_adc_handle_register_t *hal_handle = (hal_ll_adc_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_adc_hw_specifics_map_local->module_index; + + hal_ll_adc_init( hal_ll_adc_hw_specifics_map_local ); + + hal_ll_module_state[pin_check_result].hal_ll_adc_handle = (handle_t *)&hal_ll_adc_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_ADC_SUCCESS; +} + +hal_ll_err_t hal_ll_adc_set_resolution(handle_t *handle, hal_ll_adc_resolution_t resolution) +{ + low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + + low_level_handle->init_ll_state = false; + + switch( resolution ) { + case HAL_LL_ADC_RESOLUTION_12_BIT: + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_12BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_10_BIT: + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_10BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_8_BIT: + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_8BIT_RES; + break; + case HAL_LL_ADC_RESOLUTION_6_BIT: + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_6BIT_RES; + break; + + default: + return HAL_LL_ADC_UNSUPPORTED_RESOLUTION; + } + + hal_ll_adc_init( hal_ll_adc_hw_specifics_map_local ); + + low_level_handle->init_ll_state = true; + + return HAL_LL_ADC_SUCCESS; +} + +hal_ll_err_t hal_ll_adc_set_vref_input(handle_t *handle, hal_ll_adc_voltage_reference_t vref_input) +{ + low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + + low_level_handle->init_ll_state = false; + + switch( vref_input ) { + case HAL_LL_ADC_VREF_EXTERNAL: + break; + + default: + return HAL_LL_ADC_UNSUPPORTED_VREF; + } + + hal_ll_adc_init( hal_ll_adc_hw_specifics_map_local ); + + low_level_handle->init_ll_state = true; + + return HAL_LL_ADC_SUCCESS; +} + +void hal_ll_adc_set_vref_value(handle_t *handle, float vref_value) +{ + low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + + hal_ll_adc_hw_specifics_map_local->vref_value = vref_value; +} + +hal_ll_err_t hal_ll_adc_read( handle_t *handle, uint16_t *readDatabuf ) +{ + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_base_handle_t *base = ( hal_ll_adc_base_handle_t * )hal_ll_adc_hw_specifics_map_local->base ; + + while( ( check_reg_bit( &( base->cr ), HAL_LL_ADC_ADSTART_BIT ) ) ); + base->sqr1 &= ~HAL_LL_ADC_CONVERSION_ONE; + base->sqr1 |= ( ( hal_ll_adc_hw_specifics_map_local->channel << 6 ) ); + + Delay_1us(); + + // Start the conversion. + set_reg_bit( &( base->cr ), HAL_LL_ADC_ADSTART_BIT ); + + while ( !( check_reg_bit( &( base->isr ), HAL_LL_ADC_EOC_BIT ) ) ); + // Conversion result from SS3. + *readDatabuf = base->dr; + + return HAL_LL_ADC_SUCCESS; +} + +void hal_ll_adc_close( handle_t *handle ) +{ + hal_ll_adc_hw_specifics_map_t *hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + low_level_handle = hal_ll_adc_get_handle; + + if( hal_ll_adc_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + + hal_ll_adc_hw_specifics_map_local->vref_input = HAL_LL_ADC_VREF_DEFAULT; + hal_ll_adc_hw_specifics_map_local->vref_value = 0; + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_RESOLUTION_12_BIT; + + low_level_handle->hal_ll_adc_handle = NULL; + low_level_handle->hal_drv_adc_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_adc_hw_specifics_map_local->pin = HAL_LL_PIN_NC; + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static hal_ll_pin_name_t hal_ll_adc_check_pins( hal_ll_pin_name_t pin, hal_ll_adc_pin_id *index, hal_ll_adc_handle_register_t *handle_map ) +{ + static const uint16_t adc_map_size = ( sizeof( _adc_map ) / sizeof( hal_ll_adc_pin_map_t ) ); + uint16_t pin_index = 0; + uint8_t index_counter = 0; + uint8_t hal_ll_module_id = 0; + + if ( HAL_LL_PIN_NC == pin ) { + return HAL_LL_PIN_NC; + } + + for ( pin_index = 0; pin_index < adc_map_size; pin_index++ ) + { + if ( pin == _adc_map[pin_index].pin ) + { + // Get module number + hal_ll_module_id = _adc_map[pin_index].module_index; + // Map pin name + index->pin_an[hal_ll_module_id] = pin_index; + + // Check if module is taken + if ( NULL == handle_map[ hal_ll_module_id ].hal_drv_adc_handle ) { + return hal_ll_module_id; + } else if ( ADC_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static void hal_ll_adc_map_pin( uint8_t module_index, hal_ll_adc_pin_id *index ) { + // Map new pins + hal_ll_adc_hw_specifics_map[module_index].pin = _adc_map[ index->pin_an[module_index] ].pin; + hal_ll_adc_hw_specifics_map[module_index].channel = _adc_map[ index->pin_an[module_index] ].channel; +} + +static hal_ll_adc_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof(hal_ll_adc_handle_register_t)); + static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof(hal_ll_adc_handle_register_t)); + + while( hal_ll_module_count-- ) { + if (hal_ll_adc_get_base_from_hal_handle == hal_ll_adc_hw_specifics_map[hal_ll_module_count].base) { + return &hal_ll_adc_hw_specifics_map[hal_ll_module_count]; + } + } + + return &hal_ll_adc_hw_specifics_map[hal_ll_module_error]; +} +static inline void adc1_enable_clock() +{ + set_reg_bit( _RCC_AHB2ENR, HAL_LL_ADC1_ENABLE_CLOCK ); +} +static inline void adc2_enable_clock() +{ + set_reg_bit( _RCC_AHB2ENR, HAL_LL_ADC2_ENABLE_CLOCK ); +} +static inline void adc3_enable_clock() +{ + set_reg_bit( _RCC_AHB2ENR, HAL_LL_ADC3_ENABLE_CLOCK ); +} + +static void _hal_ll_adc_enable_clock( uint8_t base ) +{ + switch ( base ) + { + #ifdef ADC_MODULE_1 + case ( hal_ll_adc_module_num(ADC_MODULE_1) ): + adc1_enable_clock(); + break; + #endif + #ifdef ADC_MODULE_2 + case ( hal_ll_adc_module_num(ADC_MODULE_2) ): + adc2_enable_clock(); + break; + #endif + #ifdef ADC_MODULE_3 + case ( hal_ll_adc_module_num(ADC_MODULE_3) ): + adc3_enable_clock(); + break; + #endif + } +} +static void _hal_ll_adc_hw_init( hal_ll_adc_base_handle_t *base, uint32_t resolution ) +{ + static uint32_t wait_loop_index = 0; + static uint32_t *reg; + reg = HAL_LL_ADC_CCIPR; + + // Select ADC clock source. + *reg |= HAL_LL_ADC_CLK_SRC; + + // Exit from deep power down mode. + if ( check_reg_bit( &( base->cr ), HAL_LL_ADC_DEEPPWD_BIT ) ) + { + clear_reg_bit( &( base->cr ), HAL_LL_ADC_DEEPPWD_BIT ); + } + + // Enable voltage regulator. + base->cr &= HAL_LL_ADC_VOLTAGE; + + if ( !( check_reg_bit( &( base->cr ), HAL_LL_ADC_ADVREGEN_BIT ) ) ) + { + set_reg_bit( &( base->cr ), HAL_LL_ADC_ADVREGEN_BIT ); + } + + // Enable ADC interrupts. + set_reg_bit( &( base->ier ), HAL_LL_ADC_ADRDYIE_BIT ); + + // Disable ADC + if ( check_reg_bit( &( base->cr ), HAL_LL_ADC_ADEN_BIT ) ) + { + set_reg_bit( &( base->cr ), HAL_LL_ADC_ADDIS_BIT ); + } + + // Voltage reference enable, ckmode SYSCLK. + reg = HAL_LL_ADC_CCR; + *reg |= (HAL_LL_ADC_CKMODE_MASK | HAL_LL_ADC_VREFEN_MASK); + + // Select calibration mode. + clear_reg_bit( &( base->cr ), HAL_LL_ADC_ADCALDIF_BIT ); + + // Start ADC calibration. + set_reg_bit( &( base->cr ), HAL_LL_ADC_ADCAL_BIT ); + + // Wait for calibration. + while ( check_reg_bit( &( base->cr ), HAL_LL_ADC_ADCAL_BIT ) ); + + // Prescaler. + *reg &= HAL_LL_ADC_PRESCALER; + + // Clear ADRDY bit ADC_ISR by writting 1. + set_reg_bit( &( base->isr ), HAL_LL_ADC_ADRDY_BIT ); + + // Set delay for voltage regulator to be initialized correctly. + wait_loop_index = 10 * ( Get_Fosc_kHz() / 1000 ); + while( wait_loop_index != 0 ) + { + wait_loop_index--; + } + + // Enable ADC. + set_reg_bit( &( base->cr ), HAL_LL_ADC_ADEN_BIT ); + + // ADRDY bit. + while ( !( check_reg_bit( &( base->cr ), HAL_LL_ADC_ADRDY_BIT ) ) ); + + // Resolution. + base->cfgr &= HAL_LL_RESOLUTION_MASK; + base->cfgr |= resolution; + + // Data alignment. + clear_reg_bit( &( base->cfgr ), HAL_LL_ADC_ALIGN_BIT ); + + // Discontinuos mode disabled. + clear_reg_bit( &( base->cfgr ), HAL_LL_ADC_DISCEN_BIT ); + + // Continuos conversion mode. + clear_reg_bit( &( base->cfgr ), HAL_LL_ADC_CONT_BIT ); + + // Regular channel sequence length. + base->sqr1 &= HAL_LL_ADC_CONVERSION; +} + +static void hal_ll_adc_init( hal_ll_adc_hw_specifics_map_t *map ) { + + + hal_ll_gpio_analog_input( hal_ll_gpio_port_base( hal_ll_gpio_port_index( map->pin ) ), + hal_ll_gpio_pin_mask( map->pin ) ); + + _hal_ll_adc_enable_clock( map->module_index ); + + _hal_ll_adc_hw_init((hal_ll_adc_base_handle_t *)map->base, map->resolution); + +} + + +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/src/can/CMakeLists.txt b/targets/arm/mikroe/ai_generated/stm32/src/can/CMakeLists.txt new file mode 100644 index 000000000..8d2c4f634 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/can/CMakeLists.txt @@ -0,0 +1,74 @@ +## ./targets/arm/mikroe/ai_generated/stm32/src/can/CMakeLists.txt + +## Check if current module is generated or not +set(MODULE_IS_GENERATED false) +get_files_recurse(${CMAKE_CURRENT_LIST_DIR}/implementations CMAKE_FILES cmake) +check_if_module_is_generated(MODULE_IS_GENERATED "${CMAKE_FILES}") + +## If current MCU has this module, add it +if(MODULE_IS_GENERATED) + set(hal_ll_def_list "") + set(mcu_header_path "") + + find_cortex(hal_ll_def_list) + list(APPEND hal_ll_def_list ${MCU_NAME}) + set(mcu_header_path ${MCU_NAME}_${_MSDK_PACKAGE_ID_}) + + ## BEGIN CAN + list(APPEND hal_ll_def_list "MACRO_USAGE_CAN") + + ## i.e "if (${MCU_NAME} MATCHES "^STM32C011F6$|^STM32C011C6$")" + ## List all MCUs and or them in the regex + foreach(cmakeFile ${CMAKE_FILES}) + include(${cmakeFile}) + endforeach() + ## END CAN + + mikrosdk_add_library(lib_hal_ll_can MikroSDK.HalLowLevel.CAN + ${rcc_subimplementation}/hal_ll_rcc.h + ../../include/hal_ll_target.h + # BEGIN CAN + ${can_subimplementation} + ../../include/can/hal_ll_can.h + ${can_pin_map}/hal_ll_can_pin_map.h + # END CAN + ) + + target_compile_definitions(lib_hal_ll_can PUBLIC + ${hal_ll_def_list} + ) + + target_link_libraries(lib_hal_ll_can PUBLIC + MikroC.Core + MikroSDK.HalLowLevelCommon + ) + + string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) + target_include_directories(lib_hal_ll_can + PRIVATE + ../../include + ../../include/gpio + ${gpio_subimplementation_include_dir} + # BEGIN CAN + ../../include/can + ${can_pin_map} + # END CAN + # BEGIN RCC + ${rcc_subimplementation} + # END RCC + INTERFACE + # BUILD + $ + $ + $ + $ + $ + $ + # INSTALL + $ + $ + ) + + mikrosdk_install(MikroSDK.HalLowLevel.CAN) + install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.CAN ../../include/can/hal_ll_can.h) +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/can/implementations/.gitkeep b/targets/arm/mikroe/ai_generated/stm32/src/can/implementations/.gitkeep new file mode 100644 index 000000000..e69de29bb diff --git a/targets/arm/mikroe/ai_generated/stm32/src/can/implementations/doc_ds_160/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/can/implementations/doc_ds_160/CMakeLists.cmake new file mode 100644 index 000000000..7134598ee --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/can/implementations/doc_ds_160/CMakeLists.cmake @@ -0,0 +1,9 @@ +if(${MCU_NAME} MATCHES "^STM32L4P5AE$|^STM32L4P5AG$|^STM32L4P5CE$|^STM32L4P5CG$|^STM32L4P5QE$|^STM32L4P5QG$|^STM32L4P5RE$|^STM32L4P5RG$|^STM32L4P5VE$|^STM32L4P5VG$|^STM32L4P5ZE$|^STM32L4P5ZG$") + set(can_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_can.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_160") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_160") + list(APPEND hal_ll_def_list "STM32L4xx") + list(APPEND hal_ll_def_list "STM32L4Pxx") + list(APPEND hal_ll_def_list "STM32L4P5xx") + set(can_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/can/hal_ll_can_pin_map/implementations/doc_ds_160") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/can/implementations/doc_ds_160/hal_ll_can.c b/targets/arm/mikroe/ai_generated/stm32/src/can/implementations/doc_ds_160/hal_ll_can.c new file mode 100644 index 000000000..af71506fc --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/can/implementations/doc_ds_160/hal_ll_can.c @@ -0,0 +1,1046 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_can.c + * @brief CAN HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_rcc.h" +#include "hal_ll_can.h" +#include "hal_ll_gpio.h" +#include "hal_ll_can_pin_map.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_can_handle_register_t hal_ll_module_state[CAN_MODULE_COUNT] = { (handle_t *)NULL, (handle_t *)NULL, false }; + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_can_get_module_state_address ((hal_ll_can_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_can_get_handle (hal_ll_can_handle_register_t *)hal_ll_can_get_module_state_address->hal_ll_can_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_can_get_base_struct(_handle) ((hal_ll_can_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_can_get_base_from_hal_handle ((hal_ll_can_hw_specifics_map_t *)((hal_ll_can_handle_register_t *)\ + (((hal_ll_can_handle_register_t *)(handle))->hal_ll_can_handle))->hal_ll_can_handle)->base +/*!< @brief Helper macro for configuring the filter */ +#define hal_ll_can_filter_configure_32(mask_32) ((mask_32 & 0x07FF) << 21U | (mask_32 & 0x1FFFF800) >> 8U) +#define hal_ll_can_filter_configure_16(mask_16) ((((uint32_t)(mask_16 & 0x07FF) << 5U) | ((uint32_t)(mask_16 & 0x3800) >> 11U))) +#define hal_ll_can_filter_get_format_32(mask_32) (((mask_32 & 0x1FFFF800))?1:0) +#define hal_ll_can_filter_get_format_16(mask) ((mask & 0x1C00)?1:0) +/*!< @brief Helper macro for handling the received message */ +#define hal_ll_can_message_received(fifo,mask) ((fifo & mask)) +#define hal_ll_can_get_rx_data(byte,data_register,offset) ((uint8_t)(((byte) & data_register) >> offset)) +#define hal_ll_can_get_rx_id(id_register,mask,offset) ((id_register & mask ) >> offset) +#define hal_ll_can_get_rx_eid(id_register,mask,offset) ((id_register & mask ) << offset) +/*!< @brief Helper macros for bit rate calculation */ +#define hal_ll_can_check_time_segments(tseg1,tseg2) ((16 < tseg1) || (8 < tseg2) || (0 == tseg1) || (0 == tseg2)) +#define hal_ll_can_get_btr_element_mask(element, offset) (((uint32_t)(element - 1)) << offset) + +/*!< @brief GPIO congiguration constants */ +#ifdef GPIO_CFG_SPEED_VERY_HIGH +#define HAL_LL_CAN_AF_CONFIG (GPIO_CFG_MODE_ALT_FUNCTION | GPIO_CFG_SPEED_VERY_HIGH | GPIO_CFG_OTYPE_PP | GPIO_CFG_PULL_UP) +#else +#define HAL_LL_CAN_AF_CONFIG (GPIO_CFG_MODE_ALT_FUNCTION | GPIO_CFG_SPEED_HIGH | GPIO_CFG_OTYPE_PP | GPIO_CFG_PULL_UP) +#endif +/*!< @brief CAN clock enable bits */ +#define HAL_LL_CAN1_CLOCK_ENABLE (25) +/*!< @brief CAN baudrate constants and register bits and masks */ +#define HAL_LL_CAN_BTR_PRESCALER_OFFSET (0) +#define HAL_LL_CAN_BTR_SJW_VALUE (1) +#define HAL_LL_CAN_BTR_TSEG1_OFFSET (16) +#define HAL_LL_CAN_BTR_TSEG2_OFFSET (20) +#define HAL_LL_CAN_BTR_SJW_OFFSET (24) +#define HAL_LL_CAN_BTR_LBKM_BIT (30) +#define HAL_LL_CAN_BTR_SILM_BIT (31) +#define HAL_LL_CAN_BTR_MAX_PRESCALER_VALUE (1024) +#define HAL_LL_CAN_BTR_REGISTER_MASK (0xC37F03FFUL) +/*!< @brief CAN control and status register bits */ +#define HAL_LL_CAN_MCR_INRQ_BIT (0) +#define HAL_LL_CAN_MSR_INAK_BIT (0) +#define HAL_LL_CAN_MCR_SLEEP_BIT (1) +#define HAL_LL_CAN_MSR_SLAK_BIT (1) +/*!< @brief CAN filter constants and register bits and masks */ +#define HAL_LL_CAN_FMR_FINIT_BIT (0) +#define HAL_LL_CAN_FIR_RTR_32_BIT (1) +#define HAL_LL_CAN_FIR_EID_32_BIT (2) +#define HAL_LL_CAN_FIR_EID_16_LOW_BIT (3) +#define HAL_LL_CAN_FIR_RTR_16_LOW_BIT (4) +#define HAL_LL_CAN_SINGLE_CORE_FILTER_LIMIT (27) +#define HAL_LL_CAN_FIR_EID_16_HIGH_BIT (19) +#define HAL_LL_CAN_FIR_RTR_16_HIGH_BIT (20) +#define HAL_LL_CAN_FILTER_NUMBER (27) +/*!< @brief CAN transmit constants, registers bits and masks */ +#define HAL_LL_CAN_TIR_TXRQ_BIT (0) +#define HAL_LL_CAN_TIR_RTR_BIT (1) +#define HAL_LL_CAN_TIR_IDE_BIT (2) +#define HAL_LL_CAN_TRANSMIT_MAILBOX_COUNT (3) +#define HAL_LL_CAN_TIR_EID_SHIFT (8) +#define HAL_LL_CAN_TIR_STID_SHIFT (21) +#define HAL_LL_CAN_TSR_CODE_SHIFT (24) +#define HAL_LL_CAN_TSR_CODE_MASK (0x03000000UL) +/*!< @brief CAN receive register bits and masks */ +#define HAL_LL_CAN_RF0R_RFOM0_BIT (5) +#define HAL_LL_CAN_RF1R_RFOM1_BIT (5) +#define HAL_LL_CAN_RF0R_FMP0_MASK (0x00000003UL) +#define HAL_LL_CAN_RF1R_FMP1_MASK (0x00000003UL) +/*!< @brief CAN receive FIFO constants, register bits and masks */ +#define HAL_LL_CAN_RIR_RTR_BIT (1) +#define HAL_LL_CAN_RIR_IDE_BIT (2) +#define HAL_LL_CAN_RIR_EXID_SHIFT (8) +#define HAL_LL_CAN_RIR_STID_SHIFT (21) +#define HAL_LL_CAN_RDTR_DLC_MASK (0x0000000FUL) +#define HAL_LL_CAN_RIR_STID_MASK (0xFFE00000UL) +#define HAL_LL_CAN_RIR_EXID_MASK (0x001FFFF8UL) +/*!< @brief Helper macro for defining temout value */ +#define HAL_LL_CAN_TIMEOUT_VALUE (10000UL) +/*!< @brief Byte offset macros */ +#define HAL_LL_CAN_BYTE_OFFSET_0 (0U) +#define HAL_LL_CAN_BYTE_OFFSET_1 (8U) +#define HAL_LL_CAN_BYTE_OFFSET_2 (16U) +#define HAL_LL_CAN_BYTE_OFFSET_3 (24U) +#define HAL_LL_CAN_BYTE_FIRST (0x000000FFUL) +#define HAL_LL_CAN_BYTE_SECOND (0x0000FF00UL) +#define HAL_LL_CAN_BYTE_THIRD (0x00FF0000UL) +#define HAL_LL_CAN_BYTE_FOURTH (0xFF000000UL) + +/*!< @brief CAN hw specific structure */ +typedef struct +{ + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + hal_ll_can_pins_t pins; + hal_ll_can_mode_t mode; + uint32_t frequency; +} hal_ll_can_hw_specifics_map_t; + +/*!< @brief CAN hw specific module values */ +typedef struct +{ + hal_ll_pin_name_t pin_tx; + hal_ll_pin_name_t pin_rx; +} hal_ll_can_pin_id; + +/* @brief CAN TxMailBox structure */ +typedef struct +{ + hal_ll_base_addr_t tir; /*!< CAN TX mailbox identifier register */ + hal_ll_base_addr_t tdtr; /*!< CAN mailbox data length control and time stamp register */ + hal_ll_base_addr_t tdlr; /*!< CAN mailbox data low register */ + hal_ll_base_addr_t tdhr; /*!< CAN mailbox data high register */ +} hal_ll_can_txmailbox_t; + +/* @brief Controller Area Network FIFOMailBox structure */ +typedef struct +{ + hal_ll_base_addr_t rir; /*!< CAN receive FIFO mailbox identifier register */ + hal_ll_base_addr_t rdtr; /*!< CAN receive FIFO mailbox data length control and time stamp register */ + hal_ll_base_addr_t rdlr; /*!< CAN receive FIFO mailbox data low register */ + hal_ll_base_addr_t rdhr; /*!< CAN receive FIFO mailbox data high register */ +} hal_ll_can_fifomailbox_t; + +/* @brief Controller Area Network FilterRegister structure */ +typedef struct +{ + hal_ll_base_addr_t fr1; /*!< CAN Filter bank register 1 */ + hal_ll_base_addr_t fr2; /*!< CAN Filter bank register 2 */ +} hal_ll_can_filter_reg_t; + +/*!< @brief CAN HW register structure */ +typedef struct +{ + hal_ll_base_addr_t mcr; /*CAN master control register*/ + hal_ll_base_addr_t msr; /*CAN master status register*/ + hal_ll_base_addr_t tsr; /*CAN transmit status register*/ + hal_ll_base_addr_t rf0r; /*CAN receive FIFO 0 register*/ + hal_ll_base_addr_t rf1r; /*CAN receive FIFO 1 register*/ + hal_ll_base_addr_t ier; /*CAN interrupt enable register*/ + hal_ll_base_addr_t esr; /*CAN error status register*/ + hal_ll_base_addr_t btr; /*CAN bit timing register*/ + hal_ll_base_addr_t __unused1[88]; + hal_ll_can_txmailbox_t tx_mailbox[3]; + hal_ll_can_fifomailbox_t fifo_mailbox[2]; + hal_ll_base_addr_t __unused2[12]; + hal_ll_base_addr_t fmr; /*CAN filter master register*/ + hal_ll_base_addr_t fm1r; /*CAN filter mode register*/ + hal_ll_base_addr_t __unused3[1]; + hal_ll_base_addr_t fs1r; /*CAN filter scale register*/ + hal_ll_base_addr_t __unused4[1]; + hal_ll_base_addr_t ffa1r; /*CAN filter FIFO assignment register*/ + hal_ll_base_addr_t __unused5[1]; + hal_ll_base_addr_t fa1r; /*CAN filter activation register*/ + hal_ll_base_addr_t __unused6[8]; + hal_ll_can_filter_reg_t filter_reg[28]; +} hal_ll_can_base_handle_t; + +/*!< @brief CAN hw specific error values */ +typedef enum +{ + HAL_LL_CAN_SUCCESS = 0, + HAL_LL_CAN_WRONG_PINS, + HAL_LL_CAN_MODULE_ERROR, + + HAL_LL_CAN_ERROR = (-1) +} hal_ll_can_err_t; +// ------------------------------------------------------------------ VARIABLES +/*!< @brief CAN hardware specific info */ +static hal_ll_can_hw_specifics_map_t hal_ll_can_hw_specifics_map[] = +{ + #ifdef CAN_MODULE_1 + { HAL_LL_CAN1_BASE_ADDRESS, hal_ll_can_module_num( CAN_MODULE_1 ), { HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0 }, HAL_LL_CAN_MODE_NORMAL, 500000 }, + #endif + { HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, { HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0 }, HAL_LL_CAN_MODE_NORMAL, 500000 } +}; + + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_can_handle_register_t *low_level_handle; +static volatile hal_ll_can_hw_specifics_map_t *hal_ll_can_hw_specifics_map_local; +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Check if pins are adequate. + * + * Checks tx and rx pins the user has passed with pre-defined + * pins in tx and rx maps. Take into consideration that module + * index numbers have to be the same for both pins. + * + * @param[in] tx_pin - TX pre-defined pin name. + * @param[in] rx_pin - RX pre-defined pin name. + * @param[in] *index_list - Index list address + * @param[in] *handle_map - HAL low level context object handle. + * @return hal_ll_pin_name_t Module index based on pins. + * + * Returns pre-defined module index from pin maps, if pins + * are adequate. + */ +static hal_ll_pin_name_t hal_ll_can_check_pins( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, + hal_ll_can_pin_id *index_list, hal_ll_can_handle_register_t *handle_map ); + +/** + * @brief Sets CAN pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if CAN is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_state - Init/De-init + * + * @return None + */ +static void hal_ll_can_alternate_functions_set_state( hal_ll_can_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * CAN TX and RX pins. + * + * @param[in] module_index CAN HW module index -- 0,1,2... + * @param[in] *index_list Array with TX and RX map index values + * and module number + * + * @return None + */ +static void hal_ll_can_map_pins( uint8_t module_index, hal_ll_can_pin_id *index_list ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_can_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_can_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_can_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Full CAN module initialization procedure. + * + * Initializes CAN module on hardware level, based on beforehand + * set configuration and module handler. Sets control and filter registers. + * Initializes module clock. + * + * @param[in] map - Object specific context handler. + * @param[in] config - CAN config structure. + * @param[in] filter_config - CAN filter config structure. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_can_hw_init( hal_ll_can_hw_specifics_map_t *map, hal_ll_can_config_t *config, + hal_ll_can_filter_config_t *filter_config ); + +/** + * @brief Calculates parameters for desired CAN frequency. + * + * Calculates adequate values to be written in CAN_BTR register + * in order to set appropriate baud rate. + * + * @param[in] map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_can_bit_timing( hal_ll_can_hw_specifics_map_t *map ); + +/** + * @brief Initialize CAN module on hardware level. + * + * Initializes CAN module on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] map - Object specific context handler. + * @param[in] config - CAN config structure. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_can_module_init( hal_ll_can_hw_specifics_map_t *map, hal_ll_can_config_t *config ); + +/** + * @brief Configure CAN filter. + * + * Initializes CAN filter on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] map - Object specific context handler. + * @param[in] filter_config - CAN filter config structure. + * @param[in] default_config - Defines if we should check if filter is assignable. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_can_filter_init( hal_ll_can_hw_specifics_map_t *map, hal_ll_can_filter_config_t *filter_config, bool default_config ); + +/** + * @brief Enable clock for CAN module on hardware level. + * + * Initializes CAN module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] module_index - Object specific context handler. + * @param[in] clock_enable - True(enable clock)/False(disable clock). + * + * @return None + */ +static void hal_ll_can_clock_enable( uint8_t module_index, bool clock_enable ); + +/** + * @brief Set operation mode. + * + * Sets an operation mode requested by user. + * + * @param[in] map - Object specific context handler. + * @param[in] config - CAN config structure. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_can_set_operation_mode( hal_ll_can_hw_specifics_map_t *map, hal_ll_can_config_t *config ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_can_register_handle( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_can_handle_register_t *handle_map, uint8_t *hal_module_id ) { + + hal_ll_can_pin_id index_list[CAN_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + uint16_t pin_check_result; + + // Check if pins are valid. + if (( pin_check_result = hal_ll_can_check_pins( tx_pin, rx_pin, &index_list, handle_map )) == HAL_LL_PIN_NC ) { + return HAL_LL_CAN_WRONG_PINS; + }; + + if (( hal_ll_can_hw_specifics_map[pin_check_result].pins.tx_pin.pin_name != tx_pin ) || + ( hal_ll_can_hw_specifics_map[pin_check_result].pins.rx_pin.pin_name != rx_pin )) + { + // Clear previous alternate function for chosen CAN pins. + hal_ll_can_alternate_functions_set_state( &hal_ll_can_hw_specifics_map[ pin_check_result ], false ); + + hal_ll_can_map_pins( pin_check_result, &index_list ); + + // Set adequate CAN alternate function for chosen CAN pins. + hal_ll_can_alternate_functions_set_state( &hal_ll_can_hw_specifics_map[ pin_check_result ], true ); + + handle_map[pin_check_result].init_ll_state = false; + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[pin_check_result].hal_ll_can_handle = ( handle_t * )&hal_ll_can_hw_specifics_map[pin_check_result].base; + + handle_map[pin_check_result].hal_ll_can_handle = ( handle_t * )&hal_ll_module_state[pin_check_result].hal_ll_can_handle; + + return HAL_LL_CAN_SUCCESS; +} + +hal_ll_err_t hal_ll_can_init( handle_t *handle, hal_ll_can_config_t *config, + hal_ll_can_filter_config_t *filter_config ) { + hal_ll_can_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_can_get_module_state_address ); + hal_ll_can_handle_register_t *hal_handle = ( hal_ll_can_handle_register_t * )*handle; + uint8_t pin_check_result = hal_ll_can_hw_specifics_map_local->module_index; + + if ( HAL_LL_CAN_ERROR == hal_ll_can_hw_init( hal_ll_can_hw_specifics_map_local, config, filter_config )) + return HAL_LL_CAN_ERROR; + + hal_ll_module_state[pin_check_result].hal_ll_can_handle = ( handle_t * )&hal_ll_can_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_CAN_SUCCESS; +} + +hal_ll_err_t hal_ll_can_set_filter( handle_t *handle, hal_ll_can_config_t *config, + hal_ll_can_filter_config_t *filter_config ) { + low_level_handle = hal_ll_can_get_handle; + hal_ll_can_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_can_get_module_state_address ); + + low_level_handle->init_ll_state = false; + if ( HAL_LL_CAN_ERROR == hal_ll_can_filter_init( hal_ll_can_hw_specifics_map_local, filter_config, false )) + return HAL_LL_CAN_ERROR; + + low_level_handle->init_ll_state = true; + + return HAL_LL_CAN_SUCCESS; +} + +hal_ll_err_t hal_ll_can_set_frequency( handle_t *handle, hal_ll_can_config_t *config, + hal_ll_can_filter_config_t *filter_config ) { + low_level_handle = hal_ll_can_get_handle; + hal_ll_can_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_can_get_module_state_address ); + uint32_t original_frequency; + hal_ll_err_t result; + + low_level_handle->init_ll_state = false; + + original_frequency = hal_ll_can_hw_specifics_map_local->frequency; + + hal_ll_can_hw_specifics_map_local->frequency = config->frequency; + result = hal_ll_can_hw_init( hal_ll_can_hw_specifics_map_local, config, filter_config ); + + // In case the desired frequency setting hasn't been achieved, there's no need to update the map. + if( HAL_LL_CAN_SUCCESS != result ) + hal_ll_can_hw_specifics_map_local->frequency = original_frequency; + + low_level_handle->init_ll_state = true; + + return result; +} + +hal_ll_err_t hal_ll_can_get_frequency( handle_t *handle ) { + hal_ll_can_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_can_get_module_state_address ); + + return hal_ll_can_hw_specifics_map_local->frequency; +} + +hal_ll_err_t hal_ll_can_set_mode( handle_t *handle, hal_ll_can_config_t *config, + hal_ll_can_filter_config_t *filter_config ) { + low_level_handle = hal_ll_can_get_handle; + hal_ll_can_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_can_get_module_state_address ); + hal_ll_err_t result; + + low_level_handle->init_ll_state = false; + + // NOTE: Changing mode won't result in an error, so saving the previous value is not needed. + hal_ll_can_hw_specifics_map_local->mode = config->mode; + result = hal_ll_can_hw_init( hal_ll_can_hw_specifics_map_local, config, filter_config ); + + low_level_handle->init_ll_state = true; + + return result; +} + +hal_ll_err_t hal_ll_can_get_mode( handle_t *handle ) { + hal_ll_can_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_can_get_module_state_address ); + + return hal_ll_can_hw_specifics_map_local->mode; +} + +hal_ll_err_t hal_ll_can_transmit( handle_t *handle, hal_ll_can_transmit_message_struct *transmit_message ) { + hal_ll_can_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_can_get_module_state_address ); + hal_ll_can_base_handle_t *hal_ll_hw_reg = ( hal_ll_can_base_handle_t *)hal_ll_can_hw_specifics_map_local->base; + uint8_t tx_mailbox_num; + uint16_t timeout = HAL_LL_CAN_TIMEOUT_VALUE; + + tx_mailbox_num = ( hal_ll_hw_reg->tsr & HAL_LL_CAN_TSR_CODE_MASK ) >> HAL_LL_CAN_TSR_CODE_SHIFT; + + hal_ll_hw_reg->tx_mailbox[tx_mailbox_num].tir = hal_ll_can_filter_configure_32( transmit_message->message.id ); + + // Set an appropriate frame format of the message. + if( HAL_LL_CAN_FRAME_FORMAT_STANDARD_11BITS == transmit_message->message.frame_format ) + clear_reg_bit( &hal_ll_hw_reg->tx_mailbox[tx_mailbox_num].tir, HAL_LL_CAN_TIR_IDE_BIT ); + else + set_reg_bit( &hal_ll_hw_reg->tx_mailbox[tx_mailbox_num].tir, HAL_LL_CAN_TIR_IDE_BIT ); + + // Set an appropriate frame type of the message. + if( HAL_LL_CAN_FRAME_TYPE_DATA == transmit_message->message.frame_type ) + clear_reg_bit( &hal_ll_hw_reg->tx_mailbox[tx_mailbox_num].tir, HAL_LL_CAN_TIR_RTR_BIT ); + else + set_reg_bit( &hal_ll_hw_reg->tx_mailbox[tx_mailbox_num].tir, HAL_LL_CAN_TIR_RTR_BIT ); + + hal_ll_hw_reg->tx_mailbox[tx_mailbox_num].tdtr = transmit_message->message.data_len; + + hal_ll_hw_reg->tx_mailbox[tx_mailbox_num].tdlr = (( uint32_t )transmit_message->message.message_data[0] ) | + (( uint32_t )transmit_message->message.message_data[1] << HAL_LL_CAN_BYTE_OFFSET_1 ) | + (( uint32_t )transmit_message->message.message_data[2] << HAL_LL_CAN_BYTE_OFFSET_2 ) | + (( uint32_t )transmit_message->message.message_data[3] << HAL_LL_CAN_BYTE_OFFSET_3 ); + + hal_ll_hw_reg->tx_mailbox[tx_mailbox_num].tdhr = (( uint32_t )transmit_message->message.message_data[4] ) | + (( uint32_t )transmit_message->message.message_data[5] << HAL_LL_CAN_BYTE_OFFSET_1 ) | + (( uint32_t )transmit_message->message.message_data[6] << HAL_LL_CAN_BYTE_OFFSET_2 ) | + (( uint32_t )transmit_message->message.message_data[7] << HAL_LL_CAN_BYTE_OFFSET_3 ); + + // Transmit mailbox request. + set_reg_bit( &hal_ll_hw_reg->tx_mailbox[tx_mailbox_num].tir, HAL_LL_CAN_TIR_TXRQ_BIT ); + // Waiting for message to be received by receiver. + while ( check_reg_bit( &hal_ll_hw_reg->tx_mailbox[tx_mailbox_num].tir, HAL_LL_CAN_TIR_TXRQ_BIT )) { + if( 0 == timeout-- ) + return HAL_LL_CAN_ERROR; + } + + return HAL_LL_CAN_SUCCESS; +} + +void hal_ll_can_transmission_stop( handle_t *handle ) { + hal_ll_can_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_can_get_module_state_address ); + hal_ll_can_base_handle_t *hal_ll_hw_reg = ( hal_ll_can_base_handle_t *)hal_ll_can_hw_specifics_map_local->base; + uint8_t tx_mailbox_num; + + // Stop transmitting any messages. + for ( tx_mailbox_num = 0; tx_mailbox_num < HAL_LL_CAN_TRANSMIT_MAILBOX_COUNT; tx_mailbox_num++ ) { + if ( check_reg_bit( &hal_ll_hw_reg->tx_mailbox[tx_mailbox_num].tir, HAL_LL_CAN_TIR_TXRQ_BIT )) + clear_reg_bit( &hal_ll_hw_reg->tx_mailbox[tx_mailbox_num].tir, HAL_LL_CAN_TIR_TXRQ_BIT ); + } +} + +hal_ll_err_t hal_ll_can_receive( handle_t *handle, hal_ll_can_receive_message_struct *receive_message ) { + hal_ll_can_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_can_get_module_state_address ); + hal_ll_can_base_handle_t *hal_ll_hw_reg = ( hal_ll_can_base_handle_t *)hal_ll_can_hw_specifics_map_local->base; + uint8_t rx_fifo_num = receive_message->rx_fifo_number; + uint32_t timeout = HAL_LL_CAN_TIMEOUT_VALUE; + + if ( HAL_LL_CAN_FILTER_FIFO0 == rx_fifo_num ) { + while( !( hal_ll_can_message_received( hal_ll_hw_reg->rf0r, HAL_LL_CAN_RF0R_FMP0_MASK ))) { + if( 0 == timeout-- ) + return HAL_LL_CAN_ERROR; + } + } else if ( HAL_LL_CAN_FILTER_FIFO1 == rx_fifo_num ) { + while ( !( hal_ll_can_message_received( hal_ll_hw_reg->rf1r, HAL_LL_CAN_RF1R_FMP1_MASK ))) { + if( 0 == timeout-- ) + return HAL_LL_CAN_ERROR; + } + } else + // STM32 MCUs have only 2 RX FIFOs. + return HAL_LL_CAN_ERROR; + + // Get parameters. + receive_message->message.data_len = hal_ll_hw_reg->fifo_mailbox[rx_fifo_num].rdtr & HAL_LL_CAN_RDTR_DLC_MASK; + receive_message->message.frame_type = check_reg_bit( &hal_ll_hw_reg->fifo_mailbox[rx_fifo_num].rir, HAL_LL_CAN_RIR_RTR_BIT ); + receive_message->message.frame_format = check_reg_bit( &hal_ll_hw_reg->fifo_mailbox[rx_fifo_num].rir, HAL_LL_CAN_RIR_IDE_BIT ); + + receive_message->message.std_id = hal_ll_can_get_rx_id( hal_ll_hw_reg->fifo_mailbox[rx_fifo_num].rir, HAL_LL_CAN_RIR_STID_MASK, HAL_LL_CAN_RIR_STID_SHIFT ); + if ( HAL_LL_CAN_FRAME_FORMAT_EXTENDED_29BITS == receive_message->message.frame_format ) + receive_message->message.id |= hal_ll_can_get_rx_eid( hal_ll_hw_reg->fifo_mailbox[rx_fifo_num].rir, HAL_LL_CAN_RIR_EXID_MASK, HAL_LL_CAN_RIR_EXID_SHIFT ); + + // Get all data bytes. + receive_message->message.message_data[0] = hal_ll_can_get_rx_data( HAL_LL_CAN_BYTE_FIRST, hal_ll_hw_reg->fifo_mailbox[rx_fifo_num].rdlr, HAL_LL_CAN_BYTE_OFFSET_0 ); + receive_message->message.message_data[1] = hal_ll_can_get_rx_data( HAL_LL_CAN_BYTE_SECOND, hal_ll_hw_reg->fifo_mailbox[rx_fifo_num].rdlr, HAL_LL_CAN_BYTE_OFFSET_1 ); + receive_message->message.message_data[2] = hal_ll_can_get_rx_data( HAL_LL_CAN_BYTE_THIRD, hal_ll_hw_reg->fifo_mailbox[rx_fifo_num].rdlr, HAL_LL_CAN_BYTE_OFFSET_2 ); + receive_message->message.message_data[3] = hal_ll_can_get_rx_data( HAL_LL_CAN_BYTE_FOURTH, hal_ll_hw_reg->fifo_mailbox[rx_fifo_num].rdlr, HAL_LL_CAN_BYTE_OFFSET_3 ); + receive_message->message.message_data[4] = hal_ll_can_get_rx_data( HAL_LL_CAN_BYTE_FIRST, hal_ll_hw_reg->fifo_mailbox[rx_fifo_num].rdhr, HAL_LL_CAN_BYTE_OFFSET_0 ); + receive_message->message.message_data[5] = hal_ll_can_get_rx_data( HAL_LL_CAN_BYTE_SECOND, hal_ll_hw_reg->fifo_mailbox[rx_fifo_num].rdhr, HAL_LL_CAN_BYTE_OFFSET_1 ); + receive_message->message.message_data[6] = hal_ll_can_get_rx_data( HAL_LL_CAN_BYTE_THIRD, hal_ll_hw_reg->fifo_mailbox[rx_fifo_num].rdhr, HAL_LL_CAN_BYTE_OFFSET_2 ); + receive_message->message.message_data[7] = hal_ll_can_get_rx_data( HAL_LL_CAN_BYTE_FOURTH, hal_ll_hw_reg->fifo_mailbox[rx_fifo_num].rdhr, HAL_LL_CAN_BYTE_OFFSET_3 ); + + // Release RX FIFO. + if ( HAL_LL_CAN_FILTER_FIFO0 == rx_fifo_num ) + set_reg_bit( &hal_ll_hw_reg->rf0r, HAL_LL_CAN_RF0R_RFOM0_BIT ); + else + set_reg_bit( &hal_ll_hw_reg->rf1r, HAL_LL_CAN_RF1R_RFOM1_BIT ); + + return HAL_LL_CAN_SUCCESS; +} + +hal_ll_err_t hal_ll_can_close( handle_t *handle ) { + low_level_handle = hal_ll_can_get_handle; + hal_ll_can_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_can_get_module_state_address); + + if( low_level_handle->hal_ll_can_handle != NULL ) { + hal_ll_can_clock_enable(hal_ll_can_hw_specifics_map_local->module_index, true); + hal_ll_can_alternate_functions_set_state( hal_ll_can_hw_specifics_map_local, false ); + + hal_ll_can_clock_enable(hal_ll_can_hw_specifics_map_local->module_index, false); + + hal_ll_can_hw_specifics_map_local->pins.tx_pin.pin_name = HAL_LL_PIN_NC; + hal_ll_can_hw_specifics_map_local->pins.tx_pin.pin_af = 0; + hal_ll_can_hw_specifics_map_local->pins.rx_pin.pin_name = HAL_LL_PIN_NC; + hal_ll_can_hw_specifics_map_local->pins.rx_pin.pin_af = 0; + + hal_ll_can_hw_specifics_map_local->frequency = 500000UL; + + low_level_handle->hal_ll_can_handle = NULL; + low_level_handle->hal_drv_can_handle = NULL; + + low_level_handle->init_ll_state = false; + + return HAL_LL_CAN_SUCCESS; + } else + return HAL_LL_CAN_ERROR; +} + +// ---------------------------------------------- PRIVATE FUNCTION DEFINITIONS + +static hal_ll_pin_name_t hal_ll_can_check_pins( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, + hal_ll_can_pin_id *index_list, hal_ll_can_handle_register_t *handle_map ) { + static const uint16_t tx_map_size = ( sizeof( hal_ll_can_tx_map ) / sizeof( hal_ll_can_pin_map_t ) ); + static const uint16_t rx_map_size = ( sizeof( hal_ll_can_rx_map ) / sizeof( hal_ll_can_pin_map_t ) ); + uint8_t hal_ll_module_id = 0; + uint8_t index_counter = 0; + uint16_t tx_index; + uint16_t rx_index; + + if ( (HAL_LL_PIN_NC == tx_pin) || (HAL_LL_PIN_NC == rx_pin) ) { + return HAL_LL_PIN_NC; + } + + for ( tx_index = 0; tx_index < tx_map_size; tx_index++ ) + { + if ( hal_ll_can_tx_map[ tx_index ].pin == tx_pin ) + { + for ( rx_index = 0; rx_index < rx_map_size; rx_index++ ) + { + if ( hal_ll_can_rx_map[ rx_index ].pin == rx_pin ) + { + if ( hal_ll_can_tx_map[ tx_index ].base == hal_ll_can_rx_map[ rx_index ].base ) { + // Get module number. + hal_ll_module_id = hal_ll_can_tx_map[ tx_index ].module_index; + + // Map pin names. + index_list[hal_ll_module_id].pin_tx = tx_index; + index_list[hal_ll_module_id].pin_rx = rx_index; + + // Check if module is taken. + if ( NULL == handle_map[ hal_ll_module_id ].hal_drv_can_handle ) { + return hal_ll_module_id; + } else if ( CAN_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static void hal_ll_can_alternate_functions_set_state( hal_ll_can_hw_specifics_map_t *map, bool hal_ll_state ) { + module_struct module; + + if ( (map->pins.tx_pin.pin_name != HAL_LL_PIN_NC) && map->pins.rx_pin.pin_name != HAL_LL_PIN_NC ) { + module.pins[0] = VALUE( map->pins.tx_pin.pin_name, map->pins.tx_pin.pin_af ); + module.pins[1] = VALUE( map->pins.rx_pin.pin_name, map->pins.rx_pin.pin_af ); + module.pins[2] = GPIO_MODULE_STRUCT_END; + + module.configs[0] = HAL_LL_CAN_AF_CONFIG; + module.configs[1] = HAL_LL_CAN_AF_CONFIG; + module.configs[2] = GPIO_MODULE_STRUCT_END; + + /* STM32F1xx specific. */ + module.gpio_remap = map->pins.tx_pin.pin_af; + + hal_ll_gpio_module_struct_init( &module, hal_ll_state ); + } +} + +static void hal_ll_can_map_pins( uint8_t module_index, hal_ll_can_pin_id *index_list ) { + // Map new pins. + hal_ll_can_hw_specifics_map[module_index].pins.tx_pin.pin_name = hal_ll_can_tx_map[index_list[module_index].pin_tx].pin; + hal_ll_can_hw_specifics_map[module_index].pins.rx_pin.pin_name = hal_ll_can_rx_map[index_list[module_index].pin_rx].pin; + // TX and RX could have different alternate function settings, hence save both AF values. + hal_ll_can_hw_specifics_map[module_index].pins.tx_pin.pin_af = hal_ll_can_tx_map[index_list[module_index].pin_tx].af; + hal_ll_can_hw_specifics_map[module_index].pins.rx_pin.pin_af = hal_ll_can_rx_map[index_list[module_index].pin_rx].af; +} + +static hal_ll_can_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + uint8_t hal_ll_module_count = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_can_handle_register_t )); + static uint8_t hal_ll_module_error = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_can_handle_register_t )); + + while( hal_ll_module_count-- ) { + if (hal_ll_can_get_base_from_hal_handle == hal_ll_can_hw_specifics_map[hal_ll_module_count].base) { + return &hal_ll_can_hw_specifics_map[hal_ll_module_count]; + } + } + + return &hal_ll_can_hw_specifics_map[hal_ll_module_error]; +} + +static void hal_ll_can_clock_enable( uint8_t module_index, bool clock_enable ) { + switch( module_index ) { + #ifdef CAN_MODULE_1 + case ( hal_ll_can_module_num( CAN_MODULE_1 )): + #ifdef _RCC_APB1ENR1 + if( true == clock_enable ) + set_reg_bit( _RCC_APB1ENR1, HAL_LL_CAN1_CLOCK_ENABLE ); + else + clear_reg_bit( _RCC_APB1ENR1, HAL_LL_CAN1_CLOCK_ENABLE ); + break; + #endif + #endif + default: + break; + } +} + +static hal_ll_err_t hal_ll_can_bit_timing( hal_ll_can_hw_specifics_map_t *map ) { + hal_ll_can_base_handle_t *hal_ll_hw_reg = hal_ll_can_get_base_struct( map->base ); + rcc_clocks_t rcc_clocks; + uint16_t prescaler, temp; + double time_quanta, bit_time, num_of_tq; + uint8_t sjw, tseg1, tseg2; + uint32_t baud_rate, can_clock; + + baud_rate = map->frequency; + + RCC_GetClocksFrequency( &rcc_clocks ); + can_clock = rcc_clocks.pclk1; + + /* + * Description: This code snippet calculates the optimal settings for configuring + * the CAN bus baud rate on STM32 microcontrollers, based on the provided parameters. + * + * Initial parameters: + * - can_clock: CAN source clock frequency (APB1) in Hz. + * - baud_rate: Desired CAN bus baud rate. + * + * Calculated parameters: + * - prescaler: The prescaler value to achieve the desired baud rate. + * - tseg1, tseg2: Time segment values for configuring the CAN bus. + * + * Formulas used: + * - time_quanta = 1 / can_clock + * - bit_time = 1 / baud_rate + * - num_of_tq = bit_time / time_quanta (number of time quanta) + * - (sjw + tseg1) / (sjw + tseg1 + tseg2) = 87.5% (optimal sampling for CAN) + * - baud_rate = can_clock / (prescaler * (tseg1 + tseg2 + 1)) (from STM32 Reference manuals) + * + * Note: sjw (synchronization jump width) is fixed to 1, the preferred value, but can range from 1 to 4. + */ + + sjw = HAL_LL_CAN_BTR_SJW_VALUE; + + bit_time = (double) 1 / baud_rate; + + for( prescaler = 1; prescaler <= HAL_LL_CAN_BTR_MAX_PRESCALER_VALUE; prescaler++ ) { + time_quanta = (double) prescaler / can_clock; + num_of_tq = bit_time / time_quanta; + tseg1 = 0.875 * num_of_tq - sjw; + tseg2 = num_of_tq - tseg1 - sjw; + + // Time segment 1 can be anywhere between 1 and 16, while the value of time segment 2 goes from 1 to 8. + if ( hal_ll_can_check_time_segments( tseg1, tseg2 )) continue; + + temp = prescaler * ( tseg1 + tseg2 + 1 ); + uint32_t actual_baud_rate = can_clock / temp; + + if( actual_baud_rate == baud_rate ) { + // Exact match found. + uint32_t sjw_val = hal_ll_can_get_btr_element_mask( sjw, HAL_LL_CAN_BTR_SJW_OFFSET ); + uint32_t tseg1_val = hal_ll_can_get_btr_element_mask( tseg1, HAL_LL_CAN_BTR_TSEG1_OFFSET ); + uint32_t tseg2_val = hal_ll_can_get_btr_element_mask( tseg2, HAL_LL_CAN_BTR_TSEG2_OFFSET ); + uint32_t prescaler_val = hal_ll_can_get_btr_element_mask( prescaler, HAL_LL_CAN_BTR_PRESCALER_OFFSET );; + + hal_ll_hw_reg->btr |= sjw_val | tseg1_val | tseg2_val | prescaler_val; + return HAL_LL_CAN_SUCCESS; + } + + /* + * Note: Setting parameters that result in a baud rate that differs from the desired value is not acceptable. + * If two devices communicate over CAN, their baud rates need to be exactly the same. + */ + } + + // If this point was reached, baud rate wasn't set to the desired value and error is returned. + return HAL_LL_CAN_ERROR; +} + +static hal_ll_err_t hal_ll_can_set_operation_mode( hal_ll_can_hw_specifics_map_t *map, hal_ll_can_config_t *config ) { + hal_ll_can_base_handle_t *hal_ll_hw_reg = hal_ll_can_get_base_struct(map->base); + uint16_t timeout = HAL_LL_CAN_TIMEOUT_VALUE; + + clear_reg_bit( &hal_ll_hw_reg->btr, HAL_LL_CAN_BTR_LBKM_BIT ); + clear_reg_bit( &hal_ll_hw_reg->btr, HAL_LL_CAN_BTR_SILM_BIT ); + + switch ( config->mode ) { + case HAL_LL_CAN_MODE_NORMAL: + break; + case HAL_LL_CAN_MODE_LOOPBACK: + set_reg_bit( &hal_ll_hw_reg->btr, HAL_LL_CAN_BTR_LBKM_BIT ); + break; + case HAL_LL_CAN_MODE_SILENT: + set_reg_bit( &hal_ll_hw_reg->btr, HAL_LL_CAN_BTR_SILM_BIT ); + break; + case HAL_LL_CAN_MODE_LOOPBACK_SILENT: + set_reg_bit( &hal_ll_hw_reg->btr, HAL_LL_CAN_BTR_LBKM_BIT ); + set_reg_bit( &hal_ll_hw_reg->btr, HAL_LL_CAN_BTR_SILM_BIT ); + break; + + default: + // STM32 doesn't have operation mode requested by user. + return HAL_LL_CAN_ERROR; + } + return HAL_LL_CAN_SUCCESS; +} + +static hal_ll_err_t hal_ll_can_module_init( hal_ll_can_hw_specifics_map_t *map, hal_ll_can_config_t *config ) { + hal_ll_can_base_handle_t *hal_ll_hw_reg = hal_ll_can_get_base_struct( map->base ); + uint16_t timeout = HAL_LL_CAN_TIMEOUT_VALUE; + + // Request iitialization mode. + set_reg_bit( &hal_ll_hw_reg->mcr, HAL_LL_CAN_MCR_INRQ_BIT ); + // Wait until HW enters initialization mode. + while( !check_reg_bit( &hal_ll_hw_reg->msr, HAL_LL_CAN_MSR_INAK_BIT )) { + if( 0 == timeout-- ) + return HAL_LL_CAN_ERROR; + } + + timeout = HAL_LL_CAN_TIMEOUT_VALUE; + // Request the exit from sleep mode. + clear_reg_bit( &hal_ll_hw_reg->mcr, HAL_LL_CAN_MCR_SLEEP_BIT ); + // Wait until HW exits sleep mode. + while( check_reg_bit( &hal_ll_hw_reg->msr, HAL_LL_CAN_MSR_SLAK_BIT )) { + if( 0 == timeout-- ) + return HAL_LL_CAN_ERROR; + } + + // Clear CAN baudrate register. + hal_ll_hw_reg->btr &= ~HAL_LL_CAN_BTR_REGISTER_MASK; + + // Set the operation mode requested by user. + if ( HAL_LL_CAN_ERROR == hal_ll_can_set_operation_mode( map, config )) + return HAL_LL_CAN_ERROR; + + // Configure bit timing. + return hal_ll_can_bit_timing( map ); +} + +static hal_ll_err_t hal_ll_can_filter_init( hal_ll_can_hw_specifics_map_t *map, hal_ll_can_filter_config_t *filter_config, bool default_config ) { + hal_ll_can_base_handle_t *hal_ll_hw_reg = hal_ll_can_get_base_struct( map->base );; + uint8_t filter_number_pos = filter_config->can_filter_bank; + hal_ll_can_frame_format_t frame_format_id_mask[4]; + + /* + * CAN2 as a slave core of CAN1 uses the same filter registers as CAN1. + * Filter banks dedication for devices with multiple CAN modules is following: + * - Filters 0 to 13 are used for single core CAN usage (CAN1 or CAN3 only); + * - Filters 0 to 27 are used for dual core CAN usage (CAN1 and CAN2): + * - Number of start bank filter for CAN2 is configured with CANSB[5:0] bits in CAN_FMR register, + but this implementation uses default configuration (CAN2 start bank filter is 14). + */ + if ( !default_config ) { + #ifdef CAN_MODULE_1 + if ( HAL_LL_CAN1_BASE_ADDRESS == map->base ) { + if ( HAL_LL_CAN_SINGLE_CORE_FILTER_LIMIT < filter_number_pos ) + return HAL_LL_CAN_ERROR; + } + #endif + } + + // STM32 MCUs have only 2 FIFOs. + if ( HAL_LL_CAN_FILTER_FIFO1 < filter_config->can_filter_fifo ) + return HAL_LL_CAN_ERROR; + + // Set an initialization mode for the filters. + set_reg_bit( &hal_ll_hw_reg->fmr, HAL_LL_CAN_FMR_FINIT_BIT ); + + if( HAL_LL_CAN_FILTER_SCALE_32BIT == filter_config->can_filter_scale ) { + // Set single 32-bit filter scale configuration. + set_reg_bit( &hal_ll_hw_reg->fs1r, filter_number_pos ); + + hal_ll_hw_reg->filter_reg[filter_number_pos].fr1 = hal_ll_can_filter_configure_32( filter_config->can_filter_id ); + hal_ll_hw_reg->filter_reg[filter_number_pos].fr2 = hal_ll_can_filter_configure_32( filter_config->can_filter_mask_id ); + + // Configure the frame type of filter/mask. + if ( HAL_LL_CAN_FRAME_TYPE_RTR == filter_config->can_filter_frame_type[0] ) + set_reg_bit( &hal_ll_hw_reg->filter_reg[filter_number_pos].fr1, HAL_LL_CAN_FIR_RTR_32_BIT ); + else + clear_reg_bit( &hal_ll_hw_reg->filter_reg[filter_number_pos].fr1, HAL_LL_CAN_FIR_RTR_32_BIT ); + + if ( HAL_LL_CAN_FRAME_TYPE_RTR == filter_config->can_filter_frame_type[1] ) + set_reg_bit( &hal_ll_hw_reg->filter_reg[filter_number_pos].fr2, HAL_LL_CAN_FIR_RTR_32_BIT ); + else + clear_reg_bit( &hal_ll_hw_reg->filter_reg[filter_number_pos].fr2, HAL_LL_CAN_FIR_RTR_32_BIT ); + + + // Configure the format of filter/mask. + frame_format_id_mask[0] = hal_ll_can_filter_get_format_32( filter_config->can_filter_id ); + frame_format_id_mask[1] = hal_ll_can_filter_get_format_32( filter_config->can_filter_mask_id ); + + if ( HAL_LL_CAN_FRAME_FORMAT_EXTENDED_29BITS == frame_format_id_mask[0] ) + set_reg_bit( &hal_ll_hw_reg->filter_reg[filter_number_pos].fr1, HAL_LL_CAN_FIR_EID_32_BIT ); + else + clear_reg_bit( &hal_ll_hw_reg->filter_reg[filter_number_pos].fr1, HAL_LL_CAN_FIR_EID_32_BIT ); + + if ( HAL_LL_CAN_FRAME_FORMAT_EXTENDED_29BITS == frame_format_id_mask[1] ) + set_reg_bit( &hal_ll_hw_reg->filter_reg[filter_number_pos].fr2, HAL_LL_CAN_FIR_EID_32_BIT ); + else + clear_reg_bit( &hal_ll_hw_reg->filter_reg[filter_number_pos].fr2, HAL_LL_CAN_FIR_EID_32_BIT ); + + } else { + // Set dual 16-bit filter scale configuration. + clear_reg_bit( &hal_ll_hw_reg->fs1r, filter_number_pos ); + + hal_ll_hw_reg->filter_reg[filter_number_pos].fr1 = + ( hal_ll_can_filter_configure_16( filter_config->can_filter_id_low ) | + hal_ll_can_filter_configure_16( filter_config->can_filter_mask_id_low ) << HAL_LL_CAN_BYTE_OFFSET_2 ); + hal_ll_hw_reg->filter_reg[filter_number_pos].fr2 = + ( hal_ll_can_filter_configure_16( filter_config->can_filter_id_high ) | + hal_ll_can_filter_configure_16( filter_config->can_filter_mask_id_high ) << HAL_LL_CAN_BYTE_OFFSET_2 ); + + // Configure the frame type of filter/mask. + if ( HAL_LL_CAN_FRAME_TYPE_RTR == filter_config->can_filter_frame_type[0] ) + set_reg_bit( &hal_ll_hw_reg->filter_reg[filter_number_pos].fr1, HAL_LL_CAN_FIR_RTR_16_LOW_BIT ); + else + clear_reg_bit( &hal_ll_hw_reg->filter_reg[filter_number_pos].fr1, HAL_LL_CAN_FIR_RTR_16_LOW_BIT ); + + if ( HAL_LL_CAN_FRAME_TYPE_RTR == filter_config->can_filter_frame_type[1] ) + set_reg_bit( &hal_ll_hw_reg->filter_reg[filter_number_pos].fr1, HAL_LL_CAN_FIR_RTR_16_HIGH_BIT ); + else + clear_reg_bit( &hal_ll_hw_reg->filter_reg[filter_number_pos].fr1, HAL_LL_CAN_FIR_RTR_16_HIGH_BIT ); + + if ( HAL_LL_CAN_FRAME_TYPE_RTR == filter_config->can_filter_frame_type[2] ) + set_reg_bit( &hal_ll_hw_reg->filter_reg[filter_number_pos].fr2, HAL_LL_CAN_FIR_RTR_16_LOW_BIT ); + else + clear_reg_bit( &hal_ll_hw_reg->filter_reg[filter_number_pos].fr2, HAL_LL_CAN_FIR_RTR_16_LOW_BIT ); + + if ( HAL_LL_CAN_FRAME_TYPE_RTR == filter_config->can_filter_frame_type[3] ) + set_reg_bit( &hal_ll_hw_reg->filter_reg[filter_number_pos].fr2, HAL_LL_CAN_FIR_RTR_16_HIGH_BIT ); + else + clear_reg_bit( &hal_ll_hw_reg->filter_reg[filter_number_pos].fr2, HAL_LL_CAN_FIR_RTR_16_HIGH_BIT ); + + // Configure the format of filter/mask. + frame_format_id_mask[0] = hal_ll_can_filter_get_format_16( filter_config->can_filter_id_low ); + frame_format_id_mask[1] = hal_ll_can_filter_get_format_16( filter_config->can_filter_mask_id_low ); + frame_format_id_mask[2] = hal_ll_can_filter_get_format_16( filter_config->can_filter_id_high ); + frame_format_id_mask[3] = hal_ll_can_filter_get_format_16( filter_config->can_filter_mask_id_high ); + + if ( HAL_LL_CAN_FRAME_FORMAT_EXTENDED_29BITS == frame_format_id_mask[0] ) + set_reg_bit( &hal_ll_hw_reg->filter_reg[filter_number_pos].fr1, HAL_LL_CAN_FIR_EID_16_LOW_BIT ); + else + clear_reg_bit( &hal_ll_hw_reg->filter_reg[filter_number_pos].fr1, HAL_LL_CAN_FIR_EID_16_LOW_BIT ); + + if ( HAL_LL_CAN_FRAME_FORMAT_EXTENDED_29BITS == frame_format_id_mask[1] ) + set_reg_bit( &hal_ll_hw_reg->filter_reg[filter_number_pos].fr1, HAL_LL_CAN_FIR_EID_16_HIGH_BIT ); + else + clear_reg_bit( &hal_ll_hw_reg->filter_reg[filter_number_pos].fr1, HAL_LL_CAN_FIR_EID_16_HIGH_BIT ); + + if ( HAL_LL_CAN_FRAME_FORMAT_EXTENDED_29BITS == frame_format_id_mask[2] ) + set_reg_bit( &hal_ll_hw_reg->filter_reg[filter_number_pos].fr2, HAL_LL_CAN_FIR_EID_16_LOW_BIT ); + else + clear_reg_bit( &hal_ll_hw_reg->filter_reg[filter_number_pos].fr2, HAL_LL_CAN_FIR_EID_16_LOW_BIT ); + + if ( HAL_LL_CAN_FRAME_FORMAT_EXTENDED_29BITS == frame_format_id_mask[3] ) + set_reg_bit( &hal_ll_hw_reg->filter_reg[filter_number_pos].fr2, HAL_LL_CAN_FIR_EID_16_HIGH_BIT ); + else + clear_reg_bit( &hal_ll_hw_reg->filter_reg[filter_number_pos].fr2, HAL_LL_CAN_FIR_EID_16_HIGH_BIT ); + } + + if ( HAL_LL_CAN_FILTER_MODE_IDMASK == filter_config->can_filter_mode ) + // Set ID-Mask Mode for the filter. + clear_reg_bit( &hal_ll_hw_reg->fm1r, filter_number_pos ); + else + // Set ID-List Mode for the filter. + set_reg_bit( &hal_ll_hw_reg->fm1r, filter_number_pos ); + + if ( HAL_LL_CAN_FILTER_FIFO0 == filter_config->can_filter_fifo ) + // Map this filter to FIFO0. + clear_reg_bit( &hal_ll_hw_reg->ffa1r, filter_number_pos ); + else + // Map this filter to FIFO1. + set_reg_bit( &hal_ll_hw_reg->ffa1r, filter_number_pos ); + + if ( HAL_LL_CAN_FILTER_ENABLE == filter_config->can_filter_enable ) + // Enable this filter. + set_reg_bit( &hal_ll_hw_reg->fa1r, filter_number_pos ); + else + // Disable this filter. + clear_reg_bit( &hal_ll_hw_reg->fa1r, filter_number_pos ); + + // Leave the initialization mode. + clear_reg_bit( &hal_ll_hw_reg->fmr, HAL_LL_CAN_FMR_FINIT_BIT ); +} + +static hal_ll_err_t hal_ll_can_hw_init( hal_ll_can_hw_specifics_map_t *map, hal_ll_can_config_t *config, + hal_ll_can_filter_config_t *filter_config ) { + hal_ll_can_base_handle_t *hal_ll_hw_reg = hal_ll_can_get_base_struct( map->base ); + uint16_t timeout = HAL_LL_CAN_TIMEOUT_VALUE; + + // Enable clock for CAN. + hal_ll_can_clock_enable( map->module_index, true ); + + if ( HAL_LL_CAN_ERROR == hal_ll_can_module_init( map, config )) + return HAL_LL_CAN_ERROR; + + if ( HAL_LL_CAN_ERROR == hal_ll_can_filter_init( map, filter_config, true )) + return HAL_LL_CAN_ERROR; + + // Request the start of CAN. + clear_reg_bit( &hal_ll_hw_reg->mcr, HAL_LL_CAN_MCR_INRQ_BIT ); + // Wait until HW starts CAN. + while( check_reg_bit( &hal_ll_hw_reg->msr, HAL_LL_CAN_MSR_INAK_BIT )) { + if( 0 == timeout-- ) + return HAL_LL_CAN_ERROR; + } + + return HAL_LL_CAN_SUCCESS; +} +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/src/can/implementations/doc_ds_161/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/can/implementations/doc_ds_161/CMakeLists.cmake new file mode 100644 index 000000000..715f1d3ba --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/can/implementations/doc_ds_161/CMakeLists.cmake @@ -0,0 +1,9 @@ +if(${MCU_NAME} MATCHES "^STM32L4Q5AG$|^STM32L4Q5CG$|^STM32L4Q5QG$|^STM32L4Q5RG$|^STM32L4Q5VG$|^STM32L4Q5ZG$") + set(can_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_can.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_161") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_161") + list(APPEND hal_ll_def_list "STM32L4xx") + list(APPEND hal_ll_def_list "STM32L4Qxx") + list(APPEND hal_ll_def_list "STM32L4Q5xx") + set(can_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/can/hal_ll_can_pin_map/implementations/doc_ds_161") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/can/implementations/doc_ds_161/hal_ll_can.c b/targets/arm/mikroe/ai_generated/stm32/src/can/implementations/doc_ds_161/hal_ll_can.c new file mode 100644 index 000000000..af71506fc --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/can/implementations/doc_ds_161/hal_ll_can.c @@ -0,0 +1,1046 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_can.c + * @brief CAN HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_rcc.h" +#include "hal_ll_can.h" +#include "hal_ll_gpio.h" +#include "hal_ll_can_pin_map.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_can_handle_register_t hal_ll_module_state[CAN_MODULE_COUNT] = { (handle_t *)NULL, (handle_t *)NULL, false }; + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_can_get_module_state_address ((hal_ll_can_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_can_get_handle (hal_ll_can_handle_register_t *)hal_ll_can_get_module_state_address->hal_ll_can_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_can_get_base_struct(_handle) ((hal_ll_can_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_can_get_base_from_hal_handle ((hal_ll_can_hw_specifics_map_t *)((hal_ll_can_handle_register_t *)\ + (((hal_ll_can_handle_register_t *)(handle))->hal_ll_can_handle))->hal_ll_can_handle)->base +/*!< @brief Helper macro for configuring the filter */ +#define hal_ll_can_filter_configure_32(mask_32) ((mask_32 & 0x07FF) << 21U | (mask_32 & 0x1FFFF800) >> 8U) +#define hal_ll_can_filter_configure_16(mask_16) ((((uint32_t)(mask_16 & 0x07FF) << 5U) | ((uint32_t)(mask_16 & 0x3800) >> 11U))) +#define hal_ll_can_filter_get_format_32(mask_32) (((mask_32 & 0x1FFFF800))?1:0) +#define hal_ll_can_filter_get_format_16(mask) ((mask & 0x1C00)?1:0) +/*!< @brief Helper macro for handling the received message */ +#define hal_ll_can_message_received(fifo,mask) ((fifo & mask)) +#define hal_ll_can_get_rx_data(byte,data_register,offset) ((uint8_t)(((byte) & data_register) >> offset)) +#define hal_ll_can_get_rx_id(id_register,mask,offset) ((id_register & mask ) >> offset) +#define hal_ll_can_get_rx_eid(id_register,mask,offset) ((id_register & mask ) << offset) +/*!< @brief Helper macros for bit rate calculation */ +#define hal_ll_can_check_time_segments(tseg1,tseg2) ((16 < tseg1) || (8 < tseg2) || (0 == tseg1) || (0 == tseg2)) +#define hal_ll_can_get_btr_element_mask(element, offset) (((uint32_t)(element - 1)) << offset) + +/*!< @brief GPIO congiguration constants */ +#ifdef GPIO_CFG_SPEED_VERY_HIGH +#define HAL_LL_CAN_AF_CONFIG (GPIO_CFG_MODE_ALT_FUNCTION | GPIO_CFG_SPEED_VERY_HIGH | GPIO_CFG_OTYPE_PP | GPIO_CFG_PULL_UP) +#else +#define HAL_LL_CAN_AF_CONFIG (GPIO_CFG_MODE_ALT_FUNCTION | GPIO_CFG_SPEED_HIGH | GPIO_CFG_OTYPE_PP | GPIO_CFG_PULL_UP) +#endif +/*!< @brief CAN clock enable bits */ +#define HAL_LL_CAN1_CLOCK_ENABLE (25) +/*!< @brief CAN baudrate constants and register bits and masks */ +#define HAL_LL_CAN_BTR_PRESCALER_OFFSET (0) +#define HAL_LL_CAN_BTR_SJW_VALUE (1) +#define HAL_LL_CAN_BTR_TSEG1_OFFSET (16) +#define HAL_LL_CAN_BTR_TSEG2_OFFSET (20) +#define HAL_LL_CAN_BTR_SJW_OFFSET (24) +#define HAL_LL_CAN_BTR_LBKM_BIT (30) +#define HAL_LL_CAN_BTR_SILM_BIT (31) +#define HAL_LL_CAN_BTR_MAX_PRESCALER_VALUE (1024) +#define HAL_LL_CAN_BTR_REGISTER_MASK (0xC37F03FFUL) +/*!< @brief CAN control and status register bits */ +#define HAL_LL_CAN_MCR_INRQ_BIT (0) +#define HAL_LL_CAN_MSR_INAK_BIT (0) +#define HAL_LL_CAN_MCR_SLEEP_BIT (1) +#define HAL_LL_CAN_MSR_SLAK_BIT (1) +/*!< @brief CAN filter constants and register bits and masks */ +#define HAL_LL_CAN_FMR_FINIT_BIT (0) +#define HAL_LL_CAN_FIR_RTR_32_BIT (1) +#define HAL_LL_CAN_FIR_EID_32_BIT (2) +#define HAL_LL_CAN_FIR_EID_16_LOW_BIT (3) +#define HAL_LL_CAN_FIR_RTR_16_LOW_BIT (4) +#define HAL_LL_CAN_SINGLE_CORE_FILTER_LIMIT (27) +#define HAL_LL_CAN_FIR_EID_16_HIGH_BIT (19) +#define HAL_LL_CAN_FIR_RTR_16_HIGH_BIT (20) +#define HAL_LL_CAN_FILTER_NUMBER (27) +/*!< @brief CAN transmit constants, registers bits and masks */ +#define HAL_LL_CAN_TIR_TXRQ_BIT (0) +#define HAL_LL_CAN_TIR_RTR_BIT (1) +#define HAL_LL_CAN_TIR_IDE_BIT (2) +#define HAL_LL_CAN_TRANSMIT_MAILBOX_COUNT (3) +#define HAL_LL_CAN_TIR_EID_SHIFT (8) +#define HAL_LL_CAN_TIR_STID_SHIFT (21) +#define HAL_LL_CAN_TSR_CODE_SHIFT (24) +#define HAL_LL_CAN_TSR_CODE_MASK (0x03000000UL) +/*!< @brief CAN receive register bits and masks */ +#define HAL_LL_CAN_RF0R_RFOM0_BIT (5) +#define HAL_LL_CAN_RF1R_RFOM1_BIT (5) +#define HAL_LL_CAN_RF0R_FMP0_MASK (0x00000003UL) +#define HAL_LL_CAN_RF1R_FMP1_MASK (0x00000003UL) +/*!< @brief CAN receive FIFO constants, register bits and masks */ +#define HAL_LL_CAN_RIR_RTR_BIT (1) +#define HAL_LL_CAN_RIR_IDE_BIT (2) +#define HAL_LL_CAN_RIR_EXID_SHIFT (8) +#define HAL_LL_CAN_RIR_STID_SHIFT (21) +#define HAL_LL_CAN_RDTR_DLC_MASK (0x0000000FUL) +#define HAL_LL_CAN_RIR_STID_MASK (0xFFE00000UL) +#define HAL_LL_CAN_RIR_EXID_MASK (0x001FFFF8UL) +/*!< @brief Helper macro for defining temout value */ +#define HAL_LL_CAN_TIMEOUT_VALUE (10000UL) +/*!< @brief Byte offset macros */ +#define HAL_LL_CAN_BYTE_OFFSET_0 (0U) +#define HAL_LL_CAN_BYTE_OFFSET_1 (8U) +#define HAL_LL_CAN_BYTE_OFFSET_2 (16U) +#define HAL_LL_CAN_BYTE_OFFSET_3 (24U) +#define HAL_LL_CAN_BYTE_FIRST (0x000000FFUL) +#define HAL_LL_CAN_BYTE_SECOND (0x0000FF00UL) +#define HAL_LL_CAN_BYTE_THIRD (0x00FF0000UL) +#define HAL_LL_CAN_BYTE_FOURTH (0xFF000000UL) + +/*!< @brief CAN hw specific structure */ +typedef struct +{ + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + hal_ll_can_pins_t pins; + hal_ll_can_mode_t mode; + uint32_t frequency; +} hal_ll_can_hw_specifics_map_t; + +/*!< @brief CAN hw specific module values */ +typedef struct +{ + hal_ll_pin_name_t pin_tx; + hal_ll_pin_name_t pin_rx; +} hal_ll_can_pin_id; + +/* @brief CAN TxMailBox structure */ +typedef struct +{ + hal_ll_base_addr_t tir; /*!< CAN TX mailbox identifier register */ + hal_ll_base_addr_t tdtr; /*!< CAN mailbox data length control and time stamp register */ + hal_ll_base_addr_t tdlr; /*!< CAN mailbox data low register */ + hal_ll_base_addr_t tdhr; /*!< CAN mailbox data high register */ +} hal_ll_can_txmailbox_t; + +/* @brief Controller Area Network FIFOMailBox structure */ +typedef struct +{ + hal_ll_base_addr_t rir; /*!< CAN receive FIFO mailbox identifier register */ + hal_ll_base_addr_t rdtr; /*!< CAN receive FIFO mailbox data length control and time stamp register */ + hal_ll_base_addr_t rdlr; /*!< CAN receive FIFO mailbox data low register */ + hal_ll_base_addr_t rdhr; /*!< CAN receive FIFO mailbox data high register */ +} hal_ll_can_fifomailbox_t; + +/* @brief Controller Area Network FilterRegister structure */ +typedef struct +{ + hal_ll_base_addr_t fr1; /*!< CAN Filter bank register 1 */ + hal_ll_base_addr_t fr2; /*!< CAN Filter bank register 2 */ +} hal_ll_can_filter_reg_t; + +/*!< @brief CAN HW register structure */ +typedef struct +{ + hal_ll_base_addr_t mcr; /*CAN master control register*/ + hal_ll_base_addr_t msr; /*CAN master status register*/ + hal_ll_base_addr_t tsr; /*CAN transmit status register*/ + hal_ll_base_addr_t rf0r; /*CAN receive FIFO 0 register*/ + hal_ll_base_addr_t rf1r; /*CAN receive FIFO 1 register*/ + hal_ll_base_addr_t ier; /*CAN interrupt enable register*/ + hal_ll_base_addr_t esr; /*CAN error status register*/ + hal_ll_base_addr_t btr; /*CAN bit timing register*/ + hal_ll_base_addr_t __unused1[88]; + hal_ll_can_txmailbox_t tx_mailbox[3]; + hal_ll_can_fifomailbox_t fifo_mailbox[2]; + hal_ll_base_addr_t __unused2[12]; + hal_ll_base_addr_t fmr; /*CAN filter master register*/ + hal_ll_base_addr_t fm1r; /*CAN filter mode register*/ + hal_ll_base_addr_t __unused3[1]; + hal_ll_base_addr_t fs1r; /*CAN filter scale register*/ + hal_ll_base_addr_t __unused4[1]; + hal_ll_base_addr_t ffa1r; /*CAN filter FIFO assignment register*/ + hal_ll_base_addr_t __unused5[1]; + hal_ll_base_addr_t fa1r; /*CAN filter activation register*/ + hal_ll_base_addr_t __unused6[8]; + hal_ll_can_filter_reg_t filter_reg[28]; +} hal_ll_can_base_handle_t; + +/*!< @brief CAN hw specific error values */ +typedef enum +{ + HAL_LL_CAN_SUCCESS = 0, + HAL_LL_CAN_WRONG_PINS, + HAL_LL_CAN_MODULE_ERROR, + + HAL_LL_CAN_ERROR = (-1) +} hal_ll_can_err_t; +// ------------------------------------------------------------------ VARIABLES +/*!< @brief CAN hardware specific info */ +static hal_ll_can_hw_specifics_map_t hal_ll_can_hw_specifics_map[] = +{ + #ifdef CAN_MODULE_1 + { HAL_LL_CAN1_BASE_ADDRESS, hal_ll_can_module_num( CAN_MODULE_1 ), { HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0 }, HAL_LL_CAN_MODE_NORMAL, 500000 }, + #endif + { HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, { HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0 }, HAL_LL_CAN_MODE_NORMAL, 500000 } +}; + + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_can_handle_register_t *low_level_handle; +static volatile hal_ll_can_hw_specifics_map_t *hal_ll_can_hw_specifics_map_local; +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Check if pins are adequate. + * + * Checks tx and rx pins the user has passed with pre-defined + * pins in tx and rx maps. Take into consideration that module + * index numbers have to be the same for both pins. + * + * @param[in] tx_pin - TX pre-defined pin name. + * @param[in] rx_pin - RX pre-defined pin name. + * @param[in] *index_list - Index list address + * @param[in] *handle_map - HAL low level context object handle. + * @return hal_ll_pin_name_t Module index based on pins. + * + * Returns pre-defined module index from pin maps, if pins + * are adequate. + */ +static hal_ll_pin_name_t hal_ll_can_check_pins( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, + hal_ll_can_pin_id *index_list, hal_ll_can_handle_register_t *handle_map ); + +/** + * @brief Sets CAN pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if CAN is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_state - Init/De-init + * + * @return None + */ +static void hal_ll_can_alternate_functions_set_state( hal_ll_can_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * CAN TX and RX pins. + * + * @param[in] module_index CAN HW module index -- 0,1,2... + * @param[in] *index_list Array with TX and RX map index values + * and module number + * + * @return None + */ +static void hal_ll_can_map_pins( uint8_t module_index, hal_ll_can_pin_id *index_list ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_can_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_can_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_can_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Full CAN module initialization procedure. + * + * Initializes CAN module on hardware level, based on beforehand + * set configuration and module handler. Sets control and filter registers. + * Initializes module clock. + * + * @param[in] map - Object specific context handler. + * @param[in] config - CAN config structure. + * @param[in] filter_config - CAN filter config structure. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_can_hw_init( hal_ll_can_hw_specifics_map_t *map, hal_ll_can_config_t *config, + hal_ll_can_filter_config_t *filter_config ); + +/** + * @brief Calculates parameters for desired CAN frequency. + * + * Calculates adequate values to be written in CAN_BTR register + * in order to set appropriate baud rate. + * + * @param[in] map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_can_bit_timing( hal_ll_can_hw_specifics_map_t *map ); + +/** + * @brief Initialize CAN module on hardware level. + * + * Initializes CAN module on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] map - Object specific context handler. + * @param[in] config - CAN config structure. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_can_module_init( hal_ll_can_hw_specifics_map_t *map, hal_ll_can_config_t *config ); + +/** + * @brief Configure CAN filter. + * + * Initializes CAN filter on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] map - Object specific context handler. + * @param[in] filter_config - CAN filter config structure. + * @param[in] default_config - Defines if we should check if filter is assignable. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_can_filter_init( hal_ll_can_hw_specifics_map_t *map, hal_ll_can_filter_config_t *filter_config, bool default_config ); + +/** + * @brief Enable clock for CAN module on hardware level. + * + * Initializes CAN module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] module_index - Object specific context handler. + * @param[in] clock_enable - True(enable clock)/False(disable clock). + * + * @return None + */ +static void hal_ll_can_clock_enable( uint8_t module_index, bool clock_enable ); + +/** + * @brief Set operation mode. + * + * Sets an operation mode requested by user. + * + * @param[in] map - Object specific context handler. + * @param[in] config - CAN config structure. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_can_set_operation_mode( hal_ll_can_hw_specifics_map_t *map, hal_ll_can_config_t *config ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_can_register_handle( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_can_handle_register_t *handle_map, uint8_t *hal_module_id ) { + + hal_ll_can_pin_id index_list[CAN_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + uint16_t pin_check_result; + + // Check if pins are valid. + if (( pin_check_result = hal_ll_can_check_pins( tx_pin, rx_pin, &index_list, handle_map )) == HAL_LL_PIN_NC ) { + return HAL_LL_CAN_WRONG_PINS; + }; + + if (( hal_ll_can_hw_specifics_map[pin_check_result].pins.tx_pin.pin_name != tx_pin ) || + ( hal_ll_can_hw_specifics_map[pin_check_result].pins.rx_pin.pin_name != rx_pin )) + { + // Clear previous alternate function for chosen CAN pins. + hal_ll_can_alternate_functions_set_state( &hal_ll_can_hw_specifics_map[ pin_check_result ], false ); + + hal_ll_can_map_pins( pin_check_result, &index_list ); + + // Set adequate CAN alternate function for chosen CAN pins. + hal_ll_can_alternate_functions_set_state( &hal_ll_can_hw_specifics_map[ pin_check_result ], true ); + + handle_map[pin_check_result].init_ll_state = false; + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[pin_check_result].hal_ll_can_handle = ( handle_t * )&hal_ll_can_hw_specifics_map[pin_check_result].base; + + handle_map[pin_check_result].hal_ll_can_handle = ( handle_t * )&hal_ll_module_state[pin_check_result].hal_ll_can_handle; + + return HAL_LL_CAN_SUCCESS; +} + +hal_ll_err_t hal_ll_can_init( handle_t *handle, hal_ll_can_config_t *config, + hal_ll_can_filter_config_t *filter_config ) { + hal_ll_can_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_can_get_module_state_address ); + hal_ll_can_handle_register_t *hal_handle = ( hal_ll_can_handle_register_t * )*handle; + uint8_t pin_check_result = hal_ll_can_hw_specifics_map_local->module_index; + + if ( HAL_LL_CAN_ERROR == hal_ll_can_hw_init( hal_ll_can_hw_specifics_map_local, config, filter_config )) + return HAL_LL_CAN_ERROR; + + hal_ll_module_state[pin_check_result].hal_ll_can_handle = ( handle_t * )&hal_ll_can_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_CAN_SUCCESS; +} + +hal_ll_err_t hal_ll_can_set_filter( handle_t *handle, hal_ll_can_config_t *config, + hal_ll_can_filter_config_t *filter_config ) { + low_level_handle = hal_ll_can_get_handle; + hal_ll_can_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_can_get_module_state_address ); + + low_level_handle->init_ll_state = false; + if ( HAL_LL_CAN_ERROR == hal_ll_can_filter_init( hal_ll_can_hw_specifics_map_local, filter_config, false )) + return HAL_LL_CAN_ERROR; + + low_level_handle->init_ll_state = true; + + return HAL_LL_CAN_SUCCESS; +} + +hal_ll_err_t hal_ll_can_set_frequency( handle_t *handle, hal_ll_can_config_t *config, + hal_ll_can_filter_config_t *filter_config ) { + low_level_handle = hal_ll_can_get_handle; + hal_ll_can_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_can_get_module_state_address ); + uint32_t original_frequency; + hal_ll_err_t result; + + low_level_handle->init_ll_state = false; + + original_frequency = hal_ll_can_hw_specifics_map_local->frequency; + + hal_ll_can_hw_specifics_map_local->frequency = config->frequency; + result = hal_ll_can_hw_init( hal_ll_can_hw_specifics_map_local, config, filter_config ); + + // In case the desired frequency setting hasn't been achieved, there's no need to update the map. + if( HAL_LL_CAN_SUCCESS != result ) + hal_ll_can_hw_specifics_map_local->frequency = original_frequency; + + low_level_handle->init_ll_state = true; + + return result; +} + +hal_ll_err_t hal_ll_can_get_frequency( handle_t *handle ) { + hal_ll_can_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_can_get_module_state_address ); + + return hal_ll_can_hw_specifics_map_local->frequency; +} + +hal_ll_err_t hal_ll_can_set_mode( handle_t *handle, hal_ll_can_config_t *config, + hal_ll_can_filter_config_t *filter_config ) { + low_level_handle = hal_ll_can_get_handle; + hal_ll_can_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_can_get_module_state_address ); + hal_ll_err_t result; + + low_level_handle->init_ll_state = false; + + // NOTE: Changing mode won't result in an error, so saving the previous value is not needed. + hal_ll_can_hw_specifics_map_local->mode = config->mode; + result = hal_ll_can_hw_init( hal_ll_can_hw_specifics_map_local, config, filter_config ); + + low_level_handle->init_ll_state = true; + + return result; +} + +hal_ll_err_t hal_ll_can_get_mode( handle_t *handle ) { + hal_ll_can_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_can_get_module_state_address ); + + return hal_ll_can_hw_specifics_map_local->mode; +} + +hal_ll_err_t hal_ll_can_transmit( handle_t *handle, hal_ll_can_transmit_message_struct *transmit_message ) { + hal_ll_can_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_can_get_module_state_address ); + hal_ll_can_base_handle_t *hal_ll_hw_reg = ( hal_ll_can_base_handle_t *)hal_ll_can_hw_specifics_map_local->base; + uint8_t tx_mailbox_num; + uint16_t timeout = HAL_LL_CAN_TIMEOUT_VALUE; + + tx_mailbox_num = ( hal_ll_hw_reg->tsr & HAL_LL_CAN_TSR_CODE_MASK ) >> HAL_LL_CAN_TSR_CODE_SHIFT; + + hal_ll_hw_reg->tx_mailbox[tx_mailbox_num].tir = hal_ll_can_filter_configure_32( transmit_message->message.id ); + + // Set an appropriate frame format of the message. + if( HAL_LL_CAN_FRAME_FORMAT_STANDARD_11BITS == transmit_message->message.frame_format ) + clear_reg_bit( &hal_ll_hw_reg->tx_mailbox[tx_mailbox_num].tir, HAL_LL_CAN_TIR_IDE_BIT ); + else + set_reg_bit( &hal_ll_hw_reg->tx_mailbox[tx_mailbox_num].tir, HAL_LL_CAN_TIR_IDE_BIT ); + + // Set an appropriate frame type of the message. + if( HAL_LL_CAN_FRAME_TYPE_DATA == transmit_message->message.frame_type ) + clear_reg_bit( &hal_ll_hw_reg->tx_mailbox[tx_mailbox_num].tir, HAL_LL_CAN_TIR_RTR_BIT ); + else + set_reg_bit( &hal_ll_hw_reg->tx_mailbox[tx_mailbox_num].tir, HAL_LL_CAN_TIR_RTR_BIT ); + + hal_ll_hw_reg->tx_mailbox[tx_mailbox_num].tdtr = transmit_message->message.data_len; + + hal_ll_hw_reg->tx_mailbox[tx_mailbox_num].tdlr = (( uint32_t )transmit_message->message.message_data[0] ) | + (( uint32_t )transmit_message->message.message_data[1] << HAL_LL_CAN_BYTE_OFFSET_1 ) | + (( uint32_t )transmit_message->message.message_data[2] << HAL_LL_CAN_BYTE_OFFSET_2 ) | + (( uint32_t )transmit_message->message.message_data[3] << HAL_LL_CAN_BYTE_OFFSET_3 ); + + hal_ll_hw_reg->tx_mailbox[tx_mailbox_num].tdhr = (( uint32_t )transmit_message->message.message_data[4] ) | + (( uint32_t )transmit_message->message.message_data[5] << HAL_LL_CAN_BYTE_OFFSET_1 ) | + (( uint32_t )transmit_message->message.message_data[6] << HAL_LL_CAN_BYTE_OFFSET_2 ) | + (( uint32_t )transmit_message->message.message_data[7] << HAL_LL_CAN_BYTE_OFFSET_3 ); + + // Transmit mailbox request. + set_reg_bit( &hal_ll_hw_reg->tx_mailbox[tx_mailbox_num].tir, HAL_LL_CAN_TIR_TXRQ_BIT ); + // Waiting for message to be received by receiver. + while ( check_reg_bit( &hal_ll_hw_reg->tx_mailbox[tx_mailbox_num].tir, HAL_LL_CAN_TIR_TXRQ_BIT )) { + if( 0 == timeout-- ) + return HAL_LL_CAN_ERROR; + } + + return HAL_LL_CAN_SUCCESS; +} + +void hal_ll_can_transmission_stop( handle_t *handle ) { + hal_ll_can_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_can_get_module_state_address ); + hal_ll_can_base_handle_t *hal_ll_hw_reg = ( hal_ll_can_base_handle_t *)hal_ll_can_hw_specifics_map_local->base; + uint8_t tx_mailbox_num; + + // Stop transmitting any messages. + for ( tx_mailbox_num = 0; tx_mailbox_num < HAL_LL_CAN_TRANSMIT_MAILBOX_COUNT; tx_mailbox_num++ ) { + if ( check_reg_bit( &hal_ll_hw_reg->tx_mailbox[tx_mailbox_num].tir, HAL_LL_CAN_TIR_TXRQ_BIT )) + clear_reg_bit( &hal_ll_hw_reg->tx_mailbox[tx_mailbox_num].tir, HAL_LL_CAN_TIR_TXRQ_BIT ); + } +} + +hal_ll_err_t hal_ll_can_receive( handle_t *handle, hal_ll_can_receive_message_struct *receive_message ) { + hal_ll_can_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_can_get_module_state_address ); + hal_ll_can_base_handle_t *hal_ll_hw_reg = ( hal_ll_can_base_handle_t *)hal_ll_can_hw_specifics_map_local->base; + uint8_t rx_fifo_num = receive_message->rx_fifo_number; + uint32_t timeout = HAL_LL_CAN_TIMEOUT_VALUE; + + if ( HAL_LL_CAN_FILTER_FIFO0 == rx_fifo_num ) { + while( !( hal_ll_can_message_received( hal_ll_hw_reg->rf0r, HAL_LL_CAN_RF0R_FMP0_MASK ))) { + if( 0 == timeout-- ) + return HAL_LL_CAN_ERROR; + } + } else if ( HAL_LL_CAN_FILTER_FIFO1 == rx_fifo_num ) { + while ( !( hal_ll_can_message_received( hal_ll_hw_reg->rf1r, HAL_LL_CAN_RF1R_FMP1_MASK ))) { + if( 0 == timeout-- ) + return HAL_LL_CAN_ERROR; + } + } else + // STM32 MCUs have only 2 RX FIFOs. + return HAL_LL_CAN_ERROR; + + // Get parameters. + receive_message->message.data_len = hal_ll_hw_reg->fifo_mailbox[rx_fifo_num].rdtr & HAL_LL_CAN_RDTR_DLC_MASK; + receive_message->message.frame_type = check_reg_bit( &hal_ll_hw_reg->fifo_mailbox[rx_fifo_num].rir, HAL_LL_CAN_RIR_RTR_BIT ); + receive_message->message.frame_format = check_reg_bit( &hal_ll_hw_reg->fifo_mailbox[rx_fifo_num].rir, HAL_LL_CAN_RIR_IDE_BIT ); + + receive_message->message.std_id = hal_ll_can_get_rx_id( hal_ll_hw_reg->fifo_mailbox[rx_fifo_num].rir, HAL_LL_CAN_RIR_STID_MASK, HAL_LL_CAN_RIR_STID_SHIFT ); + if ( HAL_LL_CAN_FRAME_FORMAT_EXTENDED_29BITS == receive_message->message.frame_format ) + receive_message->message.id |= hal_ll_can_get_rx_eid( hal_ll_hw_reg->fifo_mailbox[rx_fifo_num].rir, HAL_LL_CAN_RIR_EXID_MASK, HAL_LL_CAN_RIR_EXID_SHIFT ); + + // Get all data bytes. + receive_message->message.message_data[0] = hal_ll_can_get_rx_data( HAL_LL_CAN_BYTE_FIRST, hal_ll_hw_reg->fifo_mailbox[rx_fifo_num].rdlr, HAL_LL_CAN_BYTE_OFFSET_0 ); + receive_message->message.message_data[1] = hal_ll_can_get_rx_data( HAL_LL_CAN_BYTE_SECOND, hal_ll_hw_reg->fifo_mailbox[rx_fifo_num].rdlr, HAL_LL_CAN_BYTE_OFFSET_1 ); + receive_message->message.message_data[2] = hal_ll_can_get_rx_data( HAL_LL_CAN_BYTE_THIRD, hal_ll_hw_reg->fifo_mailbox[rx_fifo_num].rdlr, HAL_LL_CAN_BYTE_OFFSET_2 ); + receive_message->message.message_data[3] = hal_ll_can_get_rx_data( HAL_LL_CAN_BYTE_FOURTH, hal_ll_hw_reg->fifo_mailbox[rx_fifo_num].rdlr, HAL_LL_CAN_BYTE_OFFSET_3 ); + receive_message->message.message_data[4] = hal_ll_can_get_rx_data( HAL_LL_CAN_BYTE_FIRST, hal_ll_hw_reg->fifo_mailbox[rx_fifo_num].rdhr, HAL_LL_CAN_BYTE_OFFSET_0 ); + receive_message->message.message_data[5] = hal_ll_can_get_rx_data( HAL_LL_CAN_BYTE_SECOND, hal_ll_hw_reg->fifo_mailbox[rx_fifo_num].rdhr, HAL_LL_CAN_BYTE_OFFSET_1 ); + receive_message->message.message_data[6] = hal_ll_can_get_rx_data( HAL_LL_CAN_BYTE_THIRD, hal_ll_hw_reg->fifo_mailbox[rx_fifo_num].rdhr, HAL_LL_CAN_BYTE_OFFSET_2 ); + receive_message->message.message_data[7] = hal_ll_can_get_rx_data( HAL_LL_CAN_BYTE_FOURTH, hal_ll_hw_reg->fifo_mailbox[rx_fifo_num].rdhr, HAL_LL_CAN_BYTE_OFFSET_3 ); + + // Release RX FIFO. + if ( HAL_LL_CAN_FILTER_FIFO0 == rx_fifo_num ) + set_reg_bit( &hal_ll_hw_reg->rf0r, HAL_LL_CAN_RF0R_RFOM0_BIT ); + else + set_reg_bit( &hal_ll_hw_reg->rf1r, HAL_LL_CAN_RF1R_RFOM1_BIT ); + + return HAL_LL_CAN_SUCCESS; +} + +hal_ll_err_t hal_ll_can_close( handle_t *handle ) { + low_level_handle = hal_ll_can_get_handle; + hal_ll_can_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_can_get_module_state_address); + + if( low_level_handle->hal_ll_can_handle != NULL ) { + hal_ll_can_clock_enable(hal_ll_can_hw_specifics_map_local->module_index, true); + hal_ll_can_alternate_functions_set_state( hal_ll_can_hw_specifics_map_local, false ); + + hal_ll_can_clock_enable(hal_ll_can_hw_specifics_map_local->module_index, false); + + hal_ll_can_hw_specifics_map_local->pins.tx_pin.pin_name = HAL_LL_PIN_NC; + hal_ll_can_hw_specifics_map_local->pins.tx_pin.pin_af = 0; + hal_ll_can_hw_specifics_map_local->pins.rx_pin.pin_name = HAL_LL_PIN_NC; + hal_ll_can_hw_specifics_map_local->pins.rx_pin.pin_af = 0; + + hal_ll_can_hw_specifics_map_local->frequency = 500000UL; + + low_level_handle->hal_ll_can_handle = NULL; + low_level_handle->hal_drv_can_handle = NULL; + + low_level_handle->init_ll_state = false; + + return HAL_LL_CAN_SUCCESS; + } else + return HAL_LL_CAN_ERROR; +} + +// ---------------------------------------------- PRIVATE FUNCTION DEFINITIONS + +static hal_ll_pin_name_t hal_ll_can_check_pins( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, + hal_ll_can_pin_id *index_list, hal_ll_can_handle_register_t *handle_map ) { + static const uint16_t tx_map_size = ( sizeof( hal_ll_can_tx_map ) / sizeof( hal_ll_can_pin_map_t ) ); + static const uint16_t rx_map_size = ( sizeof( hal_ll_can_rx_map ) / sizeof( hal_ll_can_pin_map_t ) ); + uint8_t hal_ll_module_id = 0; + uint8_t index_counter = 0; + uint16_t tx_index; + uint16_t rx_index; + + if ( (HAL_LL_PIN_NC == tx_pin) || (HAL_LL_PIN_NC == rx_pin) ) { + return HAL_LL_PIN_NC; + } + + for ( tx_index = 0; tx_index < tx_map_size; tx_index++ ) + { + if ( hal_ll_can_tx_map[ tx_index ].pin == tx_pin ) + { + for ( rx_index = 0; rx_index < rx_map_size; rx_index++ ) + { + if ( hal_ll_can_rx_map[ rx_index ].pin == rx_pin ) + { + if ( hal_ll_can_tx_map[ tx_index ].base == hal_ll_can_rx_map[ rx_index ].base ) { + // Get module number. + hal_ll_module_id = hal_ll_can_tx_map[ tx_index ].module_index; + + // Map pin names. + index_list[hal_ll_module_id].pin_tx = tx_index; + index_list[hal_ll_module_id].pin_rx = rx_index; + + // Check if module is taken. + if ( NULL == handle_map[ hal_ll_module_id ].hal_drv_can_handle ) { + return hal_ll_module_id; + } else if ( CAN_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static void hal_ll_can_alternate_functions_set_state( hal_ll_can_hw_specifics_map_t *map, bool hal_ll_state ) { + module_struct module; + + if ( (map->pins.tx_pin.pin_name != HAL_LL_PIN_NC) && map->pins.rx_pin.pin_name != HAL_LL_PIN_NC ) { + module.pins[0] = VALUE( map->pins.tx_pin.pin_name, map->pins.tx_pin.pin_af ); + module.pins[1] = VALUE( map->pins.rx_pin.pin_name, map->pins.rx_pin.pin_af ); + module.pins[2] = GPIO_MODULE_STRUCT_END; + + module.configs[0] = HAL_LL_CAN_AF_CONFIG; + module.configs[1] = HAL_LL_CAN_AF_CONFIG; + module.configs[2] = GPIO_MODULE_STRUCT_END; + + /* STM32F1xx specific. */ + module.gpio_remap = map->pins.tx_pin.pin_af; + + hal_ll_gpio_module_struct_init( &module, hal_ll_state ); + } +} + +static void hal_ll_can_map_pins( uint8_t module_index, hal_ll_can_pin_id *index_list ) { + // Map new pins. + hal_ll_can_hw_specifics_map[module_index].pins.tx_pin.pin_name = hal_ll_can_tx_map[index_list[module_index].pin_tx].pin; + hal_ll_can_hw_specifics_map[module_index].pins.rx_pin.pin_name = hal_ll_can_rx_map[index_list[module_index].pin_rx].pin; + // TX and RX could have different alternate function settings, hence save both AF values. + hal_ll_can_hw_specifics_map[module_index].pins.tx_pin.pin_af = hal_ll_can_tx_map[index_list[module_index].pin_tx].af; + hal_ll_can_hw_specifics_map[module_index].pins.rx_pin.pin_af = hal_ll_can_rx_map[index_list[module_index].pin_rx].af; +} + +static hal_ll_can_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + uint8_t hal_ll_module_count = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_can_handle_register_t )); + static uint8_t hal_ll_module_error = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_can_handle_register_t )); + + while( hal_ll_module_count-- ) { + if (hal_ll_can_get_base_from_hal_handle == hal_ll_can_hw_specifics_map[hal_ll_module_count].base) { + return &hal_ll_can_hw_specifics_map[hal_ll_module_count]; + } + } + + return &hal_ll_can_hw_specifics_map[hal_ll_module_error]; +} + +static void hal_ll_can_clock_enable( uint8_t module_index, bool clock_enable ) { + switch( module_index ) { + #ifdef CAN_MODULE_1 + case ( hal_ll_can_module_num( CAN_MODULE_1 )): + #ifdef _RCC_APB1ENR1 + if( true == clock_enable ) + set_reg_bit( _RCC_APB1ENR1, HAL_LL_CAN1_CLOCK_ENABLE ); + else + clear_reg_bit( _RCC_APB1ENR1, HAL_LL_CAN1_CLOCK_ENABLE ); + break; + #endif + #endif + default: + break; + } +} + +static hal_ll_err_t hal_ll_can_bit_timing( hal_ll_can_hw_specifics_map_t *map ) { + hal_ll_can_base_handle_t *hal_ll_hw_reg = hal_ll_can_get_base_struct( map->base ); + rcc_clocks_t rcc_clocks; + uint16_t prescaler, temp; + double time_quanta, bit_time, num_of_tq; + uint8_t sjw, tseg1, tseg2; + uint32_t baud_rate, can_clock; + + baud_rate = map->frequency; + + RCC_GetClocksFrequency( &rcc_clocks ); + can_clock = rcc_clocks.pclk1; + + /* + * Description: This code snippet calculates the optimal settings for configuring + * the CAN bus baud rate on STM32 microcontrollers, based on the provided parameters. + * + * Initial parameters: + * - can_clock: CAN source clock frequency (APB1) in Hz. + * - baud_rate: Desired CAN bus baud rate. + * + * Calculated parameters: + * - prescaler: The prescaler value to achieve the desired baud rate. + * - tseg1, tseg2: Time segment values for configuring the CAN bus. + * + * Formulas used: + * - time_quanta = 1 / can_clock + * - bit_time = 1 / baud_rate + * - num_of_tq = bit_time / time_quanta (number of time quanta) + * - (sjw + tseg1) / (sjw + tseg1 + tseg2) = 87.5% (optimal sampling for CAN) + * - baud_rate = can_clock / (prescaler * (tseg1 + tseg2 + 1)) (from STM32 Reference manuals) + * + * Note: sjw (synchronization jump width) is fixed to 1, the preferred value, but can range from 1 to 4. + */ + + sjw = HAL_LL_CAN_BTR_SJW_VALUE; + + bit_time = (double) 1 / baud_rate; + + for( prescaler = 1; prescaler <= HAL_LL_CAN_BTR_MAX_PRESCALER_VALUE; prescaler++ ) { + time_quanta = (double) prescaler / can_clock; + num_of_tq = bit_time / time_quanta; + tseg1 = 0.875 * num_of_tq - sjw; + tseg2 = num_of_tq - tseg1 - sjw; + + // Time segment 1 can be anywhere between 1 and 16, while the value of time segment 2 goes from 1 to 8. + if ( hal_ll_can_check_time_segments( tseg1, tseg2 )) continue; + + temp = prescaler * ( tseg1 + tseg2 + 1 ); + uint32_t actual_baud_rate = can_clock / temp; + + if( actual_baud_rate == baud_rate ) { + // Exact match found. + uint32_t sjw_val = hal_ll_can_get_btr_element_mask( sjw, HAL_LL_CAN_BTR_SJW_OFFSET ); + uint32_t tseg1_val = hal_ll_can_get_btr_element_mask( tseg1, HAL_LL_CAN_BTR_TSEG1_OFFSET ); + uint32_t tseg2_val = hal_ll_can_get_btr_element_mask( tseg2, HAL_LL_CAN_BTR_TSEG2_OFFSET ); + uint32_t prescaler_val = hal_ll_can_get_btr_element_mask( prescaler, HAL_LL_CAN_BTR_PRESCALER_OFFSET );; + + hal_ll_hw_reg->btr |= sjw_val | tseg1_val | tseg2_val | prescaler_val; + return HAL_LL_CAN_SUCCESS; + } + + /* + * Note: Setting parameters that result in a baud rate that differs from the desired value is not acceptable. + * If two devices communicate over CAN, their baud rates need to be exactly the same. + */ + } + + // If this point was reached, baud rate wasn't set to the desired value and error is returned. + return HAL_LL_CAN_ERROR; +} + +static hal_ll_err_t hal_ll_can_set_operation_mode( hal_ll_can_hw_specifics_map_t *map, hal_ll_can_config_t *config ) { + hal_ll_can_base_handle_t *hal_ll_hw_reg = hal_ll_can_get_base_struct(map->base); + uint16_t timeout = HAL_LL_CAN_TIMEOUT_VALUE; + + clear_reg_bit( &hal_ll_hw_reg->btr, HAL_LL_CAN_BTR_LBKM_BIT ); + clear_reg_bit( &hal_ll_hw_reg->btr, HAL_LL_CAN_BTR_SILM_BIT ); + + switch ( config->mode ) { + case HAL_LL_CAN_MODE_NORMAL: + break; + case HAL_LL_CAN_MODE_LOOPBACK: + set_reg_bit( &hal_ll_hw_reg->btr, HAL_LL_CAN_BTR_LBKM_BIT ); + break; + case HAL_LL_CAN_MODE_SILENT: + set_reg_bit( &hal_ll_hw_reg->btr, HAL_LL_CAN_BTR_SILM_BIT ); + break; + case HAL_LL_CAN_MODE_LOOPBACK_SILENT: + set_reg_bit( &hal_ll_hw_reg->btr, HAL_LL_CAN_BTR_LBKM_BIT ); + set_reg_bit( &hal_ll_hw_reg->btr, HAL_LL_CAN_BTR_SILM_BIT ); + break; + + default: + // STM32 doesn't have operation mode requested by user. + return HAL_LL_CAN_ERROR; + } + return HAL_LL_CAN_SUCCESS; +} + +static hal_ll_err_t hal_ll_can_module_init( hal_ll_can_hw_specifics_map_t *map, hal_ll_can_config_t *config ) { + hal_ll_can_base_handle_t *hal_ll_hw_reg = hal_ll_can_get_base_struct( map->base ); + uint16_t timeout = HAL_LL_CAN_TIMEOUT_VALUE; + + // Request iitialization mode. + set_reg_bit( &hal_ll_hw_reg->mcr, HAL_LL_CAN_MCR_INRQ_BIT ); + // Wait until HW enters initialization mode. + while( !check_reg_bit( &hal_ll_hw_reg->msr, HAL_LL_CAN_MSR_INAK_BIT )) { + if( 0 == timeout-- ) + return HAL_LL_CAN_ERROR; + } + + timeout = HAL_LL_CAN_TIMEOUT_VALUE; + // Request the exit from sleep mode. + clear_reg_bit( &hal_ll_hw_reg->mcr, HAL_LL_CAN_MCR_SLEEP_BIT ); + // Wait until HW exits sleep mode. + while( check_reg_bit( &hal_ll_hw_reg->msr, HAL_LL_CAN_MSR_SLAK_BIT )) { + if( 0 == timeout-- ) + return HAL_LL_CAN_ERROR; + } + + // Clear CAN baudrate register. + hal_ll_hw_reg->btr &= ~HAL_LL_CAN_BTR_REGISTER_MASK; + + // Set the operation mode requested by user. + if ( HAL_LL_CAN_ERROR == hal_ll_can_set_operation_mode( map, config )) + return HAL_LL_CAN_ERROR; + + // Configure bit timing. + return hal_ll_can_bit_timing( map ); +} + +static hal_ll_err_t hal_ll_can_filter_init( hal_ll_can_hw_specifics_map_t *map, hal_ll_can_filter_config_t *filter_config, bool default_config ) { + hal_ll_can_base_handle_t *hal_ll_hw_reg = hal_ll_can_get_base_struct( map->base );; + uint8_t filter_number_pos = filter_config->can_filter_bank; + hal_ll_can_frame_format_t frame_format_id_mask[4]; + + /* + * CAN2 as a slave core of CAN1 uses the same filter registers as CAN1. + * Filter banks dedication for devices with multiple CAN modules is following: + * - Filters 0 to 13 are used for single core CAN usage (CAN1 or CAN3 only); + * - Filters 0 to 27 are used for dual core CAN usage (CAN1 and CAN2): + * - Number of start bank filter for CAN2 is configured with CANSB[5:0] bits in CAN_FMR register, + but this implementation uses default configuration (CAN2 start bank filter is 14). + */ + if ( !default_config ) { + #ifdef CAN_MODULE_1 + if ( HAL_LL_CAN1_BASE_ADDRESS == map->base ) { + if ( HAL_LL_CAN_SINGLE_CORE_FILTER_LIMIT < filter_number_pos ) + return HAL_LL_CAN_ERROR; + } + #endif + } + + // STM32 MCUs have only 2 FIFOs. + if ( HAL_LL_CAN_FILTER_FIFO1 < filter_config->can_filter_fifo ) + return HAL_LL_CAN_ERROR; + + // Set an initialization mode for the filters. + set_reg_bit( &hal_ll_hw_reg->fmr, HAL_LL_CAN_FMR_FINIT_BIT ); + + if( HAL_LL_CAN_FILTER_SCALE_32BIT == filter_config->can_filter_scale ) { + // Set single 32-bit filter scale configuration. + set_reg_bit( &hal_ll_hw_reg->fs1r, filter_number_pos ); + + hal_ll_hw_reg->filter_reg[filter_number_pos].fr1 = hal_ll_can_filter_configure_32( filter_config->can_filter_id ); + hal_ll_hw_reg->filter_reg[filter_number_pos].fr2 = hal_ll_can_filter_configure_32( filter_config->can_filter_mask_id ); + + // Configure the frame type of filter/mask. + if ( HAL_LL_CAN_FRAME_TYPE_RTR == filter_config->can_filter_frame_type[0] ) + set_reg_bit( &hal_ll_hw_reg->filter_reg[filter_number_pos].fr1, HAL_LL_CAN_FIR_RTR_32_BIT ); + else + clear_reg_bit( &hal_ll_hw_reg->filter_reg[filter_number_pos].fr1, HAL_LL_CAN_FIR_RTR_32_BIT ); + + if ( HAL_LL_CAN_FRAME_TYPE_RTR == filter_config->can_filter_frame_type[1] ) + set_reg_bit( &hal_ll_hw_reg->filter_reg[filter_number_pos].fr2, HAL_LL_CAN_FIR_RTR_32_BIT ); + else + clear_reg_bit( &hal_ll_hw_reg->filter_reg[filter_number_pos].fr2, HAL_LL_CAN_FIR_RTR_32_BIT ); + + + // Configure the format of filter/mask. + frame_format_id_mask[0] = hal_ll_can_filter_get_format_32( filter_config->can_filter_id ); + frame_format_id_mask[1] = hal_ll_can_filter_get_format_32( filter_config->can_filter_mask_id ); + + if ( HAL_LL_CAN_FRAME_FORMAT_EXTENDED_29BITS == frame_format_id_mask[0] ) + set_reg_bit( &hal_ll_hw_reg->filter_reg[filter_number_pos].fr1, HAL_LL_CAN_FIR_EID_32_BIT ); + else + clear_reg_bit( &hal_ll_hw_reg->filter_reg[filter_number_pos].fr1, HAL_LL_CAN_FIR_EID_32_BIT ); + + if ( HAL_LL_CAN_FRAME_FORMAT_EXTENDED_29BITS == frame_format_id_mask[1] ) + set_reg_bit( &hal_ll_hw_reg->filter_reg[filter_number_pos].fr2, HAL_LL_CAN_FIR_EID_32_BIT ); + else + clear_reg_bit( &hal_ll_hw_reg->filter_reg[filter_number_pos].fr2, HAL_LL_CAN_FIR_EID_32_BIT ); + + } else { + // Set dual 16-bit filter scale configuration. + clear_reg_bit( &hal_ll_hw_reg->fs1r, filter_number_pos ); + + hal_ll_hw_reg->filter_reg[filter_number_pos].fr1 = + ( hal_ll_can_filter_configure_16( filter_config->can_filter_id_low ) | + hal_ll_can_filter_configure_16( filter_config->can_filter_mask_id_low ) << HAL_LL_CAN_BYTE_OFFSET_2 ); + hal_ll_hw_reg->filter_reg[filter_number_pos].fr2 = + ( hal_ll_can_filter_configure_16( filter_config->can_filter_id_high ) | + hal_ll_can_filter_configure_16( filter_config->can_filter_mask_id_high ) << HAL_LL_CAN_BYTE_OFFSET_2 ); + + // Configure the frame type of filter/mask. + if ( HAL_LL_CAN_FRAME_TYPE_RTR == filter_config->can_filter_frame_type[0] ) + set_reg_bit( &hal_ll_hw_reg->filter_reg[filter_number_pos].fr1, HAL_LL_CAN_FIR_RTR_16_LOW_BIT ); + else + clear_reg_bit( &hal_ll_hw_reg->filter_reg[filter_number_pos].fr1, HAL_LL_CAN_FIR_RTR_16_LOW_BIT ); + + if ( HAL_LL_CAN_FRAME_TYPE_RTR == filter_config->can_filter_frame_type[1] ) + set_reg_bit( &hal_ll_hw_reg->filter_reg[filter_number_pos].fr1, HAL_LL_CAN_FIR_RTR_16_HIGH_BIT ); + else + clear_reg_bit( &hal_ll_hw_reg->filter_reg[filter_number_pos].fr1, HAL_LL_CAN_FIR_RTR_16_HIGH_BIT ); + + if ( HAL_LL_CAN_FRAME_TYPE_RTR == filter_config->can_filter_frame_type[2] ) + set_reg_bit( &hal_ll_hw_reg->filter_reg[filter_number_pos].fr2, HAL_LL_CAN_FIR_RTR_16_LOW_BIT ); + else + clear_reg_bit( &hal_ll_hw_reg->filter_reg[filter_number_pos].fr2, HAL_LL_CAN_FIR_RTR_16_LOW_BIT ); + + if ( HAL_LL_CAN_FRAME_TYPE_RTR == filter_config->can_filter_frame_type[3] ) + set_reg_bit( &hal_ll_hw_reg->filter_reg[filter_number_pos].fr2, HAL_LL_CAN_FIR_RTR_16_HIGH_BIT ); + else + clear_reg_bit( &hal_ll_hw_reg->filter_reg[filter_number_pos].fr2, HAL_LL_CAN_FIR_RTR_16_HIGH_BIT ); + + // Configure the format of filter/mask. + frame_format_id_mask[0] = hal_ll_can_filter_get_format_16( filter_config->can_filter_id_low ); + frame_format_id_mask[1] = hal_ll_can_filter_get_format_16( filter_config->can_filter_mask_id_low ); + frame_format_id_mask[2] = hal_ll_can_filter_get_format_16( filter_config->can_filter_id_high ); + frame_format_id_mask[3] = hal_ll_can_filter_get_format_16( filter_config->can_filter_mask_id_high ); + + if ( HAL_LL_CAN_FRAME_FORMAT_EXTENDED_29BITS == frame_format_id_mask[0] ) + set_reg_bit( &hal_ll_hw_reg->filter_reg[filter_number_pos].fr1, HAL_LL_CAN_FIR_EID_16_LOW_BIT ); + else + clear_reg_bit( &hal_ll_hw_reg->filter_reg[filter_number_pos].fr1, HAL_LL_CAN_FIR_EID_16_LOW_BIT ); + + if ( HAL_LL_CAN_FRAME_FORMAT_EXTENDED_29BITS == frame_format_id_mask[1] ) + set_reg_bit( &hal_ll_hw_reg->filter_reg[filter_number_pos].fr1, HAL_LL_CAN_FIR_EID_16_HIGH_BIT ); + else + clear_reg_bit( &hal_ll_hw_reg->filter_reg[filter_number_pos].fr1, HAL_LL_CAN_FIR_EID_16_HIGH_BIT ); + + if ( HAL_LL_CAN_FRAME_FORMAT_EXTENDED_29BITS == frame_format_id_mask[2] ) + set_reg_bit( &hal_ll_hw_reg->filter_reg[filter_number_pos].fr2, HAL_LL_CAN_FIR_EID_16_LOW_BIT ); + else + clear_reg_bit( &hal_ll_hw_reg->filter_reg[filter_number_pos].fr2, HAL_LL_CAN_FIR_EID_16_LOW_BIT ); + + if ( HAL_LL_CAN_FRAME_FORMAT_EXTENDED_29BITS == frame_format_id_mask[3] ) + set_reg_bit( &hal_ll_hw_reg->filter_reg[filter_number_pos].fr2, HAL_LL_CAN_FIR_EID_16_HIGH_BIT ); + else + clear_reg_bit( &hal_ll_hw_reg->filter_reg[filter_number_pos].fr2, HAL_LL_CAN_FIR_EID_16_HIGH_BIT ); + } + + if ( HAL_LL_CAN_FILTER_MODE_IDMASK == filter_config->can_filter_mode ) + // Set ID-Mask Mode for the filter. + clear_reg_bit( &hal_ll_hw_reg->fm1r, filter_number_pos ); + else + // Set ID-List Mode for the filter. + set_reg_bit( &hal_ll_hw_reg->fm1r, filter_number_pos ); + + if ( HAL_LL_CAN_FILTER_FIFO0 == filter_config->can_filter_fifo ) + // Map this filter to FIFO0. + clear_reg_bit( &hal_ll_hw_reg->ffa1r, filter_number_pos ); + else + // Map this filter to FIFO1. + set_reg_bit( &hal_ll_hw_reg->ffa1r, filter_number_pos ); + + if ( HAL_LL_CAN_FILTER_ENABLE == filter_config->can_filter_enable ) + // Enable this filter. + set_reg_bit( &hal_ll_hw_reg->fa1r, filter_number_pos ); + else + // Disable this filter. + clear_reg_bit( &hal_ll_hw_reg->fa1r, filter_number_pos ); + + // Leave the initialization mode. + clear_reg_bit( &hal_ll_hw_reg->fmr, HAL_LL_CAN_FMR_FINIT_BIT ); +} + +static hal_ll_err_t hal_ll_can_hw_init( hal_ll_can_hw_specifics_map_t *map, hal_ll_can_config_t *config, + hal_ll_can_filter_config_t *filter_config ) { + hal_ll_can_base_handle_t *hal_ll_hw_reg = hal_ll_can_get_base_struct( map->base ); + uint16_t timeout = HAL_LL_CAN_TIMEOUT_VALUE; + + // Enable clock for CAN. + hal_ll_can_clock_enable( map->module_index, true ); + + if ( HAL_LL_CAN_ERROR == hal_ll_can_module_init( map, config )) + return HAL_LL_CAN_ERROR; + + if ( HAL_LL_CAN_ERROR == hal_ll_can_filter_init( map, filter_config, true )) + return HAL_LL_CAN_ERROR; + + // Request the start of CAN. + clear_reg_bit( &hal_ll_hw_reg->mcr, HAL_LL_CAN_MCR_INRQ_BIT ); + // Wait until HW starts CAN. + while( check_reg_bit( &hal_ll_hw_reg->msr, HAL_LL_CAN_MSR_INAK_BIT )) { + if( 0 == timeout-- ) + return HAL_LL_CAN_ERROR; + } + + return HAL_LL_CAN_SUCCESS; +} +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/src/dma/CMakeLists.txt b/targets/arm/mikroe/ai_generated/stm32/src/dma/CMakeLists.txt new file mode 100644 index 000000000..d89f07cee --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/dma/CMakeLists.txt @@ -0,0 +1,72 @@ +## ./targets/arm/mikroe/ai_generated/stm32/src/dma/CMakeLists.txt + +## Check if current module is generated or not +set(MODULE_IS_GENERATED false) +get_files_recurse(${CMAKE_CURRENT_LIST_DIR}/implementations CMAKE_FILES cmake) +check_if_module_is_generated(MODULE_IS_GENERATED "${CMAKE_FILES}") + +## If current MCU has this module, add it +if(MODULE_IS_GENERATED) + set(hal_ll_def_list "") + set(mcu_header_path "") + + find_cortex(hal_ll_def_list) + list(APPEND hal_ll_def_list ${MCU_NAME}) + set(mcu_header_path ${MCU_NAME}_${_MSDK_PACKAGE_ID_}) + + ## BEGIN DMA + list(APPEND hal_ll_def_list "MACRO_USAGE_DMA") + + ## i.e "if (${MCU_NAME} MATCHES "^STM32C011F6$|^STM32C011C6$")" + ## List all MCUs and or them in the regex + foreach(cmakeFile ${CMAKE_FILES}) + include(${cmakeFile}) + endforeach() + ## END DMA + + mikrosdk_add_library(lib_hal_ll_dma MikroSDK.HalLowLevel.DMA + ${rcc_subimplementation}/hal_ll_rcc.h + ../../include/hal_ll_target.h + # BEGIN DMA + ${dma_subimplementation} + ../../include/dma/hal_ll_dma.h + # END DMA + ) + + target_compile_definitions(lib_hal_ll_dma PUBLIC + ${hal_ll_def_list} + ) + + target_link_libraries(lib_hal_ll_dma PUBLIC + MikroC.Core + MikroSDK.HalLowLevelCore + MikroSDK.HalLowLevelCommon + ) + + string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) + target_include_directories(lib_hal_ll_dma + PRIVATE + ../../include + ../../include/gpio + ${gpio_subimplementation_include_dir} + # BEGIN DMA + ../../include/dma + # END DMA + # BEGIN RCC + ${rcc_subimplementation} + # END RCC + INTERFACE + # BUILD + $ + $ + $ + $ + $ + # INSTALL + $ + $ + ) + + mikrosdk_install(MikroSDK.HalLowLevel.DMA) + install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.DMA ../../include/dma/hal_ll_dma.h) +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_1/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_1/CMakeLists.cmake new file mode 100644 index 000000000..ab18268bf --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_1/CMakeLists.cmake @@ -0,0 +1,8 @@ +if(${MCU_NAME} MATCHES "^STM32C011F4$|^STM32C011J4$|^STM32C011F6$|^STM32C011J6$|^STM32C011D6$") + set(dma_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_dma.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_1") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_1") + list(APPEND hal_ll_def_list "STM32C0xx") + list(APPEND hal_ll_def_list "STM32C01xx") + list(APPEND hal_ll_def_list "STM32C011xx") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_1/hal_ll_dma.c b/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_1/hal_ll_dma.c new file mode 100644 index 000000000..e3f91a06f --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_1/hal_ll_dma.c @@ -0,0 +1,640 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_dma.c + * @brief DMA HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_rcc.h" +#include "hal_ll_dma.h" +#include "hal_ll_gpio.h" + +// ------------------------------------------------------------- PRIVATE MACROS + +#define MODULE_SUPPORTED + +/*!< @brief DMA interrupt definitions. */ +#define HAL_LL_DMA_IT_FT ((uint32_t)(1U << 1)) +#define HAL_LL_DMA_IT_HT ((uint32_t)(1U << 2)) +#define HAL_LL_DMA_IT_ET ((uint32_t)(1U << 3)) +#define HAL_LL_DMA_IT_CLEAR_MASK (0x0fUL) + +#define HAL_LL_DMA_CCR_PRIORITY_VERY_HIGH_MASK (0x00003000) +#define HAL_LL_DMA_CCR_PRIORITY_HIGH_MASK (0x00002000) +#define HAL_LL_DMA_CCR_PRIORITY_MEDIUM_MASK (0x00001000) +#define HAL_LL_DMA_CCR_PRIORITY_LOW_MASK (0x00000000) +#define HAL_LL_DMA_CCR_CIRC_MASK (0x00000020) +#define HAL_LL_DMA_CCR_PSIZE_BYTE_MASK (0x00000000) +#define HAL_LL_DMA_CCR_PSIZE_HALFWORD_MASK (0x00000100) +#define HAL_LL_DMA_CCR_PSIZE_WORD_MASK (0x00000200) +#define HAL_LL_DMA_MSIZE_BYTE_MASK (0x00000000) +#define HAL_LL_DMA_MSIZE_HALFWORD_MASK (0x00000400) +#define HAL_LL_DMA_MSIZE_WORD_MASK (0x00000800) +#define HAL_LL_DMA_MINC_MASK (0x00000080) +#define HAL_LL_DMA_PINC_MASK (0x00000040) + +#define HAL_LL_DMA_DIRECTION_MEMORY_TO_MEMORY_MASK (0x4000) +#define HAL_LL_DMA_DIRECTION_MEMORY_TO_PERIPH_MASK (0x10) +#define HAL_LL_DMA_DIRECTION_PERIPH_TO_MEMORY_MASK (0x0) + +#define HAL_LL_DMA_CCR_PSIZE_MASK (0x00000300) +#define HAL_LL_DMA_CCR_MSIZE_MASK (0x00000C00) +#define HAL_LL_DMA_CCR_PRIO_MASK (0x00003000) +#define HAL_LL_DMA_CCR_EN_BIT (0) +#define HAL_LL_DMA_CCR_TEIE_BIT (3) +#define HAL_LL_DMA_CCR_HTIE_BIT (2) +#define HAL_LL_DMA_CCR_TCIE_BIT (1) +#define HAL_LL_DMA_CCR_DIR_BIT (4) +#define HAL_LL_DMA_CCR_CIRC_BIT (5) +#define HAL_LL_DMA_CCR_PINC_BIT (6) +#define HAL_LL_DMA_CCR_MINC_BIT (7) +#define HAL_LL_DMA_CCR_M2M_BIT (14) + +#ifdef MODULE_SUPPORTED + #define DMA1_BASE (0x40020000UL) + + #define HAL_LL_DMA1_CLOCK_BIT (0) + #define HAL_LL_DMA1_CLOCK_BASE ((uint32_t)_RCC_AHBENR) + #define HAL_LL_DMA1_STREAM_BASE (DMA1_BASE + CCR_BASE_OFFSET) + + #define CCR_BASE_OFFSET (0x8U) + #define STREAM_BASE_OFFSET (0x14U) + #define IFCR_BASE_OFFSET (0x4U) + #define HAL_LL_PWRCLK_BIT (28) + + /*diff bits/offsets:*/ + #define HAL_LL_PWRCLK_BASE (_RCC_APBENR1) + + #define DMAMUX1_BASE (0x40020800UL) + #define DMAMUX1_OFFSET (0x04U) + #define HAL_LL_DMAMUX1_CLOCK_BIT (2) +#endif + +/*!< @brief Clock enable macros. */ +#ifdef HAL_LL_PWRCLK_BASE +#define _HAL_LL_ENABLE_CLOCK_PWR_ ((HAL_LL_PWRCLK_BASE) ? (*HAL_LL_PWRCLK_BASE |= 1UL << HAL_LL_PWRCLK_BIT) : 0) +#endif + +/*!< @brief DMA module enable macro. */ +#define HAL_LL_DMA_MODULE_ENABLE(_x) (_x->cr |= 1U << HAL_LL_DMA_CCR_EN_BIT) + +/*!< @brief DMA module disable macro. */ +#define HAL_LL_DMA_MODULE_DISABLE(_x) (_x->cr &= ~(1U << HAL_LL_DMA_CCR_EN_BIT)) + +/*!< @brief Default timeout value to wait when checking if module is disabled/enabled. */ +#define DEFAULT_TIMEOUT_VALUE (0xFFFFU) + +// ----------------------------------------------------------- PRIVATE TYPEDEFS + +/*!< @brief DMA HW register structure. */ +typedef struct dma_handle +{ + volatile uint32_t cr; /*!< DMA channel x configuration register (DMA_CCRx) */ + volatile uint32_t ndtr; /*!< DMA channel x number of data to transfer register (DMA_CNDTRx) */ + volatile uint32_t par; /*!< DMA channel x peripheral address register (DMA_CPARx) */ + volatile uint32_t mar; /*!< DMA channel x memory address register (DMA_CMARx) */ +} dma_handle_t; + +typedef struct dmamux_registers +{ + volatile uint32_t dmamux_cr; /*!< DMA interrupt status register */ +} dmamux_registers_t; + +/*!< @brief DMA HW ISR register structure. */ +typedef struct dma_isr_registers +{ + volatile uint32_t isr; /*!< DMA interrupt status register (DMA_ISR) */ + volatile uint32_t ifcr; /*!< DMA interrupt flag clear register (DMA_IFCR) */ +} dma_isr_registers_t; + +/*!< @brief DMA HW clock settings structure. */ +typedef struct +{ + uint8_t clock_bit; + hal_ll_base_addr_t clock_base; +} dma_clock_t; + +/*!< @brief DMA control settings structure. */ +typedef struct +{ + dma_clock_t clock; + hal_ll_base_addr_t stream_base; +} dma_control_struct_t; + +// ------------------------------------------------------------------ VARIABLES + +static const dma_control_struct_t dma_controller[ DMA_NUM_OF_MODULES ] = +{ + { + { HAL_LL_DMA1_CLOCK_BIT, HAL_LL_DMA1_CLOCK_BASE }, HAL_LL_DMA1_STREAM_BASE + } +}; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS + +/** + * @brief Gets current stream address. + * @details Returns stream address based on @ref module value and + * desired @ref stream value. + * @param[in] module DMA module number. + * @param[in] stream DMA stream number. + * @return hal_ll_base_addr_t stream base register address. + */ +static hal_ll_base_addr_t hal_ll_dma_get_stream_address( uint8_t module, uint8_t stream ); + +/** + * @brief Sets current module clock. + * @details If @ref state is @b true, enables DMA module clock. + * If @ref state is @b false, disables DMA module clock. + * @param[in] dma_obj DMA object. + * @param[in] state Desired state. + * - @b true + * - @b false + * @return Nothing. + */ +static void hal_ll_dma_clock_set( hal_ll_dma_t *dma_obj, bool state ); + +/** + * @brief Initializes DMA module. + * @details Initializes DMA module, stream to + * values from @ref config structure. + * @param[in] dma_obj DMA object. + * @param[in] dma DMA HW handle. + * @param[in] config DMA configuration structure. + * @return hal_ll_err_t Returns initialization state, either success or fail. + */ +static hal_ll_err_t hal_ll_dma_init_hw( hal_ll_dma_t *dma_obj, dma_handle_t *dma, hal_ll_dma_config_t config ); + +/** + * @brief Gets DMA module state. + * @details Checks if current DMA module stream has been stopped. + * Waits for defined @ref DEFAULT_TIMEOUT_VALUE number of cycles + * before jumping out of loop and returning @ref HAL_LL_DMA_ERROR. + * @param[in] dma DMA HW handle. + * @return hal_ll_err_t Returns success or fail. + */ +static inline hal_ll_err_t hal_ll_dma_is_module_disabled( dma_handle_t *dma ); + +/** + * @brief Gets DMA channel. + * @details Returns appropriate value to be set in HW register + * for desired @ref channel. + * @param[in] channel DMA channel number. + * @return uint32_t Returns actual HW register value based on @ref channel. + */ +static inline uint32_t hal_ll_dma_get_reg_value_channel( uint8_t channel ); + +/** + * @brief Gets DMA direction. + * @details Returns appropriate value to be set in HW register + * for desired @ref direction. + * @param[in] direction DMA stream direction. + * Refer to @hal_ll_dma_direction_t for possible values. + * @return uint8_t Returns actual HW register value based on @ref direction. + */ +static inline uint16_t hal_ll_dma_get_reg_value_direction( hal_ll_dma_direction_t direction ); + +/** + * @brief Gets DMA peripheral address increment. + * @details Returns appropriate value to be set in HW register + * for desired @ref set_inc. + * @param[in] set_inc DMA channel peripheral address increment. + * Set to @b true in order to increment address. + * Set to @b false in order to keep address the same. + * @return uint16_t Returns actual HW register value based on @ref set_inc. + */ +static inline uint16_t hal_ll_dma_get_reg_value_dst_inc( bool set_inc ); + +/** + * @brief Gets DMA memory address increment. + * @details Returns appropriate value to be set in HW register + * for desired @ref set_inc. + * @param[in] set_inc DMA channel memory address increment. + * Set to @b true in order to increment address. + * Set to @b false in order to keep address the same. + * @return uint16_t Returns actual HW register value based on @ref set_inc. + */ +static inline uint16_t hal_ll_dma_get_reg_value_src_inc( bool set_inc ); + +/** + * @brief Gets DMA memory address alignment. + * @details Returns appropriate value to be set in HW register + * for desired @ref align. + * @param[in] align DMA channel memory address increment. + * Refer to @ref hal_ll_dma_data_align_t for possible values. + * @return uint16_t Returns actual HW register value based on @ref align. + */ +static inline uint16_t hal_ll_dma_get_reg_value_source_size( hal_ll_dma_data_align_t align ); + +/** + * @brief Gets DMA peripheral address alignment. + * @details Returns appropriate value to be set in HW register + * for desired @ref align. + * @param[in] align DMA channel peripheral address increment. + * Refer to @ref hal_ll_dma_data_align_t for possible values. + * @return uint16_t Returns actual HW register value based on @ref align. + */ +static inline uint16_t hal_ll_dma_get_reg_value_destination_size( hal_ll_dma_data_align_t align ); + +/** + * @brief Gets DMA mode value. + * @details Returns appropriate value to be set in HW register + * for desired @ref mode. + * @param[in] mode DMA mode for object channel. + * Refer to @ref hal_ll_dma_mode_t for possible values. + * @return uint16_t Returns actual HW register value based on @ref mode. + */ +static inline uint16_t hal_ll_dma_get_reg_value_mode( hal_ll_dma_mode_t mode ); + +/** + * @brief Gets DMA priority value. + * @details Returns appropriate value to be set in HW register + * for desired @ref priority. + * @param[in] priority DMA priority for object channel. + * Refer to @ref hal_ll_dma_priority_t for possible values. + * @return uint32_t Returns actual HW register value based on @ref priority. + */ +static inline uint32_t hal_ll_dma_get_reg_value_priority( hal_ll_dma_priority_t priority ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS + +hal_ll_err_t hal_ll_dma_init( hal_ll_dma_t *obj ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + + // Enable PWRCLK. + #ifdef HAL_LL_PWRCLK_BASE + _HAL_LL_ENABLE_CLOCK_PWR_; + #endif + + // Enable current stream clock. + hal_ll_dma_clock_set( obj, true ); + + // Initialize current stream. + obj->handle = hal_ll_dma_get_stream_address( obj->module, obj->stream ); + status = hal_ll_dma_init_hw( obj, + (dma_handle_t *)obj->handle, + obj->config ); + + if ( HAL_LL_DMA_SUCCESS != status ) { + obj->handle = 0; // If initialization failed, reset handle. + } + + return status; +} + +hal_ll_err_t hal_ll_dma_deinit( hal_ll_dma_t *obj ) { + // First abort current transfer. + if ( HAL_LL_DMA_SUCCESS != hal_ll_dma_transfer_abort( obj ) ) + return HAL_LL_DMA_ERROR; + // Finally, disable module clock. + hal_ll_dma_clock_set( obj, false ); + + return HAL_LL_DMA_SUCCESS; +} + +hal_ll_err_t hal_ll_dma_set_mode( hal_ll_dma_t *obj, hal_ll_dma_mode_t mode ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + // Get new mode. + hal_ll_dma_config_t cfg = obj->config; + cfg.mode = mode; + // Disable module first. + HAL_LL_DMA_MODULE_DISABLE( ((dma_handle_t *)obj->handle) ); + // Try to set new mode. + status = hal_ll_dma_init_hw( obj, + (dma_handle_t *)obj->handle, + cfg ); + + return status; +} + +hal_ll_err_t hal_ll_dma_set_direction( hal_ll_dma_t *obj, hal_ll_dma_direction_t direction ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + // Get new direction. + hal_ll_dma_config_t cfg = obj->config; + cfg.direction = direction; + // Disable module first. + HAL_LL_DMA_MODULE_DISABLE( ((dma_handle_t *)obj->handle) ); + // Try to set new value. + status = hal_ll_dma_init_hw( obj, + (dma_handle_t *)obj->handle, + cfg ); + + return status; +} + +hal_ll_err_t hal_ll_dma_set_priority( hal_ll_dma_t *obj, hal_ll_dma_priority_t priority ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + // Get new priority. + hal_ll_dma_config_t cfg = obj->config; + cfg.priority = priority; + // Disable module first. + HAL_LL_DMA_MODULE_DISABLE( ((dma_handle_t *)obj->handle) ); + // Try to set new value. + status = hal_ll_dma_init_hw( obj, + (dma_handle_t *)obj->handle, + cfg ); + + return status; +} + +hal_ll_err_t hal_ll_dma_set_parameters( hal_ll_dma_t *obj, uint32_t addr_src, uint32_t addr_dst, size_t transfer_size, hal_ll_dma_source_memory_region_t src_mem_type ) { + dma_handle_t *dma = (dma_handle_t *)obj->handle; + uint8_t ndtr_divisor; + + // This parameter is not relevant on this architecture. + (void)src_mem_type; + + // Configure DMA Stream data length. + switch ( obj->config.data_align_destination ) { + case HAL_LL_DMA_DATA_ALIGN_BYTES_1: + case HAL_LL_DMA_DATA_ALIGN_BYTES_2: + ndtr_divisor = obj->config.data_align_destination; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_4: + ndtr_divisor = 2; + break; + + default: + return HAL_LL_DMA_ERROR; + } + dma->ndtr = transfer_size >> ndtr_divisor; + + // Memory to Peripheral. + if ( HAL_LL_DMA_DIRECTION_MEMORY_TO_PERIPH == obj->config.direction ) { + // Configure DMA stream destination address. + dma->par = addr_dst; + // Configure DMA stream source address. + dma->mar = addr_src; + } else { // Peripheral to Memory. + // Configure DMA stream source address. + dma->par = addr_src; + // Configure DMA stream destination address. + dma->mar = addr_dst; + } + return HAL_LL_DMA_SUCCESS; +} + +hal_ll_err_t hal_ll_dma_transfer_start( hal_ll_dma_t *obj ) { + HAL_LL_DMA_MODULE_ENABLE( ((dma_handle_t *)obj->handle) ); + return HAL_LL_DMA_SUCCESS; +} + +hal_ll_err_t hal_ll_dma_transfer_stop( hal_ll_dma_t *obj ) { + dma_handle_t *dma = (dma_handle_t *)obj->handle; + uint16_t timeout = DEFAULT_TIMEOUT_VALUE; + + if ( HAL_LL_DMA_MODE_CIRCULAR == obj->config.mode ) + return HAL_LL_DMA_ERROR; + + while ( dma->ndtr ) { + if ( 0 == timeout-- ) + return HAL_LL_DMA_ERROR; + } + + HAL_LL_DMA_MODULE_DISABLE( dma ); + + return HAL_LL_DMA_SUCCESS; +} + +hal_ll_err_t hal_ll_dma_transfer_abort( hal_ll_dma_t *obj ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + dma_handle_t *dma = (dma_handle_t *)obj->handle; + + // Calculate DMA base and stream number. + dma_isr_registers_t *regs = (dma_isr_registers_t *)(dma_controller[obj->module].stream_base - CCR_BASE_OFFSET); + + // Disable all the transfer interrupts. + dma->cr &= ~(HAL_LL_DMA_CCR_TCIE_BIT | HAL_LL_DMA_CCR_HTIE_BIT | HAL_LL_DMA_CCR_TEIE_BIT); + + // Disable the stream. + HAL_LL_DMA_MODULE_DISABLE( dma ); + + // Wait for bit to be cleared. + status = hal_ll_dma_is_module_disabled( dma ); + + // Clear all interrupt flags at correct offset within the register. + if ( HAL_LL_DMA_SUCCESS == status ) + regs->ifcr = HAL_LL_DMA_IT_CLEAR_MASK << ( obj->stream * 4 ); + + return status; +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS + +static hal_ll_base_addr_t hal_ll_dma_get_stream_address( uint8_t module, uint8_t stream ) { + return ((hal_ll_base_addr_t)dma_controller[module].stream_base + (hal_ll_base_addr_t)(STREAM_BASE_OFFSET * (stream))); +} + +static void hal_ll_dma_clock_set( hal_ll_dma_t *obj, bool state ) { + if ( state ) { + set_reg_bit( (uint32_t *)dma_controller[obj->module].clock.clock_base, + dma_controller[obj->module].clock.clock_bit ); + set_reg_bit( (uint32_t *)dma_controller[obj->module].clock.clock_base, HAL_LL_DMAMUX1_CLOCK_BIT); + } else { + clear_reg_bit( (uint32_t *)dma_controller[obj->module].clock.clock_base, + dma_controller[obj->module].clock.clock_bit ); + } +} + +static hal_ll_err_t hal_ll_dma_init_hw( hal_ll_dma_t *obj, dma_handle_t *dma, hal_ll_dma_config_t config ) { + volatile uint32_t tmp = 0UL; + // Check if user entered invalid data aka HAL_LL_DMA_DATA_ALIGN_BYTES_3 + if (HAL_LL_DMA_DATA_ALIGN_BYTES_3 == config.data_align_source || HAL_LL_DMA_DATA_ALIGN_BYTES_3 == config.data_align_destination ) { + return HAL_LL_DMA_ERROR; + } + + // Disable the peripheral first. + HAL_LL_DMA_MODULE_DISABLE(dma); + + // Wait for bit to be cleared. + if ( HAL_LL_DMA_ERROR == hal_ll_dma_is_module_disabled( dma ) ) + return HAL_LL_DMA_ERROR; + + // Get the CR register value. + tmp = dma->cr; + + // Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits. + tmp &= ((uint32_t)~( HAL_LL_DMA_CCR_EN_BIT | HAL_LL_DMA_CCR_TCIE_BIT | HAL_LL_DMA_CCR_HTIE_BIT | \ + HAL_LL_DMA_CCR_TEIE_BIT | HAL_LL_DMA_CCR_DIR_BIT | HAL_LL_DMA_CCR_CIRC_BIT | \ + HAL_LL_DMA_CCR_PINC_BIT | HAL_LL_DMA_CCR_MINC_BIT | HAL_LL_DMA_CCR_M2M_BIT | \ + HAL_LL_DMA_CCR_PSIZE_MASK | HAL_LL_DMA_CCR_MSIZE_MASK | HAL_LL_DMA_CCR_PRIO_MASK )); + + // BEGIN Prepare the DMA stream configuration. + // Set desired direction value. + tmp |= hal_ll_dma_get_reg_value_direction(config.direction); + // Set desired memory increment settings. + tmp |= hal_ll_dma_get_reg_value_src_inc(config.src_inc); + tmp |= hal_ll_dma_get_reg_value_dst_inc(config.dst_inc); + // Set desired data size settings. + tmp |= hal_ll_dma_get_reg_value_source_size(config.data_align_source); + tmp |= hal_ll_dma_get_reg_value_destination_size(config.data_align_destination); + // Set desired mode. + tmp |= hal_ll_dma_get_reg_value_mode(config.mode); + // Finally, set desired priority. + tmp |= hal_ll_dma_get_reg_value_priority(config.priority); + + // And then write to DMA stream CR register. + dma->cr = tmp; + + if (obj->module == 0 ) { + dmamux_registers_t * dmamux = (dmamux_registers_t*)( DMAMUX1_BASE + ( obj->stream * DMAMUX1_OFFSET ) ); + dmamux->dmamux_cr |= obj->channel; + } else { + dmamux_registers_t * dmamux = (dmamux_registers_t*)( DMAMUX1_BASE + 0x20 + ( obj->stream * DMAMUX1_OFFSET ) ); + dmamux->dmamux_cr |= obj->channel; + } + + return HAL_LL_DMA_SUCCESS; +} + +static inline hal_ll_err_t hal_ll_dma_is_module_disabled( dma_handle_t *dma ) { + uint16_t timeout = DEFAULT_TIMEOUT_VALUE; + + while ( (dma->cr & (1U << HAL_LL_DMA_CCR_EN_BIT)) != 0 ) { + if ( 0 == timeout-- ) + return HAL_LL_DMA_ERROR; + } + + return HAL_LL_DMA_SUCCESS; +} + +static inline uint16_t hal_ll_dma_get_reg_value_direction( hal_ll_dma_direction_t direction ) { + volatile uint16_t direction_set = (uint8_t)HAL_LL_DMA_DIRECTION_MEMORY_TO_MEMORY; + + switch ( direction ) + { + case HAL_LL_DMA_DIRECTION_MEMORY_TO_MEMORY: + direction_set = HAL_LL_DMA_DIRECTION_MEMORY_TO_MEMORY_MASK; + break; + case HAL_LL_DMA_DIRECTION_MEMORY_TO_PERIPH: + direction_set = HAL_LL_DMA_DIRECTION_MEMORY_TO_PERIPH_MASK; + break; + case HAL_LL_DMA_DIRECTION_PERIPH_TO_MEMORY: + direction_set = HAL_LL_DMA_DIRECTION_PERIPH_TO_MEMORY_MASK; + break; + + default: + break; + } + + return (uint16_t)direction_set; +} + +static inline uint16_t hal_ll_dma_get_reg_value_dst_inc( bool set_inc ) { + return (uint16_t)((set_inc) ? (HAL_LL_DMA_PINC_MASK) : (0)); +} + +static inline uint16_t hal_ll_dma_get_reg_value_src_inc( bool set_inc ) { + return (uint16_t)((set_inc) ? (HAL_LL_DMA_MINC_MASK) : (0)); +} + +static inline uint16_t hal_ll_dma_get_reg_value_source_size( hal_ll_dma_data_align_t align ) { + volatile uint16_t align_set = (uint16_t)HAL_LL_DMA_DATA_ALIGN_BYTES_1; + + switch ( align ) + { + case HAL_LL_DMA_DATA_ALIGN_BYTES_1: + align_set = HAL_LL_DMA_MSIZE_BYTE_MASK; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_2: + align_set = HAL_LL_DMA_MSIZE_HALFWORD_MASK; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_4: + align_set = HAL_LL_DMA_MSIZE_WORD_MASK; + break; + + default: + break; + } + + return (uint16_t)align_set; +} + +static inline uint16_t hal_ll_dma_get_reg_value_destination_size( hal_ll_dma_data_align_t align ) { + volatile uint16_t align_set = (uint16_t)HAL_LL_DMA_DATA_ALIGN_BYTES_1; + + switch ( align ) + { + case HAL_LL_DMA_DATA_ALIGN_BYTES_1: + align_set = HAL_LL_DMA_CCR_PSIZE_BYTE_MASK; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_2: + align_set = HAL_LL_DMA_CCR_PSIZE_HALFWORD_MASK; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_4: + align_set = HAL_LL_DMA_CCR_PSIZE_WORD_MASK; + break; + + default: + break; + } + + return (uint16_t)align_set; +} + +static inline uint16_t hal_ll_dma_get_reg_value_mode( hal_ll_dma_mode_t mode ) { + return (uint16_t)((mode) ? (HAL_LL_DMA_CCR_CIRC_MASK) : (0)); +} + +static inline uint32_t hal_ll_dma_get_reg_value_priority( hal_ll_dma_priority_t priority ) { + volatile uint32_t priority_set = (uint32_t)HAL_LL_DMA_PRIORITY_LOW; + + switch ( priority ) + { + case HAL_LL_DMA_PRIORITY_LOW: + priority_set = HAL_LL_DMA_CCR_PRIORITY_LOW_MASK; + break; + case HAL_LL_DMA_PRIORITY_MEDIUM: + priority_set = HAL_LL_DMA_CCR_PRIORITY_MEDIUM_MASK; + break; + case HAL_LL_DMA_PRIORITY_HIGH: + priority_set = HAL_LL_DMA_CCR_PRIORITY_HIGH_MASK; + break; + case HAL_LL_DMA_PRIORITY_VERY_HIGH: + priority_set = HAL_LL_DMA_CCR_PRIORITY_VERY_HIGH_MASK; + break; + + default: + break; + } + + return (uint32_t)priority_set; +} + +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_160/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_160/CMakeLists.cmake new file mode 100644 index 000000000..844bbdcdd --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_160/CMakeLists.cmake @@ -0,0 +1,8 @@ +if(${MCU_NAME} MATCHES "^STM32L4P5AE$|^STM32L4P5AG$|^STM32L4P5CE$|^STM32L4P5CG$|^STM32L4P5QE$|^STM32L4P5QG$|^STM32L4P5RE$|^STM32L4P5RG$|^STM32L4P5VE$|^STM32L4P5VG$|^STM32L4P5ZE$|^STM32L4P5ZG$") + set(dma_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_dma.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_160") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_160") + list(APPEND hal_ll_def_list "STM32L4xx") + list(APPEND hal_ll_def_list "STM32L4Pxx") + list(APPEND hal_ll_def_list "STM32L4P5xx") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_160/hal_ll_dma.c b/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_160/hal_ll_dma.c new file mode 100644 index 000000000..66ae43f66 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_160/hal_ll_dma.c @@ -0,0 +1,645 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_dma.c + * @brief DMA HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_rcc.h" +#include "hal_ll_dma.h" +#include "hal_ll_gpio.h" + +// ------------------------------------------------------------- PRIVATE MACROS + +/*!< @brief DMA interrupt definitions. */ +#define HAL_LL_DMA_IT_FT ((uint32_t)(1U << 1)) +#define HAL_LL_DMA_IT_HT ((uint32_t)(1U << 2)) +#define HAL_LL_DMA_IT_ET ((uint32_t)(1U << 3)) +#define HAL_LL_DMA_IT_CLEAR_MASK (0x0fUL) + +#define HAL_LL_DMA_CCR_PRIORITY_VERY_HIGH_MASK (0x00003000) +#define HAL_LL_DMA_CCR_PRIORITY_HIGH_MASK (0x00002000) +#define HAL_LL_DMA_CCR_PRIORITY_MEDIUM_MASK (0x00001000) +#define HAL_LL_DMA_CCR_PRIORITY_LOW_MASK (0x00000000) +#define HAL_LL_DMA_CCR_CIRC_MASK (0x00000020) +#define HAL_LL_DMA_CCR_PSIZE_BYTE_MASK (0x00000000) +#define HAL_LL_DMA_CCR_PSIZE_HALFWORD_MASK (0x00000100) +#define HAL_LL_DMA_CCR_PSIZE_WORD_MASK (0x00000200) +#define HAL_LL_DMA_MSIZE_BYTE_MASK (0x00000000) +#define HAL_LL_DMA_MSIZE_HALFWORD_MASK (0x00000400) +#define HAL_LL_DMA_MSIZE_WORD_MASK (0x00000800) +#define HAL_LL_DMA_MINC_MASK (0x00000080) +#define HAL_LL_DMA_PINC_MASK (0x00000040) + +#define HAL_LL_DMA_DIRECTION_MEMORY_TO_MEMORY_MASK (0x4000) +#define HAL_LL_DMA_DIRECTION_MEMORY_TO_PERIPH_MASK (0x10) +#define HAL_LL_DMA_DIRECTION_PERIPH_TO_MEMORY_MASK (0x0) + +#define HAL_LL_DMA_CCR_PSIZE_MASK (0x00000300) +#define HAL_LL_DMA_CCR_MSIZE_MASK (0x00000C00) +#define HAL_LL_DMA_CCR_PRIO_MASK (0x00003000) +#define HAL_LL_DMA_CCR_EN_BIT (0) +#define HAL_LL_DMA_CCR_TEIE_BIT (3) +#define HAL_LL_DMA_CCR_HTIE_BIT (2) +#define HAL_LL_DMA_CCR_TCIE_BIT (1) +#define HAL_LL_DMA_CCR_DIR_BIT (4) +#define HAL_LL_DMA_CCR_CIRC_BIT (5) +#define HAL_LL_DMA_CCR_PINC_BIT (6) +#define HAL_LL_DMA_CCR_MINC_BIT (7) +#define HAL_LL_DMA_CCR_M2M_BIT (14) + +#define DMA1_BASE (0x40020000UL) +#define DMA2_BASE (0x40020400UL) + +#define HAL_LL_DMA1_CLOCK_BIT (0) +#define HAL_LL_DMA1_CLOCK_BASE ((uint32_t)_RCC_AHB1ENR) +#define HAL_LL_DMA1_STREAM_BASE (DMA1_BASE + CCR_BASE_OFFSET) +#define HAL_LL_DMA2_CLOCK_BIT (1) +#define HAL_LL_DMA2_CLOCK_BASE ((uint32_t)_RCC_AHB1ENR) +#define HAL_LL_DMA2_STREAM_BASE (DMA2_BASE + CCR_BASE_OFFSET) + +#define CCR_BASE_OFFSET (0x8U) +#define STREAM_BASE_OFFSET (0x14U) +#define IFCR_BASE_OFFSET (0x4U) +#define HAL_LL_PWRCLK_BIT (28) + +/*diff bits/offsets:*/ +#define HAL_LL_PWRCLK_BASE (_RCC_APB1ENR1) + +#define DMAMUX1_BASE (0x40020800UL) +#define DMAMUX1_OFFSET (0x04U) +#define HAL_LL_DMAMUX1_CLOCK_BIT (2) + +/*!< @brief Clock enable macros. */ +#ifdef HAL_LL_PWRCLK_BASE +#define _HAL_LL_ENABLE_CLOCK_PWR_ ((HAL_LL_PWRCLK_BASE) ? (*HAL_LL_PWRCLK_BASE |= 1UL << HAL_LL_PWRCLK_BIT) : 0) +#endif + +/*!< @brief DMA module enable macro. */ +#define HAL_LL_DMA_MODULE_ENABLE(_x) (_x->cr |= 1U << HAL_LL_DMA_CCR_EN_BIT) + +/*!< @brief DMA module disable macro. */ +#define HAL_LL_DMA_MODULE_DISABLE(_x) (_x->cr &= ~(1U << HAL_LL_DMA_CCR_EN_BIT)) + +/*!< @brief Default timeout value to wait when checking if module is disabled/enabled. */ +#define DEFAULT_TIMEOUT_VALUE (0xFFFFU) + +// ----------------------------------------------------------- PRIVATE TYPEDEFS + +/*!< @brief DMA HW register structure. */ +typedef struct dma_handle +{ + volatile uint32_t cr; /*!< DMA channel x configuration register (DMA_CCRx) */ + volatile uint32_t ndtr; /*!< DMA channel x number of data to transfer register (DMA_CNDTRx) */ + volatile uint32_t par; /*!< DMA channel x peripheral address register (DMA_CPARx) */ + volatile uint32_t mar; /*!< DMA channel x memory address register (DMA_CMARx) */ +} dma_handle_t; +typedef struct dmamux_registers +{ + volatile uint32_t dmamux_cr; /*!< DMA interrupt status register */ +} dmamux_registers_t; + +/*!< @brief DMA HW ISR register structure. */ +typedef struct dma_isr_registers +{ + volatile uint32_t isr; /*!< DMA interrupt status register (DMA_ISR) */ + volatile uint32_t ifcr; /*!< DMA interrupt flag clear register (DMA_IFCR) */ + + /*volatile uint32_t isr; /*!< DMA interrupt status register */ + /*volatile uint32_t ifcr; /*!< DMA interrupt flag clear register */ +} dma_isr_registers_t; + +/*!< @brief DMA HW clock settings structure. */ +typedef struct +{ + uint8_t clock_bit; + hal_ll_base_addr_t clock_base; +} dma_clock_t; + +/*!< @brief DMA control settings structure. */ +typedef struct +{ + dma_clock_t clock; + hal_ll_base_addr_t stream_base; +} dma_control_struct_t; + +// ------------------------------------------------------------------ VARIABLES + +static const dma_control_struct_t dma_controller[ DMA_NUM_OF_MODULES ] = +{ + { + { HAL_LL_DMA1_CLOCK_BIT, HAL_LL_DMA1_CLOCK_BASE }, HAL_LL_DMA1_STREAM_BASE + } + ,{ + { HAL_LL_DMA2_CLOCK_BIT, HAL_LL_DMA2_CLOCK_BASE }, HAL_LL_DMA2_STREAM_BASE + } +}; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS + +/** + * @brief Gets current stream address. + * @details Returns stream address based on @ref module value and + * desired @ref stream value. + * @param[in] module DMA module number. + * @param[in] stream DMA stream number. + * @return hal_ll_base_addr_t stream base register address. + */ +static hal_ll_base_addr_t hal_ll_dma_get_stream_address( uint8_t module, uint8_t stream ); + +/** + * @brief Sets current module clock. + * @details If @ref state is @b true, enables DMA module clock. + * If @ref state is @b false, disables DMA module clock. + * @param[in] dma_obj DMA object. + * @param[in] state Desired state. + * - @b true + * - @b false + * @return Nothing. + */ +static void hal_ll_dma_clock_set( hal_ll_dma_t *dma_obj, bool state ); + +/** + * @brief Initializes DMA module. + * @details Initializes DMA module, stream to + * values from @ref config structure. + * @param[in] dma_obj DMA object. + * @param[in] dma DMA HW handle. + * @param[in] config DMA configuration structure. + * @return hal_ll_err_t Returns initialization state, either success or fail. + */ +static hal_ll_err_t hal_ll_dma_init_hw( hal_ll_dma_t *dma_obj, dma_handle_t *dma, hal_ll_dma_config_t config ); + +/** + * @brief Gets DMA module state. + * @details Checks if current DMA module stream has been stopped. + * Waits for defined @ref DEFAULT_TIMEOUT_VALUE number of cycles + * before jumping out of loop and returning @ref HAL_LL_DMA_ERROR. + * @param[in] dma DMA HW handle. + * @return hal_ll_err_t Returns success or fail. + */ +static inline hal_ll_err_t hal_ll_dma_is_module_disabled( dma_handle_t *dma ); + +/** + * @brief Gets DMA channel. + * @details Returns appropriate value to be set in HW register + * for desired @ref channel. + * @param[in] channel DMA channel number. + * @return uint32_t Returns actual HW register value based on @ref channel. + */ +static inline uint32_t hal_ll_dma_get_reg_value_channel( uint8_t channel ); + +/** + * @brief Gets DMA direction. + * @details Returns appropriate value to be set in HW register + * for desired @ref direction. + * @param[in] direction DMA stream direction. + * Refer to @hal_ll_dma_direction_t for possible values. + * @return uint8_t Returns actual HW register value based on @ref direction. + */ +static inline uint16_t hal_ll_dma_get_reg_value_direction( hal_ll_dma_direction_t direction ); + +/** + * @brief Gets DMA peripheral address increment. + * @details Returns appropriate value to be set in HW register + * for desired @ref set_inc. + * @param[in] set_inc DMA channel peripheral address increment. + * Set to @b true in order to increment address. + * Set to @b false in order to keep address the same. + * @return uint16_t Returns actual HW register value based on @ref set_inc. + */ +static inline uint16_t hal_ll_dma_get_reg_value_dst_inc( bool set_inc ); + +/** + * @brief Gets DMA memory address increment. + * @details Returns appropriate value to be set in HW register + * for desired @ref set_inc. + * @param[in] set_inc DMA channel memory address increment. + * Set to @b true in order to increment address. + * Set to @b false in order to keep address the same. + * @return uint16_t Returns actual HW register value based on @ref set_inc. + */ +static inline uint16_t hal_ll_dma_get_reg_value_src_inc( bool set_inc ); + +/** + * @brief Gets DMA memory address alignment. + * @details Returns appropriate value to be set in HW register + * for desired @ref align. + * @param[in] align DMA channel memory address increment. + * Refer to @ref hal_ll_dma_data_align_t for possible values. + * @return uint16_t Returns actual HW register value based on @ref align. + */ +static inline uint16_t hal_ll_dma_get_reg_value_source_size( hal_ll_dma_data_align_t align ); + +/** + * @brief Gets DMA peripheral address alignment. + * @details Returns appropriate value to be set in HW register + * for desired @ref align. + * @param[in] align DMA channel peripheral address increment. + * Refer to @ref hal_ll_dma_data_align_t for possible values. + * @return uint16_t Returns actual HW register value based on @ref align. + */ +static inline uint16_t hal_ll_dma_get_reg_value_destination_size( hal_ll_dma_data_align_t align ); + +/** + * @brief Gets DMA mode value. + * @details Returns appropriate value to be set in HW register + * for desired @ref mode. + * @param[in] mode DMA mode for object channel. + * Refer to @ref hal_ll_dma_mode_t for possible values. + * @return uint16_t Returns actual HW register value based on @ref mode. + */ +static inline uint16_t hal_ll_dma_get_reg_value_mode( hal_ll_dma_mode_t mode ); + +/** + * @brief Gets DMA priority value. + * @details Returns appropriate value to be set in HW register + * for desired @ref priority. + * @param[in] priority DMA priority for object channel. + * Refer to @ref hal_ll_dma_priority_t for possible values. + * @return uint32_t Returns actual HW register value based on @ref priority. + */ +static inline uint32_t hal_ll_dma_get_reg_value_priority( hal_ll_dma_priority_t priority ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS + +hal_ll_err_t hal_ll_dma_init( hal_ll_dma_t *obj ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + + // Enable PWRCLK. + #ifdef HAL_LL_PWRCLK_BASE + _HAL_LL_ENABLE_CLOCK_PWR_; + #endif + + // Enable current stream clock. + hal_ll_dma_clock_set( obj, true ); + + // Initialize current stream. + obj->handle = hal_ll_dma_get_stream_address( obj->module, obj->stream ); + status = hal_ll_dma_init_hw( obj, + (dma_handle_t *)obj->handle, + obj->config ); + + if ( HAL_LL_DMA_SUCCESS != status ) { + obj->handle = 0; // If initialization failed, reset handle. + } + + return status; +} + +hal_ll_err_t hal_ll_dma_deinit( hal_ll_dma_t *obj ) { + // First abort current transfer. + if ( HAL_LL_DMA_SUCCESS != hal_ll_dma_transfer_abort( obj ) ) + return HAL_LL_DMA_ERROR; + // Finally, disable module clock. + hal_ll_dma_clock_set( obj, false ); + + return HAL_LL_DMA_SUCCESS; +} + +hal_ll_err_t hal_ll_dma_set_mode( hal_ll_dma_t *obj, hal_ll_dma_mode_t mode ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + // Get new mode. + hal_ll_dma_config_t cfg = obj->config; + cfg.mode = mode; + // Disable module first. + HAL_LL_DMA_MODULE_DISABLE( ((dma_handle_t *)obj->handle) ); + // Try to set new mode. + status = hal_ll_dma_init_hw( obj, + (dma_handle_t *)obj->handle, + cfg ); + + return status; +} + +hal_ll_err_t hal_ll_dma_set_direction( hal_ll_dma_t *obj, hal_ll_dma_direction_t direction ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + // Get new direction. + hal_ll_dma_config_t cfg = obj->config; + cfg.direction = direction; + // Disable module first. + HAL_LL_DMA_MODULE_DISABLE( ((dma_handle_t *)obj->handle) ); + // Try to set new value. + status = hal_ll_dma_init_hw( obj, + (dma_handle_t *)obj->handle, + cfg ); + + return status; +} + +hal_ll_err_t hal_ll_dma_set_priority( hal_ll_dma_t *obj, hal_ll_dma_priority_t priority ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + // Get new priority. + hal_ll_dma_config_t cfg = obj->config; + cfg.priority = priority; + // Disable module first. + HAL_LL_DMA_MODULE_DISABLE( ((dma_handle_t *)obj->handle) ); + // Try to set new value. + status = hal_ll_dma_init_hw( obj, + (dma_handle_t *)obj->handle, + cfg ); + + return status; +} + +hal_ll_err_t hal_ll_dma_set_parameters( hal_ll_dma_t *obj, uint32_t addr_src, uint32_t addr_dst, size_t transfer_size, hal_ll_dma_source_memory_region_t src_mem_type ) { + dma_handle_t *dma = (dma_handle_t *)obj->handle; + uint8_t ndtr_divisor; + + // This parameter is not relevant on this architecture. + (void)src_mem_type; + + // Configure DMA Stream data length. + switch ( obj->config.data_align_destination ) { + case HAL_LL_DMA_DATA_ALIGN_BYTES_1: + case HAL_LL_DMA_DATA_ALIGN_BYTES_2: + ndtr_divisor = obj->config.data_align_destination; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_4: + ndtr_divisor = 2; + break; + + default: + return HAL_LL_DMA_ERROR; + } + dma->ndtr = transfer_size >> ndtr_divisor; + + // Memory to Peripheral. + if ( HAL_LL_DMA_DIRECTION_MEMORY_TO_PERIPH == obj->config.direction ) { + // Configure DMA stream destination address. + dma->par = addr_dst; + // Configure DMA stream source address. + dma->mar = addr_src; + } else { // Peripheral to Memory. + // Configure DMA stream source address. + dma->par = addr_src; + // Configure DMA stream destination address. + dma->mar = addr_dst; + } + return HAL_LL_DMA_SUCCESS; +} + +hal_ll_err_t hal_ll_dma_transfer_start( hal_ll_dma_t *obj ) { + HAL_LL_DMA_MODULE_ENABLE( ((dma_handle_t *)obj->handle) ); + return HAL_LL_DMA_SUCCESS; +} + +hal_ll_err_t hal_ll_dma_transfer_stop( hal_ll_dma_t *obj ) { + dma_handle_t *dma = (dma_handle_t *)obj->handle; + uint16_t timeout = DEFAULT_TIMEOUT_VALUE; + + if ( HAL_LL_DMA_MODE_CIRCULAR == obj->config.mode ) + return HAL_LL_DMA_ERROR; + + while ( dma->ndtr ) { + if ( 0 == timeout-- ) + return HAL_LL_DMA_ERROR; + } + + HAL_LL_DMA_MODULE_DISABLE( dma ); + + return HAL_LL_DMA_SUCCESS; +} + +hal_ll_err_t hal_ll_dma_transfer_abort( hal_ll_dma_t *obj ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + dma_handle_t *dma = (dma_handle_t *)obj->handle; + + // Calculate DMA base and stream number. + dma_isr_registers_t *regs = (dma_isr_registers_t *)(dma_controller[obj->module].stream_base - CCR_BASE_OFFSET); + + // Disable all the transfer interrupts. + dma->cr &= ~(HAL_LL_DMA_CCR_TCIE_BIT | HAL_LL_DMA_CCR_HTIE_BIT | HAL_LL_DMA_CCR_TEIE_BIT); + + // Disable the stream. + HAL_LL_DMA_MODULE_DISABLE( dma ); + + // Wait for bit to be cleared. + status = hal_ll_dma_is_module_disabled( dma ); + + // Clear all interrupt flags at correct offset within the register. + if ( HAL_LL_DMA_SUCCESS == status ) + regs->ifcr = HAL_LL_DMA_IT_CLEAR_MASK << ( obj->stream * 4 ); + + return status; +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS + +static hal_ll_base_addr_t hal_ll_dma_get_stream_address( uint8_t module, uint8_t stream ) { + return ((hal_ll_base_addr_t)dma_controller[module].stream_base + (hal_ll_base_addr_t)(STREAM_BASE_OFFSET * (stream))); +} + +static void hal_ll_dma_clock_set( hal_ll_dma_t *obj, bool state ) { + if ( state ) { + set_reg_bit( (uint32_t *)dma_controller[obj->module].clock.clock_base, + dma_controller[obj->module].clock.clock_bit ); + set_reg_bit( (uint32_t *)dma_controller[obj->module].clock.clock_base, HAL_LL_DMAMUX1_CLOCK_BIT); + } else { + clear_reg_bit( (uint32_t *)dma_controller[obj->module].clock.clock_base, + dma_controller[obj->module].clock.clock_bit ); + } +} + +static hal_ll_err_t hal_ll_dma_init_hw( hal_ll_dma_t *obj, dma_handle_t *dma, hal_ll_dma_config_t config ) { + volatile uint32_t tmp = 0UL; + // Check if user entered invalid data aka HAL_LL_DMA_DATA_ALIGN_BYTES_3 + if (HAL_LL_DMA_DATA_ALIGN_BYTES_3 == config.data_align_source || HAL_LL_DMA_DATA_ALIGN_BYTES_3 == config.data_align_destination ) { + return HAL_LL_DMA_ERROR; + } + + // Disable the peripheral first. + HAL_LL_DMA_MODULE_DISABLE(dma); + + // Wait for bit to be cleared. + if ( HAL_LL_DMA_ERROR == hal_ll_dma_is_module_disabled( dma ) ) + return HAL_LL_DMA_ERROR; + + // Get the CR register value. + tmp = dma->cr; + + // Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits. + tmp &= ((uint32_t)~( HAL_LL_DMA_CCR_EN_BIT | HAL_LL_DMA_CCR_TCIE_BIT | HAL_LL_DMA_CCR_HTIE_BIT | \ + HAL_LL_DMA_CCR_TEIE_BIT | HAL_LL_DMA_CCR_DIR_BIT | HAL_LL_DMA_CCR_CIRC_BIT | \ + HAL_LL_DMA_CCR_PINC_BIT | HAL_LL_DMA_CCR_MINC_BIT | HAL_LL_DMA_CCR_M2M_BIT | \ + HAL_LL_DMA_CCR_PSIZE_MASK | HAL_LL_DMA_CCR_MSIZE_MASK | HAL_LL_DMA_CCR_PRIO_MASK )); + + // BEGIN Prepare the DMA stream configuration. + // Set desired direction value. + tmp |= hal_ll_dma_get_reg_value_direction(config.direction); + // Set desired memory increment settings. + tmp |= hal_ll_dma_get_reg_value_src_inc(config.src_inc); + tmp |= hal_ll_dma_get_reg_value_dst_inc(config.dst_inc); + // Set desired data size settings. + tmp |= hal_ll_dma_get_reg_value_source_size(config.data_align_source); + tmp |= hal_ll_dma_get_reg_value_destination_size(config.data_align_destination); + // Set desired mode. + tmp |= hal_ll_dma_get_reg_value_mode(config.mode); + // Finally, set desired priority. + tmp |= hal_ll_dma_get_reg_value_priority(config.priority); + + // And then write to DMA stream CR register. + dma->cr = tmp; + + if (obj->module == 0 ) { + dmamux_registers_t * dmamux = (dmamux_registers_t*)( DMAMUX1_BASE + ( obj->stream * DMAMUX1_OFFSET ) ); + dmamux->dmamux_cr |= obj->channel; + } else { + dmamux_registers_t * dmamux = (dmamux_registers_t*)( DMAMUX1_BASE + ( DMA_NUM_OF_STREAMS * DMAMUX1_OFFSET ) + ( obj->stream * DMAMUX1_OFFSET ) ); + dmamux->dmamux_cr |= obj->channel; + } + + return HAL_LL_DMA_SUCCESS; +} + +static inline hal_ll_err_t hal_ll_dma_is_module_disabled( dma_handle_t *dma ) { + uint16_t timeout = DEFAULT_TIMEOUT_VALUE; + + while ( (dma->cr & (1U << HAL_LL_DMA_CCR_EN_BIT)) != 0 ) { + if ( 0 == timeout-- ) + return HAL_LL_DMA_ERROR; + } + + return HAL_LL_DMA_SUCCESS; +} + +static inline uint16_t hal_ll_dma_get_reg_value_direction( hal_ll_dma_direction_t direction ) { + volatile uint16_t direction_set = (uint8_t)HAL_LL_DMA_DIRECTION_MEMORY_TO_MEMORY; + + switch ( direction ) + { + case HAL_LL_DMA_DIRECTION_MEMORY_TO_MEMORY: + direction_set = HAL_LL_DMA_DIRECTION_MEMORY_TO_MEMORY_MASK; + break; + case HAL_LL_DMA_DIRECTION_MEMORY_TO_PERIPH: + direction_set = HAL_LL_DMA_DIRECTION_MEMORY_TO_PERIPH_MASK; + break; + case HAL_LL_DMA_DIRECTION_PERIPH_TO_MEMORY: + direction_set = HAL_LL_DMA_DIRECTION_PERIPH_TO_MEMORY_MASK; + break; + + default: + break; + } + + return (uint16_t)direction_set; +} + +static inline uint16_t hal_ll_dma_get_reg_value_dst_inc( bool set_inc ) { + return (uint16_t)((set_inc) ? (HAL_LL_DMA_PINC_MASK) : (0)); +} + +static inline uint16_t hal_ll_dma_get_reg_value_src_inc( bool set_inc ) { + return (uint16_t)((set_inc) ? (HAL_LL_DMA_MINC_MASK) : (0)); +} + +static inline uint16_t hal_ll_dma_get_reg_value_source_size( hal_ll_dma_data_align_t align ) { + volatile uint16_t align_set = (uint16_t)HAL_LL_DMA_DATA_ALIGN_BYTES_1; + + switch ( align ) + { + case HAL_LL_DMA_DATA_ALIGN_BYTES_1: + align_set = HAL_LL_DMA_MSIZE_BYTE_MASK; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_2: + align_set = HAL_LL_DMA_MSIZE_HALFWORD_MASK; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_4: + align_set = HAL_LL_DMA_MSIZE_WORD_MASK; + break; + + default: + break; + } + + return (uint16_t)align_set; +} + +static inline uint16_t hal_ll_dma_get_reg_value_destination_size( hal_ll_dma_data_align_t align ) { + volatile uint16_t align_set = (uint16_t)HAL_LL_DMA_DATA_ALIGN_BYTES_1; + + switch ( align ) + { + case HAL_LL_DMA_DATA_ALIGN_BYTES_1: + align_set = HAL_LL_DMA_CCR_PSIZE_BYTE_MASK; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_2: + align_set = HAL_LL_DMA_CCR_PSIZE_HALFWORD_MASK; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_4: + align_set = HAL_LL_DMA_CCR_PSIZE_WORD_MASK; + break; + + default: + break; + } + + return (uint16_t)align_set; +} + +static inline uint16_t hal_ll_dma_get_reg_value_mode( hal_ll_dma_mode_t mode ) { + return (uint16_t)((mode) ? (HAL_LL_DMA_CCR_CIRC_MASK) : (0)); +} + +static inline uint32_t hal_ll_dma_get_reg_value_priority( hal_ll_dma_priority_t priority ) { + volatile uint32_t priority_set = (uint32_t)HAL_LL_DMA_PRIORITY_LOW; + + switch ( priority ) + { + case HAL_LL_DMA_PRIORITY_LOW: + priority_set = HAL_LL_DMA_CCR_PRIORITY_LOW_MASK; + break; + case HAL_LL_DMA_PRIORITY_MEDIUM: + priority_set = HAL_LL_DMA_CCR_PRIORITY_MEDIUM_MASK; + break; + case HAL_LL_DMA_PRIORITY_HIGH: + priority_set = HAL_LL_DMA_CCR_PRIORITY_HIGH_MASK; + break; + case HAL_LL_DMA_PRIORITY_VERY_HIGH: + priority_set = HAL_LL_DMA_CCR_PRIORITY_VERY_HIGH_MASK; + break; + + default: + break; + } + + return (uint32_t)priority_set; +} + +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_161/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_161/CMakeLists.cmake new file mode 100644 index 000000000..b81b8a1ba --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_161/CMakeLists.cmake @@ -0,0 +1,8 @@ +if(${MCU_NAME} MATCHES "^STM32L4Q5AG$|^STM32L4Q5CG$|^STM32L4Q5QG$|^STM32L4Q5RG$|^STM32L4Q5VG$|^STM32L4Q5ZG$") + set(dma_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_dma.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_161") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_161") + list(APPEND hal_ll_def_list "STM32L4xx") + list(APPEND hal_ll_def_list "STM32L4Qxx") + list(APPEND hal_ll_def_list "STM32L4Q5xx") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_161/hal_ll_dma.c b/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_161/hal_ll_dma.c new file mode 100644 index 000000000..2ed93bbdb --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_161/hal_ll_dma.c @@ -0,0 +1,661 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_dma.c + * @brief DMA HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_rcc.h" +#include "hal_ll_dma.h" +#include "hal_ll_gpio.h" + +// ------------------------------------------------------------- PRIVATE MACROS + + +/*!< @brief DMA interrupt definitions. */ +#define HAL_LL_DMA_IT_FT ((uint32_t)(1U << 1)) +#define HAL_LL_DMA_IT_HT ((uint32_t)(1U << 2)) +#define HAL_LL_DMA_IT_ET ((uint32_t)(1U << 3)) +#define HAL_LL_DMA_IT_CLEAR_MASK (0x0fUL) + +/*!< @brief DMA SCR register masks. */ + + + +#define HAL_LL_DMA_CCR_PRIORITY_VERY_HIGH_MASK (0x00003000) +#define HAL_LL_DMA_CCR_PRIORITY_HIGH_MASK (0x00002000) +#define HAL_LL_DMA_CCR_PRIORITY_MEDIUM_MASK (0x00001000) +#define HAL_LL_DMA_CCR_PRIORITY_LOW_MASK (0x00000000) +#define HAL_LL_DMA_CCR_CIRC_MASK (0x00000020) +#define HAL_LL_DMA_CCR_PSIZE_BYTE_MASK (0x00000000) +#define HAL_LL_DMA_CCR_PSIZE_HALFWORD_MASK (0x00000100) +#define HAL_LL_DMA_CCR_PSIZE_WORD_MASK (0x00000200) +#define HAL_LL_DMA_MSIZE_BYTE_MASK (0x00000000) +#define HAL_LL_DMA_MSIZE_HALFWORD_MASK (0x00000400) +#define HAL_LL_DMA_MSIZE_WORD_MASK (0x00000800) +#define HAL_LL_DMA_MINC_MASK (0x00000080) +#define HAL_LL_DMA_PINC_MASK (0x00000040) + +#define HAL_LL_DMA_DIRECTION_MEMORY_TO_MEMORY_MASK (0x4000) +#define HAL_LL_DMA_DIRECTION_MEMORY_TO_PERIPH_MASK (0x10) +#define HAL_LL_DMA_DIRECTION_PERIPH_TO_MEMORY_MASK (0x0) + +#define HAL_LL_DMA_CCR_PSIZE_MASK (0x00000300) +#define HAL_LL_DMA_CCR_MSIZE_MASK (0x00000C00) +#define HAL_LL_DMA_CCR_PRIO_MASK (0x00003000) +#define HAL_LL_DMA_CCR_EN_BIT (0) +#define HAL_LL_DMA_CCR_TEIE_BIT (3) +#define HAL_LL_DMA_CCR_HTIE_BIT (2) +#define HAL_LL_DMA_CCR_TCIE_BIT (1) +#define HAL_LL_DMA_CCR_DIR_BIT (4) +#define HAL_LL_DMA_CCR_CIRC_BIT (5) +#define HAL_LL_DMA_CCR_PINC_BIT (6) +#define HAL_LL_DMA_CCR_MINC_BIT (7) +#define HAL_LL_DMA_CCR_M2M_BIT (14) + + + +#define DMA1_BASE (0x40020000UL) +#define DMA2_BASE (0x40020400UL) + +#define HAL_LL_DMA1_CLOCK_BIT (0) +#define HAL_LL_DMA1_CLOCK_BASE ((uint32_t)_RCC_AHB1ENR) +#define HAL_LL_DMA1_STREAM_BASE (DMA1_BASE + CCR_BASE_OFFSET) +#define HAL_LL_DMA2_CLOCK_BIT (1) +#define HAL_LL_DMA2_CLOCK_BASE ((uint32_t)_RCC_AHB1ENR) +#define HAL_LL_DMA2_STREAM_BASE (DMA2_BASE + CCR_BASE_OFFSET) + +#define CCR_BASE_OFFSET (0x8U) +#define STREAM_BASE_OFFSET (0x14U) +#define IFCR_BASE_OFFSET (0x4U) +#define HAL_LL_PWRCLK_BIT (28) + +/*diff bits/offsets:*/ +#define HAL_LL_PWRCLK_BASE (_RCC_APB1ENR1) + +#define DMAMUX1_BASE (0x40020800UL) +#define DMAMUX1_OFFSET (0x04U) +#define HAL_LL_DMAMUX1_CLOCK_BIT (2) + + + + + +/*!< @brief Clock enable macros. */ +#ifdef HAL_LL_PWRCLK_BASE +#define _HAL_LL_ENABLE_CLOCK_PWR_ ((HAL_LL_PWRCLK_BASE) ? (*HAL_LL_PWRCLK_BASE |= 1UL << HAL_LL_PWRCLK_BIT) : 0) +#endif + +/*!< @brief DMA module enable macro. */ +#define HAL_LL_DMA_MODULE_ENABLE(_x) (_x->cr |= 1U << HAL_LL_DMA_CCR_EN_BIT) + +/*!< @brief DMA module disable macro. */ +#define HAL_LL_DMA_MODULE_DISABLE(_x) (_x->cr &= ~(1U << HAL_LL_DMA_CCR_EN_BIT)) + +/*!< @brief Default timeout value to wait when checking if module is disabled/enabled. */ +#define DEFAULT_TIMEOUT_VALUE (0xFFFFU) + +// ----------------------------------------------------------- PRIVATE TYPEDEFS + +/*!< @brief DMA HW register structure. */ +typedef struct dma_handle +{ + volatile uint32_t cr; /*!< DMA channel x configuration register (DMA_CCRx) */ + volatile uint32_t ndtr; /*!< DMA channel x number of data to transfer register (DMA_CNDTRx) */ + volatile uint32_t par; /*!< DMA channel x peripheral address register (DMA_CPARx) */ + volatile uint32_t mar; /*!< DMA channel x memory address register (DMA_CMARx) */ + +} dma_handle_t; + + +typedef struct dmamux_registers +{ + volatile uint32_t dmamux_cr; /*!< DMA interrupt status register */ + +} dmamux_registers_t; + +/*!< @brief DMA HW ISR register structure. */ +typedef struct dma_isr_registers +{ + volatile uint32_t isr; /*!< DMA interrupt status register (DMA_ISR) */ + volatile uint32_t ifcr; /*!< DMA interrupt flag clear register (DMA_IFCR) */ + +} dma_isr_registers_t; + +/*!< @brief DMA HW clock settings structure. */ +typedef struct +{ + uint8_t clock_bit; + hal_ll_base_addr_t clock_base; +} dma_clock_t; + +/*!< @brief DMA control settings structure. */ +typedef struct +{ + dma_clock_t clock; + hal_ll_base_addr_t stream_base; +} dma_control_struct_t; + +// ------------------------------------------------------------------ VARIABLES + +static const dma_control_struct_t dma_controller[ DMA_NUM_OF_MODULES ] = +{ + { + { HAL_LL_DMA1_CLOCK_BIT, HAL_LL_DMA1_CLOCK_BASE }, HAL_LL_DMA1_STREAM_BASE + } + ,{ + { HAL_LL_DMA2_CLOCK_BIT, HAL_LL_DMA2_CLOCK_BASE }, HAL_LL_DMA2_STREAM_BASE + } +}; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS + +/** + * @brief Gets current stream address. + * @details Returns stream address based on @ref module value and + * desired @ref stream value. + * @param[in] module DMA module number. + * @param[in] stream DMA stream number. + * @return hal_ll_base_addr_t stream base register address. + */ +static hal_ll_base_addr_t hal_ll_dma_get_stream_address( uint8_t module, uint8_t stream ); + +/** + * @brief Sets current module clock. + * @details If @ref state is @b true, enables DMA module clock. + * If @ref state is @b false, disables DMA module clock. + * @param[in] dma_obj DMA object. + * @param[in] state Desired state. + * - @b true + * - @b false + * @return Nothing. + */ +static void hal_ll_dma_clock_set( hal_ll_dma_t *dma_obj, bool state ); + +/** + * @brief Initializes DMA module. + * @details Initializes DMA module, stream to + * values from @ref config structure. + * @param[in] dma_obj DMA object. + * @param[in] dma DMA HW handle. + * @param[in] config DMA configuration structure. + * @return hal_ll_err_t Returns initialization state, either success or fail. + */ +static hal_ll_err_t hal_ll_dma_init_hw( hal_ll_dma_t *dma_obj, dma_handle_t *dma, hal_ll_dma_config_t config ); + +/** + * @brief Gets DMA module state. + * @details Checks if current DMA module stream has been stopped. + * Waits for defined @ref DEFAULT_TIMEOUT_VALUE number of cycles + * before jumping out of loop and returning @ref HAL_LL_DMA_ERROR. + * @param[in] dma DMA HW handle. + * @return hal_ll_err_t Returns success or fail. + */ +static inline hal_ll_err_t hal_ll_dma_is_module_disabled( dma_handle_t *dma ); + +/** + * @brief Gets DMA channel. + * @details Returns appropriate value to be set in HW register + * for desired @ref channel. + * @param[in] channel DMA channel number. + * @return uint32_t Returns actual HW register value based on @ref channel. + */ +static inline uint32_t hal_ll_dma_get_reg_value_channel( uint8_t channel ); + +/** + * @brief Gets DMA direction. + * @details Returns appropriate value to be set in HW register + * for desired @ref direction. + * @param[in] direction DMA stream direction. + * Refer to @hal_ll_dma_direction_t for possible values. + * @return uint8_t Returns actual HW register value based on @ref direction. + */ +static inline uint16_t hal_ll_dma_get_reg_value_direction( hal_ll_dma_direction_t direction ); + +/** + * @brief Gets DMA peripheral address increment. + * @details Returns appropriate value to be set in HW register + * for desired @ref set_inc. + * @param[in] set_inc DMA channel peripheral address increment. + * Set to @b true in order to increment address. + * Set to @b false in order to keep address the same. + * @return uint16_t Returns actual HW register value based on @ref set_inc. + */ +static inline uint16_t hal_ll_dma_get_reg_value_dst_inc( bool set_inc ); + +/** + * @brief Gets DMA memory address increment. + * @details Returns appropriate value to be set in HW register + * for desired @ref set_inc. + * @param[in] set_inc DMA channel memory address increment. + * Set to @b true in order to increment address. + * Set to @b false in order to keep address the same. + * @return uint16_t Returns actual HW register value based on @ref set_inc. + */ +static inline uint16_t hal_ll_dma_get_reg_value_src_inc( bool set_inc ); + +/** + * @brief Gets DMA memory address alignment. + * @details Returns appropriate value to be set in HW register + * for desired @ref align. + * @param[in] align DMA channel memory address increment. + * Refer to @ref hal_ll_dma_data_align_t for possible values. + * @return uint16_t Returns actual HW register value based on @ref align. + */ +static inline uint16_t hal_ll_dma_get_reg_value_source_size( hal_ll_dma_data_align_t align ); + +/** + * @brief Gets DMA peripheral address alignment. + * @details Returns appropriate value to be set in HW register + * for desired @ref align. + * @param[in] align DMA channel peripheral address increment. + * Refer to @ref hal_ll_dma_data_align_t for possible values. + * @return uint16_t Returns actual HW register value based on @ref align. + */ +static inline uint16_t hal_ll_dma_get_reg_value_destination_size( hal_ll_dma_data_align_t align ); + +/** + * @brief Gets DMA mode value. + * @details Returns appropriate value to be set in HW register + * for desired @ref mode. + * @param[in] mode DMA mode for object channel. + * Refer to @ref hal_ll_dma_mode_t for possible values. + * @return uint16_t Returns actual HW register value based on @ref mode. + */ +static inline uint16_t hal_ll_dma_get_reg_value_mode( hal_ll_dma_mode_t mode ); + +/** + * @brief Gets DMA priority value. + * @details Returns appropriate value to be set in HW register + * for desired @ref priority. + * @param[in] priority DMA priority for object channel. + * Refer to @ref hal_ll_dma_priority_t for possible values. + * @return uint32_t Returns actual HW register value based on @ref priority. + */ +static inline uint32_t hal_ll_dma_get_reg_value_priority( hal_ll_dma_priority_t priority ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS + +hal_ll_err_t hal_ll_dma_init( hal_ll_dma_t *obj ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + + // Enable PWRCLK. + #ifdef HAL_LL_PWRCLK_BASE + _HAL_LL_ENABLE_CLOCK_PWR_; + #endif + + // Enable current stream clock. + hal_ll_dma_clock_set( obj, true ); + + // Initialize current stream. + obj->handle = hal_ll_dma_get_stream_address( obj->module, obj->stream ); + status = hal_ll_dma_init_hw( obj, + (dma_handle_t *)obj->handle, + obj->config ); + + if ( HAL_LL_DMA_SUCCESS != status ) { + obj->handle = 0; // If initialization failed, reset handle. + } + + return status; +} + +hal_ll_err_t hal_ll_dma_deinit( hal_ll_dma_t *obj ) { + // First abort current transfer. + if ( HAL_LL_DMA_SUCCESS != hal_ll_dma_transfer_abort( obj ) ) + return HAL_LL_DMA_ERROR; + // Finally, disable module clock. + hal_ll_dma_clock_set( obj, false ); + + return HAL_LL_DMA_SUCCESS; +} + +hal_ll_err_t hal_ll_dma_set_mode( hal_ll_dma_t *obj, hal_ll_dma_mode_t mode ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + // Get new mode. + hal_ll_dma_config_t cfg = obj->config; + cfg.mode = mode; + // Disable module first. + HAL_LL_DMA_MODULE_DISABLE( ((dma_handle_t *)obj->handle) ); + // Try to set new mode. + status = hal_ll_dma_init_hw( obj, + (dma_handle_t *)obj->handle, + cfg ); + + return status; +} + +hal_ll_err_t hal_ll_dma_set_direction( hal_ll_dma_t *obj, hal_ll_dma_direction_t direction ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + // Get new direction. + hal_ll_dma_config_t cfg = obj->config; + cfg.direction = direction; + // Disable module first. + HAL_LL_DMA_MODULE_DISABLE( ((dma_handle_t *)obj->handle) ); + // Try to set new value. + status = hal_ll_dma_init_hw( obj, + (dma_handle_t *)obj->handle, + cfg ); + + return status; +} + +hal_ll_err_t hal_ll_dma_set_priority( hal_ll_dma_t *obj, hal_ll_dma_priority_t priority ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + // Get new priority. + hal_ll_dma_config_t cfg = obj->config; + cfg.priority = priority; + // Disable module first. + HAL_LL_DMA_MODULE_DISABLE( ((dma_handle_t *)obj->handle) ); + // Try to set new value. + status = hal_ll_dma_init_hw( obj, + (dma_handle_t *)obj->handle, + cfg ); + + return status; +} + +hal_ll_err_t hal_ll_dma_set_parameters( hal_ll_dma_t *obj, uint32_t addr_src, uint32_t addr_dst, size_t transfer_size, hal_ll_dma_source_memory_region_t src_mem_type ) { + dma_handle_t *dma = (dma_handle_t *)obj->handle; + uint8_t ndtr_divisor; + + // This parameter is not relevant on this architecture. + (void)src_mem_type; + + // Configure DMA Stream data length. + switch ( obj->config.data_align_destination ) { + case HAL_LL_DMA_DATA_ALIGN_BYTES_1: + case HAL_LL_DMA_DATA_ALIGN_BYTES_2: + ndtr_divisor = obj->config.data_align_destination; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_4: + ndtr_divisor = 2; + break; + + default: + return HAL_LL_DMA_ERROR; + } + dma->ndtr = transfer_size >> ndtr_divisor; + + // Memory to Peripheral. + if ( HAL_LL_DMA_DIRECTION_MEMORY_TO_PERIPH == obj->config.direction ) { + // Configure DMA stream destination address. + dma->par = addr_dst; + // Configure DMA stream source address. + dma->mar = addr_src; + } else { // Peripheral to Memory. + // Configure DMA stream source address. + dma->par = addr_src; + // Configure DMA stream destination address. + dma->mar = addr_dst; + } + return HAL_LL_DMA_SUCCESS; +} + +hal_ll_err_t hal_ll_dma_transfer_start( hal_ll_dma_t *obj ) { + HAL_LL_DMA_MODULE_ENABLE( ((dma_handle_t *)obj->handle) ); + return HAL_LL_DMA_SUCCESS; +} + +hal_ll_err_t hal_ll_dma_transfer_stop( hal_ll_dma_t *obj ) { + dma_handle_t *dma = (dma_handle_t *)obj->handle; + uint16_t timeout = DEFAULT_TIMEOUT_VALUE; + + if ( HAL_LL_DMA_MODE_CIRCULAR == obj->config.mode ) + return HAL_LL_DMA_ERROR; + + while ( dma->ndtr ) { + if ( 0 == timeout-- ) + return HAL_LL_DMA_ERROR; + } + + HAL_LL_DMA_MODULE_DISABLE( dma ); + + return HAL_LL_DMA_SUCCESS; +} + +hal_ll_err_t hal_ll_dma_transfer_abort( hal_ll_dma_t *obj ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + dma_handle_t *dma = (dma_handle_t *)obj->handle; + + // Calculate DMA base and stream number. + dma_isr_registers_t *regs = (dma_isr_registers_t *)(dma_controller[obj->module].stream_base - CCR_BASE_OFFSET); + + // Disable all the transfer interrupts. + dma->cr &= ~(HAL_LL_DMA_CCR_TCIE_BIT | HAL_LL_DMA_CCR_HTIE_BIT | HAL_LL_DMA_CCR_TEIE_BIT); + + // Disable the stream. + HAL_LL_DMA_MODULE_DISABLE( dma ); + + // Wait for bit to be cleared. + status = hal_ll_dma_is_module_disabled( dma ); + + // Clear all interrupt flags at correct offset within the register. + if ( HAL_LL_DMA_SUCCESS == status ) + regs->ifcr = HAL_LL_DMA_IT_CLEAR_MASK << ( obj->stream * 4 ); + + return status; +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS + +static hal_ll_base_addr_t hal_ll_dma_get_stream_address( uint8_t module, uint8_t stream ) { + return ((hal_ll_base_addr_t)dma_controller[module].stream_base + (hal_ll_base_addr_t)(STREAM_BASE_OFFSET * (stream))); +} + +static void hal_ll_dma_clock_set( hal_ll_dma_t *obj, bool state ) { + if ( state ) { + set_reg_bit( (uint32_t *)dma_controller[obj->module].clock.clock_base, + dma_controller[obj->module].clock.clock_bit ); + set_reg_bit( (uint32_t *)dma_controller[obj->module].clock.clock_base, HAL_LL_DMAMUX1_CLOCK_BIT); + } else { + clear_reg_bit( (uint32_t *)dma_controller[obj->module].clock.clock_base, + dma_controller[obj->module].clock.clock_bit ); + } +} + +static hal_ll_err_t hal_ll_dma_init_hw( hal_ll_dma_t *obj, dma_handle_t *dma, hal_ll_dma_config_t config ) { + volatile uint32_t tmp = 0UL; + // Check if user entered invalid data aka HAL_LL_DMA_DATA_ALIGN_BYTES_3 + if (HAL_LL_DMA_DATA_ALIGN_BYTES_3 == config.data_align_source || HAL_LL_DMA_DATA_ALIGN_BYTES_3 == config.data_align_destination ) { + return HAL_LL_DMA_ERROR; + } + + // Disable the peripheral first. + HAL_LL_DMA_MODULE_DISABLE(dma); + + // Wait for bit to be cleared. + if ( HAL_LL_DMA_ERROR == hal_ll_dma_is_module_disabled( dma ) ) + return HAL_LL_DMA_ERROR; + + // Get the CR register value. + tmp = dma->cr; + + // Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits. + tmp &= ((uint32_t)~( HAL_LL_DMA_CCR_EN_BIT | HAL_LL_DMA_CCR_TCIE_BIT | HAL_LL_DMA_CCR_HTIE_BIT | \ + HAL_LL_DMA_CCR_TEIE_BIT | HAL_LL_DMA_CCR_DIR_BIT | HAL_LL_DMA_CCR_CIRC_BIT | \ + HAL_LL_DMA_CCR_PINC_BIT | HAL_LL_DMA_CCR_MINC_BIT | HAL_LL_DMA_CCR_M2M_BIT | \ + HAL_LL_DMA_CCR_PSIZE_MASK | HAL_LL_DMA_CCR_MSIZE_MASK | HAL_LL_DMA_CCR_PRIO_MASK )); + + // BEGIN Prepare the DMA stream configuration. + // Set desired direction value. + tmp |= hal_ll_dma_get_reg_value_direction(config.direction); + // Set desired memory increment settings. + tmp |= hal_ll_dma_get_reg_value_src_inc(config.src_inc); + tmp |= hal_ll_dma_get_reg_value_dst_inc(config.dst_inc); + // Set desired data size settings. + tmp |= hal_ll_dma_get_reg_value_source_size(config.data_align_source); + tmp |= hal_ll_dma_get_reg_value_destination_size(config.data_align_destination); + // Set desired mode. + tmp |= hal_ll_dma_get_reg_value_mode(config.mode); + // Finally, set desired priority. + tmp |= hal_ll_dma_get_reg_value_priority(config.priority); + + // And then write to DMA stream CR register. + dma->cr = tmp; + + if (obj->module == 0 ) { + dmamux_registers_t * dmamux = (dmamux_registers_t*)( DMAMUX1_BASE + ( obj->stream * DMAMUX1_OFFSET ) ); + dmamux->dmamux_cr |= obj->channel; + } else { + dmamux_registers_t * dmamux = (dmamux_registers_t*)( DMAMUX1_BASE + ( DMA_NUM_OF_STREAMS * DMAMUX1_OFFSET ) + ( obj->stream * DMAMUX1_OFFSET ) ); + dmamux->dmamux_cr |= obj->channel; + } + + return HAL_LL_DMA_SUCCESS; +} + +static inline hal_ll_err_t hal_ll_dma_is_module_disabled( dma_handle_t *dma ) { + uint16_t timeout = DEFAULT_TIMEOUT_VALUE; + + while ( (dma->cr & (1U << HAL_LL_DMA_CCR_EN_BIT)) != 0 ) { + if ( 0 == timeout-- ) + return HAL_LL_DMA_ERROR; + } + + return HAL_LL_DMA_SUCCESS; +} + +static inline uint16_t hal_ll_dma_get_reg_value_direction( hal_ll_dma_direction_t direction ) { + volatile uint16_t direction_set = (uint8_t)HAL_LL_DMA_DIRECTION_MEMORY_TO_MEMORY; + + switch ( direction ) + { + case HAL_LL_DMA_DIRECTION_MEMORY_TO_MEMORY: + direction_set = HAL_LL_DMA_DIRECTION_MEMORY_TO_MEMORY_MASK; + break; + case HAL_LL_DMA_DIRECTION_MEMORY_TO_PERIPH: + direction_set = HAL_LL_DMA_DIRECTION_MEMORY_TO_PERIPH_MASK; + break; + case HAL_LL_DMA_DIRECTION_PERIPH_TO_MEMORY: + direction_set = HAL_LL_DMA_DIRECTION_PERIPH_TO_MEMORY_MASK; + break; + + default: + break; + } + + return (uint16_t)direction_set; +} + +static inline uint16_t hal_ll_dma_get_reg_value_dst_inc( bool set_inc ) { + return (uint16_t)((set_inc) ? (HAL_LL_DMA_PINC_MASK) : (0)); +} + +static inline uint16_t hal_ll_dma_get_reg_value_src_inc( bool set_inc ) { + return (uint16_t)((set_inc) ? (HAL_LL_DMA_MINC_MASK) : (0)); +} + +static inline uint16_t hal_ll_dma_get_reg_value_source_size( hal_ll_dma_data_align_t align ) { + volatile uint16_t align_set = (uint16_t)HAL_LL_DMA_DATA_ALIGN_BYTES_1; + + switch ( align ) + { + case HAL_LL_DMA_DATA_ALIGN_BYTES_1: + align_set = HAL_LL_DMA_MSIZE_BYTE_MASK; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_2: + align_set = HAL_LL_DMA_MSIZE_HALFWORD_MASK; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_4: + align_set = HAL_LL_DMA_MSIZE_WORD_MASK; + break; + + default: + break; + } + + return (uint16_t)align_set; +} + +static inline uint16_t hal_ll_dma_get_reg_value_destination_size( hal_ll_dma_data_align_t align ) { + volatile uint16_t align_set = (uint16_t)HAL_LL_DMA_DATA_ALIGN_BYTES_1; + + switch ( align ) + { + case HAL_LL_DMA_DATA_ALIGN_BYTES_1: + align_set = HAL_LL_DMA_CCR_PSIZE_BYTE_MASK; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_2: + align_set = HAL_LL_DMA_CCR_PSIZE_HALFWORD_MASK; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_4: + align_set = HAL_LL_DMA_CCR_PSIZE_WORD_MASK; + break; + + default: + break; + } + + return (uint16_t)align_set; +} + +static inline uint16_t hal_ll_dma_get_reg_value_mode( hal_ll_dma_mode_t mode ) { + return (uint16_t)((mode) ? (HAL_LL_DMA_CCR_CIRC_MASK) : (0)); +} + +static inline uint32_t hal_ll_dma_get_reg_value_priority( hal_ll_dma_priority_t priority ) { + volatile uint32_t priority_set = (uint32_t)HAL_LL_DMA_PRIORITY_LOW; + + switch ( priority ) + { + case HAL_LL_DMA_PRIORITY_LOW: + priority_set = HAL_LL_DMA_CCR_PRIORITY_LOW_MASK; + break; + case HAL_LL_DMA_PRIORITY_MEDIUM: + priority_set = HAL_LL_DMA_CCR_PRIORITY_MEDIUM_MASK; + break; + case HAL_LL_DMA_PRIORITY_HIGH: + priority_set = HAL_LL_DMA_CCR_PRIORITY_HIGH_MASK; + break; + case HAL_LL_DMA_PRIORITY_VERY_HIGH: + priority_set = HAL_LL_DMA_CCR_PRIORITY_VERY_HIGH_MASK; + break; + + default: + break; + } + + return (uint32_t)priority_set; +} + +// ------------------------------------------------------------------------- END + + + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_2/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_2/CMakeLists.cmake new file mode 100644 index 000000000..fc67f829e --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_2/CMakeLists.cmake @@ -0,0 +1,8 @@ +if(${MCU_NAME} MATCHES "^STM32C031C4$|^STM32C031F4$|^STM32C031G4$|^STM32C031K4$|^STM32C031C6$|^STM32C031F6$|^STM32C031G6$|^STM32C031K6$") + set(dma_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_dma.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_2") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_2") + list(APPEND hal_ll_def_list "STM32C0xx") + list(APPEND hal_ll_def_list "STM32C03xx") + list(APPEND hal_ll_def_list "STM32C031xx") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_2/hal_ll_dma.c b/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_2/hal_ll_dma.c new file mode 100644 index 000000000..c6f0fc1e6 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_2/hal_ll_dma.c @@ -0,0 +1,654 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_dma.c + * @brief DMA HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_rcc.h" +#include "hal_ll_dma.h" +#include "hal_ll_gpio.h" + +// ------------------------------------------------------------- PRIVATE MACROS + + +/*!< @brief DMA interrupt definitions. */ +#define HAL_LL_DMA_IT_FT ((uint32_t)(1U << 1)) +#define HAL_LL_DMA_IT_HT ((uint32_t)(1U << 2)) +#define HAL_LL_DMA_IT_ET ((uint32_t)(1U << 3)) +#define HAL_LL_DMA_IT_CLEAR_MASK (0x0fUL) + +/*!< @brief DMA SCR register masks. */ + + + +#define HAL_LL_DMA_CCR_PRIORITY_VERY_HIGH_MASK (0x00003000) +#define HAL_LL_DMA_CCR_PRIORITY_HIGH_MASK (0x00002000) +#define HAL_LL_DMA_CCR_PRIORITY_MEDIUM_MASK (0x00001000) +#define HAL_LL_DMA_CCR_PRIORITY_LOW_MASK (0x00000000) +#define HAL_LL_DMA_CCR_CIRC_MASK (0x00000020) +#define HAL_LL_DMA_CCR_PSIZE_BYTE_MASK (0x00000000) +#define HAL_LL_DMA_CCR_PSIZE_HALFWORD_MASK (0x00000100) +#define HAL_LL_DMA_CCR_PSIZE_WORD_MASK (0x00000200) +#define HAL_LL_DMA_MSIZE_BYTE_MASK (0x00000000) +#define HAL_LL_DMA_MSIZE_HALFWORD_MASK (0x00000400) +#define HAL_LL_DMA_MSIZE_WORD_MASK (0x00000800) +#define HAL_LL_DMA_MINC_MASK (0x00000080) +#define HAL_LL_DMA_PINC_MASK (0x00000040) + +#define HAL_LL_DMA_DIRECTION_MEMORY_TO_MEMORY_MASK (0x4000) +#define HAL_LL_DMA_DIRECTION_MEMORY_TO_PERIPH_MASK (0x10) +#define HAL_LL_DMA_DIRECTION_PERIPH_TO_MEMORY_MASK (0x0) + +#define HAL_LL_DMA_CCR_PSIZE_MASK (0x00000300) +#define HAL_LL_DMA_CCR_MSIZE_MASK (0x00000C00) +#define HAL_LL_DMA_CCR_PRIO_MASK (0x00003000) +#define HAL_LL_DMA_CCR_EN_BIT (0) +#define HAL_LL_DMA_CCR_TEIE_BIT (3) +#define HAL_LL_DMA_CCR_HTIE_BIT (2) +#define HAL_LL_DMA_CCR_TCIE_BIT (1) +#define HAL_LL_DMA_CCR_DIR_BIT (4) +#define HAL_LL_DMA_CCR_CIRC_BIT (5) +#define HAL_LL_DMA_CCR_PINC_BIT (6) +#define HAL_LL_DMA_CCR_MINC_BIT (7) +#define HAL_LL_DMA_CCR_M2M_BIT (14) + + + +#define DMA1_BASE (0x40020000UL) + +#define HAL_LL_DMA1_CLOCK_BIT (0) +#define HAL_LL_DMA1_CLOCK_BASE ((uint32_t)_RCC_AHBENR) +#define HAL_LL_DMA1_STREAM_BASE (DMA1_BASE + CCR_BASE_OFFSET) + +#define CCR_BASE_OFFSET (0x8U) +#define STREAM_BASE_OFFSET (0x14U) +#define IFCR_BASE_OFFSET (0x4U) +#define HAL_LL_PWRCLK_BIT (28) + +/*diff bits/offsets:*/ +#define HAL_LL_PWRCLK_BASE (_RCC_APBENR1) + +#define DMAMUX1_BASE (0x40020800UL) +#define DMAMUX1_OFFSET (0x04U) +#define HAL_LL_DMAMUX1_CLOCK_BIT (2) + + + + + +/*!< @brief Clock enable macros. */ +#ifdef HAL_LL_PWRCLK_BASE +#define _HAL_LL_ENABLE_CLOCK_PWR_ ((HAL_LL_PWRCLK_BASE) ? (*HAL_LL_PWRCLK_BASE |= 1UL << HAL_LL_PWRCLK_BIT) : 0) +#endif + +/*!< @brief DMA module enable macro. */ +#define HAL_LL_DMA_MODULE_ENABLE(_x) (_x->cr |= 1U << HAL_LL_DMA_CCR_EN_BIT) + +/*!< @brief DMA module disable macro. */ +#define HAL_LL_DMA_MODULE_DISABLE(_x) (_x->cr &= ~(1U << HAL_LL_DMA_CCR_EN_BIT)) + +/*!< @brief Default timeout value to wait when checking if module is disabled/enabled. */ +#define DEFAULT_TIMEOUT_VALUE (0xFFFFU) + +// ----------------------------------------------------------- PRIVATE TYPEDEFS + +/*!< @brief DMA HW register structure. */ +typedef struct dma_handle +{ + volatile uint32_t cr; /*!< DMA channel x configuration register (DMA_CCRx) */ + volatile uint32_t ndtr; /*!< DMA channel x number of data to transfer register (DMA_CNDTRx) */ + volatile uint32_t par; /*!< DMA channel x peripheral address register (DMA_CPARx) */ + volatile uint32_t mar; /*!< DMA channel x memory address register (DMA_CMARx) */ + +} dma_handle_t; + + +typedef struct dmamux_registers +{ + volatile uint32_t dmamux_cr; /*!< DMA interrupt status register */ + +} dmamux_registers_t; + +/*!< @brief DMA HW ISR register structure. */ +typedef struct dma_isr_registers +{ + volatile uint32_t isr; /*!< DMA interrupt status register (DMA_ISR) */ + volatile uint32_t ifcr; /*!< DMA interrupt flag clear register (DMA_IFCR) */ + +} dma_isr_registers_t; + +/*!< @brief DMA HW clock settings structure. */ +typedef struct +{ + uint8_t clock_bit; + hal_ll_base_addr_t clock_base; +} dma_clock_t; + +/*!< @brief DMA control settings structure. */ +typedef struct +{ + dma_clock_t clock; + hal_ll_base_addr_t stream_base; +} dma_control_struct_t; + +// ------------------------------------------------------------------ VARIABLES + +static const dma_control_struct_t dma_controller[ DMA_NUM_OF_MODULES ] = +{ + { + { HAL_LL_DMA1_CLOCK_BIT, HAL_LL_DMA1_CLOCK_BASE }, HAL_LL_DMA1_STREAM_BASE + } +}; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS + +/** + * @brief Gets current stream address. + * @details Returns stream address based on @ref module value and + * desired @ref stream value. + * @param[in] module DMA module number. + * @param[in] stream DMA stream number. + * @return hal_ll_base_addr_t stream base register address. + */ +static hal_ll_base_addr_t hal_ll_dma_get_stream_address( uint8_t module, uint8_t stream ); + +/** + * @brief Sets current module clock. + * @details If @ref state is @b true, enables DMA module clock. + * If @ref state is @b false, disables DMA module clock. + * @param[in] dma_obj DMA object. + * @param[in] state Desired state. + * - @b true + * - @b false + * @return Nothing. + */ +static void hal_ll_dma_clock_set( hal_ll_dma_t *dma_obj, bool state ); + +/** + * @brief Initializes DMA module. + * @details Initializes DMA module, stream to + * values from @ref config structure. + * @param[in] dma_obj DMA object. + * @param[in] dma DMA HW handle. + * @param[in] config DMA configuration structure. + * @return hal_ll_err_t Returns initialization state, either success or fail. + */ +static hal_ll_err_t hal_ll_dma_init_hw( hal_ll_dma_t *dma_obj, dma_handle_t *dma, hal_ll_dma_config_t config ); + +/** + * @brief Gets DMA module state. + * @details Checks if current DMA module stream has been stopped. + * Waits for defined @ref DEFAULT_TIMEOUT_VALUE number of cycles + * before jumping out of loop and returning @ref HAL_LL_DMA_ERROR. + * @param[in] dma DMA HW handle. + * @return hal_ll_err_t Returns success or fail. + */ +static inline hal_ll_err_t hal_ll_dma_is_module_disabled( dma_handle_t *dma ); + +/** + * @brief Gets DMA channel. + * @details Returns appropriate value to be set in HW register + * for desired @ref channel. + * @param[in] channel DMA channel number. + * @return uint32_t Returns actual HW register value based on @ref channel. + */ +static inline uint32_t hal_ll_dma_get_reg_value_channel( uint8_t channel ); + +/** + * @brief Gets DMA direction. + * @details Returns appropriate value to be set in HW register + * for desired @ref direction. + * @param[in] direction DMA stream direction. + * Refer to @hal_ll_dma_direction_t for possible values. + * @return uint8_t Returns actual HW register value based on @ref direction. + */ +static inline uint16_t hal_ll_dma_get_reg_value_direction( hal_ll_dma_direction_t direction ); + +/** + * @brief Gets DMA peripheral address increment. + * @details Returns appropriate value to be set in HW register + * for desired @ref set_inc. + * @param[in] set_inc DMA channel peripheral address increment. + * Set to @b true in order to increment address. + * Set to @b false in order to keep address the same. + * @return uint16_t Returns actual HW register value based on @ref set_inc. + */ +static inline uint16_t hal_ll_dma_get_reg_value_dst_inc( bool set_inc ); + +/** + * @brief Gets DMA memory address increment. + * @details Returns appropriate value to be set in HW register + * for desired @ref set_inc. + * @param[in] set_inc DMA channel memory address increment. + * Set to @b true in order to increment address. + * Set to @b false in order to keep address the same. + * @return uint16_t Returns actual HW register value based on @ref set_inc. + */ +static inline uint16_t hal_ll_dma_get_reg_value_src_inc( bool set_inc ); + +/** + * @brief Gets DMA memory address alignment. + * @details Returns appropriate value to be set in HW register + * for desired @ref align. + * @param[in] align DMA channel memory address increment. + * Refer to @ref hal_ll_dma_data_align_t for possible values. + * @return uint16_t Returns actual HW register value based on @ref align. + */ +static inline uint16_t hal_ll_dma_get_reg_value_source_size( hal_ll_dma_data_align_t align ); + +/** + * @brief Gets DMA peripheral address alignment. + * @details Returns appropriate value to be set in HW register + * for desired @ref align. + * @param[in] align DMA channel peripheral address increment. + * Refer to @ref hal_ll_dma_data_align_t for possible values. + * @return uint16_t Returns actual HW register value based on @ref align. + */ +static inline uint16_t hal_ll_dma_get_reg_value_destination_size( hal_ll_dma_data_align_t align ); + +/** + * @brief Gets DMA mode value. + * @details Returns appropriate value to be set in HW register + * for desired @ref mode. + * @param[in] mode DMA mode for object channel. + * Refer to @ref hal_ll_dma_mode_t for possible values. + * @return uint16_t Returns actual HW register value based on @ref mode. + */ +static inline uint16_t hal_ll_dma_get_reg_value_mode( hal_ll_dma_mode_t mode ); + +/** + * @brief Gets DMA priority value. + * @details Returns appropriate value to be set in HW register + * for desired @ref priority. + * @param[in] priority DMA priority for object channel. + * Refer to @ref hal_ll_dma_priority_t for possible values. + * @return uint32_t Returns actual HW register value based on @ref priority. + */ +static inline uint32_t hal_ll_dma_get_reg_value_priority( hal_ll_dma_priority_t priority ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS + +hal_ll_err_t hal_ll_dma_init( hal_ll_dma_t *obj ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + + // Enable PWRCLK. + #ifdef HAL_LL_PWRCLK_BASE + _HAL_LL_ENABLE_CLOCK_PWR_; + #endif + + // Enable current stream clock. + hal_ll_dma_clock_set( obj, true ); + + // Initialize current stream. + obj->handle = hal_ll_dma_get_stream_address( obj->module, obj->stream ); + status = hal_ll_dma_init_hw( obj, + (dma_handle_t *)obj->handle, + obj->config ); + + if ( HAL_LL_DMA_SUCCESS != status ) { + obj->handle = 0; // If initialization failed, reset handle. + } + + return status; +} + +hal_ll_err_t hal_ll_dma_deinit( hal_ll_dma_t *obj ) { + // First abort current transfer. + if ( HAL_LL_DMA_SUCCESS != hal_ll_dma_transfer_abort( obj ) ) + return HAL_LL_DMA_ERROR; + // Finally, disable module clock. + hal_ll_dma_clock_set( obj, false ); + + return HAL_LL_DMA_SUCCESS; +} + +hal_ll_err_t hal_ll_dma_set_mode( hal_ll_dma_t *obj, hal_ll_dma_mode_t mode ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + // Get new mode. + hal_ll_dma_config_t cfg = obj->config; + cfg.mode = mode; + // Disable module first. + HAL_LL_DMA_MODULE_DISABLE( ((dma_handle_t *)obj->handle) ); + // Try to set new mode. + status = hal_ll_dma_init_hw( obj, + (dma_handle_t *)obj->handle, + cfg ); + + return status; +} + +hal_ll_err_t hal_ll_dma_set_direction( hal_ll_dma_t *obj, hal_ll_dma_direction_t direction ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + // Get new direction. + hal_ll_dma_config_t cfg = obj->config; + cfg.direction = direction; + // Disable module first. + HAL_LL_DMA_MODULE_DISABLE( ((dma_handle_t *)obj->handle) ); + // Try to set new value. + status = hal_ll_dma_init_hw( obj, + (dma_handle_t *)obj->handle, + cfg ); + + return status; +} + +hal_ll_err_t hal_ll_dma_set_priority( hal_ll_dma_t *obj, hal_ll_dma_priority_t priority ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + // Get new priority. + hal_ll_dma_config_t cfg = obj->config; + cfg.priority = priority; + // Disable module first. + HAL_LL_DMA_MODULE_DISABLE( ((dma_handle_t *)obj->handle) ); + // Try to set new value. + status = hal_ll_dma_init_hw( obj, + (dma_handle_t *)obj->handle, + cfg ); + + return status; +} + +hal_ll_err_t hal_ll_dma_set_parameters( hal_ll_dma_t *obj, uint32_t addr_src, uint32_t addr_dst, size_t transfer_size, hal_ll_dma_source_memory_region_t src_mem_type ) { + dma_handle_t *dma = (dma_handle_t *)obj->handle; + uint8_t ndtr_divisor; + + // This parameter is not relevant on this architecture. + (void)src_mem_type; + + // Configure DMA Stream data length. + switch ( obj->config.data_align_destination ) { + case HAL_LL_DMA_DATA_ALIGN_BYTES_1: + case HAL_LL_DMA_DATA_ALIGN_BYTES_2: + ndtr_divisor = obj->config.data_align_destination; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_4: + ndtr_divisor = 2; + break; + + default: + return HAL_LL_DMA_ERROR; + } + dma->ndtr = transfer_size >> ndtr_divisor; + + // Memory to Peripheral. + if ( HAL_LL_DMA_DIRECTION_MEMORY_TO_PERIPH == obj->config.direction ) { + // Configure DMA stream destination address. + dma->par = addr_dst; + // Configure DMA stream source address. + dma->mar = addr_src; + } else { // Peripheral to Memory. + // Configure DMA stream source address. + dma->par = addr_src; + // Configure DMA stream destination address. + dma->mar = addr_dst; + } + return HAL_LL_DMA_SUCCESS; +} + +hal_ll_err_t hal_ll_dma_transfer_start( hal_ll_dma_t *obj ) { + HAL_LL_DMA_MODULE_ENABLE( ((dma_handle_t *)obj->handle) ); + return HAL_LL_DMA_SUCCESS; +} + +hal_ll_err_t hal_ll_dma_transfer_stop( hal_ll_dma_t *obj ) { + dma_handle_t *dma = (dma_handle_t *)obj->handle; + uint16_t timeout = DEFAULT_TIMEOUT_VALUE; + + if ( HAL_LL_DMA_MODE_CIRCULAR == obj->config.mode ) + return HAL_LL_DMA_ERROR; + + while ( dma->ndtr ) { + if ( 0 == timeout-- ) + return HAL_LL_DMA_ERROR; + } + + HAL_LL_DMA_MODULE_DISABLE( dma ); + + return HAL_LL_DMA_SUCCESS; +} + +hal_ll_err_t hal_ll_dma_transfer_abort( hal_ll_dma_t *obj ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + dma_handle_t *dma = (dma_handle_t *)obj->handle; + + // Calculate DMA base and stream number. + dma_isr_registers_t *regs = (dma_isr_registers_t *)(dma_controller[obj->module].stream_base - CCR_BASE_OFFSET); + + // Disable all the transfer interrupts. + dma->cr &= ~(HAL_LL_DMA_CCR_TCIE_BIT | HAL_LL_DMA_CCR_HTIE_BIT | HAL_LL_DMA_CCR_TEIE_BIT); + + // Disable the stream. + HAL_LL_DMA_MODULE_DISABLE( dma ); + + // Wait for bit to be cleared. + status = hal_ll_dma_is_module_disabled( dma ); + + // Clear all interrupt flags at correct offset within the register. + if ( HAL_LL_DMA_SUCCESS == status ) + regs->ifcr = HAL_LL_DMA_IT_CLEAR_MASK << ( obj->stream * 4 ); + + return status; +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS + +static hal_ll_base_addr_t hal_ll_dma_get_stream_address( uint8_t module, uint8_t stream ) { + return ((hal_ll_base_addr_t)dma_controller[module].stream_base + (hal_ll_base_addr_t)(STREAM_BASE_OFFSET * (stream))); +} + +static void hal_ll_dma_clock_set( hal_ll_dma_t *obj, bool state ) { + if ( state ) { + set_reg_bit( (uint32_t *)dma_controller[obj->module].clock.clock_base, + dma_controller[obj->module].clock.clock_bit ); + set_reg_bit( (uint32_t *)dma_controller[obj->module].clock.clock_base, HAL_LL_DMAMUX1_CLOCK_BIT); + } else { + clear_reg_bit( (uint32_t *)dma_controller[obj->module].clock.clock_base, + dma_controller[obj->module].clock.clock_bit ); + } +} + +static hal_ll_err_t hal_ll_dma_init_hw( hal_ll_dma_t *obj, dma_handle_t *dma, hal_ll_dma_config_t config ) { + volatile uint32_t tmp = 0UL; + // Check if user entered invalid data aka HAL_LL_DMA_DATA_ALIGN_BYTES_3 + if (HAL_LL_DMA_DATA_ALIGN_BYTES_3 == config.data_align_source || HAL_LL_DMA_DATA_ALIGN_BYTES_3 == config.data_align_destination ) { + return HAL_LL_DMA_ERROR; + } + + // Disable the peripheral first. + HAL_LL_DMA_MODULE_DISABLE(dma); + + // Wait for bit to be cleared. + if ( HAL_LL_DMA_ERROR == hal_ll_dma_is_module_disabled( dma ) ) + return HAL_LL_DMA_ERROR; + + // Get the CR register value. + tmp = dma->cr; + + // Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits. + tmp &= ((uint32_t)~( HAL_LL_DMA_CCR_EN_BIT | HAL_LL_DMA_CCR_TCIE_BIT | HAL_LL_DMA_CCR_HTIE_BIT | \ + HAL_LL_DMA_CCR_TEIE_BIT | HAL_LL_DMA_CCR_DIR_BIT | HAL_LL_DMA_CCR_CIRC_BIT | \ + HAL_LL_DMA_CCR_PINC_BIT | HAL_LL_DMA_CCR_MINC_BIT | HAL_LL_DMA_CCR_M2M_BIT | \ + HAL_LL_DMA_CCR_PSIZE_MASK | HAL_LL_DMA_CCR_MSIZE_MASK | HAL_LL_DMA_CCR_PRIO_MASK )); + + // BEGIN Prepare the DMA stream configuration. + // Set desired direction value. + tmp |= hal_ll_dma_get_reg_value_direction(config.direction); + // Set desired memory increment settings. + tmp |= hal_ll_dma_get_reg_value_src_inc(config.src_inc); + tmp |= hal_ll_dma_get_reg_value_dst_inc(config.dst_inc); + // Set desired data size settings. + tmp |= hal_ll_dma_get_reg_value_source_size(config.data_align_source); + tmp |= hal_ll_dma_get_reg_value_destination_size(config.data_align_destination); + // Set desired mode. + tmp |= hal_ll_dma_get_reg_value_mode(config.mode); + // Finally, set desired priority. + tmp |= hal_ll_dma_get_reg_value_priority(config.priority); + + // And then write to DMA stream CR register. + dma->cr = tmp; + + if (obj->module == 0 ) { + dmamux_registers_t * dmamux = (dmamux_registers_t*)( DMAMUX1_BASE + ( obj->stream * DMAMUX1_OFFSET ) ); + dmamux->dmamux_cr |= obj->channel; + } else { + dmamux_registers_t * dmamux = (dmamux_registers_t*)( DMAMUX1_BASE + ( DMA_NUM_OF_STREAMS * DMAMUX1_OFFSET ) + ( obj->stream * DMAMUX1_OFFSET ) ); + dmamux->dmamux_cr |= obj->channel; + } + + return HAL_LL_DMA_SUCCESS; +} + +static inline hal_ll_err_t hal_ll_dma_is_module_disabled( dma_handle_t *dma ) { + uint16_t timeout = DEFAULT_TIMEOUT_VALUE; + + while ( (dma->cr & (1U << HAL_LL_DMA_CCR_EN_BIT)) != 0 ) { + if ( 0 == timeout-- ) + return HAL_LL_DMA_ERROR; + } + + return HAL_LL_DMA_SUCCESS; +} + +static inline uint16_t hal_ll_dma_get_reg_value_direction( hal_ll_dma_direction_t direction ) { + volatile uint16_t direction_set = (uint8_t)HAL_LL_DMA_DIRECTION_MEMORY_TO_MEMORY; + + switch ( direction ) + { + case HAL_LL_DMA_DIRECTION_MEMORY_TO_MEMORY: + direction_set = HAL_LL_DMA_DIRECTION_MEMORY_TO_MEMORY_MASK; + break; + case HAL_LL_DMA_DIRECTION_MEMORY_TO_PERIPH: + direction_set = HAL_LL_DMA_DIRECTION_MEMORY_TO_PERIPH_MASK; + break; + case HAL_LL_DMA_DIRECTION_PERIPH_TO_MEMORY: + direction_set = HAL_LL_DMA_DIRECTION_PERIPH_TO_MEMORY_MASK; + break; + + default: + break; + } + + return (uint16_t)direction_set; +} + +static inline uint16_t hal_ll_dma_get_reg_value_dst_inc( bool set_inc ) { + return (uint16_t)((set_inc) ? (HAL_LL_DMA_PINC_MASK) : (0)); +} + +static inline uint16_t hal_ll_dma_get_reg_value_src_inc( bool set_inc ) { + return (uint16_t)((set_inc) ? (HAL_LL_DMA_MINC_MASK) : (0)); +} + +static inline uint16_t hal_ll_dma_get_reg_value_source_size( hal_ll_dma_data_align_t align ) { + volatile uint16_t align_set = (uint16_t)HAL_LL_DMA_DATA_ALIGN_BYTES_1; + + switch ( align ) + { + case HAL_LL_DMA_DATA_ALIGN_BYTES_1: + align_set = HAL_LL_DMA_MSIZE_BYTE_MASK; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_2: + align_set = HAL_LL_DMA_MSIZE_HALFWORD_MASK; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_4: + align_set = HAL_LL_DMA_MSIZE_WORD_MASK; + break; + + default: + break; + } + + return (uint16_t)align_set; +} + +static inline uint16_t hal_ll_dma_get_reg_value_destination_size( hal_ll_dma_data_align_t align ) { + volatile uint16_t align_set = (uint16_t)HAL_LL_DMA_DATA_ALIGN_BYTES_1; + + switch ( align ) + { + case HAL_LL_DMA_DATA_ALIGN_BYTES_1: + align_set = HAL_LL_DMA_CCR_PSIZE_BYTE_MASK; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_2: + align_set = HAL_LL_DMA_CCR_PSIZE_HALFWORD_MASK; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_4: + align_set = HAL_LL_DMA_CCR_PSIZE_WORD_MASK; + break; + + default: + break; + } + + return (uint16_t)align_set; +} + +static inline uint16_t hal_ll_dma_get_reg_value_mode( hal_ll_dma_mode_t mode ) { + return (uint16_t)((mode) ? (HAL_LL_DMA_CCR_CIRC_MASK) : (0)); +} + +static inline uint32_t hal_ll_dma_get_reg_value_priority( hal_ll_dma_priority_t priority ) { + volatile uint32_t priority_set = (uint32_t)HAL_LL_DMA_PRIORITY_LOW; + + switch ( priority ) + { + case HAL_LL_DMA_PRIORITY_LOW: + priority_set = HAL_LL_DMA_CCR_PRIORITY_LOW_MASK; + break; + case HAL_LL_DMA_PRIORITY_MEDIUM: + priority_set = HAL_LL_DMA_CCR_PRIORITY_MEDIUM_MASK; + break; + case HAL_LL_DMA_PRIORITY_HIGH: + priority_set = HAL_LL_DMA_CCR_PRIORITY_HIGH_MASK; + break; + case HAL_LL_DMA_PRIORITY_VERY_HIGH: + priority_set = HAL_LL_DMA_CCR_PRIORITY_VERY_HIGH_MASK; + break; + + default: + break; + } + + return (uint32_t)priority_set; +} + +// ------------------------------------------------------------------------- END + + + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_74/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_74/CMakeLists.cmake new file mode 100644 index 000000000..f0a8109ec --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_74/CMakeLists.cmake @@ -0,0 +1,8 @@ +if(${MCU_NAME} MATCHES "^STM32G051C6$|^STM32G051F6$|^STM32G051G6$|^STM32G051K6$|^STM32G051C8$|^STM32G051F8$|^STM32G051G8$|^STM32G051K8$") + set(dma_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_dma.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_74") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_74") + list(APPEND hal_ll_def_list "STM32G0xx") + list(APPEND hal_ll_def_list "STM32G05xx") + list(APPEND hal_ll_def_list "STM32G051xx") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_74/hal_ll_dma.c b/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_74/hal_ll_dma.c new file mode 100644 index 000000000..87a32e7b4 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_74/hal_ll_dma.c @@ -0,0 +1,661 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_dma.c + * @brief DMA HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_rcc.h" +#include "hal_ll_dma.h" +#include "hal_ll_gpio.h" + +// ------------------------------------------------------------- PRIVATE MACROS + + +/*!< @brief DMA interrupt definitions. */ +#define HAL_LL_DMA_IT_FT ((uint32_t)(1U << 1)) +#define HAL_LL_DMA_IT_HT ((uint32_t)(1U << 2)) +#define HAL_LL_DMA_IT_ET ((uint32_t)(1U << 3)) +#define HAL_LL_DMA_IT_CLEAR_MASK (0x0fUL) + +/*!< @brief DMA SCR register masks. */ + + + +#define HAL_LL_DMA_CCR_PRIORITY_VERY_HIGH_MASK (0x00003000) +#define HAL_LL_DMA_CCR_PRIORITY_HIGH_MASK (0x00002000) +#define HAL_LL_DMA_CCR_PRIORITY_MEDIUM_MASK (0x00001000) +#define HAL_LL_DMA_CCR_PRIORITY_LOW_MASK (0x00000000) +#define HAL_LL_DMA_CCR_CIRC_MASK (0x00000020) +#define HAL_LL_DMA_CCR_PSIZE_BYTE_MASK (0x00000000) +#define HAL_LL_DMA_CCR_PSIZE_HALFWORD_MASK (0x00000100) +#define HAL_LL_DMA_CCR_PSIZE_WORD_MASK (0x00000200) +#define HAL_LL_DMA_MSIZE_BYTE_MASK (0x00000000) +#define HAL_LL_DMA_MSIZE_HALFWORD_MASK (0x00000400) +#define HAL_LL_DMA_MSIZE_WORD_MASK (0x00000800) +#define HAL_LL_DMA_MINC_MASK (0x00000080) +#define HAL_LL_DMA_PINC_MASK (0x00000040) + +#define HAL_LL_DMA_DIRECTION_MEMORY_TO_MEMORY_MASK (0x4000) +#define HAL_LL_DMA_DIRECTION_MEMORY_TO_PERIPH_MASK (0x10) +#define HAL_LL_DMA_DIRECTION_PERIPH_TO_MEMORY_MASK (0x0) + +#define HAL_LL_DMA_CCR_PSIZE_MASK (0x00000300) +#define HAL_LL_DMA_CCR_MSIZE_MASK (0x00000C00) +#define HAL_LL_DMA_CCR_PRIO_MASK (0x00003000) +#define HAL_LL_DMA_CCR_EN_BIT (0) +#define HAL_LL_DMA_CCR_TEIE_BIT (3) +#define HAL_LL_DMA_CCR_HTIE_BIT (2) +#define HAL_LL_DMA_CCR_TCIE_BIT (1) +#define HAL_LL_DMA_CCR_DIR_BIT (4) +#define HAL_LL_DMA_CCR_CIRC_BIT (5) +#define HAL_LL_DMA_CCR_PINC_BIT (6) +#define HAL_LL_DMA_CCR_MINC_BIT (7) +#define HAL_LL_DMA_CCR_M2M_BIT (14) + + + +#define DMA1_BASE (0x40020000UL) +#define DMA2_BASE (0x40020400UL) + +#define HAL_LL_DMA1_CLOCK_BIT (0) +#define HAL_LL_DMA1_CLOCK_BASE ((uint32_t)_RCC_AHBENR) +#define HAL_LL_DMA1_STREAM_BASE (DMA1_BASE + CCR_BASE_OFFSET) +#define HAL_LL_DMA2_CLOCK_BIT (1) +#define HAL_LL_DMA2_CLOCK_BASE ((uint32_t)_RCC_AHBENR) +#define HAL_LL_DMA2_STREAM_BASE (DMA2_BASE + CCR_BASE_OFFSET) + +#define CCR_BASE_OFFSET (0x8U) +#define STREAM_BASE_OFFSET (0x14U) +#define IFCR_BASE_OFFSET (0x4U) +#define HAL_LL_PWRCLK_BIT (28) + +/*diff bits/offsets:*/ +#define HAL_LL_PWRCLK_BASE (_RCC_APBENR1) + +#define DMAMUX1_BASE (0x40020800UL) +#define DMAMUX1_OFFSET (0x04U) +#define HAL_LL_DMAMUX1_CLOCK_BIT (2) + + + + + +/*!< @brief Clock enable macros. */ +#ifdef HAL_LL_PWRCLK_BASE +#define _HAL_LL_ENABLE_CLOCK_PWR_ ((HAL_LL_PWRCLK_BASE) ? (*HAL_LL_PWRCLK_BASE |= 1UL << HAL_LL_PWRCLK_BIT) : 0) +#endif + +/*!< @brief DMA module enable macro. */ +#define HAL_LL_DMA_MODULE_ENABLE(_x) (_x->cr |= 1U << HAL_LL_DMA_CCR_EN_BIT) + +/*!< @brief DMA module disable macro. */ +#define HAL_LL_DMA_MODULE_DISABLE(_x) (_x->cr &= ~(1U << HAL_LL_DMA_CCR_EN_BIT)) + +/*!< @brief Default timeout value to wait when checking if module is disabled/enabled. */ +#define DEFAULT_TIMEOUT_VALUE (0xFFFFU) + +// ----------------------------------------------------------- PRIVATE TYPEDEFS + +/*!< @brief DMA HW register structure. */ +typedef struct dma_handle +{ + volatile uint32_t cr; /*!< DMA channel x configuration register (DMA_CCRx) */ + volatile uint32_t ndtr; /*!< DMA channel x number of data to transfer register (DMA_CNDTRx) */ + volatile uint32_t par; /*!< DMA channel x peripheral address register (DMA_CPARx) */ + volatile uint32_t mar; /*!< DMA channel x memory address register (DMA_CMARx) */ + +} dma_handle_t; + + +typedef struct dmamux_registers +{ + volatile uint32_t dmamux_cr; /*!< DMA interrupt status register */ + +} dmamux_registers_t; + +/*!< @brief DMA HW ISR register structure. */ +typedef struct dma_isr_registers +{ + volatile uint32_t isr; /*!< DMA interrupt status register (DMA_ISR) */ + volatile uint32_t ifcr; /*!< DMA interrupt flag clear register (DMA_IFCR) */ + +} dma_isr_registers_t; + +/*!< @brief DMA HW clock settings structure. */ +typedef struct +{ + uint8_t clock_bit; + hal_ll_base_addr_t clock_base; +} dma_clock_t; + +/*!< @brief DMA control settings structure. */ +typedef struct +{ + dma_clock_t clock; + hal_ll_base_addr_t stream_base; +} dma_control_struct_t; + +// ------------------------------------------------------------------ VARIABLES + +static const dma_control_struct_t dma_controller[ DMA_NUM_OF_MODULES ] = +{ + { + { HAL_LL_DMA1_CLOCK_BIT, HAL_LL_DMA1_CLOCK_BASE }, HAL_LL_DMA1_STREAM_BASE + } + ,{ + { HAL_LL_DMA2_CLOCK_BIT, HAL_LL_DMA2_CLOCK_BASE }, HAL_LL_DMA2_STREAM_BASE + } +}; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS + +/** + * @brief Gets current stream address. + * @details Returns stream address based on @ref module value and + * desired @ref stream value. + * @param[in] module DMA module number. + * @param[in] stream DMA stream number. + * @return hal_ll_base_addr_t stream base register address. + */ +static hal_ll_base_addr_t hal_ll_dma_get_stream_address( uint8_t module, uint8_t stream ); + +/** + * @brief Sets current module clock. + * @details If @ref state is @b true, enables DMA module clock. + * If @ref state is @b false, disables DMA module clock. + * @param[in] dma_obj DMA object. + * @param[in] state Desired state. + * - @b true + * - @b false + * @return Nothing. + */ +static void hal_ll_dma_clock_set( hal_ll_dma_t *dma_obj, bool state ); + +/** + * @brief Initializes DMA module. + * @details Initializes DMA module, stream to + * values from @ref config structure. + * @param[in] dma_obj DMA object. + * @param[in] dma DMA HW handle. + * @param[in] config DMA configuration structure. + * @return hal_ll_err_t Returns initialization state, either success or fail. + */ +static hal_ll_err_t hal_ll_dma_init_hw( hal_ll_dma_t *dma_obj, dma_handle_t *dma, hal_ll_dma_config_t config ); + +/** + * @brief Gets DMA module state. + * @details Checks if current DMA module stream has been stopped. + * Waits for defined @ref DEFAULT_TIMEOUT_VALUE number of cycles + * before jumping out of loop and returning @ref HAL_LL_DMA_ERROR. + * @param[in] dma DMA HW handle. + * @return hal_ll_err_t Returns success or fail. + */ +static inline hal_ll_err_t hal_ll_dma_is_module_disabled( dma_handle_t *dma ); + +/** + * @brief Gets DMA channel. + * @details Returns appropriate value to be set in HW register + * for desired @ref channel. + * @param[in] channel DMA channel number. + * @return uint32_t Returns actual HW register value based on @ref channel. + */ +static inline uint32_t hal_ll_dma_get_reg_value_channel( uint8_t channel ); + +/** + * @brief Gets DMA direction. + * @details Returns appropriate value to be set in HW register + * for desired @ref direction. + * @param[in] direction DMA stream direction. + * Refer to @hal_ll_dma_direction_t for possible values. + * @return uint8_t Returns actual HW register value based on @ref direction. + */ +static inline uint16_t hal_ll_dma_get_reg_value_direction( hal_ll_dma_direction_t direction ); + +/** + * @brief Gets DMA peripheral address increment. + * @details Returns appropriate value to be set in HW register + * for desired @ref set_inc. + * @param[in] set_inc DMA channel peripheral address increment. + * Set to @b true in order to increment address. + * Set to @b false in order to keep address the same. + * @return uint16_t Returns actual HW register value based on @ref set_inc. + */ +static inline uint16_t hal_ll_dma_get_reg_value_dst_inc( bool set_inc ); + +/** + * @brief Gets DMA memory address increment. + * @details Returns appropriate value to be set in HW register + * for desired @ref set_inc. + * @param[in] set_inc DMA channel memory address increment. + * Set to @b true in order to increment address. + * Set to @b false in order to keep address the same. + * @return uint16_t Returns actual HW register value based on @ref set_inc. + */ +static inline uint16_t hal_ll_dma_get_reg_value_src_inc( bool set_inc ); + +/** + * @brief Gets DMA memory address alignment. + * @details Returns appropriate value to be set in HW register + * for desired @ref align. + * @param[in] align DMA channel memory address increment. + * Refer to @ref hal_ll_dma_data_align_t for possible values. + * @return uint16_t Returns actual HW register value based on @ref align. + */ +static inline uint16_t hal_ll_dma_get_reg_value_source_size( hal_ll_dma_data_align_t align ); + +/** + * @brief Gets DMA peripheral address alignment. + * @details Returns appropriate value to be set in HW register + * for desired @ref align. + * @param[in] align DMA channel peripheral address increment. + * Refer to @ref hal_ll_dma_data_align_t for possible values. + * @return uint16_t Returns actual HW register value based on @ref align. + */ +static inline uint16_t hal_ll_dma_get_reg_value_destination_size( hal_ll_dma_data_align_t align ); + +/** + * @brief Gets DMA mode value. + * @details Returns appropriate value to be set in HW register + * for desired @ref mode. + * @param[in] mode DMA mode for object channel. + * Refer to @ref hal_ll_dma_mode_t for possible values. + * @return uint16_t Returns actual HW register value based on @ref mode. + */ +static inline uint16_t hal_ll_dma_get_reg_value_mode( hal_ll_dma_mode_t mode ); + +/** + * @brief Gets DMA priority value. + * @details Returns appropriate value to be set in HW register + * for desired @ref priority. + * @param[in] priority DMA priority for object channel. + * Refer to @ref hal_ll_dma_priority_t for possible values. + * @return uint32_t Returns actual HW register value based on @ref priority. + */ +static inline uint32_t hal_ll_dma_get_reg_value_priority( hal_ll_dma_priority_t priority ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS + +hal_ll_err_t hal_ll_dma_init( hal_ll_dma_t *obj ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + + // Enable PWRCLK. + #ifdef HAL_LL_PWRCLK_BASE + _HAL_LL_ENABLE_CLOCK_PWR_; + #endif + + // Enable current stream clock. + hal_ll_dma_clock_set( obj, true ); + + // Initialize current stream. + obj->handle = hal_ll_dma_get_stream_address( obj->module, obj->stream ); + status = hal_ll_dma_init_hw( obj, + (dma_handle_t *)obj->handle, + obj->config ); + + if ( HAL_LL_DMA_SUCCESS != status ) { + obj->handle = 0; // If initialization failed, reset handle. + } + + return status; +} + +hal_ll_err_t hal_ll_dma_deinit( hal_ll_dma_t *obj ) { + // First abort current transfer. + if ( HAL_LL_DMA_SUCCESS != hal_ll_dma_transfer_abort( obj ) ) + return HAL_LL_DMA_ERROR; + // Finally, disable module clock. + hal_ll_dma_clock_set( obj, false ); + + return HAL_LL_DMA_SUCCESS; +} + +hal_ll_err_t hal_ll_dma_set_mode( hal_ll_dma_t *obj, hal_ll_dma_mode_t mode ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + // Get new mode. + hal_ll_dma_config_t cfg = obj->config; + cfg.mode = mode; + // Disable module first. + HAL_LL_DMA_MODULE_DISABLE( ((dma_handle_t *)obj->handle) ); + // Try to set new mode. + status = hal_ll_dma_init_hw( obj, + (dma_handle_t *)obj->handle, + cfg ); + + return status; +} + +hal_ll_err_t hal_ll_dma_set_direction( hal_ll_dma_t *obj, hal_ll_dma_direction_t direction ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + // Get new direction. + hal_ll_dma_config_t cfg = obj->config; + cfg.direction = direction; + // Disable module first. + HAL_LL_DMA_MODULE_DISABLE( ((dma_handle_t *)obj->handle) ); + // Try to set new value. + status = hal_ll_dma_init_hw( obj, + (dma_handle_t *)obj->handle, + cfg ); + + return status; +} + +hal_ll_err_t hal_ll_dma_set_priority( hal_ll_dma_t *obj, hal_ll_dma_priority_t priority ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + // Get new priority. + hal_ll_dma_config_t cfg = obj->config; + cfg.priority = priority; + // Disable module first. + HAL_LL_DMA_MODULE_DISABLE( ((dma_handle_t *)obj->handle) ); + // Try to set new value. + status = hal_ll_dma_init_hw( obj, + (dma_handle_t *)obj->handle, + cfg ); + + return status; +} + +hal_ll_err_t hal_ll_dma_set_parameters( hal_ll_dma_t *obj, uint32_t addr_src, uint32_t addr_dst, size_t transfer_size, hal_ll_dma_source_memory_region_t src_mem_type ) { + dma_handle_t *dma = (dma_handle_t *)obj->handle; + uint8_t ndtr_divisor; + + // This parameter is not relevant on this architecture. + (void)src_mem_type; + + // Configure DMA Stream data length. + switch ( obj->config.data_align_destination ) { + case HAL_LL_DMA_DATA_ALIGN_BYTES_1: + case HAL_LL_DMA_DATA_ALIGN_BYTES_2: + ndtr_divisor = obj->config.data_align_destination; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_4: + ndtr_divisor = 2; + break; + + default: + return HAL_LL_DMA_ERROR; + } + dma->ndtr = transfer_size >> ndtr_divisor; + + // Memory to Peripheral. + if ( HAL_LL_DMA_DIRECTION_MEMORY_TO_PERIPH == obj->config.direction ) { + // Configure DMA stream destination address. + dma->par = addr_dst; + // Configure DMA stream source address. + dma->mar = addr_src; + } else { // Peripheral to Memory. + // Configure DMA stream source address. + dma->par = addr_src; + // Configure DMA stream destination address. + dma->mar = addr_dst; + } + return HAL_LL_DMA_SUCCESS; +} + +hal_ll_err_t hal_ll_dma_transfer_start( hal_ll_dma_t *obj ) { + HAL_LL_DMA_MODULE_ENABLE( ((dma_handle_t *)obj->handle) ); + return HAL_LL_DMA_SUCCESS; +} + +hal_ll_err_t hal_ll_dma_transfer_stop( hal_ll_dma_t *obj ) { + dma_handle_t *dma = (dma_handle_t *)obj->handle; + uint16_t timeout = DEFAULT_TIMEOUT_VALUE; + + if ( HAL_LL_DMA_MODE_CIRCULAR == obj->config.mode ) + return HAL_LL_DMA_ERROR; + + while ( dma->ndtr ) { + if ( 0 == timeout-- ) + return HAL_LL_DMA_ERROR; + } + + HAL_LL_DMA_MODULE_DISABLE( dma ); + + return HAL_LL_DMA_SUCCESS; +} + +hal_ll_err_t hal_ll_dma_transfer_abort( hal_ll_dma_t *obj ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + dma_handle_t *dma = (dma_handle_t *)obj->handle; + + // Calculate DMA base and stream number. + dma_isr_registers_t *regs = (dma_isr_registers_t *)(dma_controller[obj->module].stream_base - CCR_BASE_OFFSET); + + // Disable all the transfer interrupts. + dma->cr &= ~(HAL_LL_DMA_CCR_TCIE_BIT | HAL_LL_DMA_CCR_HTIE_BIT | HAL_LL_DMA_CCR_TEIE_BIT); + + // Disable the stream. + HAL_LL_DMA_MODULE_DISABLE( dma ); + + // Wait for bit to be cleared. + status = hal_ll_dma_is_module_disabled( dma ); + + // Clear all interrupt flags at correct offset within the register. + if ( HAL_LL_DMA_SUCCESS == status ) + regs->ifcr = HAL_LL_DMA_IT_CLEAR_MASK << ( obj->stream * 4 ); + + return status; +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS + +static hal_ll_base_addr_t hal_ll_dma_get_stream_address( uint8_t module, uint8_t stream ) { + return ((hal_ll_base_addr_t)dma_controller[module].stream_base + (hal_ll_base_addr_t)(STREAM_BASE_OFFSET * (stream))); +} + +static void hal_ll_dma_clock_set( hal_ll_dma_t *obj, bool state ) { + if ( state ) { + set_reg_bit( (uint32_t *)dma_controller[obj->module].clock.clock_base, + dma_controller[obj->module].clock.clock_bit ); + set_reg_bit( (uint32_t *)dma_controller[obj->module].clock.clock_base, HAL_LL_DMAMUX1_CLOCK_BIT); + } else { + clear_reg_bit( (uint32_t *)dma_controller[obj->module].clock.clock_base, + dma_controller[obj->module].clock.clock_bit ); + } +} + +static hal_ll_err_t hal_ll_dma_init_hw( hal_ll_dma_t *obj, dma_handle_t *dma, hal_ll_dma_config_t config ) { + volatile uint32_t tmp = 0UL; + // Check if user entered invalid data aka HAL_LL_DMA_DATA_ALIGN_BYTES_3 + if (HAL_LL_DMA_DATA_ALIGN_BYTES_3 == config.data_align_source || HAL_LL_DMA_DATA_ALIGN_BYTES_3 == config.data_align_destination ) { + return HAL_LL_DMA_ERROR; + } + + // Disable the peripheral first. + HAL_LL_DMA_MODULE_DISABLE(dma); + + // Wait for bit to be cleared. + if ( HAL_LL_DMA_ERROR == hal_ll_dma_is_module_disabled( dma ) ) + return HAL_LL_DMA_ERROR; + + // Get the CR register value. + tmp = dma->cr; + + // Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits. + tmp &= ((uint32_t)~( HAL_LL_DMA_CCR_EN_BIT | HAL_LL_DMA_CCR_TCIE_BIT | HAL_LL_DMA_CCR_HTIE_BIT | \ + HAL_LL_DMA_CCR_TEIE_BIT | HAL_LL_DMA_CCR_DIR_BIT | HAL_LL_DMA_CCR_CIRC_BIT | \ + HAL_LL_DMA_CCR_PINC_BIT | HAL_LL_DMA_CCR_MINC_BIT | HAL_LL_DMA_CCR_M2M_BIT | \ + HAL_LL_DMA_CCR_PSIZE_MASK | HAL_LL_DMA_CCR_MSIZE_MASK | HAL_LL_DMA_CCR_PRIO_MASK )); + + // BEGIN Prepare the DMA stream configuration. + // Set desired direction value. + tmp |= hal_ll_dma_get_reg_value_direction(config.direction); + // Set desired memory increment settings. + tmp |= hal_ll_dma_get_reg_value_src_inc(config.src_inc); + tmp |= hal_ll_dma_get_reg_value_dst_inc(config.dst_inc); + // Set desired data size settings. + tmp |= hal_ll_dma_get_reg_value_source_size(config.data_align_source); + tmp |= hal_ll_dma_get_reg_value_destination_size(config.data_align_destination); + // Set desired mode. + tmp |= hal_ll_dma_get_reg_value_mode(config.mode); + // Finally, set desired priority. + tmp |= hal_ll_dma_get_reg_value_priority(config.priority); + + // And then write to DMA stream CR register. + dma->cr = tmp; + + if (obj->module == 0 ) { + dmamux_registers_t * dmamux = (dmamux_registers_t*)( DMAMUX1_BASE + ( obj->stream * DMAMUX1_OFFSET ) ); + dmamux->dmamux_cr |= obj->channel; + } else { + dmamux_registers_t * dmamux = (dmamux_registers_t*)( DMAMUX1_BASE + ( DMA_NUM_OF_STREAMS * DMAMUX1_OFFSET ) + ( obj->stream * DMAMUX1_OFFSET ) ); + dmamux->dmamux_cr |= obj->channel; + } + + return HAL_LL_DMA_SUCCESS; +} + +static inline hal_ll_err_t hal_ll_dma_is_module_disabled( dma_handle_t *dma ) { + uint16_t timeout = DEFAULT_TIMEOUT_VALUE; + + while ( (dma->cr & (1U << HAL_LL_DMA_CCR_EN_BIT)) != 0 ) { + if ( 0 == timeout-- ) + return HAL_LL_DMA_ERROR; + } + + return HAL_LL_DMA_SUCCESS; +} + +static inline uint16_t hal_ll_dma_get_reg_value_direction( hal_ll_dma_direction_t direction ) { + volatile uint16_t direction_set = (uint8_t)HAL_LL_DMA_DIRECTION_MEMORY_TO_MEMORY; + + switch ( direction ) + { + case HAL_LL_DMA_DIRECTION_MEMORY_TO_MEMORY: + direction_set = HAL_LL_DMA_DIRECTION_MEMORY_TO_MEMORY_MASK; + break; + case HAL_LL_DMA_DIRECTION_MEMORY_TO_PERIPH: + direction_set = HAL_LL_DMA_DIRECTION_MEMORY_TO_PERIPH_MASK; + break; + case HAL_LL_DMA_DIRECTION_PERIPH_TO_MEMORY: + direction_set = HAL_LL_DMA_DIRECTION_PERIPH_TO_MEMORY_MASK; + break; + + default: + break; + } + + return (uint16_t)direction_set; +} + +static inline uint16_t hal_ll_dma_get_reg_value_dst_inc( bool set_inc ) { + return (uint16_t)((set_inc) ? (HAL_LL_DMA_PINC_MASK) : (0)); +} + +static inline uint16_t hal_ll_dma_get_reg_value_src_inc( bool set_inc ) { + return (uint16_t)((set_inc) ? (HAL_LL_DMA_MINC_MASK) : (0)); +} + +static inline uint16_t hal_ll_dma_get_reg_value_source_size( hal_ll_dma_data_align_t align ) { + volatile uint16_t align_set = (uint16_t)HAL_LL_DMA_DATA_ALIGN_BYTES_1; + + switch ( align ) + { + case HAL_LL_DMA_DATA_ALIGN_BYTES_1: + align_set = HAL_LL_DMA_MSIZE_BYTE_MASK; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_2: + align_set = HAL_LL_DMA_MSIZE_HALFWORD_MASK; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_4: + align_set = HAL_LL_DMA_MSIZE_WORD_MASK; + break; + + default: + break; + } + + return (uint16_t)align_set; +} + +static inline uint16_t hal_ll_dma_get_reg_value_destination_size( hal_ll_dma_data_align_t align ) { + volatile uint16_t align_set = (uint16_t)HAL_LL_DMA_DATA_ALIGN_BYTES_1; + + switch ( align ) + { + case HAL_LL_DMA_DATA_ALIGN_BYTES_1: + align_set = HAL_LL_DMA_CCR_PSIZE_BYTE_MASK; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_2: + align_set = HAL_LL_DMA_CCR_PSIZE_HALFWORD_MASK; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_4: + align_set = HAL_LL_DMA_CCR_PSIZE_WORD_MASK; + break; + + default: + break; + } + + return (uint16_t)align_set; +} + +static inline uint16_t hal_ll_dma_get_reg_value_mode( hal_ll_dma_mode_t mode ) { + return (uint16_t)((mode) ? (HAL_LL_DMA_CCR_CIRC_MASK) : (0)); +} + +static inline uint32_t hal_ll_dma_get_reg_value_priority( hal_ll_dma_priority_t priority ) { + volatile uint32_t priority_set = (uint32_t)HAL_LL_DMA_PRIORITY_LOW; + + switch ( priority ) + { + case HAL_LL_DMA_PRIORITY_LOW: + priority_set = HAL_LL_DMA_CCR_PRIORITY_LOW_MASK; + break; + case HAL_LL_DMA_PRIORITY_MEDIUM: + priority_set = HAL_LL_DMA_CCR_PRIORITY_MEDIUM_MASK; + break; + case HAL_LL_DMA_PRIORITY_HIGH: + priority_set = HAL_LL_DMA_CCR_PRIORITY_HIGH_MASK; + break; + case HAL_LL_DMA_PRIORITY_VERY_HIGH: + priority_set = HAL_LL_DMA_CCR_PRIORITY_VERY_HIGH_MASK; + break; + + default: + break; + } + + return (uint32_t)priority_set; +} + +// ------------------------------------------------------------------------- END + + + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_75/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_75/CMakeLists.cmake new file mode 100644 index 000000000..a518ec345 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_75/CMakeLists.cmake @@ -0,0 +1,8 @@ +if(${MCU_NAME} MATCHES "^STM32G061C6$|^STM32G061F6$|^STM32G061G6$|^STM32G061K6$|^STM32G061C8$|^STM32G061F8$|^STM32G061G8$|^STM32G061K8$") + set(dma_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_dma.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_75") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_75") + list(APPEND hal_ll_def_list "STM32G0xx") + list(APPEND hal_ll_def_list "STM32G06xx") + list(APPEND hal_ll_def_list "STM32G061xx") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_75/hal_ll_dma.c b/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_75/hal_ll_dma.c new file mode 100644 index 000000000..87a32e7b4 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_75/hal_ll_dma.c @@ -0,0 +1,661 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_dma.c + * @brief DMA HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_rcc.h" +#include "hal_ll_dma.h" +#include "hal_ll_gpio.h" + +// ------------------------------------------------------------- PRIVATE MACROS + + +/*!< @brief DMA interrupt definitions. */ +#define HAL_LL_DMA_IT_FT ((uint32_t)(1U << 1)) +#define HAL_LL_DMA_IT_HT ((uint32_t)(1U << 2)) +#define HAL_LL_DMA_IT_ET ((uint32_t)(1U << 3)) +#define HAL_LL_DMA_IT_CLEAR_MASK (0x0fUL) + +/*!< @brief DMA SCR register masks. */ + + + +#define HAL_LL_DMA_CCR_PRIORITY_VERY_HIGH_MASK (0x00003000) +#define HAL_LL_DMA_CCR_PRIORITY_HIGH_MASK (0x00002000) +#define HAL_LL_DMA_CCR_PRIORITY_MEDIUM_MASK (0x00001000) +#define HAL_LL_DMA_CCR_PRIORITY_LOW_MASK (0x00000000) +#define HAL_LL_DMA_CCR_CIRC_MASK (0x00000020) +#define HAL_LL_DMA_CCR_PSIZE_BYTE_MASK (0x00000000) +#define HAL_LL_DMA_CCR_PSIZE_HALFWORD_MASK (0x00000100) +#define HAL_LL_DMA_CCR_PSIZE_WORD_MASK (0x00000200) +#define HAL_LL_DMA_MSIZE_BYTE_MASK (0x00000000) +#define HAL_LL_DMA_MSIZE_HALFWORD_MASK (0x00000400) +#define HAL_LL_DMA_MSIZE_WORD_MASK (0x00000800) +#define HAL_LL_DMA_MINC_MASK (0x00000080) +#define HAL_LL_DMA_PINC_MASK (0x00000040) + +#define HAL_LL_DMA_DIRECTION_MEMORY_TO_MEMORY_MASK (0x4000) +#define HAL_LL_DMA_DIRECTION_MEMORY_TO_PERIPH_MASK (0x10) +#define HAL_LL_DMA_DIRECTION_PERIPH_TO_MEMORY_MASK (0x0) + +#define HAL_LL_DMA_CCR_PSIZE_MASK (0x00000300) +#define HAL_LL_DMA_CCR_MSIZE_MASK (0x00000C00) +#define HAL_LL_DMA_CCR_PRIO_MASK (0x00003000) +#define HAL_LL_DMA_CCR_EN_BIT (0) +#define HAL_LL_DMA_CCR_TEIE_BIT (3) +#define HAL_LL_DMA_CCR_HTIE_BIT (2) +#define HAL_LL_DMA_CCR_TCIE_BIT (1) +#define HAL_LL_DMA_CCR_DIR_BIT (4) +#define HAL_LL_DMA_CCR_CIRC_BIT (5) +#define HAL_LL_DMA_CCR_PINC_BIT (6) +#define HAL_LL_DMA_CCR_MINC_BIT (7) +#define HAL_LL_DMA_CCR_M2M_BIT (14) + + + +#define DMA1_BASE (0x40020000UL) +#define DMA2_BASE (0x40020400UL) + +#define HAL_LL_DMA1_CLOCK_BIT (0) +#define HAL_LL_DMA1_CLOCK_BASE ((uint32_t)_RCC_AHBENR) +#define HAL_LL_DMA1_STREAM_BASE (DMA1_BASE + CCR_BASE_OFFSET) +#define HAL_LL_DMA2_CLOCK_BIT (1) +#define HAL_LL_DMA2_CLOCK_BASE ((uint32_t)_RCC_AHBENR) +#define HAL_LL_DMA2_STREAM_BASE (DMA2_BASE + CCR_BASE_OFFSET) + +#define CCR_BASE_OFFSET (0x8U) +#define STREAM_BASE_OFFSET (0x14U) +#define IFCR_BASE_OFFSET (0x4U) +#define HAL_LL_PWRCLK_BIT (28) + +/*diff bits/offsets:*/ +#define HAL_LL_PWRCLK_BASE (_RCC_APBENR1) + +#define DMAMUX1_BASE (0x40020800UL) +#define DMAMUX1_OFFSET (0x04U) +#define HAL_LL_DMAMUX1_CLOCK_BIT (2) + + + + + +/*!< @brief Clock enable macros. */ +#ifdef HAL_LL_PWRCLK_BASE +#define _HAL_LL_ENABLE_CLOCK_PWR_ ((HAL_LL_PWRCLK_BASE) ? (*HAL_LL_PWRCLK_BASE |= 1UL << HAL_LL_PWRCLK_BIT) : 0) +#endif + +/*!< @brief DMA module enable macro. */ +#define HAL_LL_DMA_MODULE_ENABLE(_x) (_x->cr |= 1U << HAL_LL_DMA_CCR_EN_BIT) + +/*!< @brief DMA module disable macro. */ +#define HAL_LL_DMA_MODULE_DISABLE(_x) (_x->cr &= ~(1U << HAL_LL_DMA_CCR_EN_BIT)) + +/*!< @brief Default timeout value to wait when checking if module is disabled/enabled. */ +#define DEFAULT_TIMEOUT_VALUE (0xFFFFU) + +// ----------------------------------------------------------- PRIVATE TYPEDEFS + +/*!< @brief DMA HW register structure. */ +typedef struct dma_handle +{ + volatile uint32_t cr; /*!< DMA channel x configuration register (DMA_CCRx) */ + volatile uint32_t ndtr; /*!< DMA channel x number of data to transfer register (DMA_CNDTRx) */ + volatile uint32_t par; /*!< DMA channel x peripheral address register (DMA_CPARx) */ + volatile uint32_t mar; /*!< DMA channel x memory address register (DMA_CMARx) */ + +} dma_handle_t; + + +typedef struct dmamux_registers +{ + volatile uint32_t dmamux_cr; /*!< DMA interrupt status register */ + +} dmamux_registers_t; + +/*!< @brief DMA HW ISR register structure. */ +typedef struct dma_isr_registers +{ + volatile uint32_t isr; /*!< DMA interrupt status register (DMA_ISR) */ + volatile uint32_t ifcr; /*!< DMA interrupt flag clear register (DMA_IFCR) */ + +} dma_isr_registers_t; + +/*!< @brief DMA HW clock settings structure. */ +typedef struct +{ + uint8_t clock_bit; + hal_ll_base_addr_t clock_base; +} dma_clock_t; + +/*!< @brief DMA control settings structure. */ +typedef struct +{ + dma_clock_t clock; + hal_ll_base_addr_t stream_base; +} dma_control_struct_t; + +// ------------------------------------------------------------------ VARIABLES + +static const dma_control_struct_t dma_controller[ DMA_NUM_OF_MODULES ] = +{ + { + { HAL_LL_DMA1_CLOCK_BIT, HAL_LL_DMA1_CLOCK_BASE }, HAL_LL_DMA1_STREAM_BASE + } + ,{ + { HAL_LL_DMA2_CLOCK_BIT, HAL_LL_DMA2_CLOCK_BASE }, HAL_LL_DMA2_STREAM_BASE + } +}; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS + +/** + * @brief Gets current stream address. + * @details Returns stream address based on @ref module value and + * desired @ref stream value. + * @param[in] module DMA module number. + * @param[in] stream DMA stream number. + * @return hal_ll_base_addr_t stream base register address. + */ +static hal_ll_base_addr_t hal_ll_dma_get_stream_address( uint8_t module, uint8_t stream ); + +/** + * @brief Sets current module clock. + * @details If @ref state is @b true, enables DMA module clock. + * If @ref state is @b false, disables DMA module clock. + * @param[in] dma_obj DMA object. + * @param[in] state Desired state. + * - @b true + * - @b false + * @return Nothing. + */ +static void hal_ll_dma_clock_set( hal_ll_dma_t *dma_obj, bool state ); + +/** + * @brief Initializes DMA module. + * @details Initializes DMA module, stream to + * values from @ref config structure. + * @param[in] dma_obj DMA object. + * @param[in] dma DMA HW handle. + * @param[in] config DMA configuration structure. + * @return hal_ll_err_t Returns initialization state, either success or fail. + */ +static hal_ll_err_t hal_ll_dma_init_hw( hal_ll_dma_t *dma_obj, dma_handle_t *dma, hal_ll_dma_config_t config ); + +/** + * @brief Gets DMA module state. + * @details Checks if current DMA module stream has been stopped. + * Waits for defined @ref DEFAULT_TIMEOUT_VALUE number of cycles + * before jumping out of loop and returning @ref HAL_LL_DMA_ERROR. + * @param[in] dma DMA HW handle. + * @return hal_ll_err_t Returns success or fail. + */ +static inline hal_ll_err_t hal_ll_dma_is_module_disabled( dma_handle_t *dma ); + +/** + * @brief Gets DMA channel. + * @details Returns appropriate value to be set in HW register + * for desired @ref channel. + * @param[in] channel DMA channel number. + * @return uint32_t Returns actual HW register value based on @ref channel. + */ +static inline uint32_t hal_ll_dma_get_reg_value_channel( uint8_t channel ); + +/** + * @brief Gets DMA direction. + * @details Returns appropriate value to be set in HW register + * for desired @ref direction. + * @param[in] direction DMA stream direction. + * Refer to @hal_ll_dma_direction_t for possible values. + * @return uint8_t Returns actual HW register value based on @ref direction. + */ +static inline uint16_t hal_ll_dma_get_reg_value_direction( hal_ll_dma_direction_t direction ); + +/** + * @brief Gets DMA peripheral address increment. + * @details Returns appropriate value to be set in HW register + * for desired @ref set_inc. + * @param[in] set_inc DMA channel peripheral address increment. + * Set to @b true in order to increment address. + * Set to @b false in order to keep address the same. + * @return uint16_t Returns actual HW register value based on @ref set_inc. + */ +static inline uint16_t hal_ll_dma_get_reg_value_dst_inc( bool set_inc ); + +/** + * @brief Gets DMA memory address increment. + * @details Returns appropriate value to be set in HW register + * for desired @ref set_inc. + * @param[in] set_inc DMA channel memory address increment. + * Set to @b true in order to increment address. + * Set to @b false in order to keep address the same. + * @return uint16_t Returns actual HW register value based on @ref set_inc. + */ +static inline uint16_t hal_ll_dma_get_reg_value_src_inc( bool set_inc ); + +/** + * @brief Gets DMA memory address alignment. + * @details Returns appropriate value to be set in HW register + * for desired @ref align. + * @param[in] align DMA channel memory address increment. + * Refer to @ref hal_ll_dma_data_align_t for possible values. + * @return uint16_t Returns actual HW register value based on @ref align. + */ +static inline uint16_t hal_ll_dma_get_reg_value_source_size( hal_ll_dma_data_align_t align ); + +/** + * @brief Gets DMA peripheral address alignment. + * @details Returns appropriate value to be set in HW register + * for desired @ref align. + * @param[in] align DMA channel peripheral address increment. + * Refer to @ref hal_ll_dma_data_align_t for possible values. + * @return uint16_t Returns actual HW register value based on @ref align. + */ +static inline uint16_t hal_ll_dma_get_reg_value_destination_size( hal_ll_dma_data_align_t align ); + +/** + * @brief Gets DMA mode value. + * @details Returns appropriate value to be set in HW register + * for desired @ref mode. + * @param[in] mode DMA mode for object channel. + * Refer to @ref hal_ll_dma_mode_t for possible values. + * @return uint16_t Returns actual HW register value based on @ref mode. + */ +static inline uint16_t hal_ll_dma_get_reg_value_mode( hal_ll_dma_mode_t mode ); + +/** + * @brief Gets DMA priority value. + * @details Returns appropriate value to be set in HW register + * for desired @ref priority. + * @param[in] priority DMA priority for object channel. + * Refer to @ref hal_ll_dma_priority_t for possible values. + * @return uint32_t Returns actual HW register value based on @ref priority. + */ +static inline uint32_t hal_ll_dma_get_reg_value_priority( hal_ll_dma_priority_t priority ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS + +hal_ll_err_t hal_ll_dma_init( hal_ll_dma_t *obj ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + + // Enable PWRCLK. + #ifdef HAL_LL_PWRCLK_BASE + _HAL_LL_ENABLE_CLOCK_PWR_; + #endif + + // Enable current stream clock. + hal_ll_dma_clock_set( obj, true ); + + // Initialize current stream. + obj->handle = hal_ll_dma_get_stream_address( obj->module, obj->stream ); + status = hal_ll_dma_init_hw( obj, + (dma_handle_t *)obj->handle, + obj->config ); + + if ( HAL_LL_DMA_SUCCESS != status ) { + obj->handle = 0; // If initialization failed, reset handle. + } + + return status; +} + +hal_ll_err_t hal_ll_dma_deinit( hal_ll_dma_t *obj ) { + // First abort current transfer. + if ( HAL_LL_DMA_SUCCESS != hal_ll_dma_transfer_abort( obj ) ) + return HAL_LL_DMA_ERROR; + // Finally, disable module clock. + hal_ll_dma_clock_set( obj, false ); + + return HAL_LL_DMA_SUCCESS; +} + +hal_ll_err_t hal_ll_dma_set_mode( hal_ll_dma_t *obj, hal_ll_dma_mode_t mode ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + // Get new mode. + hal_ll_dma_config_t cfg = obj->config; + cfg.mode = mode; + // Disable module first. + HAL_LL_DMA_MODULE_DISABLE( ((dma_handle_t *)obj->handle) ); + // Try to set new mode. + status = hal_ll_dma_init_hw( obj, + (dma_handle_t *)obj->handle, + cfg ); + + return status; +} + +hal_ll_err_t hal_ll_dma_set_direction( hal_ll_dma_t *obj, hal_ll_dma_direction_t direction ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + // Get new direction. + hal_ll_dma_config_t cfg = obj->config; + cfg.direction = direction; + // Disable module first. + HAL_LL_DMA_MODULE_DISABLE( ((dma_handle_t *)obj->handle) ); + // Try to set new value. + status = hal_ll_dma_init_hw( obj, + (dma_handle_t *)obj->handle, + cfg ); + + return status; +} + +hal_ll_err_t hal_ll_dma_set_priority( hal_ll_dma_t *obj, hal_ll_dma_priority_t priority ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + // Get new priority. + hal_ll_dma_config_t cfg = obj->config; + cfg.priority = priority; + // Disable module first. + HAL_LL_DMA_MODULE_DISABLE( ((dma_handle_t *)obj->handle) ); + // Try to set new value. + status = hal_ll_dma_init_hw( obj, + (dma_handle_t *)obj->handle, + cfg ); + + return status; +} + +hal_ll_err_t hal_ll_dma_set_parameters( hal_ll_dma_t *obj, uint32_t addr_src, uint32_t addr_dst, size_t transfer_size, hal_ll_dma_source_memory_region_t src_mem_type ) { + dma_handle_t *dma = (dma_handle_t *)obj->handle; + uint8_t ndtr_divisor; + + // This parameter is not relevant on this architecture. + (void)src_mem_type; + + // Configure DMA Stream data length. + switch ( obj->config.data_align_destination ) { + case HAL_LL_DMA_DATA_ALIGN_BYTES_1: + case HAL_LL_DMA_DATA_ALIGN_BYTES_2: + ndtr_divisor = obj->config.data_align_destination; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_4: + ndtr_divisor = 2; + break; + + default: + return HAL_LL_DMA_ERROR; + } + dma->ndtr = transfer_size >> ndtr_divisor; + + // Memory to Peripheral. + if ( HAL_LL_DMA_DIRECTION_MEMORY_TO_PERIPH == obj->config.direction ) { + // Configure DMA stream destination address. + dma->par = addr_dst; + // Configure DMA stream source address. + dma->mar = addr_src; + } else { // Peripheral to Memory. + // Configure DMA stream source address. + dma->par = addr_src; + // Configure DMA stream destination address. + dma->mar = addr_dst; + } + return HAL_LL_DMA_SUCCESS; +} + +hal_ll_err_t hal_ll_dma_transfer_start( hal_ll_dma_t *obj ) { + HAL_LL_DMA_MODULE_ENABLE( ((dma_handle_t *)obj->handle) ); + return HAL_LL_DMA_SUCCESS; +} + +hal_ll_err_t hal_ll_dma_transfer_stop( hal_ll_dma_t *obj ) { + dma_handle_t *dma = (dma_handle_t *)obj->handle; + uint16_t timeout = DEFAULT_TIMEOUT_VALUE; + + if ( HAL_LL_DMA_MODE_CIRCULAR == obj->config.mode ) + return HAL_LL_DMA_ERROR; + + while ( dma->ndtr ) { + if ( 0 == timeout-- ) + return HAL_LL_DMA_ERROR; + } + + HAL_LL_DMA_MODULE_DISABLE( dma ); + + return HAL_LL_DMA_SUCCESS; +} + +hal_ll_err_t hal_ll_dma_transfer_abort( hal_ll_dma_t *obj ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + dma_handle_t *dma = (dma_handle_t *)obj->handle; + + // Calculate DMA base and stream number. + dma_isr_registers_t *regs = (dma_isr_registers_t *)(dma_controller[obj->module].stream_base - CCR_BASE_OFFSET); + + // Disable all the transfer interrupts. + dma->cr &= ~(HAL_LL_DMA_CCR_TCIE_BIT | HAL_LL_DMA_CCR_HTIE_BIT | HAL_LL_DMA_CCR_TEIE_BIT); + + // Disable the stream. + HAL_LL_DMA_MODULE_DISABLE( dma ); + + // Wait for bit to be cleared. + status = hal_ll_dma_is_module_disabled( dma ); + + // Clear all interrupt flags at correct offset within the register. + if ( HAL_LL_DMA_SUCCESS == status ) + regs->ifcr = HAL_LL_DMA_IT_CLEAR_MASK << ( obj->stream * 4 ); + + return status; +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS + +static hal_ll_base_addr_t hal_ll_dma_get_stream_address( uint8_t module, uint8_t stream ) { + return ((hal_ll_base_addr_t)dma_controller[module].stream_base + (hal_ll_base_addr_t)(STREAM_BASE_OFFSET * (stream))); +} + +static void hal_ll_dma_clock_set( hal_ll_dma_t *obj, bool state ) { + if ( state ) { + set_reg_bit( (uint32_t *)dma_controller[obj->module].clock.clock_base, + dma_controller[obj->module].clock.clock_bit ); + set_reg_bit( (uint32_t *)dma_controller[obj->module].clock.clock_base, HAL_LL_DMAMUX1_CLOCK_BIT); + } else { + clear_reg_bit( (uint32_t *)dma_controller[obj->module].clock.clock_base, + dma_controller[obj->module].clock.clock_bit ); + } +} + +static hal_ll_err_t hal_ll_dma_init_hw( hal_ll_dma_t *obj, dma_handle_t *dma, hal_ll_dma_config_t config ) { + volatile uint32_t tmp = 0UL; + // Check if user entered invalid data aka HAL_LL_DMA_DATA_ALIGN_BYTES_3 + if (HAL_LL_DMA_DATA_ALIGN_BYTES_3 == config.data_align_source || HAL_LL_DMA_DATA_ALIGN_BYTES_3 == config.data_align_destination ) { + return HAL_LL_DMA_ERROR; + } + + // Disable the peripheral first. + HAL_LL_DMA_MODULE_DISABLE(dma); + + // Wait for bit to be cleared. + if ( HAL_LL_DMA_ERROR == hal_ll_dma_is_module_disabled( dma ) ) + return HAL_LL_DMA_ERROR; + + // Get the CR register value. + tmp = dma->cr; + + // Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits. + tmp &= ((uint32_t)~( HAL_LL_DMA_CCR_EN_BIT | HAL_LL_DMA_CCR_TCIE_BIT | HAL_LL_DMA_CCR_HTIE_BIT | \ + HAL_LL_DMA_CCR_TEIE_BIT | HAL_LL_DMA_CCR_DIR_BIT | HAL_LL_DMA_CCR_CIRC_BIT | \ + HAL_LL_DMA_CCR_PINC_BIT | HAL_LL_DMA_CCR_MINC_BIT | HAL_LL_DMA_CCR_M2M_BIT | \ + HAL_LL_DMA_CCR_PSIZE_MASK | HAL_LL_DMA_CCR_MSIZE_MASK | HAL_LL_DMA_CCR_PRIO_MASK )); + + // BEGIN Prepare the DMA stream configuration. + // Set desired direction value. + tmp |= hal_ll_dma_get_reg_value_direction(config.direction); + // Set desired memory increment settings. + tmp |= hal_ll_dma_get_reg_value_src_inc(config.src_inc); + tmp |= hal_ll_dma_get_reg_value_dst_inc(config.dst_inc); + // Set desired data size settings. + tmp |= hal_ll_dma_get_reg_value_source_size(config.data_align_source); + tmp |= hal_ll_dma_get_reg_value_destination_size(config.data_align_destination); + // Set desired mode. + tmp |= hal_ll_dma_get_reg_value_mode(config.mode); + // Finally, set desired priority. + tmp |= hal_ll_dma_get_reg_value_priority(config.priority); + + // And then write to DMA stream CR register. + dma->cr = tmp; + + if (obj->module == 0 ) { + dmamux_registers_t * dmamux = (dmamux_registers_t*)( DMAMUX1_BASE + ( obj->stream * DMAMUX1_OFFSET ) ); + dmamux->dmamux_cr |= obj->channel; + } else { + dmamux_registers_t * dmamux = (dmamux_registers_t*)( DMAMUX1_BASE + ( DMA_NUM_OF_STREAMS * DMAMUX1_OFFSET ) + ( obj->stream * DMAMUX1_OFFSET ) ); + dmamux->dmamux_cr |= obj->channel; + } + + return HAL_LL_DMA_SUCCESS; +} + +static inline hal_ll_err_t hal_ll_dma_is_module_disabled( dma_handle_t *dma ) { + uint16_t timeout = DEFAULT_TIMEOUT_VALUE; + + while ( (dma->cr & (1U << HAL_LL_DMA_CCR_EN_BIT)) != 0 ) { + if ( 0 == timeout-- ) + return HAL_LL_DMA_ERROR; + } + + return HAL_LL_DMA_SUCCESS; +} + +static inline uint16_t hal_ll_dma_get_reg_value_direction( hal_ll_dma_direction_t direction ) { + volatile uint16_t direction_set = (uint8_t)HAL_LL_DMA_DIRECTION_MEMORY_TO_MEMORY; + + switch ( direction ) + { + case HAL_LL_DMA_DIRECTION_MEMORY_TO_MEMORY: + direction_set = HAL_LL_DMA_DIRECTION_MEMORY_TO_MEMORY_MASK; + break; + case HAL_LL_DMA_DIRECTION_MEMORY_TO_PERIPH: + direction_set = HAL_LL_DMA_DIRECTION_MEMORY_TO_PERIPH_MASK; + break; + case HAL_LL_DMA_DIRECTION_PERIPH_TO_MEMORY: + direction_set = HAL_LL_DMA_DIRECTION_PERIPH_TO_MEMORY_MASK; + break; + + default: + break; + } + + return (uint16_t)direction_set; +} + +static inline uint16_t hal_ll_dma_get_reg_value_dst_inc( bool set_inc ) { + return (uint16_t)((set_inc) ? (HAL_LL_DMA_PINC_MASK) : (0)); +} + +static inline uint16_t hal_ll_dma_get_reg_value_src_inc( bool set_inc ) { + return (uint16_t)((set_inc) ? (HAL_LL_DMA_MINC_MASK) : (0)); +} + +static inline uint16_t hal_ll_dma_get_reg_value_source_size( hal_ll_dma_data_align_t align ) { + volatile uint16_t align_set = (uint16_t)HAL_LL_DMA_DATA_ALIGN_BYTES_1; + + switch ( align ) + { + case HAL_LL_DMA_DATA_ALIGN_BYTES_1: + align_set = HAL_LL_DMA_MSIZE_BYTE_MASK; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_2: + align_set = HAL_LL_DMA_MSIZE_HALFWORD_MASK; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_4: + align_set = HAL_LL_DMA_MSIZE_WORD_MASK; + break; + + default: + break; + } + + return (uint16_t)align_set; +} + +static inline uint16_t hal_ll_dma_get_reg_value_destination_size( hal_ll_dma_data_align_t align ) { + volatile uint16_t align_set = (uint16_t)HAL_LL_DMA_DATA_ALIGN_BYTES_1; + + switch ( align ) + { + case HAL_LL_DMA_DATA_ALIGN_BYTES_1: + align_set = HAL_LL_DMA_CCR_PSIZE_BYTE_MASK; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_2: + align_set = HAL_LL_DMA_CCR_PSIZE_HALFWORD_MASK; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_4: + align_set = HAL_LL_DMA_CCR_PSIZE_WORD_MASK; + break; + + default: + break; + } + + return (uint16_t)align_set; +} + +static inline uint16_t hal_ll_dma_get_reg_value_mode( hal_ll_dma_mode_t mode ) { + return (uint16_t)((mode) ? (HAL_LL_DMA_CCR_CIRC_MASK) : (0)); +} + +static inline uint32_t hal_ll_dma_get_reg_value_priority( hal_ll_dma_priority_t priority ) { + volatile uint32_t priority_set = (uint32_t)HAL_LL_DMA_PRIORITY_LOW; + + switch ( priority ) + { + case HAL_LL_DMA_PRIORITY_LOW: + priority_set = HAL_LL_DMA_CCR_PRIORITY_LOW_MASK; + break; + case HAL_LL_DMA_PRIORITY_MEDIUM: + priority_set = HAL_LL_DMA_CCR_PRIORITY_MEDIUM_MASK; + break; + case HAL_LL_DMA_PRIORITY_HIGH: + priority_set = HAL_LL_DMA_CCR_PRIORITY_HIGH_MASK; + break; + case HAL_LL_DMA_PRIORITY_VERY_HIGH: + priority_set = HAL_LL_DMA_CCR_PRIORITY_VERY_HIGH_MASK; + break; + + default: + break; + } + + return (uint32_t)priority_set; +} + +// ------------------------------------------------------------------------- END + + + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_80/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_80/CMakeLists.cmake new file mode 100644 index 000000000..4bf531636 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_80/CMakeLists.cmake @@ -0,0 +1,8 @@ +if(${MCU_NAME} MATCHES "^STM32G0B1CB$|^STM32G0B1KB$|^STM32G0B1MB$|^STM32G0B1RB$|^STM32G0B1VB$|^STM32G0B1CC$|^STM32G0B1KC$|^STM32G0B1MC$|^STM32G0B1RC$|^STM32G0B1VC$|^STM32G0B1CE$|^STM32G0B1KE$|^STM32G0B1ME$|^STM32G0B1NE$|^STM32G0B1RE$|^STM32G0B1VE$") + set(dma_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_dma.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_80") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_80") + list(APPEND hal_ll_def_list "STM32G0xx") + list(APPEND hal_ll_def_list "STM32G0Bxx") + list(APPEND hal_ll_def_list "STM32G0B1xx") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_80/hal_ll_dma.c b/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_80/hal_ll_dma.c new file mode 100644 index 000000000..cf0165bba --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_80/hal_ll_dma.c @@ -0,0 +1,657 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_dma.c + * @brief DMA HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_rcc.h" +#include "hal_ll_dma.h" +#include "hal_ll_gpio.h" + +// ------------------------------------------------------------- PRIVATE MACROS + +#define MODULE_SUPPORTED + +/*!< @brief DMA interrupt definitions. */ +#define HAL_LL_DMA_IT_FT ((uint32_t)(1U << 1)) +#define HAL_LL_DMA_IT_HT ((uint32_t)(1U << 2)) +#define HAL_LL_DMA_IT_ET ((uint32_t)(1U << 3)) +#define HAL_LL_DMA_IT_CLEAR_MASK (0x0fUL) + +#define HAL_LL_DMA_CCR_PRIORITY_VERY_HIGH_MASK (0x00003000) +#define HAL_LL_DMA_CCR_PRIORITY_HIGH_MASK (0x00002000) +#define HAL_LL_DMA_CCR_PRIORITY_MEDIUM_MASK (0x00001000) +#define HAL_LL_DMA_CCR_PRIORITY_LOW_MASK (0x00000000) +#define HAL_LL_DMA_CCR_CIRC_MASK (0x00000020) +#define HAL_LL_DMA_CCR_PSIZE_BYTE_MASK (0x00000000) +#define HAL_LL_DMA_CCR_PSIZE_HALFWORD_MASK (0x00000100) +#define HAL_LL_DMA_CCR_PSIZE_WORD_MASK (0x00000200) +#define HAL_LL_DMA_MSIZE_BYTE_MASK (0x00000000) +#define HAL_LL_DMA_MSIZE_HALFWORD_MASK (0x00000400) +#define HAL_LL_DMA_MSIZE_WORD_MASK (0x00000800) +#define HAL_LL_DMA_MINC_MASK (0x00000080) +#define HAL_LL_DMA_PINC_MASK (0x00000040) + +#define HAL_LL_DMA_DIRECTION_MEMORY_TO_MEMORY_MASK (0x4000) +#define HAL_LL_DMA_DIRECTION_MEMORY_TO_PERIPH_MASK (0x10) +#define HAL_LL_DMA_DIRECTION_PERIPH_TO_MEMORY_MASK (0x0) + +#define HAL_LL_DMA_CCR_PSIZE_MASK (0x00000300) +#define HAL_LL_DMA_CCR_MSIZE_MASK (0x00000C00) +#define HAL_LL_DMA_CCR_PRIO_MASK (0x00003000) +#define HAL_LL_DMA_CCR_EN_BIT (0) +#define HAL_LL_DMA_CCR_TEIE_BIT (3) +#define HAL_LL_DMA_CCR_HTIE_BIT (2) +#define HAL_LL_DMA_CCR_TCIE_BIT (1) +#define HAL_LL_DMA_CCR_DIR_BIT (4) +#define HAL_LL_DMA_CCR_CIRC_BIT (5) +#define HAL_LL_DMA_CCR_PINC_BIT (6) +#define HAL_LL_DMA_CCR_MINC_BIT (7) +#define HAL_LL_DMA_CCR_M2M_BIT (14) + +#ifdef MODULE_SUPPORTED + #define DMA1_BASE (0x40020000UL) + #define DMA2_BASE (0x40020400UL) + + #define HAL_LL_DMA1_CLOCK_BIT (0) + #define HAL_LL_DMA1_CLOCK_BASE ((uint32_t)_RCC_AHBENR) + #define HAL_LL_DMA1_STREAM_BASE (DMA1_BASE + CCR_BASE_OFFSET) + #define HAL_LL_DMA2_CLOCK_BIT (1) + #define HAL_LL_DMA2_CLOCK_BASE ((uint32_t)_RCC_AHBENR) + #define HAL_LL_DMA2_STREAM_BASE (DMA2_BASE + CCR_BASE_OFFSET) + #define HAL_LL_DMA1_CLOCK_BIT (0) + + #define CCR_BASE_OFFSET (0x8U) + #define STREAM_BASE_OFFSET (0x14U) + #define IFCR_BASE_OFFSET (0x4U) + #define HAL_LL_PWRCLK_BIT (28) + + /*diff bits/offsets:*/ + #define HAL_LL_PWRCLK_BASE (_RCC_APBENR1) + + #define DMAMUX1_BASE (0x40020800UL) + #define DMAMUX1_OFFSET (0x04U) + #define HAL_LL_DMAMUX1_CLOCK_BIT (2) +#endif + +/*!< @brief Clock enable macros. */ +#ifdef HAL_LL_PWRCLK_BASE +#define _HAL_LL_ENABLE_CLOCK_PWR_ ((HAL_LL_PWRCLK_BASE) ? (*HAL_LL_PWRCLK_BASE |= 1UL << HAL_LL_PWRCLK_BIT) : 0) +#endif + +/*!< @brief DMA module enable macro. */ +#define HAL_LL_DMA_MODULE_ENABLE(_x) (_x->cr |= 1U << HAL_LL_DMA_CCR_EN_BIT) + +/*!< @brief DMA module disable macro. */ +#define HAL_LL_DMA_MODULE_DISABLE(_x) (_x->cr &= ~(1U << HAL_LL_DMA_CCR_EN_BIT)) + +/*!< @brief Default timeout value to wait when checking if module is disabled/enabled. */ +#define DEFAULT_TIMEOUT_VALUE (0xFFFFU) + +// ----------------------------------------------------------- PRIVATE TYPEDEFS + +/*!< @brief DMA HW register structure. */ +typedef struct dma_handle +{ + volatile uint32_t cr; /*!< DMA channel x configuration register (DMA_CCRx) */ + volatile uint32_t ndtr; /*!< DMA channel x number of data to transfer register (DMA_CNDTRx) */ + volatile uint32_t par; /*!< DMA channel x peripheral address register (DMA_CPARx) */ + volatile uint32_t mar; /*!< DMA channel x memory address register (DMA_CMARx) */ +} dma_handle_t; + +typedef struct dmamux_registers +{ + volatile uint32_t dmamux_cr; /*!< DMA interrupt status register */ +} dmamux_registers_t; + +/*!< @brief DMA HW ISR register structure. */ +typedef struct dma_isr_registers +{ + volatile uint32_t isr; /*!< DMA interrupt status register (DMA_ISR) */ + volatile uint32_t ifcr; /*!< DMA interrupt flag clear register (DMA_IFCR) */ +} dma_isr_registers_t; + +/*!< @brief DMA HW clock settings structure. */ +typedef struct +{ + uint8_t clock_bit; + hal_ll_base_addr_t clock_base; +} dma_clock_t; + +/*!< @brief DMA control settings structure. */ +typedef struct +{ + dma_clock_t clock; + hal_ll_base_addr_t stream_base; +} dma_control_struct_t; + +// ------------------------------------------------------------------ VARIABLES + +static const dma_control_struct_t dma_controller[ DMA_NUM_OF_MODULES ] = +{ + { + { HAL_LL_DMA1_CLOCK_BIT, HAL_LL_DMA1_CLOCK_BASE }, HAL_LL_DMA1_STREAM_BASE + } + ,{ + { HAL_LL_DMA2_CLOCK_BIT, HAL_LL_DMA2_CLOCK_BASE }, HAL_LL_DMA2_STREAM_BASE + } + ,{ + { HAL_LL_DMA1_CLOCK_BIT, HAL_LL_DMA1_CLOCK_BASE }, HAL_LL_DMA1_STREAM_BASE + } + ,{ + { HAL_LL_DMA2_CLOCK_BIT, HAL_LL_DMA2_CLOCK_BASE }, HAL_LL_DMA2_STREAM_BASE + } + ,{ + { HAL_LL_DMA1_CLOCK_BIT, HAL_LL_DMA1_CLOCK_BASE }, HAL_LL_DMA1_STREAM_BASE + } +}; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS + +/** + * @brief Gets current stream address. + * @details Returns stream address based on @ref module value and + * desired @ref stream value. + * @param[in] module DMA module number. + * @param[in] stream DMA stream number. + * @return hal_ll_base_addr_t stream base register address. + */ +static hal_ll_base_addr_t hal_ll_dma_get_stream_address( uint8_t module, uint8_t stream ); + +/** + * @brief Sets current module clock. + * @details If @ref state is @b true, enables DMA module clock. + * If @ref state is @b false, disables DMA module clock. + * @param[in] dma_obj DMA object. + * @param[in] state Desired state. + * - @b true + * - @b false + * @return Nothing. + */ +static void hal_ll_dma_clock_set( hal_ll_dma_t *dma_obj, bool state ); + +/** + * @brief Initializes DMA module. + * @details Initializes DMA module, stream to + * values from @ref config structure. + * @param[in] dma_obj DMA object. + * @param[in] dma DMA HW handle. + * @param[in] config DMA configuration structure. + * @return hal_ll_err_t Returns initialization state, either success or fail. + */ +static hal_ll_err_t hal_ll_dma_init_hw( hal_ll_dma_t *dma_obj, dma_handle_t *dma, hal_ll_dma_config_t config ); + +/** + * @brief Gets DMA module state. + * @details Checks if current DMA module stream has been stopped. + * Waits for defined @ref DEFAULT_TIMEOUT_VALUE number of cycles + * before jumping out of loop and returning @ref HAL_LL_DMA_ERROR. + * @param[in] dma DMA HW handle. + * @return hal_ll_err_t Returns success or fail. + */ +static inline hal_ll_err_t hal_ll_dma_is_module_disabled( dma_handle_t *dma ); + +/** + * @brief Gets DMA channel. + * @details Returns appropriate value to be set in HW register + * for desired @ref channel. + * @param[in] channel DMA channel number. + * @return uint32_t Returns actual HW register value based on @ref channel. + */ +static inline uint32_t hal_ll_dma_get_reg_value_channel( uint8_t channel ); + +/** + * @brief Gets DMA direction. + * @details Returns appropriate value to be set in HW register + * for desired @ref direction. + * @param[in] direction DMA stream direction. + * Refer to @hal_ll_dma_direction_t for possible values. + * @return uint8_t Returns actual HW register value based on @ref direction. + */ +static inline uint16_t hal_ll_dma_get_reg_value_direction( hal_ll_dma_direction_t direction ); + +/** + * @brief Gets DMA peripheral address increment. + * @details Returns appropriate value to be set in HW register + * for desired @ref set_inc. + * @param[in] set_inc DMA channel peripheral address increment. + * Set to @b true in order to increment address. + * Set to @b false in order to keep address the same. + * @return uint16_t Returns actual HW register value based on @ref set_inc. + */ +static inline uint16_t hal_ll_dma_get_reg_value_dst_inc( bool set_inc ); + +/** + * @brief Gets DMA memory address increment. + * @details Returns appropriate value to be set in HW register + * for desired @ref set_inc. + * @param[in] set_inc DMA channel memory address increment. + * Set to @b true in order to increment address. + * Set to @b false in order to keep address the same. + * @return uint16_t Returns actual HW register value based on @ref set_inc. + */ +static inline uint16_t hal_ll_dma_get_reg_value_src_inc( bool set_inc ); + +/** + * @brief Gets DMA memory address alignment. + * @details Returns appropriate value to be set in HW register + * for desired @ref align. + * @param[in] align DMA channel memory address increment. + * Refer to @ref hal_ll_dma_data_align_t for possible values. + * @return uint16_t Returns actual HW register value based on @ref align. + */ +static inline uint16_t hal_ll_dma_get_reg_value_source_size( hal_ll_dma_data_align_t align ); + +/** + * @brief Gets DMA peripheral address alignment. + * @details Returns appropriate value to be set in HW register + * for desired @ref align. + * @param[in] align DMA channel peripheral address increment. + * Refer to @ref hal_ll_dma_data_align_t for possible values. + * @return uint16_t Returns actual HW register value based on @ref align. + */ +static inline uint16_t hal_ll_dma_get_reg_value_destination_size( hal_ll_dma_data_align_t align ); + +/** + * @brief Gets DMA mode value. + * @details Returns appropriate value to be set in HW register + * for desired @ref mode. + * @param[in] mode DMA mode for object channel. + * Refer to @ref hal_ll_dma_mode_t for possible values. + * @return uint16_t Returns actual HW register value based on @ref mode. + */ +static inline uint16_t hal_ll_dma_get_reg_value_mode( hal_ll_dma_mode_t mode ); + +/** + * @brief Gets DMA priority value. + * @details Returns appropriate value to be set in HW register + * for desired @ref priority. + * @param[in] priority DMA priority for object channel. + * Refer to @ref hal_ll_dma_priority_t for possible values. + * @return uint32_t Returns actual HW register value based on @ref priority. + */ +static inline uint32_t hal_ll_dma_get_reg_value_priority( hal_ll_dma_priority_t priority ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS + +hal_ll_err_t hal_ll_dma_init( hal_ll_dma_t *obj ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + + // Enable PWRCLK. + #ifdef HAL_LL_PWRCLK_BASE + _HAL_LL_ENABLE_CLOCK_PWR_; + #endif + + // Enable current stream clock. + hal_ll_dma_clock_set( obj, true ); + + // Initialize current stream. + obj->handle = hal_ll_dma_get_stream_address( obj->module, obj->stream ); + status = hal_ll_dma_init_hw( obj, + (dma_handle_t *)obj->handle, + obj->config ); + + if ( HAL_LL_DMA_SUCCESS != status ) { + obj->handle = 0; // If initialization failed, reset handle. + } + + return status; +} + +hal_ll_err_t hal_ll_dma_deinit( hal_ll_dma_t *obj ) { + // First abort current transfer. + if ( HAL_LL_DMA_SUCCESS != hal_ll_dma_transfer_abort( obj ) ) + return HAL_LL_DMA_ERROR; + // Finally, disable module clock. + hal_ll_dma_clock_set( obj, false ); + + return HAL_LL_DMA_SUCCESS; +} + +hal_ll_err_t hal_ll_dma_set_mode( hal_ll_dma_t *obj, hal_ll_dma_mode_t mode ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + // Get new mode. + hal_ll_dma_config_t cfg = obj->config; + cfg.mode = mode; + // Disable module first. + HAL_LL_DMA_MODULE_DISABLE( ((dma_handle_t *)obj->handle) ); + // Try to set new mode. + status = hal_ll_dma_init_hw( obj, + (dma_handle_t *)obj->handle, + cfg ); + + return status; +} + +hal_ll_err_t hal_ll_dma_set_direction( hal_ll_dma_t *obj, hal_ll_dma_direction_t direction ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + // Get new direction. + hal_ll_dma_config_t cfg = obj->config; + cfg.direction = direction; + // Disable module first. + HAL_LL_DMA_MODULE_DISABLE( ((dma_handle_t *)obj->handle) ); + // Try to set new value. + status = hal_ll_dma_init_hw( obj, + (dma_handle_t *)obj->handle, + cfg ); + + return status; +} + +hal_ll_err_t hal_ll_dma_set_priority( hal_ll_dma_t *obj, hal_ll_dma_priority_t priority ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + // Get new priority. + hal_ll_dma_config_t cfg = obj->config; + cfg.priority = priority; + // Disable module first. + HAL_LL_DMA_MODULE_DISABLE( ((dma_handle_t *)obj->handle) ); + // Try to set new value. + status = hal_ll_dma_init_hw( obj, + (dma_handle_t *)obj->handle, + cfg ); + + return status; +} + +hal_ll_err_t hal_ll_dma_set_parameters( hal_ll_dma_t *obj, uint32_t addr_src, uint32_t addr_dst, size_t transfer_size, hal_ll_dma_source_memory_region_t src_mem_type ) { + dma_handle_t *dma = (dma_handle_t *)obj->handle; + uint8_t ndtr_divisor; + + // This parameter is not relevant on this architecture. + (void)src_mem_type; + + // Configure DMA Stream data length. + switch ( obj->config.data_align_destination ) { + case HAL_LL_DMA_DATA_ALIGN_BYTES_1: + case HAL_LL_DMA_DATA_ALIGN_BYTES_2: + ndtr_divisor = obj->config.data_align_destination; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_4: + ndtr_divisor = 2; + break; + + default: + return HAL_LL_DMA_ERROR; + } + dma->ndtr = transfer_size >> ndtr_divisor; + + // Memory to Peripheral. + if ( HAL_LL_DMA_DIRECTION_MEMORY_TO_PERIPH == obj->config.direction ) { + // Configure DMA stream destination address. + dma->par = addr_dst; + // Configure DMA stream source address. + dma->mar = addr_src; + } else { // Peripheral to Memory. + // Configure DMA stream source address. + dma->par = addr_src; + // Configure DMA stream destination address. + dma->mar = addr_dst; + } + return HAL_LL_DMA_SUCCESS; +} + +hal_ll_err_t hal_ll_dma_transfer_start( hal_ll_dma_t *obj ) { + HAL_LL_DMA_MODULE_ENABLE( ((dma_handle_t *)obj->handle) ); + return HAL_LL_DMA_SUCCESS; +} + +hal_ll_err_t hal_ll_dma_transfer_stop( hal_ll_dma_t *obj ) { + dma_handle_t *dma = (dma_handle_t *)obj->handle; + uint16_t timeout = DEFAULT_TIMEOUT_VALUE; + + if ( HAL_LL_DMA_MODE_CIRCULAR == obj->config.mode ) + return HAL_LL_DMA_ERROR; + + while ( dma->ndtr ) { + if ( 0 == timeout-- ) + return HAL_LL_DMA_ERROR; + } + + HAL_LL_DMA_MODULE_DISABLE( dma ); + + return HAL_LL_DMA_SUCCESS; +} + +hal_ll_err_t hal_ll_dma_transfer_abort( hal_ll_dma_t *obj ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + dma_handle_t *dma = (dma_handle_t *)obj->handle; + + // Calculate DMA base and stream number. + dma_isr_registers_t *regs = (dma_isr_registers_t *)(dma_controller[obj->module].stream_base - CCR_BASE_OFFSET); + + // Disable all the transfer interrupts. + dma->cr &= ~(HAL_LL_DMA_CCR_TCIE_BIT | HAL_LL_DMA_CCR_HTIE_BIT | HAL_LL_DMA_CCR_TEIE_BIT); + + // Disable the stream. + HAL_LL_DMA_MODULE_DISABLE( dma ); + + // Wait for bit to be cleared. + status = hal_ll_dma_is_module_disabled( dma ); + + // Clear all interrupt flags at correct offset within the register. + if ( HAL_LL_DMA_SUCCESS == status ) + regs->ifcr = HAL_LL_DMA_IT_CLEAR_MASK << ( obj->stream * 4 ); + + return status; +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS + +static hal_ll_base_addr_t hal_ll_dma_get_stream_address( uint8_t module, uint8_t stream ) { + return ((hal_ll_base_addr_t)dma_controller[module].stream_base + (hal_ll_base_addr_t)(STREAM_BASE_OFFSET * (stream))); +} + +static void hal_ll_dma_clock_set( hal_ll_dma_t *obj, bool state ) { + if ( state ) { + set_reg_bit( (uint32_t *)dma_controller[obj->module].clock.clock_base, + dma_controller[obj->module].clock.clock_bit ); + set_reg_bit( (uint32_t *)dma_controller[obj->module].clock.clock_base, HAL_LL_DMAMUX1_CLOCK_BIT); + } else { + clear_reg_bit( (uint32_t *)dma_controller[obj->module].clock.clock_base, + dma_controller[obj->module].clock.clock_bit ); + } +} + +static hal_ll_err_t hal_ll_dma_init_hw( hal_ll_dma_t *obj, dma_handle_t *dma, hal_ll_dma_config_t config ) { + volatile uint32_t tmp = 0UL; + // Check if user entered invalid data aka HAL_LL_DMA_DATA_ALIGN_BYTES_3 + if (HAL_LL_DMA_DATA_ALIGN_BYTES_3 == config.data_align_source || HAL_LL_DMA_DATA_ALIGN_BYTES_3 == config.data_align_destination ) { + return HAL_LL_DMA_ERROR; + } + + // Disable the peripheral first. + HAL_LL_DMA_MODULE_DISABLE(dma); + + // Wait for bit to be cleared. + if ( HAL_LL_DMA_ERROR == hal_ll_dma_is_module_disabled( dma ) ) + return HAL_LL_DMA_ERROR; + + // Get the CR register value. + tmp = dma->cr; + + // Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits. + tmp &= ((uint32_t)~( HAL_LL_DMA_CCR_EN_BIT | HAL_LL_DMA_CCR_TCIE_BIT | HAL_LL_DMA_CCR_HTIE_BIT | \ + HAL_LL_DMA_CCR_TEIE_BIT | HAL_LL_DMA_CCR_DIR_BIT | HAL_LL_DMA_CCR_CIRC_BIT | \ + HAL_LL_DMA_CCR_PINC_BIT | HAL_LL_DMA_CCR_MINC_BIT | HAL_LL_DMA_CCR_M2M_BIT | \ + HAL_LL_DMA_CCR_PSIZE_MASK | HAL_LL_DMA_CCR_MSIZE_MASK | HAL_LL_DMA_CCR_PRIO_MASK )); + + // BEGIN Prepare the DMA stream configuration. + // Set desired direction value. + tmp |= hal_ll_dma_get_reg_value_direction(config.direction); + // Set desired memory increment settings. + tmp |= hal_ll_dma_get_reg_value_src_inc(config.src_inc); + tmp |= hal_ll_dma_get_reg_value_dst_inc(config.dst_inc); + // Set desired data size settings. + tmp |= hal_ll_dma_get_reg_value_source_size(config.data_align_source); + tmp |= hal_ll_dma_get_reg_value_destination_size(config.data_align_destination); + // Set desired mode. + tmp |= hal_ll_dma_get_reg_value_mode(config.mode); + // Finally, set desired priority. + tmp |= hal_ll_dma_get_reg_value_priority(config.priority); + + // And then write to DMA stream CR register. + dma->cr = tmp; + + if (obj->module == 0 ) { + dmamux_registers_t * dmamux = (dmamux_registers_t*)( DMAMUX1_BASE + ( obj->stream * DMAMUX1_OFFSET ) ); + dmamux->dmamux_cr |= obj->channel; + } else { + dmamux_registers_t * dmamux = (dmamux_registers_t*)( DMAMUX1_BASE + 0x20 + ( obj->stream * DMAMUX1_OFFSET ) ); + dmamux->dmamux_cr |= obj->channel; + } + + return HAL_LL_DMA_SUCCESS; +} + +static inline hal_ll_err_t hal_ll_dma_is_module_disabled( dma_handle_t *dma ) { + uint16_t timeout = DEFAULT_TIMEOUT_VALUE; + + while ( (dma->cr & (1U << HAL_LL_DMA_CCR_EN_BIT)) != 0 ) { + if ( 0 == timeout-- ) + return HAL_LL_DMA_ERROR; + } + + return HAL_LL_DMA_SUCCESS; +} + +static inline uint16_t hal_ll_dma_get_reg_value_direction( hal_ll_dma_direction_t direction ) { + volatile uint16_t direction_set = (uint8_t)HAL_LL_DMA_DIRECTION_MEMORY_TO_MEMORY; + + switch ( direction ) + { + case HAL_LL_DMA_DIRECTION_MEMORY_TO_MEMORY: + direction_set = HAL_LL_DMA_DIRECTION_MEMORY_TO_MEMORY_MASK; + break; + case HAL_LL_DMA_DIRECTION_MEMORY_TO_PERIPH: + direction_set = HAL_LL_DMA_DIRECTION_MEMORY_TO_PERIPH_MASK; + break; + case HAL_LL_DMA_DIRECTION_PERIPH_TO_MEMORY: + direction_set = HAL_LL_DMA_DIRECTION_PERIPH_TO_MEMORY_MASK; + break; + + default: + break; + } + + return (uint16_t)direction_set; +} + +static inline uint16_t hal_ll_dma_get_reg_value_dst_inc( bool set_inc ) { + return (uint16_t)((set_inc) ? (HAL_LL_DMA_PINC_MASK) : (0)); +} + +static inline uint16_t hal_ll_dma_get_reg_value_src_inc( bool set_inc ) { + return (uint16_t)((set_inc) ? (HAL_LL_DMA_MINC_MASK) : (0)); +} + +static inline uint16_t hal_ll_dma_get_reg_value_source_size( hal_ll_dma_data_align_t align ) { + volatile uint16_t align_set = (uint16_t)HAL_LL_DMA_DATA_ALIGN_BYTES_1; + + switch ( align ) + { + case HAL_LL_DMA_DATA_ALIGN_BYTES_1: + align_set = HAL_LL_DMA_MSIZE_BYTE_MASK; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_2: + align_set = HAL_LL_DMA_MSIZE_HALFWORD_MASK; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_4: + align_set = HAL_LL_DMA_MSIZE_WORD_MASK; + break; + + default: + break; + } + + return (uint16_t)align_set; +} + +static inline uint16_t hal_ll_dma_get_reg_value_destination_size( hal_ll_dma_data_align_t align ) { + volatile uint16_t align_set = (uint16_t)HAL_LL_DMA_DATA_ALIGN_BYTES_1; + + switch ( align ) + { + case HAL_LL_DMA_DATA_ALIGN_BYTES_1: + align_set = HAL_LL_DMA_CCR_PSIZE_BYTE_MASK; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_2: + align_set = HAL_LL_DMA_CCR_PSIZE_HALFWORD_MASK; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_4: + align_set = HAL_LL_DMA_CCR_PSIZE_WORD_MASK; + break; + + default: + break; + } + + return (uint16_t)align_set; +} + +static inline uint16_t hal_ll_dma_get_reg_value_mode( hal_ll_dma_mode_t mode ) { + return (uint16_t)((mode) ? (HAL_LL_DMA_CCR_CIRC_MASK) : (0)); +} + +static inline uint32_t hal_ll_dma_get_reg_value_priority( hal_ll_dma_priority_t priority ) { + volatile uint32_t priority_set = (uint32_t)HAL_LL_DMA_PRIORITY_LOW; + + switch ( priority ) + { + case HAL_LL_DMA_PRIORITY_LOW: + priority_set = HAL_LL_DMA_CCR_PRIORITY_LOW_MASK; + break; + case HAL_LL_DMA_PRIORITY_MEDIUM: + priority_set = HAL_LL_DMA_CCR_PRIORITY_MEDIUM_MASK; + break; + case HAL_LL_DMA_PRIORITY_HIGH: + priority_set = HAL_LL_DMA_CCR_PRIORITY_HIGH_MASK; + break; + case HAL_LL_DMA_PRIORITY_VERY_HIGH: + priority_set = HAL_LL_DMA_CCR_PRIORITY_VERY_HIGH_MASK; + break; + + default: + break; + } + + return (uint32_t)priority_set; +} + +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_81/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_81/CMakeLists.cmake new file mode 100644 index 000000000..ba6617546 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_81/CMakeLists.cmake @@ -0,0 +1,8 @@ +if(${MCU_NAME} MATCHES "^STM32G0C1CC$|^STM32G0C1KC$|^STM32G0C1MC$|^STM32G0C1RC$|^STM32G0C1VC$|^STM32G0C1CE$|^STM32G0C1KE$|^STM32G0C1ME$|^STM32G0C1NE$|^STM32G0C1RE$|^STM32G0C1VE$") + set(dma_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_dma.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_81") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_81") + list(APPEND hal_ll_def_list "STM32G0xx") + list(APPEND hal_ll_def_list "STM32G0Cxx") + list(APPEND hal_ll_def_list "STM32G0C1xx") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_81/hal_ll_dma.c b/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_81/hal_ll_dma.c new file mode 100644 index 000000000..87a32e7b4 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_81/hal_ll_dma.c @@ -0,0 +1,661 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_dma.c + * @brief DMA HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_rcc.h" +#include "hal_ll_dma.h" +#include "hal_ll_gpio.h" + +// ------------------------------------------------------------- PRIVATE MACROS + + +/*!< @brief DMA interrupt definitions. */ +#define HAL_LL_DMA_IT_FT ((uint32_t)(1U << 1)) +#define HAL_LL_DMA_IT_HT ((uint32_t)(1U << 2)) +#define HAL_LL_DMA_IT_ET ((uint32_t)(1U << 3)) +#define HAL_LL_DMA_IT_CLEAR_MASK (0x0fUL) + +/*!< @brief DMA SCR register masks. */ + + + +#define HAL_LL_DMA_CCR_PRIORITY_VERY_HIGH_MASK (0x00003000) +#define HAL_LL_DMA_CCR_PRIORITY_HIGH_MASK (0x00002000) +#define HAL_LL_DMA_CCR_PRIORITY_MEDIUM_MASK (0x00001000) +#define HAL_LL_DMA_CCR_PRIORITY_LOW_MASK (0x00000000) +#define HAL_LL_DMA_CCR_CIRC_MASK (0x00000020) +#define HAL_LL_DMA_CCR_PSIZE_BYTE_MASK (0x00000000) +#define HAL_LL_DMA_CCR_PSIZE_HALFWORD_MASK (0x00000100) +#define HAL_LL_DMA_CCR_PSIZE_WORD_MASK (0x00000200) +#define HAL_LL_DMA_MSIZE_BYTE_MASK (0x00000000) +#define HAL_LL_DMA_MSIZE_HALFWORD_MASK (0x00000400) +#define HAL_LL_DMA_MSIZE_WORD_MASK (0x00000800) +#define HAL_LL_DMA_MINC_MASK (0x00000080) +#define HAL_LL_DMA_PINC_MASK (0x00000040) + +#define HAL_LL_DMA_DIRECTION_MEMORY_TO_MEMORY_MASK (0x4000) +#define HAL_LL_DMA_DIRECTION_MEMORY_TO_PERIPH_MASK (0x10) +#define HAL_LL_DMA_DIRECTION_PERIPH_TO_MEMORY_MASK (0x0) + +#define HAL_LL_DMA_CCR_PSIZE_MASK (0x00000300) +#define HAL_LL_DMA_CCR_MSIZE_MASK (0x00000C00) +#define HAL_LL_DMA_CCR_PRIO_MASK (0x00003000) +#define HAL_LL_DMA_CCR_EN_BIT (0) +#define HAL_LL_DMA_CCR_TEIE_BIT (3) +#define HAL_LL_DMA_CCR_HTIE_BIT (2) +#define HAL_LL_DMA_CCR_TCIE_BIT (1) +#define HAL_LL_DMA_CCR_DIR_BIT (4) +#define HAL_LL_DMA_CCR_CIRC_BIT (5) +#define HAL_LL_DMA_CCR_PINC_BIT (6) +#define HAL_LL_DMA_CCR_MINC_BIT (7) +#define HAL_LL_DMA_CCR_M2M_BIT (14) + + + +#define DMA1_BASE (0x40020000UL) +#define DMA2_BASE (0x40020400UL) + +#define HAL_LL_DMA1_CLOCK_BIT (0) +#define HAL_LL_DMA1_CLOCK_BASE ((uint32_t)_RCC_AHBENR) +#define HAL_LL_DMA1_STREAM_BASE (DMA1_BASE + CCR_BASE_OFFSET) +#define HAL_LL_DMA2_CLOCK_BIT (1) +#define HAL_LL_DMA2_CLOCK_BASE ((uint32_t)_RCC_AHBENR) +#define HAL_LL_DMA2_STREAM_BASE (DMA2_BASE + CCR_BASE_OFFSET) + +#define CCR_BASE_OFFSET (0x8U) +#define STREAM_BASE_OFFSET (0x14U) +#define IFCR_BASE_OFFSET (0x4U) +#define HAL_LL_PWRCLK_BIT (28) + +/*diff bits/offsets:*/ +#define HAL_LL_PWRCLK_BASE (_RCC_APBENR1) + +#define DMAMUX1_BASE (0x40020800UL) +#define DMAMUX1_OFFSET (0x04U) +#define HAL_LL_DMAMUX1_CLOCK_BIT (2) + + + + + +/*!< @brief Clock enable macros. */ +#ifdef HAL_LL_PWRCLK_BASE +#define _HAL_LL_ENABLE_CLOCK_PWR_ ((HAL_LL_PWRCLK_BASE) ? (*HAL_LL_PWRCLK_BASE |= 1UL << HAL_LL_PWRCLK_BIT) : 0) +#endif + +/*!< @brief DMA module enable macro. */ +#define HAL_LL_DMA_MODULE_ENABLE(_x) (_x->cr |= 1U << HAL_LL_DMA_CCR_EN_BIT) + +/*!< @brief DMA module disable macro. */ +#define HAL_LL_DMA_MODULE_DISABLE(_x) (_x->cr &= ~(1U << HAL_LL_DMA_CCR_EN_BIT)) + +/*!< @brief Default timeout value to wait when checking if module is disabled/enabled. */ +#define DEFAULT_TIMEOUT_VALUE (0xFFFFU) + +// ----------------------------------------------------------- PRIVATE TYPEDEFS + +/*!< @brief DMA HW register structure. */ +typedef struct dma_handle +{ + volatile uint32_t cr; /*!< DMA channel x configuration register (DMA_CCRx) */ + volatile uint32_t ndtr; /*!< DMA channel x number of data to transfer register (DMA_CNDTRx) */ + volatile uint32_t par; /*!< DMA channel x peripheral address register (DMA_CPARx) */ + volatile uint32_t mar; /*!< DMA channel x memory address register (DMA_CMARx) */ + +} dma_handle_t; + + +typedef struct dmamux_registers +{ + volatile uint32_t dmamux_cr; /*!< DMA interrupt status register */ + +} dmamux_registers_t; + +/*!< @brief DMA HW ISR register structure. */ +typedef struct dma_isr_registers +{ + volatile uint32_t isr; /*!< DMA interrupt status register (DMA_ISR) */ + volatile uint32_t ifcr; /*!< DMA interrupt flag clear register (DMA_IFCR) */ + +} dma_isr_registers_t; + +/*!< @brief DMA HW clock settings structure. */ +typedef struct +{ + uint8_t clock_bit; + hal_ll_base_addr_t clock_base; +} dma_clock_t; + +/*!< @brief DMA control settings structure. */ +typedef struct +{ + dma_clock_t clock; + hal_ll_base_addr_t stream_base; +} dma_control_struct_t; + +// ------------------------------------------------------------------ VARIABLES + +static const dma_control_struct_t dma_controller[ DMA_NUM_OF_MODULES ] = +{ + { + { HAL_LL_DMA1_CLOCK_BIT, HAL_LL_DMA1_CLOCK_BASE }, HAL_LL_DMA1_STREAM_BASE + } + ,{ + { HAL_LL_DMA2_CLOCK_BIT, HAL_LL_DMA2_CLOCK_BASE }, HAL_LL_DMA2_STREAM_BASE + } +}; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS + +/** + * @brief Gets current stream address. + * @details Returns stream address based on @ref module value and + * desired @ref stream value. + * @param[in] module DMA module number. + * @param[in] stream DMA stream number. + * @return hal_ll_base_addr_t stream base register address. + */ +static hal_ll_base_addr_t hal_ll_dma_get_stream_address( uint8_t module, uint8_t stream ); + +/** + * @brief Sets current module clock. + * @details If @ref state is @b true, enables DMA module clock. + * If @ref state is @b false, disables DMA module clock. + * @param[in] dma_obj DMA object. + * @param[in] state Desired state. + * - @b true + * - @b false + * @return Nothing. + */ +static void hal_ll_dma_clock_set( hal_ll_dma_t *dma_obj, bool state ); + +/** + * @brief Initializes DMA module. + * @details Initializes DMA module, stream to + * values from @ref config structure. + * @param[in] dma_obj DMA object. + * @param[in] dma DMA HW handle. + * @param[in] config DMA configuration structure. + * @return hal_ll_err_t Returns initialization state, either success or fail. + */ +static hal_ll_err_t hal_ll_dma_init_hw( hal_ll_dma_t *dma_obj, dma_handle_t *dma, hal_ll_dma_config_t config ); + +/** + * @brief Gets DMA module state. + * @details Checks if current DMA module stream has been stopped. + * Waits for defined @ref DEFAULT_TIMEOUT_VALUE number of cycles + * before jumping out of loop and returning @ref HAL_LL_DMA_ERROR. + * @param[in] dma DMA HW handle. + * @return hal_ll_err_t Returns success or fail. + */ +static inline hal_ll_err_t hal_ll_dma_is_module_disabled( dma_handle_t *dma ); + +/** + * @brief Gets DMA channel. + * @details Returns appropriate value to be set in HW register + * for desired @ref channel. + * @param[in] channel DMA channel number. + * @return uint32_t Returns actual HW register value based on @ref channel. + */ +static inline uint32_t hal_ll_dma_get_reg_value_channel( uint8_t channel ); + +/** + * @brief Gets DMA direction. + * @details Returns appropriate value to be set in HW register + * for desired @ref direction. + * @param[in] direction DMA stream direction. + * Refer to @hal_ll_dma_direction_t for possible values. + * @return uint8_t Returns actual HW register value based on @ref direction. + */ +static inline uint16_t hal_ll_dma_get_reg_value_direction( hal_ll_dma_direction_t direction ); + +/** + * @brief Gets DMA peripheral address increment. + * @details Returns appropriate value to be set in HW register + * for desired @ref set_inc. + * @param[in] set_inc DMA channel peripheral address increment. + * Set to @b true in order to increment address. + * Set to @b false in order to keep address the same. + * @return uint16_t Returns actual HW register value based on @ref set_inc. + */ +static inline uint16_t hal_ll_dma_get_reg_value_dst_inc( bool set_inc ); + +/** + * @brief Gets DMA memory address increment. + * @details Returns appropriate value to be set in HW register + * for desired @ref set_inc. + * @param[in] set_inc DMA channel memory address increment. + * Set to @b true in order to increment address. + * Set to @b false in order to keep address the same. + * @return uint16_t Returns actual HW register value based on @ref set_inc. + */ +static inline uint16_t hal_ll_dma_get_reg_value_src_inc( bool set_inc ); + +/** + * @brief Gets DMA memory address alignment. + * @details Returns appropriate value to be set in HW register + * for desired @ref align. + * @param[in] align DMA channel memory address increment. + * Refer to @ref hal_ll_dma_data_align_t for possible values. + * @return uint16_t Returns actual HW register value based on @ref align. + */ +static inline uint16_t hal_ll_dma_get_reg_value_source_size( hal_ll_dma_data_align_t align ); + +/** + * @brief Gets DMA peripheral address alignment. + * @details Returns appropriate value to be set in HW register + * for desired @ref align. + * @param[in] align DMA channel peripheral address increment. + * Refer to @ref hal_ll_dma_data_align_t for possible values. + * @return uint16_t Returns actual HW register value based on @ref align. + */ +static inline uint16_t hal_ll_dma_get_reg_value_destination_size( hal_ll_dma_data_align_t align ); + +/** + * @brief Gets DMA mode value. + * @details Returns appropriate value to be set in HW register + * for desired @ref mode. + * @param[in] mode DMA mode for object channel. + * Refer to @ref hal_ll_dma_mode_t for possible values. + * @return uint16_t Returns actual HW register value based on @ref mode. + */ +static inline uint16_t hal_ll_dma_get_reg_value_mode( hal_ll_dma_mode_t mode ); + +/** + * @brief Gets DMA priority value. + * @details Returns appropriate value to be set in HW register + * for desired @ref priority. + * @param[in] priority DMA priority for object channel. + * Refer to @ref hal_ll_dma_priority_t for possible values. + * @return uint32_t Returns actual HW register value based on @ref priority. + */ +static inline uint32_t hal_ll_dma_get_reg_value_priority( hal_ll_dma_priority_t priority ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS + +hal_ll_err_t hal_ll_dma_init( hal_ll_dma_t *obj ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + + // Enable PWRCLK. + #ifdef HAL_LL_PWRCLK_BASE + _HAL_LL_ENABLE_CLOCK_PWR_; + #endif + + // Enable current stream clock. + hal_ll_dma_clock_set( obj, true ); + + // Initialize current stream. + obj->handle = hal_ll_dma_get_stream_address( obj->module, obj->stream ); + status = hal_ll_dma_init_hw( obj, + (dma_handle_t *)obj->handle, + obj->config ); + + if ( HAL_LL_DMA_SUCCESS != status ) { + obj->handle = 0; // If initialization failed, reset handle. + } + + return status; +} + +hal_ll_err_t hal_ll_dma_deinit( hal_ll_dma_t *obj ) { + // First abort current transfer. + if ( HAL_LL_DMA_SUCCESS != hal_ll_dma_transfer_abort( obj ) ) + return HAL_LL_DMA_ERROR; + // Finally, disable module clock. + hal_ll_dma_clock_set( obj, false ); + + return HAL_LL_DMA_SUCCESS; +} + +hal_ll_err_t hal_ll_dma_set_mode( hal_ll_dma_t *obj, hal_ll_dma_mode_t mode ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + // Get new mode. + hal_ll_dma_config_t cfg = obj->config; + cfg.mode = mode; + // Disable module first. + HAL_LL_DMA_MODULE_DISABLE( ((dma_handle_t *)obj->handle) ); + // Try to set new mode. + status = hal_ll_dma_init_hw( obj, + (dma_handle_t *)obj->handle, + cfg ); + + return status; +} + +hal_ll_err_t hal_ll_dma_set_direction( hal_ll_dma_t *obj, hal_ll_dma_direction_t direction ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + // Get new direction. + hal_ll_dma_config_t cfg = obj->config; + cfg.direction = direction; + // Disable module first. + HAL_LL_DMA_MODULE_DISABLE( ((dma_handle_t *)obj->handle) ); + // Try to set new value. + status = hal_ll_dma_init_hw( obj, + (dma_handle_t *)obj->handle, + cfg ); + + return status; +} + +hal_ll_err_t hal_ll_dma_set_priority( hal_ll_dma_t *obj, hal_ll_dma_priority_t priority ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + // Get new priority. + hal_ll_dma_config_t cfg = obj->config; + cfg.priority = priority; + // Disable module first. + HAL_LL_DMA_MODULE_DISABLE( ((dma_handle_t *)obj->handle) ); + // Try to set new value. + status = hal_ll_dma_init_hw( obj, + (dma_handle_t *)obj->handle, + cfg ); + + return status; +} + +hal_ll_err_t hal_ll_dma_set_parameters( hal_ll_dma_t *obj, uint32_t addr_src, uint32_t addr_dst, size_t transfer_size, hal_ll_dma_source_memory_region_t src_mem_type ) { + dma_handle_t *dma = (dma_handle_t *)obj->handle; + uint8_t ndtr_divisor; + + // This parameter is not relevant on this architecture. + (void)src_mem_type; + + // Configure DMA Stream data length. + switch ( obj->config.data_align_destination ) { + case HAL_LL_DMA_DATA_ALIGN_BYTES_1: + case HAL_LL_DMA_DATA_ALIGN_BYTES_2: + ndtr_divisor = obj->config.data_align_destination; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_4: + ndtr_divisor = 2; + break; + + default: + return HAL_LL_DMA_ERROR; + } + dma->ndtr = transfer_size >> ndtr_divisor; + + // Memory to Peripheral. + if ( HAL_LL_DMA_DIRECTION_MEMORY_TO_PERIPH == obj->config.direction ) { + // Configure DMA stream destination address. + dma->par = addr_dst; + // Configure DMA stream source address. + dma->mar = addr_src; + } else { // Peripheral to Memory. + // Configure DMA stream source address. + dma->par = addr_src; + // Configure DMA stream destination address. + dma->mar = addr_dst; + } + return HAL_LL_DMA_SUCCESS; +} + +hal_ll_err_t hal_ll_dma_transfer_start( hal_ll_dma_t *obj ) { + HAL_LL_DMA_MODULE_ENABLE( ((dma_handle_t *)obj->handle) ); + return HAL_LL_DMA_SUCCESS; +} + +hal_ll_err_t hal_ll_dma_transfer_stop( hal_ll_dma_t *obj ) { + dma_handle_t *dma = (dma_handle_t *)obj->handle; + uint16_t timeout = DEFAULT_TIMEOUT_VALUE; + + if ( HAL_LL_DMA_MODE_CIRCULAR == obj->config.mode ) + return HAL_LL_DMA_ERROR; + + while ( dma->ndtr ) { + if ( 0 == timeout-- ) + return HAL_LL_DMA_ERROR; + } + + HAL_LL_DMA_MODULE_DISABLE( dma ); + + return HAL_LL_DMA_SUCCESS; +} + +hal_ll_err_t hal_ll_dma_transfer_abort( hal_ll_dma_t *obj ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + dma_handle_t *dma = (dma_handle_t *)obj->handle; + + // Calculate DMA base and stream number. + dma_isr_registers_t *regs = (dma_isr_registers_t *)(dma_controller[obj->module].stream_base - CCR_BASE_OFFSET); + + // Disable all the transfer interrupts. + dma->cr &= ~(HAL_LL_DMA_CCR_TCIE_BIT | HAL_LL_DMA_CCR_HTIE_BIT | HAL_LL_DMA_CCR_TEIE_BIT); + + // Disable the stream. + HAL_LL_DMA_MODULE_DISABLE( dma ); + + // Wait for bit to be cleared. + status = hal_ll_dma_is_module_disabled( dma ); + + // Clear all interrupt flags at correct offset within the register. + if ( HAL_LL_DMA_SUCCESS == status ) + regs->ifcr = HAL_LL_DMA_IT_CLEAR_MASK << ( obj->stream * 4 ); + + return status; +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS + +static hal_ll_base_addr_t hal_ll_dma_get_stream_address( uint8_t module, uint8_t stream ) { + return ((hal_ll_base_addr_t)dma_controller[module].stream_base + (hal_ll_base_addr_t)(STREAM_BASE_OFFSET * (stream))); +} + +static void hal_ll_dma_clock_set( hal_ll_dma_t *obj, bool state ) { + if ( state ) { + set_reg_bit( (uint32_t *)dma_controller[obj->module].clock.clock_base, + dma_controller[obj->module].clock.clock_bit ); + set_reg_bit( (uint32_t *)dma_controller[obj->module].clock.clock_base, HAL_LL_DMAMUX1_CLOCK_BIT); + } else { + clear_reg_bit( (uint32_t *)dma_controller[obj->module].clock.clock_base, + dma_controller[obj->module].clock.clock_bit ); + } +} + +static hal_ll_err_t hal_ll_dma_init_hw( hal_ll_dma_t *obj, dma_handle_t *dma, hal_ll_dma_config_t config ) { + volatile uint32_t tmp = 0UL; + // Check if user entered invalid data aka HAL_LL_DMA_DATA_ALIGN_BYTES_3 + if (HAL_LL_DMA_DATA_ALIGN_BYTES_3 == config.data_align_source || HAL_LL_DMA_DATA_ALIGN_BYTES_3 == config.data_align_destination ) { + return HAL_LL_DMA_ERROR; + } + + // Disable the peripheral first. + HAL_LL_DMA_MODULE_DISABLE(dma); + + // Wait for bit to be cleared. + if ( HAL_LL_DMA_ERROR == hal_ll_dma_is_module_disabled( dma ) ) + return HAL_LL_DMA_ERROR; + + // Get the CR register value. + tmp = dma->cr; + + // Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits. + tmp &= ((uint32_t)~( HAL_LL_DMA_CCR_EN_BIT | HAL_LL_DMA_CCR_TCIE_BIT | HAL_LL_DMA_CCR_HTIE_BIT | \ + HAL_LL_DMA_CCR_TEIE_BIT | HAL_LL_DMA_CCR_DIR_BIT | HAL_LL_DMA_CCR_CIRC_BIT | \ + HAL_LL_DMA_CCR_PINC_BIT | HAL_LL_DMA_CCR_MINC_BIT | HAL_LL_DMA_CCR_M2M_BIT | \ + HAL_LL_DMA_CCR_PSIZE_MASK | HAL_LL_DMA_CCR_MSIZE_MASK | HAL_LL_DMA_CCR_PRIO_MASK )); + + // BEGIN Prepare the DMA stream configuration. + // Set desired direction value. + tmp |= hal_ll_dma_get_reg_value_direction(config.direction); + // Set desired memory increment settings. + tmp |= hal_ll_dma_get_reg_value_src_inc(config.src_inc); + tmp |= hal_ll_dma_get_reg_value_dst_inc(config.dst_inc); + // Set desired data size settings. + tmp |= hal_ll_dma_get_reg_value_source_size(config.data_align_source); + tmp |= hal_ll_dma_get_reg_value_destination_size(config.data_align_destination); + // Set desired mode. + tmp |= hal_ll_dma_get_reg_value_mode(config.mode); + // Finally, set desired priority. + tmp |= hal_ll_dma_get_reg_value_priority(config.priority); + + // And then write to DMA stream CR register. + dma->cr = tmp; + + if (obj->module == 0 ) { + dmamux_registers_t * dmamux = (dmamux_registers_t*)( DMAMUX1_BASE + ( obj->stream * DMAMUX1_OFFSET ) ); + dmamux->dmamux_cr |= obj->channel; + } else { + dmamux_registers_t * dmamux = (dmamux_registers_t*)( DMAMUX1_BASE + ( DMA_NUM_OF_STREAMS * DMAMUX1_OFFSET ) + ( obj->stream * DMAMUX1_OFFSET ) ); + dmamux->dmamux_cr |= obj->channel; + } + + return HAL_LL_DMA_SUCCESS; +} + +static inline hal_ll_err_t hal_ll_dma_is_module_disabled( dma_handle_t *dma ) { + uint16_t timeout = DEFAULT_TIMEOUT_VALUE; + + while ( (dma->cr & (1U << HAL_LL_DMA_CCR_EN_BIT)) != 0 ) { + if ( 0 == timeout-- ) + return HAL_LL_DMA_ERROR; + } + + return HAL_LL_DMA_SUCCESS; +} + +static inline uint16_t hal_ll_dma_get_reg_value_direction( hal_ll_dma_direction_t direction ) { + volatile uint16_t direction_set = (uint8_t)HAL_LL_DMA_DIRECTION_MEMORY_TO_MEMORY; + + switch ( direction ) + { + case HAL_LL_DMA_DIRECTION_MEMORY_TO_MEMORY: + direction_set = HAL_LL_DMA_DIRECTION_MEMORY_TO_MEMORY_MASK; + break; + case HAL_LL_DMA_DIRECTION_MEMORY_TO_PERIPH: + direction_set = HAL_LL_DMA_DIRECTION_MEMORY_TO_PERIPH_MASK; + break; + case HAL_LL_DMA_DIRECTION_PERIPH_TO_MEMORY: + direction_set = HAL_LL_DMA_DIRECTION_PERIPH_TO_MEMORY_MASK; + break; + + default: + break; + } + + return (uint16_t)direction_set; +} + +static inline uint16_t hal_ll_dma_get_reg_value_dst_inc( bool set_inc ) { + return (uint16_t)((set_inc) ? (HAL_LL_DMA_PINC_MASK) : (0)); +} + +static inline uint16_t hal_ll_dma_get_reg_value_src_inc( bool set_inc ) { + return (uint16_t)((set_inc) ? (HAL_LL_DMA_MINC_MASK) : (0)); +} + +static inline uint16_t hal_ll_dma_get_reg_value_source_size( hal_ll_dma_data_align_t align ) { + volatile uint16_t align_set = (uint16_t)HAL_LL_DMA_DATA_ALIGN_BYTES_1; + + switch ( align ) + { + case HAL_LL_DMA_DATA_ALIGN_BYTES_1: + align_set = HAL_LL_DMA_MSIZE_BYTE_MASK; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_2: + align_set = HAL_LL_DMA_MSIZE_HALFWORD_MASK; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_4: + align_set = HAL_LL_DMA_MSIZE_WORD_MASK; + break; + + default: + break; + } + + return (uint16_t)align_set; +} + +static inline uint16_t hal_ll_dma_get_reg_value_destination_size( hal_ll_dma_data_align_t align ) { + volatile uint16_t align_set = (uint16_t)HAL_LL_DMA_DATA_ALIGN_BYTES_1; + + switch ( align ) + { + case HAL_LL_DMA_DATA_ALIGN_BYTES_1: + align_set = HAL_LL_DMA_CCR_PSIZE_BYTE_MASK; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_2: + align_set = HAL_LL_DMA_CCR_PSIZE_HALFWORD_MASK; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_4: + align_set = HAL_LL_DMA_CCR_PSIZE_WORD_MASK; + break; + + default: + break; + } + + return (uint16_t)align_set; +} + +static inline uint16_t hal_ll_dma_get_reg_value_mode( hal_ll_dma_mode_t mode ) { + return (uint16_t)((mode) ? (HAL_LL_DMA_CCR_CIRC_MASK) : (0)); +} + +static inline uint32_t hal_ll_dma_get_reg_value_priority( hal_ll_dma_priority_t priority ) { + volatile uint32_t priority_set = (uint32_t)HAL_LL_DMA_PRIORITY_LOW; + + switch ( priority ) + { + case HAL_LL_DMA_PRIORITY_LOW: + priority_set = HAL_LL_DMA_CCR_PRIORITY_LOW_MASK; + break; + case HAL_LL_DMA_PRIORITY_MEDIUM: + priority_set = HAL_LL_DMA_CCR_PRIORITY_MEDIUM_MASK; + break; + case HAL_LL_DMA_PRIORITY_HIGH: + priority_set = HAL_LL_DMA_CCR_PRIORITY_HIGH_MASK; + break; + case HAL_LL_DMA_PRIORITY_VERY_HIGH: + priority_set = HAL_LL_DMA_CCR_PRIORITY_VERY_HIGH_MASK; + break; + + default: + break; + } + + return (uint32_t)priority_set; +} + +// ------------------------------------------------------------------------- END + + + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_82/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_82/CMakeLists.cmake new file mode 100644 index 000000000..b61cca105 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_82/CMakeLists.cmake @@ -0,0 +1,8 @@ +if(${MCU_NAME} MATCHES "^STM32G431C6$|^STM32G431K6$|^STM32G431R6$|^STM32G431V6$|^STM32G431M6$|^STM32G431C8$|^STM32G431K8$|^STM32G431R8$|^STM32G431V8$|^STM32G431M8$|^STM32G431CB$|^STM32G431KB$|^STM32G431RB$|^STM32G431VB$|^STM32G431MB$") + set(dma_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_dma.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_82") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_82") + list(APPEND hal_ll_def_list "STM32G4xx") + list(APPEND hal_ll_def_list "STM32G43xx") + list(APPEND hal_ll_def_list "STM32G431xx") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_82/hal_ll_dma.c b/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_82/hal_ll_dma.c new file mode 100644 index 000000000..6da1a0a11 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_82/hal_ll_dma.c @@ -0,0 +1,644 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_dma.c + * @brief DMA HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_rcc.h" +#include "hal_ll_dma.h" +#include "hal_ll_gpio.h" + +// ------------------------------------------------------------- PRIVATE MACROS + + +/*!< @brief DMA interrupt definitions. */ +#define HAL_LL_DMA_IT_FT ((uint32_t)(1U << 1)) +#define HAL_LL_DMA_IT_HT ((uint32_t)(1U << 2)) +#define HAL_LL_DMA_IT_ET ((uint32_t)(1U << 3)) +#define HAL_LL_DMA_IT_CLEAR_MASK (0x0fUL) + +#define HAL_LL_DMA_CCR_PRIORITY_VERY_HIGH_MASK (0x00003000) +#define HAL_LL_DMA_CCR_PRIORITY_HIGH_MASK (0x00002000) +#define HAL_LL_DMA_CCR_PRIORITY_MEDIUM_MASK (0x00001000) +#define HAL_LL_DMA_CCR_PRIORITY_LOW_MASK (0x00000000) +#define HAL_LL_DMA_CCR_CIRC_MASK (0x00000020) +#define HAL_LL_DMA_CCR_PSIZE_BYTE_MASK (0x00000000) +#define HAL_LL_DMA_CCR_PSIZE_HALFWORD_MASK (0x00000100) +#define HAL_LL_DMA_CCR_PSIZE_WORD_MASK (0x00000200) +#define HAL_LL_DMA_MSIZE_BYTE_MASK (0x00000000) +#define HAL_LL_DMA_MSIZE_HALFWORD_MASK (0x00000400) +#define HAL_LL_DMA_MSIZE_WORD_MASK (0x00000800) +#define HAL_LL_DMA_MINC_MASK (0x00000080) +#define HAL_LL_DMA_PINC_MASK (0x00000040) + +#define HAL_LL_DMA_DIRECTION_MEMORY_TO_MEMORY_MASK (0x4000) +#define HAL_LL_DMA_DIRECTION_MEMORY_TO_PERIPH_MASK (0x10) +#define HAL_LL_DMA_DIRECTION_PERIPH_TO_MEMORY_MASK (0x0) + +#define HAL_LL_DMA_CCR_PSIZE_MASK (0x00000300) +#define HAL_LL_DMA_CCR_MSIZE_MASK (0x00000C00) +#define HAL_LL_DMA_CCR_PRIO_MASK (0x00003000) +#define HAL_LL_DMA_CCR_EN_BIT (0) +#define HAL_LL_DMA_CCR_TEIE_BIT (3) +#define HAL_LL_DMA_CCR_HTIE_BIT (2) +#define HAL_LL_DMA_CCR_TCIE_BIT (1) +#define HAL_LL_DMA_CCR_DIR_BIT (4) +#define HAL_LL_DMA_CCR_CIRC_BIT (5) +#define HAL_LL_DMA_CCR_PINC_BIT (6) +#define HAL_LL_DMA_CCR_MINC_BIT (7) +#define HAL_LL_DMA_CCR_M2M_BIT (14) + +#define DMA1_BASE (0x40020000UL) +#define DMA2_BASE (0x40020400UL) + +#define HAL_LL_DMA1_CLOCK_BIT (0) +#define HAL_LL_DMA1_CLOCK_BASE ((uint32_t)_RCC_AHB1ENR) +#define HAL_LL_DMA1_STREAM_BASE (DMA1_BASE + CCR_BASE_OFFSET) +#define HAL_LL_DMA2_CLOCK_BIT (1) +#define HAL_LL_DMA2_CLOCK_BASE ((uint32_t)_RCC_AHB1ENR) +#define HAL_LL_DMA2_STREAM_BASE (DMA2_BASE + CCR_BASE_OFFSET) + +#define CCR_BASE_OFFSET (0x8U) +#define STREAM_BASE_OFFSET (0x14U) +#define IFCR_BASE_OFFSET (0x4U) +#define HAL_LL_PWRCLK_BIT (28) + +/*diff bits/offsets:*/ +#define HAL_LL_PWRCLK_BASE (_RCC_APB1ENR1) + +#define DMAMUX1_BASE (0x40020800UL) +#define DMAMUX1_OFFSET (0x04U) +#define HAL_LL_DMAMUX1_CLOCK_BIT (2) + +/*!< @brief Clock enable macros. */ +#ifdef HAL_LL_PWRCLK_BASE +#define _HAL_LL_ENABLE_CLOCK_PWR_ ((HAL_LL_PWRCLK_BASE) ? (*HAL_LL_PWRCLK_BASE |= 1UL << HAL_LL_PWRCLK_BIT) : 0) +#endif + +/*!< @brief DMA module enable macro. */ +#define HAL_LL_DMA_MODULE_ENABLE(_x) (_x->cr |= 1U << HAL_LL_DMA_CCR_EN_BIT) + +/*!< @brief DMA module disable macro. */ +#define HAL_LL_DMA_MODULE_DISABLE(_x) (_x->cr &= ~(1U << HAL_LL_DMA_CCR_EN_BIT)) + +/*!< @brief Default timeout value to wait when checking if module is disabled/enabled. */ +#define DEFAULT_TIMEOUT_VALUE (0xFFFFU) + +// ----------------------------------------------------------- PRIVATE TYPEDEFS + +/*!< @brief DMA HW register structure. */ +typedef struct dma_handle +{ + volatile uint32_t cr; /*!< DMA channel x configuration register (DMA_CCRx) */ + volatile uint32_t ndtr; /*!< DMA channel x number of data to transfer register (DMA_CNDTRx) */ + volatile uint32_t par; /*!< DMA channel x peripheral address register (DMA_CPARx) */ + volatile uint32_t mar; /*!< DMA channel x memory address register (DMA_CMARx) */ +} dma_handle_t; + +typedef struct dmamux_registers +{ + volatile uint32_t dmamux_cr; /*!< DMA interrupt status register */ +} dmamux_registers_t; + +/*!< @brief DMA HW ISR register structure. */ +typedef struct dma_isr_registers +{ + volatile uint32_t isr; /*!< DMA interrupt status register (DMA_ISR) */ + volatile uint32_t ifcr; /*!< DMA interrupt flag clear register (DMA_IFCR) */ +} dma_isr_registers_t; + +/*!< @brief DMA HW clock settings structure. */ +typedef struct +{ + uint8_t clock_bit; + hal_ll_base_addr_t clock_base; +} dma_clock_t; + +/*!< @brief DMA control settings structure. */ +typedef struct +{ + dma_clock_t clock; + hal_ll_base_addr_t stream_base; +} dma_control_struct_t; + +// ------------------------------------------------------------------ VARIABLES + +static const dma_control_struct_t dma_controller[ DMA_NUM_OF_MODULES ] = +{ + { + { HAL_LL_DMA1_CLOCK_BIT, HAL_LL_DMA1_CLOCK_BASE }, HAL_LL_DMA1_STREAM_BASE + } + ,{ + { HAL_LL_DMA2_CLOCK_BIT, HAL_LL_DMA2_CLOCK_BASE }, HAL_LL_DMA2_STREAM_BASE + } +}; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS + +/** + * @brief Gets current stream address. + * @details Returns stream address based on @ref module value and + * desired @ref stream value. + * @param[in] module DMA module number. + * @param[in] stream DMA stream number. + * @return hal_ll_base_addr_t stream base register address. + */ +static hal_ll_base_addr_t hal_ll_dma_get_stream_address( uint8_t module, uint8_t stream ); + +/** + * @brief Sets current module clock. + * @details If @ref state is @b true, enables DMA module clock. + * If @ref state is @b false, disables DMA module clock. + * @param[in] dma_obj DMA object. + * @param[in] state Desired state. + * - @b true + * - @b false + * @return Nothing. + */ +static void hal_ll_dma_clock_set( hal_ll_dma_t *dma_obj, bool state ); + +/** + * @brief Initializes DMA module. + * @details Initializes DMA module, stream to + * values from @ref config structure. + * @param[in] dma_obj DMA object. + * @param[in] dma DMA HW handle. + * @param[in] config DMA configuration structure. + * @return hal_ll_err_t Returns initialization state, either success or fail. + */ +static hal_ll_err_t hal_ll_dma_init_hw( hal_ll_dma_t *dma_obj, dma_handle_t *dma, hal_ll_dma_config_t config ); + +/** + * @brief Gets DMA module state. + * @details Checks if current DMA module stream has been stopped. + * Waits for defined @ref DEFAULT_TIMEOUT_VALUE number of cycles + * before jumping out of loop and returning @ref HAL_LL_DMA_ERROR. + * @param[in] dma DMA HW handle. + * @return hal_ll_err_t Returns success or fail. + */ +static inline hal_ll_err_t hal_ll_dma_is_module_disabled( dma_handle_t *dma ); + +/** + * @brief Gets DMA channel. + * @details Returns appropriate value to be set in HW register + * for desired @ref channel. + * @param[in] channel DMA channel number. + * @return uint32_t Returns actual HW register value based on @ref channel. + */ +static inline uint32_t hal_ll_dma_get_reg_value_channel( uint8_t channel ); + +/** + * @brief Gets DMA direction. + * @details Returns appropriate value to be set in HW register + * for desired @ref direction. + * @param[in] direction DMA stream direction. + * Refer to @hal_ll_dma_direction_t for possible values. + * @return uint8_t Returns actual HW register value based on @ref direction. + */ +static inline uint16_t hal_ll_dma_get_reg_value_direction( hal_ll_dma_direction_t direction ); + +/** + * @brief Gets DMA peripheral address increment. + * @details Returns appropriate value to be set in HW register + * for desired @ref set_inc. + * @param[in] set_inc DMA channel peripheral address increment. + * Set to @b true in order to increment address. + * Set to @b false in order to keep address the same. + * @return uint16_t Returns actual HW register value based on @ref set_inc. + */ +static inline uint16_t hal_ll_dma_get_reg_value_dst_inc( bool set_inc ); + +/** + * @brief Gets DMA memory address increment. + * @details Returns appropriate value to be set in HW register + * for desired @ref set_inc. + * @param[in] set_inc DMA channel memory address increment. + * Set to @b true in order to increment address. + * Set to @b false in order to keep address the same. + * @return uint16_t Returns actual HW register value based on @ref set_inc. + */ +static inline uint16_t hal_ll_dma_get_reg_value_src_inc( bool set_inc ); + +/** + * @brief Gets DMA memory address alignment. + * @details Returns appropriate value to be set in HW register + * for desired @ref align. + * @param[in] align DMA channel memory address increment. + * Refer to @ref hal_ll_dma_data_align_t for possible values. + * @return uint16_t Returns actual HW register value based on @ref align. + */ +static inline uint16_t hal_ll_dma_get_reg_value_source_size( hal_ll_dma_data_align_t align ); + +/** + * @brief Gets DMA peripheral address alignment. + * @details Returns appropriate value to be set in HW register + * for desired @ref align. + * @param[in] align DMA channel peripheral address increment. + * Refer to @ref hal_ll_dma_data_align_t for possible values. + * @return uint16_t Returns actual HW register value based on @ref align. + */ +static inline uint16_t hal_ll_dma_get_reg_value_destination_size( hal_ll_dma_data_align_t align ); + +/** + * @brief Gets DMA mode value. + * @details Returns appropriate value to be set in HW register + * for desired @ref mode. + * @param[in] mode DMA mode for object channel. + * Refer to @ref hal_ll_dma_mode_t for possible values. + * @return uint16_t Returns actual HW register value based on @ref mode. + */ +static inline uint16_t hal_ll_dma_get_reg_value_mode( hal_ll_dma_mode_t mode ); + +/** + * @brief Gets DMA priority value. + * @details Returns appropriate value to be set in HW register + * for desired @ref priority. + * @param[in] priority DMA priority for object channel. + * Refer to @ref hal_ll_dma_priority_t for possible values. + * @return uint32_t Returns actual HW register value based on @ref priority. + */ +static inline uint32_t hal_ll_dma_get_reg_value_priority( hal_ll_dma_priority_t priority ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS + +hal_ll_err_t hal_ll_dma_init( hal_ll_dma_t *obj ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + + // Enable PWRCLK. + #ifdef HAL_LL_PWRCLK_BASE + _HAL_LL_ENABLE_CLOCK_PWR_; + #endif + + // Enable current stream clock. + hal_ll_dma_clock_set( obj, true ); + + // Initialize current stream. + obj->handle = hal_ll_dma_get_stream_address( obj->module, obj->stream ); + status = hal_ll_dma_init_hw( obj, + (dma_handle_t *)obj->handle, + obj->config ); + + if ( HAL_LL_DMA_SUCCESS != status ) { + obj->handle = 0; // If initialization failed, reset handle. + } + + return status; +} + +hal_ll_err_t hal_ll_dma_deinit( hal_ll_dma_t *obj ) { + // First abort current transfer. + if ( HAL_LL_DMA_SUCCESS != hal_ll_dma_transfer_abort( obj ) ) + return HAL_LL_DMA_ERROR; + // Finally, disable module clock. + hal_ll_dma_clock_set( obj, false ); + + return HAL_LL_DMA_SUCCESS; +} + +hal_ll_err_t hal_ll_dma_set_mode( hal_ll_dma_t *obj, hal_ll_dma_mode_t mode ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + // Get new mode. + hal_ll_dma_config_t cfg = obj->config; + cfg.mode = mode; + // Disable module first. + HAL_LL_DMA_MODULE_DISABLE( ((dma_handle_t *)obj->handle) ); + // Try to set new mode. + status = hal_ll_dma_init_hw( obj, + (dma_handle_t *)obj->handle, + cfg ); + + return status; +} + +hal_ll_err_t hal_ll_dma_set_direction( hal_ll_dma_t *obj, hal_ll_dma_direction_t direction ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + // Get new direction. + hal_ll_dma_config_t cfg = obj->config; + cfg.direction = direction; + // Disable module first. + HAL_LL_DMA_MODULE_DISABLE( ((dma_handle_t *)obj->handle) ); + // Try to set new value. + status = hal_ll_dma_init_hw( obj, + (dma_handle_t *)obj->handle, + cfg ); + + return status; +} + +hal_ll_err_t hal_ll_dma_set_priority( hal_ll_dma_t *obj, hal_ll_dma_priority_t priority ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + // Get new priority. + hal_ll_dma_config_t cfg = obj->config; + cfg.priority = priority; + // Disable module first. + HAL_LL_DMA_MODULE_DISABLE( ((dma_handle_t *)obj->handle) ); + // Try to set new value. + status = hal_ll_dma_init_hw( obj, + (dma_handle_t *)obj->handle, + cfg ); + + return status; +} + +hal_ll_err_t hal_ll_dma_set_parameters( hal_ll_dma_t *obj, uint32_t addr_src, uint32_t addr_dst, size_t transfer_size, hal_ll_dma_source_memory_region_t src_mem_type ) { + dma_handle_t *dma = (dma_handle_t *)obj->handle; + uint8_t ndtr_divisor; + + // This parameter is not relevant on this architecture. + (void)src_mem_type; + + // Configure DMA Stream data length. + switch ( obj->config.data_align_destination ) { + case HAL_LL_DMA_DATA_ALIGN_BYTES_1: + case HAL_LL_DMA_DATA_ALIGN_BYTES_2: + ndtr_divisor = obj->config.data_align_destination; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_4: + ndtr_divisor = 2; + break; + + default: + return HAL_LL_DMA_ERROR; + } + dma->ndtr = transfer_size >> ndtr_divisor; + + // Memory to Peripheral. + if ( HAL_LL_DMA_DIRECTION_MEMORY_TO_PERIPH == obj->config.direction ) { + // Configure DMA stream destination address. + dma->par = addr_dst; + // Configure DMA stream source address. + dma->mar = addr_src; + } else { // Peripheral to Memory. + // Configure DMA stream source address. + dma->par = addr_src; + // Configure DMA stream destination address. + dma->mar = addr_dst; + } + return HAL_LL_DMA_SUCCESS; +} + +hal_ll_err_t hal_ll_dma_transfer_start( hal_ll_dma_t *obj ) { + HAL_LL_DMA_MODULE_ENABLE( ((dma_handle_t *)obj->handle) ); + return HAL_LL_DMA_SUCCESS; +} + +hal_ll_err_t hal_ll_dma_transfer_stop( hal_ll_dma_t *obj ) { + dma_handle_t *dma = (dma_handle_t *)obj->handle; + uint16_t timeout = DEFAULT_TIMEOUT_VALUE; + + if ( HAL_LL_DMA_MODE_CIRCULAR == obj->config.mode ) + return HAL_LL_DMA_ERROR; + + while ( dma->ndtr ) { + if ( 0 == timeout-- ) + return HAL_LL_DMA_ERROR; + } + + HAL_LL_DMA_MODULE_DISABLE( dma ); + + return HAL_LL_DMA_SUCCESS; +} + +hal_ll_err_t hal_ll_dma_transfer_abort( hal_ll_dma_t *obj ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + dma_handle_t *dma = (dma_handle_t *)obj->handle; + + // Calculate DMA base and stream number. + dma_isr_registers_t *regs = (dma_isr_registers_t *)(dma_controller[obj->module].stream_base - CCR_BASE_OFFSET); + + // Disable all the transfer interrupts. + dma->cr &= ~(HAL_LL_DMA_CCR_TCIE_BIT | HAL_LL_DMA_CCR_HTIE_BIT | HAL_LL_DMA_CCR_TEIE_BIT); + + // Disable the stream. + HAL_LL_DMA_MODULE_DISABLE( dma ); + + // Wait for bit to be cleared. + status = hal_ll_dma_is_module_disabled( dma ); + + // Clear all interrupt flags at correct offset within the register. + if ( HAL_LL_DMA_SUCCESS == status ) + regs->ifcr = HAL_LL_DMA_IT_CLEAR_MASK << ( obj->stream * 4 ); + + return status; +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS + +static hal_ll_base_addr_t hal_ll_dma_get_stream_address( uint8_t module, uint8_t stream ) { + return ((hal_ll_base_addr_t)dma_controller[module].stream_base + (hal_ll_base_addr_t)(STREAM_BASE_OFFSET * (stream))); +} + +static void hal_ll_dma_clock_set( hal_ll_dma_t *obj, bool state ) { + if ( state ) { + set_reg_bit( (uint32_t *)dma_controller[obj->module].clock.clock_base, + dma_controller[obj->module].clock.clock_bit ); + set_reg_bit( (uint32_t *)dma_controller[obj->module].clock.clock_base, HAL_LL_DMAMUX1_CLOCK_BIT); + } else { + clear_reg_bit( (uint32_t *)dma_controller[obj->module].clock.clock_base, + dma_controller[obj->module].clock.clock_bit ); + } +} + +static hal_ll_err_t hal_ll_dma_init_hw( hal_ll_dma_t *obj, dma_handle_t *dma, hal_ll_dma_config_t config ) { + volatile uint32_t tmp = 0UL; + // Check if user entered invalid data aka HAL_LL_DMA_DATA_ALIGN_BYTES_3 + if (HAL_LL_DMA_DATA_ALIGN_BYTES_3 == config.data_align_source || HAL_LL_DMA_DATA_ALIGN_BYTES_3 == config.data_align_destination ) { + return HAL_LL_DMA_ERROR; + } + + // Disable the peripheral first. + HAL_LL_DMA_MODULE_DISABLE(dma); + + // Wait for bit to be cleared. + if ( HAL_LL_DMA_ERROR == hal_ll_dma_is_module_disabled( dma ) ) + return HAL_LL_DMA_ERROR; + + // Get the CR register value. + tmp = dma->cr; + + // Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits. + tmp &= ((uint32_t)~( HAL_LL_DMA_CCR_EN_BIT | HAL_LL_DMA_CCR_TCIE_BIT | HAL_LL_DMA_CCR_HTIE_BIT | \ + HAL_LL_DMA_CCR_TEIE_BIT | HAL_LL_DMA_CCR_DIR_BIT | HAL_LL_DMA_CCR_CIRC_BIT | \ + HAL_LL_DMA_CCR_PINC_BIT | HAL_LL_DMA_CCR_MINC_BIT | HAL_LL_DMA_CCR_M2M_BIT | \ + HAL_LL_DMA_CCR_PSIZE_MASK | HAL_LL_DMA_CCR_MSIZE_MASK | HAL_LL_DMA_CCR_PRIO_MASK )); + + // BEGIN Prepare the DMA stream configuration. + // Set desired direction value. + tmp |= hal_ll_dma_get_reg_value_direction(config.direction); + // Set desired memory increment settings. + tmp |= hal_ll_dma_get_reg_value_src_inc(config.src_inc); + tmp |= hal_ll_dma_get_reg_value_dst_inc(config.dst_inc); + // Set desired data size settings. + tmp |= hal_ll_dma_get_reg_value_source_size(config.data_align_source); + tmp |= hal_ll_dma_get_reg_value_destination_size(config.data_align_destination); + // Set desired mode. + tmp |= hal_ll_dma_get_reg_value_mode(config.mode); + // Finally, set desired priority. + tmp |= hal_ll_dma_get_reg_value_priority(config.priority); + + // And then write to DMA stream CR register. + dma->cr = tmp; + + if (obj->module == 0 ) { + dmamux_registers_t * dmamux = (dmamux_registers_t*)( DMAMUX1_BASE + ( obj->stream * DMAMUX1_OFFSET ) ); + dmamux->dmamux_cr |= obj->channel; + } else { + dmamux_registers_t * dmamux = (dmamux_registers_t*)( DMAMUX1_BASE + ( DMA_NUM_OF_STREAMS * DMAMUX1_OFFSET ) + ( obj->stream * DMAMUX1_OFFSET ) ); + dmamux->dmamux_cr |= obj->channel; + } + + return HAL_LL_DMA_SUCCESS; +} + +static inline hal_ll_err_t hal_ll_dma_is_module_disabled( dma_handle_t *dma ) { + uint16_t timeout = DEFAULT_TIMEOUT_VALUE; + + while ( (dma->cr & (1U << HAL_LL_DMA_CCR_EN_BIT)) != 0 ) { + if ( 0 == timeout-- ) + return HAL_LL_DMA_ERROR; + } + + return HAL_LL_DMA_SUCCESS; +} + +static inline uint16_t hal_ll_dma_get_reg_value_direction( hal_ll_dma_direction_t direction ) { + volatile uint16_t direction_set = (uint8_t)HAL_LL_DMA_DIRECTION_MEMORY_TO_MEMORY; + + switch ( direction ) + { + case HAL_LL_DMA_DIRECTION_MEMORY_TO_MEMORY: + direction_set = HAL_LL_DMA_DIRECTION_MEMORY_TO_MEMORY_MASK; + break; + case HAL_LL_DMA_DIRECTION_MEMORY_TO_PERIPH: + direction_set = HAL_LL_DMA_DIRECTION_MEMORY_TO_PERIPH_MASK; + break; + case HAL_LL_DMA_DIRECTION_PERIPH_TO_MEMORY: + direction_set = HAL_LL_DMA_DIRECTION_PERIPH_TO_MEMORY_MASK; + break; + + default: + break; + } + + return (uint16_t)direction_set; +} + +static inline uint16_t hal_ll_dma_get_reg_value_dst_inc( bool set_inc ) { + return (uint16_t)((set_inc) ? (HAL_LL_DMA_PINC_MASK) : (0)); +} + +static inline uint16_t hal_ll_dma_get_reg_value_src_inc( bool set_inc ) { + return (uint16_t)((set_inc) ? (HAL_LL_DMA_MINC_MASK) : (0)); +} + +static inline uint16_t hal_ll_dma_get_reg_value_source_size( hal_ll_dma_data_align_t align ) { + volatile uint16_t align_set = (uint16_t)HAL_LL_DMA_DATA_ALIGN_BYTES_1; + + switch ( align ) + { + case HAL_LL_DMA_DATA_ALIGN_BYTES_1: + align_set = HAL_LL_DMA_MSIZE_BYTE_MASK; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_2: + align_set = HAL_LL_DMA_MSIZE_HALFWORD_MASK; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_4: + align_set = HAL_LL_DMA_MSIZE_WORD_MASK; + break; + + default: + break; + } + + return (uint16_t)align_set; +} + +static inline uint16_t hal_ll_dma_get_reg_value_destination_size( hal_ll_dma_data_align_t align ) { + volatile uint16_t align_set = (uint16_t)HAL_LL_DMA_DATA_ALIGN_BYTES_1; + + switch ( align ) + { + case HAL_LL_DMA_DATA_ALIGN_BYTES_1: + align_set = HAL_LL_DMA_CCR_PSIZE_BYTE_MASK; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_2: + align_set = HAL_LL_DMA_CCR_PSIZE_HALFWORD_MASK; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_4: + align_set = HAL_LL_DMA_CCR_PSIZE_WORD_MASK; + break; + + default: + break; + } + + return (uint16_t)align_set; +} + +static inline uint16_t hal_ll_dma_get_reg_value_mode( hal_ll_dma_mode_t mode ) { + return (uint16_t)((mode) ? (HAL_LL_DMA_CCR_CIRC_MASK) : (0)); +} + +static inline uint32_t hal_ll_dma_get_reg_value_priority( hal_ll_dma_priority_t priority ) { + volatile uint32_t priority_set = (uint32_t)HAL_LL_DMA_PRIORITY_LOW; + + switch ( priority ) + { + case HAL_LL_DMA_PRIORITY_LOW: + priority_set = HAL_LL_DMA_CCR_PRIORITY_LOW_MASK; + break; + case HAL_LL_DMA_PRIORITY_MEDIUM: + priority_set = HAL_LL_DMA_CCR_PRIORITY_MEDIUM_MASK; + break; + case HAL_LL_DMA_PRIORITY_HIGH: + priority_set = HAL_LL_DMA_CCR_PRIORITY_HIGH_MASK; + break; + case HAL_LL_DMA_PRIORITY_VERY_HIGH: + priority_set = HAL_LL_DMA_CCR_PRIORITY_VERY_HIGH_MASK; + break; + + default: + break; + } + + return (uint32_t)priority_set; +} + +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_83/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_83/CMakeLists.cmake new file mode 100644 index 000000000..f634ae28f --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_83/CMakeLists.cmake @@ -0,0 +1,8 @@ +if(${MCU_NAME} MATCHES "^STM32G441CB$|^STM32G441KB$|^STM32G441RB$|^STM32G441MB$|^STM32G441VB$") + set(dma_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_dma.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_83") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_83") + list(APPEND hal_ll_def_list "STM32G4xx") + list(APPEND hal_ll_def_list "STM32G44xx") + list(APPEND hal_ll_def_list "STM32G441xx") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_83/hal_ll_dma.c b/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_83/hal_ll_dma.c new file mode 100644 index 000000000..2ed93bbdb --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_83/hal_ll_dma.c @@ -0,0 +1,661 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_dma.c + * @brief DMA HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_rcc.h" +#include "hal_ll_dma.h" +#include "hal_ll_gpio.h" + +// ------------------------------------------------------------- PRIVATE MACROS + + +/*!< @brief DMA interrupt definitions. */ +#define HAL_LL_DMA_IT_FT ((uint32_t)(1U << 1)) +#define HAL_LL_DMA_IT_HT ((uint32_t)(1U << 2)) +#define HAL_LL_DMA_IT_ET ((uint32_t)(1U << 3)) +#define HAL_LL_DMA_IT_CLEAR_MASK (0x0fUL) + +/*!< @brief DMA SCR register masks. */ + + + +#define HAL_LL_DMA_CCR_PRIORITY_VERY_HIGH_MASK (0x00003000) +#define HAL_LL_DMA_CCR_PRIORITY_HIGH_MASK (0x00002000) +#define HAL_LL_DMA_CCR_PRIORITY_MEDIUM_MASK (0x00001000) +#define HAL_LL_DMA_CCR_PRIORITY_LOW_MASK (0x00000000) +#define HAL_LL_DMA_CCR_CIRC_MASK (0x00000020) +#define HAL_LL_DMA_CCR_PSIZE_BYTE_MASK (0x00000000) +#define HAL_LL_DMA_CCR_PSIZE_HALFWORD_MASK (0x00000100) +#define HAL_LL_DMA_CCR_PSIZE_WORD_MASK (0x00000200) +#define HAL_LL_DMA_MSIZE_BYTE_MASK (0x00000000) +#define HAL_LL_DMA_MSIZE_HALFWORD_MASK (0x00000400) +#define HAL_LL_DMA_MSIZE_WORD_MASK (0x00000800) +#define HAL_LL_DMA_MINC_MASK (0x00000080) +#define HAL_LL_DMA_PINC_MASK (0x00000040) + +#define HAL_LL_DMA_DIRECTION_MEMORY_TO_MEMORY_MASK (0x4000) +#define HAL_LL_DMA_DIRECTION_MEMORY_TO_PERIPH_MASK (0x10) +#define HAL_LL_DMA_DIRECTION_PERIPH_TO_MEMORY_MASK (0x0) + +#define HAL_LL_DMA_CCR_PSIZE_MASK (0x00000300) +#define HAL_LL_DMA_CCR_MSIZE_MASK (0x00000C00) +#define HAL_LL_DMA_CCR_PRIO_MASK (0x00003000) +#define HAL_LL_DMA_CCR_EN_BIT (0) +#define HAL_LL_DMA_CCR_TEIE_BIT (3) +#define HAL_LL_DMA_CCR_HTIE_BIT (2) +#define HAL_LL_DMA_CCR_TCIE_BIT (1) +#define HAL_LL_DMA_CCR_DIR_BIT (4) +#define HAL_LL_DMA_CCR_CIRC_BIT (5) +#define HAL_LL_DMA_CCR_PINC_BIT (6) +#define HAL_LL_DMA_CCR_MINC_BIT (7) +#define HAL_LL_DMA_CCR_M2M_BIT (14) + + + +#define DMA1_BASE (0x40020000UL) +#define DMA2_BASE (0x40020400UL) + +#define HAL_LL_DMA1_CLOCK_BIT (0) +#define HAL_LL_DMA1_CLOCK_BASE ((uint32_t)_RCC_AHB1ENR) +#define HAL_LL_DMA1_STREAM_BASE (DMA1_BASE + CCR_BASE_OFFSET) +#define HAL_LL_DMA2_CLOCK_BIT (1) +#define HAL_LL_DMA2_CLOCK_BASE ((uint32_t)_RCC_AHB1ENR) +#define HAL_LL_DMA2_STREAM_BASE (DMA2_BASE + CCR_BASE_OFFSET) + +#define CCR_BASE_OFFSET (0x8U) +#define STREAM_BASE_OFFSET (0x14U) +#define IFCR_BASE_OFFSET (0x4U) +#define HAL_LL_PWRCLK_BIT (28) + +/*diff bits/offsets:*/ +#define HAL_LL_PWRCLK_BASE (_RCC_APB1ENR1) + +#define DMAMUX1_BASE (0x40020800UL) +#define DMAMUX1_OFFSET (0x04U) +#define HAL_LL_DMAMUX1_CLOCK_BIT (2) + + + + + +/*!< @brief Clock enable macros. */ +#ifdef HAL_LL_PWRCLK_BASE +#define _HAL_LL_ENABLE_CLOCK_PWR_ ((HAL_LL_PWRCLK_BASE) ? (*HAL_LL_PWRCLK_BASE |= 1UL << HAL_LL_PWRCLK_BIT) : 0) +#endif + +/*!< @brief DMA module enable macro. */ +#define HAL_LL_DMA_MODULE_ENABLE(_x) (_x->cr |= 1U << HAL_LL_DMA_CCR_EN_BIT) + +/*!< @brief DMA module disable macro. */ +#define HAL_LL_DMA_MODULE_DISABLE(_x) (_x->cr &= ~(1U << HAL_LL_DMA_CCR_EN_BIT)) + +/*!< @brief Default timeout value to wait when checking if module is disabled/enabled. */ +#define DEFAULT_TIMEOUT_VALUE (0xFFFFU) + +// ----------------------------------------------------------- PRIVATE TYPEDEFS + +/*!< @brief DMA HW register structure. */ +typedef struct dma_handle +{ + volatile uint32_t cr; /*!< DMA channel x configuration register (DMA_CCRx) */ + volatile uint32_t ndtr; /*!< DMA channel x number of data to transfer register (DMA_CNDTRx) */ + volatile uint32_t par; /*!< DMA channel x peripheral address register (DMA_CPARx) */ + volatile uint32_t mar; /*!< DMA channel x memory address register (DMA_CMARx) */ + +} dma_handle_t; + + +typedef struct dmamux_registers +{ + volatile uint32_t dmamux_cr; /*!< DMA interrupt status register */ + +} dmamux_registers_t; + +/*!< @brief DMA HW ISR register structure. */ +typedef struct dma_isr_registers +{ + volatile uint32_t isr; /*!< DMA interrupt status register (DMA_ISR) */ + volatile uint32_t ifcr; /*!< DMA interrupt flag clear register (DMA_IFCR) */ + +} dma_isr_registers_t; + +/*!< @brief DMA HW clock settings structure. */ +typedef struct +{ + uint8_t clock_bit; + hal_ll_base_addr_t clock_base; +} dma_clock_t; + +/*!< @brief DMA control settings structure. */ +typedef struct +{ + dma_clock_t clock; + hal_ll_base_addr_t stream_base; +} dma_control_struct_t; + +// ------------------------------------------------------------------ VARIABLES + +static const dma_control_struct_t dma_controller[ DMA_NUM_OF_MODULES ] = +{ + { + { HAL_LL_DMA1_CLOCK_BIT, HAL_LL_DMA1_CLOCK_BASE }, HAL_LL_DMA1_STREAM_BASE + } + ,{ + { HAL_LL_DMA2_CLOCK_BIT, HAL_LL_DMA2_CLOCK_BASE }, HAL_LL_DMA2_STREAM_BASE + } +}; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS + +/** + * @brief Gets current stream address. + * @details Returns stream address based on @ref module value and + * desired @ref stream value. + * @param[in] module DMA module number. + * @param[in] stream DMA stream number. + * @return hal_ll_base_addr_t stream base register address. + */ +static hal_ll_base_addr_t hal_ll_dma_get_stream_address( uint8_t module, uint8_t stream ); + +/** + * @brief Sets current module clock. + * @details If @ref state is @b true, enables DMA module clock. + * If @ref state is @b false, disables DMA module clock. + * @param[in] dma_obj DMA object. + * @param[in] state Desired state. + * - @b true + * - @b false + * @return Nothing. + */ +static void hal_ll_dma_clock_set( hal_ll_dma_t *dma_obj, bool state ); + +/** + * @brief Initializes DMA module. + * @details Initializes DMA module, stream to + * values from @ref config structure. + * @param[in] dma_obj DMA object. + * @param[in] dma DMA HW handle. + * @param[in] config DMA configuration structure. + * @return hal_ll_err_t Returns initialization state, either success or fail. + */ +static hal_ll_err_t hal_ll_dma_init_hw( hal_ll_dma_t *dma_obj, dma_handle_t *dma, hal_ll_dma_config_t config ); + +/** + * @brief Gets DMA module state. + * @details Checks if current DMA module stream has been stopped. + * Waits for defined @ref DEFAULT_TIMEOUT_VALUE number of cycles + * before jumping out of loop and returning @ref HAL_LL_DMA_ERROR. + * @param[in] dma DMA HW handle. + * @return hal_ll_err_t Returns success or fail. + */ +static inline hal_ll_err_t hal_ll_dma_is_module_disabled( dma_handle_t *dma ); + +/** + * @brief Gets DMA channel. + * @details Returns appropriate value to be set in HW register + * for desired @ref channel. + * @param[in] channel DMA channel number. + * @return uint32_t Returns actual HW register value based on @ref channel. + */ +static inline uint32_t hal_ll_dma_get_reg_value_channel( uint8_t channel ); + +/** + * @brief Gets DMA direction. + * @details Returns appropriate value to be set in HW register + * for desired @ref direction. + * @param[in] direction DMA stream direction. + * Refer to @hal_ll_dma_direction_t for possible values. + * @return uint8_t Returns actual HW register value based on @ref direction. + */ +static inline uint16_t hal_ll_dma_get_reg_value_direction( hal_ll_dma_direction_t direction ); + +/** + * @brief Gets DMA peripheral address increment. + * @details Returns appropriate value to be set in HW register + * for desired @ref set_inc. + * @param[in] set_inc DMA channel peripheral address increment. + * Set to @b true in order to increment address. + * Set to @b false in order to keep address the same. + * @return uint16_t Returns actual HW register value based on @ref set_inc. + */ +static inline uint16_t hal_ll_dma_get_reg_value_dst_inc( bool set_inc ); + +/** + * @brief Gets DMA memory address increment. + * @details Returns appropriate value to be set in HW register + * for desired @ref set_inc. + * @param[in] set_inc DMA channel memory address increment. + * Set to @b true in order to increment address. + * Set to @b false in order to keep address the same. + * @return uint16_t Returns actual HW register value based on @ref set_inc. + */ +static inline uint16_t hal_ll_dma_get_reg_value_src_inc( bool set_inc ); + +/** + * @brief Gets DMA memory address alignment. + * @details Returns appropriate value to be set in HW register + * for desired @ref align. + * @param[in] align DMA channel memory address increment. + * Refer to @ref hal_ll_dma_data_align_t for possible values. + * @return uint16_t Returns actual HW register value based on @ref align. + */ +static inline uint16_t hal_ll_dma_get_reg_value_source_size( hal_ll_dma_data_align_t align ); + +/** + * @brief Gets DMA peripheral address alignment. + * @details Returns appropriate value to be set in HW register + * for desired @ref align. + * @param[in] align DMA channel peripheral address increment. + * Refer to @ref hal_ll_dma_data_align_t for possible values. + * @return uint16_t Returns actual HW register value based on @ref align. + */ +static inline uint16_t hal_ll_dma_get_reg_value_destination_size( hal_ll_dma_data_align_t align ); + +/** + * @brief Gets DMA mode value. + * @details Returns appropriate value to be set in HW register + * for desired @ref mode. + * @param[in] mode DMA mode for object channel. + * Refer to @ref hal_ll_dma_mode_t for possible values. + * @return uint16_t Returns actual HW register value based on @ref mode. + */ +static inline uint16_t hal_ll_dma_get_reg_value_mode( hal_ll_dma_mode_t mode ); + +/** + * @brief Gets DMA priority value. + * @details Returns appropriate value to be set in HW register + * for desired @ref priority. + * @param[in] priority DMA priority for object channel. + * Refer to @ref hal_ll_dma_priority_t for possible values. + * @return uint32_t Returns actual HW register value based on @ref priority. + */ +static inline uint32_t hal_ll_dma_get_reg_value_priority( hal_ll_dma_priority_t priority ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS + +hal_ll_err_t hal_ll_dma_init( hal_ll_dma_t *obj ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + + // Enable PWRCLK. + #ifdef HAL_LL_PWRCLK_BASE + _HAL_LL_ENABLE_CLOCK_PWR_; + #endif + + // Enable current stream clock. + hal_ll_dma_clock_set( obj, true ); + + // Initialize current stream. + obj->handle = hal_ll_dma_get_stream_address( obj->module, obj->stream ); + status = hal_ll_dma_init_hw( obj, + (dma_handle_t *)obj->handle, + obj->config ); + + if ( HAL_LL_DMA_SUCCESS != status ) { + obj->handle = 0; // If initialization failed, reset handle. + } + + return status; +} + +hal_ll_err_t hal_ll_dma_deinit( hal_ll_dma_t *obj ) { + // First abort current transfer. + if ( HAL_LL_DMA_SUCCESS != hal_ll_dma_transfer_abort( obj ) ) + return HAL_LL_DMA_ERROR; + // Finally, disable module clock. + hal_ll_dma_clock_set( obj, false ); + + return HAL_LL_DMA_SUCCESS; +} + +hal_ll_err_t hal_ll_dma_set_mode( hal_ll_dma_t *obj, hal_ll_dma_mode_t mode ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + // Get new mode. + hal_ll_dma_config_t cfg = obj->config; + cfg.mode = mode; + // Disable module first. + HAL_LL_DMA_MODULE_DISABLE( ((dma_handle_t *)obj->handle) ); + // Try to set new mode. + status = hal_ll_dma_init_hw( obj, + (dma_handle_t *)obj->handle, + cfg ); + + return status; +} + +hal_ll_err_t hal_ll_dma_set_direction( hal_ll_dma_t *obj, hal_ll_dma_direction_t direction ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + // Get new direction. + hal_ll_dma_config_t cfg = obj->config; + cfg.direction = direction; + // Disable module first. + HAL_LL_DMA_MODULE_DISABLE( ((dma_handle_t *)obj->handle) ); + // Try to set new value. + status = hal_ll_dma_init_hw( obj, + (dma_handle_t *)obj->handle, + cfg ); + + return status; +} + +hal_ll_err_t hal_ll_dma_set_priority( hal_ll_dma_t *obj, hal_ll_dma_priority_t priority ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + // Get new priority. + hal_ll_dma_config_t cfg = obj->config; + cfg.priority = priority; + // Disable module first. + HAL_LL_DMA_MODULE_DISABLE( ((dma_handle_t *)obj->handle) ); + // Try to set new value. + status = hal_ll_dma_init_hw( obj, + (dma_handle_t *)obj->handle, + cfg ); + + return status; +} + +hal_ll_err_t hal_ll_dma_set_parameters( hal_ll_dma_t *obj, uint32_t addr_src, uint32_t addr_dst, size_t transfer_size, hal_ll_dma_source_memory_region_t src_mem_type ) { + dma_handle_t *dma = (dma_handle_t *)obj->handle; + uint8_t ndtr_divisor; + + // This parameter is not relevant on this architecture. + (void)src_mem_type; + + // Configure DMA Stream data length. + switch ( obj->config.data_align_destination ) { + case HAL_LL_DMA_DATA_ALIGN_BYTES_1: + case HAL_LL_DMA_DATA_ALIGN_BYTES_2: + ndtr_divisor = obj->config.data_align_destination; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_4: + ndtr_divisor = 2; + break; + + default: + return HAL_LL_DMA_ERROR; + } + dma->ndtr = transfer_size >> ndtr_divisor; + + // Memory to Peripheral. + if ( HAL_LL_DMA_DIRECTION_MEMORY_TO_PERIPH == obj->config.direction ) { + // Configure DMA stream destination address. + dma->par = addr_dst; + // Configure DMA stream source address. + dma->mar = addr_src; + } else { // Peripheral to Memory. + // Configure DMA stream source address. + dma->par = addr_src; + // Configure DMA stream destination address. + dma->mar = addr_dst; + } + return HAL_LL_DMA_SUCCESS; +} + +hal_ll_err_t hal_ll_dma_transfer_start( hal_ll_dma_t *obj ) { + HAL_LL_DMA_MODULE_ENABLE( ((dma_handle_t *)obj->handle) ); + return HAL_LL_DMA_SUCCESS; +} + +hal_ll_err_t hal_ll_dma_transfer_stop( hal_ll_dma_t *obj ) { + dma_handle_t *dma = (dma_handle_t *)obj->handle; + uint16_t timeout = DEFAULT_TIMEOUT_VALUE; + + if ( HAL_LL_DMA_MODE_CIRCULAR == obj->config.mode ) + return HAL_LL_DMA_ERROR; + + while ( dma->ndtr ) { + if ( 0 == timeout-- ) + return HAL_LL_DMA_ERROR; + } + + HAL_LL_DMA_MODULE_DISABLE( dma ); + + return HAL_LL_DMA_SUCCESS; +} + +hal_ll_err_t hal_ll_dma_transfer_abort( hal_ll_dma_t *obj ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + dma_handle_t *dma = (dma_handle_t *)obj->handle; + + // Calculate DMA base and stream number. + dma_isr_registers_t *regs = (dma_isr_registers_t *)(dma_controller[obj->module].stream_base - CCR_BASE_OFFSET); + + // Disable all the transfer interrupts. + dma->cr &= ~(HAL_LL_DMA_CCR_TCIE_BIT | HAL_LL_DMA_CCR_HTIE_BIT | HAL_LL_DMA_CCR_TEIE_BIT); + + // Disable the stream. + HAL_LL_DMA_MODULE_DISABLE( dma ); + + // Wait for bit to be cleared. + status = hal_ll_dma_is_module_disabled( dma ); + + // Clear all interrupt flags at correct offset within the register. + if ( HAL_LL_DMA_SUCCESS == status ) + regs->ifcr = HAL_LL_DMA_IT_CLEAR_MASK << ( obj->stream * 4 ); + + return status; +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS + +static hal_ll_base_addr_t hal_ll_dma_get_stream_address( uint8_t module, uint8_t stream ) { + return ((hal_ll_base_addr_t)dma_controller[module].stream_base + (hal_ll_base_addr_t)(STREAM_BASE_OFFSET * (stream))); +} + +static void hal_ll_dma_clock_set( hal_ll_dma_t *obj, bool state ) { + if ( state ) { + set_reg_bit( (uint32_t *)dma_controller[obj->module].clock.clock_base, + dma_controller[obj->module].clock.clock_bit ); + set_reg_bit( (uint32_t *)dma_controller[obj->module].clock.clock_base, HAL_LL_DMAMUX1_CLOCK_BIT); + } else { + clear_reg_bit( (uint32_t *)dma_controller[obj->module].clock.clock_base, + dma_controller[obj->module].clock.clock_bit ); + } +} + +static hal_ll_err_t hal_ll_dma_init_hw( hal_ll_dma_t *obj, dma_handle_t *dma, hal_ll_dma_config_t config ) { + volatile uint32_t tmp = 0UL; + // Check if user entered invalid data aka HAL_LL_DMA_DATA_ALIGN_BYTES_3 + if (HAL_LL_DMA_DATA_ALIGN_BYTES_3 == config.data_align_source || HAL_LL_DMA_DATA_ALIGN_BYTES_3 == config.data_align_destination ) { + return HAL_LL_DMA_ERROR; + } + + // Disable the peripheral first. + HAL_LL_DMA_MODULE_DISABLE(dma); + + // Wait for bit to be cleared. + if ( HAL_LL_DMA_ERROR == hal_ll_dma_is_module_disabled( dma ) ) + return HAL_LL_DMA_ERROR; + + // Get the CR register value. + tmp = dma->cr; + + // Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits. + tmp &= ((uint32_t)~( HAL_LL_DMA_CCR_EN_BIT | HAL_LL_DMA_CCR_TCIE_BIT | HAL_LL_DMA_CCR_HTIE_BIT | \ + HAL_LL_DMA_CCR_TEIE_BIT | HAL_LL_DMA_CCR_DIR_BIT | HAL_LL_DMA_CCR_CIRC_BIT | \ + HAL_LL_DMA_CCR_PINC_BIT | HAL_LL_DMA_CCR_MINC_BIT | HAL_LL_DMA_CCR_M2M_BIT | \ + HAL_LL_DMA_CCR_PSIZE_MASK | HAL_LL_DMA_CCR_MSIZE_MASK | HAL_LL_DMA_CCR_PRIO_MASK )); + + // BEGIN Prepare the DMA stream configuration. + // Set desired direction value. + tmp |= hal_ll_dma_get_reg_value_direction(config.direction); + // Set desired memory increment settings. + tmp |= hal_ll_dma_get_reg_value_src_inc(config.src_inc); + tmp |= hal_ll_dma_get_reg_value_dst_inc(config.dst_inc); + // Set desired data size settings. + tmp |= hal_ll_dma_get_reg_value_source_size(config.data_align_source); + tmp |= hal_ll_dma_get_reg_value_destination_size(config.data_align_destination); + // Set desired mode. + tmp |= hal_ll_dma_get_reg_value_mode(config.mode); + // Finally, set desired priority. + tmp |= hal_ll_dma_get_reg_value_priority(config.priority); + + // And then write to DMA stream CR register. + dma->cr = tmp; + + if (obj->module == 0 ) { + dmamux_registers_t * dmamux = (dmamux_registers_t*)( DMAMUX1_BASE + ( obj->stream * DMAMUX1_OFFSET ) ); + dmamux->dmamux_cr |= obj->channel; + } else { + dmamux_registers_t * dmamux = (dmamux_registers_t*)( DMAMUX1_BASE + ( DMA_NUM_OF_STREAMS * DMAMUX1_OFFSET ) + ( obj->stream * DMAMUX1_OFFSET ) ); + dmamux->dmamux_cr |= obj->channel; + } + + return HAL_LL_DMA_SUCCESS; +} + +static inline hal_ll_err_t hal_ll_dma_is_module_disabled( dma_handle_t *dma ) { + uint16_t timeout = DEFAULT_TIMEOUT_VALUE; + + while ( (dma->cr & (1U << HAL_LL_DMA_CCR_EN_BIT)) != 0 ) { + if ( 0 == timeout-- ) + return HAL_LL_DMA_ERROR; + } + + return HAL_LL_DMA_SUCCESS; +} + +static inline uint16_t hal_ll_dma_get_reg_value_direction( hal_ll_dma_direction_t direction ) { + volatile uint16_t direction_set = (uint8_t)HAL_LL_DMA_DIRECTION_MEMORY_TO_MEMORY; + + switch ( direction ) + { + case HAL_LL_DMA_DIRECTION_MEMORY_TO_MEMORY: + direction_set = HAL_LL_DMA_DIRECTION_MEMORY_TO_MEMORY_MASK; + break; + case HAL_LL_DMA_DIRECTION_MEMORY_TO_PERIPH: + direction_set = HAL_LL_DMA_DIRECTION_MEMORY_TO_PERIPH_MASK; + break; + case HAL_LL_DMA_DIRECTION_PERIPH_TO_MEMORY: + direction_set = HAL_LL_DMA_DIRECTION_PERIPH_TO_MEMORY_MASK; + break; + + default: + break; + } + + return (uint16_t)direction_set; +} + +static inline uint16_t hal_ll_dma_get_reg_value_dst_inc( bool set_inc ) { + return (uint16_t)((set_inc) ? (HAL_LL_DMA_PINC_MASK) : (0)); +} + +static inline uint16_t hal_ll_dma_get_reg_value_src_inc( bool set_inc ) { + return (uint16_t)((set_inc) ? (HAL_LL_DMA_MINC_MASK) : (0)); +} + +static inline uint16_t hal_ll_dma_get_reg_value_source_size( hal_ll_dma_data_align_t align ) { + volatile uint16_t align_set = (uint16_t)HAL_LL_DMA_DATA_ALIGN_BYTES_1; + + switch ( align ) + { + case HAL_LL_DMA_DATA_ALIGN_BYTES_1: + align_set = HAL_LL_DMA_MSIZE_BYTE_MASK; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_2: + align_set = HAL_LL_DMA_MSIZE_HALFWORD_MASK; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_4: + align_set = HAL_LL_DMA_MSIZE_WORD_MASK; + break; + + default: + break; + } + + return (uint16_t)align_set; +} + +static inline uint16_t hal_ll_dma_get_reg_value_destination_size( hal_ll_dma_data_align_t align ) { + volatile uint16_t align_set = (uint16_t)HAL_LL_DMA_DATA_ALIGN_BYTES_1; + + switch ( align ) + { + case HAL_LL_DMA_DATA_ALIGN_BYTES_1: + align_set = HAL_LL_DMA_CCR_PSIZE_BYTE_MASK; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_2: + align_set = HAL_LL_DMA_CCR_PSIZE_HALFWORD_MASK; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_4: + align_set = HAL_LL_DMA_CCR_PSIZE_WORD_MASK; + break; + + default: + break; + } + + return (uint16_t)align_set; +} + +static inline uint16_t hal_ll_dma_get_reg_value_mode( hal_ll_dma_mode_t mode ) { + return (uint16_t)((mode) ? (HAL_LL_DMA_CCR_CIRC_MASK) : (0)); +} + +static inline uint32_t hal_ll_dma_get_reg_value_priority( hal_ll_dma_priority_t priority ) { + volatile uint32_t priority_set = (uint32_t)HAL_LL_DMA_PRIORITY_LOW; + + switch ( priority ) + { + case HAL_LL_DMA_PRIORITY_LOW: + priority_set = HAL_LL_DMA_CCR_PRIORITY_LOW_MASK; + break; + case HAL_LL_DMA_PRIORITY_MEDIUM: + priority_set = HAL_LL_DMA_CCR_PRIORITY_MEDIUM_MASK; + break; + case HAL_LL_DMA_PRIORITY_HIGH: + priority_set = HAL_LL_DMA_CCR_PRIORITY_HIGH_MASK; + break; + case HAL_LL_DMA_PRIORITY_VERY_HIGH: + priority_set = HAL_LL_DMA_CCR_PRIORITY_VERY_HIGH_MASK; + break; + + default: + break; + } + + return (uint32_t)priority_set; +} + +// ------------------------------------------------------------------------- END + + + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_84/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_84/CMakeLists.cmake new file mode 100644 index 000000000..95b49978b --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_84/CMakeLists.cmake @@ -0,0 +1,8 @@ +if(${MCU_NAME} MATCHES "^STM32G473CB$|^STM32G473MB$|^STM32G473PB$|^STM32G473RB$|^STM32G473VB$|^STM32G473QB$|^STM32G473CC$|^STM32G473MC$|^STM32G473PC$|^STM32G473RC$|^STM32G473VC$|^STM32G473QC$|^STM32G473CE$|^STM32G473ME$|^STM32G473PE$|^STM32G473RE$|^STM32G473VE$|^STM32G473QE$") + set(dma_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_dma.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_84") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_84") + list(APPEND hal_ll_def_list "STM32G4xx") + list(APPEND hal_ll_def_list "STM32G47xx") + list(APPEND hal_ll_def_list "STM32G473xx") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_84/hal_ll_dma.c b/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_84/hal_ll_dma.c new file mode 100644 index 000000000..2ed93bbdb --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_84/hal_ll_dma.c @@ -0,0 +1,661 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_dma.c + * @brief DMA HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_rcc.h" +#include "hal_ll_dma.h" +#include "hal_ll_gpio.h" + +// ------------------------------------------------------------- PRIVATE MACROS + + +/*!< @brief DMA interrupt definitions. */ +#define HAL_LL_DMA_IT_FT ((uint32_t)(1U << 1)) +#define HAL_LL_DMA_IT_HT ((uint32_t)(1U << 2)) +#define HAL_LL_DMA_IT_ET ((uint32_t)(1U << 3)) +#define HAL_LL_DMA_IT_CLEAR_MASK (0x0fUL) + +/*!< @brief DMA SCR register masks. */ + + + +#define HAL_LL_DMA_CCR_PRIORITY_VERY_HIGH_MASK (0x00003000) +#define HAL_LL_DMA_CCR_PRIORITY_HIGH_MASK (0x00002000) +#define HAL_LL_DMA_CCR_PRIORITY_MEDIUM_MASK (0x00001000) +#define HAL_LL_DMA_CCR_PRIORITY_LOW_MASK (0x00000000) +#define HAL_LL_DMA_CCR_CIRC_MASK (0x00000020) +#define HAL_LL_DMA_CCR_PSIZE_BYTE_MASK (0x00000000) +#define HAL_LL_DMA_CCR_PSIZE_HALFWORD_MASK (0x00000100) +#define HAL_LL_DMA_CCR_PSIZE_WORD_MASK (0x00000200) +#define HAL_LL_DMA_MSIZE_BYTE_MASK (0x00000000) +#define HAL_LL_DMA_MSIZE_HALFWORD_MASK (0x00000400) +#define HAL_LL_DMA_MSIZE_WORD_MASK (0x00000800) +#define HAL_LL_DMA_MINC_MASK (0x00000080) +#define HAL_LL_DMA_PINC_MASK (0x00000040) + +#define HAL_LL_DMA_DIRECTION_MEMORY_TO_MEMORY_MASK (0x4000) +#define HAL_LL_DMA_DIRECTION_MEMORY_TO_PERIPH_MASK (0x10) +#define HAL_LL_DMA_DIRECTION_PERIPH_TO_MEMORY_MASK (0x0) + +#define HAL_LL_DMA_CCR_PSIZE_MASK (0x00000300) +#define HAL_LL_DMA_CCR_MSIZE_MASK (0x00000C00) +#define HAL_LL_DMA_CCR_PRIO_MASK (0x00003000) +#define HAL_LL_DMA_CCR_EN_BIT (0) +#define HAL_LL_DMA_CCR_TEIE_BIT (3) +#define HAL_LL_DMA_CCR_HTIE_BIT (2) +#define HAL_LL_DMA_CCR_TCIE_BIT (1) +#define HAL_LL_DMA_CCR_DIR_BIT (4) +#define HAL_LL_DMA_CCR_CIRC_BIT (5) +#define HAL_LL_DMA_CCR_PINC_BIT (6) +#define HAL_LL_DMA_CCR_MINC_BIT (7) +#define HAL_LL_DMA_CCR_M2M_BIT (14) + + + +#define DMA1_BASE (0x40020000UL) +#define DMA2_BASE (0x40020400UL) + +#define HAL_LL_DMA1_CLOCK_BIT (0) +#define HAL_LL_DMA1_CLOCK_BASE ((uint32_t)_RCC_AHB1ENR) +#define HAL_LL_DMA1_STREAM_BASE (DMA1_BASE + CCR_BASE_OFFSET) +#define HAL_LL_DMA2_CLOCK_BIT (1) +#define HAL_LL_DMA2_CLOCK_BASE ((uint32_t)_RCC_AHB1ENR) +#define HAL_LL_DMA2_STREAM_BASE (DMA2_BASE + CCR_BASE_OFFSET) + +#define CCR_BASE_OFFSET (0x8U) +#define STREAM_BASE_OFFSET (0x14U) +#define IFCR_BASE_OFFSET (0x4U) +#define HAL_LL_PWRCLK_BIT (28) + +/*diff bits/offsets:*/ +#define HAL_LL_PWRCLK_BASE (_RCC_APB1ENR1) + +#define DMAMUX1_BASE (0x40020800UL) +#define DMAMUX1_OFFSET (0x04U) +#define HAL_LL_DMAMUX1_CLOCK_BIT (2) + + + + + +/*!< @brief Clock enable macros. */ +#ifdef HAL_LL_PWRCLK_BASE +#define _HAL_LL_ENABLE_CLOCK_PWR_ ((HAL_LL_PWRCLK_BASE) ? (*HAL_LL_PWRCLK_BASE |= 1UL << HAL_LL_PWRCLK_BIT) : 0) +#endif + +/*!< @brief DMA module enable macro. */ +#define HAL_LL_DMA_MODULE_ENABLE(_x) (_x->cr |= 1U << HAL_LL_DMA_CCR_EN_BIT) + +/*!< @brief DMA module disable macro. */ +#define HAL_LL_DMA_MODULE_DISABLE(_x) (_x->cr &= ~(1U << HAL_LL_DMA_CCR_EN_BIT)) + +/*!< @brief Default timeout value to wait when checking if module is disabled/enabled. */ +#define DEFAULT_TIMEOUT_VALUE (0xFFFFU) + +// ----------------------------------------------------------- PRIVATE TYPEDEFS + +/*!< @brief DMA HW register structure. */ +typedef struct dma_handle +{ + volatile uint32_t cr; /*!< DMA channel x configuration register (DMA_CCRx) */ + volatile uint32_t ndtr; /*!< DMA channel x number of data to transfer register (DMA_CNDTRx) */ + volatile uint32_t par; /*!< DMA channel x peripheral address register (DMA_CPARx) */ + volatile uint32_t mar; /*!< DMA channel x memory address register (DMA_CMARx) */ + +} dma_handle_t; + + +typedef struct dmamux_registers +{ + volatile uint32_t dmamux_cr; /*!< DMA interrupt status register */ + +} dmamux_registers_t; + +/*!< @brief DMA HW ISR register structure. */ +typedef struct dma_isr_registers +{ + volatile uint32_t isr; /*!< DMA interrupt status register (DMA_ISR) */ + volatile uint32_t ifcr; /*!< DMA interrupt flag clear register (DMA_IFCR) */ + +} dma_isr_registers_t; + +/*!< @brief DMA HW clock settings structure. */ +typedef struct +{ + uint8_t clock_bit; + hal_ll_base_addr_t clock_base; +} dma_clock_t; + +/*!< @brief DMA control settings structure. */ +typedef struct +{ + dma_clock_t clock; + hal_ll_base_addr_t stream_base; +} dma_control_struct_t; + +// ------------------------------------------------------------------ VARIABLES + +static const dma_control_struct_t dma_controller[ DMA_NUM_OF_MODULES ] = +{ + { + { HAL_LL_DMA1_CLOCK_BIT, HAL_LL_DMA1_CLOCK_BASE }, HAL_LL_DMA1_STREAM_BASE + } + ,{ + { HAL_LL_DMA2_CLOCK_BIT, HAL_LL_DMA2_CLOCK_BASE }, HAL_LL_DMA2_STREAM_BASE + } +}; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS + +/** + * @brief Gets current stream address. + * @details Returns stream address based on @ref module value and + * desired @ref stream value. + * @param[in] module DMA module number. + * @param[in] stream DMA stream number. + * @return hal_ll_base_addr_t stream base register address. + */ +static hal_ll_base_addr_t hal_ll_dma_get_stream_address( uint8_t module, uint8_t stream ); + +/** + * @brief Sets current module clock. + * @details If @ref state is @b true, enables DMA module clock. + * If @ref state is @b false, disables DMA module clock. + * @param[in] dma_obj DMA object. + * @param[in] state Desired state. + * - @b true + * - @b false + * @return Nothing. + */ +static void hal_ll_dma_clock_set( hal_ll_dma_t *dma_obj, bool state ); + +/** + * @brief Initializes DMA module. + * @details Initializes DMA module, stream to + * values from @ref config structure. + * @param[in] dma_obj DMA object. + * @param[in] dma DMA HW handle. + * @param[in] config DMA configuration structure. + * @return hal_ll_err_t Returns initialization state, either success or fail. + */ +static hal_ll_err_t hal_ll_dma_init_hw( hal_ll_dma_t *dma_obj, dma_handle_t *dma, hal_ll_dma_config_t config ); + +/** + * @brief Gets DMA module state. + * @details Checks if current DMA module stream has been stopped. + * Waits for defined @ref DEFAULT_TIMEOUT_VALUE number of cycles + * before jumping out of loop and returning @ref HAL_LL_DMA_ERROR. + * @param[in] dma DMA HW handle. + * @return hal_ll_err_t Returns success or fail. + */ +static inline hal_ll_err_t hal_ll_dma_is_module_disabled( dma_handle_t *dma ); + +/** + * @brief Gets DMA channel. + * @details Returns appropriate value to be set in HW register + * for desired @ref channel. + * @param[in] channel DMA channel number. + * @return uint32_t Returns actual HW register value based on @ref channel. + */ +static inline uint32_t hal_ll_dma_get_reg_value_channel( uint8_t channel ); + +/** + * @brief Gets DMA direction. + * @details Returns appropriate value to be set in HW register + * for desired @ref direction. + * @param[in] direction DMA stream direction. + * Refer to @hal_ll_dma_direction_t for possible values. + * @return uint8_t Returns actual HW register value based on @ref direction. + */ +static inline uint16_t hal_ll_dma_get_reg_value_direction( hal_ll_dma_direction_t direction ); + +/** + * @brief Gets DMA peripheral address increment. + * @details Returns appropriate value to be set in HW register + * for desired @ref set_inc. + * @param[in] set_inc DMA channel peripheral address increment. + * Set to @b true in order to increment address. + * Set to @b false in order to keep address the same. + * @return uint16_t Returns actual HW register value based on @ref set_inc. + */ +static inline uint16_t hal_ll_dma_get_reg_value_dst_inc( bool set_inc ); + +/** + * @brief Gets DMA memory address increment. + * @details Returns appropriate value to be set in HW register + * for desired @ref set_inc. + * @param[in] set_inc DMA channel memory address increment. + * Set to @b true in order to increment address. + * Set to @b false in order to keep address the same. + * @return uint16_t Returns actual HW register value based on @ref set_inc. + */ +static inline uint16_t hal_ll_dma_get_reg_value_src_inc( bool set_inc ); + +/** + * @brief Gets DMA memory address alignment. + * @details Returns appropriate value to be set in HW register + * for desired @ref align. + * @param[in] align DMA channel memory address increment. + * Refer to @ref hal_ll_dma_data_align_t for possible values. + * @return uint16_t Returns actual HW register value based on @ref align. + */ +static inline uint16_t hal_ll_dma_get_reg_value_source_size( hal_ll_dma_data_align_t align ); + +/** + * @brief Gets DMA peripheral address alignment. + * @details Returns appropriate value to be set in HW register + * for desired @ref align. + * @param[in] align DMA channel peripheral address increment. + * Refer to @ref hal_ll_dma_data_align_t for possible values. + * @return uint16_t Returns actual HW register value based on @ref align. + */ +static inline uint16_t hal_ll_dma_get_reg_value_destination_size( hal_ll_dma_data_align_t align ); + +/** + * @brief Gets DMA mode value. + * @details Returns appropriate value to be set in HW register + * for desired @ref mode. + * @param[in] mode DMA mode for object channel. + * Refer to @ref hal_ll_dma_mode_t for possible values. + * @return uint16_t Returns actual HW register value based on @ref mode. + */ +static inline uint16_t hal_ll_dma_get_reg_value_mode( hal_ll_dma_mode_t mode ); + +/** + * @brief Gets DMA priority value. + * @details Returns appropriate value to be set in HW register + * for desired @ref priority. + * @param[in] priority DMA priority for object channel. + * Refer to @ref hal_ll_dma_priority_t for possible values. + * @return uint32_t Returns actual HW register value based on @ref priority. + */ +static inline uint32_t hal_ll_dma_get_reg_value_priority( hal_ll_dma_priority_t priority ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS + +hal_ll_err_t hal_ll_dma_init( hal_ll_dma_t *obj ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + + // Enable PWRCLK. + #ifdef HAL_LL_PWRCLK_BASE + _HAL_LL_ENABLE_CLOCK_PWR_; + #endif + + // Enable current stream clock. + hal_ll_dma_clock_set( obj, true ); + + // Initialize current stream. + obj->handle = hal_ll_dma_get_stream_address( obj->module, obj->stream ); + status = hal_ll_dma_init_hw( obj, + (dma_handle_t *)obj->handle, + obj->config ); + + if ( HAL_LL_DMA_SUCCESS != status ) { + obj->handle = 0; // If initialization failed, reset handle. + } + + return status; +} + +hal_ll_err_t hal_ll_dma_deinit( hal_ll_dma_t *obj ) { + // First abort current transfer. + if ( HAL_LL_DMA_SUCCESS != hal_ll_dma_transfer_abort( obj ) ) + return HAL_LL_DMA_ERROR; + // Finally, disable module clock. + hal_ll_dma_clock_set( obj, false ); + + return HAL_LL_DMA_SUCCESS; +} + +hal_ll_err_t hal_ll_dma_set_mode( hal_ll_dma_t *obj, hal_ll_dma_mode_t mode ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + // Get new mode. + hal_ll_dma_config_t cfg = obj->config; + cfg.mode = mode; + // Disable module first. + HAL_LL_DMA_MODULE_DISABLE( ((dma_handle_t *)obj->handle) ); + // Try to set new mode. + status = hal_ll_dma_init_hw( obj, + (dma_handle_t *)obj->handle, + cfg ); + + return status; +} + +hal_ll_err_t hal_ll_dma_set_direction( hal_ll_dma_t *obj, hal_ll_dma_direction_t direction ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + // Get new direction. + hal_ll_dma_config_t cfg = obj->config; + cfg.direction = direction; + // Disable module first. + HAL_LL_DMA_MODULE_DISABLE( ((dma_handle_t *)obj->handle) ); + // Try to set new value. + status = hal_ll_dma_init_hw( obj, + (dma_handle_t *)obj->handle, + cfg ); + + return status; +} + +hal_ll_err_t hal_ll_dma_set_priority( hal_ll_dma_t *obj, hal_ll_dma_priority_t priority ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + // Get new priority. + hal_ll_dma_config_t cfg = obj->config; + cfg.priority = priority; + // Disable module first. + HAL_LL_DMA_MODULE_DISABLE( ((dma_handle_t *)obj->handle) ); + // Try to set new value. + status = hal_ll_dma_init_hw( obj, + (dma_handle_t *)obj->handle, + cfg ); + + return status; +} + +hal_ll_err_t hal_ll_dma_set_parameters( hal_ll_dma_t *obj, uint32_t addr_src, uint32_t addr_dst, size_t transfer_size, hal_ll_dma_source_memory_region_t src_mem_type ) { + dma_handle_t *dma = (dma_handle_t *)obj->handle; + uint8_t ndtr_divisor; + + // This parameter is not relevant on this architecture. + (void)src_mem_type; + + // Configure DMA Stream data length. + switch ( obj->config.data_align_destination ) { + case HAL_LL_DMA_DATA_ALIGN_BYTES_1: + case HAL_LL_DMA_DATA_ALIGN_BYTES_2: + ndtr_divisor = obj->config.data_align_destination; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_4: + ndtr_divisor = 2; + break; + + default: + return HAL_LL_DMA_ERROR; + } + dma->ndtr = transfer_size >> ndtr_divisor; + + // Memory to Peripheral. + if ( HAL_LL_DMA_DIRECTION_MEMORY_TO_PERIPH == obj->config.direction ) { + // Configure DMA stream destination address. + dma->par = addr_dst; + // Configure DMA stream source address. + dma->mar = addr_src; + } else { // Peripheral to Memory. + // Configure DMA stream source address. + dma->par = addr_src; + // Configure DMA stream destination address. + dma->mar = addr_dst; + } + return HAL_LL_DMA_SUCCESS; +} + +hal_ll_err_t hal_ll_dma_transfer_start( hal_ll_dma_t *obj ) { + HAL_LL_DMA_MODULE_ENABLE( ((dma_handle_t *)obj->handle) ); + return HAL_LL_DMA_SUCCESS; +} + +hal_ll_err_t hal_ll_dma_transfer_stop( hal_ll_dma_t *obj ) { + dma_handle_t *dma = (dma_handle_t *)obj->handle; + uint16_t timeout = DEFAULT_TIMEOUT_VALUE; + + if ( HAL_LL_DMA_MODE_CIRCULAR == obj->config.mode ) + return HAL_LL_DMA_ERROR; + + while ( dma->ndtr ) { + if ( 0 == timeout-- ) + return HAL_LL_DMA_ERROR; + } + + HAL_LL_DMA_MODULE_DISABLE( dma ); + + return HAL_LL_DMA_SUCCESS; +} + +hal_ll_err_t hal_ll_dma_transfer_abort( hal_ll_dma_t *obj ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + dma_handle_t *dma = (dma_handle_t *)obj->handle; + + // Calculate DMA base and stream number. + dma_isr_registers_t *regs = (dma_isr_registers_t *)(dma_controller[obj->module].stream_base - CCR_BASE_OFFSET); + + // Disable all the transfer interrupts. + dma->cr &= ~(HAL_LL_DMA_CCR_TCIE_BIT | HAL_LL_DMA_CCR_HTIE_BIT | HAL_LL_DMA_CCR_TEIE_BIT); + + // Disable the stream. + HAL_LL_DMA_MODULE_DISABLE( dma ); + + // Wait for bit to be cleared. + status = hal_ll_dma_is_module_disabled( dma ); + + // Clear all interrupt flags at correct offset within the register. + if ( HAL_LL_DMA_SUCCESS == status ) + regs->ifcr = HAL_LL_DMA_IT_CLEAR_MASK << ( obj->stream * 4 ); + + return status; +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS + +static hal_ll_base_addr_t hal_ll_dma_get_stream_address( uint8_t module, uint8_t stream ) { + return ((hal_ll_base_addr_t)dma_controller[module].stream_base + (hal_ll_base_addr_t)(STREAM_BASE_OFFSET * (stream))); +} + +static void hal_ll_dma_clock_set( hal_ll_dma_t *obj, bool state ) { + if ( state ) { + set_reg_bit( (uint32_t *)dma_controller[obj->module].clock.clock_base, + dma_controller[obj->module].clock.clock_bit ); + set_reg_bit( (uint32_t *)dma_controller[obj->module].clock.clock_base, HAL_LL_DMAMUX1_CLOCK_BIT); + } else { + clear_reg_bit( (uint32_t *)dma_controller[obj->module].clock.clock_base, + dma_controller[obj->module].clock.clock_bit ); + } +} + +static hal_ll_err_t hal_ll_dma_init_hw( hal_ll_dma_t *obj, dma_handle_t *dma, hal_ll_dma_config_t config ) { + volatile uint32_t tmp = 0UL; + // Check if user entered invalid data aka HAL_LL_DMA_DATA_ALIGN_BYTES_3 + if (HAL_LL_DMA_DATA_ALIGN_BYTES_3 == config.data_align_source || HAL_LL_DMA_DATA_ALIGN_BYTES_3 == config.data_align_destination ) { + return HAL_LL_DMA_ERROR; + } + + // Disable the peripheral first. + HAL_LL_DMA_MODULE_DISABLE(dma); + + // Wait for bit to be cleared. + if ( HAL_LL_DMA_ERROR == hal_ll_dma_is_module_disabled( dma ) ) + return HAL_LL_DMA_ERROR; + + // Get the CR register value. + tmp = dma->cr; + + // Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits. + tmp &= ((uint32_t)~( HAL_LL_DMA_CCR_EN_BIT | HAL_LL_DMA_CCR_TCIE_BIT | HAL_LL_DMA_CCR_HTIE_BIT | \ + HAL_LL_DMA_CCR_TEIE_BIT | HAL_LL_DMA_CCR_DIR_BIT | HAL_LL_DMA_CCR_CIRC_BIT | \ + HAL_LL_DMA_CCR_PINC_BIT | HAL_LL_DMA_CCR_MINC_BIT | HAL_LL_DMA_CCR_M2M_BIT | \ + HAL_LL_DMA_CCR_PSIZE_MASK | HAL_LL_DMA_CCR_MSIZE_MASK | HAL_LL_DMA_CCR_PRIO_MASK )); + + // BEGIN Prepare the DMA stream configuration. + // Set desired direction value. + tmp |= hal_ll_dma_get_reg_value_direction(config.direction); + // Set desired memory increment settings. + tmp |= hal_ll_dma_get_reg_value_src_inc(config.src_inc); + tmp |= hal_ll_dma_get_reg_value_dst_inc(config.dst_inc); + // Set desired data size settings. + tmp |= hal_ll_dma_get_reg_value_source_size(config.data_align_source); + tmp |= hal_ll_dma_get_reg_value_destination_size(config.data_align_destination); + // Set desired mode. + tmp |= hal_ll_dma_get_reg_value_mode(config.mode); + // Finally, set desired priority. + tmp |= hal_ll_dma_get_reg_value_priority(config.priority); + + // And then write to DMA stream CR register. + dma->cr = tmp; + + if (obj->module == 0 ) { + dmamux_registers_t * dmamux = (dmamux_registers_t*)( DMAMUX1_BASE + ( obj->stream * DMAMUX1_OFFSET ) ); + dmamux->dmamux_cr |= obj->channel; + } else { + dmamux_registers_t * dmamux = (dmamux_registers_t*)( DMAMUX1_BASE + ( DMA_NUM_OF_STREAMS * DMAMUX1_OFFSET ) + ( obj->stream * DMAMUX1_OFFSET ) ); + dmamux->dmamux_cr |= obj->channel; + } + + return HAL_LL_DMA_SUCCESS; +} + +static inline hal_ll_err_t hal_ll_dma_is_module_disabled( dma_handle_t *dma ) { + uint16_t timeout = DEFAULT_TIMEOUT_VALUE; + + while ( (dma->cr & (1U << HAL_LL_DMA_CCR_EN_BIT)) != 0 ) { + if ( 0 == timeout-- ) + return HAL_LL_DMA_ERROR; + } + + return HAL_LL_DMA_SUCCESS; +} + +static inline uint16_t hal_ll_dma_get_reg_value_direction( hal_ll_dma_direction_t direction ) { + volatile uint16_t direction_set = (uint8_t)HAL_LL_DMA_DIRECTION_MEMORY_TO_MEMORY; + + switch ( direction ) + { + case HAL_LL_DMA_DIRECTION_MEMORY_TO_MEMORY: + direction_set = HAL_LL_DMA_DIRECTION_MEMORY_TO_MEMORY_MASK; + break; + case HAL_LL_DMA_DIRECTION_MEMORY_TO_PERIPH: + direction_set = HAL_LL_DMA_DIRECTION_MEMORY_TO_PERIPH_MASK; + break; + case HAL_LL_DMA_DIRECTION_PERIPH_TO_MEMORY: + direction_set = HAL_LL_DMA_DIRECTION_PERIPH_TO_MEMORY_MASK; + break; + + default: + break; + } + + return (uint16_t)direction_set; +} + +static inline uint16_t hal_ll_dma_get_reg_value_dst_inc( bool set_inc ) { + return (uint16_t)((set_inc) ? (HAL_LL_DMA_PINC_MASK) : (0)); +} + +static inline uint16_t hal_ll_dma_get_reg_value_src_inc( bool set_inc ) { + return (uint16_t)((set_inc) ? (HAL_LL_DMA_MINC_MASK) : (0)); +} + +static inline uint16_t hal_ll_dma_get_reg_value_source_size( hal_ll_dma_data_align_t align ) { + volatile uint16_t align_set = (uint16_t)HAL_LL_DMA_DATA_ALIGN_BYTES_1; + + switch ( align ) + { + case HAL_LL_DMA_DATA_ALIGN_BYTES_1: + align_set = HAL_LL_DMA_MSIZE_BYTE_MASK; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_2: + align_set = HAL_LL_DMA_MSIZE_HALFWORD_MASK; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_4: + align_set = HAL_LL_DMA_MSIZE_WORD_MASK; + break; + + default: + break; + } + + return (uint16_t)align_set; +} + +static inline uint16_t hal_ll_dma_get_reg_value_destination_size( hal_ll_dma_data_align_t align ) { + volatile uint16_t align_set = (uint16_t)HAL_LL_DMA_DATA_ALIGN_BYTES_1; + + switch ( align ) + { + case HAL_LL_DMA_DATA_ALIGN_BYTES_1: + align_set = HAL_LL_DMA_CCR_PSIZE_BYTE_MASK; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_2: + align_set = HAL_LL_DMA_CCR_PSIZE_HALFWORD_MASK; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_4: + align_set = HAL_LL_DMA_CCR_PSIZE_WORD_MASK; + break; + + default: + break; + } + + return (uint16_t)align_set; +} + +static inline uint16_t hal_ll_dma_get_reg_value_mode( hal_ll_dma_mode_t mode ) { + return (uint16_t)((mode) ? (HAL_LL_DMA_CCR_CIRC_MASK) : (0)); +} + +static inline uint32_t hal_ll_dma_get_reg_value_priority( hal_ll_dma_priority_t priority ) { + volatile uint32_t priority_set = (uint32_t)HAL_LL_DMA_PRIORITY_LOW; + + switch ( priority ) + { + case HAL_LL_DMA_PRIORITY_LOW: + priority_set = HAL_LL_DMA_CCR_PRIORITY_LOW_MASK; + break; + case HAL_LL_DMA_PRIORITY_MEDIUM: + priority_set = HAL_LL_DMA_CCR_PRIORITY_MEDIUM_MASK; + break; + case HAL_LL_DMA_PRIORITY_HIGH: + priority_set = HAL_LL_DMA_CCR_PRIORITY_HIGH_MASK; + break; + case HAL_LL_DMA_PRIORITY_VERY_HIGH: + priority_set = HAL_LL_DMA_CCR_PRIORITY_VERY_HIGH_MASK; + break; + + default: + break; + } + + return (uint32_t)priority_set; +} + +// ------------------------------------------------------------------------- END + + + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_85/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_85/CMakeLists.cmake new file mode 100644 index 000000000..33915cc3f --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_85/CMakeLists.cmake @@ -0,0 +1,8 @@ +if(${MCU_NAME} MATCHES "^STM32G474CB$|^STM32G474MB$|^STM32G474RB$|^STM32G474VB$|^STM32G474QB$|^STM32G474PB$|^STM32G474CC$|^STM32G474MC$|^STM32G474RC$|^STM32G474VC$|^STM32G474QC$|^STM32G474PC$|^STM32G474CE$|^STM32G474ME$|^STM32G474RE$|^STM32G474VE$|^STM32G474QE$|^STM32G474PE$") + set(dma_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_dma.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_85") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_85") + list(APPEND hal_ll_def_list "STM32G4xx") + list(APPEND hal_ll_def_list "STM32G47xx") + list(APPEND hal_ll_def_list "STM32G474xx") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_85/hal_ll_dma.c b/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_85/hal_ll_dma.c new file mode 100644 index 000000000..2ed93bbdb --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_85/hal_ll_dma.c @@ -0,0 +1,661 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_dma.c + * @brief DMA HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_rcc.h" +#include "hal_ll_dma.h" +#include "hal_ll_gpio.h" + +// ------------------------------------------------------------- PRIVATE MACROS + + +/*!< @brief DMA interrupt definitions. */ +#define HAL_LL_DMA_IT_FT ((uint32_t)(1U << 1)) +#define HAL_LL_DMA_IT_HT ((uint32_t)(1U << 2)) +#define HAL_LL_DMA_IT_ET ((uint32_t)(1U << 3)) +#define HAL_LL_DMA_IT_CLEAR_MASK (0x0fUL) + +/*!< @brief DMA SCR register masks. */ + + + +#define HAL_LL_DMA_CCR_PRIORITY_VERY_HIGH_MASK (0x00003000) +#define HAL_LL_DMA_CCR_PRIORITY_HIGH_MASK (0x00002000) +#define HAL_LL_DMA_CCR_PRIORITY_MEDIUM_MASK (0x00001000) +#define HAL_LL_DMA_CCR_PRIORITY_LOW_MASK (0x00000000) +#define HAL_LL_DMA_CCR_CIRC_MASK (0x00000020) +#define HAL_LL_DMA_CCR_PSIZE_BYTE_MASK (0x00000000) +#define HAL_LL_DMA_CCR_PSIZE_HALFWORD_MASK (0x00000100) +#define HAL_LL_DMA_CCR_PSIZE_WORD_MASK (0x00000200) +#define HAL_LL_DMA_MSIZE_BYTE_MASK (0x00000000) +#define HAL_LL_DMA_MSIZE_HALFWORD_MASK (0x00000400) +#define HAL_LL_DMA_MSIZE_WORD_MASK (0x00000800) +#define HAL_LL_DMA_MINC_MASK (0x00000080) +#define HAL_LL_DMA_PINC_MASK (0x00000040) + +#define HAL_LL_DMA_DIRECTION_MEMORY_TO_MEMORY_MASK (0x4000) +#define HAL_LL_DMA_DIRECTION_MEMORY_TO_PERIPH_MASK (0x10) +#define HAL_LL_DMA_DIRECTION_PERIPH_TO_MEMORY_MASK (0x0) + +#define HAL_LL_DMA_CCR_PSIZE_MASK (0x00000300) +#define HAL_LL_DMA_CCR_MSIZE_MASK (0x00000C00) +#define HAL_LL_DMA_CCR_PRIO_MASK (0x00003000) +#define HAL_LL_DMA_CCR_EN_BIT (0) +#define HAL_LL_DMA_CCR_TEIE_BIT (3) +#define HAL_LL_DMA_CCR_HTIE_BIT (2) +#define HAL_LL_DMA_CCR_TCIE_BIT (1) +#define HAL_LL_DMA_CCR_DIR_BIT (4) +#define HAL_LL_DMA_CCR_CIRC_BIT (5) +#define HAL_LL_DMA_CCR_PINC_BIT (6) +#define HAL_LL_DMA_CCR_MINC_BIT (7) +#define HAL_LL_DMA_CCR_M2M_BIT (14) + + + +#define DMA1_BASE (0x40020000UL) +#define DMA2_BASE (0x40020400UL) + +#define HAL_LL_DMA1_CLOCK_BIT (0) +#define HAL_LL_DMA1_CLOCK_BASE ((uint32_t)_RCC_AHB1ENR) +#define HAL_LL_DMA1_STREAM_BASE (DMA1_BASE + CCR_BASE_OFFSET) +#define HAL_LL_DMA2_CLOCK_BIT (1) +#define HAL_LL_DMA2_CLOCK_BASE ((uint32_t)_RCC_AHB1ENR) +#define HAL_LL_DMA2_STREAM_BASE (DMA2_BASE + CCR_BASE_OFFSET) + +#define CCR_BASE_OFFSET (0x8U) +#define STREAM_BASE_OFFSET (0x14U) +#define IFCR_BASE_OFFSET (0x4U) +#define HAL_LL_PWRCLK_BIT (28) + +/*diff bits/offsets:*/ +#define HAL_LL_PWRCLK_BASE (_RCC_APB1ENR1) + +#define DMAMUX1_BASE (0x40020800UL) +#define DMAMUX1_OFFSET (0x04U) +#define HAL_LL_DMAMUX1_CLOCK_BIT (2) + + + + + +/*!< @brief Clock enable macros. */ +#ifdef HAL_LL_PWRCLK_BASE +#define _HAL_LL_ENABLE_CLOCK_PWR_ ((HAL_LL_PWRCLK_BASE) ? (*HAL_LL_PWRCLK_BASE |= 1UL << HAL_LL_PWRCLK_BIT) : 0) +#endif + +/*!< @brief DMA module enable macro. */ +#define HAL_LL_DMA_MODULE_ENABLE(_x) (_x->cr |= 1U << HAL_LL_DMA_CCR_EN_BIT) + +/*!< @brief DMA module disable macro. */ +#define HAL_LL_DMA_MODULE_DISABLE(_x) (_x->cr &= ~(1U << HAL_LL_DMA_CCR_EN_BIT)) + +/*!< @brief Default timeout value to wait when checking if module is disabled/enabled. */ +#define DEFAULT_TIMEOUT_VALUE (0xFFFFU) + +// ----------------------------------------------------------- PRIVATE TYPEDEFS + +/*!< @brief DMA HW register structure. */ +typedef struct dma_handle +{ + volatile uint32_t cr; /*!< DMA channel x configuration register (DMA_CCRx) */ + volatile uint32_t ndtr; /*!< DMA channel x number of data to transfer register (DMA_CNDTRx) */ + volatile uint32_t par; /*!< DMA channel x peripheral address register (DMA_CPARx) */ + volatile uint32_t mar; /*!< DMA channel x memory address register (DMA_CMARx) */ + +} dma_handle_t; + + +typedef struct dmamux_registers +{ + volatile uint32_t dmamux_cr; /*!< DMA interrupt status register */ + +} dmamux_registers_t; + +/*!< @brief DMA HW ISR register structure. */ +typedef struct dma_isr_registers +{ + volatile uint32_t isr; /*!< DMA interrupt status register (DMA_ISR) */ + volatile uint32_t ifcr; /*!< DMA interrupt flag clear register (DMA_IFCR) */ + +} dma_isr_registers_t; + +/*!< @brief DMA HW clock settings structure. */ +typedef struct +{ + uint8_t clock_bit; + hal_ll_base_addr_t clock_base; +} dma_clock_t; + +/*!< @brief DMA control settings structure. */ +typedef struct +{ + dma_clock_t clock; + hal_ll_base_addr_t stream_base; +} dma_control_struct_t; + +// ------------------------------------------------------------------ VARIABLES + +static const dma_control_struct_t dma_controller[ DMA_NUM_OF_MODULES ] = +{ + { + { HAL_LL_DMA1_CLOCK_BIT, HAL_LL_DMA1_CLOCK_BASE }, HAL_LL_DMA1_STREAM_BASE + } + ,{ + { HAL_LL_DMA2_CLOCK_BIT, HAL_LL_DMA2_CLOCK_BASE }, HAL_LL_DMA2_STREAM_BASE + } +}; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS + +/** + * @brief Gets current stream address. + * @details Returns stream address based on @ref module value and + * desired @ref stream value. + * @param[in] module DMA module number. + * @param[in] stream DMA stream number. + * @return hal_ll_base_addr_t stream base register address. + */ +static hal_ll_base_addr_t hal_ll_dma_get_stream_address( uint8_t module, uint8_t stream ); + +/** + * @brief Sets current module clock. + * @details If @ref state is @b true, enables DMA module clock. + * If @ref state is @b false, disables DMA module clock. + * @param[in] dma_obj DMA object. + * @param[in] state Desired state. + * - @b true + * - @b false + * @return Nothing. + */ +static void hal_ll_dma_clock_set( hal_ll_dma_t *dma_obj, bool state ); + +/** + * @brief Initializes DMA module. + * @details Initializes DMA module, stream to + * values from @ref config structure. + * @param[in] dma_obj DMA object. + * @param[in] dma DMA HW handle. + * @param[in] config DMA configuration structure. + * @return hal_ll_err_t Returns initialization state, either success or fail. + */ +static hal_ll_err_t hal_ll_dma_init_hw( hal_ll_dma_t *dma_obj, dma_handle_t *dma, hal_ll_dma_config_t config ); + +/** + * @brief Gets DMA module state. + * @details Checks if current DMA module stream has been stopped. + * Waits for defined @ref DEFAULT_TIMEOUT_VALUE number of cycles + * before jumping out of loop and returning @ref HAL_LL_DMA_ERROR. + * @param[in] dma DMA HW handle. + * @return hal_ll_err_t Returns success or fail. + */ +static inline hal_ll_err_t hal_ll_dma_is_module_disabled( dma_handle_t *dma ); + +/** + * @brief Gets DMA channel. + * @details Returns appropriate value to be set in HW register + * for desired @ref channel. + * @param[in] channel DMA channel number. + * @return uint32_t Returns actual HW register value based on @ref channel. + */ +static inline uint32_t hal_ll_dma_get_reg_value_channel( uint8_t channel ); + +/** + * @brief Gets DMA direction. + * @details Returns appropriate value to be set in HW register + * for desired @ref direction. + * @param[in] direction DMA stream direction. + * Refer to @hal_ll_dma_direction_t for possible values. + * @return uint8_t Returns actual HW register value based on @ref direction. + */ +static inline uint16_t hal_ll_dma_get_reg_value_direction( hal_ll_dma_direction_t direction ); + +/** + * @brief Gets DMA peripheral address increment. + * @details Returns appropriate value to be set in HW register + * for desired @ref set_inc. + * @param[in] set_inc DMA channel peripheral address increment. + * Set to @b true in order to increment address. + * Set to @b false in order to keep address the same. + * @return uint16_t Returns actual HW register value based on @ref set_inc. + */ +static inline uint16_t hal_ll_dma_get_reg_value_dst_inc( bool set_inc ); + +/** + * @brief Gets DMA memory address increment. + * @details Returns appropriate value to be set in HW register + * for desired @ref set_inc. + * @param[in] set_inc DMA channel memory address increment. + * Set to @b true in order to increment address. + * Set to @b false in order to keep address the same. + * @return uint16_t Returns actual HW register value based on @ref set_inc. + */ +static inline uint16_t hal_ll_dma_get_reg_value_src_inc( bool set_inc ); + +/** + * @brief Gets DMA memory address alignment. + * @details Returns appropriate value to be set in HW register + * for desired @ref align. + * @param[in] align DMA channel memory address increment. + * Refer to @ref hal_ll_dma_data_align_t for possible values. + * @return uint16_t Returns actual HW register value based on @ref align. + */ +static inline uint16_t hal_ll_dma_get_reg_value_source_size( hal_ll_dma_data_align_t align ); + +/** + * @brief Gets DMA peripheral address alignment. + * @details Returns appropriate value to be set in HW register + * for desired @ref align. + * @param[in] align DMA channel peripheral address increment. + * Refer to @ref hal_ll_dma_data_align_t for possible values. + * @return uint16_t Returns actual HW register value based on @ref align. + */ +static inline uint16_t hal_ll_dma_get_reg_value_destination_size( hal_ll_dma_data_align_t align ); + +/** + * @brief Gets DMA mode value. + * @details Returns appropriate value to be set in HW register + * for desired @ref mode. + * @param[in] mode DMA mode for object channel. + * Refer to @ref hal_ll_dma_mode_t for possible values. + * @return uint16_t Returns actual HW register value based on @ref mode. + */ +static inline uint16_t hal_ll_dma_get_reg_value_mode( hal_ll_dma_mode_t mode ); + +/** + * @brief Gets DMA priority value. + * @details Returns appropriate value to be set in HW register + * for desired @ref priority. + * @param[in] priority DMA priority for object channel. + * Refer to @ref hal_ll_dma_priority_t for possible values. + * @return uint32_t Returns actual HW register value based on @ref priority. + */ +static inline uint32_t hal_ll_dma_get_reg_value_priority( hal_ll_dma_priority_t priority ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS + +hal_ll_err_t hal_ll_dma_init( hal_ll_dma_t *obj ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + + // Enable PWRCLK. + #ifdef HAL_LL_PWRCLK_BASE + _HAL_LL_ENABLE_CLOCK_PWR_; + #endif + + // Enable current stream clock. + hal_ll_dma_clock_set( obj, true ); + + // Initialize current stream. + obj->handle = hal_ll_dma_get_stream_address( obj->module, obj->stream ); + status = hal_ll_dma_init_hw( obj, + (dma_handle_t *)obj->handle, + obj->config ); + + if ( HAL_LL_DMA_SUCCESS != status ) { + obj->handle = 0; // If initialization failed, reset handle. + } + + return status; +} + +hal_ll_err_t hal_ll_dma_deinit( hal_ll_dma_t *obj ) { + // First abort current transfer. + if ( HAL_LL_DMA_SUCCESS != hal_ll_dma_transfer_abort( obj ) ) + return HAL_LL_DMA_ERROR; + // Finally, disable module clock. + hal_ll_dma_clock_set( obj, false ); + + return HAL_LL_DMA_SUCCESS; +} + +hal_ll_err_t hal_ll_dma_set_mode( hal_ll_dma_t *obj, hal_ll_dma_mode_t mode ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + // Get new mode. + hal_ll_dma_config_t cfg = obj->config; + cfg.mode = mode; + // Disable module first. + HAL_LL_DMA_MODULE_DISABLE( ((dma_handle_t *)obj->handle) ); + // Try to set new mode. + status = hal_ll_dma_init_hw( obj, + (dma_handle_t *)obj->handle, + cfg ); + + return status; +} + +hal_ll_err_t hal_ll_dma_set_direction( hal_ll_dma_t *obj, hal_ll_dma_direction_t direction ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + // Get new direction. + hal_ll_dma_config_t cfg = obj->config; + cfg.direction = direction; + // Disable module first. + HAL_LL_DMA_MODULE_DISABLE( ((dma_handle_t *)obj->handle) ); + // Try to set new value. + status = hal_ll_dma_init_hw( obj, + (dma_handle_t *)obj->handle, + cfg ); + + return status; +} + +hal_ll_err_t hal_ll_dma_set_priority( hal_ll_dma_t *obj, hal_ll_dma_priority_t priority ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + // Get new priority. + hal_ll_dma_config_t cfg = obj->config; + cfg.priority = priority; + // Disable module first. + HAL_LL_DMA_MODULE_DISABLE( ((dma_handle_t *)obj->handle) ); + // Try to set new value. + status = hal_ll_dma_init_hw( obj, + (dma_handle_t *)obj->handle, + cfg ); + + return status; +} + +hal_ll_err_t hal_ll_dma_set_parameters( hal_ll_dma_t *obj, uint32_t addr_src, uint32_t addr_dst, size_t transfer_size, hal_ll_dma_source_memory_region_t src_mem_type ) { + dma_handle_t *dma = (dma_handle_t *)obj->handle; + uint8_t ndtr_divisor; + + // This parameter is not relevant on this architecture. + (void)src_mem_type; + + // Configure DMA Stream data length. + switch ( obj->config.data_align_destination ) { + case HAL_LL_DMA_DATA_ALIGN_BYTES_1: + case HAL_LL_DMA_DATA_ALIGN_BYTES_2: + ndtr_divisor = obj->config.data_align_destination; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_4: + ndtr_divisor = 2; + break; + + default: + return HAL_LL_DMA_ERROR; + } + dma->ndtr = transfer_size >> ndtr_divisor; + + // Memory to Peripheral. + if ( HAL_LL_DMA_DIRECTION_MEMORY_TO_PERIPH == obj->config.direction ) { + // Configure DMA stream destination address. + dma->par = addr_dst; + // Configure DMA stream source address. + dma->mar = addr_src; + } else { // Peripheral to Memory. + // Configure DMA stream source address. + dma->par = addr_src; + // Configure DMA stream destination address. + dma->mar = addr_dst; + } + return HAL_LL_DMA_SUCCESS; +} + +hal_ll_err_t hal_ll_dma_transfer_start( hal_ll_dma_t *obj ) { + HAL_LL_DMA_MODULE_ENABLE( ((dma_handle_t *)obj->handle) ); + return HAL_LL_DMA_SUCCESS; +} + +hal_ll_err_t hal_ll_dma_transfer_stop( hal_ll_dma_t *obj ) { + dma_handle_t *dma = (dma_handle_t *)obj->handle; + uint16_t timeout = DEFAULT_TIMEOUT_VALUE; + + if ( HAL_LL_DMA_MODE_CIRCULAR == obj->config.mode ) + return HAL_LL_DMA_ERROR; + + while ( dma->ndtr ) { + if ( 0 == timeout-- ) + return HAL_LL_DMA_ERROR; + } + + HAL_LL_DMA_MODULE_DISABLE( dma ); + + return HAL_LL_DMA_SUCCESS; +} + +hal_ll_err_t hal_ll_dma_transfer_abort( hal_ll_dma_t *obj ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + dma_handle_t *dma = (dma_handle_t *)obj->handle; + + // Calculate DMA base and stream number. + dma_isr_registers_t *regs = (dma_isr_registers_t *)(dma_controller[obj->module].stream_base - CCR_BASE_OFFSET); + + // Disable all the transfer interrupts. + dma->cr &= ~(HAL_LL_DMA_CCR_TCIE_BIT | HAL_LL_DMA_CCR_HTIE_BIT | HAL_LL_DMA_CCR_TEIE_BIT); + + // Disable the stream. + HAL_LL_DMA_MODULE_DISABLE( dma ); + + // Wait for bit to be cleared. + status = hal_ll_dma_is_module_disabled( dma ); + + // Clear all interrupt flags at correct offset within the register. + if ( HAL_LL_DMA_SUCCESS == status ) + regs->ifcr = HAL_LL_DMA_IT_CLEAR_MASK << ( obj->stream * 4 ); + + return status; +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS + +static hal_ll_base_addr_t hal_ll_dma_get_stream_address( uint8_t module, uint8_t stream ) { + return ((hal_ll_base_addr_t)dma_controller[module].stream_base + (hal_ll_base_addr_t)(STREAM_BASE_OFFSET * (stream))); +} + +static void hal_ll_dma_clock_set( hal_ll_dma_t *obj, bool state ) { + if ( state ) { + set_reg_bit( (uint32_t *)dma_controller[obj->module].clock.clock_base, + dma_controller[obj->module].clock.clock_bit ); + set_reg_bit( (uint32_t *)dma_controller[obj->module].clock.clock_base, HAL_LL_DMAMUX1_CLOCK_BIT); + } else { + clear_reg_bit( (uint32_t *)dma_controller[obj->module].clock.clock_base, + dma_controller[obj->module].clock.clock_bit ); + } +} + +static hal_ll_err_t hal_ll_dma_init_hw( hal_ll_dma_t *obj, dma_handle_t *dma, hal_ll_dma_config_t config ) { + volatile uint32_t tmp = 0UL; + // Check if user entered invalid data aka HAL_LL_DMA_DATA_ALIGN_BYTES_3 + if (HAL_LL_DMA_DATA_ALIGN_BYTES_3 == config.data_align_source || HAL_LL_DMA_DATA_ALIGN_BYTES_3 == config.data_align_destination ) { + return HAL_LL_DMA_ERROR; + } + + // Disable the peripheral first. + HAL_LL_DMA_MODULE_DISABLE(dma); + + // Wait for bit to be cleared. + if ( HAL_LL_DMA_ERROR == hal_ll_dma_is_module_disabled( dma ) ) + return HAL_LL_DMA_ERROR; + + // Get the CR register value. + tmp = dma->cr; + + // Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits. + tmp &= ((uint32_t)~( HAL_LL_DMA_CCR_EN_BIT | HAL_LL_DMA_CCR_TCIE_BIT | HAL_LL_DMA_CCR_HTIE_BIT | \ + HAL_LL_DMA_CCR_TEIE_BIT | HAL_LL_DMA_CCR_DIR_BIT | HAL_LL_DMA_CCR_CIRC_BIT | \ + HAL_LL_DMA_CCR_PINC_BIT | HAL_LL_DMA_CCR_MINC_BIT | HAL_LL_DMA_CCR_M2M_BIT | \ + HAL_LL_DMA_CCR_PSIZE_MASK | HAL_LL_DMA_CCR_MSIZE_MASK | HAL_LL_DMA_CCR_PRIO_MASK )); + + // BEGIN Prepare the DMA stream configuration. + // Set desired direction value. + tmp |= hal_ll_dma_get_reg_value_direction(config.direction); + // Set desired memory increment settings. + tmp |= hal_ll_dma_get_reg_value_src_inc(config.src_inc); + tmp |= hal_ll_dma_get_reg_value_dst_inc(config.dst_inc); + // Set desired data size settings. + tmp |= hal_ll_dma_get_reg_value_source_size(config.data_align_source); + tmp |= hal_ll_dma_get_reg_value_destination_size(config.data_align_destination); + // Set desired mode. + tmp |= hal_ll_dma_get_reg_value_mode(config.mode); + // Finally, set desired priority. + tmp |= hal_ll_dma_get_reg_value_priority(config.priority); + + // And then write to DMA stream CR register. + dma->cr = tmp; + + if (obj->module == 0 ) { + dmamux_registers_t * dmamux = (dmamux_registers_t*)( DMAMUX1_BASE + ( obj->stream * DMAMUX1_OFFSET ) ); + dmamux->dmamux_cr |= obj->channel; + } else { + dmamux_registers_t * dmamux = (dmamux_registers_t*)( DMAMUX1_BASE + ( DMA_NUM_OF_STREAMS * DMAMUX1_OFFSET ) + ( obj->stream * DMAMUX1_OFFSET ) ); + dmamux->dmamux_cr |= obj->channel; + } + + return HAL_LL_DMA_SUCCESS; +} + +static inline hal_ll_err_t hal_ll_dma_is_module_disabled( dma_handle_t *dma ) { + uint16_t timeout = DEFAULT_TIMEOUT_VALUE; + + while ( (dma->cr & (1U << HAL_LL_DMA_CCR_EN_BIT)) != 0 ) { + if ( 0 == timeout-- ) + return HAL_LL_DMA_ERROR; + } + + return HAL_LL_DMA_SUCCESS; +} + +static inline uint16_t hal_ll_dma_get_reg_value_direction( hal_ll_dma_direction_t direction ) { + volatile uint16_t direction_set = (uint8_t)HAL_LL_DMA_DIRECTION_MEMORY_TO_MEMORY; + + switch ( direction ) + { + case HAL_LL_DMA_DIRECTION_MEMORY_TO_MEMORY: + direction_set = HAL_LL_DMA_DIRECTION_MEMORY_TO_MEMORY_MASK; + break; + case HAL_LL_DMA_DIRECTION_MEMORY_TO_PERIPH: + direction_set = HAL_LL_DMA_DIRECTION_MEMORY_TO_PERIPH_MASK; + break; + case HAL_LL_DMA_DIRECTION_PERIPH_TO_MEMORY: + direction_set = HAL_LL_DMA_DIRECTION_PERIPH_TO_MEMORY_MASK; + break; + + default: + break; + } + + return (uint16_t)direction_set; +} + +static inline uint16_t hal_ll_dma_get_reg_value_dst_inc( bool set_inc ) { + return (uint16_t)((set_inc) ? (HAL_LL_DMA_PINC_MASK) : (0)); +} + +static inline uint16_t hal_ll_dma_get_reg_value_src_inc( bool set_inc ) { + return (uint16_t)((set_inc) ? (HAL_LL_DMA_MINC_MASK) : (0)); +} + +static inline uint16_t hal_ll_dma_get_reg_value_source_size( hal_ll_dma_data_align_t align ) { + volatile uint16_t align_set = (uint16_t)HAL_LL_DMA_DATA_ALIGN_BYTES_1; + + switch ( align ) + { + case HAL_LL_DMA_DATA_ALIGN_BYTES_1: + align_set = HAL_LL_DMA_MSIZE_BYTE_MASK; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_2: + align_set = HAL_LL_DMA_MSIZE_HALFWORD_MASK; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_4: + align_set = HAL_LL_DMA_MSIZE_WORD_MASK; + break; + + default: + break; + } + + return (uint16_t)align_set; +} + +static inline uint16_t hal_ll_dma_get_reg_value_destination_size( hal_ll_dma_data_align_t align ) { + volatile uint16_t align_set = (uint16_t)HAL_LL_DMA_DATA_ALIGN_BYTES_1; + + switch ( align ) + { + case HAL_LL_DMA_DATA_ALIGN_BYTES_1: + align_set = HAL_LL_DMA_CCR_PSIZE_BYTE_MASK; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_2: + align_set = HAL_LL_DMA_CCR_PSIZE_HALFWORD_MASK; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_4: + align_set = HAL_LL_DMA_CCR_PSIZE_WORD_MASK; + break; + + default: + break; + } + + return (uint16_t)align_set; +} + +static inline uint16_t hal_ll_dma_get_reg_value_mode( hal_ll_dma_mode_t mode ) { + return (uint16_t)((mode) ? (HAL_LL_DMA_CCR_CIRC_MASK) : (0)); +} + +static inline uint32_t hal_ll_dma_get_reg_value_priority( hal_ll_dma_priority_t priority ) { + volatile uint32_t priority_set = (uint32_t)HAL_LL_DMA_PRIORITY_LOW; + + switch ( priority ) + { + case HAL_LL_DMA_PRIORITY_LOW: + priority_set = HAL_LL_DMA_CCR_PRIORITY_LOW_MASK; + break; + case HAL_LL_DMA_PRIORITY_MEDIUM: + priority_set = HAL_LL_DMA_CCR_PRIORITY_MEDIUM_MASK; + break; + case HAL_LL_DMA_PRIORITY_HIGH: + priority_set = HAL_LL_DMA_CCR_PRIORITY_HIGH_MASK; + break; + case HAL_LL_DMA_PRIORITY_VERY_HIGH: + priority_set = HAL_LL_DMA_CCR_PRIORITY_VERY_HIGH_MASK; + break; + + default: + break; + } + + return (uint32_t)priority_set; +} + +// ------------------------------------------------------------------------- END + + + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_86/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_86/CMakeLists.cmake new file mode 100644 index 000000000..7bdd008e6 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_86/CMakeLists.cmake @@ -0,0 +1,8 @@ +if(${MCU_NAME} MATCHES "^STM32G483CE$|^STM32G483RE$|^STM32G483ME$|^STM32G483PE$|^STM32G483VE$|^STM32G483QE$") + set(dma_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_dma.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_86") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_86") + list(APPEND hal_ll_def_list "STM32G4xx") + list(APPEND hal_ll_def_list "STM32G48xx") + list(APPEND hal_ll_def_list "STM32G483xx") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_86/hal_ll_dma.c b/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_86/hal_ll_dma.c new file mode 100644 index 000000000..2ed93bbdb --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_86/hal_ll_dma.c @@ -0,0 +1,661 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_dma.c + * @brief DMA HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_rcc.h" +#include "hal_ll_dma.h" +#include "hal_ll_gpio.h" + +// ------------------------------------------------------------- PRIVATE MACROS + + +/*!< @brief DMA interrupt definitions. */ +#define HAL_LL_DMA_IT_FT ((uint32_t)(1U << 1)) +#define HAL_LL_DMA_IT_HT ((uint32_t)(1U << 2)) +#define HAL_LL_DMA_IT_ET ((uint32_t)(1U << 3)) +#define HAL_LL_DMA_IT_CLEAR_MASK (0x0fUL) + +/*!< @brief DMA SCR register masks. */ + + + +#define HAL_LL_DMA_CCR_PRIORITY_VERY_HIGH_MASK (0x00003000) +#define HAL_LL_DMA_CCR_PRIORITY_HIGH_MASK (0x00002000) +#define HAL_LL_DMA_CCR_PRIORITY_MEDIUM_MASK (0x00001000) +#define HAL_LL_DMA_CCR_PRIORITY_LOW_MASK (0x00000000) +#define HAL_LL_DMA_CCR_CIRC_MASK (0x00000020) +#define HAL_LL_DMA_CCR_PSIZE_BYTE_MASK (0x00000000) +#define HAL_LL_DMA_CCR_PSIZE_HALFWORD_MASK (0x00000100) +#define HAL_LL_DMA_CCR_PSIZE_WORD_MASK (0x00000200) +#define HAL_LL_DMA_MSIZE_BYTE_MASK (0x00000000) +#define HAL_LL_DMA_MSIZE_HALFWORD_MASK (0x00000400) +#define HAL_LL_DMA_MSIZE_WORD_MASK (0x00000800) +#define HAL_LL_DMA_MINC_MASK (0x00000080) +#define HAL_LL_DMA_PINC_MASK (0x00000040) + +#define HAL_LL_DMA_DIRECTION_MEMORY_TO_MEMORY_MASK (0x4000) +#define HAL_LL_DMA_DIRECTION_MEMORY_TO_PERIPH_MASK (0x10) +#define HAL_LL_DMA_DIRECTION_PERIPH_TO_MEMORY_MASK (0x0) + +#define HAL_LL_DMA_CCR_PSIZE_MASK (0x00000300) +#define HAL_LL_DMA_CCR_MSIZE_MASK (0x00000C00) +#define HAL_LL_DMA_CCR_PRIO_MASK (0x00003000) +#define HAL_LL_DMA_CCR_EN_BIT (0) +#define HAL_LL_DMA_CCR_TEIE_BIT (3) +#define HAL_LL_DMA_CCR_HTIE_BIT (2) +#define HAL_LL_DMA_CCR_TCIE_BIT (1) +#define HAL_LL_DMA_CCR_DIR_BIT (4) +#define HAL_LL_DMA_CCR_CIRC_BIT (5) +#define HAL_LL_DMA_CCR_PINC_BIT (6) +#define HAL_LL_DMA_CCR_MINC_BIT (7) +#define HAL_LL_DMA_CCR_M2M_BIT (14) + + + +#define DMA1_BASE (0x40020000UL) +#define DMA2_BASE (0x40020400UL) + +#define HAL_LL_DMA1_CLOCK_BIT (0) +#define HAL_LL_DMA1_CLOCK_BASE ((uint32_t)_RCC_AHB1ENR) +#define HAL_LL_DMA1_STREAM_BASE (DMA1_BASE + CCR_BASE_OFFSET) +#define HAL_LL_DMA2_CLOCK_BIT (1) +#define HAL_LL_DMA2_CLOCK_BASE ((uint32_t)_RCC_AHB1ENR) +#define HAL_LL_DMA2_STREAM_BASE (DMA2_BASE + CCR_BASE_OFFSET) + +#define CCR_BASE_OFFSET (0x8U) +#define STREAM_BASE_OFFSET (0x14U) +#define IFCR_BASE_OFFSET (0x4U) +#define HAL_LL_PWRCLK_BIT (28) + +/*diff bits/offsets:*/ +#define HAL_LL_PWRCLK_BASE (_RCC_APB1ENR1) + +#define DMAMUX1_BASE (0x40020800UL) +#define DMAMUX1_OFFSET (0x04U) +#define HAL_LL_DMAMUX1_CLOCK_BIT (2) + + + + + +/*!< @brief Clock enable macros. */ +#ifdef HAL_LL_PWRCLK_BASE +#define _HAL_LL_ENABLE_CLOCK_PWR_ ((HAL_LL_PWRCLK_BASE) ? (*HAL_LL_PWRCLK_BASE |= 1UL << HAL_LL_PWRCLK_BIT) : 0) +#endif + +/*!< @brief DMA module enable macro. */ +#define HAL_LL_DMA_MODULE_ENABLE(_x) (_x->cr |= 1U << HAL_LL_DMA_CCR_EN_BIT) + +/*!< @brief DMA module disable macro. */ +#define HAL_LL_DMA_MODULE_DISABLE(_x) (_x->cr &= ~(1U << HAL_LL_DMA_CCR_EN_BIT)) + +/*!< @brief Default timeout value to wait when checking if module is disabled/enabled. */ +#define DEFAULT_TIMEOUT_VALUE (0xFFFFU) + +// ----------------------------------------------------------- PRIVATE TYPEDEFS + +/*!< @brief DMA HW register structure. */ +typedef struct dma_handle +{ + volatile uint32_t cr; /*!< DMA channel x configuration register (DMA_CCRx) */ + volatile uint32_t ndtr; /*!< DMA channel x number of data to transfer register (DMA_CNDTRx) */ + volatile uint32_t par; /*!< DMA channel x peripheral address register (DMA_CPARx) */ + volatile uint32_t mar; /*!< DMA channel x memory address register (DMA_CMARx) */ + +} dma_handle_t; + + +typedef struct dmamux_registers +{ + volatile uint32_t dmamux_cr; /*!< DMA interrupt status register */ + +} dmamux_registers_t; + +/*!< @brief DMA HW ISR register structure. */ +typedef struct dma_isr_registers +{ + volatile uint32_t isr; /*!< DMA interrupt status register (DMA_ISR) */ + volatile uint32_t ifcr; /*!< DMA interrupt flag clear register (DMA_IFCR) */ + +} dma_isr_registers_t; + +/*!< @brief DMA HW clock settings structure. */ +typedef struct +{ + uint8_t clock_bit; + hal_ll_base_addr_t clock_base; +} dma_clock_t; + +/*!< @brief DMA control settings structure. */ +typedef struct +{ + dma_clock_t clock; + hal_ll_base_addr_t stream_base; +} dma_control_struct_t; + +// ------------------------------------------------------------------ VARIABLES + +static const dma_control_struct_t dma_controller[ DMA_NUM_OF_MODULES ] = +{ + { + { HAL_LL_DMA1_CLOCK_BIT, HAL_LL_DMA1_CLOCK_BASE }, HAL_LL_DMA1_STREAM_BASE + } + ,{ + { HAL_LL_DMA2_CLOCK_BIT, HAL_LL_DMA2_CLOCK_BASE }, HAL_LL_DMA2_STREAM_BASE + } +}; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS + +/** + * @brief Gets current stream address. + * @details Returns stream address based on @ref module value and + * desired @ref stream value. + * @param[in] module DMA module number. + * @param[in] stream DMA stream number. + * @return hal_ll_base_addr_t stream base register address. + */ +static hal_ll_base_addr_t hal_ll_dma_get_stream_address( uint8_t module, uint8_t stream ); + +/** + * @brief Sets current module clock. + * @details If @ref state is @b true, enables DMA module clock. + * If @ref state is @b false, disables DMA module clock. + * @param[in] dma_obj DMA object. + * @param[in] state Desired state. + * - @b true + * - @b false + * @return Nothing. + */ +static void hal_ll_dma_clock_set( hal_ll_dma_t *dma_obj, bool state ); + +/** + * @brief Initializes DMA module. + * @details Initializes DMA module, stream to + * values from @ref config structure. + * @param[in] dma_obj DMA object. + * @param[in] dma DMA HW handle. + * @param[in] config DMA configuration structure. + * @return hal_ll_err_t Returns initialization state, either success or fail. + */ +static hal_ll_err_t hal_ll_dma_init_hw( hal_ll_dma_t *dma_obj, dma_handle_t *dma, hal_ll_dma_config_t config ); + +/** + * @brief Gets DMA module state. + * @details Checks if current DMA module stream has been stopped. + * Waits for defined @ref DEFAULT_TIMEOUT_VALUE number of cycles + * before jumping out of loop and returning @ref HAL_LL_DMA_ERROR. + * @param[in] dma DMA HW handle. + * @return hal_ll_err_t Returns success or fail. + */ +static inline hal_ll_err_t hal_ll_dma_is_module_disabled( dma_handle_t *dma ); + +/** + * @brief Gets DMA channel. + * @details Returns appropriate value to be set in HW register + * for desired @ref channel. + * @param[in] channel DMA channel number. + * @return uint32_t Returns actual HW register value based on @ref channel. + */ +static inline uint32_t hal_ll_dma_get_reg_value_channel( uint8_t channel ); + +/** + * @brief Gets DMA direction. + * @details Returns appropriate value to be set in HW register + * for desired @ref direction. + * @param[in] direction DMA stream direction. + * Refer to @hal_ll_dma_direction_t for possible values. + * @return uint8_t Returns actual HW register value based on @ref direction. + */ +static inline uint16_t hal_ll_dma_get_reg_value_direction( hal_ll_dma_direction_t direction ); + +/** + * @brief Gets DMA peripheral address increment. + * @details Returns appropriate value to be set in HW register + * for desired @ref set_inc. + * @param[in] set_inc DMA channel peripheral address increment. + * Set to @b true in order to increment address. + * Set to @b false in order to keep address the same. + * @return uint16_t Returns actual HW register value based on @ref set_inc. + */ +static inline uint16_t hal_ll_dma_get_reg_value_dst_inc( bool set_inc ); + +/** + * @brief Gets DMA memory address increment. + * @details Returns appropriate value to be set in HW register + * for desired @ref set_inc. + * @param[in] set_inc DMA channel memory address increment. + * Set to @b true in order to increment address. + * Set to @b false in order to keep address the same. + * @return uint16_t Returns actual HW register value based on @ref set_inc. + */ +static inline uint16_t hal_ll_dma_get_reg_value_src_inc( bool set_inc ); + +/** + * @brief Gets DMA memory address alignment. + * @details Returns appropriate value to be set in HW register + * for desired @ref align. + * @param[in] align DMA channel memory address increment. + * Refer to @ref hal_ll_dma_data_align_t for possible values. + * @return uint16_t Returns actual HW register value based on @ref align. + */ +static inline uint16_t hal_ll_dma_get_reg_value_source_size( hal_ll_dma_data_align_t align ); + +/** + * @brief Gets DMA peripheral address alignment. + * @details Returns appropriate value to be set in HW register + * for desired @ref align. + * @param[in] align DMA channel peripheral address increment. + * Refer to @ref hal_ll_dma_data_align_t for possible values. + * @return uint16_t Returns actual HW register value based on @ref align. + */ +static inline uint16_t hal_ll_dma_get_reg_value_destination_size( hal_ll_dma_data_align_t align ); + +/** + * @brief Gets DMA mode value. + * @details Returns appropriate value to be set in HW register + * for desired @ref mode. + * @param[in] mode DMA mode for object channel. + * Refer to @ref hal_ll_dma_mode_t for possible values. + * @return uint16_t Returns actual HW register value based on @ref mode. + */ +static inline uint16_t hal_ll_dma_get_reg_value_mode( hal_ll_dma_mode_t mode ); + +/** + * @brief Gets DMA priority value. + * @details Returns appropriate value to be set in HW register + * for desired @ref priority. + * @param[in] priority DMA priority for object channel. + * Refer to @ref hal_ll_dma_priority_t for possible values. + * @return uint32_t Returns actual HW register value based on @ref priority. + */ +static inline uint32_t hal_ll_dma_get_reg_value_priority( hal_ll_dma_priority_t priority ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS + +hal_ll_err_t hal_ll_dma_init( hal_ll_dma_t *obj ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + + // Enable PWRCLK. + #ifdef HAL_LL_PWRCLK_BASE + _HAL_LL_ENABLE_CLOCK_PWR_; + #endif + + // Enable current stream clock. + hal_ll_dma_clock_set( obj, true ); + + // Initialize current stream. + obj->handle = hal_ll_dma_get_stream_address( obj->module, obj->stream ); + status = hal_ll_dma_init_hw( obj, + (dma_handle_t *)obj->handle, + obj->config ); + + if ( HAL_LL_DMA_SUCCESS != status ) { + obj->handle = 0; // If initialization failed, reset handle. + } + + return status; +} + +hal_ll_err_t hal_ll_dma_deinit( hal_ll_dma_t *obj ) { + // First abort current transfer. + if ( HAL_LL_DMA_SUCCESS != hal_ll_dma_transfer_abort( obj ) ) + return HAL_LL_DMA_ERROR; + // Finally, disable module clock. + hal_ll_dma_clock_set( obj, false ); + + return HAL_LL_DMA_SUCCESS; +} + +hal_ll_err_t hal_ll_dma_set_mode( hal_ll_dma_t *obj, hal_ll_dma_mode_t mode ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + // Get new mode. + hal_ll_dma_config_t cfg = obj->config; + cfg.mode = mode; + // Disable module first. + HAL_LL_DMA_MODULE_DISABLE( ((dma_handle_t *)obj->handle) ); + // Try to set new mode. + status = hal_ll_dma_init_hw( obj, + (dma_handle_t *)obj->handle, + cfg ); + + return status; +} + +hal_ll_err_t hal_ll_dma_set_direction( hal_ll_dma_t *obj, hal_ll_dma_direction_t direction ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + // Get new direction. + hal_ll_dma_config_t cfg = obj->config; + cfg.direction = direction; + // Disable module first. + HAL_LL_DMA_MODULE_DISABLE( ((dma_handle_t *)obj->handle) ); + // Try to set new value. + status = hal_ll_dma_init_hw( obj, + (dma_handle_t *)obj->handle, + cfg ); + + return status; +} + +hal_ll_err_t hal_ll_dma_set_priority( hal_ll_dma_t *obj, hal_ll_dma_priority_t priority ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + // Get new priority. + hal_ll_dma_config_t cfg = obj->config; + cfg.priority = priority; + // Disable module first. + HAL_LL_DMA_MODULE_DISABLE( ((dma_handle_t *)obj->handle) ); + // Try to set new value. + status = hal_ll_dma_init_hw( obj, + (dma_handle_t *)obj->handle, + cfg ); + + return status; +} + +hal_ll_err_t hal_ll_dma_set_parameters( hal_ll_dma_t *obj, uint32_t addr_src, uint32_t addr_dst, size_t transfer_size, hal_ll_dma_source_memory_region_t src_mem_type ) { + dma_handle_t *dma = (dma_handle_t *)obj->handle; + uint8_t ndtr_divisor; + + // This parameter is not relevant on this architecture. + (void)src_mem_type; + + // Configure DMA Stream data length. + switch ( obj->config.data_align_destination ) { + case HAL_LL_DMA_DATA_ALIGN_BYTES_1: + case HAL_LL_DMA_DATA_ALIGN_BYTES_2: + ndtr_divisor = obj->config.data_align_destination; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_4: + ndtr_divisor = 2; + break; + + default: + return HAL_LL_DMA_ERROR; + } + dma->ndtr = transfer_size >> ndtr_divisor; + + // Memory to Peripheral. + if ( HAL_LL_DMA_DIRECTION_MEMORY_TO_PERIPH == obj->config.direction ) { + // Configure DMA stream destination address. + dma->par = addr_dst; + // Configure DMA stream source address. + dma->mar = addr_src; + } else { // Peripheral to Memory. + // Configure DMA stream source address. + dma->par = addr_src; + // Configure DMA stream destination address. + dma->mar = addr_dst; + } + return HAL_LL_DMA_SUCCESS; +} + +hal_ll_err_t hal_ll_dma_transfer_start( hal_ll_dma_t *obj ) { + HAL_LL_DMA_MODULE_ENABLE( ((dma_handle_t *)obj->handle) ); + return HAL_LL_DMA_SUCCESS; +} + +hal_ll_err_t hal_ll_dma_transfer_stop( hal_ll_dma_t *obj ) { + dma_handle_t *dma = (dma_handle_t *)obj->handle; + uint16_t timeout = DEFAULT_TIMEOUT_VALUE; + + if ( HAL_LL_DMA_MODE_CIRCULAR == obj->config.mode ) + return HAL_LL_DMA_ERROR; + + while ( dma->ndtr ) { + if ( 0 == timeout-- ) + return HAL_LL_DMA_ERROR; + } + + HAL_LL_DMA_MODULE_DISABLE( dma ); + + return HAL_LL_DMA_SUCCESS; +} + +hal_ll_err_t hal_ll_dma_transfer_abort( hal_ll_dma_t *obj ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + dma_handle_t *dma = (dma_handle_t *)obj->handle; + + // Calculate DMA base and stream number. + dma_isr_registers_t *regs = (dma_isr_registers_t *)(dma_controller[obj->module].stream_base - CCR_BASE_OFFSET); + + // Disable all the transfer interrupts. + dma->cr &= ~(HAL_LL_DMA_CCR_TCIE_BIT | HAL_LL_DMA_CCR_HTIE_BIT | HAL_LL_DMA_CCR_TEIE_BIT); + + // Disable the stream. + HAL_LL_DMA_MODULE_DISABLE( dma ); + + // Wait for bit to be cleared. + status = hal_ll_dma_is_module_disabled( dma ); + + // Clear all interrupt flags at correct offset within the register. + if ( HAL_LL_DMA_SUCCESS == status ) + regs->ifcr = HAL_LL_DMA_IT_CLEAR_MASK << ( obj->stream * 4 ); + + return status; +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS + +static hal_ll_base_addr_t hal_ll_dma_get_stream_address( uint8_t module, uint8_t stream ) { + return ((hal_ll_base_addr_t)dma_controller[module].stream_base + (hal_ll_base_addr_t)(STREAM_BASE_OFFSET * (stream))); +} + +static void hal_ll_dma_clock_set( hal_ll_dma_t *obj, bool state ) { + if ( state ) { + set_reg_bit( (uint32_t *)dma_controller[obj->module].clock.clock_base, + dma_controller[obj->module].clock.clock_bit ); + set_reg_bit( (uint32_t *)dma_controller[obj->module].clock.clock_base, HAL_LL_DMAMUX1_CLOCK_BIT); + } else { + clear_reg_bit( (uint32_t *)dma_controller[obj->module].clock.clock_base, + dma_controller[obj->module].clock.clock_bit ); + } +} + +static hal_ll_err_t hal_ll_dma_init_hw( hal_ll_dma_t *obj, dma_handle_t *dma, hal_ll_dma_config_t config ) { + volatile uint32_t tmp = 0UL; + // Check if user entered invalid data aka HAL_LL_DMA_DATA_ALIGN_BYTES_3 + if (HAL_LL_DMA_DATA_ALIGN_BYTES_3 == config.data_align_source || HAL_LL_DMA_DATA_ALIGN_BYTES_3 == config.data_align_destination ) { + return HAL_LL_DMA_ERROR; + } + + // Disable the peripheral first. + HAL_LL_DMA_MODULE_DISABLE(dma); + + // Wait for bit to be cleared. + if ( HAL_LL_DMA_ERROR == hal_ll_dma_is_module_disabled( dma ) ) + return HAL_LL_DMA_ERROR; + + // Get the CR register value. + tmp = dma->cr; + + // Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits. + tmp &= ((uint32_t)~( HAL_LL_DMA_CCR_EN_BIT | HAL_LL_DMA_CCR_TCIE_BIT | HAL_LL_DMA_CCR_HTIE_BIT | \ + HAL_LL_DMA_CCR_TEIE_BIT | HAL_LL_DMA_CCR_DIR_BIT | HAL_LL_DMA_CCR_CIRC_BIT | \ + HAL_LL_DMA_CCR_PINC_BIT | HAL_LL_DMA_CCR_MINC_BIT | HAL_LL_DMA_CCR_M2M_BIT | \ + HAL_LL_DMA_CCR_PSIZE_MASK | HAL_LL_DMA_CCR_MSIZE_MASK | HAL_LL_DMA_CCR_PRIO_MASK )); + + // BEGIN Prepare the DMA stream configuration. + // Set desired direction value. + tmp |= hal_ll_dma_get_reg_value_direction(config.direction); + // Set desired memory increment settings. + tmp |= hal_ll_dma_get_reg_value_src_inc(config.src_inc); + tmp |= hal_ll_dma_get_reg_value_dst_inc(config.dst_inc); + // Set desired data size settings. + tmp |= hal_ll_dma_get_reg_value_source_size(config.data_align_source); + tmp |= hal_ll_dma_get_reg_value_destination_size(config.data_align_destination); + // Set desired mode. + tmp |= hal_ll_dma_get_reg_value_mode(config.mode); + // Finally, set desired priority. + tmp |= hal_ll_dma_get_reg_value_priority(config.priority); + + // And then write to DMA stream CR register. + dma->cr = tmp; + + if (obj->module == 0 ) { + dmamux_registers_t * dmamux = (dmamux_registers_t*)( DMAMUX1_BASE + ( obj->stream * DMAMUX1_OFFSET ) ); + dmamux->dmamux_cr |= obj->channel; + } else { + dmamux_registers_t * dmamux = (dmamux_registers_t*)( DMAMUX1_BASE + ( DMA_NUM_OF_STREAMS * DMAMUX1_OFFSET ) + ( obj->stream * DMAMUX1_OFFSET ) ); + dmamux->dmamux_cr |= obj->channel; + } + + return HAL_LL_DMA_SUCCESS; +} + +static inline hal_ll_err_t hal_ll_dma_is_module_disabled( dma_handle_t *dma ) { + uint16_t timeout = DEFAULT_TIMEOUT_VALUE; + + while ( (dma->cr & (1U << HAL_LL_DMA_CCR_EN_BIT)) != 0 ) { + if ( 0 == timeout-- ) + return HAL_LL_DMA_ERROR; + } + + return HAL_LL_DMA_SUCCESS; +} + +static inline uint16_t hal_ll_dma_get_reg_value_direction( hal_ll_dma_direction_t direction ) { + volatile uint16_t direction_set = (uint8_t)HAL_LL_DMA_DIRECTION_MEMORY_TO_MEMORY; + + switch ( direction ) + { + case HAL_LL_DMA_DIRECTION_MEMORY_TO_MEMORY: + direction_set = HAL_LL_DMA_DIRECTION_MEMORY_TO_MEMORY_MASK; + break; + case HAL_LL_DMA_DIRECTION_MEMORY_TO_PERIPH: + direction_set = HAL_LL_DMA_DIRECTION_MEMORY_TO_PERIPH_MASK; + break; + case HAL_LL_DMA_DIRECTION_PERIPH_TO_MEMORY: + direction_set = HAL_LL_DMA_DIRECTION_PERIPH_TO_MEMORY_MASK; + break; + + default: + break; + } + + return (uint16_t)direction_set; +} + +static inline uint16_t hal_ll_dma_get_reg_value_dst_inc( bool set_inc ) { + return (uint16_t)((set_inc) ? (HAL_LL_DMA_PINC_MASK) : (0)); +} + +static inline uint16_t hal_ll_dma_get_reg_value_src_inc( bool set_inc ) { + return (uint16_t)((set_inc) ? (HAL_LL_DMA_MINC_MASK) : (0)); +} + +static inline uint16_t hal_ll_dma_get_reg_value_source_size( hal_ll_dma_data_align_t align ) { + volatile uint16_t align_set = (uint16_t)HAL_LL_DMA_DATA_ALIGN_BYTES_1; + + switch ( align ) + { + case HAL_LL_DMA_DATA_ALIGN_BYTES_1: + align_set = HAL_LL_DMA_MSIZE_BYTE_MASK; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_2: + align_set = HAL_LL_DMA_MSIZE_HALFWORD_MASK; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_4: + align_set = HAL_LL_DMA_MSIZE_WORD_MASK; + break; + + default: + break; + } + + return (uint16_t)align_set; +} + +static inline uint16_t hal_ll_dma_get_reg_value_destination_size( hal_ll_dma_data_align_t align ) { + volatile uint16_t align_set = (uint16_t)HAL_LL_DMA_DATA_ALIGN_BYTES_1; + + switch ( align ) + { + case HAL_LL_DMA_DATA_ALIGN_BYTES_1: + align_set = HAL_LL_DMA_CCR_PSIZE_BYTE_MASK; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_2: + align_set = HAL_LL_DMA_CCR_PSIZE_HALFWORD_MASK; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_4: + align_set = HAL_LL_DMA_CCR_PSIZE_WORD_MASK; + break; + + default: + break; + } + + return (uint16_t)align_set; +} + +static inline uint16_t hal_ll_dma_get_reg_value_mode( hal_ll_dma_mode_t mode ) { + return (uint16_t)((mode) ? (HAL_LL_DMA_CCR_CIRC_MASK) : (0)); +} + +static inline uint32_t hal_ll_dma_get_reg_value_priority( hal_ll_dma_priority_t priority ) { + volatile uint32_t priority_set = (uint32_t)HAL_LL_DMA_PRIORITY_LOW; + + switch ( priority ) + { + case HAL_LL_DMA_PRIORITY_LOW: + priority_set = HAL_LL_DMA_CCR_PRIORITY_LOW_MASK; + break; + case HAL_LL_DMA_PRIORITY_MEDIUM: + priority_set = HAL_LL_DMA_CCR_PRIORITY_MEDIUM_MASK; + break; + case HAL_LL_DMA_PRIORITY_HIGH: + priority_set = HAL_LL_DMA_CCR_PRIORITY_HIGH_MASK; + break; + case HAL_LL_DMA_PRIORITY_VERY_HIGH: + priority_set = HAL_LL_DMA_CCR_PRIORITY_VERY_HIGH_MASK; + break; + + default: + break; + } + + return (uint32_t)priority_set; +} + +// ------------------------------------------------------------------------- END + + + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_87/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_87/CMakeLists.cmake new file mode 100644 index 000000000..2da5f7aa2 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_87/CMakeLists.cmake @@ -0,0 +1,8 @@ +if(${MCU_NAME} MATCHES "^STM32G484CE$|^STM32G484ME$|^STM32G484PE$|^STM32G484RE$|^STM32G484QE$|^STM32G484VE$") + set(dma_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_dma.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_87") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_87") + list(APPEND hal_ll_def_list "STM32G4xx") + list(APPEND hal_ll_def_list "STM32G48xx") + list(APPEND hal_ll_def_list "STM32G484xx") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_87/hal_ll_dma.c b/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_87/hal_ll_dma.c new file mode 100644 index 000000000..2ed93bbdb --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_87/hal_ll_dma.c @@ -0,0 +1,661 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_dma.c + * @brief DMA HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_rcc.h" +#include "hal_ll_dma.h" +#include "hal_ll_gpio.h" + +// ------------------------------------------------------------- PRIVATE MACROS + + +/*!< @brief DMA interrupt definitions. */ +#define HAL_LL_DMA_IT_FT ((uint32_t)(1U << 1)) +#define HAL_LL_DMA_IT_HT ((uint32_t)(1U << 2)) +#define HAL_LL_DMA_IT_ET ((uint32_t)(1U << 3)) +#define HAL_LL_DMA_IT_CLEAR_MASK (0x0fUL) + +/*!< @brief DMA SCR register masks. */ + + + +#define HAL_LL_DMA_CCR_PRIORITY_VERY_HIGH_MASK (0x00003000) +#define HAL_LL_DMA_CCR_PRIORITY_HIGH_MASK (0x00002000) +#define HAL_LL_DMA_CCR_PRIORITY_MEDIUM_MASK (0x00001000) +#define HAL_LL_DMA_CCR_PRIORITY_LOW_MASK (0x00000000) +#define HAL_LL_DMA_CCR_CIRC_MASK (0x00000020) +#define HAL_LL_DMA_CCR_PSIZE_BYTE_MASK (0x00000000) +#define HAL_LL_DMA_CCR_PSIZE_HALFWORD_MASK (0x00000100) +#define HAL_LL_DMA_CCR_PSIZE_WORD_MASK (0x00000200) +#define HAL_LL_DMA_MSIZE_BYTE_MASK (0x00000000) +#define HAL_LL_DMA_MSIZE_HALFWORD_MASK (0x00000400) +#define HAL_LL_DMA_MSIZE_WORD_MASK (0x00000800) +#define HAL_LL_DMA_MINC_MASK (0x00000080) +#define HAL_LL_DMA_PINC_MASK (0x00000040) + +#define HAL_LL_DMA_DIRECTION_MEMORY_TO_MEMORY_MASK (0x4000) +#define HAL_LL_DMA_DIRECTION_MEMORY_TO_PERIPH_MASK (0x10) +#define HAL_LL_DMA_DIRECTION_PERIPH_TO_MEMORY_MASK (0x0) + +#define HAL_LL_DMA_CCR_PSIZE_MASK (0x00000300) +#define HAL_LL_DMA_CCR_MSIZE_MASK (0x00000C00) +#define HAL_LL_DMA_CCR_PRIO_MASK (0x00003000) +#define HAL_LL_DMA_CCR_EN_BIT (0) +#define HAL_LL_DMA_CCR_TEIE_BIT (3) +#define HAL_LL_DMA_CCR_HTIE_BIT (2) +#define HAL_LL_DMA_CCR_TCIE_BIT (1) +#define HAL_LL_DMA_CCR_DIR_BIT (4) +#define HAL_LL_DMA_CCR_CIRC_BIT (5) +#define HAL_LL_DMA_CCR_PINC_BIT (6) +#define HAL_LL_DMA_CCR_MINC_BIT (7) +#define HAL_LL_DMA_CCR_M2M_BIT (14) + + + +#define DMA1_BASE (0x40020000UL) +#define DMA2_BASE (0x40020400UL) + +#define HAL_LL_DMA1_CLOCK_BIT (0) +#define HAL_LL_DMA1_CLOCK_BASE ((uint32_t)_RCC_AHB1ENR) +#define HAL_LL_DMA1_STREAM_BASE (DMA1_BASE + CCR_BASE_OFFSET) +#define HAL_LL_DMA2_CLOCK_BIT (1) +#define HAL_LL_DMA2_CLOCK_BASE ((uint32_t)_RCC_AHB1ENR) +#define HAL_LL_DMA2_STREAM_BASE (DMA2_BASE + CCR_BASE_OFFSET) + +#define CCR_BASE_OFFSET (0x8U) +#define STREAM_BASE_OFFSET (0x14U) +#define IFCR_BASE_OFFSET (0x4U) +#define HAL_LL_PWRCLK_BIT (28) + +/*diff bits/offsets:*/ +#define HAL_LL_PWRCLK_BASE (_RCC_APB1ENR1) + +#define DMAMUX1_BASE (0x40020800UL) +#define DMAMUX1_OFFSET (0x04U) +#define HAL_LL_DMAMUX1_CLOCK_BIT (2) + + + + + +/*!< @brief Clock enable macros. */ +#ifdef HAL_LL_PWRCLK_BASE +#define _HAL_LL_ENABLE_CLOCK_PWR_ ((HAL_LL_PWRCLK_BASE) ? (*HAL_LL_PWRCLK_BASE |= 1UL << HAL_LL_PWRCLK_BIT) : 0) +#endif + +/*!< @brief DMA module enable macro. */ +#define HAL_LL_DMA_MODULE_ENABLE(_x) (_x->cr |= 1U << HAL_LL_DMA_CCR_EN_BIT) + +/*!< @brief DMA module disable macro. */ +#define HAL_LL_DMA_MODULE_DISABLE(_x) (_x->cr &= ~(1U << HAL_LL_DMA_CCR_EN_BIT)) + +/*!< @brief Default timeout value to wait when checking if module is disabled/enabled. */ +#define DEFAULT_TIMEOUT_VALUE (0xFFFFU) + +// ----------------------------------------------------------- PRIVATE TYPEDEFS + +/*!< @brief DMA HW register structure. */ +typedef struct dma_handle +{ + volatile uint32_t cr; /*!< DMA channel x configuration register (DMA_CCRx) */ + volatile uint32_t ndtr; /*!< DMA channel x number of data to transfer register (DMA_CNDTRx) */ + volatile uint32_t par; /*!< DMA channel x peripheral address register (DMA_CPARx) */ + volatile uint32_t mar; /*!< DMA channel x memory address register (DMA_CMARx) */ + +} dma_handle_t; + + +typedef struct dmamux_registers +{ + volatile uint32_t dmamux_cr; /*!< DMA interrupt status register */ + +} dmamux_registers_t; + +/*!< @brief DMA HW ISR register structure. */ +typedef struct dma_isr_registers +{ + volatile uint32_t isr; /*!< DMA interrupt status register (DMA_ISR) */ + volatile uint32_t ifcr; /*!< DMA interrupt flag clear register (DMA_IFCR) */ + +} dma_isr_registers_t; + +/*!< @brief DMA HW clock settings structure. */ +typedef struct +{ + uint8_t clock_bit; + hal_ll_base_addr_t clock_base; +} dma_clock_t; + +/*!< @brief DMA control settings structure. */ +typedef struct +{ + dma_clock_t clock; + hal_ll_base_addr_t stream_base; +} dma_control_struct_t; + +// ------------------------------------------------------------------ VARIABLES + +static const dma_control_struct_t dma_controller[ DMA_NUM_OF_MODULES ] = +{ + { + { HAL_LL_DMA1_CLOCK_BIT, HAL_LL_DMA1_CLOCK_BASE }, HAL_LL_DMA1_STREAM_BASE + } + ,{ + { HAL_LL_DMA2_CLOCK_BIT, HAL_LL_DMA2_CLOCK_BASE }, HAL_LL_DMA2_STREAM_BASE + } +}; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS + +/** + * @brief Gets current stream address. + * @details Returns stream address based on @ref module value and + * desired @ref stream value. + * @param[in] module DMA module number. + * @param[in] stream DMA stream number. + * @return hal_ll_base_addr_t stream base register address. + */ +static hal_ll_base_addr_t hal_ll_dma_get_stream_address( uint8_t module, uint8_t stream ); + +/** + * @brief Sets current module clock. + * @details If @ref state is @b true, enables DMA module clock. + * If @ref state is @b false, disables DMA module clock. + * @param[in] dma_obj DMA object. + * @param[in] state Desired state. + * - @b true + * - @b false + * @return Nothing. + */ +static void hal_ll_dma_clock_set( hal_ll_dma_t *dma_obj, bool state ); + +/** + * @brief Initializes DMA module. + * @details Initializes DMA module, stream to + * values from @ref config structure. + * @param[in] dma_obj DMA object. + * @param[in] dma DMA HW handle. + * @param[in] config DMA configuration structure. + * @return hal_ll_err_t Returns initialization state, either success or fail. + */ +static hal_ll_err_t hal_ll_dma_init_hw( hal_ll_dma_t *dma_obj, dma_handle_t *dma, hal_ll_dma_config_t config ); + +/** + * @brief Gets DMA module state. + * @details Checks if current DMA module stream has been stopped. + * Waits for defined @ref DEFAULT_TIMEOUT_VALUE number of cycles + * before jumping out of loop and returning @ref HAL_LL_DMA_ERROR. + * @param[in] dma DMA HW handle. + * @return hal_ll_err_t Returns success or fail. + */ +static inline hal_ll_err_t hal_ll_dma_is_module_disabled( dma_handle_t *dma ); + +/** + * @brief Gets DMA channel. + * @details Returns appropriate value to be set in HW register + * for desired @ref channel. + * @param[in] channel DMA channel number. + * @return uint32_t Returns actual HW register value based on @ref channel. + */ +static inline uint32_t hal_ll_dma_get_reg_value_channel( uint8_t channel ); + +/** + * @brief Gets DMA direction. + * @details Returns appropriate value to be set in HW register + * for desired @ref direction. + * @param[in] direction DMA stream direction. + * Refer to @hal_ll_dma_direction_t for possible values. + * @return uint8_t Returns actual HW register value based on @ref direction. + */ +static inline uint16_t hal_ll_dma_get_reg_value_direction( hal_ll_dma_direction_t direction ); + +/** + * @brief Gets DMA peripheral address increment. + * @details Returns appropriate value to be set in HW register + * for desired @ref set_inc. + * @param[in] set_inc DMA channel peripheral address increment. + * Set to @b true in order to increment address. + * Set to @b false in order to keep address the same. + * @return uint16_t Returns actual HW register value based on @ref set_inc. + */ +static inline uint16_t hal_ll_dma_get_reg_value_dst_inc( bool set_inc ); + +/** + * @brief Gets DMA memory address increment. + * @details Returns appropriate value to be set in HW register + * for desired @ref set_inc. + * @param[in] set_inc DMA channel memory address increment. + * Set to @b true in order to increment address. + * Set to @b false in order to keep address the same. + * @return uint16_t Returns actual HW register value based on @ref set_inc. + */ +static inline uint16_t hal_ll_dma_get_reg_value_src_inc( bool set_inc ); + +/** + * @brief Gets DMA memory address alignment. + * @details Returns appropriate value to be set in HW register + * for desired @ref align. + * @param[in] align DMA channel memory address increment. + * Refer to @ref hal_ll_dma_data_align_t for possible values. + * @return uint16_t Returns actual HW register value based on @ref align. + */ +static inline uint16_t hal_ll_dma_get_reg_value_source_size( hal_ll_dma_data_align_t align ); + +/** + * @brief Gets DMA peripheral address alignment. + * @details Returns appropriate value to be set in HW register + * for desired @ref align. + * @param[in] align DMA channel peripheral address increment. + * Refer to @ref hal_ll_dma_data_align_t for possible values. + * @return uint16_t Returns actual HW register value based on @ref align. + */ +static inline uint16_t hal_ll_dma_get_reg_value_destination_size( hal_ll_dma_data_align_t align ); + +/** + * @brief Gets DMA mode value. + * @details Returns appropriate value to be set in HW register + * for desired @ref mode. + * @param[in] mode DMA mode for object channel. + * Refer to @ref hal_ll_dma_mode_t for possible values. + * @return uint16_t Returns actual HW register value based on @ref mode. + */ +static inline uint16_t hal_ll_dma_get_reg_value_mode( hal_ll_dma_mode_t mode ); + +/** + * @brief Gets DMA priority value. + * @details Returns appropriate value to be set in HW register + * for desired @ref priority. + * @param[in] priority DMA priority for object channel. + * Refer to @ref hal_ll_dma_priority_t for possible values. + * @return uint32_t Returns actual HW register value based on @ref priority. + */ +static inline uint32_t hal_ll_dma_get_reg_value_priority( hal_ll_dma_priority_t priority ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS + +hal_ll_err_t hal_ll_dma_init( hal_ll_dma_t *obj ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + + // Enable PWRCLK. + #ifdef HAL_LL_PWRCLK_BASE + _HAL_LL_ENABLE_CLOCK_PWR_; + #endif + + // Enable current stream clock. + hal_ll_dma_clock_set( obj, true ); + + // Initialize current stream. + obj->handle = hal_ll_dma_get_stream_address( obj->module, obj->stream ); + status = hal_ll_dma_init_hw( obj, + (dma_handle_t *)obj->handle, + obj->config ); + + if ( HAL_LL_DMA_SUCCESS != status ) { + obj->handle = 0; // If initialization failed, reset handle. + } + + return status; +} + +hal_ll_err_t hal_ll_dma_deinit( hal_ll_dma_t *obj ) { + // First abort current transfer. + if ( HAL_LL_DMA_SUCCESS != hal_ll_dma_transfer_abort( obj ) ) + return HAL_LL_DMA_ERROR; + // Finally, disable module clock. + hal_ll_dma_clock_set( obj, false ); + + return HAL_LL_DMA_SUCCESS; +} + +hal_ll_err_t hal_ll_dma_set_mode( hal_ll_dma_t *obj, hal_ll_dma_mode_t mode ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + // Get new mode. + hal_ll_dma_config_t cfg = obj->config; + cfg.mode = mode; + // Disable module first. + HAL_LL_DMA_MODULE_DISABLE( ((dma_handle_t *)obj->handle) ); + // Try to set new mode. + status = hal_ll_dma_init_hw( obj, + (dma_handle_t *)obj->handle, + cfg ); + + return status; +} + +hal_ll_err_t hal_ll_dma_set_direction( hal_ll_dma_t *obj, hal_ll_dma_direction_t direction ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + // Get new direction. + hal_ll_dma_config_t cfg = obj->config; + cfg.direction = direction; + // Disable module first. + HAL_LL_DMA_MODULE_DISABLE( ((dma_handle_t *)obj->handle) ); + // Try to set new value. + status = hal_ll_dma_init_hw( obj, + (dma_handle_t *)obj->handle, + cfg ); + + return status; +} + +hal_ll_err_t hal_ll_dma_set_priority( hal_ll_dma_t *obj, hal_ll_dma_priority_t priority ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + // Get new priority. + hal_ll_dma_config_t cfg = obj->config; + cfg.priority = priority; + // Disable module first. + HAL_LL_DMA_MODULE_DISABLE( ((dma_handle_t *)obj->handle) ); + // Try to set new value. + status = hal_ll_dma_init_hw( obj, + (dma_handle_t *)obj->handle, + cfg ); + + return status; +} + +hal_ll_err_t hal_ll_dma_set_parameters( hal_ll_dma_t *obj, uint32_t addr_src, uint32_t addr_dst, size_t transfer_size, hal_ll_dma_source_memory_region_t src_mem_type ) { + dma_handle_t *dma = (dma_handle_t *)obj->handle; + uint8_t ndtr_divisor; + + // This parameter is not relevant on this architecture. + (void)src_mem_type; + + // Configure DMA Stream data length. + switch ( obj->config.data_align_destination ) { + case HAL_LL_DMA_DATA_ALIGN_BYTES_1: + case HAL_LL_DMA_DATA_ALIGN_BYTES_2: + ndtr_divisor = obj->config.data_align_destination; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_4: + ndtr_divisor = 2; + break; + + default: + return HAL_LL_DMA_ERROR; + } + dma->ndtr = transfer_size >> ndtr_divisor; + + // Memory to Peripheral. + if ( HAL_LL_DMA_DIRECTION_MEMORY_TO_PERIPH == obj->config.direction ) { + // Configure DMA stream destination address. + dma->par = addr_dst; + // Configure DMA stream source address. + dma->mar = addr_src; + } else { // Peripheral to Memory. + // Configure DMA stream source address. + dma->par = addr_src; + // Configure DMA stream destination address. + dma->mar = addr_dst; + } + return HAL_LL_DMA_SUCCESS; +} + +hal_ll_err_t hal_ll_dma_transfer_start( hal_ll_dma_t *obj ) { + HAL_LL_DMA_MODULE_ENABLE( ((dma_handle_t *)obj->handle) ); + return HAL_LL_DMA_SUCCESS; +} + +hal_ll_err_t hal_ll_dma_transfer_stop( hal_ll_dma_t *obj ) { + dma_handle_t *dma = (dma_handle_t *)obj->handle; + uint16_t timeout = DEFAULT_TIMEOUT_VALUE; + + if ( HAL_LL_DMA_MODE_CIRCULAR == obj->config.mode ) + return HAL_LL_DMA_ERROR; + + while ( dma->ndtr ) { + if ( 0 == timeout-- ) + return HAL_LL_DMA_ERROR; + } + + HAL_LL_DMA_MODULE_DISABLE( dma ); + + return HAL_LL_DMA_SUCCESS; +} + +hal_ll_err_t hal_ll_dma_transfer_abort( hal_ll_dma_t *obj ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + dma_handle_t *dma = (dma_handle_t *)obj->handle; + + // Calculate DMA base and stream number. + dma_isr_registers_t *regs = (dma_isr_registers_t *)(dma_controller[obj->module].stream_base - CCR_BASE_OFFSET); + + // Disable all the transfer interrupts. + dma->cr &= ~(HAL_LL_DMA_CCR_TCIE_BIT | HAL_LL_DMA_CCR_HTIE_BIT | HAL_LL_DMA_CCR_TEIE_BIT); + + // Disable the stream. + HAL_LL_DMA_MODULE_DISABLE( dma ); + + // Wait for bit to be cleared. + status = hal_ll_dma_is_module_disabled( dma ); + + // Clear all interrupt flags at correct offset within the register. + if ( HAL_LL_DMA_SUCCESS == status ) + regs->ifcr = HAL_LL_DMA_IT_CLEAR_MASK << ( obj->stream * 4 ); + + return status; +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS + +static hal_ll_base_addr_t hal_ll_dma_get_stream_address( uint8_t module, uint8_t stream ) { + return ((hal_ll_base_addr_t)dma_controller[module].stream_base + (hal_ll_base_addr_t)(STREAM_BASE_OFFSET * (stream))); +} + +static void hal_ll_dma_clock_set( hal_ll_dma_t *obj, bool state ) { + if ( state ) { + set_reg_bit( (uint32_t *)dma_controller[obj->module].clock.clock_base, + dma_controller[obj->module].clock.clock_bit ); + set_reg_bit( (uint32_t *)dma_controller[obj->module].clock.clock_base, HAL_LL_DMAMUX1_CLOCK_BIT); + } else { + clear_reg_bit( (uint32_t *)dma_controller[obj->module].clock.clock_base, + dma_controller[obj->module].clock.clock_bit ); + } +} + +static hal_ll_err_t hal_ll_dma_init_hw( hal_ll_dma_t *obj, dma_handle_t *dma, hal_ll_dma_config_t config ) { + volatile uint32_t tmp = 0UL; + // Check if user entered invalid data aka HAL_LL_DMA_DATA_ALIGN_BYTES_3 + if (HAL_LL_DMA_DATA_ALIGN_BYTES_3 == config.data_align_source || HAL_LL_DMA_DATA_ALIGN_BYTES_3 == config.data_align_destination ) { + return HAL_LL_DMA_ERROR; + } + + // Disable the peripheral first. + HAL_LL_DMA_MODULE_DISABLE(dma); + + // Wait for bit to be cleared. + if ( HAL_LL_DMA_ERROR == hal_ll_dma_is_module_disabled( dma ) ) + return HAL_LL_DMA_ERROR; + + // Get the CR register value. + tmp = dma->cr; + + // Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits. + tmp &= ((uint32_t)~( HAL_LL_DMA_CCR_EN_BIT | HAL_LL_DMA_CCR_TCIE_BIT | HAL_LL_DMA_CCR_HTIE_BIT | \ + HAL_LL_DMA_CCR_TEIE_BIT | HAL_LL_DMA_CCR_DIR_BIT | HAL_LL_DMA_CCR_CIRC_BIT | \ + HAL_LL_DMA_CCR_PINC_BIT | HAL_LL_DMA_CCR_MINC_BIT | HAL_LL_DMA_CCR_M2M_BIT | \ + HAL_LL_DMA_CCR_PSIZE_MASK | HAL_LL_DMA_CCR_MSIZE_MASK | HAL_LL_DMA_CCR_PRIO_MASK )); + + // BEGIN Prepare the DMA stream configuration. + // Set desired direction value. + tmp |= hal_ll_dma_get_reg_value_direction(config.direction); + // Set desired memory increment settings. + tmp |= hal_ll_dma_get_reg_value_src_inc(config.src_inc); + tmp |= hal_ll_dma_get_reg_value_dst_inc(config.dst_inc); + // Set desired data size settings. + tmp |= hal_ll_dma_get_reg_value_source_size(config.data_align_source); + tmp |= hal_ll_dma_get_reg_value_destination_size(config.data_align_destination); + // Set desired mode. + tmp |= hal_ll_dma_get_reg_value_mode(config.mode); + // Finally, set desired priority. + tmp |= hal_ll_dma_get_reg_value_priority(config.priority); + + // And then write to DMA stream CR register. + dma->cr = tmp; + + if (obj->module == 0 ) { + dmamux_registers_t * dmamux = (dmamux_registers_t*)( DMAMUX1_BASE + ( obj->stream * DMAMUX1_OFFSET ) ); + dmamux->dmamux_cr |= obj->channel; + } else { + dmamux_registers_t * dmamux = (dmamux_registers_t*)( DMAMUX1_BASE + ( DMA_NUM_OF_STREAMS * DMAMUX1_OFFSET ) + ( obj->stream * DMAMUX1_OFFSET ) ); + dmamux->dmamux_cr |= obj->channel; + } + + return HAL_LL_DMA_SUCCESS; +} + +static inline hal_ll_err_t hal_ll_dma_is_module_disabled( dma_handle_t *dma ) { + uint16_t timeout = DEFAULT_TIMEOUT_VALUE; + + while ( (dma->cr & (1U << HAL_LL_DMA_CCR_EN_BIT)) != 0 ) { + if ( 0 == timeout-- ) + return HAL_LL_DMA_ERROR; + } + + return HAL_LL_DMA_SUCCESS; +} + +static inline uint16_t hal_ll_dma_get_reg_value_direction( hal_ll_dma_direction_t direction ) { + volatile uint16_t direction_set = (uint8_t)HAL_LL_DMA_DIRECTION_MEMORY_TO_MEMORY; + + switch ( direction ) + { + case HAL_LL_DMA_DIRECTION_MEMORY_TO_MEMORY: + direction_set = HAL_LL_DMA_DIRECTION_MEMORY_TO_MEMORY_MASK; + break; + case HAL_LL_DMA_DIRECTION_MEMORY_TO_PERIPH: + direction_set = HAL_LL_DMA_DIRECTION_MEMORY_TO_PERIPH_MASK; + break; + case HAL_LL_DMA_DIRECTION_PERIPH_TO_MEMORY: + direction_set = HAL_LL_DMA_DIRECTION_PERIPH_TO_MEMORY_MASK; + break; + + default: + break; + } + + return (uint16_t)direction_set; +} + +static inline uint16_t hal_ll_dma_get_reg_value_dst_inc( bool set_inc ) { + return (uint16_t)((set_inc) ? (HAL_LL_DMA_PINC_MASK) : (0)); +} + +static inline uint16_t hal_ll_dma_get_reg_value_src_inc( bool set_inc ) { + return (uint16_t)((set_inc) ? (HAL_LL_DMA_MINC_MASK) : (0)); +} + +static inline uint16_t hal_ll_dma_get_reg_value_source_size( hal_ll_dma_data_align_t align ) { + volatile uint16_t align_set = (uint16_t)HAL_LL_DMA_DATA_ALIGN_BYTES_1; + + switch ( align ) + { + case HAL_LL_DMA_DATA_ALIGN_BYTES_1: + align_set = HAL_LL_DMA_MSIZE_BYTE_MASK; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_2: + align_set = HAL_LL_DMA_MSIZE_HALFWORD_MASK; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_4: + align_set = HAL_LL_DMA_MSIZE_WORD_MASK; + break; + + default: + break; + } + + return (uint16_t)align_set; +} + +static inline uint16_t hal_ll_dma_get_reg_value_destination_size( hal_ll_dma_data_align_t align ) { + volatile uint16_t align_set = (uint16_t)HAL_LL_DMA_DATA_ALIGN_BYTES_1; + + switch ( align ) + { + case HAL_LL_DMA_DATA_ALIGN_BYTES_1: + align_set = HAL_LL_DMA_CCR_PSIZE_BYTE_MASK; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_2: + align_set = HAL_LL_DMA_CCR_PSIZE_HALFWORD_MASK; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_4: + align_set = HAL_LL_DMA_CCR_PSIZE_WORD_MASK; + break; + + default: + break; + } + + return (uint16_t)align_set; +} + +static inline uint16_t hal_ll_dma_get_reg_value_mode( hal_ll_dma_mode_t mode ) { + return (uint16_t)((mode) ? (HAL_LL_DMA_CCR_CIRC_MASK) : (0)); +} + +static inline uint32_t hal_ll_dma_get_reg_value_priority( hal_ll_dma_priority_t priority ) { + volatile uint32_t priority_set = (uint32_t)HAL_LL_DMA_PRIORITY_LOW; + + switch ( priority ) + { + case HAL_LL_DMA_PRIORITY_LOW: + priority_set = HAL_LL_DMA_CCR_PRIORITY_LOW_MASK; + break; + case HAL_LL_DMA_PRIORITY_MEDIUM: + priority_set = HAL_LL_DMA_CCR_PRIORITY_MEDIUM_MASK; + break; + case HAL_LL_DMA_PRIORITY_HIGH: + priority_set = HAL_LL_DMA_CCR_PRIORITY_HIGH_MASK; + break; + case HAL_LL_DMA_PRIORITY_VERY_HIGH: + priority_set = HAL_LL_DMA_CCR_PRIORITY_VERY_HIGH_MASK; + break; + + default: + break; + } + + return (uint32_t)priority_set; +} + +// ------------------------------------------------------------------------- END + + + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_88/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_88/CMakeLists.cmake new file mode 100644 index 000000000..7482e9c85 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_88/CMakeLists.cmake @@ -0,0 +1,8 @@ +if(${MCU_NAME} MATCHES "^STM32G491CC$|^STM32G491KC$|^STM32G491RC$|^STM32G491VC$|^STM32G491MC$|^STM32G491CE$|^STM32G491KE$|^STM32G491RE$|^STM32G491VE$|^STM32G491ME$") + set(dma_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_dma.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_88") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_88") + list(APPEND hal_ll_def_list "STM32G4xx") + list(APPEND hal_ll_def_list "STM32G49xx") + list(APPEND hal_ll_def_list "STM32G491xx") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_88/hal_ll_dma.c b/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_88/hal_ll_dma.c new file mode 100644 index 000000000..2ed93bbdb --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_88/hal_ll_dma.c @@ -0,0 +1,661 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_dma.c + * @brief DMA HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_rcc.h" +#include "hal_ll_dma.h" +#include "hal_ll_gpio.h" + +// ------------------------------------------------------------- PRIVATE MACROS + + +/*!< @brief DMA interrupt definitions. */ +#define HAL_LL_DMA_IT_FT ((uint32_t)(1U << 1)) +#define HAL_LL_DMA_IT_HT ((uint32_t)(1U << 2)) +#define HAL_LL_DMA_IT_ET ((uint32_t)(1U << 3)) +#define HAL_LL_DMA_IT_CLEAR_MASK (0x0fUL) + +/*!< @brief DMA SCR register masks. */ + + + +#define HAL_LL_DMA_CCR_PRIORITY_VERY_HIGH_MASK (0x00003000) +#define HAL_LL_DMA_CCR_PRIORITY_HIGH_MASK (0x00002000) +#define HAL_LL_DMA_CCR_PRIORITY_MEDIUM_MASK (0x00001000) +#define HAL_LL_DMA_CCR_PRIORITY_LOW_MASK (0x00000000) +#define HAL_LL_DMA_CCR_CIRC_MASK (0x00000020) +#define HAL_LL_DMA_CCR_PSIZE_BYTE_MASK (0x00000000) +#define HAL_LL_DMA_CCR_PSIZE_HALFWORD_MASK (0x00000100) +#define HAL_LL_DMA_CCR_PSIZE_WORD_MASK (0x00000200) +#define HAL_LL_DMA_MSIZE_BYTE_MASK (0x00000000) +#define HAL_LL_DMA_MSIZE_HALFWORD_MASK (0x00000400) +#define HAL_LL_DMA_MSIZE_WORD_MASK (0x00000800) +#define HAL_LL_DMA_MINC_MASK (0x00000080) +#define HAL_LL_DMA_PINC_MASK (0x00000040) + +#define HAL_LL_DMA_DIRECTION_MEMORY_TO_MEMORY_MASK (0x4000) +#define HAL_LL_DMA_DIRECTION_MEMORY_TO_PERIPH_MASK (0x10) +#define HAL_LL_DMA_DIRECTION_PERIPH_TO_MEMORY_MASK (0x0) + +#define HAL_LL_DMA_CCR_PSIZE_MASK (0x00000300) +#define HAL_LL_DMA_CCR_MSIZE_MASK (0x00000C00) +#define HAL_LL_DMA_CCR_PRIO_MASK (0x00003000) +#define HAL_LL_DMA_CCR_EN_BIT (0) +#define HAL_LL_DMA_CCR_TEIE_BIT (3) +#define HAL_LL_DMA_CCR_HTIE_BIT (2) +#define HAL_LL_DMA_CCR_TCIE_BIT (1) +#define HAL_LL_DMA_CCR_DIR_BIT (4) +#define HAL_LL_DMA_CCR_CIRC_BIT (5) +#define HAL_LL_DMA_CCR_PINC_BIT (6) +#define HAL_LL_DMA_CCR_MINC_BIT (7) +#define HAL_LL_DMA_CCR_M2M_BIT (14) + + + +#define DMA1_BASE (0x40020000UL) +#define DMA2_BASE (0x40020400UL) + +#define HAL_LL_DMA1_CLOCK_BIT (0) +#define HAL_LL_DMA1_CLOCK_BASE ((uint32_t)_RCC_AHB1ENR) +#define HAL_LL_DMA1_STREAM_BASE (DMA1_BASE + CCR_BASE_OFFSET) +#define HAL_LL_DMA2_CLOCK_BIT (1) +#define HAL_LL_DMA2_CLOCK_BASE ((uint32_t)_RCC_AHB1ENR) +#define HAL_LL_DMA2_STREAM_BASE (DMA2_BASE + CCR_BASE_OFFSET) + +#define CCR_BASE_OFFSET (0x8U) +#define STREAM_BASE_OFFSET (0x14U) +#define IFCR_BASE_OFFSET (0x4U) +#define HAL_LL_PWRCLK_BIT (28) + +/*diff bits/offsets:*/ +#define HAL_LL_PWRCLK_BASE (_RCC_APB1ENR1) + +#define DMAMUX1_BASE (0x40020800UL) +#define DMAMUX1_OFFSET (0x04U) +#define HAL_LL_DMAMUX1_CLOCK_BIT (2) + + + + + +/*!< @brief Clock enable macros. */ +#ifdef HAL_LL_PWRCLK_BASE +#define _HAL_LL_ENABLE_CLOCK_PWR_ ((HAL_LL_PWRCLK_BASE) ? (*HAL_LL_PWRCLK_BASE |= 1UL << HAL_LL_PWRCLK_BIT) : 0) +#endif + +/*!< @brief DMA module enable macro. */ +#define HAL_LL_DMA_MODULE_ENABLE(_x) (_x->cr |= 1U << HAL_LL_DMA_CCR_EN_BIT) + +/*!< @brief DMA module disable macro. */ +#define HAL_LL_DMA_MODULE_DISABLE(_x) (_x->cr &= ~(1U << HAL_LL_DMA_CCR_EN_BIT)) + +/*!< @brief Default timeout value to wait when checking if module is disabled/enabled. */ +#define DEFAULT_TIMEOUT_VALUE (0xFFFFU) + +// ----------------------------------------------------------- PRIVATE TYPEDEFS + +/*!< @brief DMA HW register structure. */ +typedef struct dma_handle +{ + volatile uint32_t cr; /*!< DMA channel x configuration register (DMA_CCRx) */ + volatile uint32_t ndtr; /*!< DMA channel x number of data to transfer register (DMA_CNDTRx) */ + volatile uint32_t par; /*!< DMA channel x peripheral address register (DMA_CPARx) */ + volatile uint32_t mar; /*!< DMA channel x memory address register (DMA_CMARx) */ + +} dma_handle_t; + + +typedef struct dmamux_registers +{ + volatile uint32_t dmamux_cr; /*!< DMA interrupt status register */ + +} dmamux_registers_t; + +/*!< @brief DMA HW ISR register structure. */ +typedef struct dma_isr_registers +{ + volatile uint32_t isr; /*!< DMA interrupt status register (DMA_ISR) */ + volatile uint32_t ifcr; /*!< DMA interrupt flag clear register (DMA_IFCR) */ + +} dma_isr_registers_t; + +/*!< @brief DMA HW clock settings structure. */ +typedef struct +{ + uint8_t clock_bit; + hal_ll_base_addr_t clock_base; +} dma_clock_t; + +/*!< @brief DMA control settings structure. */ +typedef struct +{ + dma_clock_t clock; + hal_ll_base_addr_t stream_base; +} dma_control_struct_t; + +// ------------------------------------------------------------------ VARIABLES + +static const dma_control_struct_t dma_controller[ DMA_NUM_OF_MODULES ] = +{ + { + { HAL_LL_DMA1_CLOCK_BIT, HAL_LL_DMA1_CLOCK_BASE }, HAL_LL_DMA1_STREAM_BASE + } + ,{ + { HAL_LL_DMA2_CLOCK_BIT, HAL_LL_DMA2_CLOCK_BASE }, HAL_LL_DMA2_STREAM_BASE + } +}; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS + +/** + * @brief Gets current stream address. + * @details Returns stream address based on @ref module value and + * desired @ref stream value. + * @param[in] module DMA module number. + * @param[in] stream DMA stream number. + * @return hal_ll_base_addr_t stream base register address. + */ +static hal_ll_base_addr_t hal_ll_dma_get_stream_address( uint8_t module, uint8_t stream ); + +/** + * @brief Sets current module clock. + * @details If @ref state is @b true, enables DMA module clock. + * If @ref state is @b false, disables DMA module clock. + * @param[in] dma_obj DMA object. + * @param[in] state Desired state. + * - @b true + * - @b false + * @return Nothing. + */ +static void hal_ll_dma_clock_set( hal_ll_dma_t *dma_obj, bool state ); + +/** + * @brief Initializes DMA module. + * @details Initializes DMA module, stream to + * values from @ref config structure. + * @param[in] dma_obj DMA object. + * @param[in] dma DMA HW handle. + * @param[in] config DMA configuration structure. + * @return hal_ll_err_t Returns initialization state, either success or fail. + */ +static hal_ll_err_t hal_ll_dma_init_hw( hal_ll_dma_t *dma_obj, dma_handle_t *dma, hal_ll_dma_config_t config ); + +/** + * @brief Gets DMA module state. + * @details Checks if current DMA module stream has been stopped. + * Waits for defined @ref DEFAULT_TIMEOUT_VALUE number of cycles + * before jumping out of loop and returning @ref HAL_LL_DMA_ERROR. + * @param[in] dma DMA HW handle. + * @return hal_ll_err_t Returns success or fail. + */ +static inline hal_ll_err_t hal_ll_dma_is_module_disabled( dma_handle_t *dma ); + +/** + * @brief Gets DMA channel. + * @details Returns appropriate value to be set in HW register + * for desired @ref channel. + * @param[in] channel DMA channel number. + * @return uint32_t Returns actual HW register value based on @ref channel. + */ +static inline uint32_t hal_ll_dma_get_reg_value_channel( uint8_t channel ); + +/** + * @brief Gets DMA direction. + * @details Returns appropriate value to be set in HW register + * for desired @ref direction. + * @param[in] direction DMA stream direction. + * Refer to @hal_ll_dma_direction_t for possible values. + * @return uint8_t Returns actual HW register value based on @ref direction. + */ +static inline uint16_t hal_ll_dma_get_reg_value_direction( hal_ll_dma_direction_t direction ); + +/** + * @brief Gets DMA peripheral address increment. + * @details Returns appropriate value to be set in HW register + * for desired @ref set_inc. + * @param[in] set_inc DMA channel peripheral address increment. + * Set to @b true in order to increment address. + * Set to @b false in order to keep address the same. + * @return uint16_t Returns actual HW register value based on @ref set_inc. + */ +static inline uint16_t hal_ll_dma_get_reg_value_dst_inc( bool set_inc ); + +/** + * @brief Gets DMA memory address increment. + * @details Returns appropriate value to be set in HW register + * for desired @ref set_inc. + * @param[in] set_inc DMA channel memory address increment. + * Set to @b true in order to increment address. + * Set to @b false in order to keep address the same. + * @return uint16_t Returns actual HW register value based on @ref set_inc. + */ +static inline uint16_t hal_ll_dma_get_reg_value_src_inc( bool set_inc ); + +/** + * @brief Gets DMA memory address alignment. + * @details Returns appropriate value to be set in HW register + * for desired @ref align. + * @param[in] align DMA channel memory address increment. + * Refer to @ref hal_ll_dma_data_align_t for possible values. + * @return uint16_t Returns actual HW register value based on @ref align. + */ +static inline uint16_t hal_ll_dma_get_reg_value_source_size( hal_ll_dma_data_align_t align ); + +/** + * @brief Gets DMA peripheral address alignment. + * @details Returns appropriate value to be set in HW register + * for desired @ref align. + * @param[in] align DMA channel peripheral address increment. + * Refer to @ref hal_ll_dma_data_align_t for possible values. + * @return uint16_t Returns actual HW register value based on @ref align. + */ +static inline uint16_t hal_ll_dma_get_reg_value_destination_size( hal_ll_dma_data_align_t align ); + +/** + * @brief Gets DMA mode value. + * @details Returns appropriate value to be set in HW register + * for desired @ref mode. + * @param[in] mode DMA mode for object channel. + * Refer to @ref hal_ll_dma_mode_t for possible values. + * @return uint16_t Returns actual HW register value based on @ref mode. + */ +static inline uint16_t hal_ll_dma_get_reg_value_mode( hal_ll_dma_mode_t mode ); + +/** + * @brief Gets DMA priority value. + * @details Returns appropriate value to be set in HW register + * for desired @ref priority. + * @param[in] priority DMA priority for object channel. + * Refer to @ref hal_ll_dma_priority_t for possible values. + * @return uint32_t Returns actual HW register value based on @ref priority. + */ +static inline uint32_t hal_ll_dma_get_reg_value_priority( hal_ll_dma_priority_t priority ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS + +hal_ll_err_t hal_ll_dma_init( hal_ll_dma_t *obj ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + + // Enable PWRCLK. + #ifdef HAL_LL_PWRCLK_BASE + _HAL_LL_ENABLE_CLOCK_PWR_; + #endif + + // Enable current stream clock. + hal_ll_dma_clock_set( obj, true ); + + // Initialize current stream. + obj->handle = hal_ll_dma_get_stream_address( obj->module, obj->stream ); + status = hal_ll_dma_init_hw( obj, + (dma_handle_t *)obj->handle, + obj->config ); + + if ( HAL_LL_DMA_SUCCESS != status ) { + obj->handle = 0; // If initialization failed, reset handle. + } + + return status; +} + +hal_ll_err_t hal_ll_dma_deinit( hal_ll_dma_t *obj ) { + // First abort current transfer. + if ( HAL_LL_DMA_SUCCESS != hal_ll_dma_transfer_abort( obj ) ) + return HAL_LL_DMA_ERROR; + // Finally, disable module clock. + hal_ll_dma_clock_set( obj, false ); + + return HAL_LL_DMA_SUCCESS; +} + +hal_ll_err_t hal_ll_dma_set_mode( hal_ll_dma_t *obj, hal_ll_dma_mode_t mode ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + // Get new mode. + hal_ll_dma_config_t cfg = obj->config; + cfg.mode = mode; + // Disable module first. + HAL_LL_DMA_MODULE_DISABLE( ((dma_handle_t *)obj->handle) ); + // Try to set new mode. + status = hal_ll_dma_init_hw( obj, + (dma_handle_t *)obj->handle, + cfg ); + + return status; +} + +hal_ll_err_t hal_ll_dma_set_direction( hal_ll_dma_t *obj, hal_ll_dma_direction_t direction ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + // Get new direction. + hal_ll_dma_config_t cfg = obj->config; + cfg.direction = direction; + // Disable module first. + HAL_LL_DMA_MODULE_DISABLE( ((dma_handle_t *)obj->handle) ); + // Try to set new value. + status = hal_ll_dma_init_hw( obj, + (dma_handle_t *)obj->handle, + cfg ); + + return status; +} + +hal_ll_err_t hal_ll_dma_set_priority( hal_ll_dma_t *obj, hal_ll_dma_priority_t priority ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + // Get new priority. + hal_ll_dma_config_t cfg = obj->config; + cfg.priority = priority; + // Disable module first. + HAL_LL_DMA_MODULE_DISABLE( ((dma_handle_t *)obj->handle) ); + // Try to set new value. + status = hal_ll_dma_init_hw( obj, + (dma_handle_t *)obj->handle, + cfg ); + + return status; +} + +hal_ll_err_t hal_ll_dma_set_parameters( hal_ll_dma_t *obj, uint32_t addr_src, uint32_t addr_dst, size_t transfer_size, hal_ll_dma_source_memory_region_t src_mem_type ) { + dma_handle_t *dma = (dma_handle_t *)obj->handle; + uint8_t ndtr_divisor; + + // This parameter is not relevant on this architecture. + (void)src_mem_type; + + // Configure DMA Stream data length. + switch ( obj->config.data_align_destination ) { + case HAL_LL_DMA_DATA_ALIGN_BYTES_1: + case HAL_LL_DMA_DATA_ALIGN_BYTES_2: + ndtr_divisor = obj->config.data_align_destination; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_4: + ndtr_divisor = 2; + break; + + default: + return HAL_LL_DMA_ERROR; + } + dma->ndtr = transfer_size >> ndtr_divisor; + + // Memory to Peripheral. + if ( HAL_LL_DMA_DIRECTION_MEMORY_TO_PERIPH == obj->config.direction ) { + // Configure DMA stream destination address. + dma->par = addr_dst; + // Configure DMA stream source address. + dma->mar = addr_src; + } else { // Peripheral to Memory. + // Configure DMA stream source address. + dma->par = addr_src; + // Configure DMA stream destination address. + dma->mar = addr_dst; + } + return HAL_LL_DMA_SUCCESS; +} + +hal_ll_err_t hal_ll_dma_transfer_start( hal_ll_dma_t *obj ) { + HAL_LL_DMA_MODULE_ENABLE( ((dma_handle_t *)obj->handle) ); + return HAL_LL_DMA_SUCCESS; +} + +hal_ll_err_t hal_ll_dma_transfer_stop( hal_ll_dma_t *obj ) { + dma_handle_t *dma = (dma_handle_t *)obj->handle; + uint16_t timeout = DEFAULT_TIMEOUT_VALUE; + + if ( HAL_LL_DMA_MODE_CIRCULAR == obj->config.mode ) + return HAL_LL_DMA_ERROR; + + while ( dma->ndtr ) { + if ( 0 == timeout-- ) + return HAL_LL_DMA_ERROR; + } + + HAL_LL_DMA_MODULE_DISABLE( dma ); + + return HAL_LL_DMA_SUCCESS; +} + +hal_ll_err_t hal_ll_dma_transfer_abort( hal_ll_dma_t *obj ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + dma_handle_t *dma = (dma_handle_t *)obj->handle; + + // Calculate DMA base and stream number. + dma_isr_registers_t *regs = (dma_isr_registers_t *)(dma_controller[obj->module].stream_base - CCR_BASE_OFFSET); + + // Disable all the transfer interrupts. + dma->cr &= ~(HAL_LL_DMA_CCR_TCIE_BIT | HAL_LL_DMA_CCR_HTIE_BIT | HAL_LL_DMA_CCR_TEIE_BIT); + + // Disable the stream. + HAL_LL_DMA_MODULE_DISABLE( dma ); + + // Wait for bit to be cleared. + status = hal_ll_dma_is_module_disabled( dma ); + + // Clear all interrupt flags at correct offset within the register. + if ( HAL_LL_DMA_SUCCESS == status ) + regs->ifcr = HAL_LL_DMA_IT_CLEAR_MASK << ( obj->stream * 4 ); + + return status; +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS + +static hal_ll_base_addr_t hal_ll_dma_get_stream_address( uint8_t module, uint8_t stream ) { + return ((hal_ll_base_addr_t)dma_controller[module].stream_base + (hal_ll_base_addr_t)(STREAM_BASE_OFFSET * (stream))); +} + +static void hal_ll_dma_clock_set( hal_ll_dma_t *obj, bool state ) { + if ( state ) { + set_reg_bit( (uint32_t *)dma_controller[obj->module].clock.clock_base, + dma_controller[obj->module].clock.clock_bit ); + set_reg_bit( (uint32_t *)dma_controller[obj->module].clock.clock_base, HAL_LL_DMAMUX1_CLOCK_BIT); + } else { + clear_reg_bit( (uint32_t *)dma_controller[obj->module].clock.clock_base, + dma_controller[obj->module].clock.clock_bit ); + } +} + +static hal_ll_err_t hal_ll_dma_init_hw( hal_ll_dma_t *obj, dma_handle_t *dma, hal_ll_dma_config_t config ) { + volatile uint32_t tmp = 0UL; + // Check if user entered invalid data aka HAL_LL_DMA_DATA_ALIGN_BYTES_3 + if (HAL_LL_DMA_DATA_ALIGN_BYTES_3 == config.data_align_source || HAL_LL_DMA_DATA_ALIGN_BYTES_3 == config.data_align_destination ) { + return HAL_LL_DMA_ERROR; + } + + // Disable the peripheral first. + HAL_LL_DMA_MODULE_DISABLE(dma); + + // Wait for bit to be cleared. + if ( HAL_LL_DMA_ERROR == hal_ll_dma_is_module_disabled( dma ) ) + return HAL_LL_DMA_ERROR; + + // Get the CR register value. + tmp = dma->cr; + + // Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits. + tmp &= ((uint32_t)~( HAL_LL_DMA_CCR_EN_BIT | HAL_LL_DMA_CCR_TCIE_BIT | HAL_LL_DMA_CCR_HTIE_BIT | \ + HAL_LL_DMA_CCR_TEIE_BIT | HAL_LL_DMA_CCR_DIR_BIT | HAL_LL_DMA_CCR_CIRC_BIT | \ + HAL_LL_DMA_CCR_PINC_BIT | HAL_LL_DMA_CCR_MINC_BIT | HAL_LL_DMA_CCR_M2M_BIT | \ + HAL_LL_DMA_CCR_PSIZE_MASK | HAL_LL_DMA_CCR_MSIZE_MASK | HAL_LL_DMA_CCR_PRIO_MASK )); + + // BEGIN Prepare the DMA stream configuration. + // Set desired direction value. + tmp |= hal_ll_dma_get_reg_value_direction(config.direction); + // Set desired memory increment settings. + tmp |= hal_ll_dma_get_reg_value_src_inc(config.src_inc); + tmp |= hal_ll_dma_get_reg_value_dst_inc(config.dst_inc); + // Set desired data size settings. + tmp |= hal_ll_dma_get_reg_value_source_size(config.data_align_source); + tmp |= hal_ll_dma_get_reg_value_destination_size(config.data_align_destination); + // Set desired mode. + tmp |= hal_ll_dma_get_reg_value_mode(config.mode); + // Finally, set desired priority. + tmp |= hal_ll_dma_get_reg_value_priority(config.priority); + + // And then write to DMA stream CR register. + dma->cr = tmp; + + if (obj->module == 0 ) { + dmamux_registers_t * dmamux = (dmamux_registers_t*)( DMAMUX1_BASE + ( obj->stream * DMAMUX1_OFFSET ) ); + dmamux->dmamux_cr |= obj->channel; + } else { + dmamux_registers_t * dmamux = (dmamux_registers_t*)( DMAMUX1_BASE + ( DMA_NUM_OF_STREAMS * DMAMUX1_OFFSET ) + ( obj->stream * DMAMUX1_OFFSET ) ); + dmamux->dmamux_cr |= obj->channel; + } + + return HAL_LL_DMA_SUCCESS; +} + +static inline hal_ll_err_t hal_ll_dma_is_module_disabled( dma_handle_t *dma ) { + uint16_t timeout = DEFAULT_TIMEOUT_VALUE; + + while ( (dma->cr & (1U << HAL_LL_DMA_CCR_EN_BIT)) != 0 ) { + if ( 0 == timeout-- ) + return HAL_LL_DMA_ERROR; + } + + return HAL_LL_DMA_SUCCESS; +} + +static inline uint16_t hal_ll_dma_get_reg_value_direction( hal_ll_dma_direction_t direction ) { + volatile uint16_t direction_set = (uint8_t)HAL_LL_DMA_DIRECTION_MEMORY_TO_MEMORY; + + switch ( direction ) + { + case HAL_LL_DMA_DIRECTION_MEMORY_TO_MEMORY: + direction_set = HAL_LL_DMA_DIRECTION_MEMORY_TO_MEMORY_MASK; + break; + case HAL_LL_DMA_DIRECTION_MEMORY_TO_PERIPH: + direction_set = HAL_LL_DMA_DIRECTION_MEMORY_TO_PERIPH_MASK; + break; + case HAL_LL_DMA_DIRECTION_PERIPH_TO_MEMORY: + direction_set = HAL_LL_DMA_DIRECTION_PERIPH_TO_MEMORY_MASK; + break; + + default: + break; + } + + return (uint16_t)direction_set; +} + +static inline uint16_t hal_ll_dma_get_reg_value_dst_inc( bool set_inc ) { + return (uint16_t)((set_inc) ? (HAL_LL_DMA_PINC_MASK) : (0)); +} + +static inline uint16_t hal_ll_dma_get_reg_value_src_inc( bool set_inc ) { + return (uint16_t)((set_inc) ? (HAL_LL_DMA_MINC_MASK) : (0)); +} + +static inline uint16_t hal_ll_dma_get_reg_value_source_size( hal_ll_dma_data_align_t align ) { + volatile uint16_t align_set = (uint16_t)HAL_LL_DMA_DATA_ALIGN_BYTES_1; + + switch ( align ) + { + case HAL_LL_DMA_DATA_ALIGN_BYTES_1: + align_set = HAL_LL_DMA_MSIZE_BYTE_MASK; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_2: + align_set = HAL_LL_DMA_MSIZE_HALFWORD_MASK; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_4: + align_set = HAL_LL_DMA_MSIZE_WORD_MASK; + break; + + default: + break; + } + + return (uint16_t)align_set; +} + +static inline uint16_t hal_ll_dma_get_reg_value_destination_size( hal_ll_dma_data_align_t align ) { + volatile uint16_t align_set = (uint16_t)HAL_LL_DMA_DATA_ALIGN_BYTES_1; + + switch ( align ) + { + case HAL_LL_DMA_DATA_ALIGN_BYTES_1: + align_set = HAL_LL_DMA_CCR_PSIZE_BYTE_MASK; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_2: + align_set = HAL_LL_DMA_CCR_PSIZE_HALFWORD_MASK; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_4: + align_set = HAL_LL_DMA_CCR_PSIZE_WORD_MASK; + break; + + default: + break; + } + + return (uint16_t)align_set; +} + +static inline uint16_t hal_ll_dma_get_reg_value_mode( hal_ll_dma_mode_t mode ) { + return (uint16_t)((mode) ? (HAL_LL_DMA_CCR_CIRC_MASK) : (0)); +} + +static inline uint32_t hal_ll_dma_get_reg_value_priority( hal_ll_dma_priority_t priority ) { + volatile uint32_t priority_set = (uint32_t)HAL_LL_DMA_PRIORITY_LOW; + + switch ( priority ) + { + case HAL_LL_DMA_PRIORITY_LOW: + priority_set = HAL_LL_DMA_CCR_PRIORITY_LOW_MASK; + break; + case HAL_LL_DMA_PRIORITY_MEDIUM: + priority_set = HAL_LL_DMA_CCR_PRIORITY_MEDIUM_MASK; + break; + case HAL_LL_DMA_PRIORITY_HIGH: + priority_set = HAL_LL_DMA_CCR_PRIORITY_HIGH_MASK; + break; + case HAL_LL_DMA_PRIORITY_VERY_HIGH: + priority_set = HAL_LL_DMA_CCR_PRIORITY_VERY_HIGH_MASK; + break; + + default: + break; + } + + return (uint32_t)priority_set; +} + +// ------------------------------------------------------------------------- END + + + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_89/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_89/CMakeLists.cmake new file mode 100644 index 000000000..664456f36 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_89/CMakeLists.cmake @@ -0,0 +1,8 @@ +if(${MCU_NAME} MATCHES "^STM32G4A1CE$|^STM32G4A1KE$|^STM32G4A1ME$|^STM32G4A1RE$|^STM32G4A1VE$") + set(dma_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_dma.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_89") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_89") + list(APPEND hal_ll_def_list "STM32G4xx") + list(APPEND hal_ll_def_list "STM32G4Axx") + list(APPEND hal_ll_def_list "STM32G4A1xx") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_89/hal_ll_dma.c b/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_89/hal_ll_dma.c new file mode 100644 index 000000000..2ed93bbdb --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/dma/implementations/doc_ds_89/hal_ll_dma.c @@ -0,0 +1,661 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_dma.c + * @brief DMA HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_rcc.h" +#include "hal_ll_dma.h" +#include "hal_ll_gpio.h" + +// ------------------------------------------------------------- PRIVATE MACROS + + +/*!< @brief DMA interrupt definitions. */ +#define HAL_LL_DMA_IT_FT ((uint32_t)(1U << 1)) +#define HAL_LL_DMA_IT_HT ((uint32_t)(1U << 2)) +#define HAL_LL_DMA_IT_ET ((uint32_t)(1U << 3)) +#define HAL_LL_DMA_IT_CLEAR_MASK (0x0fUL) + +/*!< @brief DMA SCR register masks. */ + + + +#define HAL_LL_DMA_CCR_PRIORITY_VERY_HIGH_MASK (0x00003000) +#define HAL_LL_DMA_CCR_PRIORITY_HIGH_MASK (0x00002000) +#define HAL_LL_DMA_CCR_PRIORITY_MEDIUM_MASK (0x00001000) +#define HAL_LL_DMA_CCR_PRIORITY_LOW_MASK (0x00000000) +#define HAL_LL_DMA_CCR_CIRC_MASK (0x00000020) +#define HAL_LL_DMA_CCR_PSIZE_BYTE_MASK (0x00000000) +#define HAL_LL_DMA_CCR_PSIZE_HALFWORD_MASK (0x00000100) +#define HAL_LL_DMA_CCR_PSIZE_WORD_MASK (0x00000200) +#define HAL_LL_DMA_MSIZE_BYTE_MASK (0x00000000) +#define HAL_LL_DMA_MSIZE_HALFWORD_MASK (0x00000400) +#define HAL_LL_DMA_MSIZE_WORD_MASK (0x00000800) +#define HAL_LL_DMA_MINC_MASK (0x00000080) +#define HAL_LL_DMA_PINC_MASK (0x00000040) + +#define HAL_LL_DMA_DIRECTION_MEMORY_TO_MEMORY_MASK (0x4000) +#define HAL_LL_DMA_DIRECTION_MEMORY_TO_PERIPH_MASK (0x10) +#define HAL_LL_DMA_DIRECTION_PERIPH_TO_MEMORY_MASK (0x0) + +#define HAL_LL_DMA_CCR_PSIZE_MASK (0x00000300) +#define HAL_LL_DMA_CCR_MSIZE_MASK (0x00000C00) +#define HAL_LL_DMA_CCR_PRIO_MASK (0x00003000) +#define HAL_LL_DMA_CCR_EN_BIT (0) +#define HAL_LL_DMA_CCR_TEIE_BIT (3) +#define HAL_LL_DMA_CCR_HTIE_BIT (2) +#define HAL_LL_DMA_CCR_TCIE_BIT (1) +#define HAL_LL_DMA_CCR_DIR_BIT (4) +#define HAL_LL_DMA_CCR_CIRC_BIT (5) +#define HAL_LL_DMA_CCR_PINC_BIT (6) +#define HAL_LL_DMA_CCR_MINC_BIT (7) +#define HAL_LL_DMA_CCR_M2M_BIT (14) + + + +#define DMA1_BASE (0x40020000UL) +#define DMA2_BASE (0x40020400UL) + +#define HAL_LL_DMA1_CLOCK_BIT (0) +#define HAL_LL_DMA1_CLOCK_BASE ((uint32_t)_RCC_AHB1ENR) +#define HAL_LL_DMA1_STREAM_BASE (DMA1_BASE + CCR_BASE_OFFSET) +#define HAL_LL_DMA2_CLOCK_BIT (1) +#define HAL_LL_DMA2_CLOCK_BASE ((uint32_t)_RCC_AHB1ENR) +#define HAL_LL_DMA2_STREAM_BASE (DMA2_BASE + CCR_BASE_OFFSET) + +#define CCR_BASE_OFFSET (0x8U) +#define STREAM_BASE_OFFSET (0x14U) +#define IFCR_BASE_OFFSET (0x4U) +#define HAL_LL_PWRCLK_BIT (28) + +/*diff bits/offsets:*/ +#define HAL_LL_PWRCLK_BASE (_RCC_APB1ENR1) + +#define DMAMUX1_BASE (0x40020800UL) +#define DMAMUX1_OFFSET (0x04U) +#define HAL_LL_DMAMUX1_CLOCK_BIT (2) + + + + + +/*!< @brief Clock enable macros. */ +#ifdef HAL_LL_PWRCLK_BASE +#define _HAL_LL_ENABLE_CLOCK_PWR_ ((HAL_LL_PWRCLK_BASE) ? (*HAL_LL_PWRCLK_BASE |= 1UL << HAL_LL_PWRCLK_BIT) : 0) +#endif + +/*!< @brief DMA module enable macro. */ +#define HAL_LL_DMA_MODULE_ENABLE(_x) (_x->cr |= 1U << HAL_LL_DMA_CCR_EN_BIT) + +/*!< @brief DMA module disable macro. */ +#define HAL_LL_DMA_MODULE_DISABLE(_x) (_x->cr &= ~(1U << HAL_LL_DMA_CCR_EN_BIT)) + +/*!< @brief Default timeout value to wait when checking if module is disabled/enabled. */ +#define DEFAULT_TIMEOUT_VALUE (0xFFFFU) + +// ----------------------------------------------------------- PRIVATE TYPEDEFS + +/*!< @brief DMA HW register structure. */ +typedef struct dma_handle +{ + volatile uint32_t cr; /*!< DMA channel x configuration register (DMA_CCRx) */ + volatile uint32_t ndtr; /*!< DMA channel x number of data to transfer register (DMA_CNDTRx) */ + volatile uint32_t par; /*!< DMA channel x peripheral address register (DMA_CPARx) */ + volatile uint32_t mar; /*!< DMA channel x memory address register (DMA_CMARx) */ + +} dma_handle_t; + + +typedef struct dmamux_registers +{ + volatile uint32_t dmamux_cr; /*!< DMA interrupt status register */ + +} dmamux_registers_t; + +/*!< @brief DMA HW ISR register structure. */ +typedef struct dma_isr_registers +{ + volatile uint32_t isr; /*!< DMA interrupt status register (DMA_ISR) */ + volatile uint32_t ifcr; /*!< DMA interrupt flag clear register (DMA_IFCR) */ + +} dma_isr_registers_t; + +/*!< @brief DMA HW clock settings structure. */ +typedef struct +{ + uint8_t clock_bit; + hal_ll_base_addr_t clock_base; +} dma_clock_t; + +/*!< @brief DMA control settings structure. */ +typedef struct +{ + dma_clock_t clock; + hal_ll_base_addr_t stream_base; +} dma_control_struct_t; + +// ------------------------------------------------------------------ VARIABLES + +static const dma_control_struct_t dma_controller[ DMA_NUM_OF_MODULES ] = +{ + { + { HAL_LL_DMA1_CLOCK_BIT, HAL_LL_DMA1_CLOCK_BASE }, HAL_LL_DMA1_STREAM_BASE + } + ,{ + { HAL_LL_DMA2_CLOCK_BIT, HAL_LL_DMA2_CLOCK_BASE }, HAL_LL_DMA2_STREAM_BASE + } +}; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS + +/** + * @brief Gets current stream address. + * @details Returns stream address based on @ref module value and + * desired @ref stream value. + * @param[in] module DMA module number. + * @param[in] stream DMA stream number. + * @return hal_ll_base_addr_t stream base register address. + */ +static hal_ll_base_addr_t hal_ll_dma_get_stream_address( uint8_t module, uint8_t stream ); + +/** + * @brief Sets current module clock. + * @details If @ref state is @b true, enables DMA module clock. + * If @ref state is @b false, disables DMA module clock. + * @param[in] dma_obj DMA object. + * @param[in] state Desired state. + * - @b true + * - @b false + * @return Nothing. + */ +static void hal_ll_dma_clock_set( hal_ll_dma_t *dma_obj, bool state ); + +/** + * @brief Initializes DMA module. + * @details Initializes DMA module, stream to + * values from @ref config structure. + * @param[in] dma_obj DMA object. + * @param[in] dma DMA HW handle. + * @param[in] config DMA configuration structure. + * @return hal_ll_err_t Returns initialization state, either success or fail. + */ +static hal_ll_err_t hal_ll_dma_init_hw( hal_ll_dma_t *dma_obj, dma_handle_t *dma, hal_ll_dma_config_t config ); + +/** + * @brief Gets DMA module state. + * @details Checks if current DMA module stream has been stopped. + * Waits for defined @ref DEFAULT_TIMEOUT_VALUE number of cycles + * before jumping out of loop and returning @ref HAL_LL_DMA_ERROR. + * @param[in] dma DMA HW handle. + * @return hal_ll_err_t Returns success or fail. + */ +static inline hal_ll_err_t hal_ll_dma_is_module_disabled( dma_handle_t *dma ); + +/** + * @brief Gets DMA channel. + * @details Returns appropriate value to be set in HW register + * for desired @ref channel. + * @param[in] channel DMA channel number. + * @return uint32_t Returns actual HW register value based on @ref channel. + */ +static inline uint32_t hal_ll_dma_get_reg_value_channel( uint8_t channel ); + +/** + * @brief Gets DMA direction. + * @details Returns appropriate value to be set in HW register + * for desired @ref direction. + * @param[in] direction DMA stream direction. + * Refer to @hal_ll_dma_direction_t for possible values. + * @return uint8_t Returns actual HW register value based on @ref direction. + */ +static inline uint16_t hal_ll_dma_get_reg_value_direction( hal_ll_dma_direction_t direction ); + +/** + * @brief Gets DMA peripheral address increment. + * @details Returns appropriate value to be set in HW register + * for desired @ref set_inc. + * @param[in] set_inc DMA channel peripheral address increment. + * Set to @b true in order to increment address. + * Set to @b false in order to keep address the same. + * @return uint16_t Returns actual HW register value based on @ref set_inc. + */ +static inline uint16_t hal_ll_dma_get_reg_value_dst_inc( bool set_inc ); + +/** + * @brief Gets DMA memory address increment. + * @details Returns appropriate value to be set in HW register + * for desired @ref set_inc. + * @param[in] set_inc DMA channel memory address increment. + * Set to @b true in order to increment address. + * Set to @b false in order to keep address the same. + * @return uint16_t Returns actual HW register value based on @ref set_inc. + */ +static inline uint16_t hal_ll_dma_get_reg_value_src_inc( bool set_inc ); + +/** + * @brief Gets DMA memory address alignment. + * @details Returns appropriate value to be set in HW register + * for desired @ref align. + * @param[in] align DMA channel memory address increment. + * Refer to @ref hal_ll_dma_data_align_t for possible values. + * @return uint16_t Returns actual HW register value based on @ref align. + */ +static inline uint16_t hal_ll_dma_get_reg_value_source_size( hal_ll_dma_data_align_t align ); + +/** + * @brief Gets DMA peripheral address alignment. + * @details Returns appropriate value to be set in HW register + * for desired @ref align. + * @param[in] align DMA channel peripheral address increment. + * Refer to @ref hal_ll_dma_data_align_t for possible values. + * @return uint16_t Returns actual HW register value based on @ref align. + */ +static inline uint16_t hal_ll_dma_get_reg_value_destination_size( hal_ll_dma_data_align_t align ); + +/** + * @brief Gets DMA mode value. + * @details Returns appropriate value to be set in HW register + * for desired @ref mode. + * @param[in] mode DMA mode for object channel. + * Refer to @ref hal_ll_dma_mode_t for possible values. + * @return uint16_t Returns actual HW register value based on @ref mode. + */ +static inline uint16_t hal_ll_dma_get_reg_value_mode( hal_ll_dma_mode_t mode ); + +/** + * @brief Gets DMA priority value. + * @details Returns appropriate value to be set in HW register + * for desired @ref priority. + * @param[in] priority DMA priority for object channel. + * Refer to @ref hal_ll_dma_priority_t for possible values. + * @return uint32_t Returns actual HW register value based on @ref priority. + */ +static inline uint32_t hal_ll_dma_get_reg_value_priority( hal_ll_dma_priority_t priority ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS + +hal_ll_err_t hal_ll_dma_init( hal_ll_dma_t *obj ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + + // Enable PWRCLK. + #ifdef HAL_LL_PWRCLK_BASE + _HAL_LL_ENABLE_CLOCK_PWR_; + #endif + + // Enable current stream clock. + hal_ll_dma_clock_set( obj, true ); + + // Initialize current stream. + obj->handle = hal_ll_dma_get_stream_address( obj->module, obj->stream ); + status = hal_ll_dma_init_hw( obj, + (dma_handle_t *)obj->handle, + obj->config ); + + if ( HAL_LL_DMA_SUCCESS != status ) { + obj->handle = 0; // If initialization failed, reset handle. + } + + return status; +} + +hal_ll_err_t hal_ll_dma_deinit( hal_ll_dma_t *obj ) { + // First abort current transfer. + if ( HAL_LL_DMA_SUCCESS != hal_ll_dma_transfer_abort( obj ) ) + return HAL_LL_DMA_ERROR; + // Finally, disable module clock. + hal_ll_dma_clock_set( obj, false ); + + return HAL_LL_DMA_SUCCESS; +} + +hal_ll_err_t hal_ll_dma_set_mode( hal_ll_dma_t *obj, hal_ll_dma_mode_t mode ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + // Get new mode. + hal_ll_dma_config_t cfg = obj->config; + cfg.mode = mode; + // Disable module first. + HAL_LL_DMA_MODULE_DISABLE( ((dma_handle_t *)obj->handle) ); + // Try to set new mode. + status = hal_ll_dma_init_hw( obj, + (dma_handle_t *)obj->handle, + cfg ); + + return status; +} + +hal_ll_err_t hal_ll_dma_set_direction( hal_ll_dma_t *obj, hal_ll_dma_direction_t direction ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + // Get new direction. + hal_ll_dma_config_t cfg = obj->config; + cfg.direction = direction; + // Disable module first. + HAL_LL_DMA_MODULE_DISABLE( ((dma_handle_t *)obj->handle) ); + // Try to set new value. + status = hal_ll_dma_init_hw( obj, + (dma_handle_t *)obj->handle, + cfg ); + + return status; +} + +hal_ll_err_t hal_ll_dma_set_priority( hal_ll_dma_t *obj, hal_ll_dma_priority_t priority ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + // Get new priority. + hal_ll_dma_config_t cfg = obj->config; + cfg.priority = priority; + // Disable module first. + HAL_LL_DMA_MODULE_DISABLE( ((dma_handle_t *)obj->handle) ); + // Try to set new value. + status = hal_ll_dma_init_hw( obj, + (dma_handle_t *)obj->handle, + cfg ); + + return status; +} + +hal_ll_err_t hal_ll_dma_set_parameters( hal_ll_dma_t *obj, uint32_t addr_src, uint32_t addr_dst, size_t transfer_size, hal_ll_dma_source_memory_region_t src_mem_type ) { + dma_handle_t *dma = (dma_handle_t *)obj->handle; + uint8_t ndtr_divisor; + + // This parameter is not relevant on this architecture. + (void)src_mem_type; + + // Configure DMA Stream data length. + switch ( obj->config.data_align_destination ) { + case HAL_LL_DMA_DATA_ALIGN_BYTES_1: + case HAL_LL_DMA_DATA_ALIGN_BYTES_2: + ndtr_divisor = obj->config.data_align_destination; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_4: + ndtr_divisor = 2; + break; + + default: + return HAL_LL_DMA_ERROR; + } + dma->ndtr = transfer_size >> ndtr_divisor; + + // Memory to Peripheral. + if ( HAL_LL_DMA_DIRECTION_MEMORY_TO_PERIPH == obj->config.direction ) { + // Configure DMA stream destination address. + dma->par = addr_dst; + // Configure DMA stream source address. + dma->mar = addr_src; + } else { // Peripheral to Memory. + // Configure DMA stream source address. + dma->par = addr_src; + // Configure DMA stream destination address. + dma->mar = addr_dst; + } + return HAL_LL_DMA_SUCCESS; +} + +hal_ll_err_t hal_ll_dma_transfer_start( hal_ll_dma_t *obj ) { + HAL_LL_DMA_MODULE_ENABLE( ((dma_handle_t *)obj->handle) ); + return HAL_LL_DMA_SUCCESS; +} + +hal_ll_err_t hal_ll_dma_transfer_stop( hal_ll_dma_t *obj ) { + dma_handle_t *dma = (dma_handle_t *)obj->handle; + uint16_t timeout = DEFAULT_TIMEOUT_VALUE; + + if ( HAL_LL_DMA_MODE_CIRCULAR == obj->config.mode ) + return HAL_LL_DMA_ERROR; + + while ( dma->ndtr ) { + if ( 0 == timeout-- ) + return HAL_LL_DMA_ERROR; + } + + HAL_LL_DMA_MODULE_DISABLE( dma ); + + return HAL_LL_DMA_SUCCESS; +} + +hal_ll_err_t hal_ll_dma_transfer_abort( hal_ll_dma_t *obj ) { + hal_ll_err_t status = HAL_LL_DMA_SUCCESS; + dma_handle_t *dma = (dma_handle_t *)obj->handle; + + // Calculate DMA base and stream number. + dma_isr_registers_t *regs = (dma_isr_registers_t *)(dma_controller[obj->module].stream_base - CCR_BASE_OFFSET); + + // Disable all the transfer interrupts. + dma->cr &= ~(HAL_LL_DMA_CCR_TCIE_BIT | HAL_LL_DMA_CCR_HTIE_BIT | HAL_LL_DMA_CCR_TEIE_BIT); + + // Disable the stream. + HAL_LL_DMA_MODULE_DISABLE( dma ); + + // Wait for bit to be cleared. + status = hal_ll_dma_is_module_disabled( dma ); + + // Clear all interrupt flags at correct offset within the register. + if ( HAL_LL_DMA_SUCCESS == status ) + regs->ifcr = HAL_LL_DMA_IT_CLEAR_MASK << ( obj->stream * 4 ); + + return status; +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS + +static hal_ll_base_addr_t hal_ll_dma_get_stream_address( uint8_t module, uint8_t stream ) { + return ((hal_ll_base_addr_t)dma_controller[module].stream_base + (hal_ll_base_addr_t)(STREAM_BASE_OFFSET * (stream))); +} + +static void hal_ll_dma_clock_set( hal_ll_dma_t *obj, bool state ) { + if ( state ) { + set_reg_bit( (uint32_t *)dma_controller[obj->module].clock.clock_base, + dma_controller[obj->module].clock.clock_bit ); + set_reg_bit( (uint32_t *)dma_controller[obj->module].clock.clock_base, HAL_LL_DMAMUX1_CLOCK_BIT); + } else { + clear_reg_bit( (uint32_t *)dma_controller[obj->module].clock.clock_base, + dma_controller[obj->module].clock.clock_bit ); + } +} + +static hal_ll_err_t hal_ll_dma_init_hw( hal_ll_dma_t *obj, dma_handle_t *dma, hal_ll_dma_config_t config ) { + volatile uint32_t tmp = 0UL; + // Check if user entered invalid data aka HAL_LL_DMA_DATA_ALIGN_BYTES_3 + if (HAL_LL_DMA_DATA_ALIGN_BYTES_3 == config.data_align_source || HAL_LL_DMA_DATA_ALIGN_BYTES_3 == config.data_align_destination ) { + return HAL_LL_DMA_ERROR; + } + + // Disable the peripheral first. + HAL_LL_DMA_MODULE_DISABLE(dma); + + // Wait for bit to be cleared. + if ( HAL_LL_DMA_ERROR == hal_ll_dma_is_module_disabled( dma ) ) + return HAL_LL_DMA_ERROR; + + // Get the CR register value. + tmp = dma->cr; + + // Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits. + tmp &= ((uint32_t)~( HAL_LL_DMA_CCR_EN_BIT | HAL_LL_DMA_CCR_TCIE_BIT | HAL_LL_DMA_CCR_HTIE_BIT | \ + HAL_LL_DMA_CCR_TEIE_BIT | HAL_LL_DMA_CCR_DIR_BIT | HAL_LL_DMA_CCR_CIRC_BIT | \ + HAL_LL_DMA_CCR_PINC_BIT | HAL_LL_DMA_CCR_MINC_BIT | HAL_LL_DMA_CCR_M2M_BIT | \ + HAL_LL_DMA_CCR_PSIZE_MASK | HAL_LL_DMA_CCR_MSIZE_MASK | HAL_LL_DMA_CCR_PRIO_MASK )); + + // BEGIN Prepare the DMA stream configuration. + // Set desired direction value. + tmp |= hal_ll_dma_get_reg_value_direction(config.direction); + // Set desired memory increment settings. + tmp |= hal_ll_dma_get_reg_value_src_inc(config.src_inc); + tmp |= hal_ll_dma_get_reg_value_dst_inc(config.dst_inc); + // Set desired data size settings. + tmp |= hal_ll_dma_get_reg_value_source_size(config.data_align_source); + tmp |= hal_ll_dma_get_reg_value_destination_size(config.data_align_destination); + // Set desired mode. + tmp |= hal_ll_dma_get_reg_value_mode(config.mode); + // Finally, set desired priority. + tmp |= hal_ll_dma_get_reg_value_priority(config.priority); + + // And then write to DMA stream CR register. + dma->cr = tmp; + + if (obj->module == 0 ) { + dmamux_registers_t * dmamux = (dmamux_registers_t*)( DMAMUX1_BASE + ( obj->stream * DMAMUX1_OFFSET ) ); + dmamux->dmamux_cr |= obj->channel; + } else { + dmamux_registers_t * dmamux = (dmamux_registers_t*)( DMAMUX1_BASE + ( DMA_NUM_OF_STREAMS * DMAMUX1_OFFSET ) + ( obj->stream * DMAMUX1_OFFSET ) ); + dmamux->dmamux_cr |= obj->channel; + } + + return HAL_LL_DMA_SUCCESS; +} + +static inline hal_ll_err_t hal_ll_dma_is_module_disabled( dma_handle_t *dma ) { + uint16_t timeout = DEFAULT_TIMEOUT_VALUE; + + while ( (dma->cr & (1U << HAL_LL_DMA_CCR_EN_BIT)) != 0 ) { + if ( 0 == timeout-- ) + return HAL_LL_DMA_ERROR; + } + + return HAL_LL_DMA_SUCCESS; +} + +static inline uint16_t hal_ll_dma_get_reg_value_direction( hal_ll_dma_direction_t direction ) { + volatile uint16_t direction_set = (uint8_t)HAL_LL_DMA_DIRECTION_MEMORY_TO_MEMORY; + + switch ( direction ) + { + case HAL_LL_DMA_DIRECTION_MEMORY_TO_MEMORY: + direction_set = HAL_LL_DMA_DIRECTION_MEMORY_TO_MEMORY_MASK; + break; + case HAL_LL_DMA_DIRECTION_MEMORY_TO_PERIPH: + direction_set = HAL_LL_DMA_DIRECTION_MEMORY_TO_PERIPH_MASK; + break; + case HAL_LL_DMA_DIRECTION_PERIPH_TO_MEMORY: + direction_set = HAL_LL_DMA_DIRECTION_PERIPH_TO_MEMORY_MASK; + break; + + default: + break; + } + + return (uint16_t)direction_set; +} + +static inline uint16_t hal_ll_dma_get_reg_value_dst_inc( bool set_inc ) { + return (uint16_t)((set_inc) ? (HAL_LL_DMA_PINC_MASK) : (0)); +} + +static inline uint16_t hal_ll_dma_get_reg_value_src_inc( bool set_inc ) { + return (uint16_t)((set_inc) ? (HAL_LL_DMA_MINC_MASK) : (0)); +} + +static inline uint16_t hal_ll_dma_get_reg_value_source_size( hal_ll_dma_data_align_t align ) { + volatile uint16_t align_set = (uint16_t)HAL_LL_DMA_DATA_ALIGN_BYTES_1; + + switch ( align ) + { + case HAL_LL_DMA_DATA_ALIGN_BYTES_1: + align_set = HAL_LL_DMA_MSIZE_BYTE_MASK; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_2: + align_set = HAL_LL_DMA_MSIZE_HALFWORD_MASK; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_4: + align_set = HAL_LL_DMA_MSIZE_WORD_MASK; + break; + + default: + break; + } + + return (uint16_t)align_set; +} + +static inline uint16_t hal_ll_dma_get_reg_value_destination_size( hal_ll_dma_data_align_t align ) { + volatile uint16_t align_set = (uint16_t)HAL_LL_DMA_DATA_ALIGN_BYTES_1; + + switch ( align ) + { + case HAL_LL_DMA_DATA_ALIGN_BYTES_1: + align_set = HAL_LL_DMA_CCR_PSIZE_BYTE_MASK; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_2: + align_set = HAL_LL_DMA_CCR_PSIZE_HALFWORD_MASK; + break; + case HAL_LL_DMA_DATA_ALIGN_BYTES_4: + align_set = HAL_LL_DMA_CCR_PSIZE_WORD_MASK; + break; + + default: + break; + } + + return (uint16_t)align_set; +} + +static inline uint16_t hal_ll_dma_get_reg_value_mode( hal_ll_dma_mode_t mode ) { + return (uint16_t)((mode) ? (HAL_LL_DMA_CCR_CIRC_MASK) : (0)); +} + +static inline uint32_t hal_ll_dma_get_reg_value_priority( hal_ll_dma_priority_t priority ) { + volatile uint32_t priority_set = (uint32_t)HAL_LL_DMA_PRIORITY_LOW; + + switch ( priority ) + { + case HAL_LL_DMA_PRIORITY_LOW: + priority_set = HAL_LL_DMA_CCR_PRIORITY_LOW_MASK; + break; + case HAL_LL_DMA_PRIORITY_MEDIUM: + priority_set = HAL_LL_DMA_CCR_PRIORITY_MEDIUM_MASK; + break; + case HAL_LL_DMA_PRIORITY_HIGH: + priority_set = HAL_LL_DMA_CCR_PRIORITY_HIGH_MASK; + break; + case HAL_LL_DMA_PRIORITY_VERY_HIGH: + priority_set = HAL_LL_DMA_CCR_PRIORITY_VERY_HIGH_MASK; + break; + + default: + break; + } + + return (uint32_t)priority_set; +} + +// ------------------------------------------------------------------------- END + + + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/gpio/CMakeLists.txt b/targets/arm/mikroe/ai_generated/stm32/src/gpio/CMakeLists.txt new file mode 100644 index 000000000..c36f0debd --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/gpio/CMakeLists.txt @@ -0,0 +1,76 @@ +## ./targets/arm/mikroe/ai_generated/stm32/src/gpio/CMakeLists.txt + +## Check if current module is generated or not +set(MODULE_IS_GENERATED false) +get_files_recurse(${CMAKE_CURRENT_LIST_DIR}/implementations CMAKE_FILES cmake) +check_if_module_is_generated(MODULE_IS_GENERATED "${CMAKE_FILES}") + +## If current MCU has this module, add it +if(MODULE_IS_GENERATED) + set(hal_ll_def_list "") + set(MEMAKE_MCU_NAME_FIRST_7 "") + set(mcu_header_path "") + + find_cortex(hal_ll_def_list) + list(APPEND hal_ll_def_list ${MCU_NAME}) + set(mcu_header_path ${MCU_NAME}_${_MSDK_PACKAGE_ID_}) + + ## BEGIN GPIO + list(APPEND hal_ll_def_list "MACRO_USAGE_GPIO") + + ## i.e "if (${MCU_NAME} MATCHES "^STM32C011F6$|^STM32C011C6$")" + ## List all MCUs and or them in the regex + foreach(cmakeFile ${CMAKE_FILES}) + include(${cmakeFile}) + endforeach() + ## END GPIO + + mikrosdk_add_library(lib_hal_ll_gpio MikroSDK.HalLowLevel.GPIO + ${rcc_subimplementation}/hal_ll_rcc.h + ../../include/hal_ll_target.h + # BEGIN GPIO + hal_ll_gpio.c + ${gpio_subimplementation} + ../../include/gpio/hal_ll_gpio.h + ../../include/gpio/hal_ll_gpio_port.h + ${gpio_subimplementation_include_dir}/hal_ll_gpio_constants.h + ${gpio_subimplementation_include_dir}/hal_ll_gpio_struct_type.h + # END GPIO + + ) + + target_compile_definitions(lib_hal_ll_gpio PUBLIC + ${hal_ll_def_list} + ) + + target_link_libraries(lib_hal_ll_gpio PUBLIC + MikroC.Core + MikroSDK.HalLowLevelCore + MikroSDK.HalLowLevelCommon + ) + + string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) + target_include_directories(lib_hal_ll_gpio + PRIVATE + ../../include + # BEGIN GPIO + ../../include/gpio + ${gpio_subimplementation_include_dir} + # END GPIO + # BEGIN RCC + ${rcc_subimplementation} + # END RCC + INTERFACE + # BUILD + $ + $ + $ + $ + # INSTALL + $ + $ + ) + + mikrosdk_install(MikroSDK.HalLowLevel.GPIO) + install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.GPIO ../../include/gpio/hal_ll_gpio.h ${gpio_subimplementation_include_dir}/hal_ll_gpio_constants.h ${gpio_subimplementation_include_dir}/hal_ll_gpio_struct_type.h ../../include/gpio/hal_ll_gpio_port.h) +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/gpio/hal_ll_gpio.c b/targets/arm/mikroe/ai_generated/stm32/src/gpio/hal_ll_gpio.c new file mode 100644 index 000000000..e219f56d4 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/gpio/hal_ll_gpio.c @@ -0,0 +1,184 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_gpio.c + * @brief GPIO HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_gpio_port.h" + +/******************************************************************************* + * + */ +void hal_ll_gpio_configure_pin(hal_ll_gpio_pin_t *pin, hal_ll_pin_name_t name, hal_ll_gpio_direction_t direction) +{ + pin->base = (hal_ll_gpio_base_t)hal_ll_gpio_port_base(hal_ll_gpio_port_index(name)); + pin->mask = hal_ll_gpio_pin_mask(name); + + if ( direction == HAL_LL_GPIO_DIGITAL_INPUT) + hal_ll_gpio_digital_input(pin->base, pin->mask); + else + hal_ll_gpio_digital_output(pin->base, pin->mask); +} + +/******************************************************************************* + * + */ +#if (FLATTEN_ME_LEVEL < FLATTEN_ME_LEVEL_LOW) +uint8_t hal_ll_gpio_read_pin_input(hal_ll_gpio_pin_t *pin) +{ + uint32_t idr_value; + + idr_value = ((hal_ll_gpio_base_handle_t *)(pin->base))->idr; + return (idr_value & pin->mask) ? 0x01 : 0x00; +} +#endif + +/******************************************************************************* + * + */ +#if (FLATTEN_ME_LEVEL < FLATTEN_ME_LEVEL_LOW) +uint8_t hal_ll_gpio_read_pin_output(hal_ll_gpio_pin_t *pin) +{ + uint32_t odr_value; + + odr_value = ((hal_ll_gpio_base_handle_t *)(pin->base))->odr; + return (odr_value & pin->mask) ? 0x01 : 0x00; +} +#endif + +/******************************************************************************* + * + */ +#if (FLATTEN_ME_LEVEL < FLATTEN_ME_LEVEL_LOW) +void hal_ll_gpio_write_pin_output(hal_ll_gpio_pin_t *pin, uint8_t value) +{ + if (value) + ((hal_ll_gpio_base_handle_t *)(pin->base))->bsrr = pin->mask; + else + ((hal_ll_gpio_base_handle_t *)(pin->base))->bsrr = (uint32_t)pin->mask << RESET_PINS_OFFSET; +} +#endif + +/******************************************************************************* + * + */ +#if (FLATTEN_ME_LEVEL < FLATTEN_ME_LEVEL_LOW) +void hal_ll_gpio_toggle_pin_output(hal_ll_gpio_pin_t *pin) +{ + uint8_t value = hal_ll_gpio_read_pin_output(pin); + hal_ll_gpio_write_pin_output(pin, !value); +} +#endif + +/******************************************************************************* + * + */ +#if (FLATTEN_ME_LEVEL < FLATTEN_ME_LEVEL_LOW) +void hal_ll_gpio_set_pin_output(hal_ll_gpio_pin_t *pin) +{ + ((hal_ll_gpio_base_handle_t *)(pin->base))->bsrr = (uint32_t)pin->mask; +} +#endif + +/******************************************************************************* + * + */ +#if (FLATTEN_ME_LEVEL < FLATTEN_ME_LEVEL_LOW) +void hal_ll_gpio_clear_pin_output(hal_ll_gpio_pin_t *pin) +{ + ((hal_ll_gpio_base_handle_t *)(pin->base))->bsrr = (uint32_t)pin->mask << RESET_PINS_OFFSET; +} +#endif + +/******************************************************************************* + * + */ +void hal_ll_gpio_configure_port(hal_ll_gpio_port_t *port, hal_ll_port_name_t name, hal_ll_gpio_mask_t mask, hal_ll_gpio_direction_t direction) +{ + port->base = hal_ll_gpio_port_base(name); + port->mask = mask; + + if (direction == HAL_LL_GPIO_DIGITAL_INPUT) + hal_ll_gpio_digital_input(port->base, port->mask); + else + hal_ll_gpio_digital_output(port->base, port->mask); +} + +/******************************************************************************* + * + */ +#if (FLATTEN_ME_LEVEL < FLATTEN_ME_LEVEL_LOW) +hal_ll_port_size_t hal_ll_gpio_read_port_input(hal_ll_gpio_port_t *port) +{ + hal_ll_gpio_base_handle_t *base_reg = (hal_ll_gpio_base_handle_t *)port->base; + + hal_ll_port_size_t read_data = base_reg->idr; + + return read_data & port->mask; +} +#endif + +/******************************************************************************* + * + */ +#if (FLATTEN_ME_LEVEL < FLATTEN_ME_LEVEL_LOW) +hal_ll_port_size_t hal_ll_gpio_read_port_output(hal_ll_gpio_port_t *port) +{ + hal_ll_gpio_base_handle_t *base_reg = (hal_ll_gpio_base_handle_t *)port->base; + + hal_ll_port_size_t read_data = base_reg->odr; + + return read_data & port->mask; +} +#endif + +/******************************************************************************* + * + */ +#if (FLATTEN_ME_LEVEL < FLATTEN_ME_LEVEL_LOW) +void hal_ll_gpio_write_port_output(hal_ll_gpio_port_t *port, hal_ll_port_size_t value) +{ + hal_ll_gpio_base_handle_t *base_reg = (hal_ll_gpio_base_handle_t *)port->base; + + base_reg->bsrr = (value & port->mask) | ( (uint32_t)(~value & port->mask) << RESET_PINS_OFFSET); +} +#endif + +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_1/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_1/CMakeLists.cmake new file mode 100644 index 000000000..aa94616ad --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_1/CMakeLists.cmake @@ -0,0 +1,8 @@ +if(${MCU_NAME} MATCHES "^STM32C011F4$|^STM32C011J4$|^STM32C011F6$|^STM32C011J6$|^STM32C011D6$") + set(gpio_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_gpio_port.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_1") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_1") + list(APPEND hal_ll_def_list "STM32C0xx") + list(APPEND hal_ll_def_list "STM32C01xx") + list(APPEND hal_ll_def_list "STM32C011xx") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_1/hal_ll_gpio_port.c b/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_1/hal_ll_gpio_port.c new file mode 100644 index 000000000..2b4de562c --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_1/hal_ll_gpio_port.c @@ -0,0 +1,392 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_gpio_port.c + * @brief GPIO HAL LOW LEVEL ported layer implementation. + */ + +#include "hal_ll_gpio_port.h" +#include "hal_ll_rcc.h" + +/** + * Defines used in source + */ +#define _SYSCFG_CFGR1 ((uint32_t *)0x40010000UL) +#define GPIO_SYSCFG_CFGR1_PA11RMP (1u << 3) +#define GPIO_SYSCFG_CFGR1_PA12RMP (1u << 4) + +#define GPIOA_BASE_ADDR 0x50000000 +#define GPIOB_BASE_ADDR 0x50000400 +#define GPIOC_BASE_ADDR 0x50000800 +#define GPIOF_BASE_ADDR 0x50001400 + +#define RCC_GPIOCLOCK _RCC_IOPENR + +#ifndef GPIOA_BASE_ADDR + #define GPIOA_BASE_ADDR 0 +#endif + +#ifndef GPIOB_BASE_ADDR + #define GPIOB_BASE_ADDR 0 +#endif + +#ifndef GPIOC_BASE_ADDR + #define GPIOC_BASE_ADDR 0 +#endif + +#ifndef GPIOF_BASE_ADDR + #define GPIOF_BASE_ADDR 0 +#endif + +static void hal_ll_gpio_config( uint32_t *port, uint16_t pin_mask, uint32_t config ); + +/*!< @brief GPIO PORT array */ +static const uint32_t _hal_ll_gpio_port_base [ 4 ] = +{ + GPIOA_BASE_ADDR, + GPIOB_BASE_ADDR, + GPIOC_BASE_ADDR, + GPIOF_BASE_ADDR +}; + +/** + * @brief Enable gpio port clock + * @param port - port base address + * @return none + */ +static void _hal_ll_gpio_clock_enable( uint32_t *port ); + +/** + * @brief Configure port pins + * @param port - port base address + * pin_mask - desired pin + * config - pin settings + * @return none + */ +static void _hal_ll_gpio_config( uint32_t *port, uint16_t pin_mask, uint32_t config ); + +/** + * @brief Configure port pins alternate + * functions + * @param module_pin - desired pin + * config - pin settings + * @return none + */ +static void _hal_ll_gpio_config_pin_alternate_enable( uint32_t module_pin, uint32_t module_config, bool state ); + +static uint8_t hal_ll_gpio_pin_index( hal_ll_pin_name_t name ) +{ + return ( uint8_t )name % PORT_SIZE; +} + +uint8_t hal_ll_gpio_port_index( hal_ll_pin_name_t name ) +{ + return ( uint8_t )name / PORT_SIZE; +} + +uint32_t hal_ll_gpio_pin_mask( hal_ll_pin_name_t name ) +{ + return ( ( uint32_t )0x01 << hal_ll_gpio_pin_index( name ) ); +} + +uint32_t hal_ll_gpio_port_base( hal_ll_port_name_t name ) +{ + return _hal_ll_gpio_port_base[ name ]; +} + +void hal_ll_gpio_analog_input( uint32_t *port, uint16_t pin_mask ) +{ + hal_ll_gpio_config( port, pin_mask, GPIO_CFG_ANALOG_INPUT ); +} + +void hal_ll_gpio_digital_input( uint32_t *port, uint16_t pin_mask ) +{ + hal_ll_gpio_config( port, pin_mask, GPIO_CFG_DIGITAL_INPUT ); +} + +void hal_ll_gpio_digital_output( uint32_t *port, uint16_t pin_mask ) +{ + hal_ll_gpio_config( port, pin_mask, GPIO_CFG_DIGITAL_OUTPUT ); +} + +void hal_ll_gpio_module_struct_init( module_struct const *module, bool state ) +{ + int32_t index = 0; + + while ( module->pins[ index ] != GPIO_MODULE_STRUCT_END ) + { + _hal_ll_gpio_config_pin_alternate_enable( module->pins[ index ], module->configs[ index ], state ); + + index++; + } +} + +/** + * @brief Enable gpio port clock + * @param port - port base address + * @return none + */ +static void hal_ll_gpio_clock_enable( uint32_t *port ) +{ + uint32_t pos = 0; + + switch ( ( uint32_t )port & 0xFFFFFC00 ) + { + #ifdef __PORT_A_CN + case GPIOA_BASE_ADDR: pos = 0x01; break; + #endif + #ifdef __PORT_B_CN + case GPIOB_BASE_ADDR: pos = 0x02; break; + #endif + #ifdef __PORT_C_CN + case GPIOC_BASE_ADDR: pos = 0x04; break; + #endif + #ifdef __PORT_F_CN + case GPIOF_BASE_ADDR: pos = 0x20; break; + #endif + } + + *(uint32_t *)RCC_GPIOCLOCK |= pos; +} + +/** + * @brief Configure single port pins + * @param port - port base address + * pin_mask - desired pin + * config - pin settings + * @return none + */ +static void hal_ll_gpio_config( uint32_t *port, uint16_t pin_mask, uint32_t config ) +{ + uint32_t pin_pos = 0; + uint32_t pos = 0; + uint32_t current_pin = 0; + + uint32_t mode = 0; + uint32_t speed = 0; + uint32_t otype = 0; + uint32_t pull = 0; + + hal_ll_gpio_base_handle_t *port_ptr; + + port_ptr = ( hal_ll_gpio_base_handle_t *)port; + + hal_ll_gpio_clock_enable( port ); + + if ( pin_mask == GPIO_PIN_MASK_LOW ) + { + port_ptr->moder &= HAL_LL_NIBBLE_HIGH_32BIT; + + if ( config == GPIO_CFG_DIGITAL_OUTPUT ) + { + port_ptr->moder |= 0x00005555; + port_ptr->otyper &= 0xFFFFFF00; + port_ptr->ospeedr |= HAL_LL_NIBBLE_LOW_32BIT; + return; + } + if ( config == GPIO_CFG_DIGITAL_INPUT ) + { + port_ptr->moder &= HAL_LL_NIBBLE_HIGH_32BIT; + return; + } + } + else if ( pin_mask == GPIO_PIN_MASK_HIGH ) + { + port_ptr->moder &= HAL_LL_NIBBLE_LOW_32BIT; + + if ( config == GPIO_CFG_DIGITAL_OUTPUT ) + { + port_ptr->moder |= 0x55550000; + port_ptr->otyper &= 0xFFFF00FF; + port_ptr->ospeedr |= HAL_LL_NIBBLE_HIGH_32BIT; + return; + } + if ( config == GPIO_CFG_DIGITAL_INPUT ) + { + port_ptr->moder &= HAL_LL_NIBBLE_LOW_32BIT; + return; + } + } + + if ( pin_mask == GPIO_PIN_MASK_ALL ) + { + if ( config == GPIO_CFG_DIGITAL_OUTPUT ) + { + port_ptr->moder = 0x55555555; + port_ptr->otyper = 0; + port_ptr->ospeedr = HAL_LL_NIBBLE_HIGH_32BIT; + return; + } + if ( config == GPIO_CFG_DIGITAL_INPUT ) + { + port_ptr->moder = 0; + return; + } + } + + if ( config & GPIO_CFG_MODE_ANALOG ) + mode = 3; + else if ( config & GPIO_CFG_MODE_ALT_FUNCTION ) + mode = 2; + else if ( config & GPIO_CFG_MODE_OUTPUT ) + mode = 1; + else + mode = 0; + + if ( config & ( GPIO_CFG_SPEED_VERY_HIGH ) ) + speed = 3; + + if ( config & ( GPIO_CFG_SPEED_HIGH ) ) + speed = 2; + + if ( config & ( GPIO_CFG_SPEED_MEDIUM ) ) + speed = 2; + + if ( config & ( GPIO_CFG_SPEED_LOW ) ) + speed = 0; + + if ( config & GPIO_CFG_OTYPE_OD ) + otype = 1; + else + otype = 0; + + if ( config & GPIO_CFG_PULL_DOWN ) + pull = 2; + else if ( config & GPIO_CFG_PULL_UP ) + pull = 1; + else + pull = 0; + + for ( pin_pos = 0x00; pin_pos < 0x10; pin_pos++ ) + { + pos = ( ( uint32_t ) 0x01 ) << pin_pos; + current_pin = pin_mask & pos; + + if ( current_pin == pos ) + { + port_ptr->moder &= ~( ( uint32_t )0x03 << ( pin_pos * 2 ) ); + port_ptr->moder |= ( ( ( uint32_t )mode ) << ( pin_pos * 2 ) ); + + if ( config & ( GPIO_CFG_MODE_OUTPUT | GPIO_CFG_MODE_ALT_FUNCTION ) ) + { + port_ptr->ospeedr &= ~( ( uint32_t )0x03 << ( pin_pos * 2 ) ); + port_ptr->ospeedr |= ( ( uint32_t )( speed ) << ( pin_pos * 2 ) ); + + port_ptr->otyper &= ~( ( uint32_t )0x01 << ( ( uint16_t )pin_pos ) ) ; + port_ptr->otyper |= ( uint16_t )( ( ( uint16_t )otype ) << ( ( uint16_t )pin_pos ) ); + } + + port_ptr->pupdr &= ~( ( uint32_t )0x03 << ( ( uint16_t )pin_pos * 2 ) ); + port_ptr->pupdr |= ( ( ( uint32_t )pull ) << ( pin_pos * 2 ) ); + + // TODO - implement pin remap in an appropriate way + // #ifdef PA9 + // if ( PA9 == pin_pos ) + // { + // (*(uint32_t *)_SYSCFG_CFGR1 |= GPIO_SYSCFG_CFGR1_PA11RMP); + // } + // #endif + // #ifdef PA10 + // if ( PA10 == pin_pos ) + // { + // (*(uint32_t *)_SYSCFG_CFGR1 |= GPIO_SYSCFG_CFGR1_PA12RMP); + // } + // #endif + // #ifdef PA11 + // if ( PA11 == pin_pos ) + // { + // (*(uint32_t *)_SYSCFG_CFGR1 &= ~GPIO_SYSCFG_CFGR1_PA11RMP); + // } + // #endif + // #ifdef PA12 + // if ( PA12 == pin_pos ) + // { + // (*(uint32_t *)_SYSCFG_CFGR1 &= ~GPIO_SYSCFG_CFGR1_PA12RMP); + // } + // #endif + } + } +} + +/** + * @brief Configure port pins alternate + * functions + * @param module_pin - desired pin + * config - pin settings + * @return none + */ +static void _hal_ll_gpio_config_pin_alternate_enable( uint32_t module_pin, uint32_t module_config, bool state ) +{ + hal_ll_pin_name_t pin_name; + uint16_t pin_index; + uint32_t alternate_function; + hal_ll_gpio_base_handle_t *port_ptr; + + pin_name = module_pin & GPIO_PIN_NAME_MASK; + + alternate_function = ( module_pin >> GPIO_AF_OFFSET ) & GPIO_AF_MASK; + + port_ptr = ( hal_ll_gpio_base_handle_t *)hal_ll_gpio_port_base( hal_ll_gpio_port_index ( pin_name ) ); + + hal_ll_gpio_clock_enable( ( uint32_t *)port_ptr ); + + pin_index = hal_ll_gpio_pin_index( pin_name ); + if ( pin_index > 7 ) + { + pin_index -= 8; + if ( state ) { + port_ptr->afrh &= ~( ( uint32_t )( GPIO_AF_MASK ) << ( pin_index * 4 ) ); + port_ptr->afrh |= ( ( uint32_t )( alternate_function ) << ( pin_index * 4 ) ); + } else { + port_ptr->afrh &= ~( ( uint32_t )( alternate_function ) << ( pin_index * 4 ) ); + } + } + else + { + if ( state ) { + port_ptr->afrl &= ~( ( uint32_t )( GPIO_AF_MASK ) << ( pin_index * 4 ) ); + port_ptr->afrl |= ( ( uint32_t )( alternate_function ) << ( pin_index * 4 ) ); + } else { + port_ptr->afrl &= ~( ( uint32_t )( alternate_function ) << ( pin_index * 4 ) ); + } + } + + hal_ll_gpio_config( ( uint32_t*)port_ptr, hal_ll_gpio_pin_mask( pin_name ), module_config ); +} +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_160/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_160/CMakeLists.cmake new file mode 100644 index 000000000..1e4440a2c --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_160/CMakeLists.cmake @@ -0,0 +1,8 @@ +if(${MCU_NAME} MATCHES "^STM32L4P5AE$|^STM32L4P5AG$|^STM32L4P5CE$|^STM32L4P5CG$|^STM32L4P5QE$|^STM32L4P5QG$|^STM32L4P5RE$|^STM32L4P5RG$|^STM32L4P5VE$|^STM32L4P5VG$|^STM32L4P5ZE$|^STM32L4P5ZG$") + set(gpio_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_gpio_port.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_160") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_160") + list(APPEND hal_ll_def_list "STM32L4xx") + list(APPEND hal_ll_def_list "STM32L4Pxx") + list(APPEND hal_ll_def_list "STM32L4P5xx") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_160/hal_ll_gpio_port.c b/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_160/hal_ll_gpio_port.c new file mode 100644 index 000000000..6f6384a6e --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_160/hal_ll_gpio_port.c @@ -0,0 +1,428 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_gpio_port.c + * @brief GPIO HAL LOW LEVEL ported layer implementation. + */ + +#include "hal_ll_gpio_port.h" +#include "hal_ll_rcc.h" + +/** + * Defines used in source + */ +#define _PWR_CR2_ADDRESS ((uint32_t *)0x40007004UL) +#define PWR_CR2_IOSV_BIT_MASK (1UL << 9) +#define RCC_APB1ENR1_PWREN_BIT_MASK (1UL << 28) + +#define GPIOA_BASE_ADDR 0x48000000 +#define GPIOB_BASE_ADDR 0x48000400 +#define GPIOC_BASE_ADDR 0x48000800 +#define GPIOD_BASE_ADDR 0x48000C00 +#define GPIOE_BASE_ADDR 0x48001000 +#define GPIOF_BASE_ADDR 0x48001400 +#define GPIOG_BASE_ADDR 0x48001800 +#define GPIOH_BASE_ADDR 0x48001C00 +#define GPIOI_BASE_ADDR 0x48002000 + +#define RCC_GPIOCLOCK _RCC_AHB2ENR + +#ifndef GPIOA_BASE_ADDR + #define GPIOA_BASE_ADDR 0 +#endif + +#ifndef GPIOB_BASE_ADDR + #define GPIOB_BASE_ADDR 0 +#endif + +#ifndef GPIOC_BASE_ADDR + #define GPIOC_BASE_ADDR 0 +#endif + +#ifndef GPIOD_BASE_ADDR + #define GPIOD_BASE_ADDR 0 +#endif + +#ifndef GPIOE_BASE_ADDR + #define GPIOE_BASE_ADDR 0 +#endif + +#ifndef GPIOF_BASE_ADDR + #define GPIOF_BASE_ADDR 0 +#endif + +#ifndef GPIOG_BASE_ADDR + #define GPIOG_BASE_ADDR 0 +#endif + +#ifndef GPIOH_BASE_ADDR + #define GPIOH_BASE_ADDR 0 +#endif + +#ifndef GPIOI_BASE_ADDR + #define GPIOI_BASE_ADDR 0 +#endif + +static void hal_ll_gpio_config( uint32_t *port, uint16_t pin_mask, uint32_t config ); + +/*!< @brief GPIO PORT array */ +static const uint32_t _hal_ll_gpio_port_base [ 9 ] = +{ + GPIOA_BASE_ADDR, + GPIOB_BASE_ADDR, + GPIOC_BASE_ADDR, + GPIOD_BASE_ADDR, + GPIOE_BASE_ADDR, + GPIOF_BASE_ADDR, + GPIOG_BASE_ADDR, + GPIOH_BASE_ADDR, + GPIOI_BASE_ADDR +}; + +/** + * @brief Enable gpio port clock + * @param port - port base address + * @return none + */ +static void _hal_ll_gpio_clock_enable( uint32_t *port ); + +/** + * @brief Configure port pins + * @param port - port base address + * pin_mask - desired pin + * config - pin settings + * @return none + */ +static void _hal_ll_gpio_config( uint32_t *port, uint16_t pin_mask, uint32_t config ); + +/** + * @brief Configure port pins alternate + * functions + * @param module_pin - desired pin + * config - pin settings + * @return none + */ +static void _hal_ll_gpio_config_pin_alternate_enable( uint32_t module_pin, uint32_t module_config, bool state ); + +static uint8_t hal_ll_gpio_pin_index( hal_ll_pin_name_t name ) +{ + return ( uint8_t )name % PORT_SIZE; +} + +uint8_t hal_ll_gpio_port_index( hal_ll_pin_name_t name ) +{ + return ( uint8_t )name / PORT_SIZE; +} + +uint32_t hal_ll_gpio_pin_mask( hal_ll_pin_name_t name ) +{ + return ( ( uint32_t )0x01 << hal_ll_gpio_pin_index( name ) ); +} + +uint32_t hal_ll_gpio_port_base( hal_ll_port_name_t name ) +{ + return _hal_ll_gpio_port_base[ name ]; +} + +void hal_ll_gpio_analog_input( uint32_t *port, uint16_t pin_mask ) +{ + hal_ll_gpio_config( port, pin_mask, GPIO_CFG_ANALOG_INPUT ); +} + +void hal_ll_gpio_digital_input( uint32_t *port, uint16_t pin_mask ) +{ + hal_ll_gpio_config( port, pin_mask, GPIO_CFG_DIGITAL_INPUT ); +} + +void hal_ll_gpio_digital_output( uint32_t *port, uint16_t pin_mask ) +{ + hal_ll_gpio_config( port, pin_mask, GPIO_CFG_DIGITAL_OUTPUT ); +} + +void hal_ll_gpio_module_struct_init( module_struct const *module, bool state ) +{ + int32_t index = 0; + + while ( module->pins[ index ] != GPIO_MODULE_STRUCT_END ) + { + _hal_ll_gpio_config_pin_alternate_enable( module->pins[ index ], module->configs[ index ], state ); + + index++; + } +} + +/** + * @brief Enable gpio port clock + * @param port - port base address + * @return none + */ +static void hal_ll_gpio_clock_enable( uint32_t *port ) +{ + uint32_t pos = 0; + + switch ( ( uint32_t )port & 0xFFFFFC00 ) + { + #ifdef __PORT_A_CN + case GPIOA_BASE_ADDR: pos = 0x01; break; + #endif + #ifdef __PORT_B_CN + case GPIOB_BASE_ADDR: pos = 0x02; break; + #endif + #ifdef __PORT_C_CN + case GPIOC_BASE_ADDR: pos = 0x04; break; + #endif + #ifdef __PORT_D_CN + case GPIOD_BASE_ADDR: pos = 0x08; break; + #endif + #ifdef __PORT_E_CN + case GPIOE_BASE_ADDR: pos = 0x10; break; + #endif + #ifdef __PORT_F_CN + case GPIOF_BASE_ADDR: pos = 0x20; break; + #endif + #ifdef __PORT_G_CN + case GPIOG_BASE_ADDR: pos = 0x40; break; + #endif + #ifdef __PORT_H_CN + case GPIOH_BASE_ADDR: pos = 0x80; break; + #endif + #ifdef __PORT_I_CN + case GPIOI_BASE_ADDR: pos = 0x100; break; + #endif + } + + /* + * This bit is used to validate the VDDIO2 supply for electrical and + * logical isolation purpose.Setting this bit is mandatory to use PG[15:2]. + * If VDDIO2 is not always present in the application, the PVM can be used + * to determine whether this supply is ready or not. + * Procedure: + * 1. Enable power interface clock ( page 290 in ref manual ) + * 2. Validate VDDIO2 supply ( page 218 in ref manual ) + * + * Ref. manual + * + */ + *(uint32_t *)_RCC_APB1ENR1 |= RCC_APB1ENR1_PWREN_BIT_MASK; + *(uint32_t *)_PWR_CR2_ADDRESS |= PWR_CR2_IOSV_BIT_MASK; + + *(uint32_t *)RCC_GPIOCLOCK |= pos; +} + +/** + * @brief Configure single port pins + * @param port - port base address + * pin_mask - desired pin + * config - pin settings + * @return none + */ +static void hal_ll_gpio_config( uint32_t *port, uint16_t pin_mask, uint32_t config ) +{ + uint32_t pin_pos = 0; + uint32_t pos = 0; + uint32_t current_pin = 0; + + uint32_t mode = 0; + uint32_t speed = 0; + uint32_t otype = 0; + uint32_t pull = 0; + + hal_ll_gpio_base_handle_t *port_ptr; + + port_ptr = ( hal_ll_gpio_base_handle_t *)port; + + hal_ll_gpio_clock_enable( port ); + + if ( pin_mask == GPIO_PIN_MASK_LOW ) + { + port_ptr->moder &= HAL_LL_NIBBLE_HIGH_32BIT; + + if ( config == GPIO_CFG_DIGITAL_OUTPUT ) + { + port_ptr->moder |= 0x00005555; + port_ptr->otyper &= 0xFFFFFF00; + port_ptr->ospeedr |= HAL_LL_NIBBLE_LOW_32BIT; + return; + } + if ( config == GPIO_CFG_DIGITAL_INPUT ) + { + port_ptr->moder &= HAL_LL_NIBBLE_HIGH_32BIT; + return; + } + } + else if ( pin_mask == GPIO_PIN_MASK_HIGH ) + { + port_ptr->moder &= HAL_LL_NIBBLE_LOW_32BIT; + + if ( config == GPIO_CFG_DIGITAL_OUTPUT ) + { + port_ptr->moder |= 0x55550000; + port_ptr->otyper &= 0xFFFF00FF; + port_ptr->ospeedr |= HAL_LL_NIBBLE_HIGH_32BIT; + return; + } + if ( config == GPIO_CFG_DIGITAL_INPUT ) + { + port_ptr->moder &= HAL_LL_NIBBLE_LOW_32BIT; + return; + } + } + + if ( pin_mask == GPIO_PIN_MASK_ALL ) + { + if ( config == GPIO_CFG_DIGITAL_OUTPUT ) + { + port_ptr->moder = 0x55555555; + port_ptr->otyper = 0; + port_ptr->ospeedr = HAL_LL_NIBBLE_HIGH_32BIT; + return; + } + if ( config == GPIO_CFG_DIGITAL_INPUT ) + { + port_ptr->moder = 0; + return; + } + } + + if ( config & GPIO_CFG_MODE_ANALOG ) + mode = 3; + else if ( config & GPIO_CFG_MODE_ALT_FUNCTION ) + mode = 2; + else if ( config & GPIO_CFG_MODE_OUTPUT ) + mode = 1; + else + mode = 0; + + if ( config & ( GPIO_CFG_SPEED_VERY_HIGH ) ) + speed = 3; + + if ( config & ( GPIO_CFG_SPEED_HIGH ) ) + speed = 2; + + if ( config & ( GPIO_CFG_SPEED_MEDIUM ) ) + speed = 1; + + if ( config & ( GPIO_CFG_SPEED_LOW ) ) + speed = 0; + + if ( config & GPIO_CFG_OTYPE_OD ) + otype = 1; + else + otype = 0; + + if ( config & GPIO_CFG_PULL_DOWN ) + pull = 2; + else if ( config & GPIO_CFG_PULL_UP ) + pull = 1; + else + pull = 0; + + + for ( pin_pos = 0x00; pin_pos < 0x10; pin_pos++ ) + { + pos = ( ( uint32_t ) 0x01 ) << pin_pos; + current_pin = pin_mask & pos; + + if ( current_pin == pos ) + { + port_ptr->moder &= ~( ( uint32_t )0x03 << ( pin_pos * 2 ) ); + port_ptr->moder |= ( ( ( uint32_t )mode ) << ( pin_pos * 2 ) ); + + if ( config & ( GPIO_CFG_MODE_OUTPUT | GPIO_CFG_MODE_ALT_FUNCTION ) ) + { + port_ptr->ospeedr &= ~( ( uint32_t )0x03 << ( pin_pos * 2 ) ); + port_ptr->ospeedr |= ( ( uint32_t )( speed ) << ( pin_pos * 2 ) ); + + port_ptr->otyper &= ~( ( uint32_t )0x01 << ( ( uint16_t )pin_pos ) ) ; + port_ptr->otyper |= ( uint16_t )( ( ( uint16_t )otype ) << ( ( uint16_t )pin_pos ) ); + } + + port_ptr->pupdr &= ~( ( uint32_t )0x03 << ( ( uint16_t )pin_pos * 2 ) ); + port_ptr->pupdr |= ( ( ( uint32_t )pull ) << ( pin_pos * 2 ) ); + + } + } +} + +/** + * @brief Configure port pins alternate + * functions + * @param module_pin - desired pin + * config - pin settings + * @return none + */ +static void _hal_ll_gpio_config_pin_alternate_enable( uint32_t module_pin, uint32_t module_config, bool state ) +{ + hal_ll_pin_name_t pin_name; + uint16_t pin_index; + uint32_t alternate_function; + hal_ll_gpio_base_handle_t *port_ptr; + + pin_name = module_pin & GPIO_PIN_NAME_MASK; + + alternate_function = ( module_pin >> GPIO_AF_OFFSET ) & GPIO_AF_MASK; + + port_ptr = ( hal_ll_gpio_base_handle_t *)hal_ll_gpio_port_base( hal_ll_gpio_port_index ( pin_name ) ); + + hal_ll_gpio_clock_enable( ( uint32_t *)port_ptr ); + + pin_index = hal_ll_gpio_pin_index( pin_name ); + if ( pin_index > 7 ) + { + pin_index -= 8; + if ( state ) { + port_ptr->afrh &= ~( ( uint32_t )( GPIO_AF_MASK ) << ( pin_index * 4 ) ); + port_ptr->afrh |= ( ( uint32_t )( alternate_function ) << ( pin_index * 4 ) ); + } else { + port_ptr->afrh &= ~( ( uint32_t )( alternate_function ) << ( pin_index * 4 ) ); + } + } + else + { + if ( state ) { + port_ptr->afrl &= ~( ( uint32_t )( GPIO_AF_MASK ) << ( pin_index * 4 ) ); + port_ptr->afrl |= ( ( uint32_t )( alternate_function ) << ( pin_index * 4 ) ); + } else { + port_ptr->afrl &= ~( ( uint32_t )( alternate_function ) << ( pin_index * 4 ) ); + } + } + + hal_ll_gpio_config( ( uint32_t*)port_ptr, hal_ll_gpio_pin_mask( pin_name ), module_config ); +} +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_161/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_161/CMakeLists.cmake new file mode 100644 index 000000000..1063f8a54 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_161/CMakeLists.cmake @@ -0,0 +1,8 @@ +if(${MCU_NAME} MATCHES "^STM32L4Q5AG$|^STM32L4Q5CG$|^STM32L4Q5QG$|^STM32L4Q5RG$|^STM32L4Q5VG$|^STM32L4Q5ZG$") + set(gpio_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_gpio_port.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_161") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_161") + list(APPEND hal_ll_def_list "STM32L4xx") + list(APPEND hal_ll_def_list "STM32L4Qxx") + list(APPEND hal_ll_def_list "STM32L4Q5xx") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_161/hal_ll_gpio_port.c b/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_161/hal_ll_gpio_port.c new file mode 100644 index 000000000..0168ec4d2 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_161/hal_ll_gpio_port.c @@ -0,0 +1,501 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_gpio_port.c + * @brief GPIO HAL LOW LEVEL ported layer implementation. + */ + +#include "hal_ll_gpio_port.h" +#include "hal_ll_rcc.h" + +/** + * Defines used in source + */ + + #define GPIOA_BASE_ADDR 0x48000000 + + #define GPIOB_BASE_ADDR 0x48000400 + + #define GPIOC_BASE_ADDR 0x48000800 + + #define GPIOD_BASE_ADDR 0x48000C00 + + #define GPIOE_BASE_ADDR 0x48001000 + + #define GPIOF_BASE_ADDR 0x48001400 + + #define GPIOG_BASE_ADDR 0x48001800 + + #define GPIOH_BASE_ADDR 0x48001C00 + + #define GPIOI_BASE_ADDR 0x48002000 + + #define RCC_GPIOCLOCK _RCC_AHB2ENR + + +#ifdef STM32L4xx + #define RCC_APB1ENR1_PWREN_BIT_MASK (1UL << 28) + #define _PWR_CR2_ADDRESS ( uint32_t * )0x40007004 + #define PWR_CR2_IOSV_BIT_MASK (1U << 9) +#endif + +#ifndef GPIOA_BASE_ADDR + #define GPIOA_BASE_ADDR 0 +#endif + +#ifndef GPIOB_BASE_ADDR + #define GPIOB_BASE_ADDR 0 +#endif + +#ifndef GPIOC_BASE_ADDR + #define GPIOC_BASE_ADDR 0 +#endif + +#ifndef GPIOD_BASE_ADDR + #define GPIOD_BASE_ADDR 0 +#endif + +#ifndef GPIOE_BASE_ADDR + #define GPIOE_BASE_ADDR 0 +#endif + +#ifndef GPIOF_BASE_ADDR + #define GPIOF_BASE_ADDR 0 +#endif + +#ifndef GPIOG_BASE_ADDR + #define GPIOG_BASE_ADDR 0 +#endif + +#ifndef GPIOH_BASE_ADDR + #define GPIOH_BASE_ADDR 0 +#endif + +#ifndef GPIOI_BASE_ADDR + #define GPIOI_BASE_ADDR 0 +#endif + + +static void hal_ll_gpio_config( uint32_t *port, uint16_t pin_mask, uint32_t config ); + +/*!< @brief GPIO PORT array */ +static const uint32_t _hal_ll_gpio_port_base [ 11 ] = +{ + GPIOA_BASE_ADDR, + + GPIOB_BASE_ADDR, + + GPIOC_BASE_ADDR, + + GPIOD_BASE_ADDR, + + GPIOE_BASE_ADDR, + + GPIOF_BASE_ADDR, + + GPIOG_BASE_ADDR, + + GPIOH_BASE_ADDR, + + GPIOI_BASE_ADDR, + +}; + +/** + * @brief Enable gpio port clock + * @param port - port base address + * @return none + */ +static void _hal_ll_gpio_clock_enable( uint32_t *port ); + +/** + * @brief Configure port pins + * @param port - port base address + * pin_mask - desired pin + * config - pin settings + * @return none + */ +static void _hal_ll_gpio_config( uint32_t *port, uint16_t pin_mask, uint32_t config ); + +/** + * @brief Configure port pins alternate + * functions + * @param module_pin - desired pin + * config - pin settings + * @return none + */ +static void _hal_ll_gpio_config_pin_alternate_enable( uint32_t module_pin, uint32_t module_config, bool state ); + +static uint8_t hal_ll_gpio_pin_index( hal_ll_pin_name_t name ) +{ + return ( uint8_t )name % PORT_SIZE; +} + +uint8_t hal_ll_gpio_port_index( hal_ll_pin_name_t name ) +{ + return ( uint8_t )name / PORT_SIZE; +} + +uint32_t hal_ll_gpio_pin_mask( hal_ll_pin_name_t name ) +{ + return ( ( uint32_t )0x01 << hal_ll_gpio_pin_index( name ) ); +} + +uint32_t hal_ll_gpio_port_base( hal_ll_port_name_t name ) +{ + return _hal_ll_gpio_port_base[ name ]; +} + +void hal_ll_gpio_analog_input( uint32_t *port, uint16_t pin_mask ) +{ + hal_ll_gpio_config( port, pin_mask, GPIO_CFG_ANALOG_INPUT ); +} + +void hal_ll_gpio_digital_input( uint32_t *port, uint16_t pin_mask ) +{ + hal_ll_gpio_config( port, pin_mask, GPIO_CFG_DIGITAL_INPUT ); +} + +void hal_ll_gpio_digital_output( uint32_t *port, uint16_t pin_mask ) +{ + hal_ll_gpio_config( port, pin_mask, GPIO_CFG_DIGITAL_OUTPUT ); +} + +void hal_ll_gpio_module_struct_init( module_struct const *module, bool state ) +{ + int32_t index = 0; + + + while ( module->pins[ index ] != GPIO_MODULE_STRUCT_END ) + { + _hal_ll_gpio_config_pin_alternate_enable( module->pins[ index ], module->configs[ index ], state ); + + index++; + } +} + +/** + * @brief Enable gpio port clock + * @param port - port base address + * @return none + */ +static void hal_ll_gpio_clock_enable( uint32_t *port ) +{ + uint32_t pos = 0; + + switch ( ( uint32_t )port & 0xFFFFFC00 ) + { + #ifdef __PORT_A_CN + case GPIOA_BASE_ADDR: pos = 0x01; break; + #endif + + #ifdef __PORT_B_CN + case GPIOB_BASE_ADDR: pos = 0x02; break; + #endif + + #ifdef __PORT_C_CN + case GPIOC_BASE_ADDR: pos = 0x04; break; + #endif + + #ifdef __PORT_D_CN + case GPIOD_BASE_ADDR: pos = 0x08; break; + #endif + + #ifdef __PORT_E_CN + case GPIOE_BASE_ADDR: pos = 0x10; break; + #endif + + #ifdef __PORT_F_CN + case GPIOF_BASE_ADDR: pos = 0x20; break; + #endif + + #ifdef __PORT_G_CN + case GPIOG_BASE_ADDR: pos = 0x40; break; + #endif + + #ifdef __PORT_H_CN + case GPIOH_BASE_ADDR: pos = 0x80; break; + #endif + + #ifdef __PORT_I_CN + case GPIOI_BASE_ADDR: pos = 0x100; break; + #endif + + } + + #ifdef STM32L4xx + /* + * This bit is used to validate the VDDIO2 supply for electrical and + * logical isolation purpose.Setting this bit is mandatory to use PG[15:2]. + * If VDDIO2 is not always present in the application, the PVM can be used + * to determine whether this supply is ready or not. + * Procedure: + * 1. Enable power interface clock ( page 290 in ref manual ) + * 2. Validate VDDIO2 supply ( page 218 in ref manual ) + * + * Ref. manual + * + */ + *(uint32_t *)_RCC_APB1ENR1 |= RCC_APB1ENR1_PWREN_BIT_MASK; + *(uint32_t *)_PWR_CR2_ADDRESS |= PWR_CR2_IOSV_BIT_MASK; + #endif + + #if defined(STM32F3xx) || defined(STM32F0xx) + *(uint32_t *)RCC_GPIOCLOCK |= ( uint32_t )pos << GPIO_AHB_SHIFT; + #else + *(uint32_t *)RCC_GPIOCLOCK |= pos; + #endif +} + +/** + * @brief Configure single port pins + * @param port - port base address + * pin_mask - desired pin + * config - pin settings + * @return none + */ +static void hal_ll_gpio_config( uint32_t *port, uint16_t pin_mask, uint32_t config ) +{ + uint32_t pin_pos = 0; + uint32_t pos = 0; + uint32_t current_pin = 0; + + uint32_t mode = 0; + uint32_t speed = 0; + uint32_t otype = 0; + uint32_t pull = 0; + + hal_ll_gpio_base_handle_t *port_ptr; + + port_ptr = ( hal_ll_gpio_base_handle_t *)port; + + hal_ll_gpio_clock_enable( port ); + + if ( pin_mask == GPIO_PIN_MASK_LOW ) + { + port_ptr->moder &= HAL_LL_NIBBLE_HIGH_32BIT; + + + + if ( config == GPIO_CFG_DIGITAL_OUTPUT ) + { + port_ptr->moder |= 0x00005555; + + port_ptr->otyper &= 0xFFFFFF00; + + port_ptr->ospeedr |= HAL_LL_NIBBLE_LOW_32BIT; + + + return; + } + if ( config == GPIO_CFG_DIGITAL_INPUT ) + { + port_ptr->moder &= HAL_LL_NIBBLE_HIGH_32BIT; + + + return; + } + } + else if ( pin_mask == GPIO_PIN_MASK_HIGH ) + { + port_ptr->moder &= HAL_LL_NIBBLE_LOW_32BIT; + + + + if ( config == GPIO_CFG_DIGITAL_OUTPUT ) + { + port_ptr->moder |= 0x55550000; + + port_ptr->otyper &= 0xFFFF00FF; + + port_ptr->ospeedr |= HAL_LL_NIBBLE_HIGH_32BIT; + + + return; + } + if ( config == GPIO_CFG_DIGITAL_INPUT ) + { + port_ptr->moder &= HAL_LL_NIBBLE_LOW_32BIT; + + + return; + } + } + + if ( pin_mask == GPIO_PIN_MASK_ALL ) + { + if ( config == GPIO_CFG_DIGITAL_OUTPUT ) + { + port_ptr->moder = 0x55555555; + + port_ptr->otyper = 0; + + port_ptr->ospeedr = HAL_LL_NIBBLE_HIGH_32BIT; + + + return; + } + if ( config == GPIO_CFG_DIGITAL_INPUT ) + { + port_ptr->moder = 0; + + + return; + } + } + + if ( config & GPIO_CFG_MODE_ANALOG ) + mode = 3; + else if ( config & GPIO_CFG_MODE_ALT_FUNCTION ) + mode = 2; + else if ( config & GPIO_CFG_MODE_OUTPUT ) + mode = 1; + else + mode = 0; + + #if defined(STM32F411xx) || defined(STM32F412xx) || defined(STM32F413xx) || \ + defined(STM32F423xx) || defined(STM32F446xx) || defined(STM32F3xx) + if ( config & ( GPIO_CFG_SPEED_HIGH | GPIO_CFG_SPEED_MAX ) ) + speed = 3; + #endif + if ( config & ( GPIO_CFG_SPEED_VERY_HIGH ) ) + speed = 3; + + if ( config & ( GPIO_CFG_SPEED_HIGH ) ) + speed = 2; + + if ( config & ( GPIO_CFG_SPEED_MEDIUM ) ) + speed = 1; + + if ( config & ( GPIO_CFG_SPEED_LOW ) ) + speed = 0; + + + + if ( config & GPIO_CFG_OTYPE_OD ) + otype = 1; + + else + otype = 0; + + + if ( config & GPIO_CFG_PULL_DOWN ) + pull = 2; + + else if ( config & GPIO_CFG_PULL_UP ) + pull = 1; + + else + pull = 0; + + + for ( pin_pos = 0x00; pin_pos < 0x10; pin_pos++ ) + { + pos = ( ( uint32_t ) 0x01 ) << pin_pos; + current_pin = pin_mask & pos; + + if ( current_pin == pos ) + { + port_ptr->moder &= ~( ( uint32_t )0x03 << ( pin_pos * 2 ) ); + port_ptr->moder |= ( ( ( uint32_t )mode ) << ( pin_pos * 2 ) ); + + if ( config & ( GPIO_CFG_MODE_OUTPUT | GPIO_CFG_MODE_ALT_FUNCTION ) ) + { + port_ptr->ospeedr &= ~( ( uint32_t )0x03 << ( pin_pos * 2 ) ); + port_ptr->ospeedr |= ( ( uint32_t )( speed ) << ( pin_pos * 2 ) ); + + port_ptr->otyper &= ~( ( uint32_t )0x01 << ( ( uint16_t )pin_pos ) ) ; + port_ptr->otyper |= ( uint16_t )( ( ( uint16_t )otype ) << ( ( uint16_t )pin_pos ) ); + } + + port_ptr->pupdr &= ~( ( uint32_t )0x03 << ( ( uint16_t )pin_pos * 2 ) ); + port_ptr->pupdr |= ( ( ( uint32_t )pull ) << ( pin_pos * 2 ) ); + } + } + + +} + +/** + * @brief Configure port pins alternate + * functions + * @param module_pin - desired pin + * config - pin settings + * @return none + */ +static void _hal_ll_gpio_config_pin_alternate_enable( uint32_t module_pin, uint32_t module_config, bool state ) +{ + hal_ll_pin_name_t pin_name; + uint16_t pin_index; + uint32_t alternate_function; + hal_ll_gpio_base_handle_t *port_ptr; + + pin_name = module_pin & GPIO_PIN_NAME_MASK; + + alternate_function = ( module_pin >> GPIO_AF_OFFSET ) & GPIO_AF_MASK; + + port_ptr = ( hal_ll_gpio_base_handle_t *)hal_ll_gpio_port_base( hal_ll_gpio_port_index ( pin_name ) ); + + hal_ll_gpio_clock_enable( ( uint32_t *)port_ptr ); + + pin_index = hal_ll_gpio_pin_index( pin_name ); + if ( pin_index > 7 ) + { + pin_index -= 8; + if ( state ) { + port_ptr->afrh &= ~( ( uint32_t )( GPIO_AF_MASK ) << ( pin_index * 4 ) ); + port_ptr->afrh |= ( ( uint32_t )( alternate_function ) << ( pin_index * 4 ) ); + } else { + port_ptr->afrh &= ~( ( uint32_t )( alternate_function ) << ( pin_index * 4 ) ); + } + } + else + { + if ( state ) { + port_ptr->afrl &= ~( ( uint32_t )( GPIO_AF_MASK ) << ( pin_index * 4 ) ); + port_ptr->afrl |= ( ( uint32_t )( alternate_function ) << ( pin_index * 4 ) ); + } else { + port_ptr->afrl &= ~( ( uint32_t )( alternate_function ) << ( pin_index * 4 ) ); + } + } + + hal_ll_gpio_config( ( uint32_t*)port_ptr, hal_ll_gpio_pin_mask( pin_name ), module_config ); +} +// ------------------------------------------------------------------------- END + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_2/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_2/CMakeLists.cmake new file mode 100644 index 000000000..70be075ae --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_2/CMakeLists.cmake @@ -0,0 +1,8 @@ +if(${MCU_NAME} MATCHES "^STM32C031C4$|^STM32C031F4$|^STM32C031G4$|^STM32C031K4$|^STM32C031C6$|^STM32C031F6$|^STM32C031G6$|^STM32C031K6$") + set(gpio_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_gpio_port.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_2") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_2") + list(APPEND hal_ll_def_list "STM32C0xx") + list(APPEND hal_ll_def_list "STM32C03xx") + list(APPEND hal_ll_def_list "STM32C031xx") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_2/hal_ll_gpio_port.c b/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_2/hal_ll_gpio_port.c new file mode 100644 index 000000000..2fdf99732 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_2/hal_ll_gpio_port.c @@ -0,0 +1,453 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_gpio_port.c + * @brief GPIO HAL LOW LEVEL ported layer implementation. + */ + +#include "hal_ll_gpio_port.h" +#include "hal_ll_rcc.h" + +/** + * Defines used in source + */ + + #define GPIOA_BASE_ADDR 0x50000000 + + #define GPIOB_BASE_ADDR 0x50000400 + + #define GPIOC_BASE_ADDR 0x50000800 + + #define GPIOD_BASE_ADDR 0x50000C00 + + #define GPIOF_BASE_ADDR 0x50001400 + + #define RCC_GPIOCLOCK _RCC_IOPENR + + +#ifdef STM32L4xx + #define RCC_APB1ENR1_PWREN_BIT_MASK (1UL << 28) + #define _PWR_CR2_ADDRESS ( uint32_t * )0x40007004 + #define PWR_CR2_IOSV_BIT_MASK (1U << 9) +#endif + +#ifndef GPIOA_BASE_ADDR + #define GPIOA_BASE_ADDR 0 +#endif + +#ifndef GPIOB_BASE_ADDR + #define GPIOB_BASE_ADDR 0 +#endif + +#ifndef GPIOC_BASE_ADDR + #define GPIOC_BASE_ADDR 0 +#endif + +#ifndef GPIOD_BASE_ADDR + #define GPIOD_BASE_ADDR 0 +#endif + +#ifndef GPIOF_BASE_ADDR + #define GPIOF_BASE_ADDR 0 +#endif + + +static void hal_ll_gpio_config( uint32_t *port, uint16_t pin_mask, uint32_t config ); + +/*!< @brief GPIO PORT array */ +static const uint32_t _hal_ll_gpio_port_base [ 11 ] = +{ + GPIOA_BASE_ADDR, + + GPIOB_BASE_ADDR, + + GPIOC_BASE_ADDR, + + GPIOD_BASE_ADDR, + + GPIOF_BASE_ADDR, + +}; + +/** + * @brief Enable gpio port clock + * @param port - port base address + * @return none + */ +static void _hal_ll_gpio_clock_enable( uint32_t *port ); + +/** + * @brief Configure port pins + * @param port - port base address + * pin_mask - desired pin + * config - pin settings + * @return none + */ +static void _hal_ll_gpio_config( uint32_t *port, uint16_t pin_mask, uint32_t config ); + +/** + * @brief Configure port pins alternate + * functions + * @param module_pin - desired pin + * config - pin settings + * @return none + */ +static void _hal_ll_gpio_config_pin_alternate_enable( uint32_t module_pin, uint32_t module_config, bool state ); + +static uint8_t hal_ll_gpio_pin_index( hal_ll_pin_name_t name ) +{ + return ( uint8_t )name % PORT_SIZE; +} + +uint8_t hal_ll_gpio_port_index( hal_ll_pin_name_t name ) +{ + return ( uint8_t )name / PORT_SIZE; +} + +uint32_t hal_ll_gpio_pin_mask( hal_ll_pin_name_t name ) +{ + return ( ( uint32_t )0x01 << hal_ll_gpio_pin_index( name ) ); +} + +uint32_t hal_ll_gpio_port_base( hal_ll_port_name_t name ) +{ + return _hal_ll_gpio_port_base[ name ]; +} + +void hal_ll_gpio_analog_input( uint32_t *port, uint16_t pin_mask ) +{ + hal_ll_gpio_config( port, pin_mask, GPIO_CFG_ANALOG_INPUT ); +} + +void hal_ll_gpio_digital_input( uint32_t *port, uint16_t pin_mask ) +{ + hal_ll_gpio_config( port, pin_mask, GPIO_CFG_DIGITAL_INPUT ); +} + +void hal_ll_gpio_digital_output( uint32_t *port, uint16_t pin_mask ) +{ + hal_ll_gpio_config( port, pin_mask, GPIO_CFG_DIGITAL_OUTPUT ); +} + +void hal_ll_gpio_module_struct_init( module_struct const *module, bool state ) +{ + int32_t index = 0; + + + while ( module->pins[ index ] != GPIO_MODULE_STRUCT_END ) + { + _hal_ll_gpio_config_pin_alternate_enable( module->pins[ index ], module->configs[ index ], state ); + + index++; + } +} + +/** + * @brief Enable gpio port clock + * @param port - port base address + * @return none + */ +static void hal_ll_gpio_clock_enable( uint32_t *port ) +{ + uint32_t pos = 0; + + switch ( ( uint32_t )port & 0xFFFFFC00 ) + { + #ifdef __PORT_A_CN + case GPIOA_BASE_ADDR: pos = 0x01; break; + #endif + + #ifdef __PORT_B_CN + case GPIOB_BASE_ADDR: pos = 0x02; break; + #endif + + #ifdef __PORT_C_CN + case GPIOC_BASE_ADDR: pos = 0x04; break; + #endif + + #ifdef __PORT_D_CN + case GPIOD_BASE_ADDR: pos = 0x08; break; + #endif + + #ifdef __PORT_F_CN + case GPIOF_BASE_ADDR: pos = 0x20; break; + #endif + + } + + #ifdef STM32L4xx + /* + * This bit is used to validate the VDDIO2 supply for electrical and + * logical isolation purpose.Setting this bit is mandatory to use PG[15:2]. + * If VDDIO2 is not always present in the application, the PVM can be used + * to determine whether this supply is ready or not. + * Procedure: + * 1. Enable power interface clock ( page 290 in ref manual ) + * 2. Validate VDDIO2 supply ( page 218 in ref manual ) + * + * Ref. manual + * + */ + *(uint32_t *)_RCC_APB1ENR1 |= RCC_APB1ENR1_PWREN_BIT_MASK; + *(uint32_t *)_PWR_CR2_ADDRESS |= PWR_CR2_IOSV_BIT_MASK; + #endif + + #if defined(STM32F3xx) || defined(STM32F0xx) + *(uint32_t *)RCC_GPIOCLOCK |= ( uint32_t )pos << GPIO_AHB_SHIFT; + #else + *(uint32_t *)RCC_GPIOCLOCK |= pos; + #endif +} + +/** + * @brief Configure single port pins + * @param port - port base address + * pin_mask - desired pin + * config - pin settings + * @return none + */ +static void hal_ll_gpio_config( uint32_t *port, uint16_t pin_mask, uint32_t config ) +{ + uint32_t pin_pos = 0; + uint32_t pos = 0; + uint32_t current_pin = 0; + + uint32_t mode = 0; + uint32_t speed = 0; + uint32_t otype = 0; + uint32_t pull = 0; + + hal_ll_gpio_base_handle_t *port_ptr; + + port_ptr = ( hal_ll_gpio_base_handle_t *)port; + + hal_ll_gpio_clock_enable( port ); + + if ( pin_mask == GPIO_PIN_MASK_LOW ) + { + port_ptr->moder &= HAL_LL_NIBBLE_HIGH_32BIT; + + + + if ( config == GPIO_CFG_DIGITAL_OUTPUT ) + { + port_ptr->moder |= 0x00005555; + + port_ptr->otyper &= 0xFFFFFF00; + + port_ptr->ospeedr |= HAL_LL_NIBBLE_LOW_32BIT; + + + return; + } + if ( config == GPIO_CFG_DIGITAL_INPUT ) + { + port_ptr->moder &= HAL_LL_NIBBLE_HIGH_32BIT; + + + return; + } + } + else if ( pin_mask == GPIO_PIN_MASK_HIGH ) + { + port_ptr->moder &= HAL_LL_NIBBLE_LOW_32BIT; + + + + if ( config == GPIO_CFG_DIGITAL_OUTPUT ) + { + port_ptr->moder |= 0x55550000; + + port_ptr->otyper &= 0xFFFF00FF; + + port_ptr->ospeedr |= HAL_LL_NIBBLE_HIGH_32BIT; + + + return; + } + if ( config == GPIO_CFG_DIGITAL_INPUT ) + { + port_ptr->moder &= HAL_LL_NIBBLE_LOW_32BIT; + + + return; + } + } + + if ( pin_mask == GPIO_PIN_MASK_ALL ) + { + if ( config == GPIO_CFG_DIGITAL_OUTPUT ) + { + port_ptr->moder = 0x55555555; + + port_ptr->otyper = 0; + + port_ptr->ospeedr = HAL_LL_NIBBLE_HIGH_32BIT; + + + return; + } + if ( config == GPIO_CFG_DIGITAL_INPUT ) + { + port_ptr->moder = 0; + + + return; + } + } + + if ( config & GPIO_CFG_MODE_ANALOG ) + mode = 3; + else if ( config & GPIO_CFG_MODE_ALT_FUNCTION ) + mode = 2; + else if ( config & GPIO_CFG_MODE_OUTPUT ) + mode = 1; + else + mode = 0; + + #if defined(STM32F411xx) || defined(STM32F412xx) || defined(STM32F413xx) || \ + defined(STM32F423xx) || defined(STM32F446xx) || defined(STM32F3xx) + if ( config & ( GPIO_CFG_SPEED_HIGH | GPIO_CFG_SPEED_MAX ) ) + speed = 3; + #endif + if ( config & ( GPIO_CFG_SPEED_VERY_HIGH ) ) + speed = 3; + + if ( config & ( GPIO_CFG_SPEED_HIGH ) ) + speed = 2; + + if ( config & ( GPIO_CFG_SPEED_MEDIUM ) ) + speed = 2; + + if ( config & ( GPIO_CFG_SPEED_LOW ) ) + speed = 0; + + + + if ( config & GPIO_CFG_OTYPE_OD ) + otype = 1; + + else + otype = 0; + + + if ( config & GPIO_CFG_PULL_DOWN ) + pull = 2; + + else if ( config & GPIO_CFG_PULL_UP ) + pull = 1; + + else + pull = 0; + + + for ( pin_pos = 0x00; pin_pos < 0x10; pin_pos++ ) + { + pos = ( ( uint32_t ) 0x01 ) << pin_pos; + current_pin = pin_mask & pos; + + if ( current_pin == pos ) + { + port_ptr->moder &= ~( ( uint32_t )0x03 << ( pin_pos * 2 ) ); + port_ptr->moder |= ( ( ( uint32_t )mode ) << ( pin_pos * 2 ) ); + + if ( config & ( GPIO_CFG_MODE_OUTPUT | GPIO_CFG_MODE_ALT_FUNCTION ) ) + { + port_ptr->ospeedr &= ~( ( uint32_t )0x03 << ( pin_pos * 2 ) ); + port_ptr->ospeedr |= ( ( uint32_t )( speed ) << ( pin_pos * 2 ) ); + + port_ptr->otyper &= ~( ( uint32_t )0x01 << ( ( uint16_t )pin_pos ) ) ; + port_ptr->otyper |= ( uint16_t )( ( ( uint16_t )otype ) << ( ( uint16_t )pin_pos ) ); + } + + port_ptr->pupdr &= ~( ( uint32_t )0x03 << ( ( uint16_t )pin_pos * 2 ) ); + port_ptr->pupdr |= ( ( ( uint32_t )pull ) << ( pin_pos * 2 ) ); + } + } + + +} + +/** + * @brief Configure port pins alternate + * functions + * @param module_pin - desired pin + * config - pin settings + * @return none + */ +static void _hal_ll_gpio_config_pin_alternate_enable( uint32_t module_pin, uint32_t module_config, bool state ) +{ + hal_ll_pin_name_t pin_name; + uint16_t pin_index; + uint32_t alternate_function; + hal_ll_gpio_base_handle_t *port_ptr; + + pin_name = module_pin & GPIO_PIN_NAME_MASK; + + alternate_function = ( module_pin >> GPIO_AF_OFFSET ) & GPIO_AF_MASK; + + port_ptr = ( hal_ll_gpio_base_handle_t *)hal_ll_gpio_port_base( hal_ll_gpio_port_index ( pin_name ) ); + + hal_ll_gpio_clock_enable( ( uint32_t *)port_ptr ); + + pin_index = hal_ll_gpio_pin_index( pin_name ); + if ( pin_index > 7 ) + { + pin_index -= 8; + if ( state ) { + port_ptr->afrh &= ~( ( uint32_t )( GPIO_AF_MASK ) << ( pin_index * 4 ) ); + port_ptr->afrh |= ( ( uint32_t )( alternate_function ) << ( pin_index * 4 ) ); + } else { + port_ptr->afrh &= ~( ( uint32_t )( alternate_function ) << ( pin_index * 4 ) ); + } + } + else + { + if ( state ) { + port_ptr->afrl &= ~( ( uint32_t )( GPIO_AF_MASK ) << ( pin_index * 4 ) ); + port_ptr->afrl |= ( ( uint32_t )( alternate_function ) << ( pin_index * 4 ) ); + } else { + port_ptr->afrl &= ~( ( uint32_t )( alternate_function ) << ( pin_index * 4 ) ); + } + } + + hal_ll_gpio_config( ( uint32_t*)port_ptr, hal_ll_gpio_pin_mask( pin_name ), module_config ); +} +// ------------------------------------------------------------------------- END + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_74/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_74/CMakeLists.cmake new file mode 100644 index 000000000..01c195ecb --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_74/CMakeLists.cmake @@ -0,0 +1,8 @@ +if(${MCU_NAME} MATCHES "^STM32G051C6$|^STM32G051F6$|^STM32G051G6$|^STM32G051K6$|^STM32G051C8$|^STM32G051F8$|^STM32G051G8$|^STM32G051K8$") + set(gpio_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_gpio_port.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_74") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_74") + list(APPEND hal_ll_def_list "STM32G0xx") + list(APPEND hal_ll_def_list "STM32G05xx") + list(APPEND hal_ll_def_list "STM32G051xx") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_74/hal_ll_gpio_port.c b/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_74/hal_ll_gpio_port.c new file mode 100644 index 000000000..d9b984f87 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_74/hal_ll_gpio_port.c @@ -0,0 +1,453 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_gpio_port.c + * @brief GPIO HAL LOW LEVEL ported layer implementation. + */ + +#include "hal_ll_gpio_port.h" +#include "hal_ll_rcc.h" + +/** + * Defines used in source + */ + + #define GPIOA_BASE_ADDR 0x50000000 + + #define GPIOB_BASE_ADDR 0x50000400 + + #define GPIOC_BASE_ADDR 0x50000800 + + #define GPIOD_BASE_ADDR 0x50000C00 + + #define GPIOF_BASE_ADDR 0x50001400 + + #define RCC_GPIOCLOCK _RCC_IOPENR + + +#ifdef STM32L4xx + #define RCC_APB1ENR1_PWREN_BIT_MASK (1UL << 28) + #define _PWR_CR2_ADDRESS ( uint32_t * )0x40007004 + #define PWR_CR2_IOSV_BIT_MASK (1U << 9) +#endif + +#ifndef GPIOA_BASE_ADDR + #define GPIOA_BASE_ADDR 0 +#endif + +#ifndef GPIOB_BASE_ADDR + #define GPIOB_BASE_ADDR 0 +#endif + +#ifndef GPIOC_BASE_ADDR + #define GPIOC_BASE_ADDR 0 +#endif + +#ifndef GPIOD_BASE_ADDR + #define GPIOD_BASE_ADDR 0 +#endif + +#ifndef GPIOF_BASE_ADDR + #define GPIOF_BASE_ADDR 0 +#endif + + +static void hal_ll_gpio_config( uint32_t *port, uint16_t pin_mask, uint32_t config ); + +/*!< @brief GPIO PORT array */ +static const uint32_t _hal_ll_gpio_port_base [ 11 ] = +{ + GPIOA_BASE_ADDR, + + GPIOB_BASE_ADDR, + + GPIOC_BASE_ADDR, + + GPIOD_BASE_ADDR, + + GPIOF_BASE_ADDR, + +}; + +/** + * @brief Enable gpio port clock + * @param port - port base address + * @return none + */ +static void _hal_ll_gpio_clock_enable( uint32_t *port ); + +/** + * @brief Configure port pins + * @param port - port base address + * pin_mask - desired pin + * config - pin settings + * @return none + */ +static void _hal_ll_gpio_config( uint32_t *port, uint16_t pin_mask, uint32_t config ); + +/** + * @brief Configure port pins alternate + * functions + * @param module_pin - desired pin + * config - pin settings + * @return none + */ +static void _hal_ll_gpio_config_pin_alternate_enable( uint32_t module_pin, uint32_t module_config, bool state ); + +static uint8_t hal_ll_gpio_pin_index( hal_ll_pin_name_t name ) +{ + return ( uint8_t )name % PORT_SIZE; +} + +uint8_t hal_ll_gpio_port_index( hal_ll_pin_name_t name ) +{ + return ( uint8_t )name / PORT_SIZE; +} + +uint32_t hal_ll_gpio_pin_mask( hal_ll_pin_name_t name ) +{ + return ( ( uint32_t )0x01 << hal_ll_gpio_pin_index( name ) ); +} + +uint32_t hal_ll_gpio_port_base( hal_ll_port_name_t name ) +{ + return _hal_ll_gpio_port_base[ name ]; +} + +void hal_ll_gpio_analog_input( uint32_t *port, uint16_t pin_mask ) +{ + hal_ll_gpio_config( port, pin_mask, GPIO_CFG_ANALOG_INPUT ); +} + +void hal_ll_gpio_digital_input( uint32_t *port, uint16_t pin_mask ) +{ + hal_ll_gpio_config( port, pin_mask, GPIO_CFG_DIGITAL_INPUT ); +} + +void hal_ll_gpio_digital_output( uint32_t *port, uint16_t pin_mask ) +{ + hal_ll_gpio_config( port, pin_mask, GPIO_CFG_DIGITAL_OUTPUT ); +} + +void hal_ll_gpio_module_struct_init( module_struct const *module, bool state ) +{ + int32_t index = 0; + + + while ( module->pins[ index ] != GPIO_MODULE_STRUCT_END ) + { + _hal_ll_gpio_config_pin_alternate_enable( module->pins[ index ], module->configs[ index ], state ); + + index++; + } +} + +/** + * @brief Enable gpio port clock + * @param port - port base address + * @return none + */ +static void hal_ll_gpio_clock_enable( uint32_t *port ) +{ + uint32_t pos = 0; + + switch ( ( uint32_t )port & 0xFFFFFC00 ) + { + #ifdef __PORT_A_CN + case GPIOA_BASE_ADDR: pos = 0x01; break; + #endif + + #ifdef __PORT_B_CN + case GPIOB_BASE_ADDR: pos = 0x02; break; + #endif + + #ifdef __PORT_C_CN + case GPIOC_BASE_ADDR: pos = 0x04; break; + #endif + + #ifdef __PORT_D_CN + case GPIOD_BASE_ADDR: pos = 0x08; break; + #endif + + #ifdef __PORT_F_CN + case GPIOF_BASE_ADDR: pos = 0x20; break; + #endif + + } + + #ifdef STM32L4xx + /* + * This bit is used to validate the VDDIO2 supply for electrical and + * logical isolation purpose.Setting this bit is mandatory to use PG[15:2]. + * If VDDIO2 is not always present in the application, the PVM can be used + * to determine whether this supply is ready or not. + * Procedure: + * 1. Enable power interface clock ( page 290 in ref manual ) + * 2. Validate VDDIO2 supply ( page 218 in ref manual ) + * + * Ref. manual + * + */ + *(uint32_t *)_RCC_APB1ENR1 |= RCC_APB1ENR1_PWREN_BIT_MASK; + *(uint32_t *)_PWR_CR2_ADDRESS |= PWR_CR2_IOSV_BIT_MASK; + #endif + + #if defined(STM32F3xx) || defined(STM32F0xx) + *(uint32_t *)RCC_GPIOCLOCK |= ( uint32_t )pos << GPIO_AHB_SHIFT; + #else + *(uint32_t *)RCC_GPIOCLOCK |= pos; + #endif +} + +/** + * @brief Configure single port pins + * @param port - port base address + * pin_mask - desired pin + * config - pin settings + * @return none + */ +static void hal_ll_gpio_config( uint32_t *port, uint16_t pin_mask, uint32_t config ) +{ + uint32_t pin_pos = 0; + uint32_t pos = 0; + uint32_t current_pin = 0; + + uint32_t mode = 0; + uint32_t speed = 0; + uint32_t otype = 0; + uint32_t pull = 0; + + hal_ll_gpio_base_handle_t *port_ptr; + + port_ptr = ( hal_ll_gpio_base_handle_t *)port; + + hal_ll_gpio_clock_enable( port ); + + if ( pin_mask == GPIO_PIN_MASK_LOW ) + { + port_ptr->moder &= HAL_LL_NIBBLE_HIGH_32BIT; + + + + if ( config == GPIO_CFG_DIGITAL_OUTPUT ) + { + port_ptr->moder |= 0x00005555; + + port_ptr->otyper &= 0xFFFFFF00; + + port_ptr->ospeedr |= HAL_LL_NIBBLE_LOW_32BIT; + + + return; + } + if ( config == GPIO_CFG_DIGITAL_INPUT ) + { + port_ptr->moder &= HAL_LL_NIBBLE_HIGH_32BIT; + + + return; + } + } + else if ( pin_mask == GPIO_PIN_MASK_HIGH ) + { + port_ptr->moder &= HAL_LL_NIBBLE_LOW_32BIT; + + + + if ( config == GPIO_CFG_DIGITAL_OUTPUT ) + { + port_ptr->moder |= 0x55550000; + + port_ptr->otyper &= 0xFFFF00FF; + + port_ptr->ospeedr |= HAL_LL_NIBBLE_HIGH_32BIT; + + + return; + } + if ( config == GPIO_CFG_DIGITAL_INPUT ) + { + port_ptr->moder &= HAL_LL_NIBBLE_LOW_32BIT; + + + return; + } + } + + if ( pin_mask == GPIO_PIN_MASK_ALL ) + { + if ( config == GPIO_CFG_DIGITAL_OUTPUT ) + { + port_ptr->moder = 0x55555555; + + port_ptr->otyper = 0; + + port_ptr->ospeedr = HAL_LL_NIBBLE_HIGH_32BIT; + + + return; + } + if ( config == GPIO_CFG_DIGITAL_INPUT ) + { + port_ptr->moder = 0; + + + return; + } + } + + if ( config & GPIO_CFG_MODE_ANALOG ) + mode = 3; + else if ( config & GPIO_CFG_MODE_ALT_FUNCTION ) + mode = 2; + else if ( config & GPIO_CFG_MODE_OUTPUT ) + mode = 1; + else + mode = 0; + + #if defined(STM32F411xx) || defined(STM32F412xx) || defined(STM32F413xx) || \ + defined(STM32F423xx) || defined(STM32F446xx) || defined(STM32F3xx) + if ( config & ( GPIO_CFG_SPEED_HIGH | GPIO_CFG_SPEED_MAX ) ) + speed = 3; + #endif + if ( config & ( GPIO_CFG_SPEED_VERY_HIGH ) ) + speed = 3; + + if ( config & ( GPIO_CFG_SPEED_HIGH ) ) + speed = 2; + + if ( config & ( GPIO_CFG_SPEED_MEDIUM ) ) + speed = 2; + + if ( config & ( GPIO_CFG_SPEED_LOW ) ) + speed = 1; + + + + if ( config & GPIO_CFG_OTYPE_OD ) + otype = 1; + + else + otype = 0; + + + if ( config & GPIO_CFG_PULL_DOWN ) + pull = 2; + + else if ( config & GPIO_CFG_PULL_UP ) + pull = 1; + + else + pull = 0; + + + for ( pin_pos = 0x00; pin_pos < 0x10; pin_pos++ ) + { + pos = ( ( uint32_t ) 0x01 ) << pin_pos; + current_pin = pin_mask & pos; + + if ( current_pin == pos ) + { + port_ptr->moder &= ~( ( uint32_t )0x03 << ( pin_pos * 2 ) ); + port_ptr->moder |= ( ( ( uint32_t )mode ) << ( pin_pos * 2 ) ); + + if ( config & ( GPIO_CFG_MODE_OUTPUT | GPIO_CFG_MODE_ALT_FUNCTION ) ) + { + port_ptr->ospeedr &= ~( ( uint32_t )0x03 << ( pin_pos * 2 ) ); + port_ptr->ospeedr |= ( ( uint32_t )( speed ) << ( pin_pos * 2 ) ); + + port_ptr->otyper &= ~( ( uint32_t )0x01 << ( ( uint16_t )pin_pos ) ) ; + port_ptr->otyper |= ( uint16_t )( ( ( uint16_t )otype ) << ( ( uint16_t )pin_pos ) ); + } + + port_ptr->pupdr &= ~( ( uint32_t )0x03 << ( ( uint16_t )pin_pos * 2 ) ); + port_ptr->pupdr |= ( ( ( uint32_t )pull ) << ( pin_pos * 2 ) ); + } + } + + +} + +/** + * @brief Configure port pins alternate + * functions + * @param module_pin - desired pin + * config - pin settings + * @return none + */ +static void _hal_ll_gpio_config_pin_alternate_enable( uint32_t module_pin, uint32_t module_config, bool state ) +{ + hal_ll_pin_name_t pin_name; + uint16_t pin_index; + uint32_t alternate_function; + hal_ll_gpio_base_handle_t *port_ptr; + + pin_name = module_pin & GPIO_PIN_NAME_MASK; + + alternate_function = ( module_pin >> GPIO_AF_OFFSET ) & GPIO_AF_MASK; + + port_ptr = ( hal_ll_gpio_base_handle_t *)hal_ll_gpio_port_base( hal_ll_gpio_port_index ( pin_name ) ); + + hal_ll_gpio_clock_enable( ( uint32_t *)port_ptr ); + + pin_index = hal_ll_gpio_pin_index( pin_name ); + if ( pin_index > 7 ) + { + pin_index -= 8; + if ( state ) { + port_ptr->afrh &= ~( ( uint32_t )( GPIO_AF_MASK ) << ( pin_index * 4 ) ); + port_ptr->afrh |= ( ( uint32_t )( alternate_function ) << ( pin_index * 4 ) ); + } else { + port_ptr->afrh &= ~( ( uint32_t )( alternate_function ) << ( pin_index * 4 ) ); + } + } + else + { + if ( state ) { + port_ptr->afrl &= ~( ( uint32_t )( GPIO_AF_MASK ) << ( pin_index * 4 ) ); + port_ptr->afrl |= ( ( uint32_t )( alternate_function ) << ( pin_index * 4 ) ); + } else { + port_ptr->afrl &= ~( ( uint32_t )( alternate_function ) << ( pin_index * 4 ) ); + } + } + + hal_ll_gpio_config( ( uint32_t*)port_ptr, hal_ll_gpio_pin_mask( pin_name ), module_config ); +} +// ------------------------------------------------------------------------- END + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_75/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_75/CMakeLists.cmake new file mode 100644 index 000000000..a76961f83 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_75/CMakeLists.cmake @@ -0,0 +1,8 @@ +if(${MCU_NAME} MATCHES "^STM32G061C6$|^STM32G061F6$|^STM32G061G6$|^STM32G061K6$|^STM32G061C8$|^STM32G061F8$|^STM32G061G8$|^STM32G061K8$") + set(gpio_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_gpio_port.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_75") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_75") + list(APPEND hal_ll_def_list "STM32G0xx") + list(APPEND hal_ll_def_list "STM32G06xx") + list(APPEND hal_ll_def_list "STM32G061xx") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_75/hal_ll_gpio_port.c b/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_75/hal_ll_gpio_port.c new file mode 100644 index 000000000..d9b984f87 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_75/hal_ll_gpio_port.c @@ -0,0 +1,453 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_gpio_port.c + * @brief GPIO HAL LOW LEVEL ported layer implementation. + */ + +#include "hal_ll_gpio_port.h" +#include "hal_ll_rcc.h" + +/** + * Defines used in source + */ + + #define GPIOA_BASE_ADDR 0x50000000 + + #define GPIOB_BASE_ADDR 0x50000400 + + #define GPIOC_BASE_ADDR 0x50000800 + + #define GPIOD_BASE_ADDR 0x50000C00 + + #define GPIOF_BASE_ADDR 0x50001400 + + #define RCC_GPIOCLOCK _RCC_IOPENR + + +#ifdef STM32L4xx + #define RCC_APB1ENR1_PWREN_BIT_MASK (1UL << 28) + #define _PWR_CR2_ADDRESS ( uint32_t * )0x40007004 + #define PWR_CR2_IOSV_BIT_MASK (1U << 9) +#endif + +#ifndef GPIOA_BASE_ADDR + #define GPIOA_BASE_ADDR 0 +#endif + +#ifndef GPIOB_BASE_ADDR + #define GPIOB_BASE_ADDR 0 +#endif + +#ifndef GPIOC_BASE_ADDR + #define GPIOC_BASE_ADDR 0 +#endif + +#ifndef GPIOD_BASE_ADDR + #define GPIOD_BASE_ADDR 0 +#endif + +#ifndef GPIOF_BASE_ADDR + #define GPIOF_BASE_ADDR 0 +#endif + + +static void hal_ll_gpio_config( uint32_t *port, uint16_t pin_mask, uint32_t config ); + +/*!< @brief GPIO PORT array */ +static const uint32_t _hal_ll_gpio_port_base [ 11 ] = +{ + GPIOA_BASE_ADDR, + + GPIOB_BASE_ADDR, + + GPIOC_BASE_ADDR, + + GPIOD_BASE_ADDR, + + GPIOF_BASE_ADDR, + +}; + +/** + * @brief Enable gpio port clock + * @param port - port base address + * @return none + */ +static void _hal_ll_gpio_clock_enable( uint32_t *port ); + +/** + * @brief Configure port pins + * @param port - port base address + * pin_mask - desired pin + * config - pin settings + * @return none + */ +static void _hal_ll_gpio_config( uint32_t *port, uint16_t pin_mask, uint32_t config ); + +/** + * @brief Configure port pins alternate + * functions + * @param module_pin - desired pin + * config - pin settings + * @return none + */ +static void _hal_ll_gpio_config_pin_alternate_enable( uint32_t module_pin, uint32_t module_config, bool state ); + +static uint8_t hal_ll_gpio_pin_index( hal_ll_pin_name_t name ) +{ + return ( uint8_t )name % PORT_SIZE; +} + +uint8_t hal_ll_gpio_port_index( hal_ll_pin_name_t name ) +{ + return ( uint8_t )name / PORT_SIZE; +} + +uint32_t hal_ll_gpio_pin_mask( hal_ll_pin_name_t name ) +{ + return ( ( uint32_t )0x01 << hal_ll_gpio_pin_index( name ) ); +} + +uint32_t hal_ll_gpio_port_base( hal_ll_port_name_t name ) +{ + return _hal_ll_gpio_port_base[ name ]; +} + +void hal_ll_gpio_analog_input( uint32_t *port, uint16_t pin_mask ) +{ + hal_ll_gpio_config( port, pin_mask, GPIO_CFG_ANALOG_INPUT ); +} + +void hal_ll_gpio_digital_input( uint32_t *port, uint16_t pin_mask ) +{ + hal_ll_gpio_config( port, pin_mask, GPIO_CFG_DIGITAL_INPUT ); +} + +void hal_ll_gpio_digital_output( uint32_t *port, uint16_t pin_mask ) +{ + hal_ll_gpio_config( port, pin_mask, GPIO_CFG_DIGITAL_OUTPUT ); +} + +void hal_ll_gpio_module_struct_init( module_struct const *module, bool state ) +{ + int32_t index = 0; + + + while ( module->pins[ index ] != GPIO_MODULE_STRUCT_END ) + { + _hal_ll_gpio_config_pin_alternate_enable( module->pins[ index ], module->configs[ index ], state ); + + index++; + } +} + +/** + * @brief Enable gpio port clock + * @param port - port base address + * @return none + */ +static void hal_ll_gpio_clock_enable( uint32_t *port ) +{ + uint32_t pos = 0; + + switch ( ( uint32_t )port & 0xFFFFFC00 ) + { + #ifdef __PORT_A_CN + case GPIOA_BASE_ADDR: pos = 0x01; break; + #endif + + #ifdef __PORT_B_CN + case GPIOB_BASE_ADDR: pos = 0x02; break; + #endif + + #ifdef __PORT_C_CN + case GPIOC_BASE_ADDR: pos = 0x04; break; + #endif + + #ifdef __PORT_D_CN + case GPIOD_BASE_ADDR: pos = 0x08; break; + #endif + + #ifdef __PORT_F_CN + case GPIOF_BASE_ADDR: pos = 0x20; break; + #endif + + } + + #ifdef STM32L4xx + /* + * This bit is used to validate the VDDIO2 supply for electrical and + * logical isolation purpose.Setting this bit is mandatory to use PG[15:2]. + * If VDDIO2 is not always present in the application, the PVM can be used + * to determine whether this supply is ready or not. + * Procedure: + * 1. Enable power interface clock ( page 290 in ref manual ) + * 2. Validate VDDIO2 supply ( page 218 in ref manual ) + * + * Ref. manual + * + */ + *(uint32_t *)_RCC_APB1ENR1 |= RCC_APB1ENR1_PWREN_BIT_MASK; + *(uint32_t *)_PWR_CR2_ADDRESS |= PWR_CR2_IOSV_BIT_MASK; + #endif + + #if defined(STM32F3xx) || defined(STM32F0xx) + *(uint32_t *)RCC_GPIOCLOCK |= ( uint32_t )pos << GPIO_AHB_SHIFT; + #else + *(uint32_t *)RCC_GPIOCLOCK |= pos; + #endif +} + +/** + * @brief Configure single port pins + * @param port - port base address + * pin_mask - desired pin + * config - pin settings + * @return none + */ +static void hal_ll_gpio_config( uint32_t *port, uint16_t pin_mask, uint32_t config ) +{ + uint32_t pin_pos = 0; + uint32_t pos = 0; + uint32_t current_pin = 0; + + uint32_t mode = 0; + uint32_t speed = 0; + uint32_t otype = 0; + uint32_t pull = 0; + + hal_ll_gpio_base_handle_t *port_ptr; + + port_ptr = ( hal_ll_gpio_base_handle_t *)port; + + hal_ll_gpio_clock_enable( port ); + + if ( pin_mask == GPIO_PIN_MASK_LOW ) + { + port_ptr->moder &= HAL_LL_NIBBLE_HIGH_32BIT; + + + + if ( config == GPIO_CFG_DIGITAL_OUTPUT ) + { + port_ptr->moder |= 0x00005555; + + port_ptr->otyper &= 0xFFFFFF00; + + port_ptr->ospeedr |= HAL_LL_NIBBLE_LOW_32BIT; + + + return; + } + if ( config == GPIO_CFG_DIGITAL_INPUT ) + { + port_ptr->moder &= HAL_LL_NIBBLE_HIGH_32BIT; + + + return; + } + } + else if ( pin_mask == GPIO_PIN_MASK_HIGH ) + { + port_ptr->moder &= HAL_LL_NIBBLE_LOW_32BIT; + + + + if ( config == GPIO_CFG_DIGITAL_OUTPUT ) + { + port_ptr->moder |= 0x55550000; + + port_ptr->otyper &= 0xFFFF00FF; + + port_ptr->ospeedr |= HAL_LL_NIBBLE_HIGH_32BIT; + + + return; + } + if ( config == GPIO_CFG_DIGITAL_INPUT ) + { + port_ptr->moder &= HAL_LL_NIBBLE_LOW_32BIT; + + + return; + } + } + + if ( pin_mask == GPIO_PIN_MASK_ALL ) + { + if ( config == GPIO_CFG_DIGITAL_OUTPUT ) + { + port_ptr->moder = 0x55555555; + + port_ptr->otyper = 0; + + port_ptr->ospeedr = HAL_LL_NIBBLE_HIGH_32BIT; + + + return; + } + if ( config == GPIO_CFG_DIGITAL_INPUT ) + { + port_ptr->moder = 0; + + + return; + } + } + + if ( config & GPIO_CFG_MODE_ANALOG ) + mode = 3; + else if ( config & GPIO_CFG_MODE_ALT_FUNCTION ) + mode = 2; + else if ( config & GPIO_CFG_MODE_OUTPUT ) + mode = 1; + else + mode = 0; + + #if defined(STM32F411xx) || defined(STM32F412xx) || defined(STM32F413xx) || \ + defined(STM32F423xx) || defined(STM32F446xx) || defined(STM32F3xx) + if ( config & ( GPIO_CFG_SPEED_HIGH | GPIO_CFG_SPEED_MAX ) ) + speed = 3; + #endif + if ( config & ( GPIO_CFG_SPEED_VERY_HIGH ) ) + speed = 3; + + if ( config & ( GPIO_CFG_SPEED_HIGH ) ) + speed = 2; + + if ( config & ( GPIO_CFG_SPEED_MEDIUM ) ) + speed = 2; + + if ( config & ( GPIO_CFG_SPEED_LOW ) ) + speed = 1; + + + + if ( config & GPIO_CFG_OTYPE_OD ) + otype = 1; + + else + otype = 0; + + + if ( config & GPIO_CFG_PULL_DOWN ) + pull = 2; + + else if ( config & GPIO_CFG_PULL_UP ) + pull = 1; + + else + pull = 0; + + + for ( pin_pos = 0x00; pin_pos < 0x10; pin_pos++ ) + { + pos = ( ( uint32_t ) 0x01 ) << pin_pos; + current_pin = pin_mask & pos; + + if ( current_pin == pos ) + { + port_ptr->moder &= ~( ( uint32_t )0x03 << ( pin_pos * 2 ) ); + port_ptr->moder |= ( ( ( uint32_t )mode ) << ( pin_pos * 2 ) ); + + if ( config & ( GPIO_CFG_MODE_OUTPUT | GPIO_CFG_MODE_ALT_FUNCTION ) ) + { + port_ptr->ospeedr &= ~( ( uint32_t )0x03 << ( pin_pos * 2 ) ); + port_ptr->ospeedr |= ( ( uint32_t )( speed ) << ( pin_pos * 2 ) ); + + port_ptr->otyper &= ~( ( uint32_t )0x01 << ( ( uint16_t )pin_pos ) ) ; + port_ptr->otyper |= ( uint16_t )( ( ( uint16_t )otype ) << ( ( uint16_t )pin_pos ) ); + } + + port_ptr->pupdr &= ~( ( uint32_t )0x03 << ( ( uint16_t )pin_pos * 2 ) ); + port_ptr->pupdr |= ( ( ( uint32_t )pull ) << ( pin_pos * 2 ) ); + } + } + + +} + +/** + * @brief Configure port pins alternate + * functions + * @param module_pin - desired pin + * config - pin settings + * @return none + */ +static void _hal_ll_gpio_config_pin_alternate_enable( uint32_t module_pin, uint32_t module_config, bool state ) +{ + hal_ll_pin_name_t pin_name; + uint16_t pin_index; + uint32_t alternate_function; + hal_ll_gpio_base_handle_t *port_ptr; + + pin_name = module_pin & GPIO_PIN_NAME_MASK; + + alternate_function = ( module_pin >> GPIO_AF_OFFSET ) & GPIO_AF_MASK; + + port_ptr = ( hal_ll_gpio_base_handle_t *)hal_ll_gpio_port_base( hal_ll_gpio_port_index ( pin_name ) ); + + hal_ll_gpio_clock_enable( ( uint32_t *)port_ptr ); + + pin_index = hal_ll_gpio_pin_index( pin_name ); + if ( pin_index > 7 ) + { + pin_index -= 8; + if ( state ) { + port_ptr->afrh &= ~( ( uint32_t )( GPIO_AF_MASK ) << ( pin_index * 4 ) ); + port_ptr->afrh |= ( ( uint32_t )( alternate_function ) << ( pin_index * 4 ) ); + } else { + port_ptr->afrh &= ~( ( uint32_t )( alternate_function ) << ( pin_index * 4 ) ); + } + } + else + { + if ( state ) { + port_ptr->afrl &= ~( ( uint32_t )( GPIO_AF_MASK ) << ( pin_index * 4 ) ); + port_ptr->afrl |= ( ( uint32_t )( alternate_function ) << ( pin_index * 4 ) ); + } else { + port_ptr->afrl &= ~( ( uint32_t )( alternate_function ) << ( pin_index * 4 ) ); + } + } + + hal_ll_gpio_config( ( uint32_t*)port_ptr, hal_ll_gpio_pin_mask( pin_name ), module_config ); +} +// ------------------------------------------------------------------------- END + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_80/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_80/CMakeLists.cmake new file mode 100644 index 000000000..c873a8d76 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_80/CMakeLists.cmake @@ -0,0 +1,8 @@ +if(${MCU_NAME} MATCHES "^STM32G0B1CB$|^STM32G0B1KB$|^STM32G0B1MB$|^STM32G0B1RB$|^STM32G0B1VB$|^STM32G0B1CC$|^STM32G0B1KC$|^STM32G0B1MC$|^STM32G0B1RC$|^STM32G0B1VC$|^STM32G0B1CE$|^STM32G0B1KE$|^STM32G0B1ME$|^STM32G0B1NE$|^STM32G0B1RE$|^STM32G0B1VE$") + set(gpio_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_gpio_port.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_80") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_80") + list(APPEND hal_ll_def_list "STM32G0xx") + list(APPEND hal_ll_def_list "STM32G0Bxx") + list(APPEND hal_ll_def_list "STM32G0B1xx") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_80/hal_ll_gpio_port.c b/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_80/hal_ll_gpio_port.c new file mode 100644 index 000000000..5f81955e5 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_80/hal_ll_gpio_port.c @@ -0,0 +1,382 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_gpio_port.c + * @brief GPIO HAL LOW LEVEL ported layer implementation. + */ + +#include "hal_ll_gpio_port.h" +#include "hal_ll_rcc.h" + +/** + * Defines used in source + */ +#define GPIOA_BASE_ADDR 0x50000000 +#define GPIOB_BASE_ADDR 0x50000400 +#define GPIOC_BASE_ADDR 0x50000800 +#define GPIOD_BASE_ADDR 0x50000C00 +#define GPIOE_BASE_ADDR 0x50001000 +#define GPIOF_BASE_ADDR 0x50001400 + +#define RCC_GPIOCLOCK _RCC_IOPENR + +#ifndef GPIOA_BASE_ADDR + #define GPIOA_BASE_ADDR 0 +#endif + +#ifndef GPIOB_BASE_ADDR + #define GPIOB_BASE_ADDR 0 +#endif + +#ifndef GPIOC_BASE_ADDR + #define GPIOC_BASE_ADDR 0 +#endif + +#ifndef GPIOD_BASE_ADDR + #define GPIOD_BASE_ADDR 0 +#endif + +#ifndef GPIOE_BASE_ADDR + #define GPIOE_BASE_ADDR 0 +#endif + +#ifndef GPIOF_BASE_ADDR + #define GPIOF_BASE_ADDR 0 +#endif + +static void hal_ll_gpio_config( uint32_t *port, uint16_t pin_mask, uint32_t config ); + +/*!< @brief GPIO PORT array */ +static const uint32_t _hal_ll_gpio_port_base [ 6 ] = +{ + GPIOA_BASE_ADDR, + GPIOB_BASE_ADDR, + GPIOC_BASE_ADDR, + GPIOD_BASE_ADDR, + GPIOE_BASE_ADDR, + GPIOF_BASE_ADDR +}; + +/** + * @brief Enable gpio port clock + * @param port - port base address + * @return none + */ +static void _hal_ll_gpio_clock_enable( uint32_t *port ); + +/** + * @brief Configure port pins + * @param port - port base address + * pin_mask - desired pin + * config - pin settings + * @return none + */ +static void _hal_ll_gpio_config( uint32_t *port, uint16_t pin_mask, uint32_t config ); + +/** + * @brief Configure port pins alternate + * functions + * @param module_pin - desired pin + * config - pin settings + * @return none + */ +static void _hal_ll_gpio_config_pin_alternate_enable( uint32_t module_pin, uint32_t module_config, bool state ); + +static uint8_t hal_ll_gpio_pin_index( hal_ll_pin_name_t name ) +{ + return ( uint8_t )name % PORT_SIZE; +} + +uint8_t hal_ll_gpio_port_index( hal_ll_pin_name_t name ) +{ + return ( uint8_t )name / PORT_SIZE; +} + +uint32_t hal_ll_gpio_pin_mask( hal_ll_pin_name_t name ) +{ + return ( ( uint32_t )0x01 << hal_ll_gpio_pin_index( name ) ); +} + +uint32_t hal_ll_gpio_port_base( hal_ll_port_name_t name ) +{ + return _hal_ll_gpio_port_base[ name ]; +} + +void hal_ll_gpio_analog_input( uint32_t *port, uint16_t pin_mask ) +{ + hal_ll_gpio_config( port, pin_mask, GPIO_CFG_ANALOG_INPUT ); +} + +void hal_ll_gpio_digital_input( uint32_t *port, uint16_t pin_mask ) +{ + hal_ll_gpio_config( port, pin_mask, GPIO_CFG_DIGITAL_INPUT ); +} + +void hal_ll_gpio_digital_output( uint32_t *port, uint16_t pin_mask ) +{ + hal_ll_gpio_config( port, pin_mask, GPIO_CFG_DIGITAL_OUTPUT ); +} + +void hal_ll_gpio_module_struct_init( module_struct const *module, bool state ) +{ + int32_t index = 0; + + while ( module->pins[ index ] != GPIO_MODULE_STRUCT_END ) + { + _hal_ll_gpio_config_pin_alternate_enable( module->pins[ index ], module->configs[ index ], state ); + + index++; + } +} + +/** + * @brief Enable gpio port clock + * @param port - port base address + * @return none + */ +static void hal_ll_gpio_clock_enable( uint32_t *port ) +{ + uint32_t pos = 0; + + switch ( ( uint32_t )port & 0xFFFFFC00 ) + { + #ifdef __PORT_A_CN + case GPIOA_BASE_ADDR: pos = 0x01; break; + #endif + #ifdef __PORT_B_CN + case GPIOB_BASE_ADDR: pos = 0x02; break; + #endif + #ifdef __PORT_C_CN + case GPIOC_BASE_ADDR: pos = 0x04; break; + #endif + #ifdef __PORT_D_CN + case GPIOD_BASE_ADDR: pos = 0x08; break; + #endif + #ifdef __PORT_E_CN + case GPIOE_BASE_ADDR: pos = 0x10; break; + #endif + #ifdef __PORT_F_CN + case GPIOF_BASE_ADDR: pos = 0x20; break; + #endif + } + + *(uint32_t *)RCC_GPIOCLOCK |= pos; +} + +/** + * @brief Configure single port pins + * @param port - port base address + * pin_mask - desired pin + * config - pin settings + * @return none + */ +static void hal_ll_gpio_config( uint32_t *port, uint16_t pin_mask, uint32_t config ) +{ + uint32_t pin_pos = 0; + uint32_t pos = 0; + uint32_t current_pin = 0; + + uint32_t mode = 0; + uint32_t speed = 0; + uint32_t otype = 0; + uint32_t pull = 0; + + hal_ll_gpio_base_handle_t *port_ptr; + + port_ptr = ( hal_ll_gpio_base_handle_t *)port; + + hal_ll_gpio_clock_enable( port ); + + if ( pin_mask == GPIO_PIN_MASK_LOW ) + { + port_ptr->moder &= HAL_LL_NIBBLE_HIGH_32BIT; + + if ( config == GPIO_CFG_DIGITAL_OUTPUT ) + { + port_ptr->moder |= 0x00005555; + port_ptr->otyper &= 0xFFFFFF00; + port_ptr->ospeedr |= HAL_LL_NIBBLE_LOW_32BIT; + return; + } + if ( config == GPIO_CFG_DIGITAL_INPUT ) + { + port_ptr->moder &= HAL_LL_NIBBLE_HIGH_32BIT; + return; + } + } + else if ( pin_mask == GPIO_PIN_MASK_HIGH ) + { + port_ptr->moder &= HAL_LL_NIBBLE_LOW_32BIT; + + if ( config == GPIO_CFG_DIGITAL_OUTPUT ) + { + port_ptr->moder |= 0x55550000; + port_ptr->otyper &= 0xFFFF00FF; + port_ptr->ospeedr |= HAL_LL_NIBBLE_HIGH_32BIT; + return; + } + if ( config == GPIO_CFG_DIGITAL_INPUT ) + { + port_ptr->moder &= HAL_LL_NIBBLE_LOW_32BIT; + return; + } + } + + if ( pin_mask == GPIO_PIN_MASK_ALL ) + { + if ( config == GPIO_CFG_DIGITAL_OUTPUT ) + { + port_ptr->moder = 0x55555555; + port_ptr->otyper = 0; + port_ptr->ospeedr = HAL_LL_NIBBLE_HIGH_32BIT; + return; + } + if ( config == GPIO_CFG_DIGITAL_INPUT ) + { + port_ptr->moder = 0; + return; + } + } + + if ( config & GPIO_CFG_MODE_ANALOG ) + mode = 3; + else if ( config & GPIO_CFG_MODE_ALT_FUNCTION ) + mode = 2; + else if ( config & GPIO_CFG_MODE_OUTPUT ) + mode = 1; + else + mode = 0; + + if ( config & ( GPIO_CFG_SPEED_VERY_HIGH ) ) + speed = 3; + + if ( config & ( GPIO_CFG_SPEED_HIGH ) ) + speed = 2; + + if ( config & ( GPIO_CFG_SPEED_MEDIUM ) ) + speed = 2; + + if ( config & ( GPIO_CFG_SPEED_LOW ) ) + speed = 1; + + if ( config & GPIO_CFG_OTYPE_OD ) + otype = 1; + else + otype = 0; + + if ( config & GPIO_CFG_PULL_DOWN ) + pull = 2; + + else if ( config & GPIO_CFG_PULL_UP ) + pull = 1; + + else + pull = 0; + + for ( pin_pos = 0x00; pin_pos < 0x10; pin_pos++ ) + { + pos = ( ( uint32_t ) 0x01 ) << pin_pos; + current_pin = pin_mask & pos; + + if ( current_pin == pos ) + { + port_ptr->moder &= ~( ( uint32_t )0x03 << ( pin_pos * 2 ) ); + port_ptr->moder |= ( ( ( uint32_t )mode ) << ( pin_pos * 2 ) ); + + if ( config & ( GPIO_CFG_MODE_OUTPUT | GPIO_CFG_MODE_ALT_FUNCTION ) ) + { + port_ptr->ospeedr &= ~( ( uint32_t )0x03 << ( pin_pos * 2 ) ); + port_ptr->ospeedr |= ( ( uint32_t )( speed ) << ( pin_pos * 2 ) ); + + port_ptr->otyper &= ~( ( uint32_t )0x01 << ( ( uint16_t )pin_pos ) ) ; + port_ptr->otyper |= ( uint16_t )( ( ( uint16_t )otype ) << ( ( uint16_t )pin_pos ) ); + } + + port_ptr->pupdr &= ~( ( uint32_t )0x03 << ( ( uint16_t )pin_pos * 2 ) ); + port_ptr->pupdr |= ( ( ( uint32_t )pull ) << ( pin_pos * 2 ) ); + } + } +} + +/** + * @brief Configure port pins alternate + * functions + * @param module_pin - desired pin + * config - pin settings + * @return none + */ +static void _hal_ll_gpio_config_pin_alternate_enable( uint32_t module_pin, uint32_t module_config, bool state ) +{ + hal_ll_pin_name_t pin_name; + uint16_t pin_index; + uint32_t alternate_function; + hal_ll_gpio_base_handle_t *port_ptr; + + pin_name = module_pin & GPIO_PIN_NAME_MASK; + + alternate_function = ( module_pin >> GPIO_AF_OFFSET ) & GPIO_AF_MASK; + + port_ptr = ( hal_ll_gpio_base_handle_t *)hal_ll_gpio_port_base( hal_ll_gpio_port_index ( pin_name ) ); + + hal_ll_gpio_clock_enable( ( uint32_t *)port_ptr ); + + pin_index = hal_ll_gpio_pin_index( pin_name ); + if ( pin_index > 7 ) + { + pin_index -= 8; + if ( state ) { + port_ptr->afrh &= ~( ( uint32_t )( GPIO_AF_MASK ) << ( pin_index * 4 ) ); + port_ptr->afrh |= ( ( uint32_t )( alternate_function ) << ( pin_index * 4 ) ); + } else { + port_ptr->afrh &= ~( ( uint32_t )( alternate_function ) << ( pin_index * 4 ) ); + } + } + else + { + if ( state ) { + port_ptr->afrl &= ~( ( uint32_t )( GPIO_AF_MASK ) << ( pin_index * 4 ) ); + port_ptr->afrl |= ( ( uint32_t )( alternate_function ) << ( pin_index * 4 ) ); + } else { + port_ptr->afrl &= ~( ( uint32_t )( alternate_function ) << ( pin_index * 4 ) ); + } + } + + hal_ll_gpio_config( ( uint32_t*)port_ptr, hal_ll_gpio_pin_mask( pin_name ), module_config ); +} +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_81/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_81/CMakeLists.cmake new file mode 100644 index 000000000..194934e55 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_81/CMakeLists.cmake @@ -0,0 +1,8 @@ +if(${MCU_NAME} MATCHES "^STM32G0C1CC$|^STM32G0C1KC$|^STM32G0C1MC$|^STM32G0C1RC$|^STM32G0C1VC$|^STM32G0C1CE$|^STM32G0C1KE$|^STM32G0C1ME$|^STM32G0C1NE$|^STM32G0C1RE$|^STM32G0C1VE$") + set(gpio_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_gpio_port.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_81") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_81") + list(APPEND hal_ll_def_list "STM32G0xx") + list(APPEND hal_ll_def_list "STM32G0Cxx") + list(APPEND hal_ll_def_list "STM32G0C1xx") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_81/hal_ll_gpio_port.c b/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_81/hal_ll_gpio_port.c new file mode 100644 index 000000000..bc3a66baf --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_81/hal_ll_gpio_port.c @@ -0,0 +1,465 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_gpio_port.c + * @brief GPIO HAL LOW LEVEL ported layer implementation. + */ + +#include "hal_ll_gpio_port.h" +#include "hal_ll_rcc.h" + +/** + * Defines used in source + */ + + #define GPIOA_BASE_ADDR 0x50000000 + + #define GPIOB_BASE_ADDR 0x50000400 + + #define GPIOC_BASE_ADDR 0x50000800 + + #define GPIOD_BASE_ADDR 0x50000C00 + + #define GPIOE_BASE_ADDR 0x50001000 + + #define GPIOF_BASE_ADDR 0x50001400 + + #define RCC_GPIOCLOCK _RCC_IOPENR + + +#ifdef STM32L4xx + #define RCC_APB1ENR1_PWREN_BIT_MASK (1UL << 28) + #define _PWR_CR2_ADDRESS ( uint32_t * )0x40007004 + #define PWR_CR2_IOSV_BIT_MASK (1U << 9) +#endif + +#ifndef GPIOA_BASE_ADDR + #define GPIOA_BASE_ADDR 0 +#endif + +#ifndef GPIOB_BASE_ADDR + #define GPIOB_BASE_ADDR 0 +#endif + +#ifndef GPIOC_BASE_ADDR + #define GPIOC_BASE_ADDR 0 +#endif + +#ifndef GPIOD_BASE_ADDR + #define GPIOD_BASE_ADDR 0 +#endif + +#ifndef GPIOE_BASE_ADDR + #define GPIOE_BASE_ADDR 0 +#endif + +#ifndef GPIOF_BASE_ADDR + #define GPIOF_BASE_ADDR 0 +#endif + + +static void hal_ll_gpio_config( uint32_t *port, uint16_t pin_mask, uint32_t config ); + +/*!< @brief GPIO PORT array */ +static const uint32_t _hal_ll_gpio_port_base [ 11 ] = +{ + GPIOA_BASE_ADDR, + + GPIOB_BASE_ADDR, + + GPIOC_BASE_ADDR, + + GPIOD_BASE_ADDR, + + GPIOE_BASE_ADDR, + + GPIOF_BASE_ADDR, + +}; + +/** + * @brief Enable gpio port clock + * @param port - port base address + * @return none + */ +static void _hal_ll_gpio_clock_enable( uint32_t *port ); + +/** + * @brief Configure port pins + * @param port - port base address + * pin_mask - desired pin + * config - pin settings + * @return none + */ +static void _hal_ll_gpio_config( uint32_t *port, uint16_t pin_mask, uint32_t config ); + +/** + * @brief Configure port pins alternate + * functions + * @param module_pin - desired pin + * config - pin settings + * @return none + */ +static void _hal_ll_gpio_config_pin_alternate_enable( uint32_t module_pin, uint32_t module_config, bool state ); + +static uint8_t hal_ll_gpio_pin_index( hal_ll_pin_name_t name ) +{ + return ( uint8_t )name % PORT_SIZE; +} + +uint8_t hal_ll_gpio_port_index( hal_ll_pin_name_t name ) +{ + return ( uint8_t )name / PORT_SIZE; +} + +uint32_t hal_ll_gpio_pin_mask( hal_ll_pin_name_t name ) +{ + return ( ( uint32_t )0x01 << hal_ll_gpio_pin_index( name ) ); +} + +uint32_t hal_ll_gpio_port_base( hal_ll_port_name_t name ) +{ + return _hal_ll_gpio_port_base[ name ]; +} + +void hal_ll_gpio_analog_input( uint32_t *port, uint16_t pin_mask ) +{ + hal_ll_gpio_config( port, pin_mask, GPIO_CFG_ANALOG_INPUT ); +} + +void hal_ll_gpio_digital_input( uint32_t *port, uint16_t pin_mask ) +{ + hal_ll_gpio_config( port, pin_mask, GPIO_CFG_DIGITAL_INPUT ); +} + +void hal_ll_gpio_digital_output( uint32_t *port, uint16_t pin_mask ) +{ + hal_ll_gpio_config( port, pin_mask, GPIO_CFG_DIGITAL_OUTPUT ); +} + +void hal_ll_gpio_module_struct_init( module_struct const *module, bool state ) +{ + int32_t index = 0; + + + while ( module->pins[ index ] != GPIO_MODULE_STRUCT_END ) + { + _hal_ll_gpio_config_pin_alternate_enable( module->pins[ index ], module->configs[ index ], state ); + + index++; + } +} + +/** + * @brief Enable gpio port clock + * @param port - port base address + * @return none + */ +static void hal_ll_gpio_clock_enable( uint32_t *port ) +{ + uint32_t pos = 0; + + switch ( ( uint32_t )port & 0xFFFFFC00 ) + { + #ifdef __PORT_A_CN + case GPIOA_BASE_ADDR: pos = 0x01; break; + #endif + + #ifdef __PORT_B_CN + case GPIOB_BASE_ADDR: pos = 0x02; break; + #endif + + #ifdef __PORT_C_CN + case GPIOC_BASE_ADDR: pos = 0x04; break; + #endif + + #ifdef __PORT_D_CN + case GPIOD_BASE_ADDR: pos = 0x08; break; + #endif + + #ifdef __PORT_E_CN + case GPIOE_BASE_ADDR: pos = 0x10; break; + #endif + + #ifdef __PORT_F_CN + case GPIOF_BASE_ADDR: pos = 0x20; break; + #endif + + } + + #ifdef STM32L4xx + /* + * This bit is used to validate the VDDIO2 supply for electrical and + * logical isolation purpose.Setting this bit is mandatory to use PG[15:2]. + * If VDDIO2 is not always present in the application, the PVM can be used + * to determine whether this supply is ready or not. + * Procedure: + * 1. Enable power interface clock ( page 290 in ref manual ) + * 2. Validate VDDIO2 supply ( page 218 in ref manual ) + * + * Ref. manual + * + */ + *(uint32_t *)_RCC_APB1ENR1 |= RCC_APB1ENR1_PWREN_BIT_MASK; + *(uint32_t *)_PWR_CR2_ADDRESS |= PWR_CR2_IOSV_BIT_MASK; + #endif + + #if defined(STM32F3xx) || defined(STM32F0xx) + *(uint32_t *)RCC_GPIOCLOCK |= ( uint32_t )pos << GPIO_AHB_SHIFT; + #else + *(uint32_t *)RCC_GPIOCLOCK |= pos; + #endif +} + +/** + * @brief Configure single port pins + * @param port - port base address + * pin_mask - desired pin + * config - pin settings + * @return none + */ +static void hal_ll_gpio_config( uint32_t *port, uint16_t pin_mask, uint32_t config ) +{ + uint32_t pin_pos = 0; + uint32_t pos = 0; + uint32_t current_pin = 0; + + uint32_t mode = 0; + uint32_t speed = 0; + uint32_t otype = 0; + uint32_t pull = 0; + + hal_ll_gpio_base_handle_t *port_ptr; + + port_ptr = ( hal_ll_gpio_base_handle_t *)port; + + hal_ll_gpio_clock_enable( port ); + + if ( pin_mask == GPIO_PIN_MASK_LOW ) + { + port_ptr->moder &= HAL_LL_NIBBLE_HIGH_32BIT; + + + + if ( config == GPIO_CFG_DIGITAL_OUTPUT ) + { + port_ptr->moder |= 0x00005555; + + port_ptr->otyper &= 0xFFFFFF00; + + port_ptr->ospeedr |= HAL_LL_NIBBLE_LOW_32BIT; + + + return; + } + if ( config == GPIO_CFG_DIGITAL_INPUT ) + { + port_ptr->moder &= HAL_LL_NIBBLE_HIGH_32BIT; + + + return; + } + } + else if ( pin_mask == GPIO_PIN_MASK_HIGH ) + { + port_ptr->moder &= HAL_LL_NIBBLE_LOW_32BIT; + + + + if ( config == GPIO_CFG_DIGITAL_OUTPUT ) + { + port_ptr->moder |= 0x55550000; + + port_ptr->otyper &= 0xFFFF00FF; + + port_ptr->ospeedr |= HAL_LL_NIBBLE_HIGH_32BIT; + + + return; + } + if ( config == GPIO_CFG_DIGITAL_INPUT ) + { + port_ptr->moder &= HAL_LL_NIBBLE_LOW_32BIT; + + + return; + } + } + + if ( pin_mask == GPIO_PIN_MASK_ALL ) + { + if ( config == GPIO_CFG_DIGITAL_OUTPUT ) + { + port_ptr->moder = 0x55555555; + + port_ptr->otyper = 0; + + port_ptr->ospeedr = HAL_LL_NIBBLE_HIGH_32BIT; + + + return; + } + if ( config == GPIO_CFG_DIGITAL_INPUT ) + { + port_ptr->moder = 0; + + + return; + } + } + + if ( config & GPIO_CFG_MODE_ANALOG ) + mode = 3; + else if ( config & GPIO_CFG_MODE_ALT_FUNCTION ) + mode = 2; + else if ( config & GPIO_CFG_MODE_OUTPUT ) + mode = 1; + else + mode = 0; + + #if defined(STM32F411xx) || defined(STM32F412xx) || defined(STM32F413xx) || \ + defined(STM32F423xx) || defined(STM32F446xx) || defined(STM32F3xx) + if ( config & ( GPIO_CFG_SPEED_HIGH | GPIO_CFG_SPEED_MAX ) ) + speed = 3; + #endif + if ( config & ( GPIO_CFG_SPEED_VERY_HIGH ) ) + speed = 3; + + if ( config & ( GPIO_CFG_SPEED_HIGH ) ) + speed = 2; + + if ( config & ( GPIO_CFG_SPEED_MEDIUM ) ) + speed = 2; + + if ( config & ( GPIO_CFG_SPEED_LOW ) ) + speed = 1; + + + + if ( config & GPIO_CFG_OTYPE_OD ) + otype = 1; + + else + otype = 0; + + + if ( config & GPIO_CFG_PULL_DOWN ) + pull = 2; + + else if ( config & GPIO_CFG_PULL_UP ) + pull = 1; + + else + pull = 0; + + + for ( pin_pos = 0x00; pin_pos < 0x10; pin_pos++ ) + { + pos = ( ( uint32_t ) 0x01 ) << pin_pos; + current_pin = pin_mask & pos; + + if ( current_pin == pos ) + { + port_ptr->moder &= ~( ( uint32_t )0x03 << ( pin_pos * 2 ) ); + port_ptr->moder |= ( ( ( uint32_t )mode ) << ( pin_pos * 2 ) ); + + if ( config & ( GPIO_CFG_MODE_OUTPUT | GPIO_CFG_MODE_ALT_FUNCTION ) ) + { + port_ptr->ospeedr &= ~( ( uint32_t )0x03 << ( pin_pos * 2 ) ); + port_ptr->ospeedr |= ( ( uint32_t )( speed ) << ( pin_pos * 2 ) ); + + port_ptr->otyper &= ~( ( uint32_t )0x01 << ( ( uint16_t )pin_pos ) ) ; + port_ptr->otyper |= ( uint16_t )( ( ( uint16_t )otype ) << ( ( uint16_t )pin_pos ) ); + } + + port_ptr->pupdr &= ~( ( uint32_t )0x03 << ( ( uint16_t )pin_pos * 2 ) ); + port_ptr->pupdr |= ( ( ( uint32_t )pull ) << ( pin_pos * 2 ) ); + } + } + + +} + +/** + * @brief Configure port pins alternate + * functions + * @param module_pin - desired pin + * config - pin settings + * @return none + */ +static void _hal_ll_gpio_config_pin_alternate_enable( uint32_t module_pin, uint32_t module_config, bool state ) +{ + hal_ll_pin_name_t pin_name; + uint16_t pin_index; + uint32_t alternate_function; + hal_ll_gpio_base_handle_t *port_ptr; + + pin_name = module_pin & GPIO_PIN_NAME_MASK; + + alternate_function = ( module_pin >> GPIO_AF_OFFSET ) & GPIO_AF_MASK; + + port_ptr = ( hal_ll_gpio_base_handle_t *)hal_ll_gpio_port_base( hal_ll_gpio_port_index ( pin_name ) ); + + hal_ll_gpio_clock_enable( ( uint32_t *)port_ptr ); + + pin_index = hal_ll_gpio_pin_index( pin_name ); + if ( pin_index > 7 ) + { + pin_index -= 8; + if ( state ) { + port_ptr->afrh &= ~( ( uint32_t )( GPIO_AF_MASK ) << ( pin_index * 4 ) ); + port_ptr->afrh |= ( ( uint32_t )( alternate_function ) << ( pin_index * 4 ) ); + } else { + port_ptr->afrh &= ~( ( uint32_t )( alternate_function ) << ( pin_index * 4 ) ); + } + } + else + { + if ( state ) { + port_ptr->afrl &= ~( ( uint32_t )( GPIO_AF_MASK ) << ( pin_index * 4 ) ); + port_ptr->afrl |= ( ( uint32_t )( alternate_function ) << ( pin_index * 4 ) ); + } else { + port_ptr->afrl &= ~( ( uint32_t )( alternate_function ) << ( pin_index * 4 ) ); + } + } + + hal_ll_gpio_config( ( uint32_t*)port_ptr, hal_ll_gpio_pin_mask( pin_name ), module_config ); +} +// ------------------------------------------------------------------------- END + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_82/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_82/CMakeLists.cmake new file mode 100644 index 000000000..018718967 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_82/CMakeLists.cmake @@ -0,0 +1,8 @@ +if(${MCU_NAME} MATCHES "^STM32G431C6$|^STM32G431K6$|^STM32G431R6$|^STM32G431V6$|^STM32G431M6$|^STM32G431C8$|^STM32G431K8$|^STM32G431R8$|^STM32G431V8$|^STM32G431M8$|^STM32G431CB$|^STM32G431KB$|^STM32G431RB$|^STM32G431VB$|^STM32G431MB$") + set(gpio_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_gpio_port.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_82") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_82") + list(APPEND hal_ll_def_list "STM32G4xx") + list(APPEND hal_ll_def_list "STM32G43xx") + list(APPEND hal_ll_def_list "STM32G431xx") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_82/hal_ll_gpio_port.c b/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_82/hal_ll_gpio_port.c new file mode 100644 index 000000000..5966bee00 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_82/hal_ll_gpio_port.c @@ -0,0 +1,390 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_gpio_port.c + * @brief GPIO HAL LOW LEVEL ported layer implementation. + */ + +#include "hal_ll_gpio_port.h" +#include "hal_ll_rcc.h" + +/** + * Defines used in source + */ +#define GPIOA_BASE_ADDR 0x48000000 +#define GPIOB_BASE_ADDR 0x48000400 +#define GPIOC_BASE_ADDR 0x48000800 +#define GPIOD_BASE_ADDR 0x48000C00 +#define GPIOE_BASE_ADDR 0x48001000 +#define GPIOF_BASE_ADDR 0x48001400 +#define GPIOG_BASE_ADDR 0x48001800 + +#define RCC_GPIOCLOCK _RCC_AHB2ENR + +#ifndef GPIOA_BASE_ADDR + #define GPIOA_BASE_ADDR 0 +#endif + +#ifndef GPIOB_BASE_ADDR + #define GPIOB_BASE_ADDR 0 +#endif + +#ifndef GPIOC_BASE_ADDR + #define GPIOC_BASE_ADDR 0 +#endif + +#ifndef GPIOD_BASE_ADDR + #define GPIOD_BASE_ADDR 0 +#endif + +#ifndef GPIOE_BASE_ADDR + #define GPIOE_BASE_ADDR 0 +#endif + +#ifndef GPIOF_BASE_ADDR + #define GPIOF_BASE_ADDR 0 +#endif + +#ifndef GPIOG_BASE_ADDR + #define GPIOG_BASE_ADDR 0 +#endif + +static void hal_ll_gpio_config( uint32_t *port, uint16_t pin_mask, uint32_t config ); + +/*!< @brief GPIO PORT array */ +static const uint32_t _hal_ll_gpio_port_base [ 7 ] = +{ + GPIOA_BASE_ADDR, + GPIOB_BASE_ADDR, + GPIOC_BASE_ADDR, + GPIOD_BASE_ADDR, + GPIOE_BASE_ADDR, + GPIOF_BASE_ADDR, + GPIOG_BASE_ADDR +}; + +/** + * @brief Enable gpio port clock + * @param port - port base address + * @return none + */ +static void _hal_ll_gpio_clock_enable( uint32_t *port ); + +/** + * @brief Configure port pins + * @param port - port base address + * pin_mask - desired pin + * config - pin settings + * @return none + */ +static void _hal_ll_gpio_config( uint32_t *port, uint16_t pin_mask, uint32_t config ); + +/** + * @brief Configure port pins alternate + * functions + * @param module_pin - desired pin + * config - pin settings + * @return none + */ +static void _hal_ll_gpio_config_pin_alternate_enable( uint32_t module_pin, uint32_t module_config, bool state ); + +static uint8_t hal_ll_gpio_pin_index( hal_ll_pin_name_t name ) +{ + return ( uint8_t )name % PORT_SIZE; +} + +uint8_t hal_ll_gpio_port_index( hal_ll_pin_name_t name ) +{ + return ( uint8_t )name / PORT_SIZE; +} + +uint32_t hal_ll_gpio_pin_mask( hal_ll_pin_name_t name ) +{ + return ( ( uint32_t )0x01 << hal_ll_gpio_pin_index( name ) ); +} + +uint32_t hal_ll_gpio_port_base( hal_ll_port_name_t name ) +{ + return _hal_ll_gpio_port_base[ name ]; +} + +void hal_ll_gpio_analog_input( uint32_t *port, uint16_t pin_mask ) +{ + hal_ll_gpio_config( port, pin_mask, GPIO_CFG_ANALOG_INPUT ); +} + +void hal_ll_gpio_digital_input( uint32_t *port, uint16_t pin_mask ) +{ + hal_ll_gpio_config( port, pin_mask, GPIO_CFG_DIGITAL_INPUT ); +} + +void hal_ll_gpio_digital_output( uint32_t *port, uint16_t pin_mask ) +{ + hal_ll_gpio_config( port, pin_mask, GPIO_CFG_DIGITAL_OUTPUT ); +} + +void hal_ll_gpio_module_struct_init( module_struct const *module, bool state ) +{ + int32_t index = 0; + + while ( module->pins[ index ] != GPIO_MODULE_STRUCT_END ) + { + _hal_ll_gpio_config_pin_alternate_enable( module->pins[ index ], module->configs[ index ], state ); + + index++; + } +} + +/** + * @brief Enable gpio port clock + * @param port - port base address + * @return none + */ +static void hal_ll_gpio_clock_enable( uint32_t *port ) +{ + uint32_t pos = 0; + + switch ( ( uint32_t )port & 0xFFFFFC00 ) + { + #ifdef __PORT_A_CN + case GPIOA_BASE_ADDR: pos = 0x01; break; + #endif + #ifdef __PORT_B_CN + case GPIOB_BASE_ADDR: pos = 0x02; break; + #endif + #ifdef __PORT_C_CN + case GPIOC_BASE_ADDR: pos = 0x04; break; + #endif + #ifdef __PORT_D_CN + case GPIOD_BASE_ADDR: pos = 0x08; break; + #endif + #ifdef __PORT_E_CN + case GPIOE_BASE_ADDR: pos = 0x10; break; + #endif + #ifdef __PORT_F_CN + case GPIOF_BASE_ADDR: pos = 0x20; break; + #endif + #ifdef __PORT_G_CN + case GPIOG_BASE_ADDR: pos = 0x40; break; + #endif + } + + *(uint32_t *)RCC_GPIOCLOCK |= pos; +} + +/** + * @brief Configure single port pins + * @param port - port base address + * pin_mask - desired pin + * config - pin settings + * @return none + */ +static void hal_ll_gpio_config( uint32_t *port, uint16_t pin_mask, uint32_t config ) +{ + uint32_t pin_pos = 0; + uint32_t pos = 0; + uint32_t current_pin = 0; + + uint32_t mode = 0; + uint32_t speed = 0; + uint32_t otype = 0; + uint32_t pull = 0; + + hal_ll_gpio_base_handle_t *port_ptr; + + port_ptr = ( hal_ll_gpio_base_handle_t *)port; + + hal_ll_gpio_clock_enable( port ); + + if ( pin_mask == GPIO_PIN_MASK_LOW ) + { + port_ptr->moder &= HAL_LL_NIBBLE_HIGH_32BIT; + + if ( config == GPIO_CFG_DIGITAL_OUTPUT ) + { + port_ptr->moder |= 0x00005555; + port_ptr->otyper &= 0xFFFFFF00; + port_ptr->ospeedr |= HAL_LL_NIBBLE_LOW_32BIT; + return; + } + if ( config == GPIO_CFG_DIGITAL_INPUT ) + { + port_ptr->moder &= HAL_LL_NIBBLE_HIGH_32BIT; + return; + } + } + else if ( pin_mask == GPIO_PIN_MASK_HIGH ) + { + port_ptr->moder &= HAL_LL_NIBBLE_LOW_32BIT; + + if ( config == GPIO_CFG_DIGITAL_OUTPUT ) + { + port_ptr->moder |= 0x55550000; + port_ptr->otyper &= 0xFFFF00FF; + port_ptr->ospeedr |= HAL_LL_NIBBLE_HIGH_32BIT; + return; + } + if ( config == GPIO_CFG_DIGITAL_INPUT ) + { + port_ptr->moder &= HAL_LL_NIBBLE_LOW_32BIT; + return; + } + } + + if ( pin_mask == GPIO_PIN_MASK_ALL ) + { + if ( config == GPIO_CFG_DIGITAL_OUTPUT ) + { + port_ptr->moder = 0x55555555; + port_ptr->otyper = 0; + port_ptr->ospeedr = HAL_LL_NIBBLE_HIGH_32BIT; + return; + } + if ( config == GPIO_CFG_DIGITAL_INPUT ) + { + port_ptr->moder = 0; + return; + } + } + + if ( config & GPIO_CFG_MODE_ANALOG ) + mode = 3; + else if ( config & GPIO_CFG_MODE_ALT_FUNCTION ) + mode = 2; + else if ( config & GPIO_CFG_MODE_OUTPUT ) + mode = 1; + else + mode = 0; + + if ( config & ( GPIO_CFG_SPEED_VERY_HIGH ) ) + speed = 3; + + if ( config & ( GPIO_CFG_SPEED_HIGH ) ) + speed = 2; + + if ( config & ( GPIO_CFG_SPEED_MEDIUM ) ) + speed = 1; + + if ( config & ( GPIO_CFG_SPEED_LOW ) ) + speed = 0; + + if ( config & GPIO_CFG_OTYPE_OD ) + otype = 1; + else + otype = 0; + + if ( config & GPIO_CFG_PULL_DOWN ) + pull = 2; + else if ( config & GPIO_CFG_PULL_UP ) + pull = 1; + else + pull = 0; + + for ( pin_pos = 0x00; pin_pos < 0x10; pin_pos++ ) + { + pos = ( ( uint32_t ) 0x01 ) << pin_pos; + current_pin = pin_mask & pos; + + if ( current_pin == pos ) + { + port_ptr->moder &= ~( ( uint32_t )0x03 << ( pin_pos * 2 ) ); + port_ptr->moder |= ( ( ( uint32_t )mode ) << ( pin_pos * 2 ) ); + + if ( config & ( GPIO_CFG_MODE_OUTPUT | GPIO_CFG_MODE_ALT_FUNCTION ) ) + { + port_ptr->ospeedr &= ~( ( uint32_t )0x03 << ( pin_pos * 2 ) ); + port_ptr->ospeedr |= ( ( uint32_t )( speed ) << ( pin_pos * 2 ) ); + + port_ptr->otyper &= ~( ( uint32_t )0x01 << ( ( uint16_t )pin_pos ) ) ; + port_ptr->otyper |= ( uint16_t )( ( ( uint16_t )otype ) << ( ( uint16_t )pin_pos ) ); + } + + port_ptr->pupdr &= ~( ( uint32_t )0x03 << ( ( uint16_t )pin_pos * 2 ) ); + port_ptr->pupdr |= ( ( ( uint32_t )pull ) << ( pin_pos * 2 ) ); + + } + } +} + +/** + * @brief Configure port pins alternate + * functions + * @param module_pin - desired pin + * config - pin settings + * @return none + */ +static void _hal_ll_gpio_config_pin_alternate_enable( uint32_t module_pin, uint32_t module_config, bool state ) +{ + hal_ll_pin_name_t pin_name; + uint16_t pin_index; + uint32_t alternate_function; + hal_ll_gpio_base_handle_t *port_ptr; + + pin_name = module_pin & GPIO_PIN_NAME_MASK; + + alternate_function = ( module_pin >> GPIO_AF_OFFSET ) & GPIO_AF_MASK; + + port_ptr = ( hal_ll_gpio_base_handle_t *)hal_ll_gpio_port_base( hal_ll_gpio_port_index ( pin_name ) ); + + hal_ll_gpio_clock_enable( ( uint32_t *)port_ptr ); + + pin_index = hal_ll_gpio_pin_index( pin_name ); + if ( pin_index > 7 ) + { + pin_index -= 8; + if ( state ) { + port_ptr->afrh &= ~( ( uint32_t )( GPIO_AF_MASK ) << ( pin_index * 4 ) ); + port_ptr->afrh |= ( ( uint32_t )( alternate_function ) << ( pin_index * 4 ) ); + } else { + port_ptr->afrh &= ~( ( uint32_t )( alternate_function ) << ( pin_index * 4 ) ); + } + } + else + { + if ( state ) { + port_ptr->afrl &= ~( ( uint32_t )( GPIO_AF_MASK ) << ( pin_index * 4 ) ); + port_ptr->afrl |= ( ( uint32_t )( alternate_function ) << ( pin_index * 4 ) ); + } else { + port_ptr->afrl &= ~( ( uint32_t )( alternate_function ) << ( pin_index * 4 ) ); + } + } + + hal_ll_gpio_config( ( uint32_t*)port_ptr, hal_ll_gpio_pin_mask( pin_name ), module_config ); +} +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_83/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_83/CMakeLists.cmake new file mode 100644 index 000000000..fe38f5057 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_83/CMakeLists.cmake @@ -0,0 +1,8 @@ +if(${MCU_NAME} MATCHES "^STM32G441CB$|^STM32G441KB$|^STM32G441RB$|^STM32G441MB$|^STM32G441VB$") + set(gpio_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_gpio_port.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_83") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_83") + list(APPEND hal_ll_def_list "STM32G4xx") + list(APPEND hal_ll_def_list "STM32G44xx") + list(APPEND hal_ll_def_list "STM32G441xx") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_83/hal_ll_gpio_port.c b/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_83/hal_ll_gpio_port.c new file mode 100644 index 000000000..a5ded8222 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_83/hal_ll_gpio_port.c @@ -0,0 +1,477 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_gpio_port.c + * @brief GPIO HAL LOW LEVEL ported layer implementation. + */ + +#include "hal_ll_gpio_port.h" +#include "hal_ll_rcc.h" + +/** + * Defines used in source + */ + + #define GPIOA_BASE_ADDR 0x48000000 + + #define GPIOB_BASE_ADDR 0x48000400 + + #define GPIOC_BASE_ADDR 0x48000800 + + #define GPIOD_BASE_ADDR 0x48000C00 + + #define GPIOE_BASE_ADDR 0x48001000 + + #define GPIOF_BASE_ADDR 0x48001400 + + #define GPIOG_BASE_ADDR 0x48001800 + + #define RCC_GPIOCLOCK _RCC_AHB2ENR + + +#ifdef STM32L4xx + #define RCC_APB1ENR1_PWREN_BIT_MASK (1UL << 28) + #define _PWR_CR2_ADDRESS ( uint32_t * )0x40007004 + #define PWR_CR2_IOSV_BIT_MASK (1U << 9) +#endif + +#ifndef GPIOA_BASE_ADDR + #define GPIOA_BASE_ADDR 0 +#endif + +#ifndef GPIOB_BASE_ADDR + #define GPIOB_BASE_ADDR 0 +#endif + +#ifndef GPIOC_BASE_ADDR + #define GPIOC_BASE_ADDR 0 +#endif + +#ifndef GPIOD_BASE_ADDR + #define GPIOD_BASE_ADDR 0 +#endif + +#ifndef GPIOE_BASE_ADDR + #define GPIOE_BASE_ADDR 0 +#endif + +#ifndef GPIOF_BASE_ADDR + #define GPIOF_BASE_ADDR 0 +#endif + +#ifndef GPIOG_BASE_ADDR + #define GPIOG_BASE_ADDR 0 +#endif + + +static void hal_ll_gpio_config( uint32_t *port, uint16_t pin_mask, uint32_t config ); + +/*!< @brief GPIO PORT array */ +static const uint32_t _hal_ll_gpio_port_base [ 11 ] = +{ + GPIOA_BASE_ADDR, + + GPIOB_BASE_ADDR, + + GPIOC_BASE_ADDR, + + GPIOD_BASE_ADDR, + + GPIOE_BASE_ADDR, + + GPIOF_BASE_ADDR, + + GPIOG_BASE_ADDR, + +}; + +/** + * @brief Enable gpio port clock + * @param port - port base address + * @return none + */ +static void _hal_ll_gpio_clock_enable( uint32_t *port ); + +/** + * @brief Configure port pins + * @param port - port base address + * pin_mask - desired pin + * config - pin settings + * @return none + */ +static void _hal_ll_gpio_config( uint32_t *port, uint16_t pin_mask, uint32_t config ); + +/** + * @brief Configure port pins alternate + * functions + * @param module_pin - desired pin + * config - pin settings + * @return none + */ +static void _hal_ll_gpio_config_pin_alternate_enable( uint32_t module_pin, uint32_t module_config, bool state ); + +static uint8_t hal_ll_gpio_pin_index( hal_ll_pin_name_t name ) +{ + return ( uint8_t )name % PORT_SIZE; +} + +uint8_t hal_ll_gpio_port_index( hal_ll_pin_name_t name ) +{ + return ( uint8_t )name / PORT_SIZE; +} + +uint32_t hal_ll_gpio_pin_mask( hal_ll_pin_name_t name ) +{ + return ( ( uint32_t )0x01 << hal_ll_gpio_pin_index( name ) ); +} + +uint32_t hal_ll_gpio_port_base( hal_ll_port_name_t name ) +{ + return _hal_ll_gpio_port_base[ name ]; +} + +void hal_ll_gpio_analog_input( uint32_t *port, uint16_t pin_mask ) +{ + hal_ll_gpio_config( port, pin_mask, GPIO_CFG_ANALOG_INPUT ); +} + +void hal_ll_gpio_digital_input( uint32_t *port, uint16_t pin_mask ) +{ + hal_ll_gpio_config( port, pin_mask, GPIO_CFG_DIGITAL_INPUT ); +} + +void hal_ll_gpio_digital_output( uint32_t *port, uint16_t pin_mask ) +{ + hal_ll_gpio_config( port, pin_mask, GPIO_CFG_DIGITAL_OUTPUT ); +} + +void hal_ll_gpio_module_struct_init( module_struct const *module, bool state ) +{ + int32_t index = 0; + + + while ( module->pins[ index ] != GPIO_MODULE_STRUCT_END ) + { + _hal_ll_gpio_config_pin_alternate_enable( module->pins[ index ], module->configs[ index ], state ); + + index++; + } +} + +/** + * @brief Enable gpio port clock + * @param port - port base address + * @return none + */ +static void hal_ll_gpio_clock_enable( uint32_t *port ) +{ + uint32_t pos = 0; + + switch ( ( uint32_t )port & 0xFFFFFC00 ) + { + #ifdef __PORT_A_CN + case GPIOA_BASE_ADDR: pos = 0x01; break; + #endif + + #ifdef __PORT_B_CN + case GPIOB_BASE_ADDR: pos = 0x02; break; + #endif + + #ifdef __PORT_C_CN + case GPIOC_BASE_ADDR: pos = 0x04; break; + #endif + + #ifdef __PORT_D_CN + case GPIOD_BASE_ADDR: pos = 0x08; break; + #endif + + #ifdef __PORT_E_CN + case GPIOE_BASE_ADDR: pos = 0x10; break; + #endif + + #ifdef __PORT_F_CN + case GPIOF_BASE_ADDR: pos = 0x20; break; + #endif + + #ifdef __PORT_G_CN + case GPIOG_BASE_ADDR: pos = 0x40; break; + #endif + + } + + #ifdef STM32L4xx + /* + * This bit is used to validate the VDDIO2 supply for electrical and + * logical isolation purpose.Setting this bit is mandatory to use PG[15:2]. + * If VDDIO2 is not always present in the application, the PVM can be used + * to determine whether this supply is ready or not. + * Procedure: + * 1. Enable power interface clock ( page 290 in ref manual ) + * 2. Validate VDDIO2 supply ( page 218 in ref manual ) + * + * Ref. manual + * + */ + *(uint32_t *)_RCC_APB1ENR1 |= RCC_APB1ENR1_PWREN_BIT_MASK; + *(uint32_t *)_PWR_CR2_ADDRESS |= PWR_CR2_IOSV_BIT_MASK; + #endif + + #if defined(STM32F3xx) || defined(STM32F0xx) + *(uint32_t *)RCC_GPIOCLOCK |= ( uint32_t )pos << GPIO_AHB_SHIFT; + #else + *(uint32_t *)RCC_GPIOCLOCK |= pos; + #endif +} + +/** + * @brief Configure single port pins + * @param port - port base address + * pin_mask - desired pin + * config - pin settings + * @return none + */ +static void hal_ll_gpio_config( uint32_t *port, uint16_t pin_mask, uint32_t config ) +{ + uint32_t pin_pos = 0; + uint32_t pos = 0; + uint32_t current_pin = 0; + + uint32_t mode = 0; + uint32_t speed = 0; + uint32_t otype = 0; + uint32_t pull = 0; + + hal_ll_gpio_base_handle_t *port_ptr; + + port_ptr = ( hal_ll_gpio_base_handle_t *)port; + + hal_ll_gpio_clock_enable( port ); + + if ( pin_mask == GPIO_PIN_MASK_LOW ) + { + port_ptr->moder &= HAL_LL_NIBBLE_HIGH_32BIT; + + + + if ( config == GPIO_CFG_DIGITAL_OUTPUT ) + { + port_ptr->moder |= 0x00005555; + + port_ptr->otyper &= 0xFFFFFF00; + + port_ptr->ospeedr |= HAL_LL_NIBBLE_LOW_32BIT; + + + return; + } + if ( config == GPIO_CFG_DIGITAL_INPUT ) + { + port_ptr->moder &= HAL_LL_NIBBLE_HIGH_32BIT; + + + return; + } + } + else if ( pin_mask == GPIO_PIN_MASK_HIGH ) + { + port_ptr->moder &= HAL_LL_NIBBLE_LOW_32BIT; + + + + if ( config == GPIO_CFG_DIGITAL_OUTPUT ) + { + port_ptr->moder |= 0x55550000; + + port_ptr->otyper &= 0xFFFF00FF; + + port_ptr->ospeedr |= HAL_LL_NIBBLE_HIGH_32BIT; + + + return; + } + if ( config == GPIO_CFG_DIGITAL_INPUT ) + { + port_ptr->moder &= HAL_LL_NIBBLE_LOW_32BIT; + + + return; + } + } + + if ( pin_mask == GPIO_PIN_MASK_ALL ) + { + if ( config == GPIO_CFG_DIGITAL_OUTPUT ) + { + port_ptr->moder = 0x55555555; + + port_ptr->otyper = 0; + + port_ptr->ospeedr = HAL_LL_NIBBLE_HIGH_32BIT; + + + return; + } + if ( config == GPIO_CFG_DIGITAL_INPUT ) + { + port_ptr->moder = 0; + + + return; + } + } + + if ( config & GPIO_CFG_MODE_ANALOG ) + mode = 3; + else if ( config & GPIO_CFG_MODE_ALT_FUNCTION ) + mode = 2; + else if ( config & GPIO_CFG_MODE_OUTPUT ) + mode = 1; + else + mode = 0; + + #if defined(STM32F411xx) || defined(STM32F412xx) || defined(STM32F413xx) || \ + defined(STM32F423xx) || defined(STM32F446xx) || defined(STM32F3xx) + if ( config & ( GPIO_CFG_SPEED_HIGH | GPIO_CFG_SPEED_MAX ) ) + speed = 3; + #endif + if ( config & ( GPIO_CFG_SPEED_VERY_HIGH ) ) + speed = 3; + + if ( config & ( GPIO_CFG_SPEED_HIGH ) ) + speed = 2; + + if ( config & ( GPIO_CFG_SPEED_MEDIUM ) ) + speed = 1; + + if ( config & ( GPIO_CFG_SPEED_LOW ) ) + speed = 0; + + + + if ( config & GPIO_CFG_OTYPE_OD ) + otype = 1; + + else + otype = 0; + + + if ( config & GPIO_CFG_PULL_DOWN ) + pull = 2; + + else if ( config & GPIO_CFG_PULL_UP ) + pull = 1; + + else + pull = 0; + + + for ( pin_pos = 0x00; pin_pos < 0x10; pin_pos++ ) + { + pos = ( ( uint32_t ) 0x01 ) << pin_pos; + current_pin = pin_mask & pos; + + if ( current_pin == pos ) + { + port_ptr->moder &= ~( ( uint32_t )0x03 << ( pin_pos * 2 ) ); + port_ptr->moder |= ( ( ( uint32_t )mode ) << ( pin_pos * 2 ) ); + + if ( config & ( GPIO_CFG_MODE_OUTPUT | GPIO_CFG_MODE_ALT_FUNCTION ) ) + { + port_ptr->ospeedr &= ~( ( uint32_t )0x03 << ( pin_pos * 2 ) ); + port_ptr->ospeedr |= ( ( uint32_t )( speed ) << ( pin_pos * 2 ) ); + + port_ptr->otyper &= ~( ( uint32_t )0x01 << ( ( uint16_t )pin_pos ) ) ; + port_ptr->otyper |= ( uint16_t )( ( ( uint16_t )otype ) << ( ( uint16_t )pin_pos ) ); + } + + port_ptr->pupdr &= ~( ( uint32_t )0x03 << ( ( uint16_t )pin_pos * 2 ) ); + port_ptr->pupdr |= ( ( ( uint32_t )pull ) << ( pin_pos * 2 ) ); + } + } + + +} + +/** + * @brief Configure port pins alternate + * functions + * @param module_pin - desired pin + * config - pin settings + * @return none + */ +static void _hal_ll_gpio_config_pin_alternate_enable( uint32_t module_pin, uint32_t module_config, bool state ) +{ + hal_ll_pin_name_t pin_name; + uint16_t pin_index; + uint32_t alternate_function; + hal_ll_gpio_base_handle_t *port_ptr; + + pin_name = module_pin & GPIO_PIN_NAME_MASK; + + alternate_function = ( module_pin >> GPIO_AF_OFFSET ) & GPIO_AF_MASK; + + port_ptr = ( hal_ll_gpio_base_handle_t *)hal_ll_gpio_port_base( hal_ll_gpio_port_index ( pin_name ) ); + + hal_ll_gpio_clock_enable( ( uint32_t *)port_ptr ); + + pin_index = hal_ll_gpio_pin_index( pin_name ); + if ( pin_index > 7 ) + { + pin_index -= 8; + if ( state ) { + port_ptr->afrh &= ~( ( uint32_t )( GPIO_AF_MASK ) << ( pin_index * 4 ) ); + port_ptr->afrh |= ( ( uint32_t )( alternate_function ) << ( pin_index * 4 ) ); + } else { + port_ptr->afrh &= ~( ( uint32_t )( alternate_function ) << ( pin_index * 4 ) ); + } + } + else + { + if ( state ) { + port_ptr->afrl &= ~( ( uint32_t )( GPIO_AF_MASK ) << ( pin_index * 4 ) ); + port_ptr->afrl |= ( ( uint32_t )( alternate_function ) << ( pin_index * 4 ) ); + } else { + port_ptr->afrl &= ~( ( uint32_t )( alternate_function ) << ( pin_index * 4 ) ); + } + } + + hal_ll_gpio_config( ( uint32_t*)port_ptr, hal_ll_gpio_pin_mask( pin_name ), module_config ); +} +// ------------------------------------------------------------------------- END + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_84/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_84/CMakeLists.cmake new file mode 100644 index 000000000..2c5904e80 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_84/CMakeLists.cmake @@ -0,0 +1,8 @@ +if(${MCU_NAME} MATCHES "^STM32G473CB$|^STM32G473MB$|^STM32G473PB$|^STM32G473RB$|^STM32G473VB$|^STM32G473QB$|^STM32G473CC$|^STM32G473MC$|^STM32G473PC$|^STM32G473RC$|^STM32G473VC$|^STM32G473QC$|^STM32G473CE$|^STM32G473ME$|^STM32G473PE$|^STM32G473RE$|^STM32G473VE$|^STM32G473QE$") + set(gpio_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_gpio_port.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_84") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_84") + list(APPEND hal_ll_def_list "STM32G4xx") + list(APPEND hal_ll_def_list "STM32G47xx") + list(APPEND hal_ll_def_list "STM32G473xx") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_84/hal_ll_gpio_port.c b/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_84/hal_ll_gpio_port.c new file mode 100644 index 000000000..a5ded8222 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_84/hal_ll_gpio_port.c @@ -0,0 +1,477 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_gpio_port.c + * @brief GPIO HAL LOW LEVEL ported layer implementation. + */ + +#include "hal_ll_gpio_port.h" +#include "hal_ll_rcc.h" + +/** + * Defines used in source + */ + + #define GPIOA_BASE_ADDR 0x48000000 + + #define GPIOB_BASE_ADDR 0x48000400 + + #define GPIOC_BASE_ADDR 0x48000800 + + #define GPIOD_BASE_ADDR 0x48000C00 + + #define GPIOE_BASE_ADDR 0x48001000 + + #define GPIOF_BASE_ADDR 0x48001400 + + #define GPIOG_BASE_ADDR 0x48001800 + + #define RCC_GPIOCLOCK _RCC_AHB2ENR + + +#ifdef STM32L4xx + #define RCC_APB1ENR1_PWREN_BIT_MASK (1UL << 28) + #define _PWR_CR2_ADDRESS ( uint32_t * )0x40007004 + #define PWR_CR2_IOSV_BIT_MASK (1U << 9) +#endif + +#ifndef GPIOA_BASE_ADDR + #define GPIOA_BASE_ADDR 0 +#endif + +#ifndef GPIOB_BASE_ADDR + #define GPIOB_BASE_ADDR 0 +#endif + +#ifndef GPIOC_BASE_ADDR + #define GPIOC_BASE_ADDR 0 +#endif + +#ifndef GPIOD_BASE_ADDR + #define GPIOD_BASE_ADDR 0 +#endif + +#ifndef GPIOE_BASE_ADDR + #define GPIOE_BASE_ADDR 0 +#endif + +#ifndef GPIOF_BASE_ADDR + #define GPIOF_BASE_ADDR 0 +#endif + +#ifndef GPIOG_BASE_ADDR + #define GPIOG_BASE_ADDR 0 +#endif + + +static void hal_ll_gpio_config( uint32_t *port, uint16_t pin_mask, uint32_t config ); + +/*!< @brief GPIO PORT array */ +static const uint32_t _hal_ll_gpio_port_base [ 11 ] = +{ + GPIOA_BASE_ADDR, + + GPIOB_BASE_ADDR, + + GPIOC_BASE_ADDR, + + GPIOD_BASE_ADDR, + + GPIOE_BASE_ADDR, + + GPIOF_BASE_ADDR, + + GPIOG_BASE_ADDR, + +}; + +/** + * @brief Enable gpio port clock + * @param port - port base address + * @return none + */ +static void _hal_ll_gpio_clock_enable( uint32_t *port ); + +/** + * @brief Configure port pins + * @param port - port base address + * pin_mask - desired pin + * config - pin settings + * @return none + */ +static void _hal_ll_gpio_config( uint32_t *port, uint16_t pin_mask, uint32_t config ); + +/** + * @brief Configure port pins alternate + * functions + * @param module_pin - desired pin + * config - pin settings + * @return none + */ +static void _hal_ll_gpio_config_pin_alternate_enable( uint32_t module_pin, uint32_t module_config, bool state ); + +static uint8_t hal_ll_gpio_pin_index( hal_ll_pin_name_t name ) +{ + return ( uint8_t )name % PORT_SIZE; +} + +uint8_t hal_ll_gpio_port_index( hal_ll_pin_name_t name ) +{ + return ( uint8_t )name / PORT_SIZE; +} + +uint32_t hal_ll_gpio_pin_mask( hal_ll_pin_name_t name ) +{ + return ( ( uint32_t )0x01 << hal_ll_gpio_pin_index( name ) ); +} + +uint32_t hal_ll_gpio_port_base( hal_ll_port_name_t name ) +{ + return _hal_ll_gpio_port_base[ name ]; +} + +void hal_ll_gpio_analog_input( uint32_t *port, uint16_t pin_mask ) +{ + hal_ll_gpio_config( port, pin_mask, GPIO_CFG_ANALOG_INPUT ); +} + +void hal_ll_gpio_digital_input( uint32_t *port, uint16_t pin_mask ) +{ + hal_ll_gpio_config( port, pin_mask, GPIO_CFG_DIGITAL_INPUT ); +} + +void hal_ll_gpio_digital_output( uint32_t *port, uint16_t pin_mask ) +{ + hal_ll_gpio_config( port, pin_mask, GPIO_CFG_DIGITAL_OUTPUT ); +} + +void hal_ll_gpio_module_struct_init( module_struct const *module, bool state ) +{ + int32_t index = 0; + + + while ( module->pins[ index ] != GPIO_MODULE_STRUCT_END ) + { + _hal_ll_gpio_config_pin_alternate_enable( module->pins[ index ], module->configs[ index ], state ); + + index++; + } +} + +/** + * @brief Enable gpio port clock + * @param port - port base address + * @return none + */ +static void hal_ll_gpio_clock_enable( uint32_t *port ) +{ + uint32_t pos = 0; + + switch ( ( uint32_t )port & 0xFFFFFC00 ) + { + #ifdef __PORT_A_CN + case GPIOA_BASE_ADDR: pos = 0x01; break; + #endif + + #ifdef __PORT_B_CN + case GPIOB_BASE_ADDR: pos = 0x02; break; + #endif + + #ifdef __PORT_C_CN + case GPIOC_BASE_ADDR: pos = 0x04; break; + #endif + + #ifdef __PORT_D_CN + case GPIOD_BASE_ADDR: pos = 0x08; break; + #endif + + #ifdef __PORT_E_CN + case GPIOE_BASE_ADDR: pos = 0x10; break; + #endif + + #ifdef __PORT_F_CN + case GPIOF_BASE_ADDR: pos = 0x20; break; + #endif + + #ifdef __PORT_G_CN + case GPIOG_BASE_ADDR: pos = 0x40; break; + #endif + + } + + #ifdef STM32L4xx + /* + * This bit is used to validate the VDDIO2 supply for electrical and + * logical isolation purpose.Setting this bit is mandatory to use PG[15:2]. + * If VDDIO2 is not always present in the application, the PVM can be used + * to determine whether this supply is ready or not. + * Procedure: + * 1. Enable power interface clock ( page 290 in ref manual ) + * 2. Validate VDDIO2 supply ( page 218 in ref manual ) + * + * Ref. manual + * + */ + *(uint32_t *)_RCC_APB1ENR1 |= RCC_APB1ENR1_PWREN_BIT_MASK; + *(uint32_t *)_PWR_CR2_ADDRESS |= PWR_CR2_IOSV_BIT_MASK; + #endif + + #if defined(STM32F3xx) || defined(STM32F0xx) + *(uint32_t *)RCC_GPIOCLOCK |= ( uint32_t )pos << GPIO_AHB_SHIFT; + #else + *(uint32_t *)RCC_GPIOCLOCK |= pos; + #endif +} + +/** + * @brief Configure single port pins + * @param port - port base address + * pin_mask - desired pin + * config - pin settings + * @return none + */ +static void hal_ll_gpio_config( uint32_t *port, uint16_t pin_mask, uint32_t config ) +{ + uint32_t pin_pos = 0; + uint32_t pos = 0; + uint32_t current_pin = 0; + + uint32_t mode = 0; + uint32_t speed = 0; + uint32_t otype = 0; + uint32_t pull = 0; + + hal_ll_gpio_base_handle_t *port_ptr; + + port_ptr = ( hal_ll_gpio_base_handle_t *)port; + + hal_ll_gpio_clock_enable( port ); + + if ( pin_mask == GPIO_PIN_MASK_LOW ) + { + port_ptr->moder &= HAL_LL_NIBBLE_HIGH_32BIT; + + + + if ( config == GPIO_CFG_DIGITAL_OUTPUT ) + { + port_ptr->moder |= 0x00005555; + + port_ptr->otyper &= 0xFFFFFF00; + + port_ptr->ospeedr |= HAL_LL_NIBBLE_LOW_32BIT; + + + return; + } + if ( config == GPIO_CFG_DIGITAL_INPUT ) + { + port_ptr->moder &= HAL_LL_NIBBLE_HIGH_32BIT; + + + return; + } + } + else if ( pin_mask == GPIO_PIN_MASK_HIGH ) + { + port_ptr->moder &= HAL_LL_NIBBLE_LOW_32BIT; + + + + if ( config == GPIO_CFG_DIGITAL_OUTPUT ) + { + port_ptr->moder |= 0x55550000; + + port_ptr->otyper &= 0xFFFF00FF; + + port_ptr->ospeedr |= HAL_LL_NIBBLE_HIGH_32BIT; + + + return; + } + if ( config == GPIO_CFG_DIGITAL_INPUT ) + { + port_ptr->moder &= HAL_LL_NIBBLE_LOW_32BIT; + + + return; + } + } + + if ( pin_mask == GPIO_PIN_MASK_ALL ) + { + if ( config == GPIO_CFG_DIGITAL_OUTPUT ) + { + port_ptr->moder = 0x55555555; + + port_ptr->otyper = 0; + + port_ptr->ospeedr = HAL_LL_NIBBLE_HIGH_32BIT; + + + return; + } + if ( config == GPIO_CFG_DIGITAL_INPUT ) + { + port_ptr->moder = 0; + + + return; + } + } + + if ( config & GPIO_CFG_MODE_ANALOG ) + mode = 3; + else if ( config & GPIO_CFG_MODE_ALT_FUNCTION ) + mode = 2; + else if ( config & GPIO_CFG_MODE_OUTPUT ) + mode = 1; + else + mode = 0; + + #if defined(STM32F411xx) || defined(STM32F412xx) || defined(STM32F413xx) || \ + defined(STM32F423xx) || defined(STM32F446xx) || defined(STM32F3xx) + if ( config & ( GPIO_CFG_SPEED_HIGH | GPIO_CFG_SPEED_MAX ) ) + speed = 3; + #endif + if ( config & ( GPIO_CFG_SPEED_VERY_HIGH ) ) + speed = 3; + + if ( config & ( GPIO_CFG_SPEED_HIGH ) ) + speed = 2; + + if ( config & ( GPIO_CFG_SPEED_MEDIUM ) ) + speed = 1; + + if ( config & ( GPIO_CFG_SPEED_LOW ) ) + speed = 0; + + + + if ( config & GPIO_CFG_OTYPE_OD ) + otype = 1; + + else + otype = 0; + + + if ( config & GPIO_CFG_PULL_DOWN ) + pull = 2; + + else if ( config & GPIO_CFG_PULL_UP ) + pull = 1; + + else + pull = 0; + + + for ( pin_pos = 0x00; pin_pos < 0x10; pin_pos++ ) + { + pos = ( ( uint32_t ) 0x01 ) << pin_pos; + current_pin = pin_mask & pos; + + if ( current_pin == pos ) + { + port_ptr->moder &= ~( ( uint32_t )0x03 << ( pin_pos * 2 ) ); + port_ptr->moder |= ( ( ( uint32_t )mode ) << ( pin_pos * 2 ) ); + + if ( config & ( GPIO_CFG_MODE_OUTPUT | GPIO_CFG_MODE_ALT_FUNCTION ) ) + { + port_ptr->ospeedr &= ~( ( uint32_t )0x03 << ( pin_pos * 2 ) ); + port_ptr->ospeedr |= ( ( uint32_t )( speed ) << ( pin_pos * 2 ) ); + + port_ptr->otyper &= ~( ( uint32_t )0x01 << ( ( uint16_t )pin_pos ) ) ; + port_ptr->otyper |= ( uint16_t )( ( ( uint16_t )otype ) << ( ( uint16_t )pin_pos ) ); + } + + port_ptr->pupdr &= ~( ( uint32_t )0x03 << ( ( uint16_t )pin_pos * 2 ) ); + port_ptr->pupdr |= ( ( ( uint32_t )pull ) << ( pin_pos * 2 ) ); + } + } + + +} + +/** + * @brief Configure port pins alternate + * functions + * @param module_pin - desired pin + * config - pin settings + * @return none + */ +static void _hal_ll_gpio_config_pin_alternate_enable( uint32_t module_pin, uint32_t module_config, bool state ) +{ + hal_ll_pin_name_t pin_name; + uint16_t pin_index; + uint32_t alternate_function; + hal_ll_gpio_base_handle_t *port_ptr; + + pin_name = module_pin & GPIO_PIN_NAME_MASK; + + alternate_function = ( module_pin >> GPIO_AF_OFFSET ) & GPIO_AF_MASK; + + port_ptr = ( hal_ll_gpio_base_handle_t *)hal_ll_gpio_port_base( hal_ll_gpio_port_index ( pin_name ) ); + + hal_ll_gpio_clock_enable( ( uint32_t *)port_ptr ); + + pin_index = hal_ll_gpio_pin_index( pin_name ); + if ( pin_index > 7 ) + { + pin_index -= 8; + if ( state ) { + port_ptr->afrh &= ~( ( uint32_t )( GPIO_AF_MASK ) << ( pin_index * 4 ) ); + port_ptr->afrh |= ( ( uint32_t )( alternate_function ) << ( pin_index * 4 ) ); + } else { + port_ptr->afrh &= ~( ( uint32_t )( alternate_function ) << ( pin_index * 4 ) ); + } + } + else + { + if ( state ) { + port_ptr->afrl &= ~( ( uint32_t )( GPIO_AF_MASK ) << ( pin_index * 4 ) ); + port_ptr->afrl |= ( ( uint32_t )( alternate_function ) << ( pin_index * 4 ) ); + } else { + port_ptr->afrl &= ~( ( uint32_t )( alternate_function ) << ( pin_index * 4 ) ); + } + } + + hal_ll_gpio_config( ( uint32_t*)port_ptr, hal_ll_gpio_pin_mask( pin_name ), module_config ); +} +// ------------------------------------------------------------------------- END + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_85/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_85/CMakeLists.cmake new file mode 100644 index 000000000..2d536e317 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_85/CMakeLists.cmake @@ -0,0 +1,8 @@ +if(${MCU_NAME} MATCHES "^STM32G474CB$|^STM32G474MB$|^STM32G474RB$|^STM32G474VB$|^STM32G474QB$|^STM32G474PB$|^STM32G474CC$|^STM32G474MC$|^STM32G474RC$|^STM32G474VC$|^STM32G474QC$|^STM32G474PC$|^STM32G474CE$|^STM32G474ME$|^STM32G474RE$|^STM32G474VE$|^STM32G474QE$|^STM32G474PE$") + set(gpio_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_gpio_port.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_85") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_85") + list(APPEND hal_ll_def_list "STM32G4xx") + list(APPEND hal_ll_def_list "STM32G47xx") + list(APPEND hal_ll_def_list "STM32G474xx") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_85/hal_ll_gpio_port.c b/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_85/hal_ll_gpio_port.c new file mode 100644 index 000000000..a5ded8222 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_85/hal_ll_gpio_port.c @@ -0,0 +1,477 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_gpio_port.c + * @brief GPIO HAL LOW LEVEL ported layer implementation. + */ + +#include "hal_ll_gpio_port.h" +#include "hal_ll_rcc.h" + +/** + * Defines used in source + */ + + #define GPIOA_BASE_ADDR 0x48000000 + + #define GPIOB_BASE_ADDR 0x48000400 + + #define GPIOC_BASE_ADDR 0x48000800 + + #define GPIOD_BASE_ADDR 0x48000C00 + + #define GPIOE_BASE_ADDR 0x48001000 + + #define GPIOF_BASE_ADDR 0x48001400 + + #define GPIOG_BASE_ADDR 0x48001800 + + #define RCC_GPIOCLOCK _RCC_AHB2ENR + + +#ifdef STM32L4xx + #define RCC_APB1ENR1_PWREN_BIT_MASK (1UL << 28) + #define _PWR_CR2_ADDRESS ( uint32_t * )0x40007004 + #define PWR_CR2_IOSV_BIT_MASK (1U << 9) +#endif + +#ifndef GPIOA_BASE_ADDR + #define GPIOA_BASE_ADDR 0 +#endif + +#ifndef GPIOB_BASE_ADDR + #define GPIOB_BASE_ADDR 0 +#endif + +#ifndef GPIOC_BASE_ADDR + #define GPIOC_BASE_ADDR 0 +#endif + +#ifndef GPIOD_BASE_ADDR + #define GPIOD_BASE_ADDR 0 +#endif + +#ifndef GPIOE_BASE_ADDR + #define GPIOE_BASE_ADDR 0 +#endif + +#ifndef GPIOF_BASE_ADDR + #define GPIOF_BASE_ADDR 0 +#endif + +#ifndef GPIOG_BASE_ADDR + #define GPIOG_BASE_ADDR 0 +#endif + + +static void hal_ll_gpio_config( uint32_t *port, uint16_t pin_mask, uint32_t config ); + +/*!< @brief GPIO PORT array */ +static const uint32_t _hal_ll_gpio_port_base [ 11 ] = +{ + GPIOA_BASE_ADDR, + + GPIOB_BASE_ADDR, + + GPIOC_BASE_ADDR, + + GPIOD_BASE_ADDR, + + GPIOE_BASE_ADDR, + + GPIOF_BASE_ADDR, + + GPIOG_BASE_ADDR, + +}; + +/** + * @brief Enable gpio port clock + * @param port - port base address + * @return none + */ +static void _hal_ll_gpio_clock_enable( uint32_t *port ); + +/** + * @brief Configure port pins + * @param port - port base address + * pin_mask - desired pin + * config - pin settings + * @return none + */ +static void _hal_ll_gpio_config( uint32_t *port, uint16_t pin_mask, uint32_t config ); + +/** + * @brief Configure port pins alternate + * functions + * @param module_pin - desired pin + * config - pin settings + * @return none + */ +static void _hal_ll_gpio_config_pin_alternate_enable( uint32_t module_pin, uint32_t module_config, bool state ); + +static uint8_t hal_ll_gpio_pin_index( hal_ll_pin_name_t name ) +{ + return ( uint8_t )name % PORT_SIZE; +} + +uint8_t hal_ll_gpio_port_index( hal_ll_pin_name_t name ) +{ + return ( uint8_t )name / PORT_SIZE; +} + +uint32_t hal_ll_gpio_pin_mask( hal_ll_pin_name_t name ) +{ + return ( ( uint32_t )0x01 << hal_ll_gpio_pin_index( name ) ); +} + +uint32_t hal_ll_gpio_port_base( hal_ll_port_name_t name ) +{ + return _hal_ll_gpio_port_base[ name ]; +} + +void hal_ll_gpio_analog_input( uint32_t *port, uint16_t pin_mask ) +{ + hal_ll_gpio_config( port, pin_mask, GPIO_CFG_ANALOG_INPUT ); +} + +void hal_ll_gpio_digital_input( uint32_t *port, uint16_t pin_mask ) +{ + hal_ll_gpio_config( port, pin_mask, GPIO_CFG_DIGITAL_INPUT ); +} + +void hal_ll_gpio_digital_output( uint32_t *port, uint16_t pin_mask ) +{ + hal_ll_gpio_config( port, pin_mask, GPIO_CFG_DIGITAL_OUTPUT ); +} + +void hal_ll_gpio_module_struct_init( module_struct const *module, bool state ) +{ + int32_t index = 0; + + + while ( module->pins[ index ] != GPIO_MODULE_STRUCT_END ) + { + _hal_ll_gpio_config_pin_alternate_enable( module->pins[ index ], module->configs[ index ], state ); + + index++; + } +} + +/** + * @brief Enable gpio port clock + * @param port - port base address + * @return none + */ +static void hal_ll_gpio_clock_enable( uint32_t *port ) +{ + uint32_t pos = 0; + + switch ( ( uint32_t )port & 0xFFFFFC00 ) + { + #ifdef __PORT_A_CN + case GPIOA_BASE_ADDR: pos = 0x01; break; + #endif + + #ifdef __PORT_B_CN + case GPIOB_BASE_ADDR: pos = 0x02; break; + #endif + + #ifdef __PORT_C_CN + case GPIOC_BASE_ADDR: pos = 0x04; break; + #endif + + #ifdef __PORT_D_CN + case GPIOD_BASE_ADDR: pos = 0x08; break; + #endif + + #ifdef __PORT_E_CN + case GPIOE_BASE_ADDR: pos = 0x10; break; + #endif + + #ifdef __PORT_F_CN + case GPIOF_BASE_ADDR: pos = 0x20; break; + #endif + + #ifdef __PORT_G_CN + case GPIOG_BASE_ADDR: pos = 0x40; break; + #endif + + } + + #ifdef STM32L4xx + /* + * This bit is used to validate the VDDIO2 supply for electrical and + * logical isolation purpose.Setting this bit is mandatory to use PG[15:2]. + * If VDDIO2 is not always present in the application, the PVM can be used + * to determine whether this supply is ready or not. + * Procedure: + * 1. Enable power interface clock ( page 290 in ref manual ) + * 2. Validate VDDIO2 supply ( page 218 in ref manual ) + * + * Ref. manual + * + */ + *(uint32_t *)_RCC_APB1ENR1 |= RCC_APB1ENR1_PWREN_BIT_MASK; + *(uint32_t *)_PWR_CR2_ADDRESS |= PWR_CR2_IOSV_BIT_MASK; + #endif + + #if defined(STM32F3xx) || defined(STM32F0xx) + *(uint32_t *)RCC_GPIOCLOCK |= ( uint32_t )pos << GPIO_AHB_SHIFT; + #else + *(uint32_t *)RCC_GPIOCLOCK |= pos; + #endif +} + +/** + * @brief Configure single port pins + * @param port - port base address + * pin_mask - desired pin + * config - pin settings + * @return none + */ +static void hal_ll_gpio_config( uint32_t *port, uint16_t pin_mask, uint32_t config ) +{ + uint32_t pin_pos = 0; + uint32_t pos = 0; + uint32_t current_pin = 0; + + uint32_t mode = 0; + uint32_t speed = 0; + uint32_t otype = 0; + uint32_t pull = 0; + + hal_ll_gpio_base_handle_t *port_ptr; + + port_ptr = ( hal_ll_gpio_base_handle_t *)port; + + hal_ll_gpio_clock_enable( port ); + + if ( pin_mask == GPIO_PIN_MASK_LOW ) + { + port_ptr->moder &= HAL_LL_NIBBLE_HIGH_32BIT; + + + + if ( config == GPIO_CFG_DIGITAL_OUTPUT ) + { + port_ptr->moder |= 0x00005555; + + port_ptr->otyper &= 0xFFFFFF00; + + port_ptr->ospeedr |= HAL_LL_NIBBLE_LOW_32BIT; + + + return; + } + if ( config == GPIO_CFG_DIGITAL_INPUT ) + { + port_ptr->moder &= HAL_LL_NIBBLE_HIGH_32BIT; + + + return; + } + } + else if ( pin_mask == GPIO_PIN_MASK_HIGH ) + { + port_ptr->moder &= HAL_LL_NIBBLE_LOW_32BIT; + + + + if ( config == GPIO_CFG_DIGITAL_OUTPUT ) + { + port_ptr->moder |= 0x55550000; + + port_ptr->otyper &= 0xFFFF00FF; + + port_ptr->ospeedr |= HAL_LL_NIBBLE_HIGH_32BIT; + + + return; + } + if ( config == GPIO_CFG_DIGITAL_INPUT ) + { + port_ptr->moder &= HAL_LL_NIBBLE_LOW_32BIT; + + + return; + } + } + + if ( pin_mask == GPIO_PIN_MASK_ALL ) + { + if ( config == GPIO_CFG_DIGITAL_OUTPUT ) + { + port_ptr->moder = 0x55555555; + + port_ptr->otyper = 0; + + port_ptr->ospeedr = HAL_LL_NIBBLE_HIGH_32BIT; + + + return; + } + if ( config == GPIO_CFG_DIGITAL_INPUT ) + { + port_ptr->moder = 0; + + + return; + } + } + + if ( config & GPIO_CFG_MODE_ANALOG ) + mode = 3; + else if ( config & GPIO_CFG_MODE_ALT_FUNCTION ) + mode = 2; + else if ( config & GPIO_CFG_MODE_OUTPUT ) + mode = 1; + else + mode = 0; + + #if defined(STM32F411xx) || defined(STM32F412xx) || defined(STM32F413xx) || \ + defined(STM32F423xx) || defined(STM32F446xx) || defined(STM32F3xx) + if ( config & ( GPIO_CFG_SPEED_HIGH | GPIO_CFG_SPEED_MAX ) ) + speed = 3; + #endif + if ( config & ( GPIO_CFG_SPEED_VERY_HIGH ) ) + speed = 3; + + if ( config & ( GPIO_CFG_SPEED_HIGH ) ) + speed = 2; + + if ( config & ( GPIO_CFG_SPEED_MEDIUM ) ) + speed = 1; + + if ( config & ( GPIO_CFG_SPEED_LOW ) ) + speed = 0; + + + + if ( config & GPIO_CFG_OTYPE_OD ) + otype = 1; + + else + otype = 0; + + + if ( config & GPIO_CFG_PULL_DOWN ) + pull = 2; + + else if ( config & GPIO_CFG_PULL_UP ) + pull = 1; + + else + pull = 0; + + + for ( pin_pos = 0x00; pin_pos < 0x10; pin_pos++ ) + { + pos = ( ( uint32_t ) 0x01 ) << pin_pos; + current_pin = pin_mask & pos; + + if ( current_pin == pos ) + { + port_ptr->moder &= ~( ( uint32_t )0x03 << ( pin_pos * 2 ) ); + port_ptr->moder |= ( ( ( uint32_t )mode ) << ( pin_pos * 2 ) ); + + if ( config & ( GPIO_CFG_MODE_OUTPUT | GPIO_CFG_MODE_ALT_FUNCTION ) ) + { + port_ptr->ospeedr &= ~( ( uint32_t )0x03 << ( pin_pos * 2 ) ); + port_ptr->ospeedr |= ( ( uint32_t )( speed ) << ( pin_pos * 2 ) ); + + port_ptr->otyper &= ~( ( uint32_t )0x01 << ( ( uint16_t )pin_pos ) ) ; + port_ptr->otyper |= ( uint16_t )( ( ( uint16_t )otype ) << ( ( uint16_t )pin_pos ) ); + } + + port_ptr->pupdr &= ~( ( uint32_t )0x03 << ( ( uint16_t )pin_pos * 2 ) ); + port_ptr->pupdr |= ( ( ( uint32_t )pull ) << ( pin_pos * 2 ) ); + } + } + + +} + +/** + * @brief Configure port pins alternate + * functions + * @param module_pin - desired pin + * config - pin settings + * @return none + */ +static void _hal_ll_gpio_config_pin_alternate_enable( uint32_t module_pin, uint32_t module_config, bool state ) +{ + hal_ll_pin_name_t pin_name; + uint16_t pin_index; + uint32_t alternate_function; + hal_ll_gpio_base_handle_t *port_ptr; + + pin_name = module_pin & GPIO_PIN_NAME_MASK; + + alternate_function = ( module_pin >> GPIO_AF_OFFSET ) & GPIO_AF_MASK; + + port_ptr = ( hal_ll_gpio_base_handle_t *)hal_ll_gpio_port_base( hal_ll_gpio_port_index ( pin_name ) ); + + hal_ll_gpio_clock_enable( ( uint32_t *)port_ptr ); + + pin_index = hal_ll_gpio_pin_index( pin_name ); + if ( pin_index > 7 ) + { + pin_index -= 8; + if ( state ) { + port_ptr->afrh &= ~( ( uint32_t )( GPIO_AF_MASK ) << ( pin_index * 4 ) ); + port_ptr->afrh |= ( ( uint32_t )( alternate_function ) << ( pin_index * 4 ) ); + } else { + port_ptr->afrh &= ~( ( uint32_t )( alternate_function ) << ( pin_index * 4 ) ); + } + } + else + { + if ( state ) { + port_ptr->afrl &= ~( ( uint32_t )( GPIO_AF_MASK ) << ( pin_index * 4 ) ); + port_ptr->afrl |= ( ( uint32_t )( alternate_function ) << ( pin_index * 4 ) ); + } else { + port_ptr->afrl &= ~( ( uint32_t )( alternate_function ) << ( pin_index * 4 ) ); + } + } + + hal_ll_gpio_config( ( uint32_t*)port_ptr, hal_ll_gpio_pin_mask( pin_name ), module_config ); +} +// ------------------------------------------------------------------------- END + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_86/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_86/CMakeLists.cmake new file mode 100644 index 000000000..f71cf6080 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_86/CMakeLists.cmake @@ -0,0 +1,8 @@ +if(${MCU_NAME} MATCHES "^STM32G483CE$|^STM32G483RE$|^STM32G483ME$|^STM32G483PE$|^STM32G483VE$|^STM32G483QE$") + set(gpio_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_gpio_port.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_86") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_86") + list(APPEND hal_ll_def_list "STM32G4xx") + list(APPEND hal_ll_def_list "STM32G48xx") + list(APPEND hal_ll_def_list "STM32G483xx") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_86/hal_ll_gpio_port.c b/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_86/hal_ll_gpio_port.c new file mode 100644 index 000000000..a5ded8222 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_86/hal_ll_gpio_port.c @@ -0,0 +1,477 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_gpio_port.c + * @brief GPIO HAL LOW LEVEL ported layer implementation. + */ + +#include "hal_ll_gpio_port.h" +#include "hal_ll_rcc.h" + +/** + * Defines used in source + */ + + #define GPIOA_BASE_ADDR 0x48000000 + + #define GPIOB_BASE_ADDR 0x48000400 + + #define GPIOC_BASE_ADDR 0x48000800 + + #define GPIOD_BASE_ADDR 0x48000C00 + + #define GPIOE_BASE_ADDR 0x48001000 + + #define GPIOF_BASE_ADDR 0x48001400 + + #define GPIOG_BASE_ADDR 0x48001800 + + #define RCC_GPIOCLOCK _RCC_AHB2ENR + + +#ifdef STM32L4xx + #define RCC_APB1ENR1_PWREN_BIT_MASK (1UL << 28) + #define _PWR_CR2_ADDRESS ( uint32_t * )0x40007004 + #define PWR_CR2_IOSV_BIT_MASK (1U << 9) +#endif + +#ifndef GPIOA_BASE_ADDR + #define GPIOA_BASE_ADDR 0 +#endif + +#ifndef GPIOB_BASE_ADDR + #define GPIOB_BASE_ADDR 0 +#endif + +#ifndef GPIOC_BASE_ADDR + #define GPIOC_BASE_ADDR 0 +#endif + +#ifndef GPIOD_BASE_ADDR + #define GPIOD_BASE_ADDR 0 +#endif + +#ifndef GPIOE_BASE_ADDR + #define GPIOE_BASE_ADDR 0 +#endif + +#ifndef GPIOF_BASE_ADDR + #define GPIOF_BASE_ADDR 0 +#endif + +#ifndef GPIOG_BASE_ADDR + #define GPIOG_BASE_ADDR 0 +#endif + + +static void hal_ll_gpio_config( uint32_t *port, uint16_t pin_mask, uint32_t config ); + +/*!< @brief GPIO PORT array */ +static const uint32_t _hal_ll_gpio_port_base [ 11 ] = +{ + GPIOA_BASE_ADDR, + + GPIOB_BASE_ADDR, + + GPIOC_BASE_ADDR, + + GPIOD_BASE_ADDR, + + GPIOE_BASE_ADDR, + + GPIOF_BASE_ADDR, + + GPIOG_BASE_ADDR, + +}; + +/** + * @brief Enable gpio port clock + * @param port - port base address + * @return none + */ +static void _hal_ll_gpio_clock_enable( uint32_t *port ); + +/** + * @brief Configure port pins + * @param port - port base address + * pin_mask - desired pin + * config - pin settings + * @return none + */ +static void _hal_ll_gpio_config( uint32_t *port, uint16_t pin_mask, uint32_t config ); + +/** + * @brief Configure port pins alternate + * functions + * @param module_pin - desired pin + * config - pin settings + * @return none + */ +static void _hal_ll_gpio_config_pin_alternate_enable( uint32_t module_pin, uint32_t module_config, bool state ); + +static uint8_t hal_ll_gpio_pin_index( hal_ll_pin_name_t name ) +{ + return ( uint8_t )name % PORT_SIZE; +} + +uint8_t hal_ll_gpio_port_index( hal_ll_pin_name_t name ) +{ + return ( uint8_t )name / PORT_SIZE; +} + +uint32_t hal_ll_gpio_pin_mask( hal_ll_pin_name_t name ) +{ + return ( ( uint32_t )0x01 << hal_ll_gpio_pin_index( name ) ); +} + +uint32_t hal_ll_gpio_port_base( hal_ll_port_name_t name ) +{ + return _hal_ll_gpio_port_base[ name ]; +} + +void hal_ll_gpio_analog_input( uint32_t *port, uint16_t pin_mask ) +{ + hal_ll_gpio_config( port, pin_mask, GPIO_CFG_ANALOG_INPUT ); +} + +void hal_ll_gpio_digital_input( uint32_t *port, uint16_t pin_mask ) +{ + hal_ll_gpio_config( port, pin_mask, GPIO_CFG_DIGITAL_INPUT ); +} + +void hal_ll_gpio_digital_output( uint32_t *port, uint16_t pin_mask ) +{ + hal_ll_gpio_config( port, pin_mask, GPIO_CFG_DIGITAL_OUTPUT ); +} + +void hal_ll_gpio_module_struct_init( module_struct const *module, bool state ) +{ + int32_t index = 0; + + + while ( module->pins[ index ] != GPIO_MODULE_STRUCT_END ) + { + _hal_ll_gpio_config_pin_alternate_enable( module->pins[ index ], module->configs[ index ], state ); + + index++; + } +} + +/** + * @brief Enable gpio port clock + * @param port - port base address + * @return none + */ +static void hal_ll_gpio_clock_enable( uint32_t *port ) +{ + uint32_t pos = 0; + + switch ( ( uint32_t )port & 0xFFFFFC00 ) + { + #ifdef __PORT_A_CN + case GPIOA_BASE_ADDR: pos = 0x01; break; + #endif + + #ifdef __PORT_B_CN + case GPIOB_BASE_ADDR: pos = 0x02; break; + #endif + + #ifdef __PORT_C_CN + case GPIOC_BASE_ADDR: pos = 0x04; break; + #endif + + #ifdef __PORT_D_CN + case GPIOD_BASE_ADDR: pos = 0x08; break; + #endif + + #ifdef __PORT_E_CN + case GPIOE_BASE_ADDR: pos = 0x10; break; + #endif + + #ifdef __PORT_F_CN + case GPIOF_BASE_ADDR: pos = 0x20; break; + #endif + + #ifdef __PORT_G_CN + case GPIOG_BASE_ADDR: pos = 0x40; break; + #endif + + } + + #ifdef STM32L4xx + /* + * This bit is used to validate the VDDIO2 supply for electrical and + * logical isolation purpose.Setting this bit is mandatory to use PG[15:2]. + * If VDDIO2 is not always present in the application, the PVM can be used + * to determine whether this supply is ready or not. + * Procedure: + * 1. Enable power interface clock ( page 290 in ref manual ) + * 2. Validate VDDIO2 supply ( page 218 in ref manual ) + * + * Ref. manual + * + */ + *(uint32_t *)_RCC_APB1ENR1 |= RCC_APB1ENR1_PWREN_BIT_MASK; + *(uint32_t *)_PWR_CR2_ADDRESS |= PWR_CR2_IOSV_BIT_MASK; + #endif + + #if defined(STM32F3xx) || defined(STM32F0xx) + *(uint32_t *)RCC_GPIOCLOCK |= ( uint32_t )pos << GPIO_AHB_SHIFT; + #else + *(uint32_t *)RCC_GPIOCLOCK |= pos; + #endif +} + +/** + * @brief Configure single port pins + * @param port - port base address + * pin_mask - desired pin + * config - pin settings + * @return none + */ +static void hal_ll_gpio_config( uint32_t *port, uint16_t pin_mask, uint32_t config ) +{ + uint32_t pin_pos = 0; + uint32_t pos = 0; + uint32_t current_pin = 0; + + uint32_t mode = 0; + uint32_t speed = 0; + uint32_t otype = 0; + uint32_t pull = 0; + + hal_ll_gpio_base_handle_t *port_ptr; + + port_ptr = ( hal_ll_gpio_base_handle_t *)port; + + hal_ll_gpio_clock_enable( port ); + + if ( pin_mask == GPIO_PIN_MASK_LOW ) + { + port_ptr->moder &= HAL_LL_NIBBLE_HIGH_32BIT; + + + + if ( config == GPIO_CFG_DIGITAL_OUTPUT ) + { + port_ptr->moder |= 0x00005555; + + port_ptr->otyper &= 0xFFFFFF00; + + port_ptr->ospeedr |= HAL_LL_NIBBLE_LOW_32BIT; + + + return; + } + if ( config == GPIO_CFG_DIGITAL_INPUT ) + { + port_ptr->moder &= HAL_LL_NIBBLE_HIGH_32BIT; + + + return; + } + } + else if ( pin_mask == GPIO_PIN_MASK_HIGH ) + { + port_ptr->moder &= HAL_LL_NIBBLE_LOW_32BIT; + + + + if ( config == GPIO_CFG_DIGITAL_OUTPUT ) + { + port_ptr->moder |= 0x55550000; + + port_ptr->otyper &= 0xFFFF00FF; + + port_ptr->ospeedr |= HAL_LL_NIBBLE_HIGH_32BIT; + + + return; + } + if ( config == GPIO_CFG_DIGITAL_INPUT ) + { + port_ptr->moder &= HAL_LL_NIBBLE_LOW_32BIT; + + + return; + } + } + + if ( pin_mask == GPIO_PIN_MASK_ALL ) + { + if ( config == GPIO_CFG_DIGITAL_OUTPUT ) + { + port_ptr->moder = 0x55555555; + + port_ptr->otyper = 0; + + port_ptr->ospeedr = HAL_LL_NIBBLE_HIGH_32BIT; + + + return; + } + if ( config == GPIO_CFG_DIGITAL_INPUT ) + { + port_ptr->moder = 0; + + + return; + } + } + + if ( config & GPIO_CFG_MODE_ANALOG ) + mode = 3; + else if ( config & GPIO_CFG_MODE_ALT_FUNCTION ) + mode = 2; + else if ( config & GPIO_CFG_MODE_OUTPUT ) + mode = 1; + else + mode = 0; + + #if defined(STM32F411xx) || defined(STM32F412xx) || defined(STM32F413xx) || \ + defined(STM32F423xx) || defined(STM32F446xx) || defined(STM32F3xx) + if ( config & ( GPIO_CFG_SPEED_HIGH | GPIO_CFG_SPEED_MAX ) ) + speed = 3; + #endif + if ( config & ( GPIO_CFG_SPEED_VERY_HIGH ) ) + speed = 3; + + if ( config & ( GPIO_CFG_SPEED_HIGH ) ) + speed = 2; + + if ( config & ( GPIO_CFG_SPEED_MEDIUM ) ) + speed = 1; + + if ( config & ( GPIO_CFG_SPEED_LOW ) ) + speed = 0; + + + + if ( config & GPIO_CFG_OTYPE_OD ) + otype = 1; + + else + otype = 0; + + + if ( config & GPIO_CFG_PULL_DOWN ) + pull = 2; + + else if ( config & GPIO_CFG_PULL_UP ) + pull = 1; + + else + pull = 0; + + + for ( pin_pos = 0x00; pin_pos < 0x10; pin_pos++ ) + { + pos = ( ( uint32_t ) 0x01 ) << pin_pos; + current_pin = pin_mask & pos; + + if ( current_pin == pos ) + { + port_ptr->moder &= ~( ( uint32_t )0x03 << ( pin_pos * 2 ) ); + port_ptr->moder |= ( ( ( uint32_t )mode ) << ( pin_pos * 2 ) ); + + if ( config & ( GPIO_CFG_MODE_OUTPUT | GPIO_CFG_MODE_ALT_FUNCTION ) ) + { + port_ptr->ospeedr &= ~( ( uint32_t )0x03 << ( pin_pos * 2 ) ); + port_ptr->ospeedr |= ( ( uint32_t )( speed ) << ( pin_pos * 2 ) ); + + port_ptr->otyper &= ~( ( uint32_t )0x01 << ( ( uint16_t )pin_pos ) ) ; + port_ptr->otyper |= ( uint16_t )( ( ( uint16_t )otype ) << ( ( uint16_t )pin_pos ) ); + } + + port_ptr->pupdr &= ~( ( uint32_t )0x03 << ( ( uint16_t )pin_pos * 2 ) ); + port_ptr->pupdr |= ( ( ( uint32_t )pull ) << ( pin_pos * 2 ) ); + } + } + + +} + +/** + * @brief Configure port pins alternate + * functions + * @param module_pin - desired pin + * config - pin settings + * @return none + */ +static void _hal_ll_gpio_config_pin_alternate_enable( uint32_t module_pin, uint32_t module_config, bool state ) +{ + hal_ll_pin_name_t pin_name; + uint16_t pin_index; + uint32_t alternate_function; + hal_ll_gpio_base_handle_t *port_ptr; + + pin_name = module_pin & GPIO_PIN_NAME_MASK; + + alternate_function = ( module_pin >> GPIO_AF_OFFSET ) & GPIO_AF_MASK; + + port_ptr = ( hal_ll_gpio_base_handle_t *)hal_ll_gpio_port_base( hal_ll_gpio_port_index ( pin_name ) ); + + hal_ll_gpio_clock_enable( ( uint32_t *)port_ptr ); + + pin_index = hal_ll_gpio_pin_index( pin_name ); + if ( pin_index > 7 ) + { + pin_index -= 8; + if ( state ) { + port_ptr->afrh &= ~( ( uint32_t )( GPIO_AF_MASK ) << ( pin_index * 4 ) ); + port_ptr->afrh |= ( ( uint32_t )( alternate_function ) << ( pin_index * 4 ) ); + } else { + port_ptr->afrh &= ~( ( uint32_t )( alternate_function ) << ( pin_index * 4 ) ); + } + } + else + { + if ( state ) { + port_ptr->afrl &= ~( ( uint32_t )( GPIO_AF_MASK ) << ( pin_index * 4 ) ); + port_ptr->afrl |= ( ( uint32_t )( alternate_function ) << ( pin_index * 4 ) ); + } else { + port_ptr->afrl &= ~( ( uint32_t )( alternate_function ) << ( pin_index * 4 ) ); + } + } + + hal_ll_gpio_config( ( uint32_t*)port_ptr, hal_ll_gpio_pin_mask( pin_name ), module_config ); +} +// ------------------------------------------------------------------------- END + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_87/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_87/CMakeLists.cmake new file mode 100644 index 000000000..957352884 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_87/CMakeLists.cmake @@ -0,0 +1,8 @@ +if(${MCU_NAME} MATCHES "^STM32G484CE$|^STM32G484ME$|^STM32G484PE$|^STM32G484RE$|^STM32G484QE$|^STM32G484VE$") + set(gpio_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_gpio_port.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_87") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_87") + list(APPEND hal_ll_def_list "STM32G4xx") + list(APPEND hal_ll_def_list "STM32G48xx") + list(APPEND hal_ll_def_list "STM32G484xx") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_87/hal_ll_gpio_port.c b/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_87/hal_ll_gpio_port.c new file mode 100644 index 000000000..a5ded8222 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_87/hal_ll_gpio_port.c @@ -0,0 +1,477 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_gpio_port.c + * @brief GPIO HAL LOW LEVEL ported layer implementation. + */ + +#include "hal_ll_gpio_port.h" +#include "hal_ll_rcc.h" + +/** + * Defines used in source + */ + + #define GPIOA_BASE_ADDR 0x48000000 + + #define GPIOB_BASE_ADDR 0x48000400 + + #define GPIOC_BASE_ADDR 0x48000800 + + #define GPIOD_BASE_ADDR 0x48000C00 + + #define GPIOE_BASE_ADDR 0x48001000 + + #define GPIOF_BASE_ADDR 0x48001400 + + #define GPIOG_BASE_ADDR 0x48001800 + + #define RCC_GPIOCLOCK _RCC_AHB2ENR + + +#ifdef STM32L4xx + #define RCC_APB1ENR1_PWREN_BIT_MASK (1UL << 28) + #define _PWR_CR2_ADDRESS ( uint32_t * )0x40007004 + #define PWR_CR2_IOSV_BIT_MASK (1U << 9) +#endif + +#ifndef GPIOA_BASE_ADDR + #define GPIOA_BASE_ADDR 0 +#endif + +#ifndef GPIOB_BASE_ADDR + #define GPIOB_BASE_ADDR 0 +#endif + +#ifndef GPIOC_BASE_ADDR + #define GPIOC_BASE_ADDR 0 +#endif + +#ifndef GPIOD_BASE_ADDR + #define GPIOD_BASE_ADDR 0 +#endif + +#ifndef GPIOE_BASE_ADDR + #define GPIOE_BASE_ADDR 0 +#endif + +#ifndef GPIOF_BASE_ADDR + #define GPIOF_BASE_ADDR 0 +#endif + +#ifndef GPIOG_BASE_ADDR + #define GPIOG_BASE_ADDR 0 +#endif + + +static void hal_ll_gpio_config( uint32_t *port, uint16_t pin_mask, uint32_t config ); + +/*!< @brief GPIO PORT array */ +static const uint32_t _hal_ll_gpio_port_base [ 11 ] = +{ + GPIOA_BASE_ADDR, + + GPIOB_BASE_ADDR, + + GPIOC_BASE_ADDR, + + GPIOD_BASE_ADDR, + + GPIOE_BASE_ADDR, + + GPIOF_BASE_ADDR, + + GPIOG_BASE_ADDR, + +}; + +/** + * @brief Enable gpio port clock + * @param port - port base address + * @return none + */ +static void _hal_ll_gpio_clock_enable( uint32_t *port ); + +/** + * @brief Configure port pins + * @param port - port base address + * pin_mask - desired pin + * config - pin settings + * @return none + */ +static void _hal_ll_gpio_config( uint32_t *port, uint16_t pin_mask, uint32_t config ); + +/** + * @brief Configure port pins alternate + * functions + * @param module_pin - desired pin + * config - pin settings + * @return none + */ +static void _hal_ll_gpio_config_pin_alternate_enable( uint32_t module_pin, uint32_t module_config, bool state ); + +static uint8_t hal_ll_gpio_pin_index( hal_ll_pin_name_t name ) +{ + return ( uint8_t )name % PORT_SIZE; +} + +uint8_t hal_ll_gpio_port_index( hal_ll_pin_name_t name ) +{ + return ( uint8_t )name / PORT_SIZE; +} + +uint32_t hal_ll_gpio_pin_mask( hal_ll_pin_name_t name ) +{ + return ( ( uint32_t )0x01 << hal_ll_gpio_pin_index( name ) ); +} + +uint32_t hal_ll_gpio_port_base( hal_ll_port_name_t name ) +{ + return _hal_ll_gpio_port_base[ name ]; +} + +void hal_ll_gpio_analog_input( uint32_t *port, uint16_t pin_mask ) +{ + hal_ll_gpio_config( port, pin_mask, GPIO_CFG_ANALOG_INPUT ); +} + +void hal_ll_gpio_digital_input( uint32_t *port, uint16_t pin_mask ) +{ + hal_ll_gpio_config( port, pin_mask, GPIO_CFG_DIGITAL_INPUT ); +} + +void hal_ll_gpio_digital_output( uint32_t *port, uint16_t pin_mask ) +{ + hal_ll_gpio_config( port, pin_mask, GPIO_CFG_DIGITAL_OUTPUT ); +} + +void hal_ll_gpio_module_struct_init( module_struct const *module, bool state ) +{ + int32_t index = 0; + + + while ( module->pins[ index ] != GPIO_MODULE_STRUCT_END ) + { + _hal_ll_gpio_config_pin_alternate_enable( module->pins[ index ], module->configs[ index ], state ); + + index++; + } +} + +/** + * @brief Enable gpio port clock + * @param port - port base address + * @return none + */ +static void hal_ll_gpio_clock_enable( uint32_t *port ) +{ + uint32_t pos = 0; + + switch ( ( uint32_t )port & 0xFFFFFC00 ) + { + #ifdef __PORT_A_CN + case GPIOA_BASE_ADDR: pos = 0x01; break; + #endif + + #ifdef __PORT_B_CN + case GPIOB_BASE_ADDR: pos = 0x02; break; + #endif + + #ifdef __PORT_C_CN + case GPIOC_BASE_ADDR: pos = 0x04; break; + #endif + + #ifdef __PORT_D_CN + case GPIOD_BASE_ADDR: pos = 0x08; break; + #endif + + #ifdef __PORT_E_CN + case GPIOE_BASE_ADDR: pos = 0x10; break; + #endif + + #ifdef __PORT_F_CN + case GPIOF_BASE_ADDR: pos = 0x20; break; + #endif + + #ifdef __PORT_G_CN + case GPIOG_BASE_ADDR: pos = 0x40; break; + #endif + + } + + #ifdef STM32L4xx + /* + * This bit is used to validate the VDDIO2 supply for electrical and + * logical isolation purpose.Setting this bit is mandatory to use PG[15:2]. + * If VDDIO2 is not always present in the application, the PVM can be used + * to determine whether this supply is ready or not. + * Procedure: + * 1. Enable power interface clock ( page 290 in ref manual ) + * 2. Validate VDDIO2 supply ( page 218 in ref manual ) + * + * Ref. manual + * + */ + *(uint32_t *)_RCC_APB1ENR1 |= RCC_APB1ENR1_PWREN_BIT_MASK; + *(uint32_t *)_PWR_CR2_ADDRESS |= PWR_CR2_IOSV_BIT_MASK; + #endif + + #if defined(STM32F3xx) || defined(STM32F0xx) + *(uint32_t *)RCC_GPIOCLOCK |= ( uint32_t )pos << GPIO_AHB_SHIFT; + #else + *(uint32_t *)RCC_GPIOCLOCK |= pos; + #endif +} + +/** + * @brief Configure single port pins + * @param port - port base address + * pin_mask - desired pin + * config - pin settings + * @return none + */ +static void hal_ll_gpio_config( uint32_t *port, uint16_t pin_mask, uint32_t config ) +{ + uint32_t pin_pos = 0; + uint32_t pos = 0; + uint32_t current_pin = 0; + + uint32_t mode = 0; + uint32_t speed = 0; + uint32_t otype = 0; + uint32_t pull = 0; + + hal_ll_gpio_base_handle_t *port_ptr; + + port_ptr = ( hal_ll_gpio_base_handle_t *)port; + + hal_ll_gpio_clock_enable( port ); + + if ( pin_mask == GPIO_PIN_MASK_LOW ) + { + port_ptr->moder &= HAL_LL_NIBBLE_HIGH_32BIT; + + + + if ( config == GPIO_CFG_DIGITAL_OUTPUT ) + { + port_ptr->moder |= 0x00005555; + + port_ptr->otyper &= 0xFFFFFF00; + + port_ptr->ospeedr |= HAL_LL_NIBBLE_LOW_32BIT; + + + return; + } + if ( config == GPIO_CFG_DIGITAL_INPUT ) + { + port_ptr->moder &= HAL_LL_NIBBLE_HIGH_32BIT; + + + return; + } + } + else if ( pin_mask == GPIO_PIN_MASK_HIGH ) + { + port_ptr->moder &= HAL_LL_NIBBLE_LOW_32BIT; + + + + if ( config == GPIO_CFG_DIGITAL_OUTPUT ) + { + port_ptr->moder |= 0x55550000; + + port_ptr->otyper &= 0xFFFF00FF; + + port_ptr->ospeedr |= HAL_LL_NIBBLE_HIGH_32BIT; + + + return; + } + if ( config == GPIO_CFG_DIGITAL_INPUT ) + { + port_ptr->moder &= HAL_LL_NIBBLE_LOW_32BIT; + + + return; + } + } + + if ( pin_mask == GPIO_PIN_MASK_ALL ) + { + if ( config == GPIO_CFG_DIGITAL_OUTPUT ) + { + port_ptr->moder = 0x55555555; + + port_ptr->otyper = 0; + + port_ptr->ospeedr = HAL_LL_NIBBLE_HIGH_32BIT; + + + return; + } + if ( config == GPIO_CFG_DIGITAL_INPUT ) + { + port_ptr->moder = 0; + + + return; + } + } + + if ( config & GPIO_CFG_MODE_ANALOG ) + mode = 3; + else if ( config & GPIO_CFG_MODE_ALT_FUNCTION ) + mode = 2; + else if ( config & GPIO_CFG_MODE_OUTPUT ) + mode = 1; + else + mode = 0; + + #if defined(STM32F411xx) || defined(STM32F412xx) || defined(STM32F413xx) || \ + defined(STM32F423xx) || defined(STM32F446xx) || defined(STM32F3xx) + if ( config & ( GPIO_CFG_SPEED_HIGH | GPIO_CFG_SPEED_MAX ) ) + speed = 3; + #endif + if ( config & ( GPIO_CFG_SPEED_VERY_HIGH ) ) + speed = 3; + + if ( config & ( GPIO_CFG_SPEED_HIGH ) ) + speed = 2; + + if ( config & ( GPIO_CFG_SPEED_MEDIUM ) ) + speed = 1; + + if ( config & ( GPIO_CFG_SPEED_LOW ) ) + speed = 0; + + + + if ( config & GPIO_CFG_OTYPE_OD ) + otype = 1; + + else + otype = 0; + + + if ( config & GPIO_CFG_PULL_DOWN ) + pull = 2; + + else if ( config & GPIO_CFG_PULL_UP ) + pull = 1; + + else + pull = 0; + + + for ( pin_pos = 0x00; pin_pos < 0x10; pin_pos++ ) + { + pos = ( ( uint32_t ) 0x01 ) << pin_pos; + current_pin = pin_mask & pos; + + if ( current_pin == pos ) + { + port_ptr->moder &= ~( ( uint32_t )0x03 << ( pin_pos * 2 ) ); + port_ptr->moder |= ( ( ( uint32_t )mode ) << ( pin_pos * 2 ) ); + + if ( config & ( GPIO_CFG_MODE_OUTPUT | GPIO_CFG_MODE_ALT_FUNCTION ) ) + { + port_ptr->ospeedr &= ~( ( uint32_t )0x03 << ( pin_pos * 2 ) ); + port_ptr->ospeedr |= ( ( uint32_t )( speed ) << ( pin_pos * 2 ) ); + + port_ptr->otyper &= ~( ( uint32_t )0x01 << ( ( uint16_t )pin_pos ) ) ; + port_ptr->otyper |= ( uint16_t )( ( ( uint16_t )otype ) << ( ( uint16_t )pin_pos ) ); + } + + port_ptr->pupdr &= ~( ( uint32_t )0x03 << ( ( uint16_t )pin_pos * 2 ) ); + port_ptr->pupdr |= ( ( ( uint32_t )pull ) << ( pin_pos * 2 ) ); + } + } + + +} + +/** + * @brief Configure port pins alternate + * functions + * @param module_pin - desired pin + * config - pin settings + * @return none + */ +static void _hal_ll_gpio_config_pin_alternate_enable( uint32_t module_pin, uint32_t module_config, bool state ) +{ + hal_ll_pin_name_t pin_name; + uint16_t pin_index; + uint32_t alternate_function; + hal_ll_gpio_base_handle_t *port_ptr; + + pin_name = module_pin & GPIO_PIN_NAME_MASK; + + alternate_function = ( module_pin >> GPIO_AF_OFFSET ) & GPIO_AF_MASK; + + port_ptr = ( hal_ll_gpio_base_handle_t *)hal_ll_gpio_port_base( hal_ll_gpio_port_index ( pin_name ) ); + + hal_ll_gpio_clock_enable( ( uint32_t *)port_ptr ); + + pin_index = hal_ll_gpio_pin_index( pin_name ); + if ( pin_index > 7 ) + { + pin_index -= 8; + if ( state ) { + port_ptr->afrh &= ~( ( uint32_t )( GPIO_AF_MASK ) << ( pin_index * 4 ) ); + port_ptr->afrh |= ( ( uint32_t )( alternate_function ) << ( pin_index * 4 ) ); + } else { + port_ptr->afrh &= ~( ( uint32_t )( alternate_function ) << ( pin_index * 4 ) ); + } + } + else + { + if ( state ) { + port_ptr->afrl &= ~( ( uint32_t )( GPIO_AF_MASK ) << ( pin_index * 4 ) ); + port_ptr->afrl |= ( ( uint32_t )( alternate_function ) << ( pin_index * 4 ) ); + } else { + port_ptr->afrl &= ~( ( uint32_t )( alternate_function ) << ( pin_index * 4 ) ); + } + } + + hal_ll_gpio_config( ( uint32_t*)port_ptr, hal_ll_gpio_pin_mask( pin_name ), module_config ); +} +// ------------------------------------------------------------------------- END + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_88/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_88/CMakeLists.cmake new file mode 100644 index 000000000..b4bf635f7 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_88/CMakeLists.cmake @@ -0,0 +1,8 @@ +if(${MCU_NAME} MATCHES "^STM32G491CC$|^STM32G491KC$|^STM32G491RC$|^STM32G491VC$|^STM32G491MC$|^STM32G491CE$|^STM32G491KE$|^STM32G491RE$|^STM32G491VE$|^STM32G491ME$") + set(gpio_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_gpio_port.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_88") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_88") + list(APPEND hal_ll_def_list "STM32G4xx") + list(APPEND hal_ll_def_list "STM32G49xx") + list(APPEND hal_ll_def_list "STM32G491xx") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_88/hal_ll_gpio_port.c b/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_88/hal_ll_gpio_port.c new file mode 100644 index 000000000..a5ded8222 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_88/hal_ll_gpio_port.c @@ -0,0 +1,477 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_gpio_port.c + * @brief GPIO HAL LOW LEVEL ported layer implementation. + */ + +#include "hal_ll_gpio_port.h" +#include "hal_ll_rcc.h" + +/** + * Defines used in source + */ + + #define GPIOA_BASE_ADDR 0x48000000 + + #define GPIOB_BASE_ADDR 0x48000400 + + #define GPIOC_BASE_ADDR 0x48000800 + + #define GPIOD_BASE_ADDR 0x48000C00 + + #define GPIOE_BASE_ADDR 0x48001000 + + #define GPIOF_BASE_ADDR 0x48001400 + + #define GPIOG_BASE_ADDR 0x48001800 + + #define RCC_GPIOCLOCK _RCC_AHB2ENR + + +#ifdef STM32L4xx + #define RCC_APB1ENR1_PWREN_BIT_MASK (1UL << 28) + #define _PWR_CR2_ADDRESS ( uint32_t * )0x40007004 + #define PWR_CR2_IOSV_BIT_MASK (1U << 9) +#endif + +#ifndef GPIOA_BASE_ADDR + #define GPIOA_BASE_ADDR 0 +#endif + +#ifndef GPIOB_BASE_ADDR + #define GPIOB_BASE_ADDR 0 +#endif + +#ifndef GPIOC_BASE_ADDR + #define GPIOC_BASE_ADDR 0 +#endif + +#ifndef GPIOD_BASE_ADDR + #define GPIOD_BASE_ADDR 0 +#endif + +#ifndef GPIOE_BASE_ADDR + #define GPIOE_BASE_ADDR 0 +#endif + +#ifndef GPIOF_BASE_ADDR + #define GPIOF_BASE_ADDR 0 +#endif + +#ifndef GPIOG_BASE_ADDR + #define GPIOG_BASE_ADDR 0 +#endif + + +static void hal_ll_gpio_config( uint32_t *port, uint16_t pin_mask, uint32_t config ); + +/*!< @brief GPIO PORT array */ +static const uint32_t _hal_ll_gpio_port_base [ 11 ] = +{ + GPIOA_BASE_ADDR, + + GPIOB_BASE_ADDR, + + GPIOC_BASE_ADDR, + + GPIOD_BASE_ADDR, + + GPIOE_BASE_ADDR, + + GPIOF_BASE_ADDR, + + GPIOG_BASE_ADDR, + +}; + +/** + * @brief Enable gpio port clock + * @param port - port base address + * @return none + */ +static void _hal_ll_gpio_clock_enable( uint32_t *port ); + +/** + * @brief Configure port pins + * @param port - port base address + * pin_mask - desired pin + * config - pin settings + * @return none + */ +static void _hal_ll_gpio_config( uint32_t *port, uint16_t pin_mask, uint32_t config ); + +/** + * @brief Configure port pins alternate + * functions + * @param module_pin - desired pin + * config - pin settings + * @return none + */ +static void _hal_ll_gpio_config_pin_alternate_enable( uint32_t module_pin, uint32_t module_config, bool state ); + +static uint8_t hal_ll_gpio_pin_index( hal_ll_pin_name_t name ) +{ + return ( uint8_t )name % PORT_SIZE; +} + +uint8_t hal_ll_gpio_port_index( hal_ll_pin_name_t name ) +{ + return ( uint8_t )name / PORT_SIZE; +} + +uint32_t hal_ll_gpio_pin_mask( hal_ll_pin_name_t name ) +{ + return ( ( uint32_t )0x01 << hal_ll_gpio_pin_index( name ) ); +} + +uint32_t hal_ll_gpio_port_base( hal_ll_port_name_t name ) +{ + return _hal_ll_gpio_port_base[ name ]; +} + +void hal_ll_gpio_analog_input( uint32_t *port, uint16_t pin_mask ) +{ + hal_ll_gpio_config( port, pin_mask, GPIO_CFG_ANALOG_INPUT ); +} + +void hal_ll_gpio_digital_input( uint32_t *port, uint16_t pin_mask ) +{ + hal_ll_gpio_config( port, pin_mask, GPIO_CFG_DIGITAL_INPUT ); +} + +void hal_ll_gpio_digital_output( uint32_t *port, uint16_t pin_mask ) +{ + hal_ll_gpio_config( port, pin_mask, GPIO_CFG_DIGITAL_OUTPUT ); +} + +void hal_ll_gpio_module_struct_init( module_struct const *module, bool state ) +{ + int32_t index = 0; + + + while ( module->pins[ index ] != GPIO_MODULE_STRUCT_END ) + { + _hal_ll_gpio_config_pin_alternate_enable( module->pins[ index ], module->configs[ index ], state ); + + index++; + } +} + +/** + * @brief Enable gpio port clock + * @param port - port base address + * @return none + */ +static void hal_ll_gpio_clock_enable( uint32_t *port ) +{ + uint32_t pos = 0; + + switch ( ( uint32_t )port & 0xFFFFFC00 ) + { + #ifdef __PORT_A_CN + case GPIOA_BASE_ADDR: pos = 0x01; break; + #endif + + #ifdef __PORT_B_CN + case GPIOB_BASE_ADDR: pos = 0x02; break; + #endif + + #ifdef __PORT_C_CN + case GPIOC_BASE_ADDR: pos = 0x04; break; + #endif + + #ifdef __PORT_D_CN + case GPIOD_BASE_ADDR: pos = 0x08; break; + #endif + + #ifdef __PORT_E_CN + case GPIOE_BASE_ADDR: pos = 0x10; break; + #endif + + #ifdef __PORT_F_CN + case GPIOF_BASE_ADDR: pos = 0x20; break; + #endif + + #ifdef __PORT_G_CN + case GPIOG_BASE_ADDR: pos = 0x40; break; + #endif + + } + + #ifdef STM32L4xx + /* + * This bit is used to validate the VDDIO2 supply for electrical and + * logical isolation purpose.Setting this bit is mandatory to use PG[15:2]. + * If VDDIO2 is not always present in the application, the PVM can be used + * to determine whether this supply is ready or not. + * Procedure: + * 1. Enable power interface clock ( page 290 in ref manual ) + * 2. Validate VDDIO2 supply ( page 218 in ref manual ) + * + * Ref. manual + * + */ + *(uint32_t *)_RCC_APB1ENR1 |= RCC_APB1ENR1_PWREN_BIT_MASK; + *(uint32_t *)_PWR_CR2_ADDRESS |= PWR_CR2_IOSV_BIT_MASK; + #endif + + #if defined(STM32F3xx) || defined(STM32F0xx) + *(uint32_t *)RCC_GPIOCLOCK |= ( uint32_t )pos << GPIO_AHB_SHIFT; + #else + *(uint32_t *)RCC_GPIOCLOCK |= pos; + #endif +} + +/** + * @brief Configure single port pins + * @param port - port base address + * pin_mask - desired pin + * config - pin settings + * @return none + */ +static void hal_ll_gpio_config( uint32_t *port, uint16_t pin_mask, uint32_t config ) +{ + uint32_t pin_pos = 0; + uint32_t pos = 0; + uint32_t current_pin = 0; + + uint32_t mode = 0; + uint32_t speed = 0; + uint32_t otype = 0; + uint32_t pull = 0; + + hal_ll_gpio_base_handle_t *port_ptr; + + port_ptr = ( hal_ll_gpio_base_handle_t *)port; + + hal_ll_gpio_clock_enable( port ); + + if ( pin_mask == GPIO_PIN_MASK_LOW ) + { + port_ptr->moder &= HAL_LL_NIBBLE_HIGH_32BIT; + + + + if ( config == GPIO_CFG_DIGITAL_OUTPUT ) + { + port_ptr->moder |= 0x00005555; + + port_ptr->otyper &= 0xFFFFFF00; + + port_ptr->ospeedr |= HAL_LL_NIBBLE_LOW_32BIT; + + + return; + } + if ( config == GPIO_CFG_DIGITAL_INPUT ) + { + port_ptr->moder &= HAL_LL_NIBBLE_HIGH_32BIT; + + + return; + } + } + else if ( pin_mask == GPIO_PIN_MASK_HIGH ) + { + port_ptr->moder &= HAL_LL_NIBBLE_LOW_32BIT; + + + + if ( config == GPIO_CFG_DIGITAL_OUTPUT ) + { + port_ptr->moder |= 0x55550000; + + port_ptr->otyper &= 0xFFFF00FF; + + port_ptr->ospeedr |= HAL_LL_NIBBLE_HIGH_32BIT; + + + return; + } + if ( config == GPIO_CFG_DIGITAL_INPUT ) + { + port_ptr->moder &= HAL_LL_NIBBLE_LOW_32BIT; + + + return; + } + } + + if ( pin_mask == GPIO_PIN_MASK_ALL ) + { + if ( config == GPIO_CFG_DIGITAL_OUTPUT ) + { + port_ptr->moder = 0x55555555; + + port_ptr->otyper = 0; + + port_ptr->ospeedr = HAL_LL_NIBBLE_HIGH_32BIT; + + + return; + } + if ( config == GPIO_CFG_DIGITAL_INPUT ) + { + port_ptr->moder = 0; + + + return; + } + } + + if ( config & GPIO_CFG_MODE_ANALOG ) + mode = 3; + else if ( config & GPIO_CFG_MODE_ALT_FUNCTION ) + mode = 2; + else if ( config & GPIO_CFG_MODE_OUTPUT ) + mode = 1; + else + mode = 0; + + #if defined(STM32F411xx) || defined(STM32F412xx) || defined(STM32F413xx) || \ + defined(STM32F423xx) || defined(STM32F446xx) || defined(STM32F3xx) + if ( config & ( GPIO_CFG_SPEED_HIGH | GPIO_CFG_SPEED_MAX ) ) + speed = 3; + #endif + if ( config & ( GPIO_CFG_SPEED_VERY_HIGH ) ) + speed = 3; + + if ( config & ( GPIO_CFG_SPEED_HIGH ) ) + speed = 2; + + if ( config & ( GPIO_CFG_SPEED_MEDIUM ) ) + speed = 1; + + if ( config & ( GPIO_CFG_SPEED_LOW ) ) + speed = 0; + + + + if ( config & GPIO_CFG_OTYPE_OD ) + otype = 1; + + else + otype = 0; + + + if ( config & GPIO_CFG_PULL_DOWN ) + pull = 2; + + else if ( config & GPIO_CFG_PULL_UP ) + pull = 1; + + else + pull = 0; + + + for ( pin_pos = 0x00; pin_pos < 0x10; pin_pos++ ) + { + pos = ( ( uint32_t ) 0x01 ) << pin_pos; + current_pin = pin_mask & pos; + + if ( current_pin == pos ) + { + port_ptr->moder &= ~( ( uint32_t )0x03 << ( pin_pos * 2 ) ); + port_ptr->moder |= ( ( ( uint32_t )mode ) << ( pin_pos * 2 ) ); + + if ( config & ( GPIO_CFG_MODE_OUTPUT | GPIO_CFG_MODE_ALT_FUNCTION ) ) + { + port_ptr->ospeedr &= ~( ( uint32_t )0x03 << ( pin_pos * 2 ) ); + port_ptr->ospeedr |= ( ( uint32_t )( speed ) << ( pin_pos * 2 ) ); + + port_ptr->otyper &= ~( ( uint32_t )0x01 << ( ( uint16_t )pin_pos ) ) ; + port_ptr->otyper |= ( uint16_t )( ( ( uint16_t )otype ) << ( ( uint16_t )pin_pos ) ); + } + + port_ptr->pupdr &= ~( ( uint32_t )0x03 << ( ( uint16_t )pin_pos * 2 ) ); + port_ptr->pupdr |= ( ( ( uint32_t )pull ) << ( pin_pos * 2 ) ); + } + } + + +} + +/** + * @brief Configure port pins alternate + * functions + * @param module_pin - desired pin + * config - pin settings + * @return none + */ +static void _hal_ll_gpio_config_pin_alternate_enable( uint32_t module_pin, uint32_t module_config, bool state ) +{ + hal_ll_pin_name_t pin_name; + uint16_t pin_index; + uint32_t alternate_function; + hal_ll_gpio_base_handle_t *port_ptr; + + pin_name = module_pin & GPIO_PIN_NAME_MASK; + + alternate_function = ( module_pin >> GPIO_AF_OFFSET ) & GPIO_AF_MASK; + + port_ptr = ( hal_ll_gpio_base_handle_t *)hal_ll_gpio_port_base( hal_ll_gpio_port_index ( pin_name ) ); + + hal_ll_gpio_clock_enable( ( uint32_t *)port_ptr ); + + pin_index = hal_ll_gpio_pin_index( pin_name ); + if ( pin_index > 7 ) + { + pin_index -= 8; + if ( state ) { + port_ptr->afrh &= ~( ( uint32_t )( GPIO_AF_MASK ) << ( pin_index * 4 ) ); + port_ptr->afrh |= ( ( uint32_t )( alternate_function ) << ( pin_index * 4 ) ); + } else { + port_ptr->afrh &= ~( ( uint32_t )( alternate_function ) << ( pin_index * 4 ) ); + } + } + else + { + if ( state ) { + port_ptr->afrl &= ~( ( uint32_t )( GPIO_AF_MASK ) << ( pin_index * 4 ) ); + port_ptr->afrl |= ( ( uint32_t )( alternate_function ) << ( pin_index * 4 ) ); + } else { + port_ptr->afrl &= ~( ( uint32_t )( alternate_function ) << ( pin_index * 4 ) ); + } + } + + hal_ll_gpio_config( ( uint32_t*)port_ptr, hal_ll_gpio_pin_mask( pin_name ), module_config ); +} +// ------------------------------------------------------------------------- END + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_89/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_89/CMakeLists.cmake new file mode 100644 index 000000000..4da6d7a51 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_89/CMakeLists.cmake @@ -0,0 +1,8 @@ +if(${MCU_NAME} MATCHES "^STM32G4A1CE$|^STM32G4A1KE$|^STM32G4A1ME$|^STM32G4A1RE$|^STM32G4A1VE$") + set(gpio_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_gpio_port.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_89") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_89") + list(APPEND hal_ll_def_list "STM32G4xx") + list(APPEND hal_ll_def_list "STM32G4Axx") + list(APPEND hal_ll_def_list "STM32G4A1xx") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_89/hal_ll_gpio_port.c b/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_89/hal_ll_gpio_port.c new file mode 100644 index 000000000..a5ded8222 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/gpio/implementations/doc_ds_89/hal_ll_gpio_port.c @@ -0,0 +1,477 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_gpio_port.c + * @brief GPIO HAL LOW LEVEL ported layer implementation. + */ + +#include "hal_ll_gpio_port.h" +#include "hal_ll_rcc.h" + +/** + * Defines used in source + */ + + #define GPIOA_BASE_ADDR 0x48000000 + + #define GPIOB_BASE_ADDR 0x48000400 + + #define GPIOC_BASE_ADDR 0x48000800 + + #define GPIOD_BASE_ADDR 0x48000C00 + + #define GPIOE_BASE_ADDR 0x48001000 + + #define GPIOF_BASE_ADDR 0x48001400 + + #define GPIOG_BASE_ADDR 0x48001800 + + #define RCC_GPIOCLOCK _RCC_AHB2ENR + + +#ifdef STM32L4xx + #define RCC_APB1ENR1_PWREN_BIT_MASK (1UL << 28) + #define _PWR_CR2_ADDRESS ( uint32_t * )0x40007004 + #define PWR_CR2_IOSV_BIT_MASK (1U << 9) +#endif + +#ifndef GPIOA_BASE_ADDR + #define GPIOA_BASE_ADDR 0 +#endif + +#ifndef GPIOB_BASE_ADDR + #define GPIOB_BASE_ADDR 0 +#endif + +#ifndef GPIOC_BASE_ADDR + #define GPIOC_BASE_ADDR 0 +#endif + +#ifndef GPIOD_BASE_ADDR + #define GPIOD_BASE_ADDR 0 +#endif + +#ifndef GPIOE_BASE_ADDR + #define GPIOE_BASE_ADDR 0 +#endif + +#ifndef GPIOF_BASE_ADDR + #define GPIOF_BASE_ADDR 0 +#endif + +#ifndef GPIOG_BASE_ADDR + #define GPIOG_BASE_ADDR 0 +#endif + + +static void hal_ll_gpio_config( uint32_t *port, uint16_t pin_mask, uint32_t config ); + +/*!< @brief GPIO PORT array */ +static const uint32_t _hal_ll_gpio_port_base [ 11 ] = +{ + GPIOA_BASE_ADDR, + + GPIOB_BASE_ADDR, + + GPIOC_BASE_ADDR, + + GPIOD_BASE_ADDR, + + GPIOE_BASE_ADDR, + + GPIOF_BASE_ADDR, + + GPIOG_BASE_ADDR, + +}; + +/** + * @brief Enable gpio port clock + * @param port - port base address + * @return none + */ +static void _hal_ll_gpio_clock_enable( uint32_t *port ); + +/** + * @brief Configure port pins + * @param port - port base address + * pin_mask - desired pin + * config - pin settings + * @return none + */ +static void _hal_ll_gpio_config( uint32_t *port, uint16_t pin_mask, uint32_t config ); + +/** + * @brief Configure port pins alternate + * functions + * @param module_pin - desired pin + * config - pin settings + * @return none + */ +static void _hal_ll_gpio_config_pin_alternate_enable( uint32_t module_pin, uint32_t module_config, bool state ); + +static uint8_t hal_ll_gpio_pin_index( hal_ll_pin_name_t name ) +{ + return ( uint8_t )name % PORT_SIZE; +} + +uint8_t hal_ll_gpio_port_index( hal_ll_pin_name_t name ) +{ + return ( uint8_t )name / PORT_SIZE; +} + +uint32_t hal_ll_gpio_pin_mask( hal_ll_pin_name_t name ) +{ + return ( ( uint32_t )0x01 << hal_ll_gpio_pin_index( name ) ); +} + +uint32_t hal_ll_gpio_port_base( hal_ll_port_name_t name ) +{ + return _hal_ll_gpio_port_base[ name ]; +} + +void hal_ll_gpio_analog_input( uint32_t *port, uint16_t pin_mask ) +{ + hal_ll_gpio_config( port, pin_mask, GPIO_CFG_ANALOG_INPUT ); +} + +void hal_ll_gpio_digital_input( uint32_t *port, uint16_t pin_mask ) +{ + hal_ll_gpio_config( port, pin_mask, GPIO_CFG_DIGITAL_INPUT ); +} + +void hal_ll_gpio_digital_output( uint32_t *port, uint16_t pin_mask ) +{ + hal_ll_gpio_config( port, pin_mask, GPIO_CFG_DIGITAL_OUTPUT ); +} + +void hal_ll_gpio_module_struct_init( module_struct const *module, bool state ) +{ + int32_t index = 0; + + + while ( module->pins[ index ] != GPIO_MODULE_STRUCT_END ) + { + _hal_ll_gpio_config_pin_alternate_enable( module->pins[ index ], module->configs[ index ], state ); + + index++; + } +} + +/** + * @brief Enable gpio port clock + * @param port - port base address + * @return none + */ +static void hal_ll_gpio_clock_enable( uint32_t *port ) +{ + uint32_t pos = 0; + + switch ( ( uint32_t )port & 0xFFFFFC00 ) + { + #ifdef __PORT_A_CN + case GPIOA_BASE_ADDR: pos = 0x01; break; + #endif + + #ifdef __PORT_B_CN + case GPIOB_BASE_ADDR: pos = 0x02; break; + #endif + + #ifdef __PORT_C_CN + case GPIOC_BASE_ADDR: pos = 0x04; break; + #endif + + #ifdef __PORT_D_CN + case GPIOD_BASE_ADDR: pos = 0x08; break; + #endif + + #ifdef __PORT_E_CN + case GPIOE_BASE_ADDR: pos = 0x10; break; + #endif + + #ifdef __PORT_F_CN + case GPIOF_BASE_ADDR: pos = 0x20; break; + #endif + + #ifdef __PORT_G_CN + case GPIOG_BASE_ADDR: pos = 0x40; break; + #endif + + } + + #ifdef STM32L4xx + /* + * This bit is used to validate the VDDIO2 supply for electrical and + * logical isolation purpose.Setting this bit is mandatory to use PG[15:2]. + * If VDDIO2 is not always present in the application, the PVM can be used + * to determine whether this supply is ready or not. + * Procedure: + * 1. Enable power interface clock ( page 290 in ref manual ) + * 2. Validate VDDIO2 supply ( page 218 in ref manual ) + * + * Ref. manual + * + */ + *(uint32_t *)_RCC_APB1ENR1 |= RCC_APB1ENR1_PWREN_BIT_MASK; + *(uint32_t *)_PWR_CR2_ADDRESS |= PWR_CR2_IOSV_BIT_MASK; + #endif + + #if defined(STM32F3xx) || defined(STM32F0xx) + *(uint32_t *)RCC_GPIOCLOCK |= ( uint32_t )pos << GPIO_AHB_SHIFT; + #else + *(uint32_t *)RCC_GPIOCLOCK |= pos; + #endif +} + +/** + * @brief Configure single port pins + * @param port - port base address + * pin_mask - desired pin + * config - pin settings + * @return none + */ +static void hal_ll_gpio_config( uint32_t *port, uint16_t pin_mask, uint32_t config ) +{ + uint32_t pin_pos = 0; + uint32_t pos = 0; + uint32_t current_pin = 0; + + uint32_t mode = 0; + uint32_t speed = 0; + uint32_t otype = 0; + uint32_t pull = 0; + + hal_ll_gpio_base_handle_t *port_ptr; + + port_ptr = ( hal_ll_gpio_base_handle_t *)port; + + hal_ll_gpio_clock_enable( port ); + + if ( pin_mask == GPIO_PIN_MASK_LOW ) + { + port_ptr->moder &= HAL_LL_NIBBLE_HIGH_32BIT; + + + + if ( config == GPIO_CFG_DIGITAL_OUTPUT ) + { + port_ptr->moder |= 0x00005555; + + port_ptr->otyper &= 0xFFFFFF00; + + port_ptr->ospeedr |= HAL_LL_NIBBLE_LOW_32BIT; + + + return; + } + if ( config == GPIO_CFG_DIGITAL_INPUT ) + { + port_ptr->moder &= HAL_LL_NIBBLE_HIGH_32BIT; + + + return; + } + } + else if ( pin_mask == GPIO_PIN_MASK_HIGH ) + { + port_ptr->moder &= HAL_LL_NIBBLE_LOW_32BIT; + + + + if ( config == GPIO_CFG_DIGITAL_OUTPUT ) + { + port_ptr->moder |= 0x55550000; + + port_ptr->otyper &= 0xFFFF00FF; + + port_ptr->ospeedr |= HAL_LL_NIBBLE_HIGH_32BIT; + + + return; + } + if ( config == GPIO_CFG_DIGITAL_INPUT ) + { + port_ptr->moder &= HAL_LL_NIBBLE_LOW_32BIT; + + + return; + } + } + + if ( pin_mask == GPIO_PIN_MASK_ALL ) + { + if ( config == GPIO_CFG_DIGITAL_OUTPUT ) + { + port_ptr->moder = 0x55555555; + + port_ptr->otyper = 0; + + port_ptr->ospeedr = HAL_LL_NIBBLE_HIGH_32BIT; + + + return; + } + if ( config == GPIO_CFG_DIGITAL_INPUT ) + { + port_ptr->moder = 0; + + + return; + } + } + + if ( config & GPIO_CFG_MODE_ANALOG ) + mode = 3; + else if ( config & GPIO_CFG_MODE_ALT_FUNCTION ) + mode = 2; + else if ( config & GPIO_CFG_MODE_OUTPUT ) + mode = 1; + else + mode = 0; + + #if defined(STM32F411xx) || defined(STM32F412xx) || defined(STM32F413xx) || \ + defined(STM32F423xx) || defined(STM32F446xx) || defined(STM32F3xx) + if ( config & ( GPIO_CFG_SPEED_HIGH | GPIO_CFG_SPEED_MAX ) ) + speed = 3; + #endif + if ( config & ( GPIO_CFG_SPEED_VERY_HIGH ) ) + speed = 3; + + if ( config & ( GPIO_CFG_SPEED_HIGH ) ) + speed = 2; + + if ( config & ( GPIO_CFG_SPEED_MEDIUM ) ) + speed = 1; + + if ( config & ( GPIO_CFG_SPEED_LOW ) ) + speed = 0; + + + + if ( config & GPIO_CFG_OTYPE_OD ) + otype = 1; + + else + otype = 0; + + + if ( config & GPIO_CFG_PULL_DOWN ) + pull = 2; + + else if ( config & GPIO_CFG_PULL_UP ) + pull = 1; + + else + pull = 0; + + + for ( pin_pos = 0x00; pin_pos < 0x10; pin_pos++ ) + { + pos = ( ( uint32_t ) 0x01 ) << pin_pos; + current_pin = pin_mask & pos; + + if ( current_pin == pos ) + { + port_ptr->moder &= ~( ( uint32_t )0x03 << ( pin_pos * 2 ) ); + port_ptr->moder |= ( ( ( uint32_t )mode ) << ( pin_pos * 2 ) ); + + if ( config & ( GPIO_CFG_MODE_OUTPUT | GPIO_CFG_MODE_ALT_FUNCTION ) ) + { + port_ptr->ospeedr &= ~( ( uint32_t )0x03 << ( pin_pos * 2 ) ); + port_ptr->ospeedr |= ( ( uint32_t )( speed ) << ( pin_pos * 2 ) ); + + port_ptr->otyper &= ~( ( uint32_t )0x01 << ( ( uint16_t )pin_pos ) ) ; + port_ptr->otyper |= ( uint16_t )( ( ( uint16_t )otype ) << ( ( uint16_t )pin_pos ) ); + } + + port_ptr->pupdr &= ~( ( uint32_t )0x03 << ( ( uint16_t )pin_pos * 2 ) ); + port_ptr->pupdr |= ( ( ( uint32_t )pull ) << ( pin_pos * 2 ) ); + } + } + + +} + +/** + * @brief Configure port pins alternate + * functions + * @param module_pin - desired pin + * config - pin settings + * @return none + */ +static void _hal_ll_gpio_config_pin_alternate_enable( uint32_t module_pin, uint32_t module_config, bool state ) +{ + hal_ll_pin_name_t pin_name; + uint16_t pin_index; + uint32_t alternate_function; + hal_ll_gpio_base_handle_t *port_ptr; + + pin_name = module_pin & GPIO_PIN_NAME_MASK; + + alternate_function = ( module_pin >> GPIO_AF_OFFSET ) & GPIO_AF_MASK; + + port_ptr = ( hal_ll_gpio_base_handle_t *)hal_ll_gpio_port_base( hal_ll_gpio_port_index ( pin_name ) ); + + hal_ll_gpio_clock_enable( ( uint32_t *)port_ptr ); + + pin_index = hal_ll_gpio_pin_index( pin_name ); + if ( pin_index > 7 ) + { + pin_index -= 8; + if ( state ) { + port_ptr->afrh &= ~( ( uint32_t )( GPIO_AF_MASK ) << ( pin_index * 4 ) ); + port_ptr->afrh |= ( ( uint32_t )( alternate_function ) << ( pin_index * 4 ) ); + } else { + port_ptr->afrh &= ~( ( uint32_t )( alternate_function ) << ( pin_index * 4 ) ); + } + } + else + { + if ( state ) { + port_ptr->afrl &= ~( ( uint32_t )( GPIO_AF_MASK ) << ( pin_index * 4 ) ); + port_ptr->afrl |= ( ( uint32_t )( alternate_function ) << ( pin_index * 4 ) ); + } else { + port_ptr->afrl &= ~( ( uint32_t )( alternate_function ) << ( pin_index * 4 ) ); + } + } + + hal_ll_gpio_config( ( uint32_t*)port_ptr, hal_ll_gpio_pin_mask( pin_name ), module_config ); +} +// ------------------------------------------------------------------------- END + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/hal_ll/CMakeLists.txt b/targets/arm/mikroe/ai_generated/stm32/src/hal_ll/CMakeLists.txt new file mode 100644 index 000000000..0f1b65814 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/hal_ll/CMakeLists.txt @@ -0,0 +1,22 @@ +## ./targets/arm/mikroe/ai_generated/stm32/src/hal_ll/CMakeLists.txt +add_library(lib_hal_ll INTERFACE) + +add_library(MikroSDK.HalLowLevel ALIAS lib_hal_ll) + +target_link_libraries(lib_hal_ll INTERFACE + MikroSDK.HalLowLevel.ADC + MikroSDK.HalLowLevel.GPIO + MikroSDK.HalLowLevel.I2C.Master + MikroSDK.HalLowLevel.SPI.Master + MikroSDK.HalLowLevel.TIM + MikroSDK.HalLowLevel.UART + MikroSDK.HalLowLevel.OneWire +) + +get_files_recurse(${CMAKE_CURRENT_LIST_DIR}/../gpio CMAKE_FILES cmake) +foreach(cmakeFile ${CMAKE_FILES}) + include(${cmakeFile}) +endforeach() + +mikrosdk_install(MikroSDK.HalLowLevel) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel ${rcc_subimplementation}/hal_ll_rcc.h ../../include/hal_ll_target.h ../../include/hal_ll_pin_names.h ../../include/hal_ll_target_names.h) diff --git a/targets/arm/mikroe/ai_generated/stm32/src/i2c/CMakeLists.txt b/targets/arm/mikroe/ai_generated/stm32/src/i2c/CMakeLists.txt new file mode 100644 index 000000000..d76371bc0 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/i2c/CMakeLists.txt @@ -0,0 +1,85 @@ +## ./targets/arm/mikroe/ai_generated/stm32/src/i2c/CMakeLists.txt + +## Check if current module is generated or not +set(MODULE_IS_GENERATED false) +get_files_recurse(${CMAKE_CURRENT_LIST_DIR}/implementations CMAKE_FILES cmake) +check_if_module_is_generated(MODULE_IS_GENERATED "${CMAKE_FILES}") + +## If current MCU has this module, add it +if(MODULE_IS_GENERATED) + set(hal_ll_def_list "") + set(mcu_header_path "") + + find_cortex(hal_ll_def_list) + list(APPEND hal_ll_def_list ${MCU_NAME}) + set(mcu_header_path ${MCU_NAME}_${_MSDK_PACKAGE_ID_}) + + ## BEGIN I2C + list(APPEND hal_ll_def_list "MACRO_USAGE_I2C") + + ## i.e "if (${MCU_NAME} MATCHES "^STM32C011F6$|^STM32C011C6$")" + ## List all MCUs and or them in the regex + foreach(cmakeFile ${CMAKE_FILES}) + include(${cmakeFile}) + endforeach() + ## END I2C + + if (NOT DEFINED _MSDK_TFT_TP_) + list(APPEND hal_ll_def_list "__TFT_NON_TSC2003__") + else() + if (${_MSDK_TFT_TP_} MATCHES "__TP_TSC2003__") + list(APPEND hal_ll_def_list "__TFT_RESISTIVE_TSC2003__") + else() + list(APPEND hal_ll_def_list "__TFT_NON_TSC2003__") + endif() + endif() + + mikrosdk_add_library(lib_hal_ll_i2c_master MikroSDK.HalLowLevel.I2C.Master + ${rcc_subimplementation}/hal_ll_rcc.h + ../../include/hal_ll_target.h + # BEGIN I2C + ${i2c_subimplementation} + ../../include/i2c/hal_ll_i2c_master.h + ${i2c_pin_map}/hal_ll_i2c_pin_map.h + # END I2C + ) + + target_compile_definitions(lib_hal_ll_i2c_master PUBLIC + ${hal_ll_def_list} + ) + + target_link_libraries(lib_hal_ll_i2c_master PUBLIC + MikroC.Core + MikroSDK.HalLowLevelCore + MikroSDK.HalLowLevelCommon + ) + + string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) + target_include_directories(lib_hal_ll_i2c_master + PRIVATE + ../../include + ../../include/gpio + ${gpio_subimplementation_include_dir} + # BEGIN I2C + ../../include/i2c + ${i2c_pin_map} + # END I2C + # BEGIN RCC + ${rcc_subimplementation} + # END RCC + INTERFACE + # BUILD + $ + $ + $ + $ + $ + $ + # INSTALL + $ + $ + ) + + mikrosdk_install(MikroSDK.HalLowLevel.I2C.Master) + install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.I2C.Master ../../include/i2c/hal_ll_i2c_master.h) +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_1/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_1/CMakeLists.cmake new file mode 100644 index 000000000..8eac8aa8b --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_1/CMakeLists.cmake @@ -0,0 +1,9 @@ +if(${MCU_NAME} MATCHES "^STM32C011F4$|^STM32C011J4$|^STM32C011F6$|^STM32C011J6$|^STM32C011D6$") + set(i2c_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_i2c_master.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_1") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_1") + list(APPEND hal_ll_def_list "STM32C0xx") + list(APPEND hal_ll_def_list "STM32C01xx") + list(APPEND hal_ll_def_list "STM32C011xx") + set(i2c_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/i2c/hal_ll_i2c_pin_map/implementations/doc_ds_1") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_1/hal_ll_i2c_master.c b/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_1/hal_ll_i2c_master.c new file mode 100644 index 000000000..b2b858a56 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_1/hal_ll_i2c_master.c @@ -0,0 +1,887 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_i2c_master.c + * @brief I2C master HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_rcc.h" +#include "hal_ll_gpio.h" +#include "hal_ll_i2c_master.h" +#include "hal_ll_i2c_pin_map.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_i2c_master_handle_register_t hal_ll_module_state[I2C_MODULE_COUNT] = { (handle_t *)NULL, (handle_t *)NULL, false }; + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_i2c_get_module_state_address ((hal_ll_i2c_master_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_i2c_get_handle (hal_ll_i2c_master_handle_register_t *)hal_ll_i2c_get_module_state_address->hal_ll_i2c_master_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_i2c_get_base_struct(_handle) ((hal_ll_i2c_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_i2c_get_base_from_hal_handle ((hal_ll_i2c_hw_specifics_map_t *)((hal_ll_i2c_master_handle_register_t *)\ + (((hal_ll_i2c_master_handle_register_t *)(handle))->hal_ll_i2c_master_handle))->hal_ll_i2c_master_handle)->base + +/*!< @brief Default I2C bit-rate if no speed is set */ +#define HAL_LL_I2C_MASTER_SPEED_100K 100000UL +#define HAL_LL_I2C_MASTER_SPEED_400K 400000UL +#define HAL_LL_I2C_MASTER_SPEED_1M 1000000UL + +/*!< @brief Default pass count value upon reset */ +#define HAL_LL_I2C_DEFAULT_PASS_COUNT 0xFFFFU + +/*!< @brief Macro used for timeout */ +#define HAL_LL_I2C_LOOP_INDEX 10000U + +/*!< @brief Macros defining register bit location */ +#define HAL_LL_I2C1EN_BIT 21 +#define HAL_LL_I2C1SEL0_BIT 12 +#define HAL_LL_I2C1SEL1_BIT 13 + +#define HAL_LL_I2C_100K 0x30420F13 +#define HAL_LL_I2C_400K 0x10320309 +#define HAL_LL_I2C_1M 0x00200204 + +#define HAL_LL_I2C_PE_BIT 0 +#define HAL_LL_I2C_CR2_STOP_BIT 14 +#define HAL_LL_I2C_CR2_START_BIT 13 +#define HAL_LL_I2C_ISR_STOPF_BIT 5 +#define HAL_LL_I2C_ISR_BUSY_BIT 15 +#define HAL_LL_I2C_ARLO_BIT 9 +#define HAL_LL_I2C_RXNE_BIT 2 +#define HAL_LL_I2C_TXIS_BIT 1 +#define HAL_LL_I2C_TXE_BIT 0 + +/*!< @brief Macros defining register bit masks */ +#define HAL_LL_I2C_CR1_RXTX_INT 0x6 +#define HAL_LL_I2C_CR2_STOP 0x4000UL +#define HAL_LL_I2C_CR2_START 0x2000U +#define HAL_LL_I2C_CR2_SADD 0x3FFU +#define HAL_LL_I2C_CR2_NBYTES 0xFF0000UL +#define HAL_LL_I2C_CR2_RD_WRN 0x400U +#define HAL_LL_I2C_CR2_RELOAD 0x1000000UL +#define HAL_LL_I2C_CR2_AUTOEND 0x2000000UL +#define HAL_LL_I2C_FILTERS_OFF 0xFFFFE0FFUL +#define HAL_LL_I2C_SADD_MASK 0x3FFUL +#define HAL_LL_I2C_HEAD10R_MASK 0x1000UL +#define HAL_LL_I2C_NBYTES_MASK 0xFF0000UL +#define HAL_LL_I2C_RELOAD_MASK 0x1000000UL +#define HAL_LL_I2C_RD_WRN_MASK 0x400UL + +/*!< @brief Macros used for module pin checking */ +#define HAL_LL_I2C_SCL_PIN 0 +#define HAL_LL_I2C_SDA_PIN 1 +#define HAL_LL_I2C_MODULE_PIN_COUNT 2 + +/*!< @brief Macro used for setting pin alternate functions */ +#define HAL_LL_I2C_AF_CONFIG (GPIO_CFG_MODE_ALT_FUNCTION | GPIO_CFG_SPEED_HIGH | GPIO_CFG_OTYPE_OD) + +// -------------------------------------------------------------- PRIVATE TYPES +/*!< @brief I2C register structure */ +typedef struct +{ + hal_ll_base_addr_t cr1; + hal_ll_base_addr_t cr2; + hal_ll_base_addr_t oar1; + hal_ll_base_addr_t oar2; + hal_ll_base_addr_t timingr; + hal_ll_base_addr_t timeoutr; + hal_ll_base_addr_t isr; + hal_ll_base_addr_t icr; + hal_ll_base_addr_t pecr; + hal_ll_base_addr_t rxdr; + hal_ll_base_addr_t txdr; +} hal_ll_i2c_base_handle_t; + +/*!< @brief I2C hw specific structure */ +typedef struct +{ + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + hal_ll_i2c_pins_t pins; + uint32_t speed; + uint8_t address; + uint16_t timeout; +} hal_ll_i2c_hw_specifics_map_t; + +/*!< @brief I2C hw specific module values */ +typedef struct +{ + uint16_t pin_scl; + uint16_t pin_sda; +} hal_ll_i2c_pin_id; + +/*!< @brief I2C hw specific error values */ +typedef enum +{ + HAL_LL_I2C_MASTER_SUCCESS = 0, + HAL_LL_I2C_MASTER_WRONG_PINS, + HAL_LL_I2C_MASTER_MODULE_ERROR, + + HAL_LL_I2C_MASTER_ERROR = (-1) +} hal_ll_i2c_master_err_t; + +/*!< @brief I2C end mode selection values */ +typedef enum +{ + HAL_LL_I2C_MASTER_END_MODE_RESTART = 0, + HAL_LL_I2C_MASTER_END_MODE_STOP, + HAL_LL_I2C_MASTER_WRITE_THEN_READ +} hal_ll_i2c_master_end_mode_t; + +/*!< @brief I2C timeout error values */ +typedef enum +{ + HAL_LL_I2C_MASTER_TIMEOUT_START = 1300, + HAL_LL_I2C_MASTER_TIMEOUT_STOP, + HAL_LL_I2C_MASTER_TIMEOUT_WRITE, + HAL_LL_I2C_MASTER_TIMEOUT_READ, + HAL_LL_I2C_MASTER_ARBITRATION_LOST, + HAL_LL_I2C_MASTER_TIMEOUT_INIT +} hal_ll_i2c_master_timeout_t; + +/** + * @brief Enum containing predefined module standard speed values. + * + * Enum values: + * HAL_LL_I2C_MASTER_SPEED_STANDARD -- Speed set at 100K + * HAL_LL_I2C_MASTER_SPEED_FULL -- Speed set at 400K + * HAL_LL_I2C_MASTER_SPEED_FAST -- Speed set at 1M + */ +typedef enum +{ + HAL_LL_I2C_MASTER_SPEED_STANDARD = 0, + HAL_LL_I2C_MASTER_SPEED_FULL, + HAL_LL_I2C_MASTER_SPEED_FAST +} hal_ll_i2c_master_speed_t; + +// ------------------------------------------------------------------ VARIABLES +/*!< @brief I2C hardware specific info */ +static hal_ll_i2c_hw_specifics_map_t hal_ll_i2c_hw_specifics_map[] = +{ + #ifdef I2C_MODULE_1 + {HAL_LL_I2C1_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_1), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, + #endif + + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, 0, 0} +}; + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_i2c_master_handle_register_t *low_level_handle; +static volatile hal_ll_i2c_hw_specifics_map_t *hal_ll_i2c_hw_specifics_map_local; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Check if pins are adequate. + * + * Checks scl and sda pins the user has passed with pre-defined + * pins in scl and sda maps. Take into consideration that module + * index numbers have to be the same for both pins. + * + * @param[in] scl - SCL pre-defined pin name. + * @param[in] sda - SDA pre-defined pin name. + * @param[in] *index_list - Index list address + * @return hal_ll_pin_name_t Module index based on pins. + * + * Returns pre-defined module index from pin maps, if pins + * are adequate. + */ +static hal_ll_pin_name_t hal_ll_i2c_master_check_pins( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_pin_id *index_list, hal_ll_i2c_master_handle_register_t *handle_map ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_i2c_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_i2c_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_i2c_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Get adequate I2C bit-rate value. + * + * Returns one of pre-defined bit-rate values, + * or the closest bit-rate based on bit_rate + * value passed to the function. + * + * @param[in] bit_rate - I2C bit rate. + * @return uint32_t Adequate bit-rate value. + * + * Returns adequate value to be latter written into bare metal register address. + * Take into consideration that this returns a predefined value. + * + * HAL_LL_I2C_MASTER_SPEED_100K -- 100Kbit/s + * HAL_LL_I2C_MASTER_SPEED_400K -- 400Kbit/s + * HAL_LL_I2C_MASTER_SPEED_1M -- 1Mbit/s + * HAL_LL_I2C_MASTER_SPEED_3M2 -- 3.2Mbit/s + */ +static uint32_t hal_ll_i2c_get_speed( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Enable clock for I2C1 module on hardware level. + * + * Initializes I2C1 module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] hal_ll_state - True/False -- Init/De-init + * + * @return None + */ +static inline void hal_ll_i2c1_set_clock( bool hal_ll_state ); + +/** + * @brief Enable clock for I2C module on hardware level. + * + * Initializes I2C module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_stat - True(enable clock)/False(disable clock). + * + * @return None + */ +static void hal_ll_i2c_master_set_clock( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Initialize I2C module on hardware level. + * + * Initializes I2C module on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] map - Object specific context handler. + * @return hal_ll_err_t Module specific return values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_hw_init( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * I2C SCL and SDA pins. + * + * @param[in] module_index I2C HW module index -- 0,1,2... + * @param[in] *index_list Array with SCL and SDA map index values + * and module number + * + * @return None + */ +static void hal_ll_i2c_master_map_pins( uint8_t module_index, hal_ll_i2c_pin_id *index_list ); + +/** + * @brief Sets I2C pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if I2C is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_state - Init/De-init + * + * @return None + */ +static void hal_ll_i2c_master_alternate_functions_set_state( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Full I2C module initialization procedure. + * + * Initializes I2C module on hardware level, based on beforehand + * set configuration and module handler. Sets adequate pin alternate functions. + * Initializes module clock. + * + * @param[in] map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Configure I2C module for data transfer. + * + * @param[in] hal_ll_hw_reg - I2C module base address. + * @param[in] config - I2C config bits. + * @return void None. + */ +static void hal_ll_i2c_master_configure_transfer( hal_ll_i2c_base_handle_t *hal_ll_hw_reg, uint32_t config ); + +/** + * @brief Reset value of I2C CR2 register. + * + * @param[in] hal_ll_hw_reg - I2C module base address. + * @returnl none + */ +static void hal_ll_i2c_master_reset_cr2( hal_ll_i2c_base_handle_t *hal_ll_hw_reg ); + +/** + * @brief Generates start signal on I2C bus. + * + * Generates a start signal on the I2C bus. + * + * @param[in] map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_master_start( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Generates stop signal on I2C bus. + * + * Generates a stop signal on the I2C bus. + * + * @param[in] map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_master_stop( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Perform a read on the I2C bus. + * + * Initializes I2C module on hardware level, if not initialized beforehand + * and continues to perform a read operation on the bus. + * + * @param[in] map - Object specific context handler. + * @param[in] readDatabuf - Pointer to data buffer. + * @param[in] lenReadData - Number of data to be read. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *read_data_buf, size_t len_read_data, hal_ll_i2c_master_end_mode_t mode ); + +/** + * @brief Perform a write on the I2C bus. + * + * Initializes I2C module on hardware level, if not initialized beforehand + * and continues to perform a write operation on the bus. + * + * @param[in] map - Object specific context handler. + * @param[in] writeDatabuf - Pointer to data buffer. + * @param[in] lenWriteData - Number of data to be written. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *write_data_buf, size_t len_write_data, hal_ll_i2c_master_end_mode_t mode ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_i2c_master_register_handle( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_master_handle_register_t *handle_map, uint8_t *hal_module_id ) { + + hal_ll_i2c_pin_id index_list[I2C_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + uint16_t pin_check_result; + + // Check if pins are valid + if ( (pin_check_result = hal_ll_i2c_master_check_pins( scl, sda, &index_list, handle_map )) == HAL_LL_PIN_NC ) { + return HAL_LL_I2C_MASTER_WRONG_PINS; + }; + + if ( (hal_ll_i2c_hw_specifics_map[pin_check_result].pins.pin_scl.pin_name != scl) || + (hal_ll_i2c_hw_specifics_map[pin_check_result].pins.pin_sda.pin_name != sda) ) + { + hal_ll_i2c_master_alternate_functions_set_state( &hal_ll_i2c_hw_specifics_map[ pin_check_result ], false ); + + hal_ll_i2c_master_map_pins( pin_check_result, &index_list ); + + hal_ll_i2c_master_alternate_functions_set_state( &hal_ll_i2c_hw_specifics_map[ pin_check_result ], true ); + + handle_map[pin_check_result].init_ll_state = false; + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[pin_check_result].hal_ll_i2c_master_handle = (handle_t *)&hal_ll_i2c_hw_specifics_map[pin_check_result].base; + + handle_map[pin_check_result].hal_ll_i2c_master_handle = (handle_t *)&hal_ll_module_state[pin_check_result].hal_ll_i2c_master_handle; + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_i2c( handle_t *handle ) { + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + hal_ll_i2c_master_handle_register_t *hal_handle = (hal_ll_i2c_master_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_i2c_hw_specifics_map_local->module_index; + + hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_local ); + + hal_ll_module_state[pin_check_result].hal_ll_i2c_master_handle = (handle_t *)&hal_ll_i2c_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_i2c_master_set_speed( handle_t *handle, uint32_t speed ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + low_level_handle->init_ll_state = false; + + hal_ll_i2c_hw_specifics_map_local->speed = speed; + + if ( hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_local ) != HAL_LL_I2C_MASTER_SUCCESS ) { + return HAL_LL_I2C_MASTER_TIMEOUT_INIT; + } + + low_level_handle->init_ll_state = true; + + return hal_ll_i2c_hw_specifics_map_local->speed; +} + +void hal_ll_i2c_master_set_timeout( handle_t *handle, uint16_t timeout ) { + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + if( hal_ll_i2c_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + hal_ll_i2c_hw_specifics_map_local->timeout = timeout; + } +} + +void hal_ll_i2c_master_set_slave_address( handle_t *handle, uint8_t addr ) { + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + if( hal_ll_i2c_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + hal_ll_i2c_hw_specifics_map_local->address = addr; + } +} + +hal_ll_err_t hal_ll_i2c_master_read( handle_t *handle, uint8_t *read_data_buf, size_t len_read_data ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + return hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_local, read_data_buf, len_read_data, HAL_LL_I2C_MASTER_END_MODE_STOP ); +} + +hal_ll_err_t hal_ll_i2c_master_write( handle_t *handle, uint8_t *write_data_buf, size_t len_write_data ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + return hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_local, write_data_buf, len_write_data, HAL_LL_I2C_MASTER_END_MODE_STOP ); +} + +hal_ll_err_t hal_ll_i2c_master_write_then_read( handle_t *handle, uint8_t *write_data_buf, size_t len_write_data, uint8_t *read_data_buf, size_t len_read_data ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + if( hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_local, write_data_buf, len_write_data, HAL_LL_I2C_MASTER_WRITE_THEN_READ ) != NULL ) { + return HAL_LL_I2C_MASTER_TIMEOUT_WRITE; + } + + /** + * @note Wait for drivers to set-up + * correctly. + **/ + #ifdef __TFT_RESISTIVE_TSC2003__ + Delay_22us(); + #endif + + if( hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_local, read_data_buf, len_read_data, HAL_LL_I2C_MASTER_WRITE_THEN_READ ) != NULL ) { + return HAL_LL_I2C_MASTER_TIMEOUT_READ; + } + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +void hal_ll_i2c_master_close( handle_t *handle ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + if( low_level_handle->hal_ll_i2c_master_handle != NULL ) { + low_level_handle->hal_ll_i2c_master_handle = NULL; + low_level_handle->hal_drv_i2c_master_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_i2c_hw_specifics_map_local->address = 0; + hal_ll_i2c_hw_specifics_map_local->timeout = HAL_LL_I2C_DEFAULT_PASS_COUNT; + hal_ll_i2c_hw_specifics_map_local->speed = HAL_LL_I2C_MASTER_SPEED_100K; + + hal_ll_i2c_master_set_clock(hal_ll_i2c_hw_specifics_map_local, true); + hal_ll_i2c_master_alternate_functions_set_state( hal_ll_i2c_hw_specifics_map_local, false ); + hal_ll_i2c_master_set_clock(hal_ll_i2c_hw_specifics_map_local, false); + + hal_ll_i2c_hw_specifics_map_local->pins.pin_scl.pin_name = HAL_LL_PIN_NC; + hal_ll_i2c_hw_specifics_map_local->pins.pin_sda.pin_name = HAL_LL_PIN_NC; + hal_ll_i2c_hw_specifics_map_local->pins.pin_scl.pin_af = 0; + hal_ll_i2c_hw_specifics_map_local->pins.pin_sda.pin_af = 0; + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static hal_ll_err_t hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *read_data_buf, size_t len_read_data, hal_ll_i2c_master_end_mode_t mode ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct(map->base); + uint16_t time_counter = map->timeout; + size_t transfer_counter = NULL; + uint8_t status = NULL; + + /** + * @note When R/W = 0, the input sample acquisition period starts + * on the falling edge of SCL once the C0 bit of the command + * byte has been latched, and ends when a Stop or + * repeated Start condition has been issued. + **/ + #ifdef __TFT_RESISTIVE_TSC2003__ + Delay_1ms(); + #endif + + hal_ll_i2c_master_configure_transfer ( map->base, + ( map->address << 1 & HAL_LL_I2C_CR2_SADD ) | + ( len_read_data << 16 & HAL_LL_I2C_CR2_NBYTES ) | + HAL_LL_I2C_CR2_RD_WRN | + HAL_LL_I2C_CR2_START + ); + + for ( transfer_counter; transfer_counter < len_read_data; transfer_counter++ ) { + while ( !( check_reg_bit( &( hal_ll_hw_reg->isr ), HAL_LL_I2C_RXNE_BIT ) ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_READ; + } + } + read_data_buf[ transfer_counter ] = hal_ll_hw_reg->rxdr; + } + + if ( ( mode == HAL_LL_I2C_MASTER_END_MODE_STOP ) || ( mode == HAL_LL_I2C_MASTER_WRITE_THEN_READ ) ) { + status = hal_ll_i2c_master_stop( map ); + } else { + status = hal_ll_i2c_master_start( map ); + } + + if( status != HAL_LL_I2C_MASTER_SUCCESS ) { + return status; + } + + hal_ll_i2c_master_reset_cr2( hal_ll_hw_reg ); + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static hal_ll_err_t hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *write_data_buf, size_t len_write_data, hal_ll_i2c_master_end_mode_t mode ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct(map->base); + uint16_t time_counter = map->timeout; + size_t transfer_counter = NULL; + uint8_t status = NULL; + + hal_ll_i2c_master_configure_transfer ( map->base, + ( map->address << 1 & HAL_LL_I2C_CR2_SADD ) | + ( len_write_data << 16 & HAL_LL_I2C_CR2_NBYTES ) | + !HAL_LL_I2C_CR2_RD_WRN | + HAL_LL_I2C_CR2_START + ); + + for ( transfer_counter; transfer_counter < len_write_data; transfer_counter++ ) + { + while ( !( check_reg_bit( &( hal_ll_hw_reg->isr ), HAL_LL_I2C_TXIS_BIT ) ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_WRITE; + } + } + hal_ll_hw_reg->txdr = write_data_buf[ transfer_counter ]; + } + + time_counter = map->timeout; + while ( !( check_reg_bit( &( hal_ll_hw_reg->isr ), HAL_LL_I2C_TXE_BIT ) ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_WRITE; + } + } + + if ( mode == HAL_LL_I2C_MASTER_END_MODE_STOP ) + { + hal_ll_i2c_master_stop( map ); + } + + hal_ll_i2c_master_reset_cr2( hal_ll_hw_reg ); + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static void hal_ll_i2c_master_configure_transfer( hal_ll_i2c_base_handle_t *hal_ll_hw_reg, uint32_t config ) { + uint32_t reg = 0; + + // Clear last set slave address + hal_ll_hw_reg->cr2 &= ~HAL_LL_I2C_CR2_SADD; + + reg = hal_ll_hw_reg->cr2; + reg &= ~( uint32_t )( + ( HAL_LL_I2C_CR2_SADD ) | + ( HAL_LL_I2C_CR2_NBYTES ) | + ( HAL_LL_I2C_CR2_RELOAD ) | + ( HAL_LL_I2C_CR2_AUTOEND ) | + ( HAL_LL_I2C_CR2_RD_WRN ) | + ( HAL_LL_I2C_CR2_START ) | + ( HAL_LL_I2C_CR2_STOP ) + ); + + reg |= config; + hal_ll_hw_reg->cr2 = reg; +} + +static void hal_ll_i2c_master_reset_cr2( hal_ll_i2c_base_handle_t *hal_ll_hw_reg ) { + hal_ll_hw_reg->cr2 &= ~( uint32_t ) + ( + HAL_LL_I2C_SADD_MASK | + HAL_LL_I2C_HEAD10R_MASK | + HAL_LL_I2C_NBYTES_MASK | + HAL_LL_I2C_RELOAD_MASK | + HAL_LL_I2C_RD_WRN_MASK + ); +} + +static hal_ll_err_t hal_ll_i2c_master_start( hal_ll_i2c_hw_specifics_map_t *map ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct(map->base); + uint16_t loop_index = HAL_LL_I2C_LOOP_INDEX; + + set_reg_bit( &(hal_ll_hw_reg->cr2), HAL_LL_I2C_CR2_START_BIT ); + + if ( check_reg_bit( &( hal_ll_hw_reg->isr ), HAL_LL_I2C_ARLO_BIT ) ) + return HAL_LL_I2C_MASTER_ARBITRATION_LOST; + + while ( loop_index-- ) + assembly(nop); + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static hal_ll_err_t hal_ll_i2c_master_stop( hal_ll_i2c_hw_specifics_map_t *map ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = ( hal_ll_i2c_base_handle_t* )map->base; + uint16_t time_counter = map->timeout; + uint32_t loop_index = HAL_LL_I2C_LOOP_INDEX; + + set_reg_bit( &(hal_ll_hw_reg->cr2), HAL_LL_I2C_CR2_STOP_BIT ); + + while ( !( hal_ll_hw_reg->isr & HAL_LL_I2C_ISR_STOPF_BIT ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_STOP; + } + } + + if ( map->timeout < HAL_LL_I2C_LOOP_INDEX ) { + while ( loop_index-- ) + assembly(nop); + } + + hal_ll_hw_reg->isr &= ~HAL_LL_I2C_ISR_STOPF_BIT; + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static hal_ll_pin_name_t hal_ll_i2c_master_check_pins( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_pin_id *index_list, hal_ll_i2c_master_handle_register_t *handle_map ) { + static const uint16_t scl_map_size = ( sizeof( hal_ll_i2c_scl_map ) / sizeof( hal_ll_i2c_pin_map_t ) ); + static const uint16_t sda_map_size = ( sizeof( hal_ll_i2c_sda_map ) / sizeof( hal_ll_i2c_pin_map_t ) ); + uint8_t hal_ll_module_id = 0; + uint8_t index_counter = 0; + uint16_t scl_index; + uint16_t sda_index; + + if ( (HAL_LL_PIN_NC == scl) || (HAL_LL_PIN_NC == sda) ) { + return HAL_LL_PIN_NC; + } + + for ( scl_index = 0; scl_index < scl_map_size; scl_index++ ) { + if ( hal_ll_i2c_scl_map[ scl_index ].pin == scl ) { + for ( sda_index = 0; sda_index < sda_map_size; sda_index++ ) { + if ( hal_ll_i2c_sda_map[ sda_index ].pin == sda ) { + if ( hal_ll_i2c_scl_map[ scl_index ].module_index == hal_ll_i2c_sda_map[ sda_index ].module_index ) { + // Get module number + hal_ll_module_id = hal_ll_i2c_scl_map[ scl_index ].module_index; + // Map pin names + index_list[hal_ll_module_id].pin_scl = scl_index; + index_list[hal_ll_module_id].pin_sda = sda_index; + + // Check if module is taken + if ( NULL == handle_map[ hal_ll_module_id ].hal_drv_i2c_master_handle ) { + return hal_ll_module_id; + } else if ( I2C_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static hal_ll_i2c_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof(hal_ll_i2c_master_handle_register_t)); + static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof(hal_ll_i2c_master_handle_register_t)); + + while( hal_ll_module_count-- ) { + if (hal_ll_i2c_get_base_from_hal_handle == hal_ll_i2c_hw_specifics_map[hal_ll_module_count].base) { + return &hal_ll_i2c_hw_specifics_map[hal_ll_module_count]; + } + } + + return &hal_ll_i2c_hw_specifics_map[hal_ll_module_error]; +} + +static void hal_ll_i2c_master_set_clock( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ) { + switch ( map->module_index ) + { + #if defined(I2C_MODULE_1) + case ( hal_ll_i2c_module_num(I2C_MODULE_1) ): + hal_ll_i2c1_set_clock( hal_ll_state ); + break; + #endif + default: + break; + } +} + +static void hal_ll_i2c_master_map_pins( uint8_t module_index, hal_ll_i2c_pin_id *index_list ) { + // Map new pins + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_scl.pin_name = hal_ll_i2c_scl_map[ index_list[module_index].pin_scl ].pin; + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_sda.pin_name = hal_ll_i2c_sda_map[ index_list[module_index].pin_sda ].pin; + // SCL and SDA could have different alternate function settings, hence save both AF values + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_scl.pin_af = hal_ll_i2c_scl_map[ index_list[module_index].pin_scl ].af; + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_sda.pin_af = hal_ll_i2c_sda_map[ index_list[module_index].pin_sda ].af; +} + +static void hal_ll_i2c_master_alternate_functions_set_state( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ) { + module_struct module; + + if( (map->pins.pin_scl.pin_name != HAL_LL_PIN_NC) && (map->pins.pin_sda.pin_name != HAL_LL_PIN_NC) ) { + module.pins[0] = VALUE( map->pins.pin_scl.pin_name, map->pins.pin_scl.pin_af ); + module.pins[1] = VALUE( map->pins.pin_sda.pin_name, map->pins.pin_sda.pin_af ); + module.pins[2] = GPIO_MODULE_STRUCT_END; + + module.configs[0] = HAL_LL_I2C_AF_CONFIG; + module.configs[1] = HAL_LL_I2C_AF_CONFIG; + module.configs[2] = GPIO_MODULE_STRUCT_END; + + hal_ll_gpio_module_struct_init( &module, hal_ll_state ); + } +} + +static uint32_t hal_ll_i2c_get_speed( hal_ll_i2c_hw_specifics_map_t *map ) { + if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_FAST ) { + if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_STANDARD ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_100K; + return HAL_LL_I2C_100K; + } else if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_FULL ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_400K; + return HAL_LL_I2C_400K; + } else if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_FAST ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_1M; + return HAL_LL_I2C_1M; + } else { + map->speed = HAL_LL_I2C_MASTER_SPEED_100K; + return HAL_LL_I2C_100K; + } + } else { + if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_100K ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_100K; + return HAL_LL_I2C_100K; + } else if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_400K ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_400K; + return HAL_LL_I2C_400K; + } else if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_1M ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_1M; + return HAL_LL_I2C_1M; + } else { + map->speed = HAL_LL_I2C_MASTER_SPEED_1M; + return HAL_LL_I2C_1M; + } + } +} + +static inline void hal_ll_i2c1_set_clock( bool hal_ll_state ) { + if ( hal_ll_state ) { + set_reg_bit( _RCC_APBENR1, HAL_LL_I2C1EN_BIT ); + set_reg_bit( _RCC_CCIPR, HAL_LL_I2C1SEL1_BIT ); + } else { + clear_reg_bit( _RCC_APBENR1, HAL_LL_I2C1EN_BIT ); + clear_reg_bit( _RCC_CCIPR, HAL_LL_I2C1SEL1_BIT ); + } +} + +static hal_ll_err_t hal_ll_i2c_hw_init( hal_ll_i2c_hw_specifics_map_t *map ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct(map->base); + uint16_t time_counter = map->timeout; + + clear_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_I2C_PE_BIT ); + while ( check_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_I2C_PE_BIT ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_INIT; + } + } + + hal_ll_hw_reg->cr1 &= HAL_LL_I2C_FILTERS_OFF; + + hal_ll_hw_reg->timingr = hal_ll_i2c_get_speed( map ); + + hal_ll_hw_reg->cr1 |= HAL_LL_I2C_CR1_RXTX_INT; + + set_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_I2C_PE_BIT ); + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static hal_ll_err_t hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_t *map ) { + hal_ll_i2c_master_set_clock( map, true ); + + return hal_ll_i2c_hw_init( map ); +} +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_160/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_160/CMakeLists.cmake new file mode 100644 index 000000000..e1210a75c --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_160/CMakeLists.cmake @@ -0,0 +1,9 @@ +if(${MCU_NAME} MATCHES "^STM32L4P5AE$|^STM32L4P5AG$|^STM32L4P5CE$|^STM32L4P5CG$|^STM32L4P5QE$|^STM32L4P5QG$|^STM32L4P5RE$|^STM32L4P5RG$|^STM32L4P5VE$|^STM32L4P5VG$|^STM32L4P5ZE$|^STM32L4P5ZG$") + set(i2c_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_i2c_master.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_160") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_160") + list(APPEND hal_ll_def_list "STM32L4xx") + list(APPEND hal_ll_def_list "STM32L4Pxx") + list(APPEND hal_ll_def_list "STM32L4P5xx") + set(i2c_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/i2c/hal_ll_i2c_pin_map/implementations/doc_ds_160") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_160/hal_ll_i2c_master.c b/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_160/hal_ll_i2c_master.c new file mode 100644 index 000000000..561232d84 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_160/hal_ll_i2c_master.c @@ -0,0 +1,978 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_i2c_master.c + * @brief I2C master HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_rcc.h" +#include "hal_ll_gpio.h" +#include "hal_ll_i2c_master.h" +#include "hal_ll_i2c_pin_map.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_i2c_master_handle_register_t hal_ll_module_state[I2C_MODULE_COUNT] = { (handle_t *)NULL, (handle_t *)NULL, false }; + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_i2c_get_module_state_address ((hal_ll_i2c_master_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_i2c_get_handle (hal_ll_i2c_master_handle_register_t *)hal_ll_i2c_get_module_state_address->hal_ll_i2c_master_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_i2c_get_base_struct(_handle) ((hal_ll_i2c_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_i2c_get_base_from_hal_handle ((hal_ll_i2c_hw_specifics_map_t *)((hal_ll_i2c_master_handle_register_t *)\ + (((hal_ll_i2c_master_handle_register_t *)(handle))->hal_ll_i2c_master_handle))->hal_ll_i2c_master_handle)->base + +/*!< @brief Default I2C bit-rate if no speed is set */ +#define HAL_LL_I2C_MASTER_SPEED_100K 100000UL +#define HAL_LL_I2C_MASTER_SPEED_400K 400000UL +#define HAL_LL_I2C_MASTER_SPEED_1M 1000000UL + +/*!< @brief Default pass count value upon reset */ +#define HAL_LL_I2C_DEFAULT_PASS_COUNT 0xFFFFU + +/*!< @brief Macro used for timeout */ +#define HAL_LL_I2C_LOOP_INDEX 10000U + +/*!< @brief Macros defining register bit location */ +#define HAL_LL_I2C1EN_BIT 21 +#define HAL_LL_I2C2EN_BIT 22 +#define HAL_LL_I2C3EN_BIT 23 +#define HAL_LL_I2C4EN_BIT 1 + +#define HAL_LL_I2C1SEL0_BIT 12 +#define HAL_LL_I2C1SEL1_BIT 13 +#define HAL_LL_I2C4SEL0_BIT 0 +#define HAL_LL_I2C4SEL1_BIT 1 + +#define HAL_LL_I2C_100K 0x30420F13 +#define HAL_LL_I2C_400K 0x10320309 +#define HAL_LL_I2C_1M 0x00200204 + +#define HAL_LL_I2C_PE_BIT 0 +#define HAL_LL_I2C_CR2_STOP_BIT 14 +#define HAL_LL_I2C_CR2_START_BIT 13 +#define HAL_LL_I2C_ISR_STOPF_BIT 5 +#define HAL_LL_I2C_ISR_BUSY_BIT 15 +#define HAL_LL_I2C_ARLO_BIT 9 +#define HAL_LL_I2C_RXNE_BIT 2 +#define HAL_LL_I2C_TXIS_BIT 1 +#define HAL_LL_I2C_TXE_BIT 0 + +/*!< @brief Macros defining register bit masks */ +#define HAL_LL_I2C_CR1_RXTX_INT 0x6 +#define HAL_LL_I2C_CR2_STOP 0x4000UL +#define HAL_LL_I2C_CR2_START 0x2000U +#define HAL_LL_I2C_CR2_SADD 0x3FFU +#define HAL_LL_I2C_CR2_NBYTES 0xFF0000UL +#define HAL_LL_I2C_CR2_RD_WRN 0x400U +#define HAL_LL_I2C_CR2_RELOAD 0x1000000UL +#define HAL_LL_I2C_CR2_AUTOEND 0x2000000UL +#define HAL_LL_I2C_FILTERS_OFF 0xFFFFE0FFUL +#define HAL_LL_I2C_SADD_MASK 0x3FFUL +#define HAL_LL_I2C_HEAD10R_MASK 0x1000UL +#define HAL_LL_I2C_NBYTES_MASK 0xFF0000UL +#define HAL_LL_I2C_RELOAD_MASK 0x1000000UL +#define HAL_LL_I2C_RD_WRN_MASK 0x400UL + +/*!< @brief Macros used for module pin checking */ +#define HAL_LL_I2C_SCL_PIN 0 +#define HAL_LL_I2C_SDA_PIN 1 +#define HAL_LL_I2C_MODULE_PIN_COUNT 2 + +/*!< @brief Macro used for setting pin alternate functions */ +#define HAL_LL_I2C_AF_CONFIG (GPIO_CFG_MODE_ALT_FUNCTION | GPIO_CFG_SPEED_HIGH | GPIO_CFG_OTYPE_OD) + +// -------------------------------------------------------------- PRIVATE TYPES +/*!< @brief I2C register structure */ +typedef struct +{ + hal_ll_base_addr_t cr1; + hal_ll_base_addr_t cr2; + hal_ll_base_addr_t oar1; + hal_ll_base_addr_t oar2; + hal_ll_base_addr_t timingr; + hal_ll_base_addr_t timeoutr; + hal_ll_base_addr_t isr; + hal_ll_base_addr_t icr; + hal_ll_base_addr_t pecr; + hal_ll_base_addr_t rxdr; + hal_ll_base_addr_t txdr; +} hal_ll_i2c_base_handle_t; + +/*!< @brief I2C hw specific structure */ +typedef struct +{ + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + hal_ll_i2c_pins_t pins; + uint32_t speed; + uint8_t address; + uint16_t timeout; +} hal_ll_i2c_hw_specifics_map_t; + +/*!< @brief I2C hw specific module values */ +typedef struct +{ + uint16_t pin_scl; + uint16_t pin_sda; +} hal_ll_i2c_pin_id; + +/*!< @brief I2C hw specific error values */ +typedef enum +{ + HAL_LL_I2C_MASTER_SUCCESS = 0, + HAL_LL_I2C_MASTER_WRONG_PINS, + HAL_LL_I2C_MASTER_MODULE_ERROR, + + HAL_LL_I2C_MASTER_ERROR = (-1) +} hal_ll_i2c_master_err_t; + +/*!< @brief I2C end mode selection values */ +typedef enum +{ + HAL_LL_I2C_MASTER_END_MODE_RESTART = 0, + HAL_LL_I2C_MASTER_END_MODE_STOP, + HAL_LL_I2C_MASTER_WRITE_THEN_READ +} hal_ll_i2c_master_end_mode_t; + +/*!< @brief I2C timeout error values */ +typedef enum +{ + HAL_LL_I2C_MASTER_TIMEOUT_START = 1300, + HAL_LL_I2C_MASTER_TIMEOUT_STOP, + HAL_LL_I2C_MASTER_TIMEOUT_WRITE, + HAL_LL_I2C_MASTER_TIMEOUT_READ, + HAL_LL_I2C_MASTER_ARBITRATION_LOST, + HAL_LL_I2C_MASTER_TIMEOUT_INIT +} hal_ll_i2c_master_timeout_t; + +/** + * @brief Enum containing predefined module standard speed values. + * + * Enum values: + * HAL_LL_I2C_MASTER_SPEED_STANDARD -- Speed set at 100K + * HAL_LL_I2C_MASTER_SPEED_FULL -- Speed set at 400K + * HAL_LL_I2C_MASTER_SPEED_FAST -- Speed set at 1M + */ +typedef enum +{ + HAL_LL_I2C_MASTER_SPEED_STANDARD = 0, + HAL_LL_I2C_MASTER_SPEED_FULL, + HAL_LL_I2C_MASTER_SPEED_FAST +} hal_ll_i2c_master_speed_t; + +// ------------------------------------------------------------------ VARIABLES +/*!< @brief I2C hardware specific info */ +static hal_ll_i2c_hw_specifics_map_t hal_ll_i2c_hw_specifics_map[] = +{ + #ifdef I2C_MODULE_1 + {HAL_LL_I2C1_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_1), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, + #endif + #ifdef I2C_MODULE_2 + {HAL_LL_I2C2_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_2), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, + #endif + #ifdef I2C_MODULE_3 + {HAL_LL_I2C3_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_3), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, + #endif + #ifdef I2C_MODULE_4 + {HAL_LL_I2C4_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_4), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, + #endif + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, 0, 0} +}; + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_i2c_master_handle_register_t *low_level_handle; +static volatile hal_ll_i2c_hw_specifics_map_t *hal_ll_i2c_hw_specifics_map_local; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Check if pins are adequate. + * + * Checks scl and sda pins the user has passed with pre-defined + * pins in scl and sda maps. Take into consideration that module + * index numbers have to be the same for both pins. + * + * @param[in] scl - SCL pre-defined pin name. + * @param[in] sda - SDA pre-defined pin name. + * @param[in] *index_list - Index list address + * @return hal_ll_pin_name_t Module index based on pins. + * + * Returns pre-defined module index from pin maps, if pins + * are adequate. + */ +static hal_ll_pin_name_t hal_ll_i2c_master_check_pins( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_pin_id *index_list, hal_ll_i2c_master_handle_register_t *handle_map ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_i2c_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_i2c_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_i2c_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Get adequate I2C bit-rate value. + * + * Returns one of pre-defined bit-rate values, + * or the closest bit-rate based on bit_rate + * value passed to the function. + * + * @param[in] bit_rate - I2C bit rate. + * @return uint32_t Adequate bit-rate value. + * + * Returns adequate value to be latter written into bare metal register address. + * Take into consideration that this returns a predefined value. + * + * HAL_LL_I2C_MASTER_SPEED_100K -- 100Kbit/s + * HAL_LL_I2C_MASTER_SPEED_400K -- 400Kbit/s + * HAL_LL_I2C_MASTER_SPEED_1M -- 1Mbit/s + * HAL_LL_I2C_MASTER_SPEED_3M2 -- 3.2Mbit/s + */ +static uint32_t hal_ll_i2c_get_speed( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Enable clock for I2C1 module on hardware level. + * + * Initializes I2C1 module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] hal_ll_state - True/False -- Init/De-init + * + * @return None + */ +static inline void hal_ll_i2c1_set_clock( bool hal_ll_state ); + +/** + * @brief Enable clock for I2C2 module on hardware level. + * + * Initializes I2C2 module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] hal_ll_state - True/False -- Init/De-init + * + * @return None + */ +static inline void hal_ll_i2c2_set_clock( bool hal_ll_state ); + +/** + * @brief Enable clock for I2C3 module on hardware level. + * + * Initializes I2C3 module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] hal_ll_state - True/False -- Init/De-init + * + * @return None + */ +static inline void hal_ll_i2c3_set_clock( bool hal_ll_state ); + +/** + * @brief Enable clock for I2C4 module on hardware level. + * + * Initializes I2C4 module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] hal_ll_state - True/False -- Init/De-init + * + * @return None + */ +static inline void hal_ll_i2c4_set_clock( bool hal_ll_state ); + +/** + * @brief Enable clock for I2C module on hardware level. + * + * Initializes I2C module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_stat - True(enable clock)/False(disable clock). + * + * @return None + */ +static void hal_ll_i2c_master_set_clock( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Initialize I2C module on hardware level. + * + * Initializes I2C module on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] map - Object specific context handler. + * @return hal_ll_err_t Module specific return values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_hw_init( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * I2C SCL and SDA pins. + * + * @param[in] module_index I2C HW module index -- 0,1,2... + * @param[in] *index_list Array with SCL and SDA map index values + * and module number + * + * @return None + */ +static void hal_ll_i2c_master_map_pins( uint8_t module_index, hal_ll_i2c_pin_id *index_list ); + +/** + * @brief Sets I2C pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if I2C is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_state - Init/De-init + * + * @return None + */ +static void hal_ll_i2c_master_alternate_functions_set_state( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Full I2C module initialization procedure. + * + * Initializes I2C module on hardware level, based on beforehand + * set configuration and module handler. Sets adequate pin alternate functions. + * Initializes module clock. + * + * @param[in] map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Configure I2C module for data transfer. + * + * @param[in] hal_ll_hw_reg - I2C module base address. + * @param[in] config - I2C config bits. + * @return void None. + */ +static void hal_ll_i2c_master_configure_transfer( hal_ll_i2c_base_handle_t *hal_ll_hw_reg, uint32_t config ); + +/** + * @brief Reset value of I2C CR2 register. + * + * @param[in] hal_ll_hw_reg - I2C module base address. + * @returnl none + */ +static void hal_ll_i2c_master_reset_cr2( hal_ll_i2c_base_handle_t *hal_ll_hw_reg ); + +/** + * @brief Generates start signal on I2C bus. + * + * Generates a start signal on the I2C bus. + * + * @param[in] map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_master_start( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Generates stop signal on I2C bus. + * + * Generates a stop signal on the I2C bus. + * + * @param[in] map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_master_stop( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Perform a read on the I2C bus. + * + * Initializes I2C module on hardware level, if not initialized beforehand + * and continues to perform a read operation on the bus. + * + * @param[in] map - Object specific context handler. + * @param[in] readDatabuf - Pointer to data buffer. + * @param[in] lenReadData - Number of data to be read. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *read_data_buf, size_t len_read_data, hal_ll_i2c_master_end_mode_t mode ); + +/** + * @brief Perform a write on the I2C bus. + * + * Initializes I2C module on hardware level, if not initialized beforehand + * and continues to perform a write operation on the bus. + * + * @param[in] map - Object specific context handler. + * @param[in] writeDatabuf - Pointer to data buffer. + * @param[in] lenWriteData - Number of data to be written. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *write_data_buf, size_t len_write_data, hal_ll_i2c_master_end_mode_t mode ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_i2c_master_register_handle( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_master_handle_register_t *handle_map, uint8_t *hal_module_id ) { + + hal_ll_i2c_pin_id index_list[I2C_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + uint16_t pin_check_result; + + // Check if pins are valid + if ( (pin_check_result = hal_ll_i2c_master_check_pins( scl, sda, &index_list, handle_map )) == HAL_LL_PIN_NC ) { + return HAL_LL_I2C_MASTER_WRONG_PINS; + }; + + if ( (hal_ll_i2c_hw_specifics_map[pin_check_result].pins.pin_scl.pin_name != scl) || + (hal_ll_i2c_hw_specifics_map[pin_check_result].pins.pin_sda.pin_name != sda) ) + { + hal_ll_i2c_master_alternate_functions_set_state( &hal_ll_i2c_hw_specifics_map[ pin_check_result ], false ); + + hal_ll_i2c_master_map_pins( pin_check_result, &index_list ); + + hal_ll_i2c_master_alternate_functions_set_state( &hal_ll_i2c_hw_specifics_map[ pin_check_result ], true ); + + handle_map[pin_check_result].init_ll_state = false; + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[pin_check_result].hal_ll_i2c_master_handle = (handle_t *)&hal_ll_i2c_hw_specifics_map[pin_check_result].base; + + handle_map[pin_check_result].hal_ll_i2c_master_handle = (handle_t *)&hal_ll_module_state[pin_check_result].hal_ll_i2c_master_handle; + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_i2c( handle_t *handle ) { + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + hal_ll_i2c_master_handle_register_t *hal_handle = (hal_ll_i2c_master_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_i2c_hw_specifics_map_local->module_index; + + hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_local ); + + hal_ll_module_state[pin_check_result].hal_ll_i2c_master_handle = (handle_t *)&hal_ll_i2c_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_i2c_master_set_speed( handle_t *handle, uint32_t speed ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + low_level_handle->init_ll_state = false; + + hal_ll_i2c_hw_specifics_map_local->speed = speed; + + if ( hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_local ) != HAL_LL_I2C_MASTER_SUCCESS ) { + return HAL_LL_I2C_MASTER_TIMEOUT_INIT; + } + + low_level_handle->init_ll_state = true; + + return hal_ll_i2c_hw_specifics_map_local->speed; +} + +void hal_ll_i2c_master_set_timeout( handle_t *handle, uint16_t timeout ) { + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + if( hal_ll_i2c_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + hal_ll_i2c_hw_specifics_map_local->timeout = timeout; + } +} + +void hal_ll_i2c_master_set_slave_address( handle_t *handle, uint8_t addr ) { + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + if( hal_ll_i2c_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + hal_ll_i2c_hw_specifics_map_local->address = addr; + } +} + +hal_ll_err_t hal_ll_i2c_master_read( handle_t *handle, uint8_t *read_data_buf, size_t len_read_data ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + return hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_local, read_data_buf, len_read_data, HAL_LL_I2C_MASTER_END_MODE_STOP ); +} + +hal_ll_err_t hal_ll_i2c_master_write( handle_t *handle, uint8_t *write_data_buf, size_t len_write_data ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + return hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_local, write_data_buf, len_write_data, HAL_LL_I2C_MASTER_END_MODE_STOP ); +} + +hal_ll_err_t hal_ll_i2c_master_write_then_read( handle_t *handle, uint8_t *write_data_buf, size_t len_write_data, uint8_t *read_data_buf, size_t len_read_data ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + if( hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_local, write_data_buf, len_write_data, HAL_LL_I2C_MASTER_WRITE_THEN_READ ) != NULL ) { + return HAL_LL_I2C_MASTER_TIMEOUT_WRITE; + } + + /** + * @note Wait for drivers to set-up + * correctly. + **/ + #ifdef __TFT_RESISTIVE_TSC2003__ + Delay_22us(); + #endif + + if( hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_local, read_data_buf, len_read_data, HAL_LL_I2C_MASTER_WRITE_THEN_READ ) != NULL ) { + return HAL_LL_I2C_MASTER_TIMEOUT_READ; + } + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +void hal_ll_i2c_master_close( handle_t *handle ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + if( low_level_handle->hal_ll_i2c_master_handle != NULL ) { + low_level_handle->hal_ll_i2c_master_handle = NULL; + low_level_handle->hal_drv_i2c_master_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_i2c_hw_specifics_map_local->address = 0; + hal_ll_i2c_hw_specifics_map_local->timeout = HAL_LL_I2C_DEFAULT_PASS_COUNT; + hal_ll_i2c_hw_specifics_map_local->speed = HAL_LL_I2C_MASTER_SPEED_100K; + + hal_ll_i2c_master_set_clock(hal_ll_i2c_hw_specifics_map_local, true); + hal_ll_i2c_master_alternate_functions_set_state( hal_ll_i2c_hw_specifics_map_local, false ); + hal_ll_i2c_master_set_clock(hal_ll_i2c_hw_specifics_map_local, false); + + hal_ll_i2c_hw_specifics_map_local->pins.pin_scl.pin_name = HAL_LL_PIN_NC; + hal_ll_i2c_hw_specifics_map_local->pins.pin_sda.pin_name = HAL_LL_PIN_NC; + hal_ll_i2c_hw_specifics_map_local->pins.pin_scl.pin_af = 0; + hal_ll_i2c_hw_specifics_map_local->pins.pin_sda.pin_af = 0; + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static hal_ll_err_t hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *read_data_buf, size_t len_read_data, hal_ll_i2c_master_end_mode_t mode ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct(map->base); + uint16_t time_counter = map->timeout; + size_t transfer_counter = NULL; + uint8_t status = NULL; + + /** + * @note When R/W = 0, the input sample acquisition period starts + * on the falling edge of SCL once the C0 bit of the command + * byte has been latched, and ends when a Stop or + * repeated Start condition has been issued. + **/ + #ifdef __TFT_RESISTIVE_TSC2003__ + Delay_1ms(); + #endif + + hal_ll_i2c_master_configure_transfer ( map->base, + ( map->address << 1 & HAL_LL_I2C_CR2_SADD ) | + ( len_read_data << 16 & HAL_LL_I2C_CR2_NBYTES ) | + HAL_LL_I2C_CR2_RD_WRN | + HAL_LL_I2C_CR2_START + ); + + for ( transfer_counter; transfer_counter < len_read_data; transfer_counter++ ) { + while ( !( check_reg_bit( &( hal_ll_hw_reg->isr ), HAL_LL_I2C_RXNE_BIT ) ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_READ; + } + } + read_data_buf[ transfer_counter ] = hal_ll_hw_reg->rxdr; + } + + if ( ( mode == HAL_LL_I2C_MASTER_END_MODE_STOP ) || ( mode == HAL_LL_I2C_MASTER_WRITE_THEN_READ ) ) { + status = hal_ll_i2c_master_stop( map ); + } else { + status = hal_ll_i2c_master_start( map ); + } + + if( status != HAL_LL_I2C_MASTER_SUCCESS ) { + return status; + } + + hal_ll_i2c_master_reset_cr2( hal_ll_hw_reg ); + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static hal_ll_err_t hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *write_data_buf, size_t len_write_data, hal_ll_i2c_master_end_mode_t mode ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct(map->base); + uint16_t time_counter = map->timeout; + size_t transfer_counter = NULL; + uint8_t status = NULL; + + hal_ll_i2c_master_configure_transfer ( map->base, + ( map->address << 1 & HAL_LL_I2C_CR2_SADD ) | + ( len_write_data << 16 & HAL_LL_I2C_CR2_NBYTES ) | + !HAL_LL_I2C_CR2_RD_WRN | + HAL_LL_I2C_CR2_START + ); + + for ( transfer_counter; transfer_counter < len_write_data; transfer_counter++ ) + { + while ( !( check_reg_bit( &( hal_ll_hw_reg->isr ), HAL_LL_I2C_TXIS_BIT ) ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_WRITE; + } + } + hal_ll_hw_reg->txdr = write_data_buf[ transfer_counter ]; + } + + time_counter = map->timeout; + while ( !( check_reg_bit( &( hal_ll_hw_reg->isr ), HAL_LL_I2C_TXE_BIT ) ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_WRITE; + } + } + + if ( mode == HAL_LL_I2C_MASTER_END_MODE_STOP ) + { + hal_ll_i2c_master_stop( map ); + } + + hal_ll_i2c_master_reset_cr2( hal_ll_hw_reg ); + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static void hal_ll_i2c_master_configure_transfer( hal_ll_i2c_base_handle_t *hal_ll_hw_reg, uint32_t config ) { + uint32_t reg = 0; + + // Clear last set slave address + hal_ll_hw_reg->cr2 &= ~HAL_LL_I2C_CR2_SADD; + + reg = hal_ll_hw_reg->cr2; + reg &= ~( uint32_t )( + ( HAL_LL_I2C_CR2_SADD ) | + ( HAL_LL_I2C_CR2_NBYTES ) | + ( HAL_LL_I2C_CR2_RELOAD ) | + ( HAL_LL_I2C_CR2_AUTOEND ) | + ( HAL_LL_I2C_CR2_RD_WRN ) | + ( HAL_LL_I2C_CR2_START ) | + ( HAL_LL_I2C_CR2_STOP ) + ); + + reg |= config; + hal_ll_hw_reg->cr2 = reg; +} + +static void hal_ll_i2c_master_reset_cr2( hal_ll_i2c_base_handle_t *hal_ll_hw_reg ) { + hal_ll_hw_reg->cr2 &= ~( uint32_t ) + ( + HAL_LL_I2C_SADD_MASK | + HAL_LL_I2C_HEAD10R_MASK | + HAL_LL_I2C_NBYTES_MASK | + HAL_LL_I2C_RELOAD_MASK | + HAL_LL_I2C_RD_WRN_MASK + ); +} + +static hal_ll_err_t hal_ll_i2c_master_start( hal_ll_i2c_hw_specifics_map_t *map ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct(map->base); + uint16_t loop_index = HAL_LL_I2C_LOOP_INDEX; + + set_reg_bit( &(hal_ll_hw_reg->cr2), HAL_LL_I2C_CR2_START_BIT ); + + if ( check_reg_bit( &( hal_ll_hw_reg->isr ), HAL_LL_I2C_ARLO_BIT ) ) + return HAL_LL_I2C_MASTER_ARBITRATION_LOST; + + while ( loop_index-- ) + assembly(nop); + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static hal_ll_err_t hal_ll_i2c_master_stop( hal_ll_i2c_hw_specifics_map_t *map ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = ( hal_ll_i2c_base_handle_t* )map->base; + uint16_t time_counter = map->timeout; + uint32_t loop_index = HAL_LL_I2C_LOOP_INDEX; + + set_reg_bit( &(hal_ll_hw_reg->cr2), HAL_LL_I2C_CR2_STOP_BIT ); + + while ( !( hal_ll_hw_reg->isr & HAL_LL_I2C_ISR_STOPF_BIT ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_STOP; + } + } + + if ( map->timeout < HAL_LL_I2C_LOOP_INDEX ) { + while ( loop_index-- ) + assembly(nop); + } + + hal_ll_hw_reg->isr &= ~HAL_LL_I2C_ISR_STOPF_BIT; + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static hal_ll_pin_name_t hal_ll_i2c_master_check_pins( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_pin_id *index_list, hal_ll_i2c_master_handle_register_t *handle_map ) { + static const uint16_t scl_map_size = ( sizeof( hal_ll_i2c_scl_map ) / sizeof( hal_ll_i2c_pin_map_t ) ); + static const uint16_t sda_map_size = ( sizeof( hal_ll_i2c_sda_map ) / sizeof( hal_ll_i2c_pin_map_t ) ); + uint8_t hal_ll_module_id = 0; + uint8_t index_counter = 0; + uint16_t scl_index; + uint16_t sda_index; + + if ( (HAL_LL_PIN_NC == scl) || (HAL_LL_PIN_NC == sda) ) { + return HAL_LL_PIN_NC; + } + + for ( scl_index = 0; scl_index < scl_map_size; scl_index++ ) { + if ( hal_ll_i2c_scl_map[ scl_index ].pin == scl ) { + for ( sda_index = 0; sda_index < sda_map_size; sda_index++ ) { + if ( hal_ll_i2c_sda_map[ sda_index ].pin == sda ) { + if ( hal_ll_i2c_scl_map[ scl_index ].module_index == hal_ll_i2c_sda_map[ sda_index ].module_index ) { + // Get module number + hal_ll_module_id = hal_ll_i2c_scl_map[ scl_index ].module_index; + // Map pin names + index_list[hal_ll_module_id].pin_scl = scl_index; + index_list[hal_ll_module_id].pin_sda = sda_index; + + // Check if module is taken + if ( NULL == handle_map[ hal_ll_module_id ].hal_drv_i2c_master_handle ) { + return hal_ll_module_id; + } else if ( I2C_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static hal_ll_i2c_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof(hal_ll_i2c_master_handle_register_t)); + static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof(hal_ll_i2c_master_handle_register_t)); + + while( hal_ll_module_count-- ) { + if (hal_ll_i2c_get_base_from_hal_handle == hal_ll_i2c_hw_specifics_map[hal_ll_module_count].base) { + return &hal_ll_i2c_hw_specifics_map[hal_ll_module_count]; + } + } + + return &hal_ll_i2c_hw_specifics_map[hal_ll_module_error]; +} + +static void hal_ll_i2c_master_set_clock( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ) { + switch ( map->module_index ) + { + #if defined(I2C_MODULE_1) + case ( hal_ll_i2c_module_num(I2C_MODULE_1) ): + hal_ll_i2c1_set_clock( hal_ll_state ); + break; + #endif + #if defined(I2C_MODULE_2) + case ( hal_ll_i2c_module_num(I2C_MODULE_2) ): + hal_ll_i2c2_set_clock( hal_ll_state ); + break; + #endif + #if defined(I2C_MODULE_3) + case ( hal_ll_i2c_module_num(I2C_MODULE_3) ): + hal_ll_i2c3_set_clock( hal_ll_state ); + break; + #endif + #if defined(I2C_MODULE_4) + case ( hal_ll_i2c_module_num(I2C_MODULE_4) ): + hal_ll_i2c4_set_clock( hal_ll_state ); + break; + #endif + default: + break; + } +} + +static void hal_ll_i2c_master_map_pins( uint8_t module_index, hal_ll_i2c_pin_id *index_list ) { + // Map new pins + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_scl.pin_name = hal_ll_i2c_scl_map[ index_list[module_index].pin_scl ].pin; + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_sda.pin_name = hal_ll_i2c_sda_map[ index_list[module_index].pin_sda ].pin; + // SCL and SDA could have different alternate function settings, hence save both AF values + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_scl.pin_af = hal_ll_i2c_scl_map[ index_list[module_index].pin_scl ].af; + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_sda.pin_af = hal_ll_i2c_sda_map[ index_list[module_index].pin_sda ].af; +} + +static void hal_ll_i2c_master_alternate_functions_set_state( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ) { + module_struct module; + + if( (map->pins.pin_scl.pin_name != HAL_LL_PIN_NC) && (map->pins.pin_sda.pin_name != HAL_LL_PIN_NC) ) { + module.pins[0] = VALUE( map->pins.pin_scl.pin_name, map->pins.pin_scl.pin_af ); + module.pins[1] = VALUE( map->pins.pin_sda.pin_name, map->pins.pin_sda.pin_af ); + module.pins[2] = GPIO_MODULE_STRUCT_END; + + module.configs[0] = HAL_LL_I2C_AF_CONFIG; + module.configs[1] = HAL_LL_I2C_AF_CONFIG; + module.configs[2] = GPIO_MODULE_STRUCT_END; + + hal_ll_gpio_module_struct_init( &module, hal_ll_state ); + } +} + +static uint32_t hal_ll_i2c_get_speed( hal_ll_i2c_hw_specifics_map_t *map ) { + if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_FAST ) { + if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_STANDARD ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_100K; + return HAL_LL_I2C_100K; + } else if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_FULL ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_400K; + return HAL_LL_I2C_400K; + } else if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_FAST ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_1M; + return HAL_LL_I2C_1M; + } else { + map->speed = HAL_LL_I2C_MASTER_SPEED_100K; + return HAL_LL_I2C_100K; + } + } else { + if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_100K ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_100K; + return HAL_LL_I2C_100K; + } else if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_400K ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_400K; + return HAL_LL_I2C_400K; + } else if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_1M ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_1M; + return HAL_LL_I2C_1M; + } else { + map->speed = HAL_LL_I2C_MASTER_SPEED_1M; + return HAL_LL_I2C_1M; + } + } +} + +static inline void hal_ll_i2c1_set_clock( bool hal_ll_state ) { + if ( hal_ll_state ) { + set_reg_bit( _RCC_APB1ENR1, HAL_LL_I2C1EN_BIT ); + set_reg_bit( _RCC_CCIPR, HAL_LL_I2C1SEL1_BIT ); + } else { + clear_reg_bit( _RCC_APB1ENR1, HAL_LL_I2C1EN_BIT ); + clear_reg_bit( _RCC_CCIPR, HAL_LL_I2C1SEL1_BIT ); + } +} + +static inline void hal_ll_i2c2_set_clock( bool hal_ll_state ) { + if ( hal_ll_state ) { + set_reg_bit( _RCC_APB1ENR1, HAL_LL_I2C2EN_BIT ); + } else { + clear_reg_bit( _RCC_APB1ENR1, HAL_LL_I2C2EN_BIT ); + } +} + +static inline void hal_ll_i2c3_set_clock( bool hal_ll_state ) { + if ( hal_ll_state ) { + set_reg_bit( _RCC_APB1ENR1, HAL_LL_I2C3EN_BIT ); + } else { + clear_reg_bit( _RCC_APB1ENR1, HAL_LL_I2C3EN_BIT ); + } +} + +static inline void hal_ll_i2c4_set_clock( bool hal_ll_state ) { + if ( hal_ll_state ) { + set_reg_bit( _RCC_APB1ENR2, HAL_LL_I2C4EN_BIT ); + set_reg_bit( _RCC_CCIPR2, HAL_LL_I2C4SEL1_BIT ); + } else { + clear_reg_bit( _RCC_APB1ENR2, HAL_LL_I2C4EN_BIT ); + clear_reg_bit( _RCC_CCIPR2, HAL_LL_I2C4SEL1_BIT ); + } +} + +static hal_ll_err_t hal_ll_i2c_hw_init( hal_ll_i2c_hw_specifics_map_t *map ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct(map->base); + uint16_t time_counter = map->timeout; + + clear_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_I2C_PE_BIT ); + while ( check_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_I2C_PE_BIT ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_INIT; + } + } + + hal_ll_hw_reg->cr1 &= HAL_LL_I2C_FILTERS_OFF; + + hal_ll_hw_reg->timingr = hal_ll_i2c_get_speed( map ); + + hal_ll_hw_reg->cr1 |= HAL_LL_I2C_CR1_RXTX_INT; + + set_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_I2C_PE_BIT ); + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static hal_ll_err_t hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_t *map ) { + hal_ll_i2c_master_set_clock( map, true ); + + return hal_ll_i2c_hw_init( map ); +} +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_161/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_161/CMakeLists.cmake new file mode 100644 index 000000000..2ded736c4 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_161/CMakeLists.cmake @@ -0,0 +1,9 @@ +if(${MCU_NAME} MATCHES "^STM32L4Q5AG$|^STM32L4Q5CG$|^STM32L4Q5QG$|^STM32L4Q5RG$|^STM32L4Q5VG$|^STM32L4Q5ZG$") + set(i2c_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_i2c_master.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_161") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_161") + list(APPEND hal_ll_def_list "STM32L4xx") + list(APPEND hal_ll_def_list "STM32L4Qxx") + list(APPEND hal_ll_def_list "STM32L4Q5xx") + set(i2c_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/i2c/hal_ll_i2c_pin_map/implementations/doc_ds_161") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_161/hal_ll_i2c_master.c b/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_161/hal_ll_i2c_master.c new file mode 100644 index 000000000..3bb88c40b --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_161/hal_ll_i2c_master.c @@ -0,0 +1,1005 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_i2c_master.c + * @brief I2C master HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_rcc.h" +#include "hal_ll_gpio.h" +#include "hal_ll_i2c_master.h" +#include "hal_ll_i2c_pin_map.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_i2c_master_handle_register_t hal_ll_module_state[I2C_MODULE_COUNT] = { (handle_t *)NULL, (handle_t *)NULL, false }; + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_i2c_get_module_state_address ((hal_ll_i2c_master_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_i2c_get_handle (hal_ll_i2c_master_handle_register_t *)hal_ll_i2c_get_module_state_address->hal_ll_i2c_master_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_i2c_get_base_struct(_handle) ((hal_ll_i2c_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_i2c_get_base_from_hal_handle ((hal_ll_i2c_hw_specifics_map_t *)((hal_ll_i2c_master_handle_register_t *)\ + (((hal_ll_i2c_master_handle_register_t *)(handle))->hal_ll_i2c_master_handle))->hal_ll_i2c_master_handle)->base + +/*!< @brief Default I2C bit-rate if no speed is set */ +#define HAL_LL_I2C_MASTER_SPEED_100K 100000UL +#define HAL_LL_I2C_MASTER_SPEED_400K 400000UL +#define HAL_LL_I2C_MASTER_SPEED_1M 1000000UL + +/*!< @brief Default pass count value upon reset */ +#define HAL_LL_I2C_DEFAULT_PASS_COUNT 0xFFFFU + +/*!< @brief Macro used for timeout */ +#define HAL_LL_I2C_LOOP_INDEX 10000U + +/*!< @brief Macros defining register bit location */ +#define HAL_LL_I2C1EN_BIT 21 + +#define HAL_LL_I2C2EN_BIT 22 + +#define HAL_LL_I2C3EN_BIT 23 + +#define HAL_LL_I2C4EN_BIT 1 + +#define HAL_LL_I2C1SEL0_BIT 12 + +#define HAL_LL_I2C1SEL1_BIT 13 + +#define HAL_LL_I2C4SEL0_BIT 0 + +#define HAL_LL_I2C4SEL1_BIT 1 + + + + +#define HAL_LL_I2C_100K 0x30420F13 //?????????????????? +#define HAL_LL_I2C_400K 0x10320309 //?????????????????? +#define HAL_LL_I2C_1M 0x00200204 //?????????????????? + +#define HAL_LL_I2C_PE_BIT 0 +#define HAL_LL_I2C_CR2_STOP_BIT 14 +#define HAL_LL_I2C_CR2_START_BIT 13 +#define HAL_LL_I2C_ISR_STOPF_BIT 5 +#define HAL_LL_I2C_ISR_BUSY_BIT 15 +#define HAL_LL_I2C_ARLO_BIT 9 +#define HAL_LL_I2C_RXNE_BIT 2 +#define HAL_LL_I2C_TXIS_BIT 1 +#define HAL_LL_I2C_TXE_BIT 0 + +/*!< @brief Macros defining register bit masks */ +#define HAL_LL_I2C_CR1_RXTX_INT 0x6 +#define HAL_LL_I2C_CR2_STOP 0x4000UL +#define HAL_LL_I2C_CR2_START 0x2000U +#define HAL_LL_I2C_CR2_SADD 0x3FFU +#define HAL_LL_I2C_CR2_NBYTES 0xFF0000UL +#define HAL_LL_I2C_CR2_RD_WRN 0x400U +#define HAL_LL_I2C_CR2_RELOAD 0x1000000UL +#define HAL_LL_I2C_CR2_AUTOEND 0x2000000UL +#define HAL_LL_I2C_FILTERS_OFF 0xFFFFE0FFUL +#define HAL_LL_I2C_SADD_MASK 0x3FFUL +#define HAL_LL_I2C_HEAD10R_MASK 0x1000UL +#define HAL_LL_I2C_NBYTES_MASK 0xFF0000UL +#define HAL_LL_I2C_RELOAD_MASK 0x1000000UL +#define HAL_LL_I2C_RD_WRN_MASK 0x400UL + +/*!< @brief Macros used for module pin checking */ +#define HAL_LL_I2C_SCL_PIN 0 +#define HAL_LL_I2C_SDA_PIN 1 +#define HAL_LL_I2C_MODULE_PIN_COUNT 2 + +/*!< @brief Macro used for setting pin alternate functions */ +#define HAL_LL_I2C_AF_CONFIG (GPIO_CFG_MODE_ALT_FUNCTION | GPIO_CFG_SPEED_HIGH | GPIO_CFG_OTYPE_OD) + +// -------------------------------------------------------------- PRIVATE TYPES +/*!< @brief I2C register structure */ +typedef struct +{ + hal_ll_base_addr_t cr1; + hal_ll_base_addr_t cr2; + hal_ll_base_addr_t oar1; + hal_ll_base_addr_t oar2; + hal_ll_base_addr_t timingr; + hal_ll_base_addr_t timeoutr; + hal_ll_base_addr_t isr; + hal_ll_base_addr_t icr; + hal_ll_base_addr_t pecr; + hal_ll_base_addr_t rxdr; + hal_ll_base_addr_t txdr; + +} hal_ll_i2c_base_handle_t; + +/*!< @brief I2C hw specific structure */ +typedef struct +{ + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + hal_ll_i2c_pins_t pins; + uint32_t speed; + uint8_t address; + uint16_t timeout; +} hal_ll_i2c_hw_specifics_map_t; + +/*!< @brief I2C hw specific module values */ +typedef struct +{ + uint16_t pin_scl; + uint16_t pin_sda; +} hal_ll_i2c_pin_id; + +/*!< @brief I2C hw specific error values */ +typedef enum +{ + HAL_LL_I2C_MASTER_SUCCESS = 0, + HAL_LL_I2C_MASTER_WRONG_PINS, + HAL_LL_I2C_MASTER_MODULE_ERROR, + + HAL_LL_I2C_MASTER_ERROR = (-1) +} hal_ll_i2c_master_err_t; + +/*!< @brief I2C end mode selection values */ +typedef enum +{ + HAL_LL_I2C_MASTER_END_MODE_RESTART = 0, + HAL_LL_I2C_MASTER_END_MODE_STOP, + HAL_LL_I2C_MASTER_WRITE_THEN_READ +} hal_ll_i2c_master_end_mode_t; + +/*!< @brief I2C timeout error values */ +typedef enum +{ + HAL_LL_I2C_MASTER_TIMEOUT_START = 1300, + HAL_LL_I2C_MASTER_TIMEOUT_STOP, + HAL_LL_I2C_MASTER_TIMEOUT_WRITE, + HAL_LL_I2C_MASTER_TIMEOUT_READ, + HAL_LL_I2C_MASTER_ARBITRATION_LOST, + HAL_LL_I2C_MASTER_TIMEOUT_INIT +} hal_ll_i2c_master_timeout_t; + +/** + * @brief Enum containing predefined module standard speed values. + * + * Enum values: + * HAL_LL_I2C_MASTER_SPEED_STANDARD -- Speed set at 100K + * HAL_LL_I2C_MASTER_SPEED_FULL -- Speed set at 400K + * HAL_LL_I2C_MASTER_SPEED_FAST -- Speed set at 1M + */ +typedef enum +{ + HAL_LL_I2C_MASTER_SPEED_STANDARD = 0, + HAL_LL_I2C_MASTER_SPEED_FULL, + HAL_LL_I2C_MASTER_SPEED_FAST +} hal_ll_i2c_master_speed_t; + +// ------------------------------------------------------------------ VARIABLES +/*!< @brief I2C hardware specific info */ +static hal_ll_i2c_hw_specifics_map_t hal_ll_i2c_hw_specifics_map[] = +{ + #ifdef I2C_MODULE_1 + {HAL_LL_I2C1_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_1), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, + #endif + + #ifdef I2C_MODULE_2 + {HAL_LL_I2C2_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_2), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, + #endif + + #ifdef I2C_MODULE_3 + {HAL_LL_I2C3_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_3), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, + #endif + + #ifdef I2C_MODULE_4 + {HAL_LL_I2C4_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_4), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, + #endif + + + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, 0, 0} +}; + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_i2c_master_handle_register_t *low_level_handle; +static volatile hal_ll_i2c_hw_specifics_map_t *hal_ll_i2c_hw_specifics_map_local; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Check if pins are adequate. + * + * Checks scl and sda pins the user has passed with pre-defined + * pins in scl and sda maps. Take into consideration that module + * index numbers have to be the same for both pins. + * + * @param[in] scl - SCL pre-defined pin name. + * @param[in] sda - SDA pre-defined pin name. + * @param[in] *index_list - Index list address + * @return hal_ll_pin_name_t Module index based on pins. + * + * Returns pre-defined module index from pin maps, if pins + * are adequate. + */ +static hal_ll_pin_name_t hal_ll_i2c_master_check_pins( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_pin_id *index_list, hal_ll_i2c_master_handle_register_t *handle_map ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_i2c_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_i2c_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_i2c_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Get adequate I2C bit-rate value. + * + * Returns one of pre-defined bit-rate values, + * or the closest bit-rate based on bit_rate + * value passed to the function. + * + * @param[in] bit_rate - I2C bit rate. + * @return uint32_t Adequate bit-rate value. + * + * Returns adequate value to be latter written into bare metal register address. + * Take into consideration that this returns a predefined value. + * + * HAL_LL_I2C_MASTER_SPEED_100K -- 100Kbit/s + * HAL_LL_I2C_MASTER_SPEED_400K -- 400Kbit/s + * HAL_LL_I2C_MASTER_SPEED_1M -- 1Mbit/s + * HAL_LL_I2C_MASTER_SPEED_3M2 -- 3.2Mbit/s + */ +static uint32_t hal_ll_i2c_get_speed( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Enable clock for I2C1 module on hardware level. + * + * Initializes I2C1 module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] hal_ll_state - True/False -- Init/De-init + * + * @return None + */ +static inline void hal_ll_i2c1_set_clock( bool hal_ll_state ); + +/** + * @brief Enable clock for I2C2 module on hardware level. + * + * Initializes I2C2 module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] hal_ll_state - True/False -- Init/De-init + * + * @return None + */ +static inline void hal_ll_i2c2_set_clock( bool hal_ll_state ); + +/** + * @brief Enable clock for I2C3 module on hardware level. + * + * Initializes I2C3 module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] hal_ll_state - True/False -- Init/De-init + * + * @return None + */ +static inline void hal_ll_i2c3_set_clock( bool hal_ll_state ); + +/** + * @brief Enable clock for I2C4 module on hardware level. + * + * Initializes I2C4 module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] hal_ll_state - True/False -- Init/De-init + * + * @return None + */ +static inline void hal_ll_i2c4_set_clock( bool hal_ll_state ); + +/** + * @brief Enable clock for I2C module on hardware level. + * + * Initializes I2C module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_stat - True(enable clock)/False(disable clock). + * + * @return None + */ +static void hal_ll_i2c_master_set_clock( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Initialize I2C module on hardware level. + * + * Initializes I2C module on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] map - Object specific context handler. + * @return hal_ll_err_t Module specific return values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_hw_init( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * I2C SCL and SDA pins. + * + * @param[in] module_index I2C HW module index -- 0,1,2... + * @param[in] *index_list Array with SCL and SDA map index values + * and module number + * + * @return None + */ +static void hal_ll_i2c_master_map_pins( uint8_t module_index, hal_ll_i2c_pin_id *index_list ); + +/** + * @brief Sets I2C pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if I2C is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_state - Init/De-init + * + * @return None + */ +static void hal_ll_i2c_master_alternate_functions_set_state( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Full I2C module initialization procedure. + * + * Initializes I2C module on hardware level, based on beforehand + * set configuration and module handler. Sets adequate pin alternate functions. + * Initializes module clock. + * + * @param[in] map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Configure I2C module for data transfer. + * + * @param[in] hal_ll_hw_reg - I2C module base address. + * @param[in] config - I2C config bits. + * @return void None. + */ +static void hal_ll_i2c_master_configure_transfer( hal_ll_i2c_base_handle_t *hal_ll_hw_reg, uint32_t config ); + +/** + * @brief Reset value of I2C CR2 register. + * + * @param[in] hal_ll_hw_reg - I2C module base address. + * @returnl none + */ +static void hal_ll_i2c_master_reset_cr2( hal_ll_i2c_base_handle_t *hal_ll_hw_reg ); + +/** + * @brief Generates start signal on I2C bus. + * + * Generates a start signal on the I2C bus. + * + * @param[in] map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_master_start( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Generates stop signal on I2C bus. + * + * Generates a stop signal on the I2C bus. + * + * @param[in] map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_master_stop( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Perform a read on the I2C bus. + * + * Initializes I2C module on hardware level, if not initialized beforehand + * and continues to perform a read operation on the bus. + * + * @param[in] map - Object specific context handler. + * @param[in] readDatabuf - Pointer to data buffer. + * @param[in] lenReadData - Number of data to be read. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *read_data_buf, size_t len_read_data, hal_ll_i2c_master_end_mode_t mode ); + +/** + * @brief Perform a write on the I2C bus. + * + * Initializes I2C module on hardware level, if not initialized beforehand + * and continues to perform a write operation on the bus. + * + * @param[in] map - Object specific context handler. + * @param[in] writeDatabuf - Pointer to data buffer. + * @param[in] lenWriteData - Number of data to be written. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *write_data_buf, size_t len_write_data, hal_ll_i2c_master_end_mode_t mode ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_i2c_master_register_handle( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_master_handle_register_t *handle_map, uint8_t *hal_module_id ) { + + hal_ll_i2c_pin_id index_list[I2C_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + uint16_t pin_check_result; + + // Check if pins are valid + if ( (pin_check_result = hal_ll_i2c_master_check_pins( scl, sda, &index_list, handle_map )) == HAL_LL_PIN_NC ) { + return HAL_LL_I2C_MASTER_WRONG_PINS; + }; + + if ( (hal_ll_i2c_hw_specifics_map[pin_check_result].pins.pin_scl.pin_name != scl) || + (hal_ll_i2c_hw_specifics_map[pin_check_result].pins.pin_sda.pin_name != sda) ) + { + hal_ll_i2c_master_alternate_functions_set_state( &hal_ll_i2c_hw_specifics_map[ pin_check_result ], false ); + + hal_ll_i2c_master_map_pins( pin_check_result, &index_list ); + + hal_ll_i2c_master_alternate_functions_set_state( &hal_ll_i2c_hw_specifics_map[ pin_check_result ], true ); + + handle_map[pin_check_result].init_ll_state = false; + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[pin_check_result].hal_ll_i2c_master_handle = (handle_t *)&hal_ll_i2c_hw_specifics_map[pin_check_result].base; + + handle_map[pin_check_result].hal_ll_i2c_master_handle = (handle_t *)&hal_ll_module_state[pin_check_result].hal_ll_i2c_master_handle; + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_i2c( handle_t *handle ) { + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + hal_ll_i2c_master_handle_register_t *hal_handle = (hal_ll_i2c_master_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_i2c_hw_specifics_map_local->module_index; + + hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_local ); + + hal_ll_module_state[pin_check_result].hal_ll_i2c_master_handle = (handle_t *)&hal_ll_i2c_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_i2c_master_set_speed( handle_t *handle, uint32_t speed ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + low_level_handle->init_ll_state = false; + + hal_ll_i2c_hw_specifics_map_local->speed = speed; + + if ( hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_local ) != HAL_LL_I2C_MASTER_SUCCESS ) { + return HAL_LL_I2C_MASTER_TIMEOUT_INIT; + } + + low_level_handle->init_ll_state = true; + + return hal_ll_i2c_hw_specifics_map_local->speed; +} + +void hal_ll_i2c_master_set_timeout( handle_t *handle, uint16_t timeout ) { + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + if( hal_ll_i2c_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + hal_ll_i2c_hw_specifics_map_local->timeout = timeout; + } +} + +void hal_ll_i2c_master_set_slave_address( handle_t *handle, uint8_t addr ) { + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + if( hal_ll_i2c_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + hal_ll_i2c_hw_specifics_map_local->address = addr; + } +} + +hal_ll_err_t hal_ll_i2c_master_read( handle_t *handle, uint8_t *read_data_buf, size_t len_read_data ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + return hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_local, read_data_buf, len_read_data, HAL_LL_I2C_MASTER_END_MODE_STOP ); +} + +hal_ll_err_t hal_ll_i2c_master_write( handle_t *handle, uint8_t *write_data_buf, size_t len_write_data ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + return hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_local, write_data_buf, len_write_data, HAL_LL_I2C_MASTER_END_MODE_STOP ); +} + +hal_ll_err_t hal_ll_i2c_master_write_then_read( handle_t *handle, uint8_t *write_data_buf, size_t len_write_data, uint8_t *read_data_buf, size_t len_read_data ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + if( hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_local, write_data_buf, len_write_data, HAL_LL_I2C_MASTER_WRITE_THEN_READ ) != NULL ) { + return HAL_LL_I2C_MASTER_TIMEOUT_WRITE; + } + + /** + * @note Wait for drivers to set-up + * correctly. + **/ + #ifdef __TFT_RESISTIVE_TSC2003__ + Delay_22us(); + #endif + + if( hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_local, read_data_buf, len_read_data, HAL_LL_I2C_MASTER_WRITE_THEN_READ ) != NULL ) { + return HAL_LL_I2C_MASTER_TIMEOUT_READ; + } + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +void hal_ll_i2c_master_close( handle_t *handle ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + if( low_level_handle->hal_ll_i2c_master_handle != NULL ) { + low_level_handle->hal_ll_i2c_master_handle = NULL; + low_level_handle->hal_drv_i2c_master_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_i2c_hw_specifics_map_local->address = 0; + hal_ll_i2c_hw_specifics_map_local->timeout = HAL_LL_I2C_DEFAULT_PASS_COUNT; + hal_ll_i2c_hw_specifics_map_local->speed = HAL_LL_I2C_MASTER_SPEED_100K; + + hal_ll_i2c_master_set_clock(hal_ll_i2c_hw_specifics_map_local, true); + hal_ll_i2c_master_alternate_functions_set_state( hal_ll_i2c_hw_specifics_map_local, false ); + hal_ll_i2c_master_set_clock(hal_ll_i2c_hw_specifics_map_local, false); + + hal_ll_i2c_hw_specifics_map_local->pins.pin_scl.pin_name = HAL_LL_PIN_NC; + hal_ll_i2c_hw_specifics_map_local->pins.pin_sda.pin_name = HAL_LL_PIN_NC; + hal_ll_i2c_hw_specifics_map_local->pins.pin_scl.pin_af = 0; + hal_ll_i2c_hw_specifics_map_local->pins.pin_sda.pin_af = 0; + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static hal_ll_err_t hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *read_data_buf, size_t len_read_data, hal_ll_i2c_master_end_mode_t mode ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct(map->base); + uint16_t time_counter = map->timeout; + size_t transfer_counter = NULL; + uint8_t status = NULL; + + /** + * @note When R/W = 0, the input sample acquisition period starts + * on the falling edge of SCL once the C0 bit of the command + * byte has been latched, and ends when a Stop or + * repeated Start condition has been issued. + **/ + #ifdef __TFT_RESISTIVE_TSC2003__ + Delay_1ms(); + #endif + + hal_ll_i2c_master_configure_transfer ( map->base, + ( map->address << 1 & HAL_LL_I2C_CR2_SADD ) | + ( len_read_data << 16 & HAL_LL_I2C_CR2_NBYTES ) | + HAL_LL_I2C_CR2_RD_WRN | + HAL_LL_I2C_CR2_START + ); + + for ( transfer_counter; transfer_counter < len_read_data; transfer_counter++ ) { + while ( !( check_reg_bit( &( hal_ll_hw_reg->isr ), HAL_LL_I2C_RXNE_BIT ) ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_READ; + } + } + read_data_buf[ transfer_counter ] = hal_ll_hw_reg->rxdr; + } + + if ( ( mode == HAL_LL_I2C_MASTER_END_MODE_STOP ) || ( mode == HAL_LL_I2C_MASTER_WRITE_THEN_READ ) ) { + status = hal_ll_i2c_master_stop( map ); + } else { + status = hal_ll_i2c_master_start( map ); + } + + if( status != HAL_LL_I2C_MASTER_SUCCESS ) { + return status; + } + + hal_ll_i2c_master_reset_cr2( hal_ll_hw_reg ); + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static hal_ll_err_t hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *write_data_buf, size_t len_write_data, hal_ll_i2c_master_end_mode_t mode ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct(map->base); + uint16_t time_counter = map->timeout; + size_t transfer_counter = NULL; + uint8_t status = NULL; + + hal_ll_i2c_master_configure_transfer ( map->base, + ( map->address << 1 & HAL_LL_I2C_CR2_SADD ) | + ( len_write_data << 16 & HAL_LL_I2C_CR2_NBYTES ) | + !HAL_LL_I2C_CR2_RD_WRN | + HAL_LL_I2C_CR2_START + ); + + for ( transfer_counter; transfer_counter < len_write_data; transfer_counter++ ) + { + while ( !( check_reg_bit( &( hal_ll_hw_reg->isr ), HAL_LL_I2C_TXIS_BIT ) ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_WRITE; + } + } + hal_ll_hw_reg->txdr = write_data_buf[ transfer_counter ]; + } + + time_counter = map->timeout; + while ( !( check_reg_bit( &( hal_ll_hw_reg->isr ), HAL_LL_I2C_TXE_BIT ) ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_WRITE; + } + } + + if ( mode == HAL_LL_I2C_MASTER_END_MODE_STOP ) + { + hal_ll_i2c_master_stop( map ); + } + + hal_ll_i2c_master_reset_cr2( hal_ll_hw_reg ); + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static void hal_ll_i2c_master_configure_transfer( hal_ll_i2c_base_handle_t *hal_ll_hw_reg, uint32_t config ) { + uint32_t reg = 0; + + // Clear last set slave address + hal_ll_hw_reg->cr2 &= ~HAL_LL_I2C_CR2_SADD; + + reg = hal_ll_hw_reg->cr2; + reg &= ~( uint32_t )( + ( HAL_LL_I2C_CR2_SADD ) | + ( HAL_LL_I2C_CR2_NBYTES ) | + ( HAL_LL_I2C_CR2_RELOAD ) | + ( HAL_LL_I2C_CR2_AUTOEND ) | + ( HAL_LL_I2C_CR2_RD_WRN ) | + ( HAL_LL_I2C_CR2_START ) | + ( HAL_LL_I2C_CR2_STOP ) + ); + + reg |= config; + hal_ll_hw_reg->cr2 = reg; +} + +static void hal_ll_i2c_master_reset_cr2( hal_ll_i2c_base_handle_t *hal_ll_hw_reg ) { + hal_ll_hw_reg->cr2 &= ~( uint32_t ) + ( + HAL_LL_I2C_SADD_MASK | + HAL_LL_I2C_HEAD10R_MASK | + HAL_LL_I2C_NBYTES_MASK | + HAL_LL_I2C_RELOAD_MASK | + HAL_LL_I2C_RD_WRN_MASK + ); +} + +static hal_ll_err_t hal_ll_i2c_master_start( hal_ll_i2c_hw_specifics_map_t *map ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct(map->base); + uint16_t loop_index = HAL_LL_I2C_LOOP_INDEX; + + set_reg_bit( &(hal_ll_hw_reg->cr2), HAL_LL_I2C_CR2_START_BIT ); + + if ( check_reg_bit( &( hal_ll_hw_reg->isr ), HAL_LL_I2C_ARLO_BIT ) ) + return HAL_LL_I2C_MASTER_ARBITRATION_LOST; + + while ( loop_index-- ) + assembly(nop); + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static hal_ll_err_t hal_ll_i2c_master_stop( hal_ll_i2c_hw_specifics_map_t *map ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = ( hal_ll_i2c_base_handle_t* )map->base; + uint16_t time_counter = map->timeout; + uint32_t loop_index = HAL_LL_I2C_LOOP_INDEX; + + set_reg_bit( &(hal_ll_hw_reg->cr2), HAL_LL_I2C_CR2_STOP_BIT ); + + while ( !( hal_ll_hw_reg->isr & HAL_LL_I2C_ISR_STOPF_BIT ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_STOP; + } + } + + if ( map->timeout < HAL_LL_I2C_LOOP_INDEX ) { + while ( loop_index-- ) + assembly(nop); + } + + hal_ll_hw_reg->isr &= ~HAL_LL_I2C_ISR_STOPF_BIT; + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static hal_ll_pin_name_t hal_ll_i2c_master_check_pins( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_pin_id *index_list, hal_ll_i2c_master_handle_register_t *handle_map ) { + static const uint16_t scl_map_size = ( sizeof( hal_ll_i2c_scl_map ) / sizeof( hal_ll_i2c_pin_map_t ) ); + static const uint16_t sda_map_size = ( sizeof( hal_ll_i2c_sda_map ) / sizeof( hal_ll_i2c_pin_map_t ) ); + uint8_t hal_ll_module_id = 0; + uint8_t index_counter = 0; + uint16_t scl_index; + uint16_t sda_index; + + if ( (HAL_LL_PIN_NC == scl) || (HAL_LL_PIN_NC == sda) ) { + return HAL_LL_PIN_NC; + } + + for ( scl_index = 0; scl_index < scl_map_size; scl_index++ ) { + if ( hal_ll_i2c_scl_map[ scl_index ].pin == scl ) { + for ( sda_index = 0; sda_index < sda_map_size; sda_index++ ) { + if ( hal_ll_i2c_sda_map[ sda_index ].pin == sda ) { + if ( hal_ll_i2c_scl_map[ scl_index ].module_index == hal_ll_i2c_sda_map[ sda_index ].module_index ) { + // Get module number + hal_ll_module_id = hal_ll_i2c_scl_map[ scl_index ].module_index; + // Map pin names + index_list[hal_ll_module_id].pin_scl = scl_index; + index_list[hal_ll_module_id].pin_sda = sda_index; + + // Check if module is taken + if ( NULL == handle_map[ hal_ll_module_id ].hal_drv_i2c_master_handle ) { + return hal_ll_module_id; + } else if ( I2C_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static hal_ll_i2c_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof(hal_ll_i2c_master_handle_register_t)); + static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof(hal_ll_i2c_master_handle_register_t)); + + while( hal_ll_module_count-- ) { + if (hal_ll_i2c_get_base_from_hal_handle == hal_ll_i2c_hw_specifics_map[hal_ll_module_count].base) { + return &hal_ll_i2c_hw_specifics_map[hal_ll_module_count]; + } + } + + return &hal_ll_i2c_hw_specifics_map[hal_ll_module_error]; +} + +static void hal_ll_i2c_master_set_clock( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ) { + switch ( map->module_index ) + { + #if defined(I2C_MODULE_1) + case ( hal_ll_i2c_module_num(I2C_MODULE_1) ): + hal_ll_i2c1_set_clock( hal_ll_state ); + break; + #endif + + #if defined(I2C_MODULE_2) + case ( hal_ll_i2c_module_num(I2C_MODULE_2) ): + hal_ll_i2c2_set_clock( hal_ll_state ); + break; + #endif + + #if defined(I2C_MODULE_3) + case ( hal_ll_i2c_module_num(I2C_MODULE_3) ): + hal_ll_i2c3_set_clock( hal_ll_state ); + break; + #endif + + #if defined(I2C_MODULE_4) + case ( hal_ll_i2c_module_num(I2C_MODULE_4) ): + hal_ll_i2c4_set_clock( hal_ll_state ); + break; + #endif + + + default: + break; + } +} + +static void hal_ll_i2c_master_map_pins( uint8_t module_index, hal_ll_i2c_pin_id *index_list ) { + // Map new pins + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_scl.pin_name = hal_ll_i2c_scl_map[ index_list[module_index].pin_scl ].pin; + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_sda.pin_name = hal_ll_i2c_sda_map[ index_list[module_index].pin_sda ].pin; + // SCL and SDA could have different alternate function settings, hence save both AF values + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_scl.pin_af = hal_ll_i2c_scl_map[ index_list[module_index].pin_scl ].af; + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_sda.pin_af = hal_ll_i2c_sda_map[ index_list[module_index].pin_sda ].af; +} + +static void hal_ll_i2c_master_alternate_functions_set_state( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ) { + module_struct module; + + if( (map->pins.pin_scl.pin_name != HAL_LL_PIN_NC) && (map->pins.pin_sda.pin_name != HAL_LL_PIN_NC) ) { + module.pins[0] = VALUE( map->pins.pin_scl.pin_name, map->pins.pin_scl.pin_af ); + module.pins[1] = VALUE( map->pins.pin_sda.pin_name, map->pins.pin_sda.pin_af ); + module.pins[2] = GPIO_MODULE_STRUCT_END; + + module.configs[0] = HAL_LL_I2C_AF_CONFIG; + module.configs[1] = HAL_LL_I2C_AF_CONFIG; + module.configs[2] = GPIO_MODULE_STRUCT_END; + + hal_ll_gpio_module_struct_init( &module, hal_ll_state ); + } +} + +static uint32_t hal_ll_i2c_get_speed( hal_ll_i2c_hw_specifics_map_t *map ) { + if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_FAST ) { + if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_STANDARD ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_100K; + return HAL_LL_I2C_100K; + } else if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_FULL ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_400K; + return HAL_LL_I2C_400K; + } else if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_FAST ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_1M; + return HAL_LL_I2C_1M; + } else { + map->speed = HAL_LL_I2C_MASTER_SPEED_100K; + return HAL_LL_I2C_100K; + } + } else { + if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_100K ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_100K; + return HAL_LL_I2C_100K; + } else if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_400K ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_400K; + return HAL_LL_I2C_400K; + } else if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_1M ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_1M; + return HAL_LL_I2C_1M; + } else { + map->speed = HAL_LL_I2C_MASTER_SPEED_1M; + return HAL_LL_I2C_1M; + } + } +} +static inline void hal_ll_i2c1_set_clock( bool hal_ll_state ) { + if ( hal_ll_state ) { + set_reg_bit( _RCC_APB1ENR1, HAL_LL_I2C1EN_BIT ); + set_reg_bit( _RCC_CCIPR, HAL_LL_I2C1SEL1_BIT ); + } else { + clear_reg_bit( _RCC_APB1ENR1, HAL_LL_I2C1EN_BIT ); + clear_reg_bit( _RCC_CCIPR, HAL_LL_I2C1SEL1_BIT ); + } +} + + +static inline void hal_ll_i2c2_set_clock( bool hal_ll_state ) { + if ( hal_ll_state ) { + set_reg_bit( _RCC_APB1ENR1, HAL_LL_I2C2EN_BIT ); + } else { + clear_reg_bit( _RCC_APB1ENR1, HAL_LL_I2C2EN_BIT ); + } +} + + + +static inline void hal_ll_i2c3_set_clock( bool hal_ll_state ) { + if ( hal_ll_state ) { + set_reg_bit( _RCC_APB1ENR1, HAL_LL_I2C3EN_BIT ); + } else { + clear_reg_bit( _RCC_APB1ENR1, HAL_LL_I2C3EN_BIT ); + } +} + + + +static inline void hal_ll_i2c4_set_clock( bool hal_ll_state ) { + if ( hal_ll_state ) { + set_reg_bit( _RCC_APB1ENR2, HAL_LL_I2C4EN_BIT ); + set_reg_bit( _RCC_CCIPR2, HAL_LL_I2C4SEL1_BIT ); + } else { + clear_reg_bit( _RCC_APB1ENR2, HAL_LL_I2C4EN_BIT ); + clear_reg_bit( _RCC_CCIPR2, HAL_LL_I2C4SEL1_BIT ); + } +} + + + +static hal_ll_err_t hal_ll_i2c_hw_init( hal_ll_i2c_hw_specifics_map_t *map ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct(map->base); + uint16_t time_counter = map->timeout; + + clear_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_I2C_PE_BIT ); + while ( check_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_I2C_PE_BIT ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_INIT; + } + } + + hal_ll_hw_reg->cr1 &= HAL_LL_I2C_FILTERS_OFF; + + hal_ll_hw_reg->timingr = hal_ll_i2c_get_speed( map ); + + hal_ll_hw_reg->cr1 |= HAL_LL_I2C_CR1_RXTX_INT; + + set_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_I2C_PE_BIT ); + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static hal_ll_err_t hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_t *map ) { + hal_ll_i2c_master_set_clock( map, true ); + + return hal_ll_i2c_hw_init( map ); +} +// ------------------------------------------------------------------------- END + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_2/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_2/CMakeLists.cmake new file mode 100644 index 000000000..d3cb4c54d --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_2/CMakeLists.cmake @@ -0,0 +1,9 @@ +if(${MCU_NAME} MATCHES "^STM32C031C4$|^STM32C031F4$|^STM32C031G4$|^STM32C031K4$|^STM32C031C6$|^STM32C031F6$|^STM32C031G6$|^STM32C031K6$") + set(i2c_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_i2c_master.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_2") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_2") + list(APPEND hal_ll_def_list "STM32C0xx") + list(APPEND hal_ll_def_list "STM32C03xx") + list(APPEND hal_ll_def_list "STM32C031xx") + set(i2c_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/i2c/hal_ll_i2c_pin_map/implementations/doc_ds_2") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_2/hal_ll_i2c_master.c b/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_2/hal_ll_i2c_master.c new file mode 100644 index 000000000..0fb02ecba --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_2/hal_ll_i2c_master.c @@ -0,0 +1,898 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_i2c_master.c + * @brief I2C master HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_rcc.h" +#include "hal_ll_gpio.h" +#include "hal_ll_i2c_master.h" +#include "hal_ll_i2c_pin_map.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_i2c_master_handle_register_t hal_ll_module_state[I2C_MODULE_COUNT] = { (handle_t *)NULL, (handle_t *)NULL, false }; + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_i2c_get_module_state_address ((hal_ll_i2c_master_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_i2c_get_handle (hal_ll_i2c_master_handle_register_t *)hal_ll_i2c_get_module_state_address->hal_ll_i2c_master_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_i2c_get_base_struct(_handle) ((hal_ll_i2c_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_i2c_get_base_from_hal_handle ((hal_ll_i2c_hw_specifics_map_t *)((hal_ll_i2c_master_handle_register_t *)\ + (((hal_ll_i2c_master_handle_register_t *)(handle))->hal_ll_i2c_master_handle))->hal_ll_i2c_master_handle)->base + +/*!< @brief Default I2C bit-rate if no speed is set */ +#define HAL_LL_I2C_MASTER_SPEED_100K 100000UL +#define HAL_LL_I2C_MASTER_SPEED_400K 400000UL +#define HAL_LL_I2C_MASTER_SPEED_1M 1000000UL + +/*!< @brief Default pass count value upon reset */ +#define HAL_LL_I2C_DEFAULT_PASS_COUNT 0xFFFFU + +/*!< @brief Macro used for timeout */ +#define HAL_LL_I2C_LOOP_INDEX 10000U + +/*!< @brief Macros defining register bit location */ +#define HAL_LL_I2C1EN_BIT 21 + +#define HAL_LL_I2C1SEL0_BIT 12 + +#define HAL_LL_I2C1SEL1_BIT 13 + + + + +#define HAL_LL_I2C_100K 0x30420F13 //?????????????????? +#define HAL_LL_I2C_400K 0x10320309 //?????????????????? +#define HAL_LL_I2C_1M 0x00200204 //?????????????????? + +#define HAL_LL_I2C_PE_BIT 0 +#define HAL_LL_I2C_CR2_STOP_BIT 14 +#define HAL_LL_I2C_CR2_START_BIT 13 +#define HAL_LL_I2C_ISR_STOPF_BIT 5 +#define HAL_LL_I2C_ISR_BUSY_BIT 15 +#define HAL_LL_I2C_ARLO_BIT 9 +#define HAL_LL_I2C_RXNE_BIT 2 +#define HAL_LL_I2C_TXIS_BIT 1 +#define HAL_LL_I2C_TXE_BIT 0 + +/*!< @brief Macros defining register bit masks */ +#define HAL_LL_I2C_CR1_RXTX_INT 0x6 +#define HAL_LL_I2C_CR2_STOP 0x4000UL +#define HAL_LL_I2C_CR2_START 0x2000U +#define HAL_LL_I2C_CR2_SADD 0x3FFU +#define HAL_LL_I2C_CR2_NBYTES 0xFF0000UL +#define HAL_LL_I2C_CR2_RD_WRN 0x400U +#define HAL_LL_I2C_CR2_RELOAD 0x1000000UL +#define HAL_LL_I2C_CR2_AUTOEND 0x2000000UL +#define HAL_LL_I2C_FILTERS_OFF 0xFFFFE0FFUL +#define HAL_LL_I2C_SADD_MASK 0x3FFUL +#define HAL_LL_I2C_HEAD10R_MASK 0x1000UL +#define HAL_LL_I2C_NBYTES_MASK 0xFF0000UL +#define HAL_LL_I2C_RELOAD_MASK 0x1000000UL +#define HAL_LL_I2C_RD_WRN_MASK 0x400UL + +/*!< @brief Macros used for module pin checking */ +#define HAL_LL_I2C_SCL_PIN 0 +#define HAL_LL_I2C_SDA_PIN 1 +#define HAL_LL_I2C_MODULE_PIN_COUNT 2 + +/*!< @brief Macro used for setting pin alternate functions */ +#define HAL_LL_I2C_AF_CONFIG (GPIO_CFG_MODE_ALT_FUNCTION | GPIO_CFG_SPEED_HIGH | GPIO_CFG_OTYPE_OD) + +// -------------------------------------------------------------- PRIVATE TYPES +/*!< @brief I2C register structure */ +typedef struct +{ + hal_ll_base_addr_t cr1; + hal_ll_base_addr_t cr2; + hal_ll_base_addr_t oar1; + hal_ll_base_addr_t oar2; + hal_ll_base_addr_t timingr; + hal_ll_base_addr_t timeoutr; + hal_ll_base_addr_t isr; + hal_ll_base_addr_t icr; + hal_ll_base_addr_t pecr; + hal_ll_base_addr_t rxdr; + hal_ll_base_addr_t txdr; + +} hal_ll_i2c_base_handle_t; + +/*!< @brief I2C hw specific structure */ +typedef struct +{ + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + hal_ll_i2c_pins_t pins; + uint32_t speed; + uint8_t address; + uint16_t timeout; +} hal_ll_i2c_hw_specifics_map_t; + +/*!< @brief I2C hw specific module values */ +typedef struct +{ + uint16_t pin_scl; + uint16_t pin_sda; +} hal_ll_i2c_pin_id; + +/*!< @brief I2C hw specific error values */ +typedef enum +{ + HAL_LL_I2C_MASTER_SUCCESS = 0, + HAL_LL_I2C_MASTER_WRONG_PINS, + HAL_LL_I2C_MASTER_MODULE_ERROR, + + HAL_LL_I2C_MASTER_ERROR = (-1) +} hal_ll_i2c_master_err_t; + +/*!< @brief I2C end mode selection values */ +typedef enum +{ + HAL_LL_I2C_MASTER_END_MODE_RESTART = 0, + HAL_LL_I2C_MASTER_END_MODE_STOP, + HAL_LL_I2C_MASTER_WRITE_THEN_READ +} hal_ll_i2c_master_end_mode_t; + +/*!< @brief I2C timeout error values */ +typedef enum +{ + HAL_LL_I2C_MASTER_TIMEOUT_START = 1300, + HAL_LL_I2C_MASTER_TIMEOUT_STOP, + HAL_LL_I2C_MASTER_TIMEOUT_WRITE, + HAL_LL_I2C_MASTER_TIMEOUT_READ, + HAL_LL_I2C_MASTER_ARBITRATION_LOST, + HAL_LL_I2C_MASTER_TIMEOUT_INIT +} hal_ll_i2c_master_timeout_t; + +/** + * @brief Enum containing predefined module standard speed values. + * + * Enum values: + * HAL_LL_I2C_MASTER_SPEED_STANDARD -- Speed set at 100K + * HAL_LL_I2C_MASTER_SPEED_FULL -- Speed set at 400K + * HAL_LL_I2C_MASTER_SPEED_FAST -- Speed set at 1M + */ +typedef enum +{ + HAL_LL_I2C_MASTER_SPEED_STANDARD = 0, + HAL_LL_I2C_MASTER_SPEED_FULL, + HAL_LL_I2C_MASTER_SPEED_FAST +} hal_ll_i2c_master_speed_t; + +// ------------------------------------------------------------------ VARIABLES +/*!< @brief I2C hardware specific info */ +static hal_ll_i2c_hw_specifics_map_t hal_ll_i2c_hw_specifics_map[] = +{ + #ifdef I2C_MODULE_1 + {HAL_LL_I2C1_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_1), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, + #endif + + + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, 0, 0} +}; + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_i2c_master_handle_register_t *low_level_handle; +static volatile hal_ll_i2c_hw_specifics_map_t *hal_ll_i2c_hw_specifics_map_local; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Check if pins are adequate. + * + * Checks scl and sda pins the user has passed with pre-defined + * pins in scl and sda maps. Take into consideration that module + * index numbers have to be the same for both pins. + * + * @param[in] scl - SCL pre-defined pin name. + * @param[in] sda - SDA pre-defined pin name. + * @param[in] *index_list - Index list address + * @return hal_ll_pin_name_t Module index based on pins. + * + * Returns pre-defined module index from pin maps, if pins + * are adequate. + */ +static hal_ll_pin_name_t hal_ll_i2c_master_check_pins( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_pin_id *index_list, hal_ll_i2c_master_handle_register_t *handle_map ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_i2c_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_i2c_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_i2c_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Get adequate I2C bit-rate value. + * + * Returns one of pre-defined bit-rate values, + * or the closest bit-rate based on bit_rate + * value passed to the function. + * + * @param[in] bit_rate - I2C bit rate. + * @return uint32_t Adequate bit-rate value. + * + * Returns adequate value to be latter written into bare metal register address. + * Take into consideration that this returns a predefined value. + * + * HAL_LL_I2C_MASTER_SPEED_100K -- 100Kbit/s + * HAL_LL_I2C_MASTER_SPEED_400K -- 400Kbit/s + * HAL_LL_I2C_MASTER_SPEED_1M -- 1Mbit/s + * HAL_LL_I2C_MASTER_SPEED_3M2 -- 3.2Mbit/s + */ +static uint32_t hal_ll_i2c_get_speed( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Enable clock for I2C1 module on hardware level. + * + * Initializes I2C1 module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] hal_ll_state - True/False -- Init/De-init + * + * @return None + */ +static inline void hal_ll_i2c1_set_clock( bool hal_ll_state ); + +/** + * @brief Enable clock for I2C module on hardware level. + * + * Initializes I2C module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_stat - True(enable clock)/False(disable clock). + * + * @return None + */ +static void hal_ll_i2c_master_set_clock( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Initialize I2C module on hardware level. + * + * Initializes I2C module on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] map - Object specific context handler. + * @return hal_ll_err_t Module specific return values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_hw_init( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * I2C SCL and SDA pins. + * + * @param[in] module_index I2C HW module index -- 0,1,2... + * @param[in] *index_list Array with SCL and SDA map index values + * and module number + * + * @return None + */ +static void hal_ll_i2c_master_map_pins( uint8_t module_index, hal_ll_i2c_pin_id *index_list ); + +/** + * @brief Sets I2C pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if I2C is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_state - Init/De-init + * + * @return None + */ +static void hal_ll_i2c_master_alternate_functions_set_state( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Full I2C module initialization procedure. + * + * Initializes I2C module on hardware level, based on beforehand + * set configuration and module handler. Sets adequate pin alternate functions. + * Initializes module clock. + * + * @param[in] map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Configure I2C module for data transfer. + * + * @param[in] hal_ll_hw_reg - I2C module base address. + * @param[in] config - I2C config bits. + * @return void None. + */ +static void hal_ll_i2c_master_configure_transfer( hal_ll_i2c_base_handle_t *hal_ll_hw_reg, uint32_t config ); + +/** + * @brief Reset value of I2C CR2 register. + * + * @param[in] hal_ll_hw_reg - I2C module base address. + * @returnl none + */ +static void hal_ll_i2c_master_reset_cr2( hal_ll_i2c_base_handle_t *hal_ll_hw_reg ); + +/** + * @brief Generates start signal on I2C bus. + * + * Generates a start signal on the I2C bus. + * + * @param[in] map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_master_start( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Generates stop signal on I2C bus. + * + * Generates a stop signal on the I2C bus. + * + * @param[in] map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_master_stop( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Perform a read on the I2C bus. + * + * Initializes I2C module on hardware level, if not initialized beforehand + * and continues to perform a read operation on the bus. + * + * @param[in] map - Object specific context handler. + * @param[in] readDatabuf - Pointer to data buffer. + * @param[in] lenReadData - Number of data to be read. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *read_data_buf, size_t len_read_data, hal_ll_i2c_master_end_mode_t mode ); + +/** + * @brief Perform a write on the I2C bus. + * + * Initializes I2C module on hardware level, if not initialized beforehand + * and continues to perform a write operation on the bus. + * + * @param[in] map - Object specific context handler. + * @param[in] writeDatabuf - Pointer to data buffer. + * @param[in] lenWriteData - Number of data to be written. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *write_data_buf, size_t len_write_data, hal_ll_i2c_master_end_mode_t mode ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_i2c_master_register_handle( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_master_handle_register_t *handle_map, uint8_t *hal_module_id ) { + + hal_ll_i2c_pin_id index_list[I2C_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + uint16_t pin_check_result; + + // Check if pins are valid + if ( (pin_check_result = hal_ll_i2c_master_check_pins( scl, sda, &index_list, handle_map )) == HAL_LL_PIN_NC ) { + return HAL_LL_I2C_MASTER_WRONG_PINS; + }; + + if ( (hal_ll_i2c_hw_specifics_map[pin_check_result].pins.pin_scl.pin_name != scl) || + (hal_ll_i2c_hw_specifics_map[pin_check_result].pins.pin_sda.pin_name != sda) ) + { + hal_ll_i2c_master_alternate_functions_set_state( &hal_ll_i2c_hw_specifics_map[ pin_check_result ], false ); + + hal_ll_i2c_master_map_pins( pin_check_result, &index_list ); + + hal_ll_i2c_master_alternate_functions_set_state( &hal_ll_i2c_hw_specifics_map[ pin_check_result ], true ); + + handle_map[pin_check_result].init_ll_state = false; + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[pin_check_result].hal_ll_i2c_master_handle = (handle_t *)&hal_ll_i2c_hw_specifics_map[pin_check_result].base; + + handle_map[pin_check_result].hal_ll_i2c_master_handle = (handle_t *)&hal_ll_module_state[pin_check_result].hal_ll_i2c_master_handle; + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_i2c( handle_t *handle ) { + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + hal_ll_i2c_master_handle_register_t *hal_handle = (hal_ll_i2c_master_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_i2c_hw_specifics_map_local->module_index; + + hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_local ); + + hal_ll_module_state[pin_check_result].hal_ll_i2c_master_handle = (handle_t *)&hal_ll_i2c_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_i2c_master_set_speed( handle_t *handle, uint32_t speed ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + low_level_handle->init_ll_state = false; + + hal_ll_i2c_hw_specifics_map_local->speed = speed; + + if ( hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_local ) != HAL_LL_I2C_MASTER_SUCCESS ) { + return HAL_LL_I2C_MASTER_TIMEOUT_INIT; + } + + low_level_handle->init_ll_state = true; + + return hal_ll_i2c_hw_specifics_map_local->speed; +} + +void hal_ll_i2c_master_set_timeout( handle_t *handle, uint16_t timeout ) { + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + if( hal_ll_i2c_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + hal_ll_i2c_hw_specifics_map_local->timeout = timeout; + } +} + +void hal_ll_i2c_master_set_slave_address( handle_t *handle, uint8_t addr ) { + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + if( hal_ll_i2c_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + hal_ll_i2c_hw_specifics_map_local->address = addr; + } +} + +hal_ll_err_t hal_ll_i2c_master_read( handle_t *handle, uint8_t *read_data_buf, size_t len_read_data ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + return hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_local, read_data_buf, len_read_data, HAL_LL_I2C_MASTER_END_MODE_STOP ); +} + +hal_ll_err_t hal_ll_i2c_master_write( handle_t *handle, uint8_t *write_data_buf, size_t len_write_data ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + return hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_local, write_data_buf, len_write_data, HAL_LL_I2C_MASTER_END_MODE_STOP ); +} + +hal_ll_err_t hal_ll_i2c_master_write_then_read( handle_t *handle, uint8_t *write_data_buf, size_t len_write_data, uint8_t *read_data_buf, size_t len_read_data ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + if( hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_local, write_data_buf, len_write_data, HAL_LL_I2C_MASTER_WRITE_THEN_READ ) != NULL ) { + return HAL_LL_I2C_MASTER_TIMEOUT_WRITE; + } + + /** + * @note Wait for drivers to set-up + * correctly. + **/ + #ifdef __TFT_RESISTIVE_TSC2003__ + Delay_22us(); + #endif + + if( hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_local, read_data_buf, len_read_data, HAL_LL_I2C_MASTER_WRITE_THEN_READ ) != NULL ) { + return HAL_LL_I2C_MASTER_TIMEOUT_READ; + } + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +void hal_ll_i2c_master_close( handle_t *handle ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + if( low_level_handle->hal_ll_i2c_master_handle != NULL ) { + low_level_handle->hal_ll_i2c_master_handle = NULL; + low_level_handle->hal_drv_i2c_master_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_i2c_hw_specifics_map_local->address = 0; + hal_ll_i2c_hw_specifics_map_local->timeout = HAL_LL_I2C_DEFAULT_PASS_COUNT; + hal_ll_i2c_hw_specifics_map_local->speed = HAL_LL_I2C_MASTER_SPEED_100K; + + hal_ll_i2c_master_set_clock(hal_ll_i2c_hw_specifics_map_local, true); + hal_ll_i2c_master_alternate_functions_set_state( hal_ll_i2c_hw_specifics_map_local, false ); + hal_ll_i2c_master_set_clock(hal_ll_i2c_hw_specifics_map_local, false); + + hal_ll_i2c_hw_specifics_map_local->pins.pin_scl.pin_name = HAL_LL_PIN_NC; + hal_ll_i2c_hw_specifics_map_local->pins.pin_sda.pin_name = HAL_LL_PIN_NC; + hal_ll_i2c_hw_specifics_map_local->pins.pin_scl.pin_af = 0; + hal_ll_i2c_hw_specifics_map_local->pins.pin_sda.pin_af = 0; + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static hal_ll_err_t hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *read_data_buf, size_t len_read_data, hal_ll_i2c_master_end_mode_t mode ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct(map->base); + uint16_t time_counter = map->timeout; + size_t transfer_counter = NULL; + uint8_t status = NULL; + + /** + * @note When R/W = 0, the input sample acquisition period starts + * on the falling edge of SCL once the C0 bit of the command + * byte has been latched, and ends when a Stop or + * repeated Start condition has been issued. + **/ + #ifdef __TFT_RESISTIVE_TSC2003__ + Delay_1ms(); + #endif + + hal_ll_i2c_master_configure_transfer ( map->base, + ( map->address << 1 & HAL_LL_I2C_CR2_SADD ) | + ( len_read_data << 16 & HAL_LL_I2C_CR2_NBYTES ) | + HAL_LL_I2C_CR2_RD_WRN | + HAL_LL_I2C_CR2_START + ); + + for ( transfer_counter; transfer_counter < len_read_data; transfer_counter++ ) { + while ( !( check_reg_bit( &( hal_ll_hw_reg->isr ), HAL_LL_I2C_RXNE_BIT ) ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_READ; + } + } + read_data_buf[ transfer_counter ] = hal_ll_hw_reg->rxdr; + } + + if ( ( mode == HAL_LL_I2C_MASTER_END_MODE_STOP ) || ( mode == HAL_LL_I2C_MASTER_WRITE_THEN_READ ) ) { + status = hal_ll_i2c_master_stop( map ); + } else { + status = hal_ll_i2c_master_start( map ); + } + + if( status != HAL_LL_I2C_MASTER_SUCCESS ) { + return status; + } + + hal_ll_i2c_master_reset_cr2( hal_ll_hw_reg ); + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static hal_ll_err_t hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *write_data_buf, size_t len_write_data, hal_ll_i2c_master_end_mode_t mode ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct(map->base); + uint16_t time_counter = map->timeout; + size_t transfer_counter = NULL; + uint8_t status = NULL; + + hal_ll_i2c_master_configure_transfer ( map->base, + ( map->address << 1 & HAL_LL_I2C_CR2_SADD ) | + ( len_write_data << 16 & HAL_LL_I2C_CR2_NBYTES ) | + !HAL_LL_I2C_CR2_RD_WRN | + HAL_LL_I2C_CR2_START + ); + + for ( transfer_counter; transfer_counter < len_write_data; transfer_counter++ ) + { + while ( !( check_reg_bit( &( hal_ll_hw_reg->isr ), HAL_LL_I2C_TXIS_BIT ) ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_WRITE; + } + } + hal_ll_hw_reg->txdr = write_data_buf[ transfer_counter ]; + } + + time_counter = map->timeout; + while ( !( check_reg_bit( &( hal_ll_hw_reg->isr ), HAL_LL_I2C_TXE_BIT ) ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_WRITE; + } + } + + if ( mode == HAL_LL_I2C_MASTER_END_MODE_STOP ) + { + hal_ll_i2c_master_stop( map ); + } + + hal_ll_i2c_master_reset_cr2( hal_ll_hw_reg ); + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static void hal_ll_i2c_master_configure_transfer( hal_ll_i2c_base_handle_t *hal_ll_hw_reg, uint32_t config ) { + uint32_t reg = 0; + + // Clear last set slave address + hal_ll_hw_reg->cr2 &= ~HAL_LL_I2C_CR2_SADD; + + reg = hal_ll_hw_reg->cr2; + reg &= ~( uint32_t )( + ( HAL_LL_I2C_CR2_SADD ) | + ( HAL_LL_I2C_CR2_NBYTES ) | + ( HAL_LL_I2C_CR2_RELOAD ) | + ( HAL_LL_I2C_CR2_AUTOEND ) | + ( HAL_LL_I2C_CR2_RD_WRN ) | + ( HAL_LL_I2C_CR2_START ) | + ( HAL_LL_I2C_CR2_STOP ) + ); + + reg |= config; + hal_ll_hw_reg->cr2 = reg; +} + +static void hal_ll_i2c_master_reset_cr2( hal_ll_i2c_base_handle_t *hal_ll_hw_reg ) { + hal_ll_hw_reg->cr2 &= ~( uint32_t ) + ( + HAL_LL_I2C_SADD_MASK | + HAL_LL_I2C_HEAD10R_MASK | + HAL_LL_I2C_NBYTES_MASK | + HAL_LL_I2C_RELOAD_MASK | + HAL_LL_I2C_RD_WRN_MASK + ); +} + +static hal_ll_err_t hal_ll_i2c_master_start( hal_ll_i2c_hw_specifics_map_t *map ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct(map->base); + uint16_t loop_index = HAL_LL_I2C_LOOP_INDEX; + + set_reg_bit( &(hal_ll_hw_reg->cr2), HAL_LL_I2C_CR2_START_BIT ); + + if ( check_reg_bit( &( hal_ll_hw_reg->isr ), HAL_LL_I2C_ARLO_BIT ) ) + return HAL_LL_I2C_MASTER_ARBITRATION_LOST; + + while ( loop_index-- ) + assembly(nop); + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static hal_ll_err_t hal_ll_i2c_master_stop( hal_ll_i2c_hw_specifics_map_t *map ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = ( hal_ll_i2c_base_handle_t* )map->base; + uint16_t time_counter = map->timeout; + uint32_t loop_index = HAL_LL_I2C_LOOP_INDEX; + + set_reg_bit( &(hal_ll_hw_reg->cr2), HAL_LL_I2C_CR2_STOP_BIT ); + + while ( !( hal_ll_hw_reg->isr & HAL_LL_I2C_ISR_STOPF_BIT ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_STOP; + } + } + + if ( map->timeout < HAL_LL_I2C_LOOP_INDEX ) { + while ( loop_index-- ) + assembly(nop); + } + + hal_ll_hw_reg->isr &= ~HAL_LL_I2C_ISR_STOPF_BIT; + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static hal_ll_pin_name_t hal_ll_i2c_master_check_pins( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_pin_id *index_list, hal_ll_i2c_master_handle_register_t *handle_map ) { + static const uint16_t scl_map_size = ( sizeof( hal_ll_i2c_scl_map ) / sizeof( hal_ll_i2c_pin_map_t ) ); + static const uint16_t sda_map_size = ( sizeof( hal_ll_i2c_sda_map ) / sizeof( hal_ll_i2c_pin_map_t ) ); + uint8_t hal_ll_module_id = 0; + uint8_t index_counter = 0; + uint16_t scl_index; + uint16_t sda_index; + + if ( (HAL_LL_PIN_NC == scl) || (HAL_LL_PIN_NC == sda) ) { + return HAL_LL_PIN_NC; + } + + for ( scl_index = 0; scl_index < scl_map_size; scl_index++ ) { + if ( hal_ll_i2c_scl_map[ scl_index ].pin == scl ) { + for ( sda_index = 0; sda_index < sda_map_size; sda_index++ ) { + if ( hal_ll_i2c_sda_map[ sda_index ].pin == sda ) { + if ( hal_ll_i2c_scl_map[ scl_index ].module_index == hal_ll_i2c_sda_map[ sda_index ].module_index ) { + // Get module number + hal_ll_module_id = hal_ll_i2c_scl_map[ scl_index ].module_index; + // Map pin names + index_list[hal_ll_module_id].pin_scl = scl_index; + index_list[hal_ll_module_id].pin_sda = sda_index; + + // Check if module is taken + if ( NULL == handle_map[ hal_ll_module_id ].hal_drv_i2c_master_handle ) { + return hal_ll_module_id; + } else if ( I2C_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static hal_ll_i2c_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof(hal_ll_i2c_master_handle_register_t)); + static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof(hal_ll_i2c_master_handle_register_t)); + + while( hal_ll_module_count-- ) { + if (hal_ll_i2c_get_base_from_hal_handle == hal_ll_i2c_hw_specifics_map[hal_ll_module_count].base) { + return &hal_ll_i2c_hw_specifics_map[hal_ll_module_count]; + } + } + + return &hal_ll_i2c_hw_specifics_map[hal_ll_module_error]; +} + +static void hal_ll_i2c_master_set_clock( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ) { + switch ( map->module_index ) + { + #if defined(I2C_MODULE_1) + case ( hal_ll_i2c_module_num(I2C_MODULE_1) ): + hal_ll_i2c1_set_clock( hal_ll_state ); + break; + #endif + + + default: + break; + } +} + +static void hal_ll_i2c_master_map_pins( uint8_t module_index, hal_ll_i2c_pin_id *index_list ) { + // Map new pins + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_scl.pin_name = hal_ll_i2c_scl_map[ index_list[module_index].pin_scl ].pin; + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_sda.pin_name = hal_ll_i2c_sda_map[ index_list[module_index].pin_sda ].pin; + // SCL and SDA could have different alternate function settings, hence save both AF values + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_scl.pin_af = hal_ll_i2c_scl_map[ index_list[module_index].pin_scl ].af; + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_sda.pin_af = hal_ll_i2c_sda_map[ index_list[module_index].pin_sda ].af; +} + +static void hal_ll_i2c_master_alternate_functions_set_state( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ) { + module_struct module; + + if( (map->pins.pin_scl.pin_name != HAL_LL_PIN_NC) && (map->pins.pin_sda.pin_name != HAL_LL_PIN_NC) ) { + module.pins[0] = VALUE( map->pins.pin_scl.pin_name, map->pins.pin_scl.pin_af ); + module.pins[1] = VALUE( map->pins.pin_sda.pin_name, map->pins.pin_sda.pin_af ); + module.pins[2] = GPIO_MODULE_STRUCT_END; + + module.configs[0] = HAL_LL_I2C_AF_CONFIG; + module.configs[1] = HAL_LL_I2C_AF_CONFIG; + module.configs[2] = GPIO_MODULE_STRUCT_END; + + hal_ll_gpio_module_struct_init( &module, hal_ll_state ); + } +} + +static uint32_t hal_ll_i2c_get_speed( hal_ll_i2c_hw_specifics_map_t *map ) { + if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_FAST ) { + if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_STANDARD ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_100K; + return HAL_LL_I2C_100K; + } else if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_FULL ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_400K; + return HAL_LL_I2C_400K; + } else if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_FAST ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_1M; + return HAL_LL_I2C_1M; + } else { + map->speed = HAL_LL_I2C_MASTER_SPEED_100K; + return HAL_LL_I2C_100K; + } + } else { + if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_100K ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_100K; + return HAL_LL_I2C_100K; + } else if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_400K ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_400K; + return HAL_LL_I2C_400K; + } else if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_1M ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_1M; + return HAL_LL_I2C_1M; + } else { + map->speed = HAL_LL_I2C_MASTER_SPEED_1M; + return HAL_LL_I2C_1M; + } + } +} +static inline void hal_ll_i2c1_set_clock( bool hal_ll_state ) { + if ( hal_ll_state ) { + set_reg_bit( _RCC_APBENR1, HAL_LL_I2C1EN_BIT ); + set_reg_bit( _RCC_CCIPR, HAL_LL_I2C1SEL1_BIT ); + } else { + clear_reg_bit( _RCC_APBENR1, HAL_LL_I2C1EN_BIT ); + clear_reg_bit( _RCC_CCIPR, HAL_LL_I2C1SEL1_BIT ); + } +} + + + +static hal_ll_err_t hal_ll_i2c_hw_init( hal_ll_i2c_hw_specifics_map_t *map ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct(map->base); + uint16_t time_counter = map->timeout; + + clear_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_I2C_PE_BIT ); + while ( check_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_I2C_PE_BIT ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_INIT; + } + } + + hal_ll_hw_reg->cr1 &= HAL_LL_I2C_FILTERS_OFF; + + hal_ll_hw_reg->timingr = hal_ll_i2c_get_speed( map ); + + hal_ll_hw_reg->cr1 |= HAL_LL_I2C_CR1_RXTX_INT; + + set_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_I2C_PE_BIT ); + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static hal_ll_err_t hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_t *map ) { + hal_ll_i2c_master_set_clock( map, true ); + + return hal_ll_i2c_hw_init( map ); +} +// ------------------------------------------------------------------------- END + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_74/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_74/CMakeLists.cmake new file mode 100644 index 000000000..8a3f3464a --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_74/CMakeLists.cmake @@ -0,0 +1,9 @@ +if(${MCU_NAME} MATCHES "^STM32G051C6$|^STM32G051F6$|^STM32G051G6$|^STM32G051K6$|^STM32G051C8$|^STM32G051F8$|^STM32G051G8$|^STM32G051K8$") + set(i2c_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_i2c_master.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_74") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_74") + list(APPEND hal_ll_def_list "STM32G0xx") + list(APPEND hal_ll_def_list "STM32G05xx") + list(APPEND hal_ll_def_list "STM32G051xx") + set(i2c_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/i2c/hal_ll_i2c_pin_map/implementations/doc_ds_74") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_74/hal_ll_i2c_master.c b/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_74/hal_ll_i2c_master.c new file mode 100644 index 000000000..2eaf94125 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_74/hal_ll_i2c_master.c @@ -0,0 +1,933 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_i2c_master.c + * @brief I2C master HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_rcc.h" +#include "hal_ll_gpio.h" +#include "hal_ll_i2c_master.h" +#include "hal_ll_i2c_pin_map.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_i2c_master_handle_register_t hal_ll_module_state[I2C_MODULE_COUNT] = { (handle_t *)NULL, (handle_t *)NULL, false }; + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_i2c_get_module_state_address ((hal_ll_i2c_master_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_i2c_get_handle (hal_ll_i2c_master_handle_register_t *)hal_ll_i2c_get_module_state_address->hal_ll_i2c_master_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_i2c_get_base_struct(_handle) ((hal_ll_i2c_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_i2c_get_base_from_hal_handle ((hal_ll_i2c_hw_specifics_map_t *)((hal_ll_i2c_master_handle_register_t *)\ + (((hal_ll_i2c_master_handle_register_t *)(handle))->hal_ll_i2c_master_handle))->hal_ll_i2c_master_handle)->base + +/*!< @brief Default I2C bit-rate if no speed is set */ +#define HAL_LL_I2C_MASTER_SPEED_100K 100000UL +#define HAL_LL_I2C_MASTER_SPEED_400K 400000UL +#define HAL_LL_I2C_MASTER_SPEED_1M 1000000UL + +/*!< @brief Default pass count value upon reset */ +#define HAL_LL_I2C_DEFAULT_PASS_COUNT 0xFFFFU + +/*!< @brief Macro used for timeout */ +#define HAL_LL_I2C_LOOP_INDEX 10000U + +/*!< @brief Macros defining register bit location */ +#define HAL_LL_I2C1EN_BIT 21 + +#define HAL_LL_I2C2EN_BIT 22 + +#define HAL_LL_I2C12SEL0_BIT 14 + +#define HAL_LL_I2C12SEL1_BIT 15 + + + + +#define HAL_LL_I2C_100K 0x30420F13 //?????????????????? +#define HAL_LL_I2C_400K 0x10320309 //?????????????????? +#define HAL_LL_I2C_1M 0x00200204 //?????????????????? + +#define HAL_LL_I2C_PE_BIT 0 +#define HAL_LL_I2C_CR2_STOP_BIT 14 +#define HAL_LL_I2C_CR2_START_BIT 13 +#define HAL_LL_I2C_ISR_STOPF_BIT 5 +#define HAL_LL_I2C_ISR_BUSY_BIT 15 +#define HAL_LL_I2C_ARLO_BIT 9 +#define HAL_LL_I2C_RXNE_BIT 2 +#define HAL_LL_I2C_TXIS_BIT 1 +#define HAL_LL_I2C_TXE_BIT 0 + +/*!< @brief Macros defining register bit masks */ +#define HAL_LL_I2C_CR1_RXTX_INT 0x6 +#define HAL_LL_I2C_CR2_STOP 0x4000UL +#define HAL_LL_I2C_CR2_START 0x2000U +#define HAL_LL_I2C_CR2_SADD 0x3FFU +#define HAL_LL_I2C_CR2_NBYTES 0xFF0000UL +#define HAL_LL_I2C_CR2_RD_WRN 0x400U +#define HAL_LL_I2C_CR2_RELOAD 0x1000000UL +#define HAL_LL_I2C_CR2_AUTOEND 0x2000000UL +#define HAL_LL_I2C_FILTERS_OFF 0xFFFFE0FFUL +#define HAL_LL_I2C_SADD_MASK 0x3FFUL +#define HAL_LL_I2C_HEAD10R_MASK 0x1000UL +#define HAL_LL_I2C_NBYTES_MASK 0xFF0000UL +#define HAL_LL_I2C_RELOAD_MASK 0x1000000UL +#define HAL_LL_I2C_RD_WRN_MASK 0x400UL + +/*!< @brief Macros used for module pin checking */ +#define HAL_LL_I2C_SCL_PIN 0 +#define HAL_LL_I2C_SDA_PIN 1 +#define HAL_LL_I2C_MODULE_PIN_COUNT 2 + +/*!< @brief Macro used for setting pin alternate functions */ +#define HAL_LL_I2C_AF_CONFIG (GPIO_CFG_MODE_ALT_FUNCTION | GPIO_CFG_SPEED_HIGH | GPIO_CFG_OTYPE_OD) + +// -------------------------------------------------------------- PRIVATE TYPES +/*!< @brief I2C register structure */ +typedef struct +{ + hal_ll_base_addr_t cr1; + hal_ll_base_addr_t cr2; + hal_ll_base_addr_t oar1; + hal_ll_base_addr_t oar2; + hal_ll_base_addr_t timingr; + hal_ll_base_addr_t timeoutr; + hal_ll_base_addr_t isr; + hal_ll_base_addr_t icr; + hal_ll_base_addr_t pecr; + hal_ll_base_addr_t rxdr; + hal_ll_base_addr_t txdr; + +} hal_ll_i2c_base_handle_t; + +/*!< @brief I2C hw specific structure */ +typedef struct +{ + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + hal_ll_i2c_pins_t pins; + uint32_t speed; + uint8_t address; + uint16_t timeout; +} hal_ll_i2c_hw_specifics_map_t; + +/*!< @brief I2C hw specific module values */ +typedef struct +{ + uint16_t pin_scl; + uint16_t pin_sda; +} hal_ll_i2c_pin_id; + +/*!< @brief I2C hw specific error values */ +typedef enum +{ + HAL_LL_I2C_MASTER_SUCCESS = 0, + HAL_LL_I2C_MASTER_WRONG_PINS, + HAL_LL_I2C_MASTER_MODULE_ERROR, + + HAL_LL_I2C_MASTER_ERROR = (-1) +} hal_ll_i2c_master_err_t; + +/*!< @brief I2C end mode selection values */ +typedef enum +{ + HAL_LL_I2C_MASTER_END_MODE_RESTART = 0, + HAL_LL_I2C_MASTER_END_MODE_STOP, + HAL_LL_I2C_MASTER_WRITE_THEN_READ +} hal_ll_i2c_master_end_mode_t; + +/*!< @brief I2C timeout error values */ +typedef enum +{ + HAL_LL_I2C_MASTER_TIMEOUT_START = 1300, + HAL_LL_I2C_MASTER_TIMEOUT_STOP, + HAL_LL_I2C_MASTER_TIMEOUT_WRITE, + HAL_LL_I2C_MASTER_TIMEOUT_READ, + HAL_LL_I2C_MASTER_ARBITRATION_LOST, + HAL_LL_I2C_MASTER_TIMEOUT_INIT +} hal_ll_i2c_master_timeout_t; + +/** + * @brief Enum containing predefined module standard speed values. + * + * Enum values: + * HAL_LL_I2C_MASTER_SPEED_STANDARD -- Speed set at 100K + * HAL_LL_I2C_MASTER_SPEED_FULL -- Speed set at 400K + * HAL_LL_I2C_MASTER_SPEED_FAST -- Speed set at 1M + */ +typedef enum +{ + HAL_LL_I2C_MASTER_SPEED_STANDARD = 0, + HAL_LL_I2C_MASTER_SPEED_FULL, + HAL_LL_I2C_MASTER_SPEED_FAST +} hal_ll_i2c_master_speed_t; + +// ------------------------------------------------------------------ VARIABLES +/*!< @brief I2C hardware specific info */ +static hal_ll_i2c_hw_specifics_map_t hal_ll_i2c_hw_specifics_map[] = +{ + #ifdef I2C_MODULE_1 + {HAL_LL_I2C1_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_1), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, + #endif + + #ifdef I2C_MODULE_2 + {HAL_LL_I2C2_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_2), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, + #endif + + + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, 0, 0} +}; + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_i2c_master_handle_register_t *low_level_handle; +static volatile hal_ll_i2c_hw_specifics_map_t *hal_ll_i2c_hw_specifics_map_local; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Check if pins are adequate. + * + * Checks scl and sda pins the user has passed with pre-defined + * pins in scl and sda maps. Take into consideration that module + * index numbers have to be the same for both pins. + * + * @param[in] scl - SCL pre-defined pin name. + * @param[in] sda - SDA pre-defined pin name. + * @param[in] *index_list - Index list address + * @return hal_ll_pin_name_t Module index based on pins. + * + * Returns pre-defined module index from pin maps, if pins + * are adequate. + */ +static hal_ll_pin_name_t hal_ll_i2c_master_check_pins( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_pin_id *index_list, hal_ll_i2c_master_handle_register_t *handle_map ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_i2c_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_i2c_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_i2c_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Get adequate I2C bit-rate value. + * + * Returns one of pre-defined bit-rate values, + * or the closest bit-rate based on bit_rate + * value passed to the function. + * + * @param[in] bit_rate - I2C bit rate. + * @return uint32_t Adequate bit-rate value. + * + * Returns adequate value to be latter written into bare metal register address. + * Take into consideration that this returns a predefined value. + * + * HAL_LL_I2C_MASTER_SPEED_100K -- 100Kbit/s + * HAL_LL_I2C_MASTER_SPEED_400K -- 400Kbit/s + * HAL_LL_I2C_MASTER_SPEED_1M -- 1Mbit/s + * HAL_LL_I2C_MASTER_SPEED_3M2 -- 3.2Mbit/s + */ +static uint32_t hal_ll_i2c_get_speed( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Enable clock for I2C1 module on hardware level. + * + * Initializes I2C1 module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] hal_ll_state - True/False -- Init/De-init + * + * @return None + */ +static inline void hal_ll_i2c1_set_clock( bool hal_ll_state ); + +/** + * @brief Enable clock for I2C2 module on hardware level. + * + * Initializes I2C2 module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] hal_ll_state - True/False -- Init/De-init + * + * @return None + */ +static inline void hal_ll_i2c2_set_clock( bool hal_ll_state ); + +/** + * @brief Enable clock for I2C module on hardware level. + * + * Initializes I2C module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_stat - True(enable clock)/False(disable clock). + * + * @return None + */ +static void hal_ll_i2c_master_set_clock( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Initialize I2C module on hardware level. + * + * Initializes I2C module on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] map - Object specific context handler. + * @return hal_ll_err_t Module specific return values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_hw_init( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * I2C SCL and SDA pins. + * + * @param[in] module_index I2C HW module index -- 0,1,2... + * @param[in] *index_list Array with SCL and SDA map index values + * and module number + * + * @return None + */ +static void hal_ll_i2c_master_map_pins( uint8_t module_index, hal_ll_i2c_pin_id *index_list ); + +/** + * @brief Sets I2C pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if I2C is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_state - Init/De-init + * + * @return None + */ +static void hal_ll_i2c_master_alternate_functions_set_state( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Full I2C module initialization procedure. + * + * Initializes I2C module on hardware level, based on beforehand + * set configuration and module handler. Sets adequate pin alternate functions. + * Initializes module clock. + * + * @param[in] map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Configure I2C module for data transfer. + * + * @param[in] hal_ll_hw_reg - I2C module base address. + * @param[in] config - I2C config bits. + * @return void None. + */ +static void hal_ll_i2c_master_configure_transfer( hal_ll_i2c_base_handle_t *hal_ll_hw_reg, uint32_t config ); + +/** + * @brief Reset value of I2C CR2 register. + * + * @param[in] hal_ll_hw_reg - I2C module base address. + * @returnl none + */ +static void hal_ll_i2c_master_reset_cr2( hal_ll_i2c_base_handle_t *hal_ll_hw_reg ); + +/** + * @brief Generates start signal on I2C bus. + * + * Generates a start signal on the I2C bus. + * + * @param[in] map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_master_start( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Generates stop signal on I2C bus. + * + * Generates a stop signal on the I2C bus. + * + * @param[in] map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_master_stop( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Perform a read on the I2C bus. + * + * Initializes I2C module on hardware level, if not initialized beforehand + * and continues to perform a read operation on the bus. + * + * @param[in] map - Object specific context handler. + * @param[in] readDatabuf - Pointer to data buffer. + * @param[in] lenReadData - Number of data to be read. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *read_data_buf, size_t len_read_data, hal_ll_i2c_master_end_mode_t mode ); + +/** + * @brief Perform a write on the I2C bus. + * + * Initializes I2C module on hardware level, if not initialized beforehand + * and continues to perform a write operation on the bus. + * + * @param[in] map - Object specific context handler. + * @param[in] writeDatabuf - Pointer to data buffer. + * @param[in] lenWriteData - Number of data to be written. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *write_data_buf, size_t len_write_data, hal_ll_i2c_master_end_mode_t mode ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_i2c_master_register_handle( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_master_handle_register_t *handle_map, uint8_t *hal_module_id ) { + + hal_ll_i2c_pin_id index_list[I2C_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + uint16_t pin_check_result; + + // Check if pins are valid + if ( (pin_check_result = hal_ll_i2c_master_check_pins( scl, sda, &index_list, handle_map )) == HAL_LL_PIN_NC ) { + return HAL_LL_I2C_MASTER_WRONG_PINS; + }; + + if ( (hal_ll_i2c_hw_specifics_map[pin_check_result].pins.pin_scl.pin_name != scl) || + (hal_ll_i2c_hw_specifics_map[pin_check_result].pins.pin_sda.pin_name != sda) ) + { + hal_ll_i2c_master_alternate_functions_set_state( &hal_ll_i2c_hw_specifics_map[ pin_check_result ], false ); + + hal_ll_i2c_master_map_pins( pin_check_result, &index_list ); + + hal_ll_i2c_master_alternate_functions_set_state( &hal_ll_i2c_hw_specifics_map[ pin_check_result ], true ); + + handle_map[pin_check_result].init_ll_state = false; + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[pin_check_result].hal_ll_i2c_master_handle = (handle_t *)&hal_ll_i2c_hw_specifics_map[pin_check_result].base; + + handle_map[pin_check_result].hal_ll_i2c_master_handle = (handle_t *)&hal_ll_module_state[pin_check_result].hal_ll_i2c_master_handle; + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_i2c( handle_t *handle ) { + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + hal_ll_i2c_master_handle_register_t *hal_handle = (hal_ll_i2c_master_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_i2c_hw_specifics_map_local->module_index; + + hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_local ); + + hal_ll_module_state[pin_check_result].hal_ll_i2c_master_handle = (handle_t *)&hal_ll_i2c_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_i2c_master_set_speed( handle_t *handle, uint32_t speed ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + low_level_handle->init_ll_state = false; + + hal_ll_i2c_hw_specifics_map_local->speed = speed; + + if ( hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_local ) != HAL_LL_I2C_MASTER_SUCCESS ) { + return HAL_LL_I2C_MASTER_TIMEOUT_INIT; + } + + low_level_handle->init_ll_state = true; + + return hal_ll_i2c_hw_specifics_map_local->speed; +} + +void hal_ll_i2c_master_set_timeout( handle_t *handle, uint16_t timeout ) { + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + if( hal_ll_i2c_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + hal_ll_i2c_hw_specifics_map_local->timeout = timeout; + } +} + +void hal_ll_i2c_master_set_slave_address( handle_t *handle, uint8_t addr ) { + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + if( hal_ll_i2c_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + hal_ll_i2c_hw_specifics_map_local->address = addr; + } +} + +hal_ll_err_t hal_ll_i2c_master_read( handle_t *handle, uint8_t *read_data_buf, size_t len_read_data ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + return hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_local, read_data_buf, len_read_data, HAL_LL_I2C_MASTER_END_MODE_STOP ); +} + +hal_ll_err_t hal_ll_i2c_master_write( handle_t *handle, uint8_t *write_data_buf, size_t len_write_data ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + return hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_local, write_data_buf, len_write_data, HAL_LL_I2C_MASTER_END_MODE_STOP ); +} + +hal_ll_err_t hal_ll_i2c_master_write_then_read( handle_t *handle, uint8_t *write_data_buf, size_t len_write_data, uint8_t *read_data_buf, size_t len_read_data ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + if( hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_local, write_data_buf, len_write_data, HAL_LL_I2C_MASTER_WRITE_THEN_READ ) != NULL ) { + return HAL_LL_I2C_MASTER_TIMEOUT_WRITE; + } + + /** + * @note Wait for drivers to set-up + * correctly. + **/ + #ifdef __TFT_RESISTIVE_TSC2003__ + Delay_22us(); + #endif + + if( hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_local, read_data_buf, len_read_data, HAL_LL_I2C_MASTER_WRITE_THEN_READ ) != NULL ) { + return HAL_LL_I2C_MASTER_TIMEOUT_READ; + } + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +void hal_ll_i2c_master_close( handle_t *handle ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + if( low_level_handle->hal_ll_i2c_master_handle != NULL ) { + low_level_handle->hal_ll_i2c_master_handle = NULL; + low_level_handle->hal_drv_i2c_master_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_i2c_hw_specifics_map_local->address = 0; + hal_ll_i2c_hw_specifics_map_local->timeout = HAL_LL_I2C_DEFAULT_PASS_COUNT; + hal_ll_i2c_hw_specifics_map_local->speed = HAL_LL_I2C_MASTER_SPEED_100K; + + hal_ll_i2c_master_set_clock(hal_ll_i2c_hw_specifics_map_local, true); + hal_ll_i2c_master_alternate_functions_set_state( hal_ll_i2c_hw_specifics_map_local, false ); + hal_ll_i2c_master_set_clock(hal_ll_i2c_hw_specifics_map_local, false); + + hal_ll_i2c_hw_specifics_map_local->pins.pin_scl.pin_name = HAL_LL_PIN_NC; + hal_ll_i2c_hw_specifics_map_local->pins.pin_sda.pin_name = HAL_LL_PIN_NC; + hal_ll_i2c_hw_specifics_map_local->pins.pin_scl.pin_af = 0; + hal_ll_i2c_hw_specifics_map_local->pins.pin_sda.pin_af = 0; + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static hal_ll_err_t hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *read_data_buf, size_t len_read_data, hal_ll_i2c_master_end_mode_t mode ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct(map->base); + uint16_t time_counter = map->timeout; + size_t transfer_counter = NULL; + uint8_t status = NULL; + + /** + * @note When R/W = 0, the input sample acquisition period starts + * on the falling edge of SCL once the C0 bit of the command + * byte has been latched, and ends when a Stop or + * repeated Start condition has been issued. + **/ + #ifdef __TFT_RESISTIVE_TSC2003__ + Delay_1ms(); + #endif + + hal_ll_i2c_master_configure_transfer ( map->base, + ( map->address << 1 & HAL_LL_I2C_CR2_SADD ) | + ( len_read_data << 16 & HAL_LL_I2C_CR2_NBYTES ) | + HAL_LL_I2C_CR2_RD_WRN | + HAL_LL_I2C_CR2_START + ); + + for ( transfer_counter; transfer_counter < len_read_data; transfer_counter++ ) { + while ( !( check_reg_bit( &( hal_ll_hw_reg->isr ), HAL_LL_I2C_RXNE_BIT ) ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_READ; + } + } + read_data_buf[ transfer_counter ] = hal_ll_hw_reg->rxdr; + } + + if ( ( mode == HAL_LL_I2C_MASTER_END_MODE_STOP ) || ( mode == HAL_LL_I2C_MASTER_WRITE_THEN_READ ) ) { + status = hal_ll_i2c_master_stop( map ); + } else { + status = hal_ll_i2c_master_start( map ); + } + + if( status != HAL_LL_I2C_MASTER_SUCCESS ) { + return status; + } + + hal_ll_i2c_master_reset_cr2( hal_ll_hw_reg ); + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static hal_ll_err_t hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *write_data_buf, size_t len_write_data, hal_ll_i2c_master_end_mode_t mode ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct(map->base); + uint16_t time_counter = map->timeout; + size_t transfer_counter = NULL; + uint8_t status = NULL; + + hal_ll_i2c_master_configure_transfer ( map->base, + ( map->address << 1 & HAL_LL_I2C_CR2_SADD ) | + ( len_write_data << 16 & HAL_LL_I2C_CR2_NBYTES ) | + !HAL_LL_I2C_CR2_RD_WRN | + HAL_LL_I2C_CR2_START + ); + + for ( transfer_counter; transfer_counter < len_write_data; transfer_counter++ ) + { + while ( !( check_reg_bit( &( hal_ll_hw_reg->isr ), HAL_LL_I2C_TXIS_BIT ) ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_WRITE; + } + } + hal_ll_hw_reg->txdr = write_data_buf[ transfer_counter ]; + } + + time_counter = map->timeout; + while ( !( check_reg_bit( &( hal_ll_hw_reg->isr ), HAL_LL_I2C_TXE_BIT ) ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_WRITE; + } + } + + if ( mode == HAL_LL_I2C_MASTER_END_MODE_STOP ) + { + hal_ll_i2c_master_stop( map ); + } + + hal_ll_i2c_master_reset_cr2( hal_ll_hw_reg ); + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static void hal_ll_i2c_master_configure_transfer( hal_ll_i2c_base_handle_t *hal_ll_hw_reg, uint32_t config ) { + uint32_t reg = 0; + + // Clear last set slave address + hal_ll_hw_reg->cr2 &= ~HAL_LL_I2C_CR2_SADD; + + reg = hal_ll_hw_reg->cr2; + reg &= ~( uint32_t )( + ( HAL_LL_I2C_CR2_SADD ) | + ( HAL_LL_I2C_CR2_NBYTES ) | + ( HAL_LL_I2C_CR2_RELOAD ) | + ( HAL_LL_I2C_CR2_AUTOEND ) | + ( HAL_LL_I2C_CR2_RD_WRN ) | + ( HAL_LL_I2C_CR2_START ) | + ( HAL_LL_I2C_CR2_STOP ) + ); + + reg |= config; + hal_ll_hw_reg->cr2 = reg; +} + +static void hal_ll_i2c_master_reset_cr2( hal_ll_i2c_base_handle_t *hal_ll_hw_reg ) { + hal_ll_hw_reg->cr2 &= ~( uint32_t ) + ( + HAL_LL_I2C_SADD_MASK | + HAL_LL_I2C_HEAD10R_MASK | + HAL_LL_I2C_NBYTES_MASK | + HAL_LL_I2C_RELOAD_MASK | + HAL_LL_I2C_RD_WRN_MASK + ); +} + +static hal_ll_err_t hal_ll_i2c_master_start( hal_ll_i2c_hw_specifics_map_t *map ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct(map->base); + uint16_t loop_index = HAL_LL_I2C_LOOP_INDEX; + + set_reg_bit( &(hal_ll_hw_reg->cr2), HAL_LL_I2C_CR2_START_BIT ); + + if ( check_reg_bit( &( hal_ll_hw_reg->isr ), HAL_LL_I2C_ARLO_BIT ) ) + return HAL_LL_I2C_MASTER_ARBITRATION_LOST; + + while ( loop_index-- ) + assembly(nop); + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static hal_ll_err_t hal_ll_i2c_master_stop( hal_ll_i2c_hw_specifics_map_t *map ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = ( hal_ll_i2c_base_handle_t* )map->base; + uint16_t time_counter = map->timeout; + uint32_t loop_index = HAL_LL_I2C_LOOP_INDEX; + + set_reg_bit( &(hal_ll_hw_reg->cr2), HAL_LL_I2C_CR2_STOP_BIT ); + + while ( !( hal_ll_hw_reg->isr & HAL_LL_I2C_ISR_STOPF_BIT ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_STOP; + } + } + + if ( map->timeout < HAL_LL_I2C_LOOP_INDEX ) { + while ( loop_index-- ) + assembly(nop); + } + + hal_ll_hw_reg->isr &= ~HAL_LL_I2C_ISR_STOPF_BIT; + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static hal_ll_pin_name_t hal_ll_i2c_master_check_pins( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_pin_id *index_list, hal_ll_i2c_master_handle_register_t *handle_map ) { + static const uint16_t scl_map_size = ( sizeof( hal_ll_i2c_scl_map ) / sizeof( hal_ll_i2c_pin_map_t ) ); + static const uint16_t sda_map_size = ( sizeof( hal_ll_i2c_sda_map ) / sizeof( hal_ll_i2c_pin_map_t ) ); + uint8_t hal_ll_module_id = 0; + uint8_t index_counter = 0; + uint16_t scl_index; + uint16_t sda_index; + + if ( (HAL_LL_PIN_NC == scl) || (HAL_LL_PIN_NC == sda) ) { + return HAL_LL_PIN_NC; + } + + for ( scl_index = 0; scl_index < scl_map_size; scl_index++ ) { + if ( hal_ll_i2c_scl_map[ scl_index ].pin == scl ) { + for ( sda_index = 0; sda_index < sda_map_size; sda_index++ ) { + if ( hal_ll_i2c_sda_map[ sda_index ].pin == sda ) { + if ( hal_ll_i2c_scl_map[ scl_index ].module_index == hal_ll_i2c_sda_map[ sda_index ].module_index ) { + // Get module number + hal_ll_module_id = hal_ll_i2c_scl_map[ scl_index ].module_index; + // Map pin names + index_list[hal_ll_module_id].pin_scl = scl_index; + index_list[hal_ll_module_id].pin_sda = sda_index; + + // Check if module is taken + if ( NULL == handle_map[ hal_ll_module_id ].hal_drv_i2c_master_handle ) { + return hal_ll_module_id; + } else if ( I2C_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static hal_ll_i2c_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof(hal_ll_i2c_master_handle_register_t)); + static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof(hal_ll_i2c_master_handle_register_t)); + + while( hal_ll_module_count-- ) { + if (hal_ll_i2c_get_base_from_hal_handle == hal_ll_i2c_hw_specifics_map[hal_ll_module_count].base) { + return &hal_ll_i2c_hw_specifics_map[hal_ll_module_count]; + } + } + + return &hal_ll_i2c_hw_specifics_map[hal_ll_module_error]; +} + +static void hal_ll_i2c_master_set_clock( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ) { + switch ( map->module_index ) + { + #if defined(I2C_MODULE_1) + case ( hal_ll_i2c_module_num(I2C_MODULE_1) ): + hal_ll_i2c1_set_clock( hal_ll_state ); + break; + #endif + + #if defined(I2C_MODULE_2) + case ( hal_ll_i2c_module_num(I2C_MODULE_2) ): + hal_ll_i2c2_set_clock( hal_ll_state ); + break; + #endif + + + default: + break; + } +} + +static void hal_ll_i2c_master_map_pins( uint8_t module_index, hal_ll_i2c_pin_id *index_list ) { + // Map new pins + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_scl.pin_name = hal_ll_i2c_scl_map[ index_list[module_index].pin_scl ].pin; + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_sda.pin_name = hal_ll_i2c_sda_map[ index_list[module_index].pin_sda ].pin; + // SCL and SDA could have different alternate function settings, hence save both AF values + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_scl.pin_af = hal_ll_i2c_scl_map[ index_list[module_index].pin_scl ].af; + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_sda.pin_af = hal_ll_i2c_sda_map[ index_list[module_index].pin_sda ].af; +} + +static void hal_ll_i2c_master_alternate_functions_set_state( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ) { + module_struct module; + + if( (map->pins.pin_scl.pin_name != HAL_LL_PIN_NC) && (map->pins.pin_sda.pin_name != HAL_LL_PIN_NC) ) { + module.pins[0] = VALUE( map->pins.pin_scl.pin_name, map->pins.pin_scl.pin_af ); + module.pins[1] = VALUE( map->pins.pin_sda.pin_name, map->pins.pin_sda.pin_af ); + module.pins[2] = GPIO_MODULE_STRUCT_END; + + module.configs[0] = HAL_LL_I2C_AF_CONFIG; + module.configs[1] = HAL_LL_I2C_AF_CONFIG; + module.configs[2] = GPIO_MODULE_STRUCT_END; + + hal_ll_gpio_module_struct_init( &module, hal_ll_state ); + } +} + +static uint32_t hal_ll_i2c_get_speed( hal_ll_i2c_hw_specifics_map_t *map ) { + if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_FAST ) { + if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_STANDARD ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_100K; + return HAL_LL_I2C_100K; + } else if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_FULL ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_400K; + return HAL_LL_I2C_400K; + } else if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_FAST ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_1M; + return HAL_LL_I2C_1M; + } else { + map->speed = HAL_LL_I2C_MASTER_SPEED_100K; + return HAL_LL_I2C_100K; + } + } else { + if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_100K ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_100K; + return HAL_LL_I2C_100K; + } else if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_400K ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_400K; + return HAL_LL_I2C_400K; + } else if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_1M ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_1M; + return HAL_LL_I2C_1M; + } else { + map->speed = HAL_LL_I2C_MASTER_SPEED_1M; + return HAL_LL_I2C_1M; + } + } +} +static inline void hal_ll_i2c1_set_clock( bool hal_ll_state ) { + if ( hal_ll_state ) { + set_reg_bit( _RCC_APBENR1, HAL_LL_I2C1EN_BIT ); + set_reg_bit( _RCC_CCIPR, HAL_LL_I2C12SEL1_BIT ); + } else { + clear_reg_bit( _RCC_APBENR1, HAL_LL_I2C1EN_BIT ); + clear_reg_bit( _RCC_CCIPR, HAL_LL_I2C12SEL1_BIT ); + } +} + + +static inline void hal_ll_i2c2_set_clock( bool hal_ll_state ) { + if ( hal_ll_state ) { + set_reg_bit( _RCC_APBENR1, HAL_LL_I2C2EN_BIT ); + set_reg_bit( _RCC_CCIPR, HAL_LL_I2C12SEL1_BIT ); + } else { + clear_reg_bit( _RCC_APBENR1, HAL_LL_I2C2EN_BIT ); + clear_reg_bit( _RCC_CCIPR, HAL_LL_I2C12SEL1_BIT ); + } +} + + + +static hal_ll_err_t hal_ll_i2c_hw_init( hal_ll_i2c_hw_specifics_map_t *map ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct(map->base); + uint16_t time_counter = map->timeout; + + clear_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_I2C_PE_BIT ); + while ( check_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_I2C_PE_BIT ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_INIT; + } + } + + hal_ll_hw_reg->cr1 &= HAL_LL_I2C_FILTERS_OFF; + + hal_ll_hw_reg->timingr = hal_ll_i2c_get_speed( map ); + + hal_ll_hw_reg->cr1 |= HAL_LL_I2C_CR1_RXTX_INT; + + set_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_I2C_PE_BIT ); + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static hal_ll_err_t hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_t *map ) { + hal_ll_i2c_master_set_clock( map, true ); + + return hal_ll_i2c_hw_init( map ); +} +// ------------------------------------------------------------------------- END + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_75/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_75/CMakeLists.cmake new file mode 100644 index 000000000..f13f7f0a6 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_75/CMakeLists.cmake @@ -0,0 +1,9 @@ +if(${MCU_NAME} MATCHES "^STM32G061C6$|^STM32G061F6$|^STM32G061G6$|^STM32G061K6$|^STM32G061C8$|^STM32G061F8$|^STM32G061G8$|^STM32G061K8$") + set(i2c_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_i2c_master.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_75") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_75") + list(APPEND hal_ll_def_list "STM32G0xx") + list(APPEND hal_ll_def_list "STM32G06xx") + list(APPEND hal_ll_def_list "STM32G061xx") + set(i2c_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/i2c/hal_ll_i2c_pin_map/implementations/doc_ds_75") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_75/hal_ll_i2c_master.c b/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_75/hal_ll_i2c_master.c new file mode 100644 index 000000000..2eaf94125 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_75/hal_ll_i2c_master.c @@ -0,0 +1,933 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_i2c_master.c + * @brief I2C master HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_rcc.h" +#include "hal_ll_gpio.h" +#include "hal_ll_i2c_master.h" +#include "hal_ll_i2c_pin_map.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_i2c_master_handle_register_t hal_ll_module_state[I2C_MODULE_COUNT] = { (handle_t *)NULL, (handle_t *)NULL, false }; + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_i2c_get_module_state_address ((hal_ll_i2c_master_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_i2c_get_handle (hal_ll_i2c_master_handle_register_t *)hal_ll_i2c_get_module_state_address->hal_ll_i2c_master_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_i2c_get_base_struct(_handle) ((hal_ll_i2c_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_i2c_get_base_from_hal_handle ((hal_ll_i2c_hw_specifics_map_t *)((hal_ll_i2c_master_handle_register_t *)\ + (((hal_ll_i2c_master_handle_register_t *)(handle))->hal_ll_i2c_master_handle))->hal_ll_i2c_master_handle)->base + +/*!< @brief Default I2C bit-rate if no speed is set */ +#define HAL_LL_I2C_MASTER_SPEED_100K 100000UL +#define HAL_LL_I2C_MASTER_SPEED_400K 400000UL +#define HAL_LL_I2C_MASTER_SPEED_1M 1000000UL + +/*!< @brief Default pass count value upon reset */ +#define HAL_LL_I2C_DEFAULT_PASS_COUNT 0xFFFFU + +/*!< @brief Macro used for timeout */ +#define HAL_LL_I2C_LOOP_INDEX 10000U + +/*!< @brief Macros defining register bit location */ +#define HAL_LL_I2C1EN_BIT 21 + +#define HAL_LL_I2C2EN_BIT 22 + +#define HAL_LL_I2C12SEL0_BIT 14 + +#define HAL_LL_I2C12SEL1_BIT 15 + + + + +#define HAL_LL_I2C_100K 0x30420F13 //?????????????????? +#define HAL_LL_I2C_400K 0x10320309 //?????????????????? +#define HAL_LL_I2C_1M 0x00200204 //?????????????????? + +#define HAL_LL_I2C_PE_BIT 0 +#define HAL_LL_I2C_CR2_STOP_BIT 14 +#define HAL_LL_I2C_CR2_START_BIT 13 +#define HAL_LL_I2C_ISR_STOPF_BIT 5 +#define HAL_LL_I2C_ISR_BUSY_BIT 15 +#define HAL_LL_I2C_ARLO_BIT 9 +#define HAL_LL_I2C_RXNE_BIT 2 +#define HAL_LL_I2C_TXIS_BIT 1 +#define HAL_LL_I2C_TXE_BIT 0 + +/*!< @brief Macros defining register bit masks */ +#define HAL_LL_I2C_CR1_RXTX_INT 0x6 +#define HAL_LL_I2C_CR2_STOP 0x4000UL +#define HAL_LL_I2C_CR2_START 0x2000U +#define HAL_LL_I2C_CR2_SADD 0x3FFU +#define HAL_LL_I2C_CR2_NBYTES 0xFF0000UL +#define HAL_LL_I2C_CR2_RD_WRN 0x400U +#define HAL_LL_I2C_CR2_RELOAD 0x1000000UL +#define HAL_LL_I2C_CR2_AUTOEND 0x2000000UL +#define HAL_LL_I2C_FILTERS_OFF 0xFFFFE0FFUL +#define HAL_LL_I2C_SADD_MASK 0x3FFUL +#define HAL_LL_I2C_HEAD10R_MASK 0x1000UL +#define HAL_LL_I2C_NBYTES_MASK 0xFF0000UL +#define HAL_LL_I2C_RELOAD_MASK 0x1000000UL +#define HAL_LL_I2C_RD_WRN_MASK 0x400UL + +/*!< @brief Macros used for module pin checking */ +#define HAL_LL_I2C_SCL_PIN 0 +#define HAL_LL_I2C_SDA_PIN 1 +#define HAL_LL_I2C_MODULE_PIN_COUNT 2 + +/*!< @brief Macro used for setting pin alternate functions */ +#define HAL_LL_I2C_AF_CONFIG (GPIO_CFG_MODE_ALT_FUNCTION | GPIO_CFG_SPEED_HIGH | GPIO_CFG_OTYPE_OD) + +// -------------------------------------------------------------- PRIVATE TYPES +/*!< @brief I2C register structure */ +typedef struct +{ + hal_ll_base_addr_t cr1; + hal_ll_base_addr_t cr2; + hal_ll_base_addr_t oar1; + hal_ll_base_addr_t oar2; + hal_ll_base_addr_t timingr; + hal_ll_base_addr_t timeoutr; + hal_ll_base_addr_t isr; + hal_ll_base_addr_t icr; + hal_ll_base_addr_t pecr; + hal_ll_base_addr_t rxdr; + hal_ll_base_addr_t txdr; + +} hal_ll_i2c_base_handle_t; + +/*!< @brief I2C hw specific structure */ +typedef struct +{ + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + hal_ll_i2c_pins_t pins; + uint32_t speed; + uint8_t address; + uint16_t timeout; +} hal_ll_i2c_hw_specifics_map_t; + +/*!< @brief I2C hw specific module values */ +typedef struct +{ + uint16_t pin_scl; + uint16_t pin_sda; +} hal_ll_i2c_pin_id; + +/*!< @brief I2C hw specific error values */ +typedef enum +{ + HAL_LL_I2C_MASTER_SUCCESS = 0, + HAL_LL_I2C_MASTER_WRONG_PINS, + HAL_LL_I2C_MASTER_MODULE_ERROR, + + HAL_LL_I2C_MASTER_ERROR = (-1) +} hal_ll_i2c_master_err_t; + +/*!< @brief I2C end mode selection values */ +typedef enum +{ + HAL_LL_I2C_MASTER_END_MODE_RESTART = 0, + HAL_LL_I2C_MASTER_END_MODE_STOP, + HAL_LL_I2C_MASTER_WRITE_THEN_READ +} hal_ll_i2c_master_end_mode_t; + +/*!< @brief I2C timeout error values */ +typedef enum +{ + HAL_LL_I2C_MASTER_TIMEOUT_START = 1300, + HAL_LL_I2C_MASTER_TIMEOUT_STOP, + HAL_LL_I2C_MASTER_TIMEOUT_WRITE, + HAL_LL_I2C_MASTER_TIMEOUT_READ, + HAL_LL_I2C_MASTER_ARBITRATION_LOST, + HAL_LL_I2C_MASTER_TIMEOUT_INIT +} hal_ll_i2c_master_timeout_t; + +/** + * @brief Enum containing predefined module standard speed values. + * + * Enum values: + * HAL_LL_I2C_MASTER_SPEED_STANDARD -- Speed set at 100K + * HAL_LL_I2C_MASTER_SPEED_FULL -- Speed set at 400K + * HAL_LL_I2C_MASTER_SPEED_FAST -- Speed set at 1M + */ +typedef enum +{ + HAL_LL_I2C_MASTER_SPEED_STANDARD = 0, + HAL_LL_I2C_MASTER_SPEED_FULL, + HAL_LL_I2C_MASTER_SPEED_FAST +} hal_ll_i2c_master_speed_t; + +// ------------------------------------------------------------------ VARIABLES +/*!< @brief I2C hardware specific info */ +static hal_ll_i2c_hw_specifics_map_t hal_ll_i2c_hw_specifics_map[] = +{ + #ifdef I2C_MODULE_1 + {HAL_LL_I2C1_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_1), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, + #endif + + #ifdef I2C_MODULE_2 + {HAL_LL_I2C2_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_2), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, + #endif + + + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, 0, 0} +}; + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_i2c_master_handle_register_t *low_level_handle; +static volatile hal_ll_i2c_hw_specifics_map_t *hal_ll_i2c_hw_specifics_map_local; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Check if pins are adequate. + * + * Checks scl and sda pins the user has passed with pre-defined + * pins in scl and sda maps. Take into consideration that module + * index numbers have to be the same for both pins. + * + * @param[in] scl - SCL pre-defined pin name. + * @param[in] sda - SDA pre-defined pin name. + * @param[in] *index_list - Index list address + * @return hal_ll_pin_name_t Module index based on pins. + * + * Returns pre-defined module index from pin maps, if pins + * are adequate. + */ +static hal_ll_pin_name_t hal_ll_i2c_master_check_pins( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_pin_id *index_list, hal_ll_i2c_master_handle_register_t *handle_map ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_i2c_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_i2c_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_i2c_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Get adequate I2C bit-rate value. + * + * Returns one of pre-defined bit-rate values, + * or the closest bit-rate based on bit_rate + * value passed to the function. + * + * @param[in] bit_rate - I2C bit rate. + * @return uint32_t Adequate bit-rate value. + * + * Returns adequate value to be latter written into bare metal register address. + * Take into consideration that this returns a predefined value. + * + * HAL_LL_I2C_MASTER_SPEED_100K -- 100Kbit/s + * HAL_LL_I2C_MASTER_SPEED_400K -- 400Kbit/s + * HAL_LL_I2C_MASTER_SPEED_1M -- 1Mbit/s + * HAL_LL_I2C_MASTER_SPEED_3M2 -- 3.2Mbit/s + */ +static uint32_t hal_ll_i2c_get_speed( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Enable clock for I2C1 module on hardware level. + * + * Initializes I2C1 module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] hal_ll_state - True/False -- Init/De-init + * + * @return None + */ +static inline void hal_ll_i2c1_set_clock( bool hal_ll_state ); + +/** + * @brief Enable clock for I2C2 module on hardware level. + * + * Initializes I2C2 module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] hal_ll_state - True/False -- Init/De-init + * + * @return None + */ +static inline void hal_ll_i2c2_set_clock( bool hal_ll_state ); + +/** + * @brief Enable clock for I2C module on hardware level. + * + * Initializes I2C module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_stat - True(enable clock)/False(disable clock). + * + * @return None + */ +static void hal_ll_i2c_master_set_clock( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Initialize I2C module on hardware level. + * + * Initializes I2C module on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] map - Object specific context handler. + * @return hal_ll_err_t Module specific return values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_hw_init( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * I2C SCL and SDA pins. + * + * @param[in] module_index I2C HW module index -- 0,1,2... + * @param[in] *index_list Array with SCL and SDA map index values + * and module number + * + * @return None + */ +static void hal_ll_i2c_master_map_pins( uint8_t module_index, hal_ll_i2c_pin_id *index_list ); + +/** + * @brief Sets I2C pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if I2C is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_state - Init/De-init + * + * @return None + */ +static void hal_ll_i2c_master_alternate_functions_set_state( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Full I2C module initialization procedure. + * + * Initializes I2C module on hardware level, based on beforehand + * set configuration and module handler. Sets adequate pin alternate functions. + * Initializes module clock. + * + * @param[in] map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Configure I2C module for data transfer. + * + * @param[in] hal_ll_hw_reg - I2C module base address. + * @param[in] config - I2C config bits. + * @return void None. + */ +static void hal_ll_i2c_master_configure_transfer( hal_ll_i2c_base_handle_t *hal_ll_hw_reg, uint32_t config ); + +/** + * @brief Reset value of I2C CR2 register. + * + * @param[in] hal_ll_hw_reg - I2C module base address. + * @returnl none + */ +static void hal_ll_i2c_master_reset_cr2( hal_ll_i2c_base_handle_t *hal_ll_hw_reg ); + +/** + * @brief Generates start signal on I2C bus. + * + * Generates a start signal on the I2C bus. + * + * @param[in] map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_master_start( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Generates stop signal on I2C bus. + * + * Generates a stop signal on the I2C bus. + * + * @param[in] map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_master_stop( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Perform a read on the I2C bus. + * + * Initializes I2C module on hardware level, if not initialized beforehand + * and continues to perform a read operation on the bus. + * + * @param[in] map - Object specific context handler. + * @param[in] readDatabuf - Pointer to data buffer. + * @param[in] lenReadData - Number of data to be read. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *read_data_buf, size_t len_read_data, hal_ll_i2c_master_end_mode_t mode ); + +/** + * @brief Perform a write on the I2C bus. + * + * Initializes I2C module on hardware level, if not initialized beforehand + * and continues to perform a write operation on the bus. + * + * @param[in] map - Object specific context handler. + * @param[in] writeDatabuf - Pointer to data buffer. + * @param[in] lenWriteData - Number of data to be written. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *write_data_buf, size_t len_write_data, hal_ll_i2c_master_end_mode_t mode ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_i2c_master_register_handle( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_master_handle_register_t *handle_map, uint8_t *hal_module_id ) { + + hal_ll_i2c_pin_id index_list[I2C_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + uint16_t pin_check_result; + + // Check if pins are valid + if ( (pin_check_result = hal_ll_i2c_master_check_pins( scl, sda, &index_list, handle_map )) == HAL_LL_PIN_NC ) { + return HAL_LL_I2C_MASTER_WRONG_PINS; + }; + + if ( (hal_ll_i2c_hw_specifics_map[pin_check_result].pins.pin_scl.pin_name != scl) || + (hal_ll_i2c_hw_specifics_map[pin_check_result].pins.pin_sda.pin_name != sda) ) + { + hal_ll_i2c_master_alternate_functions_set_state( &hal_ll_i2c_hw_specifics_map[ pin_check_result ], false ); + + hal_ll_i2c_master_map_pins( pin_check_result, &index_list ); + + hal_ll_i2c_master_alternate_functions_set_state( &hal_ll_i2c_hw_specifics_map[ pin_check_result ], true ); + + handle_map[pin_check_result].init_ll_state = false; + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[pin_check_result].hal_ll_i2c_master_handle = (handle_t *)&hal_ll_i2c_hw_specifics_map[pin_check_result].base; + + handle_map[pin_check_result].hal_ll_i2c_master_handle = (handle_t *)&hal_ll_module_state[pin_check_result].hal_ll_i2c_master_handle; + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_i2c( handle_t *handle ) { + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + hal_ll_i2c_master_handle_register_t *hal_handle = (hal_ll_i2c_master_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_i2c_hw_specifics_map_local->module_index; + + hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_local ); + + hal_ll_module_state[pin_check_result].hal_ll_i2c_master_handle = (handle_t *)&hal_ll_i2c_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_i2c_master_set_speed( handle_t *handle, uint32_t speed ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + low_level_handle->init_ll_state = false; + + hal_ll_i2c_hw_specifics_map_local->speed = speed; + + if ( hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_local ) != HAL_LL_I2C_MASTER_SUCCESS ) { + return HAL_LL_I2C_MASTER_TIMEOUT_INIT; + } + + low_level_handle->init_ll_state = true; + + return hal_ll_i2c_hw_specifics_map_local->speed; +} + +void hal_ll_i2c_master_set_timeout( handle_t *handle, uint16_t timeout ) { + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + if( hal_ll_i2c_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + hal_ll_i2c_hw_specifics_map_local->timeout = timeout; + } +} + +void hal_ll_i2c_master_set_slave_address( handle_t *handle, uint8_t addr ) { + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + if( hal_ll_i2c_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + hal_ll_i2c_hw_specifics_map_local->address = addr; + } +} + +hal_ll_err_t hal_ll_i2c_master_read( handle_t *handle, uint8_t *read_data_buf, size_t len_read_data ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + return hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_local, read_data_buf, len_read_data, HAL_LL_I2C_MASTER_END_MODE_STOP ); +} + +hal_ll_err_t hal_ll_i2c_master_write( handle_t *handle, uint8_t *write_data_buf, size_t len_write_data ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + return hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_local, write_data_buf, len_write_data, HAL_LL_I2C_MASTER_END_MODE_STOP ); +} + +hal_ll_err_t hal_ll_i2c_master_write_then_read( handle_t *handle, uint8_t *write_data_buf, size_t len_write_data, uint8_t *read_data_buf, size_t len_read_data ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + if( hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_local, write_data_buf, len_write_data, HAL_LL_I2C_MASTER_WRITE_THEN_READ ) != NULL ) { + return HAL_LL_I2C_MASTER_TIMEOUT_WRITE; + } + + /** + * @note Wait for drivers to set-up + * correctly. + **/ + #ifdef __TFT_RESISTIVE_TSC2003__ + Delay_22us(); + #endif + + if( hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_local, read_data_buf, len_read_data, HAL_LL_I2C_MASTER_WRITE_THEN_READ ) != NULL ) { + return HAL_LL_I2C_MASTER_TIMEOUT_READ; + } + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +void hal_ll_i2c_master_close( handle_t *handle ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + if( low_level_handle->hal_ll_i2c_master_handle != NULL ) { + low_level_handle->hal_ll_i2c_master_handle = NULL; + low_level_handle->hal_drv_i2c_master_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_i2c_hw_specifics_map_local->address = 0; + hal_ll_i2c_hw_specifics_map_local->timeout = HAL_LL_I2C_DEFAULT_PASS_COUNT; + hal_ll_i2c_hw_specifics_map_local->speed = HAL_LL_I2C_MASTER_SPEED_100K; + + hal_ll_i2c_master_set_clock(hal_ll_i2c_hw_specifics_map_local, true); + hal_ll_i2c_master_alternate_functions_set_state( hal_ll_i2c_hw_specifics_map_local, false ); + hal_ll_i2c_master_set_clock(hal_ll_i2c_hw_specifics_map_local, false); + + hal_ll_i2c_hw_specifics_map_local->pins.pin_scl.pin_name = HAL_LL_PIN_NC; + hal_ll_i2c_hw_specifics_map_local->pins.pin_sda.pin_name = HAL_LL_PIN_NC; + hal_ll_i2c_hw_specifics_map_local->pins.pin_scl.pin_af = 0; + hal_ll_i2c_hw_specifics_map_local->pins.pin_sda.pin_af = 0; + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static hal_ll_err_t hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *read_data_buf, size_t len_read_data, hal_ll_i2c_master_end_mode_t mode ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct(map->base); + uint16_t time_counter = map->timeout; + size_t transfer_counter = NULL; + uint8_t status = NULL; + + /** + * @note When R/W = 0, the input sample acquisition period starts + * on the falling edge of SCL once the C0 bit of the command + * byte has been latched, and ends when a Stop or + * repeated Start condition has been issued. + **/ + #ifdef __TFT_RESISTIVE_TSC2003__ + Delay_1ms(); + #endif + + hal_ll_i2c_master_configure_transfer ( map->base, + ( map->address << 1 & HAL_LL_I2C_CR2_SADD ) | + ( len_read_data << 16 & HAL_LL_I2C_CR2_NBYTES ) | + HAL_LL_I2C_CR2_RD_WRN | + HAL_LL_I2C_CR2_START + ); + + for ( transfer_counter; transfer_counter < len_read_data; transfer_counter++ ) { + while ( !( check_reg_bit( &( hal_ll_hw_reg->isr ), HAL_LL_I2C_RXNE_BIT ) ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_READ; + } + } + read_data_buf[ transfer_counter ] = hal_ll_hw_reg->rxdr; + } + + if ( ( mode == HAL_LL_I2C_MASTER_END_MODE_STOP ) || ( mode == HAL_LL_I2C_MASTER_WRITE_THEN_READ ) ) { + status = hal_ll_i2c_master_stop( map ); + } else { + status = hal_ll_i2c_master_start( map ); + } + + if( status != HAL_LL_I2C_MASTER_SUCCESS ) { + return status; + } + + hal_ll_i2c_master_reset_cr2( hal_ll_hw_reg ); + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static hal_ll_err_t hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *write_data_buf, size_t len_write_data, hal_ll_i2c_master_end_mode_t mode ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct(map->base); + uint16_t time_counter = map->timeout; + size_t transfer_counter = NULL; + uint8_t status = NULL; + + hal_ll_i2c_master_configure_transfer ( map->base, + ( map->address << 1 & HAL_LL_I2C_CR2_SADD ) | + ( len_write_data << 16 & HAL_LL_I2C_CR2_NBYTES ) | + !HAL_LL_I2C_CR2_RD_WRN | + HAL_LL_I2C_CR2_START + ); + + for ( transfer_counter; transfer_counter < len_write_data; transfer_counter++ ) + { + while ( !( check_reg_bit( &( hal_ll_hw_reg->isr ), HAL_LL_I2C_TXIS_BIT ) ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_WRITE; + } + } + hal_ll_hw_reg->txdr = write_data_buf[ transfer_counter ]; + } + + time_counter = map->timeout; + while ( !( check_reg_bit( &( hal_ll_hw_reg->isr ), HAL_LL_I2C_TXE_BIT ) ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_WRITE; + } + } + + if ( mode == HAL_LL_I2C_MASTER_END_MODE_STOP ) + { + hal_ll_i2c_master_stop( map ); + } + + hal_ll_i2c_master_reset_cr2( hal_ll_hw_reg ); + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static void hal_ll_i2c_master_configure_transfer( hal_ll_i2c_base_handle_t *hal_ll_hw_reg, uint32_t config ) { + uint32_t reg = 0; + + // Clear last set slave address + hal_ll_hw_reg->cr2 &= ~HAL_LL_I2C_CR2_SADD; + + reg = hal_ll_hw_reg->cr2; + reg &= ~( uint32_t )( + ( HAL_LL_I2C_CR2_SADD ) | + ( HAL_LL_I2C_CR2_NBYTES ) | + ( HAL_LL_I2C_CR2_RELOAD ) | + ( HAL_LL_I2C_CR2_AUTOEND ) | + ( HAL_LL_I2C_CR2_RD_WRN ) | + ( HAL_LL_I2C_CR2_START ) | + ( HAL_LL_I2C_CR2_STOP ) + ); + + reg |= config; + hal_ll_hw_reg->cr2 = reg; +} + +static void hal_ll_i2c_master_reset_cr2( hal_ll_i2c_base_handle_t *hal_ll_hw_reg ) { + hal_ll_hw_reg->cr2 &= ~( uint32_t ) + ( + HAL_LL_I2C_SADD_MASK | + HAL_LL_I2C_HEAD10R_MASK | + HAL_LL_I2C_NBYTES_MASK | + HAL_LL_I2C_RELOAD_MASK | + HAL_LL_I2C_RD_WRN_MASK + ); +} + +static hal_ll_err_t hal_ll_i2c_master_start( hal_ll_i2c_hw_specifics_map_t *map ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct(map->base); + uint16_t loop_index = HAL_LL_I2C_LOOP_INDEX; + + set_reg_bit( &(hal_ll_hw_reg->cr2), HAL_LL_I2C_CR2_START_BIT ); + + if ( check_reg_bit( &( hal_ll_hw_reg->isr ), HAL_LL_I2C_ARLO_BIT ) ) + return HAL_LL_I2C_MASTER_ARBITRATION_LOST; + + while ( loop_index-- ) + assembly(nop); + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static hal_ll_err_t hal_ll_i2c_master_stop( hal_ll_i2c_hw_specifics_map_t *map ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = ( hal_ll_i2c_base_handle_t* )map->base; + uint16_t time_counter = map->timeout; + uint32_t loop_index = HAL_LL_I2C_LOOP_INDEX; + + set_reg_bit( &(hal_ll_hw_reg->cr2), HAL_LL_I2C_CR2_STOP_BIT ); + + while ( !( hal_ll_hw_reg->isr & HAL_LL_I2C_ISR_STOPF_BIT ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_STOP; + } + } + + if ( map->timeout < HAL_LL_I2C_LOOP_INDEX ) { + while ( loop_index-- ) + assembly(nop); + } + + hal_ll_hw_reg->isr &= ~HAL_LL_I2C_ISR_STOPF_BIT; + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static hal_ll_pin_name_t hal_ll_i2c_master_check_pins( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_pin_id *index_list, hal_ll_i2c_master_handle_register_t *handle_map ) { + static const uint16_t scl_map_size = ( sizeof( hal_ll_i2c_scl_map ) / sizeof( hal_ll_i2c_pin_map_t ) ); + static const uint16_t sda_map_size = ( sizeof( hal_ll_i2c_sda_map ) / sizeof( hal_ll_i2c_pin_map_t ) ); + uint8_t hal_ll_module_id = 0; + uint8_t index_counter = 0; + uint16_t scl_index; + uint16_t sda_index; + + if ( (HAL_LL_PIN_NC == scl) || (HAL_LL_PIN_NC == sda) ) { + return HAL_LL_PIN_NC; + } + + for ( scl_index = 0; scl_index < scl_map_size; scl_index++ ) { + if ( hal_ll_i2c_scl_map[ scl_index ].pin == scl ) { + for ( sda_index = 0; sda_index < sda_map_size; sda_index++ ) { + if ( hal_ll_i2c_sda_map[ sda_index ].pin == sda ) { + if ( hal_ll_i2c_scl_map[ scl_index ].module_index == hal_ll_i2c_sda_map[ sda_index ].module_index ) { + // Get module number + hal_ll_module_id = hal_ll_i2c_scl_map[ scl_index ].module_index; + // Map pin names + index_list[hal_ll_module_id].pin_scl = scl_index; + index_list[hal_ll_module_id].pin_sda = sda_index; + + // Check if module is taken + if ( NULL == handle_map[ hal_ll_module_id ].hal_drv_i2c_master_handle ) { + return hal_ll_module_id; + } else if ( I2C_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static hal_ll_i2c_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof(hal_ll_i2c_master_handle_register_t)); + static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof(hal_ll_i2c_master_handle_register_t)); + + while( hal_ll_module_count-- ) { + if (hal_ll_i2c_get_base_from_hal_handle == hal_ll_i2c_hw_specifics_map[hal_ll_module_count].base) { + return &hal_ll_i2c_hw_specifics_map[hal_ll_module_count]; + } + } + + return &hal_ll_i2c_hw_specifics_map[hal_ll_module_error]; +} + +static void hal_ll_i2c_master_set_clock( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ) { + switch ( map->module_index ) + { + #if defined(I2C_MODULE_1) + case ( hal_ll_i2c_module_num(I2C_MODULE_1) ): + hal_ll_i2c1_set_clock( hal_ll_state ); + break; + #endif + + #if defined(I2C_MODULE_2) + case ( hal_ll_i2c_module_num(I2C_MODULE_2) ): + hal_ll_i2c2_set_clock( hal_ll_state ); + break; + #endif + + + default: + break; + } +} + +static void hal_ll_i2c_master_map_pins( uint8_t module_index, hal_ll_i2c_pin_id *index_list ) { + // Map new pins + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_scl.pin_name = hal_ll_i2c_scl_map[ index_list[module_index].pin_scl ].pin; + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_sda.pin_name = hal_ll_i2c_sda_map[ index_list[module_index].pin_sda ].pin; + // SCL and SDA could have different alternate function settings, hence save both AF values + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_scl.pin_af = hal_ll_i2c_scl_map[ index_list[module_index].pin_scl ].af; + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_sda.pin_af = hal_ll_i2c_sda_map[ index_list[module_index].pin_sda ].af; +} + +static void hal_ll_i2c_master_alternate_functions_set_state( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ) { + module_struct module; + + if( (map->pins.pin_scl.pin_name != HAL_LL_PIN_NC) && (map->pins.pin_sda.pin_name != HAL_LL_PIN_NC) ) { + module.pins[0] = VALUE( map->pins.pin_scl.pin_name, map->pins.pin_scl.pin_af ); + module.pins[1] = VALUE( map->pins.pin_sda.pin_name, map->pins.pin_sda.pin_af ); + module.pins[2] = GPIO_MODULE_STRUCT_END; + + module.configs[0] = HAL_LL_I2C_AF_CONFIG; + module.configs[1] = HAL_LL_I2C_AF_CONFIG; + module.configs[2] = GPIO_MODULE_STRUCT_END; + + hal_ll_gpio_module_struct_init( &module, hal_ll_state ); + } +} + +static uint32_t hal_ll_i2c_get_speed( hal_ll_i2c_hw_specifics_map_t *map ) { + if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_FAST ) { + if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_STANDARD ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_100K; + return HAL_LL_I2C_100K; + } else if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_FULL ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_400K; + return HAL_LL_I2C_400K; + } else if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_FAST ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_1M; + return HAL_LL_I2C_1M; + } else { + map->speed = HAL_LL_I2C_MASTER_SPEED_100K; + return HAL_LL_I2C_100K; + } + } else { + if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_100K ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_100K; + return HAL_LL_I2C_100K; + } else if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_400K ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_400K; + return HAL_LL_I2C_400K; + } else if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_1M ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_1M; + return HAL_LL_I2C_1M; + } else { + map->speed = HAL_LL_I2C_MASTER_SPEED_1M; + return HAL_LL_I2C_1M; + } + } +} +static inline void hal_ll_i2c1_set_clock( bool hal_ll_state ) { + if ( hal_ll_state ) { + set_reg_bit( _RCC_APBENR1, HAL_LL_I2C1EN_BIT ); + set_reg_bit( _RCC_CCIPR, HAL_LL_I2C12SEL1_BIT ); + } else { + clear_reg_bit( _RCC_APBENR1, HAL_LL_I2C1EN_BIT ); + clear_reg_bit( _RCC_CCIPR, HAL_LL_I2C12SEL1_BIT ); + } +} + + +static inline void hal_ll_i2c2_set_clock( bool hal_ll_state ) { + if ( hal_ll_state ) { + set_reg_bit( _RCC_APBENR1, HAL_LL_I2C2EN_BIT ); + set_reg_bit( _RCC_CCIPR, HAL_LL_I2C12SEL1_BIT ); + } else { + clear_reg_bit( _RCC_APBENR1, HAL_LL_I2C2EN_BIT ); + clear_reg_bit( _RCC_CCIPR, HAL_LL_I2C12SEL1_BIT ); + } +} + + + +static hal_ll_err_t hal_ll_i2c_hw_init( hal_ll_i2c_hw_specifics_map_t *map ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct(map->base); + uint16_t time_counter = map->timeout; + + clear_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_I2C_PE_BIT ); + while ( check_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_I2C_PE_BIT ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_INIT; + } + } + + hal_ll_hw_reg->cr1 &= HAL_LL_I2C_FILTERS_OFF; + + hal_ll_hw_reg->timingr = hal_ll_i2c_get_speed( map ); + + hal_ll_hw_reg->cr1 |= HAL_LL_I2C_CR1_RXTX_INT; + + set_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_I2C_PE_BIT ); + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static hal_ll_err_t hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_t *map ) { + hal_ll_i2c_master_set_clock( map, true ); + + return hal_ll_i2c_hw_init( map ); +} +// ------------------------------------------------------------------------- END + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_80/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_80/CMakeLists.cmake new file mode 100644 index 000000000..09d728435 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_80/CMakeLists.cmake @@ -0,0 +1,9 @@ +if(${MCU_NAME} MATCHES "^STM32G0B1CB$|^STM32G0B1KB$|^STM32G0B1MB$|^STM32G0B1RB$|^STM32G0B1VB$|^STM32G0B1CC$|^STM32G0B1KC$|^STM32G0B1MC$|^STM32G0B1RC$|^STM32G0B1VC$|^STM32G0B1CE$|^STM32G0B1KE$|^STM32G0B1ME$|^STM32G0B1NE$|^STM32G0B1RE$|^STM32G0B1VE$") + set(i2c_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_i2c_master.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_80") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_80") + list(APPEND hal_ll_def_list "STM32G0xx") + list(APPEND hal_ll_def_list "STM32G0Bxx") + list(APPEND hal_ll_def_list "STM32G0B1xx") + set(i2c_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/i2c/hal_ll_i2c_pin_map/implementations/doc_ds_80") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_80/hal_ll_i2c_master.c b/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_80/hal_ll_i2c_master.c new file mode 100644 index 000000000..011c7604a --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_80/hal_ll_i2c_master.c @@ -0,0 +1,951 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_i2c_master.c + * @brief I2C master HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_rcc.h" +#include "hal_ll_gpio.h" +#include "hal_ll_i2c_master.h" +#include "hal_ll_i2c_pin_map.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_i2c_master_handle_register_t hal_ll_module_state[I2C_MODULE_COUNT] = { (handle_t *)NULL, (handle_t *)NULL, false }; + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_i2c_get_module_state_address ((hal_ll_i2c_master_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_i2c_get_handle (hal_ll_i2c_master_handle_register_t *)hal_ll_i2c_get_module_state_address->hal_ll_i2c_master_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_i2c_get_base_struct(_handle) ((hal_ll_i2c_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_i2c_get_base_from_hal_handle ((hal_ll_i2c_hw_specifics_map_t *)((hal_ll_i2c_master_handle_register_t *)\ + (((hal_ll_i2c_master_handle_register_t *)(handle))->hal_ll_i2c_master_handle))->hal_ll_i2c_master_handle)->base + +/*!< @brief Default I2C bit-rate if no speed is set */ +#define HAL_LL_I2C_MASTER_SPEED_100K 100000UL +#define HAL_LL_I2C_MASTER_SPEED_400K 400000UL +#define HAL_LL_I2C_MASTER_SPEED_1M 1000000UL + +/*!< @brief Default pass count value upon reset */ +#define HAL_LL_I2C_DEFAULT_PASS_COUNT 0xFFFFU + +/*!< @brief Macro used for timeout */ +#define HAL_LL_I2C_LOOP_INDEX 10000U + +/*!< @brief Macros defining register bit location */ +#define HAL_LL_I2C1EN_BIT 21 +#define HAL_LL_I2C2EN_BIT 22 +#define HAL_LL_I2C3EN_BIT 23 + +#define HAL_LL_I2C12SEL0_BIT 14 +#define HAL_LL_I2C12SEL1_BIT 15 + +#define HAL_LL_I2C_100K 0x30420F13 +#define HAL_LL_I2C_400K 0x10320309 +#define HAL_LL_I2C_1M 0x00200204 + +#define HAL_LL_I2C_PE_BIT 0 +#define HAL_LL_I2C_CR2_STOP_BIT 14 +#define HAL_LL_I2C_CR2_START_BIT 13 +#define HAL_LL_I2C_ISR_STOPF_BIT 5 +#define HAL_LL_I2C_ISR_BUSY_BIT 15 +#define HAL_LL_I2C_ARLO_BIT 9 +#define HAL_LL_I2C_RXNE_BIT 2 +#define HAL_LL_I2C_TXIS_BIT 1 +#define HAL_LL_I2C_TXE_BIT 0 + +/*!< @brief Macros defining register bit masks */ +#define HAL_LL_I2C_CR1_RXTX_INT 0x6 +#define HAL_LL_I2C_CR2_STOP 0x4000UL +#define HAL_LL_I2C_CR2_START 0x2000U +#define HAL_LL_I2C_CR2_SADD 0x3FFU +#define HAL_LL_I2C_CR2_NBYTES 0xFF0000UL +#define HAL_LL_I2C_CR2_RD_WRN 0x400U +#define HAL_LL_I2C_CR2_RELOAD 0x1000000UL +#define HAL_LL_I2C_CR2_AUTOEND 0x2000000UL +#define HAL_LL_I2C_FILTERS_OFF 0xFFFFE0FFUL +#define HAL_LL_I2C_SADD_MASK 0x3FFUL +#define HAL_LL_I2C_HEAD10R_MASK 0x1000UL +#define HAL_LL_I2C_NBYTES_MASK 0xFF0000UL +#define HAL_LL_I2C_RELOAD_MASK 0x1000000UL +#define HAL_LL_I2C_RD_WRN_MASK 0x400UL + +/*!< @brief Macros used for module pin checking */ +#define HAL_LL_I2C_SCL_PIN 0 +#define HAL_LL_I2C_SDA_PIN 1 +#define HAL_LL_I2C_MODULE_PIN_COUNT 2 + +/*!< @brief Macro used for setting pin alternate functions */ +#define HAL_LL_I2C_AF_CONFIG (GPIO_CFG_MODE_ALT_FUNCTION | GPIO_CFG_SPEED_HIGH | GPIO_CFG_OTYPE_OD) + +// -------------------------------------------------------------- PRIVATE TYPES +/*!< @brief I2C register structure */ +typedef struct +{ + hal_ll_base_addr_t cr1; + hal_ll_base_addr_t cr2; + hal_ll_base_addr_t oar1; + hal_ll_base_addr_t oar2; + hal_ll_base_addr_t timingr; + hal_ll_base_addr_t timeoutr; + hal_ll_base_addr_t isr; + hal_ll_base_addr_t icr; + hal_ll_base_addr_t pecr; + hal_ll_base_addr_t rxdr; + hal_ll_base_addr_t txdr; +} hal_ll_i2c_base_handle_t; + +/*!< @brief I2C hw specific structure */ +typedef struct +{ + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + hal_ll_i2c_pins_t pins; + uint32_t speed; + uint8_t address; + uint16_t timeout; +} hal_ll_i2c_hw_specifics_map_t; + +/*!< @brief I2C hw specific module values */ +typedef struct +{ + uint16_t pin_scl; + uint16_t pin_sda; +} hal_ll_i2c_pin_id; + +/*!< @brief I2C hw specific error values */ +typedef enum +{ + HAL_LL_I2C_MASTER_SUCCESS = 0, + HAL_LL_I2C_MASTER_WRONG_PINS, + HAL_LL_I2C_MASTER_MODULE_ERROR, + + HAL_LL_I2C_MASTER_ERROR = (-1) +} hal_ll_i2c_master_err_t; + +/*!< @brief I2C end mode selection values */ +typedef enum +{ + HAL_LL_I2C_MASTER_END_MODE_RESTART = 0, + HAL_LL_I2C_MASTER_END_MODE_STOP, + HAL_LL_I2C_MASTER_WRITE_THEN_READ +} hal_ll_i2c_master_end_mode_t; + +/*!< @brief I2C timeout error values */ +typedef enum +{ + HAL_LL_I2C_MASTER_TIMEOUT_START = 1300, + HAL_LL_I2C_MASTER_TIMEOUT_STOP, + HAL_LL_I2C_MASTER_TIMEOUT_WRITE, + HAL_LL_I2C_MASTER_TIMEOUT_READ, + HAL_LL_I2C_MASTER_ARBITRATION_LOST, + HAL_LL_I2C_MASTER_TIMEOUT_INIT +} hal_ll_i2c_master_timeout_t; + +/** + * @brief Enum containing predefined module standard speed values. + * + * Enum values: + * HAL_LL_I2C_MASTER_SPEED_STANDARD -- Speed set at 100K + * HAL_LL_I2C_MASTER_SPEED_FULL -- Speed set at 400K + * HAL_LL_I2C_MASTER_SPEED_FAST -- Speed set at 1M + */ +typedef enum +{ + HAL_LL_I2C_MASTER_SPEED_STANDARD = 0, + HAL_LL_I2C_MASTER_SPEED_FULL, + HAL_LL_I2C_MASTER_SPEED_FAST +} hal_ll_i2c_master_speed_t; + +// ------------------------------------------------------------------ VARIABLES +/*!< @brief I2C hardware specific info */ +static hal_ll_i2c_hw_specifics_map_t hal_ll_i2c_hw_specifics_map[] = +{ + #ifdef I2C_MODULE_1 + {HAL_LL_I2C1_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_1), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, + #endif + #ifdef I2C_MODULE_2 + {HAL_LL_I2C2_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_2), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, + #endif + #ifdef I2C_MODULE_3 + {HAL_LL_I2C3_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_3), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, + #endif + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, 0, 0} +}; + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_i2c_master_handle_register_t *low_level_handle; +static volatile hal_ll_i2c_hw_specifics_map_t *hal_ll_i2c_hw_specifics_map_local; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Check if pins are adequate. + * + * Checks scl and sda pins the user has passed with pre-defined + * pins in scl and sda maps. Take into consideration that module + * index numbers have to be the same for both pins. + * + * @param[in] scl - SCL pre-defined pin name. + * @param[in] sda - SDA pre-defined pin name. + * @param[in] *index_list - Index list address + * @return hal_ll_pin_name_t Module index based on pins. + * + * Returns pre-defined module index from pin maps, if pins + * are adequate. + */ +static hal_ll_pin_name_t hal_ll_i2c_master_check_pins( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_pin_id *index_list, hal_ll_i2c_master_handle_register_t *handle_map ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_i2c_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_i2c_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_i2c_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Get adequate I2C bit-rate value. + * + * Returns one of pre-defined bit-rate values, + * or the closest bit-rate based on bit_rate + * value passed to the function. + * + * @param[in] bit_rate - I2C bit rate. + * @return uint32_t Adequate bit-rate value. + * + * Returns adequate value to be latter written into bare metal register address. + * Take into consideration that this returns a predefined value. + * + * HAL_LL_I2C_MASTER_SPEED_100K -- 100Kbit/s + * HAL_LL_I2C_MASTER_SPEED_400K -- 400Kbit/s + * HAL_LL_I2C_MASTER_SPEED_1M -- 1Mbit/s + * HAL_LL_I2C_MASTER_SPEED_3M2 -- 3.2Mbit/s + */ +static uint32_t hal_ll_i2c_get_speed( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Enable clock for I2C1 module on hardware level. + * + * Initializes I2C1 module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] hal_ll_state - True/False -- Init/De-init + * + * @return None + */ +static inline void hal_ll_i2c1_set_clock( bool hal_ll_state ); + +/** + * @brief Enable clock for I2C2 module on hardware level. + * + * Initializes I2C2 module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] hal_ll_state - True/False -- Init/De-init + * + * @return None + */ +static inline void hal_ll_i2c2_set_clock( bool hal_ll_state ); + +/** + * @brief Enable clock for I2C3 module on hardware level. + * + * Initializes I2C3 module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] hal_ll_state - True/False -- Init/De-init + * + * @return None + */ +static inline void hal_ll_i2c3_set_clock( bool hal_ll_state ); + +/** + * @brief Enable clock for I2C module on hardware level. + * + * Initializes I2C module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_stat - True(enable clock)/False(disable clock). + * + * @return None + */ +static void hal_ll_i2c_master_set_clock( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Initialize I2C module on hardware level. + * + * Initializes I2C module on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] map - Object specific context handler. + * @return hal_ll_err_t Module specific return values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_hw_init( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * I2C SCL and SDA pins. + * + * @param[in] module_index I2C HW module index -- 0,1,2... + * @param[in] *index_list Array with SCL and SDA map index values + * and module number + * + * @return None + */ +static void hal_ll_i2c_master_map_pins( uint8_t module_index, hal_ll_i2c_pin_id *index_list ); + +/** + * @brief Sets I2C pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if I2C is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_state - Init/De-init + * + * @return None + */ +static void hal_ll_i2c_master_alternate_functions_set_state( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Full I2C module initialization procedure. + * + * Initializes I2C module on hardware level, based on beforehand + * set configuration and module handler. Sets adequate pin alternate functions. + * Initializes module clock. + * + * @param[in] map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Configure I2C module for data transfer. + * + * @param[in] hal_ll_hw_reg - I2C module base address. + * @param[in] config - I2C config bits. + * @return void None. + */ +static void hal_ll_i2c_master_configure_transfer( hal_ll_i2c_base_handle_t *hal_ll_hw_reg, uint32_t config ); + +/** + * @brief Reset value of I2C CR2 register. + * + * @param[in] hal_ll_hw_reg - I2C module base address. + * @returnl none + */ +static void hal_ll_i2c_master_reset_cr2( hal_ll_i2c_base_handle_t *hal_ll_hw_reg ); + +/** + * @brief Generates start signal on I2C bus. + * + * Generates a start signal on the I2C bus. + * + * @param[in] map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_master_start( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Generates stop signal on I2C bus. + * + * Generates a stop signal on the I2C bus. + * + * @param[in] map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_master_stop( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Perform a read on the I2C bus. + * + * Initializes I2C module on hardware level, if not initialized beforehand + * and continues to perform a read operation on the bus. + * + * @param[in] map - Object specific context handler. + * @param[in] readDatabuf - Pointer to data buffer. + * @param[in] lenReadData - Number of data to be read. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *read_data_buf, size_t len_read_data, hal_ll_i2c_master_end_mode_t mode ); + +/** + * @brief Perform a write on the I2C bus. + * + * Initializes I2C module on hardware level, if not initialized beforehand + * and continues to perform a write operation on the bus. + * + * @param[in] map - Object specific context handler. + * @param[in] writeDatabuf - Pointer to data buffer. + * @param[in] lenWriteData - Number of data to be written. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *write_data_buf, size_t len_write_data, hal_ll_i2c_master_end_mode_t mode ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_i2c_master_register_handle( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_master_handle_register_t *handle_map, uint8_t *hal_module_id ) { + + hal_ll_i2c_pin_id index_list[I2C_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + uint16_t pin_check_result; + + // Check if pins are valid + if ( (pin_check_result = hal_ll_i2c_master_check_pins( scl, sda, &index_list, handle_map )) == HAL_LL_PIN_NC ) { + return HAL_LL_I2C_MASTER_WRONG_PINS; + }; + + if ( (hal_ll_i2c_hw_specifics_map[pin_check_result].pins.pin_scl.pin_name != scl) || + (hal_ll_i2c_hw_specifics_map[pin_check_result].pins.pin_sda.pin_name != sda) ) + { + hal_ll_i2c_master_alternate_functions_set_state( &hal_ll_i2c_hw_specifics_map[ pin_check_result ], false ); + + hal_ll_i2c_master_map_pins( pin_check_result, &index_list ); + + hal_ll_i2c_master_alternate_functions_set_state( &hal_ll_i2c_hw_specifics_map[ pin_check_result ], true ); + + handle_map[pin_check_result].init_ll_state = false; + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[pin_check_result].hal_ll_i2c_master_handle = (handle_t *)&hal_ll_i2c_hw_specifics_map[pin_check_result].base; + + handle_map[pin_check_result].hal_ll_i2c_master_handle = (handle_t *)&hal_ll_module_state[pin_check_result].hal_ll_i2c_master_handle; + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_i2c( handle_t *handle ) { + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + hal_ll_i2c_master_handle_register_t *hal_handle = (hal_ll_i2c_master_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_i2c_hw_specifics_map_local->module_index; + + hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_local ); + + hal_ll_module_state[pin_check_result].hal_ll_i2c_master_handle = (handle_t *)&hal_ll_i2c_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_i2c_master_set_speed( handle_t *handle, uint32_t speed ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + low_level_handle->init_ll_state = false; + + hal_ll_i2c_hw_specifics_map_local->speed = speed; + + if ( hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_local ) != HAL_LL_I2C_MASTER_SUCCESS ) { + return HAL_LL_I2C_MASTER_TIMEOUT_INIT; + } + + low_level_handle->init_ll_state = true; + + return hal_ll_i2c_hw_specifics_map_local->speed; +} + +void hal_ll_i2c_master_set_timeout( handle_t *handle, uint16_t timeout ) { + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + if( hal_ll_i2c_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + hal_ll_i2c_hw_specifics_map_local->timeout = timeout; + } +} + +void hal_ll_i2c_master_set_slave_address( handle_t *handle, uint8_t addr ) { + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + if( hal_ll_i2c_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + hal_ll_i2c_hw_specifics_map_local->address = addr; + } +} + +hal_ll_err_t hal_ll_i2c_master_read( handle_t *handle, uint8_t *read_data_buf, size_t len_read_data ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + return hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_local, read_data_buf, len_read_data, HAL_LL_I2C_MASTER_END_MODE_STOP ); +} + +hal_ll_err_t hal_ll_i2c_master_write( handle_t *handle, uint8_t *write_data_buf, size_t len_write_data ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + return hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_local, write_data_buf, len_write_data, HAL_LL_I2C_MASTER_END_MODE_STOP ); +} + +hal_ll_err_t hal_ll_i2c_master_write_then_read( handle_t *handle, uint8_t *write_data_buf, size_t len_write_data, uint8_t *read_data_buf, size_t len_read_data ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + if( hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_local, write_data_buf, len_write_data, HAL_LL_I2C_MASTER_WRITE_THEN_READ ) != NULL ) { + return HAL_LL_I2C_MASTER_TIMEOUT_WRITE; + } + + /** + * @note Wait for drivers to set-up + * correctly. + **/ + #ifdef __TFT_RESISTIVE_TSC2003__ + Delay_22us(); + #endif + + if( hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_local, read_data_buf, len_read_data, HAL_LL_I2C_MASTER_WRITE_THEN_READ ) != NULL ) { + return HAL_LL_I2C_MASTER_TIMEOUT_READ; + } + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +void hal_ll_i2c_master_close( handle_t *handle ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + if( low_level_handle->hal_ll_i2c_master_handle != NULL ) { + low_level_handle->hal_ll_i2c_master_handle = NULL; + low_level_handle->hal_drv_i2c_master_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_i2c_hw_specifics_map_local->address = 0; + hal_ll_i2c_hw_specifics_map_local->timeout = HAL_LL_I2C_DEFAULT_PASS_COUNT; + hal_ll_i2c_hw_specifics_map_local->speed = HAL_LL_I2C_MASTER_SPEED_100K; + + hal_ll_i2c_master_set_clock(hal_ll_i2c_hw_specifics_map_local, true); + hal_ll_i2c_master_alternate_functions_set_state( hal_ll_i2c_hw_specifics_map_local, false ); + hal_ll_i2c_master_set_clock(hal_ll_i2c_hw_specifics_map_local, false); + + hal_ll_i2c_hw_specifics_map_local->pins.pin_scl.pin_name = HAL_LL_PIN_NC; + hal_ll_i2c_hw_specifics_map_local->pins.pin_sda.pin_name = HAL_LL_PIN_NC; + hal_ll_i2c_hw_specifics_map_local->pins.pin_scl.pin_af = 0; + hal_ll_i2c_hw_specifics_map_local->pins.pin_sda.pin_af = 0; + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static hal_ll_err_t hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *read_data_buf, size_t len_read_data, hal_ll_i2c_master_end_mode_t mode ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct(map->base); + uint16_t time_counter = map->timeout; + size_t transfer_counter = NULL; + uint8_t status = NULL; + + /** + * @note When R/W = 0, the input sample acquisition period starts + * on the falling edge of SCL once the C0 bit of the command + * byte has been latched, and ends when a Stop or + * repeated Start condition has been issued. + **/ + #ifdef __TFT_RESISTIVE_TSC2003__ + Delay_1ms(); + #endif + + hal_ll_i2c_master_configure_transfer ( map->base, + ( map->address << 1 & HAL_LL_I2C_CR2_SADD ) | + ( len_read_data << 16 & HAL_LL_I2C_CR2_NBYTES ) | + HAL_LL_I2C_CR2_RD_WRN | + HAL_LL_I2C_CR2_START + ); + + for ( transfer_counter; transfer_counter < len_read_data; transfer_counter++ ) { + while ( !( check_reg_bit( &( hal_ll_hw_reg->isr ), HAL_LL_I2C_RXNE_BIT ) ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_READ; + } + } + read_data_buf[ transfer_counter ] = hal_ll_hw_reg->rxdr; + } + + if ( ( mode == HAL_LL_I2C_MASTER_END_MODE_STOP ) || ( mode == HAL_LL_I2C_MASTER_WRITE_THEN_READ ) ) { + status = hal_ll_i2c_master_stop( map ); + } else { + status = hal_ll_i2c_master_start( map ); + } + + if( status != HAL_LL_I2C_MASTER_SUCCESS ) { + return status; + } + + hal_ll_i2c_master_reset_cr2( hal_ll_hw_reg ); + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static hal_ll_err_t hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *write_data_buf, size_t len_write_data, hal_ll_i2c_master_end_mode_t mode ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct(map->base); + uint16_t time_counter = map->timeout; + size_t transfer_counter = NULL; + uint8_t status = NULL; + + hal_ll_i2c_master_configure_transfer ( map->base, + ( map->address << 1 & HAL_LL_I2C_CR2_SADD ) | + ( len_write_data << 16 & HAL_LL_I2C_CR2_NBYTES ) | + !HAL_LL_I2C_CR2_RD_WRN | + HAL_LL_I2C_CR2_START + ); + + for ( transfer_counter; transfer_counter < len_write_data; transfer_counter++ ) + { + while ( !( check_reg_bit( &( hal_ll_hw_reg->isr ), HAL_LL_I2C_TXIS_BIT ) ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_WRITE; + } + } + hal_ll_hw_reg->txdr = write_data_buf[ transfer_counter ]; + } + + time_counter = map->timeout; + while ( !( check_reg_bit( &( hal_ll_hw_reg->isr ), HAL_LL_I2C_TXE_BIT ) ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_WRITE; + } + } + + if ( mode == HAL_LL_I2C_MASTER_END_MODE_STOP ) + { + hal_ll_i2c_master_stop( map ); + } + + hal_ll_i2c_master_reset_cr2( hal_ll_hw_reg ); + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static void hal_ll_i2c_master_configure_transfer( hal_ll_i2c_base_handle_t *hal_ll_hw_reg, uint32_t config ) { + uint32_t reg = 0; + + // Clear last set slave address + hal_ll_hw_reg->cr2 &= ~HAL_LL_I2C_CR2_SADD; + + reg = hal_ll_hw_reg->cr2; + reg &= ~( uint32_t )( + ( HAL_LL_I2C_CR2_SADD ) | + ( HAL_LL_I2C_CR2_NBYTES ) | + ( HAL_LL_I2C_CR2_RELOAD ) | + ( HAL_LL_I2C_CR2_AUTOEND ) | + ( HAL_LL_I2C_CR2_RD_WRN ) | + ( HAL_LL_I2C_CR2_START ) | + ( HAL_LL_I2C_CR2_STOP ) + ); + + reg |= config; + hal_ll_hw_reg->cr2 = reg; +} + +static void hal_ll_i2c_master_reset_cr2( hal_ll_i2c_base_handle_t *hal_ll_hw_reg ) { + hal_ll_hw_reg->cr2 &= ~( uint32_t ) + ( + HAL_LL_I2C_SADD_MASK | + HAL_LL_I2C_HEAD10R_MASK | + HAL_LL_I2C_NBYTES_MASK | + HAL_LL_I2C_RELOAD_MASK | + HAL_LL_I2C_RD_WRN_MASK + ); +} + +static hal_ll_err_t hal_ll_i2c_master_start( hal_ll_i2c_hw_specifics_map_t *map ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct(map->base); + uint16_t loop_index = HAL_LL_I2C_LOOP_INDEX; + + set_reg_bit( &(hal_ll_hw_reg->cr2), HAL_LL_I2C_CR2_START_BIT ); + + if ( check_reg_bit( &( hal_ll_hw_reg->isr ), HAL_LL_I2C_ARLO_BIT ) ) + return HAL_LL_I2C_MASTER_ARBITRATION_LOST; + + while ( loop_index-- ) + assembly(nop); + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static hal_ll_err_t hal_ll_i2c_master_stop( hal_ll_i2c_hw_specifics_map_t *map ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = ( hal_ll_i2c_base_handle_t* )map->base; + uint16_t time_counter = map->timeout; + uint32_t loop_index = HAL_LL_I2C_LOOP_INDEX; + + set_reg_bit( &(hal_ll_hw_reg->cr2), HAL_LL_I2C_CR2_STOP_BIT ); + + while ( !( hal_ll_hw_reg->isr & HAL_LL_I2C_ISR_STOPF_BIT ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_STOP; + } + } + + if ( map->timeout < HAL_LL_I2C_LOOP_INDEX ) { + while ( loop_index-- ) + assembly(nop); + } + + hal_ll_hw_reg->isr &= ~HAL_LL_I2C_ISR_STOPF_BIT; + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static hal_ll_pin_name_t hal_ll_i2c_master_check_pins( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_pin_id *index_list, hal_ll_i2c_master_handle_register_t *handle_map ) { + static const uint16_t scl_map_size = ( sizeof( hal_ll_i2c_scl_map ) / sizeof( hal_ll_i2c_pin_map_t ) ); + static const uint16_t sda_map_size = ( sizeof( hal_ll_i2c_sda_map ) / sizeof( hal_ll_i2c_pin_map_t ) ); + uint8_t hal_ll_module_id = 0; + uint8_t index_counter = 0; + uint16_t scl_index; + uint16_t sda_index; + + if ( (HAL_LL_PIN_NC == scl) || (HAL_LL_PIN_NC == sda) ) { + return HAL_LL_PIN_NC; + } + + for ( scl_index = 0; scl_index < scl_map_size; scl_index++ ) { + if ( hal_ll_i2c_scl_map[ scl_index ].pin == scl ) { + for ( sda_index = 0; sda_index < sda_map_size; sda_index++ ) { + if ( hal_ll_i2c_sda_map[ sda_index ].pin == sda ) { + if ( hal_ll_i2c_scl_map[ scl_index ].module_index == hal_ll_i2c_sda_map[ sda_index ].module_index ) { + // Get module number + hal_ll_module_id = hal_ll_i2c_scl_map[ scl_index ].module_index; + // Map pin names + index_list[hal_ll_module_id].pin_scl = scl_index; + index_list[hal_ll_module_id].pin_sda = sda_index; + + // Check if module is taken + if ( NULL == handle_map[ hal_ll_module_id ].hal_drv_i2c_master_handle ) { + return hal_ll_module_id; + } else if ( I2C_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static hal_ll_i2c_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof(hal_ll_i2c_master_handle_register_t)); + static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof(hal_ll_i2c_master_handle_register_t)); + + while( hal_ll_module_count-- ) { + if (hal_ll_i2c_get_base_from_hal_handle == hal_ll_i2c_hw_specifics_map[hal_ll_module_count].base) { + return &hal_ll_i2c_hw_specifics_map[hal_ll_module_count]; + } + } + + return &hal_ll_i2c_hw_specifics_map[hal_ll_module_error]; +} + +static void hal_ll_i2c_master_set_clock( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ) { + switch ( map->module_index ) + { + #if defined(I2C_MODULE_1) + case ( hal_ll_i2c_module_num(I2C_MODULE_1) ): + hal_ll_i2c1_set_clock( hal_ll_state ); + break; + #endif + + #if defined(I2C_MODULE_2) + case ( hal_ll_i2c_module_num(I2C_MODULE_2) ): + hal_ll_i2c2_set_clock( hal_ll_state ); + break; + #endif + + #if defined(I2C_MODULE_3) + case ( hal_ll_i2c_module_num(I2C_MODULE_3) ): + hal_ll_i2c3_set_clock( hal_ll_state ); + break; + #endif + + + default: + break; + } +} + +static void hal_ll_i2c_master_map_pins( uint8_t module_index, hal_ll_i2c_pin_id *index_list ) { + // Map new pins + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_scl.pin_name = hal_ll_i2c_scl_map[ index_list[module_index].pin_scl ].pin; + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_sda.pin_name = hal_ll_i2c_sda_map[ index_list[module_index].pin_sda ].pin; + // SCL and SDA could have different alternate function settings, hence save both AF values + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_scl.pin_af = hal_ll_i2c_scl_map[ index_list[module_index].pin_scl ].af; + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_sda.pin_af = hal_ll_i2c_sda_map[ index_list[module_index].pin_sda ].af; +} + +static void hal_ll_i2c_master_alternate_functions_set_state( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ) { + module_struct module; + + if( (map->pins.pin_scl.pin_name != HAL_LL_PIN_NC) && (map->pins.pin_sda.pin_name != HAL_LL_PIN_NC) ) { + module.pins[0] = VALUE( map->pins.pin_scl.pin_name, map->pins.pin_scl.pin_af ); + module.pins[1] = VALUE( map->pins.pin_sda.pin_name, map->pins.pin_sda.pin_af ); + module.pins[2] = GPIO_MODULE_STRUCT_END; + + module.configs[0] = HAL_LL_I2C_AF_CONFIG; + module.configs[1] = HAL_LL_I2C_AF_CONFIG; + module.configs[2] = GPIO_MODULE_STRUCT_END; + + hal_ll_gpio_module_struct_init( &module, hal_ll_state ); + } +} + +static uint32_t hal_ll_i2c_get_speed( hal_ll_i2c_hw_specifics_map_t *map ) { + if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_FAST ) { + if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_STANDARD ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_100K; + return HAL_LL_I2C_100K; + } else if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_FULL ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_400K; + return HAL_LL_I2C_400K; + } else if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_FAST ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_1M; + return HAL_LL_I2C_1M; + } else { + map->speed = HAL_LL_I2C_MASTER_SPEED_100K; + return HAL_LL_I2C_100K; + } + } else { + if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_100K ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_100K; + return HAL_LL_I2C_100K; + } else if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_400K ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_400K; + return HAL_LL_I2C_400K; + } else if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_1M ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_1M; + return HAL_LL_I2C_1M; + } else { + map->speed = HAL_LL_I2C_MASTER_SPEED_1M; + return HAL_LL_I2C_1M; + } + } +} + +static inline void hal_ll_i2c1_set_clock( bool hal_ll_state ) { + if ( hal_ll_state ) { + set_reg_bit( _RCC_APBENR1, HAL_LL_I2C1EN_BIT ); + set_reg_bit( _RCC_CCIPR, HAL_LL_I2C12SEL1_BIT ); + } else { + clear_reg_bit( _RCC_APBENR1, HAL_LL_I2C1EN_BIT ); + clear_reg_bit( _RCC_CCIPR, HAL_LL_I2C12SEL1_BIT ); + } +} + +static inline void hal_ll_i2c2_set_clock( bool hal_ll_state ) { + if ( hal_ll_state ) { + set_reg_bit( _RCC_APBENR1, HAL_LL_I2C2EN_BIT ); + set_reg_bit( _RCC_CCIPR, HAL_LL_I2C12SEL1_BIT ); + } else { + clear_reg_bit( _RCC_APBENR1, HAL_LL_I2C2EN_BIT ); + clear_reg_bit( _RCC_CCIPR, HAL_LL_I2C12SEL1_BIT ); + } +} + +static inline void hal_ll_i2c3_set_clock( bool hal_ll_state ) { + if ( hal_ll_state ) { + set_reg_bit( _RCC_APBENR1, HAL_LL_I2C3EN_BIT ); + } else { + clear_reg_bit( _RCC_APBENR1, HAL_LL_I2C3EN_BIT ); + } +} + +static hal_ll_err_t hal_ll_i2c_hw_init( hal_ll_i2c_hw_specifics_map_t *map ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct(map->base); + uint16_t time_counter = map->timeout; + + clear_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_I2C_PE_BIT ); + while ( check_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_I2C_PE_BIT ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_INIT; + } + } + + hal_ll_hw_reg->cr1 &= HAL_LL_I2C_FILTERS_OFF; + + hal_ll_hw_reg->timingr = hal_ll_i2c_get_speed( map ); + + hal_ll_hw_reg->cr1 |= HAL_LL_I2C_CR1_RXTX_INT; + + set_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_I2C_PE_BIT ); + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static hal_ll_err_t hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_t *map ) { + hal_ll_i2c_master_set_clock( map, true ); + + return hal_ll_i2c_hw_init( map ); +} +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_81/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_81/CMakeLists.cmake new file mode 100644 index 000000000..9ee1f2a8e --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_81/CMakeLists.cmake @@ -0,0 +1,9 @@ +if(${MCU_NAME} MATCHES "^STM32G0C1CC$|^STM32G0C1KC$|^STM32G0C1MC$|^STM32G0C1RC$|^STM32G0C1VC$|^STM32G0C1CE$|^STM32G0C1KE$|^STM32G0C1ME$|^STM32G0C1NE$|^STM32G0C1RE$|^STM32G0C1VE$") + set(i2c_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_i2c_master.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_81") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_81") + list(APPEND hal_ll_def_list "STM32G0xx") + list(APPEND hal_ll_def_list "STM32G0Cxx") + list(APPEND hal_ll_def_list "STM32G0C1xx") + set(i2c_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/i2c/hal_ll_i2c_pin_map/implementations/doc_ds_81") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_81/hal_ll_i2c_master.c b/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_81/hal_ll_i2c_master.c new file mode 100644 index 000000000..57da3c869 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_81/hal_ll_i2c_master.c @@ -0,0 +1,967 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_i2c_master.c + * @brief I2C master HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_rcc.h" +#include "hal_ll_gpio.h" +#include "hal_ll_i2c_master.h" +#include "hal_ll_i2c_pin_map.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_i2c_master_handle_register_t hal_ll_module_state[I2C_MODULE_COUNT] = { (handle_t *)NULL, (handle_t *)NULL, false }; + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_i2c_get_module_state_address ((hal_ll_i2c_master_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_i2c_get_handle (hal_ll_i2c_master_handle_register_t *)hal_ll_i2c_get_module_state_address->hal_ll_i2c_master_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_i2c_get_base_struct(_handle) ((hal_ll_i2c_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_i2c_get_base_from_hal_handle ((hal_ll_i2c_hw_specifics_map_t *)((hal_ll_i2c_master_handle_register_t *)\ + (((hal_ll_i2c_master_handle_register_t *)(handle))->hal_ll_i2c_master_handle))->hal_ll_i2c_master_handle)->base + +/*!< @brief Default I2C bit-rate if no speed is set */ +#define HAL_LL_I2C_MASTER_SPEED_100K 100000UL +#define HAL_LL_I2C_MASTER_SPEED_400K 400000UL +#define HAL_LL_I2C_MASTER_SPEED_1M 1000000UL + +/*!< @brief Default pass count value upon reset */ +#define HAL_LL_I2C_DEFAULT_PASS_COUNT 0xFFFFU + +/*!< @brief Macro used for timeout */ +#define HAL_LL_I2C_LOOP_INDEX 10000U + +/*!< @brief Macros defining register bit location */ +#define HAL_LL_I2C1EN_BIT 21 + +#define HAL_LL_I2C2EN_BIT 22 + +#define HAL_LL_I2C3EN_BIT 23 + +#define HAL_LL_I2C12SEL0_BIT 14 + +#define HAL_LL_I2C12SEL1_BIT 15 + + + + +#define HAL_LL_I2C_100K 0x30420F13 //?????????????????? +#define HAL_LL_I2C_400K 0x10320309 //?????????????????? +#define HAL_LL_I2C_1M 0x00200204 //?????????????????? + +#define HAL_LL_I2C_PE_BIT 0 +#define HAL_LL_I2C_CR2_STOP_BIT 14 +#define HAL_LL_I2C_CR2_START_BIT 13 +#define HAL_LL_I2C_ISR_STOPF_BIT 5 +#define HAL_LL_I2C_ISR_BUSY_BIT 15 +#define HAL_LL_I2C_ARLO_BIT 9 +#define HAL_LL_I2C_RXNE_BIT 2 +#define HAL_LL_I2C_TXIS_BIT 1 +#define HAL_LL_I2C_TXE_BIT 0 + +/*!< @brief Macros defining register bit masks */ +#define HAL_LL_I2C_CR1_RXTX_INT 0x6 +#define HAL_LL_I2C_CR2_STOP 0x4000UL +#define HAL_LL_I2C_CR2_START 0x2000U +#define HAL_LL_I2C_CR2_SADD 0x3FFU +#define HAL_LL_I2C_CR2_NBYTES 0xFF0000UL +#define HAL_LL_I2C_CR2_RD_WRN 0x400U +#define HAL_LL_I2C_CR2_RELOAD 0x1000000UL +#define HAL_LL_I2C_CR2_AUTOEND 0x2000000UL +#define HAL_LL_I2C_FILTERS_OFF 0xFFFFE0FFUL +#define HAL_LL_I2C_SADD_MASK 0x3FFUL +#define HAL_LL_I2C_HEAD10R_MASK 0x1000UL +#define HAL_LL_I2C_NBYTES_MASK 0xFF0000UL +#define HAL_LL_I2C_RELOAD_MASK 0x1000000UL +#define HAL_LL_I2C_RD_WRN_MASK 0x400UL + +/*!< @brief Macros used for module pin checking */ +#define HAL_LL_I2C_SCL_PIN 0 +#define HAL_LL_I2C_SDA_PIN 1 +#define HAL_LL_I2C_MODULE_PIN_COUNT 2 + +/*!< @brief Macro used for setting pin alternate functions */ +#define HAL_LL_I2C_AF_CONFIG (GPIO_CFG_MODE_ALT_FUNCTION | GPIO_CFG_SPEED_HIGH | GPIO_CFG_OTYPE_OD) + +// -------------------------------------------------------------- PRIVATE TYPES +/*!< @brief I2C register structure */ +typedef struct +{ + hal_ll_base_addr_t cr1; + hal_ll_base_addr_t cr2; + hal_ll_base_addr_t oar1; + hal_ll_base_addr_t oar2; + hal_ll_base_addr_t timingr; + hal_ll_base_addr_t timeoutr; + hal_ll_base_addr_t isr; + hal_ll_base_addr_t icr; + hal_ll_base_addr_t pecr; + hal_ll_base_addr_t rxdr; + hal_ll_base_addr_t txdr; + +} hal_ll_i2c_base_handle_t; + +/*!< @brief I2C hw specific structure */ +typedef struct +{ + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + hal_ll_i2c_pins_t pins; + uint32_t speed; + uint8_t address; + uint16_t timeout; +} hal_ll_i2c_hw_specifics_map_t; + +/*!< @brief I2C hw specific module values */ +typedef struct +{ + uint16_t pin_scl; + uint16_t pin_sda; +} hal_ll_i2c_pin_id; + +/*!< @brief I2C hw specific error values */ +typedef enum +{ + HAL_LL_I2C_MASTER_SUCCESS = 0, + HAL_LL_I2C_MASTER_WRONG_PINS, + HAL_LL_I2C_MASTER_MODULE_ERROR, + + HAL_LL_I2C_MASTER_ERROR = (-1) +} hal_ll_i2c_master_err_t; + +/*!< @brief I2C end mode selection values */ +typedef enum +{ + HAL_LL_I2C_MASTER_END_MODE_RESTART = 0, + HAL_LL_I2C_MASTER_END_MODE_STOP, + HAL_LL_I2C_MASTER_WRITE_THEN_READ +} hal_ll_i2c_master_end_mode_t; + +/*!< @brief I2C timeout error values */ +typedef enum +{ + HAL_LL_I2C_MASTER_TIMEOUT_START = 1300, + HAL_LL_I2C_MASTER_TIMEOUT_STOP, + HAL_LL_I2C_MASTER_TIMEOUT_WRITE, + HAL_LL_I2C_MASTER_TIMEOUT_READ, + HAL_LL_I2C_MASTER_ARBITRATION_LOST, + HAL_LL_I2C_MASTER_TIMEOUT_INIT +} hal_ll_i2c_master_timeout_t; + +/** + * @brief Enum containing predefined module standard speed values. + * + * Enum values: + * HAL_LL_I2C_MASTER_SPEED_STANDARD -- Speed set at 100K + * HAL_LL_I2C_MASTER_SPEED_FULL -- Speed set at 400K + * HAL_LL_I2C_MASTER_SPEED_FAST -- Speed set at 1M + */ +typedef enum +{ + HAL_LL_I2C_MASTER_SPEED_STANDARD = 0, + HAL_LL_I2C_MASTER_SPEED_FULL, + HAL_LL_I2C_MASTER_SPEED_FAST +} hal_ll_i2c_master_speed_t; + +// ------------------------------------------------------------------ VARIABLES +/*!< @brief I2C hardware specific info */ +static hal_ll_i2c_hw_specifics_map_t hal_ll_i2c_hw_specifics_map[] = +{ + #ifdef I2C_MODULE_1 + {HAL_LL_I2C1_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_1), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, + #endif + + #ifdef I2C_MODULE_2 + {HAL_LL_I2C2_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_2), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, + #endif + + #ifdef I2C_MODULE_3 + {HAL_LL_I2C3_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_3), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, + #endif + + + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, 0, 0} +}; + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_i2c_master_handle_register_t *low_level_handle; +static volatile hal_ll_i2c_hw_specifics_map_t *hal_ll_i2c_hw_specifics_map_local; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Check if pins are adequate. + * + * Checks scl and sda pins the user has passed with pre-defined + * pins in scl and sda maps. Take into consideration that module + * index numbers have to be the same for both pins. + * + * @param[in] scl - SCL pre-defined pin name. + * @param[in] sda - SDA pre-defined pin name. + * @param[in] *index_list - Index list address + * @return hal_ll_pin_name_t Module index based on pins. + * + * Returns pre-defined module index from pin maps, if pins + * are adequate. + */ +static hal_ll_pin_name_t hal_ll_i2c_master_check_pins( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_pin_id *index_list, hal_ll_i2c_master_handle_register_t *handle_map ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_i2c_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_i2c_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_i2c_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Get adequate I2C bit-rate value. + * + * Returns one of pre-defined bit-rate values, + * or the closest bit-rate based on bit_rate + * value passed to the function. + * + * @param[in] bit_rate - I2C bit rate. + * @return uint32_t Adequate bit-rate value. + * + * Returns adequate value to be latter written into bare metal register address. + * Take into consideration that this returns a predefined value. + * + * HAL_LL_I2C_MASTER_SPEED_100K -- 100Kbit/s + * HAL_LL_I2C_MASTER_SPEED_400K -- 400Kbit/s + * HAL_LL_I2C_MASTER_SPEED_1M -- 1Mbit/s + * HAL_LL_I2C_MASTER_SPEED_3M2 -- 3.2Mbit/s + */ +static uint32_t hal_ll_i2c_get_speed( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Enable clock for I2C1 module on hardware level. + * + * Initializes I2C1 module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] hal_ll_state - True/False -- Init/De-init + * + * @return None + */ +static inline void hal_ll_i2c1_set_clock( bool hal_ll_state ); + +/** + * @brief Enable clock for I2C2 module on hardware level. + * + * Initializes I2C2 module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] hal_ll_state - True/False -- Init/De-init + * + * @return None + */ +static inline void hal_ll_i2c2_set_clock( bool hal_ll_state ); + +/** + * @brief Enable clock for I2C3 module on hardware level. + * + * Initializes I2C3 module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] hal_ll_state - True/False -- Init/De-init + * + * @return None + */ +static inline void hal_ll_i2c3_set_clock( bool hal_ll_state ); + +/** + * @brief Enable clock for I2C module on hardware level. + * + * Initializes I2C module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_stat - True(enable clock)/False(disable clock). + * + * @return None + */ +static void hal_ll_i2c_master_set_clock( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Initialize I2C module on hardware level. + * + * Initializes I2C module on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] map - Object specific context handler. + * @return hal_ll_err_t Module specific return values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_hw_init( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * I2C SCL and SDA pins. + * + * @param[in] module_index I2C HW module index -- 0,1,2... + * @param[in] *index_list Array with SCL and SDA map index values + * and module number + * + * @return None + */ +static void hal_ll_i2c_master_map_pins( uint8_t module_index, hal_ll_i2c_pin_id *index_list ); + +/** + * @brief Sets I2C pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if I2C is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_state - Init/De-init + * + * @return None + */ +static void hal_ll_i2c_master_alternate_functions_set_state( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Full I2C module initialization procedure. + * + * Initializes I2C module on hardware level, based on beforehand + * set configuration and module handler. Sets adequate pin alternate functions. + * Initializes module clock. + * + * @param[in] map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Configure I2C module for data transfer. + * + * @param[in] hal_ll_hw_reg - I2C module base address. + * @param[in] config - I2C config bits. + * @return void None. + */ +static void hal_ll_i2c_master_configure_transfer( hal_ll_i2c_base_handle_t *hal_ll_hw_reg, uint32_t config ); + +/** + * @brief Reset value of I2C CR2 register. + * + * @param[in] hal_ll_hw_reg - I2C module base address. + * @returnl none + */ +static void hal_ll_i2c_master_reset_cr2( hal_ll_i2c_base_handle_t *hal_ll_hw_reg ); + +/** + * @brief Generates start signal on I2C bus. + * + * Generates a start signal on the I2C bus. + * + * @param[in] map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_master_start( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Generates stop signal on I2C bus. + * + * Generates a stop signal on the I2C bus. + * + * @param[in] map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_master_stop( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Perform a read on the I2C bus. + * + * Initializes I2C module on hardware level, if not initialized beforehand + * and continues to perform a read operation on the bus. + * + * @param[in] map - Object specific context handler. + * @param[in] readDatabuf - Pointer to data buffer. + * @param[in] lenReadData - Number of data to be read. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *read_data_buf, size_t len_read_data, hal_ll_i2c_master_end_mode_t mode ); + +/** + * @brief Perform a write on the I2C bus. + * + * Initializes I2C module on hardware level, if not initialized beforehand + * and continues to perform a write operation on the bus. + * + * @param[in] map - Object specific context handler. + * @param[in] writeDatabuf - Pointer to data buffer. + * @param[in] lenWriteData - Number of data to be written. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *write_data_buf, size_t len_write_data, hal_ll_i2c_master_end_mode_t mode ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_i2c_master_register_handle( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_master_handle_register_t *handle_map, uint8_t *hal_module_id ) { + + hal_ll_i2c_pin_id index_list[I2C_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + uint16_t pin_check_result; + + // Check if pins are valid + if ( (pin_check_result = hal_ll_i2c_master_check_pins( scl, sda, &index_list, handle_map )) == HAL_LL_PIN_NC ) { + return HAL_LL_I2C_MASTER_WRONG_PINS; + }; + + if ( (hal_ll_i2c_hw_specifics_map[pin_check_result].pins.pin_scl.pin_name != scl) || + (hal_ll_i2c_hw_specifics_map[pin_check_result].pins.pin_sda.pin_name != sda) ) + { + hal_ll_i2c_master_alternate_functions_set_state( &hal_ll_i2c_hw_specifics_map[ pin_check_result ], false ); + + hal_ll_i2c_master_map_pins( pin_check_result, &index_list ); + + hal_ll_i2c_master_alternate_functions_set_state( &hal_ll_i2c_hw_specifics_map[ pin_check_result ], true ); + + handle_map[pin_check_result].init_ll_state = false; + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[pin_check_result].hal_ll_i2c_master_handle = (handle_t *)&hal_ll_i2c_hw_specifics_map[pin_check_result].base; + + handle_map[pin_check_result].hal_ll_i2c_master_handle = (handle_t *)&hal_ll_module_state[pin_check_result].hal_ll_i2c_master_handle; + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_i2c( handle_t *handle ) { + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + hal_ll_i2c_master_handle_register_t *hal_handle = (hal_ll_i2c_master_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_i2c_hw_specifics_map_local->module_index; + + hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_local ); + + hal_ll_module_state[pin_check_result].hal_ll_i2c_master_handle = (handle_t *)&hal_ll_i2c_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_i2c_master_set_speed( handle_t *handle, uint32_t speed ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + low_level_handle->init_ll_state = false; + + hal_ll_i2c_hw_specifics_map_local->speed = speed; + + if ( hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_local ) != HAL_LL_I2C_MASTER_SUCCESS ) { + return HAL_LL_I2C_MASTER_TIMEOUT_INIT; + } + + low_level_handle->init_ll_state = true; + + return hal_ll_i2c_hw_specifics_map_local->speed; +} + +void hal_ll_i2c_master_set_timeout( handle_t *handle, uint16_t timeout ) { + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + if( hal_ll_i2c_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + hal_ll_i2c_hw_specifics_map_local->timeout = timeout; + } +} + +void hal_ll_i2c_master_set_slave_address( handle_t *handle, uint8_t addr ) { + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + if( hal_ll_i2c_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + hal_ll_i2c_hw_specifics_map_local->address = addr; + } +} + +hal_ll_err_t hal_ll_i2c_master_read( handle_t *handle, uint8_t *read_data_buf, size_t len_read_data ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + return hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_local, read_data_buf, len_read_data, HAL_LL_I2C_MASTER_END_MODE_STOP ); +} + +hal_ll_err_t hal_ll_i2c_master_write( handle_t *handle, uint8_t *write_data_buf, size_t len_write_data ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + return hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_local, write_data_buf, len_write_data, HAL_LL_I2C_MASTER_END_MODE_STOP ); +} + +hal_ll_err_t hal_ll_i2c_master_write_then_read( handle_t *handle, uint8_t *write_data_buf, size_t len_write_data, uint8_t *read_data_buf, size_t len_read_data ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + if( hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_local, write_data_buf, len_write_data, HAL_LL_I2C_MASTER_WRITE_THEN_READ ) != NULL ) { + return HAL_LL_I2C_MASTER_TIMEOUT_WRITE; + } + + /** + * @note Wait for drivers to set-up + * correctly. + **/ + #ifdef __TFT_RESISTIVE_TSC2003__ + Delay_22us(); + #endif + + if( hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_local, read_data_buf, len_read_data, HAL_LL_I2C_MASTER_WRITE_THEN_READ ) != NULL ) { + return HAL_LL_I2C_MASTER_TIMEOUT_READ; + } + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +void hal_ll_i2c_master_close( handle_t *handle ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + if( low_level_handle->hal_ll_i2c_master_handle != NULL ) { + low_level_handle->hal_ll_i2c_master_handle = NULL; + low_level_handle->hal_drv_i2c_master_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_i2c_hw_specifics_map_local->address = 0; + hal_ll_i2c_hw_specifics_map_local->timeout = HAL_LL_I2C_DEFAULT_PASS_COUNT; + hal_ll_i2c_hw_specifics_map_local->speed = HAL_LL_I2C_MASTER_SPEED_100K; + + hal_ll_i2c_master_set_clock(hal_ll_i2c_hw_specifics_map_local, true); + hal_ll_i2c_master_alternate_functions_set_state( hal_ll_i2c_hw_specifics_map_local, false ); + hal_ll_i2c_master_set_clock(hal_ll_i2c_hw_specifics_map_local, false); + + hal_ll_i2c_hw_specifics_map_local->pins.pin_scl.pin_name = HAL_LL_PIN_NC; + hal_ll_i2c_hw_specifics_map_local->pins.pin_sda.pin_name = HAL_LL_PIN_NC; + hal_ll_i2c_hw_specifics_map_local->pins.pin_scl.pin_af = 0; + hal_ll_i2c_hw_specifics_map_local->pins.pin_sda.pin_af = 0; + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static hal_ll_err_t hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *read_data_buf, size_t len_read_data, hal_ll_i2c_master_end_mode_t mode ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct(map->base); + uint16_t time_counter = map->timeout; + size_t transfer_counter = NULL; + uint8_t status = NULL; + + /** + * @note When R/W = 0, the input sample acquisition period starts + * on the falling edge of SCL once the C0 bit of the command + * byte has been latched, and ends when a Stop or + * repeated Start condition has been issued. + **/ + #ifdef __TFT_RESISTIVE_TSC2003__ + Delay_1ms(); + #endif + + hal_ll_i2c_master_configure_transfer ( map->base, + ( map->address << 1 & HAL_LL_I2C_CR2_SADD ) | + ( len_read_data << 16 & HAL_LL_I2C_CR2_NBYTES ) | + HAL_LL_I2C_CR2_RD_WRN | + HAL_LL_I2C_CR2_START + ); + + for ( transfer_counter; transfer_counter < len_read_data; transfer_counter++ ) { + while ( !( check_reg_bit( &( hal_ll_hw_reg->isr ), HAL_LL_I2C_RXNE_BIT ) ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_READ; + } + } + read_data_buf[ transfer_counter ] = hal_ll_hw_reg->rxdr; + } + + if ( ( mode == HAL_LL_I2C_MASTER_END_MODE_STOP ) || ( mode == HAL_LL_I2C_MASTER_WRITE_THEN_READ ) ) { + status = hal_ll_i2c_master_stop( map ); + } else { + status = hal_ll_i2c_master_start( map ); + } + + if( status != HAL_LL_I2C_MASTER_SUCCESS ) { + return status; + } + + hal_ll_i2c_master_reset_cr2( hal_ll_hw_reg ); + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static hal_ll_err_t hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *write_data_buf, size_t len_write_data, hal_ll_i2c_master_end_mode_t mode ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct(map->base); + uint16_t time_counter = map->timeout; + size_t transfer_counter = NULL; + uint8_t status = NULL; + + hal_ll_i2c_master_configure_transfer ( map->base, + ( map->address << 1 & HAL_LL_I2C_CR2_SADD ) | + ( len_write_data << 16 & HAL_LL_I2C_CR2_NBYTES ) | + !HAL_LL_I2C_CR2_RD_WRN | + HAL_LL_I2C_CR2_START + ); + + for ( transfer_counter; transfer_counter < len_write_data; transfer_counter++ ) + { + while ( !( check_reg_bit( &( hal_ll_hw_reg->isr ), HAL_LL_I2C_TXIS_BIT ) ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_WRITE; + } + } + hal_ll_hw_reg->txdr = write_data_buf[ transfer_counter ]; + } + + time_counter = map->timeout; + while ( !( check_reg_bit( &( hal_ll_hw_reg->isr ), HAL_LL_I2C_TXE_BIT ) ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_WRITE; + } + } + + if ( mode == HAL_LL_I2C_MASTER_END_MODE_STOP ) + { + hal_ll_i2c_master_stop( map ); + } + + hal_ll_i2c_master_reset_cr2( hal_ll_hw_reg ); + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static void hal_ll_i2c_master_configure_transfer( hal_ll_i2c_base_handle_t *hal_ll_hw_reg, uint32_t config ) { + uint32_t reg = 0; + + // Clear last set slave address + hal_ll_hw_reg->cr2 &= ~HAL_LL_I2C_CR2_SADD; + + reg = hal_ll_hw_reg->cr2; + reg &= ~( uint32_t )( + ( HAL_LL_I2C_CR2_SADD ) | + ( HAL_LL_I2C_CR2_NBYTES ) | + ( HAL_LL_I2C_CR2_RELOAD ) | + ( HAL_LL_I2C_CR2_AUTOEND ) | + ( HAL_LL_I2C_CR2_RD_WRN ) | + ( HAL_LL_I2C_CR2_START ) | + ( HAL_LL_I2C_CR2_STOP ) + ); + + reg |= config; + hal_ll_hw_reg->cr2 = reg; +} + +static void hal_ll_i2c_master_reset_cr2( hal_ll_i2c_base_handle_t *hal_ll_hw_reg ) { + hal_ll_hw_reg->cr2 &= ~( uint32_t ) + ( + HAL_LL_I2C_SADD_MASK | + HAL_LL_I2C_HEAD10R_MASK | + HAL_LL_I2C_NBYTES_MASK | + HAL_LL_I2C_RELOAD_MASK | + HAL_LL_I2C_RD_WRN_MASK + ); +} + +static hal_ll_err_t hal_ll_i2c_master_start( hal_ll_i2c_hw_specifics_map_t *map ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct(map->base); + uint16_t loop_index = HAL_LL_I2C_LOOP_INDEX; + + set_reg_bit( &(hal_ll_hw_reg->cr2), HAL_LL_I2C_CR2_START_BIT ); + + if ( check_reg_bit( &( hal_ll_hw_reg->isr ), HAL_LL_I2C_ARLO_BIT ) ) + return HAL_LL_I2C_MASTER_ARBITRATION_LOST; + + while ( loop_index-- ) + assembly(nop); + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static hal_ll_err_t hal_ll_i2c_master_stop( hal_ll_i2c_hw_specifics_map_t *map ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = ( hal_ll_i2c_base_handle_t* )map->base; + uint16_t time_counter = map->timeout; + uint32_t loop_index = HAL_LL_I2C_LOOP_INDEX; + + set_reg_bit( &(hal_ll_hw_reg->cr2), HAL_LL_I2C_CR2_STOP_BIT ); + + while ( !( hal_ll_hw_reg->isr & HAL_LL_I2C_ISR_STOPF_BIT ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_STOP; + } + } + + if ( map->timeout < HAL_LL_I2C_LOOP_INDEX ) { + while ( loop_index-- ) + assembly(nop); + } + + hal_ll_hw_reg->isr &= ~HAL_LL_I2C_ISR_STOPF_BIT; + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static hal_ll_pin_name_t hal_ll_i2c_master_check_pins( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_pin_id *index_list, hal_ll_i2c_master_handle_register_t *handle_map ) { + static const uint16_t scl_map_size = ( sizeof( hal_ll_i2c_scl_map ) / sizeof( hal_ll_i2c_pin_map_t ) ); + static const uint16_t sda_map_size = ( sizeof( hal_ll_i2c_sda_map ) / sizeof( hal_ll_i2c_pin_map_t ) ); + uint8_t hal_ll_module_id = 0; + uint8_t index_counter = 0; + uint16_t scl_index; + uint16_t sda_index; + + if ( (HAL_LL_PIN_NC == scl) || (HAL_LL_PIN_NC == sda) ) { + return HAL_LL_PIN_NC; + } + + for ( scl_index = 0; scl_index < scl_map_size; scl_index++ ) { + if ( hal_ll_i2c_scl_map[ scl_index ].pin == scl ) { + for ( sda_index = 0; sda_index < sda_map_size; sda_index++ ) { + if ( hal_ll_i2c_sda_map[ sda_index ].pin == sda ) { + if ( hal_ll_i2c_scl_map[ scl_index ].module_index == hal_ll_i2c_sda_map[ sda_index ].module_index ) { + // Get module number + hal_ll_module_id = hal_ll_i2c_scl_map[ scl_index ].module_index; + // Map pin names + index_list[hal_ll_module_id].pin_scl = scl_index; + index_list[hal_ll_module_id].pin_sda = sda_index; + + // Check if module is taken + if ( NULL == handle_map[ hal_ll_module_id ].hal_drv_i2c_master_handle ) { + return hal_ll_module_id; + } else if ( I2C_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static hal_ll_i2c_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof(hal_ll_i2c_master_handle_register_t)); + static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof(hal_ll_i2c_master_handle_register_t)); + + while( hal_ll_module_count-- ) { + if (hal_ll_i2c_get_base_from_hal_handle == hal_ll_i2c_hw_specifics_map[hal_ll_module_count].base) { + return &hal_ll_i2c_hw_specifics_map[hal_ll_module_count]; + } + } + + return &hal_ll_i2c_hw_specifics_map[hal_ll_module_error]; +} + +static void hal_ll_i2c_master_set_clock( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ) { + switch ( map->module_index ) + { + #if defined(I2C_MODULE_1) + case ( hal_ll_i2c_module_num(I2C_MODULE_1) ): + hal_ll_i2c1_set_clock( hal_ll_state ); + break; + #endif + + #if defined(I2C_MODULE_2) + case ( hal_ll_i2c_module_num(I2C_MODULE_2) ): + hal_ll_i2c2_set_clock( hal_ll_state ); + break; + #endif + + #if defined(I2C_MODULE_3) + case ( hal_ll_i2c_module_num(I2C_MODULE_3) ): + hal_ll_i2c3_set_clock( hal_ll_state ); + break; + #endif + + + default: + break; + } +} + +static void hal_ll_i2c_master_map_pins( uint8_t module_index, hal_ll_i2c_pin_id *index_list ) { + // Map new pins + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_scl.pin_name = hal_ll_i2c_scl_map[ index_list[module_index].pin_scl ].pin; + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_sda.pin_name = hal_ll_i2c_sda_map[ index_list[module_index].pin_sda ].pin; + // SCL and SDA could have different alternate function settings, hence save both AF values + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_scl.pin_af = hal_ll_i2c_scl_map[ index_list[module_index].pin_scl ].af; + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_sda.pin_af = hal_ll_i2c_sda_map[ index_list[module_index].pin_sda ].af; +} + +static void hal_ll_i2c_master_alternate_functions_set_state( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ) { + module_struct module; + + if( (map->pins.pin_scl.pin_name != HAL_LL_PIN_NC) && (map->pins.pin_sda.pin_name != HAL_LL_PIN_NC) ) { + module.pins[0] = VALUE( map->pins.pin_scl.pin_name, map->pins.pin_scl.pin_af ); + module.pins[1] = VALUE( map->pins.pin_sda.pin_name, map->pins.pin_sda.pin_af ); + module.pins[2] = GPIO_MODULE_STRUCT_END; + + module.configs[0] = HAL_LL_I2C_AF_CONFIG; + module.configs[1] = HAL_LL_I2C_AF_CONFIG; + module.configs[2] = GPIO_MODULE_STRUCT_END; + + hal_ll_gpio_module_struct_init( &module, hal_ll_state ); + } +} + +static uint32_t hal_ll_i2c_get_speed( hal_ll_i2c_hw_specifics_map_t *map ) { + if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_FAST ) { + if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_STANDARD ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_100K; + return HAL_LL_I2C_100K; + } else if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_FULL ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_400K; + return HAL_LL_I2C_400K; + } else if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_FAST ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_1M; + return HAL_LL_I2C_1M; + } else { + map->speed = HAL_LL_I2C_MASTER_SPEED_100K; + return HAL_LL_I2C_100K; + } + } else { + if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_100K ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_100K; + return HAL_LL_I2C_100K; + } else if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_400K ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_400K; + return HAL_LL_I2C_400K; + } else if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_1M ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_1M; + return HAL_LL_I2C_1M; + } else { + map->speed = HAL_LL_I2C_MASTER_SPEED_1M; + return HAL_LL_I2C_1M; + } + } +} +static inline void hal_ll_i2c1_set_clock( bool hal_ll_state ) { + if ( hal_ll_state ) { + set_reg_bit( _RCC_APBENR1, HAL_LL_I2C1EN_BIT ); + set_reg_bit( _RCC_CCIPR, HAL_LL_I2C12SEL1_BIT ); + } else { + clear_reg_bit( _RCC_APBENR1, HAL_LL_I2C1EN_BIT ); + clear_reg_bit( _RCC_CCIPR, HAL_LL_I2C12SEL1_BIT ); + } +} + + +static inline void hal_ll_i2c2_set_clock( bool hal_ll_state ) { + if ( hal_ll_state ) { + set_reg_bit( _RCC_APBENR1, HAL_LL_I2C2EN_BIT ); + set_reg_bit( _RCC_CCIPR, HAL_LL_I2C12SEL1_BIT ); + } else { + clear_reg_bit( _RCC_APBENR1, HAL_LL_I2C2EN_BIT ); + clear_reg_bit( _RCC_CCIPR, HAL_LL_I2C12SEL1_BIT ); + } +} + + +static inline void hal_ll_i2c3_set_clock( bool hal_ll_state ) { + if ( hal_ll_state ) { + set_reg_bit( _RCC_APBENR1, HAL_LL_I2C3EN_BIT ); + } else { + clear_reg_bit( _RCC_APBENR1, HAL_LL_I2C3EN_BIT ); + } +} + + + + +static hal_ll_err_t hal_ll_i2c_hw_init( hal_ll_i2c_hw_specifics_map_t *map ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct(map->base); + uint16_t time_counter = map->timeout; + + clear_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_I2C_PE_BIT ); + while ( check_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_I2C_PE_BIT ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_INIT; + } + } + + hal_ll_hw_reg->cr1 &= HAL_LL_I2C_FILTERS_OFF; + + hal_ll_hw_reg->timingr = hal_ll_i2c_get_speed( map ); + + hal_ll_hw_reg->cr1 |= HAL_LL_I2C_CR1_RXTX_INT; + + set_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_I2C_PE_BIT ); + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static hal_ll_err_t hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_t *map ) { + hal_ll_i2c_master_set_clock( map, true ); + + return hal_ll_i2c_hw_init( map ); +} +// ------------------------------------------------------------------------- END + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_82/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_82/CMakeLists.cmake new file mode 100644 index 000000000..8ea90a8ea --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_82/CMakeLists.cmake @@ -0,0 +1,9 @@ +if(${MCU_NAME} MATCHES "^STM32G431C6$|^STM32G431K6$|^STM32G431R6$|^STM32G431V6$|^STM32G431M6$|^STM32G431C8$|^STM32G431K8$|^STM32G431R8$|^STM32G431V8$|^STM32G431M8$|^STM32G431CB$|^STM32G431KB$|^STM32G431RB$|^STM32G431VB$|^STM32G431MB$") + set(i2c_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_i2c_master.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_82") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_82") + list(APPEND hal_ll_def_list "STM32G4xx") + list(APPEND hal_ll_def_list "STM32G43xx") + list(APPEND hal_ll_def_list "STM32G431xx") + set(i2c_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/i2c/hal_ll_i2c_pin_map/implementations/doc_ds_82") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_82/hal_ll_i2c_master.c b/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_82/hal_ll_i2c_master.c new file mode 100644 index 000000000..f8cf1f30e --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_82/hal_ll_i2c_master.c @@ -0,0 +1,958 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_i2c_master.c + * @brief I2C master HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_rcc.h" +#include "hal_ll_gpio.h" +#include "hal_ll_i2c_master.h" +#include "hal_ll_i2c_pin_map.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_i2c_master_handle_register_t hal_ll_module_state[I2C_MODULE_COUNT] = { (handle_t *)NULL, (handle_t *)NULL, false }; + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_i2c_get_module_state_address ((hal_ll_i2c_master_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_i2c_get_handle (hal_ll_i2c_master_handle_register_t *)hal_ll_i2c_get_module_state_address->hal_ll_i2c_master_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_i2c_get_base_struct(_handle) ((hal_ll_i2c_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_i2c_get_base_from_hal_handle ((hal_ll_i2c_hw_specifics_map_t *)((hal_ll_i2c_master_handle_register_t *)\ + (((hal_ll_i2c_master_handle_register_t *)(handle))->hal_ll_i2c_master_handle))->hal_ll_i2c_master_handle)->base + +/*!< @brief Default I2C bit-rate if no speed is set */ +#define HAL_LL_I2C_MASTER_SPEED_100K 100000UL +#define HAL_LL_I2C_MASTER_SPEED_400K 400000UL +#define HAL_LL_I2C_MASTER_SPEED_1M 1000000UL + +/*!< @brief Default pass count value upon reset */ +#define HAL_LL_I2C_DEFAULT_PASS_COUNT 0xFFFFU + +/*!< @brief Macro used for timeout */ +#define HAL_LL_I2C_LOOP_INDEX 10000U + +/*!< @brief Macros defining register bit location */ +#define HAL_LL_I2C1EN_BIT 21 +#define HAL_LL_I2C2EN_BIT 22 +#define HAL_LL_I2C3EN_BIT 30 + +#define HAL_LL_I2C1SEL0_BIT 12 +#define HAL_LL_I2C1SEL1_BIT 13 +#define HAL_LL_I2C2SEL0_BIT 14 + +#define HAL_LL_I2C2SEL1_BIT 15 +#define HAL_LL_I2C3SEL0_BIT 16 +#define HAL_LL_I2C3SEL1_BIT 17 + +#define HAL_LL_I2C_100K 0x30420F13 +#define HAL_LL_I2C_400K 0x10320309 +#define HAL_LL_I2C_1M 0x00200204 + +#define HAL_LL_I2C_PE_BIT 0 +#define HAL_LL_I2C_CR2_STOP_BIT 14 +#define HAL_LL_I2C_CR2_START_BIT 13 +#define HAL_LL_I2C_ISR_STOPF_BIT 5 +#define HAL_LL_I2C_ISR_BUSY_BIT 15 +#define HAL_LL_I2C_ARLO_BIT 9 +#define HAL_LL_I2C_RXNE_BIT 2 +#define HAL_LL_I2C_TXIS_BIT 1 +#define HAL_LL_I2C_TXE_BIT 0 + +/*!< @brief Macros defining register bit masks */ +#define HAL_LL_I2C_CR1_RXTX_INT 0x6 +#define HAL_LL_I2C_CR2_STOP 0x4000UL +#define HAL_LL_I2C_CR2_START 0x2000U +#define HAL_LL_I2C_CR2_SADD 0x3FFU +#define HAL_LL_I2C_CR2_NBYTES 0xFF0000UL +#define HAL_LL_I2C_CR2_RD_WRN 0x400U +#define HAL_LL_I2C_CR2_RELOAD 0x1000000UL +#define HAL_LL_I2C_CR2_AUTOEND 0x2000000UL +#define HAL_LL_I2C_FILTERS_OFF 0xFFFFE0FFUL +#define HAL_LL_I2C_SADD_MASK 0x3FFUL +#define HAL_LL_I2C_HEAD10R_MASK 0x1000UL +#define HAL_LL_I2C_NBYTES_MASK 0xFF0000UL +#define HAL_LL_I2C_RELOAD_MASK 0x1000000UL +#define HAL_LL_I2C_RD_WRN_MASK 0x400UL + +/*!< @brief Macros used for module pin checking */ +#define HAL_LL_I2C_SCL_PIN 0 +#define HAL_LL_I2C_SDA_PIN 1 +#define HAL_LL_I2C_MODULE_PIN_COUNT 2 + +/*!< @brief Macro used for setting pin alternate functions */ +#define HAL_LL_I2C_AF_CONFIG (GPIO_CFG_MODE_ALT_FUNCTION | GPIO_CFG_SPEED_HIGH | GPIO_CFG_OTYPE_OD) + +// -------------------------------------------------------------- PRIVATE TYPES +/*!< @brief I2C register structure */ +typedef struct +{ + hal_ll_base_addr_t cr1; + hal_ll_base_addr_t cr2; + hal_ll_base_addr_t oar1; + hal_ll_base_addr_t oar2; + hal_ll_base_addr_t timingr; + hal_ll_base_addr_t timeoutr; + hal_ll_base_addr_t isr; + hal_ll_base_addr_t icr; + hal_ll_base_addr_t pecr; + hal_ll_base_addr_t rxdr; + hal_ll_base_addr_t txdr; +} hal_ll_i2c_base_handle_t; + +/*!< @brief I2C hw specific structure */ +typedef struct +{ + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + hal_ll_i2c_pins_t pins; + uint32_t speed; + uint8_t address; + uint16_t timeout; +} hal_ll_i2c_hw_specifics_map_t; + +/*!< @brief I2C hw specific module values */ +typedef struct +{ + uint16_t pin_scl; + uint16_t pin_sda; +} hal_ll_i2c_pin_id; + +/*!< @brief I2C hw specific error values */ +typedef enum +{ + HAL_LL_I2C_MASTER_SUCCESS = 0, + HAL_LL_I2C_MASTER_WRONG_PINS, + HAL_LL_I2C_MASTER_MODULE_ERROR, + + HAL_LL_I2C_MASTER_ERROR = (-1) +} hal_ll_i2c_master_err_t; + +/*!< @brief I2C end mode selection values */ +typedef enum +{ + HAL_LL_I2C_MASTER_END_MODE_RESTART = 0, + HAL_LL_I2C_MASTER_END_MODE_STOP, + HAL_LL_I2C_MASTER_WRITE_THEN_READ +} hal_ll_i2c_master_end_mode_t; + +/*!< @brief I2C timeout error values */ +typedef enum +{ + HAL_LL_I2C_MASTER_TIMEOUT_START = 1300, + HAL_LL_I2C_MASTER_TIMEOUT_STOP, + HAL_LL_I2C_MASTER_TIMEOUT_WRITE, + HAL_LL_I2C_MASTER_TIMEOUT_READ, + HAL_LL_I2C_MASTER_ARBITRATION_LOST, + HAL_LL_I2C_MASTER_TIMEOUT_INIT +} hal_ll_i2c_master_timeout_t; + +/** + * @brief Enum containing predefined module standard speed values. + * + * Enum values: + * HAL_LL_I2C_MASTER_SPEED_STANDARD -- Speed set at 100K + * HAL_LL_I2C_MASTER_SPEED_FULL -- Speed set at 400K + * HAL_LL_I2C_MASTER_SPEED_FAST -- Speed set at 1M + */ +typedef enum +{ + HAL_LL_I2C_MASTER_SPEED_STANDARD = 0, + HAL_LL_I2C_MASTER_SPEED_FULL, + HAL_LL_I2C_MASTER_SPEED_FAST +} hal_ll_i2c_master_speed_t; + +// ------------------------------------------------------------------ VARIABLES +/*!< @brief I2C hardware specific info */ +static hal_ll_i2c_hw_specifics_map_t hal_ll_i2c_hw_specifics_map[] = +{ + #ifdef I2C_MODULE_1 + {HAL_LL_I2C1_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_1), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, + #endif + #ifdef I2C_MODULE_2 + {HAL_LL_I2C2_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_2), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, + #endif + #ifdef I2C_MODULE_3 + {HAL_LL_I2C3_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_3), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, + #endif + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, 0, 0} +}; + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_i2c_master_handle_register_t *low_level_handle; +static volatile hal_ll_i2c_hw_specifics_map_t *hal_ll_i2c_hw_specifics_map_local; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Check if pins are adequate. + * + * Checks scl and sda pins the user has passed with pre-defined + * pins in scl and sda maps. Take into consideration that module + * index numbers have to be the same for both pins. + * + * @param[in] scl - SCL pre-defined pin name. + * @param[in] sda - SDA pre-defined pin name. + * @param[in] *index_list - Index list address + * @return hal_ll_pin_name_t Module index based on pins. + * + * Returns pre-defined module index from pin maps, if pins + * are adequate. + */ +static hal_ll_pin_name_t hal_ll_i2c_master_check_pins( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_pin_id *index_list, hal_ll_i2c_master_handle_register_t *handle_map ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_i2c_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_i2c_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_i2c_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Get adequate I2C bit-rate value. + * + * Returns one of pre-defined bit-rate values, + * or the closest bit-rate based on bit_rate + * value passed to the function. + * + * @param[in] bit_rate - I2C bit rate. + * @return uint32_t Adequate bit-rate value. + * + * Returns adequate value to be latter written into bare metal register address. + * Take into consideration that this returns a predefined value. + * + * HAL_LL_I2C_MASTER_SPEED_100K -- 100Kbit/s + * HAL_LL_I2C_MASTER_SPEED_400K -- 400Kbit/s + * HAL_LL_I2C_MASTER_SPEED_1M -- 1Mbit/s + * HAL_LL_I2C_MASTER_SPEED_3M2 -- 3.2Mbit/s + */ +static uint32_t hal_ll_i2c_get_speed( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Enable clock for I2C1 module on hardware level. + * + * Initializes I2C1 module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] hal_ll_state - True/False -- Init/De-init + * + * @return None + */ +static inline void hal_ll_i2c1_set_clock( bool hal_ll_state ); + +/** + * @brief Enable clock for I2C2 module on hardware level. + * + * Initializes I2C2 module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] hal_ll_state - True/False -- Init/De-init + * + * @return None + */ +static inline void hal_ll_i2c2_set_clock( bool hal_ll_state ); + +/** + * @brief Enable clock for I2C3 module on hardware level. + * + * Initializes I2C3 module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] hal_ll_state - True/False -- Init/De-init + * + * @return None + */ +static inline void hal_ll_i2c3_set_clock( bool hal_ll_state ); + +/** + * @brief Enable clock for I2C module on hardware level. + * + * Initializes I2C module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_stat - True(enable clock)/False(disable clock). + * + * @return None + */ +static void hal_ll_i2c_master_set_clock( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Initialize I2C module on hardware level. + * + * Initializes I2C module on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] map - Object specific context handler. + * @return hal_ll_err_t Module specific return values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_hw_init( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * I2C SCL and SDA pins. + * + * @param[in] module_index I2C HW module index -- 0,1,2... + * @param[in] *index_list Array with SCL and SDA map index values + * and module number + * + * @return None + */ +static void hal_ll_i2c_master_map_pins( uint8_t module_index, hal_ll_i2c_pin_id *index_list ); + +/** + * @brief Sets I2C pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if I2C is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_state - Init/De-init + * + * @return None + */ +static void hal_ll_i2c_master_alternate_functions_set_state( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Full I2C module initialization procedure. + * + * Initializes I2C module on hardware level, based on beforehand + * set configuration and module handler. Sets adequate pin alternate functions. + * Initializes module clock. + * + * @param[in] map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Configure I2C module for data transfer. + * + * @param[in] hal_ll_hw_reg - I2C module base address. + * @param[in] config - I2C config bits. + * @return void None. + */ +static void hal_ll_i2c_master_configure_transfer( hal_ll_i2c_base_handle_t *hal_ll_hw_reg, uint32_t config ); + +/** + * @brief Reset value of I2C CR2 register. + * + * @param[in] hal_ll_hw_reg - I2C module base address. + * @returnl none + */ +static void hal_ll_i2c_master_reset_cr2( hal_ll_i2c_base_handle_t *hal_ll_hw_reg ); + +/** + * @brief Generates start signal on I2C bus. + * + * Generates a start signal on the I2C bus. + * + * @param[in] map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_master_start( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Generates stop signal on I2C bus. + * + * Generates a stop signal on the I2C bus. + * + * @param[in] map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_master_stop( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Perform a read on the I2C bus. + * + * Initializes I2C module on hardware level, if not initialized beforehand + * and continues to perform a read operation on the bus. + * + * @param[in] map - Object specific context handler. + * @param[in] readDatabuf - Pointer to data buffer. + * @param[in] lenReadData - Number of data to be read. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *read_data_buf, size_t len_read_data, hal_ll_i2c_master_end_mode_t mode ); + +/** + * @brief Perform a write on the I2C bus. + * + * Initializes I2C module on hardware level, if not initialized beforehand + * and continues to perform a write operation on the bus. + * + * @param[in] map - Object specific context handler. + * @param[in] writeDatabuf - Pointer to data buffer. + * @param[in] lenWriteData - Number of data to be written. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *write_data_buf, size_t len_write_data, hal_ll_i2c_master_end_mode_t mode ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_i2c_master_register_handle( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_master_handle_register_t *handle_map, uint8_t *hal_module_id ) { + + hal_ll_i2c_pin_id index_list[I2C_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + uint16_t pin_check_result; + + // Check if pins are valid + if ( (pin_check_result = hal_ll_i2c_master_check_pins( scl, sda, &index_list, handle_map )) == HAL_LL_PIN_NC ) { + return HAL_LL_I2C_MASTER_WRONG_PINS; + }; + + if ( (hal_ll_i2c_hw_specifics_map[pin_check_result].pins.pin_scl.pin_name != scl) || + (hal_ll_i2c_hw_specifics_map[pin_check_result].pins.pin_sda.pin_name != sda) ) + { + hal_ll_i2c_master_alternate_functions_set_state( &hal_ll_i2c_hw_specifics_map[ pin_check_result ], false ); + + hal_ll_i2c_master_map_pins( pin_check_result, &index_list ); + + hal_ll_i2c_master_alternate_functions_set_state( &hal_ll_i2c_hw_specifics_map[ pin_check_result ], true ); + + handle_map[pin_check_result].init_ll_state = false; + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[pin_check_result].hal_ll_i2c_master_handle = (handle_t *)&hal_ll_i2c_hw_specifics_map[pin_check_result].base; + + handle_map[pin_check_result].hal_ll_i2c_master_handle = (handle_t *)&hal_ll_module_state[pin_check_result].hal_ll_i2c_master_handle; + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_i2c( handle_t *handle ) { + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + hal_ll_i2c_master_handle_register_t *hal_handle = (hal_ll_i2c_master_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_i2c_hw_specifics_map_local->module_index; + + hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_local ); + + hal_ll_module_state[pin_check_result].hal_ll_i2c_master_handle = (handle_t *)&hal_ll_i2c_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_i2c_master_set_speed( handle_t *handle, uint32_t speed ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + low_level_handle->init_ll_state = false; + + hal_ll_i2c_hw_specifics_map_local->speed = speed; + + if ( hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_local ) != HAL_LL_I2C_MASTER_SUCCESS ) { + return HAL_LL_I2C_MASTER_TIMEOUT_INIT; + } + + low_level_handle->init_ll_state = true; + + return hal_ll_i2c_hw_specifics_map_local->speed; +} + +void hal_ll_i2c_master_set_timeout( handle_t *handle, uint16_t timeout ) { + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + if( hal_ll_i2c_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + hal_ll_i2c_hw_specifics_map_local->timeout = timeout; + } +} + +void hal_ll_i2c_master_set_slave_address( handle_t *handle, uint8_t addr ) { + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + if( hal_ll_i2c_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + hal_ll_i2c_hw_specifics_map_local->address = addr; + } +} + +hal_ll_err_t hal_ll_i2c_master_read( handle_t *handle, uint8_t *read_data_buf, size_t len_read_data ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + return hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_local, read_data_buf, len_read_data, HAL_LL_I2C_MASTER_END_MODE_STOP ); +} + +hal_ll_err_t hal_ll_i2c_master_write( handle_t *handle, uint8_t *write_data_buf, size_t len_write_data ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + return hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_local, write_data_buf, len_write_data, HAL_LL_I2C_MASTER_END_MODE_STOP ); +} + +hal_ll_err_t hal_ll_i2c_master_write_then_read( handle_t *handle, uint8_t *write_data_buf, size_t len_write_data, uint8_t *read_data_buf, size_t len_read_data ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + if( hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_local, write_data_buf, len_write_data, HAL_LL_I2C_MASTER_WRITE_THEN_READ ) != NULL ) { + return HAL_LL_I2C_MASTER_TIMEOUT_WRITE; + } + + /** + * @note Wait for drivers to set-up + * correctly. + **/ + #ifdef __TFT_RESISTIVE_TSC2003__ + Delay_22us(); + #endif + + if( hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_local, read_data_buf, len_read_data, HAL_LL_I2C_MASTER_WRITE_THEN_READ ) != NULL ) { + return HAL_LL_I2C_MASTER_TIMEOUT_READ; + } + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +void hal_ll_i2c_master_close( handle_t *handle ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + if( low_level_handle->hal_ll_i2c_master_handle != NULL ) { + low_level_handle->hal_ll_i2c_master_handle = NULL; + low_level_handle->hal_drv_i2c_master_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_i2c_hw_specifics_map_local->address = 0; + hal_ll_i2c_hw_specifics_map_local->timeout = HAL_LL_I2C_DEFAULT_PASS_COUNT; + hal_ll_i2c_hw_specifics_map_local->speed = HAL_LL_I2C_MASTER_SPEED_100K; + + hal_ll_i2c_master_set_clock(hal_ll_i2c_hw_specifics_map_local, true); + hal_ll_i2c_master_alternate_functions_set_state( hal_ll_i2c_hw_specifics_map_local, false ); + hal_ll_i2c_master_set_clock(hal_ll_i2c_hw_specifics_map_local, false); + + hal_ll_i2c_hw_specifics_map_local->pins.pin_scl.pin_name = HAL_LL_PIN_NC; + hal_ll_i2c_hw_specifics_map_local->pins.pin_sda.pin_name = HAL_LL_PIN_NC; + hal_ll_i2c_hw_specifics_map_local->pins.pin_scl.pin_af = 0; + hal_ll_i2c_hw_specifics_map_local->pins.pin_sda.pin_af = 0; + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static hal_ll_err_t hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *read_data_buf, size_t len_read_data, hal_ll_i2c_master_end_mode_t mode ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct(map->base); + uint16_t time_counter = map->timeout; + size_t transfer_counter = NULL; + uint8_t status = NULL; + + /** + * @note When R/W = 0, the input sample acquisition period starts + * on the falling edge of SCL once the C0 bit of the command + * byte has been latched, and ends when a Stop or + * repeated Start condition has been issued. + **/ + #ifdef __TFT_RESISTIVE_TSC2003__ + Delay_1ms(); + #endif + + hal_ll_i2c_master_configure_transfer ( map->base, + ( map->address << 1 & HAL_LL_I2C_CR2_SADD ) | + ( len_read_data << 16 & HAL_LL_I2C_CR2_NBYTES ) | + HAL_LL_I2C_CR2_RD_WRN | + HAL_LL_I2C_CR2_START + ); + + for ( transfer_counter; transfer_counter < len_read_data; transfer_counter++ ) { + while ( !( check_reg_bit( &( hal_ll_hw_reg->isr ), HAL_LL_I2C_RXNE_BIT ) ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_READ; + } + } + read_data_buf[ transfer_counter ] = hal_ll_hw_reg->rxdr; + } + + if ( ( mode == HAL_LL_I2C_MASTER_END_MODE_STOP ) || ( mode == HAL_LL_I2C_MASTER_WRITE_THEN_READ ) ) { + status = hal_ll_i2c_master_stop( map ); + } else { + status = hal_ll_i2c_master_start( map ); + } + + if( status != HAL_LL_I2C_MASTER_SUCCESS ) { + return status; + } + + hal_ll_i2c_master_reset_cr2( hal_ll_hw_reg ); + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static hal_ll_err_t hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *write_data_buf, size_t len_write_data, hal_ll_i2c_master_end_mode_t mode ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct(map->base); + uint16_t time_counter = map->timeout; + size_t transfer_counter = NULL; + uint8_t status = NULL; + + hal_ll_i2c_master_configure_transfer ( map->base, + ( map->address << 1 & HAL_LL_I2C_CR2_SADD ) | + ( len_write_data << 16 & HAL_LL_I2C_CR2_NBYTES ) | + !HAL_LL_I2C_CR2_RD_WRN | + HAL_LL_I2C_CR2_START + ); + + for ( transfer_counter; transfer_counter < len_write_data; transfer_counter++ ) + { + while ( !( check_reg_bit( &( hal_ll_hw_reg->isr ), HAL_LL_I2C_TXIS_BIT ) ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_WRITE; + } + } + hal_ll_hw_reg->txdr = write_data_buf[ transfer_counter ]; + } + + time_counter = map->timeout; + while ( !( check_reg_bit( &( hal_ll_hw_reg->isr ), HAL_LL_I2C_TXE_BIT ) ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_WRITE; + } + } + + if ( mode == HAL_LL_I2C_MASTER_END_MODE_STOP ) + { + hal_ll_i2c_master_stop( map ); + } + + hal_ll_i2c_master_reset_cr2( hal_ll_hw_reg ); + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static void hal_ll_i2c_master_configure_transfer( hal_ll_i2c_base_handle_t *hal_ll_hw_reg, uint32_t config ) { + uint32_t reg = 0; + + // Clear last set slave address + hal_ll_hw_reg->cr2 &= ~HAL_LL_I2C_CR2_SADD; + + reg = hal_ll_hw_reg->cr2; + reg &= ~( uint32_t )( + ( HAL_LL_I2C_CR2_SADD ) | + ( HAL_LL_I2C_CR2_NBYTES ) | + ( HAL_LL_I2C_CR2_RELOAD ) | + ( HAL_LL_I2C_CR2_AUTOEND ) | + ( HAL_LL_I2C_CR2_RD_WRN ) | + ( HAL_LL_I2C_CR2_START ) | + ( HAL_LL_I2C_CR2_STOP ) + ); + + reg |= config; + hal_ll_hw_reg->cr2 = reg; +} + +static void hal_ll_i2c_master_reset_cr2( hal_ll_i2c_base_handle_t *hal_ll_hw_reg ) { + hal_ll_hw_reg->cr2 &= ~( uint32_t ) + ( + HAL_LL_I2C_SADD_MASK | + HAL_LL_I2C_HEAD10R_MASK | + HAL_LL_I2C_NBYTES_MASK | + HAL_LL_I2C_RELOAD_MASK | + HAL_LL_I2C_RD_WRN_MASK + ); +} + +static hal_ll_err_t hal_ll_i2c_master_start( hal_ll_i2c_hw_specifics_map_t *map ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct(map->base); + uint16_t loop_index = HAL_LL_I2C_LOOP_INDEX; + + set_reg_bit( &(hal_ll_hw_reg->cr2), HAL_LL_I2C_CR2_START_BIT ); + + if ( check_reg_bit( &( hal_ll_hw_reg->isr ), HAL_LL_I2C_ARLO_BIT ) ) + return HAL_LL_I2C_MASTER_ARBITRATION_LOST; + + while ( loop_index-- ) + assembly(nop); + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static hal_ll_err_t hal_ll_i2c_master_stop( hal_ll_i2c_hw_specifics_map_t *map ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = ( hal_ll_i2c_base_handle_t* )map->base; + uint16_t time_counter = map->timeout; + uint32_t loop_index = HAL_LL_I2C_LOOP_INDEX; + + set_reg_bit( &(hal_ll_hw_reg->cr2), HAL_LL_I2C_CR2_STOP_BIT ); + + while ( !( hal_ll_hw_reg->isr & HAL_LL_I2C_ISR_STOPF_BIT ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_STOP; + } + } + + if ( map->timeout < HAL_LL_I2C_LOOP_INDEX ) { + while ( loop_index-- ) + assembly(nop); + } + + hal_ll_hw_reg->isr &= ~HAL_LL_I2C_ISR_STOPF_BIT; + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static hal_ll_pin_name_t hal_ll_i2c_master_check_pins( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_pin_id *index_list, hal_ll_i2c_master_handle_register_t *handle_map ) { + static const uint16_t scl_map_size = ( sizeof( hal_ll_i2c_scl_map ) / sizeof( hal_ll_i2c_pin_map_t ) ); + static const uint16_t sda_map_size = ( sizeof( hal_ll_i2c_sda_map ) / sizeof( hal_ll_i2c_pin_map_t ) ); + uint8_t hal_ll_module_id = 0; + uint8_t index_counter = 0; + uint16_t scl_index; + uint16_t sda_index; + + if ( (HAL_LL_PIN_NC == scl) || (HAL_LL_PIN_NC == sda) ) { + return HAL_LL_PIN_NC; + } + + for ( scl_index = 0; scl_index < scl_map_size; scl_index++ ) { + if ( hal_ll_i2c_scl_map[ scl_index ].pin == scl ) { + for ( sda_index = 0; sda_index < sda_map_size; sda_index++ ) { + if ( hal_ll_i2c_sda_map[ sda_index ].pin == sda ) { + if ( hal_ll_i2c_scl_map[ scl_index ].module_index == hal_ll_i2c_sda_map[ sda_index ].module_index ) { + // Get module number + hal_ll_module_id = hal_ll_i2c_scl_map[ scl_index ].module_index; + // Map pin names + index_list[hal_ll_module_id].pin_scl = scl_index; + index_list[hal_ll_module_id].pin_sda = sda_index; + + // Check if module is taken + if ( NULL == handle_map[ hal_ll_module_id ].hal_drv_i2c_master_handle ) { + return hal_ll_module_id; + } else if ( I2C_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static hal_ll_i2c_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof(hal_ll_i2c_master_handle_register_t)); + static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof(hal_ll_i2c_master_handle_register_t)); + + while( hal_ll_module_count-- ) { + if (hal_ll_i2c_get_base_from_hal_handle == hal_ll_i2c_hw_specifics_map[hal_ll_module_count].base) { + return &hal_ll_i2c_hw_specifics_map[hal_ll_module_count]; + } + } + + return &hal_ll_i2c_hw_specifics_map[hal_ll_module_error]; +} + +static void hal_ll_i2c_master_set_clock( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ) { + switch ( map->module_index ) + { + #if defined(I2C_MODULE_1) + case ( hal_ll_i2c_module_num(I2C_MODULE_1) ): + hal_ll_i2c1_set_clock( hal_ll_state ); + break; + #endif + + #if defined(I2C_MODULE_2) + case ( hal_ll_i2c_module_num(I2C_MODULE_2) ): + hal_ll_i2c2_set_clock( hal_ll_state ); + break; + #endif + + #if defined(I2C_MODULE_3) + case ( hal_ll_i2c_module_num(I2C_MODULE_3) ): + hal_ll_i2c3_set_clock( hal_ll_state ); + break; + #endif + + + default: + break; + } +} + +static void hal_ll_i2c_master_map_pins( uint8_t module_index, hal_ll_i2c_pin_id *index_list ) { + // Map new pins + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_scl.pin_name = hal_ll_i2c_scl_map[ index_list[module_index].pin_scl ].pin; + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_sda.pin_name = hal_ll_i2c_sda_map[ index_list[module_index].pin_sda ].pin; + // SCL and SDA could have different alternate function settings, hence save both AF values + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_scl.pin_af = hal_ll_i2c_scl_map[ index_list[module_index].pin_scl ].af; + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_sda.pin_af = hal_ll_i2c_sda_map[ index_list[module_index].pin_sda ].af; +} + +static void hal_ll_i2c_master_alternate_functions_set_state( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ) { + module_struct module; + + if( (map->pins.pin_scl.pin_name != HAL_LL_PIN_NC) && (map->pins.pin_sda.pin_name != HAL_LL_PIN_NC) ) { + module.pins[0] = VALUE( map->pins.pin_scl.pin_name, map->pins.pin_scl.pin_af ); + module.pins[1] = VALUE( map->pins.pin_sda.pin_name, map->pins.pin_sda.pin_af ); + module.pins[2] = GPIO_MODULE_STRUCT_END; + + module.configs[0] = HAL_LL_I2C_AF_CONFIG; + module.configs[1] = HAL_LL_I2C_AF_CONFIG; + module.configs[2] = GPIO_MODULE_STRUCT_END; + + hal_ll_gpio_module_struct_init( &module, hal_ll_state ); + } +} + +static uint32_t hal_ll_i2c_get_speed( hal_ll_i2c_hw_specifics_map_t *map ) { + if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_FAST ) { + if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_STANDARD ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_100K; + return HAL_LL_I2C_100K; + } else if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_FULL ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_400K; + return HAL_LL_I2C_400K; + } else if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_FAST ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_1M; + return HAL_LL_I2C_1M; + } else { + map->speed = HAL_LL_I2C_MASTER_SPEED_100K; + return HAL_LL_I2C_100K; + } + } else { + if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_100K ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_100K; + return HAL_LL_I2C_100K; + } else if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_400K ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_400K; + return HAL_LL_I2C_400K; + } else if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_1M ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_1M; + return HAL_LL_I2C_1M; + } else { + map->speed = HAL_LL_I2C_MASTER_SPEED_1M; + return HAL_LL_I2C_1M; + } + } +} + +static inline void hal_ll_i2c1_set_clock( bool hal_ll_state ) { + if ( hal_ll_state ) { + set_reg_bit( _RCC_APB1ENR1, HAL_LL_I2C1EN_BIT ); + set_reg_bit( _RCC_CCIPR, HAL_LL_I2C1SEL1_BIT ); + } else { + clear_reg_bit( _RCC_APB1ENR1, HAL_LL_I2C1EN_BIT ); + clear_reg_bit( _RCC_CCIPR, HAL_LL_I2C1SEL1_BIT ); + } +} + +static inline void hal_ll_i2c2_set_clock( bool hal_ll_state ) { + if ( hal_ll_state ) { + set_reg_bit( _RCC_APB1ENR1, HAL_LL_I2C2EN_BIT ); + set_reg_bit( _RCC_CCIPR, HAL_LL_I2C2SEL1_BIT ); + } else { + clear_reg_bit( _RCC_APB1ENR1, HAL_LL_I2C2EN_BIT ); + clear_reg_bit( _RCC_CCIPR, HAL_LL_I2C2SEL1_BIT ); + } +} + +static inline void hal_ll_i2c3_set_clock( bool hal_ll_state ) { + if ( hal_ll_state ) { + set_reg_bit( _RCC_APB1ENR1, HAL_LL_I2C3EN_BIT ); + set_reg_bit( _RCC_CCIPR, HAL_LL_I2C3SEL1_BIT ); + } else { + clear_reg_bit( _RCC_APB1ENR1, HAL_LL_I2C3EN_BIT ); + clear_reg_bit( _RCC_CCIPR, HAL_LL_I2C3SEL1_BIT ); + } +} + +static hal_ll_err_t hal_ll_i2c_hw_init( hal_ll_i2c_hw_specifics_map_t *map ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct(map->base); + uint16_t time_counter = map->timeout; + + clear_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_I2C_PE_BIT ); + while ( check_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_I2C_PE_BIT ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_INIT; + } + } + + hal_ll_hw_reg->cr1 &= HAL_LL_I2C_FILTERS_OFF; + + hal_ll_hw_reg->timingr = hal_ll_i2c_get_speed( map ); + + hal_ll_hw_reg->cr1 |= HAL_LL_I2C_CR1_RXTX_INT; + + set_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_I2C_PE_BIT ); + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static hal_ll_err_t hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_t *map ) { + hal_ll_i2c_master_set_clock( map, true ); + + return hal_ll_i2c_hw_init( map ); +} +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_83/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_83/CMakeLists.cmake new file mode 100644 index 000000000..e08eb0d21 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_83/CMakeLists.cmake @@ -0,0 +1,9 @@ +if(${MCU_NAME} MATCHES "^STM32G441CB$|^STM32G441KB$|^STM32G441RB$|^STM32G441MB$|^STM32G441VB$") + set(i2c_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_i2c_master.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_83") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_83") + list(APPEND hal_ll_def_list "STM32G4xx") + list(APPEND hal_ll_def_list "STM32G44xx") + list(APPEND hal_ll_def_list "STM32G441xx") + set(i2c_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/i2c/hal_ll_i2c_pin_map/implementations/doc_ds_83") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_83/hal_ll_i2c_master.c b/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_83/hal_ll_i2c_master.c new file mode 100644 index 000000000..5e1ea38a2 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_83/hal_ll_i2c_master.c @@ -0,0 +1,976 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_i2c_master.c + * @brief I2C master HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_rcc.h" +#include "hal_ll_gpio.h" +#include "hal_ll_i2c_master.h" +#include "hal_ll_i2c_pin_map.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_i2c_master_handle_register_t hal_ll_module_state[I2C_MODULE_COUNT] = { (handle_t *)NULL, (handle_t *)NULL, false }; + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_i2c_get_module_state_address ((hal_ll_i2c_master_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_i2c_get_handle (hal_ll_i2c_master_handle_register_t *)hal_ll_i2c_get_module_state_address->hal_ll_i2c_master_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_i2c_get_base_struct(_handle) ((hal_ll_i2c_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_i2c_get_base_from_hal_handle ((hal_ll_i2c_hw_specifics_map_t *)((hal_ll_i2c_master_handle_register_t *)\ + (((hal_ll_i2c_master_handle_register_t *)(handle))->hal_ll_i2c_master_handle))->hal_ll_i2c_master_handle)->base + +/*!< @brief Default I2C bit-rate if no speed is set */ +#define HAL_LL_I2C_MASTER_SPEED_100K 100000UL +#define HAL_LL_I2C_MASTER_SPEED_400K 400000UL +#define HAL_LL_I2C_MASTER_SPEED_1M 1000000UL + +/*!< @brief Default pass count value upon reset */ +#define HAL_LL_I2C_DEFAULT_PASS_COUNT 0xFFFFU + +/*!< @brief Macro used for timeout */ +#define HAL_LL_I2C_LOOP_INDEX 10000U + +/*!< @brief Macros defining register bit location */ +#define HAL_LL_I2C1EN_BIT 21 + +#define HAL_LL_I2C2EN_BIT 22 + +#define HAL_LL_I2C3EN_BIT 30 + +#define HAL_LL_I2C1SEL0_BIT 12 + +#define HAL_LL_I2C1SEL1_BIT 13 + +#define HAL_LL_I2C2SEL0_BIT 14 + +#define HAL_LL_I2C2SEL1_BIT 15 + +#define HAL_LL_I2C3SEL0_BIT 16 + +#define HAL_LL_I2C3SEL1_BIT 17 + + + + +#define HAL_LL_I2C_100K 0x30420F13 //?????????????????? +#define HAL_LL_I2C_400K 0x10320309 //?????????????????? +#define HAL_LL_I2C_1M 0x00200204 //?????????????????? + +#define HAL_LL_I2C_PE_BIT 0 +#define HAL_LL_I2C_CR2_STOP_BIT 14 +#define HAL_LL_I2C_CR2_START_BIT 13 +#define HAL_LL_I2C_ISR_STOPF_BIT 5 +#define HAL_LL_I2C_ISR_BUSY_BIT 15 +#define HAL_LL_I2C_ARLO_BIT 9 +#define HAL_LL_I2C_RXNE_BIT 2 +#define HAL_LL_I2C_TXIS_BIT 1 +#define HAL_LL_I2C_TXE_BIT 0 + +/*!< @brief Macros defining register bit masks */ +#define HAL_LL_I2C_CR1_RXTX_INT 0x6 +#define HAL_LL_I2C_CR2_STOP 0x4000UL +#define HAL_LL_I2C_CR2_START 0x2000U +#define HAL_LL_I2C_CR2_SADD 0x3FFU +#define HAL_LL_I2C_CR2_NBYTES 0xFF0000UL +#define HAL_LL_I2C_CR2_RD_WRN 0x400U +#define HAL_LL_I2C_CR2_RELOAD 0x1000000UL +#define HAL_LL_I2C_CR2_AUTOEND 0x2000000UL +#define HAL_LL_I2C_FILTERS_OFF 0xFFFFE0FFUL +#define HAL_LL_I2C_SADD_MASK 0x3FFUL +#define HAL_LL_I2C_HEAD10R_MASK 0x1000UL +#define HAL_LL_I2C_NBYTES_MASK 0xFF0000UL +#define HAL_LL_I2C_RELOAD_MASK 0x1000000UL +#define HAL_LL_I2C_RD_WRN_MASK 0x400UL + +/*!< @brief Macros used for module pin checking */ +#define HAL_LL_I2C_SCL_PIN 0 +#define HAL_LL_I2C_SDA_PIN 1 +#define HAL_LL_I2C_MODULE_PIN_COUNT 2 + +/*!< @brief Macro used for setting pin alternate functions */ +#define HAL_LL_I2C_AF_CONFIG (GPIO_CFG_MODE_ALT_FUNCTION | GPIO_CFG_SPEED_HIGH | GPIO_CFG_OTYPE_OD) + +// -------------------------------------------------------------- PRIVATE TYPES +/*!< @brief I2C register structure */ +typedef struct +{ + hal_ll_base_addr_t cr1; + hal_ll_base_addr_t cr2; + hal_ll_base_addr_t oar1; + hal_ll_base_addr_t oar2; + hal_ll_base_addr_t timingr; + hal_ll_base_addr_t timeoutr; + hal_ll_base_addr_t isr; + hal_ll_base_addr_t icr; + hal_ll_base_addr_t pecr; + hal_ll_base_addr_t rxdr; + hal_ll_base_addr_t txdr; + +} hal_ll_i2c_base_handle_t; + +/*!< @brief I2C hw specific structure */ +typedef struct +{ + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + hal_ll_i2c_pins_t pins; + uint32_t speed; + uint8_t address; + uint16_t timeout; +} hal_ll_i2c_hw_specifics_map_t; + +/*!< @brief I2C hw specific module values */ +typedef struct +{ + uint16_t pin_scl; + uint16_t pin_sda; +} hal_ll_i2c_pin_id; + +/*!< @brief I2C hw specific error values */ +typedef enum +{ + HAL_LL_I2C_MASTER_SUCCESS = 0, + HAL_LL_I2C_MASTER_WRONG_PINS, + HAL_LL_I2C_MASTER_MODULE_ERROR, + + HAL_LL_I2C_MASTER_ERROR = (-1) +} hal_ll_i2c_master_err_t; + +/*!< @brief I2C end mode selection values */ +typedef enum +{ + HAL_LL_I2C_MASTER_END_MODE_RESTART = 0, + HAL_LL_I2C_MASTER_END_MODE_STOP, + HAL_LL_I2C_MASTER_WRITE_THEN_READ +} hal_ll_i2c_master_end_mode_t; + +/*!< @brief I2C timeout error values */ +typedef enum +{ + HAL_LL_I2C_MASTER_TIMEOUT_START = 1300, + HAL_LL_I2C_MASTER_TIMEOUT_STOP, + HAL_LL_I2C_MASTER_TIMEOUT_WRITE, + HAL_LL_I2C_MASTER_TIMEOUT_READ, + HAL_LL_I2C_MASTER_ARBITRATION_LOST, + HAL_LL_I2C_MASTER_TIMEOUT_INIT +} hal_ll_i2c_master_timeout_t; + +/** + * @brief Enum containing predefined module standard speed values. + * + * Enum values: + * HAL_LL_I2C_MASTER_SPEED_STANDARD -- Speed set at 100K + * HAL_LL_I2C_MASTER_SPEED_FULL -- Speed set at 400K + * HAL_LL_I2C_MASTER_SPEED_FAST -- Speed set at 1M + */ +typedef enum +{ + HAL_LL_I2C_MASTER_SPEED_STANDARD = 0, + HAL_LL_I2C_MASTER_SPEED_FULL, + HAL_LL_I2C_MASTER_SPEED_FAST +} hal_ll_i2c_master_speed_t; + +// ------------------------------------------------------------------ VARIABLES +/*!< @brief I2C hardware specific info */ +static hal_ll_i2c_hw_specifics_map_t hal_ll_i2c_hw_specifics_map[] = +{ + #ifdef I2C_MODULE_1 + {HAL_LL_I2C1_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_1), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, + #endif + + #ifdef I2C_MODULE_2 + {HAL_LL_I2C2_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_2), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, + #endif + + #ifdef I2C_MODULE_3 + {HAL_LL_I2C3_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_3), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, + #endif + + + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, 0, 0} +}; + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_i2c_master_handle_register_t *low_level_handle; +static volatile hal_ll_i2c_hw_specifics_map_t *hal_ll_i2c_hw_specifics_map_local; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Check if pins are adequate. + * + * Checks scl and sda pins the user has passed with pre-defined + * pins in scl and sda maps. Take into consideration that module + * index numbers have to be the same for both pins. + * + * @param[in] scl - SCL pre-defined pin name. + * @param[in] sda - SDA pre-defined pin name. + * @param[in] *index_list - Index list address + * @return hal_ll_pin_name_t Module index based on pins. + * + * Returns pre-defined module index from pin maps, if pins + * are adequate. + */ +static hal_ll_pin_name_t hal_ll_i2c_master_check_pins( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_pin_id *index_list, hal_ll_i2c_master_handle_register_t *handle_map ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_i2c_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_i2c_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_i2c_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Get adequate I2C bit-rate value. + * + * Returns one of pre-defined bit-rate values, + * or the closest bit-rate based on bit_rate + * value passed to the function. + * + * @param[in] bit_rate - I2C bit rate. + * @return uint32_t Adequate bit-rate value. + * + * Returns adequate value to be latter written into bare metal register address. + * Take into consideration that this returns a predefined value. + * + * HAL_LL_I2C_MASTER_SPEED_100K -- 100Kbit/s + * HAL_LL_I2C_MASTER_SPEED_400K -- 400Kbit/s + * HAL_LL_I2C_MASTER_SPEED_1M -- 1Mbit/s + * HAL_LL_I2C_MASTER_SPEED_3M2 -- 3.2Mbit/s + */ +static uint32_t hal_ll_i2c_get_speed( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Enable clock for I2C1 module on hardware level. + * + * Initializes I2C1 module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] hal_ll_state - True/False -- Init/De-init + * + * @return None + */ +static inline void hal_ll_i2c1_set_clock( bool hal_ll_state ); + +/** + * @brief Enable clock for I2C2 module on hardware level. + * + * Initializes I2C2 module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] hal_ll_state - True/False -- Init/De-init + * + * @return None + */ +static inline void hal_ll_i2c2_set_clock( bool hal_ll_state ); + +/** + * @brief Enable clock for I2C3 module on hardware level. + * + * Initializes I2C3 module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] hal_ll_state - True/False -- Init/De-init + * + * @return None + */ +static inline void hal_ll_i2c3_set_clock( bool hal_ll_state ); + +/** + * @brief Enable clock for I2C module on hardware level. + * + * Initializes I2C module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_stat - True(enable clock)/False(disable clock). + * + * @return None + */ +static void hal_ll_i2c_master_set_clock( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Initialize I2C module on hardware level. + * + * Initializes I2C module on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] map - Object specific context handler. + * @return hal_ll_err_t Module specific return values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_hw_init( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * I2C SCL and SDA pins. + * + * @param[in] module_index I2C HW module index -- 0,1,2... + * @param[in] *index_list Array with SCL and SDA map index values + * and module number + * + * @return None + */ +static void hal_ll_i2c_master_map_pins( uint8_t module_index, hal_ll_i2c_pin_id *index_list ); + +/** + * @brief Sets I2C pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if I2C is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_state - Init/De-init + * + * @return None + */ +static void hal_ll_i2c_master_alternate_functions_set_state( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Full I2C module initialization procedure. + * + * Initializes I2C module on hardware level, based on beforehand + * set configuration and module handler. Sets adequate pin alternate functions. + * Initializes module clock. + * + * @param[in] map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Configure I2C module for data transfer. + * + * @param[in] hal_ll_hw_reg - I2C module base address. + * @param[in] config - I2C config bits. + * @return void None. + */ +static void hal_ll_i2c_master_configure_transfer( hal_ll_i2c_base_handle_t *hal_ll_hw_reg, uint32_t config ); + +/** + * @brief Reset value of I2C CR2 register. + * + * @param[in] hal_ll_hw_reg - I2C module base address. + * @returnl none + */ +static void hal_ll_i2c_master_reset_cr2( hal_ll_i2c_base_handle_t *hal_ll_hw_reg ); + +/** + * @brief Generates start signal on I2C bus. + * + * Generates a start signal on the I2C bus. + * + * @param[in] map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_master_start( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Generates stop signal on I2C bus. + * + * Generates a stop signal on the I2C bus. + * + * @param[in] map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_master_stop( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Perform a read on the I2C bus. + * + * Initializes I2C module on hardware level, if not initialized beforehand + * and continues to perform a read operation on the bus. + * + * @param[in] map - Object specific context handler. + * @param[in] readDatabuf - Pointer to data buffer. + * @param[in] lenReadData - Number of data to be read. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *read_data_buf, size_t len_read_data, hal_ll_i2c_master_end_mode_t mode ); + +/** + * @brief Perform a write on the I2C bus. + * + * Initializes I2C module on hardware level, if not initialized beforehand + * and continues to perform a write operation on the bus. + * + * @param[in] map - Object specific context handler. + * @param[in] writeDatabuf - Pointer to data buffer. + * @param[in] lenWriteData - Number of data to be written. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *write_data_buf, size_t len_write_data, hal_ll_i2c_master_end_mode_t mode ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_i2c_master_register_handle( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_master_handle_register_t *handle_map, uint8_t *hal_module_id ) { + + hal_ll_i2c_pin_id index_list[I2C_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + uint16_t pin_check_result; + + // Check if pins are valid + if ( (pin_check_result = hal_ll_i2c_master_check_pins( scl, sda, &index_list, handle_map )) == HAL_LL_PIN_NC ) { + return HAL_LL_I2C_MASTER_WRONG_PINS; + }; + + if ( (hal_ll_i2c_hw_specifics_map[pin_check_result].pins.pin_scl.pin_name != scl) || + (hal_ll_i2c_hw_specifics_map[pin_check_result].pins.pin_sda.pin_name != sda) ) + { + hal_ll_i2c_master_alternate_functions_set_state( &hal_ll_i2c_hw_specifics_map[ pin_check_result ], false ); + + hal_ll_i2c_master_map_pins( pin_check_result, &index_list ); + + hal_ll_i2c_master_alternate_functions_set_state( &hal_ll_i2c_hw_specifics_map[ pin_check_result ], true ); + + handle_map[pin_check_result].init_ll_state = false; + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[pin_check_result].hal_ll_i2c_master_handle = (handle_t *)&hal_ll_i2c_hw_specifics_map[pin_check_result].base; + + handle_map[pin_check_result].hal_ll_i2c_master_handle = (handle_t *)&hal_ll_module_state[pin_check_result].hal_ll_i2c_master_handle; + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_i2c( handle_t *handle ) { + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + hal_ll_i2c_master_handle_register_t *hal_handle = (hal_ll_i2c_master_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_i2c_hw_specifics_map_local->module_index; + + hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_local ); + + hal_ll_module_state[pin_check_result].hal_ll_i2c_master_handle = (handle_t *)&hal_ll_i2c_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_i2c_master_set_speed( handle_t *handle, uint32_t speed ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + low_level_handle->init_ll_state = false; + + hal_ll_i2c_hw_specifics_map_local->speed = speed; + + if ( hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_local ) != HAL_LL_I2C_MASTER_SUCCESS ) { + return HAL_LL_I2C_MASTER_TIMEOUT_INIT; + } + + low_level_handle->init_ll_state = true; + + return hal_ll_i2c_hw_specifics_map_local->speed; +} + +void hal_ll_i2c_master_set_timeout( handle_t *handle, uint16_t timeout ) { + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + if( hal_ll_i2c_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + hal_ll_i2c_hw_specifics_map_local->timeout = timeout; + } +} + +void hal_ll_i2c_master_set_slave_address( handle_t *handle, uint8_t addr ) { + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + if( hal_ll_i2c_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + hal_ll_i2c_hw_specifics_map_local->address = addr; + } +} + +hal_ll_err_t hal_ll_i2c_master_read( handle_t *handle, uint8_t *read_data_buf, size_t len_read_data ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + return hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_local, read_data_buf, len_read_data, HAL_LL_I2C_MASTER_END_MODE_STOP ); +} + +hal_ll_err_t hal_ll_i2c_master_write( handle_t *handle, uint8_t *write_data_buf, size_t len_write_data ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + return hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_local, write_data_buf, len_write_data, HAL_LL_I2C_MASTER_END_MODE_STOP ); +} + +hal_ll_err_t hal_ll_i2c_master_write_then_read( handle_t *handle, uint8_t *write_data_buf, size_t len_write_data, uint8_t *read_data_buf, size_t len_read_data ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + if( hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_local, write_data_buf, len_write_data, HAL_LL_I2C_MASTER_WRITE_THEN_READ ) != NULL ) { + return HAL_LL_I2C_MASTER_TIMEOUT_WRITE; + } + + /** + * @note Wait for drivers to set-up + * correctly. + **/ + #ifdef __TFT_RESISTIVE_TSC2003__ + Delay_22us(); + #endif + + if( hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_local, read_data_buf, len_read_data, HAL_LL_I2C_MASTER_WRITE_THEN_READ ) != NULL ) { + return HAL_LL_I2C_MASTER_TIMEOUT_READ; + } + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +void hal_ll_i2c_master_close( handle_t *handle ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + if( low_level_handle->hal_ll_i2c_master_handle != NULL ) { + low_level_handle->hal_ll_i2c_master_handle = NULL; + low_level_handle->hal_drv_i2c_master_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_i2c_hw_specifics_map_local->address = 0; + hal_ll_i2c_hw_specifics_map_local->timeout = HAL_LL_I2C_DEFAULT_PASS_COUNT; + hal_ll_i2c_hw_specifics_map_local->speed = HAL_LL_I2C_MASTER_SPEED_100K; + + hal_ll_i2c_master_set_clock(hal_ll_i2c_hw_specifics_map_local, true); + hal_ll_i2c_master_alternate_functions_set_state( hal_ll_i2c_hw_specifics_map_local, false ); + hal_ll_i2c_master_set_clock(hal_ll_i2c_hw_specifics_map_local, false); + + hal_ll_i2c_hw_specifics_map_local->pins.pin_scl.pin_name = HAL_LL_PIN_NC; + hal_ll_i2c_hw_specifics_map_local->pins.pin_sda.pin_name = HAL_LL_PIN_NC; + hal_ll_i2c_hw_specifics_map_local->pins.pin_scl.pin_af = 0; + hal_ll_i2c_hw_specifics_map_local->pins.pin_sda.pin_af = 0; + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static hal_ll_err_t hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *read_data_buf, size_t len_read_data, hal_ll_i2c_master_end_mode_t mode ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct(map->base); + uint16_t time_counter = map->timeout; + size_t transfer_counter = NULL; + uint8_t status = NULL; + + /** + * @note When R/W = 0, the input sample acquisition period starts + * on the falling edge of SCL once the C0 bit of the command + * byte has been latched, and ends when a Stop or + * repeated Start condition has been issued. + **/ + #ifdef __TFT_RESISTIVE_TSC2003__ + Delay_1ms(); + #endif + + hal_ll_i2c_master_configure_transfer ( map->base, + ( map->address << 1 & HAL_LL_I2C_CR2_SADD ) | + ( len_read_data << 16 & HAL_LL_I2C_CR2_NBYTES ) | + HAL_LL_I2C_CR2_RD_WRN | + HAL_LL_I2C_CR2_START + ); + + for ( transfer_counter; transfer_counter < len_read_data; transfer_counter++ ) { + while ( !( check_reg_bit( &( hal_ll_hw_reg->isr ), HAL_LL_I2C_RXNE_BIT ) ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_READ; + } + } + read_data_buf[ transfer_counter ] = hal_ll_hw_reg->rxdr; + } + + if ( ( mode == HAL_LL_I2C_MASTER_END_MODE_STOP ) || ( mode == HAL_LL_I2C_MASTER_WRITE_THEN_READ ) ) { + status = hal_ll_i2c_master_stop( map ); + } else { + status = hal_ll_i2c_master_start( map ); + } + + if( status != HAL_LL_I2C_MASTER_SUCCESS ) { + return status; + } + + hal_ll_i2c_master_reset_cr2( hal_ll_hw_reg ); + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static hal_ll_err_t hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *write_data_buf, size_t len_write_data, hal_ll_i2c_master_end_mode_t mode ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct(map->base); + uint16_t time_counter = map->timeout; + size_t transfer_counter = NULL; + uint8_t status = NULL; + + hal_ll_i2c_master_configure_transfer ( map->base, + ( map->address << 1 & HAL_LL_I2C_CR2_SADD ) | + ( len_write_data << 16 & HAL_LL_I2C_CR2_NBYTES ) | + !HAL_LL_I2C_CR2_RD_WRN | + HAL_LL_I2C_CR2_START + ); + + for ( transfer_counter; transfer_counter < len_write_data; transfer_counter++ ) + { + while ( !( check_reg_bit( &( hal_ll_hw_reg->isr ), HAL_LL_I2C_TXIS_BIT ) ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_WRITE; + } + } + hal_ll_hw_reg->txdr = write_data_buf[ transfer_counter ]; + } + + time_counter = map->timeout; + while ( !( check_reg_bit( &( hal_ll_hw_reg->isr ), HAL_LL_I2C_TXE_BIT ) ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_WRITE; + } + } + + if ( mode == HAL_LL_I2C_MASTER_END_MODE_STOP ) + { + hal_ll_i2c_master_stop( map ); + } + + hal_ll_i2c_master_reset_cr2( hal_ll_hw_reg ); + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static void hal_ll_i2c_master_configure_transfer( hal_ll_i2c_base_handle_t *hal_ll_hw_reg, uint32_t config ) { + uint32_t reg = 0; + + // Clear last set slave address + hal_ll_hw_reg->cr2 &= ~HAL_LL_I2C_CR2_SADD; + + reg = hal_ll_hw_reg->cr2; + reg &= ~( uint32_t )( + ( HAL_LL_I2C_CR2_SADD ) | + ( HAL_LL_I2C_CR2_NBYTES ) | + ( HAL_LL_I2C_CR2_RELOAD ) | + ( HAL_LL_I2C_CR2_AUTOEND ) | + ( HAL_LL_I2C_CR2_RD_WRN ) | + ( HAL_LL_I2C_CR2_START ) | + ( HAL_LL_I2C_CR2_STOP ) + ); + + reg |= config; + hal_ll_hw_reg->cr2 = reg; +} + +static void hal_ll_i2c_master_reset_cr2( hal_ll_i2c_base_handle_t *hal_ll_hw_reg ) { + hal_ll_hw_reg->cr2 &= ~( uint32_t ) + ( + HAL_LL_I2C_SADD_MASK | + HAL_LL_I2C_HEAD10R_MASK | + HAL_LL_I2C_NBYTES_MASK | + HAL_LL_I2C_RELOAD_MASK | + HAL_LL_I2C_RD_WRN_MASK + ); +} + +static hal_ll_err_t hal_ll_i2c_master_start( hal_ll_i2c_hw_specifics_map_t *map ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct(map->base); + uint16_t loop_index = HAL_LL_I2C_LOOP_INDEX; + + set_reg_bit( &(hal_ll_hw_reg->cr2), HAL_LL_I2C_CR2_START_BIT ); + + if ( check_reg_bit( &( hal_ll_hw_reg->isr ), HAL_LL_I2C_ARLO_BIT ) ) + return HAL_LL_I2C_MASTER_ARBITRATION_LOST; + + while ( loop_index-- ) + assembly(nop); + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static hal_ll_err_t hal_ll_i2c_master_stop( hal_ll_i2c_hw_specifics_map_t *map ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = ( hal_ll_i2c_base_handle_t* )map->base; + uint16_t time_counter = map->timeout; + uint32_t loop_index = HAL_LL_I2C_LOOP_INDEX; + + set_reg_bit( &(hal_ll_hw_reg->cr2), HAL_LL_I2C_CR2_STOP_BIT ); + + while ( !( hal_ll_hw_reg->isr & HAL_LL_I2C_ISR_STOPF_BIT ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_STOP; + } + } + + if ( map->timeout < HAL_LL_I2C_LOOP_INDEX ) { + while ( loop_index-- ) + assembly(nop); + } + + hal_ll_hw_reg->isr &= ~HAL_LL_I2C_ISR_STOPF_BIT; + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static hal_ll_pin_name_t hal_ll_i2c_master_check_pins( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_pin_id *index_list, hal_ll_i2c_master_handle_register_t *handle_map ) { + static const uint16_t scl_map_size = ( sizeof( hal_ll_i2c_scl_map ) / sizeof( hal_ll_i2c_pin_map_t ) ); + static const uint16_t sda_map_size = ( sizeof( hal_ll_i2c_sda_map ) / sizeof( hal_ll_i2c_pin_map_t ) ); + uint8_t hal_ll_module_id = 0; + uint8_t index_counter = 0; + uint16_t scl_index; + uint16_t sda_index; + + if ( (HAL_LL_PIN_NC == scl) || (HAL_LL_PIN_NC == sda) ) { + return HAL_LL_PIN_NC; + } + + for ( scl_index = 0; scl_index < scl_map_size; scl_index++ ) { + if ( hal_ll_i2c_scl_map[ scl_index ].pin == scl ) { + for ( sda_index = 0; sda_index < sda_map_size; sda_index++ ) { + if ( hal_ll_i2c_sda_map[ sda_index ].pin == sda ) { + if ( hal_ll_i2c_scl_map[ scl_index ].module_index == hal_ll_i2c_sda_map[ sda_index ].module_index ) { + // Get module number + hal_ll_module_id = hal_ll_i2c_scl_map[ scl_index ].module_index; + // Map pin names + index_list[hal_ll_module_id].pin_scl = scl_index; + index_list[hal_ll_module_id].pin_sda = sda_index; + + // Check if module is taken + if ( NULL == handle_map[ hal_ll_module_id ].hal_drv_i2c_master_handle ) { + return hal_ll_module_id; + } else if ( I2C_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static hal_ll_i2c_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof(hal_ll_i2c_master_handle_register_t)); + static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof(hal_ll_i2c_master_handle_register_t)); + + while( hal_ll_module_count-- ) { + if (hal_ll_i2c_get_base_from_hal_handle == hal_ll_i2c_hw_specifics_map[hal_ll_module_count].base) { + return &hal_ll_i2c_hw_specifics_map[hal_ll_module_count]; + } + } + + return &hal_ll_i2c_hw_specifics_map[hal_ll_module_error]; +} + +static void hal_ll_i2c_master_set_clock( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ) { + switch ( map->module_index ) + { + #if defined(I2C_MODULE_1) + case ( hal_ll_i2c_module_num(I2C_MODULE_1) ): + hal_ll_i2c1_set_clock( hal_ll_state ); + break; + #endif + + #if defined(I2C_MODULE_2) + case ( hal_ll_i2c_module_num(I2C_MODULE_2) ): + hal_ll_i2c2_set_clock( hal_ll_state ); + break; + #endif + + #if defined(I2C_MODULE_3) + case ( hal_ll_i2c_module_num(I2C_MODULE_3) ): + hal_ll_i2c3_set_clock( hal_ll_state ); + break; + #endif + + + default: + break; + } +} + +static void hal_ll_i2c_master_map_pins( uint8_t module_index, hal_ll_i2c_pin_id *index_list ) { + // Map new pins + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_scl.pin_name = hal_ll_i2c_scl_map[ index_list[module_index].pin_scl ].pin; + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_sda.pin_name = hal_ll_i2c_sda_map[ index_list[module_index].pin_sda ].pin; + // SCL and SDA could have different alternate function settings, hence save both AF values + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_scl.pin_af = hal_ll_i2c_scl_map[ index_list[module_index].pin_scl ].af; + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_sda.pin_af = hal_ll_i2c_sda_map[ index_list[module_index].pin_sda ].af; +} + +static void hal_ll_i2c_master_alternate_functions_set_state( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ) { + module_struct module; + + if( (map->pins.pin_scl.pin_name != HAL_LL_PIN_NC) && (map->pins.pin_sda.pin_name != HAL_LL_PIN_NC) ) { + module.pins[0] = VALUE( map->pins.pin_scl.pin_name, map->pins.pin_scl.pin_af ); + module.pins[1] = VALUE( map->pins.pin_sda.pin_name, map->pins.pin_sda.pin_af ); + module.pins[2] = GPIO_MODULE_STRUCT_END; + + module.configs[0] = HAL_LL_I2C_AF_CONFIG; + module.configs[1] = HAL_LL_I2C_AF_CONFIG; + module.configs[2] = GPIO_MODULE_STRUCT_END; + + hal_ll_gpio_module_struct_init( &module, hal_ll_state ); + } +} + +static uint32_t hal_ll_i2c_get_speed( hal_ll_i2c_hw_specifics_map_t *map ) { + if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_FAST ) { + if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_STANDARD ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_100K; + return HAL_LL_I2C_100K; + } else if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_FULL ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_400K; + return HAL_LL_I2C_400K; + } else if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_FAST ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_1M; + return HAL_LL_I2C_1M; + } else { + map->speed = HAL_LL_I2C_MASTER_SPEED_100K; + return HAL_LL_I2C_100K; + } + } else { + if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_100K ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_100K; + return HAL_LL_I2C_100K; + } else if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_400K ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_400K; + return HAL_LL_I2C_400K; + } else if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_1M ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_1M; + return HAL_LL_I2C_1M; + } else { + map->speed = HAL_LL_I2C_MASTER_SPEED_1M; + return HAL_LL_I2C_1M; + } + } +} +static inline void hal_ll_i2c1_set_clock( bool hal_ll_state ) { + if ( hal_ll_state ) { + set_reg_bit( _RCC_APB1ENR1, HAL_LL_I2C1EN_BIT ); + set_reg_bit( _RCC_CCIPR, HAL_LL_I2C1SEL1_BIT ); + } else { + clear_reg_bit( _RCC_APB1ENR1, HAL_LL_I2C1EN_BIT ); + clear_reg_bit( _RCC_CCIPR, HAL_LL_I2C1SEL1_BIT ); + } +} + + +static inline void hal_ll_i2c2_set_clock( bool hal_ll_state ) { + if ( hal_ll_state ) { + set_reg_bit( _RCC_APB1ENR1, HAL_LL_I2C2EN_BIT ); + set_reg_bit( _RCC_CCIPR, HAL_LL_I2C2SEL1_BIT ); + } else { + clear_reg_bit( _RCC_APB1ENR1, HAL_LL_I2C2EN_BIT ); + clear_reg_bit( _RCC_CCIPR, HAL_LL_I2C2SEL1_BIT ); + } +} + + +static inline void hal_ll_i2c3_set_clock( bool hal_ll_state ) { + if ( hal_ll_state ) { + set_reg_bit( _RCC_APB1ENR1, HAL_LL_I2C3EN_BIT ); + set_reg_bit( _RCC_CCIPR, HAL_LL_I2C3SEL1_BIT ); + } else { + clear_reg_bit( _RCC_APB1ENR1, HAL_LL_I2C3EN_BIT ); + clear_reg_bit( _RCC_CCIPR, HAL_LL_I2C3SEL1_BIT ); + } +} + + + +static hal_ll_err_t hal_ll_i2c_hw_init( hal_ll_i2c_hw_specifics_map_t *map ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct(map->base); + uint16_t time_counter = map->timeout; + + clear_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_I2C_PE_BIT ); + while ( check_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_I2C_PE_BIT ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_INIT; + } + } + + hal_ll_hw_reg->cr1 &= HAL_LL_I2C_FILTERS_OFF; + + hal_ll_hw_reg->timingr = hal_ll_i2c_get_speed( map ); + + hal_ll_hw_reg->cr1 |= HAL_LL_I2C_CR1_RXTX_INT; + + set_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_I2C_PE_BIT ); + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static hal_ll_err_t hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_t *map ) { + hal_ll_i2c_master_set_clock( map, true ); + + return hal_ll_i2c_hw_init( map ); +} +// ------------------------------------------------------------------------- END + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_84/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_84/CMakeLists.cmake new file mode 100644 index 000000000..344478c94 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_84/CMakeLists.cmake @@ -0,0 +1,9 @@ +if(${MCU_NAME} MATCHES "^STM32G473CB$|^STM32G473MB$|^STM32G473PB$|^STM32G473RB$|^STM32G473VB$|^STM32G473QB$|^STM32G473CC$|^STM32G473MC$|^STM32G473PC$|^STM32G473RC$|^STM32G473VC$|^STM32G473QC$|^STM32G473CE$|^STM32G473ME$|^STM32G473PE$|^STM32G473RE$|^STM32G473VE$|^STM32G473QE$") + set(i2c_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_i2c_master.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_84") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_84") + list(APPEND hal_ll_def_list "STM32G4xx") + list(APPEND hal_ll_def_list "STM32G47xx") + list(APPEND hal_ll_def_list "STM32G473xx") + set(i2c_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/i2c/hal_ll_i2c_pin_map/implementations/doc_ds_84") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_84/hal_ll_i2c_master.c b/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_84/hal_ll_i2c_master.c new file mode 100644 index 000000000..2d9b5f410 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_84/hal_ll_i2c_master.c @@ -0,0 +1,1015 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_i2c_master.c + * @brief I2C master HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_rcc.h" +#include "hal_ll_gpio.h" +#include "hal_ll_i2c_master.h" +#include "hal_ll_i2c_pin_map.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_i2c_master_handle_register_t hal_ll_module_state[I2C_MODULE_COUNT] = { (handle_t *)NULL, (handle_t *)NULL, false }; + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_i2c_get_module_state_address ((hal_ll_i2c_master_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_i2c_get_handle (hal_ll_i2c_master_handle_register_t *)hal_ll_i2c_get_module_state_address->hal_ll_i2c_master_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_i2c_get_base_struct(_handle) ((hal_ll_i2c_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_i2c_get_base_from_hal_handle ((hal_ll_i2c_hw_specifics_map_t *)((hal_ll_i2c_master_handle_register_t *)\ + (((hal_ll_i2c_master_handle_register_t *)(handle))->hal_ll_i2c_master_handle))->hal_ll_i2c_master_handle)->base + +/*!< @brief Default I2C bit-rate if no speed is set */ +#define HAL_LL_I2C_MASTER_SPEED_100K 100000UL +#define HAL_LL_I2C_MASTER_SPEED_400K 400000UL +#define HAL_LL_I2C_MASTER_SPEED_1M 1000000UL + +/*!< @brief Default pass count value upon reset */ +#define HAL_LL_I2C_DEFAULT_PASS_COUNT 0xFFFFU + +/*!< @brief Macro used for timeout */ +#define HAL_LL_I2C_LOOP_INDEX 10000U + +/*!< @brief Macros defining register bit location */ +#define HAL_LL_I2C1EN_BIT 21 + +#define HAL_LL_I2C2EN_BIT 22 + +#define HAL_LL_I2C3EN_BIT 30 + +#define HAL_LL_I2C4EN_BIT 1 + +#define HAL_LL_I2C1SEL0_BIT 12 + +#define HAL_LL_I2C1SEL1_BIT 13 + +#define HAL_LL_I2C2SEL0_BIT 14 + +#define HAL_LL_I2C2SEL1_BIT 15 + +#define HAL_LL_I2C3SEL0_BIT 16 + +#define HAL_LL_I2C3SEL1_BIT 17 + +#define HAL_LL_I2C4SEL0_BIT 0 + +#define HAL_LL_I2C4SEL1_BIT 1 + + + + +#define HAL_LL_I2C_100K 0x30420F13 //?????????????????? +#define HAL_LL_I2C_400K 0x10320309 //?????????????????? +#define HAL_LL_I2C_1M 0x00200204 //?????????????????? + +#define HAL_LL_I2C_PE_BIT 0 +#define HAL_LL_I2C_CR2_STOP_BIT 14 +#define HAL_LL_I2C_CR2_START_BIT 13 +#define HAL_LL_I2C_ISR_STOPF_BIT 5 +#define HAL_LL_I2C_ISR_BUSY_BIT 15 +#define HAL_LL_I2C_ARLO_BIT 9 +#define HAL_LL_I2C_RXNE_BIT 2 +#define HAL_LL_I2C_TXIS_BIT 1 +#define HAL_LL_I2C_TXE_BIT 0 + +/*!< @brief Macros defining register bit masks */ +#define HAL_LL_I2C_CR1_RXTX_INT 0x6 +#define HAL_LL_I2C_CR2_STOP 0x4000UL +#define HAL_LL_I2C_CR2_START 0x2000U +#define HAL_LL_I2C_CR2_SADD 0x3FFU +#define HAL_LL_I2C_CR2_NBYTES 0xFF0000UL +#define HAL_LL_I2C_CR2_RD_WRN 0x400U +#define HAL_LL_I2C_CR2_RELOAD 0x1000000UL +#define HAL_LL_I2C_CR2_AUTOEND 0x2000000UL +#define HAL_LL_I2C_FILTERS_OFF 0xFFFFE0FFUL +#define HAL_LL_I2C_SADD_MASK 0x3FFUL +#define HAL_LL_I2C_HEAD10R_MASK 0x1000UL +#define HAL_LL_I2C_NBYTES_MASK 0xFF0000UL +#define HAL_LL_I2C_RELOAD_MASK 0x1000000UL +#define HAL_LL_I2C_RD_WRN_MASK 0x400UL + +/*!< @brief Macros used for module pin checking */ +#define HAL_LL_I2C_SCL_PIN 0 +#define HAL_LL_I2C_SDA_PIN 1 +#define HAL_LL_I2C_MODULE_PIN_COUNT 2 + +/*!< @brief Macro used for setting pin alternate functions */ +#define HAL_LL_I2C_AF_CONFIG (GPIO_CFG_MODE_ALT_FUNCTION | GPIO_CFG_SPEED_HIGH | GPIO_CFG_OTYPE_OD) + +// -------------------------------------------------------------- PRIVATE TYPES +/*!< @brief I2C register structure */ +typedef struct +{ + hal_ll_base_addr_t cr1; + hal_ll_base_addr_t cr2; + hal_ll_base_addr_t oar1; + hal_ll_base_addr_t oar2; + hal_ll_base_addr_t timingr; + hal_ll_base_addr_t timeoutr; + hal_ll_base_addr_t isr; + hal_ll_base_addr_t icr; + hal_ll_base_addr_t pecr; + hal_ll_base_addr_t rxdr; + hal_ll_base_addr_t txdr; + +} hal_ll_i2c_base_handle_t; + +/*!< @brief I2C hw specific structure */ +typedef struct +{ + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + hal_ll_i2c_pins_t pins; + uint32_t speed; + uint8_t address; + uint16_t timeout; +} hal_ll_i2c_hw_specifics_map_t; + +/*!< @brief I2C hw specific module values */ +typedef struct +{ + uint16_t pin_scl; + uint16_t pin_sda; +} hal_ll_i2c_pin_id; + +/*!< @brief I2C hw specific error values */ +typedef enum +{ + HAL_LL_I2C_MASTER_SUCCESS = 0, + HAL_LL_I2C_MASTER_WRONG_PINS, + HAL_LL_I2C_MASTER_MODULE_ERROR, + + HAL_LL_I2C_MASTER_ERROR = (-1) +} hal_ll_i2c_master_err_t; + +/*!< @brief I2C end mode selection values */ +typedef enum +{ + HAL_LL_I2C_MASTER_END_MODE_RESTART = 0, + HAL_LL_I2C_MASTER_END_MODE_STOP, + HAL_LL_I2C_MASTER_WRITE_THEN_READ +} hal_ll_i2c_master_end_mode_t; + +/*!< @brief I2C timeout error values */ +typedef enum +{ + HAL_LL_I2C_MASTER_TIMEOUT_START = 1300, + HAL_LL_I2C_MASTER_TIMEOUT_STOP, + HAL_LL_I2C_MASTER_TIMEOUT_WRITE, + HAL_LL_I2C_MASTER_TIMEOUT_READ, + HAL_LL_I2C_MASTER_ARBITRATION_LOST, + HAL_LL_I2C_MASTER_TIMEOUT_INIT +} hal_ll_i2c_master_timeout_t; + +/** + * @brief Enum containing predefined module standard speed values. + * + * Enum values: + * HAL_LL_I2C_MASTER_SPEED_STANDARD -- Speed set at 100K + * HAL_LL_I2C_MASTER_SPEED_FULL -- Speed set at 400K + * HAL_LL_I2C_MASTER_SPEED_FAST -- Speed set at 1M + */ +typedef enum +{ + HAL_LL_I2C_MASTER_SPEED_STANDARD = 0, + HAL_LL_I2C_MASTER_SPEED_FULL, + HAL_LL_I2C_MASTER_SPEED_FAST +} hal_ll_i2c_master_speed_t; + +// ------------------------------------------------------------------ VARIABLES +/*!< @brief I2C hardware specific info */ +static hal_ll_i2c_hw_specifics_map_t hal_ll_i2c_hw_specifics_map[] = +{ + #ifdef I2C_MODULE_1 + {HAL_LL_I2C1_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_1), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, + #endif + + #ifdef I2C_MODULE_2 + {HAL_LL_I2C2_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_2), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, + #endif + + #ifdef I2C_MODULE_3 + {HAL_LL_I2C3_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_3), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, + #endif + + #ifdef I2C_MODULE_4 + {HAL_LL_I2C4_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_4), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, + #endif + + + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, 0, 0} +}; + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_i2c_master_handle_register_t *low_level_handle; +static volatile hal_ll_i2c_hw_specifics_map_t *hal_ll_i2c_hw_specifics_map_local; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Check if pins are adequate. + * + * Checks scl and sda pins the user has passed with pre-defined + * pins in scl and sda maps. Take into consideration that module + * index numbers have to be the same for both pins. + * + * @param[in] scl - SCL pre-defined pin name. + * @param[in] sda - SDA pre-defined pin name. + * @param[in] *index_list - Index list address + * @return hal_ll_pin_name_t Module index based on pins. + * + * Returns pre-defined module index from pin maps, if pins + * are adequate. + */ +static hal_ll_pin_name_t hal_ll_i2c_master_check_pins( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_pin_id *index_list, hal_ll_i2c_master_handle_register_t *handle_map ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_i2c_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_i2c_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_i2c_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Get adequate I2C bit-rate value. + * + * Returns one of pre-defined bit-rate values, + * or the closest bit-rate based on bit_rate + * value passed to the function. + * + * @param[in] bit_rate - I2C bit rate. + * @return uint32_t Adequate bit-rate value. + * + * Returns adequate value to be latter written into bare metal register address. + * Take into consideration that this returns a predefined value. + * + * HAL_LL_I2C_MASTER_SPEED_100K -- 100Kbit/s + * HAL_LL_I2C_MASTER_SPEED_400K -- 400Kbit/s + * HAL_LL_I2C_MASTER_SPEED_1M -- 1Mbit/s + * HAL_LL_I2C_MASTER_SPEED_3M2 -- 3.2Mbit/s + */ +static uint32_t hal_ll_i2c_get_speed( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Enable clock for I2C1 module on hardware level. + * + * Initializes I2C1 module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] hal_ll_state - True/False -- Init/De-init + * + * @return None + */ +static inline void hal_ll_i2c1_set_clock( bool hal_ll_state ); + +/** + * @brief Enable clock for I2C2 module on hardware level. + * + * Initializes I2C2 module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] hal_ll_state - True/False -- Init/De-init + * + * @return None + */ +static inline void hal_ll_i2c2_set_clock( bool hal_ll_state ); + +/** + * @brief Enable clock for I2C3 module on hardware level. + * + * Initializes I2C3 module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] hal_ll_state - True/False -- Init/De-init + * + * @return None + */ +static inline void hal_ll_i2c3_set_clock( bool hal_ll_state ); + +/** + * @brief Enable clock for I2C4 module on hardware level. + * + * Initializes I2C4 module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] hal_ll_state - True/False -- Init/De-init + * + * @return None + */ +static inline void hal_ll_i2c4_set_clock( bool hal_ll_state ); + +/** + * @brief Enable clock for I2C module on hardware level. + * + * Initializes I2C module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_stat - True(enable clock)/False(disable clock). + * + * @return None + */ +static void hal_ll_i2c_master_set_clock( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Initialize I2C module on hardware level. + * + * Initializes I2C module on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] map - Object specific context handler. + * @return hal_ll_err_t Module specific return values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_hw_init( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * I2C SCL and SDA pins. + * + * @param[in] module_index I2C HW module index -- 0,1,2... + * @param[in] *index_list Array with SCL and SDA map index values + * and module number + * + * @return None + */ +static void hal_ll_i2c_master_map_pins( uint8_t module_index, hal_ll_i2c_pin_id *index_list ); + +/** + * @brief Sets I2C pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if I2C is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_state - Init/De-init + * + * @return None + */ +static void hal_ll_i2c_master_alternate_functions_set_state( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Full I2C module initialization procedure. + * + * Initializes I2C module on hardware level, based on beforehand + * set configuration and module handler. Sets adequate pin alternate functions. + * Initializes module clock. + * + * @param[in] map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Configure I2C module for data transfer. + * + * @param[in] hal_ll_hw_reg - I2C module base address. + * @param[in] config - I2C config bits. + * @return void None. + */ +static void hal_ll_i2c_master_configure_transfer( hal_ll_i2c_base_handle_t *hal_ll_hw_reg, uint32_t config ); + +/** + * @brief Reset value of I2C CR2 register. + * + * @param[in] hal_ll_hw_reg - I2C module base address. + * @returnl none + */ +static void hal_ll_i2c_master_reset_cr2( hal_ll_i2c_base_handle_t *hal_ll_hw_reg ); + +/** + * @brief Generates start signal on I2C bus. + * + * Generates a start signal on the I2C bus. + * + * @param[in] map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_master_start( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Generates stop signal on I2C bus. + * + * Generates a stop signal on the I2C bus. + * + * @param[in] map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_master_stop( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Perform a read on the I2C bus. + * + * Initializes I2C module on hardware level, if not initialized beforehand + * and continues to perform a read operation on the bus. + * + * @param[in] map - Object specific context handler. + * @param[in] readDatabuf - Pointer to data buffer. + * @param[in] lenReadData - Number of data to be read. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *read_data_buf, size_t len_read_data, hal_ll_i2c_master_end_mode_t mode ); + +/** + * @brief Perform a write on the I2C bus. + * + * Initializes I2C module on hardware level, if not initialized beforehand + * and continues to perform a write operation on the bus. + * + * @param[in] map - Object specific context handler. + * @param[in] writeDatabuf - Pointer to data buffer. + * @param[in] lenWriteData - Number of data to be written. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *write_data_buf, size_t len_write_data, hal_ll_i2c_master_end_mode_t mode ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_i2c_master_register_handle( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_master_handle_register_t *handle_map, uint8_t *hal_module_id ) { + + hal_ll_i2c_pin_id index_list[I2C_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + uint16_t pin_check_result; + + // Check if pins are valid + if ( (pin_check_result = hal_ll_i2c_master_check_pins( scl, sda, &index_list, handle_map )) == HAL_LL_PIN_NC ) { + return HAL_LL_I2C_MASTER_WRONG_PINS; + }; + + if ( (hal_ll_i2c_hw_specifics_map[pin_check_result].pins.pin_scl.pin_name != scl) || + (hal_ll_i2c_hw_specifics_map[pin_check_result].pins.pin_sda.pin_name != sda) ) + { + hal_ll_i2c_master_alternate_functions_set_state( &hal_ll_i2c_hw_specifics_map[ pin_check_result ], false ); + + hal_ll_i2c_master_map_pins( pin_check_result, &index_list ); + + hal_ll_i2c_master_alternate_functions_set_state( &hal_ll_i2c_hw_specifics_map[ pin_check_result ], true ); + + handle_map[pin_check_result].init_ll_state = false; + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[pin_check_result].hal_ll_i2c_master_handle = (handle_t *)&hal_ll_i2c_hw_specifics_map[pin_check_result].base; + + handle_map[pin_check_result].hal_ll_i2c_master_handle = (handle_t *)&hal_ll_module_state[pin_check_result].hal_ll_i2c_master_handle; + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_i2c( handle_t *handle ) { + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + hal_ll_i2c_master_handle_register_t *hal_handle = (hal_ll_i2c_master_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_i2c_hw_specifics_map_local->module_index; + + hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_local ); + + hal_ll_module_state[pin_check_result].hal_ll_i2c_master_handle = (handle_t *)&hal_ll_i2c_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_i2c_master_set_speed( handle_t *handle, uint32_t speed ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + low_level_handle->init_ll_state = false; + + hal_ll_i2c_hw_specifics_map_local->speed = speed; + + if ( hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_local ) != HAL_LL_I2C_MASTER_SUCCESS ) { + return HAL_LL_I2C_MASTER_TIMEOUT_INIT; + } + + low_level_handle->init_ll_state = true; + + return hal_ll_i2c_hw_specifics_map_local->speed; +} + +void hal_ll_i2c_master_set_timeout( handle_t *handle, uint16_t timeout ) { + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + if( hal_ll_i2c_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + hal_ll_i2c_hw_specifics_map_local->timeout = timeout; + } +} + +void hal_ll_i2c_master_set_slave_address( handle_t *handle, uint8_t addr ) { + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + if( hal_ll_i2c_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + hal_ll_i2c_hw_specifics_map_local->address = addr; + } +} + +hal_ll_err_t hal_ll_i2c_master_read( handle_t *handle, uint8_t *read_data_buf, size_t len_read_data ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + return hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_local, read_data_buf, len_read_data, HAL_LL_I2C_MASTER_END_MODE_STOP ); +} + +hal_ll_err_t hal_ll_i2c_master_write( handle_t *handle, uint8_t *write_data_buf, size_t len_write_data ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + return hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_local, write_data_buf, len_write_data, HAL_LL_I2C_MASTER_END_MODE_STOP ); +} + +hal_ll_err_t hal_ll_i2c_master_write_then_read( handle_t *handle, uint8_t *write_data_buf, size_t len_write_data, uint8_t *read_data_buf, size_t len_read_data ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + if( hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_local, write_data_buf, len_write_data, HAL_LL_I2C_MASTER_WRITE_THEN_READ ) != NULL ) { + return HAL_LL_I2C_MASTER_TIMEOUT_WRITE; + } + + /** + * @note Wait for drivers to set-up + * correctly. + **/ + #ifdef __TFT_RESISTIVE_TSC2003__ + Delay_22us(); + #endif + + if( hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_local, read_data_buf, len_read_data, HAL_LL_I2C_MASTER_WRITE_THEN_READ ) != NULL ) { + return HAL_LL_I2C_MASTER_TIMEOUT_READ; + } + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +void hal_ll_i2c_master_close( handle_t *handle ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + if( low_level_handle->hal_ll_i2c_master_handle != NULL ) { + low_level_handle->hal_ll_i2c_master_handle = NULL; + low_level_handle->hal_drv_i2c_master_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_i2c_hw_specifics_map_local->address = 0; + hal_ll_i2c_hw_specifics_map_local->timeout = HAL_LL_I2C_DEFAULT_PASS_COUNT; + hal_ll_i2c_hw_specifics_map_local->speed = HAL_LL_I2C_MASTER_SPEED_100K; + + hal_ll_i2c_master_set_clock(hal_ll_i2c_hw_specifics_map_local, true); + hal_ll_i2c_master_alternate_functions_set_state( hal_ll_i2c_hw_specifics_map_local, false ); + hal_ll_i2c_master_set_clock(hal_ll_i2c_hw_specifics_map_local, false); + + hal_ll_i2c_hw_specifics_map_local->pins.pin_scl.pin_name = HAL_LL_PIN_NC; + hal_ll_i2c_hw_specifics_map_local->pins.pin_sda.pin_name = HAL_LL_PIN_NC; + hal_ll_i2c_hw_specifics_map_local->pins.pin_scl.pin_af = 0; + hal_ll_i2c_hw_specifics_map_local->pins.pin_sda.pin_af = 0; + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static hal_ll_err_t hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *read_data_buf, size_t len_read_data, hal_ll_i2c_master_end_mode_t mode ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct(map->base); + uint16_t time_counter = map->timeout; + size_t transfer_counter = NULL; + uint8_t status = NULL; + + /** + * @note When R/W = 0, the input sample acquisition period starts + * on the falling edge of SCL once the C0 bit of the command + * byte has been latched, and ends when a Stop or + * repeated Start condition has been issued. + **/ + #ifdef __TFT_RESISTIVE_TSC2003__ + Delay_1ms(); + #endif + + hal_ll_i2c_master_configure_transfer ( map->base, + ( map->address << 1 & HAL_LL_I2C_CR2_SADD ) | + ( len_read_data << 16 & HAL_LL_I2C_CR2_NBYTES ) | + HAL_LL_I2C_CR2_RD_WRN | + HAL_LL_I2C_CR2_START + ); + + for ( transfer_counter; transfer_counter < len_read_data; transfer_counter++ ) { + while ( !( check_reg_bit( &( hal_ll_hw_reg->isr ), HAL_LL_I2C_RXNE_BIT ) ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_READ; + } + } + read_data_buf[ transfer_counter ] = hal_ll_hw_reg->rxdr; + } + + if ( ( mode == HAL_LL_I2C_MASTER_END_MODE_STOP ) || ( mode == HAL_LL_I2C_MASTER_WRITE_THEN_READ ) ) { + status = hal_ll_i2c_master_stop( map ); + } else { + status = hal_ll_i2c_master_start( map ); + } + + if( status != HAL_LL_I2C_MASTER_SUCCESS ) { + return status; + } + + hal_ll_i2c_master_reset_cr2( hal_ll_hw_reg ); + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static hal_ll_err_t hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *write_data_buf, size_t len_write_data, hal_ll_i2c_master_end_mode_t mode ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct(map->base); + uint16_t time_counter = map->timeout; + size_t transfer_counter = NULL; + uint8_t status = NULL; + + hal_ll_i2c_master_configure_transfer ( map->base, + ( map->address << 1 & HAL_LL_I2C_CR2_SADD ) | + ( len_write_data << 16 & HAL_LL_I2C_CR2_NBYTES ) | + !HAL_LL_I2C_CR2_RD_WRN | + HAL_LL_I2C_CR2_START + ); + + for ( transfer_counter; transfer_counter < len_write_data; transfer_counter++ ) + { + while ( !( check_reg_bit( &( hal_ll_hw_reg->isr ), HAL_LL_I2C_TXIS_BIT ) ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_WRITE; + } + } + hal_ll_hw_reg->txdr = write_data_buf[ transfer_counter ]; + } + + time_counter = map->timeout; + while ( !( check_reg_bit( &( hal_ll_hw_reg->isr ), HAL_LL_I2C_TXE_BIT ) ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_WRITE; + } + } + + if ( mode == HAL_LL_I2C_MASTER_END_MODE_STOP ) + { + hal_ll_i2c_master_stop( map ); + } + + hal_ll_i2c_master_reset_cr2( hal_ll_hw_reg ); + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static void hal_ll_i2c_master_configure_transfer( hal_ll_i2c_base_handle_t *hal_ll_hw_reg, uint32_t config ) { + uint32_t reg = 0; + + // Clear last set slave address + hal_ll_hw_reg->cr2 &= ~HAL_LL_I2C_CR2_SADD; + + reg = hal_ll_hw_reg->cr2; + reg &= ~( uint32_t )( + ( HAL_LL_I2C_CR2_SADD ) | + ( HAL_LL_I2C_CR2_NBYTES ) | + ( HAL_LL_I2C_CR2_RELOAD ) | + ( HAL_LL_I2C_CR2_AUTOEND ) | + ( HAL_LL_I2C_CR2_RD_WRN ) | + ( HAL_LL_I2C_CR2_START ) | + ( HAL_LL_I2C_CR2_STOP ) + ); + + reg |= config; + hal_ll_hw_reg->cr2 = reg; +} + +static void hal_ll_i2c_master_reset_cr2( hal_ll_i2c_base_handle_t *hal_ll_hw_reg ) { + hal_ll_hw_reg->cr2 &= ~( uint32_t ) + ( + HAL_LL_I2C_SADD_MASK | + HAL_LL_I2C_HEAD10R_MASK | + HAL_LL_I2C_NBYTES_MASK | + HAL_LL_I2C_RELOAD_MASK | + HAL_LL_I2C_RD_WRN_MASK + ); +} + +static hal_ll_err_t hal_ll_i2c_master_start( hal_ll_i2c_hw_specifics_map_t *map ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct(map->base); + uint16_t loop_index = HAL_LL_I2C_LOOP_INDEX; + + set_reg_bit( &(hal_ll_hw_reg->cr2), HAL_LL_I2C_CR2_START_BIT ); + + if ( check_reg_bit( &( hal_ll_hw_reg->isr ), HAL_LL_I2C_ARLO_BIT ) ) + return HAL_LL_I2C_MASTER_ARBITRATION_LOST; + + while ( loop_index-- ) + assembly(nop); + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static hal_ll_err_t hal_ll_i2c_master_stop( hal_ll_i2c_hw_specifics_map_t *map ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = ( hal_ll_i2c_base_handle_t* )map->base; + uint16_t time_counter = map->timeout; + uint32_t loop_index = HAL_LL_I2C_LOOP_INDEX; + + set_reg_bit( &(hal_ll_hw_reg->cr2), HAL_LL_I2C_CR2_STOP_BIT ); + + while ( !( hal_ll_hw_reg->isr & HAL_LL_I2C_ISR_STOPF_BIT ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_STOP; + } + } + + if ( map->timeout < HAL_LL_I2C_LOOP_INDEX ) { + while ( loop_index-- ) + assembly(nop); + } + + hal_ll_hw_reg->isr &= ~HAL_LL_I2C_ISR_STOPF_BIT; + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static hal_ll_pin_name_t hal_ll_i2c_master_check_pins( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_pin_id *index_list, hal_ll_i2c_master_handle_register_t *handle_map ) { + static const uint16_t scl_map_size = ( sizeof( hal_ll_i2c_scl_map ) / sizeof( hal_ll_i2c_pin_map_t ) ); + static const uint16_t sda_map_size = ( sizeof( hal_ll_i2c_sda_map ) / sizeof( hal_ll_i2c_pin_map_t ) ); + uint8_t hal_ll_module_id = 0; + uint8_t index_counter = 0; + uint16_t scl_index; + uint16_t sda_index; + + if ( (HAL_LL_PIN_NC == scl) || (HAL_LL_PIN_NC == sda) ) { + return HAL_LL_PIN_NC; + } + + for ( scl_index = 0; scl_index < scl_map_size; scl_index++ ) { + if ( hal_ll_i2c_scl_map[ scl_index ].pin == scl ) { + for ( sda_index = 0; sda_index < sda_map_size; sda_index++ ) { + if ( hal_ll_i2c_sda_map[ sda_index ].pin == sda ) { + if ( hal_ll_i2c_scl_map[ scl_index ].module_index == hal_ll_i2c_sda_map[ sda_index ].module_index ) { + // Get module number + hal_ll_module_id = hal_ll_i2c_scl_map[ scl_index ].module_index; + // Map pin names + index_list[hal_ll_module_id].pin_scl = scl_index; + index_list[hal_ll_module_id].pin_sda = sda_index; + + // Check if module is taken + if ( NULL == handle_map[ hal_ll_module_id ].hal_drv_i2c_master_handle ) { + return hal_ll_module_id; + } else if ( I2C_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static hal_ll_i2c_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof(hal_ll_i2c_master_handle_register_t)); + static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof(hal_ll_i2c_master_handle_register_t)); + + while( hal_ll_module_count-- ) { + if (hal_ll_i2c_get_base_from_hal_handle == hal_ll_i2c_hw_specifics_map[hal_ll_module_count].base) { + return &hal_ll_i2c_hw_specifics_map[hal_ll_module_count]; + } + } + + return &hal_ll_i2c_hw_specifics_map[hal_ll_module_error]; +} + +static void hal_ll_i2c_master_set_clock( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ) { + switch ( map->module_index ) + { + #if defined(I2C_MODULE_1) + case ( hal_ll_i2c_module_num(I2C_MODULE_1) ): + hal_ll_i2c1_set_clock( hal_ll_state ); + break; + #endif + + #if defined(I2C_MODULE_2) + case ( hal_ll_i2c_module_num(I2C_MODULE_2) ): + hal_ll_i2c2_set_clock( hal_ll_state ); + break; + #endif + + #if defined(I2C_MODULE_3) + case ( hal_ll_i2c_module_num(I2C_MODULE_3) ): + hal_ll_i2c3_set_clock( hal_ll_state ); + break; + #endif + + #if defined(I2C_MODULE_4) + case ( hal_ll_i2c_module_num(I2C_MODULE_4) ): + hal_ll_i2c4_set_clock( hal_ll_state ); + break; + #endif + + + default: + break; + } +} + +static void hal_ll_i2c_master_map_pins( uint8_t module_index, hal_ll_i2c_pin_id *index_list ) { + // Map new pins + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_scl.pin_name = hal_ll_i2c_scl_map[ index_list[module_index].pin_scl ].pin; + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_sda.pin_name = hal_ll_i2c_sda_map[ index_list[module_index].pin_sda ].pin; + // SCL and SDA could have different alternate function settings, hence save both AF values + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_scl.pin_af = hal_ll_i2c_scl_map[ index_list[module_index].pin_scl ].af; + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_sda.pin_af = hal_ll_i2c_sda_map[ index_list[module_index].pin_sda ].af; +} + +static void hal_ll_i2c_master_alternate_functions_set_state( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ) { + module_struct module; + + if( (map->pins.pin_scl.pin_name != HAL_LL_PIN_NC) && (map->pins.pin_sda.pin_name != HAL_LL_PIN_NC) ) { + module.pins[0] = VALUE( map->pins.pin_scl.pin_name, map->pins.pin_scl.pin_af ); + module.pins[1] = VALUE( map->pins.pin_sda.pin_name, map->pins.pin_sda.pin_af ); + module.pins[2] = GPIO_MODULE_STRUCT_END; + + module.configs[0] = HAL_LL_I2C_AF_CONFIG; + module.configs[1] = HAL_LL_I2C_AF_CONFIG; + module.configs[2] = GPIO_MODULE_STRUCT_END; + + hal_ll_gpio_module_struct_init( &module, hal_ll_state ); + } +} + +static uint32_t hal_ll_i2c_get_speed( hal_ll_i2c_hw_specifics_map_t *map ) { + if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_FAST ) { + if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_STANDARD ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_100K; + return HAL_LL_I2C_100K; + } else if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_FULL ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_400K; + return HAL_LL_I2C_400K; + } else if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_FAST ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_1M; + return HAL_LL_I2C_1M; + } else { + map->speed = HAL_LL_I2C_MASTER_SPEED_100K; + return HAL_LL_I2C_100K; + } + } else { + if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_100K ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_100K; + return HAL_LL_I2C_100K; + } else if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_400K ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_400K; + return HAL_LL_I2C_400K; + } else if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_1M ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_1M; + return HAL_LL_I2C_1M; + } else { + map->speed = HAL_LL_I2C_MASTER_SPEED_1M; + return HAL_LL_I2C_1M; + } + } +} +static inline void hal_ll_i2c1_set_clock( bool hal_ll_state ) { + if ( hal_ll_state ) { + set_reg_bit( _RCC_APB1ENR1, HAL_LL_I2C1EN_BIT ); + set_reg_bit( _RCC_CCIPR, HAL_LL_I2C1SEL1_BIT ); + } else { + clear_reg_bit( _RCC_APB1ENR1, HAL_LL_I2C1EN_BIT ); + clear_reg_bit( _RCC_CCIPR, HAL_LL_I2C1SEL1_BIT ); + } +} + + +static inline void hal_ll_i2c2_set_clock( bool hal_ll_state ) { + if ( hal_ll_state ) { + set_reg_bit( _RCC_APB1ENR1, HAL_LL_I2C2EN_BIT ); + set_reg_bit( _RCC_CCIPR, HAL_LL_I2C2SEL1_BIT ); + } else { + clear_reg_bit( _RCC_APB1ENR1, HAL_LL_I2C2EN_BIT ); + clear_reg_bit( _RCC_CCIPR, HAL_LL_I2C2SEL1_BIT ); + } +} + + +static inline void hal_ll_i2c3_set_clock( bool hal_ll_state ) { + if ( hal_ll_state ) { + set_reg_bit( _RCC_APB1ENR1, HAL_LL_I2C3EN_BIT ); + set_reg_bit( _RCC_CCIPR, HAL_LL_I2C3SEL1_BIT ); + } else { + clear_reg_bit( _RCC_APB1ENR1, HAL_LL_I2C3EN_BIT ); + clear_reg_bit( _RCC_CCIPR, HAL_LL_I2C3SEL1_BIT ); + } +} + + +static inline void hal_ll_i2c4_set_clock( bool hal_ll_state ) { + if ( hal_ll_state ) { + set_reg_bit( _RCC_APB1ENR2, HAL_LL_I2C4EN_BIT ); + set_reg_bit( _RCC_CCIPR2, HAL_LL_I2C4SEL1_BIT ); + } else { + clear_reg_bit( _RCC_APB1ENR2, HAL_LL_I2C4EN_BIT ); + clear_reg_bit( _RCC_CCIPR2, HAL_LL_I2C4SEL1_BIT ); + } +} + + + +static hal_ll_err_t hal_ll_i2c_hw_init( hal_ll_i2c_hw_specifics_map_t *map ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct(map->base); + uint16_t time_counter = map->timeout; + + clear_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_I2C_PE_BIT ); + while ( check_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_I2C_PE_BIT ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_INIT; + } + } + + hal_ll_hw_reg->cr1 &= HAL_LL_I2C_FILTERS_OFF; + + hal_ll_hw_reg->timingr = hal_ll_i2c_get_speed( map ); + + hal_ll_hw_reg->cr1 |= HAL_LL_I2C_CR1_RXTX_INT; + + set_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_I2C_PE_BIT ); + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static hal_ll_err_t hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_t *map ) { + hal_ll_i2c_master_set_clock( map, true ); + + return hal_ll_i2c_hw_init( map ); +} +// ------------------------------------------------------------------------- END + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_85/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_85/CMakeLists.cmake new file mode 100644 index 000000000..7ab6792dd --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_85/CMakeLists.cmake @@ -0,0 +1,9 @@ +if(${MCU_NAME} MATCHES "^STM32G474CB$|^STM32G474MB$|^STM32G474RB$|^STM32G474VB$|^STM32G474QB$|^STM32G474PB$|^STM32G474CC$|^STM32G474MC$|^STM32G474RC$|^STM32G474VC$|^STM32G474QC$|^STM32G474PC$|^STM32G474CE$|^STM32G474ME$|^STM32G474RE$|^STM32G474VE$|^STM32G474QE$|^STM32G474PE$") + set(i2c_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_i2c_master.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_85") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_85") + list(APPEND hal_ll_def_list "STM32G4xx") + list(APPEND hal_ll_def_list "STM32G47xx") + list(APPEND hal_ll_def_list "STM32G474xx") + set(i2c_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/i2c/hal_ll_i2c_pin_map/implementations/doc_ds_85") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_85/hal_ll_i2c_master.c b/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_85/hal_ll_i2c_master.c new file mode 100644 index 000000000..2d9b5f410 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_85/hal_ll_i2c_master.c @@ -0,0 +1,1015 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_i2c_master.c + * @brief I2C master HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_rcc.h" +#include "hal_ll_gpio.h" +#include "hal_ll_i2c_master.h" +#include "hal_ll_i2c_pin_map.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_i2c_master_handle_register_t hal_ll_module_state[I2C_MODULE_COUNT] = { (handle_t *)NULL, (handle_t *)NULL, false }; + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_i2c_get_module_state_address ((hal_ll_i2c_master_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_i2c_get_handle (hal_ll_i2c_master_handle_register_t *)hal_ll_i2c_get_module_state_address->hal_ll_i2c_master_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_i2c_get_base_struct(_handle) ((hal_ll_i2c_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_i2c_get_base_from_hal_handle ((hal_ll_i2c_hw_specifics_map_t *)((hal_ll_i2c_master_handle_register_t *)\ + (((hal_ll_i2c_master_handle_register_t *)(handle))->hal_ll_i2c_master_handle))->hal_ll_i2c_master_handle)->base + +/*!< @brief Default I2C bit-rate if no speed is set */ +#define HAL_LL_I2C_MASTER_SPEED_100K 100000UL +#define HAL_LL_I2C_MASTER_SPEED_400K 400000UL +#define HAL_LL_I2C_MASTER_SPEED_1M 1000000UL + +/*!< @brief Default pass count value upon reset */ +#define HAL_LL_I2C_DEFAULT_PASS_COUNT 0xFFFFU + +/*!< @brief Macro used for timeout */ +#define HAL_LL_I2C_LOOP_INDEX 10000U + +/*!< @brief Macros defining register bit location */ +#define HAL_LL_I2C1EN_BIT 21 + +#define HAL_LL_I2C2EN_BIT 22 + +#define HAL_LL_I2C3EN_BIT 30 + +#define HAL_LL_I2C4EN_BIT 1 + +#define HAL_LL_I2C1SEL0_BIT 12 + +#define HAL_LL_I2C1SEL1_BIT 13 + +#define HAL_LL_I2C2SEL0_BIT 14 + +#define HAL_LL_I2C2SEL1_BIT 15 + +#define HAL_LL_I2C3SEL0_BIT 16 + +#define HAL_LL_I2C3SEL1_BIT 17 + +#define HAL_LL_I2C4SEL0_BIT 0 + +#define HAL_LL_I2C4SEL1_BIT 1 + + + + +#define HAL_LL_I2C_100K 0x30420F13 //?????????????????? +#define HAL_LL_I2C_400K 0x10320309 //?????????????????? +#define HAL_LL_I2C_1M 0x00200204 //?????????????????? + +#define HAL_LL_I2C_PE_BIT 0 +#define HAL_LL_I2C_CR2_STOP_BIT 14 +#define HAL_LL_I2C_CR2_START_BIT 13 +#define HAL_LL_I2C_ISR_STOPF_BIT 5 +#define HAL_LL_I2C_ISR_BUSY_BIT 15 +#define HAL_LL_I2C_ARLO_BIT 9 +#define HAL_LL_I2C_RXNE_BIT 2 +#define HAL_LL_I2C_TXIS_BIT 1 +#define HAL_LL_I2C_TXE_BIT 0 + +/*!< @brief Macros defining register bit masks */ +#define HAL_LL_I2C_CR1_RXTX_INT 0x6 +#define HAL_LL_I2C_CR2_STOP 0x4000UL +#define HAL_LL_I2C_CR2_START 0x2000U +#define HAL_LL_I2C_CR2_SADD 0x3FFU +#define HAL_LL_I2C_CR2_NBYTES 0xFF0000UL +#define HAL_LL_I2C_CR2_RD_WRN 0x400U +#define HAL_LL_I2C_CR2_RELOAD 0x1000000UL +#define HAL_LL_I2C_CR2_AUTOEND 0x2000000UL +#define HAL_LL_I2C_FILTERS_OFF 0xFFFFE0FFUL +#define HAL_LL_I2C_SADD_MASK 0x3FFUL +#define HAL_LL_I2C_HEAD10R_MASK 0x1000UL +#define HAL_LL_I2C_NBYTES_MASK 0xFF0000UL +#define HAL_LL_I2C_RELOAD_MASK 0x1000000UL +#define HAL_LL_I2C_RD_WRN_MASK 0x400UL + +/*!< @brief Macros used for module pin checking */ +#define HAL_LL_I2C_SCL_PIN 0 +#define HAL_LL_I2C_SDA_PIN 1 +#define HAL_LL_I2C_MODULE_PIN_COUNT 2 + +/*!< @brief Macro used for setting pin alternate functions */ +#define HAL_LL_I2C_AF_CONFIG (GPIO_CFG_MODE_ALT_FUNCTION | GPIO_CFG_SPEED_HIGH | GPIO_CFG_OTYPE_OD) + +// -------------------------------------------------------------- PRIVATE TYPES +/*!< @brief I2C register structure */ +typedef struct +{ + hal_ll_base_addr_t cr1; + hal_ll_base_addr_t cr2; + hal_ll_base_addr_t oar1; + hal_ll_base_addr_t oar2; + hal_ll_base_addr_t timingr; + hal_ll_base_addr_t timeoutr; + hal_ll_base_addr_t isr; + hal_ll_base_addr_t icr; + hal_ll_base_addr_t pecr; + hal_ll_base_addr_t rxdr; + hal_ll_base_addr_t txdr; + +} hal_ll_i2c_base_handle_t; + +/*!< @brief I2C hw specific structure */ +typedef struct +{ + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + hal_ll_i2c_pins_t pins; + uint32_t speed; + uint8_t address; + uint16_t timeout; +} hal_ll_i2c_hw_specifics_map_t; + +/*!< @brief I2C hw specific module values */ +typedef struct +{ + uint16_t pin_scl; + uint16_t pin_sda; +} hal_ll_i2c_pin_id; + +/*!< @brief I2C hw specific error values */ +typedef enum +{ + HAL_LL_I2C_MASTER_SUCCESS = 0, + HAL_LL_I2C_MASTER_WRONG_PINS, + HAL_LL_I2C_MASTER_MODULE_ERROR, + + HAL_LL_I2C_MASTER_ERROR = (-1) +} hal_ll_i2c_master_err_t; + +/*!< @brief I2C end mode selection values */ +typedef enum +{ + HAL_LL_I2C_MASTER_END_MODE_RESTART = 0, + HAL_LL_I2C_MASTER_END_MODE_STOP, + HAL_LL_I2C_MASTER_WRITE_THEN_READ +} hal_ll_i2c_master_end_mode_t; + +/*!< @brief I2C timeout error values */ +typedef enum +{ + HAL_LL_I2C_MASTER_TIMEOUT_START = 1300, + HAL_LL_I2C_MASTER_TIMEOUT_STOP, + HAL_LL_I2C_MASTER_TIMEOUT_WRITE, + HAL_LL_I2C_MASTER_TIMEOUT_READ, + HAL_LL_I2C_MASTER_ARBITRATION_LOST, + HAL_LL_I2C_MASTER_TIMEOUT_INIT +} hal_ll_i2c_master_timeout_t; + +/** + * @brief Enum containing predefined module standard speed values. + * + * Enum values: + * HAL_LL_I2C_MASTER_SPEED_STANDARD -- Speed set at 100K + * HAL_LL_I2C_MASTER_SPEED_FULL -- Speed set at 400K + * HAL_LL_I2C_MASTER_SPEED_FAST -- Speed set at 1M + */ +typedef enum +{ + HAL_LL_I2C_MASTER_SPEED_STANDARD = 0, + HAL_LL_I2C_MASTER_SPEED_FULL, + HAL_LL_I2C_MASTER_SPEED_FAST +} hal_ll_i2c_master_speed_t; + +// ------------------------------------------------------------------ VARIABLES +/*!< @brief I2C hardware specific info */ +static hal_ll_i2c_hw_specifics_map_t hal_ll_i2c_hw_specifics_map[] = +{ + #ifdef I2C_MODULE_1 + {HAL_LL_I2C1_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_1), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, + #endif + + #ifdef I2C_MODULE_2 + {HAL_LL_I2C2_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_2), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, + #endif + + #ifdef I2C_MODULE_3 + {HAL_LL_I2C3_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_3), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, + #endif + + #ifdef I2C_MODULE_4 + {HAL_LL_I2C4_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_4), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, + #endif + + + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, 0, 0} +}; + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_i2c_master_handle_register_t *low_level_handle; +static volatile hal_ll_i2c_hw_specifics_map_t *hal_ll_i2c_hw_specifics_map_local; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Check if pins are adequate. + * + * Checks scl and sda pins the user has passed with pre-defined + * pins in scl and sda maps. Take into consideration that module + * index numbers have to be the same for both pins. + * + * @param[in] scl - SCL pre-defined pin name. + * @param[in] sda - SDA pre-defined pin name. + * @param[in] *index_list - Index list address + * @return hal_ll_pin_name_t Module index based on pins. + * + * Returns pre-defined module index from pin maps, if pins + * are adequate. + */ +static hal_ll_pin_name_t hal_ll_i2c_master_check_pins( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_pin_id *index_list, hal_ll_i2c_master_handle_register_t *handle_map ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_i2c_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_i2c_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_i2c_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Get adequate I2C bit-rate value. + * + * Returns one of pre-defined bit-rate values, + * or the closest bit-rate based on bit_rate + * value passed to the function. + * + * @param[in] bit_rate - I2C bit rate. + * @return uint32_t Adequate bit-rate value. + * + * Returns adequate value to be latter written into bare metal register address. + * Take into consideration that this returns a predefined value. + * + * HAL_LL_I2C_MASTER_SPEED_100K -- 100Kbit/s + * HAL_LL_I2C_MASTER_SPEED_400K -- 400Kbit/s + * HAL_LL_I2C_MASTER_SPEED_1M -- 1Mbit/s + * HAL_LL_I2C_MASTER_SPEED_3M2 -- 3.2Mbit/s + */ +static uint32_t hal_ll_i2c_get_speed( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Enable clock for I2C1 module on hardware level. + * + * Initializes I2C1 module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] hal_ll_state - True/False -- Init/De-init + * + * @return None + */ +static inline void hal_ll_i2c1_set_clock( bool hal_ll_state ); + +/** + * @brief Enable clock for I2C2 module on hardware level. + * + * Initializes I2C2 module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] hal_ll_state - True/False -- Init/De-init + * + * @return None + */ +static inline void hal_ll_i2c2_set_clock( bool hal_ll_state ); + +/** + * @brief Enable clock for I2C3 module on hardware level. + * + * Initializes I2C3 module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] hal_ll_state - True/False -- Init/De-init + * + * @return None + */ +static inline void hal_ll_i2c3_set_clock( bool hal_ll_state ); + +/** + * @brief Enable clock for I2C4 module on hardware level. + * + * Initializes I2C4 module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] hal_ll_state - True/False -- Init/De-init + * + * @return None + */ +static inline void hal_ll_i2c4_set_clock( bool hal_ll_state ); + +/** + * @brief Enable clock for I2C module on hardware level. + * + * Initializes I2C module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_stat - True(enable clock)/False(disable clock). + * + * @return None + */ +static void hal_ll_i2c_master_set_clock( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Initialize I2C module on hardware level. + * + * Initializes I2C module on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] map - Object specific context handler. + * @return hal_ll_err_t Module specific return values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_hw_init( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * I2C SCL and SDA pins. + * + * @param[in] module_index I2C HW module index -- 0,1,2... + * @param[in] *index_list Array with SCL and SDA map index values + * and module number + * + * @return None + */ +static void hal_ll_i2c_master_map_pins( uint8_t module_index, hal_ll_i2c_pin_id *index_list ); + +/** + * @brief Sets I2C pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if I2C is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_state - Init/De-init + * + * @return None + */ +static void hal_ll_i2c_master_alternate_functions_set_state( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Full I2C module initialization procedure. + * + * Initializes I2C module on hardware level, based on beforehand + * set configuration and module handler. Sets adequate pin alternate functions. + * Initializes module clock. + * + * @param[in] map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Configure I2C module for data transfer. + * + * @param[in] hal_ll_hw_reg - I2C module base address. + * @param[in] config - I2C config bits. + * @return void None. + */ +static void hal_ll_i2c_master_configure_transfer( hal_ll_i2c_base_handle_t *hal_ll_hw_reg, uint32_t config ); + +/** + * @brief Reset value of I2C CR2 register. + * + * @param[in] hal_ll_hw_reg - I2C module base address. + * @returnl none + */ +static void hal_ll_i2c_master_reset_cr2( hal_ll_i2c_base_handle_t *hal_ll_hw_reg ); + +/** + * @brief Generates start signal on I2C bus. + * + * Generates a start signal on the I2C bus. + * + * @param[in] map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_master_start( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Generates stop signal on I2C bus. + * + * Generates a stop signal on the I2C bus. + * + * @param[in] map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_master_stop( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Perform a read on the I2C bus. + * + * Initializes I2C module on hardware level, if not initialized beforehand + * and continues to perform a read operation on the bus. + * + * @param[in] map - Object specific context handler. + * @param[in] readDatabuf - Pointer to data buffer. + * @param[in] lenReadData - Number of data to be read. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *read_data_buf, size_t len_read_data, hal_ll_i2c_master_end_mode_t mode ); + +/** + * @brief Perform a write on the I2C bus. + * + * Initializes I2C module on hardware level, if not initialized beforehand + * and continues to perform a write operation on the bus. + * + * @param[in] map - Object specific context handler. + * @param[in] writeDatabuf - Pointer to data buffer. + * @param[in] lenWriteData - Number of data to be written. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *write_data_buf, size_t len_write_data, hal_ll_i2c_master_end_mode_t mode ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_i2c_master_register_handle( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_master_handle_register_t *handle_map, uint8_t *hal_module_id ) { + + hal_ll_i2c_pin_id index_list[I2C_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + uint16_t pin_check_result; + + // Check if pins are valid + if ( (pin_check_result = hal_ll_i2c_master_check_pins( scl, sda, &index_list, handle_map )) == HAL_LL_PIN_NC ) { + return HAL_LL_I2C_MASTER_WRONG_PINS; + }; + + if ( (hal_ll_i2c_hw_specifics_map[pin_check_result].pins.pin_scl.pin_name != scl) || + (hal_ll_i2c_hw_specifics_map[pin_check_result].pins.pin_sda.pin_name != sda) ) + { + hal_ll_i2c_master_alternate_functions_set_state( &hal_ll_i2c_hw_specifics_map[ pin_check_result ], false ); + + hal_ll_i2c_master_map_pins( pin_check_result, &index_list ); + + hal_ll_i2c_master_alternate_functions_set_state( &hal_ll_i2c_hw_specifics_map[ pin_check_result ], true ); + + handle_map[pin_check_result].init_ll_state = false; + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[pin_check_result].hal_ll_i2c_master_handle = (handle_t *)&hal_ll_i2c_hw_specifics_map[pin_check_result].base; + + handle_map[pin_check_result].hal_ll_i2c_master_handle = (handle_t *)&hal_ll_module_state[pin_check_result].hal_ll_i2c_master_handle; + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_i2c( handle_t *handle ) { + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + hal_ll_i2c_master_handle_register_t *hal_handle = (hal_ll_i2c_master_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_i2c_hw_specifics_map_local->module_index; + + hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_local ); + + hal_ll_module_state[pin_check_result].hal_ll_i2c_master_handle = (handle_t *)&hal_ll_i2c_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_i2c_master_set_speed( handle_t *handle, uint32_t speed ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + low_level_handle->init_ll_state = false; + + hal_ll_i2c_hw_specifics_map_local->speed = speed; + + if ( hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_local ) != HAL_LL_I2C_MASTER_SUCCESS ) { + return HAL_LL_I2C_MASTER_TIMEOUT_INIT; + } + + low_level_handle->init_ll_state = true; + + return hal_ll_i2c_hw_specifics_map_local->speed; +} + +void hal_ll_i2c_master_set_timeout( handle_t *handle, uint16_t timeout ) { + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + if( hal_ll_i2c_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + hal_ll_i2c_hw_specifics_map_local->timeout = timeout; + } +} + +void hal_ll_i2c_master_set_slave_address( handle_t *handle, uint8_t addr ) { + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + if( hal_ll_i2c_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + hal_ll_i2c_hw_specifics_map_local->address = addr; + } +} + +hal_ll_err_t hal_ll_i2c_master_read( handle_t *handle, uint8_t *read_data_buf, size_t len_read_data ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + return hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_local, read_data_buf, len_read_data, HAL_LL_I2C_MASTER_END_MODE_STOP ); +} + +hal_ll_err_t hal_ll_i2c_master_write( handle_t *handle, uint8_t *write_data_buf, size_t len_write_data ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + return hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_local, write_data_buf, len_write_data, HAL_LL_I2C_MASTER_END_MODE_STOP ); +} + +hal_ll_err_t hal_ll_i2c_master_write_then_read( handle_t *handle, uint8_t *write_data_buf, size_t len_write_data, uint8_t *read_data_buf, size_t len_read_data ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + if( hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_local, write_data_buf, len_write_data, HAL_LL_I2C_MASTER_WRITE_THEN_READ ) != NULL ) { + return HAL_LL_I2C_MASTER_TIMEOUT_WRITE; + } + + /** + * @note Wait for drivers to set-up + * correctly. + **/ + #ifdef __TFT_RESISTIVE_TSC2003__ + Delay_22us(); + #endif + + if( hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_local, read_data_buf, len_read_data, HAL_LL_I2C_MASTER_WRITE_THEN_READ ) != NULL ) { + return HAL_LL_I2C_MASTER_TIMEOUT_READ; + } + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +void hal_ll_i2c_master_close( handle_t *handle ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + if( low_level_handle->hal_ll_i2c_master_handle != NULL ) { + low_level_handle->hal_ll_i2c_master_handle = NULL; + low_level_handle->hal_drv_i2c_master_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_i2c_hw_specifics_map_local->address = 0; + hal_ll_i2c_hw_specifics_map_local->timeout = HAL_LL_I2C_DEFAULT_PASS_COUNT; + hal_ll_i2c_hw_specifics_map_local->speed = HAL_LL_I2C_MASTER_SPEED_100K; + + hal_ll_i2c_master_set_clock(hal_ll_i2c_hw_specifics_map_local, true); + hal_ll_i2c_master_alternate_functions_set_state( hal_ll_i2c_hw_specifics_map_local, false ); + hal_ll_i2c_master_set_clock(hal_ll_i2c_hw_specifics_map_local, false); + + hal_ll_i2c_hw_specifics_map_local->pins.pin_scl.pin_name = HAL_LL_PIN_NC; + hal_ll_i2c_hw_specifics_map_local->pins.pin_sda.pin_name = HAL_LL_PIN_NC; + hal_ll_i2c_hw_specifics_map_local->pins.pin_scl.pin_af = 0; + hal_ll_i2c_hw_specifics_map_local->pins.pin_sda.pin_af = 0; + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static hal_ll_err_t hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *read_data_buf, size_t len_read_data, hal_ll_i2c_master_end_mode_t mode ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct(map->base); + uint16_t time_counter = map->timeout; + size_t transfer_counter = NULL; + uint8_t status = NULL; + + /** + * @note When R/W = 0, the input sample acquisition period starts + * on the falling edge of SCL once the C0 bit of the command + * byte has been latched, and ends when a Stop or + * repeated Start condition has been issued. + **/ + #ifdef __TFT_RESISTIVE_TSC2003__ + Delay_1ms(); + #endif + + hal_ll_i2c_master_configure_transfer ( map->base, + ( map->address << 1 & HAL_LL_I2C_CR2_SADD ) | + ( len_read_data << 16 & HAL_LL_I2C_CR2_NBYTES ) | + HAL_LL_I2C_CR2_RD_WRN | + HAL_LL_I2C_CR2_START + ); + + for ( transfer_counter; transfer_counter < len_read_data; transfer_counter++ ) { + while ( !( check_reg_bit( &( hal_ll_hw_reg->isr ), HAL_LL_I2C_RXNE_BIT ) ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_READ; + } + } + read_data_buf[ transfer_counter ] = hal_ll_hw_reg->rxdr; + } + + if ( ( mode == HAL_LL_I2C_MASTER_END_MODE_STOP ) || ( mode == HAL_LL_I2C_MASTER_WRITE_THEN_READ ) ) { + status = hal_ll_i2c_master_stop( map ); + } else { + status = hal_ll_i2c_master_start( map ); + } + + if( status != HAL_LL_I2C_MASTER_SUCCESS ) { + return status; + } + + hal_ll_i2c_master_reset_cr2( hal_ll_hw_reg ); + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static hal_ll_err_t hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *write_data_buf, size_t len_write_data, hal_ll_i2c_master_end_mode_t mode ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct(map->base); + uint16_t time_counter = map->timeout; + size_t transfer_counter = NULL; + uint8_t status = NULL; + + hal_ll_i2c_master_configure_transfer ( map->base, + ( map->address << 1 & HAL_LL_I2C_CR2_SADD ) | + ( len_write_data << 16 & HAL_LL_I2C_CR2_NBYTES ) | + !HAL_LL_I2C_CR2_RD_WRN | + HAL_LL_I2C_CR2_START + ); + + for ( transfer_counter; transfer_counter < len_write_data; transfer_counter++ ) + { + while ( !( check_reg_bit( &( hal_ll_hw_reg->isr ), HAL_LL_I2C_TXIS_BIT ) ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_WRITE; + } + } + hal_ll_hw_reg->txdr = write_data_buf[ transfer_counter ]; + } + + time_counter = map->timeout; + while ( !( check_reg_bit( &( hal_ll_hw_reg->isr ), HAL_LL_I2C_TXE_BIT ) ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_WRITE; + } + } + + if ( mode == HAL_LL_I2C_MASTER_END_MODE_STOP ) + { + hal_ll_i2c_master_stop( map ); + } + + hal_ll_i2c_master_reset_cr2( hal_ll_hw_reg ); + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static void hal_ll_i2c_master_configure_transfer( hal_ll_i2c_base_handle_t *hal_ll_hw_reg, uint32_t config ) { + uint32_t reg = 0; + + // Clear last set slave address + hal_ll_hw_reg->cr2 &= ~HAL_LL_I2C_CR2_SADD; + + reg = hal_ll_hw_reg->cr2; + reg &= ~( uint32_t )( + ( HAL_LL_I2C_CR2_SADD ) | + ( HAL_LL_I2C_CR2_NBYTES ) | + ( HAL_LL_I2C_CR2_RELOAD ) | + ( HAL_LL_I2C_CR2_AUTOEND ) | + ( HAL_LL_I2C_CR2_RD_WRN ) | + ( HAL_LL_I2C_CR2_START ) | + ( HAL_LL_I2C_CR2_STOP ) + ); + + reg |= config; + hal_ll_hw_reg->cr2 = reg; +} + +static void hal_ll_i2c_master_reset_cr2( hal_ll_i2c_base_handle_t *hal_ll_hw_reg ) { + hal_ll_hw_reg->cr2 &= ~( uint32_t ) + ( + HAL_LL_I2C_SADD_MASK | + HAL_LL_I2C_HEAD10R_MASK | + HAL_LL_I2C_NBYTES_MASK | + HAL_LL_I2C_RELOAD_MASK | + HAL_LL_I2C_RD_WRN_MASK + ); +} + +static hal_ll_err_t hal_ll_i2c_master_start( hal_ll_i2c_hw_specifics_map_t *map ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct(map->base); + uint16_t loop_index = HAL_LL_I2C_LOOP_INDEX; + + set_reg_bit( &(hal_ll_hw_reg->cr2), HAL_LL_I2C_CR2_START_BIT ); + + if ( check_reg_bit( &( hal_ll_hw_reg->isr ), HAL_LL_I2C_ARLO_BIT ) ) + return HAL_LL_I2C_MASTER_ARBITRATION_LOST; + + while ( loop_index-- ) + assembly(nop); + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static hal_ll_err_t hal_ll_i2c_master_stop( hal_ll_i2c_hw_specifics_map_t *map ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = ( hal_ll_i2c_base_handle_t* )map->base; + uint16_t time_counter = map->timeout; + uint32_t loop_index = HAL_LL_I2C_LOOP_INDEX; + + set_reg_bit( &(hal_ll_hw_reg->cr2), HAL_LL_I2C_CR2_STOP_BIT ); + + while ( !( hal_ll_hw_reg->isr & HAL_LL_I2C_ISR_STOPF_BIT ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_STOP; + } + } + + if ( map->timeout < HAL_LL_I2C_LOOP_INDEX ) { + while ( loop_index-- ) + assembly(nop); + } + + hal_ll_hw_reg->isr &= ~HAL_LL_I2C_ISR_STOPF_BIT; + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static hal_ll_pin_name_t hal_ll_i2c_master_check_pins( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_pin_id *index_list, hal_ll_i2c_master_handle_register_t *handle_map ) { + static const uint16_t scl_map_size = ( sizeof( hal_ll_i2c_scl_map ) / sizeof( hal_ll_i2c_pin_map_t ) ); + static const uint16_t sda_map_size = ( sizeof( hal_ll_i2c_sda_map ) / sizeof( hal_ll_i2c_pin_map_t ) ); + uint8_t hal_ll_module_id = 0; + uint8_t index_counter = 0; + uint16_t scl_index; + uint16_t sda_index; + + if ( (HAL_LL_PIN_NC == scl) || (HAL_LL_PIN_NC == sda) ) { + return HAL_LL_PIN_NC; + } + + for ( scl_index = 0; scl_index < scl_map_size; scl_index++ ) { + if ( hal_ll_i2c_scl_map[ scl_index ].pin == scl ) { + for ( sda_index = 0; sda_index < sda_map_size; sda_index++ ) { + if ( hal_ll_i2c_sda_map[ sda_index ].pin == sda ) { + if ( hal_ll_i2c_scl_map[ scl_index ].module_index == hal_ll_i2c_sda_map[ sda_index ].module_index ) { + // Get module number + hal_ll_module_id = hal_ll_i2c_scl_map[ scl_index ].module_index; + // Map pin names + index_list[hal_ll_module_id].pin_scl = scl_index; + index_list[hal_ll_module_id].pin_sda = sda_index; + + // Check if module is taken + if ( NULL == handle_map[ hal_ll_module_id ].hal_drv_i2c_master_handle ) { + return hal_ll_module_id; + } else if ( I2C_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static hal_ll_i2c_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof(hal_ll_i2c_master_handle_register_t)); + static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof(hal_ll_i2c_master_handle_register_t)); + + while( hal_ll_module_count-- ) { + if (hal_ll_i2c_get_base_from_hal_handle == hal_ll_i2c_hw_specifics_map[hal_ll_module_count].base) { + return &hal_ll_i2c_hw_specifics_map[hal_ll_module_count]; + } + } + + return &hal_ll_i2c_hw_specifics_map[hal_ll_module_error]; +} + +static void hal_ll_i2c_master_set_clock( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ) { + switch ( map->module_index ) + { + #if defined(I2C_MODULE_1) + case ( hal_ll_i2c_module_num(I2C_MODULE_1) ): + hal_ll_i2c1_set_clock( hal_ll_state ); + break; + #endif + + #if defined(I2C_MODULE_2) + case ( hal_ll_i2c_module_num(I2C_MODULE_2) ): + hal_ll_i2c2_set_clock( hal_ll_state ); + break; + #endif + + #if defined(I2C_MODULE_3) + case ( hal_ll_i2c_module_num(I2C_MODULE_3) ): + hal_ll_i2c3_set_clock( hal_ll_state ); + break; + #endif + + #if defined(I2C_MODULE_4) + case ( hal_ll_i2c_module_num(I2C_MODULE_4) ): + hal_ll_i2c4_set_clock( hal_ll_state ); + break; + #endif + + + default: + break; + } +} + +static void hal_ll_i2c_master_map_pins( uint8_t module_index, hal_ll_i2c_pin_id *index_list ) { + // Map new pins + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_scl.pin_name = hal_ll_i2c_scl_map[ index_list[module_index].pin_scl ].pin; + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_sda.pin_name = hal_ll_i2c_sda_map[ index_list[module_index].pin_sda ].pin; + // SCL and SDA could have different alternate function settings, hence save both AF values + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_scl.pin_af = hal_ll_i2c_scl_map[ index_list[module_index].pin_scl ].af; + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_sda.pin_af = hal_ll_i2c_sda_map[ index_list[module_index].pin_sda ].af; +} + +static void hal_ll_i2c_master_alternate_functions_set_state( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ) { + module_struct module; + + if( (map->pins.pin_scl.pin_name != HAL_LL_PIN_NC) && (map->pins.pin_sda.pin_name != HAL_LL_PIN_NC) ) { + module.pins[0] = VALUE( map->pins.pin_scl.pin_name, map->pins.pin_scl.pin_af ); + module.pins[1] = VALUE( map->pins.pin_sda.pin_name, map->pins.pin_sda.pin_af ); + module.pins[2] = GPIO_MODULE_STRUCT_END; + + module.configs[0] = HAL_LL_I2C_AF_CONFIG; + module.configs[1] = HAL_LL_I2C_AF_CONFIG; + module.configs[2] = GPIO_MODULE_STRUCT_END; + + hal_ll_gpio_module_struct_init( &module, hal_ll_state ); + } +} + +static uint32_t hal_ll_i2c_get_speed( hal_ll_i2c_hw_specifics_map_t *map ) { + if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_FAST ) { + if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_STANDARD ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_100K; + return HAL_LL_I2C_100K; + } else if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_FULL ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_400K; + return HAL_LL_I2C_400K; + } else if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_FAST ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_1M; + return HAL_LL_I2C_1M; + } else { + map->speed = HAL_LL_I2C_MASTER_SPEED_100K; + return HAL_LL_I2C_100K; + } + } else { + if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_100K ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_100K; + return HAL_LL_I2C_100K; + } else if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_400K ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_400K; + return HAL_LL_I2C_400K; + } else if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_1M ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_1M; + return HAL_LL_I2C_1M; + } else { + map->speed = HAL_LL_I2C_MASTER_SPEED_1M; + return HAL_LL_I2C_1M; + } + } +} +static inline void hal_ll_i2c1_set_clock( bool hal_ll_state ) { + if ( hal_ll_state ) { + set_reg_bit( _RCC_APB1ENR1, HAL_LL_I2C1EN_BIT ); + set_reg_bit( _RCC_CCIPR, HAL_LL_I2C1SEL1_BIT ); + } else { + clear_reg_bit( _RCC_APB1ENR1, HAL_LL_I2C1EN_BIT ); + clear_reg_bit( _RCC_CCIPR, HAL_LL_I2C1SEL1_BIT ); + } +} + + +static inline void hal_ll_i2c2_set_clock( bool hal_ll_state ) { + if ( hal_ll_state ) { + set_reg_bit( _RCC_APB1ENR1, HAL_LL_I2C2EN_BIT ); + set_reg_bit( _RCC_CCIPR, HAL_LL_I2C2SEL1_BIT ); + } else { + clear_reg_bit( _RCC_APB1ENR1, HAL_LL_I2C2EN_BIT ); + clear_reg_bit( _RCC_CCIPR, HAL_LL_I2C2SEL1_BIT ); + } +} + + +static inline void hal_ll_i2c3_set_clock( bool hal_ll_state ) { + if ( hal_ll_state ) { + set_reg_bit( _RCC_APB1ENR1, HAL_LL_I2C3EN_BIT ); + set_reg_bit( _RCC_CCIPR, HAL_LL_I2C3SEL1_BIT ); + } else { + clear_reg_bit( _RCC_APB1ENR1, HAL_LL_I2C3EN_BIT ); + clear_reg_bit( _RCC_CCIPR, HAL_LL_I2C3SEL1_BIT ); + } +} + + +static inline void hal_ll_i2c4_set_clock( bool hal_ll_state ) { + if ( hal_ll_state ) { + set_reg_bit( _RCC_APB1ENR2, HAL_LL_I2C4EN_BIT ); + set_reg_bit( _RCC_CCIPR2, HAL_LL_I2C4SEL1_BIT ); + } else { + clear_reg_bit( _RCC_APB1ENR2, HAL_LL_I2C4EN_BIT ); + clear_reg_bit( _RCC_CCIPR2, HAL_LL_I2C4SEL1_BIT ); + } +} + + + +static hal_ll_err_t hal_ll_i2c_hw_init( hal_ll_i2c_hw_specifics_map_t *map ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct(map->base); + uint16_t time_counter = map->timeout; + + clear_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_I2C_PE_BIT ); + while ( check_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_I2C_PE_BIT ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_INIT; + } + } + + hal_ll_hw_reg->cr1 &= HAL_LL_I2C_FILTERS_OFF; + + hal_ll_hw_reg->timingr = hal_ll_i2c_get_speed( map ); + + hal_ll_hw_reg->cr1 |= HAL_LL_I2C_CR1_RXTX_INT; + + set_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_I2C_PE_BIT ); + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static hal_ll_err_t hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_t *map ) { + hal_ll_i2c_master_set_clock( map, true ); + + return hal_ll_i2c_hw_init( map ); +} +// ------------------------------------------------------------------------- END + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_86/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_86/CMakeLists.cmake new file mode 100644 index 000000000..ff9088230 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_86/CMakeLists.cmake @@ -0,0 +1,9 @@ +if(${MCU_NAME} MATCHES "^STM32G483CE$|^STM32G483RE$|^STM32G483ME$|^STM32G483PE$|^STM32G483VE$|^STM32G483QE$") + set(i2c_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_i2c_master.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_86") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_86") + list(APPEND hal_ll_def_list "STM32G4xx") + list(APPEND hal_ll_def_list "STM32G48xx") + list(APPEND hal_ll_def_list "STM32G483xx") + set(i2c_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/i2c/hal_ll_i2c_pin_map/implementations/doc_ds_86") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_86/hal_ll_i2c_master.c b/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_86/hal_ll_i2c_master.c new file mode 100644 index 000000000..2d9b5f410 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_86/hal_ll_i2c_master.c @@ -0,0 +1,1015 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_i2c_master.c + * @brief I2C master HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_rcc.h" +#include "hal_ll_gpio.h" +#include "hal_ll_i2c_master.h" +#include "hal_ll_i2c_pin_map.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_i2c_master_handle_register_t hal_ll_module_state[I2C_MODULE_COUNT] = { (handle_t *)NULL, (handle_t *)NULL, false }; + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_i2c_get_module_state_address ((hal_ll_i2c_master_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_i2c_get_handle (hal_ll_i2c_master_handle_register_t *)hal_ll_i2c_get_module_state_address->hal_ll_i2c_master_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_i2c_get_base_struct(_handle) ((hal_ll_i2c_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_i2c_get_base_from_hal_handle ((hal_ll_i2c_hw_specifics_map_t *)((hal_ll_i2c_master_handle_register_t *)\ + (((hal_ll_i2c_master_handle_register_t *)(handle))->hal_ll_i2c_master_handle))->hal_ll_i2c_master_handle)->base + +/*!< @brief Default I2C bit-rate if no speed is set */ +#define HAL_LL_I2C_MASTER_SPEED_100K 100000UL +#define HAL_LL_I2C_MASTER_SPEED_400K 400000UL +#define HAL_LL_I2C_MASTER_SPEED_1M 1000000UL + +/*!< @brief Default pass count value upon reset */ +#define HAL_LL_I2C_DEFAULT_PASS_COUNT 0xFFFFU + +/*!< @brief Macro used for timeout */ +#define HAL_LL_I2C_LOOP_INDEX 10000U + +/*!< @brief Macros defining register bit location */ +#define HAL_LL_I2C1EN_BIT 21 + +#define HAL_LL_I2C2EN_BIT 22 + +#define HAL_LL_I2C3EN_BIT 30 + +#define HAL_LL_I2C4EN_BIT 1 + +#define HAL_LL_I2C1SEL0_BIT 12 + +#define HAL_LL_I2C1SEL1_BIT 13 + +#define HAL_LL_I2C2SEL0_BIT 14 + +#define HAL_LL_I2C2SEL1_BIT 15 + +#define HAL_LL_I2C3SEL0_BIT 16 + +#define HAL_LL_I2C3SEL1_BIT 17 + +#define HAL_LL_I2C4SEL0_BIT 0 + +#define HAL_LL_I2C4SEL1_BIT 1 + + + + +#define HAL_LL_I2C_100K 0x30420F13 //?????????????????? +#define HAL_LL_I2C_400K 0x10320309 //?????????????????? +#define HAL_LL_I2C_1M 0x00200204 //?????????????????? + +#define HAL_LL_I2C_PE_BIT 0 +#define HAL_LL_I2C_CR2_STOP_BIT 14 +#define HAL_LL_I2C_CR2_START_BIT 13 +#define HAL_LL_I2C_ISR_STOPF_BIT 5 +#define HAL_LL_I2C_ISR_BUSY_BIT 15 +#define HAL_LL_I2C_ARLO_BIT 9 +#define HAL_LL_I2C_RXNE_BIT 2 +#define HAL_LL_I2C_TXIS_BIT 1 +#define HAL_LL_I2C_TXE_BIT 0 + +/*!< @brief Macros defining register bit masks */ +#define HAL_LL_I2C_CR1_RXTX_INT 0x6 +#define HAL_LL_I2C_CR2_STOP 0x4000UL +#define HAL_LL_I2C_CR2_START 0x2000U +#define HAL_LL_I2C_CR2_SADD 0x3FFU +#define HAL_LL_I2C_CR2_NBYTES 0xFF0000UL +#define HAL_LL_I2C_CR2_RD_WRN 0x400U +#define HAL_LL_I2C_CR2_RELOAD 0x1000000UL +#define HAL_LL_I2C_CR2_AUTOEND 0x2000000UL +#define HAL_LL_I2C_FILTERS_OFF 0xFFFFE0FFUL +#define HAL_LL_I2C_SADD_MASK 0x3FFUL +#define HAL_LL_I2C_HEAD10R_MASK 0x1000UL +#define HAL_LL_I2C_NBYTES_MASK 0xFF0000UL +#define HAL_LL_I2C_RELOAD_MASK 0x1000000UL +#define HAL_LL_I2C_RD_WRN_MASK 0x400UL + +/*!< @brief Macros used for module pin checking */ +#define HAL_LL_I2C_SCL_PIN 0 +#define HAL_LL_I2C_SDA_PIN 1 +#define HAL_LL_I2C_MODULE_PIN_COUNT 2 + +/*!< @brief Macro used for setting pin alternate functions */ +#define HAL_LL_I2C_AF_CONFIG (GPIO_CFG_MODE_ALT_FUNCTION | GPIO_CFG_SPEED_HIGH | GPIO_CFG_OTYPE_OD) + +// -------------------------------------------------------------- PRIVATE TYPES +/*!< @brief I2C register structure */ +typedef struct +{ + hal_ll_base_addr_t cr1; + hal_ll_base_addr_t cr2; + hal_ll_base_addr_t oar1; + hal_ll_base_addr_t oar2; + hal_ll_base_addr_t timingr; + hal_ll_base_addr_t timeoutr; + hal_ll_base_addr_t isr; + hal_ll_base_addr_t icr; + hal_ll_base_addr_t pecr; + hal_ll_base_addr_t rxdr; + hal_ll_base_addr_t txdr; + +} hal_ll_i2c_base_handle_t; + +/*!< @brief I2C hw specific structure */ +typedef struct +{ + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + hal_ll_i2c_pins_t pins; + uint32_t speed; + uint8_t address; + uint16_t timeout; +} hal_ll_i2c_hw_specifics_map_t; + +/*!< @brief I2C hw specific module values */ +typedef struct +{ + uint16_t pin_scl; + uint16_t pin_sda; +} hal_ll_i2c_pin_id; + +/*!< @brief I2C hw specific error values */ +typedef enum +{ + HAL_LL_I2C_MASTER_SUCCESS = 0, + HAL_LL_I2C_MASTER_WRONG_PINS, + HAL_LL_I2C_MASTER_MODULE_ERROR, + + HAL_LL_I2C_MASTER_ERROR = (-1) +} hal_ll_i2c_master_err_t; + +/*!< @brief I2C end mode selection values */ +typedef enum +{ + HAL_LL_I2C_MASTER_END_MODE_RESTART = 0, + HAL_LL_I2C_MASTER_END_MODE_STOP, + HAL_LL_I2C_MASTER_WRITE_THEN_READ +} hal_ll_i2c_master_end_mode_t; + +/*!< @brief I2C timeout error values */ +typedef enum +{ + HAL_LL_I2C_MASTER_TIMEOUT_START = 1300, + HAL_LL_I2C_MASTER_TIMEOUT_STOP, + HAL_LL_I2C_MASTER_TIMEOUT_WRITE, + HAL_LL_I2C_MASTER_TIMEOUT_READ, + HAL_LL_I2C_MASTER_ARBITRATION_LOST, + HAL_LL_I2C_MASTER_TIMEOUT_INIT +} hal_ll_i2c_master_timeout_t; + +/** + * @brief Enum containing predefined module standard speed values. + * + * Enum values: + * HAL_LL_I2C_MASTER_SPEED_STANDARD -- Speed set at 100K + * HAL_LL_I2C_MASTER_SPEED_FULL -- Speed set at 400K + * HAL_LL_I2C_MASTER_SPEED_FAST -- Speed set at 1M + */ +typedef enum +{ + HAL_LL_I2C_MASTER_SPEED_STANDARD = 0, + HAL_LL_I2C_MASTER_SPEED_FULL, + HAL_LL_I2C_MASTER_SPEED_FAST +} hal_ll_i2c_master_speed_t; + +// ------------------------------------------------------------------ VARIABLES +/*!< @brief I2C hardware specific info */ +static hal_ll_i2c_hw_specifics_map_t hal_ll_i2c_hw_specifics_map[] = +{ + #ifdef I2C_MODULE_1 + {HAL_LL_I2C1_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_1), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, + #endif + + #ifdef I2C_MODULE_2 + {HAL_LL_I2C2_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_2), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, + #endif + + #ifdef I2C_MODULE_3 + {HAL_LL_I2C3_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_3), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, + #endif + + #ifdef I2C_MODULE_4 + {HAL_LL_I2C4_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_4), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, + #endif + + + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, 0, 0} +}; + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_i2c_master_handle_register_t *low_level_handle; +static volatile hal_ll_i2c_hw_specifics_map_t *hal_ll_i2c_hw_specifics_map_local; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Check if pins are adequate. + * + * Checks scl and sda pins the user has passed with pre-defined + * pins in scl and sda maps. Take into consideration that module + * index numbers have to be the same for both pins. + * + * @param[in] scl - SCL pre-defined pin name. + * @param[in] sda - SDA pre-defined pin name. + * @param[in] *index_list - Index list address + * @return hal_ll_pin_name_t Module index based on pins. + * + * Returns pre-defined module index from pin maps, if pins + * are adequate. + */ +static hal_ll_pin_name_t hal_ll_i2c_master_check_pins( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_pin_id *index_list, hal_ll_i2c_master_handle_register_t *handle_map ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_i2c_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_i2c_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_i2c_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Get adequate I2C bit-rate value. + * + * Returns one of pre-defined bit-rate values, + * or the closest bit-rate based on bit_rate + * value passed to the function. + * + * @param[in] bit_rate - I2C bit rate. + * @return uint32_t Adequate bit-rate value. + * + * Returns adequate value to be latter written into bare metal register address. + * Take into consideration that this returns a predefined value. + * + * HAL_LL_I2C_MASTER_SPEED_100K -- 100Kbit/s + * HAL_LL_I2C_MASTER_SPEED_400K -- 400Kbit/s + * HAL_LL_I2C_MASTER_SPEED_1M -- 1Mbit/s + * HAL_LL_I2C_MASTER_SPEED_3M2 -- 3.2Mbit/s + */ +static uint32_t hal_ll_i2c_get_speed( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Enable clock for I2C1 module on hardware level. + * + * Initializes I2C1 module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] hal_ll_state - True/False -- Init/De-init + * + * @return None + */ +static inline void hal_ll_i2c1_set_clock( bool hal_ll_state ); + +/** + * @brief Enable clock for I2C2 module on hardware level. + * + * Initializes I2C2 module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] hal_ll_state - True/False -- Init/De-init + * + * @return None + */ +static inline void hal_ll_i2c2_set_clock( bool hal_ll_state ); + +/** + * @brief Enable clock for I2C3 module on hardware level. + * + * Initializes I2C3 module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] hal_ll_state - True/False -- Init/De-init + * + * @return None + */ +static inline void hal_ll_i2c3_set_clock( bool hal_ll_state ); + +/** + * @brief Enable clock for I2C4 module on hardware level. + * + * Initializes I2C4 module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] hal_ll_state - True/False -- Init/De-init + * + * @return None + */ +static inline void hal_ll_i2c4_set_clock( bool hal_ll_state ); + +/** + * @brief Enable clock for I2C module on hardware level. + * + * Initializes I2C module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_stat - True(enable clock)/False(disable clock). + * + * @return None + */ +static void hal_ll_i2c_master_set_clock( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Initialize I2C module on hardware level. + * + * Initializes I2C module on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] map - Object specific context handler. + * @return hal_ll_err_t Module specific return values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_hw_init( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * I2C SCL and SDA pins. + * + * @param[in] module_index I2C HW module index -- 0,1,2... + * @param[in] *index_list Array with SCL and SDA map index values + * and module number + * + * @return None + */ +static void hal_ll_i2c_master_map_pins( uint8_t module_index, hal_ll_i2c_pin_id *index_list ); + +/** + * @brief Sets I2C pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if I2C is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_state - Init/De-init + * + * @return None + */ +static void hal_ll_i2c_master_alternate_functions_set_state( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Full I2C module initialization procedure. + * + * Initializes I2C module on hardware level, based on beforehand + * set configuration and module handler. Sets adequate pin alternate functions. + * Initializes module clock. + * + * @param[in] map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Configure I2C module for data transfer. + * + * @param[in] hal_ll_hw_reg - I2C module base address. + * @param[in] config - I2C config bits. + * @return void None. + */ +static void hal_ll_i2c_master_configure_transfer( hal_ll_i2c_base_handle_t *hal_ll_hw_reg, uint32_t config ); + +/** + * @brief Reset value of I2C CR2 register. + * + * @param[in] hal_ll_hw_reg - I2C module base address. + * @returnl none + */ +static void hal_ll_i2c_master_reset_cr2( hal_ll_i2c_base_handle_t *hal_ll_hw_reg ); + +/** + * @brief Generates start signal on I2C bus. + * + * Generates a start signal on the I2C bus. + * + * @param[in] map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_master_start( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Generates stop signal on I2C bus. + * + * Generates a stop signal on the I2C bus. + * + * @param[in] map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_master_stop( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Perform a read on the I2C bus. + * + * Initializes I2C module on hardware level, if not initialized beforehand + * and continues to perform a read operation on the bus. + * + * @param[in] map - Object specific context handler. + * @param[in] readDatabuf - Pointer to data buffer. + * @param[in] lenReadData - Number of data to be read. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *read_data_buf, size_t len_read_data, hal_ll_i2c_master_end_mode_t mode ); + +/** + * @brief Perform a write on the I2C bus. + * + * Initializes I2C module on hardware level, if not initialized beforehand + * and continues to perform a write operation on the bus. + * + * @param[in] map - Object specific context handler. + * @param[in] writeDatabuf - Pointer to data buffer. + * @param[in] lenWriteData - Number of data to be written. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *write_data_buf, size_t len_write_data, hal_ll_i2c_master_end_mode_t mode ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_i2c_master_register_handle( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_master_handle_register_t *handle_map, uint8_t *hal_module_id ) { + + hal_ll_i2c_pin_id index_list[I2C_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + uint16_t pin_check_result; + + // Check if pins are valid + if ( (pin_check_result = hal_ll_i2c_master_check_pins( scl, sda, &index_list, handle_map )) == HAL_LL_PIN_NC ) { + return HAL_LL_I2C_MASTER_WRONG_PINS; + }; + + if ( (hal_ll_i2c_hw_specifics_map[pin_check_result].pins.pin_scl.pin_name != scl) || + (hal_ll_i2c_hw_specifics_map[pin_check_result].pins.pin_sda.pin_name != sda) ) + { + hal_ll_i2c_master_alternate_functions_set_state( &hal_ll_i2c_hw_specifics_map[ pin_check_result ], false ); + + hal_ll_i2c_master_map_pins( pin_check_result, &index_list ); + + hal_ll_i2c_master_alternate_functions_set_state( &hal_ll_i2c_hw_specifics_map[ pin_check_result ], true ); + + handle_map[pin_check_result].init_ll_state = false; + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[pin_check_result].hal_ll_i2c_master_handle = (handle_t *)&hal_ll_i2c_hw_specifics_map[pin_check_result].base; + + handle_map[pin_check_result].hal_ll_i2c_master_handle = (handle_t *)&hal_ll_module_state[pin_check_result].hal_ll_i2c_master_handle; + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_i2c( handle_t *handle ) { + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + hal_ll_i2c_master_handle_register_t *hal_handle = (hal_ll_i2c_master_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_i2c_hw_specifics_map_local->module_index; + + hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_local ); + + hal_ll_module_state[pin_check_result].hal_ll_i2c_master_handle = (handle_t *)&hal_ll_i2c_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_i2c_master_set_speed( handle_t *handle, uint32_t speed ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + low_level_handle->init_ll_state = false; + + hal_ll_i2c_hw_specifics_map_local->speed = speed; + + if ( hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_local ) != HAL_LL_I2C_MASTER_SUCCESS ) { + return HAL_LL_I2C_MASTER_TIMEOUT_INIT; + } + + low_level_handle->init_ll_state = true; + + return hal_ll_i2c_hw_specifics_map_local->speed; +} + +void hal_ll_i2c_master_set_timeout( handle_t *handle, uint16_t timeout ) { + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + if( hal_ll_i2c_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + hal_ll_i2c_hw_specifics_map_local->timeout = timeout; + } +} + +void hal_ll_i2c_master_set_slave_address( handle_t *handle, uint8_t addr ) { + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + if( hal_ll_i2c_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + hal_ll_i2c_hw_specifics_map_local->address = addr; + } +} + +hal_ll_err_t hal_ll_i2c_master_read( handle_t *handle, uint8_t *read_data_buf, size_t len_read_data ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + return hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_local, read_data_buf, len_read_data, HAL_LL_I2C_MASTER_END_MODE_STOP ); +} + +hal_ll_err_t hal_ll_i2c_master_write( handle_t *handle, uint8_t *write_data_buf, size_t len_write_data ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + return hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_local, write_data_buf, len_write_data, HAL_LL_I2C_MASTER_END_MODE_STOP ); +} + +hal_ll_err_t hal_ll_i2c_master_write_then_read( handle_t *handle, uint8_t *write_data_buf, size_t len_write_data, uint8_t *read_data_buf, size_t len_read_data ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + if( hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_local, write_data_buf, len_write_data, HAL_LL_I2C_MASTER_WRITE_THEN_READ ) != NULL ) { + return HAL_LL_I2C_MASTER_TIMEOUT_WRITE; + } + + /** + * @note Wait for drivers to set-up + * correctly. + **/ + #ifdef __TFT_RESISTIVE_TSC2003__ + Delay_22us(); + #endif + + if( hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_local, read_data_buf, len_read_data, HAL_LL_I2C_MASTER_WRITE_THEN_READ ) != NULL ) { + return HAL_LL_I2C_MASTER_TIMEOUT_READ; + } + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +void hal_ll_i2c_master_close( handle_t *handle ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + if( low_level_handle->hal_ll_i2c_master_handle != NULL ) { + low_level_handle->hal_ll_i2c_master_handle = NULL; + low_level_handle->hal_drv_i2c_master_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_i2c_hw_specifics_map_local->address = 0; + hal_ll_i2c_hw_specifics_map_local->timeout = HAL_LL_I2C_DEFAULT_PASS_COUNT; + hal_ll_i2c_hw_specifics_map_local->speed = HAL_LL_I2C_MASTER_SPEED_100K; + + hal_ll_i2c_master_set_clock(hal_ll_i2c_hw_specifics_map_local, true); + hal_ll_i2c_master_alternate_functions_set_state( hal_ll_i2c_hw_specifics_map_local, false ); + hal_ll_i2c_master_set_clock(hal_ll_i2c_hw_specifics_map_local, false); + + hal_ll_i2c_hw_specifics_map_local->pins.pin_scl.pin_name = HAL_LL_PIN_NC; + hal_ll_i2c_hw_specifics_map_local->pins.pin_sda.pin_name = HAL_LL_PIN_NC; + hal_ll_i2c_hw_specifics_map_local->pins.pin_scl.pin_af = 0; + hal_ll_i2c_hw_specifics_map_local->pins.pin_sda.pin_af = 0; + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static hal_ll_err_t hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *read_data_buf, size_t len_read_data, hal_ll_i2c_master_end_mode_t mode ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct(map->base); + uint16_t time_counter = map->timeout; + size_t transfer_counter = NULL; + uint8_t status = NULL; + + /** + * @note When R/W = 0, the input sample acquisition period starts + * on the falling edge of SCL once the C0 bit of the command + * byte has been latched, and ends when a Stop or + * repeated Start condition has been issued. + **/ + #ifdef __TFT_RESISTIVE_TSC2003__ + Delay_1ms(); + #endif + + hal_ll_i2c_master_configure_transfer ( map->base, + ( map->address << 1 & HAL_LL_I2C_CR2_SADD ) | + ( len_read_data << 16 & HAL_LL_I2C_CR2_NBYTES ) | + HAL_LL_I2C_CR2_RD_WRN | + HAL_LL_I2C_CR2_START + ); + + for ( transfer_counter; transfer_counter < len_read_data; transfer_counter++ ) { + while ( !( check_reg_bit( &( hal_ll_hw_reg->isr ), HAL_LL_I2C_RXNE_BIT ) ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_READ; + } + } + read_data_buf[ transfer_counter ] = hal_ll_hw_reg->rxdr; + } + + if ( ( mode == HAL_LL_I2C_MASTER_END_MODE_STOP ) || ( mode == HAL_LL_I2C_MASTER_WRITE_THEN_READ ) ) { + status = hal_ll_i2c_master_stop( map ); + } else { + status = hal_ll_i2c_master_start( map ); + } + + if( status != HAL_LL_I2C_MASTER_SUCCESS ) { + return status; + } + + hal_ll_i2c_master_reset_cr2( hal_ll_hw_reg ); + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static hal_ll_err_t hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *write_data_buf, size_t len_write_data, hal_ll_i2c_master_end_mode_t mode ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct(map->base); + uint16_t time_counter = map->timeout; + size_t transfer_counter = NULL; + uint8_t status = NULL; + + hal_ll_i2c_master_configure_transfer ( map->base, + ( map->address << 1 & HAL_LL_I2C_CR2_SADD ) | + ( len_write_data << 16 & HAL_LL_I2C_CR2_NBYTES ) | + !HAL_LL_I2C_CR2_RD_WRN | + HAL_LL_I2C_CR2_START + ); + + for ( transfer_counter; transfer_counter < len_write_data; transfer_counter++ ) + { + while ( !( check_reg_bit( &( hal_ll_hw_reg->isr ), HAL_LL_I2C_TXIS_BIT ) ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_WRITE; + } + } + hal_ll_hw_reg->txdr = write_data_buf[ transfer_counter ]; + } + + time_counter = map->timeout; + while ( !( check_reg_bit( &( hal_ll_hw_reg->isr ), HAL_LL_I2C_TXE_BIT ) ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_WRITE; + } + } + + if ( mode == HAL_LL_I2C_MASTER_END_MODE_STOP ) + { + hal_ll_i2c_master_stop( map ); + } + + hal_ll_i2c_master_reset_cr2( hal_ll_hw_reg ); + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static void hal_ll_i2c_master_configure_transfer( hal_ll_i2c_base_handle_t *hal_ll_hw_reg, uint32_t config ) { + uint32_t reg = 0; + + // Clear last set slave address + hal_ll_hw_reg->cr2 &= ~HAL_LL_I2C_CR2_SADD; + + reg = hal_ll_hw_reg->cr2; + reg &= ~( uint32_t )( + ( HAL_LL_I2C_CR2_SADD ) | + ( HAL_LL_I2C_CR2_NBYTES ) | + ( HAL_LL_I2C_CR2_RELOAD ) | + ( HAL_LL_I2C_CR2_AUTOEND ) | + ( HAL_LL_I2C_CR2_RD_WRN ) | + ( HAL_LL_I2C_CR2_START ) | + ( HAL_LL_I2C_CR2_STOP ) + ); + + reg |= config; + hal_ll_hw_reg->cr2 = reg; +} + +static void hal_ll_i2c_master_reset_cr2( hal_ll_i2c_base_handle_t *hal_ll_hw_reg ) { + hal_ll_hw_reg->cr2 &= ~( uint32_t ) + ( + HAL_LL_I2C_SADD_MASK | + HAL_LL_I2C_HEAD10R_MASK | + HAL_LL_I2C_NBYTES_MASK | + HAL_LL_I2C_RELOAD_MASK | + HAL_LL_I2C_RD_WRN_MASK + ); +} + +static hal_ll_err_t hal_ll_i2c_master_start( hal_ll_i2c_hw_specifics_map_t *map ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct(map->base); + uint16_t loop_index = HAL_LL_I2C_LOOP_INDEX; + + set_reg_bit( &(hal_ll_hw_reg->cr2), HAL_LL_I2C_CR2_START_BIT ); + + if ( check_reg_bit( &( hal_ll_hw_reg->isr ), HAL_LL_I2C_ARLO_BIT ) ) + return HAL_LL_I2C_MASTER_ARBITRATION_LOST; + + while ( loop_index-- ) + assembly(nop); + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static hal_ll_err_t hal_ll_i2c_master_stop( hal_ll_i2c_hw_specifics_map_t *map ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = ( hal_ll_i2c_base_handle_t* )map->base; + uint16_t time_counter = map->timeout; + uint32_t loop_index = HAL_LL_I2C_LOOP_INDEX; + + set_reg_bit( &(hal_ll_hw_reg->cr2), HAL_LL_I2C_CR2_STOP_BIT ); + + while ( !( hal_ll_hw_reg->isr & HAL_LL_I2C_ISR_STOPF_BIT ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_STOP; + } + } + + if ( map->timeout < HAL_LL_I2C_LOOP_INDEX ) { + while ( loop_index-- ) + assembly(nop); + } + + hal_ll_hw_reg->isr &= ~HAL_LL_I2C_ISR_STOPF_BIT; + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static hal_ll_pin_name_t hal_ll_i2c_master_check_pins( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_pin_id *index_list, hal_ll_i2c_master_handle_register_t *handle_map ) { + static const uint16_t scl_map_size = ( sizeof( hal_ll_i2c_scl_map ) / sizeof( hal_ll_i2c_pin_map_t ) ); + static const uint16_t sda_map_size = ( sizeof( hal_ll_i2c_sda_map ) / sizeof( hal_ll_i2c_pin_map_t ) ); + uint8_t hal_ll_module_id = 0; + uint8_t index_counter = 0; + uint16_t scl_index; + uint16_t sda_index; + + if ( (HAL_LL_PIN_NC == scl) || (HAL_LL_PIN_NC == sda) ) { + return HAL_LL_PIN_NC; + } + + for ( scl_index = 0; scl_index < scl_map_size; scl_index++ ) { + if ( hal_ll_i2c_scl_map[ scl_index ].pin == scl ) { + for ( sda_index = 0; sda_index < sda_map_size; sda_index++ ) { + if ( hal_ll_i2c_sda_map[ sda_index ].pin == sda ) { + if ( hal_ll_i2c_scl_map[ scl_index ].module_index == hal_ll_i2c_sda_map[ sda_index ].module_index ) { + // Get module number + hal_ll_module_id = hal_ll_i2c_scl_map[ scl_index ].module_index; + // Map pin names + index_list[hal_ll_module_id].pin_scl = scl_index; + index_list[hal_ll_module_id].pin_sda = sda_index; + + // Check if module is taken + if ( NULL == handle_map[ hal_ll_module_id ].hal_drv_i2c_master_handle ) { + return hal_ll_module_id; + } else if ( I2C_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static hal_ll_i2c_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof(hal_ll_i2c_master_handle_register_t)); + static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof(hal_ll_i2c_master_handle_register_t)); + + while( hal_ll_module_count-- ) { + if (hal_ll_i2c_get_base_from_hal_handle == hal_ll_i2c_hw_specifics_map[hal_ll_module_count].base) { + return &hal_ll_i2c_hw_specifics_map[hal_ll_module_count]; + } + } + + return &hal_ll_i2c_hw_specifics_map[hal_ll_module_error]; +} + +static void hal_ll_i2c_master_set_clock( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ) { + switch ( map->module_index ) + { + #if defined(I2C_MODULE_1) + case ( hal_ll_i2c_module_num(I2C_MODULE_1) ): + hal_ll_i2c1_set_clock( hal_ll_state ); + break; + #endif + + #if defined(I2C_MODULE_2) + case ( hal_ll_i2c_module_num(I2C_MODULE_2) ): + hal_ll_i2c2_set_clock( hal_ll_state ); + break; + #endif + + #if defined(I2C_MODULE_3) + case ( hal_ll_i2c_module_num(I2C_MODULE_3) ): + hal_ll_i2c3_set_clock( hal_ll_state ); + break; + #endif + + #if defined(I2C_MODULE_4) + case ( hal_ll_i2c_module_num(I2C_MODULE_4) ): + hal_ll_i2c4_set_clock( hal_ll_state ); + break; + #endif + + + default: + break; + } +} + +static void hal_ll_i2c_master_map_pins( uint8_t module_index, hal_ll_i2c_pin_id *index_list ) { + // Map new pins + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_scl.pin_name = hal_ll_i2c_scl_map[ index_list[module_index].pin_scl ].pin; + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_sda.pin_name = hal_ll_i2c_sda_map[ index_list[module_index].pin_sda ].pin; + // SCL and SDA could have different alternate function settings, hence save both AF values + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_scl.pin_af = hal_ll_i2c_scl_map[ index_list[module_index].pin_scl ].af; + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_sda.pin_af = hal_ll_i2c_sda_map[ index_list[module_index].pin_sda ].af; +} + +static void hal_ll_i2c_master_alternate_functions_set_state( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ) { + module_struct module; + + if( (map->pins.pin_scl.pin_name != HAL_LL_PIN_NC) && (map->pins.pin_sda.pin_name != HAL_LL_PIN_NC) ) { + module.pins[0] = VALUE( map->pins.pin_scl.pin_name, map->pins.pin_scl.pin_af ); + module.pins[1] = VALUE( map->pins.pin_sda.pin_name, map->pins.pin_sda.pin_af ); + module.pins[2] = GPIO_MODULE_STRUCT_END; + + module.configs[0] = HAL_LL_I2C_AF_CONFIG; + module.configs[1] = HAL_LL_I2C_AF_CONFIG; + module.configs[2] = GPIO_MODULE_STRUCT_END; + + hal_ll_gpio_module_struct_init( &module, hal_ll_state ); + } +} + +static uint32_t hal_ll_i2c_get_speed( hal_ll_i2c_hw_specifics_map_t *map ) { + if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_FAST ) { + if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_STANDARD ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_100K; + return HAL_LL_I2C_100K; + } else if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_FULL ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_400K; + return HAL_LL_I2C_400K; + } else if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_FAST ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_1M; + return HAL_LL_I2C_1M; + } else { + map->speed = HAL_LL_I2C_MASTER_SPEED_100K; + return HAL_LL_I2C_100K; + } + } else { + if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_100K ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_100K; + return HAL_LL_I2C_100K; + } else if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_400K ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_400K; + return HAL_LL_I2C_400K; + } else if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_1M ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_1M; + return HAL_LL_I2C_1M; + } else { + map->speed = HAL_LL_I2C_MASTER_SPEED_1M; + return HAL_LL_I2C_1M; + } + } +} +static inline void hal_ll_i2c1_set_clock( bool hal_ll_state ) { + if ( hal_ll_state ) { + set_reg_bit( _RCC_APB1ENR1, HAL_LL_I2C1EN_BIT ); + set_reg_bit( _RCC_CCIPR, HAL_LL_I2C1SEL1_BIT ); + } else { + clear_reg_bit( _RCC_APB1ENR1, HAL_LL_I2C1EN_BIT ); + clear_reg_bit( _RCC_CCIPR, HAL_LL_I2C1SEL1_BIT ); + } +} + + +static inline void hal_ll_i2c2_set_clock( bool hal_ll_state ) { + if ( hal_ll_state ) { + set_reg_bit( _RCC_APB1ENR1, HAL_LL_I2C2EN_BIT ); + set_reg_bit( _RCC_CCIPR, HAL_LL_I2C2SEL1_BIT ); + } else { + clear_reg_bit( _RCC_APB1ENR1, HAL_LL_I2C2EN_BIT ); + clear_reg_bit( _RCC_CCIPR, HAL_LL_I2C2SEL1_BIT ); + } +} + + +static inline void hal_ll_i2c3_set_clock( bool hal_ll_state ) { + if ( hal_ll_state ) { + set_reg_bit( _RCC_APB1ENR1, HAL_LL_I2C3EN_BIT ); + set_reg_bit( _RCC_CCIPR, HAL_LL_I2C3SEL1_BIT ); + } else { + clear_reg_bit( _RCC_APB1ENR1, HAL_LL_I2C3EN_BIT ); + clear_reg_bit( _RCC_CCIPR, HAL_LL_I2C3SEL1_BIT ); + } +} + + +static inline void hal_ll_i2c4_set_clock( bool hal_ll_state ) { + if ( hal_ll_state ) { + set_reg_bit( _RCC_APB1ENR2, HAL_LL_I2C4EN_BIT ); + set_reg_bit( _RCC_CCIPR2, HAL_LL_I2C4SEL1_BIT ); + } else { + clear_reg_bit( _RCC_APB1ENR2, HAL_LL_I2C4EN_BIT ); + clear_reg_bit( _RCC_CCIPR2, HAL_LL_I2C4SEL1_BIT ); + } +} + + + +static hal_ll_err_t hal_ll_i2c_hw_init( hal_ll_i2c_hw_specifics_map_t *map ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct(map->base); + uint16_t time_counter = map->timeout; + + clear_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_I2C_PE_BIT ); + while ( check_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_I2C_PE_BIT ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_INIT; + } + } + + hal_ll_hw_reg->cr1 &= HAL_LL_I2C_FILTERS_OFF; + + hal_ll_hw_reg->timingr = hal_ll_i2c_get_speed( map ); + + hal_ll_hw_reg->cr1 |= HAL_LL_I2C_CR1_RXTX_INT; + + set_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_I2C_PE_BIT ); + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static hal_ll_err_t hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_t *map ) { + hal_ll_i2c_master_set_clock( map, true ); + + return hal_ll_i2c_hw_init( map ); +} +// ------------------------------------------------------------------------- END + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_87/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_87/CMakeLists.cmake new file mode 100644 index 000000000..abd80ba9e --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_87/CMakeLists.cmake @@ -0,0 +1,9 @@ +if(${MCU_NAME} MATCHES "^STM32G484CE$|^STM32G484ME$|^STM32G484PE$|^STM32G484RE$|^STM32G484QE$|^STM32G484VE$") + set(i2c_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_i2c_master.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_87") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_87") + list(APPEND hal_ll_def_list "STM32G4xx") + list(APPEND hal_ll_def_list "STM32G48xx") + list(APPEND hal_ll_def_list "STM32G484xx") + set(i2c_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/i2c/hal_ll_i2c_pin_map/implementations/doc_ds_87") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_87/hal_ll_i2c_master.c b/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_87/hal_ll_i2c_master.c new file mode 100644 index 000000000..2d9b5f410 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_87/hal_ll_i2c_master.c @@ -0,0 +1,1015 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_i2c_master.c + * @brief I2C master HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_rcc.h" +#include "hal_ll_gpio.h" +#include "hal_ll_i2c_master.h" +#include "hal_ll_i2c_pin_map.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_i2c_master_handle_register_t hal_ll_module_state[I2C_MODULE_COUNT] = { (handle_t *)NULL, (handle_t *)NULL, false }; + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_i2c_get_module_state_address ((hal_ll_i2c_master_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_i2c_get_handle (hal_ll_i2c_master_handle_register_t *)hal_ll_i2c_get_module_state_address->hal_ll_i2c_master_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_i2c_get_base_struct(_handle) ((hal_ll_i2c_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_i2c_get_base_from_hal_handle ((hal_ll_i2c_hw_specifics_map_t *)((hal_ll_i2c_master_handle_register_t *)\ + (((hal_ll_i2c_master_handle_register_t *)(handle))->hal_ll_i2c_master_handle))->hal_ll_i2c_master_handle)->base + +/*!< @brief Default I2C bit-rate if no speed is set */ +#define HAL_LL_I2C_MASTER_SPEED_100K 100000UL +#define HAL_LL_I2C_MASTER_SPEED_400K 400000UL +#define HAL_LL_I2C_MASTER_SPEED_1M 1000000UL + +/*!< @brief Default pass count value upon reset */ +#define HAL_LL_I2C_DEFAULT_PASS_COUNT 0xFFFFU + +/*!< @brief Macro used for timeout */ +#define HAL_LL_I2C_LOOP_INDEX 10000U + +/*!< @brief Macros defining register bit location */ +#define HAL_LL_I2C1EN_BIT 21 + +#define HAL_LL_I2C2EN_BIT 22 + +#define HAL_LL_I2C3EN_BIT 30 + +#define HAL_LL_I2C4EN_BIT 1 + +#define HAL_LL_I2C1SEL0_BIT 12 + +#define HAL_LL_I2C1SEL1_BIT 13 + +#define HAL_LL_I2C2SEL0_BIT 14 + +#define HAL_LL_I2C2SEL1_BIT 15 + +#define HAL_LL_I2C3SEL0_BIT 16 + +#define HAL_LL_I2C3SEL1_BIT 17 + +#define HAL_LL_I2C4SEL0_BIT 0 + +#define HAL_LL_I2C4SEL1_BIT 1 + + + + +#define HAL_LL_I2C_100K 0x30420F13 //?????????????????? +#define HAL_LL_I2C_400K 0x10320309 //?????????????????? +#define HAL_LL_I2C_1M 0x00200204 //?????????????????? + +#define HAL_LL_I2C_PE_BIT 0 +#define HAL_LL_I2C_CR2_STOP_BIT 14 +#define HAL_LL_I2C_CR2_START_BIT 13 +#define HAL_LL_I2C_ISR_STOPF_BIT 5 +#define HAL_LL_I2C_ISR_BUSY_BIT 15 +#define HAL_LL_I2C_ARLO_BIT 9 +#define HAL_LL_I2C_RXNE_BIT 2 +#define HAL_LL_I2C_TXIS_BIT 1 +#define HAL_LL_I2C_TXE_BIT 0 + +/*!< @brief Macros defining register bit masks */ +#define HAL_LL_I2C_CR1_RXTX_INT 0x6 +#define HAL_LL_I2C_CR2_STOP 0x4000UL +#define HAL_LL_I2C_CR2_START 0x2000U +#define HAL_LL_I2C_CR2_SADD 0x3FFU +#define HAL_LL_I2C_CR2_NBYTES 0xFF0000UL +#define HAL_LL_I2C_CR2_RD_WRN 0x400U +#define HAL_LL_I2C_CR2_RELOAD 0x1000000UL +#define HAL_LL_I2C_CR2_AUTOEND 0x2000000UL +#define HAL_LL_I2C_FILTERS_OFF 0xFFFFE0FFUL +#define HAL_LL_I2C_SADD_MASK 0x3FFUL +#define HAL_LL_I2C_HEAD10R_MASK 0x1000UL +#define HAL_LL_I2C_NBYTES_MASK 0xFF0000UL +#define HAL_LL_I2C_RELOAD_MASK 0x1000000UL +#define HAL_LL_I2C_RD_WRN_MASK 0x400UL + +/*!< @brief Macros used for module pin checking */ +#define HAL_LL_I2C_SCL_PIN 0 +#define HAL_LL_I2C_SDA_PIN 1 +#define HAL_LL_I2C_MODULE_PIN_COUNT 2 + +/*!< @brief Macro used for setting pin alternate functions */ +#define HAL_LL_I2C_AF_CONFIG (GPIO_CFG_MODE_ALT_FUNCTION | GPIO_CFG_SPEED_HIGH | GPIO_CFG_OTYPE_OD) + +// -------------------------------------------------------------- PRIVATE TYPES +/*!< @brief I2C register structure */ +typedef struct +{ + hal_ll_base_addr_t cr1; + hal_ll_base_addr_t cr2; + hal_ll_base_addr_t oar1; + hal_ll_base_addr_t oar2; + hal_ll_base_addr_t timingr; + hal_ll_base_addr_t timeoutr; + hal_ll_base_addr_t isr; + hal_ll_base_addr_t icr; + hal_ll_base_addr_t pecr; + hal_ll_base_addr_t rxdr; + hal_ll_base_addr_t txdr; + +} hal_ll_i2c_base_handle_t; + +/*!< @brief I2C hw specific structure */ +typedef struct +{ + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + hal_ll_i2c_pins_t pins; + uint32_t speed; + uint8_t address; + uint16_t timeout; +} hal_ll_i2c_hw_specifics_map_t; + +/*!< @brief I2C hw specific module values */ +typedef struct +{ + uint16_t pin_scl; + uint16_t pin_sda; +} hal_ll_i2c_pin_id; + +/*!< @brief I2C hw specific error values */ +typedef enum +{ + HAL_LL_I2C_MASTER_SUCCESS = 0, + HAL_LL_I2C_MASTER_WRONG_PINS, + HAL_LL_I2C_MASTER_MODULE_ERROR, + + HAL_LL_I2C_MASTER_ERROR = (-1) +} hal_ll_i2c_master_err_t; + +/*!< @brief I2C end mode selection values */ +typedef enum +{ + HAL_LL_I2C_MASTER_END_MODE_RESTART = 0, + HAL_LL_I2C_MASTER_END_MODE_STOP, + HAL_LL_I2C_MASTER_WRITE_THEN_READ +} hal_ll_i2c_master_end_mode_t; + +/*!< @brief I2C timeout error values */ +typedef enum +{ + HAL_LL_I2C_MASTER_TIMEOUT_START = 1300, + HAL_LL_I2C_MASTER_TIMEOUT_STOP, + HAL_LL_I2C_MASTER_TIMEOUT_WRITE, + HAL_LL_I2C_MASTER_TIMEOUT_READ, + HAL_LL_I2C_MASTER_ARBITRATION_LOST, + HAL_LL_I2C_MASTER_TIMEOUT_INIT +} hal_ll_i2c_master_timeout_t; + +/** + * @brief Enum containing predefined module standard speed values. + * + * Enum values: + * HAL_LL_I2C_MASTER_SPEED_STANDARD -- Speed set at 100K + * HAL_LL_I2C_MASTER_SPEED_FULL -- Speed set at 400K + * HAL_LL_I2C_MASTER_SPEED_FAST -- Speed set at 1M + */ +typedef enum +{ + HAL_LL_I2C_MASTER_SPEED_STANDARD = 0, + HAL_LL_I2C_MASTER_SPEED_FULL, + HAL_LL_I2C_MASTER_SPEED_FAST +} hal_ll_i2c_master_speed_t; + +// ------------------------------------------------------------------ VARIABLES +/*!< @brief I2C hardware specific info */ +static hal_ll_i2c_hw_specifics_map_t hal_ll_i2c_hw_specifics_map[] = +{ + #ifdef I2C_MODULE_1 + {HAL_LL_I2C1_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_1), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, + #endif + + #ifdef I2C_MODULE_2 + {HAL_LL_I2C2_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_2), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, + #endif + + #ifdef I2C_MODULE_3 + {HAL_LL_I2C3_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_3), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, + #endif + + #ifdef I2C_MODULE_4 + {HAL_LL_I2C4_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_4), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, + #endif + + + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, 0, 0} +}; + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_i2c_master_handle_register_t *low_level_handle; +static volatile hal_ll_i2c_hw_specifics_map_t *hal_ll_i2c_hw_specifics_map_local; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Check if pins are adequate. + * + * Checks scl and sda pins the user has passed with pre-defined + * pins in scl and sda maps. Take into consideration that module + * index numbers have to be the same for both pins. + * + * @param[in] scl - SCL pre-defined pin name. + * @param[in] sda - SDA pre-defined pin name. + * @param[in] *index_list - Index list address + * @return hal_ll_pin_name_t Module index based on pins. + * + * Returns pre-defined module index from pin maps, if pins + * are adequate. + */ +static hal_ll_pin_name_t hal_ll_i2c_master_check_pins( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_pin_id *index_list, hal_ll_i2c_master_handle_register_t *handle_map ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_i2c_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_i2c_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_i2c_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Get adequate I2C bit-rate value. + * + * Returns one of pre-defined bit-rate values, + * or the closest bit-rate based on bit_rate + * value passed to the function. + * + * @param[in] bit_rate - I2C bit rate. + * @return uint32_t Adequate bit-rate value. + * + * Returns adequate value to be latter written into bare metal register address. + * Take into consideration that this returns a predefined value. + * + * HAL_LL_I2C_MASTER_SPEED_100K -- 100Kbit/s + * HAL_LL_I2C_MASTER_SPEED_400K -- 400Kbit/s + * HAL_LL_I2C_MASTER_SPEED_1M -- 1Mbit/s + * HAL_LL_I2C_MASTER_SPEED_3M2 -- 3.2Mbit/s + */ +static uint32_t hal_ll_i2c_get_speed( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Enable clock for I2C1 module on hardware level. + * + * Initializes I2C1 module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] hal_ll_state - True/False -- Init/De-init + * + * @return None + */ +static inline void hal_ll_i2c1_set_clock( bool hal_ll_state ); + +/** + * @brief Enable clock for I2C2 module on hardware level. + * + * Initializes I2C2 module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] hal_ll_state - True/False -- Init/De-init + * + * @return None + */ +static inline void hal_ll_i2c2_set_clock( bool hal_ll_state ); + +/** + * @brief Enable clock for I2C3 module on hardware level. + * + * Initializes I2C3 module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] hal_ll_state - True/False -- Init/De-init + * + * @return None + */ +static inline void hal_ll_i2c3_set_clock( bool hal_ll_state ); + +/** + * @brief Enable clock for I2C4 module on hardware level. + * + * Initializes I2C4 module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] hal_ll_state - True/False -- Init/De-init + * + * @return None + */ +static inline void hal_ll_i2c4_set_clock( bool hal_ll_state ); + +/** + * @brief Enable clock for I2C module on hardware level. + * + * Initializes I2C module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_stat - True(enable clock)/False(disable clock). + * + * @return None + */ +static void hal_ll_i2c_master_set_clock( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Initialize I2C module on hardware level. + * + * Initializes I2C module on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] map - Object specific context handler. + * @return hal_ll_err_t Module specific return values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_hw_init( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * I2C SCL and SDA pins. + * + * @param[in] module_index I2C HW module index -- 0,1,2... + * @param[in] *index_list Array with SCL and SDA map index values + * and module number + * + * @return None + */ +static void hal_ll_i2c_master_map_pins( uint8_t module_index, hal_ll_i2c_pin_id *index_list ); + +/** + * @brief Sets I2C pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if I2C is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_state - Init/De-init + * + * @return None + */ +static void hal_ll_i2c_master_alternate_functions_set_state( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Full I2C module initialization procedure. + * + * Initializes I2C module on hardware level, based on beforehand + * set configuration and module handler. Sets adequate pin alternate functions. + * Initializes module clock. + * + * @param[in] map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Configure I2C module for data transfer. + * + * @param[in] hal_ll_hw_reg - I2C module base address. + * @param[in] config - I2C config bits. + * @return void None. + */ +static void hal_ll_i2c_master_configure_transfer( hal_ll_i2c_base_handle_t *hal_ll_hw_reg, uint32_t config ); + +/** + * @brief Reset value of I2C CR2 register. + * + * @param[in] hal_ll_hw_reg - I2C module base address. + * @returnl none + */ +static void hal_ll_i2c_master_reset_cr2( hal_ll_i2c_base_handle_t *hal_ll_hw_reg ); + +/** + * @brief Generates start signal on I2C bus. + * + * Generates a start signal on the I2C bus. + * + * @param[in] map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_master_start( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Generates stop signal on I2C bus. + * + * Generates a stop signal on the I2C bus. + * + * @param[in] map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_master_stop( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Perform a read on the I2C bus. + * + * Initializes I2C module on hardware level, if not initialized beforehand + * and continues to perform a read operation on the bus. + * + * @param[in] map - Object specific context handler. + * @param[in] readDatabuf - Pointer to data buffer. + * @param[in] lenReadData - Number of data to be read. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *read_data_buf, size_t len_read_data, hal_ll_i2c_master_end_mode_t mode ); + +/** + * @brief Perform a write on the I2C bus. + * + * Initializes I2C module on hardware level, if not initialized beforehand + * and continues to perform a write operation on the bus. + * + * @param[in] map - Object specific context handler. + * @param[in] writeDatabuf - Pointer to data buffer. + * @param[in] lenWriteData - Number of data to be written. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *write_data_buf, size_t len_write_data, hal_ll_i2c_master_end_mode_t mode ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_i2c_master_register_handle( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_master_handle_register_t *handle_map, uint8_t *hal_module_id ) { + + hal_ll_i2c_pin_id index_list[I2C_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + uint16_t pin_check_result; + + // Check if pins are valid + if ( (pin_check_result = hal_ll_i2c_master_check_pins( scl, sda, &index_list, handle_map )) == HAL_LL_PIN_NC ) { + return HAL_LL_I2C_MASTER_WRONG_PINS; + }; + + if ( (hal_ll_i2c_hw_specifics_map[pin_check_result].pins.pin_scl.pin_name != scl) || + (hal_ll_i2c_hw_specifics_map[pin_check_result].pins.pin_sda.pin_name != sda) ) + { + hal_ll_i2c_master_alternate_functions_set_state( &hal_ll_i2c_hw_specifics_map[ pin_check_result ], false ); + + hal_ll_i2c_master_map_pins( pin_check_result, &index_list ); + + hal_ll_i2c_master_alternate_functions_set_state( &hal_ll_i2c_hw_specifics_map[ pin_check_result ], true ); + + handle_map[pin_check_result].init_ll_state = false; + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[pin_check_result].hal_ll_i2c_master_handle = (handle_t *)&hal_ll_i2c_hw_specifics_map[pin_check_result].base; + + handle_map[pin_check_result].hal_ll_i2c_master_handle = (handle_t *)&hal_ll_module_state[pin_check_result].hal_ll_i2c_master_handle; + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_i2c( handle_t *handle ) { + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + hal_ll_i2c_master_handle_register_t *hal_handle = (hal_ll_i2c_master_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_i2c_hw_specifics_map_local->module_index; + + hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_local ); + + hal_ll_module_state[pin_check_result].hal_ll_i2c_master_handle = (handle_t *)&hal_ll_i2c_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_i2c_master_set_speed( handle_t *handle, uint32_t speed ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + low_level_handle->init_ll_state = false; + + hal_ll_i2c_hw_specifics_map_local->speed = speed; + + if ( hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_local ) != HAL_LL_I2C_MASTER_SUCCESS ) { + return HAL_LL_I2C_MASTER_TIMEOUT_INIT; + } + + low_level_handle->init_ll_state = true; + + return hal_ll_i2c_hw_specifics_map_local->speed; +} + +void hal_ll_i2c_master_set_timeout( handle_t *handle, uint16_t timeout ) { + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + if( hal_ll_i2c_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + hal_ll_i2c_hw_specifics_map_local->timeout = timeout; + } +} + +void hal_ll_i2c_master_set_slave_address( handle_t *handle, uint8_t addr ) { + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + if( hal_ll_i2c_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + hal_ll_i2c_hw_specifics_map_local->address = addr; + } +} + +hal_ll_err_t hal_ll_i2c_master_read( handle_t *handle, uint8_t *read_data_buf, size_t len_read_data ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + return hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_local, read_data_buf, len_read_data, HAL_LL_I2C_MASTER_END_MODE_STOP ); +} + +hal_ll_err_t hal_ll_i2c_master_write( handle_t *handle, uint8_t *write_data_buf, size_t len_write_data ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + return hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_local, write_data_buf, len_write_data, HAL_LL_I2C_MASTER_END_MODE_STOP ); +} + +hal_ll_err_t hal_ll_i2c_master_write_then_read( handle_t *handle, uint8_t *write_data_buf, size_t len_write_data, uint8_t *read_data_buf, size_t len_read_data ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + if( hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_local, write_data_buf, len_write_data, HAL_LL_I2C_MASTER_WRITE_THEN_READ ) != NULL ) { + return HAL_LL_I2C_MASTER_TIMEOUT_WRITE; + } + + /** + * @note Wait for drivers to set-up + * correctly. + **/ + #ifdef __TFT_RESISTIVE_TSC2003__ + Delay_22us(); + #endif + + if( hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_local, read_data_buf, len_read_data, HAL_LL_I2C_MASTER_WRITE_THEN_READ ) != NULL ) { + return HAL_LL_I2C_MASTER_TIMEOUT_READ; + } + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +void hal_ll_i2c_master_close( handle_t *handle ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + if( low_level_handle->hal_ll_i2c_master_handle != NULL ) { + low_level_handle->hal_ll_i2c_master_handle = NULL; + low_level_handle->hal_drv_i2c_master_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_i2c_hw_specifics_map_local->address = 0; + hal_ll_i2c_hw_specifics_map_local->timeout = HAL_LL_I2C_DEFAULT_PASS_COUNT; + hal_ll_i2c_hw_specifics_map_local->speed = HAL_LL_I2C_MASTER_SPEED_100K; + + hal_ll_i2c_master_set_clock(hal_ll_i2c_hw_specifics_map_local, true); + hal_ll_i2c_master_alternate_functions_set_state( hal_ll_i2c_hw_specifics_map_local, false ); + hal_ll_i2c_master_set_clock(hal_ll_i2c_hw_specifics_map_local, false); + + hal_ll_i2c_hw_specifics_map_local->pins.pin_scl.pin_name = HAL_LL_PIN_NC; + hal_ll_i2c_hw_specifics_map_local->pins.pin_sda.pin_name = HAL_LL_PIN_NC; + hal_ll_i2c_hw_specifics_map_local->pins.pin_scl.pin_af = 0; + hal_ll_i2c_hw_specifics_map_local->pins.pin_sda.pin_af = 0; + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static hal_ll_err_t hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *read_data_buf, size_t len_read_data, hal_ll_i2c_master_end_mode_t mode ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct(map->base); + uint16_t time_counter = map->timeout; + size_t transfer_counter = NULL; + uint8_t status = NULL; + + /** + * @note When R/W = 0, the input sample acquisition period starts + * on the falling edge of SCL once the C0 bit of the command + * byte has been latched, and ends when a Stop or + * repeated Start condition has been issued. + **/ + #ifdef __TFT_RESISTIVE_TSC2003__ + Delay_1ms(); + #endif + + hal_ll_i2c_master_configure_transfer ( map->base, + ( map->address << 1 & HAL_LL_I2C_CR2_SADD ) | + ( len_read_data << 16 & HAL_LL_I2C_CR2_NBYTES ) | + HAL_LL_I2C_CR2_RD_WRN | + HAL_LL_I2C_CR2_START + ); + + for ( transfer_counter; transfer_counter < len_read_data; transfer_counter++ ) { + while ( !( check_reg_bit( &( hal_ll_hw_reg->isr ), HAL_LL_I2C_RXNE_BIT ) ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_READ; + } + } + read_data_buf[ transfer_counter ] = hal_ll_hw_reg->rxdr; + } + + if ( ( mode == HAL_LL_I2C_MASTER_END_MODE_STOP ) || ( mode == HAL_LL_I2C_MASTER_WRITE_THEN_READ ) ) { + status = hal_ll_i2c_master_stop( map ); + } else { + status = hal_ll_i2c_master_start( map ); + } + + if( status != HAL_LL_I2C_MASTER_SUCCESS ) { + return status; + } + + hal_ll_i2c_master_reset_cr2( hal_ll_hw_reg ); + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static hal_ll_err_t hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *write_data_buf, size_t len_write_data, hal_ll_i2c_master_end_mode_t mode ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct(map->base); + uint16_t time_counter = map->timeout; + size_t transfer_counter = NULL; + uint8_t status = NULL; + + hal_ll_i2c_master_configure_transfer ( map->base, + ( map->address << 1 & HAL_LL_I2C_CR2_SADD ) | + ( len_write_data << 16 & HAL_LL_I2C_CR2_NBYTES ) | + !HAL_LL_I2C_CR2_RD_WRN | + HAL_LL_I2C_CR2_START + ); + + for ( transfer_counter; transfer_counter < len_write_data; transfer_counter++ ) + { + while ( !( check_reg_bit( &( hal_ll_hw_reg->isr ), HAL_LL_I2C_TXIS_BIT ) ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_WRITE; + } + } + hal_ll_hw_reg->txdr = write_data_buf[ transfer_counter ]; + } + + time_counter = map->timeout; + while ( !( check_reg_bit( &( hal_ll_hw_reg->isr ), HAL_LL_I2C_TXE_BIT ) ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_WRITE; + } + } + + if ( mode == HAL_LL_I2C_MASTER_END_MODE_STOP ) + { + hal_ll_i2c_master_stop( map ); + } + + hal_ll_i2c_master_reset_cr2( hal_ll_hw_reg ); + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static void hal_ll_i2c_master_configure_transfer( hal_ll_i2c_base_handle_t *hal_ll_hw_reg, uint32_t config ) { + uint32_t reg = 0; + + // Clear last set slave address + hal_ll_hw_reg->cr2 &= ~HAL_LL_I2C_CR2_SADD; + + reg = hal_ll_hw_reg->cr2; + reg &= ~( uint32_t )( + ( HAL_LL_I2C_CR2_SADD ) | + ( HAL_LL_I2C_CR2_NBYTES ) | + ( HAL_LL_I2C_CR2_RELOAD ) | + ( HAL_LL_I2C_CR2_AUTOEND ) | + ( HAL_LL_I2C_CR2_RD_WRN ) | + ( HAL_LL_I2C_CR2_START ) | + ( HAL_LL_I2C_CR2_STOP ) + ); + + reg |= config; + hal_ll_hw_reg->cr2 = reg; +} + +static void hal_ll_i2c_master_reset_cr2( hal_ll_i2c_base_handle_t *hal_ll_hw_reg ) { + hal_ll_hw_reg->cr2 &= ~( uint32_t ) + ( + HAL_LL_I2C_SADD_MASK | + HAL_LL_I2C_HEAD10R_MASK | + HAL_LL_I2C_NBYTES_MASK | + HAL_LL_I2C_RELOAD_MASK | + HAL_LL_I2C_RD_WRN_MASK + ); +} + +static hal_ll_err_t hal_ll_i2c_master_start( hal_ll_i2c_hw_specifics_map_t *map ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct(map->base); + uint16_t loop_index = HAL_LL_I2C_LOOP_INDEX; + + set_reg_bit( &(hal_ll_hw_reg->cr2), HAL_LL_I2C_CR2_START_BIT ); + + if ( check_reg_bit( &( hal_ll_hw_reg->isr ), HAL_LL_I2C_ARLO_BIT ) ) + return HAL_LL_I2C_MASTER_ARBITRATION_LOST; + + while ( loop_index-- ) + assembly(nop); + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static hal_ll_err_t hal_ll_i2c_master_stop( hal_ll_i2c_hw_specifics_map_t *map ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = ( hal_ll_i2c_base_handle_t* )map->base; + uint16_t time_counter = map->timeout; + uint32_t loop_index = HAL_LL_I2C_LOOP_INDEX; + + set_reg_bit( &(hal_ll_hw_reg->cr2), HAL_LL_I2C_CR2_STOP_BIT ); + + while ( !( hal_ll_hw_reg->isr & HAL_LL_I2C_ISR_STOPF_BIT ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_STOP; + } + } + + if ( map->timeout < HAL_LL_I2C_LOOP_INDEX ) { + while ( loop_index-- ) + assembly(nop); + } + + hal_ll_hw_reg->isr &= ~HAL_LL_I2C_ISR_STOPF_BIT; + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static hal_ll_pin_name_t hal_ll_i2c_master_check_pins( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_pin_id *index_list, hal_ll_i2c_master_handle_register_t *handle_map ) { + static const uint16_t scl_map_size = ( sizeof( hal_ll_i2c_scl_map ) / sizeof( hal_ll_i2c_pin_map_t ) ); + static const uint16_t sda_map_size = ( sizeof( hal_ll_i2c_sda_map ) / sizeof( hal_ll_i2c_pin_map_t ) ); + uint8_t hal_ll_module_id = 0; + uint8_t index_counter = 0; + uint16_t scl_index; + uint16_t sda_index; + + if ( (HAL_LL_PIN_NC == scl) || (HAL_LL_PIN_NC == sda) ) { + return HAL_LL_PIN_NC; + } + + for ( scl_index = 0; scl_index < scl_map_size; scl_index++ ) { + if ( hal_ll_i2c_scl_map[ scl_index ].pin == scl ) { + for ( sda_index = 0; sda_index < sda_map_size; sda_index++ ) { + if ( hal_ll_i2c_sda_map[ sda_index ].pin == sda ) { + if ( hal_ll_i2c_scl_map[ scl_index ].module_index == hal_ll_i2c_sda_map[ sda_index ].module_index ) { + // Get module number + hal_ll_module_id = hal_ll_i2c_scl_map[ scl_index ].module_index; + // Map pin names + index_list[hal_ll_module_id].pin_scl = scl_index; + index_list[hal_ll_module_id].pin_sda = sda_index; + + // Check if module is taken + if ( NULL == handle_map[ hal_ll_module_id ].hal_drv_i2c_master_handle ) { + return hal_ll_module_id; + } else if ( I2C_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static hal_ll_i2c_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof(hal_ll_i2c_master_handle_register_t)); + static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof(hal_ll_i2c_master_handle_register_t)); + + while( hal_ll_module_count-- ) { + if (hal_ll_i2c_get_base_from_hal_handle == hal_ll_i2c_hw_specifics_map[hal_ll_module_count].base) { + return &hal_ll_i2c_hw_specifics_map[hal_ll_module_count]; + } + } + + return &hal_ll_i2c_hw_specifics_map[hal_ll_module_error]; +} + +static void hal_ll_i2c_master_set_clock( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ) { + switch ( map->module_index ) + { + #if defined(I2C_MODULE_1) + case ( hal_ll_i2c_module_num(I2C_MODULE_1) ): + hal_ll_i2c1_set_clock( hal_ll_state ); + break; + #endif + + #if defined(I2C_MODULE_2) + case ( hal_ll_i2c_module_num(I2C_MODULE_2) ): + hal_ll_i2c2_set_clock( hal_ll_state ); + break; + #endif + + #if defined(I2C_MODULE_3) + case ( hal_ll_i2c_module_num(I2C_MODULE_3) ): + hal_ll_i2c3_set_clock( hal_ll_state ); + break; + #endif + + #if defined(I2C_MODULE_4) + case ( hal_ll_i2c_module_num(I2C_MODULE_4) ): + hal_ll_i2c4_set_clock( hal_ll_state ); + break; + #endif + + + default: + break; + } +} + +static void hal_ll_i2c_master_map_pins( uint8_t module_index, hal_ll_i2c_pin_id *index_list ) { + // Map new pins + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_scl.pin_name = hal_ll_i2c_scl_map[ index_list[module_index].pin_scl ].pin; + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_sda.pin_name = hal_ll_i2c_sda_map[ index_list[module_index].pin_sda ].pin; + // SCL and SDA could have different alternate function settings, hence save both AF values + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_scl.pin_af = hal_ll_i2c_scl_map[ index_list[module_index].pin_scl ].af; + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_sda.pin_af = hal_ll_i2c_sda_map[ index_list[module_index].pin_sda ].af; +} + +static void hal_ll_i2c_master_alternate_functions_set_state( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ) { + module_struct module; + + if( (map->pins.pin_scl.pin_name != HAL_LL_PIN_NC) && (map->pins.pin_sda.pin_name != HAL_LL_PIN_NC) ) { + module.pins[0] = VALUE( map->pins.pin_scl.pin_name, map->pins.pin_scl.pin_af ); + module.pins[1] = VALUE( map->pins.pin_sda.pin_name, map->pins.pin_sda.pin_af ); + module.pins[2] = GPIO_MODULE_STRUCT_END; + + module.configs[0] = HAL_LL_I2C_AF_CONFIG; + module.configs[1] = HAL_LL_I2C_AF_CONFIG; + module.configs[2] = GPIO_MODULE_STRUCT_END; + + hal_ll_gpio_module_struct_init( &module, hal_ll_state ); + } +} + +static uint32_t hal_ll_i2c_get_speed( hal_ll_i2c_hw_specifics_map_t *map ) { + if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_FAST ) { + if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_STANDARD ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_100K; + return HAL_LL_I2C_100K; + } else if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_FULL ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_400K; + return HAL_LL_I2C_400K; + } else if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_FAST ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_1M; + return HAL_LL_I2C_1M; + } else { + map->speed = HAL_LL_I2C_MASTER_SPEED_100K; + return HAL_LL_I2C_100K; + } + } else { + if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_100K ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_100K; + return HAL_LL_I2C_100K; + } else if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_400K ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_400K; + return HAL_LL_I2C_400K; + } else if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_1M ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_1M; + return HAL_LL_I2C_1M; + } else { + map->speed = HAL_LL_I2C_MASTER_SPEED_1M; + return HAL_LL_I2C_1M; + } + } +} +static inline void hal_ll_i2c1_set_clock( bool hal_ll_state ) { + if ( hal_ll_state ) { + set_reg_bit( _RCC_APB1ENR1, HAL_LL_I2C1EN_BIT ); + set_reg_bit( _RCC_CCIPR, HAL_LL_I2C1SEL1_BIT ); + } else { + clear_reg_bit( _RCC_APB1ENR1, HAL_LL_I2C1EN_BIT ); + clear_reg_bit( _RCC_CCIPR, HAL_LL_I2C1SEL1_BIT ); + } +} + + +static inline void hal_ll_i2c2_set_clock( bool hal_ll_state ) { + if ( hal_ll_state ) { + set_reg_bit( _RCC_APB1ENR1, HAL_LL_I2C2EN_BIT ); + set_reg_bit( _RCC_CCIPR, HAL_LL_I2C2SEL1_BIT ); + } else { + clear_reg_bit( _RCC_APB1ENR1, HAL_LL_I2C2EN_BIT ); + clear_reg_bit( _RCC_CCIPR, HAL_LL_I2C2SEL1_BIT ); + } +} + + +static inline void hal_ll_i2c3_set_clock( bool hal_ll_state ) { + if ( hal_ll_state ) { + set_reg_bit( _RCC_APB1ENR1, HAL_LL_I2C3EN_BIT ); + set_reg_bit( _RCC_CCIPR, HAL_LL_I2C3SEL1_BIT ); + } else { + clear_reg_bit( _RCC_APB1ENR1, HAL_LL_I2C3EN_BIT ); + clear_reg_bit( _RCC_CCIPR, HAL_LL_I2C3SEL1_BIT ); + } +} + + +static inline void hal_ll_i2c4_set_clock( bool hal_ll_state ) { + if ( hal_ll_state ) { + set_reg_bit( _RCC_APB1ENR2, HAL_LL_I2C4EN_BIT ); + set_reg_bit( _RCC_CCIPR2, HAL_LL_I2C4SEL1_BIT ); + } else { + clear_reg_bit( _RCC_APB1ENR2, HAL_LL_I2C4EN_BIT ); + clear_reg_bit( _RCC_CCIPR2, HAL_LL_I2C4SEL1_BIT ); + } +} + + + +static hal_ll_err_t hal_ll_i2c_hw_init( hal_ll_i2c_hw_specifics_map_t *map ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct(map->base); + uint16_t time_counter = map->timeout; + + clear_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_I2C_PE_BIT ); + while ( check_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_I2C_PE_BIT ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_INIT; + } + } + + hal_ll_hw_reg->cr1 &= HAL_LL_I2C_FILTERS_OFF; + + hal_ll_hw_reg->timingr = hal_ll_i2c_get_speed( map ); + + hal_ll_hw_reg->cr1 |= HAL_LL_I2C_CR1_RXTX_INT; + + set_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_I2C_PE_BIT ); + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static hal_ll_err_t hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_t *map ) { + hal_ll_i2c_master_set_clock( map, true ); + + return hal_ll_i2c_hw_init( map ); +} +// ------------------------------------------------------------------------- END + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_88/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_88/CMakeLists.cmake new file mode 100644 index 000000000..ce01552f5 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_88/CMakeLists.cmake @@ -0,0 +1,9 @@ +if(${MCU_NAME} MATCHES "^STM32G491CC$|^STM32G491KC$|^STM32G491RC$|^STM32G491VC$|^STM32G491MC$|^STM32G491CE$|^STM32G491KE$|^STM32G491RE$|^STM32G491VE$|^STM32G491ME$") + set(i2c_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_i2c_master.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_88") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_88") + list(APPEND hal_ll_def_list "STM32G4xx") + list(APPEND hal_ll_def_list "STM32G49xx") + list(APPEND hal_ll_def_list "STM32G491xx") + set(i2c_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/i2c/hal_ll_i2c_pin_map/implementations/doc_ds_88") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_88/hal_ll_i2c_master.c b/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_88/hal_ll_i2c_master.c new file mode 100644 index 000000000..5e1ea38a2 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_88/hal_ll_i2c_master.c @@ -0,0 +1,976 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_i2c_master.c + * @brief I2C master HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_rcc.h" +#include "hal_ll_gpio.h" +#include "hal_ll_i2c_master.h" +#include "hal_ll_i2c_pin_map.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_i2c_master_handle_register_t hal_ll_module_state[I2C_MODULE_COUNT] = { (handle_t *)NULL, (handle_t *)NULL, false }; + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_i2c_get_module_state_address ((hal_ll_i2c_master_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_i2c_get_handle (hal_ll_i2c_master_handle_register_t *)hal_ll_i2c_get_module_state_address->hal_ll_i2c_master_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_i2c_get_base_struct(_handle) ((hal_ll_i2c_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_i2c_get_base_from_hal_handle ((hal_ll_i2c_hw_specifics_map_t *)((hal_ll_i2c_master_handle_register_t *)\ + (((hal_ll_i2c_master_handle_register_t *)(handle))->hal_ll_i2c_master_handle))->hal_ll_i2c_master_handle)->base + +/*!< @brief Default I2C bit-rate if no speed is set */ +#define HAL_LL_I2C_MASTER_SPEED_100K 100000UL +#define HAL_LL_I2C_MASTER_SPEED_400K 400000UL +#define HAL_LL_I2C_MASTER_SPEED_1M 1000000UL + +/*!< @brief Default pass count value upon reset */ +#define HAL_LL_I2C_DEFAULT_PASS_COUNT 0xFFFFU + +/*!< @brief Macro used for timeout */ +#define HAL_LL_I2C_LOOP_INDEX 10000U + +/*!< @brief Macros defining register bit location */ +#define HAL_LL_I2C1EN_BIT 21 + +#define HAL_LL_I2C2EN_BIT 22 + +#define HAL_LL_I2C3EN_BIT 30 + +#define HAL_LL_I2C1SEL0_BIT 12 + +#define HAL_LL_I2C1SEL1_BIT 13 + +#define HAL_LL_I2C2SEL0_BIT 14 + +#define HAL_LL_I2C2SEL1_BIT 15 + +#define HAL_LL_I2C3SEL0_BIT 16 + +#define HAL_LL_I2C3SEL1_BIT 17 + + + + +#define HAL_LL_I2C_100K 0x30420F13 //?????????????????? +#define HAL_LL_I2C_400K 0x10320309 //?????????????????? +#define HAL_LL_I2C_1M 0x00200204 //?????????????????? + +#define HAL_LL_I2C_PE_BIT 0 +#define HAL_LL_I2C_CR2_STOP_BIT 14 +#define HAL_LL_I2C_CR2_START_BIT 13 +#define HAL_LL_I2C_ISR_STOPF_BIT 5 +#define HAL_LL_I2C_ISR_BUSY_BIT 15 +#define HAL_LL_I2C_ARLO_BIT 9 +#define HAL_LL_I2C_RXNE_BIT 2 +#define HAL_LL_I2C_TXIS_BIT 1 +#define HAL_LL_I2C_TXE_BIT 0 + +/*!< @brief Macros defining register bit masks */ +#define HAL_LL_I2C_CR1_RXTX_INT 0x6 +#define HAL_LL_I2C_CR2_STOP 0x4000UL +#define HAL_LL_I2C_CR2_START 0x2000U +#define HAL_LL_I2C_CR2_SADD 0x3FFU +#define HAL_LL_I2C_CR2_NBYTES 0xFF0000UL +#define HAL_LL_I2C_CR2_RD_WRN 0x400U +#define HAL_LL_I2C_CR2_RELOAD 0x1000000UL +#define HAL_LL_I2C_CR2_AUTOEND 0x2000000UL +#define HAL_LL_I2C_FILTERS_OFF 0xFFFFE0FFUL +#define HAL_LL_I2C_SADD_MASK 0x3FFUL +#define HAL_LL_I2C_HEAD10R_MASK 0x1000UL +#define HAL_LL_I2C_NBYTES_MASK 0xFF0000UL +#define HAL_LL_I2C_RELOAD_MASK 0x1000000UL +#define HAL_LL_I2C_RD_WRN_MASK 0x400UL + +/*!< @brief Macros used for module pin checking */ +#define HAL_LL_I2C_SCL_PIN 0 +#define HAL_LL_I2C_SDA_PIN 1 +#define HAL_LL_I2C_MODULE_PIN_COUNT 2 + +/*!< @brief Macro used for setting pin alternate functions */ +#define HAL_LL_I2C_AF_CONFIG (GPIO_CFG_MODE_ALT_FUNCTION | GPIO_CFG_SPEED_HIGH | GPIO_CFG_OTYPE_OD) + +// -------------------------------------------------------------- PRIVATE TYPES +/*!< @brief I2C register structure */ +typedef struct +{ + hal_ll_base_addr_t cr1; + hal_ll_base_addr_t cr2; + hal_ll_base_addr_t oar1; + hal_ll_base_addr_t oar2; + hal_ll_base_addr_t timingr; + hal_ll_base_addr_t timeoutr; + hal_ll_base_addr_t isr; + hal_ll_base_addr_t icr; + hal_ll_base_addr_t pecr; + hal_ll_base_addr_t rxdr; + hal_ll_base_addr_t txdr; + +} hal_ll_i2c_base_handle_t; + +/*!< @brief I2C hw specific structure */ +typedef struct +{ + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + hal_ll_i2c_pins_t pins; + uint32_t speed; + uint8_t address; + uint16_t timeout; +} hal_ll_i2c_hw_specifics_map_t; + +/*!< @brief I2C hw specific module values */ +typedef struct +{ + uint16_t pin_scl; + uint16_t pin_sda; +} hal_ll_i2c_pin_id; + +/*!< @brief I2C hw specific error values */ +typedef enum +{ + HAL_LL_I2C_MASTER_SUCCESS = 0, + HAL_LL_I2C_MASTER_WRONG_PINS, + HAL_LL_I2C_MASTER_MODULE_ERROR, + + HAL_LL_I2C_MASTER_ERROR = (-1) +} hal_ll_i2c_master_err_t; + +/*!< @brief I2C end mode selection values */ +typedef enum +{ + HAL_LL_I2C_MASTER_END_MODE_RESTART = 0, + HAL_LL_I2C_MASTER_END_MODE_STOP, + HAL_LL_I2C_MASTER_WRITE_THEN_READ +} hal_ll_i2c_master_end_mode_t; + +/*!< @brief I2C timeout error values */ +typedef enum +{ + HAL_LL_I2C_MASTER_TIMEOUT_START = 1300, + HAL_LL_I2C_MASTER_TIMEOUT_STOP, + HAL_LL_I2C_MASTER_TIMEOUT_WRITE, + HAL_LL_I2C_MASTER_TIMEOUT_READ, + HAL_LL_I2C_MASTER_ARBITRATION_LOST, + HAL_LL_I2C_MASTER_TIMEOUT_INIT +} hal_ll_i2c_master_timeout_t; + +/** + * @brief Enum containing predefined module standard speed values. + * + * Enum values: + * HAL_LL_I2C_MASTER_SPEED_STANDARD -- Speed set at 100K + * HAL_LL_I2C_MASTER_SPEED_FULL -- Speed set at 400K + * HAL_LL_I2C_MASTER_SPEED_FAST -- Speed set at 1M + */ +typedef enum +{ + HAL_LL_I2C_MASTER_SPEED_STANDARD = 0, + HAL_LL_I2C_MASTER_SPEED_FULL, + HAL_LL_I2C_MASTER_SPEED_FAST +} hal_ll_i2c_master_speed_t; + +// ------------------------------------------------------------------ VARIABLES +/*!< @brief I2C hardware specific info */ +static hal_ll_i2c_hw_specifics_map_t hal_ll_i2c_hw_specifics_map[] = +{ + #ifdef I2C_MODULE_1 + {HAL_LL_I2C1_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_1), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, + #endif + + #ifdef I2C_MODULE_2 + {HAL_LL_I2C2_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_2), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, + #endif + + #ifdef I2C_MODULE_3 + {HAL_LL_I2C3_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_3), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, + #endif + + + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, 0, 0} +}; + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_i2c_master_handle_register_t *low_level_handle; +static volatile hal_ll_i2c_hw_specifics_map_t *hal_ll_i2c_hw_specifics_map_local; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Check if pins are adequate. + * + * Checks scl and sda pins the user has passed with pre-defined + * pins in scl and sda maps. Take into consideration that module + * index numbers have to be the same for both pins. + * + * @param[in] scl - SCL pre-defined pin name. + * @param[in] sda - SDA pre-defined pin name. + * @param[in] *index_list - Index list address + * @return hal_ll_pin_name_t Module index based on pins. + * + * Returns pre-defined module index from pin maps, if pins + * are adequate. + */ +static hal_ll_pin_name_t hal_ll_i2c_master_check_pins( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_pin_id *index_list, hal_ll_i2c_master_handle_register_t *handle_map ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_i2c_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_i2c_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_i2c_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Get adequate I2C bit-rate value. + * + * Returns one of pre-defined bit-rate values, + * or the closest bit-rate based on bit_rate + * value passed to the function. + * + * @param[in] bit_rate - I2C bit rate. + * @return uint32_t Adequate bit-rate value. + * + * Returns adequate value to be latter written into bare metal register address. + * Take into consideration that this returns a predefined value. + * + * HAL_LL_I2C_MASTER_SPEED_100K -- 100Kbit/s + * HAL_LL_I2C_MASTER_SPEED_400K -- 400Kbit/s + * HAL_LL_I2C_MASTER_SPEED_1M -- 1Mbit/s + * HAL_LL_I2C_MASTER_SPEED_3M2 -- 3.2Mbit/s + */ +static uint32_t hal_ll_i2c_get_speed( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Enable clock for I2C1 module on hardware level. + * + * Initializes I2C1 module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] hal_ll_state - True/False -- Init/De-init + * + * @return None + */ +static inline void hal_ll_i2c1_set_clock( bool hal_ll_state ); + +/** + * @brief Enable clock for I2C2 module on hardware level. + * + * Initializes I2C2 module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] hal_ll_state - True/False -- Init/De-init + * + * @return None + */ +static inline void hal_ll_i2c2_set_clock( bool hal_ll_state ); + +/** + * @brief Enable clock for I2C3 module on hardware level. + * + * Initializes I2C3 module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] hal_ll_state - True/False -- Init/De-init + * + * @return None + */ +static inline void hal_ll_i2c3_set_clock( bool hal_ll_state ); + +/** + * @brief Enable clock for I2C module on hardware level. + * + * Initializes I2C module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_stat - True(enable clock)/False(disable clock). + * + * @return None + */ +static void hal_ll_i2c_master_set_clock( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Initialize I2C module on hardware level. + * + * Initializes I2C module on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] map - Object specific context handler. + * @return hal_ll_err_t Module specific return values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_hw_init( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * I2C SCL and SDA pins. + * + * @param[in] module_index I2C HW module index -- 0,1,2... + * @param[in] *index_list Array with SCL and SDA map index values + * and module number + * + * @return None + */ +static void hal_ll_i2c_master_map_pins( uint8_t module_index, hal_ll_i2c_pin_id *index_list ); + +/** + * @brief Sets I2C pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if I2C is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_state - Init/De-init + * + * @return None + */ +static void hal_ll_i2c_master_alternate_functions_set_state( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Full I2C module initialization procedure. + * + * Initializes I2C module on hardware level, based on beforehand + * set configuration and module handler. Sets adequate pin alternate functions. + * Initializes module clock. + * + * @param[in] map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Configure I2C module for data transfer. + * + * @param[in] hal_ll_hw_reg - I2C module base address. + * @param[in] config - I2C config bits. + * @return void None. + */ +static void hal_ll_i2c_master_configure_transfer( hal_ll_i2c_base_handle_t *hal_ll_hw_reg, uint32_t config ); + +/** + * @brief Reset value of I2C CR2 register. + * + * @param[in] hal_ll_hw_reg - I2C module base address. + * @returnl none + */ +static void hal_ll_i2c_master_reset_cr2( hal_ll_i2c_base_handle_t *hal_ll_hw_reg ); + +/** + * @brief Generates start signal on I2C bus. + * + * Generates a start signal on the I2C bus. + * + * @param[in] map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_master_start( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Generates stop signal on I2C bus. + * + * Generates a stop signal on the I2C bus. + * + * @param[in] map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_master_stop( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Perform a read on the I2C bus. + * + * Initializes I2C module on hardware level, if not initialized beforehand + * and continues to perform a read operation on the bus. + * + * @param[in] map - Object specific context handler. + * @param[in] readDatabuf - Pointer to data buffer. + * @param[in] lenReadData - Number of data to be read. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *read_data_buf, size_t len_read_data, hal_ll_i2c_master_end_mode_t mode ); + +/** + * @brief Perform a write on the I2C bus. + * + * Initializes I2C module on hardware level, if not initialized beforehand + * and continues to perform a write operation on the bus. + * + * @param[in] map - Object specific context handler. + * @param[in] writeDatabuf - Pointer to data buffer. + * @param[in] lenWriteData - Number of data to be written. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *write_data_buf, size_t len_write_data, hal_ll_i2c_master_end_mode_t mode ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_i2c_master_register_handle( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_master_handle_register_t *handle_map, uint8_t *hal_module_id ) { + + hal_ll_i2c_pin_id index_list[I2C_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + uint16_t pin_check_result; + + // Check if pins are valid + if ( (pin_check_result = hal_ll_i2c_master_check_pins( scl, sda, &index_list, handle_map )) == HAL_LL_PIN_NC ) { + return HAL_LL_I2C_MASTER_WRONG_PINS; + }; + + if ( (hal_ll_i2c_hw_specifics_map[pin_check_result].pins.pin_scl.pin_name != scl) || + (hal_ll_i2c_hw_specifics_map[pin_check_result].pins.pin_sda.pin_name != sda) ) + { + hal_ll_i2c_master_alternate_functions_set_state( &hal_ll_i2c_hw_specifics_map[ pin_check_result ], false ); + + hal_ll_i2c_master_map_pins( pin_check_result, &index_list ); + + hal_ll_i2c_master_alternate_functions_set_state( &hal_ll_i2c_hw_specifics_map[ pin_check_result ], true ); + + handle_map[pin_check_result].init_ll_state = false; + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[pin_check_result].hal_ll_i2c_master_handle = (handle_t *)&hal_ll_i2c_hw_specifics_map[pin_check_result].base; + + handle_map[pin_check_result].hal_ll_i2c_master_handle = (handle_t *)&hal_ll_module_state[pin_check_result].hal_ll_i2c_master_handle; + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_i2c( handle_t *handle ) { + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + hal_ll_i2c_master_handle_register_t *hal_handle = (hal_ll_i2c_master_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_i2c_hw_specifics_map_local->module_index; + + hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_local ); + + hal_ll_module_state[pin_check_result].hal_ll_i2c_master_handle = (handle_t *)&hal_ll_i2c_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_i2c_master_set_speed( handle_t *handle, uint32_t speed ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + low_level_handle->init_ll_state = false; + + hal_ll_i2c_hw_specifics_map_local->speed = speed; + + if ( hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_local ) != HAL_LL_I2C_MASTER_SUCCESS ) { + return HAL_LL_I2C_MASTER_TIMEOUT_INIT; + } + + low_level_handle->init_ll_state = true; + + return hal_ll_i2c_hw_specifics_map_local->speed; +} + +void hal_ll_i2c_master_set_timeout( handle_t *handle, uint16_t timeout ) { + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + if( hal_ll_i2c_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + hal_ll_i2c_hw_specifics_map_local->timeout = timeout; + } +} + +void hal_ll_i2c_master_set_slave_address( handle_t *handle, uint8_t addr ) { + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + if( hal_ll_i2c_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + hal_ll_i2c_hw_specifics_map_local->address = addr; + } +} + +hal_ll_err_t hal_ll_i2c_master_read( handle_t *handle, uint8_t *read_data_buf, size_t len_read_data ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + return hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_local, read_data_buf, len_read_data, HAL_LL_I2C_MASTER_END_MODE_STOP ); +} + +hal_ll_err_t hal_ll_i2c_master_write( handle_t *handle, uint8_t *write_data_buf, size_t len_write_data ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + return hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_local, write_data_buf, len_write_data, HAL_LL_I2C_MASTER_END_MODE_STOP ); +} + +hal_ll_err_t hal_ll_i2c_master_write_then_read( handle_t *handle, uint8_t *write_data_buf, size_t len_write_data, uint8_t *read_data_buf, size_t len_read_data ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + if( hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_local, write_data_buf, len_write_data, HAL_LL_I2C_MASTER_WRITE_THEN_READ ) != NULL ) { + return HAL_LL_I2C_MASTER_TIMEOUT_WRITE; + } + + /** + * @note Wait for drivers to set-up + * correctly. + **/ + #ifdef __TFT_RESISTIVE_TSC2003__ + Delay_22us(); + #endif + + if( hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_local, read_data_buf, len_read_data, HAL_LL_I2C_MASTER_WRITE_THEN_READ ) != NULL ) { + return HAL_LL_I2C_MASTER_TIMEOUT_READ; + } + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +void hal_ll_i2c_master_close( handle_t *handle ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + if( low_level_handle->hal_ll_i2c_master_handle != NULL ) { + low_level_handle->hal_ll_i2c_master_handle = NULL; + low_level_handle->hal_drv_i2c_master_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_i2c_hw_specifics_map_local->address = 0; + hal_ll_i2c_hw_specifics_map_local->timeout = HAL_LL_I2C_DEFAULT_PASS_COUNT; + hal_ll_i2c_hw_specifics_map_local->speed = HAL_LL_I2C_MASTER_SPEED_100K; + + hal_ll_i2c_master_set_clock(hal_ll_i2c_hw_specifics_map_local, true); + hal_ll_i2c_master_alternate_functions_set_state( hal_ll_i2c_hw_specifics_map_local, false ); + hal_ll_i2c_master_set_clock(hal_ll_i2c_hw_specifics_map_local, false); + + hal_ll_i2c_hw_specifics_map_local->pins.pin_scl.pin_name = HAL_LL_PIN_NC; + hal_ll_i2c_hw_specifics_map_local->pins.pin_sda.pin_name = HAL_LL_PIN_NC; + hal_ll_i2c_hw_specifics_map_local->pins.pin_scl.pin_af = 0; + hal_ll_i2c_hw_specifics_map_local->pins.pin_sda.pin_af = 0; + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static hal_ll_err_t hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *read_data_buf, size_t len_read_data, hal_ll_i2c_master_end_mode_t mode ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct(map->base); + uint16_t time_counter = map->timeout; + size_t transfer_counter = NULL; + uint8_t status = NULL; + + /** + * @note When R/W = 0, the input sample acquisition period starts + * on the falling edge of SCL once the C0 bit of the command + * byte has been latched, and ends when a Stop or + * repeated Start condition has been issued. + **/ + #ifdef __TFT_RESISTIVE_TSC2003__ + Delay_1ms(); + #endif + + hal_ll_i2c_master_configure_transfer ( map->base, + ( map->address << 1 & HAL_LL_I2C_CR2_SADD ) | + ( len_read_data << 16 & HAL_LL_I2C_CR2_NBYTES ) | + HAL_LL_I2C_CR2_RD_WRN | + HAL_LL_I2C_CR2_START + ); + + for ( transfer_counter; transfer_counter < len_read_data; transfer_counter++ ) { + while ( !( check_reg_bit( &( hal_ll_hw_reg->isr ), HAL_LL_I2C_RXNE_BIT ) ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_READ; + } + } + read_data_buf[ transfer_counter ] = hal_ll_hw_reg->rxdr; + } + + if ( ( mode == HAL_LL_I2C_MASTER_END_MODE_STOP ) || ( mode == HAL_LL_I2C_MASTER_WRITE_THEN_READ ) ) { + status = hal_ll_i2c_master_stop( map ); + } else { + status = hal_ll_i2c_master_start( map ); + } + + if( status != HAL_LL_I2C_MASTER_SUCCESS ) { + return status; + } + + hal_ll_i2c_master_reset_cr2( hal_ll_hw_reg ); + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static hal_ll_err_t hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *write_data_buf, size_t len_write_data, hal_ll_i2c_master_end_mode_t mode ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct(map->base); + uint16_t time_counter = map->timeout; + size_t transfer_counter = NULL; + uint8_t status = NULL; + + hal_ll_i2c_master_configure_transfer ( map->base, + ( map->address << 1 & HAL_LL_I2C_CR2_SADD ) | + ( len_write_data << 16 & HAL_LL_I2C_CR2_NBYTES ) | + !HAL_LL_I2C_CR2_RD_WRN | + HAL_LL_I2C_CR2_START + ); + + for ( transfer_counter; transfer_counter < len_write_data; transfer_counter++ ) + { + while ( !( check_reg_bit( &( hal_ll_hw_reg->isr ), HAL_LL_I2C_TXIS_BIT ) ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_WRITE; + } + } + hal_ll_hw_reg->txdr = write_data_buf[ transfer_counter ]; + } + + time_counter = map->timeout; + while ( !( check_reg_bit( &( hal_ll_hw_reg->isr ), HAL_LL_I2C_TXE_BIT ) ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_WRITE; + } + } + + if ( mode == HAL_LL_I2C_MASTER_END_MODE_STOP ) + { + hal_ll_i2c_master_stop( map ); + } + + hal_ll_i2c_master_reset_cr2( hal_ll_hw_reg ); + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static void hal_ll_i2c_master_configure_transfer( hal_ll_i2c_base_handle_t *hal_ll_hw_reg, uint32_t config ) { + uint32_t reg = 0; + + // Clear last set slave address + hal_ll_hw_reg->cr2 &= ~HAL_LL_I2C_CR2_SADD; + + reg = hal_ll_hw_reg->cr2; + reg &= ~( uint32_t )( + ( HAL_LL_I2C_CR2_SADD ) | + ( HAL_LL_I2C_CR2_NBYTES ) | + ( HAL_LL_I2C_CR2_RELOAD ) | + ( HAL_LL_I2C_CR2_AUTOEND ) | + ( HAL_LL_I2C_CR2_RD_WRN ) | + ( HAL_LL_I2C_CR2_START ) | + ( HAL_LL_I2C_CR2_STOP ) + ); + + reg |= config; + hal_ll_hw_reg->cr2 = reg; +} + +static void hal_ll_i2c_master_reset_cr2( hal_ll_i2c_base_handle_t *hal_ll_hw_reg ) { + hal_ll_hw_reg->cr2 &= ~( uint32_t ) + ( + HAL_LL_I2C_SADD_MASK | + HAL_LL_I2C_HEAD10R_MASK | + HAL_LL_I2C_NBYTES_MASK | + HAL_LL_I2C_RELOAD_MASK | + HAL_LL_I2C_RD_WRN_MASK + ); +} + +static hal_ll_err_t hal_ll_i2c_master_start( hal_ll_i2c_hw_specifics_map_t *map ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct(map->base); + uint16_t loop_index = HAL_LL_I2C_LOOP_INDEX; + + set_reg_bit( &(hal_ll_hw_reg->cr2), HAL_LL_I2C_CR2_START_BIT ); + + if ( check_reg_bit( &( hal_ll_hw_reg->isr ), HAL_LL_I2C_ARLO_BIT ) ) + return HAL_LL_I2C_MASTER_ARBITRATION_LOST; + + while ( loop_index-- ) + assembly(nop); + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static hal_ll_err_t hal_ll_i2c_master_stop( hal_ll_i2c_hw_specifics_map_t *map ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = ( hal_ll_i2c_base_handle_t* )map->base; + uint16_t time_counter = map->timeout; + uint32_t loop_index = HAL_LL_I2C_LOOP_INDEX; + + set_reg_bit( &(hal_ll_hw_reg->cr2), HAL_LL_I2C_CR2_STOP_BIT ); + + while ( !( hal_ll_hw_reg->isr & HAL_LL_I2C_ISR_STOPF_BIT ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_STOP; + } + } + + if ( map->timeout < HAL_LL_I2C_LOOP_INDEX ) { + while ( loop_index-- ) + assembly(nop); + } + + hal_ll_hw_reg->isr &= ~HAL_LL_I2C_ISR_STOPF_BIT; + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static hal_ll_pin_name_t hal_ll_i2c_master_check_pins( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_pin_id *index_list, hal_ll_i2c_master_handle_register_t *handle_map ) { + static const uint16_t scl_map_size = ( sizeof( hal_ll_i2c_scl_map ) / sizeof( hal_ll_i2c_pin_map_t ) ); + static const uint16_t sda_map_size = ( sizeof( hal_ll_i2c_sda_map ) / sizeof( hal_ll_i2c_pin_map_t ) ); + uint8_t hal_ll_module_id = 0; + uint8_t index_counter = 0; + uint16_t scl_index; + uint16_t sda_index; + + if ( (HAL_LL_PIN_NC == scl) || (HAL_LL_PIN_NC == sda) ) { + return HAL_LL_PIN_NC; + } + + for ( scl_index = 0; scl_index < scl_map_size; scl_index++ ) { + if ( hal_ll_i2c_scl_map[ scl_index ].pin == scl ) { + for ( sda_index = 0; sda_index < sda_map_size; sda_index++ ) { + if ( hal_ll_i2c_sda_map[ sda_index ].pin == sda ) { + if ( hal_ll_i2c_scl_map[ scl_index ].module_index == hal_ll_i2c_sda_map[ sda_index ].module_index ) { + // Get module number + hal_ll_module_id = hal_ll_i2c_scl_map[ scl_index ].module_index; + // Map pin names + index_list[hal_ll_module_id].pin_scl = scl_index; + index_list[hal_ll_module_id].pin_sda = sda_index; + + // Check if module is taken + if ( NULL == handle_map[ hal_ll_module_id ].hal_drv_i2c_master_handle ) { + return hal_ll_module_id; + } else if ( I2C_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static hal_ll_i2c_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof(hal_ll_i2c_master_handle_register_t)); + static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof(hal_ll_i2c_master_handle_register_t)); + + while( hal_ll_module_count-- ) { + if (hal_ll_i2c_get_base_from_hal_handle == hal_ll_i2c_hw_specifics_map[hal_ll_module_count].base) { + return &hal_ll_i2c_hw_specifics_map[hal_ll_module_count]; + } + } + + return &hal_ll_i2c_hw_specifics_map[hal_ll_module_error]; +} + +static void hal_ll_i2c_master_set_clock( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ) { + switch ( map->module_index ) + { + #if defined(I2C_MODULE_1) + case ( hal_ll_i2c_module_num(I2C_MODULE_1) ): + hal_ll_i2c1_set_clock( hal_ll_state ); + break; + #endif + + #if defined(I2C_MODULE_2) + case ( hal_ll_i2c_module_num(I2C_MODULE_2) ): + hal_ll_i2c2_set_clock( hal_ll_state ); + break; + #endif + + #if defined(I2C_MODULE_3) + case ( hal_ll_i2c_module_num(I2C_MODULE_3) ): + hal_ll_i2c3_set_clock( hal_ll_state ); + break; + #endif + + + default: + break; + } +} + +static void hal_ll_i2c_master_map_pins( uint8_t module_index, hal_ll_i2c_pin_id *index_list ) { + // Map new pins + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_scl.pin_name = hal_ll_i2c_scl_map[ index_list[module_index].pin_scl ].pin; + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_sda.pin_name = hal_ll_i2c_sda_map[ index_list[module_index].pin_sda ].pin; + // SCL and SDA could have different alternate function settings, hence save both AF values + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_scl.pin_af = hal_ll_i2c_scl_map[ index_list[module_index].pin_scl ].af; + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_sda.pin_af = hal_ll_i2c_sda_map[ index_list[module_index].pin_sda ].af; +} + +static void hal_ll_i2c_master_alternate_functions_set_state( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ) { + module_struct module; + + if( (map->pins.pin_scl.pin_name != HAL_LL_PIN_NC) && (map->pins.pin_sda.pin_name != HAL_LL_PIN_NC) ) { + module.pins[0] = VALUE( map->pins.pin_scl.pin_name, map->pins.pin_scl.pin_af ); + module.pins[1] = VALUE( map->pins.pin_sda.pin_name, map->pins.pin_sda.pin_af ); + module.pins[2] = GPIO_MODULE_STRUCT_END; + + module.configs[0] = HAL_LL_I2C_AF_CONFIG; + module.configs[1] = HAL_LL_I2C_AF_CONFIG; + module.configs[2] = GPIO_MODULE_STRUCT_END; + + hal_ll_gpio_module_struct_init( &module, hal_ll_state ); + } +} + +static uint32_t hal_ll_i2c_get_speed( hal_ll_i2c_hw_specifics_map_t *map ) { + if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_FAST ) { + if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_STANDARD ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_100K; + return HAL_LL_I2C_100K; + } else if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_FULL ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_400K; + return HAL_LL_I2C_400K; + } else if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_FAST ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_1M; + return HAL_LL_I2C_1M; + } else { + map->speed = HAL_LL_I2C_MASTER_SPEED_100K; + return HAL_LL_I2C_100K; + } + } else { + if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_100K ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_100K; + return HAL_LL_I2C_100K; + } else if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_400K ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_400K; + return HAL_LL_I2C_400K; + } else if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_1M ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_1M; + return HAL_LL_I2C_1M; + } else { + map->speed = HAL_LL_I2C_MASTER_SPEED_1M; + return HAL_LL_I2C_1M; + } + } +} +static inline void hal_ll_i2c1_set_clock( bool hal_ll_state ) { + if ( hal_ll_state ) { + set_reg_bit( _RCC_APB1ENR1, HAL_LL_I2C1EN_BIT ); + set_reg_bit( _RCC_CCIPR, HAL_LL_I2C1SEL1_BIT ); + } else { + clear_reg_bit( _RCC_APB1ENR1, HAL_LL_I2C1EN_BIT ); + clear_reg_bit( _RCC_CCIPR, HAL_LL_I2C1SEL1_BIT ); + } +} + + +static inline void hal_ll_i2c2_set_clock( bool hal_ll_state ) { + if ( hal_ll_state ) { + set_reg_bit( _RCC_APB1ENR1, HAL_LL_I2C2EN_BIT ); + set_reg_bit( _RCC_CCIPR, HAL_LL_I2C2SEL1_BIT ); + } else { + clear_reg_bit( _RCC_APB1ENR1, HAL_LL_I2C2EN_BIT ); + clear_reg_bit( _RCC_CCIPR, HAL_LL_I2C2SEL1_BIT ); + } +} + + +static inline void hal_ll_i2c3_set_clock( bool hal_ll_state ) { + if ( hal_ll_state ) { + set_reg_bit( _RCC_APB1ENR1, HAL_LL_I2C3EN_BIT ); + set_reg_bit( _RCC_CCIPR, HAL_LL_I2C3SEL1_BIT ); + } else { + clear_reg_bit( _RCC_APB1ENR1, HAL_LL_I2C3EN_BIT ); + clear_reg_bit( _RCC_CCIPR, HAL_LL_I2C3SEL1_BIT ); + } +} + + + +static hal_ll_err_t hal_ll_i2c_hw_init( hal_ll_i2c_hw_specifics_map_t *map ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct(map->base); + uint16_t time_counter = map->timeout; + + clear_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_I2C_PE_BIT ); + while ( check_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_I2C_PE_BIT ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_INIT; + } + } + + hal_ll_hw_reg->cr1 &= HAL_LL_I2C_FILTERS_OFF; + + hal_ll_hw_reg->timingr = hal_ll_i2c_get_speed( map ); + + hal_ll_hw_reg->cr1 |= HAL_LL_I2C_CR1_RXTX_INT; + + set_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_I2C_PE_BIT ); + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static hal_ll_err_t hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_t *map ) { + hal_ll_i2c_master_set_clock( map, true ); + + return hal_ll_i2c_hw_init( map ); +} +// ------------------------------------------------------------------------- END + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_89/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_89/CMakeLists.cmake new file mode 100644 index 000000000..6229c16d0 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_89/CMakeLists.cmake @@ -0,0 +1,9 @@ +if(${MCU_NAME} MATCHES "^STM32G4A1CE$|^STM32G4A1KE$|^STM32G4A1ME$|^STM32G4A1RE$|^STM32G4A1VE$") + set(i2c_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_i2c_master.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_89") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_89") + list(APPEND hal_ll_def_list "STM32G4xx") + list(APPEND hal_ll_def_list "STM32G4Axx") + list(APPEND hal_ll_def_list "STM32G4A1xx") + set(i2c_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/i2c/hal_ll_i2c_pin_map/implementations/doc_ds_89") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_89/hal_ll_i2c_master.c b/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_89/hal_ll_i2c_master.c new file mode 100644 index 000000000..5e1ea38a2 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/i2c/implementations/doc_ds_89/hal_ll_i2c_master.c @@ -0,0 +1,976 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_i2c_master.c + * @brief I2C master HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_rcc.h" +#include "hal_ll_gpio.h" +#include "hal_ll_i2c_master.h" +#include "hal_ll_i2c_pin_map.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_i2c_master_handle_register_t hal_ll_module_state[I2C_MODULE_COUNT] = { (handle_t *)NULL, (handle_t *)NULL, false }; + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_i2c_get_module_state_address ((hal_ll_i2c_master_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_i2c_get_handle (hal_ll_i2c_master_handle_register_t *)hal_ll_i2c_get_module_state_address->hal_ll_i2c_master_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_i2c_get_base_struct(_handle) ((hal_ll_i2c_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_i2c_get_base_from_hal_handle ((hal_ll_i2c_hw_specifics_map_t *)((hal_ll_i2c_master_handle_register_t *)\ + (((hal_ll_i2c_master_handle_register_t *)(handle))->hal_ll_i2c_master_handle))->hal_ll_i2c_master_handle)->base + +/*!< @brief Default I2C bit-rate if no speed is set */ +#define HAL_LL_I2C_MASTER_SPEED_100K 100000UL +#define HAL_LL_I2C_MASTER_SPEED_400K 400000UL +#define HAL_LL_I2C_MASTER_SPEED_1M 1000000UL + +/*!< @brief Default pass count value upon reset */ +#define HAL_LL_I2C_DEFAULT_PASS_COUNT 0xFFFFU + +/*!< @brief Macro used for timeout */ +#define HAL_LL_I2C_LOOP_INDEX 10000U + +/*!< @brief Macros defining register bit location */ +#define HAL_LL_I2C1EN_BIT 21 + +#define HAL_LL_I2C2EN_BIT 22 + +#define HAL_LL_I2C3EN_BIT 30 + +#define HAL_LL_I2C1SEL0_BIT 12 + +#define HAL_LL_I2C1SEL1_BIT 13 + +#define HAL_LL_I2C2SEL0_BIT 14 + +#define HAL_LL_I2C2SEL1_BIT 15 + +#define HAL_LL_I2C3SEL0_BIT 16 + +#define HAL_LL_I2C3SEL1_BIT 17 + + + + +#define HAL_LL_I2C_100K 0x30420F13 //?????????????????? +#define HAL_LL_I2C_400K 0x10320309 //?????????????????? +#define HAL_LL_I2C_1M 0x00200204 //?????????????????? + +#define HAL_LL_I2C_PE_BIT 0 +#define HAL_LL_I2C_CR2_STOP_BIT 14 +#define HAL_LL_I2C_CR2_START_BIT 13 +#define HAL_LL_I2C_ISR_STOPF_BIT 5 +#define HAL_LL_I2C_ISR_BUSY_BIT 15 +#define HAL_LL_I2C_ARLO_BIT 9 +#define HAL_LL_I2C_RXNE_BIT 2 +#define HAL_LL_I2C_TXIS_BIT 1 +#define HAL_LL_I2C_TXE_BIT 0 + +/*!< @brief Macros defining register bit masks */ +#define HAL_LL_I2C_CR1_RXTX_INT 0x6 +#define HAL_LL_I2C_CR2_STOP 0x4000UL +#define HAL_LL_I2C_CR2_START 0x2000U +#define HAL_LL_I2C_CR2_SADD 0x3FFU +#define HAL_LL_I2C_CR2_NBYTES 0xFF0000UL +#define HAL_LL_I2C_CR2_RD_WRN 0x400U +#define HAL_LL_I2C_CR2_RELOAD 0x1000000UL +#define HAL_LL_I2C_CR2_AUTOEND 0x2000000UL +#define HAL_LL_I2C_FILTERS_OFF 0xFFFFE0FFUL +#define HAL_LL_I2C_SADD_MASK 0x3FFUL +#define HAL_LL_I2C_HEAD10R_MASK 0x1000UL +#define HAL_LL_I2C_NBYTES_MASK 0xFF0000UL +#define HAL_LL_I2C_RELOAD_MASK 0x1000000UL +#define HAL_LL_I2C_RD_WRN_MASK 0x400UL + +/*!< @brief Macros used for module pin checking */ +#define HAL_LL_I2C_SCL_PIN 0 +#define HAL_LL_I2C_SDA_PIN 1 +#define HAL_LL_I2C_MODULE_PIN_COUNT 2 + +/*!< @brief Macro used for setting pin alternate functions */ +#define HAL_LL_I2C_AF_CONFIG (GPIO_CFG_MODE_ALT_FUNCTION | GPIO_CFG_SPEED_HIGH | GPIO_CFG_OTYPE_OD) + +// -------------------------------------------------------------- PRIVATE TYPES +/*!< @brief I2C register structure */ +typedef struct +{ + hal_ll_base_addr_t cr1; + hal_ll_base_addr_t cr2; + hal_ll_base_addr_t oar1; + hal_ll_base_addr_t oar2; + hal_ll_base_addr_t timingr; + hal_ll_base_addr_t timeoutr; + hal_ll_base_addr_t isr; + hal_ll_base_addr_t icr; + hal_ll_base_addr_t pecr; + hal_ll_base_addr_t rxdr; + hal_ll_base_addr_t txdr; + +} hal_ll_i2c_base_handle_t; + +/*!< @brief I2C hw specific structure */ +typedef struct +{ + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + hal_ll_i2c_pins_t pins; + uint32_t speed; + uint8_t address; + uint16_t timeout; +} hal_ll_i2c_hw_specifics_map_t; + +/*!< @brief I2C hw specific module values */ +typedef struct +{ + uint16_t pin_scl; + uint16_t pin_sda; +} hal_ll_i2c_pin_id; + +/*!< @brief I2C hw specific error values */ +typedef enum +{ + HAL_LL_I2C_MASTER_SUCCESS = 0, + HAL_LL_I2C_MASTER_WRONG_PINS, + HAL_LL_I2C_MASTER_MODULE_ERROR, + + HAL_LL_I2C_MASTER_ERROR = (-1) +} hal_ll_i2c_master_err_t; + +/*!< @brief I2C end mode selection values */ +typedef enum +{ + HAL_LL_I2C_MASTER_END_MODE_RESTART = 0, + HAL_LL_I2C_MASTER_END_MODE_STOP, + HAL_LL_I2C_MASTER_WRITE_THEN_READ +} hal_ll_i2c_master_end_mode_t; + +/*!< @brief I2C timeout error values */ +typedef enum +{ + HAL_LL_I2C_MASTER_TIMEOUT_START = 1300, + HAL_LL_I2C_MASTER_TIMEOUT_STOP, + HAL_LL_I2C_MASTER_TIMEOUT_WRITE, + HAL_LL_I2C_MASTER_TIMEOUT_READ, + HAL_LL_I2C_MASTER_ARBITRATION_LOST, + HAL_LL_I2C_MASTER_TIMEOUT_INIT +} hal_ll_i2c_master_timeout_t; + +/** + * @brief Enum containing predefined module standard speed values. + * + * Enum values: + * HAL_LL_I2C_MASTER_SPEED_STANDARD -- Speed set at 100K + * HAL_LL_I2C_MASTER_SPEED_FULL -- Speed set at 400K + * HAL_LL_I2C_MASTER_SPEED_FAST -- Speed set at 1M + */ +typedef enum +{ + HAL_LL_I2C_MASTER_SPEED_STANDARD = 0, + HAL_LL_I2C_MASTER_SPEED_FULL, + HAL_LL_I2C_MASTER_SPEED_FAST +} hal_ll_i2c_master_speed_t; + +// ------------------------------------------------------------------ VARIABLES +/*!< @brief I2C hardware specific info */ +static hal_ll_i2c_hw_specifics_map_t hal_ll_i2c_hw_specifics_map[] = +{ + #ifdef I2C_MODULE_1 + {HAL_LL_I2C1_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_1), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, + #endif + + #ifdef I2C_MODULE_2 + {HAL_LL_I2C2_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_2), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, + #endif + + #ifdef I2C_MODULE_3 + {HAL_LL_I2C3_BASE_ADDR, hal_ll_i2c_module_num(I2C_MODULE_3), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, + #endif + + + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, 0, 0} +}; + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_i2c_master_handle_register_t *low_level_handle; +static volatile hal_ll_i2c_hw_specifics_map_t *hal_ll_i2c_hw_specifics_map_local; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Check if pins are adequate. + * + * Checks scl and sda pins the user has passed with pre-defined + * pins in scl and sda maps. Take into consideration that module + * index numbers have to be the same for both pins. + * + * @param[in] scl - SCL pre-defined pin name. + * @param[in] sda - SDA pre-defined pin name. + * @param[in] *index_list - Index list address + * @return hal_ll_pin_name_t Module index based on pins. + * + * Returns pre-defined module index from pin maps, if pins + * are adequate. + */ +static hal_ll_pin_name_t hal_ll_i2c_master_check_pins( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_pin_id *index_list, hal_ll_i2c_master_handle_register_t *handle_map ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_i2c_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_i2c_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_i2c_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Get adequate I2C bit-rate value. + * + * Returns one of pre-defined bit-rate values, + * or the closest bit-rate based on bit_rate + * value passed to the function. + * + * @param[in] bit_rate - I2C bit rate. + * @return uint32_t Adequate bit-rate value. + * + * Returns adequate value to be latter written into bare metal register address. + * Take into consideration that this returns a predefined value. + * + * HAL_LL_I2C_MASTER_SPEED_100K -- 100Kbit/s + * HAL_LL_I2C_MASTER_SPEED_400K -- 400Kbit/s + * HAL_LL_I2C_MASTER_SPEED_1M -- 1Mbit/s + * HAL_LL_I2C_MASTER_SPEED_3M2 -- 3.2Mbit/s + */ +static uint32_t hal_ll_i2c_get_speed( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Enable clock for I2C1 module on hardware level. + * + * Initializes I2C1 module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] hal_ll_state - True/False -- Init/De-init + * + * @return None + */ +static inline void hal_ll_i2c1_set_clock( bool hal_ll_state ); + +/** + * @brief Enable clock for I2C2 module on hardware level. + * + * Initializes I2C2 module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] hal_ll_state - True/False -- Init/De-init + * + * @return None + */ +static inline void hal_ll_i2c2_set_clock( bool hal_ll_state ); + +/** + * @brief Enable clock for I2C3 module on hardware level. + * + * Initializes I2C3 module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] hal_ll_state - True/False -- Init/De-init + * + * @return None + */ +static inline void hal_ll_i2c3_set_clock( bool hal_ll_state ); + +/** + * @brief Enable clock for I2C module on hardware level. + * + * Initializes I2C module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_stat - True(enable clock)/False(disable clock). + * + * @return None + */ +static void hal_ll_i2c_master_set_clock( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Initialize I2C module on hardware level. + * + * Initializes I2C module on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] map - Object specific context handler. + * @return hal_ll_err_t Module specific return values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_hw_init( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * I2C SCL and SDA pins. + * + * @param[in] module_index I2C HW module index -- 0,1,2... + * @param[in] *index_list Array with SCL and SDA map index values + * and module number + * + * @return None + */ +static void hal_ll_i2c_master_map_pins( uint8_t module_index, hal_ll_i2c_pin_id *index_list ); + +/** + * @brief Sets I2C pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if I2C is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_state - Init/De-init + * + * @return None + */ +static void hal_ll_i2c_master_alternate_functions_set_state( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Full I2C module initialization procedure. + * + * Initializes I2C module on hardware level, based on beforehand + * set configuration and module handler. Sets adequate pin alternate functions. + * Initializes module clock. + * + * @param[in] map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Configure I2C module for data transfer. + * + * @param[in] hal_ll_hw_reg - I2C module base address. + * @param[in] config - I2C config bits. + * @return void None. + */ +static void hal_ll_i2c_master_configure_transfer( hal_ll_i2c_base_handle_t *hal_ll_hw_reg, uint32_t config ); + +/** + * @brief Reset value of I2C CR2 register. + * + * @param[in] hal_ll_hw_reg - I2C module base address. + * @returnl none + */ +static void hal_ll_i2c_master_reset_cr2( hal_ll_i2c_base_handle_t *hal_ll_hw_reg ); + +/** + * @brief Generates start signal on I2C bus. + * + * Generates a start signal on the I2C bus. + * + * @param[in] map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_master_start( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Generates stop signal on I2C bus. + * + * Generates a stop signal on the I2C bus. + * + * @param[in] map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_master_stop( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Perform a read on the I2C bus. + * + * Initializes I2C module on hardware level, if not initialized beforehand + * and continues to perform a read operation on the bus. + * + * @param[in] map - Object specific context handler. + * @param[in] readDatabuf - Pointer to data buffer. + * @param[in] lenReadData - Number of data to be read. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *read_data_buf, size_t len_read_data, hal_ll_i2c_master_end_mode_t mode ); + +/** + * @brief Perform a write on the I2C bus. + * + * Initializes I2C module on hardware level, if not initialized beforehand + * and continues to perform a write operation on the bus. + * + * @param[in] map - Object specific context handler. + * @param[in] writeDatabuf - Pointer to data buffer. + * @param[in] lenWriteData - Number of data to be written. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *write_data_buf, size_t len_write_data, hal_ll_i2c_master_end_mode_t mode ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_i2c_master_register_handle( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_master_handle_register_t *handle_map, uint8_t *hal_module_id ) { + + hal_ll_i2c_pin_id index_list[I2C_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + uint16_t pin_check_result; + + // Check if pins are valid + if ( (pin_check_result = hal_ll_i2c_master_check_pins( scl, sda, &index_list, handle_map )) == HAL_LL_PIN_NC ) { + return HAL_LL_I2C_MASTER_WRONG_PINS; + }; + + if ( (hal_ll_i2c_hw_specifics_map[pin_check_result].pins.pin_scl.pin_name != scl) || + (hal_ll_i2c_hw_specifics_map[pin_check_result].pins.pin_sda.pin_name != sda) ) + { + hal_ll_i2c_master_alternate_functions_set_state( &hal_ll_i2c_hw_specifics_map[ pin_check_result ], false ); + + hal_ll_i2c_master_map_pins( pin_check_result, &index_list ); + + hal_ll_i2c_master_alternate_functions_set_state( &hal_ll_i2c_hw_specifics_map[ pin_check_result ], true ); + + handle_map[pin_check_result].init_ll_state = false; + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[pin_check_result].hal_ll_i2c_master_handle = (handle_t *)&hal_ll_i2c_hw_specifics_map[pin_check_result].base; + + handle_map[pin_check_result].hal_ll_i2c_master_handle = (handle_t *)&hal_ll_module_state[pin_check_result].hal_ll_i2c_master_handle; + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_i2c( handle_t *handle ) { + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + hal_ll_i2c_master_handle_register_t *hal_handle = (hal_ll_i2c_master_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_i2c_hw_specifics_map_local->module_index; + + hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_local ); + + hal_ll_module_state[pin_check_result].hal_ll_i2c_master_handle = (handle_t *)&hal_ll_i2c_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_i2c_master_set_speed( handle_t *handle, uint32_t speed ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + low_level_handle->init_ll_state = false; + + hal_ll_i2c_hw_specifics_map_local->speed = speed; + + if ( hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_local ) != HAL_LL_I2C_MASTER_SUCCESS ) { + return HAL_LL_I2C_MASTER_TIMEOUT_INIT; + } + + low_level_handle->init_ll_state = true; + + return hal_ll_i2c_hw_specifics_map_local->speed; +} + +void hal_ll_i2c_master_set_timeout( handle_t *handle, uint16_t timeout ) { + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + if( hal_ll_i2c_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + hal_ll_i2c_hw_specifics_map_local->timeout = timeout; + } +} + +void hal_ll_i2c_master_set_slave_address( handle_t *handle, uint8_t addr ) { + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + if( hal_ll_i2c_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + hal_ll_i2c_hw_specifics_map_local->address = addr; + } +} + +hal_ll_err_t hal_ll_i2c_master_read( handle_t *handle, uint8_t *read_data_buf, size_t len_read_data ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + return hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_local, read_data_buf, len_read_data, HAL_LL_I2C_MASTER_END_MODE_STOP ); +} + +hal_ll_err_t hal_ll_i2c_master_write( handle_t *handle, uint8_t *write_data_buf, size_t len_write_data ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + return hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_local, write_data_buf, len_write_data, HAL_LL_I2C_MASTER_END_MODE_STOP ); +} + +hal_ll_err_t hal_ll_i2c_master_write_then_read( handle_t *handle, uint8_t *write_data_buf, size_t len_write_data, uint8_t *read_data_buf, size_t len_read_data ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + if( hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_local, write_data_buf, len_write_data, HAL_LL_I2C_MASTER_WRITE_THEN_READ ) != NULL ) { + return HAL_LL_I2C_MASTER_TIMEOUT_WRITE; + } + + /** + * @note Wait for drivers to set-up + * correctly. + **/ + #ifdef __TFT_RESISTIVE_TSC2003__ + Delay_22us(); + #endif + + if( hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_local, read_data_buf, len_read_data, HAL_LL_I2C_MASTER_WRITE_THEN_READ ) != NULL ) { + return HAL_LL_I2C_MASTER_TIMEOUT_READ; + } + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +void hal_ll_i2c_master_close( handle_t *handle ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address); + + if( low_level_handle->hal_ll_i2c_master_handle != NULL ) { + low_level_handle->hal_ll_i2c_master_handle = NULL; + low_level_handle->hal_drv_i2c_master_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_i2c_hw_specifics_map_local->address = 0; + hal_ll_i2c_hw_specifics_map_local->timeout = HAL_LL_I2C_DEFAULT_PASS_COUNT; + hal_ll_i2c_hw_specifics_map_local->speed = HAL_LL_I2C_MASTER_SPEED_100K; + + hal_ll_i2c_master_set_clock(hal_ll_i2c_hw_specifics_map_local, true); + hal_ll_i2c_master_alternate_functions_set_state( hal_ll_i2c_hw_specifics_map_local, false ); + hal_ll_i2c_master_set_clock(hal_ll_i2c_hw_specifics_map_local, false); + + hal_ll_i2c_hw_specifics_map_local->pins.pin_scl.pin_name = HAL_LL_PIN_NC; + hal_ll_i2c_hw_specifics_map_local->pins.pin_sda.pin_name = HAL_LL_PIN_NC; + hal_ll_i2c_hw_specifics_map_local->pins.pin_scl.pin_af = 0; + hal_ll_i2c_hw_specifics_map_local->pins.pin_sda.pin_af = 0; + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static hal_ll_err_t hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *read_data_buf, size_t len_read_data, hal_ll_i2c_master_end_mode_t mode ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct(map->base); + uint16_t time_counter = map->timeout; + size_t transfer_counter = NULL; + uint8_t status = NULL; + + /** + * @note When R/W = 0, the input sample acquisition period starts + * on the falling edge of SCL once the C0 bit of the command + * byte has been latched, and ends when a Stop or + * repeated Start condition has been issued. + **/ + #ifdef __TFT_RESISTIVE_TSC2003__ + Delay_1ms(); + #endif + + hal_ll_i2c_master_configure_transfer ( map->base, + ( map->address << 1 & HAL_LL_I2C_CR2_SADD ) | + ( len_read_data << 16 & HAL_LL_I2C_CR2_NBYTES ) | + HAL_LL_I2C_CR2_RD_WRN | + HAL_LL_I2C_CR2_START + ); + + for ( transfer_counter; transfer_counter < len_read_data; transfer_counter++ ) { + while ( !( check_reg_bit( &( hal_ll_hw_reg->isr ), HAL_LL_I2C_RXNE_BIT ) ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_READ; + } + } + read_data_buf[ transfer_counter ] = hal_ll_hw_reg->rxdr; + } + + if ( ( mode == HAL_LL_I2C_MASTER_END_MODE_STOP ) || ( mode == HAL_LL_I2C_MASTER_WRITE_THEN_READ ) ) { + status = hal_ll_i2c_master_stop( map ); + } else { + status = hal_ll_i2c_master_start( map ); + } + + if( status != HAL_LL_I2C_MASTER_SUCCESS ) { + return status; + } + + hal_ll_i2c_master_reset_cr2( hal_ll_hw_reg ); + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static hal_ll_err_t hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *write_data_buf, size_t len_write_data, hal_ll_i2c_master_end_mode_t mode ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct(map->base); + uint16_t time_counter = map->timeout; + size_t transfer_counter = NULL; + uint8_t status = NULL; + + hal_ll_i2c_master_configure_transfer ( map->base, + ( map->address << 1 & HAL_LL_I2C_CR2_SADD ) | + ( len_write_data << 16 & HAL_LL_I2C_CR2_NBYTES ) | + !HAL_LL_I2C_CR2_RD_WRN | + HAL_LL_I2C_CR2_START + ); + + for ( transfer_counter; transfer_counter < len_write_data; transfer_counter++ ) + { + while ( !( check_reg_bit( &( hal_ll_hw_reg->isr ), HAL_LL_I2C_TXIS_BIT ) ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_WRITE; + } + } + hal_ll_hw_reg->txdr = write_data_buf[ transfer_counter ]; + } + + time_counter = map->timeout; + while ( !( check_reg_bit( &( hal_ll_hw_reg->isr ), HAL_LL_I2C_TXE_BIT ) ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_WRITE; + } + } + + if ( mode == HAL_LL_I2C_MASTER_END_MODE_STOP ) + { + hal_ll_i2c_master_stop( map ); + } + + hal_ll_i2c_master_reset_cr2( hal_ll_hw_reg ); + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static void hal_ll_i2c_master_configure_transfer( hal_ll_i2c_base_handle_t *hal_ll_hw_reg, uint32_t config ) { + uint32_t reg = 0; + + // Clear last set slave address + hal_ll_hw_reg->cr2 &= ~HAL_LL_I2C_CR2_SADD; + + reg = hal_ll_hw_reg->cr2; + reg &= ~( uint32_t )( + ( HAL_LL_I2C_CR2_SADD ) | + ( HAL_LL_I2C_CR2_NBYTES ) | + ( HAL_LL_I2C_CR2_RELOAD ) | + ( HAL_LL_I2C_CR2_AUTOEND ) | + ( HAL_LL_I2C_CR2_RD_WRN ) | + ( HAL_LL_I2C_CR2_START ) | + ( HAL_LL_I2C_CR2_STOP ) + ); + + reg |= config; + hal_ll_hw_reg->cr2 = reg; +} + +static void hal_ll_i2c_master_reset_cr2( hal_ll_i2c_base_handle_t *hal_ll_hw_reg ) { + hal_ll_hw_reg->cr2 &= ~( uint32_t ) + ( + HAL_LL_I2C_SADD_MASK | + HAL_LL_I2C_HEAD10R_MASK | + HAL_LL_I2C_NBYTES_MASK | + HAL_LL_I2C_RELOAD_MASK | + HAL_LL_I2C_RD_WRN_MASK + ); +} + +static hal_ll_err_t hal_ll_i2c_master_start( hal_ll_i2c_hw_specifics_map_t *map ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct(map->base); + uint16_t loop_index = HAL_LL_I2C_LOOP_INDEX; + + set_reg_bit( &(hal_ll_hw_reg->cr2), HAL_LL_I2C_CR2_START_BIT ); + + if ( check_reg_bit( &( hal_ll_hw_reg->isr ), HAL_LL_I2C_ARLO_BIT ) ) + return HAL_LL_I2C_MASTER_ARBITRATION_LOST; + + while ( loop_index-- ) + assembly(nop); + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static hal_ll_err_t hal_ll_i2c_master_stop( hal_ll_i2c_hw_specifics_map_t *map ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = ( hal_ll_i2c_base_handle_t* )map->base; + uint16_t time_counter = map->timeout; + uint32_t loop_index = HAL_LL_I2C_LOOP_INDEX; + + set_reg_bit( &(hal_ll_hw_reg->cr2), HAL_LL_I2C_CR2_STOP_BIT ); + + while ( !( hal_ll_hw_reg->isr & HAL_LL_I2C_ISR_STOPF_BIT ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_STOP; + } + } + + if ( map->timeout < HAL_LL_I2C_LOOP_INDEX ) { + while ( loop_index-- ) + assembly(nop); + } + + hal_ll_hw_reg->isr &= ~HAL_LL_I2C_ISR_STOPF_BIT; + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static hal_ll_pin_name_t hal_ll_i2c_master_check_pins( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_pin_id *index_list, hal_ll_i2c_master_handle_register_t *handle_map ) { + static const uint16_t scl_map_size = ( sizeof( hal_ll_i2c_scl_map ) / sizeof( hal_ll_i2c_pin_map_t ) ); + static const uint16_t sda_map_size = ( sizeof( hal_ll_i2c_sda_map ) / sizeof( hal_ll_i2c_pin_map_t ) ); + uint8_t hal_ll_module_id = 0; + uint8_t index_counter = 0; + uint16_t scl_index; + uint16_t sda_index; + + if ( (HAL_LL_PIN_NC == scl) || (HAL_LL_PIN_NC == sda) ) { + return HAL_LL_PIN_NC; + } + + for ( scl_index = 0; scl_index < scl_map_size; scl_index++ ) { + if ( hal_ll_i2c_scl_map[ scl_index ].pin == scl ) { + for ( sda_index = 0; sda_index < sda_map_size; sda_index++ ) { + if ( hal_ll_i2c_sda_map[ sda_index ].pin == sda ) { + if ( hal_ll_i2c_scl_map[ scl_index ].module_index == hal_ll_i2c_sda_map[ sda_index ].module_index ) { + // Get module number + hal_ll_module_id = hal_ll_i2c_scl_map[ scl_index ].module_index; + // Map pin names + index_list[hal_ll_module_id].pin_scl = scl_index; + index_list[hal_ll_module_id].pin_sda = sda_index; + + // Check if module is taken + if ( NULL == handle_map[ hal_ll_module_id ].hal_drv_i2c_master_handle ) { + return hal_ll_module_id; + } else if ( I2C_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static hal_ll_i2c_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof(hal_ll_i2c_master_handle_register_t)); + static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof(hal_ll_i2c_master_handle_register_t)); + + while( hal_ll_module_count-- ) { + if (hal_ll_i2c_get_base_from_hal_handle == hal_ll_i2c_hw_specifics_map[hal_ll_module_count].base) { + return &hal_ll_i2c_hw_specifics_map[hal_ll_module_count]; + } + } + + return &hal_ll_i2c_hw_specifics_map[hal_ll_module_error]; +} + +static void hal_ll_i2c_master_set_clock( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ) { + switch ( map->module_index ) + { + #if defined(I2C_MODULE_1) + case ( hal_ll_i2c_module_num(I2C_MODULE_1) ): + hal_ll_i2c1_set_clock( hal_ll_state ); + break; + #endif + + #if defined(I2C_MODULE_2) + case ( hal_ll_i2c_module_num(I2C_MODULE_2) ): + hal_ll_i2c2_set_clock( hal_ll_state ); + break; + #endif + + #if defined(I2C_MODULE_3) + case ( hal_ll_i2c_module_num(I2C_MODULE_3) ): + hal_ll_i2c3_set_clock( hal_ll_state ); + break; + #endif + + + default: + break; + } +} + +static void hal_ll_i2c_master_map_pins( uint8_t module_index, hal_ll_i2c_pin_id *index_list ) { + // Map new pins + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_scl.pin_name = hal_ll_i2c_scl_map[ index_list[module_index].pin_scl ].pin; + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_sda.pin_name = hal_ll_i2c_sda_map[ index_list[module_index].pin_sda ].pin; + // SCL and SDA could have different alternate function settings, hence save both AF values + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_scl.pin_af = hal_ll_i2c_scl_map[ index_list[module_index].pin_scl ].af; + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_sda.pin_af = hal_ll_i2c_sda_map[ index_list[module_index].pin_sda ].af; +} + +static void hal_ll_i2c_master_alternate_functions_set_state( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ) { + module_struct module; + + if( (map->pins.pin_scl.pin_name != HAL_LL_PIN_NC) && (map->pins.pin_sda.pin_name != HAL_LL_PIN_NC) ) { + module.pins[0] = VALUE( map->pins.pin_scl.pin_name, map->pins.pin_scl.pin_af ); + module.pins[1] = VALUE( map->pins.pin_sda.pin_name, map->pins.pin_sda.pin_af ); + module.pins[2] = GPIO_MODULE_STRUCT_END; + + module.configs[0] = HAL_LL_I2C_AF_CONFIG; + module.configs[1] = HAL_LL_I2C_AF_CONFIG; + module.configs[2] = GPIO_MODULE_STRUCT_END; + + hal_ll_gpio_module_struct_init( &module, hal_ll_state ); + } +} + +static uint32_t hal_ll_i2c_get_speed( hal_ll_i2c_hw_specifics_map_t *map ) { + if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_FAST ) { + if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_STANDARD ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_100K; + return HAL_LL_I2C_100K; + } else if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_FULL ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_400K; + return HAL_LL_I2C_400K; + } else if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_FAST ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_1M; + return HAL_LL_I2C_1M; + } else { + map->speed = HAL_LL_I2C_MASTER_SPEED_100K; + return HAL_LL_I2C_100K; + } + } else { + if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_100K ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_100K; + return HAL_LL_I2C_100K; + } else if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_400K ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_400K; + return HAL_LL_I2C_400K; + } else if ( map->speed <= HAL_LL_I2C_MASTER_SPEED_1M ) { + map->speed = HAL_LL_I2C_MASTER_SPEED_1M; + return HAL_LL_I2C_1M; + } else { + map->speed = HAL_LL_I2C_MASTER_SPEED_1M; + return HAL_LL_I2C_1M; + } + } +} +static inline void hal_ll_i2c1_set_clock( bool hal_ll_state ) { + if ( hal_ll_state ) { + set_reg_bit( _RCC_APB1ENR1, HAL_LL_I2C1EN_BIT ); + set_reg_bit( _RCC_CCIPR, HAL_LL_I2C1SEL1_BIT ); + } else { + clear_reg_bit( _RCC_APB1ENR1, HAL_LL_I2C1EN_BIT ); + clear_reg_bit( _RCC_CCIPR, HAL_LL_I2C1SEL1_BIT ); + } +} + + +static inline void hal_ll_i2c2_set_clock( bool hal_ll_state ) { + if ( hal_ll_state ) { + set_reg_bit( _RCC_APB1ENR1, HAL_LL_I2C2EN_BIT ); + set_reg_bit( _RCC_CCIPR, HAL_LL_I2C2SEL1_BIT ); + } else { + clear_reg_bit( _RCC_APB1ENR1, HAL_LL_I2C2EN_BIT ); + clear_reg_bit( _RCC_CCIPR, HAL_LL_I2C2SEL1_BIT ); + } +} + + +static inline void hal_ll_i2c3_set_clock( bool hal_ll_state ) { + if ( hal_ll_state ) { + set_reg_bit( _RCC_APB1ENR1, HAL_LL_I2C3EN_BIT ); + set_reg_bit( _RCC_CCIPR, HAL_LL_I2C3SEL1_BIT ); + } else { + clear_reg_bit( _RCC_APB1ENR1, HAL_LL_I2C3EN_BIT ); + clear_reg_bit( _RCC_CCIPR, HAL_LL_I2C3SEL1_BIT ); + } +} + + + +static hal_ll_err_t hal_ll_i2c_hw_init( hal_ll_i2c_hw_specifics_map_t *map ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct(map->base); + uint16_t time_counter = map->timeout; + + clear_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_I2C_PE_BIT ); + while ( check_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_I2C_PE_BIT ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_INIT; + } + } + + hal_ll_hw_reg->cr1 &= HAL_LL_I2C_FILTERS_OFF; + + hal_ll_hw_reg->timingr = hal_ll_i2c_get_speed( map ); + + hal_ll_hw_reg->cr1 |= HAL_LL_I2C_CR1_RXTX_INT; + + set_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_I2C_PE_BIT ); + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static hal_ll_err_t hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_t *map ) { + hal_ll_i2c_master_set_clock( map, true ); + + return hal_ll_i2c_hw_init( map ); +} +// ------------------------------------------------------------------------- END + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/one_wire/CMakeLists.txt b/targets/arm/mikroe/ai_generated/stm32/src/one_wire/CMakeLists.txt new file mode 100644 index 000000000..4de6cfa1c --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/one_wire/CMakeLists.txt @@ -0,0 +1,56 @@ +## ./targets/arm/mikroe/ai_generated/stm32/src/one_wire/CMakeLists.txt + +## Check if current module is generated or not +set(MODULE_IS_GENERATED false) +get_files_recurse(${CMAKE_CURRENT_LIST_DIR}/implementations CMAKE_FILES cmake) +check_if_module_is_generated(MODULE_IS_GENERATED "${CMAKE_FILES}") + +## If current MCU has this module, add it +if(MODULE_IS_GENERATED) + set(hal_ll_def_list "") + set(mcu_header_path "") + + find_cortex(hal_ll_def_list) + list(APPEND hal_ll_def_list ${MCU_NAME}) + set(mcu_header_path ${MCU_NAME}_${_MSDK_PACKAGE_ID_}) + + list(APPEND hal_ll_def_list "MACRO_USAGE_ONE_WIRE") + + ## i.e "if (${MCU_NAME} MATCHES "^STM32C011F6$|^STM32C011C6$")" + ## List all MCUs and or them in the regex + foreach(cmakeFile ${CMAKE_FILES}) + include(${cmakeFile}) + endforeach() + ## END ADC + + mikrosdk_add_library(lib_hal_ll_one_wire MikroSDK.HalLowLevel.OneWire + hal_ll_one_wire.c + ../../include/one_wire/hal_ll_one_wire.h + ) + + target_compile_definitions(lib_hal_ll_one_wire PUBLIC + ${hal_ll_def_list} + ) + + target_link_libraries(lib_hal_ll_one_wire PUBLIC + MikroC.Core + MikroSDK.HalLowLevel.GPIO + MikroSDK.HalLowLevelCommon + ) + + target_include_directories(lib_hal_ll_one_wire + PRIVATE + ../../include/one_wire + INTERFACE + # BUILD + $ + $ + $ + $ + # INSTALL + $ + ) + + mikrosdk_install(MikroSDK.HalLowLevel.OneWire) + install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.OneWire ../../include/one_wire/hal_ll_one_wire.h) +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/one_wire/implementations/.gitkeep b/targets/arm/mikroe/ai_generated/stm32/src/one_wire/implementations/.gitkeep new file mode 100644 index 000000000..e69de29bb diff --git a/targets/arm/mikroe/ai_generated/stm32/src/rtc/CMakeLists.txt b/targets/arm/mikroe/ai_generated/stm32/src/rtc/CMakeLists.txt new file mode 100644 index 000000000..7fb0e9323 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/rtc/CMakeLists.txt @@ -0,0 +1,55 @@ +## ./targets/arm/mikroe/ai_generated/stm32/src/rtc/CMakeLists.txt + +## Check if current module is generated or not +set(MODULE_IS_GENERATED false) +get_files_recurse(${CMAKE_CURRENT_LIST_DIR}/implementations CMAKE_FILES cmake) +check_if_module_is_generated(MODULE_IS_GENERATED "${CMAKE_FILES}") + +## If current MCU has this module, add it +if(MODULE_IS_GENERATED) + set(hal_ll_def_list "") + set(mcu_header_path "") + + find_cortex(hal_ll_def_list) + list(APPEND hal_ll_def_list ${MCU_NAME}) + set(mcu_header_path ${MCU_NAME}_${_MSDK_PACKAGE_ID_}) + + ## BEGIN RTC + list(APPEND hal_ll_def_list "MACRO_USAGE_RTC") + + ## i.e "if (${MCU_NAME} MATCHES "^STM32C011F6$|^STM32C011C6$")" + ## List all MCUs and or them in the regex + foreach(cmakeFile ${CMAKE_FILES}) + include(${cmakeFile}) + endforeach() + ## END RTC + + mikrosdk_add_library(lib_hal_ll_rtc MikroSDK.HalLowLevel.RTC + ${rtc_subimplementation} + ../../include/rtc/hal_ll_rtc.h + ) + + target_compile_definitions(lib_hal_ll_rtc PUBLIC + ${hal_ll_def_list} + ) + + target_link_libraries(lib_hal_ll_rtc PUBLIC + MikroC.Core + MikroSDK.HalInterface + MikroSDK.HalLowLevelCommon + ) + + target_include_directories(lib_hal_ll_rtc + PRIVATE + ../../include/rtc/ + INTERFACE + # BUILD + $ + $ + # INSTALL + $ + ) + + mikrosdk_install(MikroSDK.HalLowLevel.RTC) + install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.RTC ../../include/rtc/hal_ll_rtc.h) +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/rtc/implementations/.gitkeep b/targets/arm/mikroe/ai_generated/stm32/src/rtc/implementations/.gitkeep new file mode 100644 index 000000000..e69de29bb diff --git a/targets/arm/mikroe/ai_generated/stm32/src/spi_master/CMakeLists.txt b/targets/arm/mikroe/ai_generated/stm32/src/spi_master/CMakeLists.txt new file mode 100644 index 000000000..86f92ffec --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/spi_master/CMakeLists.txt @@ -0,0 +1,75 @@ +## ./targets/arm/mikroe/ai_generated/stm32/src/spi_master/CMakeLists.txt + +## Check if current module is generated or not +set(MODULE_IS_GENERATED false) +get_files_recurse(${CMAKE_CURRENT_LIST_DIR}/implementations CMAKE_FILES cmake) +check_if_module_is_generated(MODULE_IS_GENERATED "${CMAKE_FILES}") + +## If current MCU has this module, add it +if(MODULE_IS_GENERATED) + set(hal_ll_def_list "") + set(mcu_header_path "") + + find_cortex(hal_ll_def_list) + list(APPEND hal_ll_def_list ${MCU_NAME}) + set(mcu_header_path ${MCU_NAME}_${_MSDK_PACKAGE_ID_}) + + # BEGIN SPI + list(APPEND hal_ll_def_list "MACRO_USAGE_SPI") + + ## i.e "if (${MCU_NAME} MATCHES "^STM32C011F6$|^STM32C011C6$")" + ## List all MCUs and or them in the regex + foreach(cmakeFile ${CMAKE_FILES}) + include(${cmakeFile}) + endforeach() + # END SPI + + mikrosdk_add_library(lib_hal_ll_spi_master MikroSDK.HalLowLevel.SPI.Master + ${rcc_subimplementation}/hal_ll_rcc.h + ../../include/hal_ll_target.h + # BEGIN SPI + ${spi_subimplementation} + ../../include/spi_master/hal_ll_spi_master.h + ${spi_pin_map}/hal_ll_spi_master_pin_map.h + # END SPI + ) + + target_compile_definitions(lib_hal_ll_spi_master PUBLIC + ${hal_ll_def_list} + ) + + target_link_libraries(lib_hal_ll_spi_master PUBLIC + MikroC.Core + MikroSDK.HalLowLevelCore + MikroSDK.HalLowLevelCommon + ) + + string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) + target_include_directories(lib_hal_ll_spi_master + PRIVATE + ../../include + ../../include/gpio + ${gpio_subimplementation_include_dir} + # BEGIN SPI + ../../include/spi_master + ${spi_pin_map} + # END SPI + # BEGIN RCC + ${rcc_subimplementation} + # END RCC + INTERFACE + # BUILD + $ + $ + $ + $ + $ + $ + # INSTALL + $ + $ + ) + + mikrosdk_install(MikroSDK.HalLowLevel.SPI.Master) + install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.SPI.Master ../../include/spi_master/hal_ll_spi_master.h) +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_1/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_1/CMakeLists.cmake new file mode 100644 index 000000000..6cfcff2ff --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_1/CMakeLists.cmake @@ -0,0 +1,9 @@ +if(${MCU_NAME} MATCHES "^STM32C011F4$|^STM32C011J4$|^STM32C011F6$|^STM32C011J6$|^STM32C011D6$") + set(spi_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_spi_master.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_1") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_1") + list(APPEND hal_ll_def_list "STM32C0xx") + list(APPEND hal_ll_def_list "STM32C01xx") + list(APPEND hal_ll_def_list "STM32C011xx") + set(spi_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/spi_master/hal_ll_spi_master_pin_map/implementations/doc_ds_1") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_1/hal_ll_spi_master.c b/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_1/hal_ll_spi_master.c new file mode 100644 index 000000000..5f8db8d0f --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_1/hal_ll_spi_master.c @@ -0,0 +1,692 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_spi_master.c + * @brief SPI Master HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_rcc.h" +#include "hal_ll_spi_master.h" +#include "hal_ll_spi_master_pin_map.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_spi_master_handle_register_t hal_ll_module_state[SPI_MODULE_COUNT] = {(handle_t *)NULL, (handle_t *)NULL, false}; + +// ------------------------------------------------------------- PRIVATE MACROS + +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_spi_master_get_module_state_address ((hal_ll_spi_master_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_spi_master_get_handle (hal_ll_spi_master_handle_register_t *)hal_ll_spi_master_get_module_state_address->hal_ll_spi_master_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_spi_master_get_base_struct(_handle) ((hal_ll_spi_master_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_spi_master_get_base_from_hal_handle ((hal_ll_spi_master_hw_specifics_map_t *)((hal_ll_spi_master_handle_register_t *)\ + (((hal_ll_spi_master_handle_register_t *)(handle))->hal_ll_spi_master_handle))->hal_ll_spi_master_handle)->base + +/*!< CR1 constants. */ +#define HAL_LL_SPI_MASTER 0x4 +#define HAL_LL_SPI_MASTER_SSI_1 8 +#define HAL_LL_SPI_MASTER_SELECTION 2 +/*!< CR2 constants. */ +#define HAL_LL_SPI_MASTER_FRXTH 0x1000ul + +#define HAL_LL_SPI_MASTER_SSOE_BIT 2 +#define HAL_LL_SPI_MASTER_SSOE 0x4 +#define HAL_LL_SPI_MASTER_SSM_ENABLE 9 +#define HAL_LL_SPI_MASTER_SSM_DISABLE 0x0000u +#define HAL_LL_SPI_MASTER_SS_ENABLE 0x10000ul +#define HAL_LL_SPI_MASTER_SS_DISABLE 0x00000ul +/*!< SR constants. */ +#define HAL_LL_SPI_MASTER_RXNE 0 +#define HAL_LL_SPI_MASTER_TXE 1 +/*!< I2SCFGR constants. */ +#define HAL_LL_SPI_MASTER_I2SMOD 11 +/*!< Enable constants. */ +#define HAL_LL_SPI_MASTER_ENABLE 6 +#define HAL_LL_SPI1_MASTER_ENABLE 12 + +/*!< General constants. */ +#define HAL_LL_SPI_MASTER_BAUD_RATE_MASK 3 +#define HAL_LL_SPI_MASTER_16_BIT_REG_SHIFT 16 +#define HAL_LL_SPI_MASTER_DEFAULT_BASE_ADDRESS 0xFF + +#define HAL_LL_SPI_MASTER_CLK_POLARITY 1 +#define HAL_LL_SPI_MASTER_CLK_PHASE 0 + +#define hal_ll_spi_master_get_speed(_fosc,_speed) (_speed >= _fosc/2)? (0):\ + ((_speed <= _fosc/2) && (_speed > _fosc/4))? (0):\ + ((_speed <= _fosc/4) && (_speed > _fosc/8))? (0x0008UL):\ + ((_speed <= _fosc/8) && (_speed > _fosc/16))? (0x0010UL):\ + ((_speed <= _fosc/16) && (_speed > _fosc/32))? (0x0018UL):\ + ((_speed <= _fosc/32) && (_speed > _fosc/64))? (0x0020UL):\ + ((_speed <= _fosc/64) && (_speed > _fosc/128))?(0x0028UL):\ + ((_speed <= _fosc/128)&& (_speed > _fosc/256))?(0x0030UL):(0x0038UL) + +#define hal_ll_spi_master_get_actual_speed(_fosc,_divider) (_divider == 0)?(_fosc/2):\ + (_divider == 0x0008UL)?(_fosc/4):\ + (_divider == 0x0010UL)?(_fosc/8):\ + (_divider == 0x0018UL)?(_fosc/16):\ + (_divider == 0x0020UL)?(_fosc/32):\ + (_divider == 0x0028UL)?(_fosc/64):\ + (_divider == 0x0030UL)?(_fosc/128):\ + (_divider == 0x0038UL)?(_fosc/256):(_fosc/256) + +/*!< @brief Default SPI Master bit-rate if no speed is set */ +#define HAL_LL_SPI_MASTER_SPEED_100K 100000 + +// -------------------------------------------------------------- PRIVATE TYPES + +/*!< @brief SPI register structure. */ +typedef struct { + uint32_t cr1; + uint32_t cr2; + uint32_t sr; + uint32_t dr; + uint32_t crcpr; + uint32_t rxcrcr; + uint32_t txcrcr; + uint32_t i2scfgr0; + uint32_t i2spr; +} hal_ll_spi_master_base_handle_t; + +/*!< @brief SPI Master hardware specific structure */ +typedef struct { + hal_ll_base_addr_t base; + uint8_t module_index; + hal_ll_spi_master_pins_t pins; + uint8_t dummy_data; + uint32_t speed; + uint32_t hw_actual_speed; + hal_ll_spi_master_mode_t mode; +} hal_ll_spi_master_hw_specifics_map_t; + +/*!< @brief SPI hw specific module values */ +typedef struct +{ + uint16_t pin_sck; + uint16_t pin_miso; + uint16_t pin_mosi; +} hal_ll_spi_pin_id; + +/*!< @brief SPI Master hw specific error values */ +typedef enum { + HAL_LL_SPI_MASTER_SUCCESS = 0, + HAL_LL_SPI_MASTER_WRONG_PINS, + HAL_LL_SPI_MASTER_MODULE_ERROR, + + HAL_LL_SPI_MASTER_ERROR = (-1) +} hal_ll_spi_master_err_t; + +// ------------------------------------------------------------------ VARIABLES + +/*!< @brief SPI Master hardware specific info */ +static hal_ll_spi_master_hw_specifics_map_t hal_ll_spi_master_hw_specifics_map[] = { + #ifdef SPI_MODULE_1 + {HAL_LL_SPI1_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_1), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, HAL_LL_SPI_MASTER_SPEED_100K, 0, HAL_LL_SPI_MASTER_MODE_DEFAULT}, + #endif + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, 0, 0, 0} +}; + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_spi_master_handle_register_t *low_level_handle; +static volatile hal_ll_spi_master_hw_specifics_map_t *hal_ll_spi_master_hw_specifics_map_local; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Check if pins are adequate. + * + * Checks SCK, MISO and MOSI pins the user has passed with pre-defined + * pins in SCK, MISO and MOSI maps. Take into consideration that module + * index numbers have to be the same for both pins. + * + * @param[in] sck - SCK pre-defined pin name. + * @param[in] miso - MISO pre-defined pin name. + * @param[in] mosi - MOSI pre-defined pin name. + * @param[in] *index_list - Index list address + * @return hal_ll_pin_name_t Module index based on pins. + * + * Returns pre-defined module index from pin maps, if pins + * are adequate. + */ +static hal_ll_pin_name_t hal_ll_spi_master_check_pins(hal_ll_pin_name_t sck, hal_ll_pin_name_t miso, hal_ll_pin_name_t mosi, hal_ll_spi_pin_id *index_list, hal_ll_spi_master_handle_register_t *handle_map ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_spi_master_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_spi_master_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_spi_master_hw_specifics_map_t *hal_ll_get_specifics(handle_t handle); + +/** + * @brief Enable clock for SPI Master module on hardware level. + * + * Initializes SPI Master module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] *map - Object specific context handler. + * @param[in] hal_ll_state - True(enable clock)/False(disable clock). + * @param[in] *clock_value - SPI Master baud rate value taken from a specific peripheral clock bus. + * @return None + */ +static void hal_ll_spi_master_set_clock(hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state, uint32_t *clock_value); + +/** + * @brief Sets SPI Master pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if SPI is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param[in] *map - Object specific context handler. + * @param[in] hal_ll_state - Init/De-init + */ +static void hal_ll_spi_master_alternate_functions_set_state(hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state); + +/** + * @brief Full SPI Master module initialization procedure. + * + * Initializes SPI Master module on hardware level, based on beforehand + * set configuration and module handler. Sets adequate pin alternate functions. + * Initializes module clock. + * + * @param[in] *map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static void hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_t *map); + +/** + * @brief Perform a read on the SPI Master bus. + * + * Initializes SPI Master module on hardware level, if not initialized beforehand + * and continues to perform a read operation on the bus. + * + * @param[in] *map - Object specific context handler. + * @param[in] *read_data_buffer - Pointer to data buffer. + * @param[in] read_data_length - Number of data to be read. + * @param[in] dummy_data - Data required for read procedure. + * @return hal_ll_err_t Module specific error values. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +static void hal_ll_spi_master_read_bare_metal(hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *read_data_buffer, size_t read_data_length, uint8_t dummy_data); + +/** + * @brief Perform a write on the SPI Master bus. + * + * Initializes SPI Master module on hardware level, if not initialized beforehand + * and continues to perform a write operation on the bus. + * + * @param[in] map - Object specific context handler. + * @param[in] *write_data_buffer - Pointer to data buffer. + * @param[in] write_data_length - Number of data to be written. + * @return hal_ll_err_t Module specific error values. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +static void hal_ll_spi_master_write_bare_metal(hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *write_data_buffer, size_t write_data_length); + +/** + * @brief Perform a write then read on the SPI Master bus. + * + * Initializes SPI Master module on hardware level, if not initialized beforehand + * and continues to perform a write operation on the bus. + * + * @param[in] *handle - Object specific context handler. + * @param[in] *write_data_buffer - Pointer to data buffer. + * @param[in] length_write_data - Number of data to be written. + * @param[in] *read_data_buffer - Pointer to data buffer. + * @param[in] length_read_data - Number of data to be read. + * @return hal_ll_err_t Module specific error values. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_spi_master_write_then_read(handle_t *handle, uint8_t *write_data_buffer, size_t length_write_data, uint8_t *read_data_buffer, size_t length_read_data); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * SPI SCK, MISO and MOSI pins. + * + * @param[in] module_index SPI HW module index -- 0,1,2... + * @param[in] *index_list Array with SCK, MISO and MOSI map index values + * and module number + * + * @return None + */ +static void hal_ll_spi_master_map_pins(uint8_t module_index, hal_ll_spi_pin_id *index_list); + + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS + +hal_ll_err_t hal_ll_spi_master_register_handle(hal_ll_pin_name_t sck, hal_ll_pin_name_t miso, hal_ll_pin_name_t mosi, hal_ll_spi_master_handle_register_t *handle_map, uint8_t *hal_module_id) { + + hal_ll_spi_pin_id index_list[SPI_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + uint16_t pin_check_result; + + // Check user-defined pins. + if ((pin_check_result = hal_ll_spi_master_check_pins(sck, miso, mosi, &index_list, handle_map)) == HAL_LL_PIN_NC) { + return HAL_LL_SPI_MASTER_WRONG_PINS; + }; + + // If user has come with the same SPI hardware module, and with the same pair of the pins, the pin mapping procedure + // will not have to take a place; otherwise, clear af-s, map new pins, set af-s, and set init state to false. + if ((hal_ll_spi_master_hw_specifics_map[pin_check_result].pins.sck.pin_name != sck) || + (hal_ll_spi_master_hw_specifics_map[pin_check_result].pins.miso.pin_name != miso) || + (hal_ll_spi_master_hw_specifics_map[pin_check_result].pins.mosi.pin_name != mosi) ) { + + hal_ll_spi_master_alternate_functions_set_state(&hal_ll_spi_master_hw_specifics_map[pin_check_result], false); + + hal_ll_spi_master_map_pins(pin_check_result, &index_list); + + hal_ll_spi_master_alternate_functions_set_state(&hal_ll_spi_master_hw_specifics_map[pin_check_result], true); + + handle_map[pin_check_result].init_ll_state = false; + } + + // Return id of the SPI module that is going to be used. + *hal_module_id = pin_check_result; + + // Insert current module into hal_ll_module_state map. + hal_ll_module_state[pin_check_result].hal_ll_spi_master_handle = (handle_t *)&hal_ll_spi_master_hw_specifics_map[pin_check_result].base; + + // Return the same info about module one level up ( into the HAL level ). + handle_map[pin_check_result].hal_ll_spi_master_handle = (handle_t*)&hal_ll_module_state[pin_check_result].hal_ll_spi_master_handle; + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_spi(handle_t *handle) { + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + hal_ll_spi_master_handle_register_t *hal_handle = (hal_ll_spi_master_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_spi_master_hw_specifics_map_local->module_index; + + hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_local); + + hal_ll_module_state[pin_check_result].hal_ll_spi_master_handle = (handle_t *)&hal_ll_spi_master_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +void hal_ll_spi_master_set_default_write_data(handle_t *handle, uint8_t dummy_data) { + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + if(hal_ll_spi_master_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR) { + hal_ll_spi_master_hw_specifics_map_local->dummy_data = dummy_data; + } +} + +hal_ll_err_t hal_ll_spi_master_write(handle_t *handle, uint8_t *write_data_buffer, size_t length_data) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + hal_ll_spi_master_write_bare_metal(hal_ll_spi_master_hw_specifics_map_local->base, write_data_buffer, length_data); + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_spi_master_read(handle_t *handle, uint8_t *read_data_buffer, size_t length_data) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + hal_ll_spi_master_read_bare_metal(hal_ll_spi_master_hw_specifics_map_local->base, read_data_buffer, length_data, hal_ll_spi_master_hw_specifics_map_local->dummy_data); + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_spi_master_write_then_read(handle_t *handle, uint8_t *write_data_buffer, size_t length_write_data, uint8_t *read_data_buffer, size_t length_read_data) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + hal_ll_spi_master_write_bare_metal(hal_ll_spi_master_hw_specifics_map_local->base, write_data_buffer, length_write_data); + + hal_ll_spi_master_read_bare_metal(hal_ll_spi_master_hw_specifics_map_local->base, read_data_buffer, length_read_data, hal_ll_spi_master_hw_specifics_map_local->dummy_data); + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +uint32_t hal_ll_spi_master_set_speed(handle_t *handle, uint32_t speed) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + low_level_handle->init_ll_state = false; + + // Insert user-defined baud rate into local map. + hal_ll_spi_master_hw_specifics_map_local->speed = speed; + + // Init once again, but with updated SPI Master baud rate value. + hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + // Return value of the SPI Master baud rate value. + return hal_ll_spi_master_hw_specifics_map_local->hw_actual_speed; +} + +hal_ll_err_t hal_ll_spi_master_set_mode(handle_t *handle, hal_ll_spi_master_mode_t mode) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + low_level_handle->init_ll_state = false; + + // Insert user-defined mode into local map. + hal_ll_spi_master_hw_specifics_map_local->mode = mode; + + // Init once again, but with updated SPI Master mode value. + hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +void hal_ll_spi_master_close(handle_t* handle) { + uint32_t dummy; + low_level_handle = hal_ll_spi_master_get_handle; + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + if(low_level_handle->hal_ll_spi_master_handle != NULL) { + low_level_handle->hal_ll_spi_master_handle = NULL; + low_level_handle->hal_drv_spi_master_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_spi_master_hw_specifics_map_local->mode = HAL_LL_SPI_MASTER_MODE_DEFAULT; + hal_ll_spi_master_hw_specifics_map_local->speed = HAL_LL_SPI_MASTER_SPEED_100K; + hal_ll_spi_master_hw_specifics_map_local->dummy_data = 0; + hal_ll_spi_master_hw_specifics_map_local->hw_actual_speed = 0; + + hal_ll_spi_master_set_clock(hal_ll_spi_master_hw_specifics_map_local, true, &dummy); + hal_ll_spi_master_alternate_functions_set_state(hal_ll_spi_master_hw_specifics_map_local, false); + hal_ll_spi_master_set_clock(hal_ll_spi_master_hw_specifics_map_local, false, &dummy); + + hal_ll_spi_master_hw_specifics_map_local->pins.sck.pin_name = HAL_LL_PIN_NC; + hal_ll_spi_master_hw_specifics_map_local->pins.miso.pin_name = HAL_LL_PIN_NC; + hal_ll_spi_master_hw_specifics_map_local->pins.mosi.pin_name = HAL_LL_PIN_NC; + hal_ll_spi_master_hw_specifics_map_local->pins.sck.pin_af = 0; + hal_ll_spi_master_hw_specifics_map_local->pins.miso.pin_af = 0; + hal_ll_spi_master_hw_specifics_map_local->pins.mosi.pin_af = 0; + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS + +uint8_t hal_ll_spi_master_transfer_bare_metal(hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t data_buffer) { + // Write user-defined data ( 'hal_ll_spi_master_read_bare_metal' procedure will send dummy data ). + *((volatile uint8_t *)&hal_ll_hw_reg->dr) = (uint8_t)data_buffer; // 8-bit data + + // Wait for receive buffer not empty status. + while (!(check_reg_bit( &(hal_ll_hw_reg->sr), HAL_LL_SPI_MASTER_RXNE))); + + // Return read data. + return *((volatile uint8_t *)&hal_ll_hw_reg->dr); // 8-bit data +} + +static void hal_ll_spi_master_write_bare_metal( hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *write_data_buffer, size_t write_data_length ) { + uint16_t transfer_counter = NULL; + + // Write the first data to be transmitted into the SPI_DR register. + for(transfer_counter = 0; transfer_counter < write_data_length; transfer_counter++) { + // If we are good to go ( if the tx buffer value has been shifted to the shift register ), write the data. + hal_ll_spi_master_transfer_bare_metal( hal_ll_hw_reg, write_data_buffer[transfer_counter]); + } +} + +static void hal_ll_spi_master_read_bare_metal(hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *read_data_buffer, size_t read_data_length, uint8_t dummy_data) { + uint16_t transfer_counter = NULL; + + // Read the first data to be transmitted into the SPI_DR register. + for(transfer_counter = 0; transfer_counter < read_data_length; transfer_counter++) { + // If we are good to go ( if the value from shift register has been shifted to the rx register ), read the data. + read_data_buffer[transfer_counter] = hal_ll_spi_master_transfer_bare_metal(hal_ll_hw_reg, dummy_data); + } +} + +static hal_ll_pin_name_t hal_ll_spi_master_check_pins(hal_ll_pin_name_t sck_pin, hal_ll_pin_name_t miso_pin, hal_ll_pin_name_t mosi_pin, hal_ll_spi_pin_id *index_list, hal_ll_spi_master_handle_register_t *handle_map) { + static const uint16_t sck_map_size = (sizeof(_spi_sck_map)) / (sizeof(hal_ll_spi_master_pin_map_t)); + static const uint16_t miso_map_size = (sizeof(_spi_miso_map)) / (sizeof(hal_ll_spi_master_pin_map_t)); + static const uint16_t mosi_map_size = (sizeof(_spi_mosi_map)) / (sizeof(hal_ll_spi_master_pin_map_t)); + uint8_t hal_ll_module_id = 0; + uint8_t index_counter = 0; + uint16_t miso_index; + uint16_t mosi_index; + uint16_t sck_index; + + if ( (HAL_LL_PIN_NC == sck_pin) || (HAL_LL_PIN_NC == miso_pin) || (HAL_LL_PIN_NC == mosi_pin) ) { + return HAL_LL_PIN_NC; + } + + // Check pins from the specific pin maps with the user defined pins. + for (sck_index = 0; sck_index < sck_map_size; sck_index++) { + if (_spi_sck_map[sck_index].pin == sck_pin) { + for (miso_index = 0; miso_index < miso_map_size; miso_index++) { + if (_spi_miso_map[miso_index].pin == miso_pin) { + if (_spi_sck_map[sck_index].module_index ==_spi_miso_map[miso_index].module_index) { + for (mosi_index = 0; mosi_index < mosi_map_size; mosi_index++) { + if (_spi_mosi_map[mosi_index ].pin == mosi_pin) { + if (_spi_sck_map[sck_index].module_index ==_spi_mosi_map[mosi_index].module_index) { + // Get module number + hal_ll_module_id = _spi_sck_map[ sck_index ].module_index; + + // Map pin names + index_list[hal_ll_module_id].pin_sck = sck_index; + index_list[hal_ll_module_id].pin_miso = miso_index; + index_list[hal_ll_module_id].pin_mosi = mosi_index; + + // Check if module is taken + if ( NULL == handle_map[hal_ll_module_id].hal_drv_spi_master_handle ) { + return hal_ll_module_id; + } else if ( SPI_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + } + } + } + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static void hal_ll_spi_master_map_pins(uint8_t module_index, hal_ll_spi_pin_id *index_list) { + // if every single pin is OK, insert them into this new map, and use this map in all low level functions. + hal_ll_spi_master_hw_specifics_map[module_index].pins.sck.pin_name = _spi_sck_map[index_list[module_index].pin_sck].pin; + hal_ll_spi_master_hw_specifics_map[module_index].pins.miso.pin_name = _spi_miso_map[index_list[module_index].pin_miso].pin; + hal_ll_spi_master_hw_specifics_map[module_index].pins.mosi.pin_name = _spi_mosi_map[index_list[module_index].pin_mosi].pin; + + // SCK, MISO and MOSI pins could have different alternate function settings, hence save all the AF-s. + hal_ll_spi_master_hw_specifics_map[module_index].pins.sck.pin_af = _spi_sck_map[index_list[module_index].pin_sck].af; + hal_ll_spi_master_hw_specifics_map[module_index].pins.miso.pin_af = _spi_miso_map[index_list[module_index].pin_miso].af; + hal_ll_spi_master_hw_specifics_map[module_index].pins.mosi.pin_af = _spi_mosi_map[index_list[module_index].pin_mosi].af; +} + +static hal_ll_spi_master_hw_specifics_map_t *hal_ll_get_specifics(handle_t handle) { + uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof( hal_ll_spi_master_handle_register_t)); + + static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof( hal_ll_spi_master_handle_register_t)); + + while (hal_ll_module_count--) { + if (hal_ll_spi_master_get_base_from_hal_handle == hal_ll_spi_master_hw_specifics_map[hal_ll_module_count].base) { + return &hal_ll_spi_master_hw_specifics_map[hal_ll_module_count]; + } + } + + // If NOK, return pointer to the last row of this map ( point to null pointer ). + return &hal_ll_spi_master_hw_specifics_map[hal_ll_module_error]; +} + +static void hal_ll_spi_master_set_clock(hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state, uint32_t *clock_value) { + rcc_clocks_t hal_ll_spi_clock_structure; + + RCC_GetClocksFrequency(&hal_ll_spi_clock_structure); + + switch (map->module_index) { + #if defined(SPI_MODULE_1) + case (hal_ll_spi_master_module_num(SPI_MODULE_1)): + if(hal_ll_state) { + set_reg_bit(_RCC_APBENR2, HAL_LL_SPI1_MASTER_ENABLE); + } else { + clear_reg_bit(_RCC_APBENR2, HAL_LL_SPI1_MASTER_ENABLE); + } + *clock_value = hal_ll_spi_clock_structure.pclk; + break; + #endif + } +} + +static void hal_ll_spi_master_alternate_functions_set_state(hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state) { + module_struct module; + uint32_t spi_config; + + if((map->pins.sck.pin_name != HAL_LL_PIN_NC) && (map->pins.miso.pin_name != HAL_LL_PIN_NC) && (map->pins.miso.pin_name != HAL_LL_PIN_NC)) { + module.pins[0] = VALUE(map->pins.sck.pin_name, map->pins.sck.pin_af); + module.pins[1] = VALUE(map->pins.miso.pin_name, map->pins.miso.pin_af); + module.pins[2] = VALUE(map->pins.mosi.pin_name, map->pins.mosi.pin_af); + module.pins[3] = GPIO_MODULE_STRUCT_END; + + spi_config = GPIO_CFG_MODE_ALT_FUNCTION | + GPIO_CFG_SPEED_HIGH | + GPIO_CFG_OTYPE_PP; + + module.configs[0] = spi_config; + module.configs[1] = spi_config; + module.configs[2] = spi_config; + module.configs[3] = GPIO_MODULE_STRUCT_END; + + module.gpio_remap = map->pins.sck.pin_af; + + hal_ll_gpio_module_struct_init(&module, hal_ll_state); + } +} + +static uint32_t hal_ll_spi_master_hw_init(hal_ll_spi_master_hw_specifics_map_t *map, uint32_t clock_value) { + uint32_t temp_speed; + + hal_ll_spi_master_base_handle_t *hal_ll_hw_reg = (hal_ll_spi_master_base_handle_t *)map->base; + + // Reset all the settings in control register. + hal_ll_hw_reg->cr1 = 0; + + // Populate appropriate register values to get appropriate data transfer baud rate prescalers. + temp_speed = hal_ll_spi_master_get_speed(clock_value, map->speed); + hal_ll_hw_reg->cr1 |= temp_speed; + + // Choose whether idle state for the clock is high level (1) or low level (0). + if (map->mode <= HAL_LL_SPI_MASTER_MODE_1) { + clear_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_CLK_POLARITY); + } else { + set_reg_bit(&( hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_CLK_POLARITY); + } + + // Choose whether transmit occurs on the transition from ACTIVE to IDLE (1), or vice versa (0). + if (map->mode == HAL_LL_SPI_MASTER_MODE_0 || map->mode == HAL_LL_SPI_MASTER_MODE_2) { + clear_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_CLK_PHASE); + } else { + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_CLK_PHASE); + } + + // Set default values for SPI Master configuration. + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_SSM_ENABLE); + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_SSI_1); + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_SELECTION); + + // Set Slave Select Output Enable bit. + set_reg_bit(&(hal_ll_hw_reg->cr2), HAL_LL_SPI_MASTER_SSOE_BIT); + + // Set FIFO reception threshold to 8-bit. + hal_ll_hw_reg->cr2 |= HAL_LL_SPI_MASTER_FRXTH; + + // Enable SPI peripheral. + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_ENABLE); + + return (hal_ll_spi_master_get_actual_speed(clock_value, temp_speed)); +} + +static void hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_t *map) { + uint32_t clock_value; + + // Enable specific clock module. + hal_ll_spi_master_set_clock(map, true, &clock_value); + + // Enable specific alternate functions. + hal_ll_spi_master_alternate_functions_set_state(map, true); + + // Finally, write user-defined settings into hardware registers. + hal_ll_spi_master_hw_init(map, clock_value); +} +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_160/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_160/CMakeLists.cmake new file mode 100644 index 000000000..6a5f6793b --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_160/CMakeLists.cmake @@ -0,0 +1,9 @@ +if(${MCU_NAME} MATCHES "^STM32L4P5AE$|^STM32L4P5AG$|^STM32L4P5CE$|^STM32L4P5CG$|^STM32L4P5QE$|^STM32L4P5QG$|^STM32L4P5RE$|^STM32L4P5RG$|^STM32L4P5VE$|^STM32L4P5VG$|^STM32L4P5ZE$|^STM32L4P5ZG$") + set(spi_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_spi_master.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_160") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_160") + list(APPEND hal_ll_def_list "STM32L4xx") + list(APPEND hal_ll_def_list "STM32L4Pxx") + list(APPEND hal_ll_def_list "STM32L4P5xx") + set(spi_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/spi_master/hal_ll_spi_master_pin_map/implementations/doc_ds_160") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_160/hal_ll_spi_master.c b/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_160/hal_ll_spi_master.c new file mode 100644 index 000000000..0e9929ee2 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_160/hal_ll_spi_master.c @@ -0,0 +1,720 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_spi_master.c + * @brief SPI Master HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_rcc.h" +#include "hal_ll_spi_master.h" +#include "hal_ll_spi_master_pin_map.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_spi_master_handle_register_t hal_ll_module_state[SPI_MODULE_COUNT] = {(handle_t *)NULL, (handle_t *)NULL, false}; + +// ------------------------------------------------------------- PRIVATE MACROS + +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_spi_master_get_module_state_address ((hal_ll_spi_master_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_spi_master_get_handle (hal_ll_spi_master_handle_register_t *)hal_ll_spi_master_get_module_state_address->hal_ll_spi_master_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_spi_master_get_base_struct(_handle) ((hal_ll_spi_master_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_spi_master_get_base_from_hal_handle ((hal_ll_spi_master_hw_specifics_map_t *)((hal_ll_spi_master_handle_register_t *)\ + (((hal_ll_spi_master_handle_register_t *)(handle))->hal_ll_spi_master_handle))->hal_ll_spi_master_handle)->base + +/*!< CR1 constants. */ +#define HAL_LL_SPI_MASTER 0x4 +#define HAL_LL_SPI_MASTER_SSI_1 8 +#define HAL_LL_SPI_MASTER_SELECTION 2 +/*!< CR2 constants. */ +#define HAL_LL_SPI_MASTER_FRXTH 0x1000ul + +#define HAL_LL_SPI_MASTER_SSOE_BIT 2 +#define HAL_LL_SPI_MASTER_SSOE 0x4 +#define HAL_LL_SPI_MASTER_SSM_ENABLE 9 +#define HAL_LL_SPI_MASTER_SSM_DISABLE 0x0000u +#define HAL_LL_SPI_MASTER_SS_ENABLE 0x10000ul +#define HAL_LL_SPI_MASTER_SS_DISABLE 0x00000ul +/*!< SR constants. */ +#define HAL_LL_SPI_MASTER_RXNE 0 +#define HAL_LL_SPI_MASTER_TXE 1 +/*!< I2SCFGR constants. */ +#define HAL_LL_SPI_MASTER_I2SMOD 11 +/*!< Enable constants. */ +#define HAL_LL_SPI_MASTER_ENABLE 6 +#define HAL_LL_SPI1_MASTER_ENABLE 12 + +#define HAL_LL_SPI2_MASTER_ENABLE 14 + +#define HAL_LL_SPI3_MASTER_ENABLE 15 + +/*!< General constants. */ +#define HAL_LL_SPI_MASTER_BAUD_RATE_MASK 3 +#define HAL_LL_SPI_MASTER_16_BIT_REG_SHIFT 16 +#define HAL_LL_SPI_MASTER_DEFAULT_BASE_ADDRESS 0xFF + +#define HAL_LL_SPI_MASTER_CLK_POLARITY 1 +#define HAL_LL_SPI_MASTER_CLK_PHASE 0 + +#define hal_ll_spi_master_get_speed(_fosc,_speed) (_speed >= _fosc/2)? (0):\ + ((_speed <= _fosc/2) && (_speed > _fosc/4))? (0):\ + ((_speed <= _fosc/4) && (_speed > _fosc/8))? (0x0008UL):\ + ((_speed <= _fosc/8) && (_speed > _fosc/16))? (0x0010UL):\ + ((_speed <= _fosc/16) && (_speed > _fosc/32))? (0x0018UL):\ + ((_speed <= _fosc/32) && (_speed > _fosc/64))? (0x0020UL):\ + ((_speed <= _fosc/64) && (_speed > _fosc/128))?(0x0028UL):\ + ((_speed <= _fosc/128)&& (_speed > _fosc/256))?(0x0030UL):(0x0038UL) + +#define hal_ll_spi_master_get_actual_speed(_fosc,_divider) (_divider == 0)?(_fosc/2):\ + (_divider == 0x0008UL)?(_fosc/4):\ + (_divider == 0x0010UL)?(_fosc/8):\ + (_divider == 0x0018UL)?(_fosc/16):\ + (_divider == 0x0020UL)?(_fosc/32):\ + (_divider == 0x0028UL)?(_fosc/64):\ + (_divider == 0x0030UL)?(_fosc/128):\ + (_divider == 0x0038UL)?(_fosc/256):(_fosc/256) + +/*!< @brief Default SPI Master bit-rate if no speed is set */ +#define HAL_LL_SPI_MASTER_SPEED_100K 100000 + +// -------------------------------------------------------------- PRIVATE TYPES + +/*!< @brief SPI register structure. */ +typedef struct { + uint32_t cr1; + uint32_t cr2; + uint32_t sr; + uint32_t dr; + uint32_t crcpr; + uint32_t rxcrcr; + uint32_t txcrcr; +} hal_ll_spi_master_base_handle_t; + +/*!< @brief SPI Master hardware specific structure */ +typedef struct { + hal_ll_base_addr_t base; + uint8_t module_index; + hal_ll_spi_master_pins_t pins; + uint8_t dummy_data; + uint32_t speed; + uint32_t hw_actual_speed; + hal_ll_spi_master_mode_t mode; +} hal_ll_spi_master_hw_specifics_map_t; + +/*!< @brief SPI hw specific module values */ +typedef struct +{ + uint16_t pin_sck; + uint16_t pin_miso; + uint16_t pin_mosi; +} hal_ll_spi_pin_id; + +/*!< @brief SPI Master hw specific error values */ +typedef enum { + HAL_LL_SPI_MASTER_SUCCESS = 0, + HAL_LL_SPI_MASTER_WRONG_PINS, + HAL_LL_SPI_MASTER_MODULE_ERROR, + + HAL_LL_SPI_MASTER_ERROR = (-1) +} hal_ll_spi_master_err_t; + +// ------------------------------------------------------------------ VARIABLES + +/*!< @brief SPI Master hardware specific info */ +static hal_ll_spi_master_hw_specifics_map_t hal_ll_spi_master_hw_specifics_map[] = { + #ifdef SPI_MODULE_1 + {HAL_LL_SPI1_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_1), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, HAL_LL_SPI_MASTER_SPEED_100K, 0, HAL_LL_SPI_MASTER_MODE_DEFAULT}, + #endif + #ifdef SPI_MODULE_2 + {HAL_LL_SPI2_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_2), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, HAL_LL_SPI_MASTER_SPEED_100K, 0, HAL_LL_SPI_MASTER_MODE_DEFAULT}, + #endif + #ifdef SPI_MODULE_3 + {HAL_LL_SPI3_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_3), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, HAL_LL_SPI_MASTER_SPEED_100K, 0, HAL_LL_SPI_MASTER_MODE_DEFAULT}, + #endif + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, 0, 0, 0} +}; + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_spi_master_handle_register_t *low_level_handle; +static volatile hal_ll_spi_master_hw_specifics_map_t *hal_ll_spi_master_hw_specifics_map_local; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Check if pins are adequate. + * + * Checks SCK, MISO and MOSI pins the user has passed with pre-defined + * pins in SCK, MISO and MOSI maps. Take into consideration that module + * index numbers have to be the same for both pins. + * + * @param[in] sck - SCK pre-defined pin name. + * @param[in] miso - MISO pre-defined pin name. + * @param[in] mosi - MOSI pre-defined pin name. + * @param[in] *index_list - Index list address + * @return hal_ll_pin_name_t Module index based on pins. + * + * Returns pre-defined module index from pin maps, if pins + * are adequate. + */ +static hal_ll_pin_name_t hal_ll_spi_master_check_pins(hal_ll_pin_name_t sck, hal_ll_pin_name_t miso, hal_ll_pin_name_t mosi, hal_ll_spi_pin_id *index_list, hal_ll_spi_master_handle_register_t *handle_map ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_spi_master_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_spi_master_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_spi_master_hw_specifics_map_t *hal_ll_get_specifics(handle_t handle); + +/** + * @brief Enable clock for SPI Master module on hardware level. + * + * Initializes SPI Master module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] *map - Object specific context handler. + * @param[in] hal_ll_state - True(enable clock)/False(disable clock). + * @param[in] *clock_value - SPI Master baud rate value taken from a specific peripheral clock bus. + * @return None + */ +static void hal_ll_spi_master_set_clock(hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state, uint32_t *clock_value); + +/** + * @brief Sets SPI Master pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if SPI is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param[in] *map - Object specific context handler. + * @param[in] hal_ll_state - Init/De-init + */ +static void hal_ll_spi_master_alternate_functions_set_state(hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state); + +/** + * @brief Full SPI Master module initialization procedure. + * + * Initializes SPI Master module on hardware level, based on beforehand + * set configuration and module handler. Sets adequate pin alternate functions. + * Initializes module clock. + * + * @param[in] *map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static void hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_t *map); + +/** + * @brief Perform a read on the SPI Master bus. + * + * Initializes SPI Master module on hardware level, if not initialized beforehand + * and continues to perform a read operation on the bus. + * + * @param[in] *map - Object specific context handler. + * @param[in] *read_data_buffer - Pointer to data buffer. + * @param[in] read_data_length - Number of data to be read. + * @param[in] dummy_data - Data required for read procedure. + * @return hal_ll_err_t Module specific error values. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +static void hal_ll_spi_master_read_bare_metal(hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *read_data_buffer, size_t read_data_length, uint8_t dummy_data); + +/** + * @brief Perform a write on the SPI Master bus. + * + * Initializes SPI Master module on hardware level, if not initialized beforehand + * and continues to perform a write operation on the bus. + * + * @param[in] map - Object specific context handler. + * @param[in] *write_data_buffer - Pointer to data buffer. + * @param[in] write_data_length - Number of data to be written. + * @return hal_ll_err_t Module specific error values. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +static void hal_ll_spi_master_write_bare_metal(hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *write_data_buffer, size_t write_data_length); + +/** + * @brief Perform a write then read on the SPI Master bus. + * + * Initializes SPI Master module on hardware level, if not initialized beforehand + * and continues to perform a write operation on the bus. + * + * @param[in] *handle - Object specific context handler. + * @param[in] *write_data_buffer - Pointer to data buffer. + * @param[in] length_write_data - Number of data to be written. + * @param[in] *read_data_buffer - Pointer to data buffer. + * @param[in] length_read_data - Number of data to be read. + * @return hal_ll_err_t Module specific error values. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_spi_master_write_then_read(handle_t *handle, uint8_t *write_data_buffer, size_t length_write_data, uint8_t *read_data_buffer, size_t length_read_data); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * SPI SCK, MISO and MOSI pins. + * + * @param[in] module_index SPI HW module index -- 0,1,2... + * @param[in] *index_list Array with SCK, MISO and MOSI map index values + * and module number + * + * @return None + */ +static void hal_ll_spi_master_map_pins(uint8_t module_index, hal_ll_spi_pin_id *index_list); + + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS + +hal_ll_err_t hal_ll_spi_master_register_handle(hal_ll_pin_name_t sck, hal_ll_pin_name_t miso, hal_ll_pin_name_t mosi, hal_ll_spi_master_handle_register_t *handle_map, uint8_t *hal_module_id) { + + hal_ll_spi_pin_id index_list[SPI_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + uint16_t pin_check_result; + + // Check user-defined pins. + if ((pin_check_result = hal_ll_spi_master_check_pins(sck, miso, mosi, &index_list, handle_map)) == HAL_LL_PIN_NC) { + return HAL_LL_SPI_MASTER_WRONG_PINS; + }; + + // If user has come with the same SPI hardware module, and with the same pair of the pins, the pin mapping procedure + // will not have to take a place; otherwise, clear af-s, map new pins, set af-s, and set init state to false. + if ((hal_ll_spi_master_hw_specifics_map[pin_check_result].pins.sck.pin_name != sck) || + (hal_ll_spi_master_hw_specifics_map[pin_check_result].pins.miso.pin_name != miso) || + (hal_ll_spi_master_hw_specifics_map[pin_check_result].pins.mosi.pin_name != mosi) ) { + + hal_ll_spi_master_alternate_functions_set_state(&hal_ll_spi_master_hw_specifics_map[pin_check_result], false); + + hal_ll_spi_master_map_pins(pin_check_result, &index_list); + + hal_ll_spi_master_alternate_functions_set_state(&hal_ll_spi_master_hw_specifics_map[pin_check_result], true); + + handle_map[pin_check_result].init_ll_state = false; + } + + // Return id of the SPI module that is going to be used. + *hal_module_id = pin_check_result; + + // Insert current module into hal_ll_module_state map. + hal_ll_module_state[pin_check_result].hal_ll_spi_master_handle = (handle_t *)&hal_ll_spi_master_hw_specifics_map[pin_check_result].base; + + // Return the same info about module one level up ( into the HAL level ). + handle_map[pin_check_result].hal_ll_spi_master_handle = (handle_t*)&hal_ll_module_state[pin_check_result].hal_ll_spi_master_handle; + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_spi(handle_t *handle) { + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + hal_ll_spi_master_handle_register_t *hal_handle = (hal_ll_spi_master_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_spi_master_hw_specifics_map_local->module_index; + + hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_local); + + hal_ll_module_state[pin_check_result].hal_ll_spi_master_handle = (handle_t *)&hal_ll_spi_master_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +void hal_ll_spi_master_set_default_write_data(handle_t *handle, uint8_t dummy_data) { + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + if(hal_ll_spi_master_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR) { + hal_ll_spi_master_hw_specifics_map_local->dummy_data = dummy_data; + } +} + +hal_ll_err_t hal_ll_spi_master_write(handle_t *handle, uint8_t *write_data_buffer, size_t length_data) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + hal_ll_spi_master_write_bare_metal(hal_ll_spi_master_hw_specifics_map_local->base, write_data_buffer, length_data); + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_spi_master_read(handle_t *handle, uint8_t *read_data_buffer, size_t length_data) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + hal_ll_spi_master_read_bare_metal(hal_ll_spi_master_hw_specifics_map_local->base, read_data_buffer, length_data, hal_ll_spi_master_hw_specifics_map_local->dummy_data); + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_spi_master_write_then_read(handle_t *handle, uint8_t *write_data_buffer, size_t length_write_data, uint8_t *read_data_buffer, size_t length_read_data) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + hal_ll_spi_master_write_bare_metal(hal_ll_spi_master_hw_specifics_map_local->base, write_data_buffer, length_write_data); + + hal_ll_spi_master_read_bare_metal(hal_ll_spi_master_hw_specifics_map_local->base, read_data_buffer, length_read_data, hal_ll_spi_master_hw_specifics_map_local->dummy_data); + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +uint32_t hal_ll_spi_master_set_speed(handle_t *handle, uint32_t speed) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + low_level_handle->init_ll_state = false; + + // Insert user-defined baud rate into local map. + hal_ll_spi_master_hw_specifics_map_local->speed = speed; + + // Init once again, but with updated SPI Master baud rate value. + hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + // Return value of the SPI Master baud rate value. + return hal_ll_spi_master_hw_specifics_map_local->hw_actual_speed; +} + +hal_ll_err_t hal_ll_spi_master_set_mode(handle_t *handle, hal_ll_spi_master_mode_t mode) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + low_level_handle->init_ll_state = false; + + // Insert user-defined mode into local map. + hal_ll_spi_master_hw_specifics_map_local->mode = mode; + + // Init once again, but with updated SPI Master mode value. + hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +void hal_ll_spi_master_close(handle_t* handle) { + uint32_t dummy; + low_level_handle = hal_ll_spi_master_get_handle; + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + if(low_level_handle->hal_ll_spi_master_handle != NULL) { + low_level_handle->hal_ll_spi_master_handle = NULL; + low_level_handle->hal_drv_spi_master_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_spi_master_hw_specifics_map_local->mode = HAL_LL_SPI_MASTER_MODE_DEFAULT; + hal_ll_spi_master_hw_specifics_map_local->speed = HAL_LL_SPI_MASTER_SPEED_100K; + hal_ll_spi_master_hw_specifics_map_local->dummy_data = 0; + hal_ll_spi_master_hw_specifics_map_local->hw_actual_speed = 0; + + hal_ll_spi_master_set_clock(hal_ll_spi_master_hw_specifics_map_local, true, &dummy); + hal_ll_spi_master_alternate_functions_set_state(hal_ll_spi_master_hw_specifics_map_local, false); + hal_ll_spi_master_set_clock(hal_ll_spi_master_hw_specifics_map_local, false, &dummy); + + hal_ll_spi_master_hw_specifics_map_local->pins.sck.pin_name = HAL_LL_PIN_NC; + hal_ll_spi_master_hw_specifics_map_local->pins.miso.pin_name = HAL_LL_PIN_NC; + hal_ll_spi_master_hw_specifics_map_local->pins.mosi.pin_name = HAL_LL_PIN_NC; + hal_ll_spi_master_hw_specifics_map_local->pins.sck.pin_af = 0; + hal_ll_spi_master_hw_specifics_map_local->pins.miso.pin_af = 0; + hal_ll_spi_master_hw_specifics_map_local->pins.mosi.pin_af = 0; + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS + +uint8_t hal_ll_spi_master_transfer_bare_metal(hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t data_buffer) { + // Write user-defined data ( 'hal_ll_spi_master_read_bare_metal' procedure will send dummy data ). + *((volatile uint8_t *)&hal_ll_hw_reg->dr) = (uint8_t)data_buffer; // 8-bit data + + // Wait for receive buffer not empty status. + while (!(check_reg_bit( &(hal_ll_hw_reg->sr), HAL_LL_SPI_MASTER_RXNE))); + + // Return read data. + return *((volatile uint8_t *)&hal_ll_hw_reg->dr); // 8-bit data +} + +static void hal_ll_spi_master_write_bare_metal( hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *write_data_buffer, size_t write_data_length ) { + uint16_t transfer_counter = NULL; + + // Write the first data to be transmitted into the SPI_DR register. + for(transfer_counter = 0; transfer_counter < write_data_length; transfer_counter++) { + // If we are good to go ( if the tx buffer value has been shifted to the shift register ), write the data. + hal_ll_spi_master_transfer_bare_metal( hal_ll_hw_reg, write_data_buffer[transfer_counter]); + } +} + +static void hal_ll_spi_master_read_bare_metal(hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *read_data_buffer, size_t read_data_length, uint8_t dummy_data) { + uint16_t transfer_counter = NULL; + + // Read the first data to be transmitted into the SPI_DR register. + for(transfer_counter = 0; transfer_counter < read_data_length; transfer_counter++) { + // If we are good to go ( if the value from shift register has been shifted to the rx register ), read the data. + read_data_buffer[transfer_counter] = hal_ll_spi_master_transfer_bare_metal(hal_ll_hw_reg, dummy_data); + } +} + +static hal_ll_pin_name_t hal_ll_spi_master_check_pins(hal_ll_pin_name_t sck_pin, hal_ll_pin_name_t miso_pin, hal_ll_pin_name_t mosi_pin, hal_ll_spi_pin_id *index_list, hal_ll_spi_master_handle_register_t *handle_map) { + static const uint16_t sck_map_size = (sizeof(_spi_sck_map)) / (sizeof(hal_ll_spi_master_pin_map_t)); + static const uint16_t miso_map_size = (sizeof(_spi_miso_map)) / (sizeof(hal_ll_spi_master_pin_map_t)); + static const uint16_t mosi_map_size = (sizeof(_spi_mosi_map)) / (sizeof(hal_ll_spi_master_pin_map_t)); + uint8_t hal_ll_module_id = 0; + uint8_t index_counter = 0; + uint16_t miso_index; + uint16_t mosi_index; + uint16_t sck_index; + + if ( (HAL_LL_PIN_NC == sck_pin) || (HAL_LL_PIN_NC == miso_pin) || (HAL_LL_PIN_NC == mosi_pin) ) { + return HAL_LL_PIN_NC; + } + + // Check pins from the specific pin maps with the user defined pins. + for (sck_index = 0; sck_index < sck_map_size; sck_index++) { + if (_spi_sck_map[sck_index].pin == sck_pin) { + for (miso_index = 0; miso_index < miso_map_size; miso_index++) { + if (_spi_miso_map[miso_index].pin == miso_pin) { + if (_spi_sck_map[sck_index].module_index ==_spi_miso_map[miso_index].module_index) { + for (mosi_index = 0; mosi_index < mosi_map_size; mosi_index++) { + if (_spi_mosi_map[mosi_index ].pin == mosi_pin) { + if (_spi_sck_map[sck_index].module_index ==_spi_mosi_map[mosi_index].module_index) { + // Get module number + hal_ll_module_id = _spi_sck_map[ sck_index ].module_index; + + // Map pin names + index_list[hal_ll_module_id].pin_sck = sck_index; + index_list[hal_ll_module_id].pin_miso = miso_index; + index_list[hal_ll_module_id].pin_mosi = mosi_index; + + // Check if module is taken + if ( NULL == handle_map[hal_ll_module_id].hal_drv_spi_master_handle ) { + return hal_ll_module_id; + } else if ( SPI_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + } + } + } + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static void hal_ll_spi_master_map_pins(uint8_t module_index, hal_ll_spi_pin_id *index_list) { + // if every single pin is OK, insert them into this new map, and use this map in all low level functions. + hal_ll_spi_master_hw_specifics_map[module_index].pins.sck.pin_name = _spi_sck_map[index_list[module_index].pin_sck].pin; + hal_ll_spi_master_hw_specifics_map[module_index].pins.miso.pin_name = _spi_miso_map[index_list[module_index].pin_miso].pin; + hal_ll_spi_master_hw_specifics_map[module_index].pins.mosi.pin_name = _spi_mosi_map[index_list[module_index].pin_mosi].pin; + + // SCK, MISO and MOSI pins could have different alternate function settings, hence save all the AF-s. + hal_ll_spi_master_hw_specifics_map[module_index].pins.sck.pin_af = _spi_sck_map[index_list[module_index].pin_sck].af; + hal_ll_spi_master_hw_specifics_map[module_index].pins.miso.pin_af = _spi_miso_map[index_list[module_index].pin_miso].af; + hal_ll_spi_master_hw_specifics_map[module_index].pins.mosi.pin_af = _spi_mosi_map[index_list[module_index].pin_mosi].af; +} + +static hal_ll_spi_master_hw_specifics_map_t *hal_ll_get_specifics(handle_t handle) { + uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof( hal_ll_spi_master_handle_register_t)); + + static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof( hal_ll_spi_master_handle_register_t)); + + while (hal_ll_module_count--) { + if (hal_ll_spi_master_get_base_from_hal_handle == hal_ll_spi_master_hw_specifics_map[hal_ll_module_count].base) { + return &hal_ll_spi_master_hw_specifics_map[hal_ll_module_count]; + } + } + + // If NOK, return pointer to the last row of this map ( point to null pointer ). + return &hal_ll_spi_master_hw_specifics_map[hal_ll_module_error]; +} + +static void hal_ll_spi_master_set_clock(hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state, uint32_t *clock_value) { + rcc_clocks_t hal_ll_spi_clock_structure; + + RCC_GetClocksFrequency(&hal_ll_spi_clock_structure); + + switch (map->module_index) { + #if defined(SPI_MODULE_1) + case (hal_ll_spi_master_module_num(SPI_MODULE_1)): + if(hal_ll_state) { + set_reg_bit(_RCC_APB2ENR, HAL_LL_SPI1_MASTER_ENABLE); + } else { + clear_reg_bit(_RCC_APB2ENR, HAL_LL_SPI1_MASTER_ENABLE); + } + *clock_value = hal_ll_spi_clock_structure.pclk2; + break; + #endif + #if defined(SPI_MODULE_2) + case (hal_ll_spi_master_module_num(SPI_MODULE_2)): + if(hal_ll_state) { + set_reg_bit(_RCC_APB1ENR1, HAL_LL_SPI2_MASTER_ENABLE); + } else { + clear_reg_bit(_RCC_APB1ENR1, HAL_LL_SPI2_MASTER_ENABLE); + } + *clock_value = hal_ll_spi_clock_structure.pclk1; + break; + #endif + #if defined(SPI_MODULE_3) + case (hal_ll_spi_master_module_num(SPI_MODULE_3)): + if(hal_ll_state) { + set_reg_bit(_RCC_APB1ENR1, HAL_LL_SPI3_MASTER_ENABLE); + } else { + clear_reg_bit(_RCC_APB1ENR1, HAL_LL_SPI3_MASTER_ENABLE); + } + *clock_value = hal_ll_spi_clock_structure.pclk1; + break; + #endif + } +} + +static void hal_ll_spi_master_alternate_functions_set_state(hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state) { + module_struct module; + uint32_t spi_config; + + if((map->pins.sck.pin_name != HAL_LL_PIN_NC) && (map->pins.miso.pin_name != HAL_LL_PIN_NC) && (map->pins.miso.pin_name != HAL_LL_PIN_NC)) { + module.pins[0] = VALUE(map->pins.sck.pin_name, map->pins.sck.pin_af); + module.pins[1] = VALUE(map->pins.miso.pin_name, map->pins.miso.pin_af); + module.pins[2] = VALUE(map->pins.mosi.pin_name, map->pins.mosi.pin_af); + module.pins[3] = GPIO_MODULE_STRUCT_END; + + spi_config = GPIO_CFG_MODE_ALT_FUNCTION | + GPIO_CFG_SPEED_HIGH | + GPIO_CFG_OTYPE_PP; + + module.configs[0] = spi_config; + module.configs[1] = spi_config; + module.configs[2] = spi_config; + module.configs[3] = GPIO_MODULE_STRUCT_END; + + module.gpio_remap = map->pins.sck.pin_af; + + hal_ll_gpio_module_struct_init(&module, hal_ll_state); + } +} + +static uint32_t hal_ll_spi_master_hw_init(hal_ll_spi_master_hw_specifics_map_t *map, uint32_t clock_value) { + uint32_t temp_speed; + + hal_ll_spi_master_base_handle_t *hal_ll_hw_reg = (hal_ll_spi_master_base_handle_t *)map->base; + + // Reset all the settings in control register. + hal_ll_hw_reg->cr1 = 0; + + // Populate appropriate register values to get appropriate data transfer baud rate prescalers. + temp_speed = hal_ll_spi_master_get_speed(clock_value, map->speed); + hal_ll_hw_reg->cr1 |= temp_speed; + + // Choose whether idle state for the clock is high level (1) or low level (0). + if (map->mode <= HAL_LL_SPI_MASTER_MODE_1) { + clear_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_CLK_POLARITY); + } else { + set_reg_bit(&( hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_CLK_POLARITY); + } + + // Choose whether transmit occurs on the transition from ACTIVE to IDLE (1), or vice versa (0). + if (map->mode == HAL_LL_SPI_MASTER_MODE_0 || map->mode == HAL_LL_SPI_MASTER_MODE_2) { + clear_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_CLK_PHASE); + } else { + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_CLK_PHASE); + } + + // Set default values for SPI Master configuration. + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_SSM_ENABLE); + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_SSI_1); + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_SELECTION); + + // Set Slave Select Output Enable bit. + set_reg_bit(&(hal_ll_hw_reg->cr2), HAL_LL_SPI_MASTER_SSOE_BIT); + + // Set FIFO reception threshold to 8-bit. + hal_ll_hw_reg->cr2 |= HAL_LL_SPI_MASTER_FRXTH; + + // Enable SPI peripheral. + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_ENABLE); + + return (hal_ll_spi_master_get_actual_speed(clock_value, temp_speed)); +} + +static void hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_t *map) { + uint32_t clock_value; + + // Enable specific clock module. + hal_ll_spi_master_set_clock (map, true, &clock_value); + + // Enable specific alternate functions. + hal_ll_spi_master_alternate_functions_set_state(map, true); + + // Finally, write user-defined settings into hardware registers. + hal_ll_spi_master_hw_init(map, clock_value); +} +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_161/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_161/CMakeLists.cmake new file mode 100644 index 000000000..1e7def129 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_161/CMakeLists.cmake @@ -0,0 +1,9 @@ +if(${MCU_NAME} MATCHES "^STM32L4Q5AG$|^STM32L4Q5CG$|^STM32L4Q5QG$|^STM32L4Q5RG$|^STM32L4Q5VG$|^STM32L4Q5ZG$") + set(spi_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_spi_master.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_161") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_161") + list(APPEND hal_ll_def_list "STM32L4xx") + list(APPEND hal_ll_def_list "STM32L4Qxx") + list(APPEND hal_ll_def_list "STM32L4Q5xx") + set(spi_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/spi_master/hal_ll_spi_master_pin_map/implementations/doc_ds_161") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_161/hal_ll_spi_master.c b/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_161/hal_ll_spi_master.c new file mode 100644 index 000000000..a96629d82 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_161/hal_ll_spi_master.c @@ -0,0 +1,730 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_spi_master.c + * @brief SPI Master HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_rcc.h" +#include "hal_ll_spi_master.h" +#include "hal_ll_spi_master_pin_map.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_spi_master_handle_register_t hal_ll_module_state[SPI_MODULE_COUNT] = {(handle_t *)NULL, (handle_t *)NULL, false}; + +// ------------------------------------------------------------- PRIVATE MACROS + +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_spi_master_get_module_state_address ((hal_ll_spi_master_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_spi_master_get_handle (hal_ll_spi_master_handle_register_t *)hal_ll_spi_master_get_module_state_address->hal_ll_spi_master_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_spi_master_get_base_struct(_handle) ((hal_ll_spi_master_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_spi_master_get_base_from_hal_handle ((hal_ll_spi_master_hw_specifics_map_t *)((hal_ll_spi_master_handle_register_t *)\ + (((hal_ll_spi_master_handle_register_t *)(handle))->hal_ll_spi_master_handle))->hal_ll_spi_master_handle)->base + +/*!< CR1 constants. */ +#define HAL_LL_SPI_MASTER 0x4 +#define HAL_LL_SPI_MASTER_SSI_1 8 +#define HAL_LL_SPI_MASTER_SELECTION 2 +/*!< CR2 constants. */ +#define HAL_LL_SPI_MASTER_FRXTH 0x1000ul + +#define HAL_LL_SPI_MASTER_SSOE_BIT 2 +#define HAL_LL_SPI_MASTER_SSOE 0x4 +#define HAL_LL_SPI_MASTER_SSM_ENABLE 9 +#define HAL_LL_SPI_MASTER_SSM_DISABLE 0x0000u +#define HAL_LL_SPI_MASTER_SS_ENABLE 0x10000ul +#define HAL_LL_SPI_MASTER_SS_DISABLE 0x00000ul +/*!< SR constants. */ +#define HAL_LL_SPI_MASTER_RXNE 0 +#define HAL_LL_SPI_MASTER_TXE 1 +/*!< I2SCFGR constants. */ +#define HAL_LL_SPI_MASTER_I2SMOD 11 +/*!< Enable constants. */ +#define HAL_LL_SPI_MASTER_ENABLE 6 +#define HAL_LL_SPI1_MASTER_ENABLE 12 + +#define HAL_LL_SPI2_MASTER_ENABLE 14 + +#define HAL_LL_SPI3_MASTER_ENABLE 15 + +/*!< General constants. */ +#define HAL_LL_SPI_MASTER_BAUD_RATE_MASK 3 +#define HAL_LL_SPI_MASTER_16_BIT_REG_SHIFT 16 +#define HAL_LL_SPI_MASTER_DEFAULT_BASE_ADDRESS 0xFF + +#define HAL_LL_SPI_MASTER_CLK_POLARITY 1 +#define HAL_LL_SPI_MASTER_CLK_PHASE 0 + +#define hal_ll_spi_master_get_speed(_fosc,_speed) (_speed >= _fosc/2)? (0):\ + ((_speed <= _fosc/2) && (_speed > _fosc/4))? (0):\ + ((_speed <= _fosc/4) && (_speed > _fosc/8))? (0x0008UL):\ + ((_speed <= _fosc/8) && (_speed > _fosc/16))? (0x0010UL):\ + ((_speed <= _fosc/16) && (_speed > _fosc/32))? (0x0018UL):\ + ((_speed <= _fosc/32) && (_speed > _fosc/64))? (0x0020UL):\ + ((_speed <= _fosc/64) && (_speed > _fosc/128))?(0x0028UL):\ + ((_speed <= _fosc/128)&& (_speed > _fosc/256))?(0x0030UL):(0x0038UL) + +#define hal_ll_spi_master_get_actual_speed(_fosc,_divider) (_divider == 0)?(_fosc/2):\ + (_divider == 0x0008UL)?(_fosc/4):\ + (_divider == 0x0010UL)?(_fosc/8):\ + (_divider == 0x0018UL)?(_fosc/16):\ + (_divider == 0x0020UL)?(_fosc/32):\ + (_divider == 0x0028UL)?(_fosc/64):\ + (_divider == 0x0030UL)?(_fosc/128):\ + (_divider == 0x0038UL)?(_fosc/256):(_fosc/256) + +/*!< @brief Default SPI Master bit-rate if no speed is set */ +#define HAL_LL_SPI_MASTER_SPEED_100K 100000 + +// -------------------------------------------------------------- PRIVATE TYPES + +/*!< @brief SPI register structure. */ +typedef struct { + uint32_t cr1; + uint32_t cr2; + uint32_t sr; + uint32_t dr; + uint32_t crcpr; + uint32_t rxcrcr; + uint32_t txcrcr; + +} hal_ll_spi_master_base_handle_t; + +/*!< @brief SPI Master hardware specific structure */ +typedef struct { + hal_ll_base_addr_t base; + uint8_t module_index; + hal_ll_spi_master_pins_t pins; + uint8_t dummy_data; + uint32_t speed; + uint32_t hw_actual_speed; + hal_ll_spi_master_mode_t mode; +} hal_ll_spi_master_hw_specifics_map_t; + +/*!< @brief SPI hw specific module values */ +typedef struct +{ + uint16_t pin_sck; + uint16_t pin_miso; + uint16_t pin_mosi; +} hal_ll_spi_pin_id; + +/*!< @brief SPI Master hw specific error values */ +typedef enum { + HAL_LL_SPI_MASTER_SUCCESS = 0, + HAL_LL_SPI_MASTER_WRONG_PINS, + HAL_LL_SPI_MASTER_MODULE_ERROR, + + HAL_LL_SPI_MASTER_ERROR = (-1) +} hal_ll_spi_master_err_t; + +// ------------------------------------------------------------------ VARIABLES + +/*!< @brief SPI Master hardware specific info */ +static hal_ll_spi_master_hw_specifics_map_t hal_ll_spi_master_hw_specifics_map[] = { + #ifdef SPI_MODULE_1 + {HAL_LL_SPI1_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_1), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, HAL_LL_SPI_MASTER_SPEED_100K, 0, HAL_LL_SPI_MASTER_MODE_DEFAULT}, + #endif + + #ifdef SPI_MODULE_2 + {HAL_LL_SPI2_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_2), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, HAL_LL_SPI_MASTER_SPEED_100K, 0, HAL_LL_SPI_MASTER_MODE_DEFAULT}, + #endif + + #ifdef SPI_MODULE_3 + {HAL_LL_SPI3_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_3), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, HAL_LL_SPI_MASTER_SPEED_100K, 0, HAL_LL_SPI_MASTER_MODE_DEFAULT}, + #endif + + + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, 0, 0, 0} +}; + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_spi_master_handle_register_t *low_level_handle; +static volatile hal_ll_spi_master_hw_specifics_map_t *hal_ll_spi_master_hw_specifics_map_local; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Check if pins are adequate. + * + * Checks SCK, MISO and MOSI pins the user has passed with pre-defined + * pins in SCK, MISO and MOSI maps. Take into consideration that module + * index numbers have to be the same for both pins. + * + * @param[in] sck - SCK pre-defined pin name. + * @param[in] miso - MISO pre-defined pin name. + * @param[in] mosi - MOSI pre-defined pin name. + * @param[in] *index_list - Index list address + * @return hal_ll_pin_name_t Module index based on pins. + * + * Returns pre-defined module index from pin maps, if pins + * are adequate. + */ +static hal_ll_pin_name_t hal_ll_spi_master_check_pins(hal_ll_pin_name_t sck, hal_ll_pin_name_t miso, hal_ll_pin_name_t mosi, hal_ll_spi_pin_id *index_list, hal_ll_spi_master_handle_register_t *handle_map ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_spi_master_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_spi_master_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_spi_master_hw_specifics_map_t *hal_ll_get_specifics(handle_t handle); + +/** + * @brief Enable clock for SPI Master module on hardware level. + * + * Initializes SPI Master module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] *map - Object specific context handler. + * @param[in] hal_ll_state - True(enable clock)/False(disable clock). + * @param[in] *clock_value - SPI Master baud rate value taken from a specific peripheral clock bus. + * @return None + */ +static void hal_ll_spi_master_set_clock(hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state, uint32_t *clock_value); + +/** + * @brief Sets SPI Master pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if SPI is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param[in] *map - Object specific context handler. + * @param[in] hal_ll_state - Init/De-init + */ +static void hal_ll_spi_master_alternate_functions_set_state(hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state); + +/** + * @brief Full SPI Master module initialization procedure. + * + * Initializes SPI Master module on hardware level, based on beforehand + * set configuration and module handler. Sets adequate pin alternate functions. + * Initializes module clock. + * + * @param[in] *map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static void hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_t *map); + +/** + * @brief Perform a read on the SPI Master bus. + * + * Initializes SPI Master module on hardware level, if not initialized beforehand + * and continues to perform a read operation on the bus. + * + * @param[in] *map - Object specific context handler. + * @param[in] *read_data_buffer - Pointer to data buffer. + * @param[in] read_data_length - Number of data to be read. + * @param[in] dummy_data - Data required for read procedure. + * @return hal_ll_err_t Module specific error values. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +static void hal_ll_spi_master_read_bare_metal(hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *read_data_buffer, size_t read_data_length, uint8_t dummy_data); + +/** + * @brief Perform a write on the SPI Master bus. + * + * Initializes SPI Master module on hardware level, if not initialized beforehand + * and continues to perform a write operation on the bus. + * + * @param[in] map - Object specific context handler. + * @param[in] *write_data_buffer - Pointer to data buffer. + * @param[in] write_data_length - Number of data to be written. + * @return hal_ll_err_t Module specific error values. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +static void hal_ll_spi_master_write_bare_metal(hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *write_data_buffer, size_t write_data_length); + +/** + * @brief Perform a write then read on the SPI Master bus. + * + * Initializes SPI Master module on hardware level, if not initialized beforehand + * and continues to perform a write operation on the bus. + * + * @param[in] *handle - Object specific context handler. + * @param[in] *write_data_buffer - Pointer to data buffer. + * @param[in] length_write_data - Number of data to be written. + * @param[in] *read_data_buffer - Pointer to data buffer. + * @param[in] length_read_data - Number of data to be read. + * @return hal_ll_err_t Module specific error values. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_spi_master_write_then_read(handle_t *handle, uint8_t *write_data_buffer, size_t length_write_data, uint8_t *read_data_buffer, size_t length_read_data); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * SPI SCK, MISO and MOSI pins. + * + * @param[in] module_index SPI HW module index -- 0,1,2... + * @param[in] *index_list Array with SCK, MISO and MOSI map index values + * and module number + * + * @return None + */ +static void hal_ll_spi_master_map_pins(uint8_t module_index, hal_ll_spi_pin_id *index_list); + + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS + +hal_ll_err_t hal_ll_spi_master_register_handle(hal_ll_pin_name_t sck, hal_ll_pin_name_t miso, hal_ll_pin_name_t mosi, hal_ll_spi_master_handle_register_t *handle_map, uint8_t *hal_module_id) { + + hal_ll_spi_pin_id index_list[SPI_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + uint16_t pin_check_result; + + // Check user-defined pins. + if ((pin_check_result = hal_ll_spi_master_check_pins(sck, miso, mosi, &index_list, handle_map)) == HAL_LL_PIN_NC) { + return HAL_LL_SPI_MASTER_WRONG_PINS; + }; + + // If user has come with the same SPI hardware module, and with the same pair of the pins, the pin mapping procedure + // will not have to take a place; otherwise, clear af-s, map new pins, set af-s, and set init state to false. + if ((hal_ll_spi_master_hw_specifics_map[pin_check_result].pins.sck.pin_name != sck) || + (hal_ll_spi_master_hw_specifics_map[pin_check_result].pins.miso.pin_name != miso) || + (hal_ll_spi_master_hw_specifics_map[pin_check_result].pins.mosi.pin_name != mosi) ) { + + hal_ll_spi_master_alternate_functions_set_state(&hal_ll_spi_master_hw_specifics_map[pin_check_result], false); + + hal_ll_spi_master_map_pins(pin_check_result, &index_list); + + hal_ll_spi_master_alternate_functions_set_state(&hal_ll_spi_master_hw_specifics_map[pin_check_result], true); + + handle_map[pin_check_result].init_ll_state = false; + } + + // Return id of the SPI module that is going to be used. + *hal_module_id = pin_check_result; + + // Insert current module into hal_ll_module_state map. + hal_ll_module_state[pin_check_result].hal_ll_spi_master_handle = (handle_t *)&hal_ll_spi_master_hw_specifics_map[pin_check_result].base; + + // Return the same info about module one level up ( into the HAL level ). + handle_map[pin_check_result].hal_ll_spi_master_handle = (handle_t*)&hal_ll_module_state[pin_check_result].hal_ll_spi_master_handle; + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_spi(handle_t *handle) { + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + hal_ll_spi_master_handle_register_t *hal_handle = (hal_ll_spi_master_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_spi_master_hw_specifics_map_local->module_index; + + hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_local); + + hal_ll_module_state[pin_check_result].hal_ll_spi_master_handle = (handle_t *)&hal_ll_spi_master_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +void hal_ll_spi_master_set_default_write_data(handle_t *handle, uint8_t dummy_data) { + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + if(hal_ll_spi_master_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR) { + hal_ll_spi_master_hw_specifics_map_local->dummy_data = dummy_data; + } +} + +hal_ll_err_t hal_ll_spi_master_write(handle_t *handle, uint8_t *write_data_buffer, size_t length_data) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + hal_ll_spi_master_write_bare_metal(hal_ll_spi_master_hw_specifics_map_local->base, write_data_buffer, length_data); + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_spi_master_read(handle_t *handle, uint8_t *read_data_buffer, size_t length_data) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + hal_ll_spi_master_read_bare_metal(hal_ll_spi_master_hw_specifics_map_local->base, read_data_buffer, length_data, hal_ll_spi_master_hw_specifics_map_local->dummy_data); + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_spi_master_write_then_read(handle_t *handle, uint8_t *write_data_buffer, size_t length_write_data, uint8_t *read_data_buffer, size_t length_read_data) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + hal_ll_spi_master_write_bare_metal(hal_ll_spi_master_hw_specifics_map_local->base, write_data_buffer, length_write_data); + + hal_ll_spi_master_read_bare_metal(hal_ll_spi_master_hw_specifics_map_local->base, read_data_buffer, length_read_data, hal_ll_spi_master_hw_specifics_map_local->dummy_data); + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +uint32_t hal_ll_spi_master_set_speed(handle_t *handle, uint32_t speed) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + low_level_handle->init_ll_state = false; + + // Insert user-defined baud rate into local map. + hal_ll_spi_master_hw_specifics_map_local->speed = speed; + + // Init once again, but with updated SPI Master baud rate value. + hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + // Return value of the SPI Master baud rate value. + return hal_ll_spi_master_hw_specifics_map_local->hw_actual_speed; +} + +hal_ll_err_t hal_ll_spi_master_set_mode(handle_t *handle, hal_ll_spi_master_mode_t mode) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + low_level_handle->init_ll_state = false; + + // Insert user-defined mode into local map. + hal_ll_spi_master_hw_specifics_map_local->mode = mode; + + // Init once again, but with updated SPI Master mode value. + hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +void hal_ll_spi_master_close(handle_t* handle) { + uint32_t dummy; + low_level_handle = hal_ll_spi_master_get_handle; + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + if(low_level_handle->hal_ll_spi_master_handle != NULL) { + low_level_handle->hal_ll_spi_master_handle = NULL; + low_level_handle->hal_drv_spi_master_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_spi_master_hw_specifics_map_local->mode = HAL_LL_SPI_MASTER_MODE_DEFAULT; + hal_ll_spi_master_hw_specifics_map_local->speed = HAL_LL_SPI_MASTER_SPEED_100K; + hal_ll_spi_master_hw_specifics_map_local->dummy_data = 0; + hal_ll_spi_master_hw_specifics_map_local->hw_actual_speed = 0; + + hal_ll_spi_master_set_clock(hal_ll_spi_master_hw_specifics_map_local, true, &dummy); + hal_ll_spi_master_alternate_functions_set_state(hal_ll_spi_master_hw_specifics_map_local, false); + hal_ll_spi_master_set_clock(hal_ll_spi_master_hw_specifics_map_local, false, &dummy); + + hal_ll_spi_master_hw_specifics_map_local->pins.sck.pin_name = HAL_LL_PIN_NC; + hal_ll_spi_master_hw_specifics_map_local->pins.miso.pin_name = HAL_LL_PIN_NC; + hal_ll_spi_master_hw_specifics_map_local->pins.mosi.pin_name = HAL_LL_PIN_NC; + hal_ll_spi_master_hw_specifics_map_local->pins.sck.pin_af = 0; + hal_ll_spi_master_hw_specifics_map_local->pins.miso.pin_af = 0; + hal_ll_spi_master_hw_specifics_map_local->pins.mosi.pin_af = 0; + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS + +uint8_t hal_ll_spi_master_transfer_bare_metal(hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t data_buffer) { + // Write user-defined data ( 'hal_ll_spi_master_read_bare_metal' procedure will send dummy data ). + *((volatile uint8_t *)&hal_ll_hw_reg->dr) = (uint8_t)data_buffer; // 8-bit data + + // Wait for receive buffer not empty status. + while (!(check_reg_bit( &(hal_ll_hw_reg->sr), HAL_LL_SPI_MASTER_RXNE))); + + // Return read data. + return *((volatile uint8_t *)&hal_ll_hw_reg->dr); // 8-bit data +} + +static void hal_ll_spi_master_write_bare_metal( hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *write_data_buffer, size_t write_data_length ) { + uint16_t transfer_counter = NULL; + + // Write the first data to be transmitted into the SPI_DR register. + for(transfer_counter = 0; transfer_counter < write_data_length; transfer_counter++) { + // If we are good to go ( if the tx buffer value has been shifted to the shift register ), write the data. + hal_ll_spi_master_transfer_bare_metal( hal_ll_hw_reg, write_data_buffer[transfer_counter]); + } +} + +static void hal_ll_spi_master_read_bare_metal(hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *read_data_buffer, size_t read_data_length, uint8_t dummy_data) { + uint16_t transfer_counter = NULL; + + // Read the first data to be transmitted into the SPI_DR register. + for(transfer_counter = 0; transfer_counter < read_data_length; transfer_counter++) { + // If we are good to go ( if the value from shift register has been shifted to the rx register ), read the data. + read_data_buffer[transfer_counter] = hal_ll_spi_master_transfer_bare_metal(hal_ll_hw_reg, dummy_data); + } +} + +static hal_ll_pin_name_t hal_ll_spi_master_check_pins(hal_ll_pin_name_t sck_pin, hal_ll_pin_name_t miso_pin, hal_ll_pin_name_t mosi_pin, hal_ll_spi_pin_id *index_list, hal_ll_spi_master_handle_register_t *handle_map) { + static const uint16_t sck_map_size = (sizeof(_spi_sck_map)) / (sizeof(hal_ll_spi_master_pin_map_t)); + static const uint16_t miso_map_size = (sizeof(_spi_miso_map)) / (sizeof(hal_ll_spi_master_pin_map_t)); + static const uint16_t mosi_map_size = (sizeof(_spi_mosi_map)) / (sizeof(hal_ll_spi_master_pin_map_t)); + uint8_t hal_ll_module_id = 0; + uint8_t index_counter = 0; + uint16_t miso_index; + uint16_t mosi_index; + uint16_t sck_index; + + if ( (HAL_LL_PIN_NC == sck_pin) || (HAL_LL_PIN_NC == miso_pin) || (HAL_LL_PIN_NC == mosi_pin) ) { + return HAL_LL_PIN_NC; + } + + // Check pins from the specific pin maps with the user defined pins. + for (sck_index = 0; sck_index < sck_map_size; sck_index++) { + if (_spi_sck_map[sck_index].pin == sck_pin) { + for (miso_index = 0; miso_index < miso_map_size; miso_index++) { + if (_spi_miso_map[miso_index].pin == miso_pin) { + if (_spi_sck_map[sck_index].module_index ==_spi_miso_map[miso_index].module_index) { + for (mosi_index = 0; mosi_index < mosi_map_size; mosi_index++) { + if (_spi_mosi_map[mosi_index ].pin == mosi_pin) { + if (_spi_sck_map[sck_index].module_index ==_spi_mosi_map[mosi_index].module_index) { + // Get module number + hal_ll_module_id = _spi_sck_map[ sck_index ].module_index; + + // Map pin names + index_list[hal_ll_module_id].pin_sck = sck_index; + index_list[hal_ll_module_id].pin_miso = miso_index; + index_list[hal_ll_module_id].pin_mosi = mosi_index; + + // Check if module is taken + if ( NULL == handle_map[hal_ll_module_id].hal_drv_spi_master_handle ) { + return hal_ll_module_id; + } else if ( SPI_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + } + } + } + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static void hal_ll_spi_master_map_pins(uint8_t module_index, hal_ll_spi_pin_id *index_list) { + // if every single pin is OK, insert them into this new map, and use this map in all low level functions. + hal_ll_spi_master_hw_specifics_map[module_index].pins.sck.pin_name = _spi_sck_map[index_list[module_index].pin_sck].pin; + hal_ll_spi_master_hw_specifics_map[module_index].pins.miso.pin_name = _spi_miso_map[index_list[module_index].pin_miso].pin; + hal_ll_spi_master_hw_specifics_map[module_index].pins.mosi.pin_name = _spi_mosi_map[index_list[module_index].pin_mosi].pin; + + // SCK, MISO and MOSI pins could have different alternate function settings, hence save all the AF-s. + hal_ll_spi_master_hw_specifics_map[module_index].pins.sck.pin_af = _spi_sck_map[index_list[module_index].pin_sck].af; + hal_ll_spi_master_hw_specifics_map[module_index].pins.miso.pin_af = _spi_miso_map[index_list[module_index].pin_miso].af; + hal_ll_spi_master_hw_specifics_map[module_index].pins.mosi.pin_af = _spi_mosi_map[index_list[module_index].pin_mosi].af; +} + +static hal_ll_spi_master_hw_specifics_map_t *hal_ll_get_specifics(handle_t handle) { + uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof( hal_ll_spi_master_handle_register_t)); + + static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof( hal_ll_spi_master_handle_register_t)); + + while (hal_ll_module_count--) { + if (hal_ll_spi_master_get_base_from_hal_handle == hal_ll_spi_master_hw_specifics_map[hal_ll_module_count].base) { + return &hal_ll_spi_master_hw_specifics_map[hal_ll_module_count]; + } + } + + // If NOK, return pointer to the last row of this map ( point to null pointer ). + return &hal_ll_spi_master_hw_specifics_map[hal_ll_module_error]; +} + +static void hal_ll_spi_master_set_clock(hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state, uint32_t *clock_value) { + rcc_clocks_t hal_ll_spi_clock_structure; + + RCC_GetClocksFrequency(&hal_ll_spi_clock_structure); + + switch (map->module_index) { + #if defined(SPI_MODULE_1) + case (hal_ll_spi_master_module_num(SPI_MODULE_1)): + if(hal_ll_state) { + set_reg_bit(_RCC_APB2ENR, HAL_LL_SPI1_MASTER_ENABLE); + } else { + clear_reg_bit(_RCC_APB2ENR, HAL_LL_SPI1_MASTER_ENABLE); + } + *clock_value = hal_ll_spi_clock_structure.pclk2; + break; + #endif + + #if defined(SPI_MODULE_2) + case (hal_ll_spi_master_module_num(SPI_MODULE_2)): + if(hal_ll_state) { + set_reg_bit(_RCC_APB1ENR1, HAL_LL_SPI2_MASTER_ENABLE); + } else { + clear_reg_bit(_RCC_APB1ENR1, HAL_LL_SPI2_MASTER_ENABLE); + } + *clock_value = hal_ll_spi_clock_structure.pclk1; + break; + #endif + + #if defined(SPI_MODULE_3) + case (hal_ll_spi_master_module_num(SPI_MODULE_3)): + if(hal_ll_state) { + set_reg_bit(_RCC_APB1ENR1, HAL_LL_SPI3_MASTER_ENABLE); + } else { + clear_reg_bit(_RCC_APB1ENR1, HAL_LL_SPI3_MASTER_ENABLE); + } + *clock_value = hal_ll_spi_clock_structure.pclk1; + break; + #endif + + + } +} + +static void hal_ll_spi_master_alternate_functions_set_state(hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state) { + module_struct module; + uint32_t spi_config; + + if((map->pins.sck.pin_name != HAL_LL_PIN_NC) && (map->pins.miso.pin_name != HAL_LL_PIN_NC) && (map->pins.miso.pin_name != HAL_LL_PIN_NC)) { + module.pins[0] = VALUE(map->pins.sck.pin_name, map->pins.sck.pin_af); + module.pins[1] = VALUE(map->pins.miso.pin_name, map->pins.miso.pin_af); + module.pins[2] = VALUE(map->pins.mosi.pin_name, map->pins.mosi.pin_af); + module.pins[3] = GPIO_MODULE_STRUCT_END; + + spi_config = GPIO_CFG_MODE_ALT_FUNCTION | + GPIO_CFG_SPEED_HIGH | + GPIO_CFG_OTYPE_PP; + + module.configs[0] = spi_config; + module.configs[1] = spi_config; + module.configs[2] = spi_config; + module.configs[3] = GPIO_MODULE_STRUCT_END; + + module.gpio_remap = map->pins.sck.pin_af; + + hal_ll_gpio_module_struct_init(&module, hal_ll_state); + } +} + +static uint32_t hal_ll_spi_master_hw_init(hal_ll_spi_master_hw_specifics_map_t *map, uint32_t clock_value) { + uint32_t temp_speed; + + hal_ll_spi_master_base_handle_t *hal_ll_hw_reg = (hal_ll_spi_master_base_handle_t *)map->base; + + // Reset all the settings in control register. + hal_ll_hw_reg->cr1 = 0; + + // Populate appropriate register values to get appropriate data transfer baud rate prescalers. + temp_speed = hal_ll_spi_master_get_speed(clock_value, map->speed); + hal_ll_hw_reg->cr1 |= temp_speed; + + // Choose whether idle state for the clock is high level (1) or low level (0). + if (map->mode <= HAL_LL_SPI_MASTER_MODE_1) { + clear_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_CLK_POLARITY); + } else { + set_reg_bit(&( hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_CLK_POLARITY); + } + + // Choose whether transmit occurs on the transition from ACTIVE to IDLE (1), or vice versa (0). + if (map->mode == HAL_LL_SPI_MASTER_MODE_0 || map->mode == HAL_LL_SPI_MASTER_MODE_2) { + clear_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_CLK_PHASE); + } else { + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_CLK_PHASE); + } + + // Set default values for SPI Master configuration. + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_SSM_ENABLE); + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_SSI_1); + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_SELECTION); + + // Set Slave Select Output Enable bit. + set_reg_bit(&(hal_ll_hw_reg->cr2), HAL_LL_SPI_MASTER_SSOE_BIT); + + // Set FIFO reception threshold to 8-bit. + hal_ll_hw_reg->cr2 |= HAL_LL_SPI_MASTER_FRXTH; + + // Enable SPI peripheral. + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_ENABLE); + + return (hal_ll_spi_master_get_actual_speed(clock_value, temp_speed)); +} + +static void hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_t *map) { + uint32_t clock_value; + + // Enable specific clock module. + hal_ll_spi_master_set_clock (map, true, &clock_value); + + // Enable specific alternate functions. + hal_ll_spi_master_alternate_functions_set_state(map, true); + + // Finally, write user-defined settings into hardware registers. + hal_ll_spi_master_hw_init(map, clock_value); +} +// ------------------------------------------------------------------------- END + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_2/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_2/CMakeLists.cmake new file mode 100644 index 000000000..b93e9f2ce --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_2/CMakeLists.cmake @@ -0,0 +1,9 @@ +if(${MCU_NAME} MATCHES "^STM32C031C4$|^STM32C031F4$|^STM32C031G4$|^STM32C031K4$|^STM32C031C6$|^STM32C031F6$|^STM32C031G6$|^STM32C031K6$") + set(spi_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_spi_master.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_2") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_2") + list(APPEND hal_ll_def_list "STM32C0xx") + list(APPEND hal_ll_def_list "STM32C03xx") + list(APPEND hal_ll_def_list "STM32C031xx") + set(spi_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/spi_master/hal_ll_spi_master_pin_map/implementations/doc_ds_2") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_2/hal_ll_spi_master.c b/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_2/hal_ll_spi_master.c new file mode 100644 index 000000000..481e0d494 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_2/hal_ll_spi_master.c @@ -0,0 +1,698 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_spi_master.c + * @brief SPI Master HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_rcc.h" +#include "hal_ll_spi_master.h" +#include "hal_ll_spi_master_pin_map.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_spi_master_handle_register_t hal_ll_module_state[SPI_MODULE_COUNT] = {(handle_t *)NULL, (handle_t *)NULL, false}; + +// ------------------------------------------------------------- PRIVATE MACROS + +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_spi_master_get_module_state_address ((hal_ll_spi_master_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_spi_master_get_handle (hal_ll_spi_master_handle_register_t *)hal_ll_spi_master_get_module_state_address->hal_ll_spi_master_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_spi_master_get_base_struct(_handle) ((hal_ll_spi_master_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_spi_master_get_base_from_hal_handle ((hal_ll_spi_master_hw_specifics_map_t *)((hal_ll_spi_master_handle_register_t *)\ + (((hal_ll_spi_master_handle_register_t *)(handle))->hal_ll_spi_master_handle))->hal_ll_spi_master_handle)->base + +/*!< CR1 constants. */ +#define HAL_LL_SPI_MASTER 0x4 +#define HAL_LL_SPI_MASTER_SSI_1 8 +#define HAL_LL_SPI_MASTER_SELECTION 2 +/*!< CR2 constants. */ +#define HAL_LL_SPI_MASTER_FRXTH 0x1000ul + +#define HAL_LL_SPI_MASTER_SSOE_BIT 2 +#define HAL_LL_SPI_MASTER_SSOE 0x4 +#define HAL_LL_SPI_MASTER_SSM_ENABLE 9 +#define HAL_LL_SPI_MASTER_SSM_DISABLE 0x0000u +#define HAL_LL_SPI_MASTER_SS_ENABLE 0x10000ul +#define HAL_LL_SPI_MASTER_SS_DISABLE 0x00000ul +/*!< SR constants. */ +#define HAL_LL_SPI_MASTER_RXNE 0 +#define HAL_LL_SPI_MASTER_TXE 1 +/*!< I2SCFGR constants. */ +#define HAL_LL_SPI_MASTER_I2SMOD 11 +/*!< Enable constants. */ +#define HAL_LL_SPI_MASTER_ENABLE 6 +#define HAL_LL_SPI1_MASTER_ENABLE 12 + +/*!< General constants. */ +#define HAL_LL_SPI_MASTER_BAUD_RATE_MASK 3 +#define HAL_LL_SPI_MASTER_16_BIT_REG_SHIFT 16 +#define HAL_LL_SPI_MASTER_DEFAULT_BASE_ADDRESS 0xFF + +#define HAL_LL_SPI_MASTER_CLK_POLARITY 1 +#define HAL_LL_SPI_MASTER_CLK_PHASE 0 + +#define hal_ll_spi_master_get_speed(_fosc,_speed) (_speed >= _fosc/2)? (0):\ + ((_speed <= _fosc/2) && (_speed > _fosc/4))? (0):\ + ((_speed <= _fosc/4) && (_speed > _fosc/8))? (0x0008UL):\ + ((_speed <= _fosc/8) && (_speed > _fosc/16))? (0x0010UL):\ + ((_speed <= _fosc/16) && (_speed > _fosc/32))? (0x0018UL):\ + ((_speed <= _fosc/32) && (_speed > _fosc/64))? (0x0020UL):\ + ((_speed <= _fosc/64) && (_speed > _fosc/128))?(0x0028UL):\ + ((_speed <= _fosc/128)&& (_speed > _fosc/256))?(0x0030UL):(0x0038UL) + +#define hal_ll_spi_master_get_actual_speed(_fosc,_divider) (_divider == 0)?(_fosc/2):\ + (_divider == 0x0008UL)?(_fosc/4):\ + (_divider == 0x0010UL)?(_fosc/8):\ + (_divider == 0x0018UL)?(_fosc/16):\ + (_divider == 0x0020UL)?(_fosc/32):\ + (_divider == 0x0028UL)?(_fosc/64):\ + (_divider == 0x0030UL)?(_fosc/128):\ + (_divider == 0x0038UL)?(_fosc/256):(_fosc/256) + +/*!< @brief Default SPI Master bit-rate if no speed is set */ +#define HAL_LL_SPI_MASTER_SPEED_100K 100000 + +// -------------------------------------------------------------- PRIVATE TYPES + +/*!< @brief SPI register structure. */ +typedef struct { + uint32_t cr1; + uint32_t cr2; + uint32_t sr; + uint32_t dr; + uint32_t crcpr; + uint32_t rxcrcr; + uint32_t txcrcr; + uint32_t i2scfgr0; + uint32_t i2spr; + +} hal_ll_spi_master_base_handle_t; + +/*!< @brief SPI Master hardware specific structure */ +typedef struct { + hal_ll_base_addr_t base; + uint8_t module_index; + hal_ll_spi_master_pins_t pins; + uint8_t dummy_data; + uint32_t speed; + uint32_t hw_actual_speed; + hal_ll_spi_master_mode_t mode; +} hal_ll_spi_master_hw_specifics_map_t; + +/*!< @brief SPI hw specific module values */ +typedef struct +{ + uint16_t pin_sck; + uint16_t pin_miso; + uint16_t pin_mosi; +} hal_ll_spi_pin_id; + +/*!< @brief SPI Master hw specific error values */ +typedef enum { + HAL_LL_SPI_MASTER_SUCCESS = 0, + HAL_LL_SPI_MASTER_WRONG_PINS, + HAL_LL_SPI_MASTER_MODULE_ERROR, + + HAL_LL_SPI_MASTER_ERROR = (-1) +} hal_ll_spi_master_err_t; + +// ------------------------------------------------------------------ VARIABLES + +/*!< @brief SPI Master hardware specific info */ +static hal_ll_spi_master_hw_specifics_map_t hal_ll_spi_master_hw_specifics_map[] = { + #ifdef SPI_MODULE_1 + {HAL_LL_SPI1_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_1), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, HAL_LL_SPI_MASTER_SPEED_100K, 0, HAL_LL_SPI_MASTER_MODE_DEFAULT}, + #endif + + + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, 0, 0, 0} +}; + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_spi_master_handle_register_t *low_level_handle; +static volatile hal_ll_spi_master_hw_specifics_map_t *hal_ll_spi_master_hw_specifics_map_local; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Check if pins are adequate. + * + * Checks SCK, MISO and MOSI pins the user has passed with pre-defined + * pins in SCK, MISO and MOSI maps. Take into consideration that module + * index numbers have to be the same for both pins. + * + * @param[in] sck - SCK pre-defined pin name. + * @param[in] miso - MISO pre-defined pin name. + * @param[in] mosi - MOSI pre-defined pin name. + * @param[in] *index_list - Index list address + * @return hal_ll_pin_name_t Module index based on pins. + * + * Returns pre-defined module index from pin maps, if pins + * are adequate. + */ +static hal_ll_pin_name_t hal_ll_spi_master_check_pins(hal_ll_pin_name_t sck, hal_ll_pin_name_t miso, hal_ll_pin_name_t mosi, hal_ll_spi_pin_id *index_list, hal_ll_spi_master_handle_register_t *handle_map ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_spi_master_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_spi_master_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_spi_master_hw_specifics_map_t *hal_ll_get_specifics(handle_t handle); + +/** + * @brief Enable clock for SPI Master module on hardware level. + * + * Initializes SPI Master module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] *map - Object specific context handler. + * @param[in] hal_ll_state - True(enable clock)/False(disable clock). + * @param[in] *clock_value - SPI Master baud rate value taken from a specific peripheral clock bus. + * @return None + */ +static void hal_ll_spi_master_set_clock(hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state, uint32_t *clock_value); + +/** + * @brief Sets SPI Master pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if SPI is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param[in] *map - Object specific context handler. + * @param[in] hal_ll_state - Init/De-init + */ +static void hal_ll_spi_master_alternate_functions_set_state(hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state); + +/** + * @brief Full SPI Master module initialization procedure. + * + * Initializes SPI Master module on hardware level, based on beforehand + * set configuration and module handler. Sets adequate pin alternate functions. + * Initializes module clock. + * + * @param[in] *map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static void hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_t *map); + +/** + * @brief Perform a read on the SPI Master bus. + * + * Initializes SPI Master module on hardware level, if not initialized beforehand + * and continues to perform a read operation on the bus. + * + * @param[in] *map - Object specific context handler. + * @param[in] *read_data_buffer - Pointer to data buffer. + * @param[in] read_data_length - Number of data to be read. + * @param[in] dummy_data - Data required for read procedure. + * @return hal_ll_err_t Module specific error values. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +static void hal_ll_spi_master_read_bare_metal(hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *read_data_buffer, size_t read_data_length, uint8_t dummy_data); + +/** + * @brief Perform a write on the SPI Master bus. + * + * Initializes SPI Master module on hardware level, if not initialized beforehand + * and continues to perform a write operation on the bus. + * + * @param[in] map - Object specific context handler. + * @param[in] *write_data_buffer - Pointer to data buffer. + * @param[in] write_data_length - Number of data to be written. + * @return hal_ll_err_t Module specific error values. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +static void hal_ll_spi_master_write_bare_metal(hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *write_data_buffer, size_t write_data_length); + +/** + * @brief Perform a write then read on the SPI Master bus. + * + * Initializes SPI Master module on hardware level, if not initialized beforehand + * and continues to perform a write operation on the bus. + * + * @param[in] *handle - Object specific context handler. + * @param[in] *write_data_buffer - Pointer to data buffer. + * @param[in] length_write_data - Number of data to be written. + * @param[in] *read_data_buffer - Pointer to data buffer. + * @param[in] length_read_data - Number of data to be read. + * @return hal_ll_err_t Module specific error values. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_spi_master_write_then_read(handle_t *handle, uint8_t *write_data_buffer, size_t length_write_data, uint8_t *read_data_buffer, size_t length_read_data); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * SPI SCK, MISO and MOSI pins. + * + * @param[in] module_index SPI HW module index -- 0,1,2... + * @param[in] *index_list Array with SCK, MISO and MOSI map index values + * and module number + * + * @return None + */ +static void hal_ll_spi_master_map_pins(uint8_t module_index, hal_ll_spi_pin_id *index_list); + + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS + +hal_ll_err_t hal_ll_spi_master_register_handle(hal_ll_pin_name_t sck, hal_ll_pin_name_t miso, hal_ll_pin_name_t mosi, hal_ll_spi_master_handle_register_t *handle_map, uint8_t *hal_module_id) { + + hal_ll_spi_pin_id index_list[SPI_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + uint16_t pin_check_result; + + // Check user-defined pins. + if ((pin_check_result = hal_ll_spi_master_check_pins(sck, miso, mosi, &index_list, handle_map)) == HAL_LL_PIN_NC) { + return HAL_LL_SPI_MASTER_WRONG_PINS; + }; + + // If user has come with the same SPI hardware module, and with the same pair of the pins, the pin mapping procedure + // will not have to take a place; otherwise, clear af-s, map new pins, set af-s, and set init state to false. + if ((hal_ll_spi_master_hw_specifics_map[pin_check_result].pins.sck.pin_name != sck) || + (hal_ll_spi_master_hw_specifics_map[pin_check_result].pins.miso.pin_name != miso) || + (hal_ll_spi_master_hw_specifics_map[pin_check_result].pins.mosi.pin_name != mosi) ) { + + hal_ll_spi_master_alternate_functions_set_state(&hal_ll_spi_master_hw_specifics_map[pin_check_result], false); + + hal_ll_spi_master_map_pins(pin_check_result, &index_list); + + hal_ll_spi_master_alternate_functions_set_state(&hal_ll_spi_master_hw_specifics_map[pin_check_result], true); + + handle_map[pin_check_result].init_ll_state = false; + } + + // Return id of the SPI module that is going to be used. + *hal_module_id = pin_check_result; + + // Insert current module into hal_ll_module_state map. + hal_ll_module_state[pin_check_result].hal_ll_spi_master_handle = (handle_t *)&hal_ll_spi_master_hw_specifics_map[pin_check_result].base; + + // Return the same info about module one level up ( into the HAL level ). + handle_map[pin_check_result].hal_ll_spi_master_handle = (handle_t*)&hal_ll_module_state[pin_check_result].hal_ll_spi_master_handle; + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_spi(handle_t *handle) { + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + hal_ll_spi_master_handle_register_t *hal_handle = (hal_ll_spi_master_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_spi_master_hw_specifics_map_local->module_index; + + hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_local); + + hal_ll_module_state[pin_check_result].hal_ll_spi_master_handle = (handle_t *)&hal_ll_spi_master_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +void hal_ll_spi_master_set_default_write_data(handle_t *handle, uint8_t dummy_data) { + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + if(hal_ll_spi_master_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR) { + hal_ll_spi_master_hw_specifics_map_local->dummy_data = dummy_data; + } +} + +hal_ll_err_t hal_ll_spi_master_write(handle_t *handle, uint8_t *write_data_buffer, size_t length_data) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + hal_ll_spi_master_write_bare_metal(hal_ll_spi_master_hw_specifics_map_local->base, write_data_buffer, length_data); + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_spi_master_read(handle_t *handle, uint8_t *read_data_buffer, size_t length_data) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + hal_ll_spi_master_read_bare_metal(hal_ll_spi_master_hw_specifics_map_local->base, read_data_buffer, length_data, hal_ll_spi_master_hw_specifics_map_local->dummy_data); + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_spi_master_write_then_read(handle_t *handle, uint8_t *write_data_buffer, size_t length_write_data, uint8_t *read_data_buffer, size_t length_read_data) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + hal_ll_spi_master_write_bare_metal(hal_ll_spi_master_hw_specifics_map_local->base, write_data_buffer, length_write_data); + + hal_ll_spi_master_read_bare_metal(hal_ll_spi_master_hw_specifics_map_local->base, read_data_buffer, length_read_data, hal_ll_spi_master_hw_specifics_map_local->dummy_data); + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +uint32_t hal_ll_spi_master_set_speed(handle_t *handle, uint32_t speed) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + low_level_handle->init_ll_state = false; + + // Insert user-defined baud rate into local map. + hal_ll_spi_master_hw_specifics_map_local->speed = speed; + + // Init once again, but with updated SPI Master baud rate value. + hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + // Return value of the SPI Master baud rate value. + return hal_ll_spi_master_hw_specifics_map_local->hw_actual_speed; +} + +hal_ll_err_t hal_ll_spi_master_set_mode(handle_t *handle, hal_ll_spi_master_mode_t mode) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + low_level_handle->init_ll_state = false; + + // Insert user-defined mode into local map. + hal_ll_spi_master_hw_specifics_map_local->mode = mode; + + // Init once again, but with updated SPI Master mode value. + hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +void hal_ll_spi_master_close(handle_t* handle) { + uint32_t dummy; + low_level_handle = hal_ll_spi_master_get_handle; + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + if(low_level_handle->hal_ll_spi_master_handle != NULL) { + low_level_handle->hal_ll_spi_master_handle = NULL; + low_level_handle->hal_drv_spi_master_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_spi_master_hw_specifics_map_local->mode = HAL_LL_SPI_MASTER_MODE_DEFAULT; + hal_ll_spi_master_hw_specifics_map_local->speed = HAL_LL_SPI_MASTER_SPEED_100K; + hal_ll_spi_master_hw_specifics_map_local->dummy_data = 0; + hal_ll_spi_master_hw_specifics_map_local->hw_actual_speed = 0; + + hal_ll_spi_master_set_clock(hal_ll_spi_master_hw_specifics_map_local, true, &dummy); + hal_ll_spi_master_alternate_functions_set_state(hal_ll_spi_master_hw_specifics_map_local, false); + hal_ll_spi_master_set_clock(hal_ll_spi_master_hw_specifics_map_local, false, &dummy); + + hal_ll_spi_master_hw_specifics_map_local->pins.sck.pin_name = HAL_LL_PIN_NC; + hal_ll_spi_master_hw_specifics_map_local->pins.miso.pin_name = HAL_LL_PIN_NC; + hal_ll_spi_master_hw_specifics_map_local->pins.mosi.pin_name = HAL_LL_PIN_NC; + hal_ll_spi_master_hw_specifics_map_local->pins.sck.pin_af = 0; + hal_ll_spi_master_hw_specifics_map_local->pins.miso.pin_af = 0; + hal_ll_spi_master_hw_specifics_map_local->pins.mosi.pin_af = 0; + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS + +uint8_t hal_ll_spi_master_transfer_bare_metal(hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t data_buffer) { + // Write user-defined data ( 'hal_ll_spi_master_read_bare_metal' procedure will send dummy data ). + *((volatile uint8_t *)&hal_ll_hw_reg->dr) = (uint8_t)data_buffer; // 8-bit data + + // Wait for receive buffer not empty status. + while (!(check_reg_bit( &(hal_ll_hw_reg->sr), HAL_LL_SPI_MASTER_RXNE))); + + // Return read data. + return *((volatile uint8_t *)&hal_ll_hw_reg->dr); // 8-bit data +} + +static void hal_ll_spi_master_write_bare_metal( hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *write_data_buffer, size_t write_data_length ) { + uint16_t transfer_counter = NULL; + + // Write the first data to be transmitted into the SPI_DR register. + for(transfer_counter = 0; transfer_counter < write_data_length; transfer_counter++) { + // If we are good to go ( if the tx buffer value has been shifted to the shift register ), write the data. + hal_ll_spi_master_transfer_bare_metal( hal_ll_hw_reg, write_data_buffer[transfer_counter]); + } +} + +static void hal_ll_spi_master_read_bare_metal(hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *read_data_buffer, size_t read_data_length, uint8_t dummy_data) { + uint16_t transfer_counter = NULL; + + // Read the first data to be transmitted into the SPI_DR register. + for(transfer_counter = 0; transfer_counter < read_data_length; transfer_counter++) { + // If we are good to go ( if the value from shift register has been shifted to the rx register ), read the data. + read_data_buffer[transfer_counter] = hal_ll_spi_master_transfer_bare_metal(hal_ll_hw_reg, dummy_data); + } +} + +static hal_ll_pin_name_t hal_ll_spi_master_check_pins(hal_ll_pin_name_t sck_pin, hal_ll_pin_name_t miso_pin, hal_ll_pin_name_t mosi_pin, hal_ll_spi_pin_id *index_list, hal_ll_spi_master_handle_register_t *handle_map) { + static const uint16_t sck_map_size = (sizeof(_spi_sck_map)) / (sizeof(hal_ll_spi_master_pin_map_t)); + static const uint16_t miso_map_size = (sizeof(_spi_miso_map)) / (sizeof(hal_ll_spi_master_pin_map_t)); + static const uint16_t mosi_map_size = (sizeof(_spi_mosi_map)) / (sizeof(hal_ll_spi_master_pin_map_t)); + uint8_t hal_ll_module_id = 0; + uint8_t index_counter = 0; + uint16_t miso_index; + uint16_t mosi_index; + uint16_t sck_index; + + if ( (HAL_LL_PIN_NC == sck_pin) || (HAL_LL_PIN_NC == miso_pin) || (HAL_LL_PIN_NC == mosi_pin) ) { + return HAL_LL_PIN_NC; + } + + // Check pins from the specific pin maps with the user defined pins. + for (sck_index = 0; sck_index < sck_map_size; sck_index++) { + if (_spi_sck_map[sck_index].pin == sck_pin) { + for (miso_index = 0; miso_index < miso_map_size; miso_index++) { + if (_spi_miso_map[miso_index].pin == miso_pin) { + if (_spi_sck_map[sck_index].module_index ==_spi_miso_map[miso_index].module_index) { + for (mosi_index = 0; mosi_index < mosi_map_size; mosi_index++) { + if (_spi_mosi_map[mosi_index ].pin == mosi_pin) { + if (_spi_sck_map[sck_index].module_index ==_spi_mosi_map[mosi_index].module_index) { + // Get module number + hal_ll_module_id = _spi_sck_map[ sck_index ].module_index; + + // Map pin names + index_list[hal_ll_module_id].pin_sck = sck_index; + index_list[hal_ll_module_id].pin_miso = miso_index; + index_list[hal_ll_module_id].pin_mosi = mosi_index; + + // Check if module is taken + if ( NULL == handle_map[hal_ll_module_id].hal_drv_spi_master_handle ) { + return hal_ll_module_id; + } else if ( SPI_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + } + } + } + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static void hal_ll_spi_master_map_pins(uint8_t module_index, hal_ll_spi_pin_id *index_list) { + // if every single pin is OK, insert them into this new map, and use this map in all low level functions. + hal_ll_spi_master_hw_specifics_map[module_index].pins.sck.pin_name = _spi_sck_map[index_list[module_index].pin_sck].pin; + hal_ll_spi_master_hw_specifics_map[module_index].pins.miso.pin_name = _spi_miso_map[index_list[module_index].pin_miso].pin; + hal_ll_spi_master_hw_specifics_map[module_index].pins.mosi.pin_name = _spi_mosi_map[index_list[module_index].pin_mosi].pin; + + // SCK, MISO and MOSI pins could have different alternate function settings, hence save all the AF-s. + hal_ll_spi_master_hw_specifics_map[module_index].pins.sck.pin_af = _spi_sck_map[index_list[module_index].pin_sck].af; + hal_ll_spi_master_hw_specifics_map[module_index].pins.miso.pin_af = _spi_miso_map[index_list[module_index].pin_miso].af; + hal_ll_spi_master_hw_specifics_map[module_index].pins.mosi.pin_af = _spi_mosi_map[index_list[module_index].pin_mosi].af; +} + +static hal_ll_spi_master_hw_specifics_map_t *hal_ll_get_specifics(handle_t handle) { + uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof( hal_ll_spi_master_handle_register_t)); + + static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof( hal_ll_spi_master_handle_register_t)); + + while (hal_ll_module_count--) { + if (hal_ll_spi_master_get_base_from_hal_handle == hal_ll_spi_master_hw_specifics_map[hal_ll_module_count].base) { + return &hal_ll_spi_master_hw_specifics_map[hal_ll_module_count]; + } + } + + // If NOK, return pointer to the last row of this map ( point to null pointer ). + return &hal_ll_spi_master_hw_specifics_map[hal_ll_module_error]; +} + +static void hal_ll_spi_master_set_clock(hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state, uint32_t *clock_value) { + rcc_clocks_t hal_ll_spi_clock_structure; + + RCC_GetClocksFrequency(&hal_ll_spi_clock_structure); + + switch (map->module_index) { + #if defined(SPI_MODULE_1) + case (hal_ll_spi_master_module_num(SPI_MODULE_1)): + if(hal_ll_state) { + set_reg_bit(_RCC_APBENR2, HAL_LL_SPI1_MASTER_ENABLE); + } else { + clear_reg_bit(_RCC_APBENR2, HAL_LL_SPI1_MASTER_ENABLE); + } + *clock_value = hal_ll_spi_clock_structure.pclk; + break; + #endif + + + } +} + +static void hal_ll_spi_master_alternate_functions_set_state(hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state) { + module_struct module; + uint32_t spi_config; + + if((map->pins.sck.pin_name != HAL_LL_PIN_NC) && (map->pins.miso.pin_name != HAL_LL_PIN_NC) && (map->pins.miso.pin_name != HAL_LL_PIN_NC)) { + module.pins[0] = VALUE(map->pins.sck.pin_name, map->pins.sck.pin_af); + module.pins[1] = VALUE(map->pins.miso.pin_name, map->pins.miso.pin_af); + module.pins[2] = VALUE(map->pins.mosi.pin_name, map->pins.mosi.pin_af); + module.pins[3] = GPIO_MODULE_STRUCT_END; + + spi_config = GPIO_CFG_MODE_ALT_FUNCTION | + GPIO_CFG_SPEED_HIGH | + GPIO_CFG_OTYPE_PP; + + module.configs[0] = spi_config; + module.configs[1] = spi_config; + module.configs[2] = spi_config; + module.configs[3] = GPIO_MODULE_STRUCT_END; + + module.gpio_remap = map->pins.sck.pin_af; + + hal_ll_gpio_module_struct_init(&module, hal_ll_state); + } +} + +static uint32_t hal_ll_spi_master_hw_init(hal_ll_spi_master_hw_specifics_map_t *map, uint32_t clock_value) { + uint32_t temp_speed; + + hal_ll_spi_master_base_handle_t *hal_ll_hw_reg = (hal_ll_spi_master_base_handle_t *)map->base; + + // Reset all the settings in control register. + hal_ll_hw_reg->cr1 = 0; + + // Populate appropriate register values to get appropriate data transfer baud rate prescalers. + temp_speed = hal_ll_spi_master_get_speed(clock_value, map->speed); + hal_ll_hw_reg->cr1 |= temp_speed; + + // Choose whether idle state for the clock is high level (1) or low level (0). + if (map->mode <= HAL_LL_SPI_MASTER_MODE_1) { + clear_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_CLK_POLARITY); + } else { + set_reg_bit(&( hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_CLK_POLARITY); + } + + // Choose whether transmit occurs on the transition from ACTIVE to IDLE (1), or vice versa (0). + if (map->mode == HAL_LL_SPI_MASTER_MODE_0 || map->mode == HAL_LL_SPI_MASTER_MODE_2) { + clear_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_CLK_PHASE); + } else { + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_CLK_PHASE); + } + + // Set default values for SPI Master configuration. + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_SSM_ENABLE); + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_SSI_1); + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_SELECTION); + + // Set Slave Select Output Enable bit. + set_reg_bit(&(hal_ll_hw_reg->cr2), HAL_LL_SPI_MASTER_SSOE_BIT); + + // Set FIFO reception threshold to 8-bit. + hal_ll_hw_reg->cr2 |= HAL_LL_SPI_MASTER_FRXTH; + + // Enable SPI peripheral. + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_ENABLE); + + return (hal_ll_spi_master_get_actual_speed(clock_value, temp_speed)); +} + +static void hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_t *map) { + uint32_t clock_value; + + // Enable specific clock module. + hal_ll_spi_master_set_clock (map, true, &clock_value); + + // Enable specific alternate functions. + hal_ll_spi_master_alternate_functions_set_state(map, true); + + // Finally, write user-defined settings into hardware registers. + hal_ll_spi_master_hw_init(map, clock_value); +} +// ------------------------------------------------------------------------- END + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_74/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_74/CMakeLists.cmake new file mode 100644 index 000000000..9f1fb55cf --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_74/CMakeLists.cmake @@ -0,0 +1,9 @@ +if(${MCU_NAME} MATCHES "^STM32G051C6$|^STM32G051F6$|^STM32G051G6$|^STM32G051K6$|^STM32G051C8$|^STM32G051F8$|^STM32G051G8$|^STM32G051K8$") + set(spi_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_spi_master.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_74") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_74") + list(APPEND hal_ll_def_list "STM32G0xx") + list(APPEND hal_ll_def_list "STM32G05xx") + list(APPEND hal_ll_def_list "STM32G051xx") + set(spi_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/spi_master/hal_ll_spi_master_pin_map/implementations/doc_ds_74") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_74/hal_ll_spi_master.c b/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_74/hal_ll_spi_master.c new file mode 100644 index 000000000..cd91d45ff --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_74/hal_ll_spi_master.c @@ -0,0 +1,715 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_spi_master.c + * @brief SPI Master HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_rcc.h" +#include "hal_ll_spi_master.h" +#include "hal_ll_spi_master_pin_map.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_spi_master_handle_register_t hal_ll_module_state[SPI_MODULE_COUNT] = {(handle_t *)NULL, (handle_t *)NULL, false}; + +// ------------------------------------------------------------- PRIVATE MACROS + +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_spi_master_get_module_state_address ((hal_ll_spi_master_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_spi_master_get_handle (hal_ll_spi_master_handle_register_t *)hal_ll_spi_master_get_module_state_address->hal_ll_spi_master_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_spi_master_get_base_struct(_handle) ((hal_ll_spi_master_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_spi_master_get_base_from_hal_handle ((hal_ll_spi_master_hw_specifics_map_t *)((hal_ll_spi_master_handle_register_t *)\ + (((hal_ll_spi_master_handle_register_t *)(handle))->hal_ll_spi_master_handle))->hal_ll_spi_master_handle)->base + +/*!< CR1 constants. */ +#define HAL_LL_SPI_MASTER 0x4 +#define HAL_LL_SPI_MASTER_SSI_1 8 +#define HAL_LL_SPI_MASTER_SELECTION 2 +/*!< CR2 constants. */ +#define HAL_LL_SPI_MASTER_FRXTH 0x1000ul + +#define HAL_LL_SPI_MASTER_SSOE_BIT 2 +#define HAL_LL_SPI_MASTER_SSOE 0x4 +#define HAL_LL_SPI_MASTER_SSM_ENABLE 9 +#define HAL_LL_SPI_MASTER_SSM_DISABLE 0x0000u +#define HAL_LL_SPI_MASTER_SS_ENABLE 0x10000ul +#define HAL_LL_SPI_MASTER_SS_DISABLE 0x00000ul +/*!< SR constants. */ +#define HAL_LL_SPI_MASTER_RXNE 0 +#define HAL_LL_SPI_MASTER_TXE 1 +/*!< I2SCFGR constants. */ +#define HAL_LL_SPI_MASTER_I2SMOD 11 +/*!< Enable constants. */ +#define HAL_LL_SPI_MASTER_ENABLE 6 +#define HAL_LL_SPI1_MASTER_ENABLE 12 + +#define HAL_LL_SPI2_MASTER_ENABLE 14 + +/*!< General constants. */ +#define HAL_LL_SPI_MASTER_BAUD_RATE_MASK 3 +#define HAL_LL_SPI_MASTER_16_BIT_REG_SHIFT 16 +#define HAL_LL_SPI_MASTER_DEFAULT_BASE_ADDRESS 0xFF + +#define HAL_LL_SPI_MASTER_CLK_POLARITY 1 +#define HAL_LL_SPI_MASTER_CLK_PHASE 0 + +#define hal_ll_spi_master_get_speed(_fosc,_speed) (_speed >= _fosc/2)? (0):\ + ((_speed <= _fosc/2) && (_speed > _fosc/4))? (0):\ + ((_speed <= _fosc/4) && (_speed > _fosc/8))? (0x0008UL):\ + ((_speed <= _fosc/8) && (_speed > _fosc/16))? (0x0010UL):\ + ((_speed <= _fosc/16) && (_speed > _fosc/32))? (0x0018UL):\ + ((_speed <= _fosc/32) && (_speed > _fosc/64))? (0x0020UL):\ + ((_speed <= _fosc/64) && (_speed > _fosc/128))?(0x0028UL):\ + ((_speed <= _fosc/128)&& (_speed > _fosc/256))?(0x0030UL):(0x0038UL) + +#define hal_ll_spi_master_get_actual_speed(_fosc,_divider) (_divider == 0)?(_fosc/2):\ + (_divider == 0x0008UL)?(_fosc/4):\ + (_divider == 0x0010UL)?(_fosc/8):\ + (_divider == 0x0018UL)?(_fosc/16):\ + (_divider == 0x0020UL)?(_fosc/32):\ + (_divider == 0x0028UL)?(_fosc/64):\ + (_divider == 0x0030UL)?(_fosc/128):\ + (_divider == 0x0038UL)?(_fosc/256):(_fosc/256) + +/*!< @brief Default SPI Master bit-rate if no speed is set */ +#define HAL_LL_SPI_MASTER_SPEED_100K 100000 + +// -------------------------------------------------------------- PRIVATE TYPES + +/*!< @brief SPI register structure. */ +typedef struct { + uint32_t cr1; + uint32_t cr2; + uint32_t sr; + uint32_t dr; + uint32_t crcpr; + uint32_t rxcrcr; + uint32_t txcrcr; + uint32_t i2scfgr; + uint32_t i2spr; + +} hal_ll_spi_master_base_handle_t; + +/*!< @brief SPI Master hardware specific structure */ +typedef struct { + hal_ll_base_addr_t base; + uint8_t module_index; + hal_ll_spi_master_pins_t pins; + uint8_t dummy_data; + uint32_t speed; + uint32_t hw_actual_speed; + hal_ll_spi_master_mode_t mode; +} hal_ll_spi_master_hw_specifics_map_t; + +/*!< @brief SPI hw specific module values */ +typedef struct +{ + uint16_t pin_sck; + uint16_t pin_miso; + uint16_t pin_mosi; +} hal_ll_spi_pin_id; + +/*!< @brief SPI Master hw specific error values */ +typedef enum { + HAL_LL_SPI_MASTER_SUCCESS = 0, + HAL_LL_SPI_MASTER_WRONG_PINS, + HAL_LL_SPI_MASTER_MODULE_ERROR, + + HAL_LL_SPI_MASTER_ERROR = (-1) +} hal_ll_spi_master_err_t; + +// ------------------------------------------------------------------ VARIABLES + +/*!< @brief SPI Master hardware specific info */ +static hal_ll_spi_master_hw_specifics_map_t hal_ll_spi_master_hw_specifics_map[] = { + #ifdef SPI_MODULE_1 + {HAL_LL_SPI1_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_1), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, HAL_LL_SPI_MASTER_SPEED_100K, 0, HAL_LL_SPI_MASTER_MODE_DEFAULT}, + #endif + + #ifdef SPI_MODULE_2 + {HAL_LL_SPI2_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_2), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, HAL_LL_SPI_MASTER_SPEED_100K, 0, HAL_LL_SPI_MASTER_MODE_DEFAULT}, + #endif + + + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, 0, 0, 0} +}; + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_spi_master_handle_register_t *low_level_handle; +static volatile hal_ll_spi_master_hw_specifics_map_t *hal_ll_spi_master_hw_specifics_map_local; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Check if pins are adequate. + * + * Checks SCK, MISO and MOSI pins the user has passed with pre-defined + * pins in SCK, MISO and MOSI maps. Take into consideration that module + * index numbers have to be the same for both pins. + * + * @param[in] sck - SCK pre-defined pin name. + * @param[in] miso - MISO pre-defined pin name. + * @param[in] mosi - MOSI pre-defined pin name. + * @param[in] *index_list - Index list address + * @return hal_ll_pin_name_t Module index based on pins. + * + * Returns pre-defined module index from pin maps, if pins + * are adequate. + */ +static hal_ll_pin_name_t hal_ll_spi_master_check_pins(hal_ll_pin_name_t sck, hal_ll_pin_name_t miso, hal_ll_pin_name_t mosi, hal_ll_spi_pin_id *index_list, hal_ll_spi_master_handle_register_t *handle_map ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_spi_master_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_spi_master_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_spi_master_hw_specifics_map_t *hal_ll_get_specifics(handle_t handle); + +/** + * @brief Enable clock for SPI Master module on hardware level. + * + * Initializes SPI Master module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] *map - Object specific context handler. + * @param[in] hal_ll_state - True(enable clock)/False(disable clock). + * @param[in] *clock_value - SPI Master baud rate value taken from a specific peripheral clock bus. + * @return None + */ +static void hal_ll_spi_master_set_clock(hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state, uint32_t *clock_value); + +/** + * @brief Sets SPI Master pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if SPI is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param[in] *map - Object specific context handler. + * @param[in] hal_ll_state - Init/De-init + */ +static void hal_ll_spi_master_alternate_functions_set_state(hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state); + +/** + * @brief Full SPI Master module initialization procedure. + * + * Initializes SPI Master module on hardware level, based on beforehand + * set configuration and module handler. Sets adequate pin alternate functions. + * Initializes module clock. + * + * @param[in] *map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static void hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_t *map); + +/** + * @brief Perform a read on the SPI Master bus. + * + * Initializes SPI Master module on hardware level, if not initialized beforehand + * and continues to perform a read operation on the bus. + * + * @param[in] *map - Object specific context handler. + * @param[in] *read_data_buffer - Pointer to data buffer. + * @param[in] read_data_length - Number of data to be read. + * @param[in] dummy_data - Data required for read procedure. + * @return hal_ll_err_t Module specific error values. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +static void hal_ll_spi_master_read_bare_metal(hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *read_data_buffer, size_t read_data_length, uint8_t dummy_data); + +/** + * @brief Perform a write on the SPI Master bus. + * + * Initializes SPI Master module on hardware level, if not initialized beforehand + * and continues to perform a write operation on the bus. + * + * @param[in] map - Object specific context handler. + * @param[in] *write_data_buffer - Pointer to data buffer. + * @param[in] write_data_length - Number of data to be written. + * @return hal_ll_err_t Module specific error values. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +static void hal_ll_spi_master_write_bare_metal(hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *write_data_buffer, size_t write_data_length); + +/** + * @brief Perform a write then read on the SPI Master bus. + * + * Initializes SPI Master module on hardware level, if not initialized beforehand + * and continues to perform a write operation on the bus. + * + * @param[in] *handle - Object specific context handler. + * @param[in] *write_data_buffer - Pointer to data buffer. + * @param[in] length_write_data - Number of data to be written. + * @param[in] *read_data_buffer - Pointer to data buffer. + * @param[in] length_read_data - Number of data to be read. + * @return hal_ll_err_t Module specific error values. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_spi_master_write_then_read(handle_t *handle, uint8_t *write_data_buffer, size_t length_write_data, uint8_t *read_data_buffer, size_t length_read_data); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * SPI SCK, MISO and MOSI pins. + * + * @param[in] module_index SPI HW module index -- 0,1,2... + * @param[in] *index_list Array with SCK, MISO and MOSI map index values + * and module number + * + * @return None + */ +static void hal_ll_spi_master_map_pins(uint8_t module_index, hal_ll_spi_pin_id *index_list); + + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS + +hal_ll_err_t hal_ll_spi_master_register_handle(hal_ll_pin_name_t sck, hal_ll_pin_name_t miso, hal_ll_pin_name_t mosi, hal_ll_spi_master_handle_register_t *handle_map, uint8_t *hal_module_id) { + + hal_ll_spi_pin_id index_list[SPI_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + uint16_t pin_check_result; + + // Check user-defined pins. + if ((pin_check_result = hal_ll_spi_master_check_pins(sck, miso, mosi, &index_list, handle_map)) == HAL_LL_PIN_NC) { + return HAL_LL_SPI_MASTER_WRONG_PINS; + }; + + // If user has come with the same SPI hardware module, and with the same pair of the pins, the pin mapping procedure + // will not have to take a place; otherwise, clear af-s, map new pins, set af-s, and set init state to false. + if ((hal_ll_spi_master_hw_specifics_map[pin_check_result].pins.sck.pin_name != sck) || + (hal_ll_spi_master_hw_specifics_map[pin_check_result].pins.miso.pin_name != miso) || + (hal_ll_spi_master_hw_specifics_map[pin_check_result].pins.mosi.pin_name != mosi) ) { + + hal_ll_spi_master_alternate_functions_set_state(&hal_ll_spi_master_hw_specifics_map[pin_check_result], false); + + hal_ll_spi_master_map_pins(pin_check_result, &index_list); + + hal_ll_spi_master_alternate_functions_set_state(&hal_ll_spi_master_hw_specifics_map[pin_check_result], true); + + handle_map[pin_check_result].init_ll_state = false; + } + + // Return id of the SPI module that is going to be used. + *hal_module_id = pin_check_result; + + // Insert current module into hal_ll_module_state map. + hal_ll_module_state[pin_check_result].hal_ll_spi_master_handle = (handle_t *)&hal_ll_spi_master_hw_specifics_map[pin_check_result].base; + + // Return the same info about module one level up ( into the HAL level ). + handle_map[pin_check_result].hal_ll_spi_master_handle = (handle_t*)&hal_ll_module_state[pin_check_result].hal_ll_spi_master_handle; + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_spi(handle_t *handle) { + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + hal_ll_spi_master_handle_register_t *hal_handle = (hal_ll_spi_master_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_spi_master_hw_specifics_map_local->module_index; + + hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_local); + + hal_ll_module_state[pin_check_result].hal_ll_spi_master_handle = (handle_t *)&hal_ll_spi_master_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +void hal_ll_spi_master_set_default_write_data(handle_t *handle, uint8_t dummy_data) { + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + if(hal_ll_spi_master_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR) { + hal_ll_spi_master_hw_specifics_map_local->dummy_data = dummy_data; + } +} + +hal_ll_err_t hal_ll_spi_master_write(handle_t *handle, uint8_t *write_data_buffer, size_t length_data) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + hal_ll_spi_master_write_bare_metal(hal_ll_spi_master_hw_specifics_map_local->base, write_data_buffer, length_data); + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_spi_master_read(handle_t *handle, uint8_t *read_data_buffer, size_t length_data) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + hal_ll_spi_master_read_bare_metal(hal_ll_spi_master_hw_specifics_map_local->base, read_data_buffer, length_data, hal_ll_spi_master_hw_specifics_map_local->dummy_data); + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_spi_master_write_then_read(handle_t *handle, uint8_t *write_data_buffer, size_t length_write_data, uint8_t *read_data_buffer, size_t length_read_data) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + hal_ll_spi_master_write_bare_metal(hal_ll_spi_master_hw_specifics_map_local->base, write_data_buffer, length_write_data); + + hal_ll_spi_master_read_bare_metal(hal_ll_spi_master_hw_specifics_map_local->base, read_data_buffer, length_read_data, hal_ll_spi_master_hw_specifics_map_local->dummy_data); + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +uint32_t hal_ll_spi_master_set_speed(handle_t *handle, uint32_t speed) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + low_level_handle->init_ll_state = false; + + // Insert user-defined baud rate into local map. + hal_ll_spi_master_hw_specifics_map_local->speed = speed; + + // Init once again, but with updated SPI Master baud rate value. + hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + // Return value of the SPI Master baud rate value. + return hal_ll_spi_master_hw_specifics_map_local->hw_actual_speed; +} + +hal_ll_err_t hal_ll_spi_master_set_mode(handle_t *handle, hal_ll_spi_master_mode_t mode) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + low_level_handle->init_ll_state = false; + + // Insert user-defined mode into local map. + hal_ll_spi_master_hw_specifics_map_local->mode = mode; + + // Init once again, but with updated SPI Master mode value. + hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +void hal_ll_spi_master_close(handle_t* handle) { + uint32_t dummy; + low_level_handle = hal_ll_spi_master_get_handle; + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + if(low_level_handle->hal_ll_spi_master_handle != NULL) { + low_level_handle->hal_ll_spi_master_handle = NULL; + low_level_handle->hal_drv_spi_master_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_spi_master_hw_specifics_map_local->mode = HAL_LL_SPI_MASTER_MODE_DEFAULT; + hal_ll_spi_master_hw_specifics_map_local->speed = HAL_LL_SPI_MASTER_SPEED_100K; + hal_ll_spi_master_hw_specifics_map_local->dummy_data = 0; + hal_ll_spi_master_hw_specifics_map_local->hw_actual_speed = 0; + + hal_ll_spi_master_set_clock(hal_ll_spi_master_hw_specifics_map_local, true, &dummy); + hal_ll_spi_master_alternate_functions_set_state(hal_ll_spi_master_hw_specifics_map_local, false); + hal_ll_spi_master_set_clock(hal_ll_spi_master_hw_specifics_map_local, false, &dummy); + + hal_ll_spi_master_hw_specifics_map_local->pins.sck.pin_name = HAL_LL_PIN_NC; + hal_ll_spi_master_hw_specifics_map_local->pins.miso.pin_name = HAL_LL_PIN_NC; + hal_ll_spi_master_hw_specifics_map_local->pins.mosi.pin_name = HAL_LL_PIN_NC; + hal_ll_spi_master_hw_specifics_map_local->pins.sck.pin_af = 0; + hal_ll_spi_master_hw_specifics_map_local->pins.miso.pin_af = 0; + hal_ll_spi_master_hw_specifics_map_local->pins.mosi.pin_af = 0; + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS + +uint8_t hal_ll_spi_master_transfer_bare_metal(hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t data_buffer) { + // Write user-defined data ( 'hal_ll_spi_master_read_bare_metal' procedure will send dummy data ). + *((volatile uint8_t *)&hal_ll_hw_reg->dr) = (uint8_t)data_buffer; // 8-bit data + + // Wait for receive buffer not empty status. + while (!(check_reg_bit( &(hal_ll_hw_reg->sr), HAL_LL_SPI_MASTER_RXNE))); + + // Return read data. + return *((volatile uint8_t *)&hal_ll_hw_reg->dr); // 8-bit data +} + +static void hal_ll_spi_master_write_bare_metal( hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *write_data_buffer, size_t write_data_length ) { + uint16_t transfer_counter = NULL; + + // Write the first data to be transmitted into the SPI_DR register. + for(transfer_counter = 0; transfer_counter < write_data_length; transfer_counter++) { + // If we are good to go ( if the tx buffer value has been shifted to the shift register ), write the data. + hal_ll_spi_master_transfer_bare_metal( hal_ll_hw_reg, write_data_buffer[transfer_counter]); + } +} + +static void hal_ll_spi_master_read_bare_metal(hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *read_data_buffer, size_t read_data_length, uint8_t dummy_data) { + uint16_t transfer_counter = NULL; + + // Read the first data to be transmitted into the SPI_DR register. + for(transfer_counter = 0; transfer_counter < read_data_length; transfer_counter++) { + // If we are good to go ( if the value from shift register has been shifted to the rx register ), read the data. + read_data_buffer[transfer_counter] = hal_ll_spi_master_transfer_bare_metal(hal_ll_hw_reg, dummy_data); + } +} + +static hal_ll_pin_name_t hal_ll_spi_master_check_pins(hal_ll_pin_name_t sck_pin, hal_ll_pin_name_t miso_pin, hal_ll_pin_name_t mosi_pin, hal_ll_spi_pin_id *index_list, hal_ll_spi_master_handle_register_t *handle_map) { + static const uint16_t sck_map_size = (sizeof(_spi_sck_map)) / (sizeof(hal_ll_spi_master_pin_map_t)); + static const uint16_t miso_map_size = (sizeof(_spi_miso_map)) / (sizeof(hal_ll_spi_master_pin_map_t)); + static const uint16_t mosi_map_size = (sizeof(_spi_mosi_map)) / (sizeof(hal_ll_spi_master_pin_map_t)); + uint8_t hal_ll_module_id = 0; + uint8_t index_counter = 0; + uint16_t miso_index; + uint16_t mosi_index; + uint16_t sck_index; + + if ( (HAL_LL_PIN_NC == sck_pin) || (HAL_LL_PIN_NC == miso_pin) || (HAL_LL_PIN_NC == mosi_pin) ) { + return HAL_LL_PIN_NC; + } + + // Check pins from the specific pin maps with the user defined pins. + for (sck_index = 0; sck_index < sck_map_size; sck_index++) { + if (_spi_sck_map[sck_index].pin == sck_pin) { + for (miso_index = 0; miso_index < miso_map_size; miso_index++) { + if (_spi_miso_map[miso_index].pin == miso_pin) { + if (_spi_sck_map[sck_index].module_index ==_spi_miso_map[miso_index].module_index) { + for (mosi_index = 0; mosi_index < mosi_map_size; mosi_index++) { + if (_spi_mosi_map[mosi_index ].pin == mosi_pin) { + if (_spi_sck_map[sck_index].module_index ==_spi_mosi_map[mosi_index].module_index) { + // Get module number + hal_ll_module_id = _spi_sck_map[ sck_index ].module_index; + + // Map pin names + index_list[hal_ll_module_id].pin_sck = sck_index; + index_list[hal_ll_module_id].pin_miso = miso_index; + index_list[hal_ll_module_id].pin_mosi = mosi_index; + + // Check if module is taken + if ( NULL == handle_map[hal_ll_module_id].hal_drv_spi_master_handle ) { + return hal_ll_module_id; + } else if ( SPI_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + } + } + } + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static void hal_ll_spi_master_map_pins(uint8_t module_index, hal_ll_spi_pin_id *index_list) { + // if every single pin is OK, insert them into this new map, and use this map in all low level functions. + hal_ll_spi_master_hw_specifics_map[module_index].pins.sck.pin_name = _spi_sck_map[index_list[module_index].pin_sck].pin; + hal_ll_spi_master_hw_specifics_map[module_index].pins.miso.pin_name = _spi_miso_map[index_list[module_index].pin_miso].pin; + hal_ll_spi_master_hw_specifics_map[module_index].pins.mosi.pin_name = _spi_mosi_map[index_list[module_index].pin_mosi].pin; + + // SCK, MISO and MOSI pins could have different alternate function settings, hence save all the AF-s. + hal_ll_spi_master_hw_specifics_map[module_index].pins.sck.pin_af = _spi_sck_map[index_list[module_index].pin_sck].af; + hal_ll_spi_master_hw_specifics_map[module_index].pins.miso.pin_af = _spi_miso_map[index_list[module_index].pin_miso].af; + hal_ll_spi_master_hw_specifics_map[module_index].pins.mosi.pin_af = _spi_mosi_map[index_list[module_index].pin_mosi].af; +} + +static hal_ll_spi_master_hw_specifics_map_t *hal_ll_get_specifics(handle_t handle) { + uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof( hal_ll_spi_master_handle_register_t)); + + static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof( hal_ll_spi_master_handle_register_t)); + + while (hal_ll_module_count--) { + if (hal_ll_spi_master_get_base_from_hal_handle == hal_ll_spi_master_hw_specifics_map[hal_ll_module_count].base) { + return &hal_ll_spi_master_hw_specifics_map[hal_ll_module_count]; + } + } + + // If NOK, return pointer to the last row of this map ( point to null pointer ). + return &hal_ll_spi_master_hw_specifics_map[hal_ll_module_error]; +} + +static void hal_ll_spi_master_set_clock(hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state, uint32_t *clock_value) { + rcc_clocks_t hal_ll_spi_clock_structure; + + RCC_GetClocksFrequency(&hal_ll_spi_clock_structure); + + switch (map->module_index) { + #if defined(SPI_MODULE_1) + case (hal_ll_spi_master_module_num(SPI_MODULE_1)): + if(hal_ll_state) { + set_reg_bit(_RCC_APBENR2, HAL_LL_SPI1_MASTER_ENABLE); + } else { + clear_reg_bit(_RCC_APBENR2, HAL_LL_SPI1_MASTER_ENABLE); + } + *clock_value = hal_ll_spi_clock_structure.pclk; + break; + #endif + + #if defined(SPI_MODULE_2) + case (hal_ll_spi_master_module_num(SPI_MODULE_2)): + if(hal_ll_state) { + set_reg_bit(_RCC_APBENR1, HAL_LL_SPI2_MASTER_ENABLE); + } else { + clear_reg_bit(_RCC_APBENR1, HAL_LL_SPI2_MASTER_ENABLE); + } + *clock_value = hal_ll_spi_clock_structure.pclk; + break; + #endif + + + } +} + +static void hal_ll_spi_master_alternate_functions_set_state(hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state) { + module_struct module; + uint32_t spi_config; + + if((map->pins.sck.pin_name != HAL_LL_PIN_NC) && (map->pins.miso.pin_name != HAL_LL_PIN_NC) && (map->pins.miso.pin_name != HAL_LL_PIN_NC)) { + module.pins[0] = VALUE(map->pins.sck.pin_name, map->pins.sck.pin_af); + module.pins[1] = VALUE(map->pins.miso.pin_name, map->pins.miso.pin_af); + module.pins[2] = VALUE(map->pins.mosi.pin_name, map->pins.mosi.pin_af); + module.pins[3] = GPIO_MODULE_STRUCT_END; + + spi_config = GPIO_CFG_MODE_ALT_FUNCTION | + GPIO_CFG_SPEED_HIGH | + GPIO_CFG_OTYPE_PP; + + module.configs[0] = spi_config; + module.configs[1] = spi_config; + module.configs[2] = spi_config; + module.configs[3] = GPIO_MODULE_STRUCT_END; + + module.gpio_remap = map->pins.sck.pin_af; + + hal_ll_gpio_module_struct_init(&module, hal_ll_state); + } +} + +static uint32_t hal_ll_spi_master_hw_init(hal_ll_spi_master_hw_specifics_map_t *map, uint32_t clock_value) { + uint32_t temp_speed; + + hal_ll_spi_master_base_handle_t *hal_ll_hw_reg = (hal_ll_spi_master_base_handle_t *)map->base; + + // Reset all the settings in control register. + hal_ll_hw_reg->cr1 = 0; + + // Populate appropriate register values to get appropriate data transfer baud rate prescalers. + temp_speed = hal_ll_spi_master_get_speed(clock_value, map->speed); + hal_ll_hw_reg->cr1 |= temp_speed; + + // Choose whether idle state for the clock is high level (1) or low level (0). + if (map->mode <= HAL_LL_SPI_MASTER_MODE_1) { + clear_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_CLK_POLARITY); + } else { + set_reg_bit(&( hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_CLK_POLARITY); + } + + // Choose whether transmit occurs on the transition from ACTIVE to IDLE (1), or vice versa (0). + if (map->mode == HAL_LL_SPI_MASTER_MODE_0 || map->mode == HAL_LL_SPI_MASTER_MODE_2) { + clear_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_CLK_PHASE); + } else { + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_CLK_PHASE); + } + + // Set default values for SPI Master configuration. + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_SSM_ENABLE); + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_SSI_1); + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_SELECTION); + + // Set Slave Select Output Enable bit. + set_reg_bit(&(hal_ll_hw_reg->cr2), HAL_LL_SPI_MASTER_SSOE_BIT); + + // Set FIFO reception threshold to 8-bit. + hal_ll_hw_reg->cr2 |= HAL_LL_SPI_MASTER_FRXTH; + + // Enable SPI peripheral. + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_ENABLE); + + return (hal_ll_spi_master_get_actual_speed(clock_value, temp_speed)); +} + +static void hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_t *map) { + uint32_t clock_value; + + // Enable specific clock module. + hal_ll_spi_master_set_clock (map, true, &clock_value); + + // Enable specific alternate functions. + hal_ll_spi_master_alternate_functions_set_state(map, true); + + // Finally, write user-defined settings into hardware registers. + hal_ll_spi_master_hw_init(map, clock_value); +} +// ------------------------------------------------------------------------- END + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_75/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_75/CMakeLists.cmake new file mode 100644 index 000000000..0ccf62c68 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_75/CMakeLists.cmake @@ -0,0 +1,9 @@ +if(${MCU_NAME} MATCHES "^STM32G061C6$|^STM32G061F6$|^STM32G061G6$|^STM32G061K6$|^STM32G061C8$|^STM32G061F8$|^STM32G061G8$|^STM32G061K8$") + set(spi_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_spi_master.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_75") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_75") + list(APPEND hal_ll_def_list "STM32G0xx") + list(APPEND hal_ll_def_list "STM32G06xx") + list(APPEND hal_ll_def_list "STM32G061xx") + set(spi_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/spi_master/hal_ll_spi_master_pin_map/implementations/doc_ds_75") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_75/hal_ll_spi_master.c b/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_75/hal_ll_spi_master.c new file mode 100644 index 000000000..cd91d45ff --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_75/hal_ll_spi_master.c @@ -0,0 +1,715 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_spi_master.c + * @brief SPI Master HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_rcc.h" +#include "hal_ll_spi_master.h" +#include "hal_ll_spi_master_pin_map.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_spi_master_handle_register_t hal_ll_module_state[SPI_MODULE_COUNT] = {(handle_t *)NULL, (handle_t *)NULL, false}; + +// ------------------------------------------------------------- PRIVATE MACROS + +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_spi_master_get_module_state_address ((hal_ll_spi_master_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_spi_master_get_handle (hal_ll_spi_master_handle_register_t *)hal_ll_spi_master_get_module_state_address->hal_ll_spi_master_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_spi_master_get_base_struct(_handle) ((hal_ll_spi_master_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_spi_master_get_base_from_hal_handle ((hal_ll_spi_master_hw_specifics_map_t *)((hal_ll_spi_master_handle_register_t *)\ + (((hal_ll_spi_master_handle_register_t *)(handle))->hal_ll_spi_master_handle))->hal_ll_spi_master_handle)->base + +/*!< CR1 constants. */ +#define HAL_LL_SPI_MASTER 0x4 +#define HAL_LL_SPI_MASTER_SSI_1 8 +#define HAL_LL_SPI_MASTER_SELECTION 2 +/*!< CR2 constants. */ +#define HAL_LL_SPI_MASTER_FRXTH 0x1000ul + +#define HAL_LL_SPI_MASTER_SSOE_BIT 2 +#define HAL_LL_SPI_MASTER_SSOE 0x4 +#define HAL_LL_SPI_MASTER_SSM_ENABLE 9 +#define HAL_LL_SPI_MASTER_SSM_DISABLE 0x0000u +#define HAL_LL_SPI_MASTER_SS_ENABLE 0x10000ul +#define HAL_LL_SPI_MASTER_SS_DISABLE 0x00000ul +/*!< SR constants. */ +#define HAL_LL_SPI_MASTER_RXNE 0 +#define HAL_LL_SPI_MASTER_TXE 1 +/*!< I2SCFGR constants. */ +#define HAL_LL_SPI_MASTER_I2SMOD 11 +/*!< Enable constants. */ +#define HAL_LL_SPI_MASTER_ENABLE 6 +#define HAL_LL_SPI1_MASTER_ENABLE 12 + +#define HAL_LL_SPI2_MASTER_ENABLE 14 + +/*!< General constants. */ +#define HAL_LL_SPI_MASTER_BAUD_RATE_MASK 3 +#define HAL_LL_SPI_MASTER_16_BIT_REG_SHIFT 16 +#define HAL_LL_SPI_MASTER_DEFAULT_BASE_ADDRESS 0xFF + +#define HAL_LL_SPI_MASTER_CLK_POLARITY 1 +#define HAL_LL_SPI_MASTER_CLK_PHASE 0 + +#define hal_ll_spi_master_get_speed(_fosc,_speed) (_speed >= _fosc/2)? (0):\ + ((_speed <= _fosc/2) && (_speed > _fosc/4))? (0):\ + ((_speed <= _fosc/4) && (_speed > _fosc/8))? (0x0008UL):\ + ((_speed <= _fosc/8) && (_speed > _fosc/16))? (0x0010UL):\ + ((_speed <= _fosc/16) && (_speed > _fosc/32))? (0x0018UL):\ + ((_speed <= _fosc/32) && (_speed > _fosc/64))? (0x0020UL):\ + ((_speed <= _fosc/64) && (_speed > _fosc/128))?(0x0028UL):\ + ((_speed <= _fosc/128)&& (_speed > _fosc/256))?(0x0030UL):(0x0038UL) + +#define hal_ll_spi_master_get_actual_speed(_fosc,_divider) (_divider == 0)?(_fosc/2):\ + (_divider == 0x0008UL)?(_fosc/4):\ + (_divider == 0x0010UL)?(_fosc/8):\ + (_divider == 0x0018UL)?(_fosc/16):\ + (_divider == 0x0020UL)?(_fosc/32):\ + (_divider == 0x0028UL)?(_fosc/64):\ + (_divider == 0x0030UL)?(_fosc/128):\ + (_divider == 0x0038UL)?(_fosc/256):(_fosc/256) + +/*!< @brief Default SPI Master bit-rate if no speed is set */ +#define HAL_LL_SPI_MASTER_SPEED_100K 100000 + +// -------------------------------------------------------------- PRIVATE TYPES + +/*!< @brief SPI register structure. */ +typedef struct { + uint32_t cr1; + uint32_t cr2; + uint32_t sr; + uint32_t dr; + uint32_t crcpr; + uint32_t rxcrcr; + uint32_t txcrcr; + uint32_t i2scfgr; + uint32_t i2spr; + +} hal_ll_spi_master_base_handle_t; + +/*!< @brief SPI Master hardware specific structure */ +typedef struct { + hal_ll_base_addr_t base; + uint8_t module_index; + hal_ll_spi_master_pins_t pins; + uint8_t dummy_data; + uint32_t speed; + uint32_t hw_actual_speed; + hal_ll_spi_master_mode_t mode; +} hal_ll_spi_master_hw_specifics_map_t; + +/*!< @brief SPI hw specific module values */ +typedef struct +{ + uint16_t pin_sck; + uint16_t pin_miso; + uint16_t pin_mosi; +} hal_ll_spi_pin_id; + +/*!< @brief SPI Master hw specific error values */ +typedef enum { + HAL_LL_SPI_MASTER_SUCCESS = 0, + HAL_LL_SPI_MASTER_WRONG_PINS, + HAL_LL_SPI_MASTER_MODULE_ERROR, + + HAL_LL_SPI_MASTER_ERROR = (-1) +} hal_ll_spi_master_err_t; + +// ------------------------------------------------------------------ VARIABLES + +/*!< @brief SPI Master hardware specific info */ +static hal_ll_spi_master_hw_specifics_map_t hal_ll_spi_master_hw_specifics_map[] = { + #ifdef SPI_MODULE_1 + {HAL_LL_SPI1_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_1), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, HAL_LL_SPI_MASTER_SPEED_100K, 0, HAL_LL_SPI_MASTER_MODE_DEFAULT}, + #endif + + #ifdef SPI_MODULE_2 + {HAL_LL_SPI2_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_2), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, HAL_LL_SPI_MASTER_SPEED_100K, 0, HAL_LL_SPI_MASTER_MODE_DEFAULT}, + #endif + + + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, 0, 0, 0} +}; + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_spi_master_handle_register_t *low_level_handle; +static volatile hal_ll_spi_master_hw_specifics_map_t *hal_ll_spi_master_hw_specifics_map_local; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Check if pins are adequate. + * + * Checks SCK, MISO and MOSI pins the user has passed with pre-defined + * pins in SCK, MISO and MOSI maps. Take into consideration that module + * index numbers have to be the same for both pins. + * + * @param[in] sck - SCK pre-defined pin name. + * @param[in] miso - MISO pre-defined pin name. + * @param[in] mosi - MOSI pre-defined pin name. + * @param[in] *index_list - Index list address + * @return hal_ll_pin_name_t Module index based on pins. + * + * Returns pre-defined module index from pin maps, if pins + * are adequate. + */ +static hal_ll_pin_name_t hal_ll_spi_master_check_pins(hal_ll_pin_name_t sck, hal_ll_pin_name_t miso, hal_ll_pin_name_t mosi, hal_ll_spi_pin_id *index_list, hal_ll_spi_master_handle_register_t *handle_map ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_spi_master_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_spi_master_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_spi_master_hw_specifics_map_t *hal_ll_get_specifics(handle_t handle); + +/** + * @brief Enable clock for SPI Master module on hardware level. + * + * Initializes SPI Master module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] *map - Object specific context handler. + * @param[in] hal_ll_state - True(enable clock)/False(disable clock). + * @param[in] *clock_value - SPI Master baud rate value taken from a specific peripheral clock bus. + * @return None + */ +static void hal_ll_spi_master_set_clock(hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state, uint32_t *clock_value); + +/** + * @brief Sets SPI Master pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if SPI is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param[in] *map - Object specific context handler. + * @param[in] hal_ll_state - Init/De-init + */ +static void hal_ll_spi_master_alternate_functions_set_state(hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state); + +/** + * @brief Full SPI Master module initialization procedure. + * + * Initializes SPI Master module on hardware level, based on beforehand + * set configuration and module handler. Sets adequate pin alternate functions. + * Initializes module clock. + * + * @param[in] *map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static void hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_t *map); + +/** + * @brief Perform a read on the SPI Master bus. + * + * Initializes SPI Master module on hardware level, if not initialized beforehand + * and continues to perform a read operation on the bus. + * + * @param[in] *map - Object specific context handler. + * @param[in] *read_data_buffer - Pointer to data buffer. + * @param[in] read_data_length - Number of data to be read. + * @param[in] dummy_data - Data required for read procedure. + * @return hal_ll_err_t Module specific error values. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +static void hal_ll_spi_master_read_bare_metal(hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *read_data_buffer, size_t read_data_length, uint8_t dummy_data); + +/** + * @brief Perform a write on the SPI Master bus. + * + * Initializes SPI Master module on hardware level, if not initialized beforehand + * and continues to perform a write operation on the bus. + * + * @param[in] map - Object specific context handler. + * @param[in] *write_data_buffer - Pointer to data buffer. + * @param[in] write_data_length - Number of data to be written. + * @return hal_ll_err_t Module specific error values. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +static void hal_ll_spi_master_write_bare_metal(hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *write_data_buffer, size_t write_data_length); + +/** + * @brief Perform a write then read on the SPI Master bus. + * + * Initializes SPI Master module on hardware level, if not initialized beforehand + * and continues to perform a write operation on the bus. + * + * @param[in] *handle - Object specific context handler. + * @param[in] *write_data_buffer - Pointer to data buffer. + * @param[in] length_write_data - Number of data to be written. + * @param[in] *read_data_buffer - Pointer to data buffer. + * @param[in] length_read_data - Number of data to be read. + * @return hal_ll_err_t Module specific error values. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_spi_master_write_then_read(handle_t *handle, uint8_t *write_data_buffer, size_t length_write_data, uint8_t *read_data_buffer, size_t length_read_data); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * SPI SCK, MISO and MOSI pins. + * + * @param[in] module_index SPI HW module index -- 0,1,2... + * @param[in] *index_list Array with SCK, MISO and MOSI map index values + * and module number + * + * @return None + */ +static void hal_ll_spi_master_map_pins(uint8_t module_index, hal_ll_spi_pin_id *index_list); + + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS + +hal_ll_err_t hal_ll_spi_master_register_handle(hal_ll_pin_name_t sck, hal_ll_pin_name_t miso, hal_ll_pin_name_t mosi, hal_ll_spi_master_handle_register_t *handle_map, uint8_t *hal_module_id) { + + hal_ll_spi_pin_id index_list[SPI_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + uint16_t pin_check_result; + + // Check user-defined pins. + if ((pin_check_result = hal_ll_spi_master_check_pins(sck, miso, mosi, &index_list, handle_map)) == HAL_LL_PIN_NC) { + return HAL_LL_SPI_MASTER_WRONG_PINS; + }; + + // If user has come with the same SPI hardware module, and with the same pair of the pins, the pin mapping procedure + // will not have to take a place; otherwise, clear af-s, map new pins, set af-s, and set init state to false. + if ((hal_ll_spi_master_hw_specifics_map[pin_check_result].pins.sck.pin_name != sck) || + (hal_ll_spi_master_hw_specifics_map[pin_check_result].pins.miso.pin_name != miso) || + (hal_ll_spi_master_hw_specifics_map[pin_check_result].pins.mosi.pin_name != mosi) ) { + + hal_ll_spi_master_alternate_functions_set_state(&hal_ll_spi_master_hw_specifics_map[pin_check_result], false); + + hal_ll_spi_master_map_pins(pin_check_result, &index_list); + + hal_ll_spi_master_alternate_functions_set_state(&hal_ll_spi_master_hw_specifics_map[pin_check_result], true); + + handle_map[pin_check_result].init_ll_state = false; + } + + // Return id of the SPI module that is going to be used. + *hal_module_id = pin_check_result; + + // Insert current module into hal_ll_module_state map. + hal_ll_module_state[pin_check_result].hal_ll_spi_master_handle = (handle_t *)&hal_ll_spi_master_hw_specifics_map[pin_check_result].base; + + // Return the same info about module one level up ( into the HAL level ). + handle_map[pin_check_result].hal_ll_spi_master_handle = (handle_t*)&hal_ll_module_state[pin_check_result].hal_ll_spi_master_handle; + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_spi(handle_t *handle) { + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + hal_ll_spi_master_handle_register_t *hal_handle = (hal_ll_spi_master_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_spi_master_hw_specifics_map_local->module_index; + + hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_local); + + hal_ll_module_state[pin_check_result].hal_ll_spi_master_handle = (handle_t *)&hal_ll_spi_master_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +void hal_ll_spi_master_set_default_write_data(handle_t *handle, uint8_t dummy_data) { + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + if(hal_ll_spi_master_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR) { + hal_ll_spi_master_hw_specifics_map_local->dummy_data = dummy_data; + } +} + +hal_ll_err_t hal_ll_spi_master_write(handle_t *handle, uint8_t *write_data_buffer, size_t length_data) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + hal_ll_spi_master_write_bare_metal(hal_ll_spi_master_hw_specifics_map_local->base, write_data_buffer, length_data); + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_spi_master_read(handle_t *handle, uint8_t *read_data_buffer, size_t length_data) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + hal_ll_spi_master_read_bare_metal(hal_ll_spi_master_hw_specifics_map_local->base, read_data_buffer, length_data, hal_ll_spi_master_hw_specifics_map_local->dummy_data); + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_spi_master_write_then_read(handle_t *handle, uint8_t *write_data_buffer, size_t length_write_data, uint8_t *read_data_buffer, size_t length_read_data) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + hal_ll_spi_master_write_bare_metal(hal_ll_spi_master_hw_specifics_map_local->base, write_data_buffer, length_write_data); + + hal_ll_spi_master_read_bare_metal(hal_ll_spi_master_hw_specifics_map_local->base, read_data_buffer, length_read_data, hal_ll_spi_master_hw_specifics_map_local->dummy_data); + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +uint32_t hal_ll_spi_master_set_speed(handle_t *handle, uint32_t speed) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + low_level_handle->init_ll_state = false; + + // Insert user-defined baud rate into local map. + hal_ll_spi_master_hw_specifics_map_local->speed = speed; + + // Init once again, but with updated SPI Master baud rate value. + hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + // Return value of the SPI Master baud rate value. + return hal_ll_spi_master_hw_specifics_map_local->hw_actual_speed; +} + +hal_ll_err_t hal_ll_spi_master_set_mode(handle_t *handle, hal_ll_spi_master_mode_t mode) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + low_level_handle->init_ll_state = false; + + // Insert user-defined mode into local map. + hal_ll_spi_master_hw_specifics_map_local->mode = mode; + + // Init once again, but with updated SPI Master mode value. + hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +void hal_ll_spi_master_close(handle_t* handle) { + uint32_t dummy; + low_level_handle = hal_ll_spi_master_get_handle; + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + if(low_level_handle->hal_ll_spi_master_handle != NULL) { + low_level_handle->hal_ll_spi_master_handle = NULL; + low_level_handle->hal_drv_spi_master_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_spi_master_hw_specifics_map_local->mode = HAL_LL_SPI_MASTER_MODE_DEFAULT; + hal_ll_spi_master_hw_specifics_map_local->speed = HAL_LL_SPI_MASTER_SPEED_100K; + hal_ll_spi_master_hw_specifics_map_local->dummy_data = 0; + hal_ll_spi_master_hw_specifics_map_local->hw_actual_speed = 0; + + hal_ll_spi_master_set_clock(hal_ll_spi_master_hw_specifics_map_local, true, &dummy); + hal_ll_spi_master_alternate_functions_set_state(hal_ll_spi_master_hw_specifics_map_local, false); + hal_ll_spi_master_set_clock(hal_ll_spi_master_hw_specifics_map_local, false, &dummy); + + hal_ll_spi_master_hw_specifics_map_local->pins.sck.pin_name = HAL_LL_PIN_NC; + hal_ll_spi_master_hw_specifics_map_local->pins.miso.pin_name = HAL_LL_PIN_NC; + hal_ll_spi_master_hw_specifics_map_local->pins.mosi.pin_name = HAL_LL_PIN_NC; + hal_ll_spi_master_hw_specifics_map_local->pins.sck.pin_af = 0; + hal_ll_spi_master_hw_specifics_map_local->pins.miso.pin_af = 0; + hal_ll_spi_master_hw_specifics_map_local->pins.mosi.pin_af = 0; + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS + +uint8_t hal_ll_spi_master_transfer_bare_metal(hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t data_buffer) { + // Write user-defined data ( 'hal_ll_spi_master_read_bare_metal' procedure will send dummy data ). + *((volatile uint8_t *)&hal_ll_hw_reg->dr) = (uint8_t)data_buffer; // 8-bit data + + // Wait for receive buffer not empty status. + while (!(check_reg_bit( &(hal_ll_hw_reg->sr), HAL_LL_SPI_MASTER_RXNE))); + + // Return read data. + return *((volatile uint8_t *)&hal_ll_hw_reg->dr); // 8-bit data +} + +static void hal_ll_spi_master_write_bare_metal( hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *write_data_buffer, size_t write_data_length ) { + uint16_t transfer_counter = NULL; + + // Write the first data to be transmitted into the SPI_DR register. + for(transfer_counter = 0; transfer_counter < write_data_length; transfer_counter++) { + // If we are good to go ( if the tx buffer value has been shifted to the shift register ), write the data. + hal_ll_spi_master_transfer_bare_metal( hal_ll_hw_reg, write_data_buffer[transfer_counter]); + } +} + +static void hal_ll_spi_master_read_bare_metal(hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *read_data_buffer, size_t read_data_length, uint8_t dummy_data) { + uint16_t transfer_counter = NULL; + + // Read the first data to be transmitted into the SPI_DR register. + for(transfer_counter = 0; transfer_counter < read_data_length; transfer_counter++) { + // If we are good to go ( if the value from shift register has been shifted to the rx register ), read the data. + read_data_buffer[transfer_counter] = hal_ll_spi_master_transfer_bare_metal(hal_ll_hw_reg, dummy_data); + } +} + +static hal_ll_pin_name_t hal_ll_spi_master_check_pins(hal_ll_pin_name_t sck_pin, hal_ll_pin_name_t miso_pin, hal_ll_pin_name_t mosi_pin, hal_ll_spi_pin_id *index_list, hal_ll_spi_master_handle_register_t *handle_map) { + static const uint16_t sck_map_size = (sizeof(_spi_sck_map)) / (sizeof(hal_ll_spi_master_pin_map_t)); + static const uint16_t miso_map_size = (sizeof(_spi_miso_map)) / (sizeof(hal_ll_spi_master_pin_map_t)); + static const uint16_t mosi_map_size = (sizeof(_spi_mosi_map)) / (sizeof(hal_ll_spi_master_pin_map_t)); + uint8_t hal_ll_module_id = 0; + uint8_t index_counter = 0; + uint16_t miso_index; + uint16_t mosi_index; + uint16_t sck_index; + + if ( (HAL_LL_PIN_NC == sck_pin) || (HAL_LL_PIN_NC == miso_pin) || (HAL_LL_PIN_NC == mosi_pin) ) { + return HAL_LL_PIN_NC; + } + + // Check pins from the specific pin maps with the user defined pins. + for (sck_index = 0; sck_index < sck_map_size; sck_index++) { + if (_spi_sck_map[sck_index].pin == sck_pin) { + for (miso_index = 0; miso_index < miso_map_size; miso_index++) { + if (_spi_miso_map[miso_index].pin == miso_pin) { + if (_spi_sck_map[sck_index].module_index ==_spi_miso_map[miso_index].module_index) { + for (mosi_index = 0; mosi_index < mosi_map_size; mosi_index++) { + if (_spi_mosi_map[mosi_index ].pin == mosi_pin) { + if (_spi_sck_map[sck_index].module_index ==_spi_mosi_map[mosi_index].module_index) { + // Get module number + hal_ll_module_id = _spi_sck_map[ sck_index ].module_index; + + // Map pin names + index_list[hal_ll_module_id].pin_sck = sck_index; + index_list[hal_ll_module_id].pin_miso = miso_index; + index_list[hal_ll_module_id].pin_mosi = mosi_index; + + // Check if module is taken + if ( NULL == handle_map[hal_ll_module_id].hal_drv_spi_master_handle ) { + return hal_ll_module_id; + } else if ( SPI_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + } + } + } + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static void hal_ll_spi_master_map_pins(uint8_t module_index, hal_ll_spi_pin_id *index_list) { + // if every single pin is OK, insert them into this new map, and use this map in all low level functions. + hal_ll_spi_master_hw_specifics_map[module_index].pins.sck.pin_name = _spi_sck_map[index_list[module_index].pin_sck].pin; + hal_ll_spi_master_hw_specifics_map[module_index].pins.miso.pin_name = _spi_miso_map[index_list[module_index].pin_miso].pin; + hal_ll_spi_master_hw_specifics_map[module_index].pins.mosi.pin_name = _spi_mosi_map[index_list[module_index].pin_mosi].pin; + + // SCK, MISO and MOSI pins could have different alternate function settings, hence save all the AF-s. + hal_ll_spi_master_hw_specifics_map[module_index].pins.sck.pin_af = _spi_sck_map[index_list[module_index].pin_sck].af; + hal_ll_spi_master_hw_specifics_map[module_index].pins.miso.pin_af = _spi_miso_map[index_list[module_index].pin_miso].af; + hal_ll_spi_master_hw_specifics_map[module_index].pins.mosi.pin_af = _spi_mosi_map[index_list[module_index].pin_mosi].af; +} + +static hal_ll_spi_master_hw_specifics_map_t *hal_ll_get_specifics(handle_t handle) { + uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof( hal_ll_spi_master_handle_register_t)); + + static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof( hal_ll_spi_master_handle_register_t)); + + while (hal_ll_module_count--) { + if (hal_ll_spi_master_get_base_from_hal_handle == hal_ll_spi_master_hw_specifics_map[hal_ll_module_count].base) { + return &hal_ll_spi_master_hw_specifics_map[hal_ll_module_count]; + } + } + + // If NOK, return pointer to the last row of this map ( point to null pointer ). + return &hal_ll_spi_master_hw_specifics_map[hal_ll_module_error]; +} + +static void hal_ll_spi_master_set_clock(hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state, uint32_t *clock_value) { + rcc_clocks_t hal_ll_spi_clock_structure; + + RCC_GetClocksFrequency(&hal_ll_spi_clock_structure); + + switch (map->module_index) { + #if defined(SPI_MODULE_1) + case (hal_ll_spi_master_module_num(SPI_MODULE_1)): + if(hal_ll_state) { + set_reg_bit(_RCC_APBENR2, HAL_LL_SPI1_MASTER_ENABLE); + } else { + clear_reg_bit(_RCC_APBENR2, HAL_LL_SPI1_MASTER_ENABLE); + } + *clock_value = hal_ll_spi_clock_structure.pclk; + break; + #endif + + #if defined(SPI_MODULE_2) + case (hal_ll_spi_master_module_num(SPI_MODULE_2)): + if(hal_ll_state) { + set_reg_bit(_RCC_APBENR1, HAL_LL_SPI2_MASTER_ENABLE); + } else { + clear_reg_bit(_RCC_APBENR1, HAL_LL_SPI2_MASTER_ENABLE); + } + *clock_value = hal_ll_spi_clock_structure.pclk; + break; + #endif + + + } +} + +static void hal_ll_spi_master_alternate_functions_set_state(hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state) { + module_struct module; + uint32_t spi_config; + + if((map->pins.sck.pin_name != HAL_LL_PIN_NC) && (map->pins.miso.pin_name != HAL_LL_PIN_NC) && (map->pins.miso.pin_name != HAL_LL_PIN_NC)) { + module.pins[0] = VALUE(map->pins.sck.pin_name, map->pins.sck.pin_af); + module.pins[1] = VALUE(map->pins.miso.pin_name, map->pins.miso.pin_af); + module.pins[2] = VALUE(map->pins.mosi.pin_name, map->pins.mosi.pin_af); + module.pins[3] = GPIO_MODULE_STRUCT_END; + + spi_config = GPIO_CFG_MODE_ALT_FUNCTION | + GPIO_CFG_SPEED_HIGH | + GPIO_CFG_OTYPE_PP; + + module.configs[0] = spi_config; + module.configs[1] = spi_config; + module.configs[2] = spi_config; + module.configs[3] = GPIO_MODULE_STRUCT_END; + + module.gpio_remap = map->pins.sck.pin_af; + + hal_ll_gpio_module_struct_init(&module, hal_ll_state); + } +} + +static uint32_t hal_ll_spi_master_hw_init(hal_ll_spi_master_hw_specifics_map_t *map, uint32_t clock_value) { + uint32_t temp_speed; + + hal_ll_spi_master_base_handle_t *hal_ll_hw_reg = (hal_ll_spi_master_base_handle_t *)map->base; + + // Reset all the settings in control register. + hal_ll_hw_reg->cr1 = 0; + + // Populate appropriate register values to get appropriate data transfer baud rate prescalers. + temp_speed = hal_ll_spi_master_get_speed(clock_value, map->speed); + hal_ll_hw_reg->cr1 |= temp_speed; + + // Choose whether idle state for the clock is high level (1) or low level (0). + if (map->mode <= HAL_LL_SPI_MASTER_MODE_1) { + clear_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_CLK_POLARITY); + } else { + set_reg_bit(&( hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_CLK_POLARITY); + } + + // Choose whether transmit occurs on the transition from ACTIVE to IDLE (1), or vice versa (0). + if (map->mode == HAL_LL_SPI_MASTER_MODE_0 || map->mode == HAL_LL_SPI_MASTER_MODE_2) { + clear_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_CLK_PHASE); + } else { + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_CLK_PHASE); + } + + // Set default values for SPI Master configuration. + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_SSM_ENABLE); + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_SSI_1); + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_SELECTION); + + // Set Slave Select Output Enable bit. + set_reg_bit(&(hal_ll_hw_reg->cr2), HAL_LL_SPI_MASTER_SSOE_BIT); + + // Set FIFO reception threshold to 8-bit. + hal_ll_hw_reg->cr2 |= HAL_LL_SPI_MASTER_FRXTH; + + // Enable SPI peripheral. + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_ENABLE); + + return (hal_ll_spi_master_get_actual_speed(clock_value, temp_speed)); +} + +static void hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_t *map) { + uint32_t clock_value; + + // Enable specific clock module. + hal_ll_spi_master_set_clock (map, true, &clock_value); + + // Enable specific alternate functions. + hal_ll_spi_master_alternate_functions_set_state(map, true); + + // Finally, write user-defined settings into hardware registers. + hal_ll_spi_master_hw_init(map, clock_value); +} +// ------------------------------------------------------------------------- END + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_80/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_80/CMakeLists.cmake new file mode 100644 index 000000000..93b3f1b3e --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_80/CMakeLists.cmake @@ -0,0 +1,9 @@ +if(${MCU_NAME} MATCHES "^STM32G0B1CB$|^STM32G0B1KB$|^STM32G0B1MB$|^STM32G0B1RB$|^STM32G0B1VB$|^STM32G0B1CC$|^STM32G0B1KC$|^STM32G0B1MC$|^STM32G0B1RC$|^STM32G0B1VC$|^STM32G0B1CE$|^STM32G0B1KE$|^STM32G0B1ME$|^STM32G0B1NE$|^STM32G0B1RE$|^STM32G0B1VE$") + set(spi_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_spi_master.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_80") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_80") + list(APPEND hal_ll_def_list "STM32G0xx") + list(APPEND hal_ll_def_list "STM32G0Bxx") + list(APPEND hal_ll_def_list "STM32G0B1xx") + set(spi_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/spi_master/hal_ll_spi_master_pin_map/implementations/doc_ds_80") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_80/hal_ll_spi_master.c b/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_80/hal_ll_spi_master.c new file mode 100644 index 000000000..a8c725477 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_80/hal_ll_spi_master.c @@ -0,0 +1,722 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_spi_master.c + * @brief SPI Master HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_rcc.h" +#include "hal_ll_spi_master.h" +#include "hal_ll_spi_master_pin_map.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_spi_master_handle_register_t hal_ll_module_state[SPI_MODULE_COUNT] = {(handle_t *)NULL, (handle_t *)NULL, false}; + +// ------------------------------------------------------------- PRIVATE MACROS + +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_spi_master_get_module_state_address ((hal_ll_spi_master_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_spi_master_get_handle (hal_ll_spi_master_handle_register_t *)hal_ll_spi_master_get_module_state_address->hal_ll_spi_master_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_spi_master_get_base_struct(_handle) ((hal_ll_spi_master_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_spi_master_get_base_from_hal_handle ((hal_ll_spi_master_hw_specifics_map_t *)((hal_ll_spi_master_handle_register_t *)\ + (((hal_ll_spi_master_handle_register_t *)(handle))->hal_ll_spi_master_handle))->hal_ll_spi_master_handle)->base + +/*!< CR1 constants. */ +#define HAL_LL_SPI_MASTER 0x4 +#define HAL_LL_SPI_MASTER_SSI_1 8 +#define HAL_LL_SPI_MASTER_SELECTION 2 +/*!< CR2 constants. */ +#define HAL_LL_SPI_MASTER_FRXTH 0x1000ul + +#define HAL_LL_SPI_MASTER_SSOE_BIT 2 +#define HAL_LL_SPI_MASTER_SSOE 0x4 +#define HAL_LL_SPI_MASTER_SSM_ENABLE 9 +#define HAL_LL_SPI_MASTER_SSM_DISABLE 0x0000u +#define HAL_LL_SPI_MASTER_SS_ENABLE 0x10000ul +#define HAL_LL_SPI_MASTER_SS_DISABLE 0x00000ul +/*!< SR constants. */ +#define HAL_LL_SPI_MASTER_RXNE 0 +#define HAL_LL_SPI_MASTER_TXE 1 +/*!< I2SCFGR constants. */ +#define HAL_LL_SPI_MASTER_I2SMOD 11 +/*!< Enable constants. */ +#define HAL_LL_SPI_MASTER_ENABLE 6 +#define HAL_LL_SPI1_MASTER_ENABLE 12 + +#define HAL_LL_SPI2_MASTER_ENABLE 14 + +#define HAL_LL_SPI3_MASTER_ENABLE 15 + +/*!< General constants. */ +#define HAL_LL_SPI_MASTER_BAUD_RATE_MASK 3 +#define HAL_LL_SPI_MASTER_16_BIT_REG_SHIFT 16 +#define HAL_LL_SPI_MASTER_DEFAULT_BASE_ADDRESS 0xFF + +#define HAL_LL_SPI_MASTER_CLK_POLARITY 1 +#define HAL_LL_SPI_MASTER_CLK_PHASE 0 + +#define hal_ll_spi_master_get_speed(_fosc,_speed) (_speed >= _fosc/2)? (0):\ + ((_speed <= _fosc/2) && (_speed > _fosc/4))? (0):\ + ((_speed <= _fosc/4) && (_speed > _fosc/8))? (0x0008UL):\ + ((_speed <= _fosc/8) && (_speed > _fosc/16))? (0x0010UL):\ + ((_speed <= _fosc/16) && (_speed > _fosc/32))? (0x0018UL):\ + ((_speed <= _fosc/32) && (_speed > _fosc/64))? (0x0020UL):\ + ((_speed <= _fosc/64) && (_speed > _fosc/128))?(0x0028UL):\ + ((_speed <= _fosc/128)&& (_speed > _fosc/256))?(0x0030UL):(0x0038UL) + +#define hal_ll_spi_master_get_actual_speed(_fosc,_divider) (_divider == 0)?(_fosc/2):\ + (_divider == 0x0008UL)?(_fosc/4):\ + (_divider == 0x0010UL)?(_fosc/8):\ + (_divider == 0x0018UL)?(_fosc/16):\ + (_divider == 0x0020UL)?(_fosc/32):\ + (_divider == 0x0028UL)?(_fosc/64):\ + (_divider == 0x0030UL)?(_fosc/128):\ + (_divider == 0x0038UL)?(_fosc/256):(_fosc/256) + +/*!< @brief Default SPI Master bit-rate if no speed is set */ +#define HAL_LL_SPI_MASTER_SPEED_100K 100000 + +// -------------------------------------------------------------- PRIVATE TYPES + +/*!< @brief SPI register structure. */ +typedef struct { + uint32_t cr1; + uint32_t cr2; + uint32_t sr; + uint32_t dr; + uint32_t crcpr; + uint32_t rxcrcr; + uint32_t txcrcr; + uint32_t i2scfgr; + uint32_t i2spr; +} hal_ll_spi_master_base_handle_t; + +/*!< @brief SPI Master hardware specific structure */ +typedef struct { + hal_ll_base_addr_t base; + uint8_t module_index; + hal_ll_spi_master_pins_t pins; + uint8_t dummy_data; + uint32_t speed; + uint32_t hw_actual_speed; + hal_ll_spi_master_mode_t mode; +} hal_ll_spi_master_hw_specifics_map_t; + +/*!< @brief SPI hw specific module values */ +typedef struct +{ + uint16_t pin_sck; + uint16_t pin_miso; + uint16_t pin_mosi; +} hal_ll_spi_pin_id; + +/*!< @brief SPI Master hw specific error values */ +typedef enum { + HAL_LL_SPI_MASTER_SUCCESS = 0, + HAL_LL_SPI_MASTER_WRONG_PINS, + HAL_LL_SPI_MASTER_MODULE_ERROR, + + HAL_LL_SPI_MASTER_ERROR = (-1) +} hal_ll_spi_master_err_t; + +// ------------------------------------------------------------------ VARIABLES + +/*!< @brief SPI Master hardware specific info */ +static hal_ll_spi_master_hw_specifics_map_t hal_ll_spi_master_hw_specifics_map[] = { + #ifdef SPI_MODULE_1 + {HAL_LL_SPI1_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_1), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, HAL_LL_SPI_MASTER_SPEED_100K, 0, HAL_LL_SPI_MASTER_MODE_DEFAULT}, + #endif + #ifdef SPI_MODULE_2 + {HAL_LL_SPI2_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_2), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, HAL_LL_SPI_MASTER_SPEED_100K, 0, HAL_LL_SPI_MASTER_MODE_DEFAULT}, + #endif + #ifdef SPI_MODULE_3 + {HAL_LL_SPI3_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_3), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, HAL_LL_SPI_MASTER_SPEED_100K, 0, HAL_LL_SPI_MASTER_MODE_DEFAULT}, + #endif + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, 0, 0, 0} +}; + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_spi_master_handle_register_t *low_level_handle; +static volatile hal_ll_spi_master_hw_specifics_map_t *hal_ll_spi_master_hw_specifics_map_local; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Check if pins are adequate. + * + * Checks SCK, MISO and MOSI pins the user has passed with pre-defined + * pins in SCK, MISO and MOSI maps. Take into consideration that module + * index numbers have to be the same for both pins. + * + * @param[in] sck - SCK pre-defined pin name. + * @param[in] miso - MISO pre-defined pin name. + * @param[in] mosi - MOSI pre-defined pin name. + * @param[in] *index_list - Index list address + * @return hal_ll_pin_name_t Module index based on pins. + * + * Returns pre-defined module index from pin maps, if pins + * are adequate. + */ +static hal_ll_pin_name_t hal_ll_spi_master_check_pins(hal_ll_pin_name_t sck, hal_ll_pin_name_t miso, hal_ll_pin_name_t mosi, hal_ll_spi_pin_id *index_list, hal_ll_spi_master_handle_register_t *handle_map ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_spi_master_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_spi_master_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_spi_master_hw_specifics_map_t *hal_ll_get_specifics(handle_t handle); + +/** + * @brief Enable clock for SPI Master module on hardware level. + * + * Initializes SPI Master module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] *map - Object specific context handler. + * @param[in] hal_ll_state - True(enable clock)/False(disable clock). + * @param[in] *clock_value - SPI Master baud rate value taken from a specific peripheral clock bus. + * @return None + */ +static void hal_ll_spi_master_set_clock(hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state, uint32_t *clock_value); + +/** + * @brief Sets SPI Master pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if SPI is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param[in] *map - Object specific context handler. + * @param[in] hal_ll_state - Init/De-init + */ +static void hal_ll_spi_master_alternate_functions_set_state(hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state); + +/** + * @brief Full SPI Master module initialization procedure. + * + * Initializes SPI Master module on hardware level, based on beforehand + * set configuration and module handler. Sets adequate pin alternate functions. + * Initializes module clock. + * + * @param[in] *map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static void hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_t *map); + +/** + * @brief Perform a read on the SPI Master bus. + * + * Initializes SPI Master module on hardware level, if not initialized beforehand + * and continues to perform a read operation on the bus. + * + * @param[in] *map - Object specific context handler. + * @param[in] *read_data_buffer - Pointer to data buffer. + * @param[in] read_data_length - Number of data to be read. + * @param[in] dummy_data - Data required for read procedure. + * @return hal_ll_err_t Module specific error values. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +static void hal_ll_spi_master_read_bare_metal(hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *read_data_buffer, size_t read_data_length, uint8_t dummy_data); + +/** + * @brief Perform a write on the SPI Master bus. + * + * Initializes SPI Master module on hardware level, if not initialized beforehand + * and continues to perform a write operation on the bus. + * + * @param[in] map - Object specific context handler. + * @param[in] *write_data_buffer - Pointer to data buffer. + * @param[in] write_data_length - Number of data to be written. + * @return hal_ll_err_t Module specific error values. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +static void hal_ll_spi_master_write_bare_metal(hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *write_data_buffer, size_t write_data_length); + +/** + * @brief Perform a write then read on the SPI Master bus. + * + * Initializes SPI Master module on hardware level, if not initialized beforehand + * and continues to perform a write operation on the bus. + * + * @param[in] *handle - Object specific context handler. + * @param[in] *write_data_buffer - Pointer to data buffer. + * @param[in] length_write_data - Number of data to be written. + * @param[in] *read_data_buffer - Pointer to data buffer. + * @param[in] length_read_data - Number of data to be read. + * @return hal_ll_err_t Module specific error values. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_spi_master_write_then_read(handle_t *handle, uint8_t *write_data_buffer, size_t length_write_data, uint8_t *read_data_buffer, size_t length_read_data); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * SPI SCK, MISO and MOSI pins. + * + * @param[in] module_index SPI HW module index -- 0,1,2... + * @param[in] *index_list Array with SCK, MISO and MOSI map index values + * and module number + * + * @return None + */ +static void hal_ll_spi_master_map_pins(uint8_t module_index, hal_ll_spi_pin_id *index_list); + + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS + +hal_ll_err_t hal_ll_spi_master_register_handle(hal_ll_pin_name_t sck, hal_ll_pin_name_t miso, hal_ll_pin_name_t mosi, hal_ll_spi_master_handle_register_t *handle_map, uint8_t *hal_module_id) { + + hal_ll_spi_pin_id index_list[SPI_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + uint16_t pin_check_result; + + // Check user-defined pins. + if ((pin_check_result = hal_ll_spi_master_check_pins(sck, miso, mosi, &index_list, handle_map)) == HAL_LL_PIN_NC) { + return HAL_LL_SPI_MASTER_WRONG_PINS; + }; + + // If user has come with the same SPI hardware module, and with the same pair of the pins, the pin mapping procedure + // will not have to take a place; otherwise, clear af-s, map new pins, set af-s, and set init state to false. + if ((hal_ll_spi_master_hw_specifics_map[pin_check_result].pins.sck.pin_name != sck) || + (hal_ll_spi_master_hw_specifics_map[pin_check_result].pins.miso.pin_name != miso) || + (hal_ll_spi_master_hw_specifics_map[pin_check_result].pins.mosi.pin_name != mosi) ) { + + hal_ll_spi_master_alternate_functions_set_state(&hal_ll_spi_master_hw_specifics_map[pin_check_result], false); + + hal_ll_spi_master_map_pins(pin_check_result, &index_list); + + hal_ll_spi_master_alternate_functions_set_state(&hal_ll_spi_master_hw_specifics_map[pin_check_result], true); + + handle_map[pin_check_result].init_ll_state = false; + } + + // Return id of the SPI module that is going to be used. + *hal_module_id = pin_check_result; + + // Insert current module into hal_ll_module_state map. + hal_ll_module_state[pin_check_result].hal_ll_spi_master_handle = (handle_t *)&hal_ll_spi_master_hw_specifics_map[pin_check_result].base; + + // Return the same info about module one level up ( into the HAL level ). + handle_map[pin_check_result].hal_ll_spi_master_handle = (handle_t*)&hal_ll_module_state[pin_check_result].hal_ll_spi_master_handle; + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_spi(handle_t *handle) { + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + hal_ll_spi_master_handle_register_t *hal_handle = (hal_ll_spi_master_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_spi_master_hw_specifics_map_local->module_index; + + hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_local); + + hal_ll_module_state[pin_check_result].hal_ll_spi_master_handle = (handle_t *)&hal_ll_spi_master_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +void hal_ll_spi_master_set_default_write_data(handle_t *handle, uint8_t dummy_data) { + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + if(hal_ll_spi_master_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR) { + hal_ll_spi_master_hw_specifics_map_local->dummy_data = dummy_data; + } +} + +hal_ll_err_t hal_ll_spi_master_write(handle_t *handle, uint8_t *write_data_buffer, size_t length_data) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + hal_ll_spi_master_write_bare_metal(hal_ll_spi_master_hw_specifics_map_local->base, write_data_buffer, length_data); + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_spi_master_read(handle_t *handle, uint8_t *read_data_buffer, size_t length_data) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + hal_ll_spi_master_read_bare_metal(hal_ll_spi_master_hw_specifics_map_local->base, read_data_buffer, length_data, hal_ll_spi_master_hw_specifics_map_local->dummy_data); + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_spi_master_write_then_read(handle_t *handle, uint8_t *write_data_buffer, size_t length_write_data, uint8_t *read_data_buffer, size_t length_read_data) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + hal_ll_spi_master_write_bare_metal(hal_ll_spi_master_hw_specifics_map_local->base, write_data_buffer, length_write_data); + + hal_ll_spi_master_read_bare_metal(hal_ll_spi_master_hw_specifics_map_local->base, read_data_buffer, length_read_data, hal_ll_spi_master_hw_specifics_map_local->dummy_data); + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +uint32_t hal_ll_spi_master_set_speed(handle_t *handle, uint32_t speed) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + low_level_handle->init_ll_state = false; + + // Insert user-defined baud rate into local map. + hal_ll_spi_master_hw_specifics_map_local->speed = speed; + + // Init once again, but with updated SPI Master baud rate value. + hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + // Return value of the SPI Master baud rate value. + return hal_ll_spi_master_hw_specifics_map_local->hw_actual_speed; +} + +hal_ll_err_t hal_ll_spi_master_set_mode(handle_t *handle, hal_ll_spi_master_mode_t mode) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + low_level_handle->init_ll_state = false; + + // Insert user-defined mode into local map. + hal_ll_spi_master_hw_specifics_map_local->mode = mode; + + // Init once again, but with updated SPI Master mode value. + hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +void hal_ll_spi_master_close(handle_t* handle) { + uint32_t dummy; + low_level_handle = hal_ll_spi_master_get_handle; + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + if(low_level_handle->hal_ll_spi_master_handle != NULL) { + low_level_handle->hal_ll_spi_master_handle = NULL; + low_level_handle->hal_drv_spi_master_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_spi_master_hw_specifics_map_local->mode = HAL_LL_SPI_MASTER_MODE_DEFAULT; + hal_ll_spi_master_hw_specifics_map_local->speed = HAL_LL_SPI_MASTER_SPEED_100K; + hal_ll_spi_master_hw_specifics_map_local->dummy_data = 0; + hal_ll_spi_master_hw_specifics_map_local->hw_actual_speed = 0; + + hal_ll_spi_master_set_clock(hal_ll_spi_master_hw_specifics_map_local, true, &dummy); + hal_ll_spi_master_alternate_functions_set_state(hal_ll_spi_master_hw_specifics_map_local, false); + hal_ll_spi_master_set_clock(hal_ll_spi_master_hw_specifics_map_local, false, &dummy); + + hal_ll_spi_master_hw_specifics_map_local->pins.sck.pin_name = HAL_LL_PIN_NC; + hal_ll_spi_master_hw_specifics_map_local->pins.miso.pin_name = HAL_LL_PIN_NC; + hal_ll_spi_master_hw_specifics_map_local->pins.mosi.pin_name = HAL_LL_PIN_NC; + hal_ll_spi_master_hw_specifics_map_local->pins.sck.pin_af = 0; + hal_ll_spi_master_hw_specifics_map_local->pins.miso.pin_af = 0; + hal_ll_spi_master_hw_specifics_map_local->pins.mosi.pin_af = 0; + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS + +uint8_t hal_ll_spi_master_transfer_bare_metal(hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t data_buffer) { + // Write user-defined data ( 'hal_ll_spi_master_read_bare_metal' procedure will send dummy data ). + *((volatile uint8_t *)&hal_ll_hw_reg->dr) = (uint8_t)data_buffer; // 8-bit data + + // Wait for receive buffer not empty status. + while (!(check_reg_bit( &(hal_ll_hw_reg->sr), HAL_LL_SPI_MASTER_RXNE))); + + // Return read data. + return *((volatile uint8_t *)&hal_ll_hw_reg->dr); // 8-bit data +} + +static void hal_ll_spi_master_write_bare_metal( hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *write_data_buffer, size_t write_data_length ) { + uint16_t transfer_counter = NULL; + + // Write the first data to be transmitted into the SPI_DR register. + for(transfer_counter = 0; transfer_counter < write_data_length; transfer_counter++) { + // If we are good to go ( if the tx buffer value has been shifted to the shift register ), write the data. + hal_ll_spi_master_transfer_bare_metal( hal_ll_hw_reg, write_data_buffer[transfer_counter]); + } +} + +static void hal_ll_spi_master_read_bare_metal(hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *read_data_buffer, size_t read_data_length, uint8_t dummy_data) { + uint16_t transfer_counter = NULL; + + // Read the first data to be transmitted into the SPI_DR register. + for(transfer_counter = 0; transfer_counter < read_data_length; transfer_counter++) { + // If we are good to go ( if the value from shift register has been shifted to the rx register ), read the data. + read_data_buffer[transfer_counter] = hal_ll_spi_master_transfer_bare_metal(hal_ll_hw_reg, dummy_data); + } +} + +static hal_ll_pin_name_t hal_ll_spi_master_check_pins(hal_ll_pin_name_t sck_pin, hal_ll_pin_name_t miso_pin, hal_ll_pin_name_t mosi_pin, hal_ll_spi_pin_id *index_list, hal_ll_spi_master_handle_register_t *handle_map) { + static const uint16_t sck_map_size = (sizeof(_spi_sck_map)) / (sizeof(hal_ll_spi_master_pin_map_t)); + static const uint16_t miso_map_size = (sizeof(_spi_miso_map)) / (sizeof(hal_ll_spi_master_pin_map_t)); + static const uint16_t mosi_map_size = (sizeof(_spi_mosi_map)) / (sizeof(hal_ll_spi_master_pin_map_t)); + uint8_t hal_ll_module_id = 0; + uint8_t index_counter = 0; + uint16_t miso_index; + uint16_t mosi_index; + uint16_t sck_index; + + if ( (HAL_LL_PIN_NC == sck_pin) || (HAL_LL_PIN_NC == miso_pin) || (HAL_LL_PIN_NC == mosi_pin) ) { + return HAL_LL_PIN_NC; + } + + // Check pins from the specific pin maps with the user defined pins. + for (sck_index = 0; sck_index < sck_map_size; sck_index++) { + if (_spi_sck_map[sck_index].pin == sck_pin) { + for (miso_index = 0; miso_index < miso_map_size; miso_index++) { + if (_spi_miso_map[miso_index].pin == miso_pin) { + if (_spi_sck_map[sck_index].module_index ==_spi_miso_map[miso_index].module_index) { + for (mosi_index = 0; mosi_index < mosi_map_size; mosi_index++) { + if (_spi_mosi_map[mosi_index ].pin == mosi_pin) { + if (_spi_sck_map[sck_index].module_index ==_spi_mosi_map[mosi_index].module_index) { + // Get module number + hal_ll_module_id = _spi_sck_map[ sck_index ].module_index; + + // Map pin names + index_list[hal_ll_module_id].pin_sck = sck_index; + index_list[hal_ll_module_id].pin_miso = miso_index; + index_list[hal_ll_module_id].pin_mosi = mosi_index; + + // Check if module is taken + if ( NULL == handle_map[hal_ll_module_id].hal_drv_spi_master_handle ) { + return hal_ll_module_id; + } else if ( SPI_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + } + } + } + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static void hal_ll_spi_master_map_pins(uint8_t module_index, hal_ll_spi_pin_id *index_list) { + // if every single pin is OK, insert them into this new map, and use this map in all low level functions. + hal_ll_spi_master_hw_specifics_map[module_index].pins.sck.pin_name = _spi_sck_map[index_list[module_index].pin_sck].pin; + hal_ll_spi_master_hw_specifics_map[module_index].pins.miso.pin_name = _spi_miso_map[index_list[module_index].pin_miso].pin; + hal_ll_spi_master_hw_specifics_map[module_index].pins.mosi.pin_name = _spi_mosi_map[index_list[module_index].pin_mosi].pin; + + // SCK, MISO and MOSI pins could have different alternate function settings, hence save all the AF-s. + hal_ll_spi_master_hw_specifics_map[module_index].pins.sck.pin_af = _spi_sck_map[index_list[module_index].pin_sck].af; + hal_ll_spi_master_hw_specifics_map[module_index].pins.miso.pin_af = _spi_miso_map[index_list[module_index].pin_miso].af; + hal_ll_spi_master_hw_specifics_map[module_index].pins.mosi.pin_af = _spi_mosi_map[index_list[module_index].pin_mosi].af; +} + +static hal_ll_spi_master_hw_specifics_map_t *hal_ll_get_specifics(handle_t handle) { + uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof( hal_ll_spi_master_handle_register_t)); + + static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof( hal_ll_spi_master_handle_register_t)); + + while (hal_ll_module_count--) { + if (hal_ll_spi_master_get_base_from_hal_handle == hal_ll_spi_master_hw_specifics_map[hal_ll_module_count].base) { + return &hal_ll_spi_master_hw_specifics_map[hal_ll_module_count]; + } + } + + // If NOK, return pointer to the last row of this map ( point to null pointer ). + return &hal_ll_spi_master_hw_specifics_map[hal_ll_module_error]; +} + +static void hal_ll_spi_master_set_clock(hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state, uint32_t *clock_value) { + rcc_clocks_t hal_ll_spi_clock_structure; + + RCC_GetClocksFrequency(&hal_ll_spi_clock_structure); + + switch (map->module_index) { + #if defined(SPI_MODULE_1) + case (hal_ll_spi_master_module_num(SPI_MODULE_1)): + if(hal_ll_state) { + set_reg_bit(_RCC_APBENR2, HAL_LL_SPI1_MASTER_ENABLE); + } else { + clear_reg_bit(_RCC_APBENR2, HAL_LL_SPI1_MASTER_ENABLE); + } + *clock_value = hal_ll_spi_clock_structure.pclk; + break; + #endif + #if defined(SPI_MODULE_2) + case (hal_ll_spi_master_module_num(SPI_MODULE_2)): + if(hal_ll_state) { + set_reg_bit(_RCC_APBENR1, HAL_LL_SPI2_MASTER_ENABLE); + } else { + clear_reg_bit(_RCC_APBENR1, HAL_LL_SPI2_MASTER_ENABLE); + } + *clock_value = hal_ll_spi_clock_structure.pclk; + break; + #endif + #if defined(SPI_MODULE_3) + case (hal_ll_spi_master_module_num(SPI_MODULE_3)): + if(hal_ll_state) { + set_reg_bit(_RCC_APBENR1, HAL_LL_SPI3_MASTER_ENABLE); + } else { + clear_reg_bit(_RCC_APBENR1, HAL_LL_SPI3_MASTER_ENABLE); + } + *clock_value = hal_ll_spi_clock_structure.pclk; + break; + #endif + } +} + +static void hal_ll_spi_master_alternate_functions_set_state(hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state) { + module_struct module; + uint32_t spi_config; + + if((map->pins.sck.pin_name != HAL_LL_PIN_NC) && (map->pins.miso.pin_name != HAL_LL_PIN_NC) && (map->pins.miso.pin_name != HAL_LL_PIN_NC)) { + module.pins[0] = VALUE(map->pins.sck.pin_name, map->pins.sck.pin_af); + module.pins[1] = VALUE(map->pins.miso.pin_name, map->pins.miso.pin_af); + module.pins[2] = VALUE(map->pins.mosi.pin_name, map->pins.mosi.pin_af); + module.pins[3] = GPIO_MODULE_STRUCT_END; + + spi_config = GPIO_CFG_MODE_ALT_FUNCTION | + GPIO_CFG_SPEED_HIGH | + GPIO_CFG_OTYPE_PP; + + module.configs[0] = spi_config; + module.configs[1] = spi_config; + module.configs[2] = spi_config; + module.configs[3] = GPIO_MODULE_STRUCT_END; + + module.gpio_remap = map->pins.sck.pin_af; + + hal_ll_gpio_module_struct_init(&module, hal_ll_state); + } +} + +static uint32_t hal_ll_spi_master_hw_init(hal_ll_spi_master_hw_specifics_map_t *map, uint32_t clock_value) { + uint32_t temp_speed; + + hal_ll_spi_master_base_handle_t *hal_ll_hw_reg = (hal_ll_spi_master_base_handle_t *)map->base; + + // Reset all the settings in control register. + hal_ll_hw_reg->cr1 = 0; + + // Populate appropriate register values to get appropriate data transfer baud rate prescalers. + temp_speed = hal_ll_spi_master_get_speed(clock_value, map->speed); + hal_ll_hw_reg->cr1 |= temp_speed; + + // Choose whether idle state for the clock is high level (1) or low level (0). + if (map->mode <= HAL_LL_SPI_MASTER_MODE_1) { + clear_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_CLK_POLARITY); + } else { + set_reg_bit(&( hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_CLK_POLARITY); + } + + // Choose whether transmit occurs on the transition from ACTIVE to IDLE (1), or vice versa (0). + if (map->mode == HAL_LL_SPI_MASTER_MODE_0 || map->mode == HAL_LL_SPI_MASTER_MODE_2) { + clear_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_CLK_PHASE); + } else { + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_CLK_PHASE); + } + + // Set default values for SPI Master configuration. + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_SSM_ENABLE); + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_SSI_1); + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_SELECTION); + + // Set Slave Select Output Enable bit. + set_reg_bit(&(hal_ll_hw_reg->cr2), HAL_LL_SPI_MASTER_SSOE_BIT); + + // Set FIFO reception threshold to 8-bit. + hal_ll_hw_reg->cr2 |= HAL_LL_SPI_MASTER_FRXTH; + + // Enable SPI peripheral. + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_ENABLE); + + return (hal_ll_spi_master_get_actual_speed(clock_value, temp_speed)); +} + +static void hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_t *map) { + uint32_t clock_value; + + // Enable specific clock module. + hal_ll_spi_master_set_clock (map, true, &clock_value); + + // Enable specific alternate functions. + hal_ll_spi_master_alternate_functions_set_state(map, true); + + // Finally, write user-defined settings into hardware registers. + hal_ll_spi_master_hw_init(map, clock_value); +} +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_81/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_81/CMakeLists.cmake new file mode 100644 index 000000000..6bbca12b3 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_81/CMakeLists.cmake @@ -0,0 +1,9 @@ +if(${MCU_NAME} MATCHES "^STM32G0C1CC$|^STM32G0C1KC$|^STM32G0C1MC$|^STM32G0C1RC$|^STM32G0C1VC$|^STM32G0C1CE$|^STM32G0C1KE$|^STM32G0C1ME$|^STM32G0C1NE$|^STM32G0C1RE$|^STM32G0C1VE$") + set(spi_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_spi_master.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_81") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_81") + list(APPEND hal_ll_def_list "STM32G0xx") + list(APPEND hal_ll_def_list "STM32G0Cxx") + list(APPEND hal_ll_def_list "STM32G0C1xx") + set(spi_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/spi_master/hal_ll_spi_master_pin_map/implementations/doc_ds_81") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_81/hal_ll_spi_master.c b/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_81/hal_ll_spi_master.c new file mode 100644 index 000000000..f4c4abcca --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_81/hal_ll_spi_master.c @@ -0,0 +1,732 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_spi_master.c + * @brief SPI Master HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_rcc.h" +#include "hal_ll_spi_master.h" +#include "hal_ll_spi_master_pin_map.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_spi_master_handle_register_t hal_ll_module_state[SPI_MODULE_COUNT] = {(handle_t *)NULL, (handle_t *)NULL, false}; + +// ------------------------------------------------------------- PRIVATE MACROS + +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_spi_master_get_module_state_address ((hal_ll_spi_master_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_spi_master_get_handle (hal_ll_spi_master_handle_register_t *)hal_ll_spi_master_get_module_state_address->hal_ll_spi_master_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_spi_master_get_base_struct(_handle) ((hal_ll_spi_master_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_spi_master_get_base_from_hal_handle ((hal_ll_spi_master_hw_specifics_map_t *)((hal_ll_spi_master_handle_register_t *)\ + (((hal_ll_spi_master_handle_register_t *)(handle))->hal_ll_spi_master_handle))->hal_ll_spi_master_handle)->base + +/*!< CR1 constants. */ +#define HAL_LL_SPI_MASTER 0x4 +#define HAL_LL_SPI_MASTER_SSI_1 8 +#define HAL_LL_SPI_MASTER_SELECTION 2 +/*!< CR2 constants. */ +#define HAL_LL_SPI_MASTER_FRXTH 0x1000ul + +#define HAL_LL_SPI_MASTER_SSOE_BIT 2 +#define HAL_LL_SPI_MASTER_SSOE 0x4 +#define HAL_LL_SPI_MASTER_SSM_ENABLE 9 +#define HAL_LL_SPI_MASTER_SSM_DISABLE 0x0000u +#define HAL_LL_SPI_MASTER_SS_ENABLE 0x10000ul +#define HAL_LL_SPI_MASTER_SS_DISABLE 0x00000ul +/*!< SR constants. */ +#define HAL_LL_SPI_MASTER_RXNE 0 +#define HAL_LL_SPI_MASTER_TXE 1 +/*!< I2SCFGR constants. */ +#define HAL_LL_SPI_MASTER_I2SMOD 11 +/*!< Enable constants. */ +#define HAL_LL_SPI_MASTER_ENABLE 6 +#define HAL_LL_SPI1_MASTER_ENABLE 12 + +#define HAL_LL_SPI2_MASTER_ENABLE 14 + +#define HAL_LL_SPI3_MASTER_ENABLE 15 + +/*!< General constants. */ +#define HAL_LL_SPI_MASTER_BAUD_RATE_MASK 3 +#define HAL_LL_SPI_MASTER_16_BIT_REG_SHIFT 16 +#define HAL_LL_SPI_MASTER_DEFAULT_BASE_ADDRESS 0xFF + +#define HAL_LL_SPI_MASTER_CLK_POLARITY 1 +#define HAL_LL_SPI_MASTER_CLK_PHASE 0 + +#define hal_ll_spi_master_get_speed(_fosc,_speed) (_speed >= _fosc/2)? (0):\ + ((_speed <= _fosc/2) && (_speed > _fosc/4))? (0):\ + ((_speed <= _fosc/4) && (_speed > _fosc/8))? (0x0008UL):\ + ((_speed <= _fosc/8) && (_speed > _fosc/16))? (0x0010UL):\ + ((_speed <= _fosc/16) && (_speed > _fosc/32))? (0x0018UL):\ + ((_speed <= _fosc/32) && (_speed > _fosc/64))? (0x0020UL):\ + ((_speed <= _fosc/64) && (_speed > _fosc/128))?(0x0028UL):\ + ((_speed <= _fosc/128)&& (_speed > _fosc/256))?(0x0030UL):(0x0038UL) + +#define hal_ll_spi_master_get_actual_speed(_fosc,_divider) (_divider == 0)?(_fosc/2):\ + (_divider == 0x0008UL)?(_fosc/4):\ + (_divider == 0x0010UL)?(_fosc/8):\ + (_divider == 0x0018UL)?(_fosc/16):\ + (_divider == 0x0020UL)?(_fosc/32):\ + (_divider == 0x0028UL)?(_fosc/64):\ + (_divider == 0x0030UL)?(_fosc/128):\ + (_divider == 0x0038UL)?(_fosc/256):(_fosc/256) + +/*!< @brief Default SPI Master bit-rate if no speed is set */ +#define HAL_LL_SPI_MASTER_SPEED_100K 100000 + +// -------------------------------------------------------------- PRIVATE TYPES + +/*!< @brief SPI register structure. */ +typedef struct { + uint32_t cr1; + uint32_t cr2; + uint32_t sr; + uint32_t dr; + uint32_t crcpr; + uint32_t rxcrcr; + uint32_t txcrcr; + uint32_t i2scfgr; + uint32_t i2spr; + +} hal_ll_spi_master_base_handle_t; + +/*!< @brief SPI Master hardware specific structure */ +typedef struct { + hal_ll_base_addr_t base; + uint8_t module_index; + hal_ll_spi_master_pins_t pins; + uint8_t dummy_data; + uint32_t speed; + uint32_t hw_actual_speed; + hal_ll_spi_master_mode_t mode; +} hal_ll_spi_master_hw_specifics_map_t; + +/*!< @brief SPI hw specific module values */ +typedef struct +{ + uint16_t pin_sck; + uint16_t pin_miso; + uint16_t pin_mosi; +} hal_ll_spi_pin_id; + +/*!< @brief SPI Master hw specific error values */ +typedef enum { + HAL_LL_SPI_MASTER_SUCCESS = 0, + HAL_LL_SPI_MASTER_WRONG_PINS, + HAL_LL_SPI_MASTER_MODULE_ERROR, + + HAL_LL_SPI_MASTER_ERROR = (-1) +} hal_ll_spi_master_err_t; + +// ------------------------------------------------------------------ VARIABLES + +/*!< @brief SPI Master hardware specific info */ +static hal_ll_spi_master_hw_specifics_map_t hal_ll_spi_master_hw_specifics_map[] = { + #ifdef SPI_MODULE_1 + {HAL_LL_SPI1_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_1), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, HAL_LL_SPI_MASTER_SPEED_100K, 0, HAL_LL_SPI_MASTER_MODE_DEFAULT}, + #endif + + #ifdef SPI_MODULE_2 + {HAL_LL_SPI2_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_2), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, HAL_LL_SPI_MASTER_SPEED_100K, 0, HAL_LL_SPI_MASTER_MODE_DEFAULT}, + #endif + + #ifdef SPI_MODULE_3 + {HAL_LL_SPI3_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_3), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, HAL_LL_SPI_MASTER_SPEED_100K, 0, HAL_LL_SPI_MASTER_MODE_DEFAULT}, + #endif + + + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, 0, 0, 0} +}; + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_spi_master_handle_register_t *low_level_handle; +static volatile hal_ll_spi_master_hw_specifics_map_t *hal_ll_spi_master_hw_specifics_map_local; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Check if pins are adequate. + * + * Checks SCK, MISO and MOSI pins the user has passed with pre-defined + * pins in SCK, MISO and MOSI maps. Take into consideration that module + * index numbers have to be the same for both pins. + * + * @param[in] sck - SCK pre-defined pin name. + * @param[in] miso - MISO pre-defined pin name. + * @param[in] mosi - MOSI pre-defined pin name. + * @param[in] *index_list - Index list address + * @return hal_ll_pin_name_t Module index based on pins. + * + * Returns pre-defined module index from pin maps, if pins + * are adequate. + */ +static hal_ll_pin_name_t hal_ll_spi_master_check_pins(hal_ll_pin_name_t sck, hal_ll_pin_name_t miso, hal_ll_pin_name_t mosi, hal_ll_spi_pin_id *index_list, hal_ll_spi_master_handle_register_t *handle_map ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_spi_master_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_spi_master_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_spi_master_hw_specifics_map_t *hal_ll_get_specifics(handle_t handle); + +/** + * @brief Enable clock for SPI Master module on hardware level. + * + * Initializes SPI Master module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] *map - Object specific context handler. + * @param[in] hal_ll_state - True(enable clock)/False(disable clock). + * @param[in] *clock_value - SPI Master baud rate value taken from a specific peripheral clock bus. + * @return None + */ +static void hal_ll_spi_master_set_clock(hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state, uint32_t *clock_value); + +/** + * @brief Sets SPI Master pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if SPI is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param[in] *map - Object specific context handler. + * @param[in] hal_ll_state - Init/De-init + */ +static void hal_ll_spi_master_alternate_functions_set_state(hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state); + +/** + * @brief Full SPI Master module initialization procedure. + * + * Initializes SPI Master module on hardware level, based on beforehand + * set configuration and module handler. Sets adequate pin alternate functions. + * Initializes module clock. + * + * @param[in] *map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static void hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_t *map); + +/** + * @brief Perform a read on the SPI Master bus. + * + * Initializes SPI Master module on hardware level, if not initialized beforehand + * and continues to perform a read operation on the bus. + * + * @param[in] *map - Object specific context handler. + * @param[in] *read_data_buffer - Pointer to data buffer. + * @param[in] read_data_length - Number of data to be read. + * @param[in] dummy_data - Data required for read procedure. + * @return hal_ll_err_t Module specific error values. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +static void hal_ll_spi_master_read_bare_metal(hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *read_data_buffer, size_t read_data_length, uint8_t dummy_data); + +/** + * @brief Perform a write on the SPI Master bus. + * + * Initializes SPI Master module on hardware level, if not initialized beforehand + * and continues to perform a write operation on the bus. + * + * @param[in] map - Object specific context handler. + * @param[in] *write_data_buffer - Pointer to data buffer. + * @param[in] write_data_length - Number of data to be written. + * @return hal_ll_err_t Module specific error values. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +static void hal_ll_spi_master_write_bare_metal(hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *write_data_buffer, size_t write_data_length); + +/** + * @brief Perform a write then read on the SPI Master bus. + * + * Initializes SPI Master module on hardware level, if not initialized beforehand + * and continues to perform a write operation on the bus. + * + * @param[in] *handle - Object specific context handler. + * @param[in] *write_data_buffer - Pointer to data buffer. + * @param[in] length_write_data - Number of data to be written. + * @param[in] *read_data_buffer - Pointer to data buffer. + * @param[in] length_read_data - Number of data to be read. + * @return hal_ll_err_t Module specific error values. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_spi_master_write_then_read(handle_t *handle, uint8_t *write_data_buffer, size_t length_write_data, uint8_t *read_data_buffer, size_t length_read_data); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * SPI SCK, MISO and MOSI pins. + * + * @param[in] module_index SPI HW module index -- 0,1,2... + * @param[in] *index_list Array with SCK, MISO and MOSI map index values + * and module number + * + * @return None + */ +static void hal_ll_spi_master_map_pins(uint8_t module_index, hal_ll_spi_pin_id *index_list); + + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS + +hal_ll_err_t hal_ll_spi_master_register_handle(hal_ll_pin_name_t sck, hal_ll_pin_name_t miso, hal_ll_pin_name_t mosi, hal_ll_spi_master_handle_register_t *handle_map, uint8_t *hal_module_id) { + + hal_ll_spi_pin_id index_list[SPI_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + uint16_t pin_check_result; + + // Check user-defined pins. + if ((pin_check_result = hal_ll_spi_master_check_pins(sck, miso, mosi, &index_list, handle_map)) == HAL_LL_PIN_NC) { + return HAL_LL_SPI_MASTER_WRONG_PINS; + }; + + // If user has come with the same SPI hardware module, and with the same pair of the pins, the pin mapping procedure + // will not have to take a place; otherwise, clear af-s, map new pins, set af-s, and set init state to false. + if ((hal_ll_spi_master_hw_specifics_map[pin_check_result].pins.sck.pin_name != sck) || + (hal_ll_spi_master_hw_specifics_map[pin_check_result].pins.miso.pin_name != miso) || + (hal_ll_spi_master_hw_specifics_map[pin_check_result].pins.mosi.pin_name != mosi) ) { + + hal_ll_spi_master_alternate_functions_set_state(&hal_ll_spi_master_hw_specifics_map[pin_check_result], false); + + hal_ll_spi_master_map_pins(pin_check_result, &index_list); + + hal_ll_spi_master_alternate_functions_set_state(&hal_ll_spi_master_hw_specifics_map[pin_check_result], true); + + handle_map[pin_check_result].init_ll_state = false; + } + + // Return id of the SPI module that is going to be used. + *hal_module_id = pin_check_result; + + // Insert current module into hal_ll_module_state map. + hal_ll_module_state[pin_check_result].hal_ll_spi_master_handle = (handle_t *)&hal_ll_spi_master_hw_specifics_map[pin_check_result].base; + + // Return the same info about module one level up ( into the HAL level ). + handle_map[pin_check_result].hal_ll_spi_master_handle = (handle_t*)&hal_ll_module_state[pin_check_result].hal_ll_spi_master_handle; + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_spi(handle_t *handle) { + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + hal_ll_spi_master_handle_register_t *hal_handle = (hal_ll_spi_master_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_spi_master_hw_specifics_map_local->module_index; + + hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_local); + + hal_ll_module_state[pin_check_result].hal_ll_spi_master_handle = (handle_t *)&hal_ll_spi_master_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +void hal_ll_spi_master_set_default_write_data(handle_t *handle, uint8_t dummy_data) { + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + if(hal_ll_spi_master_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR) { + hal_ll_spi_master_hw_specifics_map_local->dummy_data = dummy_data; + } +} + +hal_ll_err_t hal_ll_spi_master_write(handle_t *handle, uint8_t *write_data_buffer, size_t length_data) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + hal_ll_spi_master_write_bare_metal(hal_ll_spi_master_hw_specifics_map_local->base, write_data_buffer, length_data); + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_spi_master_read(handle_t *handle, uint8_t *read_data_buffer, size_t length_data) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + hal_ll_spi_master_read_bare_metal(hal_ll_spi_master_hw_specifics_map_local->base, read_data_buffer, length_data, hal_ll_spi_master_hw_specifics_map_local->dummy_data); + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_spi_master_write_then_read(handle_t *handle, uint8_t *write_data_buffer, size_t length_write_data, uint8_t *read_data_buffer, size_t length_read_data) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + hal_ll_spi_master_write_bare_metal(hal_ll_spi_master_hw_specifics_map_local->base, write_data_buffer, length_write_data); + + hal_ll_spi_master_read_bare_metal(hal_ll_spi_master_hw_specifics_map_local->base, read_data_buffer, length_read_data, hal_ll_spi_master_hw_specifics_map_local->dummy_data); + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +uint32_t hal_ll_spi_master_set_speed(handle_t *handle, uint32_t speed) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + low_level_handle->init_ll_state = false; + + // Insert user-defined baud rate into local map. + hal_ll_spi_master_hw_specifics_map_local->speed = speed; + + // Init once again, but with updated SPI Master baud rate value. + hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + // Return value of the SPI Master baud rate value. + return hal_ll_spi_master_hw_specifics_map_local->hw_actual_speed; +} + +hal_ll_err_t hal_ll_spi_master_set_mode(handle_t *handle, hal_ll_spi_master_mode_t mode) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + low_level_handle->init_ll_state = false; + + // Insert user-defined mode into local map. + hal_ll_spi_master_hw_specifics_map_local->mode = mode; + + // Init once again, but with updated SPI Master mode value. + hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +void hal_ll_spi_master_close(handle_t* handle) { + uint32_t dummy; + low_level_handle = hal_ll_spi_master_get_handle; + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + if(low_level_handle->hal_ll_spi_master_handle != NULL) { + low_level_handle->hal_ll_spi_master_handle = NULL; + low_level_handle->hal_drv_spi_master_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_spi_master_hw_specifics_map_local->mode = HAL_LL_SPI_MASTER_MODE_DEFAULT; + hal_ll_spi_master_hw_specifics_map_local->speed = HAL_LL_SPI_MASTER_SPEED_100K; + hal_ll_spi_master_hw_specifics_map_local->dummy_data = 0; + hal_ll_spi_master_hw_specifics_map_local->hw_actual_speed = 0; + + hal_ll_spi_master_set_clock(hal_ll_spi_master_hw_specifics_map_local, true, &dummy); + hal_ll_spi_master_alternate_functions_set_state(hal_ll_spi_master_hw_specifics_map_local, false); + hal_ll_spi_master_set_clock(hal_ll_spi_master_hw_specifics_map_local, false, &dummy); + + hal_ll_spi_master_hw_specifics_map_local->pins.sck.pin_name = HAL_LL_PIN_NC; + hal_ll_spi_master_hw_specifics_map_local->pins.miso.pin_name = HAL_LL_PIN_NC; + hal_ll_spi_master_hw_specifics_map_local->pins.mosi.pin_name = HAL_LL_PIN_NC; + hal_ll_spi_master_hw_specifics_map_local->pins.sck.pin_af = 0; + hal_ll_spi_master_hw_specifics_map_local->pins.miso.pin_af = 0; + hal_ll_spi_master_hw_specifics_map_local->pins.mosi.pin_af = 0; + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS + +uint8_t hal_ll_spi_master_transfer_bare_metal(hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t data_buffer) { + // Write user-defined data ( 'hal_ll_spi_master_read_bare_metal' procedure will send dummy data ). + *((volatile uint8_t *)&hal_ll_hw_reg->dr) = (uint8_t)data_buffer; // 8-bit data + + // Wait for receive buffer not empty status. + while (!(check_reg_bit( &(hal_ll_hw_reg->sr), HAL_LL_SPI_MASTER_RXNE))); + + // Return read data. + return *((volatile uint8_t *)&hal_ll_hw_reg->dr); // 8-bit data +} + +static void hal_ll_spi_master_write_bare_metal( hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *write_data_buffer, size_t write_data_length ) { + uint16_t transfer_counter = NULL; + + // Write the first data to be transmitted into the SPI_DR register. + for(transfer_counter = 0; transfer_counter < write_data_length; transfer_counter++) { + // If we are good to go ( if the tx buffer value has been shifted to the shift register ), write the data. + hal_ll_spi_master_transfer_bare_metal( hal_ll_hw_reg, write_data_buffer[transfer_counter]); + } +} + +static void hal_ll_spi_master_read_bare_metal(hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *read_data_buffer, size_t read_data_length, uint8_t dummy_data) { + uint16_t transfer_counter = NULL; + + // Read the first data to be transmitted into the SPI_DR register. + for(transfer_counter = 0; transfer_counter < read_data_length; transfer_counter++) { + // If we are good to go ( if the value from shift register has been shifted to the rx register ), read the data. + read_data_buffer[transfer_counter] = hal_ll_spi_master_transfer_bare_metal(hal_ll_hw_reg, dummy_data); + } +} + +static hal_ll_pin_name_t hal_ll_spi_master_check_pins(hal_ll_pin_name_t sck_pin, hal_ll_pin_name_t miso_pin, hal_ll_pin_name_t mosi_pin, hal_ll_spi_pin_id *index_list, hal_ll_spi_master_handle_register_t *handle_map) { + static const uint16_t sck_map_size = (sizeof(_spi_sck_map)) / (sizeof(hal_ll_spi_master_pin_map_t)); + static const uint16_t miso_map_size = (sizeof(_spi_miso_map)) / (sizeof(hal_ll_spi_master_pin_map_t)); + static const uint16_t mosi_map_size = (sizeof(_spi_mosi_map)) / (sizeof(hal_ll_spi_master_pin_map_t)); + uint8_t hal_ll_module_id = 0; + uint8_t index_counter = 0; + uint16_t miso_index; + uint16_t mosi_index; + uint16_t sck_index; + + if ( (HAL_LL_PIN_NC == sck_pin) || (HAL_LL_PIN_NC == miso_pin) || (HAL_LL_PIN_NC == mosi_pin) ) { + return HAL_LL_PIN_NC; + } + + // Check pins from the specific pin maps with the user defined pins. + for (sck_index = 0; sck_index < sck_map_size; sck_index++) { + if (_spi_sck_map[sck_index].pin == sck_pin) { + for (miso_index = 0; miso_index < miso_map_size; miso_index++) { + if (_spi_miso_map[miso_index].pin == miso_pin) { + if (_spi_sck_map[sck_index].module_index ==_spi_miso_map[miso_index].module_index) { + for (mosi_index = 0; mosi_index < mosi_map_size; mosi_index++) { + if (_spi_mosi_map[mosi_index ].pin == mosi_pin) { + if (_spi_sck_map[sck_index].module_index ==_spi_mosi_map[mosi_index].module_index) { + // Get module number + hal_ll_module_id = _spi_sck_map[ sck_index ].module_index; + + // Map pin names + index_list[hal_ll_module_id].pin_sck = sck_index; + index_list[hal_ll_module_id].pin_miso = miso_index; + index_list[hal_ll_module_id].pin_mosi = mosi_index; + + // Check if module is taken + if ( NULL == handle_map[hal_ll_module_id].hal_drv_spi_master_handle ) { + return hal_ll_module_id; + } else if ( SPI_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + } + } + } + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static void hal_ll_spi_master_map_pins(uint8_t module_index, hal_ll_spi_pin_id *index_list) { + // if every single pin is OK, insert them into this new map, and use this map in all low level functions. + hal_ll_spi_master_hw_specifics_map[module_index].pins.sck.pin_name = _spi_sck_map[index_list[module_index].pin_sck].pin; + hal_ll_spi_master_hw_specifics_map[module_index].pins.miso.pin_name = _spi_miso_map[index_list[module_index].pin_miso].pin; + hal_ll_spi_master_hw_specifics_map[module_index].pins.mosi.pin_name = _spi_mosi_map[index_list[module_index].pin_mosi].pin; + + // SCK, MISO and MOSI pins could have different alternate function settings, hence save all the AF-s. + hal_ll_spi_master_hw_specifics_map[module_index].pins.sck.pin_af = _spi_sck_map[index_list[module_index].pin_sck].af; + hal_ll_spi_master_hw_specifics_map[module_index].pins.miso.pin_af = _spi_miso_map[index_list[module_index].pin_miso].af; + hal_ll_spi_master_hw_specifics_map[module_index].pins.mosi.pin_af = _spi_mosi_map[index_list[module_index].pin_mosi].af; +} + +static hal_ll_spi_master_hw_specifics_map_t *hal_ll_get_specifics(handle_t handle) { + uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof( hal_ll_spi_master_handle_register_t)); + + static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof( hal_ll_spi_master_handle_register_t)); + + while (hal_ll_module_count--) { + if (hal_ll_spi_master_get_base_from_hal_handle == hal_ll_spi_master_hw_specifics_map[hal_ll_module_count].base) { + return &hal_ll_spi_master_hw_specifics_map[hal_ll_module_count]; + } + } + + // If NOK, return pointer to the last row of this map ( point to null pointer ). + return &hal_ll_spi_master_hw_specifics_map[hal_ll_module_error]; +} + +static void hal_ll_spi_master_set_clock(hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state, uint32_t *clock_value) { + rcc_clocks_t hal_ll_spi_clock_structure; + + RCC_GetClocksFrequency(&hal_ll_spi_clock_structure); + + switch (map->module_index) { + #if defined(SPI_MODULE_1) + case (hal_ll_spi_master_module_num(SPI_MODULE_1)): + if(hal_ll_state) { + set_reg_bit(_RCC_APBENR2, HAL_LL_SPI1_MASTER_ENABLE); + } else { + clear_reg_bit(_RCC_APBENR2, HAL_LL_SPI1_MASTER_ENABLE); + } + *clock_value = hal_ll_spi_clock_structure.pclk; + break; + #endif + + #if defined(SPI_MODULE_2) + case (hal_ll_spi_master_module_num(SPI_MODULE_2)): + if(hal_ll_state) { + set_reg_bit(_RCC_APBENR1, HAL_LL_SPI2_MASTER_ENABLE); + } else { + clear_reg_bit(_RCC_APBENR1, HAL_LL_SPI2_MASTER_ENABLE); + } + *clock_value = hal_ll_spi_clock_structure.pclk; + break; + #endif + + #if defined(SPI_MODULE_3) + case (hal_ll_spi_master_module_num(SPI_MODULE_3)): + if(hal_ll_state) { + set_reg_bit(_RCC_APBENR1, HAL_LL_SPI3_MASTER_ENABLE); + } else { + clear_reg_bit(_RCC_APBENR1, HAL_LL_SPI3_MASTER_ENABLE); + } + *clock_value = hal_ll_spi_clock_structure.pclk; + break; + #endif + + + } +} + +static void hal_ll_spi_master_alternate_functions_set_state(hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state) { + module_struct module; + uint32_t spi_config; + + if((map->pins.sck.pin_name != HAL_LL_PIN_NC) && (map->pins.miso.pin_name != HAL_LL_PIN_NC) && (map->pins.miso.pin_name != HAL_LL_PIN_NC)) { + module.pins[0] = VALUE(map->pins.sck.pin_name, map->pins.sck.pin_af); + module.pins[1] = VALUE(map->pins.miso.pin_name, map->pins.miso.pin_af); + module.pins[2] = VALUE(map->pins.mosi.pin_name, map->pins.mosi.pin_af); + module.pins[3] = GPIO_MODULE_STRUCT_END; + + spi_config = GPIO_CFG_MODE_ALT_FUNCTION | + GPIO_CFG_SPEED_HIGH | + GPIO_CFG_OTYPE_PP; + + module.configs[0] = spi_config; + module.configs[1] = spi_config; + module.configs[2] = spi_config; + module.configs[3] = GPIO_MODULE_STRUCT_END; + + module.gpio_remap = map->pins.sck.pin_af; + + hal_ll_gpio_module_struct_init(&module, hal_ll_state); + } +} + +static uint32_t hal_ll_spi_master_hw_init(hal_ll_spi_master_hw_specifics_map_t *map, uint32_t clock_value) { + uint32_t temp_speed; + + hal_ll_spi_master_base_handle_t *hal_ll_hw_reg = (hal_ll_spi_master_base_handle_t *)map->base; + + // Reset all the settings in control register. + hal_ll_hw_reg->cr1 = 0; + + // Populate appropriate register values to get appropriate data transfer baud rate prescalers. + temp_speed = hal_ll_spi_master_get_speed(clock_value, map->speed); + hal_ll_hw_reg->cr1 |= temp_speed; + + // Choose whether idle state for the clock is high level (1) or low level (0). + if (map->mode <= HAL_LL_SPI_MASTER_MODE_1) { + clear_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_CLK_POLARITY); + } else { + set_reg_bit(&( hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_CLK_POLARITY); + } + + // Choose whether transmit occurs on the transition from ACTIVE to IDLE (1), or vice versa (0). + if (map->mode == HAL_LL_SPI_MASTER_MODE_0 || map->mode == HAL_LL_SPI_MASTER_MODE_2) { + clear_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_CLK_PHASE); + } else { + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_CLK_PHASE); + } + + // Set default values for SPI Master configuration. + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_SSM_ENABLE); + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_SSI_1); + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_SELECTION); + + // Set Slave Select Output Enable bit. + set_reg_bit(&(hal_ll_hw_reg->cr2), HAL_LL_SPI_MASTER_SSOE_BIT); + + // Set FIFO reception threshold to 8-bit. + hal_ll_hw_reg->cr2 |= HAL_LL_SPI_MASTER_FRXTH; + + // Enable SPI peripheral. + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_ENABLE); + + return (hal_ll_spi_master_get_actual_speed(clock_value, temp_speed)); +} + +static void hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_t *map) { + uint32_t clock_value; + + // Enable specific clock module. + hal_ll_spi_master_set_clock (map, true, &clock_value); + + // Enable specific alternate functions. + hal_ll_spi_master_alternate_functions_set_state(map, true); + + // Finally, write user-defined settings into hardware registers. + hal_ll_spi_master_hw_init(map, clock_value); +} +// ------------------------------------------------------------------------- END + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_82/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_82/CMakeLists.cmake new file mode 100644 index 000000000..a00ea22b7 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_82/CMakeLists.cmake @@ -0,0 +1,9 @@ +if(${MCU_NAME} MATCHES "^STM32G431C6$|^STM32G431K6$|^STM32G431R6$|^STM32G431V6$|^STM32G431M6$|^STM32G431C8$|^STM32G431K8$|^STM32G431R8$|^STM32G431V8$|^STM32G431M8$|^STM32G431CB$|^STM32G431KB$|^STM32G431RB$|^STM32G431VB$|^STM32G431MB$") + set(spi_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_spi_master.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_82") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_82") + list(APPEND hal_ll_def_list "STM32G4xx") + list(APPEND hal_ll_def_list "STM32G43xx") + list(APPEND hal_ll_def_list "STM32G431xx") + set(spi_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/spi_master/hal_ll_spi_master_pin_map/implementations/doc_ds_82") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_82/hal_ll_spi_master.c b/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_82/hal_ll_spi_master.c new file mode 100644 index 000000000..36396937d --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_82/hal_ll_spi_master.c @@ -0,0 +1,722 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_spi_master.c + * @brief SPI Master HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_rcc.h" +#include "hal_ll_spi_master.h" +#include "hal_ll_spi_master_pin_map.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_spi_master_handle_register_t hal_ll_module_state[SPI_MODULE_COUNT] = {(handle_t *)NULL, (handle_t *)NULL, false}; + +// ------------------------------------------------------------- PRIVATE MACROS + +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_spi_master_get_module_state_address ((hal_ll_spi_master_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_spi_master_get_handle (hal_ll_spi_master_handle_register_t *)hal_ll_spi_master_get_module_state_address->hal_ll_spi_master_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_spi_master_get_base_struct(_handle) ((hal_ll_spi_master_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_spi_master_get_base_from_hal_handle ((hal_ll_spi_master_hw_specifics_map_t *)((hal_ll_spi_master_handle_register_t *)\ + (((hal_ll_spi_master_handle_register_t *)(handle))->hal_ll_spi_master_handle))->hal_ll_spi_master_handle)->base + +/*!< CR1 constants. */ +#define HAL_LL_SPI_MASTER 0x4 +#define HAL_LL_SPI_MASTER_SSI_1 8 +#define HAL_LL_SPI_MASTER_SELECTION 2 +/*!< CR2 constants. */ +#define HAL_LL_SPI_MASTER_FRXTH 0x1000ul + +#define HAL_LL_SPI_MASTER_SSOE_BIT 2 +#define HAL_LL_SPI_MASTER_SSOE 0x4 +#define HAL_LL_SPI_MASTER_SSM_ENABLE 9 +#define HAL_LL_SPI_MASTER_SSM_DISABLE 0x0000u +#define HAL_LL_SPI_MASTER_SS_ENABLE 0x10000ul +#define HAL_LL_SPI_MASTER_SS_DISABLE 0x00000ul +/*!< SR constants. */ +#define HAL_LL_SPI_MASTER_RXNE 0 +#define HAL_LL_SPI_MASTER_TXE 1 +/*!< I2SCFGR constants. */ +#define HAL_LL_SPI_MASTER_I2SMOD 11 +/*!< Enable constants. */ +#define HAL_LL_SPI_MASTER_ENABLE 6 +#define HAL_LL_SPI1_MASTER_ENABLE 12 + +#define HAL_LL_SPI2_MASTER_ENABLE 14 + +#define HAL_LL_SPI3_MASTER_ENABLE 15 + +/*!< General constants. */ +#define HAL_LL_SPI_MASTER_BAUD_RATE_MASK 3 +#define HAL_LL_SPI_MASTER_16_BIT_REG_SHIFT 16 +#define HAL_LL_SPI_MASTER_DEFAULT_BASE_ADDRESS 0xFF + +#define HAL_LL_SPI_MASTER_CLK_POLARITY 1 +#define HAL_LL_SPI_MASTER_CLK_PHASE 0 + +#define hal_ll_spi_master_get_speed(_fosc,_speed) (_speed >= _fosc/2)? (0):\ + ((_speed <= _fosc/2) && (_speed > _fosc/4))? (0):\ + ((_speed <= _fosc/4) && (_speed > _fosc/8))? (0x0008UL):\ + ((_speed <= _fosc/8) && (_speed > _fosc/16))? (0x0010UL):\ + ((_speed <= _fosc/16) && (_speed > _fosc/32))? (0x0018UL):\ + ((_speed <= _fosc/32) && (_speed > _fosc/64))? (0x0020UL):\ + ((_speed <= _fosc/64) && (_speed > _fosc/128))?(0x0028UL):\ + ((_speed <= _fosc/128)&& (_speed > _fosc/256))?(0x0030UL):(0x0038UL) + +#define hal_ll_spi_master_get_actual_speed(_fosc,_divider) (_divider == 0)?(_fosc/2):\ + (_divider == 0x0008UL)?(_fosc/4):\ + (_divider == 0x0010UL)?(_fosc/8):\ + (_divider == 0x0018UL)?(_fosc/16):\ + (_divider == 0x0020UL)?(_fosc/32):\ + (_divider == 0x0028UL)?(_fosc/64):\ + (_divider == 0x0030UL)?(_fosc/128):\ + (_divider == 0x0038UL)?(_fosc/256):(_fosc/256) + +/*!< @brief Default SPI Master bit-rate if no speed is set */ +#define HAL_LL_SPI_MASTER_SPEED_100K 100000 + +// -------------------------------------------------------------- PRIVATE TYPES + +/*!< @brief SPI register structure. */ +typedef struct { + uint32_t cr1; + uint32_t cr2; + uint32_t sr; + uint32_t dr; + uint32_t crcpr; + uint32_t rxcrcr; + uint32_t txcrcr; + uint32_t i2scfgr; + uint32_t i2spr; +} hal_ll_spi_master_base_handle_t; + +/*!< @brief SPI Master hardware specific structure */ +typedef struct { + hal_ll_base_addr_t base; + uint8_t module_index; + hal_ll_spi_master_pins_t pins; + uint8_t dummy_data; + uint32_t speed; + uint32_t hw_actual_speed; + hal_ll_spi_master_mode_t mode; +} hal_ll_spi_master_hw_specifics_map_t; + +/*!< @brief SPI hw specific module values */ +typedef struct +{ + uint16_t pin_sck; + uint16_t pin_miso; + uint16_t pin_mosi; +} hal_ll_spi_pin_id; + +/*!< @brief SPI Master hw specific error values */ +typedef enum { + HAL_LL_SPI_MASTER_SUCCESS = 0, + HAL_LL_SPI_MASTER_WRONG_PINS, + HAL_LL_SPI_MASTER_MODULE_ERROR, + + HAL_LL_SPI_MASTER_ERROR = (-1) +} hal_ll_spi_master_err_t; + +// ------------------------------------------------------------------ VARIABLES + +/*!< @brief SPI Master hardware specific info */ +static hal_ll_spi_master_hw_specifics_map_t hal_ll_spi_master_hw_specifics_map[] = { + #ifdef SPI_MODULE_1 + {HAL_LL_SPI1_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_1), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, HAL_LL_SPI_MASTER_SPEED_100K, 0, HAL_LL_SPI_MASTER_MODE_DEFAULT}, + #endif + #ifdef SPI_MODULE_2 + {HAL_LL_SPI2_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_2), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, HAL_LL_SPI_MASTER_SPEED_100K, 0, HAL_LL_SPI_MASTER_MODE_DEFAULT}, + #endif + #ifdef SPI_MODULE_3 + {HAL_LL_SPI3_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_3), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, HAL_LL_SPI_MASTER_SPEED_100K, 0, HAL_LL_SPI_MASTER_MODE_DEFAULT}, + #endif + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, 0, 0, 0} +}; + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_spi_master_handle_register_t *low_level_handle; +static volatile hal_ll_spi_master_hw_specifics_map_t *hal_ll_spi_master_hw_specifics_map_local; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Check if pins are adequate. + * + * Checks SCK, MISO and MOSI pins the user has passed with pre-defined + * pins in SCK, MISO and MOSI maps. Take into consideration that module + * index numbers have to be the same for both pins. + * + * @param[in] sck - SCK pre-defined pin name. + * @param[in] miso - MISO pre-defined pin name. + * @param[in] mosi - MOSI pre-defined pin name. + * @param[in] *index_list - Index list address + * @return hal_ll_pin_name_t Module index based on pins. + * + * Returns pre-defined module index from pin maps, if pins + * are adequate. + */ +static hal_ll_pin_name_t hal_ll_spi_master_check_pins(hal_ll_pin_name_t sck, hal_ll_pin_name_t miso, hal_ll_pin_name_t mosi, hal_ll_spi_pin_id *index_list, hal_ll_spi_master_handle_register_t *handle_map ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_spi_master_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_spi_master_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_spi_master_hw_specifics_map_t *hal_ll_get_specifics(handle_t handle); + +/** + * @brief Enable clock for SPI Master module on hardware level. + * + * Initializes SPI Master module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] *map - Object specific context handler. + * @param[in] hal_ll_state - True(enable clock)/False(disable clock). + * @param[in] *clock_value - SPI Master baud rate value taken from a specific peripheral clock bus. + * @return None + */ +static void hal_ll_spi_master_set_clock(hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state, uint32_t *clock_value); + +/** + * @brief Sets SPI Master pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if SPI is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param[in] *map - Object specific context handler. + * @param[in] hal_ll_state - Init/De-init + */ +static void hal_ll_spi_master_alternate_functions_set_state(hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state); + +/** + * @brief Full SPI Master module initialization procedure. + * + * Initializes SPI Master module on hardware level, based on beforehand + * set configuration and module handler. Sets adequate pin alternate functions. + * Initializes module clock. + * + * @param[in] *map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static void hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_t *map); + +/** + * @brief Perform a read on the SPI Master bus. + * + * Initializes SPI Master module on hardware level, if not initialized beforehand + * and continues to perform a read operation on the bus. + * + * @param[in] *map - Object specific context handler. + * @param[in] *read_data_buffer - Pointer to data buffer. + * @param[in] read_data_length - Number of data to be read. + * @param[in] dummy_data - Data required for read procedure. + * @return hal_ll_err_t Module specific error values. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +static void hal_ll_spi_master_read_bare_metal(hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *read_data_buffer, size_t read_data_length, uint8_t dummy_data); + +/** + * @brief Perform a write on the SPI Master bus. + * + * Initializes SPI Master module on hardware level, if not initialized beforehand + * and continues to perform a write operation on the bus. + * + * @param[in] map - Object specific context handler. + * @param[in] *write_data_buffer - Pointer to data buffer. + * @param[in] write_data_length - Number of data to be written. + * @return hal_ll_err_t Module specific error values. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +static void hal_ll_spi_master_write_bare_metal(hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *write_data_buffer, size_t write_data_length); + +/** + * @brief Perform a write then read on the SPI Master bus. + * + * Initializes SPI Master module on hardware level, if not initialized beforehand + * and continues to perform a write operation on the bus. + * + * @param[in] *handle - Object specific context handler. + * @param[in] *write_data_buffer - Pointer to data buffer. + * @param[in] length_write_data - Number of data to be written. + * @param[in] *read_data_buffer - Pointer to data buffer. + * @param[in] length_read_data - Number of data to be read. + * @return hal_ll_err_t Module specific error values. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_spi_master_write_then_read(handle_t *handle, uint8_t *write_data_buffer, size_t length_write_data, uint8_t *read_data_buffer, size_t length_read_data); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * SPI SCK, MISO and MOSI pins. + * + * @param[in] module_index SPI HW module index -- 0,1,2... + * @param[in] *index_list Array with SCK, MISO and MOSI map index values + * and module number + * + * @return None + */ +static void hal_ll_spi_master_map_pins(uint8_t module_index, hal_ll_spi_pin_id *index_list); + + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS + +hal_ll_err_t hal_ll_spi_master_register_handle(hal_ll_pin_name_t sck, hal_ll_pin_name_t miso, hal_ll_pin_name_t mosi, hal_ll_spi_master_handle_register_t *handle_map, uint8_t *hal_module_id) { + + hal_ll_spi_pin_id index_list[SPI_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + uint16_t pin_check_result; + + // Check user-defined pins. + if ((pin_check_result = hal_ll_spi_master_check_pins(sck, miso, mosi, &index_list, handle_map)) == HAL_LL_PIN_NC) { + return HAL_LL_SPI_MASTER_WRONG_PINS; + }; + + // If user has come with the same SPI hardware module, and with the same pair of the pins, the pin mapping procedure + // will not have to take a place; otherwise, clear af-s, map new pins, set af-s, and set init state to false. + if ((hal_ll_spi_master_hw_specifics_map[pin_check_result].pins.sck.pin_name != sck) || + (hal_ll_spi_master_hw_specifics_map[pin_check_result].pins.miso.pin_name != miso) || + (hal_ll_spi_master_hw_specifics_map[pin_check_result].pins.mosi.pin_name != mosi) ) { + + hal_ll_spi_master_alternate_functions_set_state(&hal_ll_spi_master_hw_specifics_map[pin_check_result], false); + + hal_ll_spi_master_map_pins(pin_check_result, &index_list); + + hal_ll_spi_master_alternate_functions_set_state(&hal_ll_spi_master_hw_specifics_map[pin_check_result], true); + + handle_map[pin_check_result].init_ll_state = false; + } + + // Return id of the SPI module that is going to be used. + *hal_module_id = pin_check_result; + + // Insert current module into hal_ll_module_state map. + hal_ll_module_state[pin_check_result].hal_ll_spi_master_handle = (handle_t *)&hal_ll_spi_master_hw_specifics_map[pin_check_result].base; + + // Return the same info about module one level up ( into the HAL level ). + handle_map[pin_check_result].hal_ll_spi_master_handle = (handle_t*)&hal_ll_module_state[pin_check_result].hal_ll_spi_master_handle; + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_spi(handle_t *handle) { + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + hal_ll_spi_master_handle_register_t *hal_handle = (hal_ll_spi_master_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_spi_master_hw_specifics_map_local->module_index; + + hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_local); + + hal_ll_module_state[pin_check_result].hal_ll_spi_master_handle = (handle_t *)&hal_ll_spi_master_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +void hal_ll_spi_master_set_default_write_data(handle_t *handle, uint8_t dummy_data) { + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + if(hal_ll_spi_master_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR) { + hal_ll_spi_master_hw_specifics_map_local->dummy_data = dummy_data; + } +} + +hal_ll_err_t hal_ll_spi_master_write(handle_t *handle, uint8_t *write_data_buffer, size_t length_data) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + hal_ll_spi_master_write_bare_metal(hal_ll_spi_master_hw_specifics_map_local->base, write_data_buffer, length_data); + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_spi_master_read(handle_t *handle, uint8_t *read_data_buffer, size_t length_data) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + hal_ll_spi_master_read_bare_metal(hal_ll_spi_master_hw_specifics_map_local->base, read_data_buffer, length_data, hal_ll_spi_master_hw_specifics_map_local->dummy_data); + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_spi_master_write_then_read(handle_t *handle, uint8_t *write_data_buffer, size_t length_write_data, uint8_t *read_data_buffer, size_t length_read_data) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + hal_ll_spi_master_write_bare_metal(hal_ll_spi_master_hw_specifics_map_local->base, write_data_buffer, length_write_data); + + hal_ll_spi_master_read_bare_metal(hal_ll_spi_master_hw_specifics_map_local->base, read_data_buffer, length_read_data, hal_ll_spi_master_hw_specifics_map_local->dummy_data); + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +uint32_t hal_ll_spi_master_set_speed(handle_t *handle, uint32_t speed) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + low_level_handle->init_ll_state = false; + + // Insert user-defined baud rate into local map. + hal_ll_spi_master_hw_specifics_map_local->speed = speed; + + // Init once again, but with updated SPI Master baud rate value. + hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + // Return value of the SPI Master baud rate value. + return hal_ll_spi_master_hw_specifics_map_local->hw_actual_speed; +} + +hal_ll_err_t hal_ll_spi_master_set_mode(handle_t *handle, hal_ll_spi_master_mode_t mode) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + low_level_handle->init_ll_state = false; + + // Insert user-defined mode into local map. + hal_ll_spi_master_hw_specifics_map_local->mode = mode; + + // Init once again, but with updated SPI Master mode value. + hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +void hal_ll_spi_master_close(handle_t* handle) { + uint32_t dummy; + low_level_handle = hal_ll_spi_master_get_handle; + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + if(low_level_handle->hal_ll_spi_master_handle != NULL) { + low_level_handle->hal_ll_spi_master_handle = NULL; + low_level_handle->hal_drv_spi_master_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_spi_master_hw_specifics_map_local->mode = HAL_LL_SPI_MASTER_MODE_DEFAULT; + hal_ll_spi_master_hw_specifics_map_local->speed = HAL_LL_SPI_MASTER_SPEED_100K; + hal_ll_spi_master_hw_specifics_map_local->dummy_data = 0; + hal_ll_spi_master_hw_specifics_map_local->hw_actual_speed = 0; + + hal_ll_spi_master_set_clock(hal_ll_spi_master_hw_specifics_map_local, true, &dummy); + hal_ll_spi_master_alternate_functions_set_state(hal_ll_spi_master_hw_specifics_map_local, false); + hal_ll_spi_master_set_clock(hal_ll_spi_master_hw_specifics_map_local, false, &dummy); + + hal_ll_spi_master_hw_specifics_map_local->pins.sck.pin_name = HAL_LL_PIN_NC; + hal_ll_spi_master_hw_specifics_map_local->pins.miso.pin_name = HAL_LL_PIN_NC; + hal_ll_spi_master_hw_specifics_map_local->pins.mosi.pin_name = HAL_LL_PIN_NC; + hal_ll_spi_master_hw_specifics_map_local->pins.sck.pin_af = 0; + hal_ll_spi_master_hw_specifics_map_local->pins.miso.pin_af = 0; + hal_ll_spi_master_hw_specifics_map_local->pins.mosi.pin_af = 0; + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS + +uint8_t hal_ll_spi_master_transfer_bare_metal(hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t data_buffer) { + // Write user-defined data ( 'hal_ll_spi_master_read_bare_metal' procedure will send dummy data ). + *((volatile uint8_t *)&hal_ll_hw_reg->dr) = (uint8_t)data_buffer; // 8-bit data + + // Wait for receive buffer not empty status. + while (!(check_reg_bit( &(hal_ll_hw_reg->sr), HAL_LL_SPI_MASTER_RXNE))); + + // Return read data. + return *((volatile uint8_t *)&hal_ll_hw_reg->dr); // 8-bit data +} + +static void hal_ll_spi_master_write_bare_metal( hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *write_data_buffer, size_t write_data_length ) { + uint16_t transfer_counter = NULL; + + // Write the first data to be transmitted into the SPI_DR register. + for(transfer_counter = 0; transfer_counter < write_data_length; transfer_counter++) { + // If we are good to go ( if the tx buffer value has been shifted to the shift register ), write the data. + hal_ll_spi_master_transfer_bare_metal( hal_ll_hw_reg, write_data_buffer[transfer_counter]); + } +} + +static void hal_ll_spi_master_read_bare_metal(hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *read_data_buffer, size_t read_data_length, uint8_t dummy_data) { + uint16_t transfer_counter = NULL; + + // Read the first data to be transmitted into the SPI_DR register. + for(transfer_counter = 0; transfer_counter < read_data_length; transfer_counter++) { + // If we are good to go ( if the value from shift register has been shifted to the rx register ), read the data. + read_data_buffer[transfer_counter] = hal_ll_spi_master_transfer_bare_metal(hal_ll_hw_reg, dummy_data); + } +} + +static hal_ll_pin_name_t hal_ll_spi_master_check_pins(hal_ll_pin_name_t sck_pin, hal_ll_pin_name_t miso_pin, hal_ll_pin_name_t mosi_pin, hal_ll_spi_pin_id *index_list, hal_ll_spi_master_handle_register_t *handle_map) { + static const uint16_t sck_map_size = (sizeof(_spi_sck_map)) / (sizeof(hal_ll_spi_master_pin_map_t)); + static const uint16_t miso_map_size = (sizeof(_spi_miso_map)) / (sizeof(hal_ll_spi_master_pin_map_t)); + static const uint16_t mosi_map_size = (sizeof(_spi_mosi_map)) / (sizeof(hal_ll_spi_master_pin_map_t)); + uint8_t hal_ll_module_id = 0; + uint8_t index_counter = 0; + uint16_t miso_index; + uint16_t mosi_index; + uint16_t sck_index; + + if ( (HAL_LL_PIN_NC == sck_pin) || (HAL_LL_PIN_NC == miso_pin) || (HAL_LL_PIN_NC == mosi_pin) ) { + return HAL_LL_PIN_NC; + } + + // Check pins from the specific pin maps with the user defined pins. + for (sck_index = 0; sck_index < sck_map_size; sck_index++) { + if (_spi_sck_map[sck_index].pin == sck_pin) { + for (miso_index = 0; miso_index < miso_map_size; miso_index++) { + if (_spi_miso_map[miso_index].pin == miso_pin) { + if (_spi_sck_map[sck_index].module_index ==_spi_miso_map[miso_index].module_index) { + for (mosi_index = 0; mosi_index < mosi_map_size; mosi_index++) { + if (_spi_mosi_map[mosi_index ].pin == mosi_pin) { + if (_spi_sck_map[sck_index].module_index ==_spi_mosi_map[mosi_index].module_index) { + // Get module number + hal_ll_module_id = _spi_sck_map[ sck_index ].module_index; + + // Map pin names + index_list[hal_ll_module_id].pin_sck = sck_index; + index_list[hal_ll_module_id].pin_miso = miso_index; + index_list[hal_ll_module_id].pin_mosi = mosi_index; + + // Check if module is taken + if ( NULL == handle_map[hal_ll_module_id].hal_drv_spi_master_handle ) { + return hal_ll_module_id; + } else if ( SPI_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + } + } + } + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static void hal_ll_spi_master_map_pins(uint8_t module_index, hal_ll_spi_pin_id *index_list) { + // if every single pin is OK, insert them into this new map, and use this map in all low level functions. + hal_ll_spi_master_hw_specifics_map[module_index].pins.sck.pin_name = _spi_sck_map[index_list[module_index].pin_sck].pin; + hal_ll_spi_master_hw_specifics_map[module_index].pins.miso.pin_name = _spi_miso_map[index_list[module_index].pin_miso].pin; + hal_ll_spi_master_hw_specifics_map[module_index].pins.mosi.pin_name = _spi_mosi_map[index_list[module_index].pin_mosi].pin; + + // SCK, MISO and MOSI pins could have different alternate function settings, hence save all the AF-s. + hal_ll_spi_master_hw_specifics_map[module_index].pins.sck.pin_af = _spi_sck_map[index_list[module_index].pin_sck].af; + hal_ll_spi_master_hw_specifics_map[module_index].pins.miso.pin_af = _spi_miso_map[index_list[module_index].pin_miso].af; + hal_ll_spi_master_hw_specifics_map[module_index].pins.mosi.pin_af = _spi_mosi_map[index_list[module_index].pin_mosi].af; +} + +static hal_ll_spi_master_hw_specifics_map_t *hal_ll_get_specifics(handle_t handle) { + uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof( hal_ll_spi_master_handle_register_t)); + + static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof( hal_ll_spi_master_handle_register_t)); + + while (hal_ll_module_count--) { + if (hal_ll_spi_master_get_base_from_hal_handle == hal_ll_spi_master_hw_specifics_map[hal_ll_module_count].base) { + return &hal_ll_spi_master_hw_specifics_map[hal_ll_module_count]; + } + } + + // If NOK, return pointer to the last row of this map ( point to null pointer ). + return &hal_ll_spi_master_hw_specifics_map[hal_ll_module_error]; +} + +static void hal_ll_spi_master_set_clock(hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state, uint32_t *clock_value) { + rcc_clocks_t hal_ll_spi_clock_structure; + + RCC_GetClocksFrequency(&hal_ll_spi_clock_structure); + + switch (map->module_index) { + #if defined(SPI_MODULE_1) + case (hal_ll_spi_master_module_num(SPI_MODULE_1)): + if(hal_ll_state) { + set_reg_bit(_RCC_APB2ENR, HAL_LL_SPI1_MASTER_ENABLE); + } else { + clear_reg_bit(_RCC_APB2ENR, HAL_LL_SPI1_MASTER_ENABLE); + } + *clock_value = hal_ll_spi_clock_structure.pclk2; + break; + #endif + #if defined(SPI_MODULE_2) + case (hal_ll_spi_master_module_num(SPI_MODULE_2)): + if(hal_ll_state) { + set_reg_bit(_RCC_APB1ENR1, HAL_LL_SPI2_MASTER_ENABLE); + } else { + clear_reg_bit(_RCC_APB1ENR1, HAL_LL_SPI2_MASTER_ENABLE); + } + *clock_value = hal_ll_spi_clock_structure.pclk1; + break; + #endif + #if defined(SPI_MODULE_3) + case (hal_ll_spi_master_module_num(SPI_MODULE_3)): + if(hal_ll_state) { + set_reg_bit(_RCC_APB1ENR1, HAL_LL_SPI3_MASTER_ENABLE); + } else { + clear_reg_bit(_RCC_APB1ENR1, HAL_LL_SPI3_MASTER_ENABLE); + } + *clock_value = hal_ll_spi_clock_structure.pclk1; + break; + #endif + } +} + +static void hal_ll_spi_master_alternate_functions_set_state(hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state) { + module_struct module; + uint32_t spi_config; + + if((map->pins.sck.pin_name != HAL_LL_PIN_NC) && (map->pins.miso.pin_name != HAL_LL_PIN_NC) && (map->pins.miso.pin_name != HAL_LL_PIN_NC)) { + module.pins[0] = VALUE(map->pins.sck.pin_name, map->pins.sck.pin_af); + module.pins[1] = VALUE(map->pins.miso.pin_name, map->pins.miso.pin_af); + module.pins[2] = VALUE(map->pins.mosi.pin_name, map->pins.mosi.pin_af); + module.pins[3] = GPIO_MODULE_STRUCT_END; + + spi_config = GPIO_CFG_MODE_ALT_FUNCTION | + GPIO_CFG_SPEED_HIGH | + GPIO_CFG_OTYPE_PP; + + module.configs[0] = spi_config; + module.configs[1] = spi_config; + module.configs[2] = spi_config; + module.configs[3] = GPIO_MODULE_STRUCT_END; + + module.gpio_remap = map->pins.sck.pin_af; + + hal_ll_gpio_module_struct_init(&module, hal_ll_state); + } +} + +static uint32_t hal_ll_spi_master_hw_init(hal_ll_spi_master_hw_specifics_map_t *map, uint32_t clock_value) { + uint32_t temp_speed; + + hal_ll_spi_master_base_handle_t *hal_ll_hw_reg = (hal_ll_spi_master_base_handle_t *)map->base; + + // Reset all the settings in control register. + hal_ll_hw_reg->cr1 = 0; + + // Populate appropriate register values to get appropriate data transfer baud rate prescalers. + temp_speed = hal_ll_spi_master_get_speed(clock_value, map->speed); + hal_ll_hw_reg->cr1 |= temp_speed; + + // Choose whether idle state for the clock is high level (1) or low level (0). + if (map->mode <= HAL_LL_SPI_MASTER_MODE_1) { + clear_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_CLK_POLARITY); + } else { + set_reg_bit(&( hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_CLK_POLARITY); + } + + // Choose whether transmit occurs on the transition from ACTIVE to IDLE (1), or vice versa (0). + if (map->mode == HAL_LL_SPI_MASTER_MODE_0 || map->mode == HAL_LL_SPI_MASTER_MODE_2) { + clear_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_CLK_PHASE); + } else { + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_CLK_PHASE); + } + + // Set default values for SPI Master configuration. + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_SSM_ENABLE); + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_SSI_1); + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_SELECTION); + + // Set Slave Select Output Enable bit. + set_reg_bit(&(hal_ll_hw_reg->cr2), HAL_LL_SPI_MASTER_SSOE_BIT); + + // Set FIFO reception threshold to 8-bit. + hal_ll_hw_reg->cr2 |= HAL_LL_SPI_MASTER_FRXTH; + + // Enable SPI peripheral. + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_ENABLE); + + return (hal_ll_spi_master_get_actual_speed(clock_value, temp_speed)); +} + +static void hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_t *map) { + uint32_t clock_value; + + // Enable specific clock module. + hal_ll_spi_master_set_clock (map, true, &clock_value); + + // Enable specific alternate functions. + hal_ll_spi_master_alternate_functions_set_state(map, true); + + // Finally, write user-defined settings into hardware registers. + hal_ll_spi_master_hw_init(map, clock_value); +} +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_83/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_83/CMakeLists.cmake new file mode 100644 index 000000000..82d6fb096 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_83/CMakeLists.cmake @@ -0,0 +1,9 @@ +if(${MCU_NAME} MATCHES "^STM32G441CB$|^STM32G441KB$|^STM32G441RB$|^STM32G441MB$|^STM32G441VB$") + set(spi_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_spi_master.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_83") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_83") + list(APPEND hal_ll_def_list "STM32G4xx") + list(APPEND hal_ll_def_list "STM32G44xx") + list(APPEND hal_ll_def_list "STM32G441xx") + set(spi_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/spi_master/hal_ll_spi_master_pin_map/implementations/doc_ds_83") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_83/hal_ll_spi_master.c b/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_83/hal_ll_spi_master.c new file mode 100644 index 000000000..557d57519 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_83/hal_ll_spi_master.c @@ -0,0 +1,732 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_spi_master.c + * @brief SPI Master HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_rcc.h" +#include "hal_ll_spi_master.h" +#include "hal_ll_spi_master_pin_map.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_spi_master_handle_register_t hal_ll_module_state[SPI_MODULE_COUNT] = {(handle_t *)NULL, (handle_t *)NULL, false}; + +// ------------------------------------------------------------- PRIVATE MACROS + +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_spi_master_get_module_state_address ((hal_ll_spi_master_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_spi_master_get_handle (hal_ll_spi_master_handle_register_t *)hal_ll_spi_master_get_module_state_address->hal_ll_spi_master_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_spi_master_get_base_struct(_handle) ((hal_ll_spi_master_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_spi_master_get_base_from_hal_handle ((hal_ll_spi_master_hw_specifics_map_t *)((hal_ll_spi_master_handle_register_t *)\ + (((hal_ll_spi_master_handle_register_t *)(handle))->hal_ll_spi_master_handle))->hal_ll_spi_master_handle)->base + +/*!< CR1 constants. */ +#define HAL_LL_SPI_MASTER 0x4 +#define HAL_LL_SPI_MASTER_SSI_1 8 +#define HAL_LL_SPI_MASTER_SELECTION 2 +/*!< CR2 constants. */ +#define HAL_LL_SPI_MASTER_FRXTH 0x1000ul + +#define HAL_LL_SPI_MASTER_SSOE_BIT 2 +#define HAL_LL_SPI_MASTER_SSOE 0x4 +#define HAL_LL_SPI_MASTER_SSM_ENABLE 9 +#define HAL_LL_SPI_MASTER_SSM_DISABLE 0x0000u +#define HAL_LL_SPI_MASTER_SS_ENABLE 0x10000ul +#define HAL_LL_SPI_MASTER_SS_DISABLE 0x00000ul +/*!< SR constants. */ +#define HAL_LL_SPI_MASTER_RXNE 0 +#define HAL_LL_SPI_MASTER_TXE 1 +/*!< I2SCFGR constants. */ +#define HAL_LL_SPI_MASTER_I2SMOD 11 +/*!< Enable constants. */ +#define HAL_LL_SPI_MASTER_ENABLE 6 +#define HAL_LL_SPI1_MASTER_ENABLE 12 + +#define HAL_LL_SPI2_MASTER_ENABLE 14 + +#define HAL_LL_SPI3_MASTER_ENABLE 15 + +/*!< General constants. */ +#define HAL_LL_SPI_MASTER_BAUD_RATE_MASK 3 +#define HAL_LL_SPI_MASTER_16_BIT_REG_SHIFT 16 +#define HAL_LL_SPI_MASTER_DEFAULT_BASE_ADDRESS 0xFF + +#define HAL_LL_SPI_MASTER_CLK_POLARITY 1 +#define HAL_LL_SPI_MASTER_CLK_PHASE 0 + +#define hal_ll_spi_master_get_speed(_fosc,_speed) (_speed >= _fosc/2)? (0):\ + ((_speed <= _fosc/2) && (_speed > _fosc/4))? (0):\ + ((_speed <= _fosc/4) && (_speed > _fosc/8))? (0x0008UL):\ + ((_speed <= _fosc/8) && (_speed > _fosc/16))? (0x0010UL):\ + ((_speed <= _fosc/16) && (_speed > _fosc/32))? (0x0018UL):\ + ((_speed <= _fosc/32) && (_speed > _fosc/64))? (0x0020UL):\ + ((_speed <= _fosc/64) && (_speed > _fosc/128))?(0x0028UL):\ + ((_speed <= _fosc/128)&& (_speed > _fosc/256))?(0x0030UL):(0x0038UL) + +#define hal_ll_spi_master_get_actual_speed(_fosc,_divider) (_divider == 0)?(_fosc/2):\ + (_divider == 0x0008UL)?(_fosc/4):\ + (_divider == 0x0010UL)?(_fosc/8):\ + (_divider == 0x0018UL)?(_fosc/16):\ + (_divider == 0x0020UL)?(_fosc/32):\ + (_divider == 0x0028UL)?(_fosc/64):\ + (_divider == 0x0030UL)?(_fosc/128):\ + (_divider == 0x0038UL)?(_fosc/256):(_fosc/256) + +/*!< @brief Default SPI Master bit-rate if no speed is set */ +#define HAL_LL_SPI_MASTER_SPEED_100K 100000 + +// -------------------------------------------------------------- PRIVATE TYPES + +/*!< @brief SPI register structure. */ +typedef struct { + uint32_t cr1; + uint32_t cr2; + uint32_t sr; + uint32_t dr; + uint32_t crcpr; + uint32_t rxcrcr; + uint32_t txcrcr; + uint32_t i2scfgr; + uint32_t i2spr; + +} hal_ll_spi_master_base_handle_t; + +/*!< @brief SPI Master hardware specific structure */ +typedef struct { + hal_ll_base_addr_t base; + uint8_t module_index; + hal_ll_spi_master_pins_t pins; + uint8_t dummy_data; + uint32_t speed; + uint32_t hw_actual_speed; + hal_ll_spi_master_mode_t mode; +} hal_ll_spi_master_hw_specifics_map_t; + +/*!< @brief SPI hw specific module values */ +typedef struct +{ + uint16_t pin_sck; + uint16_t pin_miso; + uint16_t pin_mosi; +} hal_ll_spi_pin_id; + +/*!< @brief SPI Master hw specific error values */ +typedef enum { + HAL_LL_SPI_MASTER_SUCCESS = 0, + HAL_LL_SPI_MASTER_WRONG_PINS, + HAL_LL_SPI_MASTER_MODULE_ERROR, + + HAL_LL_SPI_MASTER_ERROR = (-1) +} hal_ll_spi_master_err_t; + +// ------------------------------------------------------------------ VARIABLES + +/*!< @brief SPI Master hardware specific info */ +static hal_ll_spi_master_hw_specifics_map_t hal_ll_spi_master_hw_specifics_map[] = { + #ifdef SPI_MODULE_1 + {HAL_LL_SPI1_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_1), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, HAL_LL_SPI_MASTER_SPEED_100K, 0, HAL_LL_SPI_MASTER_MODE_DEFAULT}, + #endif + + #ifdef SPI_MODULE_2 + {HAL_LL_SPI2_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_2), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, HAL_LL_SPI_MASTER_SPEED_100K, 0, HAL_LL_SPI_MASTER_MODE_DEFAULT}, + #endif + + #ifdef SPI_MODULE_3 + {HAL_LL_SPI3_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_3), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, HAL_LL_SPI_MASTER_SPEED_100K, 0, HAL_LL_SPI_MASTER_MODE_DEFAULT}, + #endif + + + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, 0, 0, 0} +}; + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_spi_master_handle_register_t *low_level_handle; +static volatile hal_ll_spi_master_hw_specifics_map_t *hal_ll_spi_master_hw_specifics_map_local; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Check if pins are adequate. + * + * Checks SCK, MISO and MOSI pins the user has passed with pre-defined + * pins in SCK, MISO and MOSI maps. Take into consideration that module + * index numbers have to be the same for both pins. + * + * @param[in] sck - SCK pre-defined pin name. + * @param[in] miso - MISO pre-defined pin name. + * @param[in] mosi - MOSI pre-defined pin name. + * @param[in] *index_list - Index list address + * @return hal_ll_pin_name_t Module index based on pins. + * + * Returns pre-defined module index from pin maps, if pins + * are adequate. + */ +static hal_ll_pin_name_t hal_ll_spi_master_check_pins(hal_ll_pin_name_t sck, hal_ll_pin_name_t miso, hal_ll_pin_name_t mosi, hal_ll_spi_pin_id *index_list, hal_ll_spi_master_handle_register_t *handle_map ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_spi_master_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_spi_master_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_spi_master_hw_specifics_map_t *hal_ll_get_specifics(handle_t handle); + +/** + * @brief Enable clock for SPI Master module on hardware level. + * + * Initializes SPI Master module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] *map - Object specific context handler. + * @param[in] hal_ll_state - True(enable clock)/False(disable clock). + * @param[in] *clock_value - SPI Master baud rate value taken from a specific peripheral clock bus. + * @return None + */ +static void hal_ll_spi_master_set_clock(hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state, uint32_t *clock_value); + +/** + * @brief Sets SPI Master pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if SPI is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param[in] *map - Object specific context handler. + * @param[in] hal_ll_state - Init/De-init + */ +static void hal_ll_spi_master_alternate_functions_set_state(hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state); + +/** + * @brief Full SPI Master module initialization procedure. + * + * Initializes SPI Master module on hardware level, based on beforehand + * set configuration and module handler. Sets adequate pin alternate functions. + * Initializes module clock. + * + * @param[in] *map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static void hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_t *map); + +/** + * @brief Perform a read on the SPI Master bus. + * + * Initializes SPI Master module on hardware level, if not initialized beforehand + * and continues to perform a read operation on the bus. + * + * @param[in] *map - Object specific context handler. + * @param[in] *read_data_buffer - Pointer to data buffer. + * @param[in] read_data_length - Number of data to be read. + * @param[in] dummy_data - Data required for read procedure. + * @return hal_ll_err_t Module specific error values. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +static void hal_ll_spi_master_read_bare_metal(hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *read_data_buffer, size_t read_data_length, uint8_t dummy_data); + +/** + * @brief Perform a write on the SPI Master bus. + * + * Initializes SPI Master module on hardware level, if not initialized beforehand + * and continues to perform a write operation on the bus. + * + * @param[in] map - Object specific context handler. + * @param[in] *write_data_buffer - Pointer to data buffer. + * @param[in] write_data_length - Number of data to be written. + * @return hal_ll_err_t Module specific error values. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +static void hal_ll_spi_master_write_bare_metal(hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *write_data_buffer, size_t write_data_length); + +/** + * @brief Perform a write then read on the SPI Master bus. + * + * Initializes SPI Master module on hardware level, if not initialized beforehand + * and continues to perform a write operation on the bus. + * + * @param[in] *handle - Object specific context handler. + * @param[in] *write_data_buffer - Pointer to data buffer. + * @param[in] length_write_data - Number of data to be written. + * @param[in] *read_data_buffer - Pointer to data buffer. + * @param[in] length_read_data - Number of data to be read. + * @return hal_ll_err_t Module specific error values. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_spi_master_write_then_read(handle_t *handle, uint8_t *write_data_buffer, size_t length_write_data, uint8_t *read_data_buffer, size_t length_read_data); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * SPI SCK, MISO and MOSI pins. + * + * @param[in] module_index SPI HW module index -- 0,1,2... + * @param[in] *index_list Array with SCK, MISO and MOSI map index values + * and module number + * + * @return None + */ +static void hal_ll_spi_master_map_pins(uint8_t module_index, hal_ll_spi_pin_id *index_list); + + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS + +hal_ll_err_t hal_ll_spi_master_register_handle(hal_ll_pin_name_t sck, hal_ll_pin_name_t miso, hal_ll_pin_name_t mosi, hal_ll_spi_master_handle_register_t *handle_map, uint8_t *hal_module_id) { + + hal_ll_spi_pin_id index_list[SPI_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + uint16_t pin_check_result; + + // Check user-defined pins. + if ((pin_check_result = hal_ll_spi_master_check_pins(sck, miso, mosi, &index_list, handle_map)) == HAL_LL_PIN_NC) { + return HAL_LL_SPI_MASTER_WRONG_PINS; + }; + + // If user has come with the same SPI hardware module, and with the same pair of the pins, the pin mapping procedure + // will not have to take a place; otherwise, clear af-s, map new pins, set af-s, and set init state to false. + if ((hal_ll_spi_master_hw_specifics_map[pin_check_result].pins.sck.pin_name != sck) || + (hal_ll_spi_master_hw_specifics_map[pin_check_result].pins.miso.pin_name != miso) || + (hal_ll_spi_master_hw_specifics_map[pin_check_result].pins.mosi.pin_name != mosi) ) { + + hal_ll_spi_master_alternate_functions_set_state(&hal_ll_spi_master_hw_specifics_map[pin_check_result], false); + + hal_ll_spi_master_map_pins(pin_check_result, &index_list); + + hal_ll_spi_master_alternate_functions_set_state(&hal_ll_spi_master_hw_specifics_map[pin_check_result], true); + + handle_map[pin_check_result].init_ll_state = false; + } + + // Return id of the SPI module that is going to be used. + *hal_module_id = pin_check_result; + + // Insert current module into hal_ll_module_state map. + hal_ll_module_state[pin_check_result].hal_ll_spi_master_handle = (handle_t *)&hal_ll_spi_master_hw_specifics_map[pin_check_result].base; + + // Return the same info about module one level up ( into the HAL level ). + handle_map[pin_check_result].hal_ll_spi_master_handle = (handle_t*)&hal_ll_module_state[pin_check_result].hal_ll_spi_master_handle; + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_spi(handle_t *handle) { + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + hal_ll_spi_master_handle_register_t *hal_handle = (hal_ll_spi_master_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_spi_master_hw_specifics_map_local->module_index; + + hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_local); + + hal_ll_module_state[pin_check_result].hal_ll_spi_master_handle = (handle_t *)&hal_ll_spi_master_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +void hal_ll_spi_master_set_default_write_data(handle_t *handle, uint8_t dummy_data) { + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + if(hal_ll_spi_master_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR) { + hal_ll_spi_master_hw_specifics_map_local->dummy_data = dummy_data; + } +} + +hal_ll_err_t hal_ll_spi_master_write(handle_t *handle, uint8_t *write_data_buffer, size_t length_data) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + hal_ll_spi_master_write_bare_metal(hal_ll_spi_master_hw_specifics_map_local->base, write_data_buffer, length_data); + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_spi_master_read(handle_t *handle, uint8_t *read_data_buffer, size_t length_data) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + hal_ll_spi_master_read_bare_metal(hal_ll_spi_master_hw_specifics_map_local->base, read_data_buffer, length_data, hal_ll_spi_master_hw_specifics_map_local->dummy_data); + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_spi_master_write_then_read(handle_t *handle, uint8_t *write_data_buffer, size_t length_write_data, uint8_t *read_data_buffer, size_t length_read_data) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + hal_ll_spi_master_write_bare_metal(hal_ll_spi_master_hw_specifics_map_local->base, write_data_buffer, length_write_data); + + hal_ll_spi_master_read_bare_metal(hal_ll_spi_master_hw_specifics_map_local->base, read_data_buffer, length_read_data, hal_ll_spi_master_hw_specifics_map_local->dummy_data); + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +uint32_t hal_ll_spi_master_set_speed(handle_t *handle, uint32_t speed) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + low_level_handle->init_ll_state = false; + + // Insert user-defined baud rate into local map. + hal_ll_spi_master_hw_specifics_map_local->speed = speed; + + // Init once again, but with updated SPI Master baud rate value. + hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + // Return value of the SPI Master baud rate value. + return hal_ll_spi_master_hw_specifics_map_local->hw_actual_speed; +} + +hal_ll_err_t hal_ll_spi_master_set_mode(handle_t *handle, hal_ll_spi_master_mode_t mode) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + low_level_handle->init_ll_state = false; + + // Insert user-defined mode into local map. + hal_ll_spi_master_hw_specifics_map_local->mode = mode; + + // Init once again, but with updated SPI Master mode value. + hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +void hal_ll_spi_master_close(handle_t* handle) { + uint32_t dummy; + low_level_handle = hal_ll_spi_master_get_handle; + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + if(low_level_handle->hal_ll_spi_master_handle != NULL) { + low_level_handle->hal_ll_spi_master_handle = NULL; + low_level_handle->hal_drv_spi_master_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_spi_master_hw_specifics_map_local->mode = HAL_LL_SPI_MASTER_MODE_DEFAULT; + hal_ll_spi_master_hw_specifics_map_local->speed = HAL_LL_SPI_MASTER_SPEED_100K; + hal_ll_spi_master_hw_specifics_map_local->dummy_data = 0; + hal_ll_spi_master_hw_specifics_map_local->hw_actual_speed = 0; + + hal_ll_spi_master_set_clock(hal_ll_spi_master_hw_specifics_map_local, true, &dummy); + hal_ll_spi_master_alternate_functions_set_state(hal_ll_spi_master_hw_specifics_map_local, false); + hal_ll_spi_master_set_clock(hal_ll_spi_master_hw_specifics_map_local, false, &dummy); + + hal_ll_spi_master_hw_specifics_map_local->pins.sck.pin_name = HAL_LL_PIN_NC; + hal_ll_spi_master_hw_specifics_map_local->pins.miso.pin_name = HAL_LL_PIN_NC; + hal_ll_spi_master_hw_specifics_map_local->pins.mosi.pin_name = HAL_LL_PIN_NC; + hal_ll_spi_master_hw_specifics_map_local->pins.sck.pin_af = 0; + hal_ll_spi_master_hw_specifics_map_local->pins.miso.pin_af = 0; + hal_ll_spi_master_hw_specifics_map_local->pins.mosi.pin_af = 0; + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS + +uint8_t hal_ll_spi_master_transfer_bare_metal(hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t data_buffer) { + // Write user-defined data ( 'hal_ll_spi_master_read_bare_metal' procedure will send dummy data ). + *((volatile uint8_t *)&hal_ll_hw_reg->dr) = (uint8_t)data_buffer; // 8-bit data + + // Wait for receive buffer not empty status. + while (!(check_reg_bit( &(hal_ll_hw_reg->sr), HAL_LL_SPI_MASTER_RXNE))); + + // Return read data. + return *((volatile uint8_t *)&hal_ll_hw_reg->dr); // 8-bit data +} + +static void hal_ll_spi_master_write_bare_metal( hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *write_data_buffer, size_t write_data_length ) { + uint16_t transfer_counter = NULL; + + // Write the first data to be transmitted into the SPI_DR register. + for(transfer_counter = 0; transfer_counter < write_data_length; transfer_counter++) { + // If we are good to go ( if the tx buffer value has been shifted to the shift register ), write the data. + hal_ll_spi_master_transfer_bare_metal( hal_ll_hw_reg, write_data_buffer[transfer_counter]); + } +} + +static void hal_ll_spi_master_read_bare_metal(hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *read_data_buffer, size_t read_data_length, uint8_t dummy_data) { + uint16_t transfer_counter = NULL; + + // Read the first data to be transmitted into the SPI_DR register. + for(transfer_counter = 0; transfer_counter < read_data_length; transfer_counter++) { + // If we are good to go ( if the value from shift register has been shifted to the rx register ), read the data. + read_data_buffer[transfer_counter] = hal_ll_spi_master_transfer_bare_metal(hal_ll_hw_reg, dummy_data); + } +} + +static hal_ll_pin_name_t hal_ll_spi_master_check_pins(hal_ll_pin_name_t sck_pin, hal_ll_pin_name_t miso_pin, hal_ll_pin_name_t mosi_pin, hal_ll_spi_pin_id *index_list, hal_ll_spi_master_handle_register_t *handle_map) { + static const uint16_t sck_map_size = (sizeof(_spi_sck_map)) / (sizeof(hal_ll_spi_master_pin_map_t)); + static const uint16_t miso_map_size = (sizeof(_spi_miso_map)) / (sizeof(hal_ll_spi_master_pin_map_t)); + static const uint16_t mosi_map_size = (sizeof(_spi_mosi_map)) / (sizeof(hal_ll_spi_master_pin_map_t)); + uint8_t hal_ll_module_id = 0; + uint8_t index_counter = 0; + uint16_t miso_index; + uint16_t mosi_index; + uint16_t sck_index; + + if ( (HAL_LL_PIN_NC == sck_pin) || (HAL_LL_PIN_NC == miso_pin) || (HAL_LL_PIN_NC == mosi_pin) ) { + return HAL_LL_PIN_NC; + } + + // Check pins from the specific pin maps with the user defined pins. + for (sck_index = 0; sck_index < sck_map_size; sck_index++) { + if (_spi_sck_map[sck_index].pin == sck_pin) { + for (miso_index = 0; miso_index < miso_map_size; miso_index++) { + if (_spi_miso_map[miso_index].pin == miso_pin) { + if (_spi_sck_map[sck_index].module_index ==_spi_miso_map[miso_index].module_index) { + for (mosi_index = 0; mosi_index < mosi_map_size; mosi_index++) { + if (_spi_mosi_map[mosi_index ].pin == mosi_pin) { + if (_spi_sck_map[sck_index].module_index ==_spi_mosi_map[mosi_index].module_index) { + // Get module number + hal_ll_module_id = _spi_sck_map[ sck_index ].module_index; + + // Map pin names + index_list[hal_ll_module_id].pin_sck = sck_index; + index_list[hal_ll_module_id].pin_miso = miso_index; + index_list[hal_ll_module_id].pin_mosi = mosi_index; + + // Check if module is taken + if ( NULL == handle_map[hal_ll_module_id].hal_drv_spi_master_handle ) { + return hal_ll_module_id; + } else if ( SPI_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + } + } + } + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static void hal_ll_spi_master_map_pins(uint8_t module_index, hal_ll_spi_pin_id *index_list) { + // if every single pin is OK, insert them into this new map, and use this map in all low level functions. + hal_ll_spi_master_hw_specifics_map[module_index].pins.sck.pin_name = _spi_sck_map[index_list[module_index].pin_sck].pin; + hal_ll_spi_master_hw_specifics_map[module_index].pins.miso.pin_name = _spi_miso_map[index_list[module_index].pin_miso].pin; + hal_ll_spi_master_hw_specifics_map[module_index].pins.mosi.pin_name = _spi_mosi_map[index_list[module_index].pin_mosi].pin; + + // SCK, MISO and MOSI pins could have different alternate function settings, hence save all the AF-s. + hal_ll_spi_master_hw_specifics_map[module_index].pins.sck.pin_af = _spi_sck_map[index_list[module_index].pin_sck].af; + hal_ll_spi_master_hw_specifics_map[module_index].pins.miso.pin_af = _spi_miso_map[index_list[module_index].pin_miso].af; + hal_ll_spi_master_hw_specifics_map[module_index].pins.mosi.pin_af = _spi_mosi_map[index_list[module_index].pin_mosi].af; +} + +static hal_ll_spi_master_hw_specifics_map_t *hal_ll_get_specifics(handle_t handle) { + uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof( hal_ll_spi_master_handle_register_t)); + + static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof( hal_ll_spi_master_handle_register_t)); + + while (hal_ll_module_count--) { + if (hal_ll_spi_master_get_base_from_hal_handle == hal_ll_spi_master_hw_specifics_map[hal_ll_module_count].base) { + return &hal_ll_spi_master_hw_specifics_map[hal_ll_module_count]; + } + } + + // If NOK, return pointer to the last row of this map ( point to null pointer ). + return &hal_ll_spi_master_hw_specifics_map[hal_ll_module_error]; +} + +static void hal_ll_spi_master_set_clock(hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state, uint32_t *clock_value) { + rcc_clocks_t hal_ll_spi_clock_structure; + + RCC_GetClocksFrequency(&hal_ll_spi_clock_structure); + + switch (map->module_index) { + #if defined(SPI_MODULE_1) + case (hal_ll_spi_master_module_num(SPI_MODULE_1)): + if(hal_ll_state) { + set_reg_bit(_RCC_APB2ENR, HAL_LL_SPI1_MASTER_ENABLE); + } else { + clear_reg_bit(_RCC_APB2ENR, HAL_LL_SPI1_MASTER_ENABLE); + } + *clock_value = hal_ll_spi_clock_structure.pclk2; + break; + #endif + + #if defined(SPI_MODULE_2) + case (hal_ll_spi_master_module_num(SPI_MODULE_2)): + if(hal_ll_state) { + set_reg_bit(_RCC_APB1ENR1, HAL_LL_SPI2_MASTER_ENABLE); + } else { + clear_reg_bit(_RCC_APB1ENR1, HAL_LL_SPI2_MASTER_ENABLE); + } + *clock_value = hal_ll_spi_clock_structure.pclk1; + break; + #endif + + #if defined(SPI_MODULE_3) + case (hal_ll_spi_master_module_num(SPI_MODULE_3)): + if(hal_ll_state) { + set_reg_bit(_RCC_APB1ENR1, HAL_LL_SPI3_MASTER_ENABLE); + } else { + clear_reg_bit(_RCC_APB1ENR1, HAL_LL_SPI3_MASTER_ENABLE); + } + *clock_value = hal_ll_spi_clock_structure.pclk1; + break; + #endif + + + } +} + +static void hal_ll_spi_master_alternate_functions_set_state(hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state) { + module_struct module; + uint32_t spi_config; + + if((map->pins.sck.pin_name != HAL_LL_PIN_NC) && (map->pins.miso.pin_name != HAL_LL_PIN_NC) && (map->pins.miso.pin_name != HAL_LL_PIN_NC)) { + module.pins[0] = VALUE(map->pins.sck.pin_name, map->pins.sck.pin_af); + module.pins[1] = VALUE(map->pins.miso.pin_name, map->pins.miso.pin_af); + module.pins[2] = VALUE(map->pins.mosi.pin_name, map->pins.mosi.pin_af); + module.pins[3] = GPIO_MODULE_STRUCT_END; + + spi_config = GPIO_CFG_MODE_ALT_FUNCTION | + GPIO_CFG_SPEED_HIGH | + GPIO_CFG_OTYPE_PP; + + module.configs[0] = spi_config; + module.configs[1] = spi_config; + module.configs[2] = spi_config; + module.configs[3] = GPIO_MODULE_STRUCT_END; + + module.gpio_remap = map->pins.sck.pin_af; + + hal_ll_gpio_module_struct_init(&module, hal_ll_state); + } +} + +static uint32_t hal_ll_spi_master_hw_init(hal_ll_spi_master_hw_specifics_map_t *map, uint32_t clock_value) { + uint32_t temp_speed; + + hal_ll_spi_master_base_handle_t *hal_ll_hw_reg = (hal_ll_spi_master_base_handle_t *)map->base; + + // Reset all the settings in control register. + hal_ll_hw_reg->cr1 = 0; + + // Populate appropriate register values to get appropriate data transfer baud rate prescalers. + temp_speed = hal_ll_spi_master_get_speed(clock_value, map->speed); + hal_ll_hw_reg->cr1 |= temp_speed; + + // Choose whether idle state for the clock is high level (1) or low level (0). + if (map->mode <= HAL_LL_SPI_MASTER_MODE_1) { + clear_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_CLK_POLARITY); + } else { + set_reg_bit(&( hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_CLK_POLARITY); + } + + // Choose whether transmit occurs on the transition from ACTIVE to IDLE (1), or vice versa (0). + if (map->mode == HAL_LL_SPI_MASTER_MODE_0 || map->mode == HAL_LL_SPI_MASTER_MODE_2) { + clear_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_CLK_PHASE); + } else { + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_CLK_PHASE); + } + + // Set default values for SPI Master configuration. + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_SSM_ENABLE); + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_SSI_1); + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_SELECTION); + + // Set Slave Select Output Enable bit. + set_reg_bit(&(hal_ll_hw_reg->cr2), HAL_LL_SPI_MASTER_SSOE_BIT); + + // Set FIFO reception threshold to 8-bit. + hal_ll_hw_reg->cr2 |= HAL_LL_SPI_MASTER_FRXTH; + + // Enable SPI peripheral. + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_ENABLE); + + return (hal_ll_spi_master_get_actual_speed(clock_value, temp_speed)); +} + +static void hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_t *map) { + uint32_t clock_value; + + // Enable specific clock module. + hal_ll_spi_master_set_clock (map, true, &clock_value); + + // Enable specific alternate functions. + hal_ll_spi_master_alternate_functions_set_state(map, true); + + // Finally, write user-defined settings into hardware registers. + hal_ll_spi_master_hw_init(map, clock_value); +} +// ------------------------------------------------------------------------- END + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_84/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_84/CMakeLists.cmake new file mode 100644 index 000000000..7770791ae --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_84/CMakeLists.cmake @@ -0,0 +1,9 @@ +if(${MCU_NAME} MATCHES "^STM32G473CB$|^STM32G473MB$|^STM32G473PB$|^STM32G473RB$|^STM32G473VB$|^STM32G473QB$|^STM32G473CC$|^STM32G473MC$|^STM32G473PC$|^STM32G473RC$|^STM32G473VC$|^STM32G473QC$|^STM32G473CE$|^STM32G473ME$|^STM32G473PE$|^STM32G473RE$|^STM32G473VE$|^STM32G473QE$") + set(spi_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_spi_master.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_84") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_84") + list(APPEND hal_ll_def_list "STM32G4xx") + list(APPEND hal_ll_def_list "STM32G47xx") + list(APPEND hal_ll_def_list "STM32G473xx") + set(spi_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/spi_master/hal_ll_spi_master_pin_map/implementations/doc_ds_84") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_84/hal_ll_spi_master.c b/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_84/hal_ll_spi_master.c new file mode 100644 index 000000000..aabcbbc5d --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_84/hal_ll_spi_master.c @@ -0,0 +1,749 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_spi_master.c + * @brief SPI Master HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_rcc.h" +#include "hal_ll_spi_master.h" +#include "hal_ll_spi_master_pin_map.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_spi_master_handle_register_t hal_ll_module_state[SPI_MODULE_COUNT] = {(handle_t *)NULL, (handle_t *)NULL, false}; + +// ------------------------------------------------------------- PRIVATE MACROS + +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_spi_master_get_module_state_address ((hal_ll_spi_master_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_spi_master_get_handle (hal_ll_spi_master_handle_register_t *)hal_ll_spi_master_get_module_state_address->hal_ll_spi_master_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_spi_master_get_base_struct(_handle) ((hal_ll_spi_master_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_spi_master_get_base_from_hal_handle ((hal_ll_spi_master_hw_specifics_map_t *)((hal_ll_spi_master_handle_register_t *)\ + (((hal_ll_spi_master_handle_register_t *)(handle))->hal_ll_spi_master_handle))->hal_ll_spi_master_handle)->base + +/*!< CR1 constants. */ +#define HAL_LL_SPI_MASTER 0x4 +#define HAL_LL_SPI_MASTER_SSI_1 8 +#define HAL_LL_SPI_MASTER_SELECTION 2 +/*!< CR2 constants. */ +#define HAL_LL_SPI_MASTER_FRXTH 0x1000ul + +#define HAL_LL_SPI_MASTER_SSOE_BIT 2 +#define HAL_LL_SPI_MASTER_SSOE 0x4 +#define HAL_LL_SPI_MASTER_SSM_ENABLE 9 +#define HAL_LL_SPI_MASTER_SSM_DISABLE 0x0000u +#define HAL_LL_SPI_MASTER_SS_ENABLE 0x10000ul +#define HAL_LL_SPI_MASTER_SS_DISABLE 0x00000ul +/*!< SR constants. */ +#define HAL_LL_SPI_MASTER_RXNE 0 +#define HAL_LL_SPI_MASTER_TXE 1 +/*!< I2SCFGR constants. */ +#define HAL_LL_SPI_MASTER_I2SMOD 11 +/*!< Enable constants. */ +#define HAL_LL_SPI_MASTER_ENABLE 6 +#define HAL_LL_SPI1_MASTER_ENABLE 12 + +#define HAL_LL_SPI2_MASTER_ENABLE 14 + +#define HAL_LL_SPI3_MASTER_ENABLE 15 + +#define HAL_LL_SPI4_MASTER_ENABLE 15 + +/*!< General constants. */ +#define HAL_LL_SPI_MASTER_BAUD_RATE_MASK 3 +#define HAL_LL_SPI_MASTER_16_BIT_REG_SHIFT 16 +#define HAL_LL_SPI_MASTER_DEFAULT_BASE_ADDRESS 0xFF + +#define HAL_LL_SPI_MASTER_CLK_POLARITY 1 +#define HAL_LL_SPI_MASTER_CLK_PHASE 0 + +#define hal_ll_spi_master_get_speed(_fosc,_speed) (_speed >= _fosc/2)? (0):\ + ((_speed <= _fosc/2) && (_speed > _fosc/4))? (0):\ + ((_speed <= _fosc/4) && (_speed > _fosc/8))? (0x0008UL):\ + ((_speed <= _fosc/8) && (_speed > _fosc/16))? (0x0010UL):\ + ((_speed <= _fosc/16) && (_speed > _fosc/32))? (0x0018UL):\ + ((_speed <= _fosc/32) && (_speed > _fosc/64))? (0x0020UL):\ + ((_speed <= _fosc/64) && (_speed > _fosc/128))?(0x0028UL):\ + ((_speed <= _fosc/128)&& (_speed > _fosc/256))?(0x0030UL):(0x0038UL) + +#define hal_ll_spi_master_get_actual_speed(_fosc,_divider) (_divider == 0)?(_fosc/2):\ + (_divider == 0x0008UL)?(_fosc/4):\ + (_divider == 0x0010UL)?(_fosc/8):\ + (_divider == 0x0018UL)?(_fosc/16):\ + (_divider == 0x0020UL)?(_fosc/32):\ + (_divider == 0x0028UL)?(_fosc/64):\ + (_divider == 0x0030UL)?(_fosc/128):\ + (_divider == 0x0038UL)?(_fosc/256):(_fosc/256) + +/*!< @brief Default SPI Master bit-rate if no speed is set */ +#define HAL_LL_SPI_MASTER_SPEED_100K 100000 + +// -------------------------------------------------------------- PRIVATE TYPES + +/*!< @brief SPI register structure. */ +typedef struct { + uint32_t cr1; + uint32_t cr2; + uint32_t sr; + uint32_t dr; + uint32_t crcpr; + uint32_t rxcrcr; + uint32_t txcrcr; + uint32_t i2scfgr; + uint32_t i2spr; + +} hal_ll_spi_master_base_handle_t; + +/*!< @brief SPI Master hardware specific structure */ +typedef struct { + hal_ll_base_addr_t base; + uint8_t module_index; + hal_ll_spi_master_pins_t pins; + uint8_t dummy_data; + uint32_t speed; + uint32_t hw_actual_speed; + hal_ll_spi_master_mode_t mode; +} hal_ll_spi_master_hw_specifics_map_t; + +/*!< @brief SPI hw specific module values */ +typedef struct +{ + uint16_t pin_sck; + uint16_t pin_miso; + uint16_t pin_mosi; +} hal_ll_spi_pin_id; + +/*!< @brief SPI Master hw specific error values */ +typedef enum { + HAL_LL_SPI_MASTER_SUCCESS = 0, + HAL_LL_SPI_MASTER_WRONG_PINS, + HAL_LL_SPI_MASTER_MODULE_ERROR, + + HAL_LL_SPI_MASTER_ERROR = (-1) +} hal_ll_spi_master_err_t; + +// ------------------------------------------------------------------ VARIABLES + +/*!< @brief SPI Master hardware specific info */ +static hal_ll_spi_master_hw_specifics_map_t hal_ll_spi_master_hw_specifics_map[] = { + #ifdef SPI_MODULE_1 + {HAL_LL_SPI1_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_1), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, HAL_LL_SPI_MASTER_SPEED_100K, 0, HAL_LL_SPI_MASTER_MODE_DEFAULT}, + #endif + + #ifdef SPI_MODULE_2 + {HAL_LL_SPI2_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_2), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, HAL_LL_SPI_MASTER_SPEED_100K, 0, HAL_LL_SPI_MASTER_MODE_DEFAULT}, + #endif + + #ifdef SPI_MODULE_3 + {HAL_LL_SPI3_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_3), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, HAL_LL_SPI_MASTER_SPEED_100K, 0, HAL_LL_SPI_MASTER_MODE_DEFAULT}, + #endif + + #ifdef SPI_MODULE_4 + {HAL_LL_SPI4_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_4), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, HAL_LL_SPI_MASTER_SPEED_100K, 0, HAL_LL_SPI_MASTER_MODE_DEFAULT}, + #endif + + + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, 0, 0, 0} +}; + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_spi_master_handle_register_t *low_level_handle; +static volatile hal_ll_spi_master_hw_specifics_map_t *hal_ll_spi_master_hw_specifics_map_local; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Check if pins are adequate. + * + * Checks SCK, MISO and MOSI pins the user has passed with pre-defined + * pins in SCK, MISO and MOSI maps. Take into consideration that module + * index numbers have to be the same for both pins. + * + * @param[in] sck - SCK pre-defined pin name. + * @param[in] miso - MISO pre-defined pin name. + * @param[in] mosi - MOSI pre-defined pin name. + * @param[in] *index_list - Index list address + * @return hal_ll_pin_name_t Module index based on pins. + * + * Returns pre-defined module index from pin maps, if pins + * are adequate. + */ +static hal_ll_pin_name_t hal_ll_spi_master_check_pins(hal_ll_pin_name_t sck, hal_ll_pin_name_t miso, hal_ll_pin_name_t mosi, hal_ll_spi_pin_id *index_list, hal_ll_spi_master_handle_register_t *handle_map ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_spi_master_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_spi_master_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_spi_master_hw_specifics_map_t *hal_ll_get_specifics(handle_t handle); + +/** + * @brief Enable clock for SPI Master module on hardware level. + * + * Initializes SPI Master module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] *map - Object specific context handler. + * @param[in] hal_ll_state - True(enable clock)/False(disable clock). + * @param[in] *clock_value - SPI Master baud rate value taken from a specific peripheral clock bus. + * @return None + */ +static void hal_ll_spi_master_set_clock(hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state, uint32_t *clock_value); + +/** + * @brief Sets SPI Master pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if SPI is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param[in] *map - Object specific context handler. + * @param[in] hal_ll_state - Init/De-init + */ +static void hal_ll_spi_master_alternate_functions_set_state(hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state); + +/** + * @brief Full SPI Master module initialization procedure. + * + * Initializes SPI Master module on hardware level, based on beforehand + * set configuration and module handler. Sets adequate pin alternate functions. + * Initializes module clock. + * + * @param[in] *map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static void hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_t *map); + +/** + * @brief Perform a read on the SPI Master bus. + * + * Initializes SPI Master module on hardware level, if not initialized beforehand + * and continues to perform a read operation on the bus. + * + * @param[in] *map - Object specific context handler. + * @param[in] *read_data_buffer - Pointer to data buffer. + * @param[in] read_data_length - Number of data to be read. + * @param[in] dummy_data - Data required for read procedure. + * @return hal_ll_err_t Module specific error values. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +static void hal_ll_spi_master_read_bare_metal(hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *read_data_buffer, size_t read_data_length, uint8_t dummy_data); + +/** + * @brief Perform a write on the SPI Master bus. + * + * Initializes SPI Master module on hardware level, if not initialized beforehand + * and continues to perform a write operation on the bus. + * + * @param[in] map - Object specific context handler. + * @param[in] *write_data_buffer - Pointer to data buffer. + * @param[in] write_data_length - Number of data to be written. + * @return hal_ll_err_t Module specific error values. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +static void hal_ll_spi_master_write_bare_metal(hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *write_data_buffer, size_t write_data_length); + +/** + * @brief Perform a write then read on the SPI Master bus. + * + * Initializes SPI Master module on hardware level, if not initialized beforehand + * and continues to perform a write operation on the bus. + * + * @param[in] *handle - Object specific context handler. + * @param[in] *write_data_buffer - Pointer to data buffer. + * @param[in] length_write_data - Number of data to be written. + * @param[in] *read_data_buffer - Pointer to data buffer. + * @param[in] length_read_data - Number of data to be read. + * @return hal_ll_err_t Module specific error values. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_spi_master_write_then_read(handle_t *handle, uint8_t *write_data_buffer, size_t length_write_data, uint8_t *read_data_buffer, size_t length_read_data); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * SPI SCK, MISO and MOSI pins. + * + * @param[in] module_index SPI HW module index -- 0,1,2... + * @param[in] *index_list Array with SCK, MISO and MOSI map index values + * and module number + * + * @return None + */ +static void hal_ll_spi_master_map_pins(uint8_t module_index, hal_ll_spi_pin_id *index_list); + + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS + +hal_ll_err_t hal_ll_spi_master_register_handle(hal_ll_pin_name_t sck, hal_ll_pin_name_t miso, hal_ll_pin_name_t mosi, hal_ll_spi_master_handle_register_t *handle_map, uint8_t *hal_module_id) { + + hal_ll_spi_pin_id index_list[SPI_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + uint16_t pin_check_result; + + // Check user-defined pins. + if ((pin_check_result = hal_ll_spi_master_check_pins(sck, miso, mosi, &index_list, handle_map)) == HAL_LL_PIN_NC) { + return HAL_LL_SPI_MASTER_WRONG_PINS; + }; + + // If user has come with the same SPI hardware module, and with the same pair of the pins, the pin mapping procedure + // will not have to take a place; otherwise, clear af-s, map new pins, set af-s, and set init state to false. + if ((hal_ll_spi_master_hw_specifics_map[pin_check_result].pins.sck.pin_name != sck) || + (hal_ll_spi_master_hw_specifics_map[pin_check_result].pins.miso.pin_name != miso) || + (hal_ll_spi_master_hw_specifics_map[pin_check_result].pins.mosi.pin_name != mosi) ) { + + hal_ll_spi_master_alternate_functions_set_state(&hal_ll_spi_master_hw_specifics_map[pin_check_result], false); + + hal_ll_spi_master_map_pins(pin_check_result, &index_list); + + hal_ll_spi_master_alternate_functions_set_state(&hal_ll_spi_master_hw_specifics_map[pin_check_result], true); + + handle_map[pin_check_result].init_ll_state = false; + } + + // Return id of the SPI module that is going to be used. + *hal_module_id = pin_check_result; + + // Insert current module into hal_ll_module_state map. + hal_ll_module_state[pin_check_result].hal_ll_spi_master_handle = (handle_t *)&hal_ll_spi_master_hw_specifics_map[pin_check_result].base; + + // Return the same info about module one level up ( into the HAL level ). + handle_map[pin_check_result].hal_ll_spi_master_handle = (handle_t*)&hal_ll_module_state[pin_check_result].hal_ll_spi_master_handle; + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_spi(handle_t *handle) { + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + hal_ll_spi_master_handle_register_t *hal_handle = (hal_ll_spi_master_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_spi_master_hw_specifics_map_local->module_index; + + hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_local); + + hal_ll_module_state[pin_check_result].hal_ll_spi_master_handle = (handle_t *)&hal_ll_spi_master_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +void hal_ll_spi_master_set_default_write_data(handle_t *handle, uint8_t dummy_data) { + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + if(hal_ll_spi_master_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR) { + hal_ll_spi_master_hw_specifics_map_local->dummy_data = dummy_data; + } +} + +hal_ll_err_t hal_ll_spi_master_write(handle_t *handle, uint8_t *write_data_buffer, size_t length_data) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + hal_ll_spi_master_write_bare_metal(hal_ll_spi_master_hw_specifics_map_local->base, write_data_buffer, length_data); + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_spi_master_read(handle_t *handle, uint8_t *read_data_buffer, size_t length_data) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + hal_ll_spi_master_read_bare_metal(hal_ll_spi_master_hw_specifics_map_local->base, read_data_buffer, length_data, hal_ll_spi_master_hw_specifics_map_local->dummy_data); + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_spi_master_write_then_read(handle_t *handle, uint8_t *write_data_buffer, size_t length_write_data, uint8_t *read_data_buffer, size_t length_read_data) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + hal_ll_spi_master_write_bare_metal(hal_ll_spi_master_hw_specifics_map_local->base, write_data_buffer, length_write_data); + + hal_ll_spi_master_read_bare_metal(hal_ll_spi_master_hw_specifics_map_local->base, read_data_buffer, length_read_data, hal_ll_spi_master_hw_specifics_map_local->dummy_data); + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +uint32_t hal_ll_spi_master_set_speed(handle_t *handle, uint32_t speed) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + low_level_handle->init_ll_state = false; + + // Insert user-defined baud rate into local map. + hal_ll_spi_master_hw_specifics_map_local->speed = speed; + + // Init once again, but with updated SPI Master baud rate value. + hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + // Return value of the SPI Master baud rate value. + return hal_ll_spi_master_hw_specifics_map_local->hw_actual_speed; +} + +hal_ll_err_t hal_ll_spi_master_set_mode(handle_t *handle, hal_ll_spi_master_mode_t mode) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + low_level_handle->init_ll_state = false; + + // Insert user-defined mode into local map. + hal_ll_spi_master_hw_specifics_map_local->mode = mode; + + // Init once again, but with updated SPI Master mode value. + hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +void hal_ll_spi_master_close(handle_t* handle) { + uint32_t dummy; + low_level_handle = hal_ll_spi_master_get_handle; + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + if(low_level_handle->hal_ll_spi_master_handle != NULL) { + low_level_handle->hal_ll_spi_master_handle = NULL; + low_level_handle->hal_drv_spi_master_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_spi_master_hw_specifics_map_local->mode = HAL_LL_SPI_MASTER_MODE_DEFAULT; + hal_ll_spi_master_hw_specifics_map_local->speed = HAL_LL_SPI_MASTER_SPEED_100K; + hal_ll_spi_master_hw_specifics_map_local->dummy_data = 0; + hal_ll_spi_master_hw_specifics_map_local->hw_actual_speed = 0; + + hal_ll_spi_master_set_clock(hal_ll_spi_master_hw_specifics_map_local, true, &dummy); + hal_ll_spi_master_alternate_functions_set_state(hal_ll_spi_master_hw_specifics_map_local, false); + hal_ll_spi_master_set_clock(hal_ll_spi_master_hw_specifics_map_local, false, &dummy); + + hal_ll_spi_master_hw_specifics_map_local->pins.sck.pin_name = HAL_LL_PIN_NC; + hal_ll_spi_master_hw_specifics_map_local->pins.miso.pin_name = HAL_LL_PIN_NC; + hal_ll_spi_master_hw_specifics_map_local->pins.mosi.pin_name = HAL_LL_PIN_NC; + hal_ll_spi_master_hw_specifics_map_local->pins.sck.pin_af = 0; + hal_ll_spi_master_hw_specifics_map_local->pins.miso.pin_af = 0; + hal_ll_spi_master_hw_specifics_map_local->pins.mosi.pin_af = 0; + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS + +uint8_t hal_ll_spi_master_transfer_bare_metal(hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t data_buffer) { + // Write user-defined data ( 'hal_ll_spi_master_read_bare_metal' procedure will send dummy data ). + *((volatile uint8_t *)&hal_ll_hw_reg->dr) = (uint8_t)data_buffer; // 8-bit data + + // Wait for receive buffer not empty status. + while (!(check_reg_bit( &(hal_ll_hw_reg->sr), HAL_LL_SPI_MASTER_RXNE))); + + // Return read data. + return *((volatile uint8_t *)&hal_ll_hw_reg->dr); // 8-bit data +} + +static void hal_ll_spi_master_write_bare_metal( hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *write_data_buffer, size_t write_data_length ) { + uint16_t transfer_counter = NULL; + + // Write the first data to be transmitted into the SPI_DR register. + for(transfer_counter = 0; transfer_counter < write_data_length; transfer_counter++) { + // If we are good to go ( if the tx buffer value has been shifted to the shift register ), write the data. + hal_ll_spi_master_transfer_bare_metal( hal_ll_hw_reg, write_data_buffer[transfer_counter]); + } +} + +static void hal_ll_spi_master_read_bare_metal(hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *read_data_buffer, size_t read_data_length, uint8_t dummy_data) { + uint16_t transfer_counter = NULL; + + // Read the first data to be transmitted into the SPI_DR register. + for(transfer_counter = 0; transfer_counter < read_data_length; transfer_counter++) { + // If we are good to go ( if the value from shift register has been shifted to the rx register ), read the data. + read_data_buffer[transfer_counter] = hal_ll_spi_master_transfer_bare_metal(hal_ll_hw_reg, dummy_data); + } +} + +static hal_ll_pin_name_t hal_ll_spi_master_check_pins(hal_ll_pin_name_t sck_pin, hal_ll_pin_name_t miso_pin, hal_ll_pin_name_t mosi_pin, hal_ll_spi_pin_id *index_list, hal_ll_spi_master_handle_register_t *handle_map) { + static const uint16_t sck_map_size = (sizeof(_spi_sck_map)) / (sizeof(hal_ll_spi_master_pin_map_t)); + static const uint16_t miso_map_size = (sizeof(_spi_miso_map)) / (sizeof(hal_ll_spi_master_pin_map_t)); + static const uint16_t mosi_map_size = (sizeof(_spi_mosi_map)) / (sizeof(hal_ll_spi_master_pin_map_t)); + uint8_t hal_ll_module_id = 0; + uint8_t index_counter = 0; + uint16_t miso_index; + uint16_t mosi_index; + uint16_t sck_index; + + if ( (HAL_LL_PIN_NC == sck_pin) || (HAL_LL_PIN_NC == miso_pin) || (HAL_LL_PIN_NC == mosi_pin) ) { + return HAL_LL_PIN_NC; + } + + // Check pins from the specific pin maps with the user defined pins. + for (sck_index = 0; sck_index < sck_map_size; sck_index++) { + if (_spi_sck_map[sck_index].pin == sck_pin) { + for (miso_index = 0; miso_index < miso_map_size; miso_index++) { + if (_spi_miso_map[miso_index].pin == miso_pin) { + if (_spi_sck_map[sck_index].module_index ==_spi_miso_map[miso_index].module_index) { + for (mosi_index = 0; mosi_index < mosi_map_size; mosi_index++) { + if (_spi_mosi_map[mosi_index ].pin == mosi_pin) { + if (_spi_sck_map[sck_index].module_index ==_spi_mosi_map[mosi_index].module_index) { + // Get module number + hal_ll_module_id = _spi_sck_map[ sck_index ].module_index; + + // Map pin names + index_list[hal_ll_module_id].pin_sck = sck_index; + index_list[hal_ll_module_id].pin_miso = miso_index; + index_list[hal_ll_module_id].pin_mosi = mosi_index; + + // Check if module is taken + if ( NULL == handle_map[hal_ll_module_id].hal_drv_spi_master_handle ) { + return hal_ll_module_id; + } else if ( SPI_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + } + } + } + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static void hal_ll_spi_master_map_pins(uint8_t module_index, hal_ll_spi_pin_id *index_list) { + // if every single pin is OK, insert them into this new map, and use this map in all low level functions. + hal_ll_spi_master_hw_specifics_map[module_index].pins.sck.pin_name = _spi_sck_map[index_list[module_index].pin_sck].pin; + hal_ll_spi_master_hw_specifics_map[module_index].pins.miso.pin_name = _spi_miso_map[index_list[module_index].pin_miso].pin; + hal_ll_spi_master_hw_specifics_map[module_index].pins.mosi.pin_name = _spi_mosi_map[index_list[module_index].pin_mosi].pin; + + // SCK, MISO and MOSI pins could have different alternate function settings, hence save all the AF-s. + hal_ll_spi_master_hw_specifics_map[module_index].pins.sck.pin_af = _spi_sck_map[index_list[module_index].pin_sck].af; + hal_ll_spi_master_hw_specifics_map[module_index].pins.miso.pin_af = _spi_miso_map[index_list[module_index].pin_miso].af; + hal_ll_spi_master_hw_specifics_map[module_index].pins.mosi.pin_af = _spi_mosi_map[index_list[module_index].pin_mosi].af; +} + +static hal_ll_spi_master_hw_specifics_map_t *hal_ll_get_specifics(handle_t handle) { + uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof( hal_ll_spi_master_handle_register_t)); + + static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof( hal_ll_spi_master_handle_register_t)); + + while (hal_ll_module_count--) { + if (hal_ll_spi_master_get_base_from_hal_handle == hal_ll_spi_master_hw_specifics_map[hal_ll_module_count].base) { + return &hal_ll_spi_master_hw_specifics_map[hal_ll_module_count]; + } + } + + // If NOK, return pointer to the last row of this map ( point to null pointer ). + return &hal_ll_spi_master_hw_specifics_map[hal_ll_module_error]; +} + +static void hal_ll_spi_master_set_clock(hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state, uint32_t *clock_value) { + rcc_clocks_t hal_ll_spi_clock_structure; + + RCC_GetClocksFrequency(&hal_ll_spi_clock_structure); + + switch (map->module_index) { + #if defined(SPI_MODULE_1) + case (hal_ll_spi_master_module_num(SPI_MODULE_1)): + if(hal_ll_state) { + set_reg_bit(_RCC_APB2ENR, HAL_LL_SPI1_MASTER_ENABLE); + } else { + clear_reg_bit(_RCC_APB2ENR, HAL_LL_SPI1_MASTER_ENABLE); + } + *clock_value = hal_ll_spi_clock_structure.pclk2; + break; + #endif + + #if defined(SPI_MODULE_2) + case (hal_ll_spi_master_module_num(SPI_MODULE_2)): + if(hal_ll_state) { + set_reg_bit(_RCC_APB1ENR1, HAL_LL_SPI2_MASTER_ENABLE); + } else { + clear_reg_bit(_RCC_APB1ENR1, HAL_LL_SPI2_MASTER_ENABLE); + } + *clock_value = hal_ll_spi_clock_structure.pclk1; + break; + #endif + + #if defined(SPI_MODULE_3) + case (hal_ll_spi_master_module_num(SPI_MODULE_3)): + if(hal_ll_state) { + set_reg_bit(_RCC_APB1ENR1, HAL_LL_SPI3_MASTER_ENABLE); + } else { + clear_reg_bit(_RCC_APB1ENR1, HAL_LL_SPI3_MASTER_ENABLE); + } + *clock_value = hal_ll_spi_clock_structure.pclk1; + break; + #endif + + #if defined(SPI_MODULE_4) + case (hal_ll_spi_master_module_num(SPI_MODULE_4)): + if(hal_ll_state) { + set_reg_bit(_RCC_APB2ENR, HAL_LL_SPI4_MASTER_ENABLE); + } else { + clear_reg_bit(_RCC_APB2ENR, HAL_LL_SPI4_MASTER_ENABLE); + } + *clock_value = hal_ll_spi_clock_structure.pclk2; + break; + #endif + + + } +} + +static void hal_ll_spi_master_alternate_functions_set_state(hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state) { + module_struct module; + uint32_t spi_config; + + if((map->pins.sck.pin_name != HAL_LL_PIN_NC) && (map->pins.miso.pin_name != HAL_LL_PIN_NC) && (map->pins.miso.pin_name != HAL_LL_PIN_NC)) { + module.pins[0] = VALUE(map->pins.sck.pin_name, map->pins.sck.pin_af); + module.pins[1] = VALUE(map->pins.miso.pin_name, map->pins.miso.pin_af); + module.pins[2] = VALUE(map->pins.mosi.pin_name, map->pins.mosi.pin_af); + module.pins[3] = GPIO_MODULE_STRUCT_END; + + spi_config = GPIO_CFG_MODE_ALT_FUNCTION | + GPIO_CFG_SPEED_HIGH | + GPIO_CFG_OTYPE_PP; + + module.configs[0] = spi_config; + module.configs[1] = spi_config; + module.configs[2] = spi_config; + module.configs[3] = GPIO_MODULE_STRUCT_END; + + module.gpio_remap = map->pins.sck.pin_af; + + hal_ll_gpio_module_struct_init(&module, hal_ll_state); + } +} + +static uint32_t hal_ll_spi_master_hw_init(hal_ll_spi_master_hw_specifics_map_t *map, uint32_t clock_value) { + uint32_t temp_speed; + + hal_ll_spi_master_base_handle_t *hal_ll_hw_reg = (hal_ll_spi_master_base_handle_t *)map->base; + + // Reset all the settings in control register. + hal_ll_hw_reg->cr1 = 0; + + // Populate appropriate register values to get appropriate data transfer baud rate prescalers. + temp_speed = hal_ll_spi_master_get_speed(clock_value, map->speed); + hal_ll_hw_reg->cr1 |= temp_speed; + + // Choose whether idle state for the clock is high level (1) or low level (0). + if (map->mode <= HAL_LL_SPI_MASTER_MODE_1) { + clear_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_CLK_POLARITY); + } else { + set_reg_bit(&( hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_CLK_POLARITY); + } + + // Choose whether transmit occurs on the transition from ACTIVE to IDLE (1), or vice versa (0). + if (map->mode == HAL_LL_SPI_MASTER_MODE_0 || map->mode == HAL_LL_SPI_MASTER_MODE_2) { + clear_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_CLK_PHASE); + } else { + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_CLK_PHASE); + } + + // Set default values for SPI Master configuration. + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_SSM_ENABLE); + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_SSI_1); + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_SELECTION); + + // Set Slave Select Output Enable bit. + set_reg_bit(&(hal_ll_hw_reg->cr2), HAL_LL_SPI_MASTER_SSOE_BIT); + + // Set FIFO reception threshold to 8-bit. + hal_ll_hw_reg->cr2 |= HAL_LL_SPI_MASTER_FRXTH; + + // Enable SPI peripheral. + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_ENABLE); + + return (hal_ll_spi_master_get_actual_speed(clock_value, temp_speed)); +} + +static void hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_t *map) { + uint32_t clock_value; + + // Enable specific clock module. + hal_ll_spi_master_set_clock (map, true, &clock_value); + + // Enable specific alternate functions. + hal_ll_spi_master_alternate_functions_set_state(map, true); + + // Finally, write user-defined settings into hardware registers. + hal_ll_spi_master_hw_init(map, clock_value); +} +// ------------------------------------------------------------------------- END + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_85/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_85/CMakeLists.cmake new file mode 100644 index 000000000..23b631386 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_85/CMakeLists.cmake @@ -0,0 +1,9 @@ +if(${MCU_NAME} MATCHES "^STM32G474CB$|^STM32G474MB$|^STM32G474RB$|^STM32G474VB$|^STM32G474QB$|^STM32G474PB$|^STM32G474CC$|^STM32G474MC$|^STM32G474RC$|^STM32G474VC$|^STM32G474QC$|^STM32G474PC$|^STM32G474CE$|^STM32G474ME$|^STM32G474RE$|^STM32G474VE$|^STM32G474QE$|^STM32G474PE$") + set(spi_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_spi_master.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_85") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_85") + list(APPEND hal_ll_def_list "STM32G4xx") + list(APPEND hal_ll_def_list "STM32G47xx") + list(APPEND hal_ll_def_list "STM32G474xx") + set(spi_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/spi_master/hal_ll_spi_master_pin_map/implementations/doc_ds_85") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_85/hal_ll_spi_master.c b/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_85/hal_ll_spi_master.c new file mode 100644 index 000000000..aabcbbc5d --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_85/hal_ll_spi_master.c @@ -0,0 +1,749 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_spi_master.c + * @brief SPI Master HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_rcc.h" +#include "hal_ll_spi_master.h" +#include "hal_ll_spi_master_pin_map.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_spi_master_handle_register_t hal_ll_module_state[SPI_MODULE_COUNT] = {(handle_t *)NULL, (handle_t *)NULL, false}; + +// ------------------------------------------------------------- PRIVATE MACROS + +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_spi_master_get_module_state_address ((hal_ll_spi_master_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_spi_master_get_handle (hal_ll_spi_master_handle_register_t *)hal_ll_spi_master_get_module_state_address->hal_ll_spi_master_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_spi_master_get_base_struct(_handle) ((hal_ll_spi_master_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_spi_master_get_base_from_hal_handle ((hal_ll_spi_master_hw_specifics_map_t *)((hal_ll_spi_master_handle_register_t *)\ + (((hal_ll_spi_master_handle_register_t *)(handle))->hal_ll_spi_master_handle))->hal_ll_spi_master_handle)->base + +/*!< CR1 constants. */ +#define HAL_LL_SPI_MASTER 0x4 +#define HAL_LL_SPI_MASTER_SSI_1 8 +#define HAL_LL_SPI_MASTER_SELECTION 2 +/*!< CR2 constants. */ +#define HAL_LL_SPI_MASTER_FRXTH 0x1000ul + +#define HAL_LL_SPI_MASTER_SSOE_BIT 2 +#define HAL_LL_SPI_MASTER_SSOE 0x4 +#define HAL_LL_SPI_MASTER_SSM_ENABLE 9 +#define HAL_LL_SPI_MASTER_SSM_DISABLE 0x0000u +#define HAL_LL_SPI_MASTER_SS_ENABLE 0x10000ul +#define HAL_LL_SPI_MASTER_SS_DISABLE 0x00000ul +/*!< SR constants. */ +#define HAL_LL_SPI_MASTER_RXNE 0 +#define HAL_LL_SPI_MASTER_TXE 1 +/*!< I2SCFGR constants. */ +#define HAL_LL_SPI_MASTER_I2SMOD 11 +/*!< Enable constants. */ +#define HAL_LL_SPI_MASTER_ENABLE 6 +#define HAL_LL_SPI1_MASTER_ENABLE 12 + +#define HAL_LL_SPI2_MASTER_ENABLE 14 + +#define HAL_LL_SPI3_MASTER_ENABLE 15 + +#define HAL_LL_SPI4_MASTER_ENABLE 15 + +/*!< General constants. */ +#define HAL_LL_SPI_MASTER_BAUD_RATE_MASK 3 +#define HAL_LL_SPI_MASTER_16_BIT_REG_SHIFT 16 +#define HAL_LL_SPI_MASTER_DEFAULT_BASE_ADDRESS 0xFF + +#define HAL_LL_SPI_MASTER_CLK_POLARITY 1 +#define HAL_LL_SPI_MASTER_CLK_PHASE 0 + +#define hal_ll_spi_master_get_speed(_fosc,_speed) (_speed >= _fosc/2)? (0):\ + ((_speed <= _fosc/2) && (_speed > _fosc/4))? (0):\ + ((_speed <= _fosc/4) && (_speed > _fosc/8))? (0x0008UL):\ + ((_speed <= _fosc/8) && (_speed > _fosc/16))? (0x0010UL):\ + ((_speed <= _fosc/16) && (_speed > _fosc/32))? (0x0018UL):\ + ((_speed <= _fosc/32) && (_speed > _fosc/64))? (0x0020UL):\ + ((_speed <= _fosc/64) && (_speed > _fosc/128))?(0x0028UL):\ + ((_speed <= _fosc/128)&& (_speed > _fosc/256))?(0x0030UL):(0x0038UL) + +#define hal_ll_spi_master_get_actual_speed(_fosc,_divider) (_divider == 0)?(_fosc/2):\ + (_divider == 0x0008UL)?(_fosc/4):\ + (_divider == 0x0010UL)?(_fosc/8):\ + (_divider == 0x0018UL)?(_fosc/16):\ + (_divider == 0x0020UL)?(_fosc/32):\ + (_divider == 0x0028UL)?(_fosc/64):\ + (_divider == 0x0030UL)?(_fosc/128):\ + (_divider == 0x0038UL)?(_fosc/256):(_fosc/256) + +/*!< @brief Default SPI Master bit-rate if no speed is set */ +#define HAL_LL_SPI_MASTER_SPEED_100K 100000 + +// -------------------------------------------------------------- PRIVATE TYPES + +/*!< @brief SPI register structure. */ +typedef struct { + uint32_t cr1; + uint32_t cr2; + uint32_t sr; + uint32_t dr; + uint32_t crcpr; + uint32_t rxcrcr; + uint32_t txcrcr; + uint32_t i2scfgr; + uint32_t i2spr; + +} hal_ll_spi_master_base_handle_t; + +/*!< @brief SPI Master hardware specific structure */ +typedef struct { + hal_ll_base_addr_t base; + uint8_t module_index; + hal_ll_spi_master_pins_t pins; + uint8_t dummy_data; + uint32_t speed; + uint32_t hw_actual_speed; + hal_ll_spi_master_mode_t mode; +} hal_ll_spi_master_hw_specifics_map_t; + +/*!< @brief SPI hw specific module values */ +typedef struct +{ + uint16_t pin_sck; + uint16_t pin_miso; + uint16_t pin_mosi; +} hal_ll_spi_pin_id; + +/*!< @brief SPI Master hw specific error values */ +typedef enum { + HAL_LL_SPI_MASTER_SUCCESS = 0, + HAL_LL_SPI_MASTER_WRONG_PINS, + HAL_LL_SPI_MASTER_MODULE_ERROR, + + HAL_LL_SPI_MASTER_ERROR = (-1) +} hal_ll_spi_master_err_t; + +// ------------------------------------------------------------------ VARIABLES + +/*!< @brief SPI Master hardware specific info */ +static hal_ll_spi_master_hw_specifics_map_t hal_ll_spi_master_hw_specifics_map[] = { + #ifdef SPI_MODULE_1 + {HAL_LL_SPI1_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_1), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, HAL_LL_SPI_MASTER_SPEED_100K, 0, HAL_LL_SPI_MASTER_MODE_DEFAULT}, + #endif + + #ifdef SPI_MODULE_2 + {HAL_LL_SPI2_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_2), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, HAL_LL_SPI_MASTER_SPEED_100K, 0, HAL_LL_SPI_MASTER_MODE_DEFAULT}, + #endif + + #ifdef SPI_MODULE_3 + {HAL_LL_SPI3_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_3), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, HAL_LL_SPI_MASTER_SPEED_100K, 0, HAL_LL_SPI_MASTER_MODE_DEFAULT}, + #endif + + #ifdef SPI_MODULE_4 + {HAL_LL_SPI4_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_4), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, HAL_LL_SPI_MASTER_SPEED_100K, 0, HAL_LL_SPI_MASTER_MODE_DEFAULT}, + #endif + + + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, 0, 0, 0} +}; + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_spi_master_handle_register_t *low_level_handle; +static volatile hal_ll_spi_master_hw_specifics_map_t *hal_ll_spi_master_hw_specifics_map_local; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Check if pins are adequate. + * + * Checks SCK, MISO and MOSI pins the user has passed with pre-defined + * pins in SCK, MISO and MOSI maps. Take into consideration that module + * index numbers have to be the same for both pins. + * + * @param[in] sck - SCK pre-defined pin name. + * @param[in] miso - MISO pre-defined pin name. + * @param[in] mosi - MOSI pre-defined pin name. + * @param[in] *index_list - Index list address + * @return hal_ll_pin_name_t Module index based on pins. + * + * Returns pre-defined module index from pin maps, if pins + * are adequate. + */ +static hal_ll_pin_name_t hal_ll_spi_master_check_pins(hal_ll_pin_name_t sck, hal_ll_pin_name_t miso, hal_ll_pin_name_t mosi, hal_ll_spi_pin_id *index_list, hal_ll_spi_master_handle_register_t *handle_map ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_spi_master_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_spi_master_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_spi_master_hw_specifics_map_t *hal_ll_get_specifics(handle_t handle); + +/** + * @brief Enable clock for SPI Master module on hardware level. + * + * Initializes SPI Master module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] *map - Object specific context handler. + * @param[in] hal_ll_state - True(enable clock)/False(disable clock). + * @param[in] *clock_value - SPI Master baud rate value taken from a specific peripheral clock bus. + * @return None + */ +static void hal_ll_spi_master_set_clock(hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state, uint32_t *clock_value); + +/** + * @brief Sets SPI Master pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if SPI is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param[in] *map - Object specific context handler. + * @param[in] hal_ll_state - Init/De-init + */ +static void hal_ll_spi_master_alternate_functions_set_state(hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state); + +/** + * @brief Full SPI Master module initialization procedure. + * + * Initializes SPI Master module on hardware level, based on beforehand + * set configuration and module handler. Sets adequate pin alternate functions. + * Initializes module clock. + * + * @param[in] *map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static void hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_t *map); + +/** + * @brief Perform a read on the SPI Master bus. + * + * Initializes SPI Master module on hardware level, if not initialized beforehand + * and continues to perform a read operation on the bus. + * + * @param[in] *map - Object specific context handler. + * @param[in] *read_data_buffer - Pointer to data buffer. + * @param[in] read_data_length - Number of data to be read. + * @param[in] dummy_data - Data required for read procedure. + * @return hal_ll_err_t Module specific error values. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +static void hal_ll_spi_master_read_bare_metal(hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *read_data_buffer, size_t read_data_length, uint8_t dummy_data); + +/** + * @brief Perform a write on the SPI Master bus. + * + * Initializes SPI Master module on hardware level, if not initialized beforehand + * and continues to perform a write operation on the bus. + * + * @param[in] map - Object specific context handler. + * @param[in] *write_data_buffer - Pointer to data buffer. + * @param[in] write_data_length - Number of data to be written. + * @return hal_ll_err_t Module specific error values. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +static void hal_ll_spi_master_write_bare_metal(hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *write_data_buffer, size_t write_data_length); + +/** + * @brief Perform a write then read on the SPI Master bus. + * + * Initializes SPI Master module on hardware level, if not initialized beforehand + * and continues to perform a write operation on the bus. + * + * @param[in] *handle - Object specific context handler. + * @param[in] *write_data_buffer - Pointer to data buffer. + * @param[in] length_write_data - Number of data to be written. + * @param[in] *read_data_buffer - Pointer to data buffer. + * @param[in] length_read_data - Number of data to be read. + * @return hal_ll_err_t Module specific error values. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_spi_master_write_then_read(handle_t *handle, uint8_t *write_data_buffer, size_t length_write_data, uint8_t *read_data_buffer, size_t length_read_data); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * SPI SCK, MISO and MOSI pins. + * + * @param[in] module_index SPI HW module index -- 0,1,2... + * @param[in] *index_list Array with SCK, MISO and MOSI map index values + * and module number + * + * @return None + */ +static void hal_ll_spi_master_map_pins(uint8_t module_index, hal_ll_spi_pin_id *index_list); + + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS + +hal_ll_err_t hal_ll_spi_master_register_handle(hal_ll_pin_name_t sck, hal_ll_pin_name_t miso, hal_ll_pin_name_t mosi, hal_ll_spi_master_handle_register_t *handle_map, uint8_t *hal_module_id) { + + hal_ll_spi_pin_id index_list[SPI_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + uint16_t pin_check_result; + + // Check user-defined pins. + if ((pin_check_result = hal_ll_spi_master_check_pins(sck, miso, mosi, &index_list, handle_map)) == HAL_LL_PIN_NC) { + return HAL_LL_SPI_MASTER_WRONG_PINS; + }; + + // If user has come with the same SPI hardware module, and with the same pair of the pins, the pin mapping procedure + // will not have to take a place; otherwise, clear af-s, map new pins, set af-s, and set init state to false. + if ((hal_ll_spi_master_hw_specifics_map[pin_check_result].pins.sck.pin_name != sck) || + (hal_ll_spi_master_hw_specifics_map[pin_check_result].pins.miso.pin_name != miso) || + (hal_ll_spi_master_hw_specifics_map[pin_check_result].pins.mosi.pin_name != mosi) ) { + + hal_ll_spi_master_alternate_functions_set_state(&hal_ll_spi_master_hw_specifics_map[pin_check_result], false); + + hal_ll_spi_master_map_pins(pin_check_result, &index_list); + + hal_ll_spi_master_alternate_functions_set_state(&hal_ll_spi_master_hw_specifics_map[pin_check_result], true); + + handle_map[pin_check_result].init_ll_state = false; + } + + // Return id of the SPI module that is going to be used. + *hal_module_id = pin_check_result; + + // Insert current module into hal_ll_module_state map. + hal_ll_module_state[pin_check_result].hal_ll_spi_master_handle = (handle_t *)&hal_ll_spi_master_hw_specifics_map[pin_check_result].base; + + // Return the same info about module one level up ( into the HAL level ). + handle_map[pin_check_result].hal_ll_spi_master_handle = (handle_t*)&hal_ll_module_state[pin_check_result].hal_ll_spi_master_handle; + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_spi(handle_t *handle) { + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + hal_ll_spi_master_handle_register_t *hal_handle = (hal_ll_spi_master_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_spi_master_hw_specifics_map_local->module_index; + + hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_local); + + hal_ll_module_state[pin_check_result].hal_ll_spi_master_handle = (handle_t *)&hal_ll_spi_master_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +void hal_ll_spi_master_set_default_write_data(handle_t *handle, uint8_t dummy_data) { + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + if(hal_ll_spi_master_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR) { + hal_ll_spi_master_hw_specifics_map_local->dummy_data = dummy_data; + } +} + +hal_ll_err_t hal_ll_spi_master_write(handle_t *handle, uint8_t *write_data_buffer, size_t length_data) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + hal_ll_spi_master_write_bare_metal(hal_ll_spi_master_hw_specifics_map_local->base, write_data_buffer, length_data); + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_spi_master_read(handle_t *handle, uint8_t *read_data_buffer, size_t length_data) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + hal_ll_spi_master_read_bare_metal(hal_ll_spi_master_hw_specifics_map_local->base, read_data_buffer, length_data, hal_ll_spi_master_hw_specifics_map_local->dummy_data); + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_spi_master_write_then_read(handle_t *handle, uint8_t *write_data_buffer, size_t length_write_data, uint8_t *read_data_buffer, size_t length_read_data) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + hal_ll_spi_master_write_bare_metal(hal_ll_spi_master_hw_specifics_map_local->base, write_data_buffer, length_write_data); + + hal_ll_spi_master_read_bare_metal(hal_ll_spi_master_hw_specifics_map_local->base, read_data_buffer, length_read_data, hal_ll_spi_master_hw_specifics_map_local->dummy_data); + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +uint32_t hal_ll_spi_master_set_speed(handle_t *handle, uint32_t speed) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + low_level_handle->init_ll_state = false; + + // Insert user-defined baud rate into local map. + hal_ll_spi_master_hw_specifics_map_local->speed = speed; + + // Init once again, but with updated SPI Master baud rate value. + hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + // Return value of the SPI Master baud rate value. + return hal_ll_spi_master_hw_specifics_map_local->hw_actual_speed; +} + +hal_ll_err_t hal_ll_spi_master_set_mode(handle_t *handle, hal_ll_spi_master_mode_t mode) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + low_level_handle->init_ll_state = false; + + // Insert user-defined mode into local map. + hal_ll_spi_master_hw_specifics_map_local->mode = mode; + + // Init once again, but with updated SPI Master mode value. + hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +void hal_ll_spi_master_close(handle_t* handle) { + uint32_t dummy; + low_level_handle = hal_ll_spi_master_get_handle; + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + if(low_level_handle->hal_ll_spi_master_handle != NULL) { + low_level_handle->hal_ll_spi_master_handle = NULL; + low_level_handle->hal_drv_spi_master_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_spi_master_hw_specifics_map_local->mode = HAL_LL_SPI_MASTER_MODE_DEFAULT; + hal_ll_spi_master_hw_specifics_map_local->speed = HAL_LL_SPI_MASTER_SPEED_100K; + hal_ll_spi_master_hw_specifics_map_local->dummy_data = 0; + hal_ll_spi_master_hw_specifics_map_local->hw_actual_speed = 0; + + hal_ll_spi_master_set_clock(hal_ll_spi_master_hw_specifics_map_local, true, &dummy); + hal_ll_spi_master_alternate_functions_set_state(hal_ll_spi_master_hw_specifics_map_local, false); + hal_ll_spi_master_set_clock(hal_ll_spi_master_hw_specifics_map_local, false, &dummy); + + hal_ll_spi_master_hw_specifics_map_local->pins.sck.pin_name = HAL_LL_PIN_NC; + hal_ll_spi_master_hw_specifics_map_local->pins.miso.pin_name = HAL_LL_PIN_NC; + hal_ll_spi_master_hw_specifics_map_local->pins.mosi.pin_name = HAL_LL_PIN_NC; + hal_ll_spi_master_hw_specifics_map_local->pins.sck.pin_af = 0; + hal_ll_spi_master_hw_specifics_map_local->pins.miso.pin_af = 0; + hal_ll_spi_master_hw_specifics_map_local->pins.mosi.pin_af = 0; + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS + +uint8_t hal_ll_spi_master_transfer_bare_metal(hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t data_buffer) { + // Write user-defined data ( 'hal_ll_spi_master_read_bare_metal' procedure will send dummy data ). + *((volatile uint8_t *)&hal_ll_hw_reg->dr) = (uint8_t)data_buffer; // 8-bit data + + // Wait for receive buffer not empty status. + while (!(check_reg_bit( &(hal_ll_hw_reg->sr), HAL_LL_SPI_MASTER_RXNE))); + + // Return read data. + return *((volatile uint8_t *)&hal_ll_hw_reg->dr); // 8-bit data +} + +static void hal_ll_spi_master_write_bare_metal( hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *write_data_buffer, size_t write_data_length ) { + uint16_t transfer_counter = NULL; + + // Write the first data to be transmitted into the SPI_DR register. + for(transfer_counter = 0; transfer_counter < write_data_length; transfer_counter++) { + // If we are good to go ( if the tx buffer value has been shifted to the shift register ), write the data. + hal_ll_spi_master_transfer_bare_metal( hal_ll_hw_reg, write_data_buffer[transfer_counter]); + } +} + +static void hal_ll_spi_master_read_bare_metal(hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *read_data_buffer, size_t read_data_length, uint8_t dummy_data) { + uint16_t transfer_counter = NULL; + + // Read the first data to be transmitted into the SPI_DR register. + for(transfer_counter = 0; transfer_counter < read_data_length; transfer_counter++) { + // If we are good to go ( if the value from shift register has been shifted to the rx register ), read the data. + read_data_buffer[transfer_counter] = hal_ll_spi_master_transfer_bare_metal(hal_ll_hw_reg, dummy_data); + } +} + +static hal_ll_pin_name_t hal_ll_spi_master_check_pins(hal_ll_pin_name_t sck_pin, hal_ll_pin_name_t miso_pin, hal_ll_pin_name_t mosi_pin, hal_ll_spi_pin_id *index_list, hal_ll_spi_master_handle_register_t *handle_map) { + static const uint16_t sck_map_size = (sizeof(_spi_sck_map)) / (sizeof(hal_ll_spi_master_pin_map_t)); + static const uint16_t miso_map_size = (sizeof(_spi_miso_map)) / (sizeof(hal_ll_spi_master_pin_map_t)); + static const uint16_t mosi_map_size = (sizeof(_spi_mosi_map)) / (sizeof(hal_ll_spi_master_pin_map_t)); + uint8_t hal_ll_module_id = 0; + uint8_t index_counter = 0; + uint16_t miso_index; + uint16_t mosi_index; + uint16_t sck_index; + + if ( (HAL_LL_PIN_NC == sck_pin) || (HAL_LL_PIN_NC == miso_pin) || (HAL_LL_PIN_NC == mosi_pin) ) { + return HAL_LL_PIN_NC; + } + + // Check pins from the specific pin maps with the user defined pins. + for (sck_index = 0; sck_index < sck_map_size; sck_index++) { + if (_spi_sck_map[sck_index].pin == sck_pin) { + for (miso_index = 0; miso_index < miso_map_size; miso_index++) { + if (_spi_miso_map[miso_index].pin == miso_pin) { + if (_spi_sck_map[sck_index].module_index ==_spi_miso_map[miso_index].module_index) { + for (mosi_index = 0; mosi_index < mosi_map_size; mosi_index++) { + if (_spi_mosi_map[mosi_index ].pin == mosi_pin) { + if (_spi_sck_map[sck_index].module_index ==_spi_mosi_map[mosi_index].module_index) { + // Get module number + hal_ll_module_id = _spi_sck_map[ sck_index ].module_index; + + // Map pin names + index_list[hal_ll_module_id].pin_sck = sck_index; + index_list[hal_ll_module_id].pin_miso = miso_index; + index_list[hal_ll_module_id].pin_mosi = mosi_index; + + // Check if module is taken + if ( NULL == handle_map[hal_ll_module_id].hal_drv_spi_master_handle ) { + return hal_ll_module_id; + } else if ( SPI_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + } + } + } + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static void hal_ll_spi_master_map_pins(uint8_t module_index, hal_ll_spi_pin_id *index_list) { + // if every single pin is OK, insert them into this new map, and use this map in all low level functions. + hal_ll_spi_master_hw_specifics_map[module_index].pins.sck.pin_name = _spi_sck_map[index_list[module_index].pin_sck].pin; + hal_ll_spi_master_hw_specifics_map[module_index].pins.miso.pin_name = _spi_miso_map[index_list[module_index].pin_miso].pin; + hal_ll_spi_master_hw_specifics_map[module_index].pins.mosi.pin_name = _spi_mosi_map[index_list[module_index].pin_mosi].pin; + + // SCK, MISO and MOSI pins could have different alternate function settings, hence save all the AF-s. + hal_ll_spi_master_hw_specifics_map[module_index].pins.sck.pin_af = _spi_sck_map[index_list[module_index].pin_sck].af; + hal_ll_spi_master_hw_specifics_map[module_index].pins.miso.pin_af = _spi_miso_map[index_list[module_index].pin_miso].af; + hal_ll_spi_master_hw_specifics_map[module_index].pins.mosi.pin_af = _spi_mosi_map[index_list[module_index].pin_mosi].af; +} + +static hal_ll_spi_master_hw_specifics_map_t *hal_ll_get_specifics(handle_t handle) { + uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof( hal_ll_spi_master_handle_register_t)); + + static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof( hal_ll_spi_master_handle_register_t)); + + while (hal_ll_module_count--) { + if (hal_ll_spi_master_get_base_from_hal_handle == hal_ll_spi_master_hw_specifics_map[hal_ll_module_count].base) { + return &hal_ll_spi_master_hw_specifics_map[hal_ll_module_count]; + } + } + + // If NOK, return pointer to the last row of this map ( point to null pointer ). + return &hal_ll_spi_master_hw_specifics_map[hal_ll_module_error]; +} + +static void hal_ll_spi_master_set_clock(hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state, uint32_t *clock_value) { + rcc_clocks_t hal_ll_spi_clock_structure; + + RCC_GetClocksFrequency(&hal_ll_spi_clock_structure); + + switch (map->module_index) { + #if defined(SPI_MODULE_1) + case (hal_ll_spi_master_module_num(SPI_MODULE_1)): + if(hal_ll_state) { + set_reg_bit(_RCC_APB2ENR, HAL_LL_SPI1_MASTER_ENABLE); + } else { + clear_reg_bit(_RCC_APB2ENR, HAL_LL_SPI1_MASTER_ENABLE); + } + *clock_value = hal_ll_spi_clock_structure.pclk2; + break; + #endif + + #if defined(SPI_MODULE_2) + case (hal_ll_spi_master_module_num(SPI_MODULE_2)): + if(hal_ll_state) { + set_reg_bit(_RCC_APB1ENR1, HAL_LL_SPI2_MASTER_ENABLE); + } else { + clear_reg_bit(_RCC_APB1ENR1, HAL_LL_SPI2_MASTER_ENABLE); + } + *clock_value = hal_ll_spi_clock_structure.pclk1; + break; + #endif + + #if defined(SPI_MODULE_3) + case (hal_ll_spi_master_module_num(SPI_MODULE_3)): + if(hal_ll_state) { + set_reg_bit(_RCC_APB1ENR1, HAL_LL_SPI3_MASTER_ENABLE); + } else { + clear_reg_bit(_RCC_APB1ENR1, HAL_LL_SPI3_MASTER_ENABLE); + } + *clock_value = hal_ll_spi_clock_structure.pclk1; + break; + #endif + + #if defined(SPI_MODULE_4) + case (hal_ll_spi_master_module_num(SPI_MODULE_4)): + if(hal_ll_state) { + set_reg_bit(_RCC_APB2ENR, HAL_LL_SPI4_MASTER_ENABLE); + } else { + clear_reg_bit(_RCC_APB2ENR, HAL_LL_SPI4_MASTER_ENABLE); + } + *clock_value = hal_ll_spi_clock_structure.pclk2; + break; + #endif + + + } +} + +static void hal_ll_spi_master_alternate_functions_set_state(hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state) { + module_struct module; + uint32_t spi_config; + + if((map->pins.sck.pin_name != HAL_LL_PIN_NC) && (map->pins.miso.pin_name != HAL_LL_PIN_NC) && (map->pins.miso.pin_name != HAL_LL_PIN_NC)) { + module.pins[0] = VALUE(map->pins.sck.pin_name, map->pins.sck.pin_af); + module.pins[1] = VALUE(map->pins.miso.pin_name, map->pins.miso.pin_af); + module.pins[2] = VALUE(map->pins.mosi.pin_name, map->pins.mosi.pin_af); + module.pins[3] = GPIO_MODULE_STRUCT_END; + + spi_config = GPIO_CFG_MODE_ALT_FUNCTION | + GPIO_CFG_SPEED_HIGH | + GPIO_CFG_OTYPE_PP; + + module.configs[0] = spi_config; + module.configs[1] = spi_config; + module.configs[2] = spi_config; + module.configs[3] = GPIO_MODULE_STRUCT_END; + + module.gpio_remap = map->pins.sck.pin_af; + + hal_ll_gpio_module_struct_init(&module, hal_ll_state); + } +} + +static uint32_t hal_ll_spi_master_hw_init(hal_ll_spi_master_hw_specifics_map_t *map, uint32_t clock_value) { + uint32_t temp_speed; + + hal_ll_spi_master_base_handle_t *hal_ll_hw_reg = (hal_ll_spi_master_base_handle_t *)map->base; + + // Reset all the settings in control register. + hal_ll_hw_reg->cr1 = 0; + + // Populate appropriate register values to get appropriate data transfer baud rate prescalers. + temp_speed = hal_ll_spi_master_get_speed(clock_value, map->speed); + hal_ll_hw_reg->cr1 |= temp_speed; + + // Choose whether idle state for the clock is high level (1) or low level (0). + if (map->mode <= HAL_LL_SPI_MASTER_MODE_1) { + clear_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_CLK_POLARITY); + } else { + set_reg_bit(&( hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_CLK_POLARITY); + } + + // Choose whether transmit occurs on the transition from ACTIVE to IDLE (1), or vice versa (0). + if (map->mode == HAL_LL_SPI_MASTER_MODE_0 || map->mode == HAL_LL_SPI_MASTER_MODE_2) { + clear_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_CLK_PHASE); + } else { + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_CLK_PHASE); + } + + // Set default values for SPI Master configuration. + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_SSM_ENABLE); + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_SSI_1); + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_SELECTION); + + // Set Slave Select Output Enable bit. + set_reg_bit(&(hal_ll_hw_reg->cr2), HAL_LL_SPI_MASTER_SSOE_BIT); + + // Set FIFO reception threshold to 8-bit. + hal_ll_hw_reg->cr2 |= HAL_LL_SPI_MASTER_FRXTH; + + // Enable SPI peripheral. + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_ENABLE); + + return (hal_ll_spi_master_get_actual_speed(clock_value, temp_speed)); +} + +static void hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_t *map) { + uint32_t clock_value; + + // Enable specific clock module. + hal_ll_spi_master_set_clock (map, true, &clock_value); + + // Enable specific alternate functions. + hal_ll_spi_master_alternate_functions_set_state(map, true); + + // Finally, write user-defined settings into hardware registers. + hal_ll_spi_master_hw_init(map, clock_value); +} +// ------------------------------------------------------------------------- END + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_86/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_86/CMakeLists.cmake new file mode 100644 index 000000000..3d4246c5a --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_86/CMakeLists.cmake @@ -0,0 +1,9 @@ +if(${MCU_NAME} MATCHES "^STM32G483CE$|^STM32G483RE$|^STM32G483ME$|^STM32G483PE$|^STM32G483VE$|^STM32G483QE$") + set(spi_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_spi_master.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_86") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_86") + list(APPEND hal_ll_def_list "STM32G4xx") + list(APPEND hal_ll_def_list "STM32G48xx") + list(APPEND hal_ll_def_list "STM32G483xx") + set(spi_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/spi_master/hal_ll_spi_master_pin_map/implementations/doc_ds_86") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_86/hal_ll_spi_master.c b/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_86/hal_ll_spi_master.c new file mode 100644 index 000000000..aabcbbc5d --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_86/hal_ll_spi_master.c @@ -0,0 +1,749 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_spi_master.c + * @brief SPI Master HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_rcc.h" +#include "hal_ll_spi_master.h" +#include "hal_ll_spi_master_pin_map.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_spi_master_handle_register_t hal_ll_module_state[SPI_MODULE_COUNT] = {(handle_t *)NULL, (handle_t *)NULL, false}; + +// ------------------------------------------------------------- PRIVATE MACROS + +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_spi_master_get_module_state_address ((hal_ll_spi_master_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_spi_master_get_handle (hal_ll_spi_master_handle_register_t *)hal_ll_spi_master_get_module_state_address->hal_ll_spi_master_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_spi_master_get_base_struct(_handle) ((hal_ll_spi_master_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_spi_master_get_base_from_hal_handle ((hal_ll_spi_master_hw_specifics_map_t *)((hal_ll_spi_master_handle_register_t *)\ + (((hal_ll_spi_master_handle_register_t *)(handle))->hal_ll_spi_master_handle))->hal_ll_spi_master_handle)->base + +/*!< CR1 constants. */ +#define HAL_LL_SPI_MASTER 0x4 +#define HAL_LL_SPI_MASTER_SSI_1 8 +#define HAL_LL_SPI_MASTER_SELECTION 2 +/*!< CR2 constants. */ +#define HAL_LL_SPI_MASTER_FRXTH 0x1000ul + +#define HAL_LL_SPI_MASTER_SSOE_BIT 2 +#define HAL_LL_SPI_MASTER_SSOE 0x4 +#define HAL_LL_SPI_MASTER_SSM_ENABLE 9 +#define HAL_LL_SPI_MASTER_SSM_DISABLE 0x0000u +#define HAL_LL_SPI_MASTER_SS_ENABLE 0x10000ul +#define HAL_LL_SPI_MASTER_SS_DISABLE 0x00000ul +/*!< SR constants. */ +#define HAL_LL_SPI_MASTER_RXNE 0 +#define HAL_LL_SPI_MASTER_TXE 1 +/*!< I2SCFGR constants. */ +#define HAL_LL_SPI_MASTER_I2SMOD 11 +/*!< Enable constants. */ +#define HAL_LL_SPI_MASTER_ENABLE 6 +#define HAL_LL_SPI1_MASTER_ENABLE 12 + +#define HAL_LL_SPI2_MASTER_ENABLE 14 + +#define HAL_LL_SPI3_MASTER_ENABLE 15 + +#define HAL_LL_SPI4_MASTER_ENABLE 15 + +/*!< General constants. */ +#define HAL_LL_SPI_MASTER_BAUD_RATE_MASK 3 +#define HAL_LL_SPI_MASTER_16_BIT_REG_SHIFT 16 +#define HAL_LL_SPI_MASTER_DEFAULT_BASE_ADDRESS 0xFF + +#define HAL_LL_SPI_MASTER_CLK_POLARITY 1 +#define HAL_LL_SPI_MASTER_CLK_PHASE 0 + +#define hal_ll_spi_master_get_speed(_fosc,_speed) (_speed >= _fosc/2)? (0):\ + ((_speed <= _fosc/2) && (_speed > _fosc/4))? (0):\ + ((_speed <= _fosc/4) && (_speed > _fosc/8))? (0x0008UL):\ + ((_speed <= _fosc/8) && (_speed > _fosc/16))? (0x0010UL):\ + ((_speed <= _fosc/16) && (_speed > _fosc/32))? (0x0018UL):\ + ((_speed <= _fosc/32) && (_speed > _fosc/64))? (0x0020UL):\ + ((_speed <= _fosc/64) && (_speed > _fosc/128))?(0x0028UL):\ + ((_speed <= _fosc/128)&& (_speed > _fosc/256))?(0x0030UL):(0x0038UL) + +#define hal_ll_spi_master_get_actual_speed(_fosc,_divider) (_divider == 0)?(_fosc/2):\ + (_divider == 0x0008UL)?(_fosc/4):\ + (_divider == 0x0010UL)?(_fosc/8):\ + (_divider == 0x0018UL)?(_fosc/16):\ + (_divider == 0x0020UL)?(_fosc/32):\ + (_divider == 0x0028UL)?(_fosc/64):\ + (_divider == 0x0030UL)?(_fosc/128):\ + (_divider == 0x0038UL)?(_fosc/256):(_fosc/256) + +/*!< @brief Default SPI Master bit-rate if no speed is set */ +#define HAL_LL_SPI_MASTER_SPEED_100K 100000 + +// -------------------------------------------------------------- PRIVATE TYPES + +/*!< @brief SPI register structure. */ +typedef struct { + uint32_t cr1; + uint32_t cr2; + uint32_t sr; + uint32_t dr; + uint32_t crcpr; + uint32_t rxcrcr; + uint32_t txcrcr; + uint32_t i2scfgr; + uint32_t i2spr; + +} hal_ll_spi_master_base_handle_t; + +/*!< @brief SPI Master hardware specific structure */ +typedef struct { + hal_ll_base_addr_t base; + uint8_t module_index; + hal_ll_spi_master_pins_t pins; + uint8_t dummy_data; + uint32_t speed; + uint32_t hw_actual_speed; + hal_ll_spi_master_mode_t mode; +} hal_ll_spi_master_hw_specifics_map_t; + +/*!< @brief SPI hw specific module values */ +typedef struct +{ + uint16_t pin_sck; + uint16_t pin_miso; + uint16_t pin_mosi; +} hal_ll_spi_pin_id; + +/*!< @brief SPI Master hw specific error values */ +typedef enum { + HAL_LL_SPI_MASTER_SUCCESS = 0, + HAL_LL_SPI_MASTER_WRONG_PINS, + HAL_LL_SPI_MASTER_MODULE_ERROR, + + HAL_LL_SPI_MASTER_ERROR = (-1) +} hal_ll_spi_master_err_t; + +// ------------------------------------------------------------------ VARIABLES + +/*!< @brief SPI Master hardware specific info */ +static hal_ll_spi_master_hw_specifics_map_t hal_ll_spi_master_hw_specifics_map[] = { + #ifdef SPI_MODULE_1 + {HAL_LL_SPI1_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_1), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, HAL_LL_SPI_MASTER_SPEED_100K, 0, HAL_LL_SPI_MASTER_MODE_DEFAULT}, + #endif + + #ifdef SPI_MODULE_2 + {HAL_LL_SPI2_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_2), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, HAL_LL_SPI_MASTER_SPEED_100K, 0, HAL_LL_SPI_MASTER_MODE_DEFAULT}, + #endif + + #ifdef SPI_MODULE_3 + {HAL_LL_SPI3_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_3), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, HAL_LL_SPI_MASTER_SPEED_100K, 0, HAL_LL_SPI_MASTER_MODE_DEFAULT}, + #endif + + #ifdef SPI_MODULE_4 + {HAL_LL_SPI4_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_4), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, HAL_LL_SPI_MASTER_SPEED_100K, 0, HAL_LL_SPI_MASTER_MODE_DEFAULT}, + #endif + + + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, 0, 0, 0} +}; + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_spi_master_handle_register_t *low_level_handle; +static volatile hal_ll_spi_master_hw_specifics_map_t *hal_ll_spi_master_hw_specifics_map_local; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Check if pins are adequate. + * + * Checks SCK, MISO and MOSI pins the user has passed with pre-defined + * pins in SCK, MISO and MOSI maps. Take into consideration that module + * index numbers have to be the same for both pins. + * + * @param[in] sck - SCK pre-defined pin name. + * @param[in] miso - MISO pre-defined pin name. + * @param[in] mosi - MOSI pre-defined pin name. + * @param[in] *index_list - Index list address + * @return hal_ll_pin_name_t Module index based on pins. + * + * Returns pre-defined module index from pin maps, if pins + * are adequate. + */ +static hal_ll_pin_name_t hal_ll_spi_master_check_pins(hal_ll_pin_name_t sck, hal_ll_pin_name_t miso, hal_ll_pin_name_t mosi, hal_ll_spi_pin_id *index_list, hal_ll_spi_master_handle_register_t *handle_map ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_spi_master_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_spi_master_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_spi_master_hw_specifics_map_t *hal_ll_get_specifics(handle_t handle); + +/** + * @brief Enable clock for SPI Master module on hardware level. + * + * Initializes SPI Master module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] *map - Object specific context handler. + * @param[in] hal_ll_state - True(enable clock)/False(disable clock). + * @param[in] *clock_value - SPI Master baud rate value taken from a specific peripheral clock bus. + * @return None + */ +static void hal_ll_spi_master_set_clock(hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state, uint32_t *clock_value); + +/** + * @brief Sets SPI Master pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if SPI is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param[in] *map - Object specific context handler. + * @param[in] hal_ll_state - Init/De-init + */ +static void hal_ll_spi_master_alternate_functions_set_state(hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state); + +/** + * @brief Full SPI Master module initialization procedure. + * + * Initializes SPI Master module on hardware level, based on beforehand + * set configuration and module handler. Sets adequate pin alternate functions. + * Initializes module clock. + * + * @param[in] *map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static void hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_t *map); + +/** + * @brief Perform a read on the SPI Master bus. + * + * Initializes SPI Master module on hardware level, if not initialized beforehand + * and continues to perform a read operation on the bus. + * + * @param[in] *map - Object specific context handler. + * @param[in] *read_data_buffer - Pointer to data buffer. + * @param[in] read_data_length - Number of data to be read. + * @param[in] dummy_data - Data required for read procedure. + * @return hal_ll_err_t Module specific error values. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +static void hal_ll_spi_master_read_bare_metal(hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *read_data_buffer, size_t read_data_length, uint8_t dummy_data); + +/** + * @brief Perform a write on the SPI Master bus. + * + * Initializes SPI Master module on hardware level, if not initialized beforehand + * and continues to perform a write operation on the bus. + * + * @param[in] map - Object specific context handler. + * @param[in] *write_data_buffer - Pointer to data buffer. + * @param[in] write_data_length - Number of data to be written. + * @return hal_ll_err_t Module specific error values. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +static void hal_ll_spi_master_write_bare_metal(hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *write_data_buffer, size_t write_data_length); + +/** + * @brief Perform a write then read on the SPI Master bus. + * + * Initializes SPI Master module on hardware level, if not initialized beforehand + * and continues to perform a write operation on the bus. + * + * @param[in] *handle - Object specific context handler. + * @param[in] *write_data_buffer - Pointer to data buffer. + * @param[in] length_write_data - Number of data to be written. + * @param[in] *read_data_buffer - Pointer to data buffer. + * @param[in] length_read_data - Number of data to be read. + * @return hal_ll_err_t Module specific error values. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_spi_master_write_then_read(handle_t *handle, uint8_t *write_data_buffer, size_t length_write_data, uint8_t *read_data_buffer, size_t length_read_data); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * SPI SCK, MISO and MOSI pins. + * + * @param[in] module_index SPI HW module index -- 0,1,2... + * @param[in] *index_list Array with SCK, MISO and MOSI map index values + * and module number + * + * @return None + */ +static void hal_ll_spi_master_map_pins(uint8_t module_index, hal_ll_spi_pin_id *index_list); + + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS + +hal_ll_err_t hal_ll_spi_master_register_handle(hal_ll_pin_name_t sck, hal_ll_pin_name_t miso, hal_ll_pin_name_t mosi, hal_ll_spi_master_handle_register_t *handle_map, uint8_t *hal_module_id) { + + hal_ll_spi_pin_id index_list[SPI_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + uint16_t pin_check_result; + + // Check user-defined pins. + if ((pin_check_result = hal_ll_spi_master_check_pins(sck, miso, mosi, &index_list, handle_map)) == HAL_LL_PIN_NC) { + return HAL_LL_SPI_MASTER_WRONG_PINS; + }; + + // If user has come with the same SPI hardware module, and with the same pair of the pins, the pin mapping procedure + // will not have to take a place; otherwise, clear af-s, map new pins, set af-s, and set init state to false. + if ((hal_ll_spi_master_hw_specifics_map[pin_check_result].pins.sck.pin_name != sck) || + (hal_ll_spi_master_hw_specifics_map[pin_check_result].pins.miso.pin_name != miso) || + (hal_ll_spi_master_hw_specifics_map[pin_check_result].pins.mosi.pin_name != mosi) ) { + + hal_ll_spi_master_alternate_functions_set_state(&hal_ll_spi_master_hw_specifics_map[pin_check_result], false); + + hal_ll_spi_master_map_pins(pin_check_result, &index_list); + + hal_ll_spi_master_alternate_functions_set_state(&hal_ll_spi_master_hw_specifics_map[pin_check_result], true); + + handle_map[pin_check_result].init_ll_state = false; + } + + // Return id of the SPI module that is going to be used. + *hal_module_id = pin_check_result; + + // Insert current module into hal_ll_module_state map. + hal_ll_module_state[pin_check_result].hal_ll_spi_master_handle = (handle_t *)&hal_ll_spi_master_hw_specifics_map[pin_check_result].base; + + // Return the same info about module one level up ( into the HAL level ). + handle_map[pin_check_result].hal_ll_spi_master_handle = (handle_t*)&hal_ll_module_state[pin_check_result].hal_ll_spi_master_handle; + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_spi(handle_t *handle) { + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + hal_ll_spi_master_handle_register_t *hal_handle = (hal_ll_spi_master_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_spi_master_hw_specifics_map_local->module_index; + + hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_local); + + hal_ll_module_state[pin_check_result].hal_ll_spi_master_handle = (handle_t *)&hal_ll_spi_master_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +void hal_ll_spi_master_set_default_write_data(handle_t *handle, uint8_t dummy_data) { + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + if(hal_ll_spi_master_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR) { + hal_ll_spi_master_hw_specifics_map_local->dummy_data = dummy_data; + } +} + +hal_ll_err_t hal_ll_spi_master_write(handle_t *handle, uint8_t *write_data_buffer, size_t length_data) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + hal_ll_spi_master_write_bare_metal(hal_ll_spi_master_hw_specifics_map_local->base, write_data_buffer, length_data); + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_spi_master_read(handle_t *handle, uint8_t *read_data_buffer, size_t length_data) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + hal_ll_spi_master_read_bare_metal(hal_ll_spi_master_hw_specifics_map_local->base, read_data_buffer, length_data, hal_ll_spi_master_hw_specifics_map_local->dummy_data); + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_spi_master_write_then_read(handle_t *handle, uint8_t *write_data_buffer, size_t length_write_data, uint8_t *read_data_buffer, size_t length_read_data) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + hal_ll_spi_master_write_bare_metal(hal_ll_spi_master_hw_specifics_map_local->base, write_data_buffer, length_write_data); + + hal_ll_spi_master_read_bare_metal(hal_ll_spi_master_hw_specifics_map_local->base, read_data_buffer, length_read_data, hal_ll_spi_master_hw_specifics_map_local->dummy_data); + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +uint32_t hal_ll_spi_master_set_speed(handle_t *handle, uint32_t speed) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + low_level_handle->init_ll_state = false; + + // Insert user-defined baud rate into local map. + hal_ll_spi_master_hw_specifics_map_local->speed = speed; + + // Init once again, but with updated SPI Master baud rate value. + hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + // Return value of the SPI Master baud rate value. + return hal_ll_spi_master_hw_specifics_map_local->hw_actual_speed; +} + +hal_ll_err_t hal_ll_spi_master_set_mode(handle_t *handle, hal_ll_spi_master_mode_t mode) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + low_level_handle->init_ll_state = false; + + // Insert user-defined mode into local map. + hal_ll_spi_master_hw_specifics_map_local->mode = mode; + + // Init once again, but with updated SPI Master mode value. + hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +void hal_ll_spi_master_close(handle_t* handle) { + uint32_t dummy; + low_level_handle = hal_ll_spi_master_get_handle; + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + if(low_level_handle->hal_ll_spi_master_handle != NULL) { + low_level_handle->hal_ll_spi_master_handle = NULL; + low_level_handle->hal_drv_spi_master_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_spi_master_hw_specifics_map_local->mode = HAL_LL_SPI_MASTER_MODE_DEFAULT; + hal_ll_spi_master_hw_specifics_map_local->speed = HAL_LL_SPI_MASTER_SPEED_100K; + hal_ll_spi_master_hw_specifics_map_local->dummy_data = 0; + hal_ll_spi_master_hw_specifics_map_local->hw_actual_speed = 0; + + hal_ll_spi_master_set_clock(hal_ll_spi_master_hw_specifics_map_local, true, &dummy); + hal_ll_spi_master_alternate_functions_set_state(hal_ll_spi_master_hw_specifics_map_local, false); + hal_ll_spi_master_set_clock(hal_ll_spi_master_hw_specifics_map_local, false, &dummy); + + hal_ll_spi_master_hw_specifics_map_local->pins.sck.pin_name = HAL_LL_PIN_NC; + hal_ll_spi_master_hw_specifics_map_local->pins.miso.pin_name = HAL_LL_PIN_NC; + hal_ll_spi_master_hw_specifics_map_local->pins.mosi.pin_name = HAL_LL_PIN_NC; + hal_ll_spi_master_hw_specifics_map_local->pins.sck.pin_af = 0; + hal_ll_spi_master_hw_specifics_map_local->pins.miso.pin_af = 0; + hal_ll_spi_master_hw_specifics_map_local->pins.mosi.pin_af = 0; + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS + +uint8_t hal_ll_spi_master_transfer_bare_metal(hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t data_buffer) { + // Write user-defined data ( 'hal_ll_spi_master_read_bare_metal' procedure will send dummy data ). + *((volatile uint8_t *)&hal_ll_hw_reg->dr) = (uint8_t)data_buffer; // 8-bit data + + // Wait for receive buffer not empty status. + while (!(check_reg_bit( &(hal_ll_hw_reg->sr), HAL_LL_SPI_MASTER_RXNE))); + + // Return read data. + return *((volatile uint8_t *)&hal_ll_hw_reg->dr); // 8-bit data +} + +static void hal_ll_spi_master_write_bare_metal( hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *write_data_buffer, size_t write_data_length ) { + uint16_t transfer_counter = NULL; + + // Write the first data to be transmitted into the SPI_DR register. + for(transfer_counter = 0; transfer_counter < write_data_length; transfer_counter++) { + // If we are good to go ( if the tx buffer value has been shifted to the shift register ), write the data. + hal_ll_spi_master_transfer_bare_metal( hal_ll_hw_reg, write_data_buffer[transfer_counter]); + } +} + +static void hal_ll_spi_master_read_bare_metal(hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *read_data_buffer, size_t read_data_length, uint8_t dummy_data) { + uint16_t transfer_counter = NULL; + + // Read the first data to be transmitted into the SPI_DR register. + for(transfer_counter = 0; transfer_counter < read_data_length; transfer_counter++) { + // If we are good to go ( if the value from shift register has been shifted to the rx register ), read the data. + read_data_buffer[transfer_counter] = hal_ll_spi_master_transfer_bare_metal(hal_ll_hw_reg, dummy_data); + } +} + +static hal_ll_pin_name_t hal_ll_spi_master_check_pins(hal_ll_pin_name_t sck_pin, hal_ll_pin_name_t miso_pin, hal_ll_pin_name_t mosi_pin, hal_ll_spi_pin_id *index_list, hal_ll_spi_master_handle_register_t *handle_map) { + static const uint16_t sck_map_size = (sizeof(_spi_sck_map)) / (sizeof(hal_ll_spi_master_pin_map_t)); + static const uint16_t miso_map_size = (sizeof(_spi_miso_map)) / (sizeof(hal_ll_spi_master_pin_map_t)); + static const uint16_t mosi_map_size = (sizeof(_spi_mosi_map)) / (sizeof(hal_ll_spi_master_pin_map_t)); + uint8_t hal_ll_module_id = 0; + uint8_t index_counter = 0; + uint16_t miso_index; + uint16_t mosi_index; + uint16_t sck_index; + + if ( (HAL_LL_PIN_NC == sck_pin) || (HAL_LL_PIN_NC == miso_pin) || (HAL_LL_PIN_NC == mosi_pin) ) { + return HAL_LL_PIN_NC; + } + + // Check pins from the specific pin maps with the user defined pins. + for (sck_index = 0; sck_index < sck_map_size; sck_index++) { + if (_spi_sck_map[sck_index].pin == sck_pin) { + for (miso_index = 0; miso_index < miso_map_size; miso_index++) { + if (_spi_miso_map[miso_index].pin == miso_pin) { + if (_spi_sck_map[sck_index].module_index ==_spi_miso_map[miso_index].module_index) { + for (mosi_index = 0; mosi_index < mosi_map_size; mosi_index++) { + if (_spi_mosi_map[mosi_index ].pin == mosi_pin) { + if (_spi_sck_map[sck_index].module_index ==_spi_mosi_map[mosi_index].module_index) { + // Get module number + hal_ll_module_id = _spi_sck_map[ sck_index ].module_index; + + // Map pin names + index_list[hal_ll_module_id].pin_sck = sck_index; + index_list[hal_ll_module_id].pin_miso = miso_index; + index_list[hal_ll_module_id].pin_mosi = mosi_index; + + // Check if module is taken + if ( NULL == handle_map[hal_ll_module_id].hal_drv_spi_master_handle ) { + return hal_ll_module_id; + } else if ( SPI_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + } + } + } + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static void hal_ll_spi_master_map_pins(uint8_t module_index, hal_ll_spi_pin_id *index_list) { + // if every single pin is OK, insert them into this new map, and use this map in all low level functions. + hal_ll_spi_master_hw_specifics_map[module_index].pins.sck.pin_name = _spi_sck_map[index_list[module_index].pin_sck].pin; + hal_ll_spi_master_hw_specifics_map[module_index].pins.miso.pin_name = _spi_miso_map[index_list[module_index].pin_miso].pin; + hal_ll_spi_master_hw_specifics_map[module_index].pins.mosi.pin_name = _spi_mosi_map[index_list[module_index].pin_mosi].pin; + + // SCK, MISO and MOSI pins could have different alternate function settings, hence save all the AF-s. + hal_ll_spi_master_hw_specifics_map[module_index].pins.sck.pin_af = _spi_sck_map[index_list[module_index].pin_sck].af; + hal_ll_spi_master_hw_specifics_map[module_index].pins.miso.pin_af = _spi_miso_map[index_list[module_index].pin_miso].af; + hal_ll_spi_master_hw_specifics_map[module_index].pins.mosi.pin_af = _spi_mosi_map[index_list[module_index].pin_mosi].af; +} + +static hal_ll_spi_master_hw_specifics_map_t *hal_ll_get_specifics(handle_t handle) { + uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof( hal_ll_spi_master_handle_register_t)); + + static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof( hal_ll_spi_master_handle_register_t)); + + while (hal_ll_module_count--) { + if (hal_ll_spi_master_get_base_from_hal_handle == hal_ll_spi_master_hw_specifics_map[hal_ll_module_count].base) { + return &hal_ll_spi_master_hw_specifics_map[hal_ll_module_count]; + } + } + + // If NOK, return pointer to the last row of this map ( point to null pointer ). + return &hal_ll_spi_master_hw_specifics_map[hal_ll_module_error]; +} + +static void hal_ll_spi_master_set_clock(hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state, uint32_t *clock_value) { + rcc_clocks_t hal_ll_spi_clock_structure; + + RCC_GetClocksFrequency(&hal_ll_spi_clock_structure); + + switch (map->module_index) { + #if defined(SPI_MODULE_1) + case (hal_ll_spi_master_module_num(SPI_MODULE_1)): + if(hal_ll_state) { + set_reg_bit(_RCC_APB2ENR, HAL_LL_SPI1_MASTER_ENABLE); + } else { + clear_reg_bit(_RCC_APB2ENR, HAL_LL_SPI1_MASTER_ENABLE); + } + *clock_value = hal_ll_spi_clock_structure.pclk2; + break; + #endif + + #if defined(SPI_MODULE_2) + case (hal_ll_spi_master_module_num(SPI_MODULE_2)): + if(hal_ll_state) { + set_reg_bit(_RCC_APB1ENR1, HAL_LL_SPI2_MASTER_ENABLE); + } else { + clear_reg_bit(_RCC_APB1ENR1, HAL_LL_SPI2_MASTER_ENABLE); + } + *clock_value = hal_ll_spi_clock_structure.pclk1; + break; + #endif + + #if defined(SPI_MODULE_3) + case (hal_ll_spi_master_module_num(SPI_MODULE_3)): + if(hal_ll_state) { + set_reg_bit(_RCC_APB1ENR1, HAL_LL_SPI3_MASTER_ENABLE); + } else { + clear_reg_bit(_RCC_APB1ENR1, HAL_LL_SPI3_MASTER_ENABLE); + } + *clock_value = hal_ll_spi_clock_structure.pclk1; + break; + #endif + + #if defined(SPI_MODULE_4) + case (hal_ll_spi_master_module_num(SPI_MODULE_4)): + if(hal_ll_state) { + set_reg_bit(_RCC_APB2ENR, HAL_LL_SPI4_MASTER_ENABLE); + } else { + clear_reg_bit(_RCC_APB2ENR, HAL_LL_SPI4_MASTER_ENABLE); + } + *clock_value = hal_ll_spi_clock_structure.pclk2; + break; + #endif + + + } +} + +static void hal_ll_spi_master_alternate_functions_set_state(hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state) { + module_struct module; + uint32_t spi_config; + + if((map->pins.sck.pin_name != HAL_LL_PIN_NC) && (map->pins.miso.pin_name != HAL_LL_PIN_NC) && (map->pins.miso.pin_name != HAL_LL_PIN_NC)) { + module.pins[0] = VALUE(map->pins.sck.pin_name, map->pins.sck.pin_af); + module.pins[1] = VALUE(map->pins.miso.pin_name, map->pins.miso.pin_af); + module.pins[2] = VALUE(map->pins.mosi.pin_name, map->pins.mosi.pin_af); + module.pins[3] = GPIO_MODULE_STRUCT_END; + + spi_config = GPIO_CFG_MODE_ALT_FUNCTION | + GPIO_CFG_SPEED_HIGH | + GPIO_CFG_OTYPE_PP; + + module.configs[0] = spi_config; + module.configs[1] = spi_config; + module.configs[2] = spi_config; + module.configs[3] = GPIO_MODULE_STRUCT_END; + + module.gpio_remap = map->pins.sck.pin_af; + + hal_ll_gpio_module_struct_init(&module, hal_ll_state); + } +} + +static uint32_t hal_ll_spi_master_hw_init(hal_ll_spi_master_hw_specifics_map_t *map, uint32_t clock_value) { + uint32_t temp_speed; + + hal_ll_spi_master_base_handle_t *hal_ll_hw_reg = (hal_ll_spi_master_base_handle_t *)map->base; + + // Reset all the settings in control register. + hal_ll_hw_reg->cr1 = 0; + + // Populate appropriate register values to get appropriate data transfer baud rate prescalers. + temp_speed = hal_ll_spi_master_get_speed(clock_value, map->speed); + hal_ll_hw_reg->cr1 |= temp_speed; + + // Choose whether idle state for the clock is high level (1) or low level (0). + if (map->mode <= HAL_LL_SPI_MASTER_MODE_1) { + clear_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_CLK_POLARITY); + } else { + set_reg_bit(&( hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_CLK_POLARITY); + } + + // Choose whether transmit occurs on the transition from ACTIVE to IDLE (1), or vice versa (0). + if (map->mode == HAL_LL_SPI_MASTER_MODE_0 || map->mode == HAL_LL_SPI_MASTER_MODE_2) { + clear_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_CLK_PHASE); + } else { + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_CLK_PHASE); + } + + // Set default values for SPI Master configuration. + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_SSM_ENABLE); + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_SSI_1); + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_SELECTION); + + // Set Slave Select Output Enable bit. + set_reg_bit(&(hal_ll_hw_reg->cr2), HAL_LL_SPI_MASTER_SSOE_BIT); + + // Set FIFO reception threshold to 8-bit. + hal_ll_hw_reg->cr2 |= HAL_LL_SPI_MASTER_FRXTH; + + // Enable SPI peripheral. + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_ENABLE); + + return (hal_ll_spi_master_get_actual_speed(clock_value, temp_speed)); +} + +static void hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_t *map) { + uint32_t clock_value; + + // Enable specific clock module. + hal_ll_spi_master_set_clock (map, true, &clock_value); + + // Enable specific alternate functions. + hal_ll_spi_master_alternate_functions_set_state(map, true); + + // Finally, write user-defined settings into hardware registers. + hal_ll_spi_master_hw_init(map, clock_value); +} +// ------------------------------------------------------------------------- END + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_87/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_87/CMakeLists.cmake new file mode 100644 index 000000000..c02f31c41 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_87/CMakeLists.cmake @@ -0,0 +1,9 @@ +if(${MCU_NAME} MATCHES "^STM32G484CE$|^STM32G484ME$|^STM32G484PE$|^STM32G484RE$|^STM32G484QE$|^STM32G484VE$") + set(spi_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_spi_master.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_87") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_87") + list(APPEND hal_ll_def_list "STM32G4xx") + list(APPEND hal_ll_def_list "STM32G48xx") + list(APPEND hal_ll_def_list "STM32G484xx") + set(spi_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/spi_master/hal_ll_spi_master_pin_map/implementations/doc_ds_87") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_87/hal_ll_spi_master.c b/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_87/hal_ll_spi_master.c new file mode 100644 index 000000000..aabcbbc5d --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_87/hal_ll_spi_master.c @@ -0,0 +1,749 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_spi_master.c + * @brief SPI Master HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_rcc.h" +#include "hal_ll_spi_master.h" +#include "hal_ll_spi_master_pin_map.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_spi_master_handle_register_t hal_ll_module_state[SPI_MODULE_COUNT] = {(handle_t *)NULL, (handle_t *)NULL, false}; + +// ------------------------------------------------------------- PRIVATE MACROS + +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_spi_master_get_module_state_address ((hal_ll_spi_master_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_spi_master_get_handle (hal_ll_spi_master_handle_register_t *)hal_ll_spi_master_get_module_state_address->hal_ll_spi_master_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_spi_master_get_base_struct(_handle) ((hal_ll_spi_master_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_spi_master_get_base_from_hal_handle ((hal_ll_spi_master_hw_specifics_map_t *)((hal_ll_spi_master_handle_register_t *)\ + (((hal_ll_spi_master_handle_register_t *)(handle))->hal_ll_spi_master_handle))->hal_ll_spi_master_handle)->base + +/*!< CR1 constants. */ +#define HAL_LL_SPI_MASTER 0x4 +#define HAL_LL_SPI_MASTER_SSI_1 8 +#define HAL_LL_SPI_MASTER_SELECTION 2 +/*!< CR2 constants. */ +#define HAL_LL_SPI_MASTER_FRXTH 0x1000ul + +#define HAL_LL_SPI_MASTER_SSOE_BIT 2 +#define HAL_LL_SPI_MASTER_SSOE 0x4 +#define HAL_LL_SPI_MASTER_SSM_ENABLE 9 +#define HAL_LL_SPI_MASTER_SSM_DISABLE 0x0000u +#define HAL_LL_SPI_MASTER_SS_ENABLE 0x10000ul +#define HAL_LL_SPI_MASTER_SS_DISABLE 0x00000ul +/*!< SR constants. */ +#define HAL_LL_SPI_MASTER_RXNE 0 +#define HAL_LL_SPI_MASTER_TXE 1 +/*!< I2SCFGR constants. */ +#define HAL_LL_SPI_MASTER_I2SMOD 11 +/*!< Enable constants. */ +#define HAL_LL_SPI_MASTER_ENABLE 6 +#define HAL_LL_SPI1_MASTER_ENABLE 12 + +#define HAL_LL_SPI2_MASTER_ENABLE 14 + +#define HAL_LL_SPI3_MASTER_ENABLE 15 + +#define HAL_LL_SPI4_MASTER_ENABLE 15 + +/*!< General constants. */ +#define HAL_LL_SPI_MASTER_BAUD_RATE_MASK 3 +#define HAL_LL_SPI_MASTER_16_BIT_REG_SHIFT 16 +#define HAL_LL_SPI_MASTER_DEFAULT_BASE_ADDRESS 0xFF + +#define HAL_LL_SPI_MASTER_CLK_POLARITY 1 +#define HAL_LL_SPI_MASTER_CLK_PHASE 0 + +#define hal_ll_spi_master_get_speed(_fosc,_speed) (_speed >= _fosc/2)? (0):\ + ((_speed <= _fosc/2) && (_speed > _fosc/4))? (0):\ + ((_speed <= _fosc/4) && (_speed > _fosc/8))? (0x0008UL):\ + ((_speed <= _fosc/8) && (_speed > _fosc/16))? (0x0010UL):\ + ((_speed <= _fosc/16) && (_speed > _fosc/32))? (0x0018UL):\ + ((_speed <= _fosc/32) && (_speed > _fosc/64))? (0x0020UL):\ + ((_speed <= _fosc/64) && (_speed > _fosc/128))?(0x0028UL):\ + ((_speed <= _fosc/128)&& (_speed > _fosc/256))?(0x0030UL):(0x0038UL) + +#define hal_ll_spi_master_get_actual_speed(_fosc,_divider) (_divider == 0)?(_fosc/2):\ + (_divider == 0x0008UL)?(_fosc/4):\ + (_divider == 0x0010UL)?(_fosc/8):\ + (_divider == 0x0018UL)?(_fosc/16):\ + (_divider == 0x0020UL)?(_fosc/32):\ + (_divider == 0x0028UL)?(_fosc/64):\ + (_divider == 0x0030UL)?(_fosc/128):\ + (_divider == 0x0038UL)?(_fosc/256):(_fosc/256) + +/*!< @brief Default SPI Master bit-rate if no speed is set */ +#define HAL_LL_SPI_MASTER_SPEED_100K 100000 + +// -------------------------------------------------------------- PRIVATE TYPES + +/*!< @brief SPI register structure. */ +typedef struct { + uint32_t cr1; + uint32_t cr2; + uint32_t sr; + uint32_t dr; + uint32_t crcpr; + uint32_t rxcrcr; + uint32_t txcrcr; + uint32_t i2scfgr; + uint32_t i2spr; + +} hal_ll_spi_master_base_handle_t; + +/*!< @brief SPI Master hardware specific structure */ +typedef struct { + hal_ll_base_addr_t base; + uint8_t module_index; + hal_ll_spi_master_pins_t pins; + uint8_t dummy_data; + uint32_t speed; + uint32_t hw_actual_speed; + hal_ll_spi_master_mode_t mode; +} hal_ll_spi_master_hw_specifics_map_t; + +/*!< @brief SPI hw specific module values */ +typedef struct +{ + uint16_t pin_sck; + uint16_t pin_miso; + uint16_t pin_mosi; +} hal_ll_spi_pin_id; + +/*!< @brief SPI Master hw specific error values */ +typedef enum { + HAL_LL_SPI_MASTER_SUCCESS = 0, + HAL_LL_SPI_MASTER_WRONG_PINS, + HAL_LL_SPI_MASTER_MODULE_ERROR, + + HAL_LL_SPI_MASTER_ERROR = (-1) +} hal_ll_spi_master_err_t; + +// ------------------------------------------------------------------ VARIABLES + +/*!< @brief SPI Master hardware specific info */ +static hal_ll_spi_master_hw_specifics_map_t hal_ll_spi_master_hw_specifics_map[] = { + #ifdef SPI_MODULE_1 + {HAL_LL_SPI1_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_1), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, HAL_LL_SPI_MASTER_SPEED_100K, 0, HAL_LL_SPI_MASTER_MODE_DEFAULT}, + #endif + + #ifdef SPI_MODULE_2 + {HAL_LL_SPI2_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_2), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, HAL_LL_SPI_MASTER_SPEED_100K, 0, HAL_LL_SPI_MASTER_MODE_DEFAULT}, + #endif + + #ifdef SPI_MODULE_3 + {HAL_LL_SPI3_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_3), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, HAL_LL_SPI_MASTER_SPEED_100K, 0, HAL_LL_SPI_MASTER_MODE_DEFAULT}, + #endif + + #ifdef SPI_MODULE_4 + {HAL_LL_SPI4_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_4), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, HAL_LL_SPI_MASTER_SPEED_100K, 0, HAL_LL_SPI_MASTER_MODE_DEFAULT}, + #endif + + + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, 0, 0, 0} +}; + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_spi_master_handle_register_t *low_level_handle; +static volatile hal_ll_spi_master_hw_specifics_map_t *hal_ll_spi_master_hw_specifics_map_local; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Check if pins are adequate. + * + * Checks SCK, MISO and MOSI pins the user has passed with pre-defined + * pins in SCK, MISO and MOSI maps. Take into consideration that module + * index numbers have to be the same for both pins. + * + * @param[in] sck - SCK pre-defined pin name. + * @param[in] miso - MISO pre-defined pin name. + * @param[in] mosi - MOSI pre-defined pin name. + * @param[in] *index_list - Index list address + * @return hal_ll_pin_name_t Module index based on pins. + * + * Returns pre-defined module index from pin maps, if pins + * are adequate. + */ +static hal_ll_pin_name_t hal_ll_spi_master_check_pins(hal_ll_pin_name_t sck, hal_ll_pin_name_t miso, hal_ll_pin_name_t mosi, hal_ll_spi_pin_id *index_list, hal_ll_spi_master_handle_register_t *handle_map ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_spi_master_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_spi_master_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_spi_master_hw_specifics_map_t *hal_ll_get_specifics(handle_t handle); + +/** + * @brief Enable clock for SPI Master module on hardware level. + * + * Initializes SPI Master module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] *map - Object specific context handler. + * @param[in] hal_ll_state - True(enable clock)/False(disable clock). + * @param[in] *clock_value - SPI Master baud rate value taken from a specific peripheral clock bus. + * @return None + */ +static void hal_ll_spi_master_set_clock(hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state, uint32_t *clock_value); + +/** + * @brief Sets SPI Master pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if SPI is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param[in] *map - Object specific context handler. + * @param[in] hal_ll_state - Init/De-init + */ +static void hal_ll_spi_master_alternate_functions_set_state(hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state); + +/** + * @brief Full SPI Master module initialization procedure. + * + * Initializes SPI Master module on hardware level, based on beforehand + * set configuration and module handler. Sets adequate pin alternate functions. + * Initializes module clock. + * + * @param[in] *map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static void hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_t *map); + +/** + * @brief Perform a read on the SPI Master bus. + * + * Initializes SPI Master module on hardware level, if not initialized beforehand + * and continues to perform a read operation on the bus. + * + * @param[in] *map - Object specific context handler. + * @param[in] *read_data_buffer - Pointer to data buffer. + * @param[in] read_data_length - Number of data to be read. + * @param[in] dummy_data - Data required for read procedure. + * @return hal_ll_err_t Module specific error values. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +static void hal_ll_spi_master_read_bare_metal(hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *read_data_buffer, size_t read_data_length, uint8_t dummy_data); + +/** + * @brief Perform a write on the SPI Master bus. + * + * Initializes SPI Master module on hardware level, if not initialized beforehand + * and continues to perform a write operation on the bus. + * + * @param[in] map - Object specific context handler. + * @param[in] *write_data_buffer - Pointer to data buffer. + * @param[in] write_data_length - Number of data to be written. + * @return hal_ll_err_t Module specific error values. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +static void hal_ll_spi_master_write_bare_metal(hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *write_data_buffer, size_t write_data_length); + +/** + * @brief Perform a write then read on the SPI Master bus. + * + * Initializes SPI Master module on hardware level, if not initialized beforehand + * and continues to perform a write operation on the bus. + * + * @param[in] *handle - Object specific context handler. + * @param[in] *write_data_buffer - Pointer to data buffer. + * @param[in] length_write_data - Number of data to be written. + * @param[in] *read_data_buffer - Pointer to data buffer. + * @param[in] length_read_data - Number of data to be read. + * @return hal_ll_err_t Module specific error values. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_spi_master_write_then_read(handle_t *handle, uint8_t *write_data_buffer, size_t length_write_data, uint8_t *read_data_buffer, size_t length_read_data); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * SPI SCK, MISO and MOSI pins. + * + * @param[in] module_index SPI HW module index -- 0,1,2... + * @param[in] *index_list Array with SCK, MISO and MOSI map index values + * and module number + * + * @return None + */ +static void hal_ll_spi_master_map_pins(uint8_t module_index, hal_ll_spi_pin_id *index_list); + + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS + +hal_ll_err_t hal_ll_spi_master_register_handle(hal_ll_pin_name_t sck, hal_ll_pin_name_t miso, hal_ll_pin_name_t mosi, hal_ll_spi_master_handle_register_t *handle_map, uint8_t *hal_module_id) { + + hal_ll_spi_pin_id index_list[SPI_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + uint16_t pin_check_result; + + // Check user-defined pins. + if ((pin_check_result = hal_ll_spi_master_check_pins(sck, miso, mosi, &index_list, handle_map)) == HAL_LL_PIN_NC) { + return HAL_LL_SPI_MASTER_WRONG_PINS; + }; + + // If user has come with the same SPI hardware module, and with the same pair of the pins, the pin mapping procedure + // will not have to take a place; otherwise, clear af-s, map new pins, set af-s, and set init state to false. + if ((hal_ll_spi_master_hw_specifics_map[pin_check_result].pins.sck.pin_name != sck) || + (hal_ll_spi_master_hw_specifics_map[pin_check_result].pins.miso.pin_name != miso) || + (hal_ll_spi_master_hw_specifics_map[pin_check_result].pins.mosi.pin_name != mosi) ) { + + hal_ll_spi_master_alternate_functions_set_state(&hal_ll_spi_master_hw_specifics_map[pin_check_result], false); + + hal_ll_spi_master_map_pins(pin_check_result, &index_list); + + hal_ll_spi_master_alternate_functions_set_state(&hal_ll_spi_master_hw_specifics_map[pin_check_result], true); + + handle_map[pin_check_result].init_ll_state = false; + } + + // Return id of the SPI module that is going to be used. + *hal_module_id = pin_check_result; + + // Insert current module into hal_ll_module_state map. + hal_ll_module_state[pin_check_result].hal_ll_spi_master_handle = (handle_t *)&hal_ll_spi_master_hw_specifics_map[pin_check_result].base; + + // Return the same info about module one level up ( into the HAL level ). + handle_map[pin_check_result].hal_ll_spi_master_handle = (handle_t*)&hal_ll_module_state[pin_check_result].hal_ll_spi_master_handle; + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_spi(handle_t *handle) { + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + hal_ll_spi_master_handle_register_t *hal_handle = (hal_ll_spi_master_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_spi_master_hw_specifics_map_local->module_index; + + hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_local); + + hal_ll_module_state[pin_check_result].hal_ll_spi_master_handle = (handle_t *)&hal_ll_spi_master_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +void hal_ll_spi_master_set_default_write_data(handle_t *handle, uint8_t dummy_data) { + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + if(hal_ll_spi_master_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR) { + hal_ll_spi_master_hw_specifics_map_local->dummy_data = dummy_data; + } +} + +hal_ll_err_t hal_ll_spi_master_write(handle_t *handle, uint8_t *write_data_buffer, size_t length_data) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + hal_ll_spi_master_write_bare_metal(hal_ll_spi_master_hw_specifics_map_local->base, write_data_buffer, length_data); + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_spi_master_read(handle_t *handle, uint8_t *read_data_buffer, size_t length_data) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + hal_ll_spi_master_read_bare_metal(hal_ll_spi_master_hw_specifics_map_local->base, read_data_buffer, length_data, hal_ll_spi_master_hw_specifics_map_local->dummy_data); + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_spi_master_write_then_read(handle_t *handle, uint8_t *write_data_buffer, size_t length_write_data, uint8_t *read_data_buffer, size_t length_read_data) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + hal_ll_spi_master_write_bare_metal(hal_ll_spi_master_hw_specifics_map_local->base, write_data_buffer, length_write_data); + + hal_ll_spi_master_read_bare_metal(hal_ll_spi_master_hw_specifics_map_local->base, read_data_buffer, length_read_data, hal_ll_spi_master_hw_specifics_map_local->dummy_data); + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +uint32_t hal_ll_spi_master_set_speed(handle_t *handle, uint32_t speed) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + low_level_handle->init_ll_state = false; + + // Insert user-defined baud rate into local map. + hal_ll_spi_master_hw_specifics_map_local->speed = speed; + + // Init once again, but with updated SPI Master baud rate value. + hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + // Return value of the SPI Master baud rate value. + return hal_ll_spi_master_hw_specifics_map_local->hw_actual_speed; +} + +hal_ll_err_t hal_ll_spi_master_set_mode(handle_t *handle, hal_ll_spi_master_mode_t mode) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + low_level_handle->init_ll_state = false; + + // Insert user-defined mode into local map. + hal_ll_spi_master_hw_specifics_map_local->mode = mode; + + // Init once again, but with updated SPI Master mode value. + hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +void hal_ll_spi_master_close(handle_t* handle) { + uint32_t dummy; + low_level_handle = hal_ll_spi_master_get_handle; + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + if(low_level_handle->hal_ll_spi_master_handle != NULL) { + low_level_handle->hal_ll_spi_master_handle = NULL; + low_level_handle->hal_drv_spi_master_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_spi_master_hw_specifics_map_local->mode = HAL_LL_SPI_MASTER_MODE_DEFAULT; + hal_ll_spi_master_hw_specifics_map_local->speed = HAL_LL_SPI_MASTER_SPEED_100K; + hal_ll_spi_master_hw_specifics_map_local->dummy_data = 0; + hal_ll_spi_master_hw_specifics_map_local->hw_actual_speed = 0; + + hal_ll_spi_master_set_clock(hal_ll_spi_master_hw_specifics_map_local, true, &dummy); + hal_ll_spi_master_alternate_functions_set_state(hal_ll_spi_master_hw_specifics_map_local, false); + hal_ll_spi_master_set_clock(hal_ll_spi_master_hw_specifics_map_local, false, &dummy); + + hal_ll_spi_master_hw_specifics_map_local->pins.sck.pin_name = HAL_LL_PIN_NC; + hal_ll_spi_master_hw_specifics_map_local->pins.miso.pin_name = HAL_LL_PIN_NC; + hal_ll_spi_master_hw_specifics_map_local->pins.mosi.pin_name = HAL_LL_PIN_NC; + hal_ll_spi_master_hw_specifics_map_local->pins.sck.pin_af = 0; + hal_ll_spi_master_hw_specifics_map_local->pins.miso.pin_af = 0; + hal_ll_spi_master_hw_specifics_map_local->pins.mosi.pin_af = 0; + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS + +uint8_t hal_ll_spi_master_transfer_bare_metal(hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t data_buffer) { + // Write user-defined data ( 'hal_ll_spi_master_read_bare_metal' procedure will send dummy data ). + *((volatile uint8_t *)&hal_ll_hw_reg->dr) = (uint8_t)data_buffer; // 8-bit data + + // Wait for receive buffer not empty status. + while (!(check_reg_bit( &(hal_ll_hw_reg->sr), HAL_LL_SPI_MASTER_RXNE))); + + // Return read data. + return *((volatile uint8_t *)&hal_ll_hw_reg->dr); // 8-bit data +} + +static void hal_ll_spi_master_write_bare_metal( hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *write_data_buffer, size_t write_data_length ) { + uint16_t transfer_counter = NULL; + + // Write the first data to be transmitted into the SPI_DR register. + for(transfer_counter = 0; transfer_counter < write_data_length; transfer_counter++) { + // If we are good to go ( if the tx buffer value has been shifted to the shift register ), write the data. + hal_ll_spi_master_transfer_bare_metal( hal_ll_hw_reg, write_data_buffer[transfer_counter]); + } +} + +static void hal_ll_spi_master_read_bare_metal(hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *read_data_buffer, size_t read_data_length, uint8_t dummy_data) { + uint16_t transfer_counter = NULL; + + // Read the first data to be transmitted into the SPI_DR register. + for(transfer_counter = 0; transfer_counter < read_data_length; transfer_counter++) { + // If we are good to go ( if the value from shift register has been shifted to the rx register ), read the data. + read_data_buffer[transfer_counter] = hal_ll_spi_master_transfer_bare_metal(hal_ll_hw_reg, dummy_data); + } +} + +static hal_ll_pin_name_t hal_ll_spi_master_check_pins(hal_ll_pin_name_t sck_pin, hal_ll_pin_name_t miso_pin, hal_ll_pin_name_t mosi_pin, hal_ll_spi_pin_id *index_list, hal_ll_spi_master_handle_register_t *handle_map) { + static const uint16_t sck_map_size = (sizeof(_spi_sck_map)) / (sizeof(hal_ll_spi_master_pin_map_t)); + static const uint16_t miso_map_size = (sizeof(_spi_miso_map)) / (sizeof(hal_ll_spi_master_pin_map_t)); + static const uint16_t mosi_map_size = (sizeof(_spi_mosi_map)) / (sizeof(hal_ll_spi_master_pin_map_t)); + uint8_t hal_ll_module_id = 0; + uint8_t index_counter = 0; + uint16_t miso_index; + uint16_t mosi_index; + uint16_t sck_index; + + if ( (HAL_LL_PIN_NC == sck_pin) || (HAL_LL_PIN_NC == miso_pin) || (HAL_LL_PIN_NC == mosi_pin) ) { + return HAL_LL_PIN_NC; + } + + // Check pins from the specific pin maps with the user defined pins. + for (sck_index = 0; sck_index < sck_map_size; sck_index++) { + if (_spi_sck_map[sck_index].pin == sck_pin) { + for (miso_index = 0; miso_index < miso_map_size; miso_index++) { + if (_spi_miso_map[miso_index].pin == miso_pin) { + if (_spi_sck_map[sck_index].module_index ==_spi_miso_map[miso_index].module_index) { + for (mosi_index = 0; mosi_index < mosi_map_size; mosi_index++) { + if (_spi_mosi_map[mosi_index ].pin == mosi_pin) { + if (_spi_sck_map[sck_index].module_index ==_spi_mosi_map[mosi_index].module_index) { + // Get module number + hal_ll_module_id = _spi_sck_map[ sck_index ].module_index; + + // Map pin names + index_list[hal_ll_module_id].pin_sck = sck_index; + index_list[hal_ll_module_id].pin_miso = miso_index; + index_list[hal_ll_module_id].pin_mosi = mosi_index; + + // Check if module is taken + if ( NULL == handle_map[hal_ll_module_id].hal_drv_spi_master_handle ) { + return hal_ll_module_id; + } else if ( SPI_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + } + } + } + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static void hal_ll_spi_master_map_pins(uint8_t module_index, hal_ll_spi_pin_id *index_list) { + // if every single pin is OK, insert them into this new map, and use this map in all low level functions. + hal_ll_spi_master_hw_specifics_map[module_index].pins.sck.pin_name = _spi_sck_map[index_list[module_index].pin_sck].pin; + hal_ll_spi_master_hw_specifics_map[module_index].pins.miso.pin_name = _spi_miso_map[index_list[module_index].pin_miso].pin; + hal_ll_spi_master_hw_specifics_map[module_index].pins.mosi.pin_name = _spi_mosi_map[index_list[module_index].pin_mosi].pin; + + // SCK, MISO and MOSI pins could have different alternate function settings, hence save all the AF-s. + hal_ll_spi_master_hw_specifics_map[module_index].pins.sck.pin_af = _spi_sck_map[index_list[module_index].pin_sck].af; + hal_ll_spi_master_hw_specifics_map[module_index].pins.miso.pin_af = _spi_miso_map[index_list[module_index].pin_miso].af; + hal_ll_spi_master_hw_specifics_map[module_index].pins.mosi.pin_af = _spi_mosi_map[index_list[module_index].pin_mosi].af; +} + +static hal_ll_spi_master_hw_specifics_map_t *hal_ll_get_specifics(handle_t handle) { + uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof( hal_ll_spi_master_handle_register_t)); + + static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof( hal_ll_spi_master_handle_register_t)); + + while (hal_ll_module_count--) { + if (hal_ll_spi_master_get_base_from_hal_handle == hal_ll_spi_master_hw_specifics_map[hal_ll_module_count].base) { + return &hal_ll_spi_master_hw_specifics_map[hal_ll_module_count]; + } + } + + // If NOK, return pointer to the last row of this map ( point to null pointer ). + return &hal_ll_spi_master_hw_specifics_map[hal_ll_module_error]; +} + +static void hal_ll_spi_master_set_clock(hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state, uint32_t *clock_value) { + rcc_clocks_t hal_ll_spi_clock_structure; + + RCC_GetClocksFrequency(&hal_ll_spi_clock_structure); + + switch (map->module_index) { + #if defined(SPI_MODULE_1) + case (hal_ll_spi_master_module_num(SPI_MODULE_1)): + if(hal_ll_state) { + set_reg_bit(_RCC_APB2ENR, HAL_LL_SPI1_MASTER_ENABLE); + } else { + clear_reg_bit(_RCC_APB2ENR, HAL_LL_SPI1_MASTER_ENABLE); + } + *clock_value = hal_ll_spi_clock_structure.pclk2; + break; + #endif + + #if defined(SPI_MODULE_2) + case (hal_ll_spi_master_module_num(SPI_MODULE_2)): + if(hal_ll_state) { + set_reg_bit(_RCC_APB1ENR1, HAL_LL_SPI2_MASTER_ENABLE); + } else { + clear_reg_bit(_RCC_APB1ENR1, HAL_LL_SPI2_MASTER_ENABLE); + } + *clock_value = hal_ll_spi_clock_structure.pclk1; + break; + #endif + + #if defined(SPI_MODULE_3) + case (hal_ll_spi_master_module_num(SPI_MODULE_3)): + if(hal_ll_state) { + set_reg_bit(_RCC_APB1ENR1, HAL_LL_SPI3_MASTER_ENABLE); + } else { + clear_reg_bit(_RCC_APB1ENR1, HAL_LL_SPI3_MASTER_ENABLE); + } + *clock_value = hal_ll_spi_clock_structure.pclk1; + break; + #endif + + #if defined(SPI_MODULE_4) + case (hal_ll_spi_master_module_num(SPI_MODULE_4)): + if(hal_ll_state) { + set_reg_bit(_RCC_APB2ENR, HAL_LL_SPI4_MASTER_ENABLE); + } else { + clear_reg_bit(_RCC_APB2ENR, HAL_LL_SPI4_MASTER_ENABLE); + } + *clock_value = hal_ll_spi_clock_structure.pclk2; + break; + #endif + + + } +} + +static void hal_ll_spi_master_alternate_functions_set_state(hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state) { + module_struct module; + uint32_t spi_config; + + if((map->pins.sck.pin_name != HAL_LL_PIN_NC) && (map->pins.miso.pin_name != HAL_LL_PIN_NC) && (map->pins.miso.pin_name != HAL_LL_PIN_NC)) { + module.pins[0] = VALUE(map->pins.sck.pin_name, map->pins.sck.pin_af); + module.pins[1] = VALUE(map->pins.miso.pin_name, map->pins.miso.pin_af); + module.pins[2] = VALUE(map->pins.mosi.pin_name, map->pins.mosi.pin_af); + module.pins[3] = GPIO_MODULE_STRUCT_END; + + spi_config = GPIO_CFG_MODE_ALT_FUNCTION | + GPIO_CFG_SPEED_HIGH | + GPIO_CFG_OTYPE_PP; + + module.configs[0] = spi_config; + module.configs[1] = spi_config; + module.configs[2] = spi_config; + module.configs[3] = GPIO_MODULE_STRUCT_END; + + module.gpio_remap = map->pins.sck.pin_af; + + hal_ll_gpio_module_struct_init(&module, hal_ll_state); + } +} + +static uint32_t hal_ll_spi_master_hw_init(hal_ll_spi_master_hw_specifics_map_t *map, uint32_t clock_value) { + uint32_t temp_speed; + + hal_ll_spi_master_base_handle_t *hal_ll_hw_reg = (hal_ll_spi_master_base_handle_t *)map->base; + + // Reset all the settings in control register. + hal_ll_hw_reg->cr1 = 0; + + // Populate appropriate register values to get appropriate data transfer baud rate prescalers. + temp_speed = hal_ll_spi_master_get_speed(clock_value, map->speed); + hal_ll_hw_reg->cr1 |= temp_speed; + + // Choose whether idle state for the clock is high level (1) or low level (0). + if (map->mode <= HAL_LL_SPI_MASTER_MODE_1) { + clear_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_CLK_POLARITY); + } else { + set_reg_bit(&( hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_CLK_POLARITY); + } + + // Choose whether transmit occurs on the transition from ACTIVE to IDLE (1), or vice versa (0). + if (map->mode == HAL_LL_SPI_MASTER_MODE_0 || map->mode == HAL_LL_SPI_MASTER_MODE_2) { + clear_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_CLK_PHASE); + } else { + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_CLK_PHASE); + } + + // Set default values for SPI Master configuration. + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_SSM_ENABLE); + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_SSI_1); + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_SELECTION); + + // Set Slave Select Output Enable bit. + set_reg_bit(&(hal_ll_hw_reg->cr2), HAL_LL_SPI_MASTER_SSOE_BIT); + + // Set FIFO reception threshold to 8-bit. + hal_ll_hw_reg->cr2 |= HAL_LL_SPI_MASTER_FRXTH; + + // Enable SPI peripheral. + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_ENABLE); + + return (hal_ll_spi_master_get_actual_speed(clock_value, temp_speed)); +} + +static void hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_t *map) { + uint32_t clock_value; + + // Enable specific clock module. + hal_ll_spi_master_set_clock (map, true, &clock_value); + + // Enable specific alternate functions. + hal_ll_spi_master_alternate_functions_set_state(map, true); + + // Finally, write user-defined settings into hardware registers. + hal_ll_spi_master_hw_init(map, clock_value); +} +// ------------------------------------------------------------------------- END + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_88/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_88/CMakeLists.cmake new file mode 100644 index 000000000..adc8aebf0 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_88/CMakeLists.cmake @@ -0,0 +1,9 @@ +if(${MCU_NAME} MATCHES "^STM32G491CC$|^STM32G491KC$|^STM32G491RC$|^STM32G491VC$|^STM32G491MC$|^STM32G491CE$|^STM32G491KE$|^STM32G491RE$|^STM32G491VE$|^STM32G491ME$") + set(spi_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_spi_master.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_88") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_88") + list(APPEND hal_ll_def_list "STM32G4xx") + list(APPEND hal_ll_def_list "STM32G49xx") + list(APPEND hal_ll_def_list "STM32G491xx") + set(spi_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/spi_master/hal_ll_spi_master_pin_map/implementations/doc_ds_88") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_88/hal_ll_spi_master.c b/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_88/hal_ll_spi_master.c new file mode 100644 index 000000000..557d57519 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_88/hal_ll_spi_master.c @@ -0,0 +1,732 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_spi_master.c + * @brief SPI Master HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_rcc.h" +#include "hal_ll_spi_master.h" +#include "hal_ll_spi_master_pin_map.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_spi_master_handle_register_t hal_ll_module_state[SPI_MODULE_COUNT] = {(handle_t *)NULL, (handle_t *)NULL, false}; + +// ------------------------------------------------------------- PRIVATE MACROS + +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_spi_master_get_module_state_address ((hal_ll_spi_master_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_spi_master_get_handle (hal_ll_spi_master_handle_register_t *)hal_ll_spi_master_get_module_state_address->hal_ll_spi_master_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_spi_master_get_base_struct(_handle) ((hal_ll_spi_master_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_spi_master_get_base_from_hal_handle ((hal_ll_spi_master_hw_specifics_map_t *)((hal_ll_spi_master_handle_register_t *)\ + (((hal_ll_spi_master_handle_register_t *)(handle))->hal_ll_spi_master_handle))->hal_ll_spi_master_handle)->base + +/*!< CR1 constants. */ +#define HAL_LL_SPI_MASTER 0x4 +#define HAL_LL_SPI_MASTER_SSI_1 8 +#define HAL_LL_SPI_MASTER_SELECTION 2 +/*!< CR2 constants. */ +#define HAL_LL_SPI_MASTER_FRXTH 0x1000ul + +#define HAL_LL_SPI_MASTER_SSOE_BIT 2 +#define HAL_LL_SPI_MASTER_SSOE 0x4 +#define HAL_LL_SPI_MASTER_SSM_ENABLE 9 +#define HAL_LL_SPI_MASTER_SSM_DISABLE 0x0000u +#define HAL_LL_SPI_MASTER_SS_ENABLE 0x10000ul +#define HAL_LL_SPI_MASTER_SS_DISABLE 0x00000ul +/*!< SR constants. */ +#define HAL_LL_SPI_MASTER_RXNE 0 +#define HAL_LL_SPI_MASTER_TXE 1 +/*!< I2SCFGR constants. */ +#define HAL_LL_SPI_MASTER_I2SMOD 11 +/*!< Enable constants. */ +#define HAL_LL_SPI_MASTER_ENABLE 6 +#define HAL_LL_SPI1_MASTER_ENABLE 12 + +#define HAL_LL_SPI2_MASTER_ENABLE 14 + +#define HAL_LL_SPI3_MASTER_ENABLE 15 + +/*!< General constants. */ +#define HAL_LL_SPI_MASTER_BAUD_RATE_MASK 3 +#define HAL_LL_SPI_MASTER_16_BIT_REG_SHIFT 16 +#define HAL_LL_SPI_MASTER_DEFAULT_BASE_ADDRESS 0xFF + +#define HAL_LL_SPI_MASTER_CLK_POLARITY 1 +#define HAL_LL_SPI_MASTER_CLK_PHASE 0 + +#define hal_ll_spi_master_get_speed(_fosc,_speed) (_speed >= _fosc/2)? (0):\ + ((_speed <= _fosc/2) && (_speed > _fosc/4))? (0):\ + ((_speed <= _fosc/4) && (_speed > _fosc/8))? (0x0008UL):\ + ((_speed <= _fosc/8) && (_speed > _fosc/16))? (0x0010UL):\ + ((_speed <= _fosc/16) && (_speed > _fosc/32))? (0x0018UL):\ + ((_speed <= _fosc/32) && (_speed > _fosc/64))? (0x0020UL):\ + ((_speed <= _fosc/64) && (_speed > _fosc/128))?(0x0028UL):\ + ((_speed <= _fosc/128)&& (_speed > _fosc/256))?(0x0030UL):(0x0038UL) + +#define hal_ll_spi_master_get_actual_speed(_fosc,_divider) (_divider == 0)?(_fosc/2):\ + (_divider == 0x0008UL)?(_fosc/4):\ + (_divider == 0x0010UL)?(_fosc/8):\ + (_divider == 0x0018UL)?(_fosc/16):\ + (_divider == 0x0020UL)?(_fosc/32):\ + (_divider == 0x0028UL)?(_fosc/64):\ + (_divider == 0x0030UL)?(_fosc/128):\ + (_divider == 0x0038UL)?(_fosc/256):(_fosc/256) + +/*!< @brief Default SPI Master bit-rate if no speed is set */ +#define HAL_LL_SPI_MASTER_SPEED_100K 100000 + +// -------------------------------------------------------------- PRIVATE TYPES + +/*!< @brief SPI register structure. */ +typedef struct { + uint32_t cr1; + uint32_t cr2; + uint32_t sr; + uint32_t dr; + uint32_t crcpr; + uint32_t rxcrcr; + uint32_t txcrcr; + uint32_t i2scfgr; + uint32_t i2spr; + +} hal_ll_spi_master_base_handle_t; + +/*!< @brief SPI Master hardware specific structure */ +typedef struct { + hal_ll_base_addr_t base; + uint8_t module_index; + hal_ll_spi_master_pins_t pins; + uint8_t dummy_data; + uint32_t speed; + uint32_t hw_actual_speed; + hal_ll_spi_master_mode_t mode; +} hal_ll_spi_master_hw_specifics_map_t; + +/*!< @brief SPI hw specific module values */ +typedef struct +{ + uint16_t pin_sck; + uint16_t pin_miso; + uint16_t pin_mosi; +} hal_ll_spi_pin_id; + +/*!< @brief SPI Master hw specific error values */ +typedef enum { + HAL_LL_SPI_MASTER_SUCCESS = 0, + HAL_LL_SPI_MASTER_WRONG_PINS, + HAL_LL_SPI_MASTER_MODULE_ERROR, + + HAL_LL_SPI_MASTER_ERROR = (-1) +} hal_ll_spi_master_err_t; + +// ------------------------------------------------------------------ VARIABLES + +/*!< @brief SPI Master hardware specific info */ +static hal_ll_spi_master_hw_specifics_map_t hal_ll_spi_master_hw_specifics_map[] = { + #ifdef SPI_MODULE_1 + {HAL_LL_SPI1_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_1), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, HAL_LL_SPI_MASTER_SPEED_100K, 0, HAL_LL_SPI_MASTER_MODE_DEFAULT}, + #endif + + #ifdef SPI_MODULE_2 + {HAL_LL_SPI2_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_2), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, HAL_LL_SPI_MASTER_SPEED_100K, 0, HAL_LL_SPI_MASTER_MODE_DEFAULT}, + #endif + + #ifdef SPI_MODULE_3 + {HAL_LL_SPI3_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_3), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, HAL_LL_SPI_MASTER_SPEED_100K, 0, HAL_LL_SPI_MASTER_MODE_DEFAULT}, + #endif + + + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, 0, 0, 0} +}; + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_spi_master_handle_register_t *low_level_handle; +static volatile hal_ll_spi_master_hw_specifics_map_t *hal_ll_spi_master_hw_specifics_map_local; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Check if pins are adequate. + * + * Checks SCK, MISO and MOSI pins the user has passed with pre-defined + * pins in SCK, MISO and MOSI maps. Take into consideration that module + * index numbers have to be the same for both pins. + * + * @param[in] sck - SCK pre-defined pin name. + * @param[in] miso - MISO pre-defined pin name. + * @param[in] mosi - MOSI pre-defined pin name. + * @param[in] *index_list - Index list address + * @return hal_ll_pin_name_t Module index based on pins. + * + * Returns pre-defined module index from pin maps, if pins + * are adequate. + */ +static hal_ll_pin_name_t hal_ll_spi_master_check_pins(hal_ll_pin_name_t sck, hal_ll_pin_name_t miso, hal_ll_pin_name_t mosi, hal_ll_spi_pin_id *index_list, hal_ll_spi_master_handle_register_t *handle_map ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_spi_master_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_spi_master_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_spi_master_hw_specifics_map_t *hal_ll_get_specifics(handle_t handle); + +/** + * @brief Enable clock for SPI Master module on hardware level. + * + * Initializes SPI Master module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] *map - Object specific context handler. + * @param[in] hal_ll_state - True(enable clock)/False(disable clock). + * @param[in] *clock_value - SPI Master baud rate value taken from a specific peripheral clock bus. + * @return None + */ +static void hal_ll_spi_master_set_clock(hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state, uint32_t *clock_value); + +/** + * @brief Sets SPI Master pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if SPI is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param[in] *map - Object specific context handler. + * @param[in] hal_ll_state - Init/De-init + */ +static void hal_ll_spi_master_alternate_functions_set_state(hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state); + +/** + * @brief Full SPI Master module initialization procedure. + * + * Initializes SPI Master module on hardware level, based on beforehand + * set configuration and module handler. Sets adequate pin alternate functions. + * Initializes module clock. + * + * @param[in] *map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static void hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_t *map); + +/** + * @brief Perform a read on the SPI Master bus. + * + * Initializes SPI Master module on hardware level, if not initialized beforehand + * and continues to perform a read operation on the bus. + * + * @param[in] *map - Object specific context handler. + * @param[in] *read_data_buffer - Pointer to data buffer. + * @param[in] read_data_length - Number of data to be read. + * @param[in] dummy_data - Data required for read procedure. + * @return hal_ll_err_t Module specific error values. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +static void hal_ll_spi_master_read_bare_metal(hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *read_data_buffer, size_t read_data_length, uint8_t dummy_data); + +/** + * @brief Perform a write on the SPI Master bus. + * + * Initializes SPI Master module on hardware level, if not initialized beforehand + * and continues to perform a write operation on the bus. + * + * @param[in] map - Object specific context handler. + * @param[in] *write_data_buffer - Pointer to data buffer. + * @param[in] write_data_length - Number of data to be written. + * @return hal_ll_err_t Module specific error values. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +static void hal_ll_spi_master_write_bare_metal(hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *write_data_buffer, size_t write_data_length); + +/** + * @brief Perform a write then read on the SPI Master bus. + * + * Initializes SPI Master module on hardware level, if not initialized beforehand + * and continues to perform a write operation on the bus. + * + * @param[in] *handle - Object specific context handler. + * @param[in] *write_data_buffer - Pointer to data buffer. + * @param[in] length_write_data - Number of data to be written. + * @param[in] *read_data_buffer - Pointer to data buffer. + * @param[in] length_read_data - Number of data to be read. + * @return hal_ll_err_t Module specific error values. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_spi_master_write_then_read(handle_t *handle, uint8_t *write_data_buffer, size_t length_write_data, uint8_t *read_data_buffer, size_t length_read_data); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * SPI SCK, MISO and MOSI pins. + * + * @param[in] module_index SPI HW module index -- 0,1,2... + * @param[in] *index_list Array with SCK, MISO and MOSI map index values + * and module number + * + * @return None + */ +static void hal_ll_spi_master_map_pins(uint8_t module_index, hal_ll_spi_pin_id *index_list); + + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS + +hal_ll_err_t hal_ll_spi_master_register_handle(hal_ll_pin_name_t sck, hal_ll_pin_name_t miso, hal_ll_pin_name_t mosi, hal_ll_spi_master_handle_register_t *handle_map, uint8_t *hal_module_id) { + + hal_ll_spi_pin_id index_list[SPI_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + uint16_t pin_check_result; + + // Check user-defined pins. + if ((pin_check_result = hal_ll_spi_master_check_pins(sck, miso, mosi, &index_list, handle_map)) == HAL_LL_PIN_NC) { + return HAL_LL_SPI_MASTER_WRONG_PINS; + }; + + // If user has come with the same SPI hardware module, and with the same pair of the pins, the pin mapping procedure + // will not have to take a place; otherwise, clear af-s, map new pins, set af-s, and set init state to false. + if ((hal_ll_spi_master_hw_specifics_map[pin_check_result].pins.sck.pin_name != sck) || + (hal_ll_spi_master_hw_specifics_map[pin_check_result].pins.miso.pin_name != miso) || + (hal_ll_spi_master_hw_specifics_map[pin_check_result].pins.mosi.pin_name != mosi) ) { + + hal_ll_spi_master_alternate_functions_set_state(&hal_ll_spi_master_hw_specifics_map[pin_check_result], false); + + hal_ll_spi_master_map_pins(pin_check_result, &index_list); + + hal_ll_spi_master_alternate_functions_set_state(&hal_ll_spi_master_hw_specifics_map[pin_check_result], true); + + handle_map[pin_check_result].init_ll_state = false; + } + + // Return id of the SPI module that is going to be used. + *hal_module_id = pin_check_result; + + // Insert current module into hal_ll_module_state map. + hal_ll_module_state[pin_check_result].hal_ll_spi_master_handle = (handle_t *)&hal_ll_spi_master_hw_specifics_map[pin_check_result].base; + + // Return the same info about module one level up ( into the HAL level ). + handle_map[pin_check_result].hal_ll_spi_master_handle = (handle_t*)&hal_ll_module_state[pin_check_result].hal_ll_spi_master_handle; + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_spi(handle_t *handle) { + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + hal_ll_spi_master_handle_register_t *hal_handle = (hal_ll_spi_master_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_spi_master_hw_specifics_map_local->module_index; + + hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_local); + + hal_ll_module_state[pin_check_result].hal_ll_spi_master_handle = (handle_t *)&hal_ll_spi_master_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +void hal_ll_spi_master_set_default_write_data(handle_t *handle, uint8_t dummy_data) { + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + if(hal_ll_spi_master_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR) { + hal_ll_spi_master_hw_specifics_map_local->dummy_data = dummy_data; + } +} + +hal_ll_err_t hal_ll_spi_master_write(handle_t *handle, uint8_t *write_data_buffer, size_t length_data) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + hal_ll_spi_master_write_bare_metal(hal_ll_spi_master_hw_specifics_map_local->base, write_data_buffer, length_data); + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_spi_master_read(handle_t *handle, uint8_t *read_data_buffer, size_t length_data) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + hal_ll_spi_master_read_bare_metal(hal_ll_spi_master_hw_specifics_map_local->base, read_data_buffer, length_data, hal_ll_spi_master_hw_specifics_map_local->dummy_data); + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_spi_master_write_then_read(handle_t *handle, uint8_t *write_data_buffer, size_t length_write_data, uint8_t *read_data_buffer, size_t length_read_data) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + hal_ll_spi_master_write_bare_metal(hal_ll_spi_master_hw_specifics_map_local->base, write_data_buffer, length_write_data); + + hal_ll_spi_master_read_bare_metal(hal_ll_spi_master_hw_specifics_map_local->base, read_data_buffer, length_read_data, hal_ll_spi_master_hw_specifics_map_local->dummy_data); + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +uint32_t hal_ll_spi_master_set_speed(handle_t *handle, uint32_t speed) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + low_level_handle->init_ll_state = false; + + // Insert user-defined baud rate into local map. + hal_ll_spi_master_hw_specifics_map_local->speed = speed; + + // Init once again, but with updated SPI Master baud rate value. + hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + // Return value of the SPI Master baud rate value. + return hal_ll_spi_master_hw_specifics_map_local->hw_actual_speed; +} + +hal_ll_err_t hal_ll_spi_master_set_mode(handle_t *handle, hal_ll_spi_master_mode_t mode) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + low_level_handle->init_ll_state = false; + + // Insert user-defined mode into local map. + hal_ll_spi_master_hw_specifics_map_local->mode = mode; + + // Init once again, but with updated SPI Master mode value. + hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +void hal_ll_spi_master_close(handle_t* handle) { + uint32_t dummy; + low_level_handle = hal_ll_spi_master_get_handle; + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + if(low_level_handle->hal_ll_spi_master_handle != NULL) { + low_level_handle->hal_ll_spi_master_handle = NULL; + low_level_handle->hal_drv_spi_master_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_spi_master_hw_specifics_map_local->mode = HAL_LL_SPI_MASTER_MODE_DEFAULT; + hal_ll_spi_master_hw_specifics_map_local->speed = HAL_LL_SPI_MASTER_SPEED_100K; + hal_ll_spi_master_hw_specifics_map_local->dummy_data = 0; + hal_ll_spi_master_hw_specifics_map_local->hw_actual_speed = 0; + + hal_ll_spi_master_set_clock(hal_ll_spi_master_hw_specifics_map_local, true, &dummy); + hal_ll_spi_master_alternate_functions_set_state(hal_ll_spi_master_hw_specifics_map_local, false); + hal_ll_spi_master_set_clock(hal_ll_spi_master_hw_specifics_map_local, false, &dummy); + + hal_ll_spi_master_hw_specifics_map_local->pins.sck.pin_name = HAL_LL_PIN_NC; + hal_ll_spi_master_hw_specifics_map_local->pins.miso.pin_name = HAL_LL_PIN_NC; + hal_ll_spi_master_hw_specifics_map_local->pins.mosi.pin_name = HAL_LL_PIN_NC; + hal_ll_spi_master_hw_specifics_map_local->pins.sck.pin_af = 0; + hal_ll_spi_master_hw_specifics_map_local->pins.miso.pin_af = 0; + hal_ll_spi_master_hw_specifics_map_local->pins.mosi.pin_af = 0; + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS + +uint8_t hal_ll_spi_master_transfer_bare_metal(hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t data_buffer) { + // Write user-defined data ( 'hal_ll_spi_master_read_bare_metal' procedure will send dummy data ). + *((volatile uint8_t *)&hal_ll_hw_reg->dr) = (uint8_t)data_buffer; // 8-bit data + + // Wait for receive buffer not empty status. + while (!(check_reg_bit( &(hal_ll_hw_reg->sr), HAL_LL_SPI_MASTER_RXNE))); + + // Return read data. + return *((volatile uint8_t *)&hal_ll_hw_reg->dr); // 8-bit data +} + +static void hal_ll_spi_master_write_bare_metal( hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *write_data_buffer, size_t write_data_length ) { + uint16_t transfer_counter = NULL; + + // Write the first data to be transmitted into the SPI_DR register. + for(transfer_counter = 0; transfer_counter < write_data_length; transfer_counter++) { + // If we are good to go ( if the tx buffer value has been shifted to the shift register ), write the data. + hal_ll_spi_master_transfer_bare_metal( hal_ll_hw_reg, write_data_buffer[transfer_counter]); + } +} + +static void hal_ll_spi_master_read_bare_metal(hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *read_data_buffer, size_t read_data_length, uint8_t dummy_data) { + uint16_t transfer_counter = NULL; + + // Read the first data to be transmitted into the SPI_DR register. + for(transfer_counter = 0; transfer_counter < read_data_length; transfer_counter++) { + // If we are good to go ( if the value from shift register has been shifted to the rx register ), read the data. + read_data_buffer[transfer_counter] = hal_ll_spi_master_transfer_bare_metal(hal_ll_hw_reg, dummy_data); + } +} + +static hal_ll_pin_name_t hal_ll_spi_master_check_pins(hal_ll_pin_name_t sck_pin, hal_ll_pin_name_t miso_pin, hal_ll_pin_name_t mosi_pin, hal_ll_spi_pin_id *index_list, hal_ll_spi_master_handle_register_t *handle_map) { + static const uint16_t sck_map_size = (sizeof(_spi_sck_map)) / (sizeof(hal_ll_spi_master_pin_map_t)); + static const uint16_t miso_map_size = (sizeof(_spi_miso_map)) / (sizeof(hal_ll_spi_master_pin_map_t)); + static const uint16_t mosi_map_size = (sizeof(_spi_mosi_map)) / (sizeof(hal_ll_spi_master_pin_map_t)); + uint8_t hal_ll_module_id = 0; + uint8_t index_counter = 0; + uint16_t miso_index; + uint16_t mosi_index; + uint16_t sck_index; + + if ( (HAL_LL_PIN_NC == sck_pin) || (HAL_LL_PIN_NC == miso_pin) || (HAL_LL_PIN_NC == mosi_pin) ) { + return HAL_LL_PIN_NC; + } + + // Check pins from the specific pin maps with the user defined pins. + for (sck_index = 0; sck_index < sck_map_size; sck_index++) { + if (_spi_sck_map[sck_index].pin == sck_pin) { + for (miso_index = 0; miso_index < miso_map_size; miso_index++) { + if (_spi_miso_map[miso_index].pin == miso_pin) { + if (_spi_sck_map[sck_index].module_index ==_spi_miso_map[miso_index].module_index) { + for (mosi_index = 0; mosi_index < mosi_map_size; mosi_index++) { + if (_spi_mosi_map[mosi_index ].pin == mosi_pin) { + if (_spi_sck_map[sck_index].module_index ==_spi_mosi_map[mosi_index].module_index) { + // Get module number + hal_ll_module_id = _spi_sck_map[ sck_index ].module_index; + + // Map pin names + index_list[hal_ll_module_id].pin_sck = sck_index; + index_list[hal_ll_module_id].pin_miso = miso_index; + index_list[hal_ll_module_id].pin_mosi = mosi_index; + + // Check if module is taken + if ( NULL == handle_map[hal_ll_module_id].hal_drv_spi_master_handle ) { + return hal_ll_module_id; + } else if ( SPI_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + } + } + } + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static void hal_ll_spi_master_map_pins(uint8_t module_index, hal_ll_spi_pin_id *index_list) { + // if every single pin is OK, insert them into this new map, and use this map in all low level functions. + hal_ll_spi_master_hw_specifics_map[module_index].pins.sck.pin_name = _spi_sck_map[index_list[module_index].pin_sck].pin; + hal_ll_spi_master_hw_specifics_map[module_index].pins.miso.pin_name = _spi_miso_map[index_list[module_index].pin_miso].pin; + hal_ll_spi_master_hw_specifics_map[module_index].pins.mosi.pin_name = _spi_mosi_map[index_list[module_index].pin_mosi].pin; + + // SCK, MISO and MOSI pins could have different alternate function settings, hence save all the AF-s. + hal_ll_spi_master_hw_specifics_map[module_index].pins.sck.pin_af = _spi_sck_map[index_list[module_index].pin_sck].af; + hal_ll_spi_master_hw_specifics_map[module_index].pins.miso.pin_af = _spi_miso_map[index_list[module_index].pin_miso].af; + hal_ll_spi_master_hw_specifics_map[module_index].pins.mosi.pin_af = _spi_mosi_map[index_list[module_index].pin_mosi].af; +} + +static hal_ll_spi_master_hw_specifics_map_t *hal_ll_get_specifics(handle_t handle) { + uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof( hal_ll_spi_master_handle_register_t)); + + static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof( hal_ll_spi_master_handle_register_t)); + + while (hal_ll_module_count--) { + if (hal_ll_spi_master_get_base_from_hal_handle == hal_ll_spi_master_hw_specifics_map[hal_ll_module_count].base) { + return &hal_ll_spi_master_hw_specifics_map[hal_ll_module_count]; + } + } + + // If NOK, return pointer to the last row of this map ( point to null pointer ). + return &hal_ll_spi_master_hw_specifics_map[hal_ll_module_error]; +} + +static void hal_ll_spi_master_set_clock(hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state, uint32_t *clock_value) { + rcc_clocks_t hal_ll_spi_clock_structure; + + RCC_GetClocksFrequency(&hal_ll_spi_clock_structure); + + switch (map->module_index) { + #if defined(SPI_MODULE_1) + case (hal_ll_spi_master_module_num(SPI_MODULE_1)): + if(hal_ll_state) { + set_reg_bit(_RCC_APB2ENR, HAL_LL_SPI1_MASTER_ENABLE); + } else { + clear_reg_bit(_RCC_APB2ENR, HAL_LL_SPI1_MASTER_ENABLE); + } + *clock_value = hal_ll_spi_clock_structure.pclk2; + break; + #endif + + #if defined(SPI_MODULE_2) + case (hal_ll_spi_master_module_num(SPI_MODULE_2)): + if(hal_ll_state) { + set_reg_bit(_RCC_APB1ENR1, HAL_LL_SPI2_MASTER_ENABLE); + } else { + clear_reg_bit(_RCC_APB1ENR1, HAL_LL_SPI2_MASTER_ENABLE); + } + *clock_value = hal_ll_spi_clock_structure.pclk1; + break; + #endif + + #if defined(SPI_MODULE_3) + case (hal_ll_spi_master_module_num(SPI_MODULE_3)): + if(hal_ll_state) { + set_reg_bit(_RCC_APB1ENR1, HAL_LL_SPI3_MASTER_ENABLE); + } else { + clear_reg_bit(_RCC_APB1ENR1, HAL_LL_SPI3_MASTER_ENABLE); + } + *clock_value = hal_ll_spi_clock_structure.pclk1; + break; + #endif + + + } +} + +static void hal_ll_spi_master_alternate_functions_set_state(hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state) { + module_struct module; + uint32_t spi_config; + + if((map->pins.sck.pin_name != HAL_LL_PIN_NC) && (map->pins.miso.pin_name != HAL_LL_PIN_NC) && (map->pins.miso.pin_name != HAL_LL_PIN_NC)) { + module.pins[0] = VALUE(map->pins.sck.pin_name, map->pins.sck.pin_af); + module.pins[1] = VALUE(map->pins.miso.pin_name, map->pins.miso.pin_af); + module.pins[2] = VALUE(map->pins.mosi.pin_name, map->pins.mosi.pin_af); + module.pins[3] = GPIO_MODULE_STRUCT_END; + + spi_config = GPIO_CFG_MODE_ALT_FUNCTION | + GPIO_CFG_SPEED_HIGH | + GPIO_CFG_OTYPE_PP; + + module.configs[0] = spi_config; + module.configs[1] = spi_config; + module.configs[2] = spi_config; + module.configs[3] = GPIO_MODULE_STRUCT_END; + + module.gpio_remap = map->pins.sck.pin_af; + + hal_ll_gpio_module_struct_init(&module, hal_ll_state); + } +} + +static uint32_t hal_ll_spi_master_hw_init(hal_ll_spi_master_hw_specifics_map_t *map, uint32_t clock_value) { + uint32_t temp_speed; + + hal_ll_spi_master_base_handle_t *hal_ll_hw_reg = (hal_ll_spi_master_base_handle_t *)map->base; + + // Reset all the settings in control register. + hal_ll_hw_reg->cr1 = 0; + + // Populate appropriate register values to get appropriate data transfer baud rate prescalers. + temp_speed = hal_ll_spi_master_get_speed(clock_value, map->speed); + hal_ll_hw_reg->cr1 |= temp_speed; + + // Choose whether idle state for the clock is high level (1) or low level (0). + if (map->mode <= HAL_LL_SPI_MASTER_MODE_1) { + clear_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_CLK_POLARITY); + } else { + set_reg_bit(&( hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_CLK_POLARITY); + } + + // Choose whether transmit occurs on the transition from ACTIVE to IDLE (1), or vice versa (0). + if (map->mode == HAL_LL_SPI_MASTER_MODE_0 || map->mode == HAL_LL_SPI_MASTER_MODE_2) { + clear_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_CLK_PHASE); + } else { + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_CLK_PHASE); + } + + // Set default values for SPI Master configuration. + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_SSM_ENABLE); + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_SSI_1); + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_SELECTION); + + // Set Slave Select Output Enable bit. + set_reg_bit(&(hal_ll_hw_reg->cr2), HAL_LL_SPI_MASTER_SSOE_BIT); + + // Set FIFO reception threshold to 8-bit. + hal_ll_hw_reg->cr2 |= HAL_LL_SPI_MASTER_FRXTH; + + // Enable SPI peripheral. + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_ENABLE); + + return (hal_ll_spi_master_get_actual_speed(clock_value, temp_speed)); +} + +static void hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_t *map) { + uint32_t clock_value; + + // Enable specific clock module. + hal_ll_spi_master_set_clock (map, true, &clock_value); + + // Enable specific alternate functions. + hal_ll_spi_master_alternate_functions_set_state(map, true); + + // Finally, write user-defined settings into hardware registers. + hal_ll_spi_master_hw_init(map, clock_value); +} +// ------------------------------------------------------------------------- END + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_89/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_89/CMakeLists.cmake new file mode 100644 index 000000000..5c408dfa2 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_89/CMakeLists.cmake @@ -0,0 +1,9 @@ +if(${MCU_NAME} MATCHES "^STM32G4A1CE$|^STM32G4A1KE$|^STM32G4A1ME$|^STM32G4A1RE$|^STM32G4A1VE$") + set(spi_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_spi_master.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_89") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_89") + list(APPEND hal_ll_def_list "STM32G4xx") + list(APPEND hal_ll_def_list "STM32G4Axx") + list(APPEND hal_ll_def_list "STM32G4A1xx") + set(spi_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/spi_master/hal_ll_spi_master_pin_map/implementations/doc_ds_89") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_89/hal_ll_spi_master.c b/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_89/hal_ll_spi_master.c new file mode 100644 index 000000000..557d57519 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/spi_master/implementations/doc_ds_89/hal_ll_spi_master.c @@ -0,0 +1,732 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_spi_master.c + * @brief SPI Master HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_rcc.h" +#include "hal_ll_spi_master.h" +#include "hal_ll_spi_master_pin_map.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_spi_master_handle_register_t hal_ll_module_state[SPI_MODULE_COUNT] = {(handle_t *)NULL, (handle_t *)NULL, false}; + +// ------------------------------------------------------------- PRIVATE MACROS + +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_spi_master_get_module_state_address ((hal_ll_spi_master_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_spi_master_get_handle (hal_ll_spi_master_handle_register_t *)hal_ll_spi_master_get_module_state_address->hal_ll_spi_master_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_spi_master_get_base_struct(_handle) ((hal_ll_spi_master_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_spi_master_get_base_from_hal_handle ((hal_ll_spi_master_hw_specifics_map_t *)((hal_ll_spi_master_handle_register_t *)\ + (((hal_ll_spi_master_handle_register_t *)(handle))->hal_ll_spi_master_handle))->hal_ll_spi_master_handle)->base + +/*!< CR1 constants. */ +#define HAL_LL_SPI_MASTER 0x4 +#define HAL_LL_SPI_MASTER_SSI_1 8 +#define HAL_LL_SPI_MASTER_SELECTION 2 +/*!< CR2 constants. */ +#define HAL_LL_SPI_MASTER_FRXTH 0x1000ul + +#define HAL_LL_SPI_MASTER_SSOE_BIT 2 +#define HAL_LL_SPI_MASTER_SSOE 0x4 +#define HAL_LL_SPI_MASTER_SSM_ENABLE 9 +#define HAL_LL_SPI_MASTER_SSM_DISABLE 0x0000u +#define HAL_LL_SPI_MASTER_SS_ENABLE 0x10000ul +#define HAL_LL_SPI_MASTER_SS_DISABLE 0x00000ul +/*!< SR constants. */ +#define HAL_LL_SPI_MASTER_RXNE 0 +#define HAL_LL_SPI_MASTER_TXE 1 +/*!< I2SCFGR constants. */ +#define HAL_LL_SPI_MASTER_I2SMOD 11 +/*!< Enable constants. */ +#define HAL_LL_SPI_MASTER_ENABLE 6 +#define HAL_LL_SPI1_MASTER_ENABLE 12 + +#define HAL_LL_SPI2_MASTER_ENABLE 14 + +#define HAL_LL_SPI3_MASTER_ENABLE 15 + +/*!< General constants. */ +#define HAL_LL_SPI_MASTER_BAUD_RATE_MASK 3 +#define HAL_LL_SPI_MASTER_16_BIT_REG_SHIFT 16 +#define HAL_LL_SPI_MASTER_DEFAULT_BASE_ADDRESS 0xFF + +#define HAL_LL_SPI_MASTER_CLK_POLARITY 1 +#define HAL_LL_SPI_MASTER_CLK_PHASE 0 + +#define hal_ll_spi_master_get_speed(_fosc,_speed) (_speed >= _fosc/2)? (0):\ + ((_speed <= _fosc/2) && (_speed > _fosc/4))? (0):\ + ((_speed <= _fosc/4) && (_speed > _fosc/8))? (0x0008UL):\ + ((_speed <= _fosc/8) && (_speed > _fosc/16))? (0x0010UL):\ + ((_speed <= _fosc/16) && (_speed > _fosc/32))? (0x0018UL):\ + ((_speed <= _fosc/32) && (_speed > _fosc/64))? (0x0020UL):\ + ((_speed <= _fosc/64) && (_speed > _fosc/128))?(0x0028UL):\ + ((_speed <= _fosc/128)&& (_speed > _fosc/256))?(0x0030UL):(0x0038UL) + +#define hal_ll_spi_master_get_actual_speed(_fosc,_divider) (_divider == 0)?(_fosc/2):\ + (_divider == 0x0008UL)?(_fosc/4):\ + (_divider == 0x0010UL)?(_fosc/8):\ + (_divider == 0x0018UL)?(_fosc/16):\ + (_divider == 0x0020UL)?(_fosc/32):\ + (_divider == 0x0028UL)?(_fosc/64):\ + (_divider == 0x0030UL)?(_fosc/128):\ + (_divider == 0x0038UL)?(_fosc/256):(_fosc/256) + +/*!< @brief Default SPI Master bit-rate if no speed is set */ +#define HAL_LL_SPI_MASTER_SPEED_100K 100000 + +// -------------------------------------------------------------- PRIVATE TYPES + +/*!< @brief SPI register structure. */ +typedef struct { + uint32_t cr1; + uint32_t cr2; + uint32_t sr; + uint32_t dr; + uint32_t crcpr; + uint32_t rxcrcr; + uint32_t txcrcr; + uint32_t i2scfgr; + uint32_t i2spr; + +} hal_ll_spi_master_base_handle_t; + +/*!< @brief SPI Master hardware specific structure */ +typedef struct { + hal_ll_base_addr_t base; + uint8_t module_index; + hal_ll_spi_master_pins_t pins; + uint8_t dummy_data; + uint32_t speed; + uint32_t hw_actual_speed; + hal_ll_spi_master_mode_t mode; +} hal_ll_spi_master_hw_specifics_map_t; + +/*!< @brief SPI hw specific module values */ +typedef struct +{ + uint16_t pin_sck; + uint16_t pin_miso; + uint16_t pin_mosi; +} hal_ll_spi_pin_id; + +/*!< @brief SPI Master hw specific error values */ +typedef enum { + HAL_LL_SPI_MASTER_SUCCESS = 0, + HAL_LL_SPI_MASTER_WRONG_PINS, + HAL_LL_SPI_MASTER_MODULE_ERROR, + + HAL_LL_SPI_MASTER_ERROR = (-1) +} hal_ll_spi_master_err_t; + +// ------------------------------------------------------------------ VARIABLES + +/*!< @brief SPI Master hardware specific info */ +static hal_ll_spi_master_hw_specifics_map_t hal_ll_spi_master_hw_specifics_map[] = { + #ifdef SPI_MODULE_1 + {HAL_LL_SPI1_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_1), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, HAL_LL_SPI_MASTER_SPEED_100K, 0, HAL_LL_SPI_MASTER_MODE_DEFAULT}, + #endif + + #ifdef SPI_MODULE_2 + {HAL_LL_SPI2_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_2), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, HAL_LL_SPI_MASTER_SPEED_100K, 0, HAL_LL_SPI_MASTER_MODE_DEFAULT}, + #endif + + #ifdef SPI_MODULE_3 + {HAL_LL_SPI3_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_3), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, HAL_LL_SPI_MASTER_SPEED_100K, 0, HAL_LL_SPI_MASTER_MODE_DEFAULT}, + #endif + + + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, 0, 0, 0} +}; + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_spi_master_handle_register_t *low_level_handle; +static volatile hal_ll_spi_master_hw_specifics_map_t *hal_ll_spi_master_hw_specifics_map_local; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Check if pins are adequate. + * + * Checks SCK, MISO and MOSI pins the user has passed with pre-defined + * pins in SCK, MISO and MOSI maps. Take into consideration that module + * index numbers have to be the same for both pins. + * + * @param[in] sck - SCK pre-defined pin name. + * @param[in] miso - MISO pre-defined pin name. + * @param[in] mosi - MOSI pre-defined pin name. + * @param[in] *index_list - Index list address + * @return hal_ll_pin_name_t Module index based on pins. + * + * Returns pre-defined module index from pin maps, if pins + * are adequate. + */ +static hal_ll_pin_name_t hal_ll_spi_master_check_pins(hal_ll_pin_name_t sck, hal_ll_pin_name_t miso, hal_ll_pin_name_t mosi, hal_ll_spi_pin_id *index_list, hal_ll_spi_master_handle_register_t *handle_map ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_spi_master_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_spi_master_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_spi_master_hw_specifics_map_t *hal_ll_get_specifics(handle_t handle); + +/** + * @brief Enable clock for SPI Master module on hardware level. + * + * Initializes SPI Master module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] *map - Object specific context handler. + * @param[in] hal_ll_state - True(enable clock)/False(disable clock). + * @param[in] *clock_value - SPI Master baud rate value taken from a specific peripheral clock bus. + * @return None + */ +static void hal_ll_spi_master_set_clock(hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state, uint32_t *clock_value); + +/** + * @brief Sets SPI Master pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if SPI is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param[in] *map - Object specific context handler. + * @param[in] hal_ll_state - Init/De-init + */ +static void hal_ll_spi_master_alternate_functions_set_state(hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state); + +/** + * @brief Full SPI Master module initialization procedure. + * + * Initializes SPI Master module on hardware level, based on beforehand + * set configuration and module handler. Sets adequate pin alternate functions. + * Initializes module clock. + * + * @param[in] *map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static void hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_t *map); + +/** + * @brief Perform a read on the SPI Master bus. + * + * Initializes SPI Master module on hardware level, if not initialized beforehand + * and continues to perform a read operation on the bus. + * + * @param[in] *map - Object specific context handler. + * @param[in] *read_data_buffer - Pointer to data buffer. + * @param[in] read_data_length - Number of data to be read. + * @param[in] dummy_data - Data required for read procedure. + * @return hal_ll_err_t Module specific error values. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +static void hal_ll_spi_master_read_bare_metal(hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *read_data_buffer, size_t read_data_length, uint8_t dummy_data); + +/** + * @brief Perform a write on the SPI Master bus. + * + * Initializes SPI Master module on hardware level, if not initialized beforehand + * and continues to perform a write operation on the bus. + * + * @param[in] map - Object specific context handler. + * @param[in] *write_data_buffer - Pointer to data buffer. + * @param[in] write_data_length - Number of data to be written. + * @return hal_ll_err_t Module specific error values. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +static void hal_ll_spi_master_write_bare_metal(hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *write_data_buffer, size_t write_data_length); + +/** + * @brief Perform a write then read on the SPI Master bus. + * + * Initializes SPI Master module on hardware level, if not initialized beforehand + * and continues to perform a write operation on the bus. + * + * @param[in] *handle - Object specific context handler. + * @param[in] *write_data_buffer - Pointer to data buffer. + * @param[in] length_write_data - Number of data to be written. + * @param[in] *read_data_buffer - Pointer to data buffer. + * @param[in] length_read_data - Number of data to be read. + * @return hal_ll_err_t Module specific error values. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_spi_master_write_then_read(handle_t *handle, uint8_t *write_data_buffer, size_t length_write_data, uint8_t *read_data_buffer, size_t length_read_data); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * SPI SCK, MISO and MOSI pins. + * + * @param[in] module_index SPI HW module index -- 0,1,2... + * @param[in] *index_list Array with SCK, MISO and MOSI map index values + * and module number + * + * @return None + */ +static void hal_ll_spi_master_map_pins(uint8_t module_index, hal_ll_spi_pin_id *index_list); + + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS + +hal_ll_err_t hal_ll_spi_master_register_handle(hal_ll_pin_name_t sck, hal_ll_pin_name_t miso, hal_ll_pin_name_t mosi, hal_ll_spi_master_handle_register_t *handle_map, uint8_t *hal_module_id) { + + hal_ll_spi_pin_id index_list[SPI_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + uint16_t pin_check_result; + + // Check user-defined pins. + if ((pin_check_result = hal_ll_spi_master_check_pins(sck, miso, mosi, &index_list, handle_map)) == HAL_LL_PIN_NC) { + return HAL_LL_SPI_MASTER_WRONG_PINS; + }; + + // If user has come with the same SPI hardware module, and with the same pair of the pins, the pin mapping procedure + // will not have to take a place; otherwise, clear af-s, map new pins, set af-s, and set init state to false. + if ((hal_ll_spi_master_hw_specifics_map[pin_check_result].pins.sck.pin_name != sck) || + (hal_ll_spi_master_hw_specifics_map[pin_check_result].pins.miso.pin_name != miso) || + (hal_ll_spi_master_hw_specifics_map[pin_check_result].pins.mosi.pin_name != mosi) ) { + + hal_ll_spi_master_alternate_functions_set_state(&hal_ll_spi_master_hw_specifics_map[pin_check_result], false); + + hal_ll_spi_master_map_pins(pin_check_result, &index_list); + + hal_ll_spi_master_alternate_functions_set_state(&hal_ll_spi_master_hw_specifics_map[pin_check_result], true); + + handle_map[pin_check_result].init_ll_state = false; + } + + // Return id of the SPI module that is going to be used. + *hal_module_id = pin_check_result; + + // Insert current module into hal_ll_module_state map. + hal_ll_module_state[pin_check_result].hal_ll_spi_master_handle = (handle_t *)&hal_ll_spi_master_hw_specifics_map[pin_check_result].base; + + // Return the same info about module one level up ( into the HAL level ). + handle_map[pin_check_result].hal_ll_spi_master_handle = (handle_t*)&hal_ll_module_state[pin_check_result].hal_ll_spi_master_handle; + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_spi(handle_t *handle) { + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + hal_ll_spi_master_handle_register_t *hal_handle = (hal_ll_spi_master_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_spi_master_hw_specifics_map_local->module_index; + + hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_local); + + hal_ll_module_state[pin_check_result].hal_ll_spi_master_handle = (handle_t *)&hal_ll_spi_master_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +void hal_ll_spi_master_set_default_write_data(handle_t *handle, uint8_t dummy_data) { + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + if(hal_ll_spi_master_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR) { + hal_ll_spi_master_hw_specifics_map_local->dummy_data = dummy_data; + } +} + +hal_ll_err_t hal_ll_spi_master_write(handle_t *handle, uint8_t *write_data_buffer, size_t length_data) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + hal_ll_spi_master_write_bare_metal(hal_ll_spi_master_hw_specifics_map_local->base, write_data_buffer, length_data); + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_spi_master_read(handle_t *handle, uint8_t *read_data_buffer, size_t length_data) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + hal_ll_spi_master_read_bare_metal(hal_ll_spi_master_hw_specifics_map_local->base, read_data_buffer, length_data, hal_ll_spi_master_hw_specifics_map_local->dummy_data); + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_spi_master_write_then_read(handle_t *handle, uint8_t *write_data_buffer, size_t length_write_data, uint8_t *read_data_buffer, size_t length_read_data) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + hal_ll_spi_master_write_bare_metal(hal_ll_spi_master_hw_specifics_map_local->base, write_data_buffer, length_write_data); + + hal_ll_spi_master_read_bare_metal(hal_ll_spi_master_hw_specifics_map_local->base, read_data_buffer, length_read_data, hal_ll_spi_master_hw_specifics_map_local->dummy_data); + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +uint32_t hal_ll_spi_master_set_speed(handle_t *handle, uint32_t speed) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + low_level_handle->init_ll_state = false; + + // Insert user-defined baud rate into local map. + hal_ll_spi_master_hw_specifics_map_local->speed = speed; + + // Init once again, but with updated SPI Master baud rate value. + hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + // Return value of the SPI Master baud rate value. + return hal_ll_spi_master_hw_specifics_map_local->hw_actual_speed; +} + +hal_ll_err_t hal_ll_spi_master_set_mode(handle_t *handle, hal_ll_spi_master_mode_t mode) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + low_level_handle->init_ll_state = false; + + // Insert user-defined mode into local map. + hal_ll_spi_master_hw_specifics_map_local->mode = mode; + + // Init once again, but with updated SPI Master mode value. + hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +void hal_ll_spi_master_close(handle_t* handle) { + uint32_t dummy; + low_level_handle = hal_ll_spi_master_get_handle; + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address); + + if(low_level_handle->hal_ll_spi_master_handle != NULL) { + low_level_handle->hal_ll_spi_master_handle = NULL; + low_level_handle->hal_drv_spi_master_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_spi_master_hw_specifics_map_local->mode = HAL_LL_SPI_MASTER_MODE_DEFAULT; + hal_ll_spi_master_hw_specifics_map_local->speed = HAL_LL_SPI_MASTER_SPEED_100K; + hal_ll_spi_master_hw_specifics_map_local->dummy_data = 0; + hal_ll_spi_master_hw_specifics_map_local->hw_actual_speed = 0; + + hal_ll_spi_master_set_clock(hal_ll_spi_master_hw_specifics_map_local, true, &dummy); + hal_ll_spi_master_alternate_functions_set_state(hal_ll_spi_master_hw_specifics_map_local, false); + hal_ll_spi_master_set_clock(hal_ll_spi_master_hw_specifics_map_local, false, &dummy); + + hal_ll_spi_master_hw_specifics_map_local->pins.sck.pin_name = HAL_LL_PIN_NC; + hal_ll_spi_master_hw_specifics_map_local->pins.miso.pin_name = HAL_LL_PIN_NC; + hal_ll_spi_master_hw_specifics_map_local->pins.mosi.pin_name = HAL_LL_PIN_NC; + hal_ll_spi_master_hw_specifics_map_local->pins.sck.pin_af = 0; + hal_ll_spi_master_hw_specifics_map_local->pins.miso.pin_af = 0; + hal_ll_spi_master_hw_specifics_map_local->pins.mosi.pin_af = 0; + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS + +uint8_t hal_ll_spi_master_transfer_bare_metal(hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t data_buffer) { + // Write user-defined data ( 'hal_ll_spi_master_read_bare_metal' procedure will send dummy data ). + *((volatile uint8_t *)&hal_ll_hw_reg->dr) = (uint8_t)data_buffer; // 8-bit data + + // Wait for receive buffer not empty status. + while (!(check_reg_bit( &(hal_ll_hw_reg->sr), HAL_LL_SPI_MASTER_RXNE))); + + // Return read data. + return *((volatile uint8_t *)&hal_ll_hw_reg->dr); // 8-bit data +} + +static void hal_ll_spi_master_write_bare_metal( hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *write_data_buffer, size_t write_data_length ) { + uint16_t transfer_counter = NULL; + + // Write the first data to be transmitted into the SPI_DR register. + for(transfer_counter = 0; transfer_counter < write_data_length; transfer_counter++) { + // If we are good to go ( if the tx buffer value has been shifted to the shift register ), write the data. + hal_ll_spi_master_transfer_bare_metal( hal_ll_hw_reg, write_data_buffer[transfer_counter]); + } +} + +static void hal_ll_spi_master_read_bare_metal(hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *read_data_buffer, size_t read_data_length, uint8_t dummy_data) { + uint16_t transfer_counter = NULL; + + // Read the first data to be transmitted into the SPI_DR register. + for(transfer_counter = 0; transfer_counter < read_data_length; transfer_counter++) { + // If we are good to go ( if the value from shift register has been shifted to the rx register ), read the data. + read_data_buffer[transfer_counter] = hal_ll_spi_master_transfer_bare_metal(hal_ll_hw_reg, dummy_data); + } +} + +static hal_ll_pin_name_t hal_ll_spi_master_check_pins(hal_ll_pin_name_t sck_pin, hal_ll_pin_name_t miso_pin, hal_ll_pin_name_t mosi_pin, hal_ll_spi_pin_id *index_list, hal_ll_spi_master_handle_register_t *handle_map) { + static const uint16_t sck_map_size = (sizeof(_spi_sck_map)) / (sizeof(hal_ll_spi_master_pin_map_t)); + static const uint16_t miso_map_size = (sizeof(_spi_miso_map)) / (sizeof(hal_ll_spi_master_pin_map_t)); + static const uint16_t mosi_map_size = (sizeof(_spi_mosi_map)) / (sizeof(hal_ll_spi_master_pin_map_t)); + uint8_t hal_ll_module_id = 0; + uint8_t index_counter = 0; + uint16_t miso_index; + uint16_t mosi_index; + uint16_t sck_index; + + if ( (HAL_LL_PIN_NC == sck_pin) || (HAL_LL_PIN_NC == miso_pin) || (HAL_LL_PIN_NC == mosi_pin) ) { + return HAL_LL_PIN_NC; + } + + // Check pins from the specific pin maps with the user defined pins. + for (sck_index = 0; sck_index < sck_map_size; sck_index++) { + if (_spi_sck_map[sck_index].pin == sck_pin) { + for (miso_index = 0; miso_index < miso_map_size; miso_index++) { + if (_spi_miso_map[miso_index].pin == miso_pin) { + if (_spi_sck_map[sck_index].module_index ==_spi_miso_map[miso_index].module_index) { + for (mosi_index = 0; mosi_index < mosi_map_size; mosi_index++) { + if (_spi_mosi_map[mosi_index ].pin == mosi_pin) { + if (_spi_sck_map[sck_index].module_index ==_spi_mosi_map[mosi_index].module_index) { + // Get module number + hal_ll_module_id = _spi_sck_map[ sck_index ].module_index; + + // Map pin names + index_list[hal_ll_module_id].pin_sck = sck_index; + index_list[hal_ll_module_id].pin_miso = miso_index; + index_list[hal_ll_module_id].pin_mosi = mosi_index; + + // Check if module is taken + if ( NULL == handle_map[hal_ll_module_id].hal_drv_spi_master_handle ) { + return hal_ll_module_id; + } else if ( SPI_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + } + } + } + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static void hal_ll_spi_master_map_pins(uint8_t module_index, hal_ll_spi_pin_id *index_list) { + // if every single pin is OK, insert them into this new map, and use this map in all low level functions. + hal_ll_spi_master_hw_specifics_map[module_index].pins.sck.pin_name = _spi_sck_map[index_list[module_index].pin_sck].pin; + hal_ll_spi_master_hw_specifics_map[module_index].pins.miso.pin_name = _spi_miso_map[index_list[module_index].pin_miso].pin; + hal_ll_spi_master_hw_specifics_map[module_index].pins.mosi.pin_name = _spi_mosi_map[index_list[module_index].pin_mosi].pin; + + // SCK, MISO and MOSI pins could have different alternate function settings, hence save all the AF-s. + hal_ll_spi_master_hw_specifics_map[module_index].pins.sck.pin_af = _spi_sck_map[index_list[module_index].pin_sck].af; + hal_ll_spi_master_hw_specifics_map[module_index].pins.miso.pin_af = _spi_miso_map[index_list[module_index].pin_miso].af; + hal_ll_spi_master_hw_specifics_map[module_index].pins.mosi.pin_af = _spi_mosi_map[index_list[module_index].pin_mosi].af; +} + +static hal_ll_spi_master_hw_specifics_map_t *hal_ll_get_specifics(handle_t handle) { + uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof( hal_ll_spi_master_handle_register_t)); + + static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof( hal_ll_spi_master_handle_register_t)); + + while (hal_ll_module_count--) { + if (hal_ll_spi_master_get_base_from_hal_handle == hal_ll_spi_master_hw_specifics_map[hal_ll_module_count].base) { + return &hal_ll_spi_master_hw_specifics_map[hal_ll_module_count]; + } + } + + // If NOK, return pointer to the last row of this map ( point to null pointer ). + return &hal_ll_spi_master_hw_specifics_map[hal_ll_module_error]; +} + +static void hal_ll_spi_master_set_clock(hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state, uint32_t *clock_value) { + rcc_clocks_t hal_ll_spi_clock_structure; + + RCC_GetClocksFrequency(&hal_ll_spi_clock_structure); + + switch (map->module_index) { + #if defined(SPI_MODULE_1) + case (hal_ll_spi_master_module_num(SPI_MODULE_1)): + if(hal_ll_state) { + set_reg_bit(_RCC_APB2ENR, HAL_LL_SPI1_MASTER_ENABLE); + } else { + clear_reg_bit(_RCC_APB2ENR, HAL_LL_SPI1_MASTER_ENABLE); + } + *clock_value = hal_ll_spi_clock_structure.pclk2; + break; + #endif + + #if defined(SPI_MODULE_2) + case (hal_ll_spi_master_module_num(SPI_MODULE_2)): + if(hal_ll_state) { + set_reg_bit(_RCC_APB1ENR1, HAL_LL_SPI2_MASTER_ENABLE); + } else { + clear_reg_bit(_RCC_APB1ENR1, HAL_LL_SPI2_MASTER_ENABLE); + } + *clock_value = hal_ll_spi_clock_structure.pclk1; + break; + #endif + + #if defined(SPI_MODULE_3) + case (hal_ll_spi_master_module_num(SPI_MODULE_3)): + if(hal_ll_state) { + set_reg_bit(_RCC_APB1ENR1, HAL_LL_SPI3_MASTER_ENABLE); + } else { + clear_reg_bit(_RCC_APB1ENR1, HAL_LL_SPI3_MASTER_ENABLE); + } + *clock_value = hal_ll_spi_clock_structure.pclk1; + break; + #endif + + + } +} + +static void hal_ll_spi_master_alternate_functions_set_state(hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state) { + module_struct module; + uint32_t spi_config; + + if((map->pins.sck.pin_name != HAL_LL_PIN_NC) && (map->pins.miso.pin_name != HAL_LL_PIN_NC) && (map->pins.miso.pin_name != HAL_LL_PIN_NC)) { + module.pins[0] = VALUE(map->pins.sck.pin_name, map->pins.sck.pin_af); + module.pins[1] = VALUE(map->pins.miso.pin_name, map->pins.miso.pin_af); + module.pins[2] = VALUE(map->pins.mosi.pin_name, map->pins.mosi.pin_af); + module.pins[3] = GPIO_MODULE_STRUCT_END; + + spi_config = GPIO_CFG_MODE_ALT_FUNCTION | + GPIO_CFG_SPEED_HIGH | + GPIO_CFG_OTYPE_PP; + + module.configs[0] = spi_config; + module.configs[1] = spi_config; + module.configs[2] = spi_config; + module.configs[3] = GPIO_MODULE_STRUCT_END; + + module.gpio_remap = map->pins.sck.pin_af; + + hal_ll_gpio_module_struct_init(&module, hal_ll_state); + } +} + +static uint32_t hal_ll_spi_master_hw_init(hal_ll_spi_master_hw_specifics_map_t *map, uint32_t clock_value) { + uint32_t temp_speed; + + hal_ll_spi_master_base_handle_t *hal_ll_hw_reg = (hal_ll_spi_master_base_handle_t *)map->base; + + // Reset all the settings in control register. + hal_ll_hw_reg->cr1 = 0; + + // Populate appropriate register values to get appropriate data transfer baud rate prescalers. + temp_speed = hal_ll_spi_master_get_speed(clock_value, map->speed); + hal_ll_hw_reg->cr1 |= temp_speed; + + // Choose whether idle state for the clock is high level (1) or low level (0). + if (map->mode <= HAL_LL_SPI_MASTER_MODE_1) { + clear_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_CLK_POLARITY); + } else { + set_reg_bit(&( hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_CLK_POLARITY); + } + + // Choose whether transmit occurs on the transition from ACTIVE to IDLE (1), or vice versa (0). + if (map->mode == HAL_LL_SPI_MASTER_MODE_0 || map->mode == HAL_LL_SPI_MASTER_MODE_2) { + clear_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_CLK_PHASE); + } else { + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_CLK_PHASE); + } + + // Set default values for SPI Master configuration. + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_SSM_ENABLE); + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_SSI_1); + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_SELECTION); + + // Set Slave Select Output Enable bit. + set_reg_bit(&(hal_ll_hw_reg->cr2), HAL_LL_SPI_MASTER_SSOE_BIT); + + // Set FIFO reception threshold to 8-bit. + hal_ll_hw_reg->cr2 |= HAL_LL_SPI_MASTER_FRXTH; + + // Enable SPI peripheral. + set_reg_bit(&(hal_ll_hw_reg->cr1), HAL_LL_SPI_MASTER_ENABLE); + + return (hal_ll_spi_master_get_actual_speed(clock_value, temp_speed)); +} + +static void hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_t *map) { + uint32_t clock_value; + + // Enable specific clock module. + hal_ll_spi_master_set_clock (map, true, &clock_value); + + // Enable specific alternate functions. + hal_ll_spi_master_alternate_functions_set_state(map, true); + + // Finally, write user-defined settings into hardware registers. + hal_ll_spi_master_hw_init(map, clock_value); +} +// ------------------------------------------------------------------------- END + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/tim/CMakeLists.txt b/targets/arm/mikroe/ai_generated/stm32/src/tim/CMakeLists.txt new file mode 100644 index 000000000..34bb262e3 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/tim/CMakeLists.txt @@ -0,0 +1,74 @@ +## ./targets/arm/mikroe/ai_generated/stm32/src/tim/CMakeLists.txt + +## Check if current module is generated or not +set(MODULE_IS_GENERATED false) +get_files_recurse(${CMAKE_CURRENT_LIST_DIR}/implementations CMAKE_FILES cmake) +check_if_module_is_generated(MODULE_IS_GENERATED "${CMAKE_FILES}") + +## If current MCU has this module, add it +if(MODULE_IS_GENERATED) + set(hal_ll_def_list "") + set(mcu_header_path "") + + find_cortex(hal_ll_def_list) + list(APPEND hal_ll_def_list ${MCU_NAME}) + set(mcu_header_path ${MCU_NAME}_${_MSDK_PACKAGE_ID_}) + + ## BEGIN TIM + list(APPEND hal_ll_def_list "MACRO_USAGE_TIM") + + ## i.e "if (${MCU_NAME} MATCHES "^STM32C011F6$|^STM32C011C6$")" + ## List all MCUs and or them in the regex + foreach(cmakeFile ${CMAKE_FILES}) + include(${cmakeFile}) + endforeach() + ## END TIM + + mikrosdk_add_library(lib_hal_ll_tim MikroSDK.HalLowLevel.TIM + ${rcc_subimplementation}/hal_ll_rcc.h + ../../include/hal_ll_target.h + # BEGIN TIM + ${tim_subimplementation} + ../../include/tim/hal_ll_tim.h + ${tim_pin_map}/hal_ll_tim_pin_map.h + # END TIM + ) + + target_compile_definitions(lib_hal_ll_tim PUBLIC + ${hal_ll_def_list} + ) + + target_link_libraries(lib_hal_ll_tim PUBLIC + MikroC.Core + MikroSDK.HalLowLevelCore + MikroSDK.HalLowLevelCommon + ) + + string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) + target_include_directories(lib_hal_ll_tim + PRIVATE + ../../include + ../../include/gpio + ${gpio_subimplementation_include_dir} + # BEGIN TIM + ../../include/tim + ${tim_pin_map} + # END TIM + # BEGIN RCC + ${rcc_subimplementation} + # END RCC + INTERFACE + # BUILD + $ + $ + $ + $ + $ + # INSTALL + $ + $ + ) + + mikrosdk_install(MikroSDK.HalLowLevel.TIM) + install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.TIM ../../include/tim/hal_ll_tim.h) +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_1/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_1/CMakeLists.cmake new file mode 100644 index 000000000..2c9ef585a --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_1/CMakeLists.cmake @@ -0,0 +1,9 @@ +if(${MCU_NAME} MATCHES "^STM32C011F4$|^STM32C011J4$|^STM32C011F6$|^STM32C011J6$|^STM32C011D6$") + set(tim_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_tim.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_1") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_1") + list(APPEND hal_ll_def_list "STM32C0xx") + list(APPEND hal_ll_def_list "STM32C01xx") + list(APPEND hal_ll_def_list "STM32C011xx") + set(tim_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/tim/hal_ll_tim_pin_map/implementations/doc_ds_1") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_1/hal_ll_tim.c b/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_1/hal_ll_tim.c new file mode 100644 index 000000000..3df7728d6 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_1/hal_ll_tim.c @@ -0,0 +1,811 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_tim.c + * @brief TIM HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_gpio.h" +#include "hal_ll_rcc.h" +#include "hal_ll_tim.h" +#include "hal_ll_tim_pin_map.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_tim_handle_register_t hal_ll_module_state[ TIM_MODULE_COUNT ]; + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< CR1 constants. */ +#define HAL_LL_TIM_ENABLE_COUNTER_BIT 0 +#define HAL_LL_TIM_BDTR_MOE_BIT 15 +#define HAL_LL_TIM_BDTR_MOE 0x8000 + +#define HAL_LL_TIM_CCMR_CC2S_BIT0 0x100u +#define HAL_LL_TIM_CCMR_CC2S_BIT1 0x200u +#define HAL_LL_TIM_CCMR_OC2PE 0x800u +#define HAL_LL_TIM_CCMR_OC2M_BIT0 0x1000u +#define HAL_LL_TIM_CCMR_OC2M_BIT1 0x2000u +#define HAL_LL_TIM_CCMR_OC2M_BIT2 0x4000u + +#define HAL_LL_TIM_CCMR_CC3S_BIT0 0x1u +#define HAL_LL_TIM_CCMR_CC3S_BIT1 0x2u +#define HAL_LL_TIM_CCMR_OC3PE 0x8u +#define HAL_LL_TIM_CCMR_OC3M_BIT0 0x10u +#define HAL_LL_TIM_CCMR_OC3M_BIT1 0x20u +#define HAL_LL_TIM_CCMR_OC3M_BIT2 0x40u + +#define HAL_LL_TIM_CR1_DIR 0x10 +#define HAL_LL_TIM_CR1_DIR_BIT 4 + +#define HAL_LL_TIM_ENABLE_1 11 +#define HAL_LL_TIM_ENABLE_3 1 +#define HAL_LL_TIM_ENABLE_14 15 +#define HAL_LL_TIM_ENABLE_16 17 +#define HAL_LL_TIM_ENABLE_17 18 + +#define HAL_LL_APB1_TIMER_CLOCK 1 + +#define hal_ll_tim_channel_static( _chn ) ( _chn-1 ) + +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_tim_get_base_struct(_handle) ((hal_ll_tim_base_handle_t *)_handle) + +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_tim_get_module_state_address ((hal_ll_tim_handle_register_t *)*handle) + +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_tim_get_handle ( hal_ll_tim_handle_register_t * )hal_ll_tim_get_module_state_address->hal_ll_tim_handle + +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_tim_get_base_from_hal_handle ((hal_ll_tim_hw_specifics_map_t *)((hal_ll_tim_handle_register_t *)\ + (((hal_ll_tim_handle_register_t *)(handle))->hal_ll_tim_handle))->hal_ll_tim_handle)->base + +// -------------------------------------------------------------- PRIVATE TYPES +/*!< @brief TIM register structure. */ +typedef struct +{ + uint32_t cr1; /* Address offset 0x00 */ + uint32_t cr2; /* Address offset 0x04 */ + uint32_t smcr; /* Address offset 0x08 */ + uint32_t dier; /* Address offset 0x0C */ + uint32_t sr; /* Address offset 0x10 */ + uint32_t egr; /* Address offset 0x14 */ + uint32_t ccmr1; /* Address offset 0x18 */ + uint32_t ccmr2; /* Address offset 0x1C */ + uint32_t ccer; /* Address offset 0x20 */ + uint32_t cnt; /* Address offset 0x24 */ + uint32_t psc; /* Address offset 0x28 */ + uint32_t arr; /* Address offset 0x2C */ + uint32_t rcr; /* Address offset 0x30 */ + uint32_t ccr1; /* Address offset 0x34 */ + uint32_t ccr2; /* Address offset 0x38 */ + uint32_t ccr3; /* Address offset 0x3C */ + uint32_t ccr4; /* Address offset 0x40 */ + uint32_t bdtr; /* Address offset 0x44 */ + uint32_t dcr; /* Address offset 0x48 */ + uint32_t dmar; /* Address offset 0x4C */ + uint32_t tim2_5_or; /* Address offset 0x50 */ +} hal_ll_tim_base_handle_t; + +/*!< @brief TIM pin structure */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_channel_t channel; + uint32_t af; +} hal_ll_tim_t; + +/*!< @brief TIM hw specific structure */ +typedef struct +{ + hal_ll_base_addr_t base; + hal_ll_tim_t config; + uint16_t max_period; + uint32_t freq_hz; + hal_ll_pin_name_t module_index; +} hal_ll_tim_hw_specifics_map_t; + +/*!< @brief TIM hw specific error values */ +typedef enum +{ + HAL_LL_TIM_SUCCESS = 0, + HAL_LL_TIM_MODULE_ERROR, + HAL_LL_TIM_WRONG_PIN, + + HAL_LL_TIM_ERROR = (-1) +} hal_ll_tim_err_t; + +// ------------------------------------------------------------------ VARIABLES +/*!< @brief TIM specific info */ +static hal_ll_tim_hw_specifics_map_t hal_ll_tim_hw_specifics_map[] = +{ + #ifdef TIM_MODULE_1 + {HAL_LL_TIM1_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_1 - 1}, + #endif + #ifdef TIM_MODULE_3 + {HAL_LL_TIM3_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_3 - 1}, + #endif + #ifdef TIM_MODULE_14 + {HAL_LL_TIM14_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_14 - 1}, + #endif + #ifdef TIM_MODULE_16 + {HAL_LL_TIM16_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_16 - 1}, + #endif + #ifdef TIM_MODULE_17 + {HAL_LL_TIM17_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_17 - 1}, + #endif + {HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, HAL_LL_PIN_NC} +}; + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_tim_handle_register_t *low_level_handle; +static volatile hal_ll_tim_hw_specifics_map_t *hal_ll_tim_hw_specifics_map_local; + +static bool HAL_LL_TIM_IS_COMPLEMENTARY; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Enable TIM module 1 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim1_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 3 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim3_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 14 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim14_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 16 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim16_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 17 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim17_set_clock( bool hal_ll_state ); + + +/** + * @brief Enable TIM module gate clock. + * @param base - TIM module base + * address + * @return None + */ +static void _hal_ll_tim_set_clock( hal_ll_base_addr_t base, bool hal_ll_state ); + +/** + * @brief Select TIM clock source + * @param selector - clock source selector + * @return uint32_t - clock source + */ +static uint32_t _hal_ll_tim_clock_source( uint8_t selector ); + +/** + * @brief Based on selected TIM, + * return clock speed. + * @param base - TIM module base + * address + * @return uint32_t clock source. + */ +static uint32_t _hal_ll_tim_get_clock_speed( hal_ll_base_addr_t base ); + +/** + * @brief Initialize TIM module on hardware level. + * + * Initializes TIM module on hardware level, based on beforehand + * set configuration and module handler. + * + * @param map - Object specific context handler. + * @return none + * + */ +static void _hal_ll_tim_hw_init( hal_ll_tim_hw_specifics_map_t *map ); + +/** + * @brief Full TIM module initialization procedure. + * + * Initializes TIM module on hardware level, based on beforehand + * set configuration and module handler. Sets adequate pin alternate functions. + * Initializes module clock. + * + * @param map - Object specific context handler. + * @return none + * + */ +static void _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_t *map ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_tim_hw_specifics_map array index. + * + * @param handle - Object specific context handler. + * @return hal_ll_tim_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_tim_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Check if pin is adequate. + * + * Checks tim pin the user has passed with pre-defined + * pin in tim map. + * + * @param pin - TIM pre-defined pin name. + * @return hal_ll_pin_name_t Module index based on pin. + * + * Returns pre-defined module index from pin maps, if pin + * is adequate. + */ +static hal_ll_pin_name_t _hal_ll_tim_check_pin( hal_ll_pin_name_t pin, uint8_t *index, hal_ll_tim_handle_register_t *handle_map ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * TIM pin. + * + * @param[in] module_index TIM HW module index -- 0,1,2... + * @param[in] *index_list Array with TIM map index values + * + * @return None + */ +static void _hal_ll_tim_map_pin( uint8_t module_index, uint8_t index ); + +/** + * @brief Sets TIM pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if TIM is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param map - Object specific context handler. + * + * @param hal_ll_state - Init/De-init + * @return none + * + */ +static void _hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_map_t *map, bool hal_ll_state ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_tim_register_handle( hal_ll_pin_name_t pin, hal_ll_tim_handle_register_t *handle_map, + uint8_t *hal_module_id ) { + + uint8_t index; + uint16_t pin_check_result; + + if ( ( pin_check_result = _hal_ll_tim_check_pin( pin, &index, handle_map ) ) == HAL_LL_PIN_NC ) { + return HAL_LL_TIM_WRONG_PIN; + } + + if ( hal_ll_tim_hw_specifics_map[ pin_check_result ].config.pin != pin ){ + // Clear previous module alternate functions + _hal_ll_tim_alternate_functions_set_state( &hal_ll_tim_hw_specifics_map[ pin_check_result ], false ); + + _hal_ll_tim_map_pin( pin_check_result, index ); + + _hal_ll_tim_alternate_functions_set_state( &hal_ll_tim_hw_specifics_map[ pin_check_result ], true ); + + handle_map[ pin_check_result ].init_ll_state = false; + + hal_ll_module_state[ pin_check_result ].init_ll_state = false; + + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle = ( handle_t * )&hal_ll_tim_hw_specifics_map[ pin_check_result ].base; + + handle_map[ pin_check_result ].hal_ll_tim_handle = ( handle_t *)&hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle; + + return HAL_LL_TIM_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_tim( handle_t *handle ) { + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + hal_ll_tim_handle_register_t *hal_handle = (hal_ll_tim_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_tim_hw_specifics_map_local->module_index; + + _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_local ); + + hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle = (handle_t *)&hal_ll_tim_hw_specifics_map[ pin_check_result ].base; + hal_ll_module_state[ pin_check_result ].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_TIM_SUCCESS; +} + +uint32_t hal_ll_tim_set_freq( handle_t *handle, uint32_t freq_hz ) { + + uint32_t tmp_channel; + uint32_t ck_psc; + uint32_t local_base_addr; + uint32_t local_freq; + uint32_t tmp_freq; + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + if( hal_ll_tim_hw_specifics_map_local->base == HAL_LL_MODULE_ERROR ) { + return HAL_LL_TIM_MODULE_ERROR; + } + + low_level_handle->init_ll_state = false; + + tmp_channel = hal_ll_tim_hw_specifics_map_local->config.channel; + + // If complementary output channel is used. + if ( HAL_LL_TIM_IS_COMPLEMENTARY ) { + // Stop capture/compare. + hal_ll_hw_reg->ccer &= 1UL << tmp_channel * 4 + 2; + } else { + // Stop capture/compare. + hal_ll_hw_reg->ccer &= 1UL << tmp_channel * 4; + } + + // Set TIM duty to 0. + *( &hal_ll_hw_reg->ccr1 + hal_ll_tim_channel_static( tmp_channel ) ) = 0; + + hal_ll_tim_hw_specifics_map_local->freq_hz = freq_hz; + + local_freq = hal_ll_tim_hw_specifics_map_local->freq_hz; + local_base_addr = hal_ll_tim_hw_specifics_map_local->base; + + ck_psc = _hal_ll_tim_get_clock_speed( local_base_addr ) / local_freq; + + if ( ck_psc > UINT16_MAX ) { + tmp_freq = _hal_ll_tim_get_clock_speed( local_base_addr ) / UINT16_MAX; + hal_ll_tim_hw_specifics_map_local->freq_hz = tmp_freq; + } else { + tmp_freq = freq_hz; + hal_ll_tim_hw_specifics_map_local->freq_hz = freq_hz; + } + + _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_local ); + + low_level_handle->init_ll_state = true; + + return tmp_freq; +} + +hal_ll_err_t hal_ll_tim_set_duty( handle_t *handle, float duty_ratio ) { + + float tmp_duty; + uint32_t max_duty = 0; + uint16_t max_period; + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + if ( low_level_handle->init_ll_state == false ) { + hal_ll_tim_start( handle ); + low_level_handle->init_ll_state = true; + } + + tmp_duty = duty_ratio * 100; + max_period = hal_ll_tim_hw_specifics_map_local->max_period; + + max_duty = ( ( float )max_period / 100 ) * tmp_duty; + + *( &hal_ll_hw_reg->ccr1 + hal_ll_tim_channel_static( hal_ll_tim_hw_specifics_map_local->config.channel ) ) = max_duty; + + return HAL_LL_TIM_SUCCESS; +} + +hal_ll_err_t hal_ll_tim_start( handle_t *handle ) { + + uint32_t tmp_channel; + volatile uint32_t tmp, + *tmpPtr; + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + tmp_channel = hal_ll_tim_hw_specifics_map_local->config.channel; + + // Capture/Compare 1 output enable. + tmp = hal_ll_hw_reg->ccer; + + // If complementary output channel is used. + if ( HAL_LL_TIM_IS_COMPLEMENTARY ) { + // Capture/Compare complementary output enable + tmp |= ( 1UL << ( hal_ll_tim_channel_static( tmp_channel ) * 4 + 2 ) ); + // Capture/Compare complementary output polarity(ACTIVE HIGH). + tmp &= ~( 1UL << ( hal_ll_tim_channel_static( tmp_channel ) * 4 + 3 ) ); + } else { + // Capture/Compare output polarity. + tmp |= ( 1UL << ( hal_ll_tim_channel_static( tmp_channel ) * 4 ) ); + // Capture/Compare output polarity(ACTIVE HIGH). + tmp &= ~( 1UL << ( hal_ll_tim_channel_static( tmp_channel ) * 4 + 1 ) ); + } + + hal_ll_hw_reg->ccer = tmp; + + #if defined(TIM_MODULE_1) || defined(TIM_MODULE_8) || defined(TIM_MODULE_20) + // Main output enabled. + set_reg_bit( &hal_ll_hw_reg->bdtr, HAL_LL_TIM_BDTR_MOE_BIT ); + #endif + + tmpPtr = &hal_ll_hw_reg->ccmr1; + + if( hal_ll_tim_channel_static( tmp_channel ) > 1 ) { + tmpPtr = &hal_ll_hw_reg->ccmr2; + } + + if( ( hal_ll_tim_channel_static( tmp_channel ) / 2 ) * 2 != + hal_ll_tim_channel_static( tmp_channel ) ) { + // Clear CCxS, OCxM[0]. + *tmpPtr &= ~( HAL_LL_TIM_CCMR_CC2S_BIT0 | + HAL_LL_TIM_CCMR_CC2S_BIT1 | + HAL_LL_TIM_CCMR_OC2PE | + HAL_LL_TIM_CCMR_OC2M_BIT0 ); + // Set OCxM[2, 1] + *tmpPtr |= HAL_LL_TIM_CCMR_OC2M_BIT1 | HAL_LL_TIM_CCMR_OC2M_BIT2; + } else { + // Clear CCxS, OCxM[0]. + *tmpPtr &= ~( HAL_LL_TIM_CCMR_CC3S_BIT0 | + HAL_LL_TIM_CCMR_CC3S_BIT1 | + HAL_LL_TIM_CCMR_OC3PE | + HAL_LL_TIM_CCMR_OC3M_BIT0 ); + + // Set OCxM[2, 1]. + *tmpPtr |= HAL_LL_TIM_CCMR_OC3M_BIT1 | HAL_LL_TIM_CCMR_OC3M_BIT2; + } + + // Enable counter. + set_reg_bit( &hal_ll_hw_reg->cr1, HAL_LL_TIM_ENABLE_COUNTER_BIT ); + + return HAL_LL_TIM_SUCCESS; +} + +hal_ll_err_t hal_ll_tim_stop( handle_t *handle ) { + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + // If complementary output channel is used. + if ( HAL_LL_TIM_IS_COMPLEMENTARY ) { + hal_ll_hw_reg->ccer &= 1UL << hal_ll_tim_hw_specifics_map_local->config.channel * 4 + 2; + } else { + hal_ll_hw_reg->ccer &= 1UL << hal_ll_tim_hw_specifics_map_local->config.channel * 4; + } + + return HAL_LL_TIM_SUCCESS; +} + +void hal_ll_tim_close( handle_t *handle ) { + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_tim_get_module_state_address); + + if( low_level_handle->hal_ll_tim_handle != NULL ) { + low_level_handle->hal_ll_tim_handle = NULL; + low_level_handle->hal_drv_tim_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_tim_hw_specifics_map_local->max_period = 0; + hal_ll_tim_hw_specifics_map_local->freq_hz = 0; + + _hal_ll_tim_set_clock( hal_ll_tim_hw_specifics_map_local->base, true ); + _hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_map_local, false ); + _hal_ll_tim_set_clock( hal_ll_tim_hw_specifics_map_local->base, false ); + + hal_ll_tim_hw_specifics_map_local->config.pin = HAL_LL_PIN_NC; + hal_ll_tim_hw_specifics_map_local->config.channel = HAL_LL_PIN_NC; + hal_ll_tim_hw_specifics_map_local->config.af = NULL; + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static inline void _hal_ll_tim1_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APBENR2, HAL_LL_TIM_ENABLE_1 ); + } else { + clear_reg_bit( _RCC_APBENR2, HAL_LL_TIM_ENABLE_1 ); + } +} + +static inline void _hal_ll_tim3_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APBENR1, HAL_LL_TIM_ENABLE_3 ); + } else { + clear_reg_bit( _RCC_APBENR1, HAL_LL_TIM_ENABLE_3 ); + } +} + +static inline void _hal_ll_tim14_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APBENR2, HAL_LL_TIM_ENABLE_14 ); + } else { + clear_reg_bit( _RCC_APBENR2, HAL_LL_TIM_ENABLE_14 ); + } +} + +static inline void _hal_ll_tim16_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APBENR2, HAL_LL_TIM_ENABLE_16 ); + } else { + clear_reg_bit( _RCC_APBENR2, HAL_LL_TIM_ENABLE_16 ); + } +} + +static inline void _hal_ll_tim17_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APBENR2, HAL_LL_TIM_ENABLE_17 ); + } else { + clear_reg_bit( _RCC_APBENR2, HAL_LL_TIM_ENABLE_17 ); + } +} + +static hal_ll_pin_name_t _hal_ll_tim_check_pin( hal_ll_pin_name_t pin, uint8_t *index, hal_ll_tim_handle_register_t *handle_map ) { + + hal_ll_pin_name_t pin_num; + uint8_t index_counter = 0; + uint8_t hal_ll_module_id = 0; + uint16_t map_size = ( sizeof( _tim_map ) / sizeof( hal_ll_tim_pin_map_t ) ); + + if ( HAL_LL_PIN_NC == pin ) { + return HAL_LL_PIN_NC; + } + + // Check if the selected pin is valid. + for ( pin_num = 0; pin_num < map_size; pin_num++ ) { + if ( _tim_map[ pin_num ].pin == pin ) { + // Get module number + hal_ll_module_id = _tim_map[ pin_num ].module_index; + if ( NULL == handle_map[hal_ll_module_id].hal_drv_tim_handle ) { + *index = pin_num; + return hal_ll_module_id; + } else if ( TIM_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + // By default return last error msg. + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static hal_ll_tim_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + + uint8_t hal_ll_module_count = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_tim_handle_register_t ) ); + static uint8_t hal_ll_module_error = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_tim_handle_register_t ) ); + + while( hal_ll_module_count-- ) { + if ( hal_ll_tim_get_base_from_hal_handle == hal_ll_tim_hw_specifics_map [ hal_ll_module_count ].base) { + return &hal_ll_tim_hw_specifics_map[ hal_ll_module_count ]; + } + } + + return &hal_ll_tim_hw_specifics_map[ hal_ll_module_error ]; +} + +static void _hal_ll_tim_set_clock( hal_ll_base_addr_t base, bool hal_ll_state ) { + + switch ( ( uint32_t )base ) { // 32-bit base address. + #ifdef TIM_MODULE_1 + case ( HAL_LL_TIM1_BASE_ADDR ): + _hal_ll_tim1_set_clock( hal_ll_state ); + break; + #endif + #ifdef TIM_MODULE_3 + case ( HAL_LL_TIM3_BASE_ADDR ): + _hal_ll_tim3_set_clock( hal_ll_state ); + break; + #endif + #ifdef TIM_MODULE_14 + case ( HAL_LL_TIM14_BASE_ADDR ): + _hal_ll_tim14_set_clock( hal_ll_state ); + break; + #endif + #ifdef TIM_MODULE_16 + case ( HAL_LL_TIM16_BASE_ADDR ): + _hal_ll_tim16_set_clock( hal_ll_state ); + break; + #endif + #ifdef TIM_MODULE_17 + case ( HAL_LL_TIM17_BASE_ADDR ): + _hal_ll_tim17_set_clock( hal_ll_state ); + break; + #endif + } +} + +static uint32_t _hal_ll_tim_clock_source( uint8_t selector ) { + + rcc_clocks_t rcc_clocks; + + RCC_GetClocksFrequency( &rcc_clocks ); + + if( selector == HAL_LL_APB1_TIMER_CLOCK ) { + if( rcc_clocks.hclk/rcc_clocks.pclk > 1 ) { + return rcc_clocks.pclk * 2; + } else { + return rcc_clocks.pclk; + } + } + + return 0; +} + +static uint32_t _hal_ll_tim_get_clock_speed( hal_ll_base_addr_t base ) { + + switch ( ( uint32_t )base ) { + #ifdef TIM_MODULE_1 + case ( HAL_LL_TIM1_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM1_BUS ); + break; + #endif + #ifdef TIM_MODULE_3 + case ( HAL_LL_TIM3_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM3_BUS ); + break; + #endif + #ifdef TIM_MODULE_14 + case ( HAL_LL_TIM14_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM14_BUS ); + break; + #endif + #ifdef TIM_MODULE_16 + case ( HAL_LL_TIM16_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM16_BUS ); + break; + #endif + #ifdef TIM_MODULE_17 + case ( HAL_LL_TIM17_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM17_BUS ); + break; + #endif + } + return 0; +} + +static void _hal_ll_tim_map_pin( uint8_t module_index, uint8_t index ) { + + uint8_t tmp_channel; + + // Map new pin + hal_ll_tim_hw_specifics_map[ module_index ].config.pin = _tim_map[ index ].pin; + tmp_channel = _tim_map[ index ].channel; + hal_ll_tim_hw_specifics_map[ module_index ].config.af = _tim_map[ index ].af; + + if ( tmp_channel >= HAL_LL_TIM_CHANNEL_1N ) { + HAL_LL_TIM_IS_COMPLEMENTARY = true; + hal_ll_tim_hw_specifics_map[ module_index ].config.channel = tmp_channel - 4; + } else { + HAL_LL_TIM_IS_COMPLEMENTARY = false; + hal_ll_tim_hw_specifics_map[ module_index ].config.channel = tmp_channel; + } +} + +static void _hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_map_t *map, bool hal_ll_state ) { + + module_struct module; + uint32_t tim_config = 0; + + if( map->config.pin != HAL_LL_PIN_NC ) { + if( hal_ll_state == false ) { + tim_config = GPIO_CFG_MODE_ALT_FUNCTION | + GPIO_CFG_SPEED_LOW | + GPIO_CFG_OTYPE_PP; + } else { + tim_config = GPIO_CFG_MODE_ALT_FUNCTION | + GPIO_CFG_SPEED_HIGH | + GPIO_CFG_OTYPE_PP; + } + + module.pins[ 0 ] = VALUE( map->config.pin, map->config.af ); + module.pins[ 1 ] = GPIO_MODULE_STRUCT_END; + + module.configs[ 0 ] = tim_config; + module.configs[ 1 ] = GPIO_MODULE_STRUCT_END; + + hal_ll_gpio_module_struct_init( &module, hal_ll_state ); + } +} + +static void _hal_ll_tim_hw_init( hal_ll_tim_hw_specifics_map_t *map ) { + + uint32_t ck_psc; + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( map->base ); + + // Counter used as upcounter. + clear_reg_bit( &hal_ll_hw_reg->cr1, HAL_LL_TIM_CR1_DIR_BIT ); + + // Get clock speed. + ck_psc = _hal_ll_tim_get_clock_speed( map->base ) / map->freq_hz; + + // This should not be the case. ck_psc should not be greater than 65535, which is max value. + if( ck_psc > UINT16_MAX ) { + // In case of duty period beeing greater than 65535 set ck_psc to max value. + ck_psc = UINT16_MAX - 1; // Because of ( ck_psc / UINT16_MAX + 1 ) ), has to be minus 1. + }else if ( ck_psc < 1 ) { + ck_psc = 1; + } + + // Write prescale value. + hal_ll_hw_reg->psc = ( uint16_t )( ck_psc / UINT16_MAX ); + + // Write max count value. + hal_ll_hw_reg->arr = ( uint16_t )( ck_psc/( ck_psc / UINT16_MAX + 1 ) ); + + // Write max period to global array. + map->max_period = ( uint16_t )ck_psc; +} + +static void _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_t *map ) { + + _hal_ll_tim_set_clock( map->base, true ); + + _hal_ll_tim_alternate_functions_set_state( map, true ); + + _hal_ll_tim_hw_init( map ); +} +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_160/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_160/CMakeLists.cmake new file mode 100644 index 000000000..afc0ac2c9 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_160/CMakeLists.cmake @@ -0,0 +1,9 @@ +if(${MCU_NAME} MATCHES "^STM32L4P5AE$|^STM32L4P5AG$|^STM32L4P5CE$|^STM32L4P5CG$|^STM32L4P5QE$|^STM32L4P5QG$|^STM32L4P5RE$|^STM32L4P5RG$|^STM32L4P5VE$|^STM32L4P5VG$|^STM32L4P5ZE$|^STM32L4P5ZG$") + set(tim_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_tim.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_160") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_160") + list(APPEND hal_ll_def_list "STM32L4xx") + list(APPEND hal_ll_def_list "STM32L4Pxx") + list(APPEND hal_ll_def_list "STM32L4P5xx") + set(tim_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/tim/hal_ll_tim_pin_map/implementations/doc_ds_160") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_160/hal_ll_tim.c b/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_160/hal_ll_tim.c new file mode 100644 index 000000000..b0413832a --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_160/hal_ll_tim.c @@ -0,0 +1,937 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_tim.c + * @brief TIM HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_gpio.h" +#include "hal_ll_rcc.h" +#include "hal_ll_tim.h" +#include "hal_ll_tim_pin_map.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_tim_handle_register_t hal_ll_module_state[ TIM_MODULE_COUNT ]; + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< CR1 constants. */ +#define HAL_LL_TIM_ENABLE_COUNTER_BIT 0 +#define HAL_LL_TIM_BDTR_MOE_BIT 15 +#define HAL_LL_TIM_BDTR_MOE 0x8000 + +#define HAL_LL_TIM_CCMR_CC2S_BIT0 0x100u +#define HAL_LL_TIM_CCMR_CC2S_BIT1 0x200u +#define HAL_LL_TIM_CCMR_OC2PE 0x800u +#define HAL_LL_TIM_CCMR_OC2M_BIT0 0x1000u +#define HAL_LL_TIM_CCMR_OC2M_BIT1 0x2000u +#define HAL_LL_TIM_CCMR_OC2M_BIT2 0x4000u + +#define HAL_LL_TIM_CCMR_CC3S_BIT0 0x1u +#define HAL_LL_TIM_CCMR_CC3S_BIT1 0x2u +#define HAL_LL_TIM_CCMR_OC3PE 0x8u +#define HAL_LL_TIM_CCMR_OC3M_BIT0 0x10u +#define HAL_LL_TIM_CCMR_OC3M_BIT1 0x20u +#define HAL_LL_TIM_CCMR_OC3M_BIT2 0x40u + +#define HAL_LL_TIM_CR1_DIR 0x10 +#define HAL_LL_TIM_CR1_DIR_BIT 4 + +#define HAL_LL_TIM_ENABLE_1 11 +#define HAL_LL_TIM_ENABLE_2 0 +#define HAL_LL_TIM_ENABLE_3 1 +#define HAL_LL_TIM_ENABLE_4 2 +#define HAL_LL_TIM_ENABLE_5 3 +#define HAL_LL_TIM_ENABLE_8 13 +#define HAL_LL_TIM_ENABLE_15 16 +#define HAL_LL_TIM_ENABLE_16 17 +#define HAL_LL_TIM_ENABLE_17 18 + +#define HAL_LL_APB2_TIMER_CLOCK 2 + +#define HAL_LL_APB1_TIMER_CLOCK 1 + +#define hal_ll_tim_channel_static( _chn ) ( _chn-1 ) + +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_tim_get_base_struct(_handle) ((hal_ll_tim_base_handle_t *)_handle) + +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_tim_get_module_state_address ((hal_ll_tim_handle_register_t *)*handle) + +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_tim_get_handle ( hal_ll_tim_handle_register_t * )hal_ll_tim_get_module_state_address->hal_ll_tim_handle + +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_tim_get_base_from_hal_handle ((hal_ll_tim_hw_specifics_map_t *)((hal_ll_tim_handle_register_t *)\ + (((hal_ll_tim_handle_register_t *)(handle))->hal_ll_tim_handle))->hal_ll_tim_handle)->base + +// -------------------------------------------------------------- PRIVATE TYPES +/*!< @brief TIM register structure. */ +typedef struct +{ + uint32_t cr1; /* Address offset 0x00 */ + uint32_t cr2; /* Address offset 0x04 */ + uint32_t smcr; /* Address offset 0x08 */ + uint32_t dier; /* Address offset 0x0C */ + uint32_t sr; /* Address offset 0x10 */ + uint32_t egr; /* Address offset 0x14 */ + uint32_t ccmr1; /* Address offset 0x18 */ + uint32_t ccmr2; /* Address offset 0x1C */ + uint32_t ccer; /* Address offset 0x20 */ + uint32_t cnt; /* Address offset 0x24 */ + uint32_t psc; /* Address offset 0x28 */ + uint32_t arr; /* Address offset 0x2C */ + uint32_t rcr; /* Address offset 0x30 */ + uint32_t ccr1; /* Address offset 0x34 */ + uint32_t ccr2; /* Address offset 0x38 */ + uint32_t ccr3; /* Address offset 0x3C */ + uint32_t ccr4; /* Address offset 0x40 */ + uint32_t bdtr; /* Address offset 0x44 */ + uint32_t dcr; /* Address offset 0x48 */ + uint32_t dmar; /* Address offset 0x4C */ + uint32_t tim2_5_or; /* Address offset 0x50 */ +} hal_ll_tim_base_handle_t; + +/*!< @brief TIM pin structure */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_channel_t channel; + uint32_t af; +} hal_ll_tim_t; + +/*!< @brief TIM hw specific structure */ +typedef struct +{ + hal_ll_base_addr_t base; + hal_ll_tim_t config; + uint16_t max_period; + uint32_t freq_hz; + hal_ll_pin_name_t module_index; +} hal_ll_tim_hw_specifics_map_t; + +/*!< @brief TIM hw specific error values */ +typedef enum +{ + HAL_LL_TIM_SUCCESS = 0, + HAL_LL_TIM_MODULE_ERROR, + HAL_LL_TIM_WRONG_PIN, + + HAL_LL_TIM_ERROR = (-1) +} hal_ll_tim_err_t; + +// ------------------------------------------------------------------ VARIABLES +/*!< @brief TIM specific info */ +static hal_ll_tim_hw_specifics_map_t hal_ll_tim_hw_specifics_map[] = +{ + #ifdef TIM_MODULE_1 + {HAL_LL_TIM1_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_1 - 1}, + #endif + #ifdef TIM_MODULE_2 + {HAL_LL_TIM2_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_2 - 1}, + #endif + #ifdef TIM_MODULE_3 + {HAL_LL_TIM3_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_3 - 1}, + #endif + #ifdef TIM_MODULE_4 + {HAL_LL_TIM4_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_4 - 1}, + #endif + #ifdef TIM_MODULE_5 + {HAL_LL_TIM5_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_5 - 1}, + #endif + #ifdef TIM_MODULE_8 + {HAL_LL_TIM8_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_8 - 1}, + #endif + #ifdef TIM_MODULE_15 + {HAL_LL_TIM15_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_15 - 1}, + #endif + #ifdef TIM_MODULE_16 + {HAL_LL_TIM16_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_16 - 1}, + #endif + #ifdef TIM_MODULE_17 + {HAL_LL_TIM17_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_17 - 1}, + #endif + {HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, HAL_LL_PIN_NC} +}; + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_tim_handle_register_t *low_level_handle; +static volatile hal_ll_tim_hw_specifics_map_t *hal_ll_tim_hw_specifics_map_local; + +static bool HAL_LL_TIM_IS_COMPLEMENTARY; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Enable TIM module 1 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim1_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 2 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim2_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 3 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim3_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 4 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim4_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 5 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim5_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 8 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim8_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 15 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim15_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 16 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim16_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 17 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim17_set_clock( bool hal_ll_state ); + + +/** + * @brief Enable TIM module gate clock. + * @param base - TIM module base + * address + * @return None + */ +static void _hal_ll_tim_set_clock( hal_ll_base_addr_t base, bool hal_ll_state ); + +/** + * @brief Select TIM clock source + * @param selector - clock source selector + * @return uint32_t - clock source + */ +static uint32_t _hal_ll_tim_clock_source( uint8_t selector ); + +/** + * @brief Based on selected TIM, + * return clock speed. + * @param base - TIM module base + * address + * @return uint32_t clock source. + */ +static uint32_t _hal_ll_tim_get_clock_speed( hal_ll_base_addr_t base ); + +/** + * @brief Initialize TIM module on hardware level. + * + * Initializes TIM module on hardware level, based on beforehand + * set configuration and module handler. + * + * @param map - Object specific context handler. + * @return none + * + */ +static void _hal_ll_tim_hw_init( hal_ll_tim_hw_specifics_map_t *map ); + +/** + * @brief Full TIM module initialization procedure. + * + * Initializes TIM module on hardware level, based on beforehand + * set configuration and module handler. Sets adequate pin alternate functions. + * Initializes module clock. + * + * @param map - Object specific context handler. + * @return none + * + */ +static void _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_t *map ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_tim_hw_specifics_map array index. + * + * @param handle - Object specific context handler. + * @return hal_ll_tim_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_tim_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Check if pin is adequate. + * + * Checks tim pin the user has passed with pre-defined + * pin in tim map. + * + * @param pin - TIM pre-defined pin name. + * @return hal_ll_pin_name_t Module index based on pin. + * + * Returns pre-defined module index from pin maps, if pin + * is adequate. + */ +static hal_ll_pin_name_t _hal_ll_tim_check_pin( hal_ll_pin_name_t pin, uint8_t *index, hal_ll_tim_handle_register_t *handle_map ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * TIM pin. + * + * @param[in] module_index TIM HW module index -- 0,1,2... + * @param[in] *index_list Array with TIM map index values + * + * @return None + */ +static void _hal_ll_tim_map_pin( uint8_t module_index, uint8_t index ); + +/** + * @brief Sets TIM pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if TIM is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param map - Object specific context handler. + * + * @param hal_ll_state - Init/De-init + * @return none + * + */ +static void _hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_map_t *map, bool hal_ll_state ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_tim_register_handle( hal_ll_pin_name_t pin, hal_ll_tim_handle_register_t *handle_map, + uint8_t *hal_module_id ) { + + uint8_t index; + uint16_t pin_check_result; + + if ( ( pin_check_result = _hal_ll_tim_check_pin( pin, &index, handle_map ) ) == HAL_LL_PIN_NC ) { + return HAL_LL_TIM_WRONG_PIN; + } + + if ( hal_ll_tim_hw_specifics_map[ pin_check_result ].config.pin != pin ){ + // Clear previous module alternate functions + _hal_ll_tim_alternate_functions_set_state( &hal_ll_tim_hw_specifics_map[ pin_check_result ], false ); + + _hal_ll_tim_map_pin( pin_check_result, index ); + + _hal_ll_tim_alternate_functions_set_state( &hal_ll_tim_hw_specifics_map[ pin_check_result ], true ); + + handle_map[ pin_check_result ].init_ll_state = false; + + hal_ll_module_state[ pin_check_result ].init_ll_state = false; + + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle = ( handle_t * )&hal_ll_tim_hw_specifics_map[ pin_check_result ].base; + + handle_map[ pin_check_result ].hal_ll_tim_handle = ( handle_t *)&hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle; + + return HAL_LL_TIM_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_tim( handle_t *handle ) { + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + hal_ll_tim_handle_register_t *hal_handle = (hal_ll_tim_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_tim_hw_specifics_map_local->module_index; + + _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_local ); + + hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle = (handle_t *)&hal_ll_tim_hw_specifics_map[ pin_check_result ].base; + hal_ll_module_state[ pin_check_result ].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_TIM_SUCCESS; +} + +uint32_t hal_ll_tim_set_freq( handle_t *handle, uint32_t freq_hz ) { + + uint32_t tmp_channel; + uint32_t ck_psc; + uint32_t local_base_addr; + uint32_t local_freq; + uint32_t tmp_freq; + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + if( hal_ll_tim_hw_specifics_map_local->base == HAL_LL_MODULE_ERROR ) { + return HAL_LL_TIM_MODULE_ERROR; + } + + low_level_handle->init_ll_state = false; + + tmp_channel = hal_ll_tim_hw_specifics_map_local->config.channel; + + // If complementary output channel is used. + if ( HAL_LL_TIM_IS_COMPLEMENTARY ) { + // Stop capture/compare. + hal_ll_hw_reg->ccer &= 1UL << tmp_channel * 4 + 2; + } else { + // Stop capture/compare. + hal_ll_hw_reg->ccer &= 1UL << tmp_channel * 4; + } + + // Set TIM duty to 0. + *( &hal_ll_hw_reg->ccr1 + hal_ll_tim_channel_static( tmp_channel ) ) = 0; + + hal_ll_tim_hw_specifics_map_local->freq_hz = freq_hz; + + local_freq = hal_ll_tim_hw_specifics_map_local->freq_hz; + local_base_addr = hal_ll_tim_hw_specifics_map_local->base; + + ck_psc = _hal_ll_tim_get_clock_speed( local_base_addr ) / local_freq; + + if ( ck_psc > UINT16_MAX ) { + tmp_freq = _hal_ll_tim_get_clock_speed( local_base_addr ) / UINT16_MAX; + hal_ll_tim_hw_specifics_map_local->freq_hz = tmp_freq; + } else { + tmp_freq = freq_hz; + hal_ll_tim_hw_specifics_map_local->freq_hz = freq_hz; + } + + _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_local ); + + low_level_handle->init_ll_state = true; + + return tmp_freq; +} + +hal_ll_err_t hal_ll_tim_set_duty( handle_t *handle, float duty_ratio ) { + + float tmp_duty; + uint32_t max_duty = 0; + uint16_t max_period; + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + if ( low_level_handle->init_ll_state == false ) { + hal_ll_tim_start( handle ); + low_level_handle->init_ll_state = true; + } + + tmp_duty = duty_ratio * 100; + max_period = hal_ll_tim_hw_specifics_map_local->max_period; + + max_duty = ( ( float )max_period / 100 ) * tmp_duty; + + *( &hal_ll_hw_reg->ccr1 + hal_ll_tim_channel_static( hal_ll_tim_hw_specifics_map_local->config.channel ) ) = max_duty; + + return HAL_LL_TIM_SUCCESS; +} + +hal_ll_err_t hal_ll_tim_start( handle_t *handle ) { + + uint32_t tmp_channel; + volatile uint32_t tmp, + *tmpPtr; + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + tmp_channel = hal_ll_tim_hw_specifics_map_local->config.channel; + + // Capture/Compare 1 output enable. + tmp = hal_ll_hw_reg->ccer; + + // If complementary output channel is used. + if ( HAL_LL_TIM_IS_COMPLEMENTARY ) { + // Capture/Compare complementary output enable + tmp |= ( 1UL << ( hal_ll_tim_channel_static( tmp_channel ) * 4 + 2 ) ); + // Capture/Compare complementary output polarity(ACTIVE HIGH). + tmp &= ~( 1UL << ( hal_ll_tim_channel_static( tmp_channel ) * 4 + 3 ) ); + } else { + // Capture/Compare output polarity. + tmp |= ( 1UL << ( hal_ll_tim_channel_static( tmp_channel ) * 4 ) ); + // Capture/Compare output polarity(ACTIVE HIGH). + tmp &= ~( 1UL << ( hal_ll_tim_channel_static( tmp_channel ) * 4 + 1 ) ); + } + + hal_ll_hw_reg->ccer = tmp; + + #if defined(TIM_MODULE_1) || defined(TIM_MODULE_8) || defined(TIM_MODULE_20) + // Main output enabled. + set_reg_bit( &hal_ll_hw_reg->bdtr, HAL_LL_TIM_BDTR_MOE_BIT ); + #endif + + tmpPtr = &hal_ll_hw_reg->ccmr1; + + if( hal_ll_tim_channel_static( tmp_channel ) > 1 ) { + tmpPtr = &hal_ll_hw_reg->ccmr2; + } + + if( ( hal_ll_tim_channel_static( tmp_channel ) / 2 ) * 2 != + hal_ll_tim_channel_static( tmp_channel ) ) { + // Clear CCxS, OCxM[0]. + *tmpPtr &= ~( HAL_LL_TIM_CCMR_CC2S_BIT0 | + HAL_LL_TIM_CCMR_CC2S_BIT1 | + HAL_LL_TIM_CCMR_OC2PE | + HAL_LL_TIM_CCMR_OC2M_BIT0 ); + // Set OCxM[2, 1] + *tmpPtr |= HAL_LL_TIM_CCMR_OC2M_BIT1 | HAL_LL_TIM_CCMR_OC2M_BIT2; + } else { + // Clear CCxS, OCxM[0]. + *tmpPtr &= ~( HAL_LL_TIM_CCMR_CC3S_BIT0 | + HAL_LL_TIM_CCMR_CC3S_BIT1 | + HAL_LL_TIM_CCMR_OC3PE | + HAL_LL_TIM_CCMR_OC3M_BIT0 ); + + // Set OCxM[2, 1]. + *tmpPtr |= HAL_LL_TIM_CCMR_OC3M_BIT1 | HAL_LL_TIM_CCMR_OC3M_BIT2; + } + + // Enable counter. + set_reg_bit( &hal_ll_hw_reg->cr1, HAL_LL_TIM_ENABLE_COUNTER_BIT ); + + return HAL_LL_TIM_SUCCESS; +} + +hal_ll_err_t hal_ll_tim_stop( handle_t *handle ) { + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + // If complementary output channel is used. + if ( HAL_LL_TIM_IS_COMPLEMENTARY ) { + hal_ll_hw_reg->ccer &= 1UL << hal_ll_tim_hw_specifics_map_local->config.channel * 4 + 2; + } else { + hal_ll_hw_reg->ccer &= 1UL << hal_ll_tim_hw_specifics_map_local->config.channel * 4; + } + + return HAL_LL_TIM_SUCCESS; +} + +void hal_ll_tim_close( handle_t *handle ) { + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_tim_get_module_state_address); + + if( low_level_handle->hal_ll_tim_handle != NULL ) { + low_level_handle->hal_ll_tim_handle = NULL; + low_level_handle->hal_drv_tim_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_tim_hw_specifics_map_local->max_period = 0; + hal_ll_tim_hw_specifics_map_local->freq_hz = 0; + + _hal_ll_tim_set_clock( hal_ll_tim_hw_specifics_map_local->base, true ); + _hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_map_local, false ); + _hal_ll_tim_set_clock( hal_ll_tim_hw_specifics_map_local->base, false ); + + hal_ll_tim_hw_specifics_map_local->config.pin = HAL_LL_PIN_NC; + hal_ll_tim_hw_specifics_map_local->config.channel = HAL_LL_PIN_NC; + hal_ll_tim_hw_specifics_map_local->config.af = NULL; + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static inline void _hal_ll_tim1_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_1 ); + } else { + clear_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_1 ); + } +} + +static inline void _hal_ll_tim2_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB1ENR1, HAL_LL_TIM_ENABLE_2 ); + } else { + clear_reg_bit( _RCC_APB1ENR1, HAL_LL_TIM_ENABLE_2 ); + } +} + +static inline void _hal_ll_tim3_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB1ENR1, HAL_LL_TIM_ENABLE_3 ); + } else { + clear_reg_bit( _RCC_APB1ENR1, HAL_LL_TIM_ENABLE_3 ); + } +} + +static inline void _hal_ll_tim4_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB1ENR1, HAL_LL_TIM_ENABLE_4 ); + } else { + clear_reg_bit( _RCC_APB1ENR1, HAL_LL_TIM_ENABLE_4 ); + } +} + +static inline void _hal_ll_tim5_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB1ENR1, HAL_LL_TIM_ENABLE_5 ); + } else { + clear_reg_bit( _RCC_APB1ENR1, HAL_LL_TIM_ENABLE_5 ); + } +} + +static inline void _hal_ll_tim8_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_8 ); + } else { + clear_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_8 ); + } +} + +static inline void _hal_ll_tim15_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_15 ); + } else { + clear_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_15 ); + } +} + +static inline void _hal_ll_tim16_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_16 ); + } else { + clear_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_16 ); + } +} + +static inline void _hal_ll_tim17_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_17 ); + } else { + clear_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_17 ); + } +} + +static hal_ll_pin_name_t _hal_ll_tim_check_pin( hal_ll_pin_name_t pin, uint8_t *index, hal_ll_tim_handle_register_t *handle_map ) { + + hal_ll_pin_name_t pin_num; + uint8_t index_counter = 0; + uint8_t hal_ll_module_id = 0; + uint16_t map_size = ( sizeof( _tim_map ) / sizeof( hal_ll_tim_pin_map_t ) ); + + if ( HAL_LL_PIN_NC == pin ) { + return HAL_LL_PIN_NC; + } + + // Check if the selected pin is valid. + for ( pin_num = 0; pin_num < map_size; pin_num++ ) { + if ( _tim_map[ pin_num ].pin == pin ) { + // Get module number + hal_ll_module_id = _tim_map[ pin_num ].module_index; + if ( NULL == handle_map[hal_ll_module_id].hal_drv_tim_handle ) { + *index = pin_num; + return hal_ll_module_id; + } else if ( TIM_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + // By default return last error msg. + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static hal_ll_tim_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + + uint8_t hal_ll_module_count = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_tim_handle_register_t ) ); + static uint8_t hal_ll_module_error = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_tim_handle_register_t ) ); + + while( hal_ll_module_count-- ) { + if ( hal_ll_tim_get_base_from_hal_handle == hal_ll_tim_hw_specifics_map [ hal_ll_module_count ].base) { + return &hal_ll_tim_hw_specifics_map[ hal_ll_module_count ]; + } + } + + return &hal_ll_tim_hw_specifics_map[ hal_ll_module_error ]; +} + +static void _hal_ll_tim_set_clock( hal_ll_base_addr_t base, bool hal_ll_state ) { + + switch ( ( uint32_t )base ) { // 32-bit base address. + #ifdef TIM_MODULE_1 + case ( HAL_LL_TIM1_BASE_ADDR ): + _hal_ll_tim1_set_clock( hal_ll_state ); + break; + #endif + #ifdef TIM_MODULE_2 + case ( HAL_LL_TIM2_BASE_ADDR ): + _hal_ll_tim2_set_clock( hal_ll_state ); + break; + #endif + #ifdef TIM_MODULE_3 + case ( HAL_LL_TIM3_BASE_ADDR ): + _hal_ll_tim3_set_clock( hal_ll_state ); + break; + #endif + #ifdef TIM_MODULE_4 + case ( HAL_LL_TIM4_BASE_ADDR ): + _hal_ll_tim4_set_clock( hal_ll_state ); + break; + #endif + #ifdef TIM_MODULE_5 + case ( HAL_LL_TIM5_BASE_ADDR ): + _hal_ll_tim5_set_clock( hal_ll_state ); + break; + #endif + #ifdef TIM_MODULE_8 + case ( HAL_LL_TIM8_BASE_ADDR ): + _hal_ll_tim8_set_clock( hal_ll_state ); + break; + #endif + #ifdef TIM_MODULE_15 + case ( HAL_LL_TIM15_BASE_ADDR ): + _hal_ll_tim15_set_clock( hal_ll_state ); + break; + #endif + #ifdef TIM_MODULE_16 + case ( HAL_LL_TIM16_BASE_ADDR ): + _hal_ll_tim16_set_clock( hal_ll_state ); + break; + #endif + #ifdef TIM_MODULE_17 + case ( HAL_LL_TIM17_BASE_ADDR ): + _hal_ll_tim17_set_clock( hal_ll_state ); + break; + #endif + } +} + +static uint32_t _hal_ll_tim_clock_source( uint8_t selector ) { + + rcc_clocks_t rcc_clocks; + + RCC_GetClocksFrequency( &rcc_clocks ); + + if( selector == HAL_LL_APB2_TIMER_CLOCK ) { + if( rcc_clocks.hclk/rcc_clocks.pclk2 > 1 ) { + return rcc_clocks.pclk2 * 2; + } else { + return rcc_clocks.pclk2; + } + } + + if( selector == HAL_LL_APB1_TIMER_CLOCK ) { + if( rcc_clocks.hclk/rcc_clocks.pclk1 > 1 ) { + return rcc_clocks.pclk1 * 2; + } else { + return rcc_clocks.pclk1; + } + } + + return 0; +} + +static uint32_t _hal_ll_tim_get_clock_speed( hal_ll_base_addr_t base ) { + + switch ( ( uint32_t )base ) { + #ifdef TIM_MODULE_1 + case ( HAL_LL_TIM1_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM1_BUS ); + break; + #endif + #ifdef TIM_MODULE_2 + case ( HAL_LL_TIM2_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM2_BUS ); + break; + #endif + #ifdef TIM_MODULE_3 + case ( HAL_LL_TIM3_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM3_BUS ); + break; + #endif + #ifdef TIM_MODULE_4 + case ( HAL_LL_TIM4_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM4_BUS ); + break; + #endif + #ifdef TIM_MODULE_5 + case ( HAL_LL_TIM5_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM5_BUS ); + break; + #endif + #ifdef TIM_MODULE_8 + case ( HAL_LL_TIM8_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM8_BUS ); + break; + #endif + #ifdef TIM_MODULE_15 + case ( HAL_LL_TIM15_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM15_BUS ); + break; + #endif + #ifdef TIM_MODULE_16 + case ( HAL_LL_TIM16_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM16_BUS ); + break; + #endif + #ifdef TIM_MODULE_17 + case ( HAL_LL_TIM17_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM17_BUS ); + break; + #endif + } + return 0; +} + +static void _hal_ll_tim_map_pin( uint8_t module_index, uint8_t index ) { + + uint8_t tmp_channel; + + // Map new pin + hal_ll_tim_hw_specifics_map[ module_index ].config.pin = _tim_map[ index ].pin; + tmp_channel = _tim_map[ index ].channel; + hal_ll_tim_hw_specifics_map[ module_index ].config.af = _tim_map[ index ].af; + + if ( tmp_channel >= HAL_LL_TIM_CHANNEL_1N ) { + HAL_LL_TIM_IS_COMPLEMENTARY = true; + hal_ll_tim_hw_specifics_map[ module_index ].config.channel = tmp_channel - 4; + } else { + HAL_LL_TIM_IS_COMPLEMENTARY = false; + hal_ll_tim_hw_specifics_map[ module_index ].config.channel = tmp_channel; + } +} + +static void _hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_map_t *map, bool hal_ll_state ) { + + module_struct module; + uint32_t tim_config = 0; + + if( map->config.pin != HAL_LL_PIN_NC ) { + if( hal_ll_state == false ) { + tim_config = GPIO_CFG_MODE_ALT_FUNCTION | + GPIO_CFG_SPEED_LOW | + GPIO_CFG_OTYPE_PP; + } else { + tim_config = GPIO_CFG_MODE_ALT_FUNCTION | + GPIO_CFG_SPEED_HIGH | + GPIO_CFG_OTYPE_PP; + } + + module.pins[ 0 ] = VALUE( map->config.pin, map->config.af ); + module.pins[ 1 ] = GPIO_MODULE_STRUCT_END; + + module.configs[ 0 ] = tim_config; + module.configs[ 1 ] = GPIO_MODULE_STRUCT_END; + + hal_ll_gpio_module_struct_init( &module, hal_ll_state ); + } +} + +static void _hal_ll_tim_hw_init( hal_ll_tim_hw_specifics_map_t *map ) { + + uint32_t ck_psc; + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( map->base ); + + // Counter used as upcounter. + clear_reg_bit( &hal_ll_hw_reg->cr1, HAL_LL_TIM_CR1_DIR_BIT ); + + // Get clock speed. + ck_psc = _hal_ll_tim_get_clock_speed( map->base ) / map->freq_hz; + + // This should not be the case. ck_psc should not be greater than 65535, which is max value. + if( ck_psc > UINT16_MAX ) { + // In case of duty period beeing greater than 65535 set ck_psc to max value. + ck_psc = UINT16_MAX - 1; // Because of ( ck_psc / UINT16_MAX + 1 ) ), has to be minus 1. + }else if ( ck_psc < 1 ) { + ck_psc = 1; + } + + // Write prescale value. + hal_ll_hw_reg->psc = ( uint16_t )( ck_psc / UINT16_MAX ); + + // Write max count value. + hal_ll_hw_reg->arr = ( uint16_t )( ck_psc/( ck_psc / UINT16_MAX + 1 ) ); + + // Write max period to global array. + map->max_period = ( uint16_t )ck_psc; +} + +static void _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_t *map ) { + + _hal_ll_tim_set_clock( map->base, true ); + + _hal_ll_tim_alternate_functions_set_state( map, true ); + + _hal_ll_tim_hw_init( map ); +} +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_161/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_161/CMakeLists.cmake new file mode 100644 index 000000000..9b6723f78 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_161/CMakeLists.cmake @@ -0,0 +1,9 @@ +if(${MCU_NAME} MATCHES "^STM32L4Q5AG$|^STM32L4Q5CG$|^STM32L4Q5QG$|^STM32L4Q5RG$|^STM32L4Q5VG$|^STM32L4Q5ZG$") + set(tim_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_tim.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_161") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_161") + list(APPEND hal_ll_def_list "STM32L4xx") + list(APPEND hal_ll_def_list "STM32L4Qxx") + list(APPEND hal_ll_def_list "STM32L4Q5xx") + set(tim_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/tim/hal_ll_tim_pin_map/implementations/doc_ds_161") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_161/hal_ll_tim.c b/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_161/hal_ll_tim.c new file mode 100644 index 000000000..4390790e9 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_161/hal_ll_tim.c @@ -0,0 +1,978 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_tim.c + * @brief TIM HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_gpio.h" +#include "hal_ll_rcc.h" +#include "hal_ll_tim.h" +#include "hal_ll_tim_pin_map.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_tim_handle_register_t hal_ll_module_state[ TIM_MODULE_COUNT ]; + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< CR1 constants. */ +#define HAL_LL_TIM_ENABLE_COUNTER_BIT 0 +#define HAL_LL_TIM_BDTR_MOE_BIT 15 +#define HAL_LL_TIM_BDTR_MOE 0x8000 + +#define HAL_LL_TIM_CCMR_CC2S_BIT0 0x100u +#define HAL_LL_TIM_CCMR_CC2S_BIT1 0x200u +#define HAL_LL_TIM_CCMR_OC2PE 0x800u +#define HAL_LL_TIM_CCMR_OC2M_BIT0 0x1000u +#define HAL_LL_TIM_CCMR_OC2M_BIT1 0x2000u +#define HAL_LL_TIM_CCMR_OC2M_BIT2 0x4000u + +#define HAL_LL_TIM_CCMR_CC3S_BIT0 0x1u +#define HAL_LL_TIM_CCMR_CC3S_BIT1 0x2u +#define HAL_LL_TIM_CCMR_OC3PE 0x8u +#define HAL_LL_TIM_CCMR_OC3M_BIT0 0x10u +#define HAL_LL_TIM_CCMR_OC3M_BIT1 0x20u +#define HAL_LL_TIM_CCMR_OC3M_BIT2 0x40u + +#define HAL_LL_TIM_CR1_DIR 0x10 +#define HAL_LL_TIM_CR1_DIR_BIT 4 + +#define HAL_LL_TIM_ENABLE_1 11 + +#define HAL_LL_TIM_ENABLE_2 0 + +#define HAL_LL_TIM_ENABLE_3 1 + +#define HAL_LL_TIM_ENABLE_4 2 + +#define HAL_LL_TIM_ENABLE_5 3 + +#define HAL_LL_TIM_ENABLE_8 13 + +#define HAL_LL_TIM_ENABLE_15 16 + +#define HAL_LL_TIM_ENABLE_16 17 + +#define HAL_LL_TIM_ENABLE_17 18 + + +#define HAL_LL_APB2_TIMER_CLOCK 2 + +#define HAL_LL_APB1_TIMER_CLOCK 1 + + + +#define hal_ll_tim_channel_static( _chn ) ( _chn-1 ) + +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_tim_get_base_struct(_handle) ((hal_ll_tim_base_handle_t *)_handle) + +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_tim_get_module_state_address ((hal_ll_tim_handle_register_t *)*handle) + +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_tim_get_handle ( hal_ll_tim_handle_register_t * )hal_ll_tim_get_module_state_address->hal_ll_tim_handle + +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_tim_get_base_from_hal_handle ((hal_ll_tim_hw_specifics_map_t *)((hal_ll_tim_handle_register_t *)\ + (((hal_ll_tim_handle_register_t *)(handle))->hal_ll_tim_handle))->hal_ll_tim_handle)->base + +// -------------------------------------------------------------- PRIVATE TYPES +/*!< @brief TIM register structure. */ +typedef struct +{ + uint32_t cr1; /* Address offset 0x00 */ + uint32_t cr2; /* Address offset 0x04 */ + uint32_t smcr; /* Address offset 0x08 */ + uint32_t dier; /* Address offset 0x0C */ + uint32_t sr; /* Address offset 0x10 */ + uint32_t egr; /* Address offset 0x14 */ + uint32_t ccmr1; /* Address offset 0x18 */ + uint32_t ccmr2; /* Address offset 0x1C */ + uint32_t ccer; /* Address offset 0x20 */ + uint32_t cnt; /* Address offset 0x24 */ + uint32_t psc; /* Address offset 0x28 */ + uint32_t arr; /* Address offset 0x2C */ + uint32_t rcr; /* Address offset 0x30 */ + uint32_t ccr1; /* Address offset 0x34 */ + uint32_t ccr2; /* Address offset 0x38 */ + uint32_t ccr3; /* Address offset 0x3C */ + uint32_t ccr4; /* Address offset 0x40 */ + uint32_t bdtr; /* Address offset 0x44 */ + uint32_t dcr; /* Address offset 0x48 */ + uint32_t dmar; /* Address offset 0x4C */ + uint32_t tim2_5_or; /* Address offset 0x50 */ +} hal_ll_tim_base_handle_t; + +/*!< @brief TIM pin structure */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_channel_t channel; + uint32_t af; +} hal_ll_tim_t; + +/*!< @brief TIM hw specific structure */ +typedef struct +{ + hal_ll_base_addr_t base; + hal_ll_tim_t config; + uint16_t max_period; + uint32_t freq_hz; + hal_ll_pin_name_t module_index; +} hal_ll_tim_hw_specifics_map_t; + +/*!< @brief TIM hw specific error values */ +typedef enum +{ + HAL_LL_TIM_SUCCESS = 0, + HAL_LL_TIM_MODULE_ERROR, + HAL_LL_TIM_WRONG_PIN, + + HAL_LL_TIM_ERROR = (-1) +} hal_ll_tim_err_t; + +// ------------------------------------------------------------------ VARIABLES +/*!< @brief TIM specific info */ +static hal_ll_tim_hw_specifics_map_t hal_ll_tim_hw_specifics_map[] = +{ + #ifdef TIM_MODULE_1 + {HAL_LL_TIM1_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_1 - 1}, + #endif + + #ifdef TIM_MODULE_2 + {HAL_LL_TIM2_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_2 - 1}, + #endif + + #ifdef TIM_MODULE_3 + {HAL_LL_TIM3_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_3 - 1}, + #endif + + #ifdef TIM_MODULE_4 + {HAL_LL_TIM4_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_4 - 1}, + #endif + + #ifdef TIM_MODULE_5 + {HAL_LL_TIM5_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_5 - 1}, + #endif + + #ifdef TIM_MODULE_8 + {HAL_LL_TIM8_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_8 - 1}, + #endif + + #ifdef TIM_MODULE_15 + {HAL_LL_TIM15_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_15 - 1}, + #endif + + #ifdef TIM_MODULE_16 + {HAL_LL_TIM16_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_16 - 1}, + #endif + + #ifdef TIM_MODULE_17 + {HAL_LL_TIM17_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_17 - 1}, + #endif + + + {HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, HAL_LL_PIN_NC} +}; + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_tim_handle_register_t *low_level_handle; +static volatile hal_ll_tim_hw_specifics_map_t *hal_ll_tim_hw_specifics_map_local; + +static bool HAL_LL_TIM_IS_COMPLEMENTARY; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Enable TIM module 1 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim1_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 2 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim2_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 3 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim3_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 4 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim4_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 5 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim5_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 8 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim8_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 15 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim15_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 16 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim16_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 17 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim17_set_clock( bool hal_ll_state ); + + +/** + * @brief Enable TIM module gate clock. + * @param base - TIM module base + * address + * @return None + */ +static void _hal_ll_tim_set_clock( hal_ll_base_addr_t base, bool hal_ll_state ); + +/** + * @brief Select TIM clock source + * @param selector - clock source selector + * @return uint32_t - clock source + */ +static uint32_t _hal_ll_tim_clock_source( uint8_t selector ); + +/** + * @brief Based on selected TIM, + * return clock speed. + * @param base - TIM module base + * address + * @return uint32_t clock source. + */ +static uint32_t _hal_ll_tim_get_clock_speed( hal_ll_base_addr_t base ); + +/** + * @brief Initialize TIM module on hardware level. + * + * Initializes TIM module on hardware level, based on beforehand + * set configuration and module handler. + * + * @param map - Object specific context handler. + * @return none + * + */ +static void _hal_ll_tim_hw_init( hal_ll_tim_hw_specifics_map_t *map ); + +/** + * @brief Full TIM module initialization procedure. + * + * Initializes TIM module on hardware level, based on beforehand + * set configuration and module handler. Sets adequate pin alternate functions. + * Initializes module clock. + * + * @param map - Object specific context handler. + * @return none + * + */ +static void _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_t *map ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_tim_hw_specifics_map array index. + * + * @param handle - Object specific context handler. + * @return hal_ll_tim_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_tim_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Check if pin is adequate. + * + * Checks tim pin the user has passed with pre-defined + * pin in tim map. + * + * @param pin - TIM pre-defined pin name. + * @return hal_ll_pin_name_t Module index based on pin. + * + * Returns pre-defined module index from pin maps, if pin + * is adequate. + */ +static hal_ll_pin_name_t _hal_ll_tim_check_pin( hal_ll_pin_name_t pin, uint8_t *index, hal_ll_tim_handle_register_t *handle_map ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * TIM pin. + * + * @param[in] module_index TIM HW module index -- 0,1,2... + * @param[in] *index_list Array with TIM map index values + * + * @return None + */ +static void _hal_ll_tim_map_pin( uint8_t module_index, uint8_t index ); + +/** + * @brief Sets TIM pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if TIM is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param map - Object specific context handler. + * + * @param hal_ll_state - Init/De-init + * @return none + * + */ +static void _hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_map_t *map, bool hal_ll_state ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_tim_register_handle( hal_ll_pin_name_t pin, hal_ll_tim_handle_register_t *handle_map, + uint8_t *hal_module_id ) { + + uint8_t index; + uint16_t pin_check_result; + + if ( ( pin_check_result = _hal_ll_tim_check_pin( pin, &index, handle_map ) ) == HAL_LL_PIN_NC ) { + return HAL_LL_TIM_WRONG_PIN; + } + + if ( hal_ll_tim_hw_specifics_map[ pin_check_result ].config.pin != pin ){ + // Clear previous module alternate functions + _hal_ll_tim_alternate_functions_set_state( &hal_ll_tim_hw_specifics_map[ pin_check_result ], false ); + + _hal_ll_tim_map_pin( pin_check_result, index ); + + _hal_ll_tim_alternate_functions_set_state( &hal_ll_tim_hw_specifics_map[ pin_check_result ], true ); + + handle_map[ pin_check_result ].init_ll_state = false; + + hal_ll_module_state[ pin_check_result ].init_ll_state = false; + + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle = ( handle_t * )&hal_ll_tim_hw_specifics_map[ pin_check_result ].base; + + handle_map[ pin_check_result ].hal_ll_tim_handle = ( handle_t *)&hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle; + + return HAL_LL_TIM_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_tim( handle_t *handle ) { + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + hal_ll_tim_handle_register_t *hal_handle = (hal_ll_tim_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_tim_hw_specifics_map_local->module_index; + + _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_local ); + + hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle = (handle_t *)&hal_ll_tim_hw_specifics_map[ pin_check_result ].base; + hal_ll_module_state[ pin_check_result ].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_TIM_SUCCESS; +} + +uint32_t hal_ll_tim_set_freq( handle_t *handle, uint32_t freq_hz ) { + + uint32_t tmp_channel; + uint32_t ck_psc; + uint32_t local_base_addr; + uint32_t local_freq; + uint32_t tmp_freq; + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + if( hal_ll_tim_hw_specifics_map_local->base == HAL_LL_MODULE_ERROR ) { + return HAL_LL_TIM_MODULE_ERROR; + } + + low_level_handle->init_ll_state = false; + + tmp_channel = hal_ll_tim_hw_specifics_map_local->config.channel; + + // If complementary output channel is used. + if ( HAL_LL_TIM_IS_COMPLEMENTARY ) { + // Stop capture/compare. + hal_ll_hw_reg->ccer &= 1UL << tmp_channel * 4 + 2; + } else { + // Stop capture/compare. + hal_ll_hw_reg->ccer &= 1UL << tmp_channel * 4; + } + + // Set TIM duty to 0. + *( &hal_ll_hw_reg->ccr1 + hal_ll_tim_channel_static( tmp_channel ) ) = 0; + + hal_ll_tim_hw_specifics_map_local->freq_hz = freq_hz; + + local_freq = hal_ll_tim_hw_specifics_map_local->freq_hz; + local_base_addr = hal_ll_tim_hw_specifics_map_local->base; + + ck_psc = _hal_ll_tim_get_clock_speed( local_base_addr ) / local_freq; + + if ( ck_psc > UINT16_MAX ) { + tmp_freq = _hal_ll_tim_get_clock_speed( local_base_addr ) / UINT16_MAX; + hal_ll_tim_hw_specifics_map_local->freq_hz = tmp_freq; + } else { + tmp_freq = freq_hz; + hal_ll_tim_hw_specifics_map_local->freq_hz = freq_hz; + } + + _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_local ); + + low_level_handle->init_ll_state = true; + + return tmp_freq; +} + +hal_ll_err_t hal_ll_tim_set_duty( handle_t *handle, float duty_ratio ) { + + float tmp_duty; + uint32_t max_duty = 0; + uint16_t max_period; + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + if ( low_level_handle->init_ll_state == false ) { + hal_ll_tim_start( handle ); + low_level_handle->init_ll_state = true; + } + + tmp_duty = duty_ratio * 100; + max_period = hal_ll_tim_hw_specifics_map_local->max_period; + + max_duty = ( ( float )max_period / 100 ) * tmp_duty; + + *( &hal_ll_hw_reg->ccr1 + hal_ll_tim_channel_static( hal_ll_tim_hw_specifics_map_local->config.channel ) ) = max_duty; + + return HAL_LL_TIM_SUCCESS; +} + +hal_ll_err_t hal_ll_tim_start( handle_t *handle ) { + + uint32_t tmp_channel; + volatile uint32_t tmp, + *tmpPtr; + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + tmp_channel = hal_ll_tim_hw_specifics_map_local->config.channel; + + // Capture/Compare 1 output enable. + tmp = hal_ll_hw_reg->ccer; + + // If complementary output channel is used. + if ( HAL_LL_TIM_IS_COMPLEMENTARY ) { + // Capture/Compare complementary output enable + tmp |= ( 1UL << ( hal_ll_tim_channel_static( tmp_channel ) * 4 + 2 ) ); + // Capture/Compare complementary output polarity(ACTIVE HIGH). + tmp &= ~( 1UL << ( hal_ll_tim_channel_static( tmp_channel ) * 4 + 3 ) ); + } else { + // Capture/Compare output polarity. + tmp |= ( 1UL << ( hal_ll_tim_channel_static( tmp_channel ) * 4 ) ); + // Capture/Compare output polarity(ACTIVE HIGH). + tmp &= ~( 1UL << ( hal_ll_tim_channel_static( tmp_channel ) * 4 + 1 ) ); + } + + hal_ll_hw_reg->ccer = tmp; + + #if defined(TIM_MODULE_1) || defined(TIM_MODULE_8) || defined(TIM_MODULE_20) + // Main output enabled. + set_reg_bit( &hal_ll_hw_reg->bdtr, HAL_LL_TIM_BDTR_MOE_BIT ); + #endif + + tmpPtr = &hal_ll_hw_reg->ccmr1; + + if( hal_ll_tim_channel_static( tmp_channel ) > 1 ) { + tmpPtr = &hal_ll_hw_reg->ccmr2; + } + + if( ( hal_ll_tim_channel_static( tmp_channel ) / 2 ) * 2 != + hal_ll_tim_channel_static( tmp_channel ) ) { + // Clear CCxS, OCxM[0]. + *tmpPtr &= ~( HAL_LL_TIM_CCMR_CC2S_BIT0 | + HAL_LL_TIM_CCMR_CC2S_BIT1 | + HAL_LL_TIM_CCMR_OC2PE | + HAL_LL_TIM_CCMR_OC2M_BIT0 ); + // Set OCxM[2, 1] + *tmpPtr |= HAL_LL_TIM_CCMR_OC2M_BIT1 | HAL_LL_TIM_CCMR_OC2M_BIT2; + } else { + // Clear CCxS, OCxM[0]. + *tmpPtr &= ~( HAL_LL_TIM_CCMR_CC3S_BIT0 | + HAL_LL_TIM_CCMR_CC3S_BIT1 | + HAL_LL_TIM_CCMR_OC3PE | + HAL_LL_TIM_CCMR_OC3M_BIT0 ); + + // Set OCxM[2, 1]. + *tmpPtr |= HAL_LL_TIM_CCMR_OC3M_BIT1 | HAL_LL_TIM_CCMR_OC3M_BIT2; + } + + // Enable counter. + set_reg_bit( &hal_ll_hw_reg->cr1, HAL_LL_TIM_ENABLE_COUNTER_BIT ); + + return HAL_LL_TIM_SUCCESS; +} + +hal_ll_err_t hal_ll_tim_stop( handle_t *handle ) { + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + // If complementary output channel is used. + if ( HAL_LL_TIM_IS_COMPLEMENTARY ) { + hal_ll_hw_reg->ccer &= 1UL << hal_ll_tim_hw_specifics_map_local->config.channel * 4 + 2; + } else { + hal_ll_hw_reg->ccer &= 1UL << hal_ll_tim_hw_specifics_map_local->config.channel * 4; + } + + return HAL_LL_TIM_SUCCESS; +} + +void hal_ll_tim_close( handle_t *handle ) { + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_tim_get_module_state_address); + + if( low_level_handle->hal_ll_tim_handle != NULL ) { + low_level_handle->hal_ll_tim_handle = NULL; + low_level_handle->hal_drv_tim_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_tim_hw_specifics_map_local->max_period = 0; + hal_ll_tim_hw_specifics_map_local->freq_hz = 0; + + _hal_ll_tim_set_clock( hal_ll_tim_hw_specifics_map_local->base, true ); + _hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_map_local, false ); + _hal_ll_tim_set_clock( hal_ll_tim_hw_specifics_map_local->base, false ); + + hal_ll_tim_hw_specifics_map_local->config.pin = HAL_LL_PIN_NC; + hal_ll_tim_hw_specifics_map_local->config.channel = HAL_LL_PIN_NC; + hal_ll_tim_hw_specifics_map_local->config.af = NULL; + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static inline void _hal_ll_tim1_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_1 ); + } else { + clear_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_1 ); + } +} + +static inline void _hal_ll_tim2_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB1ENR1, HAL_LL_TIM_ENABLE_2 ); + } else { + clear_reg_bit( _RCC_APB1ENR1, HAL_LL_TIM_ENABLE_2 ); + } +} + +static inline void _hal_ll_tim3_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB1ENR1, HAL_LL_TIM_ENABLE_3 ); + } else { + clear_reg_bit( _RCC_APB1ENR1, HAL_LL_TIM_ENABLE_3 ); + } +} + +static inline void _hal_ll_tim4_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB1ENR1, HAL_LL_TIM_ENABLE_4 ); + } else { + clear_reg_bit( _RCC_APB1ENR1, HAL_LL_TIM_ENABLE_4 ); + } +} + +static inline void _hal_ll_tim5_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB1ENR1, HAL_LL_TIM_ENABLE_5 ); + } else { + clear_reg_bit( _RCC_APB1ENR1, HAL_LL_TIM_ENABLE_5 ); + } +} + +static inline void _hal_ll_tim8_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_8 ); + } else { + clear_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_8 ); + } +} + +static inline void _hal_ll_tim15_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_15 ); + } else { + clear_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_15 ); + } +} + +static inline void _hal_ll_tim16_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_16 ); + } else { + clear_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_16 ); + } +} + +static inline void _hal_ll_tim17_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_17 ); + } else { + clear_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_17 ); + } +} + + +static hal_ll_pin_name_t _hal_ll_tim_check_pin( hal_ll_pin_name_t pin, uint8_t *index, hal_ll_tim_handle_register_t *handle_map ) { + + hal_ll_pin_name_t pin_num; + uint8_t index_counter = 0; + uint8_t hal_ll_module_id = 0; + uint16_t map_size = ( sizeof( _tim_map ) / sizeof( hal_ll_tim_pin_map_t ) ); + + if ( HAL_LL_PIN_NC == pin ) { + return HAL_LL_PIN_NC; + } + + // Check if the selected pin is valid. + for ( pin_num = 0; pin_num < map_size; pin_num++ ) { + if ( _tim_map[ pin_num ].pin == pin ) { + // Get module number + hal_ll_module_id = _tim_map[ pin_num ].module_index; + if ( NULL == handle_map[hal_ll_module_id].hal_drv_tim_handle ) { + *index = pin_num; + return hal_ll_module_id; + } else if ( TIM_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + // By default return last error msg. + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static hal_ll_tim_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + + uint8_t hal_ll_module_count = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_tim_handle_register_t ) ); + static uint8_t hal_ll_module_error = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_tim_handle_register_t ) ); + + while( hal_ll_module_count-- ) { + if ( hal_ll_tim_get_base_from_hal_handle == hal_ll_tim_hw_specifics_map [ hal_ll_module_count ].base) { + return &hal_ll_tim_hw_specifics_map[ hal_ll_module_count ]; + } + } + + return &hal_ll_tim_hw_specifics_map[ hal_ll_module_error ]; +} + +static void _hal_ll_tim_set_clock( hal_ll_base_addr_t base, bool hal_ll_state ) { + + switch ( ( uint32_t )base ) { // 32-bit base address. + #ifdef TIM_MODULE_1 + case ( HAL_LL_TIM1_BASE_ADDR ): + _hal_ll_tim1_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_2 + case ( HAL_LL_TIM2_BASE_ADDR ): + _hal_ll_tim2_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_3 + case ( HAL_LL_TIM3_BASE_ADDR ): + _hal_ll_tim3_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_4 + case ( HAL_LL_TIM4_BASE_ADDR ): + _hal_ll_tim4_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_5 + case ( HAL_LL_TIM5_BASE_ADDR ): + _hal_ll_tim5_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_8 + case ( HAL_LL_TIM8_BASE_ADDR ): + _hal_ll_tim8_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_15 + case ( HAL_LL_TIM15_BASE_ADDR ): + _hal_ll_tim15_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_16 + case ( HAL_LL_TIM16_BASE_ADDR ): + _hal_ll_tim16_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_17 + case ( HAL_LL_TIM17_BASE_ADDR ): + _hal_ll_tim17_set_clock( hal_ll_state ); + break; + #endif + + } +} + +static uint32_t _hal_ll_tim_clock_source( uint8_t selector ) { + + rcc_clocks_t rcc_clocks; + + RCC_GetClocksFrequency( &rcc_clocks ); + + if( selector == HAL_LL_APB2_TIMER_CLOCK ) { + if( rcc_clocks.hclk/rcc_clocks.pclk2 > 1 ) { + return rcc_clocks.pclk2 * 2; + } else { + return rcc_clocks.pclk2; + } + } + + if( selector == HAL_LL_APB1_TIMER_CLOCK ) { + if( rcc_clocks.hclk/rcc_clocks.pclk1 > 1 ) { + return rcc_clocks.pclk1 * 2; + } else { + return rcc_clocks.pclk1; + } + } + + return 0; +} + +static uint32_t _hal_ll_tim_get_clock_speed( hal_ll_base_addr_t base ) { + + switch ( ( uint32_t )base ) { + #ifdef TIM_MODULE_1 + case ( HAL_LL_TIM1_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM1_BUS ); + break; + #endif + + #ifdef TIM_MODULE_2 + case ( HAL_LL_TIM2_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM2_BUS ); + break; + #endif + + #ifdef TIM_MODULE_3 + case ( HAL_LL_TIM3_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM3_BUS ); + break; + #endif + + #ifdef TIM_MODULE_4 + case ( HAL_LL_TIM4_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM4_BUS ); + break; + #endif + + #ifdef TIM_MODULE_5 + case ( HAL_LL_TIM5_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM5_BUS ); + break; + #endif + + #ifdef TIM_MODULE_8 + case ( HAL_LL_TIM8_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM8_BUS ); + break; + #endif + + #ifdef TIM_MODULE_15 + case ( HAL_LL_TIM15_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM15_BUS ); + break; + #endif + + #ifdef TIM_MODULE_16 + case ( HAL_LL_TIM16_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM16_BUS ); + break; + #endif + + #ifdef TIM_MODULE_17 + case ( HAL_LL_TIM17_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM17_BUS ); + break; + #endif + + } + return 0; +} + +static void _hal_ll_tim_map_pin( uint8_t module_index, uint8_t index ) { + + uint8_t tmp_channel; + + // Map new pin + hal_ll_tim_hw_specifics_map[ module_index ].config.pin = _tim_map[ index ].pin; + tmp_channel = _tim_map[ index ].channel; + hal_ll_tim_hw_specifics_map[ module_index ].config.af = _tim_map[ index ].af; + + if ( tmp_channel >= HAL_LL_TIM_CHANNEL_1N ) { + HAL_LL_TIM_IS_COMPLEMENTARY = true; + hal_ll_tim_hw_specifics_map[ module_index ].config.channel = tmp_channel - 4; + } else { + HAL_LL_TIM_IS_COMPLEMENTARY = false; + hal_ll_tim_hw_specifics_map[ module_index ].config.channel = tmp_channel; + } +} + +static void _hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_map_t *map, bool hal_ll_state ) { + + module_struct module; + uint32_t tim_config = 0; + + if( map->config.pin != HAL_LL_PIN_NC ) { + if( hal_ll_state == false ) { + tim_config = GPIO_CFG_MODE_ALT_FUNCTION | + GPIO_CFG_SPEED_LOW | + GPIO_CFG_OTYPE_PP; + } else { + tim_config = GPIO_CFG_MODE_ALT_FUNCTION | + GPIO_CFG_SPEED_HIGH | + GPIO_CFG_OTYPE_PP; + } + + module.pins[ 0 ] = VALUE( map->config.pin, map->config.af ); + module.pins[ 1 ] = GPIO_MODULE_STRUCT_END; + + module.configs[ 0 ] = tim_config; + module.configs[ 1 ] = GPIO_MODULE_STRUCT_END; + + hal_ll_gpio_module_struct_init( &module, hal_ll_state ); + } +} + +static void _hal_ll_tim_hw_init( hal_ll_tim_hw_specifics_map_t *map ) { + + uint32_t ck_psc; + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( map->base ); + + // Counter used as upcounter. + clear_reg_bit( &hal_ll_hw_reg->cr1, HAL_LL_TIM_CR1_DIR_BIT ); + + // Get clock speed. + ck_psc = _hal_ll_tim_get_clock_speed( map->base ) / map->freq_hz; + + // This should not be the case. ck_psc should not be greater than 65535, which is max value. + if( ck_psc > UINT16_MAX ) { + // In case of duty period beeing greater than 65535 set ck_psc to max value. + ck_psc = UINT16_MAX - 1; // Because of ( ck_psc / UINT16_MAX + 1 ) ), has to be minus 1. + }else if ( ck_psc < 1 ) { + ck_psc = 1; + } + + // Write prescale value. + hal_ll_hw_reg->psc = ( uint16_t )( ck_psc / UINT16_MAX ); + + // Write max count value. + hal_ll_hw_reg->arr = ( uint16_t )( ck_psc/( ck_psc / UINT16_MAX + 1 ) ); + + // Write max period to global array. + map->max_period = ( uint16_t )ck_psc; +} + +static void _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_t *map ) { + + _hal_ll_tim_set_clock( map->base, true ); + + _hal_ll_tim_alternate_functions_set_state( map, true ); + + _hal_ll_tim_hw_init( map ); +} +// ------------------------------------------------------------------------- END + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_2/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_2/CMakeLists.cmake new file mode 100644 index 000000000..c16d9c8f1 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_2/CMakeLists.cmake @@ -0,0 +1,9 @@ +if(${MCU_NAME} MATCHES "^STM32C031C4$|^STM32C031F4$|^STM32C031G4$|^STM32C031K4$|^STM32C031C6$|^STM32C031F6$|^STM32C031G6$|^STM32C031K6$") + set(tim_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_tim.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_2") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_2") + list(APPEND hal_ll_def_list "STM32C0xx") + list(APPEND hal_ll_def_list "STM32C03xx") + list(APPEND hal_ll_def_list "STM32C031xx") + set(tim_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/tim/hal_ll_tim_pin_map/implementations/doc_ds_2") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_2/hal_ll_tim.c b/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_2/hal_ll_tim.c new file mode 100644 index 000000000..4dd488bf2 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_2/hal_ll_tim.c @@ -0,0 +1,836 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_tim.c + * @brief TIM HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_gpio.h" +#include "hal_ll_rcc.h" +#include "hal_ll_tim.h" +#include "hal_ll_tim_pin_map.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_tim_handle_register_t hal_ll_module_state[ TIM_MODULE_COUNT ]; + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< CR1 constants. */ +#define HAL_LL_TIM_ENABLE_COUNTER_BIT 0 +#define HAL_LL_TIM_BDTR_MOE_BIT 15 +#define HAL_LL_TIM_BDTR_MOE 0x8000 + +#define HAL_LL_TIM_CCMR_CC2S_BIT0 0x100u +#define HAL_LL_TIM_CCMR_CC2S_BIT1 0x200u +#define HAL_LL_TIM_CCMR_OC2PE 0x800u +#define HAL_LL_TIM_CCMR_OC2M_BIT0 0x1000u +#define HAL_LL_TIM_CCMR_OC2M_BIT1 0x2000u +#define HAL_LL_TIM_CCMR_OC2M_BIT2 0x4000u + +#define HAL_LL_TIM_CCMR_CC3S_BIT0 0x1u +#define HAL_LL_TIM_CCMR_CC3S_BIT1 0x2u +#define HAL_LL_TIM_CCMR_OC3PE 0x8u +#define HAL_LL_TIM_CCMR_OC3M_BIT0 0x10u +#define HAL_LL_TIM_CCMR_OC3M_BIT1 0x20u +#define HAL_LL_TIM_CCMR_OC3M_BIT2 0x40u + +#define HAL_LL_TIM_CR1_DIR 0x10 +#define HAL_LL_TIM_CR1_DIR_BIT 4 + +#define HAL_LL_TIM_ENABLE_1 11 + +#define HAL_LL_TIM_ENABLE_3 1 + +#define HAL_LL_TIM_ENABLE_14 15 + +#define HAL_LL_TIM_ENABLE_16 17 + +#define HAL_LL_TIM_ENABLE_17 18 + + +#define HAL_LL_APB1_TIMER_CLOCK 1 + + + +#define hal_ll_tim_channel_static( _chn ) ( _chn-1 ) + +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_tim_get_base_struct(_handle) ((hal_ll_tim_base_handle_t *)_handle) + +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_tim_get_module_state_address ((hal_ll_tim_handle_register_t *)*handle) + +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_tim_get_handle ( hal_ll_tim_handle_register_t * )hal_ll_tim_get_module_state_address->hal_ll_tim_handle + +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_tim_get_base_from_hal_handle ((hal_ll_tim_hw_specifics_map_t *)((hal_ll_tim_handle_register_t *)\ + (((hal_ll_tim_handle_register_t *)(handle))->hal_ll_tim_handle))->hal_ll_tim_handle)->base + +// -------------------------------------------------------------- PRIVATE TYPES +/*!< @brief TIM register structure. */ +typedef struct +{ + uint32_t cr1; /* Address offset 0x00 */ + uint32_t cr2; /* Address offset 0x04 */ + uint32_t smcr; /* Address offset 0x08 */ + uint32_t dier; /* Address offset 0x0C */ + uint32_t sr; /* Address offset 0x10 */ + uint32_t egr; /* Address offset 0x14 */ + uint32_t ccmr1; /* Address offset 0x18 */ + uint32_t ccmr2; /* Address offset 0x1C */ + uint32_t ccer; /* Address offset 0x20 */ + uint32_t cnt; /* Address offset 0x24 */ + uint32_t psc; /* Address offset 0x28 */ + uint32_t arr; /* Address offset 0x2C */ + uint32_t rcr; /* Address offset 0x30 */ + uint32_t ccr1; /* Address offset 0x34 */ + uint32_t ccr2; /* Address offset 0x38 */ + uint32_t ccr3; /* Address offset 0x3C */ + uint32_t ccr4; /* Address offset 0x40 */ + uint32_t bdtr; /* Address offset 0x44 */ + uint32_t dcr; /* Address offset 0x48 */ + uint32_t dmar; /* Address offset 0x4C */ + uint32_t tim2_5_or; /* Address offset 0x50 */ +} hal_ll_tim_base_handle_t; + +/*!< @brief TIM pin structure */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_channel_t channel; + uint32_t af; +} hal_ll_tim_t; + +/*!< @brief TIM hw specific structure */ +typedef struct +{ + hal_ll_base_addr_t base; + hal_ll_tim_t config; + uint16_t max_period; + uint32_t freq_hz; + hal_ll_pin_name_t module_index; +} hal_ll_tim_hw_specifics_map_t; + +/*!< @brief TIM hw specific error values */ +typedef enum +{ + HAL_LL_TIM_SUCCESS = 0, + HAL_LL_TIM_MODULE_ERROR, + HAL_LL_TIM_WRONG_PIN, + + HAL_LL_TIM_ERROR = (-1) +} hal_ll_tim_err_t; + +// ------------------------------------------------------------------ VARIABLES +/*!< @brief TIM specific info */ +static hal_ll_tim_hw_specifics_map_t hal_ll_tim_hw_specifics_map[] = +{ + #ifdef TIM_MODULE_1 + {HAL_LL_TIM1_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_1 - 1}, + #endif + + #ifdef TIM_MODULE_3 + {HAL_LL_TIM3_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_3 - 1}, + #endif + + #ifdef TIM_MODULE_14 + {HAL_LL_TIM14_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_14 - 1}, + #endif + + #ifdef TIM_MODULE_16 + {HAL_LL_TIM16_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_16 - 1}, + #endif + + #ifdef TIM_MODULE_17 + {HAL_LL_TIM17_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_17 - 1}, + #endif + + + {HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, HAL_LL_PIN_NC} +}; + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_tim_handle_register_t *low_level_handle; +static volatile hal_ll_tim_hw_specifics_map_t *hal_ll_tim_hw_specifics_map_local; + +static bool HAL_LL_TIM_IS_COMPLEMENTARY; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Enable TIM module 1 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim1_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 3 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim3_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 14 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim14_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 16 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim16_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 17 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim17_set_clock( bool hal_ll_state ); + + +/** + * @brief Enable TIM module gate clock. + * @param base - TIM module base + * address + * @return None + */ +static void _hal_ll_tim_set_clock( hal_ll_base_addr_t base, bool hal_ll_state ); + +/** + * @brief Select TIM clock source + * @param selector - clock source selector + * @return uint32_t - clock source + */ +static uint32_t _hal_ll_tim_clock_source( uint8_t selector ); + +/** + * @brief Based on selected TIM, + * return clock speed. + * @param base - TIM module base + * address + * @return uint32_t clock source. + */ +static uint32_t _hal_ll_tim_get_clock_speed( hal_ll_base_addr_t base ); + +/** + * @brief Initialize TIM module on hardware level. + * + * Initializes TIM module on hardware level, based on beforehand + * set configuration and module handler. + * + * @param map - Object specific context handler. + * @return none + * + */ +static void _hal_ll_tim_hw_init( hal_ll_tim_hw_specifics_map_t *map ); + +/** + * @brief Full TIM module initialization procedure. + * + * Initializes TIM module on hardware level, based on beforehand + * set configuration and module handler. Sets adequate pin alternate functions. + * Initializes module clock. + * + * @param map - Object specific context handler. + * @return none + * + */ +static void _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_t *map ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_tim_hw_specifics_map array index. + * + * @param handle - Object specific context handler. + * @return hal_ll_tim_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_tim_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Check if pin is adequate. + * + * Checks tim pin the user has passed with pre-defined + * pin in tim map. + * + * @param pin - TIM pre-defined pin name. + * @return hal_ll_pin_name_t Module index based on pin. + * + * Returns pre-defined module index from pin maps, if pin + * is adequate. + */ +static hal_ll_pin_name_t _hal_ll_tim_check_pin( hal_ll_pin_name_t pin, uint8_t *index, hal_ll_tim_handle_register_t *handle_map ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * TIM pin. + * + * @param[in] module_index TIM HW module index -- 0,1,2... + * @param[in] *index_list Array with TIM map index values + * + * @return None + */ +static void _hal_ll_tim_map_pin( uint8_t module_index, uint8_t index ); + +/** + * @brief Sets TIM pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if TIM is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param map - Object specific context handler. + * + * @param hal_ll_state - Init/De-init + * @return none + * + */ +static void _hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_map_t *map, bool hal_ll_state ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_tim_register_handle( hal_ll_pin_name_t pin, hal_ll_tim_handle_register_t *handle_map, + uint8_t *hal_module_id ) { + + uint8_t index; + uint16_t pin_check_result; + + if ( ( pin_check_result = _hal_ll_tim_check_pin( pin, &index, handle_map ) ) == HAL_LL_PIN_NC ) { + return HAL_LL_TIM_WRONG_PIN; + } + + if ( hal_ll_tim_hw_specifics_map[ pin_check_result ].config.pin != pin ){ + // Clear previous module alternate functions + _hal_ll_tim_alternate_functions_set_state( &hal_ll_tim_hw_specifics_map[ pin_check_result ], false ); + + _hal_ll_tim_map_pin( pin_check_result, index ); + + _hal_ll_tim_alternate_functions_set_state( &hal_ll_tim_hw_specifics_map[ pin_check_result ], true ); + + handle_map[ pin_check_result ].init_ll_state = false; + + hal_ll_module_state[ pin_check_result ].init_ll_state = false; + + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle = ( handle_t * )&hal_ll_tim_hw_specifics_map[ pin_check_result ].base; + + handle_map[ pin_check_result ].hal_ll_tim_handle = ( handle_t *)&hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle; + + return HAL_LL_TIM_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_tim( handle_t *handle ) { + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + hal_ll_tim_handle_register_t *hal_handle = (hal_ll_tim_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_tim_hw_specifics_map_local->module_index; + + _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_local ); + + hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle = (handle_t *)&hal_ll_tim_hw_specifics_map[ pin_check_result ].base; + hal_ll_module_state[ pin_check_result ].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_TIM_SUCCESS; +} + +uint32_t hal_ll_tim_set_freq( handle_t *handle, uint32_t freq_hz ) { + + uint32_t tmp_channel; + uint32_t ck_psc; + uint32_t local_base_addr; + uint32_t local_freq; + uint32_t tmp_freq; + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + if( hal_ll_tim_hw_specifics_map_local->base == HAL_LL_MODULE_ERROR ) { + return HAL_LL_TIM_MODULE_ERROR; + } + + low_level_handle->init_ll_state = false; + + tmp_channel = hal_ll_tim_hw_specifics_map_local->config.channel; + + // If complementary output channel is used. + if ( HAL_LL_TIM_IS_COMPLEMENTARY ) { + // Stop capture/compare. + hal_ll_hw_reg->ccer &= 1UL << tmp_channel * 4 + 2; + } else { + // Stop capture/compare. + hal_ll_hw_reg->ccer &= 1UL << tmp_channel * 4; + } + + // Set TIM duty to 0. + *( &hal_ll_hw_reg->ccr1 + hal_ll_tim_channel_static( tmp_channel ) ) = 0; + + hal_ll_tim_hw_specifics_map_local->freq_hz = freq_hz; + + local_freq = hal_ll_tim_hw_specifics_map_local->freq_hz; + local_base_addr = hal_ll_tim_hw_specifics_map_local->base; + + ck_psc = _hal_ll_tim_get_clock_speed( local_base_addr ) / local_freq; + + if ( ck_psc > UINT16_MAX ) { + tmp_freq = _hal_ll_tim_get_clock_speed( local_base_addr ) / UINT16_MAX; + hal_ll_tim_hw_specifics_map_local->freq_hz = tmp_freq; + } else { + tmp_freq = freq_hz; + hal_ll_tim_hw_specifics_map_local->freq_hz = freq_hz; + } + + _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_local ); + + low_level_handle->init_ll_state = true; + + return tmp_freq; +} + +hal_ll_err_t hal_ll_tim_set_duty( handle_t *handle, float duty_ratio ) { + + float tmp_duty; + uint32_t max_duty = 0; + uint16_t max_period; + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + if ( low_level_handle->init_ll_state == false ) { + hal_ll_tim_start( handle ); + low_level_handle->init_ll_state = true; + } + + tmp_duty = duty_ratio * 100; + max_period = hal_ll_tim_hw_specifics_map_local->max_period; + + max_duty = ( ( float )max_period / 100 ) * tmp_duty; + + *( &hal_ll_hw_reg->ccr1 + hal_ll_tim_channel_static( hal_ll_tim_hw_specifics_map_local->config.channel ) ) = max_duty; + + return HAL_LL_TIM_SUCCESS; +} + +hal_ll_err_t hal_ll_tim_start( handle_t *handle ) { + + uint32_t tmp_channel; + volatile uint32_t tmp, + *tmpPtr; + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + tmp_channel = hal_ll_tim_hw_specifics_map_local->config.channel; + + // Capture/Compare 1 output enable. + tmp = hal_ll_hw_reg->ccer; + + // If complementary output channel is used. + if ( HAL_LL_TIM_IS_COMPLEMENTARY ) { + // Capture/Compare complementary output enable + tmp |= ( 1UL << ( hal_ll_tim_channel_static( tmp_channel ) * 4 + 2 ) ); + // Capture/Compare complementary output polarity(ACTIVE HIGH). + tmp &= ~( 1UL << ( hal_ll_tim_channel_static( tmp_channel ) * 4 + 3 ) ); + } else { + // Capture/Compare output polarity. + tmp |= ( 1UL << ( hal_ll_tim_channel_static( tmp_channel ) * 4 ) ); + // Capture/Compare output polarity(ACTIVE HIGH). + tmp &= ~( 1UL << ( hal_ll_tim_channel_static( tmp_channel ) * 4 + 1 ) ); + } + + hal_ll_hw_reg->ccer = tmp; + + #if defined(TIM_MODULE_1) || defined(TIM_MODULE_8) || defined(TIM_MODULE_20) + // Main output enabled. + set_reg_bit( &hal_ll_hw_reg->bdtr, HAL_LL_TIM_BDTR_MOE_BIT ); + #endif + + tmpPtr = &hal_ll_hw_reg->ccmr1; + + if( hal_ll_tim_channel_static( tmp_channel ) > 1 ) { + tmpPtr = &hal_ll_hw_reg->ccmr2; + } + + if( ( hal_ll_tim_channel_static( tmp_channel ) / 2 ) * 2 != + hal_ll_tim_channel_static( tmp_channel ) ) { + // Clear CCxS, OCxM[0]. + *tmpPtr &= ~( HAL_LL_TIM_CCMR_CC2S_BIT0 | + HAL_LL_TIM_CCMR_CC2S_BIT1 | + HAL_LL_TIM_CCMR_OC2PE | + HAL_LL_TIM_CCMR_OC2M_BIT0 ); + // Set OCxM[2, 1] + *tmpPtr |= HAL_LL_TIM_CCMR_OC2M_BIT1 | HAL_LL_TIM_CCMR_OC2M_BIT2; + } else { + // Clear CCxS, OCxM[0]. + *tmpPtr &= ~( HAL_LL_TIM_CCMR_CC3S_BIT0 | + HAL_LL_TIM_CCMR_CC3S_BIT1 | + HAL_LL_TIM_CCMR_OC3PE | + HAL_LL_TIM_CCMR_OC3M_BIT0 ); + + // Set OCxM[2, 1]. + *tmpPtr |= HAL_LL_TIM_CCMR_OC3M_BIT1 | HAL_LL_TIM_CCMR_OC3M_BIT2; + } + + // Enable counter. + set_reg_bit( &hal_ll_hw_reg->cr1, HAL_LL_TIM_ENABLE_COUNTER_BIT ); + + return HAL_LL_TIM_SUCCESS; +} + +hal_ll_err_t hal_ll_tim_stop( handle_t *handle ) { + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + // If complementary output channel is used. + if ( HAL_LL_TIM_IS_COMPLEMENTARY ) { + hal_ll_hw_reg->ccer &= 1UL << hal_ll_tim_hw_specifics_map_local->config.channel * 4 + 2; + } else { + hal_ll_hw_reg->ccer &= 1UL << hal_ll_tim_hw_specifics_map_local->config.channel * 4; + } + + return HAL_LL_TIM_SUCCESS; +} + +void hal_ll_tim_close( handle_t *handle ) { + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_tim_get_module_state_address); + + if( low_level_handle->hal_ll_tim_handle != NULL ) { + low_level_handle->hal_ll_tim_handle = NULL; + low_level_handle->hal_drv_tim_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_tim_hw_specifics_map_local->max_period = 0; + hal_ll_tim_hw_specifics_map_local->freq_hz = 0; + + _hal_ll_tim_set_clock( hal_ll_tim_hw_specifics_map_local->base, true ); + _hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_map_local, false ); + _hal_ll_tim_set_clock( hal_ll_tim_hw_specifics_map_local->base, false ); + + hal_ll_tim_hw_specifics_map_local->config.pin = HAL_LL_PIN_NC; + hal_ll_tim_hw_specifics_map_local->config.channel = HAL_LL_PIN_NC; + hal_ll_tim_hw_specifics_map_local->config.af = NULL; + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static inline void _hal_ll_tim1_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APBENR2, HAL_LL_TIM_ENABLE_1 ); + } else { + clear_reg_bit( _RCC_APBENR2, HAL_LL_TIM_ENABLE_1 ); + } +} + +static inline void _hal_ll_tim3_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APBENR1, HAL_LL_TIM_ENABLE_3 ); + } else { + clear_reg_bit( _RCC_APBENR1, HAL_LL_TIM_ENABLE_3 ); + } +} + +static inline void _hal_ll_tim14_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APBENR2, HAL_LL_TIM_ENABLE_14 ); + } else { + clear_reg_bit( _RCC_APBENR2, HAL_LL_TIM_ENABLE_14 ); + } +} + +static inline void _hal_ll_tim16_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APBENR2, HAL_LL_TIM_ENABLE_16 ); + } else { + clear_reg_bit( _RCC_APBENR2, HAL_LL_TIM_ENABLE_16 ); + } +} + +static inline void _hal_ll_tim17_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APBENR2, HAL_LL_TIM_ENABLE_17 ); + } else { + clear_reg_bit( _RCC_APBENR2, HAL_LL_TIM_ENABLE_17 ); + } +} + + +static hal_ll_pin_name_t _hal_ll_tim_check_pin( hal_ll_pin_name_t pin, uint8_t *index, hal_ll_tim_handle_register_t *handle_map ) { + + hal_ll_pin_name_t pin_num; + uint8_t index_counter = 0; + uint8_t hal_ll_module_id = 0; + uint16_t map_size = ( sizeof( _tim_map ) / sizeof( hal_ll_tim_pin_map_t ) ); + + if ( HAL_LL_PIN_NC == pin ) { + return HAL_LL_PIN_NC; + } + + // Check if the selected pin is valid. + for ( pin_num = 0; pin_num < map_size; pin_num++ ) { + if ( _tim_map[ pin_num ].pin == pin ) { + // Get module number + hal_ll_module_id = _tim_map[ pin_num ].module_index; + if ( NULL == handle_map[hal_ll_module_id].hal_drv_tim_handle ) { + *index = pin_num; + return hal_ll_module_id; + } else if ( TIM_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + // By default return last error msg. + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static hal_ll_tim_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + + uint8_t hal_ll_module_count = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_tim_handle_register_t ) ); + static uint8_t hal_ll_module_error = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_tim_handle_register_t ) ); + + while( hal_ll_module_count-- ) { + if ( hal_ll_tim_get_base_from_hal_handle == hal_ll_tim_hw_specifics_map [ hal_ll_module_count ].base) { + return &hal_ll_tim_hw_specifics_map[ hal_ll_module_count ]; + } + } + + return &hal_ll_tim_hw_specifics_map[ hal_ll_module_error ]; +} + +static void _hal_ll_tim_set_clock( hal_ll_base_addr_t base, bool hal_ll_state ) { + + switch ( ( uint32_t )base ) { // 32-bit base address. + #ifdef TIM_MODULE_1 + case ( HAL_LL_TIM1_BASE_ADDR ): + _hal_ll_tim1_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_3 + case ( HAL_LL_TIM3_BASE_ADDR ): + _hal_ll_tim3_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_14 + case ( HAL_LL_TIM14_BASE_ADDR ): + _hal_ll_tim14_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_16 + case ( HAL_LL_TIM16_BASE_ADDR ): + _hal_ll_tim16_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_17 + case ( HAL_LL_TIM17_BASE_ADDR ): + _hal_ll_tim17_set_clock( hal_ll_state ); + break; + #endif + + } +} + +static uint32_t _hal_ll_tim_clock_source( uint8_t selector ) { + + rcc_clocks_t rcc_clocks; + + RCC_GetClocksFrequency( &rcc_clocks ); + + if( selector == HAL_LL_APB1_TIMER_CLOCK ) { + if( rcc_clocks.hclk/rcc_clocks.pclk > 1 ) { + return rcc_clocks.pclk * 2; + } else { + return rcc_clocks.pclk; + } + } + + return 0; +} + +static uint32_t _hal_ll_tim_get_clock_speed( hal_ll_base_addr_t base ) { + + switch ( ( uint32_t )base ) { + #ifdef TIM_MODULE_1 + case ( HAL_LL_TIM1_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM1_BUS ); + break; + #endif + + #ifdef TIM_MODULE_3 + case ( HAL_LL_TIM3_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM3_BUS ); + break; + #endif + + #ifdef TIM_MODULE_14 + case ( HAL_LL_TIM14_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM14_BUS ); + break; + #endif + + #ifdef TIM_MODULE_16 + case ( HAL_LL_TIM16_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM16_BUS ); + break; + #endif + + #ifdef TIM_MODULE_17 + case ( HAL_LL_TIM17_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM17_BUS ); + break; + #endif + + } + return 0; +} + +static void _hal_ll_tim_map_pin( uint8_t module_index, uint8_t index ) { + + uint8_t tmp_channel; + + // Map new pin + hal_ll_tim_hw_specifics_map[ module_index ].config.pin = _tim_map[ index ].pin; + tmp_channel = _tim_map[ index ].channel; + hal_ll_tim_hw_specifics_map[ module_index ].config.af = _tim_map[ index ].af; + + if ( tmp_channel >= HAL_LL_TIM_CHANNEL_1N ) { + HAL_LL_TIM_IS_COMPLEMENTARY = true; + hal_ll_tim_hw_specifics_map[ module_index ].config.channel = tmp_channel - 4; + } else { + HAL_LL_TIM_IS_COMPLEMENTARY = false; + hal_ll_tim_hw_specifics_map[ module_index ].config.channel = tmp_channel; + } +} + +static void _hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_map_t *map, bool hal_ll_state ) { + + module_struct module; + uint32_t tim_config = 0; + + if( map->config.pin != HAL_LL_PIN_NC ) { + if( hal_ll_state == false ) { + tim_config = GPIO_CFG_MODE_ALT_FUNCTION | + GPIO_CFG_SPEED_LOW | + GPIO_CFG_OTYPE_PP; + } else { + tim_config = GPIO_CFG_MODE_ALT_FUNCTION | + GPIO_CFG_SPEED_HIGH | + GPIO_CFG_OTYPE_PP; + } + + module.pins[ 0 ] = VALUE( map->config.pin, map->config.af ); + module.pins[ 1 ] = GPIO_MODULE_STRUCT_END; + + module.configs[ 0 ] = tim_config; + module.configs[ 1 ] = GPIO_MODULE_STRUCT_END; + + hal_ll_gpio_module_struct_init( &module, hal_ll_state ); + } +} + +static void _hal_ll_tim_hw_init( hal_ll_tim_hw_specifics_map_t *map ) { + + uint32_t ck_psc; + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( map->base ); + + // Counter used as upcounter. + clear_reg_bit( &hal_ll_hw_reg->cr1, HAL_LL_TIM_CR1_DIR_BIT ); + + // Get clock speed. + ck_psc = _hal_ll_tim_get_clock_speed( map->base ) / map->freq_hz; + + // This should not be the case. ck_psc should not be greater than 65535, which is max value. + if( ck_psc > UINT16_MAX ) { + // In case of duty period beeing greater than 65535 set ck_psc to max value. + ck_psc = UINT16_MAX - 1; // Because of ( ck_psc / UINT16_MAX + 1 ) ), has to be minus 1. + }else if ( ck_psc < 1 ) { + ck_psc = 1; + } + + // Write prescale value. + hal_ll_hw_reg->psc = ( uint16_t )( ck_psc / UINT16_MAX ); + + // Write max count value. + hal_ll_hw_reg->arr = ( uint16_t )( ck_psc/( ck_psc / UINT16_MAX + 1 ) ); + + // Write max period to global array. + map->max_period = ( uint16_t )ck_psc; +} + +static void _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_t *map ) { + + _hal_ll_tim_set_clock( map->base, true ); + + _hal_ll_tim_alternate_functions_set_state( map, true ); + + _hal_ll_tim_hw_init( map ); +} +// ------------------------------------------------------------------------- END + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_74/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_74/CMakeLists.cmake new file mode 100644 index 000000000..d1fbf5472 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_74/CMakeLists.cmake @@ -0,0 +1,9 @@ +if(${MCU_NAME} MATCHES "^STM32G051C6$|^STM32G051F6$|^STM32G051G6$|^STM32G051K6$|^STM32G051C8$|^STM32G051F8$|^STM32G051G8$|^STM32G051K8$") + set(tim_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_tim.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_74") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_74") + list(APPEND hal_ll_def_list "STM32G0xx") + list(APPEND hal_ll_def_list "STM32G05xx") + list(APPEND hal_ll_def_list "STM32G051xx") + set(tim_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/tim/hal_ll_tim_pin_map/implementations/doc_ds_74") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_74/hal_ll_tim.c b/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_74/hal_ll_tim.c new file mode 100644 index 000000000..6254d7635 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_74/hal_ll_tim.c @@ -0,0 +1,902 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_tim.c + * @brief TIM HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_gpio.h" +#include "hal_ll_rcc.h" +#include "hal_ll_tim.h" +#include "hal_ll_tim_pin_map.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_tim_handle_register_t hal_ll_module_state[ TIM_MODULE_COUNT ]; + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< CR1 constants. */ +#define HAL_LL_TIM_ENABLE_COUNTER_BIT 0 +#define HAL_LL_TIM_BDTR_MOE_BIT 15 +#define HAL_LL_TIM_BDTR_MOE 0x8000 + +#define HAL_LL_TIM_CCMR_CC2S_BIT0 0x100u +#define HAL_LL_TIM_CCMR_CC2S_BIT1 0x200u +#define HAL_LL_TIM_CCMR_OC2PE 0x800u +#define HAL_LL_TIM_CCMR_OC2M_BIT0 0x1000u +#define HAL_LL_TIM_CCMR_OC2M_BIT1 0x2000u +#define HAL_LL_TIM_CCMR_OC2M_BIT2 0x4000u + +#define HAL_LL_TIM_CCMR_CC3S_BIT0 0x1u +#define HAL_LL_TIM_CCMR_CC3S_BIT1 0x2u +#define HAL_LL_TIM_CCMR_OC3PE 0x8u +#define HAL_LL_TIM_CCMR_OC3M_BIT0 0x10u +#define HAL_LL_TIM_CCMR_OC3M_BIT1 0x20u +#define HAL_LL_TIM_CCMR_OC3M_BIT2 0x40u + +#define HAL_LL_TIM_CR1_DIR 0x10 +#define HAL_LL_TIM_CR1_DIR_BIT 4 + +#define HAL_LL_TIM_ENABLE_1 11 + +#define HAL_LL_TIM_ENABLE_2 0 + +#define HAL_LL_TIM_ENABLE_3 1 + +#define HAL_LL_TIM_ENABLE_14 15 + +#define HAL_LL_TIM_ENABLE_15 16 + +#define HAL_LL_TIM_ENABLE_16 17 + +#define HAL_LL_TIM_ENABLE_17 18 + + +#define HAL_LL_APB1_TIMER_CLOCK 1 + + + +#define hal_ll_tim_channel_static( _chn ) ( _chn-1 ) + +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_tim_get_base_struct(_handle) ((hal_ll_tim_base_handle_t *)_handle) + +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_tim_get_module_state_address ((hal_ll_tim_handle_register_t *)*handle) + +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_tim_get_handle ( hal_ll_tim_handle_register_t * )hal_ll_tim_get_module_state_address->hal_ll_tim_handle + +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_tim_get_base_from_hal_handle ((hal_ll_tim_hw_specifics_map_t *)((hal_ll_tim_handle_register_t *)\ + (((hal_ll_tim_handle_register_t *)(handle))->hal_ll_tim_handle))->hal_ll_tim_handle)->base + +// -------------------------------------------------------------- PRIVATE TYPES +/*!< @brief TIM register structure. */ +typedef struct +{ + uint32_t cr1; /* Address offset 0x00 */ + uint32_t cr2; /* Address offset 0x04 */ + uint32_t smcr; /* Address offset 0x08 */ + uint32_t dier; /* Address offset 0x0C */ + uint32_t sr; /* Address offset 0x10 */ + uint32_t egr; /* Address offset 0x14 */ + uint32_t ccmr1; /* Address offset 0x18 */ + uint32_t ccmr2; /* Address offset 0x1C */ + uint32_t ccer; /* Address offset 0x20 */ + uint32_t cnt; /* Address offset 0x24 */ + uint32_t psc; /* Address offset 0x28 */ + uint32_t arr; /* Address offset 0x2C */ + uint32_t rcr; /* Address offset 0x30 */ + uint32_t ccr1; /* Address offset 0x34 */ + uint32_t ccr2; /* Address offset 0x38 */ + uint32_t ccr3; /* Address offset 0x3C */ + uint32_t ccr4; /* Address offset 0x40 */ + uint32_t bdtr; /* Address offset 0x44 */ + uint32_t dcr; /* Address offset 0x48 */ + uint32_t dmar; /* Address offset 0x4C */ + uint32_t tim2_5_or; /* Address offset 0x50 */ +} hal_ll_tim_base_handle_t; + +/*!< @brief TIM pin structure */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_channel_t channel; + uint32_t af; +} hal_ll_tim_t; + +/*!< @brief TIM hw specific structure */ +typedef struct +{ + hal_ll_base_addr_t base; + hal_ll_tim_t config; + uint16_t max_period; + uint32_t freq_hz; + hal_ll_pin_name_t module_index; +} hal_ll_tim_hw_specifics_map_t; + +/*!< @brief TIM hw specific error values */ +typedef enum +{ + HAL_LL_TIM_SUCCESS = 0, + HAL_LL_TIM_MODULE_ERROR, + HAL_LL_TIM_WRONG_PIN, + + HAL_LL_TIM_ERROR = (-1) +} hal_ll_tim_err_t; + +// ------------------------------------------------------------------ VARIABLES +/*!< @brief TIM specific info */ +static hal_ll_tim_hw_specifics_map_t hal_ll_tim_hw_specifics_map[] = +{ + #ifdef TIM_MODULE_1 + {HAL_LL_TIM1_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_1 - 1}, + #endif + + #ifdef TIM_MODULE_2 + {HAL_LL_TIM2_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_2 - 1}, + #endif + + #ifdef TIM_MODULE_3 + {HAL_LL_TIM3_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_3 - 1}, + #endif + + #ifdef TIM_MODULE_14 + {HAL_LL_TIM14_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_14 - 1}, + #endif + + #ifdef TIM_MODULE_15 + {HAL_LL_TIM15_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_15 - 1}, + #endif + + #ifdef TIM_MODULE_16 + {HAL_LL_TIM16_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_16 - 1}, + #endif + + #ifdef TIM_MODULE_17 + {HAL_LL_TIM17_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_17 - 1}, + #endif + + + {HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, HAL_LL_PIN_NC} +}; + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_tim_handle_register_t *low_level_handle; +static volatile hal_ll_tim_hw_specifics_map_t *hal_ll_tim_hw_specifics_map_local; + +static bool HAL_LL_TIM_IS_COMPLEMENTARY; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Enable TIM module 1 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim1_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 2 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim2_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 3 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim3_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 14 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim14_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 15 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim15_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 16 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim16_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 17 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim17_set_clock( bool hal_ll_state ); + + +/** + * @brief Enable TIM module gate clock. + * @param base - TIM module base + * address + * @return None + */ +static void _hal_ll_tim_set_clock( hal_ll_base_addr_t base, bool hal_ll_state ); + +/** + * @brief Select TIM clock source + * @param selector - clock source selector + * @return uint32_t - clock source + */ +static uint32_t _hal_ll_tim_clock_source( uint8_t selector ); + +/** + * @brief Based on selected TIM, + * return clock speed. + * @param base - TIM module base + * address + * @return uint32_t clock source. + */ +static uint32_t _hal_ll_tim_get_clock_speed( hal_ll_base_addr_t base ); + +/** + * @brief Initialize TIM module on hardware level. + * + * Initializes TIM module on hardware level, based on beforehand + * set configuration and module handler. + * + * @param map - Object specific context handler. + * @return none + * + */ +static void _hal_ll_tim_hw_init( hal_ll_tim_hw_specifics_map_t *map ); + +/** + * @brief Full TIM module initialization procedure. + * + * Initializes TIM module on hardware level, based on beforehand + * set configuration and module handler. Sets adequate pin alternate functions. + * Initializes module clock. + * + * @param map - Object specific context handler. + * @return none + * + */ +static void _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_t *map ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_tim_hw_specifics_map array index. + * + * @param handle - Object specific context handler. + * @return hal_ll_tim_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_tim_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Check if pin is adequate. + * + * Checks tim pin the user has passed with pre-defined + * pin in tim map. + * + * @param pin - TIM pre-defined pin name. + * @return hal_ll_pin_name_t Module index based on pin. + * + * Returns pre-defined module index from pin maps, if pin + * is adequate. + */ +static hal_ll_pin_name_t _hal_ll_tim_check_pin( hal_ll_pin_name_t pin, uint8_t *index, hal_ll_tim_handle_register_t *handle_map ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * TIM pin. + * + * @param[in] module_index TIM HW module index -- 0,1,2... + * @param[in] *index_list Array with TIM map index values + * + * @return None + */ +static void _hal_ll_tim_map_pin( uint8_t module_index, uint8_t index ); + +/** + * @brief Sets TIM pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if TIM is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param map - Object specific context handler. + * + * @param hal_ll_state - Init/De-init + * @return none + * + */ +static void _hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_map_t *map, bool hal_ll_state ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_tim_register_handle( hal_ll_pin_name_t pin, hal_ll_tim_handle_register_t *handle_map, + uint8_t *hal_module_id ) { + + uint8_t index; + uint16_t pin_check_result; + + if ( ( pin_check_result = _hal_ll_tim_check_pin( pin, &index, handle_map ) ) == HAL_LL_PIN_NC ) { + return HAL_LL_TIM_WRONG_PIN; + } + + if ( hal_ll_tim_hw_specifics_map[ pin_check_result ].config.pin != pin ){ + // Clear previous module alternate functions + _hal_ll_tim_alternate_functions_set_state( &hal_ll_tim_hw_specifics_map[ pin_check_result ], false ); + + _hal_ll_tim_map_pin( pin_check_result, index ); + + _hal_ll_tim_alternate_functions_set_state( &hal_ll_tim_hw_specifics_map[ pin_check_result ], true ); + + handle_map[ pin_check_result ].init_ll_state = false; + + hal_ll_module_state[ pin_check_result ].init_ll_state = false; + + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle = ( handle_t * )&hal_ll_tim_hw_specifics_map[ pin_check_result ].base; + + handle_map[ pin_check_result ].hal_ll_tim_handle = ( handle_t *)&hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle; + + return HAL_LL_TIM_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_tim( handle_t *handle ) { + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + hal_ll_tim_handle_register_t *hal_handle = (hal_ll_tim_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_tim_hw_specifics_map_local->module_index; + + _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_local ); + + hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle = (handle_t *)&hal_ll_tim_hw_specifics_map[ pin_check_result ].base; + hal_ll_module_state[ pin_check_result ].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_TIM_SUCCESS; +} + +uint32_t hal_ll_tim_set_freq( handle_t *handle, uint32_t freq_hz ) { + + uint32_t tmp_channel; + uint32_t ck_psc; + uint32_t local_base_addr; + uint32_t local_freq; + uint32_t tmp_freq; + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + if( hal_ll_tim_hw_specifics_map_local->base == HAL_LL_MODULE_ERROR ) { + return HAL_LL_TIM_MODULE_ERROR; + } + + low_level_handle->init_ll_state = false; + + tmp_channel = hal_ll_tim_hw_specifics_map_local->config.channel; + + // If complementary output channel is used. + if ( HAL_LL_TIM_IS_COMPLEMENTARY ) { + // Stop capture/compare. + hal_ll_hw_reg->ccer &= 1UL << tmp_channel * 4 + 2; + } else { + // Stop capture/compare. + hal_ll_hw_reg->ccer &= 1UL << tmp_channel * 4; + } + + // Set TIM duty to 0. + *( &hal_ll_hw_reg->ccr1 + hal_ll_tim_channel_static( tmp_channel ) ) = 0; + + hal_ll_tim_hw_specifics_map_local->freq_hz = freq_hz; + + local_freq = hal_ll_tim_hw_specifics_map_local->freq_hz; + local_base_addr = hal_ll_tim_hw_specifics_map_local->base; + + ck_psc = _hal_ll_tim_get_clock_speed( local_base_addr ) / local_freq; + + if ( ck_psc > UINT16_MAX ) { + tmp_freq = _hal_ll_tim_get_clock_speed( local_base_addr ) / UINT16_MAX; + hal_ll_tim_hw_specifics_map_local->freq_hz = tmp_freq; + } else { + tmp_freq = freq_hz; + hal_ll_tim_hw_specifics_map_local->freq_hz = freq_hz; + } + + _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_local ); + + low_level_handle->init_ll_state = true; + + return tmp_freq; +} + +hal_ll_err_t hal_ll_tim_set_duty( handle_t *handle, float duty_ratio ) { + + float tmp_duty; + uint32_t max_duty = 0; + uint16_t max_period; + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + if ( low_level_handle->init_ll_state == false ) { + hal_ll_tim_start( handle ); + low_level_handle->init_ll_state = true; + } + + tmp_duty = duty_ratio * 100; + max_period = hal_ll_tim_hw_specifics_map_local->max_period; + + max_duty = ( ( float )max_period / 100 ) * tmp_duty; + + *( &hal_ll_hw_reg->ccr1 + hal_ll_tim_channel_static( hal_ll_tim_hw_specifics_map_local->config.channel ) ) = max_duty; + + return HAL_LL_TIM_SUCCESS; +} + +hal_ll_err_t hal_ll_tim_start( handle_t *handle ) { + + uint32_t tmp_channel; + volatile uint32_t tmp, + *tmpPtr; + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + tmp_channel = hal_ll_tim_hw_specifics_map_local->config.channel; + + // Capture/Compare 1 output enable. + tmp = hal_ll_hw_reg->ccer; + + // If complementary output channel is used. + if ( HAL_LL_TIM_IS_COMPLEMENTARY ) { + // Capture/Compare complementary output enable + tmp |= ( 1UL << ( hal_ll_tim_channel_static( tmp_channel ) * 4 + 2 ) ); + // Capture/Compare complementary output polarity(ACTIVE HIGH). + tmp &= ~( 1UL << ( hal_ll_tim_channel_static( tmp_channel ) * 4 + 3 ) ); + } else { + // Capture/Compare output polarity. + tmp |= ( 1UL << ( hal_ll_tim_channel_static( tmp_channel ) * 4 ) ); + // Capture/Compare output polarity(ACTIVE HIGH). + tmp &= ~( 1UL << ( hal_ll_tim_channel_static( tmp_channel ) * 4 + 1 ) ); + } + + hal_ll_hw_reg->ccer = tmp; + + #if defined(TIM_MODULE_1) || defined(TIM_MODULE_8) || defined(TIM_MODULE_20) + // Main output enabled. + set_reg_bit( &hal_ll_hw_reg->bdtr, HAL_LL_TIM_BDTR_MOE_BIT ); + #endif + + tmpPtr = &hal_ll_hw_reg->ccmr1; + + if( hal_ll_tim_channel_static( tmp_channel ) > 1 ) { + tmpPtr = &hal_ll_hw_reg->ccmr2; + } + + if( ( hal_ll_tim_channel_static( tmp_channel ) / 2 ) * 2 != + hal_ll_tim_channel_static( tmp_channel ) ) { + // Clear CCxS, OCxM[0]. + *tmpPtr &= ~( HAL_LL_TIM_CCMR_CC2S_BIT0 | + HAL_LL_TIM_CCMR_CC2S_BIT1 | + HAL_LL_TIM_CCMR_OC2PE | + HAL_LL_TIM_CCMR_OC2M_BIT0 ); + // Set OCxM[2, 1] + *tmpPtr |= HAL_LL_TIM_CCMR_OC2M_BIT1 | HAL_LL_TIM_CCMR_OC2M_BIT2; + } else { + // Clear CCxS, OCxM[0]. + *tmpPtr &= ~( HAL_LL_TIM_CCMR_CC3S_BIT0 | + HAL_LL_TIM_CCMR_CC3S_BIT1 | + HAL_LL_TIM_CCMR_OC3PE | + HAL_LL_TIM_CCMR_OC3M_BIT0 ); + + // Set OCxM[2, 1]. + *tmpPtr |= HAL_LL_TIM_CCMR_OC3M_BIT1 | HAL_LL_TIM_CCMR_OC3M_BIT2; + } + + // Enable counter. + set_reg_bit( &hal_ll_hw_reg->cr1, HAL_LL_TIM_ENABLE_COUNTER_BIT ); + + return HAL_LL_TIM_SUCCESS; +} + +hal_ll_err_t hal_ll_tim_stop( handle_t *handle ) { + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + // If complementary output channel is used. + if ( HAL_LL_TIM_IS_COMPLEMENTARY ) { + hal_ll_hw_reg->ccer &= 1UL << hal_ll_tim_hw_specifics_map_local->config.channel * 4 + 2; + } else { + hal_ll_hw_reg->ccer &= 1UL << hal_ll_tim_hw_specifics_map_local->config.channel * 4; + } + + return HAL_LL_TIM_SUCCESS; +} + +void hal_ll_tim_close( handle_t *handle ) { + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_tim_get_module_state_address); + + if( low_level_handle->hal_ll_tim_handle != NULL ) { + low_level_handle->hal_ll_tim_handle = NULL; + low_level_handle->hal_drv_tim_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_tim_hw_specifics_map_local->max_period = 0; + hal_ll_tim_hw_specifics_map_local->freq_hz = 0; + + _hal_ll_tim_set_clock( hal_ll_tim_hw_specifics_map_local->base, true ); + _hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_map_local, false ); + _hal_ll_tim_set_clock( hal_ll_tim_hw_specifics_map_local->base, false ); + + hal_ll_tim_hw_specifics_map_local->config.pin = HAL_LL_PIN_NC; + hal_ll_tim_hw_specifics_map_local->config.channel = HAL_LL_PIN_NC; + hal_ll_tim_hw_specifics_map_local->config.af = NULL; + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static inline void _hal_ll_tim1_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APBENR2, HAL_LL_TIM_ENABLE_1 ); + } else { + clear_reg_bit( _RCC_APBENR2, HAL_LL_TIM_ENABLE_1 ); + } +} + +static inline void _hal_ll_tim2_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APBENR1, HAL_LL_TIM_ENABLE_2 ); + } else { + clear_reg_bit( _RCC_APBENR1, HAL_LL_TIM_ENABLE_2 ); + } +} + +static inline void _hal_ll_tim3_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APBENR1, HAL_LL_TIM_ENABLE_3 ); + } else { + clear_reg_bit( _RCC_APBENR1, HAL_LL_TIM_ENABLE_3 ); + } +} + +static inline void _hal_ll_tim14_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APBENR2, HAL_LL_TIM_ENABLE_14 ); + } else { + clear_reg_bit( _RCC_APBENR2, HAL_LL_TIM_ENABLE_14 ); + } +} + +static inline void _hal_ll_tim15_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APBENR2, HAL_LL_TIM_ENABLE_15 ); + } else { + clear_reg_bit( _RCC_APBENR2, HAL_LL_TIM_ENABLE_15 ); + } +} + +static inline void _hal_ll_tim16_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APBENR2, HAL_LL_TIM_ENABLE_16 ); + } else { + clear_reg_bit( _RCC_APBENR2, HAL_LL_TIM_ENABLE_16 ); + } +} + +static inline void _hal_ll_tim17_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APBENR2, HAL_LL_TIM_ENABLE_17 ); + } else { + clear_reg_bit( _RCC_APBENR2, HAL_LL_TIM_ENABLE_17 ); + } +} + + +static hal_ll_pin_name_t _hal_ll_tim_check_pin( hal_ll_pin_name_t pin, uint8_t *index, hal_ll_tim_handle_register_t *handle_map ) { + + hal_ll_pin_name_t pin_num; + uint8_t index_counter = 0; + uint8_t hal_ll_module_id = 0; + uint16_t map_size = ( sizeof( _tim_map ) / sizeof( hal_ll_tim_pin_map_t ) ); + + if ( HAL_LL_PIN_NC == pin ) { + return HAL_LL_PIN_NC; + } + + // Check if the selected pin is valid. + for ( pin_num = 0; pin_num < map_size; pin_num++ ) { + if ( _tim_map[ pin_num ].pin == pin ) { + // Get module number + hal_ll_module_id = _tim_map[ pin_num ].module_index; + if ( NULL == handle_map[hal_ll_module_id].hal_drv_tim_handle ) { + *index = pin_num; + return hal_ll_module_id; + } else if ( TIM_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + // By default return last error msg. + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static hal_ll_tim_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + + uint8_t hal_ll_module_count = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_tim_handle_register_t ) ); + static uint8_t hal_ll_module_error = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_tim_handle_register_t ) ); + + while( hal_ll_module_count-- ) { + if ( hal_ll_tim_get_base_from_hal_handle == hal_ll_tim_hw_specifics_map [ hal_ll_module_count ].base) { + return &hal_ll_tim_hw_specifics_map[ hal_ll_module_count ]; + } + } + + return &hal_ll_tim_hw_specifics_map[ hal_ll_module_error ]; +} + +static void _hal_ll_tim_set_clock( hal_ll_base_addr_t base, bool hal_ll_state ) { + + switch ( ( uint32_t )base ) { // 32-bit base address. + #ifdef TIM_MODULE_1 + case ( HAL_LL_TIM1_BASE_ADDR ): + _hal_ll_tim1_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_2 + case ( HAL_LL_TIM2_BASE_ADDR ): + _hal_ll_tim2_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_3 + case ( HAL_LL_TIM3_BASE_ADDR ): + _hal_ll_tim3_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_14 + case ( HAL_LL_TIM14_BASE_ADDR ): + _hal_ll_tim14_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_15 + case ( HAL_LL_TIM15_BASE_ADDR ): + _hal_ll_tim15_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_16 + case ( HAL_LL_TIM16_BASE_ADDR ): + _hal_ll_tim16_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_17 + case ( HAL_LL_TIM17_BASE_ADDR ): + _hal_ll_tim17_set_clock( hal_ll_state ); + break; + #endif + + } +} + +static uint32_t _hal_ll_tim_clock_source( uint8_t selector ) { + + rcc_clocks_t rcc_clocks; + + RCC_GetClocksFrequency( &rcc_clocks ); + + if( selector == HAL_LL_APB1_TIMER_CLOCK ) { + if( rcc_clocks.hclk/rcc_clocks.pclk > 1 ) { + return rcc_clocks.pclk * 2; + } else { + return rcc_clocks.pclk; + } + } + + return 0; +} + +static uint32_t _hal_ll_tim_get_clock_speed( hal_ll_base_addr_t base ) { + + switch ( ( uint32_t )base ) { + #ifdef TIM_MODULE_1 + case ( HAL_LL_TIM1_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM1_BUS ); + break; + #endif + + #ifdef TIM_MODULE_2 + case ( HAL_LL_TIM2_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM2_BUS ); + break; + #endif + + #ifdef TIM_MODULE_3 + case ( HAL_LL_TIM3_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM3_BUS ); + break; + #endif + + #ifdef TIM_MODULE_14 + case ( HAL_LL_TIM14_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM14_BUS ); + break; + #endif + + #ifdef TIM_MODULE_15 + case ( HAL_LL_TIM15_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM15_BUS ); + break; + #endif + + #ifdef TIM_MODULE_16 + case ( HAL_LL_TIM16_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM16_BUS ); + break; + #endif + + #ifdef TIM_MODULE_17 + case ( HAL_LL_TIM17_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM17_BUS ); + break; + #endif + + } + return 0; +} + +static void _hal_ll_tim_map_pin( uint8_t module_index, uint8_t index ) { + + uint8_t tmp_channel; + + // Map new pin + hal_ll_tim_hw_specifics_map[ module_index ].config.pin = _tim_map[ index ].pin; + tmp_channel = _tim_map[ index ].channel; + hal_ll_tim_hw_specifics_map[ module_index ].config.af = _tim_map[ index ].af; + + if ( tmp_channel >= HAL_LL_TIM_CHANNEL_1N ) { + HAL_LL_TIM_IS_COMPLEMENTARY = true; + hal_ll_tim_hw_specifics_map[ module_index ].config.channel = tmp_channel - 4; + } else { + HAL_LL_TIM_IS_COMPLEMENTARY = false; + hal_ll_tim_hw_specifics_map[ module_index ].config.channel = tmp_channel; + } +} + +static void _hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_map_t *map, bool hal_ll_state ) { + + module_struct module; + uint32_t tim_config = 0; + + if( map->config.pin != HAL_LL_PIN_NC ) { + if( hal_ll_state == false ) { + tim_config = GPIO_CFG_MODE_ALT_FUNCTION | + GPIO_CFG_SPEED_LOW | + GPIO_CFG_OTYPE_PP; + } else { + tim_config = GPIO_CFG_MODE_ALT_FUNCTION | + GPIO_CFG_SPEED_HIGH | + GPIO_CFG_OTYPE_PP; + } + + module.pins[ 0 ] = VALUE( map->config.pin, map->config.af ); + module.pins[ 1 ] = GPIO_MODULE_STRUCT_END; + + module.configs[ 0 ] = tim_config; + module.configs[ 1 ] = GPIO_MODULE_STRUCT_END; + + hal_ll_gpio_module_struct_init( &module, hal_ll_state ); + } +} + +static void _hal_ll_tim_hw_init( hal_ll_tim_hw_specifics_map_t *map ) { + + uint32_t ck_psc; + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( map->base ); + + // Counter used as upcounter. + clear_reg_bit( &hal_ll_hw_reg->cr1, HAL_LL_TIM_CR1_DIR_BIT ); + + // Get clock speed. + ck_psc = _hal_ll_tim_get_clock_speed( map->base ) / map->freq_hz; + + // This should not be the case. ck_psc should not be greater than 65535, which is max value. + if( ck_psc > UINT16_MAX ) { + // In case of duty period beeing greater than 65535 set ck_psc to max value. + ck_psc = UINT16_MAX - 1; // Because of ( ck_psc / UINT16_MAX + 1 ) ), has to be minus 1. + }else if ( ck_psc < 1 ) { + ck_psc = 1; + } + + // Write prescale value. + hal_ll_hw_reg->psc = ( uint16_t )( ck_psc / UINT16_MAX ); + + // Write max count value. + hal_ll_hw_reg->arr = ( uint16_t )( ck_psc/( ck_psc / UINT16_MAX + 1 ) ); + + // Write max period to global array. + map->max_period = ( uint16_t )ck_psc; +} + +static void _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_t *map ) { + + _hal_ll_tim_set_clock( map->base, true ); + + _hal_ll_tim_alternate_functions_set_state( map, true ); + + _hal_ll_tim_hw_init( map ); +} +// ------------------------------------------------------------------------- END + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_75/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_75/CMakeLists.cmake new file mode 100644 index 000000000..3c563c3af --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_75/CMakeLists.cmake @@ -0,0 +1,9 @@ +if(${MCU_NAME} MATCHES "^STM32G061C6$|^STM32G061F6$|^STM32G061G6$|^STM32G061K6$|^STM32G061C8$|^STM32G061F8$|^STM32G061G8$|^STM32G061K8$") + set(tim_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_tim.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_75") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_75") + list(APPEND hal_ll_def_list "STM32G0xx") + list(APPEND hal_ll_def_list "STM32G06xx") + list(APPEND hal_ll_def_list "STM32G061xx") + set(tim_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/tim/hal_ll_tim_pin_map/implementations/doc_ds_75") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_75/hal_ll_tim.c b/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_75/hal_ll_tim.c new file mode 100644 index 000000000..6254d7635 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_75/hal_ll_tim.c @@ -0,0 +1,902 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_tim.c + * @brief TIM HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_gpio.h" +#include "hal_ll_rcc.h" +#include "hal_ll_tim.h" +#include "hal_ll_tim_pin_map.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_tim_handle_register_t hal_ll_module_state[ TIM_MODULE_COUNT ]; + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< CR1 constants. */ +#define HAL_LL_TIM_ENABLE_COUNTER_BIT 0 +#define HAL_LL_TIM_BDTR_MOE_BIT 15 +#define HAL_LL_TIM_BDTR_MOE 0x8000 + +#define HAL_LL_TIM_CCMR_CC2S_BIT0 0x100u +#define HAL_LL_TIM_CCMR_CC2S_BIT1 0x200u +#define HAL_LL_TIM_CCMR_OC2PE 0x800u +#define HAL_LL_TIM_CCMR_OC2M_BIT0 0x1000u +#define HAL_LL_TIM_CCMR_OC2M_BIT1 0x2000u +#define HAL_LL_TIM_CCMR_OC2M_BIT2 0x4000u + +#define HAL_LL_TIM_CCMR_CC3S_BIT0 0x1u +#define HAL_LL_TIM_CCMR_CC3S_BIT1 0x2u +#define HAL_LL_TIM_CCMR_OC3PE 0x8u +#define HAL_LL_TIM_CCMR_OC3M_BIT0 0x10u +#define HAL_LL_TIM_CCMR_OC3M_BIT1 0x20u +#define HAL_LL_TIM_CCMR_OC3M_BIT2 0x40u + +#define HAL_LL_TIM_CR1_DIR 0x10 +#define HAL_LL_TIM_CR1_DIR_BIT 4 + +#define HAL_LL_TIM_ENABLE_1 11 + +#define HAL_LL_TIM_ENABLE_2 0 + +#define HAL_LL_TIM_ENABLE_3 1 + +#define HAL_LL_TIM_ENABLE_14 15 + +#define HAL_LL_TIM_ENABLE_15 16 + +#define HAL_LL_TIM_ENABLE_16 17 + +#define HAL_LL_TIM_ENABLE_17 18 + + +#define HAL_LL_APB1_TIMER_CLOCK 1 + + + +#define hal_ll_tim_channel_static( _chn ) ( _chn-1 ) + +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_tim_get_base_struct(_handle) ((hal_ll_tim_base_handle_t *)_handle) + +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_tim_get_module_state_address ((hal_ll_tim_handle_register_t *)*handle) + +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_tim_get_handle ( hal_ll_tim_handle_register_t * )hal_ll_tim_get_module_state_address->hal_ll_tim_handle + +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_tim_get_base_from_hal_handle ((hal_ll_tim_hw_specifics_map_t *)((hal_ll_tim_handle_register_t *)\ + (((hal_ll_tim_handle_register_t *)(handle))->hal_ll_tim_handle))->hal_ll_tim_handle)->base + +// -------------------------------------------------------------- PRIVATE TYPES +/*!< @brief TIM register structure. */ +typedef struct +{ + uint32_t cr1; /* Address offset 0x00 */ + uint32_t cr2; /* Address offset 0x04 */ + uint32_t smcr; /* Address offset 0x08 */ + uint32_t dier; /* Address offset 0x0C */ + uint32_t sr; /* Address offset 0x10 */ + uint32_t egr; /* Address offset 0x14 */ + uint32_t ccmr1; /* Address offset 0x18 */ + uint32_t ccmr2; /* Address offset 0x1C */ + uint32_t ccer; /* Address offset 0x20 */ + uint32_t cnt; /* Address offset 0x24 */ + uint32_t psc; /* Address offset 0x28 */ + uint32_t arr; /* Address offset 0x2C */ + uint32_t rcr; /* Address offset 0x30 */ + uint32_t ccr1; /* Address offset 0x34 */ + uint32_t ccr2; /* Address offset 0x38 */ + uint32_t ccr3; /* Address offset 0x3C */ + uint32_t ccr4; /* Address offset 0x40 */ + uint32_t bdtr; /* Address offset 0x44 */ + uint32_t dcr; /* Address offset 0x48 */ + uint32_t dmar; /* Address offset 0x4C */ + uint32_t tim2_5_or; /* Address offset 0x50 */ +} hal_ll_tim_base_handle_t; + +/*!< @brief TIM pin structure */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_channel_t channel; + uint32_t af; +} hal_ll_tim_t; + +/*!< @brief TIM hw specific structure */ +typedef struct +{ + hal_ll_base_addr_t base; + hal_ll_tim_t config; + uint16_t max_period; + uint32_t freq_hz; + hal_ll_pin_name_t module_index; +} hal_ll_tim_hw_specifics_map_t; + +/*!< @brief TIM hw specific error values */ +typedef enum +{ + HAL_LL_TIM_SUCCESS = 0, + HAL_LL_TIM_MODULE_ERROR, + HAL_LL_TIM_WRONG_PIN, + + HAL_LL_TIM_ERROR = (-1) +} hal_ll_tim_err_t; + +// ------------------------------------------------------------------ VARIABLES +/*!< @brief TIM specific info */ +static hal_ll_tim_hw_specifics_map_t hal_ll_tim_hw_specifics_map[] = +{ + #ifdef TIM_MODULE_1 + {HAL_LL_TIM1_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_1 - 1}, + #endif + + #ifdef TIM_MODULE_2 + {HAL_LL_TIM2_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_2 - 1}, + #endif + + #ifdef TIM_MODULE_3 + {HAL_LL_TIM3_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_3 - 1}, + #endif + + #ifdef TIM_MODULE_14 + {HAL_LL_TIM14_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_14 - 1}, + #endif + + #ifdef TIM_MODULE_15 + {HAL_LL_TIM15_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_15 - 1}, + #endif + + #ifdef TIM_MODULE_16 + {HAL_LL_TIM16_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_16 - 1}, + #endif + + #ifdef TIM_MODULE_17 + {HAL_LL_TIM17_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_17 - 1}, + #endif + + + {HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, HAL_LL_PIN_NC} +}; + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_tim_handle_register_t *low_level_handle; +static volatile hal_ll_tim_hw_specifics_map_t *hal_ll_tim_hw_specifics_map_local; + +static bool HAL_LL_TIM_IS_COMPLEMENTARY; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Enable TIM module 1 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim1_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 2 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim2_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 3 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim3_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 14 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim14_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 15 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim15_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 16 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim16_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 17 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim17_set_clock( bool hal_ll_state ); + + +/** + * @brief Enable TIM module gate clock. + * @param base - TIM module base + * address + * @return None + */ +static void _hal_ll_tim_set_clock( hal_ll_base_addr_t base, bool hal_ll_state ); + +/** + * @brief Select TIM clock source + * @param selector - clock source selector + * @return uint32_t - clock source + */ +static uint32_t _hal_ll_tim_clock_source( uint8_t selector ); + +/** + * @brief Based on selected TIM, + * return clock speed. + * @param base - TIM module base + * address + * @return uint32_t clock source. + */ +static uint32_t _hal_ll_tim_get_clock_speed( hal_ll_base_addr_t base ); + +/** + * @brief Initialize TIM module on hardware level. + * + * Initializes TIM module on hardware level, based on beforehand + * set configuration and module handler. + * + * @param map - Object specific context handler. + * @return none + * + */ +static void _hal_ll_tim_hw_init( hal_ll_tim_hw_specifics_map_t *map ); + +/** + * @brief Full TIM module initialization procedure. + * + * Initializes TIM module on hardware level, based on beforehand + * set configuration and module handler. Sets adequate pin alternate functions. + * Initializes module clock. + * + * @param map - Object specific context handler. + * @return none + * + */ +static void _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_t *map ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_tim_hw_specifics_map array index. + * + * @param handle - Object specific context handler. + * @return hal_ll_tim_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_tim_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Check if pin is adequate. + * + * Checks tim pin the user has passed with pre-defined + * pin in tim map. + * + * @param pin - TIM pre-defined pin name. + * @return hal_ll_pin_name_t Module index based on pin. + * + * Returns pre-defined module index from pin maps, if pin + * is adequate. + */ +static hal_ll_pin_name_t _hal_ll_tim_check_pin( hal_ll_pin_name_t pin, uint8_t *index, hal_ll_tim_handle_register_t *handle_map ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * TIM pin. + * + * @param[in] module_index TIM HW module index -- 0,1,2... + * @param[in] *index_list Array with TIM map index values + * + * @return None + */ +static void _hal_ll_tim_map_pin( uint8_t module_index, uint8_t index ); + +/** + * @brief Sets TIM pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if TIM is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param map - Object specific context handler. + * + * @param hal_ll_state - Init/De-init + * @return none + * + */ +static void _hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_map_t *map, bool hal_ll_state ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_tim_register_handle( hal_ll_pin_name_t pin, hal_ll_tim_handle_register_t *handle_map, + uint8_t *hal_module_id ) { + + uint8_t index; + uint16_t pin_check_result; + + if ( ( pin_check_result = _hal_ll_tim_check_pin( pin, &index, handle_map ) ) == HAL_LL_PIN_NC ) { + return HAL_LL_TIM_WRONG_PIN; + } + + if ( hal_ll_tim_hw_specifics_map[ pin_check_result ].config.pin != pin ){ + // Clear previous module alternate functions + _hal_ll_tim_alternate_functions_set_state( &hal_ll_tim_hw_specifics_map[ pin_check_result ], false ); + + _hal_ll_tim_map_pin( pin_check_result, index ); + + _hal_ll_tim_alternate_functions_set_state( &hal_ll_tim_hw_specifics_map[ pin_check_result ], true ); + + handle_map[ pin_check_result ].init_ll_state = false; + + hal_ll_module_state[ pin_check_result ].init_ll_state = false; + + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle = ( handle_t * )&hal_ll_tim_hw_specifics_map[ pin_check_result ].base; + + handle_map[ pin_check_result ].hal_ll_tim_handle = ( handle_t *)&hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle; + + return HAL_LL_TIM_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_tim( handle_t *handle ) { + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + hal_ll_tim_handle_register_t *hal_handle = (hal_ll_tim_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_tim_hw_specifics_map_local->module_index; + + _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_local ); + + hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle = (handle_t *)&hal_ll_tim_hw_specifics_map[ pin_check_result ].base; + hal_ll_module_state[ pin_check_result ].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_TIM_SUCCESS; +} + +uint32_t hal_ll_tim_set_freq( handle_t *handle, uint32_t freq_hz ) { + + uint32_t tmp_channel; + uint32_t ck_psc; + uint32_t local_base_addr; + uint32_t local_freq; + uint32_t tmp_freq; + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + if( hal_ll_tim_hw_specifics_map_local->base == HAL_LL_MODULE_ERROR ) { + return HAL_LL_TIM_MODULE_ERROR; + } + + low_level_handle->init_ll_state = false; + + tmp_channel = hal_ll_tim_hw_specifics_map_local->config.channel; + + // If complementary output channel is used. + if ( HAL_LL_TIM_IS_COMPLEMENTARY ) { + // Stop capture/compare. + hal_ll_hw_reg->ccer &= 1UL << tmp_channel * 4 + 2; + } else { + // Stop capture/compare. + hal_ll_hw_reg->ccer &= 1UL << tmp_channel * 4; + } + + // Set TIM duty to 0. + *( &hal_ll_hw_reg->ccr1 + hal_ll_tim_channel_static( tmp_channel ) ) = 0; + + hal_ll_tim_hw_specifics_map_local->freq_hz = freq_hz; + + local_freq = hal_ll_tim_hw_specifics_map_local->freq_hz; + local_base_addr = hal_ll_tim_hw_specifics_map_local->base; + + ck_psc = _hal_ll_tim_get_clock_speed( local_base_addr ) / local_freq; + + if ( ck_psc > UINT16_MAX ) { + tmp_freq = _hal_ll_tim_get_clock_speed( local_base_addr ) / UINT16_MAX; + hal_ll_tim_hw_specifics_map_local->freq_hz = tmp_freq; + } else { + tmp_freq = freq_hz; + hal_ll_tim_hw_specifics_map_local->freq_hz = freq_hz; + } + + _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_local ); + + low_level_handle->init_ll_state = true; + + return tmp_freq; +} + +hal_ll_err_t hal_ll_tim_set_duty( handle_t *handle, float duty_ratio ) { + + float tmp_duty; + uint32_t max_duty = 0; + uint16_t max_period; + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + if ( low_level_handle->init_ll_state == false ) { + hal_ll_tim_start( handle ); + low_level_handle->init_ll_state = true; + } + + tmp_duty = duty_ratio * 100; + max_period = hal_ll_tim_hw_specifics_map_local->max_period; + + max_duty = ( ( float )max_period / 100 ) * tmp_duty; + + *( &hal_ll_hw_reg->ccr1 + hal_ll_tim_channel_static( hal_ll_tim_hw_specifics_map_local->config.channel ) ) = max_duty; + + return HAL_LL_TIM_SUCCESS; +} + +hal_ll_err_t hal_ll_tim_start( handle_t *handle ) { + + uint32_t tmp_channel; + volatile uint32_t tmp, + *tmpPtr; + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + tmp_channel = hal_ll_tim_hw_specifics_map_local->config.channel; + + // Capture/Compare 1 output enable. + tmp = hal_ll_hw_reg->ccer; + + // If complementary output channel is used. + if ( HAL_LL_TIM_IS_COMPLEMENTARY ) { + // Capture/Compare complementary output enable + tmp |= ( 1UL << ( hal_ll_tim_channel_static( tmp_channel ) * 4 + 2 ) ); + // Capture/Compare complementary output polarity(ACTIVE HIGH). + tmp &= ~( 1UL << ( hal_ll_tim_channel_static( tmp_channel ) * 4 + 3 ) ); + } else { + // Capture/Compare output polarity. + tmp |= ( 1UL << ( hal_ll_tim_channel_static( tmp_channel ) * 4 ) ); + // Capture/Compare output polarity(ACTIVE HIGH). + tmp &= ~( 1UL << ( hal_ll_tim_channel_static( tmp_channel ) * 4 + 1 ) ); + } + + hal_ll_hw_reg->ccer = tmp; + + #if defined(TIM_MODULE_1) || defined(TIM_MODULE_8) || defined(TIM_MODULE_20) + // Main output enabled. + set_reg_bit( &hal_ll_hw_reg->bdtr, HAL_LL_TIM_BDTR_MOE_BIT ); + #endif + + tmpPtr = &hal_ll_hw_reg->ccmr1; + + if( hal_ll_tim_channel_static( tmp_channel ) > 1 ) { + tmpPtr = &hal_ll_hw_reg->ccmr2; + } + + if( ( hal_ll_tim_channel_static( tmp_channel ) / 2 ) * 2 != + hal_ll_tim_channel_static( tmp_channel ) ) { + // Clear CCxS, OCxM[0]. + *tmpPtr &= ~( HAL_LL_TIM_CCMR_CC2S_BIT0 | + HAL_LL_TIM_CCMR_CC2S_BIT1 | + HAL_LL_TIM_CCMR_OC2PE | + HAL_LL_TIM_CCMR_OC2M_BIT0 ); + // Set OCxM[2, 1] + *tmpPtr |= HAL_LL_TIM_CCMR_OC2M_BIT1 | HAL_LL_TIM_CCMR_OC2M_BIT2; + } else { + // Clear CCxS, OCxM[0]. + *tmpPtr &= ~( HAL_LL_TIM_CCMR_CC3S_BIT0 | + HAL_LL_TIM_CCMR_CC3S_BIT1 | + HAL_LL_TIM_CCMR_OC3PE | + HAL_LL_TIM_CCMR_OC3M_BIT0 ); + + // Set OCxM[2, 1]. + *tmpPtr |= HAL_LL_TIM_CCMR_OC3M_BIT1 | HAL_LL_TIM_CCMR_OC3M_BIT2; + } + + // Enable counter. + set_reg_bit( &hal_ll_hw_reg->cr1, HAL_LL_TIM_ENABLE_COUNTER_BIT ); + + return HAL_LL_TIM_SUCCESS; +} + +hal_ll_err_t hal_ll_tim_stop( handle_t *handle ) { + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + // If complementary output channel is used. + if ( HAL_LL_TIM_IS_COMPLEMENTARY ) { + hal_ll_hw_reg->ccer &= 1UL << hal_ll_tim_hw_specifics_map_local->config.channel * 4 + 2; + } else { + hal_ll_hw_reg->ccer &= 1UL << hal_ll_tim_hw_specifics_map_local->config.channel * 4; + } + + return HAL_LL_TIM_SUCCESS; +} + +void hal_ll_tim_close( handle_t *handle ) { + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_tim_get_module_state_address); + + if( low_level_handle->hal_ll_tim_handle != NULL ) { + low_level_handle->hal_ll_tim_handle = NULL; + low_level_handle->hal_drv_tim_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_tim_hw_specifics_map_local->max_period = 0; + hal_ll_tim_hw_specifics_map_local->freq_hz = 0; + + _hal_ll_tim_set_clock( hal_ll_tim_hw_specifics_map_local->base, true ); + _hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_map_local, false ); + _hal_ll_tim_set_clock( hal_ll_tim_hw_specifics_map_local->base, false ); + + hal_ll_tim_hw_specifics_map_local->config.pin = HAL_LL_PIN_NC; + hal_ll_tim_hw_specifics_map_local->config.channel = HAL_LL_PIN_NC; + hal_ll_tim_hw_specifics_map_local->config.af = NULL; + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static inline void _hal_ll_tim1_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APBENR2, HAL_LL_TIM_ENABLE_1 ); + } else { + clear_reg_bit( _RCC_APBENR2, HAL_LL_TIM_ENABLE_1 ); + } +} + +static inline void _hal_ll_tim2_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APBENR1, HAL_LL_TIM_ENABLE_2 ); + } else { + clear_reg_bit( _RCC_APBENR1, HAL_LL_TIM_ENABLE_2 ); + } +} + +static inline void _hal_ll_tim3_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APBENR1, HAL_LL_TIM_ENABLE_3 ); + } else { + clear_reg_bit( _RCC_APBENR1, HAL_LL_TIM_ENABLE_3 ); + } +} + +static inline void _hal_ll_tim14_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APBENR2, HAL_LL_TIM_ENABLE_14 ); + } else { + clear_reg_bit( _RCC_APBENR2, HAL_LL_TIM_ENABLE_14 ); + } +} + +static inline void _hal_ll_tim15_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APBENR2, HAL_LL_TIM_ENABLE_15 ); + } else { + clear_reg_bit( _RCC_APBENR2, HAL_LL_TIM_ENABLE_15 ); + } +} + +static inline void _hal_ll_tim16_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APBENR2, HAL_LL_TIM_ENABLE_16 ); + } else { + clear_reg_bit( _RCC_APBENR2, HAL_LL_TIM_ENABLE_16 ); + } +} + +static inline void _hal_ll_tim17_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APBENR2, HAL_LL_TIM_ENABLE_17 ); + } else { + clear_reg_bit( _RCC_APBENR2, HAL_LL_TIM_ENABLE_17 ); + } +} + + +static hal_ll_pin_name_t _hal_ll_tim_check_pin( hal_ll_pin_name_t pin, uint8_t *index, hal_ll_tim_handle_register_t *handle_map ) { + + hal_ll_pin_name_t pin_num; + uint8_t index_counter = 0; + uint8_t hal_ll_module_id = 0; + uint16_t map_size = ( sizeof( _tim_map ) / sizeof( hal_ll_tim_pin_map_t ) ); + + if ( HAL_LL_PIN_NC == pin ) { + return HAL_LL_PIN_NC; + } + + // Check if the selected pin is valid. + for ( pin_num = 0; pin_num < map_size; pin_num++ ) { + if ( _tim_map[ pin_num ].pin == pin ) { + // Get module number + hal_ll_module_id = _tim_map[ pin_num ].module_index; + if ( NULL == handle_map[hal_ll_module_id].hal_drv_tim_handle ) { + *index = pin_num; + return hal_ll_module_id; + } else if ( TIM_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + // By default return last error msg. + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static hal_ll_tim_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + + uint8_t hal_ll_module_count = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_tim_handle_register_t ) ); + static uint8_t hal_ll_module_error = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_tim_handle_register_t ) ); + + while( hal_ll_module_count-- ) { + if ( hal_ll_tim_get_base_from_hal_handle == hal_ll_tim_hw_specifics_map [ hal_ll_module_count ].base) { + return &hal_ll_tim_hw_specifics_map[ hal_ll_module_count ]; + } + } + + return &hal_ll_tim_hw_specifics_map[ hal_ll_module_error ]; +} + +static void _hal_ll_tim_set_clock( hal_ll_base_addr_t base, bool hal_ll_state ) { + + switch ( ( uint32_t )base ) { // 32-bit base address. + #ifdef TIM_MODULE_1 + case ( HAL_LL_TIM1_BASE_ADDR ): + _hal_ll_tim1_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_2 + case ( HAL_LL_TIM2_BASE_ADDR ): + _hal_ll_tim2_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_3 + case ( HAL_LL_TIM3_BASE_ADDR ): + _hal_ll_tim3_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_14 + case ( HAL_LL_TIM14_BASE_ADDR ): + _hal_ll_tim14_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_15 + case ( HAL_LL_TIM15_BASE_ADDR ): + _hal_ll_tim15_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_16 + case ( HAL_LL_TIM16_BASE_ADDR ): + _hal_ll_tim16_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_17 + case ( HAL_LL_TIM17_BASE_ADDR ): + _hal_ll_tim17_set_clock( hal_ll_state ); + break; + #endif + + } +} + +static uint32_t _hal_ll_tim_clock_source( uint8_t selector ) { + + rcc_clocks_t rcc_clocks; + + RCC_GetClocksFrequency( &rcc_clocks ); + + if( selector == HAL_LL_APB1_TIMER_CLOCK ) { + if( rcc_clocks.hclk/rcc_clocks.pclk > 1 ) { + return rcc_clocks.pclk * 2; + } else { + return rcc_clocks.pclk; + } + } + + return 0; +} + +static uint32_t _hal_ll_tim_get_clock_speed( hal_ll_base_addr_t base ) { + + switch ( ( uint32_t )base ) { + #ifdef TIM_MODULE_1 + case ( HAL_LL_TIM1_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM1_BUS ); + break; + #endif + + #ifdef TIM_MODULE_2 + case ( HAL_LL_TIM2_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM2_BUS ); + break; + #endif + + #ifdef TIM_MODULE_3 + case ( HAL_LL_TIM3_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM3_BUS ); + break; + #endif + + #ifdef TIM_MODULE_14 + case ( HAL_LL_TIM14_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM14_BUS ); + break; + #endif + + #ifdef TIM_MODULE_15 + case ( HAL_LL_TIM15_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM15_BUS ); + break; + #endif + + #ifdef TIM_MODULE_16 + case ( HAL_LL_TIM16_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM16_BUS ); + break; + #endif + + #ifdef TIM_MODULE_17 + case ( HAL_LL_TIM17_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM17_BUS ); + break; + #endif + + } + return 0; +} + +static void _hal_ll_tim_map_pin( uint8_t module_index, uint8_t index ) { + + uint8_t tmp_channel; + + // Map new pin + hal_ll_tim_hw_specifics_map[ module_index ].config.pin = _tim_map[ index ].pin; + tmp_channel = _tim_map[ index ].channel; + hal_ll_tim_hw_specifics_map[ module_index ].config.af = _tim_map[ index ].af; + + if ( tmp_channel >= HAL_LL_TIM_CHANNEL_1N ) { + HAL_LL_TIM_IS_COMPLEMENTARY = true; + hal_ll_tim_hw_specifics_map[ module_index ].config.channel = tmp_channel - 4; + } else { + HAL_LL_TIM_IS_COMPLEMENTARY = false; + hal_ll_tim_hw_specifics_map[ module_index ].config.channel = tmp_channel; + } +} + +static void _hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_map_t *map, bool hal_ll_state ) { + + module_struct module; + uint32_t tim_config = 0; + + if( map->config.pin != HAL_LL_PIN_NC ) { + if( hal_ll_state == false ) { + tim_config = GPIO_CFG_MODE_ALT_FUNCTION | + GPIO_CFG_SPEED_LOW | + GPIO_CFG_OTYPE_PP; + } else { + tim_config = GPIO_CFG_MODE_ALT_FUNCTION | + GPIO_CFG_SPEED_HIGH | + GPIO_CFG_OTYPE_PP; + } + + module.pins[ 0 ] = VALUE( map->config.pin, map->config.af ); + module.pins[ 1 ] = GPIO_MODULE_STRUCT_END; + + module.configs[ 0 ] = tim_config; + module.configs[ 1 ] = GPIO_MODULE_STRUCT_END; + + hal_ll_gpio_module_struct_init( &module, hal_ll_state ); + } +} + +static void _hal_ll_tim_hw_init( hal_ll_tim_hw_specifics_map_t *map ) { + + uint32_t ck_psc; + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( map->base ); + + // Counter used as upcounter. + clear_reg_bit( &hal_ll_hw_reg->cr1, HAL_LL_TIM_CR1_DIR_BIT ); + + // Get clock speed. + ck_psc = _hal_ll_tim_get_clock_speed( map->base ) / map->freq_hz; + + // This should not be the case. ck_psc should not be greater than 65535, which is max value. + if( ck_psc > UINT16_MAX ) { + // In case of duty period beeing greater than 65535 set ck_psc to max value. + ck_psc = UINT16_MAX - 1; // Because of ( ck_psc / UINT16_MAX + 1 ) ), has to be minus 1. + }else if ( ck_psc < 1 ) { + ck_psc = 1; + } + + // Write prescale value. + hal_ll_hw_reg->psc = ( uint16_t )( ck_psc / UINT16_MAX ); + + // Write max count value. + hal_ll_hw_reg->arr = ( uint16_t )( ck_psc/( ck_psc / UINT16_MAX + 1 ) ); + + // Write max period to global array. + map->max_period = ( uint16_t )ck_psc; +} + +static void _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_t *map ) { + + _hal_ll_tim_set_clock( map->base, true ); + + _hal_ll_tim_alternate_functions_set_state( map, true ); + + _hal_ll_tim_hw_init( map ); +} +// ------------------------------------------------------------------------- END + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_80/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_80/CMakeLists.cmake new file mode 100644 index 000000000..a23c31833 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_80/CMakeLists.cmake @@ -0,0 +1,9 @@ +if(${MCU_NAME} MATCHES "^STM32G0B1CB$|^STM32G0B1KB$|^STM32G0B1MB$|^STM32G0B1RB$|^STM32G0B1VB$|^STM32G0B1CC$|^STM32G0B1KC$|^STM32G0B1MC$|^STM32G0B1RC$|^STM32G0B1VC$|^STM32G0B1CE$|^STM32G0B1KE$|^STM32G0B1ME$|^STM32G0B1NE$|^STM32G0B1RE$|^STM32G0B1VE$") + set(tim_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_tim.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_80") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_80") + list(APPEND hal_ll_def_list "STM32G0xx") + list(APPEND hal_ll_def_list "STM32G0Bxx") + list(APPEND hal_ll_def_list "STM32G0B1xx") + set(tim_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/tim/hal_ll_tim_pin_map/implementations/doc_ds_80") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_80/hal_ll_tim.c b/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_80/hal_ll_tim.c new file mode 100644 index 000000000..2217c526d --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_80/hal_ll_tim.c @@ -0,0 +1,898 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_tim.c + * @brief TIM HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_gpio.h" +#include "hal_ll_rcc.h" +#include "hal_ll_tim.h" +#include "hal_ll_tim_pin_map.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_tim_handle_register_t hal_ll_module_state[ TIM_MODULE_COUNT ]; + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< CR1 constants. */ +#define HAL_LL_TIM_ENABLE_COUNTER_BIT 0 +#define HAL_LL_TIM_BDTR_MOE_BIT 15 +#define HAL_LL_TIM_BDTR_MOE 0x8000 + +#define HAL_LL_TIM_CCMR_CC2S_BIT0 0x100u +#define HAL_LL_TIM_CCMR_CC2S_BIT1 0x200u +#define HAL_LL_TIM_CCMR_OC2PE 0x800u +#define HAL_LL_TIM_CCMR_OC2M_BIT0 0x1000u +#define HAL_LL_TIM_CCMR_OC2M_BIT1 0x2000u +#define HAL_LL_TIM_CCMR_OC2M_BIT2 0x4000u + +#define HAL_LL_TIM_CCMR_CC3S_BIT0 0x1u +#define HAL_LL_TIM_CCMR_CC3S_BIT1 0x2u +#define HAL_LL_TIM_CCMR_OC3PE 0x8u +#define HAL_LL_TIM_CCMR_OC3M_BIT0 0x10u +#define HAL_LL_TIM_CCMR_OC3M_BIT1 0x20u +#define HAL_LL_TIM_CCMR_OC3M_BIT2 0x40u + +#define HAL_LL_TIM_CR1_DIR 0x10 +#define HAL_LL_TIM_CR1_DIR_BIT 4 + +#define HAL_LL_TIM_ENABLE_1 11 +#define HAL_LL_TIM_ENABLE_2 0 +#define HAL_LL_TIM_ENABLE_3 1 +#define HAL_LL_TIM_ENABLE_4 2 +#define HAL_LL_TIM_ENABLE_14 15 +#define HAL_LL_TIM_ENABLE_15 16 +#define HAL_LL_TIM_ENABLE_16 17 +#define HAL_LL_TIM_ENABLE_17 18 + +#define HAL_LL_APB1_TIMER_CLOCK 1 + +#define hal_ll_tim_channel_static( _chn ) ( _chn-1 ) + +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_tim_get_base_struct(_handle) ((hal_ll_tim_base_handle_t *)_handle) + +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_tim_get_module_state_address ((hal_ll_tim_handle_register_t *)*handle) + +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_tim_get_handle ( hal_ll_tim_handle_register_t * )hal_ll_tim_get_module_state_address->hal_ll_tim_handle + +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_tim_get_base_from_hal_handle ((hal_ll_tim_hw_specifics_map_t *)((hal_ll_tim_handle_register_t *)\ + (((hal_ll_tim_handle_register_t *)(handle))->hal_ll_tim_handle))->hal_ll_tim_handle)->base + +// -------------------------------------------------------------- PRIVATE TYPES +/*!< @brief TIM register structure. */ +typedef struct +{ + uint32_t cr1; /* Address offset 0x00 */ + uint32_t cr2; /* Address offset 0x04 */ + uint32_t smcr; /* Address offset 0x08 */ + uint32_t dier; /* Address offset 0x0C */ + uint32_t sr; /* Address offset 0x10 */ + uint32_t egr; /* Address offset 0x14 */ + uint32_t ccmr1; /* Address offset 0x18 */ + uint32_t ccmr2; /* Address offset 0x1C */ + uint32_t ccer; /* Address offset 0x20 */ + uint32_t cnt; /* Address offset 0x24 */ + uint32_t psc; /* Address offset 0x28 */ + uint32_t arr; /* Address offset 0x2C */ + uint32_t rcr; /* Address offset 0x30 */ + uint32_t ccr1; /* Address offset 0x34 */ + uint32_t ccr2; /* Address offset 0x38 */ + uint32_t ccr3; /* Address offset 0x3C */ + uint32_t ccr4; /* Address offset 0x40 */ + uint32_t bdtr; /* Address offset 0x44 */ + uint32_t dcr; /* Address offset 0x48 */ + uint32_t dmar; /* Address offset 0x4C */ + uint32_t tim2_5_or; /* Address offset 0x50 */ +} hal_ll_tim_base_handle_t; + +/*!< @brief TIM pin structure */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_channel_t channel; + uint32_t af; +} hal_ll_tim_t; + +/*!< @brief TIM hw specific structure */ +typedef struct +{ + hal_ll_base_addr_t base; + hal_ll_tim_t config; + uint16_t max_period; + uint32_t freq_hz; + hal_ll_pin_name_t module_index; +} hal_ll_tim_hw_specifics_map_t; + +/*!< @brief TIM hw specific error values */ +typedef enum +{ + HAL_LL_TIM_SUCCESS = 0, + HAL_LL_TIM_MODULE_ERROR, + HAL_LL_TIM_WRONG_PIN, + + HAL_LL_TIM_ERROR = (-1) +} hal_ll_tim_err_t; + +// ------------------------------------------------------------------ VARIABLES +/*!< @brief TIM specific info */ +static hal_ll_tim_hw_specifics_map_t hal_ll_tim_hw_specifics_map[] = +{ + #ifdef TIM_MODULE_1 + {HAL_LL_TIM1_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_1 - 1}, + #endif + #ifdef TIM_MODULE_2 + {HAL_LL_TIM2_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_2 - 1}, + #endif + #ifdef TIM_MODULE_3 + {HAL_LL_TIM3_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_3 - 1}, + #endif + #ifdef TIM_MODULE_4 + {HAL_LL_TIM4_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_4 - 1}, + #endif + #ifdef TIM_MODULE_14 + {HAL_LL_TIM14_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_14 - 1}, + #endif + #ifdef TIM_MODULE_15 + {HAL_LL_TIM15_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_15 - 1}, + #endif + #ifdef TIM_MODULE_16 + {HAL_LL_TIM16_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_16 - 1}, + #endif + #ifdef TIM_MODULE_17 + {HAL_LL_TIM17_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_17 - 1}, + #endif + {HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, HAL_LL_PIN_NC} +}; + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_tim_handle_register_t *low_level_handle; +static volatile hal_ll_tim_hw_specifics_map_t *hal_ll_tim_hw_specifics_map_local; + +static bool HAL_LL_TIM_IS_COMPLEMENTARY; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Enable TIM module 1 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim1_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 2 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim2_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 3 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim3_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 4 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim4_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 14 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim14_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 15 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim15_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 16 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim16_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 17 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim17_set_clock( bool hal_ll_state ); + + +/** + * @brief Enable TIM module gate clock. + * @param base - TIM module base + * address + * @return None + */ +static void _hal_ll_tim_set_clock( hal_ll_base_addr_t base, bool hal_ll_state ); + +/** + * @brief Select TIM clock source + * @param selector - clock source selector + * @return uint32_t - clock source + */ +static uint32_t _hal_ll_tim_clock_source( uint8_t selector ); + +/** + * @brief Based on selected TIM, + * return clock speed. + * @param base - TIM module base + * address + * @return uint32_t clock source. + */ +static uint32_t _hal_ll_tim_get_clock_speed( hal_ll_base_addr_t base ); + +/** + * @brief Initialize TIM module on hardware level. + * + * Initializes TIM module on hardware level, based on beforehand + * set configuration and module handler. + * + * @param map - Object specific context handler. + * @return none + * + */ +static void _hal_ll_tim_hw_init( hal_ll_tim_hw_specifics_map_t *map ); + +/** + * @brief Full TIM module initialization procedure. + * + * Initializes TIM module on hardware level, based on beforehand + * set configuration and module handler. Sets adequate pin alternate functions. + * Initializes module clock. + * + * @param map - Object specific context handler. + * @return none + * + */ +static void _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_t *map ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_tim_hw_specifics_map array index. + * + * @param handle - Object specific context handler. + * @return hal_ll_tim_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_tim_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Check if pin is adequate. + * + * Checks tim pin the user has passed with pre-defined + * pin in tim map. + * + * @param pin - TIM pre-defined pin name. + * @return hal_ll_pin_name_t Module index based on pin. + * + * Returns pre-defined module index from pin maps, if pin + * is adequate. + */ +static hal_ll_pin_name_t _hal_ll_tim_check_pin( hal_ll_pin_name_t pin, uint8_t *index, hal_ll_tim_handle_register_t *handle_map ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * TIM pin. + * + * @param[in] module_index TIM HW module index -- 0,1,2... + * @param[in] *index_list Array with TIM map index values + * + * @return None + */ +static void _hal_ll_tim_map_pin( uint8_t module_index, uint8_t index ); + +/** + * @brief Sets TIM pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if TIM is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param map - Object specific context handler. + * + * @param hal_ll_state - Init/De-init + * @return none + * + */ +static void _hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_map_t *map, bool hal_ll_state ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_tim_register_handle( hal_ll_pin_name_t pin, hal_ll_tim_handle_register_t *handle_map, + uint8_t *hal_module_id ) { + + uint8_t index; + uint16_t pin_check_result; + + if ( ( pin_check_result = _hal_ll_tim_check_pin( pin, &index, handle_map ) ) == HAL_LL_PIN_NC ) { + return HAL_LL_TIM_WRONG_PIN; + } + + if ( hal_ll_tim_hw_specifics_map[ pin_check_result ].config.pin != pin ){ + // Clear previous module alternate functions + _hal_ll_tim_alternate_functions_set_state( &hal_ll_tim_hw_specifics_map[ pin_check_result ], false ); + + _hal_ll_tim_map_pin( pin_check_result, index ); + + _hal_ll_tim_alternate_functions_set_state( &hal_ll_tim_hw_specifics_map[ pin_check_result ], true ); + + handle_map[ pin_check_result ].init_ll_state = false; + + hal_ll_module_state[ pin_check_result ].init_ll_state = false; + + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle = ( handle_t * )&hal_ll_tim_hw_specifics_map[ pin_check_result ].base; + + handle_map[ pin_check_result ].hal_ll_tim_handle = ( handle_t *)&hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle; + + return HAL_LL_TIM_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_tim( handle_t *handle ) { + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + hal_ll_tim_handle_register_t *hal_handle = (hal_ll_tim_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_tim_hw_specifics_map_local->module_index; + + _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_local ); + + hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle = (handle_t *)&hal_ll_tim_hw_specifics_map[ pin_check_result ].base; + hal_ll_module_state[ pin_check_result ].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_TIM_SUCCESS; +} + +uint32_t hal_ll_tim_set_freq( handle_t *handle, uint32_t freq_hz ) { + + uint32_t tmp_channel; + uint32_t ck_psc; + uint32_t local_base_addr; + uint32_t local_freq; + uint32_t tmp_freq; + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + if( hal_ll_tim_hw_specifics_map_local->base == HAL_LL_MODULE_ERROR ) { + return HAL_LL_TIM_MODULE_ERROR; + } + + low_level_handle->init_ll_state = false; + + tmp_channel = hal_ll_tim_hw_specifics_map_local->config.channel; + + // If complementary output channel is used. + if ( HAL_LL_TIM_IS_COMPLEMENTARY ) { + // Stop capture/compare. + hal_ll_hw_reg->ccer &= 1UL << tmp_channel * 4 + 2; + } else { + // Stop capture/compare. + hal_ll_hw_reg->ccer &= 1UL << tmp_channel * 4; + } + + // Set TIM duty to 0. + *( &hal_ll_hw_reg->ccr1 + hal_ll_tim_channel_static( tmp_channel ) ) = 0; + + hal_ll_tim_hw_specifics_map_local->freq_hz = freq_hz; + + local_freq = hal_ll_tim_hw_specifics_map_local->freq_hz; + local_base_addr = hal_ll_tim_hw_specifics_map_local->base; + + ck_psc = _hal_ll_tim_get_clock_speed( local_base_addr ) / local_freq; + + if ( ck_psc > UINT16_MAX ) { + tmp_freq = _hal_ll_tim_get_clock_speed( local_base_addr ) / UINT16_MAX; + hal_ll_tim_hw_specifics_map_local->freq_hz = tmp_freq; + } else { + tmp_freq = freq_hz; + hal_ll_tim_hw_specifics_map_local->freq_hz = freq_hz; + } + + _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_local ); + + low_level_handle->init_ll_state = true; + + return tmp_freq; +} + +hal_ll_err_t hal_ll_tim_set_duty( handle_t *handle, float duty_ratio ) { + + float tmp_duty; + uint32_t max_duty = 0; + uint16_t max_period; + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + if ( low_level_handle->init_ll_state == false ) { + hal_ll_tim_start( handle ); + low_level_handle->init_ll_state = true; + } + + tmp_duty = duty_ratio * 100; + max_period = hal_ll_tim_hw_specifics_map_local->max_period; + + max_duty = ( ( float )max_period / 100 ) * tmp_duty; + + *( &hal_ll_hw_reg->ccr1 + hal_ll_tim_channel_static( hal_ll_tim_hw_specifics_map_local->config.channel ) ) = max_duty; + + return HAL_LL_TIM_SUCCESS; +} + +hal_ll_err_t hal_ll_tim_start( handle_t *handle ) { + + uint32_t tmp_channel; + volatile uint32_t tmp, + *tmpPtr; + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + tmp_channel = hal_ll_tim_hw_specifics_map_local->config.channel; + + // Capture/Compare 1 output enable. + tmp = hal_ll_hw_reg->ccer; + + // If complementary output channel is used. + if ( HAL_LL_TIM_IS_COMPLEMENTARY ) { + // Capture/Compare complementary output enable + tmp |= ( 1UL << ( hal_ll_tim_channel_static( tmp_channel ) * 4 + 2 ) ); + // Capture/Compare complementary output polarity(ACTIVE HIGH). + tmp &= ~( 1UL << ( hal_ll_tim_channel_static( tmp_channel ) * 4 + 3 ) ); + } else { + // Capture/Compare output polarity. + tmp |= ( 1UL << ( hal_ll_tim_channel_static( tmp_channel ) * 4 ) ); + // Capture/Compare output polarity(ACTIVE HIGH). + tmp &= ~( 1UL << ( hal_ll_tim_channel_static( tmp_channel ) * 4 + 1 ) ); + } + + hal_ll_hw_reg->ccer = tmp; + + #if defined(TIM_MODULE_1) || defined(TIM_MODULE_8) || defined(TIM_MODULE_20) + // Main output enabled. + set_reg_bit( &hal_ll_hw_reg->bdtr, HAL_LL_TIM_BDTR_MOE_BIT ); + #endif + + tmpPtr = &hal_ll_hw_reg->ccmr1; + + if( hal_ll_tim_channel_static( tmp_channel ) > 1 ) { + tmpPtr = &hal_ll_hw_reg->ccmr2; + } + + if( ( hal_ll_tim_channel_static( tmp_channel ) / 2 ) * 2 != + hal_ll_tim_channel_static( tmp_channel ) ) { + // Clear CCxS, OCxM[0]. + *tmpPtr &= ~( HAL_LL_TIM_CCMR_CC2S_BIT0 | + HAL_LL_TIM_CCMR_CC2S_BIT1 | + HAL_LL_TIM_CCMR_OC2PE | + HAL_LL_TIM_CCMR_OC2M_BIT0 ); + // Set OCxM[2, 1] + *tmpPtr |= HAL_LL_TIM_CCMR_OC2M_BIT1 | HAL_LL_TIM_CCMR_OC2M_BIT2; + } else { + // Clear CCxS, OCxM[0]. + *tmpPtr &= ~( HAL_LL_TIM_CCMR_CC3S_BIT0 | + HAL_LL_TIM_CCMR_CC3S_BIT1 | + HAL_LL_TIM_CCMR_OC3PE | + HAL_LL_TIM_CCMR_OC3M_BIT0 ); + + // Set OCxM[2, 1]. + *tmpPtr |= HAL_LL_TIM_CCMR_OC3M_BIT1 | HAL_LL_TIM_CCMR_OC3M_BIT2; + } + + // Enable counter. + set_reg_bit( &hal_ll_hw_reg->cr1, HAL_LL_TIM_ENABLE_COUNTER_BIT ); + + return HAL_LL_TIM_SUCCESS; +} + +hal_ll_err_t hal_ll_tim_stop( handle_t *handle ) { + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + // If complementary output channel is used. + if ( HAL_LL_TIM_IS_COMPLEMENTARY ) { + hal_ll_hw_reg->ccer &= 1UL << hal_ll_tim_hw_specifics_map_local->config.channel * 4 + 2; + } else { + hal_ll_hw_reg->ccer &= 1UL << hal_ll_tim_hw_specifics_map_local->config.channel * 4; + } + + return HAL_LL_TIM_SUCCESS; +} + +void hal_ll_tim_close( handle_t *handle ) { + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_tim_get_module_state_address); + + if( low_level_handle->hal_ll_tim_handle != NULL ) { + low_level_handle->hal_ll_tim_handle = NULL; + low_level_handle->hal_drv_tim_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_tim_hw_specifics_map_local->max_period = 0; + hal_ll_tim_hw_specifics_map_local->freq_hz = 0; + + _hal_ll_tim_set_clock( hal_ll_tim_hw_specifics_map_local->base, true ); + _hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_map_local, false ); + _hal_ll_tim_set_clock( hal_ll_tim_hw_specifics_map_local->base, false ); + + hal_ll_tim_hw_specifics_map_local->config.pin = HAL_LL_PIN_NC; + hal_ll_tim_hw_specifics_map_local->config.channel = HAL_LL_PIN_NC; + hal_ll_tim_hw_specifics_map_local->config.af = NULL; + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static inline void _hal_ll_tim1_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APBENR2, HAL_LL_TIM_ENABLE_1 ); + } else { + clear_reg_bit( _RCC_APBENR2, HAL_LL_TIM_ENABLE_1 ); + } +} + +static inline void _hal_ll_tim2_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APBENR1, HAL_LL_TIM_ENABLE_2 ); + } else { + clear_reg_bit( _RCC_APBENR1, HAL_LL_TIM_ENABLE_2 ); + } +} + +static inline void _hal_ll_tim3_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APBENR1, HAL_LL_TIM_ENABLE_3 ); + } else { + clear_reg_bit( _RCC_APBENR1, HAL_LL_TIM_ENABLE_3 ); + } +} + +static inline void _hal_ll_tim4_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APBENR1, HAL_LL_TIM_ENABLE_4 ); + } else { + clear_reg_bit( _RCC_APBENR1, HAL_LL_TIM_ENABLE_4 ); + } +} + +static inline void _hal_ll_tim14_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APBENR2, HAL_LL_TIM_ENABLE_14 ); + } else { + clear_reg_bit( _RCC_APBENR2, HAL_LL_TIM_ENABLE_14 ); + } +} + +static inline void _hal_ll_tim15_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APBENR2, HAL_LL_TIM_ENABLE_15 ); + } else { + clear_reg_bit( _RCC_APBENR2, HAL_LL_TIM_ENABLE_15 ); + } +} + +static inline void _hal_ll_tim16_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APBENR2, HAL_LL_TIM_ENABLE_16 ); + } else { + clear_reg_bit( _RCC_APBENR2, HAL_LL_TIM_ENABLE_16 ); + } +} + +static inline void _hal_ll_tim17_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APBENR2, HAL_LL_TIM_ENABLE_17 ); + } else { + clear_reg_bit( _RCC_APBENR2, HAL_LL_TIM_ENABLE_17 ); + } +} + +static hal_ll_pin_name_t _hal_ll_tim_check_pin( hal_ll_pin_name_t pin, uint8_t *index, hal_ll_tim_handle_register_t *handle_map ) { + + hal_ll_pin_name_t pin_num; + uint8_t index_counter = 0; + uint8_t hal_ll_module_id = 0; + uint16_t map_size = ( sizeof( _tim_map ) / sizeof( hal_ll_tim_pin_map_t ) ); + + if ( HAL_LL_PIN_NC == pin ) { + return HAL_LL_PIN_NC; + } + + // Check if the selected pin is valid. + for ( pin_num = 0; pin_num < map_size; pin_num++ ) { + if ( _tim_map[ pin_num ].pin == pin ) { + // Get module number + hal_ll_module_id = _tim_map[ pin_num ].module_index; + if ( NULL == handle_map[hal_ll_module_id].hal_drv_tim_handle ) { + *index = pin_num; + return hal_ll_module_id; + } else if ( TIM_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + // By default return last error msg. + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static hal_ll_tim_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + + uint8_t hal_ll_module_count = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_tim_handle_register_t ) ); + static uint8_t hal_ll_module_error = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_tim_handle_register_t ) ); + + while( hal_ll_module_count-- ) { + if ( hal_ll_tim_get_base_from_hal_handle == hal_ll_tim_hw_specifics_map [ hal_ll_module_count ].base) { + return &hal_ll_tim_hw_specifics_map[ hal_ll_module_count ]; + } + } + + return &hal_ll_tim_hw_specifics_map[ hal_ll_module_error ]; +} + +static void _hal_ll_tim_set_clock( hal_ll_base_addr_t base, bool hal_ll_state ) { + + switch ( ( uint32_t )base ) { // 32-bit base address. + #ifdef TIM_MODULE_1 + case ( HAL_LL_TIM1_BASE_ADDR ): + _hal_ll_tim1_set_clock( hal_ll_state ); + break; + #endif + #ifdef TIM_MODULE_2 + case ( HAL_LL_TIM2_BASE_ADDR ): + _hal_ll_tim2_set_clock( hal_ll_state ); + break; + #endif + #ifdef TIM_MODULE_3 + case ( HAL_LL_TIM3_BASE_ADDR ): + _hal_ll_tim3_set_clock( hal_ll_state ); + break; + #endif + #ifdef TIM_MODULE_4 + case ( HAL_LL_TIM4_BASE_ADDR ): + _hal_ll_tim4_set_clock( hal_ll_state ); + break; + #endif + #ifdef TIM_MODULE_14 + case ( HAL_LL_TIM14_BASE_ADDR ): + _hal_ll_tim14_set_clock( hal_ll_state ); + break; + #endif + #ifdef TIM_MODULE_15 + case ( HAL_LL_TIM15_BASE_ADDR ): + _hal_ll_tim15_set_clock( hal_ll_state ); + break; + #endif + #ifdef TIM_MODULE_16 + case ( HAL_LL_TIM16_BASE_ADDR ): + _hal_ll_tim16_set_clock( hal_ll_state ); + break; + #endif + #ifdef TIM_MODULE_17 + case ( HAL_LL_TIM17_BASE_ADDR ): + _hal_ll_tim17_set_clock( hal_ll_state ); + break; + #endif + } +} + +static uint32_t _hal_ll_tim_clock_source( uint8_t selector ) { + + rcc_clocks_t rcc_clocks; + + RCC_GetClocksFrequency( &rcc_clocks ); + + if( selector == HAL_LL_APB1_TIMER_CLOCK ) { + if( rcc_clocks.hclk/rcc_clocks.pclk > 1 ) { + return rcc_clocks.pclk * 2; + } else { + return rcc_clocks.pclk; + } + } + + return 0; +} + +static uint32_t _hal_ll_tim_get_clock_speed( hal_ll_base_addr_t base ) { + + switch ( ( uint32_t )base ) { + #ifdef TIM_MODULE_1 + case ( HAL_LL_TIM1_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM1_BUS ); + break; + #endif + #ifdef TIM_MODULE_2 + case ( HAL_LL_TIM2_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM2_BUS ); + break; + #endif + #ifdef TIM_MODULE_3 + case ( HAL_LL_TIM3_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM3_BUS ); + break; + #endif + #ifdef TIM_MODULE_4 + case ( HAL_LL_TIM4_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM4_BUS ); + break; + #endif + #ifdef TIM_MODULE_14 + case ( HAL_LL_TIM14_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM14_BUS ); + break; + #endif + #ifdef TIM_MODULE_15 + case ( HAL_LL_TIM15_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM15_BUS ); + break; + #endif + #ifdef TIM_MODULE_16 + case ( HAL_LL_TIM16_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM16_BUS ); + break; + #endif + #ifdef TIM_MODULE_17 + case ( HAL_LL_TIM17_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM17_BUS ); + break; + #endif + } + return 0; +} + +static void _hal_ll_tim_map_pin( uint8_t module_index, uint8_t index ) { + + uint8_t tmp_channel; + + // Map new pin + hal_ll_tim_hw_specifics_map[ module_index ].config.pin = _tim_map[ index ].pin; + tmp_channel = _tim_map[ index ].channel; + hal_ll_tim_hw_specifics_map[ module_index ].config.af = _tim_map[ index ].af; + + if ( tmp_channel >= HAL_LL_TIM_CHANNEL_1N ) { + HAL_LL_TIM_IS_COMPLEMENTARY = true; + hal_ll_tim_hw_specifics_map[ module_index ].config.channel = tmp_channel - 4; + } else { + HAL_LL_TIM_IS_COMPLEMENTARY = false; + hal_ll_tim_hw_specifics_map[ module_index ].config.channel = tmp_channel; + } +} + +static void _hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_map_t *map, bool hal_ll_state ) { + + module_struct module; + uint32_t tim_config = 0; + + if( map->config.pin != HAL_LL_PIN_NC ) { + if( hal_ll_state == false ) { + tim_config = GPIO_CFG_MODE_ALT_FUNCTION | + GPIO_CFG_SPEED_LOW | + GPIO_CFG_OTYPE_PP; + } else { + tim_config = GPIO_CFG_MODE_ALT_FUNCTION | + GPIO_CFG_SPEED_HIGH | + GPIO_CFG_OTYPE_PP; + } + + module.pins[ 0 ] = VALUE( map->config.pin, map->config.af ); + module.pins[ 1 ] = GPIO_MODULE_STRUCT_END; + + module.configs[ 0 ] = tim_config; + module.configs[ 1 ] = GPIO_MODULE_STRUCT_END; + + hal_ll_gpio_module_struct_init( &module, hal_ll_state ); + } +} + +static void _hal_ll_tim_hw_init( hal_ll_tim_hw_specifics_map_t *map ) { + + uint32_t ck_psc; + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( map->base ); + + // Counter used as upcounter. + clear_reg_bit( &hal_ll_hw_reg->cr1, HAL_LL_TIM_CR1_DIR_BIT ); + + // Get clock speed. + ck_psc = _hal_ll_tim_get_clock_speed( map->base ) / map->freq_hz; + + // This should not be the case. ck_psc should not be greater than 65535, which is max value. + if( ck_psc > UINT16_MAX ) { + // In case of duty period beeing greater than 65535 set ck_psc to max value. + ck_psc = UINT16_MAX - 1; // Because of ( ck_psc / UINT16_MAX + 1 ) ), has to be minus 1. + }else if ( ck_psc < 1 ) { + ck_psc = 1; + } + + // Write prescale value. + hal_ll_hw_reg->psc = ( uint16_t )( ck_psc / UINT16_MAX ); + + // Write max count value. + hal_ll_hw_reg->arr = ( uint16_t )( ck_psc/( ck_psc / UINT16_MAX + 1 ) ); + + // Write max period to global array. + map->max_period = ( uint16_t )ck_psc; +} + +static void _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_t *map ) { + + _hal_ll_tim_set_clock( map->base, true ); + + _hal_ll_tim_alternate_functions_set_state( map, true ); + + _hal_ll_tim_hw_init( map ); +} +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_81/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_81/CMakeLists.cmake new file mode 100644 index 000000000..bd7538754 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_81/CMakeLists.cmake @@ -0,0 +1,9 @@ +if(${MCU_NAME} MATCHES "^STM32G0C1CC$|^STM32G0C1KC$|^STM32G0C1MC$|^STM32G0C1RC$|^STM32G0C1VC$|^STM32G0C1CE$|^STM32G0C1KE$|^STM32G0C1ME$|^STM32G0C1NE$|^STM32G0C1RE$|^STM32G0C1VE$") + set(tim_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_tim.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_81") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_81") + list(APPEND hal_ll_def_list "STM32G0xx") + list(APPEND hal_ll_def_list "STM32G0Cxx") + list(APPEND hal_ll_def_list "STM32G0C1xx") + set(tim_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/tim/hal_ll_tim_pin_map/implementations/doc_ds_81") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_81/hal_ll_tim.c b/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_81/hal_ll_tim.c new file mode 100644 index 000000000..d8a058490 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_81/hal_ll_tim.c @@ -0,0 +1,935 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_tim.c + * @brief TIM HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_gpio.h" +#include "hal_ll_rcc.h" +#include "hal_ll_tim.h" +#include "hal_ll_tim_pin_map.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_tim_handle_register_t hal_ll_module_state[ TIM_MODULE_COUNT ]; + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< CR1 constants. */ +#define HAL_LL_TIM_ENABLE_COUNTER_BIT 0 +#define HAL_LL_TIM_BDTR_MOE_BIT 15 +#define HAL_LL_TIM_BDTR_MOE 0x8000 + +#define HAL_LL_TIM_CCMR_CC2S_BIT0 0x100u +#define HAL_LL_TIM_CCMR_CC2S_BIT1 0x200u +#define HAL_LL_TIM_CCMR_OC2PE 0x800u +#define HAL_LL_TIM_CCMR_OC2M_BIT0 0x1000u +#define HAL_LL_TIM_CCMR_OC2M_BIT1 0x2000u +#define HAL_LL_TIM_CCMR_OC2M_BIT2 0x4000u + +#define HAL_LL_TIM_CCMR_CC3S_BIT0 0x1u +#define HAL_LL_TIM_CCMR_CC3S_BIT1 0x2u +#define HAL_LL_TIM_CCMR_OC3PE 0x8u +#define HAL_LL_TIM_CCMR_OC3M_BIT0 0x10u +#define HAL_LL_TIM_CCMR_OC3M_BIT1 0x20u +#define HAL_LL_TIM_CCMR_OC3M_BIT2 0x40u + +#define HAL_LL_TIM_CR1_DIR 0x10 +#define HAL_LL_TIM_CR1_DIR_BIT 4 + +#define HAL_LL_TIM_ENABLE_1 11 + +#define HAL_LL_TIM_ENABLE_2 0 + +#define HAL_LL_TIM_ENABLE_3 1 + +#define HAL_LL_TIM_ENABLE_4 2 + +#define HAL_LL_TIM_ENABLE_14 15 + +#define HAL_LL_TIM_ENABLE_15 16 + +#define HAL_LL_TIM_ENABLE_16 17 + +#define HAL_LL_TIM_ENABLE_17 18 + + +#define HAL_LL_APB1_TIMER_CLOCK 1 + + + +#define hal_ll_tim_channel_static( _chn ) ( _chn-1 ) + +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_tim_get_base_struct(_handle) ((hal_ll_tim_base_handle_t *)_handle) + +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_tim_get_module_state_address ((hal_ll_tim_handle_register_t *)*handle) + +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_tim_get_handle ( hal_ll_tim_handle_register_t * )hal_ll_tim_get_module_state_address->hal_ll_tim_handle + +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_tim_get_base_from_hal_handle ((hal_ll_tim_hw_specifics_map_t *)((hal_ll_tim_handle_register_t *)\ + (((hal_ll_tim_handle_register_t *)(handle))->hal_ll_tim_handle))->hal_ll_tim_handle)->base + +// -------------------------------------------------------------- PRIVATE TYPES +/*!< @brief TIM register structure. */ +typedef struct +{ + uint32_t cr1; /* Address offset 0x00 */ + uint32_t cr2; /* Address offset 0x04 */ + uint32_t smcr; /* Address offset 0x08 */ + uint32_t dier; /* Address offset 0x0C */ + uint32_t sr; /* Address offset 0x10 */ + uint32_t egr; /* Address offset 0x14 */ + uint32_t ccmr1; /* Address offset 0x18 */ + uint32_t ccmr2; /* Address offset 0x1C */ + uint32_t ccer; /* Address offset 0x20 */ + uint32_t cnt; /* Address offset 0x24 */ + uint32_t psc; /* Address offset 0x28 */ + uint32_t arr; /* Address offset 0x2C */ + uint32_t rcr; /* Address offset 0x30 */ + uint32_t ccr1; /* Address offset 0x34 */ + uint32_t ccr2; /* Address offset 0x38 */ + uint32_t ccr3; /* Address offset 0x3C */ + uint32_t ccr4; /* Address offset 0x40 */ + uint32_t bdtr; /* Address offset 0x44 */ + uint32_t dcr; /* Address offset 0x48 */ + uint32_t dmar; /* Address offset 0x4C */ + uint32_t tim2_5_or; /* Address offset 0x50 */ +} hal_ll_tim_base_handle_t; + +/*!< @brief TIM pin structure */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_channel_t channel; + uint32_t af; +} hal_ll_tim_t; + +/*!< @brief TIM hw specific structure */ +typedef struct +{ + hal_ll_base_addr_t base; + hal_ll_tim_t config; + uint16_t max_period; + uint32_t freq_hz; + hal_ll_pin_name_t module_index; +} hal_ll_tim_hw_specifics_map_t; + +/*!< @brief TIM hw specific error values */ +typedef enum +{ + HAL_LL_TIM_SUCCESS = 0, + HAL_LL_TIM_MODULE_ERROR, + HAL_LL_TIM_WRONG_PIN, + + HAL_LL_TIM_ERROR = (-1) +} hal_ll_tim_err_t; + +// ------------------------------------------------------------------ VARIABLES +/*!< @brief TIM specific info */ +static hal_ll_tim_hw_specifics_map_t hal_ll_tim_hw_specifics_map[] = +{ + #ifdef TIM_MODULE_1 + {HAL_LL_TIM1_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_1 - 1}, + #endif + + #ifdef TIM_MODULE_2 + {HAL_LL_TIM2_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_2 - 1}, + #endif + + #ifdef TIM_MODULE_3 + {HAL_LL_TIM3_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_3 - 1}, + #endif + + #ifdef TIM_MODULE_4 + {HAL_LL_TIM4_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_4 - 1}, + #endif + + #ifdef TIM_MODULE_14 + {HAL_LL_TIM14_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_14 - 1}, + #endif + + #ifdef TIM_MODULE_15 + {HAL_LL_TIM15_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_15 - 1}, + #endif + + #ifdef TIM_MODULE_16 + {HAL_LL_TIM16_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_16 - 1}, + #endif + + #ifdef TIM_MODULE_17 + {HAL_LL_TIM17_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_17 - 1}, + #endif + + + {HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, HAL_LL_PIN_NC} +}; + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_tim_handle_register_t *low_level_handle; +static volatile hal_ll_tim_hw_specifics_map_t *hal_ll_tim_hw_specifics_map_local; + +static bool HAL_LL_TIM_IS_COMPLEMENTARY; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Enable TIM module 1 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim1_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 2 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim2_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 3 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim3_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 4 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim4_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 14 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim14_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 15 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim15_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 16 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim16_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 17 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim17_set_clock( bool hal_ll_state ); + + +/** + * @brief Enable TIM module gate clock. + * @param base - TIM module base + * address + * @return None + */ +static void _hal_ll_tim_set_clock( hal_ll_base_addr_t base, bool hal_ll_state ); + +/** + * @brief Select TIM clock source + * @param selector - clock source selector + * @return uint32_t - clock source + */ +static uint32_t _hal_ll_tim_clock_source( uint8_t selector ); + +/** + * @brief Based on selected TIM, + * return clock speed. + * @param base - TIM module base + * address + * @return uint32_t clock source. + */ +static uint32_t _hal_ll_tim_get_clock_speed( hal_ll_base_addr_t base ); + +/** + * @brief Initialize TIM module on hardware level. + * + * Initializes TIM module on hardware level, based on beforehand + * set configuration and module handler. + * + * @param map - Object specific context handler. + * @return none + * + */ +static void _hal_ll_tim_hw_init( hal_ll_tim_hw_specifics_map_t *map ); + +/** + * @brief Full TIM module initialization procedure. + * + * Initializes TIM module on hardware level, based on beforehand + * set configuration and module handler. Sets adequate pin alternate functions. + * Initializes module clock. + * + * @param map - Object specific context handler. + * @return none + * + */ +static void _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_t *map ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_tim_hw_specifics_map array index. + * + * @param handle - Object specific context handler. + * @return hal_ll_tim_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_tim_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Check if pin is adequate. + * + * Checks tim pin the user has passed with pre-defined + * pin in tim map. + * + * @param pin - TIM pre-defined pin name. + * @return hal_ll_pin_name_t Module index based on pin. + * + * Returns pre-defined module index from pin maps, if pin + * is adequate. + */ +static hal_ll_pin_name_t _hal_ll_tim_check_pin( hal_ll_pin_name_t pin, uint8_t *index, hal_ll_tim_handle_register_t *handle_map ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * TIM pin. + * + * @param[in] module_index TIM HW module index -- 0,1,2... + * @param[in] *index_list Array with TIM map index values + * + * @return None + */ +static void _hal_ll_tim_map_pin( uint8_t module_index, uint8_t index ); + +/** + * @brief Sets TIM pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if TIM is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param map - Object specific context handler. + * + * @param hal_ll_state - Init/De-init + * @return none + * + */ +static void _hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_map_t *map, bool hal_ll_state ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_tim_register_handle( hal_ll_pin_name_t pin, hal_ll_tim_handle_register_t *handle_map, + uint8_t *hal_module_id ) { + + uint8_t index; + uint16_t pin_check_result; + + if ( ( pin_check_result = _hal_ll_tim_check_pin( pin, &index, handle_map ) ) == HAL_LL_PIN_NC ) { + return HAL_LL_TIM_WRONG_PIN; + } + + if ( hal_ll_tim_hw_specifics_map[ pin_check_result ].config.pin != pin ){ + // Clear previous module alternate functions + _hal_ll_tim_alternate_functions_set_state( &hal_ll_tim_hw_specifics_map[ pin_check_result ], false ); + + _hal_ll_tim_map_pin( pin_check_result, index ); + + _hal_ll_tim_alternate_functions_set_state( &hal_ll_tim_hw_specifics_map[ pin_check_result ], true ); + + handle_map[ pin_check_result ].init_ll_state = false; + + hal_ll_module_state[ pin_check_result ].init_ll_state = false; + + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle = ( handle_t * )&hal_ll_tim_hw_specifics_map[ pin_check_result ].base; + + handle_map[ pin_check_result ].hal_ll_tim_handle = ( handle_t *)&hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle; + + return HAL_LL_TIM_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_tim( handle_t *handle ) { + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + hal_ll_tim_handle_register_t *hal_handle = (hal_ll_tim_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_tim_hw_specifics_map_local->module_index; + + _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_local ); + + hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle = (handle_t *)&hal_ll_tim_hw_specifics_map[ pin_check_result ].base; + hal_ll_module_state[ pin_check_result ].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_TIM_SUCCESS; +} + +uint32_t hal_ll_tim_set_freq( handle_t *handle, uint32_t freq_hz ) { + + uint32_t tmp_channel; + uint32_t ck_psc; + uint32_t local_base_addr; + uint32_t local_freq; + uint32_t tmp_freq; + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + if( hal_ll_tim_hw_specifics_map_local->base == HAL_LL_MODULE_ERROR ) { + return HAL_LL_TIM_MODULE_ERROR; + } + + low_level_handle->init_ll_state = false; + + tmp_channel = hal_ll_tim_hw_specifics_map_local->config.channel; + + // If complementary output channel is used. + if ( HAL_LL_TIM_IS_COMPLEMENTARY ) { + // Stop capture/compare. + hal_ll_hw_reg->ccer &= 1UL << tmp_channel * 4 + 2; + } else { + // Stop capture/compare. + hal_ll_hw_reg->ccer &= 1UL << tmp_channel * 4; + } + + // Set TIM duty to 0. + *( &hal_ll_hw_reg->ccr1 + hal_ll_tim_channel_static( tmp_channel ) ) = 0; + + hal_ll_tim_hw_specifics_map_local->freq_hz = freq_hz; + + local_freq = hal_ll_tim_hw_specifics_map_local->freq_hz; + local_base_addr = hal_ll_tim_hw_specifics_map_local->base; + + ck_psc = _hal_ll_tim_get_clock_speed( local_base_addr ) / local_freq; + + if ( ck_psc > UINT16_MAX ) { + tmp_freq = _hal_ll_tim_get_clock_speed( local_base_addr ) / UINT16_MAX; + hal_ll_tim_hw_specifics_map_local->freq_hz = tmp_freq; + } else { + tmp_freq = freq_hz; + hal_ll_tim_hw_specifics_map_local->freq_hz = freq_hz; + } + + _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_local ); + + low_level_handle->init_ll_state = true; + + return tmp_freq; +} + +hal_ll_err_t hal_ll_tim_set_duty( handle_t *handle, float duty_ratio ) { + + float tmp_duty; + uint32_t max_duty = 0; + uint16_t max_period; + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + if ( low_level_handle->init_ll_state == false ) { + hal_ll_tim_start( handle ); + low_level_handle->init_ll_state = true; + } + + tmp_duty = duty_ratio * 100; + max_period = hal_ll_tim_hw_specifics_map_local->max_period; + + max_duty = ( ( float )max_period / 100 ) * tmp_duty; + + *( &hal_ll_hw_reg->ccr1 + hal_ll_tim_channel_static( hal_ll_tim_hw_specifics_map_local->config.channel ) ) = max_duty; + + return HAL_LL_TIM_SUCCESS; +} + +hal_ll_err_t hal_ll_tim_start( handle_t *handle ) { + + uint32_t tmp_channel; + volatile uint32_t tmp, + *tmpPtr; + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + tmp_channel = hal_ll_tim_hw_specifics_map_local->config.channel; + + // Capture/Compare 1 output enable. + tmp = hal_ll_hw_reg->ccer; + + // If complementary output channel is used. + if ( HAL_LL_TIM_IS_COMPLEMENTARY ) { + // Capture/Compare complementary output enable + tmp |= ( 1UL << ( hal_ll_tim_channel_static( tmp_channel ) * 4 + 2 ) ); + // Capture/Compare complementary output polarity(ACTIVE HIGH). + tmp &= ~( 1UL << ( hal_ll_tim_channel_static( tmp_channel ) * 4 + 3 ) ); + } else { + // Capture/Compare output polarity. + tmp |= ( 1UL << ( hal_ll_tim_channel_static( tmp_channel ) * 4 ) ); + // Capture/Compare output polarity(ACTIVE HIGH). + tmp &= ~( 1UL << ( hal_ll_tim_channel_static( tmp_channel ) * 4 + 1 ) ); + } + + hal_ll_hw_reg->ccer = tmp; + + #if defined(TIM_MODULE_1) || defined(TIM_MODULE_8) || defined(TIM_MODULE_20) + // Main output enabled. + set_reg_bit( &hal_ll_hw_reg->bdtr, HAL_LL_TIM_BDTR_MOE_BIT ); + #endif + + tmpPtr = &hal_ll_hw_reg->ccmr1; + + if( hal_ll_tim_channel_static( tmp_channel ) > 1 ) { + tmpPtr = &hal_ll_hw_reg->ccmr2; + } + + if( ( hal_ll_tim_channel_static( tmp_channel ) / 2 ) * 2 != + hal_ll_tim_channel_static( tmp_channel ) ) { + // Clear CCxS, OCxM[0]. + *tmpPtr &= ~( HAL_LL_TIM_CCMR_CC2S_BIT0 | + HAL_LL_TIM_CCMR_CC2S_BIT1 | + HAL_LL_TIM_CCMR_OC2PE | + HAL_LL_TIM_CCMR_OC2M_BIT0 ); + // Set OCxM[2, 1] + *tmpPtr |= HAL_LL_TIM_CCMR_OC2M_BIT1 | HAL_LL_TIM_CCMR_OC2M_BIT2; + } else { + // Clear CCxS, OCxM[0]. + *tmpPtr &= ~( HAL_LL_TIM_CCMR_CC3S_BIT0 | + HAL_LL_TIM_CCMR_CC3S_BIT1 | + HAL_LL_TIM_CCMR_OC3PE | + HAL_LL_TIM_CCMR_OC3M_BIT0 ); + + // Set OCxM[2, 1]. + *tmpPtr |= HAL_LL_TIM_CCMR_OC3M_BIT1 | HAL_LL_TIM_CCMR_OC3M_BIT2; + } + + // Enable counter. + set_reg_bit( &hal_ll_hw_reg->cr1, HAL_LL_TIM_ENABLE_COUNTER_BIT ); + + return HAL_LL_TIM_SUCCESS; +} + +hal_ll_err_t hal_ll_tim_stop( handle_t *handle ) { + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + // If complementary output channel is used. + if ( HAL_LL_TIM_IS_COMPLEMENTARY ) { + hal_ll_hw_reg->ccer &= 1UL << hal_ll_tim_hw_specifics_map_local->config.channel * 4 + 2; + } else { + hal_ll_hw_reg->ccer &= 1UL << hal_ll_tim_hw_specifics_map_local->config.channel * 4; + } + + return HAL_LL_TIM_SUCCESS; +} + +void hal_ll_tim_close( handle_t *handle ) { + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_tim_get_module_state_address); + + if( low_level_handle->hal_ll_tim_handle != NULL ) { + low_level_handle->hal_ll_tim_handle = NULL; + low_level_handle->hal_drv_tim_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_tim_hw_specifics_map_local->max_period = 0; + hal_ll_tim_hw_specifics_map_local->freq_hz = 0; + + _hal_ll_tim_set_clock( hal_ll_tim_hw_specifics_map_local->base, true ); + _hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_map_local, false ); + _hal_ll_tim_set_clock( hal_ll_tim_hw_specifics_map_local->base, false ); + + hal_ll_tim_hw_specifics_map_local->config.pin = HAL_LL_PIN_NC; + hal_ll_tim_hw_specifics_map_local->config.channel = HAL_LL_PIN_NC; + hal_ll_tim_hw_specifics_map_local->config.af = NULL; + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static inline void _hal_ll_tim1_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APBENR2, HAL_LL_TIM_ENABLE_1 ); + } else { + clear_reg_bit( _RCC_APBENR2, HAL_LL_TIM_ENABLE_1 ); + } +} + +static inline void _hal_ll_tim2_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APBENR1, HAL_LL_TIM_ENABLE_2 ); + } else { + clear_reg_bit( _RCC_APBENR1, HAL_LL_TIM_ENABLE_2 ); + } +} + +static inline void _hal_ll_tim3_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APBENR1, HAL_LL_TIM_ENABLE_3 ); + } else { + clear_reg_bit( _RCC_APBENR1, HAL_LL_TIM_ENABLE_3 ); + } +} + +static inline void _hal_ll_tim4_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APBENR1, HAL_LL_TIM_ENABLE_4 ); + } else { + clear_reg_bit( _RCC_APBENR1, HAL_LL_TIM_ENABLE_4 ); + } +} + +static inline void _hal_ll_tim14_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APBENR2, HAL_LL_TIM_ENABLE_14 ); + } else { + clear_reg_bit( _RCC_APBENR2, HAL_LL_TIM_ENABLE_14 ); + } +} + +static inline void _hal_ll_tim15_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APBENR2, HAL_LL_TIM_ENABLE_15 ); + } else { + clear_reg_bit( _RCC_APBENR2, HAL_LL_TIM_ENABLE_15 ); + } +} + +static inline void _hal_ll_tim16_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APBENR2, HAL_LL_TIM_ENABLE_16 ); + } else { + clear_reg_bit( _RCC_APBENR2, HAL_LL_TIM_ENABLE_16 ); + } +} + +static inline void _hal_ll_tim17_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APBENR2, HAL_LL_TIM_ENABLE_17 ); + } else { + clear_reg_bit( _RCC_APBENR2, HAL_LL_TIM_ENABLE_17 ); + } +} + + +static hal_ll_pin_name_t _hal_ll_tim_check_pin( hal_ll_pin_name_t pin, uint8_t *index, hal_ll_tim_handle_register_t *handle_map ) { + + hal_ll_pin_name_t pin_num; + uint8_t index_counter = 0; + uint8_t hal_ll_module_id = 0; + uint16_t map_size = ( sizeof( _tim_map ) / sizeof( hal_ll_tim_pin_map_t ) ); + + if ( HAL_LL_PIN_NC == pin ) { + return HAL_LL_PIN_NC; + } + + // Check if the selected pin is valid. + for ( pin_num = 0; pin_num < map_size; pin_num++ ) { + if ( _tim_map[ pin_num ].pin == pin ) { + // Get module number + hal_ll_module_id = _tim_map[ pin_num ].module_index; + if ( NULL == handle_map[hal_ll_module_id].hal_drv_tim_handle ) { + *index = pin_num; + return hal_ll_module_id; + } else if ( TIM_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + // By default return last error msg. + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static hal_ll_tim_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + + uint8_t hal_ll_module_count = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_tim_handle_register_t ) ); + static uint8_t hal_ll_module_error = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_tim_handle_register_t ) ); + + while( hal_ll_module_count-- ) { + if ( hal_ll_tim_get_base_from_hal_handle == hal_ll_tim_hw_specifics_map [ hal_ll_module_count ].base) { + return &hal_ll_tim_hw_specifics_map[ hal_ll_module_count ]; + } + } + + return &hal_ll_tim_hw_specifics_map[ hal_ll_module_error ]; +} + +static void _hal_ll_tim_set_clock( hal_ll_base_addr_t base, bool hal_ll_state ) { + + switch ( ( uint32_t )base ) { // 32-bit base address. + #ifdef TIM_MODULE_1 + case ( HAL_LL_TIM1_BASE_ADDR ): + _hal_ll_tim1_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_2 + case ( HAL_LL_TIM2_BASE_ADDR ): + _hal_ll_tim2_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_3 + case ( HAL_LL_TIM3_BASE_ADDR ): + _hal_ll_tim3_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_4 + case ( HAL_LL_TIM4_BASE_ADDR ): + _hal_ll_tim4_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_14 + case ( HAL_LL_TIM14_BASE_ADDR ): + _hal_ll_tim14_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_15 + case ( HAL_LL_TIM15_BASE_ADDR ): + _hal_ll_tim15_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_16 + case ( HAL_LL_TIM16_BASE_ADDR ): + _hal_ll_tim16_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_17 + case ( HAL_LL_TIM17_BASE_ADDR ): + _hal_ll_tim17_set_clock( hal_ll_state ); + break; + #endif + + } +} + +static uint32_t _hal_ll_tim_clock_source( uint8_t selector ) { + + rcc_clocks_t rcc_clocks; + + RCC_GetClocksFrequency( &rcc_clocks ); + + if( selector == HAL_LL_APB1_TIMER_CLOCK ) { + if( rcc_clocks.hclk/rcc_clocks.pclk > 1 ) { + return rcc_clocks.pclk * 2; + } else { + return rcc_clocks.pclk; + } + } + + return 0; +} + +static uint32_t _hal_ll_tim_get_clock_speed( hal_ll_base_addr_t base ) { + + switch ( ( uint32_t )base ) { + #ifdef TIM_MODULE_1 + case ( HAL_LL_TIM1_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM1_BUS ); + break; + #endif + + #ifdef TIM_MODULE_2 + case ( HAL_LL_TIM2_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM2_BUS ); + break; + #endif + + #ifdef TIM_MODULE_3 + case ( HAL_LL_TIM3_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM3_BUS ); + break; + #endif + + #ifdef TIM_MODULE_4 + case ( HAL_LL_TIM4_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM4_BUS ); + break; + #endif + + #ifdef TIM_MODULE_14 + case ( HAL_LL_TIM14_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM14_BUS ); + break; + #endif + + #ifdef TIM_MODULE_15 + case ( HAL_LL_TIM15_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM15_BUS ); + break; + #endif + + #ifdef TIM_MODULE_16 + case ( HAL_LL_TIM16_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM16_BUS ); + break; + #endif + + #ifdef TIM_MODULE_17 + case ( HAL_LL_TIM17_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM17_BUS ); + break; + #endif + + } + return 0; +} + +static void _hal_ll_tim_map_pin( uint8_t module_index, uint8_t index ) { + + uint8_t tmp_channel; + + // Map new pin + hal_ll_tim_hw_specifics_map[ module_index ].config.pin = _tim_map[ index ].pin; + tmp_channel = _tim_map[ index ].channel; + hal_ll_tim_hw_specifics_map[ module_index ].config.af = _tim_map[ index ].af; + + if ( tmp_channel >= HAL_LL_TIM_CHANNEL_1N ) { + HAL_LL_TIM_IS_COMPLEMENTARY = true; + hal_ll_tim_hw_specifics_map[ module_index ].config.channel = tmp_channel - 4; + } else { + HAL_LL_TIM_IS_COMPLEMENTARY = false; + hal_ll_tim_hw_specifics_map[ module_index ].config.channel = tmp_channel; + } +} + +static void _hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_map_t *map, bool hal_ll_state ) { + + module_struct module; + uint32_t tim_config = 0; + + if( map->config.pin != HAL_LL_PIN_NC ) { + if( hal_ll_state == false ) { + tim_config = GPIO_CFG_MODE_ALT_FUNCTION | + GPIO_CFG_SPEED_LOW | + GPIO_CFG_OTYPE_PP; + } else { + tim_config = GPIO_CFG_MODE_ALT_FUNCTION | + GPIO_CFG_SPEED_HIGH | + GPIO_CFG_OTYPE_PP; + } + + module.pins[ 0 ] = VALUE( map->config.pin, map->config.af ); + module.pins[ 1 ] = GPIO_MODULE_STRUCT_END; + + module.configs[ 0 ] = tim_config; + module.configs[ 1 ] = GPIO_MODULE_STRUCT_END; + + hal_ll_gpio_module_struct_init( &module, hal_ll_state ); + } +} + +static void _hal_ll_tim_hw_init( hal_ll_tim_hw_specifics_map_t *map ) { + + uint32_t ck_psc; + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( map->base ); + + // Counter used as upcounter. + clear_reg_bit( &hal_ll_hw_reg->cr1, HAL_LL_TIM_CR1_DIR_BIT ); + + // Get clock speed. + ck_psc = _hal_ll_tim_get_clock_speed( map->base ) / map->freq_hz; + + // This should not be the case. ck_psc should not be greater than 65535, which is max value. + if( ck_psc > UINT16_MAX ) { + // In case of duty period beeing greater than 65535 set ck_psc to max value. + ck_psc = UINT16_MAX - 1; // Because of ( ck_psc / UINT16_MAX + 1 ) ), has to be minus 1. + }else if ( ck_psc < 1 ) { + ck_psc = 1; + } + + // Write prescale value. + hal_ll_hw_reg->psc = ( uint16_t )( ck_psc / UINT16_MAX ); + + // Write max count value. + hal_ll_hw_reg->arr = ( uint16_t )( ck_psc/( ck_psc / UINT16_MAX + 1 ) ); + + // Write max period to global array. + map->max_period = ( uint16_t )ck_psc; +} + +static void _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_t *map ) { + + _hal_ll_tim_set_clock( map->base, true ); + + _hal_ll_tim_alternate_functions_set_state( map, true ); + + _hal_ll_tim_hw_init( map ); +} +// ------------------------------------------------------------------------- END + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_82/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_82/CMakeLists.cmake new file mode 100644 index 000000000..132a5322f --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_82/CMakeLists.cmake @@ -0,0 +1,9 @@ +if(${MCU_NAME} MATCHES "^STM32G431C6$|^STM32G431K6$|^STM32G431R6$|^STM32G431V6$|^STM32G431M6$|^STM32G431C8$|^STM32G431K8$|^STM32G431R8$|^STM32G431V8$|^STM32G431M8$|^STM32G431CB$|^STM32G431KB$|^STM32G431RB$|^STM32G431VB$|^STM32G431MB$") + set(tim_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_tim.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_82") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_82") + list(APPEND hal_ll_def_list "STM32G4xx") + list(APPEND hal_ll_def_list "STM32G43xx") + list(APPEND hal_ll_def_list "STM32G431xx") + set(tim_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/tim/hal_ll_tim_pin_map/implementations/doc_ds_82") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_82/hal_ll_tim.c b/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_82/hal_ll_tim.c new file mode 100644 index 000000000..32260b8a5 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_82/hal_ll_tim.c @@ -0,0 +1,908 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_tim.c + * @brief TIM HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_gpio.h" +#include "hal_ll_rcc.h" +#include "hal_ll_tim.h" +#include "hal_ll_tim_pin_map.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_tim_handle_register_t hal_ll_module_state[ TIM_MODULE_COUNT ]; + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< CR1 constants. */ +#define HAL_LL_TIM_ENABLE_COUNTER_BIT 0 +#define HAL_LL_TIM_BDTR_MOE_BIT 15 +#define HAL_LL_TIM_BDTR_MOE 0x8000 + +#define HAL_LL_TIM_CCMR_CC2S_BIT0 0x100u +#define HAL_LL_TIM_CCMR_CC2S_BIT1 0x200u +#define HAL_LL_TIM_CCMR_OC2PE 0x800u +#define HAL_LL_TIM_CCMR_OC2M_BIT0 0x1000u +#define HAL_LL_TIM_CCMR_OC2M_BIT1 0x2000u +#define HAL_LL_TIM_CCMR_OC2M_BIT2 0x4000u + +#define HAL_LL_TIM_CCMR_CC3S_BIT0 0x1u +#define HAL_LL_TIM_CCMR_CC3S_BIT1 0x2u +#define HAL_LL_TIM_CCMR_OC3PE 0x8u +#define HAL_LL_TIM_CCMR_OC3M_BIT0 0x10u +#define HAL_LL_TIM_CCMR_OC3M_BIT1 0x20u +#define HAL_LL_TIM_CCMR_OC3M_BIT2 0x40u + +#define HAL_LL_TIM_CR1_DIR 0x10 +#define HAL_LL_TIM_CR1_DIR_BIT 4 + +#define HAL_LL_TIM_ENABLE_1 11 +#define HAL_LL_TIM_ENABLE_2 0 +#define HAL_LL_TIM_ENABLE_3 1 +#define HAL_LL_TIM_ENABLE_4 2 +#define HAL_LL_TIM_ENABLE_8 13 +#define HAL_LL_TIM_ENABLE_15 16 +#define HAL_LL_TIM_ENABLE_16 17 +#define HAL_LL_TIM_ENABLE_17 18 + +#define HAL_LL_APB2_TIMER_CLOCK 2 + +#define HAL_LL_APB1_TIMER_CLOCK 1 + + +#define hal_ll_tim_channel_static( _chn ) ( _chn-1 ) + +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_tim_get_base_struct(_handle) ((hal_ll_tim_base_handle_t *)_handle) + +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_tim_get_module_state_address ((hal_ll_tim_handle_register_t *)*handle) + +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_tim_get_handle ( hal_ll_tim_handle_register_t * )hal_ll_tim_get_module_state_address->hal_ll_tim_handle + +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_tim_get_base_from_hal_handle ((hal_ll_tim_hw_specifics_map_t *)((hal_ll_tim_handle_register_t *)\ + (((hal_ll_tim_handle_register_t *)(handle))->hal_ll_tim_handle))->hal_ll_tim_handle)->base + +// -------------------------------------------------------------- PRIVATE TYPES +/*!< @brief TIM register structure. */ +typedef struct +{ + uint32_t cr1; /* Address offset 0x00 */ + uint32_t cr2; /* Address offset 0x04 */ + uint32_t smcr; /* Address offset 0x08 */ + uint32_t dier; /* Address offset 0x0C */ + uint32_t sr; /* Address offset 0x10 */ + uint32_t egr; /* Address offset 0x14 */ + uint32_t ccmr1; /* Address offset 0x18 */ + uint32_t ccmr2; /* Address offset 0x1C */ + uint32_t ccer; /* Address offset 0x20 */ + uint32_t cnt; /* Address offset 0x24 */ + uint32_t psc; /* Address offset 0x28 */ + uint32_t arr; /* Address offset 0x2C */ + uint32_t rcr; /* Address offset 0x30 */ + uint32_t ccr1; /* Address offset 0x34 */ + uint32_t ccr2; /* Address offset 0x38 */ + uint32_t ccr3; /* Address offset 0x3C */ + uint32_t ccr4; /* Address offset 0x40 */ + uint32_t bdtr; /* Address offset 0x44 */ + uint32_t dcr; /* Address offset 0x48 */ + uint32_t dmar; /* Address offset 0x4C */ + uint32_t tim2_5_or; /* Address offset 0x50 */ +} hal_ll_tim_base_handle_t; + +/*!< @brief TIM pin structure */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_channel_t channel; + uint32_t af; +} hal_ll_tim_t; + +/*!< @brief TIM hw specific structure */ +typedef struct +{ + hal_ll_base_addr_t base; + hal_ll_tim_t config; + uint16_t max_period; + uint32_t freq_hz; + hal_ll_pin_name_t module_index; +} hal_ll_tim_hw_specifics_map_t; + +/*!< @brief TIM hw specific error values */ +typedef enum +{ + HAL_LL_TIM_SUCCESS = 0, + HAL_LL_TIM_MODULE_ERROR, + HAL_LL_TIM_WRONG_PIN, + + HAL_LL_TIM_ERROR = (-1) +} hal_ll_tim_err_t; + +// ------------------------------------------------------------------ VARIABLES +/*!< @brief TIM specific info */ +static hal_ll_tim_hw_specifics_map_t hal_ll_tim_hw_specifics_map[] = +{ + #ifdef TIM_MODULE_1 + {HAL_LL_TIM1_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_1 - 1}, + #endif + #ifdef TIM_MODULE_2 + {HAL_LL_TIM2_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_2 - 1}, + #endif + #ifdef TIM_MODULE_3 + {HAL_LL_TIM3_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_3 - 1}, + #endif + #ifdef TIM_MODULE_4 + {HAL_LL_TIM4_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_4 - 1}, + #endif + #ifdef TIM_MODULE_8 + {HAL_LL_TIM8_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_8 - 1}, + #endif + #ifdef TIM_MODULE_15 + {HAL_LL_TIM15_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_15 - 1}, + #endif + #ifdef TIM_MODULE_16 + {HAL_LL_TIM16_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_16 - 1}, + #endif + #ifdef TIM_MODULE_17 + {HAL_LL_TIM17_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_17 - 1}, + #endif + {HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, HAL_LL_PIN_NC} +}; + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_tim_handle_register_t *low_level_handle; +static volatile hal_ll_tim_hw_specifics_map_t *hal_ll_tim_hw_specifics_map_local; + +static bool HAL_LL_TIM_IS_COMPLEMENTARY; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Enable TIM module 1 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim1_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 2 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim2_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 3 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim3_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 4 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim4_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 8 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim8_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 15 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim15_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 16 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim16_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 17 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim17_set_clock( bool hal_ll_state ); + + +/** + * @brief Enable TIM module gate clock. + * @param base - TIM module base + * address + * @return None + */ +static void _hal_ll_tim_set_clock( hal_ll_base_addr_t base, bool hal_ll_state ); + +/** + * @brief Select TIM clock source + * @param selector - clock source selector + * @return uint32_t - clock source + */ +static uint32_t _hal_ll_tim_clock_source( uint8_t selector ); + +/** + * @brief Based on selected TIM, + * return clock speed. + * @param base - TIM module base + * address + * @return uint32_t clock source. + */ +static uint32_t _hal_ll_tim_get_clock_speed( hal_ll_base_addr_t base ); + +/** + * @brief Initialize TIM module on hardware level. + * + * Initializes TIM module on hardware level, based on beforehand + * set configuration and module handler. + * + * @param map - Object specific context handler. + * @return none + * + */ +static void _hal_ll_tim_hw_init( hal_ll_tim_hw_specifics_map_t *map ); + +/** + * @brief Full TIM module initialization procedure. + * + * Initializes TIM module on hardware level, based on beforehand + * set configuration and module handler. Sets adequate pin alternate functions. + * Initializes module clock. + * + * @param map - Object specific context handler. + * @return none + * + */ +static void _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_t *map ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_tim_hw_specifics_map array index. + * + * @param handle - Object specific context handler. + * @return hal_ll_tim_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_tim_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Check if pin is adequate. + * + * Checks tim pin the user has passed with pre-defined + * pin in tim map. + * + * @param pin - TIM pre-defined pin name. + * @return hal_ll_pin_name_t Module index based on pin. + * + * Returns pre-defined module index from pin maps, if pin + * is adequate. + */ +static hal_ll_pin_name_t _hal_ll_tim_check_pin( hal_ll_pin_name_t pin, uint8_t *index, hal_ll_tim_handle_register_t *handle_map ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * TIM pin. + * + * @param[in] module_index TIM HW module index -- 0,1,2... + * @param[in] *index_list Array with TIM map index values + * + * @return None + */ +static void _hal_ll_tim_map_pin( uint8_t module_index, uint8_t index ); + +/** + * @brief Sets TIM pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if TIM is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param map - Object specific context handler. + * + * @param hal_ll_state - Init/De-init + * @return none + * + */ +static void _hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_map_t *map, bool hal_ll_state ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_tim_register_handle( hal_ll_pin_name_t pin, hal_ll_tim_handle_register_t *handle_map, + uint8_t *hal_module_id ) { + + uint8_t index; + uint16_t pin_check_result; + + if ( ( pin_check_result = _hal_ll_tim_check_pin( pin, &index, handle_map ) ) == HAL_LL_PIN_NC ) { + return HAL_LL_TIM_WRONG_PIN; + } + + if ( hal_ll_tim_hw_specifics_map[ pin_check_result ].config.pin != pin ){ + // Clear previous module alternate functions + _hal_ll_tim_alternate_functions_set_state( &hal_ll_tim_hw_specifics_map[ pin_check_result ], false ); + + _hal_ll_tim_map_pin( pin_check_result, index ); + + _hal_ll_tim_alternate_functions_set_state( &hal_ll_tim_hw_specifics_map[ pin_check_result ], true ); + + handle_map[ pin_check_result ].init_ll_state = false; + + hal_ll_module_state[ pin_check_result ].init_ll_state = false; + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle = ( handle_t * )&hal_ll_tim_hw_specifics_map[ pin_check_result ].base; + + handle_map[ pin_check_result ].hal_ll_tim_handle = ( handle_t *)&hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle; + + return HAL_LL_TIM_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_tim( handle_t *handle ) { + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + hal_ll_tim_handle_register_t *hal_handle = (hal_ll_tim_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_tim_hw_specifics_map_local->module_index; + + _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_local ); + + hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle = (handle_t *)&hal_ll_tim_hw_specifics_map[ pin_check_result ].base; + hal_ll_module_state[ pin_check_result ].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_TIM_SUCCESS; +} + +uint32_t hal_ll_tim_set_freq( handle_t *handle, uint32_t freq_hz ) { + + uint32_t tmp_channel; + uint32_t ck_psc; + uint32_t local_base_addr; + uint32_t local_freq; + uint32_t tmp_freq; + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + if( hal_ll_tim_hw_specifics_map_local->base == HAL_LL_MODULE_ERROR ) { + return HAL_LL_TIM_MODULE_ERROR; + } + + low_level_handle->init_ll_state = false; + + tmp_channel = hal_ll_tim_hw_specifics_map_local->config.channel; + + // If complementary output channel is used. + if ( HAL_LL_TIM_IS_COMPLEMENTARY ) { + // Stop capture/compare. + hal_ll_hw_reg->ccer &= 1UL << tmp_channel * 4 + 2; + } else { + // Stop capture/compare. + hal_ll_hw_reg->ccer &= 1UL << tmp_channel * 4; + } + + // Set TIM duty to 0. + *( &hal_ll_hw_reg->ccr1 + hal_ll_tim_channel_static( tmp_channel ) ) = 0; + + hal_ll_tim_hw_specifics_map_local->freq_hz = freq_hz; + + local_freq = hal_ll_tim_hw_specifics_map_local->freq_hz; + local_base_addr = hal_ll_tim_hw_specifics_map_local->base; + + ck_psc = _hal_ll_tim_get_clock_speed( local_base_addr ) / local_freq; + + if ( ck_psc > UINT16_MAX ) { + tmp_freq = _hal_ll_tim_get_clock_speed( local_base_addr ) / UINT16_MAX; + hal_ll_tim_hw_specifics_map_local->freq_hz = tmp_freq; + } else { + tmp_freq = freq_hz; + hal_ll_tim_hw_specifics_map_local->freq_hz = freq_hz; + } + + _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_local ); + + low_level_handle->init_ll_state = true; + + return tmp_freq; +} + +hal_ll_err_t hal_ll_tim_set_duty( handle_t *handle, float duty_ratio ) { + + float tmp_duty; + uint32_t max_duty = 0; + uint16_t max_period; + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + if ( low_level_handle->init_ll_state == false ) { + hal_ll_tim_start( handle ); + low_level_handle->init_ll_state = true; + } + + tmp_duty = duty_ratio * 100; + max_period = hal_ll_tim_hw_specifics_map_local->max_period; + + max_duty = ( ( float )max_period / 100 ) * tmp_duty; + + *( &hal_ll_hw_reg->ccr1 + hal_ll_tim_channel_static( hal_ll_tim_hw_specifics_map_local->config.channel ) ) = max_duty; + + return HAL_LL_TIM_SUCCESS; +} + +hal_ll_err_t hal_ll_tim_start( handle_t *handle ) { + + uint32_t tmp_channel; + volatile uint32_t tmp, + *tmpPtr; + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + tmp_channel = hal_ll_tim_hw_specifics_map_local->config.channel; + + // Capture/Compare 1 output enable. + tmp = hal_ll_hw_reg->ccer; + + // If complementary output channel is used. + if ( HAL_LL_TIM_IS_COMPLEMENTARY ) { + // Capture/Compare complementary output enable + tmp |= ( 1UL << ( hal_ll_tim_channel_static( tmp_channel ) * 4 + 2 ) ); + // Capture/Compare complementary output polarity(ACTIVE HIGH). + tmp &= ~( 1UL << ( hal_ll_tim_channel_static( tmp_channel ) * 4 + 3 ) ); + } else { + // Capture/Compare output polarity. + tmp |= ( 1UL << ( hal_ll_tim_channel_static( tmp_channel ) * 4 ) ); + // Capture/Compare output polarity(ACTIVE HIGH). + tmp &= ~( 1UL << ( hal_ll_tim_channel_static( tmp_channel ) * 4 + 1 ) ); + } + + hal_ll_hw_reg->ccer = tmp; + + #if defined(TIM_MODULE_1) || defined(TIM_MODULE_8) || defined(TIM_MODULE_20) + // Main output enabled. + set_reg_bit( &hal_ll_hw_reg->bdtr, HAL_LL_TIM_BDTR_MOE_BIT ); + #endif + + tmpPtr = &hal_ll_hw_reg->ccmr1; + + if( hal_ll_tim_channel_static( tmp_channel ) > 1 ) { + tmpPtr = &hal_ll_hw_reg->ccmr2; + } + + if( ( hal_ll_tim_channel_static( tmp_channel ) / 2 ) * 2 != + hal_ll_tim_channel_static( tmp_channel ) ) { + // Clear CCxS, OCxM[0]. + *tmpPtr &= ~( HAL_LL_TIM_CCMR_CC2S_BIT0 | + HAL_LL_TIM_CCMR_CC2S_BIT1 | + HAL_LL_TIM_CCMR_OC2PE | + HAL_LL_TIM_CCMR_OC2M_BIT0 ); + // Set OCxM[2, 1] + *tmpPtr |= HAL_LL_TIM_CCMR_OC2M_BIT1 | HAL_LL_TIM_CCMR_OC2M_BIT2; + } else { + // Clear CCxS, OCxM[0]. + *tmpPtr &= ~( HAL_LL_TIM_CCMR_CC3S_BIT0 | + HAL_LL_TIM_CCMR_CC3S_BIT1 | + HAL_LL_TIM_CCMR_OC3PE | + HAL_LL_TIM_CCMR_OC3M_BIT0 ); + + // Set OCxM[2, 1]. + *tmpPtr |= HAL_LL_TIM_CCMR_OC3M_BIT1 | HAL_LL_TIM_CCMR_OC3M_BIT2; + } + + // Enable counter. + set_reg_bit( &hal_ll_hw_reg->cr1, HAL_LL_TIM_ENABLE_COUNTER_BIT ); + + return HAL_LL_TIM_SUCCESS; +} + +hal_ll_err_t hal_ll_tim_stop( handle_t *handle ) { + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + // If complementary output channel is used. + if ( HAL_LL_TIM_IS_COMPLEMENTARY ) { + hal_ll_hw_reg->ccer &= 1UL << hal_ll_tim_hw_specifics_map_local->config.channel * 4 + 2; + } else { + hal_ll_hw_reg->ccer &= 1UL << hal_ll_tim_hw_specifics_map_local->config.channel * 4; + } + + return HAL_LL_TIM_SUCCESS; +} + +void hal_ll_tim_close( handle_t *handle ) { + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_tim_get_module_state_address); + + if( low_level_handle->hal_ll_tim_handle != NULL ) { + low_level_handle->hal_ll_tim_handle = NULL; + low_level_handle->hal_drv_tim_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_tim_hw_specifics_map_local->max_period = 0; + hal_ll_tim_hw_specifics_map_local->freq_hz = 0; + + _hal_ll_tim_set_clock( hal_ll_tim_hw_specifics_map_local->base, true ); + _hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_map_local, false ); + _hal_ll_tim_set_clock( hal_ll_tim_hw_specifics_map_local->base, false ); + + hal_ll_tim_hw_specifics_map_local->config.pin = HAL_LL_PIN_NC; + hal_ll_tim_hw_specifics_map_local->config.channel = HAL_LL_PIN_NC; + hal_ll_tim_hw_specifics_map_local->config.af = NULL; + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static inline void _hal_ll_tim1_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_1 ); + } else { + clear_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_1 ); + } +} + +static inline void _hal_ll_tim2_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB1ENR1, HAL_LL_TIM_ENABLE_2 ); + } else { + clear_reg_bit( _RCC_APB1ENR1, HAL_LL_TIM_ENABLE_2 ); + } +} + +static inline void _hal_ll_tim3_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB1ENR1, HAL_LL_TIM_ENABLE_3 ); + } else { + clear_reg_bit( _RCC_APB1ENR1, HAL_LL_TIM_ENABLE_3 ); + } +} + +static inline void _hal_ll_tim4_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB1ENR1, HAL_LL_TIM_ENABLE_4 ); + } else { + clear_reg_bit( _RCC_APB1ENR1, HAL_LL_TIM_ENABLE_4 ); + } +} + +static inline void _hal_ll_tim8_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_8 ); + } else { + clear_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_8 ); + } +} + +static inline void _hal_ll_tim15_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_15 ); + } else { + clear_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_15 ); + } +} + +static inline void _hal_ll_tim16_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_16 ); + } else { + clear_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_16 ); + } +} + +static inline void _hal_ll_tim17_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_17 ); + } else { + clear_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_17 ); + } +} + +static hal_ll_pin_name_t _hal_ll_tim_check_pin( hal_ll_pin_name_t pin, uint8_t *index, hal_ll_tim_handle_register_t *handle_map ) { + + hal_ll_pin_name_t pin_num; + uint8_t index_counter = 0; + uint8_t hal_ll_module_id = 0; + uint16_t map_size = ( sizeof( _tim_map ) / sizeof( hal_ll_tim_pin_map_t ) ); + + if ( HAL_LL_PIN_NC == pin ) { + return HAL_LL_PIN_NC; + } + + // Check if the selected pin is valid. + for ( pin_num = 0; pin_num < map_size; pin_num++ ) { + if ( _tim_map[ pin_num ].pin == pin ) { + // Get module number + hal_ll_module_id = _tim_map[ pin_num ].module_index; + if ( NULL == handle_map[hal_ll_module_id].hal_drv_tim_handle ) { + *index = pin_num; + return hal_ll_module_id; + } else if ( TIM_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + // By default return last error msg. + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static hal_ll_tim_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + + uint8_t hal_ll_module_count = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_tim_handle_register_t ) ); + static uint8_t hal_ll_module_error = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_tim_handle_register_t ) ); + + while( hal_ll_module_count-- ) { + if ( hal_ll_tim_get_base_from_hal_handle == hal_ll_tim_hw_specifics_map [ hal_ll_module_count ].base) { + return &hal_ll_tim_hw_specifics_map[ hal_ll_module_count ]; + } + } + + return &hal_ll_tim_hw_specifics_map[ hal_ll_module_error ]; +} + +static void _hal_ll_tim_set_clock( hal_ll_base_addr_t base, bool hal_ll_state ) { + + switch ( ( uint32_t )base ) { // 32-bit base address. + #ifdef TIM_MODULE_1 + case ( HAL_LL_TIM1_BASE_ADDR ): + _hal_ll_tim1_set_clock( hal_ll_state ); + break; + #endif + #ifdef TIM_MODULE_2 + case ( HAL_LL_TIM2_BASE_ADDR ): + _hal_ll_tim2_set_clock( hal_ll_state ); + break; + #endif + #ifdef TIM_MODULE_3 + case ( HAL_LL_TIM3_BASE_ADDR ): + _hal_ll_tim3_set_clock( hal_ll_state ); + break; + #endif + #ifdef TIM_MODULE_4 + case ( HAL_LL_TIM4_BASE_ADDR ): + _hal_ll_tim4_set_clock( hal_ll_state ); + break; + #endif + #ifdef TIM_MODULE_8 + case ( HAL_LL_TIM8_BASE_ADDR ): + _hal_ll_tim8_set_clock( hal_ll_state ); + break; + #endif + #ifdef TIM_MODULE_15 + case ( HAL_LL_TIM15_BASE_ADDR ): + _hal_ll_tim15_set_clock( hal_ll_state ); + break; + #endif + #ifdef TIM_MODULE_16 + case ( HAL_LL_TIM16_BASE_ADDR ): + _hal_ll_tim16_set_clock( hal_ll_state ); + break; + #endif + #ifdef TIM_MODULE_17 + case ( HAL_LL_TIM17_BASE_ADDR ): + _hal_ll_tim17_set_clock( hal_ll_state ); + break; + #endif + } +} + +static uint32_t _hal_ll_tim_clock_source( uint8_t selector ) { + + rcc_clocks_t rcc_clocks; + + RCC_GetClocksFrequency( &rcc_clocks ); + + if( selector == HAL_LL_APB2_TIMER_CLOCK ) { + if( rcc_clocks.hclk/rcc_clocks.pclk2 > 1 ) { + return rcc_clocks.pclk2 * 2; + } else { + return rcc_clocks.pclk2; + } + } + + if( selector == HAL_LL_APB1_TIMER_CLOCK ) { + if( rcc_clocks.hclk/rcc_clocks.pclk1 > 1 ) { + return rcc_clocks.pclk1 * 2; + } else { + return rcc_clocks.pclk1; + } + } + + return 0; +} + +static uint32_t _hal_ll_tim_get_clock_speed( hal_ll_base_addr_t base ) { + + switch ( ( uint32_t )base ) { + #ifdef TIM_MODULE_1 + case ( HAL_LL_TIM1_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM1_BUS ); + break; + #endif + #ifdef TIM_MODULE_2 + case ( HAL_LL_TIM2_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM2_BUS ); + break; + #endif + #ifdef TIM_MODULE_3 + case ( HAL_LL_TIM3_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM3_BUS ); + break; + #endif + #ifdef TIM_MODULE_4 + case ( HAL_LL_TIM4_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM4_BUS ); + break; + #endif + #ifdef TIM_MODULE_8 + case ( HAL_LL_TIM8_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM8_BUS ); + break; + #endif + #ifdef TIM_MODULE_15 + case ( HAL_LL_TIM15_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM15_BUS ); + break; + #endif + #ifdef TIM_MODULE_16 + case ( HAL_LL_TIM16_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM16_BUS ); + break; + #endif + #ifdef TIM_MODULE_17 + case ( HAL_LL_TIM17_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM17_BUS ); + break; + #endif + } + return 0; +} + +static void _hal_ll_tim_map_pin( uint8_t module_index, uint8_t index ) { + + uint8_t tmp_channel; + + // Map new pin + hal_ll_tim_hw_specifics_map[ module_index ].config.pin = _tim_map[ index ].pin; + tmp_channel = _tim_map[ index ].channel; + hal_ll_tim_hw_specifics_map[ module_index ].config.af = _tim_map[ index ].af; + + if ( tmp_channel >= HAL_LL_TIM_CHANNEL_1N ) { + HAL_LL_TIM_IS_COMPLEMENTARY = true; + hal_ll_tim_hw_specifics_map[ module_index ].config.channel = tmp_channel - 4; + } else { + HAL_LL_TIM_IS_COMPLEMENTARY = false; + hal_ll_tim_hw_specifics_map[ module_index ].config.channel = tmp_channel; + } +} + +static void _hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_map_t *map, bool hal_ll_state ) { + + module_struct module; + uint32_t tim_config = 0; + + if( map->config.pin != HAL_LL_PIN_NC ) { + if( hal_ll_state == false ) { + tim_config = GPIO_CFG_MODE_ALT_FUNCTION | + GPIO_CFG_SPEED_LOW | + GPIO_CFG_OTYPE_PP; + } else { + tim_config = GPIO_CFG_MODE_ALT_FUNCTION | + GPIO_CFG_SPEED_HIGH | + GPIO_CFG_OTYPE_PP; + } + + module.pins[ 0 ] = VALUE( map->config.pin, map->config.af ); + module.pins[ 1 ] = GPIO_MODULE_STRUCT_END; + + module.configs[ 0 ] = tim_config; + module.configs[ 1 ] = GPIO_MODULE_STRUCT_END; + + hal_ll_gpio_module_struct_init( &module, hal_ll_state ); + } +} + +static void _hal_ll_tim_hw_init( hal_ll_tim_hw_specifics_map_t *map ) { + + uint32_t ck_psc; + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( map->base ); + + // Counter used as upcounter. + clear_reg_bit( &hal_ll_hw_reg->cr1, HAL_LL_TIM_CR1_DIR_BIT ); + + // Get clock speed. + ck_psc = _hal_ll_tim_get_clock_speed( map->base ) / map->freq_hz; + + // This should not be the case. ck_psc should not be greater than 65535, which is max value. + if( ck_psc > UINT16_MAX ) { + // In case of duty period beeing greater than 65535 set ck_psc to max value. + ck_psc = UINT16_MAX - 1; // Because of ( ck_psc / UINT16_MAX + 1 ) ), has to be minus 1. + }else if ( ck_psc < 1 ) { + ck_psc = 1; + } + + // Write prescale value. + hal_ll_hw_reg->psc = ( uint16_t )( ck_psc / UINT16_MAX ); + + // Write max count value. + hal_ll_hw_reg->arr = ( uint16_t )( ck_psc/( ck_psc / UINT16_MAX + 1 ) ); + + // Write max period to global array. + map->max_period = ( uint16_t )ck_psc; +} + +static void _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_t *map ) { + + _hal_ll_tim_set_clock( map->base, true ); + + _hal_ll_tim_alternate_functions_set_state( map, true ); + + _hal_ll_tim_hw_init( map ); +} +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_83/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_83/CMakeLists.cmake new file mode 100644 index 000000000..ae2c8232d --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_83/CMakeLists.cmake @@ -0,0 +1,9 @@ +if(${MCU_NAME} MATCHES "^STM32G441CB$|^STM32G441KB$|^STM32G441RB$|^STM32G441MB$|^STM32G441VB$") + set(tim_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_tim.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_83") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_83") + list(APPEND hal_ll_def_list "STM32G4xx") + list(APPEND hal_ll_def_list "STM32G44xx") + list(APPEND hal_ll_def_list "STM32G441xx") + set(tim_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/tim/hal_ll_tim_pin_map/implementations/doc_ds_83") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_83/hal_ll_tim.c b/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_83/hal_ll_tim.c new file mode 100644 index 000000000..95c2224b7 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_83/hal_ll_tim.c @@ -0,0 +1,945 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_tim.c + * @brief TIM HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_gpio.h" +#include "hal_ll_rcc.h" +#include "hal_ll_tim.h" +#include "hal_ll_tim_pin_map.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_tim_handle_register_t hal_ll_module_state[ TIM_MODULE_COUNT ]; + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< CR1 constants. */ +#define HAL_LL_TIM_ENABLE_COUNTER_BIT 0 +#define HAL_LL_TIM_BDTR_MOE_BIT 15 +#define HAL_LL_TIM_BDTR_MOE 0x8000 + +#define HAL_LL_TIM_CCMR_CC2S_BIT0 0x100u +#define HAL_LL_TIM_CCMR_CC2S_BIT1 0x200u +#define HAL_LL_TIM_CCMR_OC2PE 0x800u +#define HAL_LL_TIM_CCMR_OC2M_BIT0 0x1000u +#define HAL_LL_TIM_CCMR_OC2M_BIT1 0x2000u +#define HAL_LL_TIM_CCMR_OC2M_BIT2 0x4000u + +#define HAL_LL_TIM_CCMR_CC3S_BIT0 0x1u +#define HAL_LL_TIM_CCMR_CC3S_BIT1 0x2u +#define HAL_LL_TIM_CCMR_OC3PE 0x8u +#define HAL_LL_TIM_CCMR_OC3M_BIT0 0x10u +#define HAL_LL_TIM_CCMR_OC3M_BIT1 0x20u +#define HAL_LL_TIM_CCMR_OC3M_BIT2 0x40u + +#define HAL_LL_TIM_CR1_DIR 0x10 +#define HAL_LL_TIM_CR1_DIR_BIT 4 + +#define HAL_LL_TIM_ENABLE_1 11 + +#define HAL_LL_TIM_ENABLE_2 0 + +#define HAL_LL_TIM_ENABLE_3 1 + +#define HAL_LL_TIM_ENABLE_4 2 + +#define HAL_LL_TIM_ENABLE_8 13 + +#define HAL_LL_TIM_ENABLE_15 16 + +#define HAL_LL_TIM_ENABLE_16 17 + +#define HAL_LL_TIM_ENABLE_17 18 + + +#define HAL_LL_APB2_TIMER_CLOCK 2 + +#define HAL_LL_APB1_TIMER_CLOCK 1 + + + +#define hal_ll_tim_channel_static( _chn ) ( _chn-1 ) + +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_tim_get_base_struct(_handle) ((hal_ll_tim_base_handle_t *)_handle) + +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_tim_get_module_state_address ((hal_ll_tim_handle_register_t *)*handle) + +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_tim_get_handle ( hal_ll_tim_handle_register_t * )hal_ll_tim_get_module_state_address->hal_ll_tim_handle + +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_tim_get_base_from_hal_handle ((hal_ll_tim_hw_specifics_map_t *)((hal_ll_tim_handle_register_t *)\ + (((hal_ll_tim_handle_register_t *)(handle))->hal_ll_tim_handle))->hal_ll_tim_handle)->base + +// -------------------------------------------------------------- PRIVATE TYPES +/*!< @brief TIM register structure. */ +typedef struct +{ + uint32_t cr1; /* Address offset 0x00 */ + uint32_t cr2; /* Address offset 0x04 */ + uint32_t smcr; /* Address offset 0x08 */ + uint32_t dier; /* Address offset 0x0C */ + uint32_t sr; /* Address offset 0x10 */ + uint32_t egr; /* Address offset 0x14 */ + uint32_t ccmr1; /* Address offset 0x18 */ + uint32_t ccmr2; /* Address offset 0x1C */ + uint32_t ccer; /* Address offset 0x20 */ + uint32_t cnt; /* Address offset 0x24 */ + uint32_t psc; /* Address offset 0x28 */ + uint32_t arr; /* Address offset 0x2C */ + uint32_t rcr; /* Address offset 0x30 */ + uint32_t ccr1; /* Address offset 0x34 */ + uint32_t ccr2; /* Address offset 0x38 */ + uint32_t ccr3; /* Address offset 0x3C */ + uint32_t ccr4; /* Address offset 0x40 */ + uint32_t bdtr; /* Address offset 0x44 */ + uint32_t dcr; /* Address offset 0x48 */ + uint32_t dmar; /* Address offset 0x4C */ + uint32_t tim2_5_or; /* Address offset 0x50 */ +} hal_ll_tim_base_handle_t; + +/*!< @brief TIM pin structure */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_channel_t channel; + uint32_t af; +} hal_ll_tim_t; + +/*!< @brief TIM hw specific structure */ +typedef struct +{ + hal_ll_base_addr_t base; + hal_ll_tim_t config; + uint16_t max_period; + uint32_t freq_hz; + hal_ll_pin_name_t module_index; +} hal_ll_tim_hw_specifics_map_t; + +/*!< @brief TIM hw specific error values */ +typedef enum +{ + HAL_LL_TIM_SUCCESS = 0, + HAL_LL_TIM_MODULE_ERROR, + HAL_LL_TIM_WRONG_PIN, + + HAL_LL_TIM_ERROR = (-1) +} hal_ll_tim_err_t; + +// ------------------------------------------------------------------ VARIABLES +/*!< @brief TIM specific info */ +static hal_ll_tim_hw_specifics_map_t hal_ll_tim_hw_specifics_map[] = +{ + #ifdef TIM_MODULE_1 + {HAL_LL_TIM1_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_1 - 1}, + #endif + + #ifdef TIM_MODULE_2 + {HAL_LL_TIM2_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_2 - 1}, + #endif + + #ifdef TIM_MODULE_3 + {HAL_LL_TIM3_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_3 - 1}, + #endif + + #ifdef TIM_MODULE_4 + {HAL_LL_TIM4_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_4 - 1}, + #endif + + #ifdef TIM_MODULE_8 + {HAL_LL_TIM8_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_8 - 1}, + #endif + + #ifdef TIM_MODULE_15 + {HAL_LL_TIM15_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_15 - 1}, + #endif + + #ifdef TIM_MODULE_16 + {HAL_LL_TIM16_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_16 - 1}, + #endif + + #ifdef TIM_MODULE_17 + {HAL_LL_TIM17_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_17 - 1}, + #endif + + + {HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, HAL_LL_PIN_NC} +}; + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_tim_handle_register_t *low_level_handle; +static volatile hal_ll_tim_hw_specifics_map_t *hal_ll_tim_hw_specifics_map_local; + +static bool HAL_LL_TIM_IS_COMPLEMENTARY; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Enable TIM module 1 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim1_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 2 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim2_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 3 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim3_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 4 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim4_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 8 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim8_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 15 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim15_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 16 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim16_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 17 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim17_set_clock( bool hal_ll_state ); + + +/** + * @brief Enable TIM module gate clock. + * @param base - TIM module base + * address + * @return None + */ +static void _hal_ll_tim_set_clock( hal_ll_base_addr_t base, bool hal_ll_state ); + +/** + * @brief Select TIM clock source + * @param selector - clock source selector + * @return uint32_t - clock source + */ +static uint32_t _hal_ll_tim_clock_source( uint8_t selector ); + +/** + * @brief Based on selected TIM, + * return clock speed. + * @param base - TIM module base + * address + * @return uint32_t clock source. + */ +static uint32_t _hal_ll_tim_get_clock_speed( hal_ll_base_addr_t base ); + +/** + * @brief Initialize TIM module on hardware level. + * + * Initializes TIM module on hardware level, based on beforehand + * set configuration and module handler. + * + * @param map - Object specific context handler. + * @return none + * + */ +static void _hal_ll_tim_hw_init( hal_ll_tim_hw_specifics_map_t *map ); + +/** + * @brief Full TIM module initialization procedure. + * + * Initializes TIM module on hardware level, based on beforehand + * set configuration and module handler. Sets adequate pin alternate functions. + * Initializes module clock. + * + * @param map - Object specific context handler. + * @return none + * + */ +static void _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_t *map ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_tim_hw_specifics_map array index. + * + * @param handle - Object specific context handler. + * @return hal_ll_tim_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_tim_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Check if pin is adequate. + * + * Checks tim pin the user has passed with pre-defined + * pin in tim map. + * + * @param pin - TIM pre-defined pin name. + * @return hal_ll_pin_name_t Module index based on pin. + * + * Returns pre-defined module index from pin maps, if pin + * is adequate. + */ +static hal_ll_pin_name_t _hal_ll_tim_check_pin( hal_ll_pin_name_t pin, uint8_t *index, hal_ll_tim_handle_register_t *handle_map ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * TIM pin. + * + * @param[in] module_index TIM HW module index -- 0,1,2... + * @param[in] *index_list Array with TIM map index values + * + * @return None + */ +static void _hal_ll_tim_map_pin( uint8_t module_index, uint8_t index ); + +/** + * @brief Sets TIM pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if TIM is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param map - Object specific context handler. + * + * @param hal_ll_state - Init/De-init + * @return none + * + */ +static void _hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_map_t *map, bool hal_ll_state ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_tim_register_handle( hal_ll_pin_name_t pin, hal_ll_tim_handle_register_t *handle_map, + uint8_t *hal_module_id ) { + + uint8_t index; + uint16_t pin_check_result; + + if ( ( pin_check_result = _hal_ll_tim_check_pin( pin, &index, handle_map ) ) == HAL_LL_PIN_NC ) { + return HAL_LL_TIM_WRONG_PIN; + } + + if ( hal_ll_tim_hw_specifics_map[ pin_check_result ].config.pin != pin ){ + // Clear previous module alternate functions + _hal_ll_tim_alternate_functions_set_state( &hal_ll_tim_hw_specifics_map[ pin_check_result ], false ); + + _hal_ll_tim_map_pin( pin_check_result, index ); + + _hal_ll_tim_alternate_functions_set_state( &hal_ll_tim_hw_specifics_map[ pin_check_result ], true ); + + handle_map[ pin_check_result ].init_ll_state = false; + + hal_ll_module_state[ pin_check_result ].init_ll_state = false; + + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle = ( handle_t * )&hal_ll_tim_hw_specifics_map[ pin_check_result ].base; + + handle_map[ pin_check_result ].hal_ll_tim_handle = ( handle_t *)&hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle; + + return HAL_LL_TIM_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_tim( handle_t *handle ) { + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + hal_ll_tim_handle_register_t *hal_handle = (hal_ll_tim_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_tim_hw_specifics_map_local->module_index; + + _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_local ); + + hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle = (handle_t *)&hal_ll_tim_hw_specifics_map[ pin_check_result ].base; + hal_ll_module_state[ pin_check_result ].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_TIM_SUCCESS; +} + +uint32_t hal_ll_tim_set_freq( handle_t *handle, uint32_t freq_hz ) { + + uint32_t tmp_channel; + uint32_t ck_psc; + uint32_t local_base_addr; + uint32_t local_freq; + uint32_t tmp_freq; + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + if( hal_ll_tim_hw_specifics_map_local->base == HAL_LL_MODULE_ERROR ) { + return HAL_LL_TIM_MODULE_ERROR; + } + + low_level_handle->init_ll_state = false; + + tmp_channel = hal_ll_tim_hw_specifics_map_local->config.channel; + + // If complementary output channel is used. + if ( HAL_LL_TIM_IS_COMPLEMENTARY ) { + // Stop capture/compare. + hal_ll_hw_reg->ccer &= 1UL << tmp_channel * 4 + 2; + } else { + // Stop capture/compare. + hal_ll_hw_reg->ccer &= 1UL << tmp_channel * 4; + } + + // Set TIM duty to 0. + *( &hal_ll_hw_reg->ccr1 + hal_ll_tim_channel_static( tmp_channel ) ) = 0; + + hal_ll_tim_hw_specifics_map_local->freq_hz = freq_hz; + + local_freq = hal_ll_tim_hw_specifics_map_local->freq_hz; + local_base_addr = hal_ll_tim_hw_specifics_map_local->base; + + ck_psc = _hal_ll_tim_get_clock_speed( local_base_addr ) / local_freq; + + if ( ck_psc > UINT16_MAX ) { + tmp_freq = _hal_ll_tim_get_clock_speed( local_base_addr ) / UINT16_MAX; + hal_ll_tim_hw_specifics_map_local->freq_hz = tmp_freq; + } else { + tmp_freq = freq_hz; + hal_ll_tim_hw_specifics_map_local->freq_hz = freq_hz; + } + + _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_local ); + + low_level_handle->init_ll_state = true; + + return tmp_freq; +} + +hal_ll_err_t hal_ll_tim_set_duty( handle_t *handle, float duty_ratio ) { + + float tmp_duty; + uint32_t max_duty = 0; + uint16_t max_period; + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + if ( low_level_handle->init_ll_state == false ) { + hal_ll_tim_start( handle ); + low_level_handle->init_ll_state = true; + } + + tmp_duty = duty_ratio * 100; + max_period = hal_ll_tim_hw_specifics_map_local->max_period; + + max_duty = ( ( float )max_period / 100 ) * tmp_duty; + + *( &hal_ll_hw_reg->ccr1 + hal_ll_tim_channel_static( hal_ll_tim_hw_specifics_map_local->config.channel ) ) = max_duty; + + return HAL_LL_TIM_SUCCESS; +} + +hal_ll_err_t hal_ll_tim_start( handle_t *handle ) { + + uint32_t tmp_channel; + volatile uint32_t tmp, + *tmpPtr; + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + tmp_channel = hal_ll_tim_hw_specifics_map_local->config.channel; + + // Capture/Compare 1 output enable. + tmp = hal_ll_hw_reg->ccer; + + // If complementary output channel is used. + if ( HAL_LL_TIM_IS_COMPLEMENTARY ) { + // Capture/Compare complementary output enable + tmp |= ( 1UL << ( hal_ll_tim_channel_static( tmp_channel ) * 4 + 2 ) ); + // Capture/Compare complementary output polarity(ACTIVE HIGH). + tmp &= ~( 1UL << ( hal_ll_tim_channel_static( tmp_channel ) * 4 + 3 ) ); + } else { + // Capture/Compare output polarity. + tmp |= ( 1UL << ( hal_ll_tim_channel_static( tmp_channel ) * 4 ) ); + // Capture/Compare output polarity(ACTIVE HIGH). + tmp &= ~( 1UL << ( hal_ll_tim_channel_static( tmp_channel ) * 4 + 1 ) ); + } + + hal_ll_hw_reg->ccer = tmp; + + #if defined(TIM_MODULE_1) || defined(TIM_MODULE_8) || defined(TIM_MODULE_20) + // Main output enabled. + set_reg_bit( &hal_ll_hw_reg->bdtr, HAL_LL_TIM_BDTR_MOE_BIT ); + #endif + + tmpPtr = &hal_ll_hw_reg->ccmr1; + + if( hal_ll_tim_channel_static( tmp_channel ) > 1 ) { + tmpPtr = &hal_ll_hw_reg->ccmr2; + } + + if( ( hal_ll_tim_channel_static( tmp_channel ) / 2 ) * 2 != + hal_ll_tim_channel_static( tmp_channel ) ) { + // Clear CCxS, OCxM[0]. + *tmpPtr &= ~( HAL_LL_TIM_CCMR_CC2S_BIT0 | + HAL_LL_TIM_CCMR_CC2S_BIT1 | + HAL_LL_TIM_CCMR_OC2PE | + HAL_LL_TIM_CCMR_OC2M_BIT0 ); + // Set OCxM[2, 1] + *tmpPtr |= HAL_LL_TIM_CCMR_OC2M_BIT1 | HAL_LL_TIM_CCMR_OC2M_BIT2; + } else { + // Clear CCxS, OCxM[0]. + *tmpPtr &= ~( HAL_LL_TIM_CCMR_CC3S_BIT0 | + HAL_LL_TIM_CCMR_CC3S_BIT1 | + HAL_LL_TIM_CCMR_OC3PE | + HAL_LL_TIM_CCMR_OC3M_BIT0 ); + + // Set OCxM[2, 1]. + *tmpPtr |= HAL_LL_TIM_CCMR_OC3M_BIT1 | HAL_LL_TIM_CCMR_OC3M_BIT2; + } + + // Enable counter. + set_reg_bit( &hal_ll_hw_reg->cr1, HAL_LL_TIM_ENABLE_COUNTER_BIT ); + + return HAL_LL_TIM_SUCCESS; +} + +hal_ll_err_t hal_ll_tim_stop( handle_t *handle ) { + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + // If complementary output channel is used. + if ( HAL_LL_TIM_IS_COMPLEMENTARY ) { + hal_ll_hw_reg->ccer &= 1UL << hal_ll_tim_hw_specifics_map_local->config.channel * 4 + 2; + } else { + hal_ll_hw_reg->ccer &= 1UL << hal_ll_tim_hw_specifics_map_local->config.channel * 4; + } + + return HAL_LL_TIM_SUCCESS; +} + +void hal_ll_tim_close( handle_t *handle ) { + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_tim_get_module_state_address); + + if( low_level_handle->hal_ll_tim_handle != NULL ) { + low_level_handle->hal_ll_tim_handle = NULL; + low_level_handle->hal_drv_tim_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_tim_hw_specifics_map_local->max_period = 0; + hal_ll_tim_hw_specifics_map_local->freq_hz = 0; + + _hal_ll_tim_set_clock( hal_ll_tim_hw_specifics_map_local->base, true ); + _hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_map_local, false ); + _hal_ll_tim_set_clock( hal_ll_tim_hw_specifics_map_local->base, false ); + + hal_ll_tim_hw_specifics_map_local->config.pin = HAL_LL_PIN_NC; + hal_ll_tim_hw_specifics_map_local->config.channel = HAL_LL_PIN_NC; + hal_ll_tim_hw_specifics_map_local->config.af = NULL; + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static inline void _hal_ll_tim1_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_1 ); + } else { + clear_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_1 ); + } +} + +static inline void _hal_ll_tim2_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB1ENR1, HAL_LL_TIM_ENABLE_2 ); + } else { + clear_reg_bit( _RCC_APB1ENR1, HAL_LL_TIM_ENABLE_2 ); + } +} + +static inline void _hal_ll_tim3_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB1ENR1, HAL_LL_TIM_ENABLE_3 ); + } else { + clear_reg_bit( _RCC_APB1ENR1, HAL_LL_TIM_ENABLE_3 ); + } +} + +static inline void _hal_ll_tim4_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB1ENR1, HAL_LL_TIM_ENABLE_4 ); + } else { + clear_reg_bit( _RCC_APB1ENR1, HAL_LL_TIM_ENABLE_4 ); + } +} + +static inline void _hal_ll_tim8_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_8 ); + } else { + clear_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_8 ); + } +} + +static inline void _hal_ll_tim15_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_15 ); + } else { + clear_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_15 ); + } +} + +static inline void _hal_ll_tim16_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_16 ); + } else { + clear_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_16 ); + } +} + +static inline void _hal_ll_tim17_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_17 ); + } else { + clear_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_17 ); + } +} + + +static hal_ll_pin_name_t _hal_ll_tim_check_pin( hal_ll_pin_name_t pin, uint8_t *index, hal_ll_tim_handle_register_t *handle_map ) { + + hal_ll_pin_name_t pin_num; + uint8_t index_counter = 0; + uint8_t hal_ll_module_id = 0; + uint16_t map_size = ( sizeof( _tim_map ) / sizeof( hal_ll_tim_pin_map_t ) ); + + if ( HAL_LL_PIN_NC == pin ) { + return HAL_LL_PIN_NC; + } + + // Check if the selected pin is valid. + for ( pin_num = 0; pin_num < map_size; pin_num++ ) { + if ( _tim_map[ pin_num ].pin == pin ) { + // Get module number + hal_ll_module_id = _tim_map[ pin_num ].module_index; + if ( NULL == handle_map[hal_ll_module_id].hal_drv_tim_handle ) { + *index = pin_num; + return hal_ll_module_id; + } else if ( TIM_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + // By default return last error msg. + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static hal_ll_tim_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + + uint8_t hal_ll_module_count = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_tim_handle_register_t ) ); + static uint8_t hal_ll_module_error = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_tim_handle_register_t ) ); + + while( hal_ll_module_count-- ) { + if ( hal_ll_tim_get_base_from_hal_handle == hal_ll_tim_hw_specifics_map [ hal_ll_module_count ].base) { + return &hal_ll_tim_hw_specifics_map[ hal_ll_module_count ]; + } + } + + return &hal_ll_tim_hw_specifics_map[ hal_ll_module_error ]; +} + +static void _hal_ll_tim_set_clock( hal_ll_base_addr_t base, bool hal_ll_state ) { + + switch ( ( uint32_t )base ) { // 32-bit base address. + #ifdef TIM_MODULE_1 + case ( HAL_LL_TIM1_BASE_ADDR ): + _hal_ll_tim1_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_2 + case ( HAL_LL_TIM2_BASE_ADDR ): + _hal_ll_tim2_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_3 + case ( HAL_LL_TIM3_BASE_ADDR ): + _hal_ll_tim3_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_4 + case ( HAL_LL_TIM4_BASE_ADDR ): + _hal_ll_tim4_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_8 + case ( HAL_LL_TIM8_BASE_ADDR ): + _hal_ll_tim8_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_15 + case ( HAL_LL_TIM15_BASE_ADDR ): + _hal_ll_tim15_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_16 + case ( HAL_LL_TIM16_BASE_ADDR ): + _hal_ll_tim16_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_17 + case ( HAL_LL_TIM17_BASE_ADDR ): + _hal_ll_tim17_set_clock( hal_ll_state ); + break; + #endif + + } +} + +static uint32_t _hal_ll_tim_clock_source( uint8_t selector ) { + + rcc_clocks_t rcc_clocks; + + RCC_GetClocksFrequency( &rcc_clocks ); + + if( selector == HAL_LL_APB2_TIMER_CLOCK ) { + if( rcc_clocks.hclk/rcc_clocks.pclk2 > 1 ) { + return rcc_clocks.pclk2 * 2; + } else { + return rcc_clocks.pclk2; + } + } + + if( selector == HAL_LL_APB1_TIMER_CLOCK ) { + if( rcc_clocks.hclk/rcc_clocks.pclk1 > 1 ) { + return rcc_clocks.pclk1 * 2; + } else { + return rcc_clocks.pclk1; + } + } + + return 0; +} + +static uint32_t _hal_ll_tim_get_clock_speed( hal_ll_base_addr_t base ) { + + switch ( ( uint32_t )base ) { + #ifdef TIM_MODULE_1 + case ( HAL_LL_TIM1_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM1_BUS ); + break; + #endif + + #ifdef TIM_MODULE_2 + case ( HAL_LL_TIM2_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM2_BUS ); + break; + #endif + + #ifdef TIM_MODULE_3 + case ( HAL_LL_TIM3_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM3_BUS ); + break; + #endif + + #ifdef TIM_MODULE_4 + case ( HAL_LL_TIM4_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM4_BUS ); + break; + #endif + + #ifdef TIM_MODULE_8 + case ( HAL_LL_TIM8_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM8_BUS ); + break; + #endif + + #ifdef TIM_MODULE_15 + case ( HAL_LL_TIM15_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM15_BUS ); + break; + #endif + + #ifdef TIM_MODULE_16 + case ( HAL_LL_TIM16_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM16_BUS ); + break; + #endif + + #ifdef TIM_MODULE_17 + case ( HAL_LL_TIM17_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM17_BUS ); + break; + #endif + + } + return 0; +} + +static void _hal_ll_tim_map_pin( uint8_t module_index, uint8_t index ) { + + uint8_t tmp_channel; + + // Map new pin + hal_ll_tim_hw_specifics_map[ module_index ].config.pin = _tim_map[ index ].pin; + tmp_channel = _tim_map[ index ].channel; + hal_ll_tim_hw_specifics_map[ module_index ].config.af = _tim_map[ index ].af; + + if ( tmp_channel >= HAL_LL_TIM_CHANNEL_1N ) { + HAL_LL_TIM_IS_COMPLEMENTARY = true; + hal_ll_tim_hw_specifics_map[ module_index ].config.channel = tmp_channel - 4; + } else { + HAL_LL_TIM_IS_COMPLEMENTARY = false; + hal_ll_tim_hw_specifics_map[ module_index ].config.channel = tmp_channel; + } +} + +static void _hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_map_t *map, bool hal_ll_state ) { + + module_struct module; + uint32_t tim_config = 0; + + if( map->config.pin != HAL_LL_PIN_NC ) { + if( hal_ll_state == false ) { + tim_config = GPIO_CFG_MODE_ALT_FUNCTION | + GPIO_CFG_SPEED_LOW | + GPIO_CFG_OTYPE_PP; + } else { + tim_config = GPIO_CFG_MODE_ALT_FUNCTION | + GPIO_CFG_SPEED_HIGH | + GPIO_CFG_OTYPE_PP; + } + + module.pins[ 0 ] = VALUE( map->config.pin, map->config.af ); + module.pins[ 1 ] = GPIO_MODULE_STRUCT_END; + + module.configs[ 0 ] = tim_config; + module.configs[ 1 ] = GPIO_MODULE_STRUCT_END; + + hal_ll_gpio_module_struct_init( &module, hal_ll_state ); + } +} + +static void _hal_ll_tim_hw_init( hal_ll_tim_hw_specifics_map_t *map ) { + + uint32_t ck_psc; + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( map->base ); + + // Counter used as upcounter. + clear_reg_bit( &hal_ll_hw_reg->cr1, HAL_LL_TIM_CR1_DIR_BIT ); + + // Get clock speed. + ck_psc = _hal_ll_tim_get_clock_speed( map->base ) / map->freq_hz; + + // This should not be the case. ck_psc should not be greater than 65535, which is max value. + if( ck_psc > UINT16_MAX ) { + // In case of duty period beeing greater than 65535 set ck_psc to max value. + ck_psc = UINT16_MAX - 1; // Because of ( ck_psc / UINT16_MAX + 1 ) ), has to be minus 1. + }else if ( ck_psc < 1 ) { + ck_psc = 1; + } + + // Write prescale value. + hal_ll_hw_reg->psc = ( uint16_t )( ck_psc / UINT16_MAX ); + + // Write max count value. + hal_ll_hw_reg->arr = ( uint16_t )( ck_psc/( ck_psc / UINT16_MAX + 1 ) ); + + // Write max period to global array. + map->max_period = ( uint16_t )ck_psc; +} + +static void _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_t *map ) { + + _hal_ll_tim_set_clock( map->base, true ); + + _hal_ll_tim_alternate_functions_set_state( map, true ); + + _hal_ll_tim_hw_init( map ); +} +// ------------------------------------------------------------------------- END + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_84/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_84/CMakeLists.cmake new file mode 100644 index 000000000..f7c153e2d --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_84/CMakeLists.cmake @@ -0,0 +1,9 @@ +if(${MCU_NAME} MATCHES "^STM32G473CB$|^STM32G473MB$|^STM32G473PB$|^STM32G473RB$|^STM32G473VB$|^STM32G473QB$|^STM32G473CC$|^STM32G473MC$|^STM32G473PC$|^STM32G473RC$|^STM32G473VC$|^STM32G473QC$|^STM32G473CE$|^STM32G473ME$|^STM32G473PE$|^STM32G473RE$|^STM32G473VE$|^STM32G473QE$") + set(tim_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_tim.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_84") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_84") + list(APPEND hal_ll_def_list "STM32G4xx") + list(APPEND hal_ll_def_list "STM32G47xx") + list(APPEND hal_ll_def_list "STM32G473xx") + set(tim_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/tim/hal_ll_tim_pin_map/implementations/doc_ds_84") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_84/hal_ll_tim.c b/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_84/hal_ll_tim.c new file mode 100644 index 000000000..877a26adb --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_84/hal_ll_tim.c @@ -0,0 +1,1011 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_tim.c + * @brief TIM HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_gpio.h" +#include "hal_ll_rcc.h" +#include "hal_ll_tim.h" +#include "hal_ll_tim_pin_map.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_tim_handle_register_t hal_ll_module_state[ TIM_MODULE_COUNT ]; + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< CR1 constants. */ +#define HAL_LL_TIM_ENABLE_COUNTER_BIT 0 +#define HAL_LL_TIM_BDTR_MOE_BIT 15 +#define HAL_LL_TIM_BDTR_MOE 0x8000 + +#define HAL_LL_TIM_CCMR_CC2S_BIT0 0x100u +#define HAL_LL_TIM_CCMR_CC2S_BIT1 0x200u +#define HAL_LL_TIM_CCMR_OC2PE 0x800u +#define HAL_LL_TIM_CCMR_OC2M_BIT0 0x1000u +#define HAL_LL_TIM_CCMR_OC2M_BIT1 0x2000u +#define HAL_LL_TIM_CCMR_OC2M_BIT2 0x4000u + +#define HAL_LL_TIM_CCMR_CC3S_BIT0 0x1u +#define HAL_LL_TIM_CCMR_CC3S_BIT1 0x2u +#define HAL_LL_TIM_CCMR_OC3PE 0x8u +#define HAL_LL_TIM_CCMR_OC3M_BIT0 0x10u +#define HAL_LL_TIM_CCMR_OC3M_BIT1 0x20u +#define HAL_LL_TIM_CCMR_OC3M_BIT2 0x40u + +#define HAL_LL_TIM_CR1_DIR 0x10 +#define HAL_LL_TIM_CR1_DIR_BIT 4 + +#define HAL_LL_TIM_ENABLE_1 11 + +#define HAL_LL_TIM_ENABLE_2 0 + +#define HAL_LL_TIM_ENABLE_3 1 + +#define HAL_LL_TIM_ENABLE_4 2 + +#define HAL_LL_TIM_ENABLE_5 3 + +#define HAL_LL_TIM_ENABLE_8 13 + +#define HAL_LL_TIM_ENABLE_15 16 + +#define HAL_LL_TIM_ENABLE_16 17 + +#define HAL_LL_TIM_ENABLE_17 18 + +#define HAL_LL_TIM_ENABLE_20 20 + + +#define HAL_LL_APB2_TIMER_CLOCK 2 + +#define HAL_LL_APB1_TIMER_CLOCK 1 + + + +#define hal_ll_tim_channel_static( _chn ) ( _chn-1 ) + +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_tim_get_base_struct(_handle) ((hal_ll_tim_base_handle_t *)_handle) + +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_tim_get_module_state_address ((hal_ll_tim_handle_register_t *)*handle) + +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_tim_get_handle ( hal_ll_tim_handle_register_t * )hal_ll_tim_get_module_state_address->hal_ll_tim_handle + +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_tim_get_base_from_hal_handle ((hal_ll_tim_hw_specifics_map_t *)((hal_ll_tim_handle_register_t *)\ + (((hal_ll_tim_handle_register_t *)(handle))->hal_ll_tim_handle))->hal_ll_tim_handle)->base + +// -------------------------------------------------------------- PRIVATE TYPES +/*!< @brief TIM register structure. */ +typedef struct +{ + uint32_t cr1; /* Address offset 0x00 */ + uint32_t cr2; /* Address offset 0x04 */ + uint32_t smcr; /* Address offset 0x08 */ + uint32_t dier; /* Address offset 0x0C */ + uint32_t sr; /* Address offset 0x10 */ + uint32_t egr; /* Address offset 0x14 */ + uint32_t ccmr1; /* Address offset 0x18 */ + uint32_t ccmr2; /* Address offset 0x1C */ + uint32_t ccer; /* Address offset 0x20 */ + uint32_t cnt; /* Address offset 0x24 */ + uint32_t psc; /* Address offset 0x28 */ + uint32_t arr; /* Address offset 0x2C */ + uint32_t rcr; /* Address offset 0x30 */ + uint32_t ccr1; /* Address offset 0x34 */ + uint32_t ccr2; /* Address offset 0x38 */ + uint32_t ccr3; /* Address offset 0x3C */ + uint32_t ccr4; /* Address offset 0x40 */ + uint32_t bdtr; /* Address offset 0x44 */ + uint32_t dcr; /* Address offset 0x48 */ + uint32_t dmar; /* Address offset 0x4C */ + uint32_t tim2_5_or; /* Address offset 0x50 */ +} hal_ll_tim_base_handle_t; + +/*!< @brief TIM pin structure */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_channel_t channel; + uint32_t af; +} hal_ll_tim_t; + +/*!< @brief TIM hw specific structure */ +typedef struct +{ + hal_ll_base_addr_t base; + hal_ll_tim_t config; + uint16_t max_period; + uint32_t freq_hz; + hal_ll_pin_name_t module_index; +} hal_ll_tim_hw_specifics_map_t; + +/*!< @brief TIM hw specific error values */ +typedef enum +{ + HAL_LL_TIM_SUCCESS = 0, + HAL_LL_TIM_MODULE_ERROR, + HAL_LL_TIM_WRONG_PIN, + + HAL_LL_TIM_ERROR = (-1) +} hal_ll_tim_err_t; + +// ------------------------------------------------------------------ VARIABLES +/*!< @brief TIM specific info */ +static hal_ll_tim_hw_specifics_map_t hal_ll_tim_hw_specifics_map[] = +{ + #ifdef TIM_MODULE_1 + {HAL_LL_TIM1_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_1 - 1}, + #endif + + #ifdef TIM_MODULE_2 + {HAL_LL_TIM2_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_2 - 1}, + #endif + + #ifdef TIM_MODULE_3 + {HAL_LL_TIM3_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_3 - 1}, + #endif + + #ifdef TIM_MODULE_4 + {HAL_LL_TIM4_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_4 - 1}, + #endif + + #ifdef TIM_MODULE_5 + {HAL_LL_TIM5_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_5 - 1}, + #endif + + #ifdef TIM_MODULE_8 + {HAL_LL_TIM8_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_8 - 1}, + #endif + + #ifdef TIM_MODULE_15 + {HAL_LL_TIM15_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_15 - 1}, + #endif + + #ifdef TIM_MODULE_16 + {HAL_LL_TIM16_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_16 - 1}, + #endif + + #ifdef TIM_MODULE_17 + {HAL_LL_TIM17_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_17 - 1}, + #endif + + #ifdef TIM_MODULE_20 + {HAL_LL_TIM20_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_20 - 1}, + #endif + + + {HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, HAL_LL_PIN_NC} +}; + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_tim_handle_register_t *low_level_handle; +static volatile hal_ll_tim_hw_specifics_map_t *hal_ll_tim_hw_specifics_map_local; + +static bool HAL_LL_TIM_IS_COMPLEMENTARY; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Enable TIM module 1 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim1_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 2 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim2_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 3 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim3_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 4 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim4_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 5 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim5_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 8 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim8_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 15 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim15_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 16 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim16_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 17 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim17_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 20 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim20_set_clock( bool hal_ll_state ); + + +/** + * @brief Enable TIM module gate clock. + * @param base - TIM module base + * address + * @return None + */ +static void _hal_ll_tim_set_clock( hal_ll_base_addr_t base, bool hal_ll_state ); + +/** + * @brief Select TIM clock source + * @param selector - clock source selector + * @return uint32_t - clock source + */ +static uint32_t _hal_ll_tim_clock_source( uint8_t selector ); + +/** + * @brief Based on selected TIM, + * return clock speed. + * @param base - TIM module base + * address + * @return uint32_t clock source. + */ +static uint32_t _hal_ll_tim_get_clock_speed( hal_ll_base_addr_t base ); + +/** + * @brief Initialize TIM module on hardware level. + * + * Initializes TIM module on hardware level, based on beforehand + * set configuration and module handler. + * + * @param map - Object specific context handler. + * @return none + * + */ +static void _hal_ll_tim_hw_init( hal_ll_tim_hw_specifics_map_t *map ); + +/** + * @brief Full TIM module initialization procedure. + * + * Initializes TIM module on hardware level, based on beforehand + * set configuration and module handler. Sets adequate pin alternate functions. + * Initializes module clock. + * + * @param map - Object specific context handler. + * @return none + * + */ +static void _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_t *map ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_tim_hw_specifics_map array index. + * + * @param handle - Object specific context handler. + * @return hal_ll_tim_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_tim_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Check if pin is adequate. + * + * Checks tim pin the user has passed with pre-defined + * pin in tim map. + * + * @param pin - TIM pre-defined pin name. + * @return hal_ll_pin_name_t Module index based on pin. + * + * Returns pre-defined module index from pin maps, if pin + * is adequate. + */ +static hal_ll_pin_name_t _hal_ll_tim_check_pin( hal_ll_pin_name_t pin, uint8_t *index, hal_ll_tim_handle_register_t *handle_map ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * TIM pin. + * + * @param[in] module_index TIM HW module index -- 0,1,2... + * @param[in] *index_list Array with TIM map index values + * + * @return None + */ +static void _hal_ll_tim_map_pin( uint8_t module_index, uint8_t index ); + +/** + * @brief Sets TIM pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if TIM is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param map - Object specific context handler. + * + * @param hal_ll_state - Init/De-init + * @return none + * + */ +static void _hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_map_t *map, bool hal_ll_state ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_tim_register_handle( hal_ll_pin_name_t pin, hal_ll_tim_handle_register_t *handle_map, + uint8_t *hal_module_id ) { + + uint8_t index; + uint16_t pin_check_result; + + if ( ( pin_check_result = _hal_ll_tim_check_pin( pin, &index, handle_map ) ) == HAL_LL_PIN_NC ) { + return HAL_LL_TIM_WRONG_PIN; + } + + if ( hal_ll_tim_hw_specifics_map[ pin_check_result ].config.pin != pin ){ + // Clear previous module alternate functions + _hal_ll_tim_alternate_functions_set_state( &hal_ll_tim_hw_specifics_map[ pin_check_result ], false ); + + _hal_ll_tim_map_pin( pin_check_result, index ); + + _hal_ll_tim_alternate_functions_set_state( &hal_ll_tim_hw_specifics_map[ pin_check_result ], true ); + + handle_map[ pin_check_result ].init_ll_state = false; + + hal_ll_module_state[ pin_check_result ].init_ll_state = false; + + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle = ( handle_t * )&hal_ll_tim_hw_specifics_map[ pin_check_result ].base; + + handle_map[ pin_check_result ].hal_ll_tim_handle = ( handle_t *)&hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle; + + return HAL_LL_TIM_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_tim( handle_t *handle ) { + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + hal_ll_tim_handle_register_t *hal_handle = (hal_ll_tim_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_tim_hw_specifics_map_local->module_index; + + _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_local ); + + hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle = (handle_t *)&hal_ll_tim_hw_specifics_map[ pin_check_result ].base; + hal_ll_module_state[ pin_check_result ].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_TIM_SUCCESS; +} + +uint32_t hal_ll_tim_set_freq( handle_t *handle, uint32_t freq_hz ) { + + uint32_t tmp_channel; + uint32_t ck_psc; + uint32_t local_base_addr; + uint32_t local_freq; + uint32_t tmp_freq; + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + if( hal_ll_tim_hw_specifics_map_local->base == HAL_LL_MODULE_ERROR ) { + return HAL_LL_TIM_MODULE_ERROR; + } + + low_level_handle->init_ll_state = false; + + tmp_channel = hal_ll_tim_hw_specifics_map_local->config.channel; + + // If complementary output channel is used. + if ( HAL_LL_TIM_IS_COMPLEMENTARY ) { + // Stop capture/compare. + hal_ll_hw_reg->ccer &= 1UL << tmp_channel * 4 + 2; + } else { + // Stop capture/compare. + hal_ll_hw_reg->ccer &= 1UL << tmp_channel * 4; + } + + // Set TIM duty to 0. + *( &hal_ll_hw_reg->ccr1 + hal_ll_tim_channel_static( tmp_channel ) ) = 0; + + hal_ll_tim_hw_specifics_map_local->freq_hz = freq_hz; + + local_freq = hal_ll_tim_hw_specifics_map_local->freq_hz; + local_base_addr = hal_ll_tim_hw_specifics_map_local->base; + + ck_psc = _hal_ll_tim_get_clock_speed( local_base_addr ) / local_freq; + + if ( ck_psc > UINT16_MAX ) { + tmp_freq = _hal_ll_tim_get_clock_speed( local_base_addr ) / UINT16_MAX; + hal_ll_tim_hw_specifics_map_local->freq_hz = tmp_freq; + } else { + tmp_freq = freq_hz; + hal_ll_tim_hw_specifics_map_local->freq_hz = freq_hz; + } + + _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_local ); + + low_level_handle->init_ll_state = true; + + return tmp_freq; +} + +hal_ll_err_t hal_ll_tim_set_duty( handle_t *handle, float duty_ratio ) { + + float tmp_duty; + uint32_t max_duty = 0; + uint16_t max_period; + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + if ( low_level_handle->init_ll_state == false ) { + hal_ll_tim_start( handle ); + low_level_handle->init_ll_state = true; + } + + tmp_duty = duty_ratio * 100; + max_period = hal_ll_tim_hw_specifics_map_local->max_period; + + max_duty = ( ( float )max_period / 100 ) * tmp_duty; + + *( &hal_ll_hw_reg->ccr1 + hal_ll_tim_channel_static( hal_ll_tim_hw_specifics_map_local->config.channel ) ) = max_duty; + + return HAL_LL_TIM_SUCCESS; +} + +hal_ll_err_t hal_ll_tim_start( handle_t *handle ) { + + uint32_t tmp_channel; + volatile uint32_t tmp, + *tmpPtr; + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + tmp_channel = hal_ll_tim_hw_specifics_map_local->config.channel; + + // Capture/Compare 1 output enable. + tmp = hal_ll_hw_reg->ccer; + + // If complementary output channel is used. + if ( HAL_LL_TIM_IS_COMPLEMENTARY ) { + // Capture/Compare complementary output enable + tmp |= ( 1UL << ( hal_ll_tim_channel_static( tmp_channel ) * 4 + 2 ) ); + // Capture/Compare complementary output polarity(ACTIVE HIGH). + tmp &= ~( 1UL << ( hal_ll_tim_channel_static( tmp_channel ) * 4 + 3 ) ); + } else { + // Capture/Compare output polarity. + tmp |= ( 1UL << ( hal_ll_tim_channel_static( tmp_channel ) * 4 ) ); + // Capture/Compare output polarity(ACTIVE HIGH). + tmp &= ~( 1UL << ( hal_ll_tim_channel_static( tmp_channel ) * 4 + 1 ) ); + } + + hal_ll_hw_reg->ccer = tmp; + + #if defined(TIM_MODULE_1) || defined(TIM_MODULE_8) || defined(TIM_MODULE_20) + // Main output enabled. + set_reg_bit( &hal_ll_hw_reg->bdtr, HAL_LL_TIM_BDTR_MOE_BIT ); + #endif + + tmpPtr = &hal_ll_hw_reg->ccmr1; + + if( hal_ll_tim_channel_static( tmp_channel ) > 1 ) { + tmpPtr = &hal_ll_hw_reg->ccmr2; + } + + if( ( hal_ll_tim_channel_static( tmp_channel ) / 2 ) * 2 != + hal_ll_tim_channel_static( tmp_channel ) ) { + // Clear CCxS, OCxM[0]. + *tmpPtr &= ~( HAL_LL_TIM_CCMR_CC2S_BIT0 | + HAL_LL_TIM_CCMR_CC2S_BIT1 | + HAL_LL_TIM_CCMR_OC2PE | + HAL_LL_TIM_CCMR_OC2M_BIT0 ); + // Set OCxM[2, 1] + *tmpPtr |= HAL_LL_TIM_CCMR_OC2M_BIT1 | HAL_LL_TIM_CCMR_OC2M_BIT2; + } else { + // Clear CCxS, OCxM[0]. + *tmpPtr &= ~( HAL_LL_TIM_CCMR_CC3S_BIT0 | + HAL_LL_TIM_CCMR_CC3S_BIT1 | + HAL_LL_TIM_CCMR_OC3PE | + HAL_LL_TIM_CCMR_OC3M_BIT0 ); + + // Set OCxM[2, 1]. + *tmpPtr |= HAL_LL_TIM_CCMR_OC3M_BIT1 | HAL_LL_TIM_CCMR_OC3M_BIT2; + } + + // Enable counter. + set_reg_bit( &hal_ll_hw_reg->cr1, HAL_LL_TIM_ENABLE_COUNTER_BIT ); + + return HAL_LL_TIM_SUCCESS; +} + +hal_ll_err_t hal_ll_tim_stop( handle_t *handle ) { + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + // If complementary output channel is used. + if ( HAL_LL_TIM_IS_COMPLEMENTARY ) { + hal_ll_hw_reg->ccer &= 1UL << hal_ll_tim_hw_specifics_map_local->config.channel * 4 + 2; + } else { + hal_ll_hw_reg->ccer &= 1UL << hal_ll_tim_hw_specifics_map_local->config.channel * 4; + } + + return HAL_LL_TIM_SUCCESS; +} + +void hal_ll_tim_close( handle_t *handle ) { + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_tim_get_module_state_address); + + if( low_level_handle->hal_ll_tim_handle != NULL ) { + low_level_handle->hal_ll_tim_handle = NULL; + low_level_handle->hal_drv_tim_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_tim_hw_specifics_map_local->max_period = 0; + hal_ll_tim_hw_specifics_map_local->freq_hz = 0; + + _hal_ll_tim_set_clock( hal_ll_tim_hw_specifics_map_local->base, true ); + _hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_map_local, false ); + _hal_ll_tim_set_clock( hal_ll_tim_hw_specifics_map_local->base, false ); + + hal_ll_tim_hw_specifics_map_local->config.pin = HAL_LL_PIN_NC; + hal_ll_tim_hw_specifics_map_local->config.channel = HAL_LL_PIN_NC; + hal_ll_tim_hw_specifics_map_local->config.af = NULL; + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static inline void _hal_ll_tim1_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_1 ); + } else { + clear_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_1 ); + } +} + +static inline void _hal_ll_tim2_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB1ENR1, HAL_LL_TIM_ENABLE_2 ); + } else { + clear_reg_bit( _RCC_APB1ENR1, HAL_LL_TIM_ENABLE_2 ); + } +} + +static inline void _hal_ll_tim3_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB1ENR1, HAL_LL_TIM_ENABLE_3 ); + } else { + clear_reg_bit( _RCC_APB1ENR1, HAL_LL_TIM_ENABLE_3 ); + } +} + +static inline void _hal_ll_tim4_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB1ENR1, HAL_LL_TIM_ENABLE_4 ); + } else { + clear_reg_bit( _RCC_APB1ENR1, HAL_LL_TIM_ENABLE_4 ); + } +} + +static inline void _hal_ll_tim5_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB1ENR1, HAL_LL_TIM_ENABLE_5 ); + } else { + clear_reg_bit( _RCC_APB1ENR1, HAL_LL_TIM_ENABLE_5 ); + } +} + +static inline void _hal_ll_tim8_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_8 ); + } else { + clear_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_8 ); + } +} + +static inline void _hal_ll_tim15_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_15 ); + } else { + clear_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_15 ); + } +} + +static inline void _hal_ll_tim16_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_16 ); + } else { + clear_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_16 ); + } +} + +static inline void _hal_ll_tim17_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_17 ); + } else { + clear_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_17 ); + } +} + +static inline void _hal_ll_tim20_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_20 ); + } else { + clear_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_20 ); + } +} + + +static hal_ll_pin_name_t _hal_ll_tim_check_pin( hal_ll_pin_name_t pin, uint8_t *index, hal_ll_tim_handle_register_t *handle_map ) { + + hal_ll_pin_name_t pin_num; + uint8_t index_counter = 0; + uint8_t hal_ll_module_id = 0; + uint16_t map_size = ( sizeof( _tim_map ) / sizeof( hal_ll_tim_pin_map_t ) ); + + if ( HAL_LL_PIN_NC == pin ) { + return HAL_LL_PIN_NC; + } + + // Check if the selected pin is valid. + for ( pin_num = 0; pin_num < map_size; pin_num++ ) { + if ( _tim_map[ pin_num ].pin == pin ) { + // Get module number + hal_ll_module_id = _tim_map[ pin_num ].module_index; + if ( NULL == handle_map[hal_ll_module_id].hal_drv_tim_handle ) { + *index = pin_num; + return hal_ll_module_id; + } else if ( TIM_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + // By default return last error msg. + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static hal_ll_tim_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + + uint8_t hal_ll_module_count = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_tim_handle_register_t ) ); + static uint8_t hal_ll_module_error = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_tim_handle_register_t ) ); + + while( hal_ll_module_count-- ) { + if ( hal_ll_tim_get_base_from_hal_handle == hal_ll_tim_hw_specifics_map [ hal_ll_module_count ].base) { + return &hal_ll_tim_hw_specifics_map[ hal_ll_module_count ]; + } + } + + return &hal_ll_tim_hw_specifics_map[ hal_ll_module_error ]; +} + +static void _hal_ll_tim_set_clock( hal_ll_base_addr_t base, bool hal_ll_state ) { + + switch ( ( uint32_t )base ) { // 32-bit base address. + #ifdef TIM_MODULE_1 + case ( HAL_LL_TIM1_BASE_ADDR ): + _hal_ll_tim1_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_2 + case ( HAL_LL_TIM2_BASE_ADDR ): + _hal_ll_tim2_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_3 + case ( HAL_LL_TIM3_BASE_ADDR ): + _hal_ll_tim3_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_4 + case ( HAL_LL_TIM4_BASE_ADDR ): + _hal_ll_tim4_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_5 + case ( HAL_LL_TIM5_BASE_ADDR ): + _hal_ll_tim5_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_8 + case ( HAL_LL_TIM8_BASE_ADDR ): + _hal_ll_tim8_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_15 + case ( HAL_LL_TIM15_BASE_ADDR ): + _hal_ll_tim15_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_16 + case ( HAL_LL_TIM16_BASE_ADDR ): + _hal_ll_tim16_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_17 + case ( HAL_LL_TIM17_BASE_ADDR ): + _hal_ll_tim17_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_20 + case ( HAL_LL_TIM20_BASE_ADDR ): + _hal_ll_tim20_set_clock( hal_ll_state ); + break; + #endif + + } +} + +static uint32_t _hal_ll_tim_clock_source( uint8_t selector ) { + + rcc_clocks_t rcc_clocks; + + RCC_GetClocksFrequency( &rcc_clocks ); + + if( selector == HAL_LL_APB2_TIMER_CLOCK ) { + if( rcc_clocks.hclk/rcc_clocks.pclk2 > 1 ) { + return rcc_clocks.pclk2 * 2; + } else { + return rcc_clocks.pclk2; + } + } + + if( selector == HAL_LL_APB1_TIMER_CLOCK ) { + if( rcc_clocks.hclk/rcc_clocks.pclk1 > 1 ) { + return rcc_clocks.pclk1 * 2; + } else { + return rcc_clocks.pclk1; + } + } + + return 0; +} + +static uint32_t _hal_ll_tim_get_clock_speed( hal_ll_base_addr_t base ) { + + switch ( ( uint32_t )base ) { + #ifdef TIM_MODULE_1 + case ( HAL_LL_TIM1_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM1_BUS ); + break; + #endif + + #ifdef TIM_MODULE_2 + case ( HAL_LL_TIM2_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM2_BUS ); + break; + #endif + + #ifdef TIM_MODULE_3 + case ( HAL_LL_TIM3_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM3_BUS ); + break; + #endif + + #ifdef TIM_MODULE_4 + case ( HAL_LL_TIM4_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM4_BUS ); + break; + #endif + + #ifdef TIM_MODULE_5 + case ( HAL_LL_TIM5_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM5_BUS ); + break; + #endif + + #ifdef TIM_MODULE_8 + case ( HAL_LL_TIM8_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM8_BUS ); + break; + #endif + + #ifdef TIM_MODULE_15 + case ( HAL_LL_TIM15_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM15_BUS ); + break; + #endif + + #ifdef TIM_MODULE_16 + case ( HAL_LL_TIM16_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM16_BUS ); + break; + #endif + + #ifdef TIM_MODULE_17 + case ( HAL_LL_TIM17_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM17_BUS ); + break; + #endif + + #ifdef TIM_MODULE_20 + case ( HAL_LL_TIM20_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM20_BUS ); + break; + #endif + + } + return 0; +} + +static void _hal_ll_tim_map_pin( uint8_t module_index, uint8_t index ) { + + uint8_t tmp_channel; + + // Map new pin + hal_ll_tim_hw_specifics_map[ module_index ].config.pin = _tim_map[ index ].pin; + tmp_channel = _tim_map[ index ].channel; + hal_ll_tim_hw_specifics_map[ module_index ].config.af = _tim_map[ index ].af; + + if ( tmp_channel >= HAL_LL_TIM_CHANNEL_1N ) { + HAL_LL_TIM_IS_COMPLEMENTARY = true; + hal_ll_tim_hw_specifics_map[ module_index ].config.channel = tmp_channel - 4; + } else { + HAL_LL_TIM_IS_COMPLEMENTARY = false; + hal_ll_tim_hw_specifics_map[ module_index ].config.channel = tmp_channel; + } +} + +static void _hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_map_t *map, bool hal_ll_state ) { + + module_struct module; + uint32_t tim_config = 0; + + if( map->config.pin != HAL_LL_PIN_NC ) { + if( hal_ll_state == false ) { + tim_config = GPIO_CFG_MODE_ALT_FUNCTION | + GPIO_CFG_SPEED_LOW | + GPIO_CFG_OTYPE_PP; + } else { + tim_config = GPIO_CFG_MODE_ALT_FUNCTION | + GPIO_CFG_SPEED_HIGH | + GPIO_CFG_OTYPE_PP; + } + + module.pins[ 0 ] = VALUE( map->config.pin, map->config.af ); + module.pins[ 1 ] = GPIO_MODULE_STRUCT_END; + + module.configs[ 0 ] = tim_config; + module.configs[ 1 ] = GPIO_MODULE_STRUCT_END; + + hal_ll_gpio_module_struct_init( &module, hal_ll_state ); + } +} + +static void _hal_ll_tim_hw_init( hal_ll_tim_hw_specifics_map_t *map ) { + + uint32_t ck_psc; + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( map->base ); + + // Counter used as upcounter. + clear_reg_bit( &hal_ll_hw_reg->cr1, HAL_LL_TIM_CR1_DIR_BIT ); + + // Get clock speed. + ck_psc = _hal_ll_tim_get_clock_speed( map->base ) / map->freq_hz; + + // This should not be the case. ck_psc should not be greater than 65535, which is max value. + if( ck_psc > UINT16_MAX ) { + // In case of duty period beeing greater than 65535 set ck_psc to max value. + ck_psc = UINT16_MAX - 1; // Because of ( ck_psc / UINT16_MAX + 1 ) ), has to be minus 1. + }else if ( ck_psc < 1 ) { + ck_psc = 1; + } + + // Write prescale value. + hal_ll_hw_reg->psc = ( uint16_t )( ck_psc / UINT16_MAX ); + + // Write max count value. + hal_ll_hw_reg->arr = ( uint16_t )( ck_psc/( ck_psc / UINT16_MAX + 1 ) ); + + // Write max period to global array. + map->max_period = ( uint16_t )ck_psc; +} + +static void _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_t *map ) { + + _hal_ll_tim_set_clock( map->base, true ); + + _hal_ll_tim_alternate_functions_set_state( map, true ); + + _hal_ll_tim_hw_init( map ); +} +// ------------------------------------------------------------------------- END + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_85/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_85/CMakeLists.cmake new file mode 100644 index 000000000..175dbd3de --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_85/CMakeLists.cmake @@ -0,0 +1,9 @@ +if(${MCU_NAME} MATCHES "^STM32G474CB$|^STM32G474MB$|^STM32G474RB$|^STM32G474VB$|^STM32G474QB$|^STM32G474PB$|^STM32G474CC$|^STM32G474MC$|^STM32G474RC$|^STM32G474VC$|^STM32G474QC$|^STM32G474PC$|^STM32G474CE$|^STM32G474ME$|^STM32G474RE$|^STM32G474VE$|^STM32G474QE$|^STM32G474PE$") + set(tim_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_tim.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_85") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_85") + list(APPEND hal_ll_def_list "STM32G4xx") + list(APPEND hal_ll_def_list "STM32G47xx") + list(APPEND hal_ll_def_list "STM32G474xx") + set(tim_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/tim/hal_ll_tim_pin_map/implementations/doc_ds_85") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_85/hal_ll_tim.c b/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_85/hal_ll_tim.c new file mode 100644 index 000000000..877a26adb --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_85/hal_ll_tim.c @@ -0,0 +1,1011 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_tim.c + * @brief TIM HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_gpio.h" +#include "hal_ll_rcc.h" +#include "hal_ll_tim.h" +#include "hal_ll_tim_pin_map.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_tim_handle_register_t hal_ll_module_state[ TIM_MODULE_COUNT ]; + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< CR1 constants. */ +#define HAL_LL_TIM_ENABLE_COUNTER_BIT 0 +#define HAL_LL_TIM_BDTR_MOE_BIT 15 +#define HAL_LL_TIM_BDTR_MOE 0x8000 + +#define HAL_LL_TIM_CCMR_CC2S_BIT0 0x100u +#define HAL_LL_TIM_CCMR_CC2S_BIT1 0x200u +#define HAL_LL_TIM_CCMR_OC2PE 0x800u +#define HAL_LL_TIM_CCMR_OC2M_BIT0 0x1000u +#define HAL_LL_TIM_CCMR_OC2M_BIT1 0x2000u +#define HAL_LL_TIM_CCMR_OC2M_BIT2 0x4000u + +#define HAL_LL_TIM_CCMR_CC3S_BIT0 0x1u +#define HAL_LL_TIM_CCMR_CC3S_BIT1 0x2u +#define HAL_LL_TIM_CCMR_OC3PE 0x8u +#define HAL_LL_TIM_CCMR_OC3M_BIT0 0x10u +#define HAL_LL_TIM_CCMR_OC3M_BIT1 0x20u +#define HAL_LL_TIM_CCMR_OC3M_BIT2 0x40u + +#define HAL_LL_TIM_CR1_DIR 0x10 +#define HAL_LL_TIM_CR1_DIR_BIT 4 + +#define HAL_LL_TIM_ENABLE_1 11 + +#define HAL_LL_TIM_ENABLE_2 0 + +#define HAL_LL_TIM_ENABLE_3 1 + +#define HAL_LL_TIM_ENABLE_4 2 + +#define HAL_LL_TIM_ENABLE_5 3 + +#define HAL_LL_TIM_ENABLE_8 13 + +#define HAL_LL_TIM_ENABLE_15 16 + +#define HAL_LL_TIM_ENABLE_16 17 + +#define HAL_LL_TIM_ENABLE_17 18 + +#define HAL_LL_TIM_ENABLE_20 20 + + +#define HAL_LL_APB2_TIMER_CLOCK 2 + +#define HAL_LL_APB1_TIMER_CLOCK 1 + + + +#define hal_ll_tim_channel_static( _chn ) ( _chn-1 ) + +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_tim_get_base_struct(_handle) ((hal_ll_tim_base_handle_t *)_handle) + +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_tim_get_module_state_address ((hal_ll_tim_handle_register_t *)*handle) + +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_tim_get_handle ( hal_ll_tim_handle_register_t * )hal_ll_tim_get_module_state_address->hal_ll_tim_handle + +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_tim_get_base_from_hal_handle ((hal_ll_tim_hw_specifics_map_t *)((hal_ll_tim_handle_register_t *)\ + (((hal_ll_tim_handle_register_t *)(handle))->hal_ll_tim_handle))->hal_ll_tim_handle)->base + +// -------------------------------------------------------------- PRIVATE TYPES +/*!< @brief TIM register structure. */ +typedef struct +{ + uint32_t cr1; /* Address offset 0x00 */ + uint32_t cr2; /* Address offset 0x04 */ + uint32_t smcr; /* Address offset 0x08 */ + uint32_t dier; /* Address offset 0x0C */ + uint32_t sr; /* Address offset 0x10 */ + uint32_t egr; /* Address offset 0x14 */ + uint32_t ccmr1; /* Address offset 0x18 */ + uint32_t ccmr2; /* Address offset 0x1C */ + uint32_t ccer; /* Address offset 0x20 */ + uint32_t cnt; /* Address offset 0x24 */ + uint32_t psc; /* Address offset 0x28 */ + uint32_t arr; /* Address offset 0x2C */ + uint32_t rcr; /* Address offset 0x30 */ + uint32_t ccr1; /* Address offset 0x34 */ + uint32_t ccr2; /* Address offset 0x38 */ + uint32_t ccr3; /* Address offset 0x3C */ + uint32_t ccr4; /* Address offset 0x40 */ + uint32_t bdtr; /* Address offset 0x44 */ + uint32_t dcr; /* Address offset 0x48 */ + uint32_t dmar; /* Address offset 0x4C */ + uint32_t tim2_5_or; /* Address offset 0x50 */ +} hal_ll_tim_base_handle_t; + +/*!< @brief TIM pin structure */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_channel_t channel; + uint32_t af; +} hal_ll_tim_t; + +/*!< @brief TIM hw specific structure */ +typedef struct +{ + hal_ll_base_addr_t base; + hal_ll_tim_t config; + uint16_t max_period; + uint32_t freq_hz; + hal_ll_pin_name_t module_index; +} hal_ll_tim_hw_specifics_map_t; + +/*!< @brief TIM hw specific error values */ +typedef enum +{ + HAL_LL_TIM_SUCCESS = 0, + HAL_LL_TIM_MODULE_ERROR, + HAL_LL_TIM_WRONG_PIN, + + HAL_LL_TIM_ERROR = (-1) +} hal_ll_tim_err_t; + +// ------------------------------------------------------------------ VARIABLES +/*!< @brief TIM specific info */ +static hal_ll_tim_hw_specifics_map_t hal_ll_tim_hw_specifics_map[] = +{ + #ifdef TIM_MODULE_1 + {HAL_LL_TIM1_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_1 - 1}, + #endif + + #ifdef TIM_MODULE_2 + {HAL_LL_TIM2_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_2 - 1}, + #endif + + #ifdef TIM_MODULE_3 + {HAL_LL_TIM3_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_3 - 1}, + #endif + + #ifdef TIM_MODULE_4 + {HAL_LL_TIM4_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_4 - 1}, + #endif + + #ifdef TIM_MODULE_5 + {HAL_LL_TIM5_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_5 - 1}, + #endif + + #ifdef TIM_MODULE_8 + {HAL_LL_TIM8_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_8 - 1}, + #endif + + #ifdef TIM_MODULE_15 + {HAL_LL_TIM15_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_15 - 1}, + #endif + + #ifdef TIM_MODULE_16 + {HAL_LL_TIM16_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_16 - 1}, + #endif + + #ifdef TIM_MODULE_17 + {HAL_LL_TIM17_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_17 - 1}, + #endif + + #ifdef TIM_MODULE_20 + {HAL_LL_TIM20_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_20 - 1}, + #endif + + + {HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, HAL_LL_PIN_NC} +}; + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_tim_handle_register_t *low_level_handle; +static volatile hal_ll_tim_hw_specifics_map_t *hal_ll_tim_hw_specifics_map_local; + +static bool HAL_LL_TIM_IS_COMPLEMENTARY; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Enable TIM module 1 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim1_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 2 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim2_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 3 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim3_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 4 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim4_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 5 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim5_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 8 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim8_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 15 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim15_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 16 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim16_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 17 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim17_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 20 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim20_set_clock( bool hal_ll_state ); + + +/** + * @brief Enable TIM module gate clock. + * @param base - TIM module base + * address + * @return None + */ +static void _hal_ll_tim_set_clock( hal_ll_base_addr_t base, bool hal_ll_state ); + +/** + * @brief Select TIM clock source + * @param selector - clock source selector + * @return uint32_t - clock source + */ +static uint32_t _hal_ll_tim_clock_source( uint8_t selector ); + +/** + * @brief Based on selected TIM, + * return clock speed. + * @param base - TIM module base + * address + * @return uint32_t clock source. + */ +static uint32_t _hal_ll_tim_get_clock_speed( hal_ll_base_addr_t base ); + +/** + * @brief Initialize TIM module on hardware level. + * + * Initializes TIM module on hardware level, based on beforehand + * set configuration and module handler. + * + * @param map - Object specific context handler. + * @return none + * + */ +static void _hal_ll_tim_hw_init( hal_ll_tim_hw_specifics_map_t *map ); + +/** + * @brief Full TIM module initialization procedure. + * + * Initializes TIM module on hardware level, based on beforehand + * set configuration and module handler. Sets adequate pin alternate functions. + * Initializes module clock. + * + * @param map - Object specific context handler. + * @return none + * + */ +static void _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_t *map ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_tim_hw_specifics_map array index. + * + * @param handle - Object specific context handler. + * @return hal_ll_tim_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_tim_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Check if pin is adequate. + * + * Checks tim pin the user has passed with pre-defined + * pin in tim map. + * + * @param pin - TIM pre-defined pin name. + * @return hal_ll_pin_name_t Module index based on pin. + * + * Returns pre-defined module index from pin maps, if pin + * is adequate. + */ +static hal_ll_pin_name_t _hal_ll_tim_check_pin( hal_ll_pin_name_t pin, uint8_t *index, hal_ll_tim_handle_register_t *handle_map ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * TIM pin. + * + * @param[in] module_index TIM HW module index -- 0,1,2... + * @param[in] *index_list Array with TIM map index values + * + * @return None + */ +static void _hal_ll_tim_map_pin( uint8_t module_index, uint8_t index ); + +/** + * @brief Sets TIM pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if TIM is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param map - Object specific context handler. + * + * @param hal_ll_state - Init/De-init + * @return none + * + */ +static void _hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_map_t *map, bool hal_ll_state ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_tim_register_handle( hal_ll_pin_name_t pin, hal_ll_tim_handle_register_t *handle_map, + uint8_t *hal_module_id ) { + + uint8_t index; + uint16_t pin_check_result; + + if ( ( pin_check_result = _hal_ll_tim_check_pin( pin, &index, handle_map ) ) == HAL_LL_PIN_NC ) { + return HAL_LL_TIM_WRONG_PIN; + } + + if ( hal_ll_tim_hw_specifics_map[ pin_check_result ].config.pin != pin ){ + // Clear previous module alternate functions + _hal_ll_tim_alternate_functions_set_state( &hal_ll_tim_hw_specifics_map[ pin_check_result ], false ); + + _hal_ll_tim_map_pin( pin_check_result, index ); + + _hal_ll_tim_alternate_functions_set_state( &hal_ll_tim_hw_specifics_map[ pin_check_result ], true ); + + handle_map[ pin_check_result ].init_ll_state = false; + + hal_ll_module_state[ pin_check_result ].init_ll_state = false; + + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle = ( handle_t * )&hal_ll_tim_hw_specifics_map[ pin_check_result ].base; + + handle_map[ pin_check_result ].hal_ll_tim_handle = ( handle_t *)&hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle; + + return HAL_LL_TIM_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_tim( handle_t *handle ) { + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + hal_ll_tim_handle_register_t *hal_handle = (hal_ll_tim_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_tim_hw_specifics_map_local->module_index; + + _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_local ); + + hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle = (handle_t *)&hal_ll_tim_hw_specifics_map[ pin_check_result ].base; + hal_ll_module_state[ pin_check_result ].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_TIM_SUCCESS; +} + +uint32_t hal_ll_tim_set_freq( handle_t *handle, uint32_t freq_hz ) { + + uint32_t tmp_channel; + uint32_t ck_psc; + uint32_t local_base_addr; + uint32_t local_freq; + uint32_t tmp_freq; + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + if( hal_ll_tim_hw_specifics_map_local->base == HAL_LL_MODULE_ERROR ) { + return HAL_LL_TIM_MODULE_ERROR; + } + + low_level_handle->init_ll_state = false; + + tmp_channel = hal_ll_tim_hw_specifics_map_local->config.channel; + + // If complementary output channel is used. + if ( HAL_LL_TIM_IS_COMPLEMENTARY ) { + // Stop capture/compare. + hal_ll_hw_reg->ccer &= 1UL << tmp_channel * 4 + 2; + } else { + // Stop capture/compare. + hal_ll_hw_reg->ccer &= 1UL << tmp_channel * 4; + } + + // Set TIM duty to 0. + *( &hal_ll_hw_reg->ccr1 + hal_ll_tim_channel_static( tmp_channel ) ) = 0; + + hal_ll_tim_hw_specifics_map_local->freq_hz = freq_hz; + + local_freq = hal_ll_tim_hw_specifics_map_local->freq_hz; + local_base_addr = hal_ll_tim_hw_specifics_map_local->base; + + ck_psc = _hal_ll_tim_get_clock_speed( local_base_addr ) / local_freq; + + if ( ck_psc > UINT16_MAX ) { + tmp_freq = _hal_ll_tim_get_clock_speed( local_base_addr ) / UINT16_MAX; + hal_ll_tim_hw_specifics_map_local->freq_hz = tmp_freq; + } else { + tmp_freq = freq_hz; + hal_ll_tim_hw_specifics_map_local->freq_hz = freq_hz; + } + + _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_local ); + + low_level_handle->init_ll_state = true; + + return tmp_freq; +} + +hal_ll_err_t hal_ll_tim_set_duty( handle_t *handle, float duty_ratio ) { + + float tmp_duty; + uint32_t max_duty = 0; + uint16_t max_period; + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + if ( low_level_handle->init_ll_state == false ) { + hal_ll_tim_start( handle ); + low_level_handle->init_ll_state = true; + } + + tmp_duty = duty_ratio * 100; + max_period = hal_ll_tim_hw_specifics_map_local->max_period; + + max_duty = ( ( float )max_period / 100 ) * tmp_duty; + + *( &hal_ll_hw_reg->ccr1 + hal_ll_tim_channel_static( hal_ll_tim_hw_specifics_map_local->config.channel ) ) = max_duty; + + return HAL_LL_TIM_SUCCESS; +} + +hal_ll_err_t hal_ll_tim_start( handle_t *handle ) { + + uint32_t tmp_channel; + volatile uint32_t tmp, + *tmpPtr; + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + tmp_channel = hal_ll_tim_hw_specifics_map_local->config.channel; + + // Capture/Compare 1 output enable. + tmp = hal_ll_hw_reg->ccer; + + // If complementary output channel is used. + if ( HAL_LL_TIM_IS_COMPLEMENTARY ) { + // Capture/Compare complementary output enable + tmp |= ( 1UL << ( hal_ll_tim_channel_static( tmp_channel ) * 4 + 2 ) ); + // Capture/Compare complementary output polarity(ACTIVE HIGH). + tmp &= ~( 1UL << ( hal_ll_tim_channel_static( tmp_channel ) * 4 + 3 ) ); + } else { + // Capture/Compare output polarity. + tmp |= ( 1UL << ( hal_ll_tim_channel_static( tmp_channel ) * 4 ) ); + // Capture/Compare output polarity(ACTIVE HIGH). + tmp &= ~( 1UL << ( hal_ll_tim_channel_static( tmp_channel ) * 4 + 1 ) ); + } + + hal_ll_hw_reg->ccer = tmp; + + #if defined(TIM_MODULE_1) || defined(TIM_MODULE_8) || defined(TIM_MODULE_20) + // Main output enabled. + set_reg_bit( &hal_ll_hw_reg->bdtr, HAL_LL_TIM_BDTR_MOE_BIT ); + #endif + + tmpPtr = &hal_ll_hw_reg->ccmr1; + + if( hal_ll_tim_channel_static( tmp_channel ) > 1 ) { + tmpPtr = &hal_ll_hw_reg->ccmr2; + } + + if( ( hal_ll_tim_channel_static( tmp_channel ) / 2 ) * 2 != + hal_ll_tim_channel_static( tmp_channel ) ) { + // Clear CCxS, OCxM[0]. + *tmpPtr &= ~( HAL_LL_TIM_CCMR_CC2S_BIT0 | + HAL_LL_TIM_CCMR_CC2S_BIT1 | + HAL_LL_TIM_CCMR_OC2PE | + HAL_LL_TIM_CCMR_OC2M_BIT0 ); + // Set OCxM[2, 1] + *tmpPtr |= HAL_LL_TIM_CCMR_OC2M_BIT1 | HAL_LL_TIM_CCMR_OC2M_BIT2; + } else { + // Clear CCxS, OCxM[0]. + *tmpPtr &= ~( HAL_LL_TIM_CCMR_CC3S_BIT0 | + HAL_LL_TIM_CCMR_CC3S_BIT1 | + HAL_LL_TIM_CCMR_OC3PE | + HAL_LL_TIM_CCMR_OC3M_BIT0 ); + + // Set OCxM[2, 1]. + *tmpPtr |= HAL_LL_TIM_CCMR_OC3M_BIT1 | HAL_LL_TIM_CCMR_OC3M_BIT2; + } + + // Enable counter. + set_reg_bit( &hal_ll_hw_reg->cr1, HAL_LL_TIM_ENABLE_COUNTER_BIT ); + + return HAL_LL_TIM_SUCCESS; +} + +hal_ll_err_t hal_ll_tim_stop( handle_t *handle ) { + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + // If complementary output channel is used. + if ( HAL_LL_TIM_IS_COMPLEMENTARY ) { + hal_ll_hw_reg->ccer &= 1UL << hal_ll_tim_hw_specifics_map_local->config.channel * 4 + 2; + } else { + hal_ll_hw_reg->ccer &= 1UL << hal_ll_tim_hw_specifics_map_local->config.channel * 4; + } + + return HAL_LL_TIM_SUCCESS; +} + +void hal_ll_tim_close( handle_t *handle ) { + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_tim_get_module_state_address); + + if( low_level_handle->hal_ll_tim_handle != NULL ) { + low_level_handle->hal_ll_tim_handle = NULL; + low_level_handle->hal_drv_tim_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_tim_hw_specifics_map_local->max_period = 0; + hal_ll_tim_hw_specifics_map_local->freq_hz = 0; + + _hal_ll_tim_set_clock( hal_ll_tim_hw_specifics_map_local->base, true ); + _hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_map_local, false ); + _hal_ll_tim_set_clock( hal_ll_tim_hw_specifics_map_local->base, false ); + + hal_ll_tim_hw_specifics_map_local->config.pin = HAL_LL_PIN_NC; + hal_ll_tim_hw_specifics_map_local->config.channel = HAL_LL_PIN_NC; + hal_ll_tim_hw_specifics_map_local->config.af = NULL; + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static inline void _hal_ll_tim1_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_1 ); + } else { + clear_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_1 ); + } +} + +static inline void _hal_ll_tim2_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB1ENR1, HAL_LL_TIM_ENABLE_2 ); + } else { + clear_reg_bit( _RCC_APB1ENR1, HAL_LL_TIM_ENABLE_2 ); + } +} + +static inline void _hal_ll_tim3_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB1ENR1, HAL_LL_TIM_ENABLE_3 ); + } else { + clear_reg_bit( _RCC_APB1ENR1, HAL_LL_TIM_ENABLE_3 ); + } +} + +static inline void _hal_ll_tim4_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB1ENR1, HAL_LL_TIM_ENABLE_4 ); + } else { + clear_reg_bit( _RCC_APB1ENR1, HAL_LL_TIM_ENABLE_4 ); + } +} + +static inline void _hal_ll_tim5_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB1ENR1, HAL_LL_TIM_ENABLE_5 ); + } else { + clear_reg_bit( _RCC_APB1ENR1, HAL_LL_TIM_ENABLE_5 ); + } +} + +static inline void _hal_ll_tim8_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_8 ); + } else { + clear_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_8 ); + } +} + +static inline void _hal_ll_tim15_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_15 ); + } else { + clear_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_15 ); + } +} + +static inline void _hal_ll_tim16_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_16 ); + } else { + clear_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_16 ); + } +} + +static inline void _hal_ll_tim17_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_17 ); + } else { + clear_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_17 ); + } +} + +static inline void _hal_ll_tim20_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_20 ); + } else { + clear_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_20 ); + } +} + + +static hal_ll_pin_name_t _hal_ll_tim_check_pin( hal_ll_pin_name_t pin, uint8_t *index, hal_ll_tim_handle_register_t *handle_map ) { + + hal_ll_pin_name_t pin_num; + uint8_t index_counter = 0; + uint8_t hal_ll_module_id = 0; + uint16_t map_size = ( sizeof( _tim_map ) / sizeof( hal_ll_tim_pin_map_t ) ); + + if ( HAL_LL_PIN_NC == pin ) { + return HAL_LL_PIN_NC; + } + + // Check if the selected pin is valid. + for ( pin_num = 0; pin_num < map_size; pin_num++ ) { + if ( _tim_map[ pin_num ].pin == pin ) { + // Get module number + hal_ll_module_id = _tim_map[ pin_num ].module_index; + if ( NULL == handle_map[hal_ll_module_id].hal_drv_tim_handle ) { + *index = pin_num; + return hal_ll_module_id; + } else if ( TIM_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + // By default return last error msg. + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static hal_ll_tim_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + + uint8_t hal_ll_module_count = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_tim_handle_register_t ) ); + static uint8_t hal_ll_module_error = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_tim_handle_register_t ) ); + + while( hal_ll_module_count-- ) { + if ( hal_ll_tim_get_base_from_hal_handle == hal_ll_tim_hw_specifics_map [ hal_ll_module_count ].base) { + return &hal_ll_tim_hw_specifics_map[ hal_ll_module_count ]; + } + } + + return &hal_ll_tim_hw_specifics_map[ hal_ll_module_error ]; +} + +static void _hal_ll_tim_set_clock( hal_ll_base_addr_t base, bool hal_ll_state ) { + + switch ( ( uint32_t )base ) { // 32-bit base address. + #ifdef TIM_MODULE_1 + case ( HAL_LL_TIM1_BASE_ADDR ): + _hal_ll_tim1_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_2 + case ( HAL_LL_TIM2_BASE_ADDR ): + _hal_ll_tim2_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_3 + case ( HAL_LL_TIM3_BASE_ADDR ): + _hal_ll_tim3_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_4 + case ( HAL_LL_TIM4_BASE_ADDR ): + _hal_ll_tim4_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_5 + case ( HAL_LL_TIM5_BASE_ADDR ): + _hal_ll_tim5_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_8 + case ( HAL_LL_TIM8_BASE_ADDR ): + _hal_ll_tim8_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_15 + case ( HAL_LL_TIM15_BASE_ADDR ): + _hal_ll_tim15_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_16 + case ( HAL_LL_TIM16_BASE_ADDR ): + _hal_ll_tim16_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_17 + case ( HAL_LL_TIM17_BASE_ADDR ): + _hal_ll_tim17_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_20 + case ( HAL_LL_TIM20_BASE_ADDR ): + _hal_ll_tim20_set_clock( hal_ll_state ); + break; + #endif + + } +} + +static uint32_t _hal_ll_tim_clock_source( uint8_t selector ) { + + rcc_clocks_t rcc_clocks; + + RCC_GetClocksFrequency( &rcc_clocks ); + + if( selector == HAL_LL_APB2_TIMER_CLOCK ) { + if( rcc_clocks.hclk/rcc_clocks.pclk2 > 1 ) { + return rcc_clocks.pclk2 * 2; + } else { + return rcc_clocks.pclk2; + } + } + + if( selector == HAL_LL_APB1_TIMER_CLOCK ) { + if( rcc_clocks.hclk/rcc_clocks.pclk1 > 1 ) { + return rcc_clocks.pclk1 * 2; + } else { + return rcc_clocks.pclk1; + } + } + + return 0; +} + +static uint32_t _hal_ll_tim_get_clock_speed( hal_ll_base_addr_t base ) { + + switch ( ( uint32_t )base ) { + #ifdef TIM_MODULE_1 + case ( HAL_LL_TIM1_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM1_BUS ); + break; + #endif + + #ifdef TIM_MODULE_2 + case ( HAL_LL_TIM2_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM2_BUS ); + break; + #endif + + #ifdef TIM_MODULE_3 + case ( HAL_LL_TIM3_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM3_BUS ); + break; + #endif + + #ifdef TIM_MODULE_4 + case ( HAL_LL_TIM4_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM4_BUS ); + break; + #endif + + #ifdef TIM_MODULE_5 + case ( HAL_LL_TIM5_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM5_BUS ); + break; + #endif + + #ifdef TIM_MODULE_8 + case ( HAL_LL_TIM8_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM8_BUS ); + break; + #endif + + #ifdef TIM_MODULE_15 + case ( HAL_LL_TIM15_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM15_BUS ); + break; + #endif + + #ifdef TIM_MODULE_16 + case ( HAL_LL_TIM16_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM16_BUS ); + break; + #endif + + #ifdef TIM_MODULE_17 + case ( HAL_LL_TIM17_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM17_BUS ); + break; + #endif + + #ifdef TIM_MODULE_20 + case ( HAL_LL_TIM20_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM20_BUS ); + break; + #endif + + } + return 0; +} + +static void _hal_ll_tim_map_pin( uint8_t module_index, uint8_t index ) { + + uint8_t tmp_channel; + + // Map new pin + hal_ll_tim_hw_specifics_map[ module_index ].config.pin = _tim_map[ index ].pin; + tmp_channel = _tim_map[ index ].channel; + hal_ll_tim_hw_specifics_map[ module_index ].config.af = _tim_map[ index ].af; + + if ( tmp_channel >= HAL_LL_TIM_CHANNEL_1N ) { + HAL_LL_TIM_IS_COMPLEMENTARY = true; + hal_ll_tim_hw_specifics_map[ module_index ].config.channel = tmp_channel - 4; + } else { + HAL_LL_TIM_IS_COMPLEMENTARY = false; + hal_ll_tim_hw_specifics_map[ module_index ].config.channel = tmp_channel; + } +} + +static void _hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_map_t *map, bool hal_ll_state ) { + + module_struct module; + uint32_t tim_config = 0; + + if( map->config.pin != HAL_LL_PIN_NC ) { + if( hal_ll_state == false ) { + tim_config = GPIO_CFG_MODE_ALT_FUNCTION | + GPIO_CFG_SPEED_LOW | + GPIO_CFG_OTYPE_PP; + } else { + tim_config = GPIO_CFG_MODE_ALT_FUNCTION | + GPIO_CFG_SPEED_HIGH | + GPIO_CFG_OTYPE_PP; + } + + module.pins[ 0 ] = VALUE( map->config.pin, map->config.af ); + module.pins[ 1 ] = GPIO_MODULE_STRUCT_END; + + module.configs[ 0 ] = tim_config; + module.configs[ 1 ] = GPIO_MODULE_STRUCT_END; + + hal_ll_gpio_module_struct_init( &module, hal_ll_state ); + } +} + +static void _hal_ll_tim_hw_init( hal_ll_tim_hw_specifics_map_t *map ) { + + uint32_t ck_psc; + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( map->base ); + + // Counter used as upcounter. + clear_reg_bit( &hal_ll_hw_reg->cr1, HAL_LL_TIM_CR1_DIR_BIT ); + + // Get clock speed. + ck_psc = _hal_ll_tim_get_clock_speed( map->base ) / map->freq_hz; + + // This should not be the case. ck_psc should not be greater than 65535, which is max value. + if( ck_psc > UINT16_MAX ) { + // In case of duty period beeing greater than 65535 set ck_psc to max value. + ck_psc = UINT16_MAX - 1; // Because of ( ck_psc / UINT16_MAX + 1 ) ), has to be minus 1. + }else if ( ck_psc < 1 ) { + ck_psc = 1; + } + + // Write prescale value. + hal_ll_hw_reg->psc = ( uint16_t )( ck_psc / UINT16_MAX ); + + // Write max count value. + hal_ll_hw_reg->arr = ( uint16_t )( ck_psc/( ck_psc / UINT16_MAX + 1 ) ); + + // Write max period to global array. + map->max_period = ( uint16_t )ck_psc; +} + +static void _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_t *map ) { + + _hal_ll_tim_set_clock( map->base, true ); + + _hal_ll_tim_alternate_functions_set_state( map, true ); + + _hal_ll_tim_hw_init( map ); +} +// ------------------------------------------------------------------------- END + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_86/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_86/CMakeLists.cmake new file mode 100644 index 000000000..f067faea2 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_86/CMakeLists.cmake @@ -0,0 +1,9 @@ +if(${MCU_NAME} MATCHES "^STM32G483CE$|^STM32G483RE$|^STM32G483ME$|^STM32G483PE$|^STM32G483VE$|^STM32G483QE$") + set(tim_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_tim.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_86") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_86") + list(APPEND hal_ll_def_list "STM32G4xx") + list(APPEND hal_ll_def_list "STM32G48xx") + list(APPEND hal_ll_def_list "STM32G483xx") + set(tim_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/tim/hal_ll_tim_pin_map/implementations/doc_ds_86") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_86/hal_ll_tim.c b/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_86/hal_ll_tim.c new file mode 100644 index 000000000..877a26adb --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_86/hal_ll_tim.c @@ -0,0 +1,1011 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_tim.c + * @brief TIM HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_gpio.h" +#include "hal_ll_rcc.h" +#include "hal_ll_tim.h" +#include "hal_ll_tim_pin_map.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_tim_handle_register_t hal_ll_module_state[ TIM_MODULE_COUNT ]; + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< CR1 constants. */ +#define HAL_LL_TIM_ENABLE_COUNTER_BIT 0 +#define HAL_LL_TIM_BDTR_MOE_BIT 15 +#define HAL_LL_TIM_BDTR_MOE 0x8000 + +#define HAL_LL_TIM_CCMR_CC2S_BIT0 0x100u +#define HAL_LL_TIM_CCMR_CC2S_BIT1 0x200u +#define HAL_LL_TIM_CCMR_OC2PE 0x800u +#define HAL_LL_TIM_CCMR_OC2M_BIT0 0x1000u +#define HAL_LL_TIM_CCMR_OC2M_BIT1 0x2000u +#define HAL_LL_TIM_CCMR_OC2M_BIT2 0x4000u + +#define HAL_LL_TIM_CCMR_CC3S_BIT0 0x1u +#define HAL_LL_TIM_CCMR_CC3S_BIT1 0x2u +#define HAL_LL_TIM_CCMR_OC3PE 0x8u +#define HAL_LL_TIM_CCMR_OC3M_BIT0 0x10u +#define HAL_LL_TIM_CCMR_OC3M_BIT1 0x20u +#define HAL_LL_TIM_CCMR_OC3M_BIT2 0x40u + +#define HAL_LL_TIM_CR1_DIR 0x10 +#define HAL_LL_TIM_CR1_DIR_BIT 4 + +#define HAL_LL_TIM_ENABLE_1 11 + +#define HAL_LL_TIM_ENABLE_2 0 + +#define HAL_LL_TIM_ENABLE_3 1 + +#define HAL_LL_TIM_ENABLE_4 2 + +#define HAL_LL_TIM_ENABLE_5 3 + +#define HAL_LL_TIM_ENABLE_8 13 + +#define HAL_LL_TIM_ENABLE_15 16 + +#define HAL_LL_TIM_ENABLE_16 17 + +#define HAL_LL_TIM_ENABLE_17 18 + +#define HAL_LL_TIM_ENABLE_20 20 + + +#define HAL_LL_APB2_TIMER_CLOCK 2 + +#define HAL_LL_APB1_TIMER_CLOCK 1 + + + +#define hal_ll_tim_channel_static( _chn ) ( _chn-1 ) + +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_tim_get_base_struct(_handle) ((hal_ll_tim_base_handle_t *)_handle) + +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_tim_get_module_state_address ((hal_ll_tim_handle_register_t *)*handle) + +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_tim_get_handle ( hal_ll_tim_handle_register_t * )hal_ll_tim_get_module_state_address->hal_ll_tim_handle + +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_tim_get_base_from_hal_handle ((hal_ll_tim_hw_specifics_map_t *)((hal_ll_tim_handle_register_t *)\ + (((hal_ll_tim_handle_register_t *)(handle))->hal_ll_tim_handle))->hal_ll_tim_handle)->base + +// -------------------------------------------------------------- PRIVATE TYPES +/*!< @brief TIM register structure. */ +typedef struct +{ + uint32_t cr1; /* Address offset 0x00 */ + uint32_t cr2; /* Address offset 0x04 */ + uint32_t smcr; /* Address offset 0x08 */ + uint32_t dier; /* Address offset 0x0C */ + uint32_t sr; /* Address offset 0x10 */ + uint32_t egr; /* Address offset 0x14 */ + uint32_t ccmr1; /* Address offset 0x18 */ + uint32_t ccmr2; /* Address offset 0x1C */ + uint32_t ccer; /* Address offset 0x20 */ + uint32_t cnt; /* Address offset 0x24 */ + uint32_t psc; /* Address offset 0x28 */ + uint32_t arr; /* Address offset 0x2C */ + uint32_t rcr; /* Address offset 0x30 */ + uint32_t ccr1; /* Address offset 0x34 */ + uint32_t ccr2; /* Address offset 0x38 */ + uint32_t ccr3; /* Address offset 0x3C */ + uint32_t ccr4; /* Address offset 0x40 */ + uint32_t bdtr; /* Address offset 0x44 */ + uint32_t dcr; /* Address offset 0x48 */ + uint32_t dmar; /* Address offset 0x4C */ + uint32_t tim2_5_or; /* Address offset 0x50 */ +} hal_ll_tim_base_handle_t; + +/*!< @brief TIM pin structure */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_channel_t channel; + uint32_t af; +} hal_ll_tim_t; + +/*!< @brief TIM hw specific structure */ +typedef struct +{ + hal_ll_base_addr_t base; + hal_ll_tim_t config; + uint16_t max_period; + uint32_t freq_hz; + hal_ll_pin_name_t module_index; +} hal_ll_tim_hw_specifics_map_t; + +/*!< @brief TIM hw specific error values */ +typedef enum +{ + HAL_LL_TIM_SUCCESS = 0, + HAL_LL_TIM_MODULE_ERROR, + HAL_LL_TIM_WRONG_PIN, + + HAL_LL_TIM_ERROR = (-1) +} hal_ll_tim_err_t; + +// ------------------------------------------------------------------ VARIABLES +/*!< @brief TIM specific info */ +static hal_ll_tim_hw_specifics_map_t hal_ll_tim_hw_specifics_map[] = +{ + #ifdef TIM_MODULE_1 + {HAL_LL_TIM1_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_1 - 1}, + #endif + + #ifdef TIM_MODULE_2 + {HAL_LL_TIM2_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_2 - 1}, + #endif + + #ifdef TIM_MODULE_3 + {HAL_LL_TIM3_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_3 - 1}, + #endif + + #ifdef TIM_MODULE_4 + {HAL_LL_TIM4_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_4 - 1}, + #endif + + #ifdef TIM_MODULE_5 + {HAL_LL_TIM5_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_5 - 1}, + #endif + + #ifdef TIM_MODULE_8 + {HAL_LL_TIM8_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_8 - 1}, + #endif + + #ifdef TIM_MODULE_15 + {HAL_LL_TIM15_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_15 - 1}, + #endif + + #ifdef TIM_MODULE_16 + {HAL_LL_TIM16_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_16 - 1}, + #endif + + #ifdef TIM_MODULE_17 + {HAL_LL_TIM17_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_17 - 1}, + #endif + + #ifdef TIM_MODULE_20 + {HAL_LL_TIM20_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_20 - 1}, + #endif + + + {HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, HAL_LL_PIN_NC} +}; + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_tim_handle_register_t *low_level_handle; +static volatile hal_ll_tim_hw_specifics_map_t *hal_ll_tim_hw_specifics_map_local; + +static bool HAL_LL_TIM_IS_COMPLEMENTARY; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Enable TIM module 1 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim1_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 2 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim2_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 3 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim3_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 4 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim4_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 5 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim5_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 8 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim8_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 15 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim15_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 16 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim16_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 17 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim17_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 20 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim20_set_clock( bool hal_ll_state ); + + +/** + * @brief Enable TIM module gate clock. + * @param base - TIM module base + * address + * @return None + */ +static void _hal_ll_tim_set_clock( hal_ll_base_addr_t base, bool hal_ll_state ); + +/** + * @brief Select TIM clock source + * @param selector - clock source selector + * @return uint32_t - clock source + */ +static uint32_t _hal_ll_tim_clock_source( uint8_t selector ); + +/** + * @brief Based on selected TIM, + * return clock speed. + * @param base - TIM module base + * address + * @return uint32_t clock source. + */ +static uint32_t _hal_ll_tim_get_clock_speed( hal_ll_base_addr_t base ); + +/** + * @brief Initialize TIM module on hardware level. + * + * Initializes TIM module on hardware level, based on beforehand + * set configuration and module handler. + * + * @param map - Object specific context handler. + * @return none + * + */ +static void _hal_ll_tim_hw_init( hal_ll_tim_hw_specifics_map_t *map ); + +/** + * @brief Full TIM module initialization procedure. + * + * Initializes TIM module on hardware level, based on beforehand + * set configuration and module handler. Sets adequate pin alternate functions. + * Initializes module clock. + * + * @param map - Object specific context handler. + * @return none + * + */ +static void _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_t *map ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_tim_hw_specifics_map array index. + * + * @param handle - Object specific context handler. + * @return hal_ll_tim_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_tim_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Check if pin is adequate. + * + * Checks tim pin the user has passed with pre-defined + * pin in tim map. + * + * @param pin - TIM pre-defined pin name. + * @return hal_ll_pin_name_t Module index based on pin. + * + * Returns pre-defined module index from pin maps, if pin + * is adequate. + */ +static hal_ll_pin_name_t _hal_ll_tim_check_pin( hal_ll_pin_name_t pin, uint8_t *index, hal_ll_tim_handle_register_t *handle_map ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * TIM pin. + * + * @param[in] module_index TIM HW module index -- 0,1,2... + * @param[in] *index_list Array with TIM map index values + * + * @return None + */ +static void _hal_ll_tim_map_pin( uint8_t module_index, uint8_t index ); + +/** + * @brief Sets TIM pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if TIM is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param map - Object specific context handler. + * + * @param hal_ll_state - Init/De-init + * @return none + * + */ +static void _hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_map_t *map, bool hal_ll_state ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_tim_register_handle( hal_ll_pin_name_t pin, hal_ll_tim_handle_register_t *handle_map, + uint8_t *hal_module_id ) { + + uint8_t index; + uint16_t pin_check_result; + + if ( ( pin_check_result = _hal_ll_tim_check_pin( pin, &index, handle_map ) ) == HAL_LL_PIN_NC ) { + return HAL_LL_TIM_WRONG_PIN; + } + + if ( hal_ll_tim_hw_specifics_map[ pin_check_result ].config.pin != pin ){ + // Clear previous module alternate functions + _hal_ll_tim_alternate_functions_set_state( &hal_ll_tim_hw_specifics_map[ pin_check_result ], false ); + + _hal_ll_tim_map_pin( pin_check_result, index ); + + _hal_ll_tim_alternate_functions_set_state( &hal_ll_tim_hw_specifics_map[ pin_check_result ], true ); + + handle_map[ pin_check_result ].init_ll_state = false; + + hal_ll_module_state[ pin_check_result ].init_ll_state = false; + + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle = ( handle_t * )&hal_ll_tim_hw_specifics_map[ pin_check_result ].base; + + handle_map[ pin_check_result ].hal_ll_tim_handle = ( handle_t *)&hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle; + + return HAL_LL_TIM_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_tim( handle_t *handle ) { + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + hal_ll_tim_handle_register_t *hal_handle = (hal_ll_tim_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_tim_hw_specifics_map_local->module_index; + + _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_local ); + + hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle = (handle_t *)&hal_ll_tim_hw_specifics_map[ pin_check_result ].base; + hal_ll_module_state[ pin_check_result ].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_TIM_SUCCESS; +} + +uint32_t hal_ll_tim_set_freq( handle_t *handle, uint32_t freq_hz ) { + + uint32_t tmp_channel; + uint32_t ck_psc; + uint32_t local_base_addr; + uint32_t local_freq; + uint32_t tmp_freq; + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + if( hal_ll_tim_hw_specifics_map_local->base == HAL_LL_MODULE_ERROR ) { + return HAL_LL_TIM_MODULE_ERROR; + } + + low_level_handle->init_ll_state = false; + + tmp_channel = hal_ll_tim_hw_specifics_map_local->config.channel; + + // If complementary output channel is used. + if ( HAL_LL_TIM_IS_COMPLEMENTARY ) { + // Stop capture/compare. + hal_ll_hw_reg->ccer &= 1UL << tmp_channel * 4 + 2; + } else { + // Stop capture/compare. + hal_ll_hw_reg->ccer &= 1UL << tmp_channel * 4; + } + + // Set TIM duty to 0. + *( &hal_ll_hw_reg->ccr1 + hal_ll_tim_channel_static( tmp_channel ) ) = 0; + + hal_ll_tim_hw_specifics_map_local->freq_hz = freq_hz; + + local_freq = hal_ll_tim_hw_specifics_map_local->freq_hz; + local_base_addr = hal_ll_tim_hw_specifics_map_local->base; + + ck_psc = _hal_ll_tim_get_clock_speed( local_base_addr ) / local_freq; + + if ( ck_psc > UINT16_MAX ) { + tmp_freq = _hal_ll_tim_get_clock_speed( local_base_addr ) / UINT16_MAX; + hal_ll_tim_hw_specifics_map_local->freq_hz = tmp_freq; + } else { + tmp_freq = freq_hz; + hal_ll_tim_hw_specifics_map_local->freq_hz = freq_hz; + } + + _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_local ); + + low_level_handle->init_ll_state = true; + + return tmp_freq; +} + +hal_ll_err_t hal_ll_tim_set_duty( handle_t *handle, float duty_ratio ) { + + float tmp_duty; + uint32_t max_duty = 0; + uint16_t max_period; + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + if ( low_level_handle->init_ll_state == false ) { + hal_ll_tim_start( handle ); + low_level_handle->init_ll_state = true; + } + + tmp_duty = duty_ratio * 100; + max_period = hal_ll_tim_hw_specifics_map_local->max_period; + + max_duty = ( ( float )max_period / 100 ) * tmp_duty; + + *( &hal_ll_hw_reg->ccr1 + hal_ll_tim_channel_static( hal_ll_tim_hw_specifics_map_local->config.channel ) ) = max_duty; + + return HAL_LL_TIM_SUCCESS; +} + +hal_ll_err_t hal_ll_tim_start( handle_t *handle ) { + + uint32_t tmp_channel; + volatile uint32_t tmp, + *tmpPtr; + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + tmp_channel = hal_ll_tim_hw_specifics_map_local->config.channel; + + // Capture/Compare 1 output enable. + tmp = hal_ll_hw_reg->ccer; + + // If complementary output channel is used. + if ( HAL_LL_TIM_IS_COMPLEMENTARY ) { + // Capture/Compare complementary output enable + tmp |= ( 1UL << ( hal_ll_tim_channel_static( tmp_channel ) * 4 + 2 ) ); + // Capture/Compare complementary output polarity(ACTIVE HIGH). + tmp &= ~( 1UL << ( hal_ll_tim_channel_static( tmp_channel ) * 4 + 3 ) ); + } else { + // Capture/Compare output polarity. + tmp |= ( 1UL << ( hal_ll_tim_channel_static( tmp_channel ) * 4 ) ); + // Capture/Compare output polarity(ACTIVE HIGH). + tmp &= ~( 1UL << ( hal_ll_tim_channel_static( tmp_channel ) * 4 + 1 ) ); + } + + hal_ll_hw_reg->ccer = tmp; + + #if defined(TIM_MODULE_1) || defined(TIM_MODULE_8) || defined(TIM_MODULE_20) + // Main output enabled. + set_reg_bit( &hal_ll_hw_reg->bdtr, HAL_LL_TIM_BDTR_MOE_BIT ); + #endif + + tmpPtr = &hal_ll_hw_reg->ccmr1; + + if( hal_ll_tim_channel_static( tmp_channel ) > 1 ) { + tmpPtr = &hal_ll_hw_reg->ccmr2; + } + + if( ( hal_ll_tim_channel_static( tmp_channel ) / 2 ) * 2 != + hal_ll_tim_channel_static( tmp_channel ) ) { + // Clear CCxS, OCxM[0]. + *tmpPtr &= ~( HAL_LL_TIM_CCMR_CC2S_BIT0 | + HAL_LL_TIM_CCMR_CC2S_BIT1 | + HAL_LL_TIM_CCMR_OC2PE | + HAL_LL_TIM_CCMR_OC2M_BIT0 ); + // Set OCxM[2, 1] + *tmpPtr |= HAL_LL_TIM_CCMR_OC2M_BIT1 | HAL_LL_TIM_CCMR_OC2M_BIT2; + } else { + // Clear CCxS, OCxM[0]. + *tmpPtr &= ~( HAL_LL_TIM_CCMR_CC3S_BIT0 | + HAL_LL_TIM_CCMR_CC3S_BIT1 | + HAL_LL_TIM_CCMR_OC3PE | + HAL_LL_TIM_CCMR_OC3M_BIT0 ); + + // Set OCxM[2, 1]. + *tmpPtr |= HAL_LL_TIM_CCMR_OC3M_BIT1 | HAL_LL_TIM_CCMR_OC3M_BIT2; + } + + // Enable counter. + set_reg_bit( &hal_ll_hw_reg->cr1, HAL_LL_TIM_ENABLE_COUNTER_BIT ); + + return HAL_LL_TIM_SUCCESS; +} + +hal_ll_err_t hal_ll_tim_stop( handle_t *handle ) { + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + // If complementary output channel is used. + if ( HAL_LL_TIM_IS_COMPLEMENTARY ) { + hal_ll_hw_reg->ccer &= 1UL << hal_ll_tim_hw_specifics_map_local->config.channel * 4 + 2; + } else { + hal_ll_hw_reg->ccer &= 1UL << hal_ll_tim_hw_specifics_map_local->config.channel * 4; + } + + return HAL_LL_TIM_SUCCESS; +} + +void hal_ll_tim_close( handle_t *handle ) { + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_tim_get_module_state_address); + + if( low_level_handle->hal_ll_tim_handle != NULL ) { + low_level_handle->hal_ll_tim_handle = NULL; + low_level_handle->hal_drv_tim_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_tim_hw_specifics_map_local->max_period = 0; + hal_ll_tim_hw_specifics_map_local->freq_hz = 0; + + _hal_ll_tim_set_clock( hal_ll_tim_hw_specifics_map_local->base, true ); + _hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_map_local, false ); + _hal_ll_tim_set_clock( hal_ll_tim_hw_specifics_map_local->base, false ); + + hal_ll_tim_hw_specifics_map_local->config.pin = HAL_LL_PIN_NC; + hal_ll_tim_hw_specifics_map_local->config.channel = HAL_LL_PIN_NC; + hal_ll_tim_hw_specifics_map_local->config.af = NULL; + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static inline void _hal_ll_tim1_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_1 ); + } else { + clear_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_1 ); + } +} + +static inline void _hal_ll_tim2_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB1ENR1, HAL_LL_TIM_ENABLE_2 ); + } else { + clear_reg_bit( _RCC_APB1ENR1, HAL_LL_TIM_ENABLE_2 ); + } +} + +static inline void _hal_ll_tim3_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB1ENR1, HAL_LL_TIM_ENABLE_3 ); + } else { + clear_reg_bit( _RCC_APB1ENR1, HAL_LL_TIM_ENABLE_3 ); + } +} + +static inline void _hal_ll_tim4_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB1ENR1, HAL_LL_TIM_ENABLE_4 ); + } else { + clear_reg_bit( _RCC_APB1ENR1, HAL_LL_TIM_ENABLE_4 ); + } +} + +static inline void _hal_ll_tim5_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB1ENR1, HAL_LL_TIM_ENABLE_5 ); + } else { + clear_reg_bit( _RCC_APB1ENR1, HAL_LL_TIM_ENABLE_5 ); + } +} + +static inline void _hal_ll_tim8_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_8 ); + } else { + clear_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_8 ); + } +} + +static inline void _hal_ll_tim15_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_15 ); + } else { + clear_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_15 ); + } +} + +static inline void _hal_ll_tim16_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_16 ); + } else { + clear_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_16 ); + } +} + +static inline void _hal_ll_tim17_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_17 ); + } else { + clear_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_17 ); + } +} + +static inline void _hal_ll_tim20_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_20 ); + } else { + clear_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_20 ); + } +} + + +static hal_ll_pin_name_t _hal_ll_tim_check_pin( hal_ll_pin_name_t pin, uint8_t *index, hal_ll_tim_handle_register_t *handle_map ) { + + hal_ll_pin_name_t pin_num; + uint8_t index_counter = 0; + uint8_t hal_ll_module_id = 0; + uint16_t map_size = ( sizeof( _tim_map ) / sizeof( hal_ll_tim_pin_map_t ) ); + + if ( HAL_LL_PIN_NC == pin ) { + return HAL_LL_PIN_NC; + } + + // Check if the selected pin is valid. + for ( pin_num = 0; pin_num < map_size; pin_num++ ) { + if ( _tim_map[ pin_num ].pin == pin ) { + // Get module number + hal_ll_module_id = _tim_map[ pin_num ].module_index; + if ( NULL == handle_map[hal_ll_module_id].hal_drv_tim_handle ) { + *index = pin_num; + return hal_ll_module_id; + } else if ( TIM_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + // By default return last error msg. + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static hal_ll_tim_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + + uint8_t hal_ll_module_count = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_tim_handle_register_t ) ); + static uint8_t hal_ll_module_error = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_tim_handle_register_t ) ); + + while( hal_ll_module_count-- ) { + if ( hal_ll_tim_get_base_from_hal_handle == hal_ll_tim_hw_specifics_map [ hal_ll_module_count ].base) { + return &hal_ll_tim_hw_specifics_map[ hal_ll_module_count ]; + } + } + + return &hal_ll_tim_hw_specifics_map[ hal_ll_module_error ]; +} + +static void _hal_ll_tim_set_clock( hal_ll_base_addr_t base, bool hal_ll_state ) { + + switch ( ( uint32_t )base ) { // 32-bit base address. + #ifdef TIM_MODULE_1 + case ( HAL_LL_TIM1_BASE_ADDR ): + _hal_ll_tim1_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_2 + case ( HAL_LL_TIM2_BASE_ADDR ): + _hal_ll_tim2_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_3 + case ( HAL_LL_TIM3_BASE_ADDR ): + _hal_ll_tim3_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_4 + case ( HAL_LL_TIM4_BASE_ADDR ): + _hal_ll_tim4_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_5 + case ( HAL_LL_TIM5_BASE_ADDR ): + _hal_ll_tim5_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_8 + case ( HAL_LL_TIM8_BASE_ADDR ): + _hal_ll_tim8_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_15 + case ( HAL_LL_TIM15_BASE_ADDR ): + _hal_ll_tim15_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_16 + case ( HAL_LL_TIM16_BASE_ADDR ): + _hal_ll_tim16_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_17 + case ( HAL_LL_TIM17_BASE_ADDR ): + _hal_ll_tim17_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_20 + case ( HAL_LL_TIM20_BASE_ADDR ): + _hal_ll_tim20_set_clock( hal_ll_state ); + break; + #endif + + } +} + +static uint32_t _hal_ll_tim_clock_source( uint8_t selector ) { + + rcc_clocks_t rcc_clocks; + + RCC_GetClocksFrequency( &rcc_clocks ); + + if( selector == HAL_LL_APB2_TIMER_CLOCK ) { + if( rcc_clocks.hclk/rcc_clocks.pclk2 > 1 ) { + return rcc_clocks.pclk2 * 2; + } else { + return rcc_clocks.pclk2; + } + } + + if( selector == HAL_LL_APB1_TIMER_CLOCK ) { + if( rcc_clocks.hclk/rcc_clocks.pclk1 > 1 ) { + return rcc_clocks.pclk1 * 2; + } else { + return rcc_clocks.pclk1; + } + } + + return 0; +} + +static uint32_t _hal_ll_tim_get_clock_speed( hal_ll_base_addr_t base ) { + + switch ( ( uint32_t )base ) { + #ifdef TIM_MODULE_1 + case ( HAL_LL_TIM1_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM1_BUS ); + break; + #endif + + #ifdef TIM_MODULE_2 + case ( HAL_LL_TIM2_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM2_BUS ); + break; + #endif + + #ifdef TIM_MODULE_3 + case ( HAL_LL_TIM3_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM3_BUS ); + break; + #endif + + #ifdef TIM_MODULE_4 + case ( HAL_LL_TIM4_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM4_BUS ); + break; + #endif + + #ifdef TIM_MODULE_5 + case ( HAL_LL_TIM5_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM5_BUS ); + break; + #endif + + #ifdef TIM_MODULE_8 + case ( HAL_LL_TIM8_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM8_BUS ); + break; + #endif + + #ifdef TIM_MODULE_15 + case ( HAL_LL_TIM15_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM15_BUS ); + break; + #endif + + #ifdef TIM_MODULE_16 + case ( HAL_LL_TIM16_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM16_BUS ); + break; + #endif + + #ifdef TIM_MODULE_17 + case ( HAL_LL_TIM17_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM17_BUS ); + break; + #endif + + #ifdef TIM_MODULE_20 + case ( HAL_LL_TIM20_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM20_BUS ); + break; + #endif + + } + return 0; +} + +static void _hal_ll_tim_map_pin( uint8_t module_index, uint8_t index ) { + + uint8_t tmp_channel; + + // Map new pin + hal_ll_tim_hw_specifics_map[ module_index ].config.pin = _tim_map[ index ].pin; + tmp_channel = _tim_map[ index ].channel; + hal_ll_tim_hw_specifics_map[ module_index ].config.af = _tim_map[ index ].af; + + if ( tmp_channel >= HAL_LL_TIM_CHANNEL_1N ) { + HAL_LL_TIM_IS_COMPLEMENTARY = true; + hal_ll_tim_hw_specifics_map[ module_index ].config.channel = tmp_channel - 4; + } else { + HAL_LL_TIM_IS_COMPLEMENTARY = false; + hal_ll_tim_hw_specifics_map[ module_index ].config.channel = tmp_channel; + } +} + +static void _hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_map_t *map, bool hal_ll_state ) { + + module_struct module; + uint32_t tim_config = 0; + + if( map->config.pin != HAL_LL_PIN_NC ) { + if( hal_ll_state == false ) { + tim_config = GPIO_CFG_MODE_ALT_FUNCTION | + GPIO_CFG_SPEED_LOW | + GPIO_CFG_OTYPE_PP; + } else { + tim_config = GPIO_CFG_MODE_ALT_FUNCTION | + GPIO_CFG_SPEED_HIGH | + GPIO_CFG_OTYPE_PP; + } + + module.pins[ 0 ] = VALUE( map->config.pin, map->config.af ); + module.pins[ 1 ] = GPIO_MODULE_STRUCT_END; + + module.configs[ 0 ] = tim_config; + module.configs[ 1 ] = GPIO_MODULE_STRUCT_END; + + hal_ll_gpio_module_struct_init( &module, hal_ll_state ); + } +} + +static void _hal_ll_tim_hw_init( hal_ll_tim_hw_specifics_map_t *map ) { + + uint32_t ck_psc; + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( map->base ); + + // Counter used as upcounter. + clear_reg_bit( &hal_ll_hw_reg->cr1, HAL_LL_TIM_CR1_DIR_BIT ); + + // Get clock speed. + ck_psc = _hal_ll_tim_get_clock_speed( map->base ) / map->freq_hz; + + // This should not be the case. ck_psc should not be greater than 65535, which is max value. + if( ck_psc > UINT16_MAX ) { + // In case of duty period beeing greater than 65535 set ck_psc to max value. + ck_psc = UINT16_MAX - 1; // Because of ( ck_psc / UINT16_MAX + 1 ) ), has to be minus 1. + }else if ( ck_psc < 1 ) { + ck_psc = 1; + } + + // Write prescale value. + hal_ll_hw_reg->psc = ( uint16_t )( ck_psc / UINT16_MAX ); + + // Write max count value. + hal_ll_hw_reg->arr = ( uint16_t )( ck_psc/( ck_psc / UINT16_MAX + 1 ) ); + + // Write max period to global array. + map->max_period = ( uint16_t )ck_psc; +} + +static void _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_t *map ) { + + _hal_ll_tim_set_clock( map->base, true ); + + _hal_ll_tim_alternate_functions_set_state( map, true ); + + _hal_ll_tim_hw_init( map ); +} +// ------------------------------------------------------------------------- END + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_87/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_87/CMakeLists.cmake new file mode 100644 index 000000000..9594d8f7c --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_87/CMakeLists.cmake @@ -0,0 +1,9 @@ +if(${MCU_NAME} MATCHES "^STM32G484CE$|^STM32G484ME$|^STM32G484PE$|^STM32G484RE$|^STM32G484QE$|^STM32G484VE$") + set(tim_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_tim.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_87") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_87") + list(APPEND hal_ll_def_list "STM32G4xx") + list(APPEND hal_ll_def_list "STM32G48xx") + list(APPEND hal_ll_def_list "STM32G484xx") + set(tim_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/tim/hal_ll_tim_pin_map/implementations/doc_ds_87") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_87/hal_ll_tim.c b/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_87/hal_ll_tim.c new file mode 100644 index 000000000..877a26adb --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_87/hal_ll_tim.c @@ -0,0 +1,1011 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_tim.c + * @brief TIM HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_gpio.h" +#include "hal_ll_rcc.h" +#include "hal_ll_tim.h" +#include "hal_ll_tim_pin_map.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_tim_handle_register_t hal_ll_module_state[ TIM_MODULE_COUNT ]; + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< CR1 constants. */ +#define HAL_LL_TIM_ENABLE_COUNTER_BIT 0 +#define HAL_LL_TIM_BDTR_MOE_BIT 15 +#define HAL_LL_TIM_BDTR_MOE 0x8000 + +#define HAL_LL_TIM_CCMR_CC2S_BIT0 0x100u +#define HAL_LL_TIM_CCMR_CC2S_BIT1 0x200u +#define HAL_LL_TIM_CCMR_OC2PE 0x800u +#define HAL_LL_TIM_CCMR_OC2M_BIT0 0x1000u +#define HAL_LL_TIM_CCMR_OC2M_BIT1 0x2000u +#define HAL_LL_TIM_CCMR_OC2M_BIT2 0x4000u + +#define HAL_LL_TIM_CCMR_CC3S_BIT0 0x1u +#define HAL_LL_TIM_CCMR_CC3S_BIT1 0x2u +#define HAL_LL_TIM_CCMR_OC3PE 0x8u +#define HAL_LL_TIM_CCMR_OC3M_BIT0 0x10u +#define HAL_LL_TIM_CCMR_OC3M_BIT1 0x20u +#define HAL_LL_TIM_CCMR_OC3M_BIT2 0x40u + +#define HAL_LL_TIM_CR1_DIR 0x10 +#define HAL_LL_TIM_CR1_DIR_BIT 4 + +#define HAL_LL_TIM_ENABLE_1 11 + +#define HAL_LL_TIM_ENABLE_2 0 + +#define HAL_LL_TIM_ENABLE_3 1 + +#define HAL_LL_TIM_ENABLE_4 2 + +#define HAL_LL_TIM_ENABLE_5 3 + +#define HAL_LL_TIM_ENABLE_8 13 + +#define HAL_LL_TIM_ENABLE_15 16 + +#define HAL_LL_TIM_ENABLE_16 17 + +#define HAL_LL_TIM_ENABLE_17 18 + +#define HAL_LL_TIM_ENABLE_20 20 + + +#define HAL_LL_APB2_TIMER_CLOCK 2 + +#define HAL_LL_APB1_TIMER_CLOCK 1 + + + +#define hal_ll_tim_channel_static( _chn ) ( _chn-1 ) + +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_tim_get_base_struct(_handle) ((hal_ll_tim_base_handle_t *)_handle) + +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_tim_get_module_state_address ((hal_ll_tim_handle_register_t *)*handle) + +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_tim_get_handle ( hal_ll_tim_handle_register_t * )hal_ll_tim_get_module_state_address->hal_ll_tim_handle + +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_tim_get_base_from_hal_handle ((hal_ll_tim_hw_specifics_map_t *)((hal_ll_tim_handle_register_t *)\ + (((hal_ll_tim_handle_register_t *)(handle))->hal_ll_tim_handle))->hal_ll_tim_handle)->base + +// -------------------------------------------------------------- PRIVATE TYPES +/*!< @brief TIM register structure. */ +typedef struct +{ + uint32_t cr1; /* Address offset 0x00 */ + uint32_t cr2; /* Address offset 0x04 */ + uint32_t smcr; /* Address offset 0x08 */ + uint32_t dier; /* Address offset 0x0C */ + uint32_t sr; /* Address offset 0x10 */ + uint32_t egr; /* Address offset 0x14 */ + uint32_t ccmr1; /* Address offset 0x18 */ + uint32_t ccmr2; /* Address offset 0x1C */ + uint32_t ccer; /* Address offset 0x20 */ + uint32_t cnt; /* Address offset 0x24 */ + uint32_t psc; /* Address offset 0x28 */ + uint32_t arr; /* Address offset 0x2C */ + uint32_t rcr; /* Address offset 0x30 */ + uint32_t ccr1; /* Address offset 0x34 */ + uint32_t ccr2; /* Address offset 0x38 */ + uint32_t ccr3; /* Address offset 0x3C */ + uint32_t ccr4; /* Address offset 0x40 */ + uint32_t bdtr; /* Address offset 0x44 */ + uint32_t dcr; /* Address offset 0x48 */ + uint32_t dmar; /* Address offset 0x4C */ + uint32_t tim2_5_or; /* Address offset 0x50 */ +} hal_ll_tim_base_handle_t; + +/*!< @brief TIM pin structure */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_channel_t channel; + uint32_t af; +} hal_ll_tim_t; + +/*!< @brief TIM hw specific structure */ +typedef struct +{ + hal_ll_base_addr_t base; + hal_ll_tim_t config; + uint16_t max_period; + uint32_t freq_hz; + hal_ll_pin_name_t module_index; +} hal_ll_tim_hw_specifics_map_t; + +/*!< @brief TIM hw specific error values */ +typedef enum +{ + HAL_LL_TIM_SUCCESS = 0, + HAL_LL_TIM_MODULE_ERROR, + HAL_LL_TIM_WRONG_PIN, + + HAL_LL_TIM_ERROR = (-1) +} hal_ll_tim_err_t; + +// ------------------------------------------------------------------ VARIABLES +/*!< @brief TIM specific info */ +static hal_ll_tim_hw_specifics_map_t hal_ll_tim_hw_specifics_map[] = +{ + #ifdef TIM_MODULE_1 + {HAL_LL_TIM1_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_1 - 1}, + #endif + + #ifdef TIM_MODULE_2 + {HAL_LL_TIM2_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_2 - 1}, + #endif + + #ifdef TIM_MODULE_3 + {HAL_LL_TIM3_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_3 - 1}, + #endif + + #ifdef TIM_MODULE_4 + {HAL_LL_TIM4_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_4 - 1}, + #endif + + #ifdef TIM_MODULE_5 + {HAL_LL_TIM5_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_5 - 1}, + #endif + + #ifdef TIM_MODULE_8 + {HAL_LL_TIM8_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_8 - 1}, + #endif + + #ifdef TIM_MODULE_15 + {HAL_LL_TIM15_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_15 - 1}, + #endif + + #ifdef TIM_MODULE_16 + {HAL_LL_TIM16_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_16 - 1}, + #endif + + #ifdef TIM_MODULE_17 + {HAL_LL_TIM17_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_17 - 1}, + #endif + + #ifdef TIM_MODULE_20 + {HAL_LL_TIM20_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_20 - 1}, + #endif + + + {HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, HAL_LL_PIN_NC} +}; + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_tim_handle_register_t *low_level_handle; +static volatile hal_ll_tim_hw_specifics_map_t *hal_ll_tim_hw_specifics_map_local; + +static bool HAL_LL_TIM_IS_COMPLEMENTARY; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Enable TIM module 1 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim1_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 2 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim2_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 3 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim3_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 4 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim4_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 5 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim5_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 8 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim8_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 15 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim15_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 16 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim16_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 17 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim17_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 20 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim20_set_clock( bool hal_ll_state ); + + +/** + * @brief Enable TIM module gate clock. + * @param base - TIM module base + * address + * @return None + */ +static void _hal_ll_tim_set_clock( hal_ll_base_addr_t base, bool hal_ll_state ); + +/** + * @brief Select TIM clock source + * @param selector - clock source selector + * @return uint32_t - clock source + */ +static uint32_t _hal_ll_tim_clock_source( uint8_t selector ); + +/** + * @brief Based on selected TIM, + * return clock speed. + * @param base - TIM module base + * address + * @return uint32_t clock source. + */ +static uint32_t _hal_ll_tim_get_clock_speed( hal_ll_base_addr_t base ); + +/** + * @brief Initialize TIM module on hardware level. + * + * Initializes TIM module on hardware level, based on beforehand + * set configuration and module handler. + * + * @param map - Object specific context handler. + * @return none + * + */ +static void _hal_ll_tim_hw_init( hal_ll_tim_hw_specifics_map_t *map ); + +/** + * @brief Full TIM module initialization procedure. + * + * Initializes TIM module on hardware level, based on beforehand + * set configuration and module handler. Sets adequate pin alternate functions. + * Initializes module clock. + * + * @param map - Object specific context handler. + * @return none + * + */ +static void _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_t *map ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_tim_hw_specifics_map array index. + * + * @param handle - Object specific context handler. + * @return hal_ll_tim_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_tim_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Check if pin is adequate. + * + * Checks tim pin the user has passed with pre-defined + * pin in tim map. + * + * @param pin - TIM pre-defined pin name. + * @return hal_ll_pin_name_t Module index based on pin. + * + * Returns pre-defined module index from pin maps, if pin + * is adequate. + */ +static hal_ll_pin_name_t _hal_ll_tim_check_pin( hal_ll_pin_name_t pin, uint8_t *index, hal_ll_tim_handle_register_t *handle_map ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * TIM pin. + * + * @param[in] module_index TIM HW module index -- 0,1,2... + * @param[in] *index_list Array with TIM map index values + * + * @return None + */ +static void _hal_ll_tim_map_pin( uint8_t module_index, uint8_t index ); + +/** + * @brief Sets TIM pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if TIM is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param map - Object specific context handler. + * + * @param hal_ll_state - Init/De-init + * @return none + * + */ +static void _hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_map_t *map, bool hal_ll_state ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_tim_register_handle( hal_ll_pin_name_t pin, hal_ll_tim_handle_register_t *handle_map, + uint8_t *hal_module_id ) { + + uint8_t index; + uint16_t pin_check_result; + + if ( ( pin_check_result = _hal_ll_tim_check_pin( pin, &index, handle_map ) ) == HAL_LL_PIN_NC ) { + return HAL_LL_TIM_WRONG_PIN; + } + + if ( hal_ll_tim_hw_specifics_map[ pin_check_result ].config.pin != pin ){ + // Clear previous module alternate functions + _hal_ll_tim_alternate_functions_set_state( &hal_ll_tim_hw_specifics_map[ pin_check_result ], false ); + + _hal_ll_tim_map_pin( pin_check_result, index ); + + _hal_ll_tim_alternate_functions_set_state( &hal_ll_tim_hw_specifics_map[ pin_check_result ], true ); + + handle_map[ pin_check_result ].init_ll_state = false; + + hal_ll_module_state[ pin_check_result ].init_ll_state = false; + + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle = ( handle_t * )&hal_ll_tim_hw_specifics_map[ pin_check_result ].base; + + handle_map[ pin_check_result ].hal_ll_tim_handle = ( handle_t *)&hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle; + + return HAL_LL_TIM_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_tim( handle_t *handle ) { + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + hal_ll_tim_handle_register_t *hal_handle = (hal_ll_tim_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_tim_hw_specifics_map_local->module_index; + + _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_local ); + + hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle = (handle_t *)&hal_ll_tim_hw_specifics_map[ pin_check_result ].base; + hal_ll_module_state[ pin_check_result ].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_TIM_SUCCESS; +} + +uint32_t hal_ll_tim_set_freq( handle_t *handle, uint32_t freq_hz ) { + + uint32_t tmp_channel; + uint32_t ck_psc; + uint32_t local_base_addr; + uint32_t local_freq; + uint32_t tmp_freq; + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + if( hal_ll_tim_hw_specifics_map_local->base == HAL_LL_MODULE_ERROR ) { + return HAL_LL_TIM_MODULE_ERROR; + } + + low_level_handle->init_ll_state = false; + + tmp_channel = hal_ll_tim_hw_specifics_map_local->config.channel; + + // If complementary output channel is used. + if ( HAL_LL_TIM_IS_COMPLEMENTARY ) { + // Stop capture/compare. + hal_ll_hw_reg->ccer &= 1UL << tmp_channel * 4 + 2; + } else { + // Stop capture/compare. + hal_ll_hw_reg->ccer &= 1UL << tmp_channel * 4; + } + + // Set TIM duty to 0. + *( &hal_ll_hw_reg->ccr1 + hal_ll_tim_channel_static( tmp_channel ) ) = 0; + + hal_ll_tim_hw_specifics_map_local->freq_hz = freq_hz; + + local_freq = hal_ll_tim_hw_specifics_map_local->freq_hz; + local_base_addr = hal_ll_tim_hw_specifics_map_local->base; + + ck_psc = _hal_ll_tim_get_clock_speed( local_base_addr ) / local_freq; + + if ( ck_psc > UINT16_MAX ) { + tmp_freq = _hal_ll_tim_get_clock_speed( local_base_addr ) / UINT16_MAX; + hal_ll_tim_hw_specifics_map_local->freq_hz = tmp_freq; + } else { + tmp_freq = freq_hz; + hal_ll_tim_hw_specifics_map_local->freq_hz = freq_hz; + } + + _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_local ); + + low_level_handle->init_ll_state = true; + + return tmp_freq; +} + +hal_ll_err_t hal_ll_tim_set_duty( handle_t *handle, float duty_ratio ) { + + float tmp_duty; + uint32_t max_duty = 0; + uint16_t max_period; + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + if ( low_level_handle->init_ll_state == false ) { + hal_ll_tim_start( handle ); + low_level_handle->init_ll_state = true; + } + + tmp_duty = duty_ratio * 100; + max_period = hal_ll_tim_hw_specifics_map_local->max_period; + + max_duty = ( ( float )max_period / 100 ) * tmp_duty; + + *( &hal_ll_hw_reg->ccr1 + hal_ll_tim_channel_static( hal_ll_tim_hw_specifics_map_local->config.channel ) ) = max_duty; + + return HAL_LL_TIM_SUCCESS; +} + +hal_ll_err_t hal_ll_tim_start( handle_t *handle ) { + + uint32_t tmp_channel; + volatile uint32_t tmp, + *tmpPtr; + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + tmp_channel = hal_ll_tim_hw_specifics_map_local->config.channel; + + // Capture/Compare 1 output enable. + tmp = hal_ll_hw_reg->ccer; + + // If complementary output channel is used. + if ( HAL_LL_TIM_IS_COMPLEMENTARY ) { + // Capture/Compare complementary output enable + tmp |= ( 1UL << ( hal_ll_tim_channel_static( tmp_channel ) * 4 + 2 ) ); + // Capture/Compare complementary output polarity(ACTIVE HIGH). + tmp &= ~( 1UL << ( hal_ll_tim_channel_static( tmp_channel ) * 4 + 3 ) ); + } else { + // Capture/Compare output polarity. + tmp |= ( 1UL << ( hal_ll_tim_channel_static( tmp_channel ) * 4 ) ); + // Capture/Compare output polarity(ACTIVE HIGH). + tmp &= ~( 1UL << ( hal_ll_tim_channel_static( tmp_channel ) * 4 + 1 ) ); + } + + hal_ll_hw_reg->ccer = tmp; + + #if defined(TIM_MODULE_1) || defined(TIM_MODULE_8) || defined(TIM_MODULE_20) + // Main output enabled. + set_reg_bit( &hal_ll_hw_reg->bdtr, HAL_LL_TIM_BDTR_MOE_BIT ); + #endif + + tmpPtr = &hal_ll_hw_reg->ccmr1; + + if( hal_ll_tim_channel_static( tmp_channel ) > 1 ) { + tmpPtr = &hal_ll_hw_reg->ccmr2; + } + + if( ( hal_ll_tim_channel_static( tmp_channel ) / 2 ) * 2 != + hal_ll_tim_channel_static( tmp_channel ) ) { + // Clear CCxS, OCxM[0]. + *tmpPtr &= ~( HAL_LL_TIM_CCMR_CC2S_BIT0 | + HAL_LL_TIM_CCMR_CC2S_BIT1 | + HAL_LL_TIM_CCMR_OC2PE | + HAL_LL_TIM_CCMR_OC2M_BIT0 ); + // Set OCxM[2, 1] + *tmpPtr |= HAL_LL_TIM_CCMR_OC2M_BIT1 | HAL_LL_TIM_CCMR_OC2M_BIT2; + } else { + // Clear CCxS, OCxM[0]. + *tmpPtr &= ~( HAL_LL_TIM_CCMR_CC3S_BIT0 | + HAL_LL_TIM_CCMR_CC3S_BIT1 | + HAL_LL_TIM_CCMR_OC3PE | + HAL_LL_TIM_CCMR_OC3M_BIT0 ); + + // Set OCxM[2, 1]. + *tmpPtr |= HAL_LL_TIM_CCMR_OC3M_BIT1 | HAL_LL_TIM_CCMR_OC3M_BIT2; + } + + // Enable counter. + set_reg_bit( &hal_ll_hw_reg->cr1, HAL_LL_TIM_ENABLE_COUNTER_BIT ); + + return HAL_LL_TIM_SUCCESS; +} + +hal_ll_err_t hal_ll_tim_stop( handle_t *handle ) { + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + // If complementary output channel is used. + if ( HAL_LL_TIM_IS_COMPLEMENTARY ) { + hal_ll_hw_reg->ccer &= 1UL << hal_ll_tim_hw_specifics_map_local->config.channel * 4 + 2; + } else { + hal_ll_hw_reg->ccer &= 1UL << hal_ll_tim_hw_specifics_map_local->config.channel * 4; + } + + return HAL_LL_TIM_SUCCESS; +} + +void hal_ll_tim_close( handle_t *handle ) { + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_tim_get_module_state_address); + + if( low_level_handle->hal_ll_tim_handle != NULL ) { + low_level_handle->hal_ll_tim_handle = NULL; + low_level_handle->hal_drv_tim_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_tim_hw_specifics_map_local->max_period = 0; + hal_ll_tim_hw_specifics_map_local->freq_hz = 0; + + _hal_ll_tim_set_clock( hal_ll_tim_hw_specifics_map_local->base, true ); + _hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_map_local, false ); + _hal_ll_tim_set_clock( hal_ll_tim_hw_specifics_map_local->base, false ); + + hal_ll_tim_hw_specifics_map_local->config.pin = HAL_LL_PIN_NC; + hal_ll_tim_hw_specifics_map_local->config.channel = HAL_LL_PIN_NC; + hal_ll_tim_hw_specifics_map_local->config.af = NULL; + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static inline void _hal_ll_tim1_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_1 ); + } else { + clear_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_1 ); + } +} + +static inline void _hal_ll_tim2_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB1ENR1, HAL_LL_TIM_ENABLE_2 ); + } else { + clear_reg_bit( _RCC_APB1ENR1, HAL_LL_TIM_ENABLE_2 ); + } +} + +static inline void _hal_ll_tim3_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB1ENR1, HAL_LL_TIM_ENABLE_3 ); + } else { + clear_reg_bit( _RCC_APB1ENR1, HAL_LL_TIM_ENABLE_3 ); + } +} + +static inline void _hal_ll_tim4_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB1ENR1, HAL_LL_TIM_ENABLE_4 ); + } else { + clear_reg_bit( _RCC_APB1ENR1, HAL_LL_TIM_ENABLE_4 ); + } +} + +static inline void _hal_ll_tim5_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB1ENR1, HAL_LL_TIM_ENABLE_5 ); + } else { + clear_reg_bit( _RCC_APB1ENR1, HAL_LL_TIM_ENABLE_5 ); + } +} + +static inline void _hal_ll_tim8_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_8 ); + } else { + clear_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_8 ); + } +} + +static inline void _hal_ll_tim15_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_15 ); + } else { + clear_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_15 ); + } +} + +static inline void _hal_ll_tim16_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_16 ); + } else { + clear_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_16 ); + } +} + +static inline void _hal_ll_tim17_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_17 ); + } else { + clear_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_17 ); + } +} + +static inline void _hal_ll_tim20_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_20 ); + } else { + clear_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_20 ); + } +} + + +static hal_ll_pin_name_t _hal_ll_tim_check_pin( hal_ll_pin_name_t pin, uint8_t *index, hal_ll_tim_handle_register_t *handle_map ) { + + hal_ll_pin_name_t pin_num; + uint8_t index_counter = 0; + uint8_t hal_ll_module_id = 0; + uint16_t map_size = ( sizeof( _tim_map ) / sizeof( hal_ll_tim_pin_map_t ) ); + + if ( HAL_LL_PIN_NC == pin ) { + return HAL_LL_PIN_NC; + } + + // Check if the selected pin is valid. + for ( pin_num = 0; pin_num < map_size; pin_num++ ) { + if ( _tim_map[ pin_num ].pin == pin ) { + // Get module number + hal_ll_module_id = _tim_map[ pin_num ].module_index; + if ( NULL == handle_map[hal_ll_module_id].hal_drv_tim_handle ) { + *index = pin_num; + return hal_ll_module_id; + } else if ( TIM_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + // By default return last error msg. + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static hal_ll_tim_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + + uint8_t hal_ll_module_count = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_tim_handle_register_t ) ); + static uint8_t hal_ll_module_error = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_tim_handle_register_t ) ); + + while( hal_ll_module_count-- ) { + if ( hal_ll_tim_get_base_from_hal_handle == hal_ll_tim_hw_specifics_map [ hal_ll_module_count ].base) { + return &hal_ll_tim_hw_specifics_map[ hal_ll_module_count ]; + } + } + + return &hal_ll_tim_hw_specifics_map[ hal_ll_module_error ]; +} + +static void _hal_ll_tim_set_clock( hal_ll_base_addr_t base, bool hal_ll_state ) { + + switch ( ( uint32_t )base ) { // 32-bit base address. + #ifdef TIM_MODULE_1 + case ( HAL_LL_TIM1_BASE_ADDR ): + _hal_ll_tim1_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_2 + case ( HAL_LL_TIM2_BASE_ADDR ): + _hal_ll_tim2_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_3 + case ( HAL_LL_TIM3_BASE_ADDR ): + _hal_ll_tim3_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_4 + case ( HAL_LL_TIM4_BASE_ADDR ): + _hal_ll_tim4_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_5 + case ( HAL_LL_TIM5_BASE_ADDR ): + _hal_ll_tim5_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_8 + case ( HAL_LL_TIM8_BASE_ADDR ): + _hal_ll_tim8_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_15 + case ( HAL_LL_TIM15_BASE_ADDR ): + _hal_ll_tim15_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_16 + case ( HAL_LL_TIM16_BASE_ADDR ): + _hal_ll_tim16_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_17 + case ( HAL_LL_TIM17_BASE_ADDR ): + _hal_ll_tim17_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_20 + case ( HAL_LL_TIM20_BASE_ADDR ): + _hal_ll_tim20_set_clock( hal_ll_state ); + break; + #endif + + } +} + +static uint32_t _hal_ll_tim_clock_source( uint8_t selector ) { + + rcc_clocks_t rcc_clocks; + + RCC_GetClocksFrequency( &rcc_clocks ); + + if( selector == HAL_LL_APB2_TIMER_CLOCK ) { + if( rcc_clocks.hclk/rcc_clocks.pclk2 > 1 ) { + return rcc_clocks.pclk2 * 2; + } else { + return rcc_clocks.pclk2; + } + } + + if( selector == HAL_LL_APB1_TIMER_CLOCK ) { + if( rcc_clocks.hclk/rcc_clocks.pclk1 > 1 ) { + return rcc_clocks.pclk1 * 2; + } else { + return rcc_clocks.pclk1; + } + } + + return 0; +} + +static uint32_t _hal_ll_tim_get_clock_speed( hal_ll_base_addr_t base ) { + + switch ( ( uint32_t )base ) { + #ifdef TIM_MODULE_1 + case ( HAL_LL_TIM1_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM1_BUS ); + break; + #endif + + #ifdef TIM_MODULE_2 + case ( HAL_LL_TIM2_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM2_BUS ); + break; + #endif + + #ifdef TIM_MODULE_3 + case ( HAL_LL_TIM3_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM3_BUS ); + break; + #endif + + #ifdef TIM_MODULE_4 + case ( HAL_LL_TIM4_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM4_BUS ); + break; + #endif + + #ifdef TIM_MODULE_5 + case ( HAL_LL_TIM5_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM5_BUS ); + break; + #endif + + #ifdef TIM_MODULE_8 + case ( HAL_LL_TIM8_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM8_BUS ); + break; + #endif + + #ifdef TIM_MODULE_15 + case ( HAL_LL_TIM15_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM15_BUS ); + break; + #endif + + #ifdef TIM_MODULE_16 + case ( HAL_LL_TIM16_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM16_BUS ); + break; + #endif + + #ifdef TIM_MODULE_17 + case ( HAL_LL_TIM17_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM17_BUS ); + break; + #endif + + #ifdef TIM_MODULE_20 + case ( HAL_LL_TIM20_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM20_BUS ); + break; + #endif + + } + return 0; +} + +static void _hal_ll_tim_map_pin( uint8_t module_index, uint8_t index ) { + + uint8_t tmp_channel; + + // Map new pin + hal_ll_tim_hw_specifics_map[ module_index ].config.pin = _tim_map[ index ].pin; + tmp_channel = _tim_map[ index ].channel; + hal_ll_tim_hw_specifics_map[ module_index ].config.af = _tim_map[ index ].af; + + if ( tmp_channel >= HAL_LL_TIM_CHANNEL_1N ) { + HAL_LL_TIM_IS_COMPLEMENTARY = true; + hal_ll_tim_hw_specifics_map[ module_index ].config.channel = tmp_channel - 4; + } else { + HAL_LL_TIM_IS_COMPLEMENTARY = false; + hal_ll_tim_hw_specifics_map[ module_index ].config.channel = tmp_channel; + } +} + +static void _hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_map_t *map, bool hal_ll_state ) { + + module_struct module; + uint32_t tim_config = 0; + + if( map->config.pin != HAL_LL_PIN_NC ) { + if( hal_ll_state == false ) { + tim_config = GPIO_CFG_MODE_ALT_FUNCTION | + GPIO_CFG_SPEED_LOW | + GPIO_CFG_OTYPE_PP; + } else { + tim_config = GPIO_CFG_MODE_ALT_FUNCTION | + GPIO_CFG_SPEED_HIGH | + GPIO_CFG_OTYPE_PP; + } + + module.pins[ 0 ] = VALUE( map->config.pin, map->config.af ); + module.pins[ 1 ] = GPIO_MODULE_STRUCT_END; + + module.configs[ 0 ] = tim_config; + module.configs[ 1 ] = GPIO_MODULE_STRUCT_END; + + hal_ll_gpio_module_struct_init( &module, hal_ll_state ); + } +} + +static void _hal_ll_tim_hw_init( hal_ll_tim_hw_specifics_map_t *map ) { + + uint32_t ck_psc; + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( map->base ); + + // Counter used as upcounter. + clear_reg_bit( &hal_ll_hw_reg->cr1, HAL_LL_TIM_CR1_DIR_BIT ); + + // Get clock speed. + ck_psc = _hal_ll_tim_get_clock_speed( map->base ) / map->freq_hz; + + // This should not be the case. ck_psc should not be greater than 65535, which is max value. + if( ck_psc > UINT16_MAX ) { + // In case of duty period beeing greater than 65535 set ck_psc to max value. + ck_psc = UINT16_MAX - 1; // Because of ( ck_psc / UINT16_MAX + 1 ) ), has to be minus 1. + }else if ( ck_psc < 1 ) { + ck_psc = 1; + } + + // Write prescale value. + hal_ll_hw_reg->psc = ( uint16_t )( ck_psc / UINT16_MAX ); + + // Write max count value. + hal_ll_hw_reg->arr = ( uint16_t )( ck_psc/( ck_psc / UINT16_MAX + 1 ) ); + + // Write max period to global array. + map->max_period = ( uint16_t )ck_psc; +} + +static void _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_t *map ) { + + _hal_ll_tim_set_clock( map->base, true ); + + _hal_ll_tim_alternate_functions_set_state( map, true ); + + _hal_ll_tim_hw_init( map ); +} +// ------------------------------------------------------------------------- END + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_88/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_88/CMakeLists.cmake new file mode 100644 index 000000000..9dfc42237 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_88/CMakeLists.cmake @@ -0,0 +1,9 @@ +if(${MCU_NAME} MATCHES "^STM32G491CC$|^STM32G491KC$|^STM32G491RC$|^STM32G491VC$|^STM32G491MC$|^STM32G491CE$|^STM32G491KE$|^STM32G491RE$|^STM32G491VE$|^STM32G491ME$") + set(tim_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_tim.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_88") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_88") + list(APPEND hal_ll_def_list "STM32G4xx") + list(APPEND hal_ll_def_list "STM32G49xx") + list(APPEND hal_ll_def_list "STM32G491xx") + set(tim_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/tim/hal_ll_tim_pin_map/implementations/doc_ds_88") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_88/hal_ll_tim.c b/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_88/hal_ll_tim.c new file mode 100644 index 000000000..65e13891b --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_88/hal_ll_tim.c @@ -0,0 +1,978 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_tim.c + * @brief TIM HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_gpio.h" +#include "hal_ll_rcc.h" +#include "hal_ll_tim.h" +#include "hal_ll_tim_pin_map.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_tim_handle_register_t hal_ll_module_state[ TIM_MODULE_COUNT ]; + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< CR1 constants. */ +#define HAL_LL_TIM_ENABLE_COUNTER_BIT 0 +#define HAL_LL_TIM_BDTR_MOE_BIT 15 +#define HAL_LL_TIM_BDTR_MOE 0x8000 + +#define HAL_LL_TIM_CCMR_CC2S_BIT0 0x100u +#define HAL_LL_TIM_CCMR_CC2S_BIT1 0x200u +#define HAL_LL_TIM_CCMR_OC2PE 0x800u +#define HAL_LL_TIM_CCMR_OC2M_BIT0 0x1000u +#define HAL_LL_TIM_CCMR_OC2M_BIT1 0x2000u +#define HAL_LL_TIM_CCMR_OC2M_BIT2 0x4000u + +#define HAL_LL_TIM_CCMR_CC3S_BIT0 0x1u +#define HAL_LL_TIM_CCMR_CC3S_BIT1 0x2u +#define HAL_LL_TIM_CCMR_OC3PE 0x8u +#define HAL_LL_TIM_CCMR_OC3M_BIT0 0x10u +#define HAL_LL_TIM_CCMR_OC3M_BIT1 0x20u +#define HAL_LL_TIM_CCMR_OC3M_BIT2 0x40u + +#define HAL_LL_TIM_CR1_DIR 0x10 +#define HAL_LL_TIM_CR1_DIR_BIT 4 + +#define HAL_LL_TIM_ENABLE_1 11 + +#define HAL_LL_TIM_ENABLE_2 0 + +#define HAL_LL_TIM_ENABLE_3 1 + +#define HAL_LL_TIM_ENABLE_4 2 + +#define HAL_LL_TIM_ENABLE_8 13 + +#define HAL_LL_TIM_ENABLE_15 16 + +#define HAL_LL_TIM_ENABLE_16 17 + +#define HAL_LL_TIM_ENABLE_17 18 + +#define HAL_LL_TIM_ENABLE_20 20 + + +#define HAL_LL_APB2_TIMER_CLOCK 2 + +#define HAL_LL_APB1_TIMER_CLOCK 1 + + + +#define hal_ll_tim_channel_static( _chn ) ( _chn-1 ) + +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_tim_get_base_struct(_handle) ((hal_ll_tim_base_handle_t *)_handle) + +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_tim_get_module_state_address ((hal_ll_tim_handle_register_t *)*handle) + +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_tim_get_handle ( hal_ll_tim_handle_register_t * )hal_ll_tim_get_module_state_address->hal_ll_tim_handle + +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_tim_get_base_from_hal_handle ((hal_ll_tim_hw_specifics_map_t *)((hal_ll_tim_handle_register_t *)\ + (((hal_ll_tim_handle_register_t *)(handle))->hal_ll_tim_handle))->hal_ll_tim_handle)->base + +// -------------------------------------------------------------- PRIVATE TYPES +/*!< @brief TIM register structure. */ +typedef struct +{ + uint32_t cr1; /* Address offset 0x00 */ + uint32_t cr2; /* Address offset 0x04 */ + uint32_t smcr; /* Address offset 0x08 */ + uint32_t dier; /* Address offset 0x0C */ + uint32_t sr; /* Address offset 0x10 */ + uint32_t egr; /* Address offset 0x14 */ + uint32_t ccmr1; /* Address offset 0x18 */ + uint32_t ccmr2; /* Address offset 0x1C */ + uint32_t ccer; /* Address offset 0x20 */ + uint32_t cnt; /* Address offset 0x24 */ + uint32_t psc; /* Address offset 0x28 */ + uint32_t arr; /* Address offset 0x2C */ + uint32_t rcr; /* Address offset 0x30 */ + uint32_t ccr1; /* Address offset 0x34 */ + uint32_t ccr2; /* Address offset 0x38 */ + uint32_t ccr3; /* Address offset 0x3C */ + uint32_t ccr4; /* Address offset 0x40 */ + uint32_t bdtr; /* Address offset 0x44 */ + uint32_t dcr; /* Address offset 0x48 */ + uint32_t dmar; /* Address offset 0x4C */ + uint32_t tim2_5_or; /* Address offset 0x50 */ +} hal_ll_tim_base_handle_t; + +/*!< @brief TIM pin structure */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_channel_t channel; + uint32_t af; +} hal_ll_tim_t; + +/*!< @brief TIM hw specific structure */ +typedef struct +{ + hal_ll_base_addr_t base; + hal_ll_tim_t config; + uint16_t max_period; + uint32_t freq_hz; + hal_ll_pin_name_t module_index; +} hal_ll_tim_hw_specifics_map_t; + +/*!< @brief TIM hw specific error values */ +typedef enum +{ + HAL_LL_TIM_SUCCESS = 0, + HAL_LL_TIM_MODULE_ERROR, + HAL_LL_TIM_WRONG_PIN, + + HAL_LL_TIM_ERROR = (-1) +} hal_ll_tim_err_t; + +// ------------------------------------------------------------------ VARIABLES +/*!< @brief TIM specific info */ +static hal_ll_tim_hw_specifics_map_t hal_ll_tim_hw_specifics_map[] = +{ + #ifdef TIM_MODULE_1 + {HAL_LL_TIM1_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_1 - 1}, + #endif + + #ifdef TIM_MODULE_2 + {HAL_LL_TIM2_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_2 - 1}, + #endif + + #ifdef TIM_MODULE_3 + {HAL_LL_TIM3_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_3 - 1}, + #endif + + #ifdef TIM_MODULE_4 + {HAL_LL_TIM4_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_4 - 1}, + #endif + + #ifdef TIM_MODULE_8 + {HAL_LL_TIM8_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_8 - 1}, + #endif + + #ifdef TIM_MODULE_15 + {HAL_LL_TIM15_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_15 - 1}, + #endif + + #ifdef TIM_MODULE_16 + {HAL_LL_TIM16_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_16 - 1}, + #endif + + #ifdef TIM_MODULE_17 + {HAL_LL_TIM17_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_17 - 1}, + #endif + + #ifdef TIM_MODULE_20 + {HAL_LL_TIM20_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_20 - 1}, + #endif + + + {HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, HAL_LL_PIN_NC} +}; + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_tim_handle_register_t *low_level_handle; +static volatile hal_ll_tim_hw_specifics_map_t *hal_ll_tim_hw_specifics_map_local; + +static bool HAL_LL_TIM_IS_COMPLEMENTARY; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Enable TIM module 1 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim1_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 2 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim2_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 3 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim3_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 4 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim4_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 8 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim8_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 15 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim15_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 16 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim16_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 17 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim17_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 20 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim20_set_clock( bool hal_ll_state ); + + +/** + * @brief Enable TIM module gate clock. + * @param base - TIM module base + * address + * @return None + */ +static void _hal_ll_tim_set_clock( hal_ll_base_addr_t base, bool hal_ll_state ); + +/** + * @brief Select TIM clock source + * @param selector - clock source selector + * @return uint32_t - clock source + */ +static uint32_t _hal_ll_tim_clock_source( uint8_t selector ); + +/** + * @brief Based on selected TIM, + * return clock speed. + * @param base - TIM module base + * address + * @return uint32_t clock source. + */ +static uint32_t _hal_ll_tim_get_clock_speed( hal_ll_base_addr_t base ); + +/** + * @brief Initialize TIM module on hardware level. + * + * Initializes TIM module on hardware level, based on beforehand + * set configuration and module handler. + * + * @param map - Object specific context handler. + * @return none + * + */ +static void _hal_ll_tim_hw_init( hal_ll_tim_hw_specifics_map_t *map ); + +/** + * @brief Full TIM module initialization procedure. + * + * Initializes TIM module on hardware level, based on beforehand + * set configuration and module handler. Sets adequate pin alternate functions. + * Initializes module clock. + * + * @param map - Object specific context handler. + * @return none + * + */ +static void _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_t *map ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_tim_hw_specifics_map array index. + * + * @param handle - Object specific context handler. + * @return hal_ll_tim_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_tim_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Check if pin is adequate. + * + * Checks tim pin the user has passed with pre-defined + * pin in tim map. + * + * @param pin - TIM pre-defined pin name. + * @return hal_ll_pin_name_t Module index based on pin. + * + * Returns pre-defined module index from pin maps, if pin + * is adequate. + */ +static hal_ll_pin_name_t _hal_ll_tim_check_pin( hal_ll_pin_name_t pin, uint8_t *index, hal_ll_tim_handle_register_t *handle_map ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * TIM pin. + * + * @param[in] module_index TIM HW module index -- 0,1,2... + * @param[in] *index_list Array with TIM map index values + * + * @return None + */ +static void _hal_ll_tim_map_pin( uint8_t module_index, uint8_t index ); + +/** + * @brief Sets TIM pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if TIM is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param map - Object specific context handler. + * + * @param hal_ll_state - Init/De-init + * @return none + * + */ +static void _hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_map_t *map, bool hal_ll_state ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_tim_register_handle( hal_ll_pin_name_t pin, hal_ll_tim_handle_register_t *handle_map, + uint8_t *hal_module_id ) { + + uint8_t index; + uint16_t pin_check_result; + + if ( ( pin_check_result = _hal_ll_tim_check_pin( pin, &index, handle_map ) ) == HAL_LL_PIN_NC ) { + return HAL_LL_TIM_WRONG_PIN; + } + + if ( hal_ll_tim_hw_specifics_map[ pin_check_result ].config.pin != pin ){ + // Clear previous module alternate functions + _hal_ll_tim_alternate_functions_set_state( &hal_ll_tim_hw_specifics_map[ pin_check_result ], false ); + + _hal_ll_tim_map_pin( pin_check_result, index ); + + _hal_ll_tim_alternate_functions_set_state( &hal_ll_tim_hw_specifics_map[ pin_check_result ], true ); + + handle_map[ pin_check_result ].init_ll_state = false; + + hal_ll_module_state[ pin_check_result ].init_ll_state = false; + + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle = ( handle_t * )&hal_ll_tim_hw_specifics_map[ pin_check_result ].base; + + handle_map[ pin_check_result ].hal_ll_tim_handle = ( handle_t *)&hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle; + + return HAL_LL_TIM_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_tim( handle_t *handle ) { + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + hal_ll_tim_handle_register_t *hal_handle = (hal_ll_tim_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_tim_hw_specifics_map_local->module_index; + + _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_local ); + + hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle = (handle_t *)&hal_ll_tim_hw_specifics_map[ pin_check_result ].base; + hal_ll_module_state[ pin_check_result ].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_TIM_SUCCESS; +} + +uint32_t hal_ll_tim_set_freq( handle_t *handle, uint32_t freq_hz ) { + + uint32_t tmp_channel; + uint32_t ck_psc; + uint32_t local_base_addr; + uint32_t local_freq; + uint32_t tmp_freq; + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + if( hal_ll_tim_hw_specifics_map_local->base == HAL_LL_MODULE_ERROR ) { + return HAL_LL_TIM_MODULE_ERROR; + } + + low_level_handle->init_ll_state = false; + + tmp_channel = hal_ll_tim_hw_specifics_map_local->config.channel; + + // If complementary output channel is used. + if ( HAL_LL_TIM_IS_COMPLEMENTARY ) { + // Stop capture/compare. + hal_ll_hw_reg->ccer &= 1UL << tmp_channel * 4 + 2; + } else { + // Stop capture/compare. + hal_ll_hw_reg->ccer &= 1UL << tmp_channel * 4; + } + + // Set TIM duty to 0. + *( &hal_ll_hw_reg->ccr1 + hal_ll_tim_channel_static( tmp_channel ) ) = 0; + + hal_ll_tim_hw_specifics_map_local->freq_hz = freq_hz; + + local_freq = hal_ll_tim_hw_specifics_map_local->freq_hz; + local_base_addr = hal_ll_tim_hw_specifics_map_local->base; + + ck_psc = _hal_ll_tim_get_clock_speed( local_base_addr ) / local_freq; + + if ( ck_psc > UINT16_MAX ) { + tmp_freq = _hal_ll_tim_get_clock_speed( local_base_addr ) / UINT16_MAX; + hal_ll_tim_hw_specifics_map_local->freq_hz = tmp_freq; + } else { + tmp_freq = freq_hz; + hal_ll_tim_hw_specifics_map_local->freq_hz = freq_hz; + } + + _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_local ); + + low_level_handle->init_ll_state = true; + + return tmp_freq; +} + +hal_ll_err_t hal_ll_tim_set_duty( handle_t *handle, float duty_ratio ) { + + float tmp_duty; + uint32_t max_duty = 0; + uint16_t max_period; + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + if ( low_level_handle->init_ll_state == false ) { + hal_ll_tim_start( handle ); + low_level_handle->init_ll_state = true; + } + + tmp_duty = duty_ratio * 100; + max_period = hal_ll_tim_hw_specifics_map_local->max_period; + + max_duty = ( ( float )max_period / 100 ) * tmp_duty; + + *( &hal_ll_hw_reg->ccr1 + hal_ll_tim_channel_static( hal_ll_tim_hw_specifics_map_local->config.channel ) ) = max_duty; + + return HAL_LL_TIM_SUCCESS; +} + +hal_ll_err_t hal_ll_tim_start( handle_t *handle ) { + + uint32_t tmp_channel; + volatile uint32_t tmp, + *tmpPtr; + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + tmp_channel = hal_ll_tim_hw_specifics_map_local->config.channel; + + // Capture/Compare 1 output enable. + tmp = hal_ll_hw_reg->ccer; + + // If complementary output channel is used. + if ( HAL_LL_TIM_IS_COMPLEMENTARY ) { + // Capture/Compare complementary output enable + tmp |= ( 1UL << ( hal_ll_tim_channel_static( tmp_channel ) * 4 + 2 ) ); + // Capture/Compare complementary output polarity(ACTIVE HIGH). + tmp &= ~( 1UL << ( hal_ll_tim_channel_static( tmp_channel ) * 4 + 3 ) ); + } else { + // Capture/Compare output polarity. + tmp |= ( 1UL << ( hal_ll_tim_channel_static( tmp_channel ) * 4 ) ); + // Capture/Compare output polarity(ACTIVE HIGH). + tmp &= ~( 1UL << ( hal_ll_tim_channel_static( tmp_channel ) * 4 + 1 ) ); + } + + hal_ll_hw_reg->ccer = tmp; + + #if defined(TIM_MODULE_1) || defined(TIM_MODULE_8) || defined(TIM_MODULE_20) + // Main output enabled. + set_reg_bit( &hal_ll_hw_reg->bdtr, HAL_LL_TIM_BDTR_MOE_BIT ); + #endif + + tmpPtr = &hal_ll_hw_reg->ccmr1; + + if( hal_ll_tim_channel_static( tmp_channel ) > 1 ) { + tmpPtr = &hal_ll_hw_reg->ccmr2; + } + + if( ( hal_ll_tim_channel_static( tmp_channel ) / 2 ) * 2 != + hal_ll_tim_channel_static( tmp_channel ) ) { + // Clear CCxS, OCxM[0]. + *tmpPtr &= ~( HAL_LL_TIM_CCMR_CC2S_BIT0 | + HAL_LL_TIM_CCMR_CC2S_BIT1 | + HAL_LL_TIM_CCMR_OC2PE | + HAL_LL_TIM_CCMR_OC2M_BIT0 ); + // Set OCxM[2, 1] + *tmpPtr |= HAL_LL_TIM_CCMR_OC2M_BIT1 | HAL_LL_TIM_CCMR_OC2M_BIT2; + } else { + // Clear CCxS, OCxM[0]. + *tmpPtr &= ~( HAL_LL_TIM_CCMR_CC3S_BIT0 | + HAL_LL_TIM_CCMR_CC3S_BIT1 | + HAL_LL_TIM_CCMR_OC3PE | + HAL_LL_TIM_CCMR_OC3M_BIT0 ); + + // Set OCxM[2, 1]. + *tmpPtr |= HAL_LL_TIM_CCMR_OC3M_BIT1 | HAL_LL_TIM_CCMR_OC3M_BIT2; + } + + // Enable counter. + set_reg_bit( &hal_ll_hw_reg->cr1, HAL_LL_TIM_ENABLE_COUNTER_BIT ); + + return HAL_LL_TIM_SUCCESS; +} + +hal_ll_err_t hal_ll_tim_stop( handle_t *handle ) { + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + // If complementary output channel is used. + if ( HAL_LL_TIM_IS_COMPLEMENTARY ) { + hal_ll_hw_reg->ccer &= 1UL << hal_ll_tim_hw_specifics_map_local->config.channel * 4 + 2; + } else { + hal_ll_hw_reg->ccer &= 1UL << hal_ll_tim_hw_specifics_map_local->config.channel * 4; + } + + return HAL_LL_TIM_SUCCESS; +} + +void hal_ll_tim_close( handle_t *handle ) { + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_tim_get_module_state_address); + + if( low_level_handle->hal_ll_tim_handle != NULL ) { + low_level_handle->hal_ll_tim_handle = NULL; + low_level_handle->hal_drv_tim_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_tim_hw_specifics_map_local->max_period = 0; + hal_ll_tim_hw_specifics_map_local->freq_hz = 0; + + _hal_ll_tim_set_clock( hal_ll_tim_hw_specifics_map_local->base, true ); + _hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_map_local, false ); + _hal_ll_tim_set_clock( hal_ll_tim_hw_specifics_map_local->base, false ); + + hal_ll_tim_hw_specifics_map_local->config.pin = HAL_LL_PIN_NC; + hal_ll_tim_hw_specifics_map_local->config.channel = HAL_LL_PIN_NC; + hal_ll_tim_hw_specifics_map_local->config.af = NULL; + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static inline void _hal_ll_tim1_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_1 ); + } else { + clear_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_1 ); + } +} + +static inline void _hal_ll_tim2_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB1ENR1, HAL_LL_TIM_ENABLE_2 ); + } else { + clear_reg_bit( _RCC_APB1ENR1, HAL_LL_TIM_ENABLE_2 ); + } +} + +static inline void _hal_ll_tim3_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB1ENR1, HAL_LL_TIM_ENABLE_3 ); + } else { + clear_reg_bit( _RCC_APB1ENR1, HAL_LL_TIM_ENABLE_3 ); + } +} + +static inline void _hal_ll_tim4_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB1ENR1, HAL_LL_TIM_ENABLE_4 ); + } else { + clear_reg_bit( _RCC_APB1ENR1, HAL_LL_TIM_ENABLE_4 ); + } +} + +static inline void _hal_ll_tim8_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_8 ); + } else { + clear_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_8 ); + } +} + +static inline void _hal_ll_tim15_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_15 ); + } else { + clear_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_15 ); + } +} + +static inline void _hal_ll_tim16_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_16 ); + } else { + clear_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_16 ); + } +} + +static inline void _hal_ll_tim17_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_17 ); + } else { + clear_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_17 ); + } +} + +static inline void _hal_ll_tim20_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_20 ); + } else { + clear_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_20 ); + } +} + + +static hal_ll_pin_name_t _hal_ll_tim_check_pin( hal_ll_pin_name_t pin, uint8_t *index, hal_ll_tim_handle_register_t *handle_map ) { + + hal_ll_pin_name_t pin_num; + uint8_t index_counter = 0; + uint8_t hal_ll_module_id = 0; + uint16_t map_size = ( sizeof( _tim_map ) / sizeof( hal_ll_tim_pin_map_t ) ); + + if ( HAL_LL_PIN_NC == pin ) { + return HAL_LL_PIN_NC; + } + + // Check if the selected pin is valid. + for ( pin_num = 0; pin_num < map_size; pin_num++ ) { + if ( _tim_map[ pin_num ].pin == pin ) { + // Get module number + hal_ll_module_id = _tim_map[ pin_num ].module_index; + if ( NULL == handle_map[hal_ll_module_id].hal_drv_tim_handle ) { + *index = pin_num; + return hal_ll_module_id; + } else if ( TIM_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + // By default return last error msg. + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static hal_ll_tim_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + + uint8_t hal_ll_module_count = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_tim_handle_register_t ) ); + static uint8_t hal_ll_module_error = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_tim_handle_register_t ) ); + + while( hal_ll_module_count-- ) { + if ( hal_ll_tim_get_base_from_hal_handle == hal_ll_tim_hw_specifics_map [ hal_ll_module_count ].base) { + return &hal_ll_tim_hw_specifics_map[ hal_ll_module_count ]; + } + } + + return &hal_ll_tim_hw_specifics_map[ hal_ll_module_error ]; +} + +static void _hal_ll_tim_set_clock( hal_ll_base_addr_t base, bool hal_ll_state ) { + + switch ( ( uint32_t )base ) { // 32-bit base address. + #ifdef TIM_MODULE_1 + case ( HAL_LL_TIM1_BASE_ADDR ): + _hal_ll_tim1_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_2 + case ( HAL_LL_TIM2_BASE_ADDR ): + _hal_ll_tim2_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_3 + case ( HAL_LL_TIM3_BASE_ADDR ): + _hal_ll_tim3_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_4 + case ( HAL_LL_TIM4_BASE_ADDR ): + _hal_ll_tim4_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_8 + case ( HAL_LL_TIM8_BASE_ADDR ): + _hal_ll_tim8_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_15 + case ( HAL_LL_TIM15_BASE_ADDR ): + _hal_ll_tim15_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_16 + case ( HAL_LL_TIM16_BASE_ADDR ): + _hal_ll_tim16_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_17 + case ( HAL_LL_TIM17_BASE_ADDR ): + _hal_ll_tim17_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_20 + case ( HAL_LL_TIM20_BASE_ADDR ): + _hal_ll_tim20_set_clock( hal_ll_state ); + break; + #endif + + } +} + +static uint32_t _hal_ll_tim_clock_source( uint8_t selector ) { + + rcc_clocks_t rcc_clocks; + + RCC_GetClocksFrequency( &rcc_clocks ); + + if( selector == HAL_LL_APB2_TIMER_CLOCK ) { + if( rcc_clocks.hclk/rcc_clocks.pclk2 > 1 ) { + return rcc_clocks.pclk2 * 2; + } else { + return rcc_clocks.pclk2; + } + } + + if( selector == HAL_LL_APB1_TIMER_CLOCK ) { + if( rcc_clocks.hclk/rcc_clocks.pclk1 > 1 ) { + return rcc_clocks.pclk1 * 2; + } else { + return rcc_clocks.pclk1; + } + } + + return 0; +} + +static uint32_t _hal_ll_tim_get_clock_speed( hal_ll_base_addr_t base ) { + + switch ( ( uint32_t )base ) { + #ifdef TIM_MODULE_1 + case ( HAL_LL_TIM1_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM1_BUS ); + break; + #endif + + #ifdef TIM_MODULE_2 + case ( HAL_LL_TIM2_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM2_BUS ); + break; + #endif + + #ifdef TIM_MODULE_3 + case ( HAL_LL_TIM3_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM3_BUS ); + break; + #endif + + #ifdef TIM_MODULE_4 + case ( HAL_LL_TIM4_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM4_BUS ); + break; + #endif + + #ifdef TIM_MODULE_8 + case ( HAL_LL_TIM8_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM8_BUS ); + break; + #endif + + #ifdef TIM_MODULE_15 + case ( HAL_LL_TIM15_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM15_BUS ); + break; + #endif + + #ifdef TIM_MODULE_16 + case ( HAL_LL_TIM16_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM16_BUS ); + break; + #endif + + #ifdef TIM_MODULE_17 + case ( HAL_LL_TIM17_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM17_BUS ); + break; + #endif + + #ifdef TIM_MODULE_20 + case ( HAL_LL_TIM20_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM20_BUS ); + break; + #endif + + } + return 0; +} + +static void _hal_ll_tim_map_pin( uint8_t module_index, uint8_t index ) { + + uint8_t tmp_channel; + + // Map new pin + hal_ll_tim_hw_specifics_map[ module_index ].config.pin = _tim_map[ index ].pin; + tmp_channel = _tim_map[ index ].channel; + hal_ll_tim_hw_specifics_map[ module_index ].config.af = _tim_map[ index ].af; + + if ( tmp_channel >= HAL_LL_TIM_CHANNEL_1N ) { + HAL_LL_TIM_IS_COMPLEMENTARY = true; + hal_ll_tim_hw_specifics_map[ module_index ].config.channel = tmp_channel - 4; + } else { + HAL_LL_TIM_IS_COMPLEMENTARY = false; + hal_ll_tim_hw_specifics_map[ module_index ].config.channel = tmp_channel; + } +} + +static void _hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_map_t *map, bool hal_ll_state ) { + + module_struct module; + uint32_t tim_config = 0; + + if( map->config.pin != HAL_LL_PIN_NC ) { + if( hal_ll_state == false ) { + tim_config = GPIO_CFG_MODE_ALT_FUNCTION | + GPIO_CFG_SPEED_LOW | + GPIO_CFG_OTYPE_PP; + } else { + tim_config = GPIO_CFG_MODE_ALT_FUNCTION | + GPIO_CFG_SPEED_HIGH | + GPIO_CFG_OTYPE_PP; + } + + module.pins[ 0 ] = VALUE( map->config.pin, map->config.af ); + module.pins[ 1 ] = GPIO_MODULE_STRUCT_END; + + module.configs[ 0 ] = tim_config; + module.configs[ 1 ] = GPIO_MODULE_STRUCT_END; + + hal_ll_gpio_module_struct_init( &module, hal_ll_state ); + } +} + +static void _hal_ll_tim_hw_init( hal_ll_tim_hw_specifics_map_t *map ) { + + uint32_t ck_psc; + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( map->base ); + + // Counter used as upcounter. + clear_reg_bit( &hal_ll_hw_reg->cr1, HAL_LL_TIM_CR1_DIR_BIT ); + + // Get clock speed. + ck_psc = _hal_ll_tim_get_clock_speed( map->base ) / map->freq_hz; + + // This should not be the case. ck_psc should not be greater than 65535, which is max value. + if( ck_psc > UINT16_MAX ) { + // In case of duty period beeing greater than 65535 set ck_psc to max value. + ck_psc = UINT16_MAX - 1; // Because of ( ck_psc / UINT16_MAX + 1 ) ), has to be minus 1. + }else if ( ck_psc < 1 ) { + ck_psc = 1; + } + + // Write prescale value. + hal_ll_hw_reg->psc = ( uint16_t )( ck_psc / UINT16_MAX ); + + // Write max count value. + hal_ll_hw_reg->arr = ( uint16_t )( ck_psc/( ck_psc / UINT16_MAX + 1 ) ); + + // Write max period to global array. + map->max_period = ( uint16_t )ck_psc; +} + +static void _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_t *map ) { + + _hal_ll_tim_set_clock( map->base, true ); + + _hal_ll_tim_alternate_functions_set_state( map, true ); + + _hal_ll_tim_hw_init( map ); +} +// ------------------------------------------------------------------------- END + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_89/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_89/CMakeLists.cmake new file mode 100644 index 000000000..14538c572 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_89/CMakeLists.cmake @@ -0,0 +1,9 @@ +if(${MCU_NAME} MATCHES "^STM32G4A1CE$|^STM32G4A1KE$|^STM32G4A1ME$|^STM32G4A1RE$|^STM32G4A1VE$") + set(tim_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_tim.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_89") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_89") + list(APPEND hal_ll_def_list "STM32G4xx") + list(APPEND hal_ll_def_list "STM32G4Axx") + list(APPEND hal_ll_def_list "STM32G4A1xx") + set(tim_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/tim/hal_ll_tim_pin_map/implementations/doc_ds_89") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_89/hal_ll_tim.c b/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_89/hal_ll_tim.c new file mode 100644 index 000000000..65e13891b --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/tim/implementations/doc_ds_89/hal_ll_tim.c @@ -0,0 +1,978 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_tim.c + * @brief TIM HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_gpio.h" +#include "hal_ll_rcc.h" +#include "hal_ll_tim.h" +#include "hal_ll_tim_pin_map.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_tim_handle_register_t hal_ll_module_state[ TIM_MODULE_COUNT ]; + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< CR1 constants. */ +#define HAL_LL_TIM_ENABLE_COUNTER_BIT 0 +#define HAL_LL_TIM_BDTR_MOE_BIT 15 +#define HAL_LL_TIM_BDTR_MOE 0x8000 + +#define HAL_LL_TIM_CCMR_CC2S_BIT0 0x100u +#define HAL_LL_TIM_CCMR_CC2S_BIT1 0x200u +#define HAL_LL_TIM_CCMR_OC2PE 0x800u +#define HAL_LL_TIM_CCMR_OC2M_BIT0 0x1000u +#define HAL_LL_TIM_CCMR_OC2M_BIT1 0x2000u +#define HAL_LL_TIM_CCMR_OC2M_BIT2 0x4000u + +#define HAL_LL_TIM_CCMR_CC3S_BIT0 0x1u +#define HAL_LL_TIM_CCMR_CC3S_BIT1 0x2u +#define HAL_LL_TIM_CCMR_OC3PE 0x8u +#define HAL_LL_TIM_CCMR_OC3M_BIT0 0x10u +#define HAL_LL_TIM_CCMR_OC3M_BIT1 0x20u +#define HAL_LL_TIM_CCMR_OC3M_BIT2 0x40u + +#define HAL_LL_TIM_CR1_DIR 0x10 +#define HAL_LL_TIM_CR1_DIR_BIT 4 + +#define HAL_LL_TIM_ENABLE_1 11 + +#define HAL_LL_TIM_ENABLE_2 0 + +#define HAL_LL_TIM_ENABLE_3 1 + +#define HAL_LL_TIM_ENABLE_4 2 + +#define HAL_LL_TIM_ENABLE_8 13 + +#define HAL_LL_TIM_ENABLE_15 16 + +#define HAL_LL_TIM_ENABLE_16 17 + +#define HAL_LL_TIM_ENABLE_17 18 + +#define HAL_LL_TIM_ENABLE_20 20 + + +#define HAL_LL_APB2_TIMER_CLOCK 2 + +#define HAL_LL_APB1_TIMER_CLOCK 1 + + + +#define hal_ll_tim_channel_static( _chn ) ( _chn-1 ) + +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_tim_get_base_struct(_handle) ((hal_ll_tim_base_handle_t *)_handle) + +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_tim_get_module_state_address ((hal_ll_tim_handle_register_t *)*handle) + +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_tim_get_handle ( hal_ll_tim_handle_register_t * )hal_ll_tim_get_module_state_address->hal_ll_tim_handle + +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_tim_get_base_from_hal_handle ((hal_ll_tim_hw_specifics_map_t *)((hal_ll_tim_handle_register_t *)\ + (((hal_ll_tim_handle_register_t *)(handle))->hal_ll_tim_handle))->hal_ll_tim_handle)->base + +// -------------------------------------------------------------- PRIVATE TYPES +/*!< @brief TIM register structure. */ +typedef struct +{ + uint32_t cr1; /* Address offset 0x00 */ + uint32_t cr2; /* Address offset 0x04 */ + uint32_t smcr; /* Address offset 0x08 */ + uint32_t dier; /* Address offset 0x0C */ + uint32_t sr; /* Address offset 0x10 */ + uint32_t egr; /* Address offset 0x14 */ + uint32_t ccmr1; /* Address offset 0x18 */ + uint32_t ccmr2; /* Address offset 0x1C */ + uint32_t ccer; /* Address offset 0x20 */ + uint32_t cnt; /* Address offset 0x24 */ + uint32_t psc; /* Address offset 0x28 */ + uint32_t arr; /* Address offset 0x2C */ + uint32_t rcr; /* Address offset 0x30 */ + uint32_t ccr1; /* Address offset 0x34 */ + uint32_t ccr2; /* Address offset 0x38 */ + uint32_t ccr3; /* Address offset 0x3C */ + uint32_t ccr4; /* Address offset 0x40 */ + uint32_t bdtr; /* Address offset 0x44 */ + uint32_t dcr; /* Address offset 0x48 */ + uint32_t dmar; /* Address offset 0x4C */ + uint32_t tim2_5_or; /* Address offset 0x50 */ +} hal_ll_tim_base_handle_t; + +/*!< @brief TIM pin structure */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_channel_t channel; + uint32_t af; +} hal_ll_tim_t; + +/*!< @brief TIM hw specific structure */ +typedef struct +{ + hal_ll_base_addr_t base; + hal_ll_tim_t config; + uint16_t max_period; + uint32_t freq_hz; + hal_ll_pin_name_t module_index; +} hal_ll_tim_hw_specifics_map_t; + +/*!< @brief TIM hw specific error values */ +typedef enum +{ + HAL_LL_TIM_SUCCESS = 0, + HAL_LL_TIM_MODULE_ERROR, + HAL_LL_TIM_WRONG_PIN, + + HAL_LL_TIM_ERROR = (-1) +} hal_ll_tim_err_t; + +// ------------------------------------------------------------------ VARIABLES +/*!< @brief TIM specific info */ +static hal_ll_tim_hw_specifics_map_t hal_ll_tim_hw_specifics_map[] = +{ + #ifdef TIM_MODULE_1 + {HAL_LL_TIM1_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_1 - 1}, + #endif + + #ifdef TIM_MODULE_2 + {HAL_LL_TIM2_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_2 - 1}, + #endif + + #ifdef TIM_MODULE_3 + {HAL_LL_TIM3_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_3 - 1}, + #endif + + #ifdef TIM_MODULE_4 + {HAL_LL_TIM4_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_4 - 1}, + #endif + + #ifdef TIM_MODULE_8 + {HAL_LL_TIM8_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_8 - 1}, + #endif + + #ifdef TIM_MODULE_15 + {HAL_LL_TIM15_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_15 - 1}, + #endif + + #ifdef TIM_MODULE_16 + {HAL_LL_TIM16_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_16 - 1}, + #endif + + #ifdef TIM_MODULE_17 + {HAL_LL_TIM17_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_17 - 1}, + #endif + + #ifdef TIM_MODULE_20 + {HAL_LL_TIM20_BASE_ADDR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, TIM_MODULE_20 - 1}, + #endif + + + {HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, HAL_LL_PIN_NC} +}; + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_tim_handle_register_t *low_level_handle; +static volatile hal_ll_tim_hw_specifics_map_t *hal_ll_tim_hw_specifics_map_local; + +static bool HAL_LL_TIM_IS_COMPLEMENTARY; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Enable TIM module 1 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim1_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 2 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim2_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 3 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim3_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 4 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim4_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 8 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim8_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 15 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim15_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 16 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim16_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 17 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim17_set_clock( bool hal_ll_state ); + +/** + * @brief Enable TIM module 20 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @return none + */ +static inline void _hal_ll_tim20_set_clock( bool hal_ll_state ); + + +/** + * @brief Enable TIM module gate clock. + * @param base - TIM module base + * address + * @return None + */ +static void _hal_ll_tim_set_clock( hal_ll_base_addr_t base, bool hal_ll_state ); + +/** + * @brief Select TIM clock source + * @param selector - clock source selector + * @return uint32_t - clock source + */ +static uint32_t _hal_ll_tim_clock_source( uint8_t selector ); + +/** + * @brief Based on selected TIM, + * return clock speed. + * @param base - TIM module base + * address + * @return uint32_t clock source. + */ +static uint32_t _hal_ll_tim_get_clock_speed( hal_ll_base_addr_t base ); + +/** + * @brief Initialize TIM module on hardware level. + * + * Initializes TIM module on hardware level, based on beforehand + * set configuration and module handler. + * + * @param map - Object specific context handler. + * @return none + * + */ +static void _hal_ll_tim_hw_init( hal_ll_tim_hw_specifics_map_t *map ); + +/** + * @brief Full TIM module initialization procedure. + * + * Initializes TIM module on hardware level, based on beforehand + * set configuration and module handler. Sets adequate pin alternate functions. + * Initializes module clock. + * + * @param map - Object specific context handler. + * @return none + * + */ +static void _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_t *map ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_tim_hw_specifics_map array index. + * + * @param handle - Object specific context handler. + * @return hal_ll_tim_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_tim_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Check if pin is adequate. + * + * Checks tim pin the user has passed with pre-defined + * pin in tim map. + * + * @param pin - TIM pre-defined pin name. + * @return hal_ll_pin_name_t Module index based on pin. + * + * Returns pre-defined module index from pin maps, if pin + * is adequate. + */ +static hal_ll_pin_name_t _hal_ll_tim_check_pin( hal_ll_pin_name_t pin, uint8_t *index, hal_ll_tim_handle_register_t *handle_map ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * TIM pin. + * + * @param[in] module_index TIM HW module index -- 0,1,2... + * @param[in] *index_list Array with TIM map index values + * + * @return None + */ +static void _hal_ll_tim_map_pin( uint8_t module_index, uint8_t index ); + +/** + * @brief Sets TIM pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if TIM is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param map - Object specific context handler. + * + * @param hal_ll_state - Init/De-init + * @return none + * + */ +static void _hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_map_t *map, bool hal_ll_state ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_tim_register_handle( hal_ll_pin_name_t pin, hal_ll_tim_handle_register_t *handle_map, + uint8_t *hal_module_id ) { + + uint8_t index; + uint16_t pin_check_result; + + if ( ( pin_check_result = _hal_ll_tim_check_pin( pin, &index, handle_map ) ) == HAL_LL_PIN_NC ) { + return HAL_LL_TIM_WRONG_PIN; + } + + if ( hal_ll_tim_hw_specifics_map[ pin_check_result ].config.pin != pin ){ + // Clear previous module alternate functions + _hal_ll_tim_alternate_functions_set_state( &hal_ll_tim_hw_specifics_map[ pin_check_result ], false ); + + _hal_ll_tim_map_pin( pin_check_result, index ); + + _hal_ll_tim_alternate_functions_set_state( &hal_ll_tim_hw_specifics_map[ pin_check_result ], true ); + + handle_map[ pin_check_result ].init_ll_state = false; + + hal_ll_module_state[ pin_check_result ].init_ll_state = false; + + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle = ( handle_t * )&hal_ll_tim_hw_specifics_map[ pin_check_result ].base; + + handle_map[ pin_check_result ].hal_ll_tim_handle = ( handle_t *)&hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle; + + return HAL_LL_TIM_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_tim( handle_t *handle ) { + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + hal_ll_tim_handle_register_t *hal_handle = (hal_ll_tim_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_tim_hw_specifics_map_local->module_index; + + _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_local ); + + hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle = (handle_t *)&hal_ll_tim_hw_specifics_map[ pin_check_result ].base; + hal_ll_module_state[ pin_check_result ].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_TIM_SUCCESS; +} + +uint32_t hal_ll_tim_set_freq( handle_t *handle, uint32_t freq_hz ) { + + uint32_t tmp_channel; + uint32_t ck_psc; + uint32_t local_base_addr; + uint32_t local_freq; + uint32_t tmp_freq; + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + if( hal_ll_tim_hw_specifics_map_local->base == HAL_LL_MODULE_ERROR ) { + return HAL_LL_TIM_MODULE_ERROR; + } + + low_level_handle->init_ll_state = false; + + tmp_channel = hal_ll_tim_hw_specifics_map_local->config.channel; + + // If complementary output channel is used. + if ( HAL_LL_TIM_IS_COMPLEMENTARY ) { + // Stop capture/compare. + hal_ll_hw_reg->ccer &= 1UL << tmp_channel * 4 + 2; + } else { + // Stop capture/compare. + hal_ll_hw_reg->ccer &= 1UL << tmp_channel * 4; + } + + // Set TIM duty to 0. + *( &hal_ll_hw_reg->ccr1 + hal_ll_tim_channel_static( tmp_channel ) ) = 0; + + hal_ll_tim_hw_specifics_map_local->freq_hz = freq_hz; + + local_freq = hal_ll_tim_hw_specifics_map_local->freq_hz; + local_base_addr = hal_ll_tim_hw_specifics_map_local->base; + + ck_psc = _hal_ll_tim_get_clock_speed( local_base_addr ) / local_freq; + + if ( ck_psc > UINT16_MAX ) { + tmp_freq = _hal_ll_tim_get_clock_speed( local_base_addr ) / UINT16_MAX; + hal_ll_tim_hw_specifics_map_local->freq_hz = tmp_freq; + } else { + tmp_freq = freq_hz; + hal_ll_tim_hw_specifics_map_local->freq_hz = freq_hz; + } + + _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_local ); + + low_level_handle->init_ll_state = true; + + return tmp_freq; +} + +hal_ll_err_t hal_ll_tim_set_duty( handle_t *handle, float duty_ratio ) { + + float tmp_duty; + uint32_t max_duty = 0; + uint16_t max_period; + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + if ( low_level_handle->init_ll_state == false ) { + hal_ll_tim_start( handle ); + low_level_handle->init_ll_state = true; + } + + tmp_duty = duty_ratio * 100; + max_period = hal_ll_tim_hw_specifics_map_local->max_period; + + max_duty = ( ( float )max_period / 100 ) * tmp_duty; + + *( &hal_ll_hw_reg->ccr1 + hal_ll_tim_channel_static( hal_ll_tim_hw_specifics_map_local->config.channel ) ) = max_duty; + + return HAL_LL_TIM_SUCCESS; +} + +hal_ll_err_t hal_ll_tim_start( handle_t *handle ) { + + uint32_t tmp_channel; + volatile uint32_t tmp, + *tmpPtr; + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + tmp_channel = hal_ll_tim_hw_specifics_map_local->config.channel; + + // Capture/Compare 1 output enable. + tmp = hal_ll_hw_reg->ccer; + + // If complementary output channel is used. + if ( HAL_LL_TIM_IS_COMPLEMENTARY ) { + // Capture/Compare complementary output enable + tmp |= ( 1UL << ( hal_ll_tim_channel_static( tmp_channel ) * 4 + 2 ) ); + // Capture/Compare complementary output polarity(ACTIVE HIGH). + tmp &= ~( 1UL << ( hal_ll_tim_channel_static( tmp_channel ) * 4 + 3 ) ); + } else { + // Capture/Compare output polarity. + tmp |= ( 1UL << ( hal_ll_tim_channel_static( tmp_channel ) * 4 ) ); + // Capture/Compare output polarity(ACTIVE HIGH). + tmp &= ~( 1UL << ( hal_ll_tim_channel_static( tmp_channel ) * 4 + 1 ) ); + } + + hal_ll_hw_reg->ccer = tmp; + + #if defined(TIM_MODULE_1) || defined(TIM_MODULE_8) || defined(TIM_MODULE_20) + // Main output enabled. + set_reg_bit( &hal_ll_hw_reg->bdtr, HAL_LL_TIM_BDTR_MOE_BIT ); + #endif + + tmpPtr = &hal_ll_hw_reg->ccmr1; + + if( hal_ll_tim_channel_static( tmp_channel ) > 1 ) { + tmpPtr = &hal_ll_hw_reg->ccmr2; + } + + if( ( hal_ll_tim_channel_static( tmp_channel ) / 2 ) * 2 != + hal_ll_tim_channel_static( tmp_channel ) ) { + // Clear CCxS, OCxM[0]. + *tmpPtr &= ~( HAL_LL_TIM_CCMR_CC2S_BIT0 | + HAL_LL_TIM_CCMR_CC2S_BIT1 | + HAL_LL_TIM_CCMR_OC2PE | + HAL_LL_TIM_CCMR_OC2M_BIT0 ); + // Set OCxM[2, 1] + *tmpPtr |= HAL_LL_TIM_CCMR_OC2M_BIT1 | HAL_LL_TIM_CCMR_OC2M_BIT2; + } else { + // Clear CCxS, OCxM[0]. + *tmpPtr &= ~( HAL_LL_TIM_CCMR_CC3S_BIT0 | + HAL_LL_TIM_CCMR_CC3S_BIT1 | + HAL_LL_TIM_CCMR_OC3PE | + HAL_LL_TIM_CCMR_OC3M_BIT0 ); + + // Set OCxM[2, 1]. + *tmpPtr |= HAL_LL_TIM_CCMR_OC3M_BIT1 | HAL_LL_TIM_CCMR_OC3M_BIT2; + } + + // Enable counter. + set_reg_bit( &hal_ll_hw_reg->cr1, HAL_LL_TIM_ENABLE_COUNTER_BIT ); + + return HAL_LL_TIM_SUCCESS; +} + +hal_ll_err_t hal_ll_tim_stop( handle_t *handle ) { + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + // If complementary output channel is used. + if ( HAL_LL_TIM_IS_COMPLEMENTARY ) { + hal_ll_hw_reg->ccer &= 1UL << hal_ll_tim_hw_specifics_map_local->config.channel * 4 + 2; + } else { + hal_ll_hw_reg->ccer &= 1UL << hal_ll_tim_hw_specifics_map_local->config.channel * 4; + } + + return HAL_LL_TIM_SUCCESS; +} + +void hal_ll_tim_close( handle_t *handle ) { + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_tim_get_module_state_address); + + if( low_level_handle->hal_ll_tim_handle != NULL ) { + low_level_handle->hal_ll_tim_handle = NULL; + low_level_handle->hal_drv_tim_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_tim_hw_specifics_map_local->max_period = 0; + hal_ll_tim_hw_specifics_map_local->freq_hz = 0; + + _hal_ll_tim_set_clock( hal_ll_tim_hw_specifics_map_local->base, true ); + _hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_map_local, false ); + _hal_ll_tim_set_clock( hal_ll_tim_hw_specifics_map_local->base, false ); + + hal_ll_tim_hw_specifics_map_local->config.pin = HAL_LL_PIN_NC; + hal_ll_tim_hw_specifics_map_local->config.channel = HAL_LL_PIN_NC; + hal_ll_tim_hw_specifics_map_local->config.af = NULL; + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static inline void _hal_ll_tim1_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_1 ); + } else { + clear_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_1 ); + } +} + +static inline void _hal_ll_tim2_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB1ENR1, HAL_LL_TIM_ENABLE_2 ); + } else { + clear_reg_bit( _RCC_APB1ENR1, HAL_LL_TIM_ENABLE_2 ); + } +} + +static inline void _hal_ll_tim3_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB1ENR1, HAL_LL_TIM_ENABLE_3 ); + } else { + clear_reg_bit( _RCC_APB1ENR1, HAL_LL_TIM_ENABLE_3 ); + } +} + +static inline void _hal_ll_tim4_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB1ENR1, HAL_LL_TIM_ENABLE_4 ); + } else { + clear_reg_bit( _RCC_APB1ENR1, HAL_LL_TIM_ENABLE_4 ); + } +} + +static inline void _hal_ll_tim8_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_8 ); + } else { + clear_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_8 ); + } +} + +static inline void _hal_ll_tim15_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_15 ); + } else { + clear_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_15 ); + } +} + +static inline void _hal_ll_tim16_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_16 ); + } else { + clear_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_16 ); + } +} + +static inline void _hal_ll_tim17_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_17 ); + } else { + clear_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_17 ); + } +} + +static inline void _hal_ll_tim20_set_clock( bool hal_ll_state ) { + if( hal_ll_state ) { + set_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_20 ); + } else { + clear_reg_bit( _RCC_APB2ENR, HAL_LL_TIM_ENABLE_20 ); + } +} + + +static hal_ll_pin_name_t _hal_ll_tim_check_pin( hal_ll_pin_name_t pin, uint8_t *index, hal_ll_tim_handle_register_t *handle_map ) { + + hal_ll_pin_name_t pin_num; + uint8_t index_counter = 0; + uint8_t hal_ll_module_id = 0; + uint16_t map_size = ( sizeof( _tim_map ) / sizeof( hal_ll_tim_pin_map_t ) ); + + if ( HAL_LL_PIN_NC == pin ) { + return HAL_LL_PIN_NC; + } + + // Check if the selected pin is valid. + for ( pin_num = 0; pin_num < map_size; pin_num++ ) { + if ( _tim_map[ pin_num ].pin == pin ) { + // Get module number + hal_ll_module_id = _tim_map[ pin_num ].module_index; + if ( NULL == handle_map[hal_ll_module_id].hal_drv_tim_handle ) { + *index = pin_num; + return hal_ll_module_id; + } else if ( TIM_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + // By default return last error msg. + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static hal_ll_tim_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + + uint8_t hal_ll_module_count = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_tim_handle_register_t ) ); + static uint8_t hal_ll_module_error = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_tim_handle_register_t ) ); + + while( hal_ll_module_count-- ) { + if ( hal_ll_tim_get_base_from_hal_handle == hal_ll_tim_hw_specifics_map [ hal_ll_module_count ].base) { + return &hal_ll_tim_hw_specifics_map[ hal_ll_module_count ]; + } + } + + return &hal_ll_tim_hw_specifics_map[ hal_ll_module_error ]; +} + +static void _hal_ll_tim_set_clock( hal_ll_base_addr_t base, bool hal_ll_state ) { + + switch ( ( uint32_t )base ) { // 32-bit base address. + #ifdef TIM_MODULE_1 + case ( HAL_LL_TIM1_BASE_ADDR ): + _hal_ll_tim1_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_2 + case ( HAL_LL_TIM2_BASE_ADDR ): + _hal_ll_tim2_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_3 + case ( HAL_LL_TIM3_BASE_ADDR ): + _hal_ll_tim3_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_4 + case ( HAL_LL_TIM4_BASE_ADDR ): + _hal_ll_tim4_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_8 + case ( HAL_LL_TIM8_BASE_ADDR ): + _hal_ll_tim8_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_15 + case ( HAL_LL_TIM15_BASE_ADDR ): + _hal_ll_tim15_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_16 + case ( HAL_LL_TIM16_BASE_ADDR ): + _hal_ll_tim16_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_17 + case ( HAL_LL_TIM17_BASE_ADDR ): + _hal_ll_tim17_set_clock( hal_ll_state ); + break; + #endif + + #ifdef TIM_MODULE_20 + case ( HAL_LL_TIM20_BASE_ADDR ): + _hal_ll_tim20_set_clock( hal_ll_state ); + break; + #endif + + } +} + +static uint32_t _hal_ll_tim_clock_source( uint8_t selector ) { + + rcc_clocks_t rcc_clocks; + + RCC_GetClocksFrequency( &rcc_clocks ); + + if( selector == HAL_LL_APB2_TIMER_CLOCK ) { + if( rcc_clocks.hclk/rcc_clocks.pclk2 > 1 ) { + return rcc_clocks.pclk2 * 2; + } else { + return rcc_clocks.pclk2; + } + } + + if( selector == HAL_LL_APB1_TIMER_CLOCK ) { + if( rcc_clocks.hclk/rcc_clocks.pclk1 > 1 ) { + return rcc_clocks.pclk1 * 2; + } else { + return rcc_clocks.pclk1; + } + } + + return 0; +} + +static uint32_t _hal_ll_tim_get_clock_speed( hal_ll_base_addr_t base ) { + + switch ( ( uint32_t )base ) { + #ifdef TIM_MODULE_1 + case ( HAL_LL_TIM1_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM1_BUS ); + break; + #endif + + #ifdef TIM_MODULE_2 + case ( HAL_LL_TIM2_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM2_BUS ); + break; + #endif + + #ifdef TIM_MODULE_3 + case ( HAL_LL_TIM3_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM3_BUS ); + break; + #endif + + #ifdef TIM_MODULE_4 + case ( HAL_LL_TIM4_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM4_BUS ); + break; + #endif + + #ifdef TIM_MODULE_8 + case ( HAL_LL_TIM8_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM8_BUS ); + break; + #endif + + #ifdef TIM_MODULE_15 + case ( HAL_LL_TIM15_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM15_BUS ); + break; + #endif + + #ifdef TIM_MODULE_16 + case ( HAL_LL_TIM16_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM16_BUS ); + break; + #endif + + #ifdef TIM_MODULE_17 + case ( HAL_LL_TIM17_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM17_BUS ); + break; + #endif + + #ifdef TIM_MODULE_20 + case ( HAL_LL_TIM20_BASE_ADDR ): + return _hal_ll_tim_clock_source( TIM20_BUS ); + break; + #endif + + } + return 0; +} + +static void _hal_ll_tim_map_pin( uint8_t module_index, uint8_t index ) { + + uint8_t tmp_channel; + + // Map new pin + hal_ll_tim_hw_specifics_map[ module_index ].config.pin = _tim_map[ index ].pin; + tmp_channel = _tim_map[ index ].channel; + hal_ll_tim_hw_specifics_map[ module_index ].config.af = _tim_map[ index ].af; + + if ( tmp_channel >= HAL_LL_TIM_CHANNEL_1N ) { + HAL_LL_TIM_IS_COMPLEMENTARY = true; + hal_ll_tim_hw_specifics_map[ module_index ].config.channel = tmp_channel - 4; + } else { + HAL_LL_TIM_IS_COMPLEMENTARY = false; + hal_ll_tim_hw_specifics_map[ module_index ].config.channel = tmp_channel; + } +} + +static void _hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_map_t *map, bool hal_ll_state ) { + + module_struct module; + uint32_t tim_config = 0; + + if( map->config.pin != HAL_LL_PIN_NC ) { + if( hal_ll_state == false ) { + tim_config = GPIO_CFG_MODE_ALT_FUNCTION | + GPIO_CFG_SPEED_LOW | + GPIO_CFG_OTYPE_PP; + } else { + tim_config = GPIO_CFG_MODE_ALT_FUNCTION | + GPIO_CFG_SPEED_HIGH | + GPIO_CFG_OTYPE_PP; + } + + module.pins[ 0 ] = VALUE( map->config.pin, map->config.af ); + module.pins[ 1 ] = GPIO_MODULE_STRUCT_END; + + module.configs[ 0 ] = tim_config; + module.configs[ 1 ] = GPIO_MODULE_STRUCT_END; + + hal_ll_gpio_module_struct_init( &module, hal_ll_state ); + } +} + +static void _hal_ll_tim_hw_init( hal_ll_tim_hw_specifics_map_t *map ) { + + uint32_t ck_psc; + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( map->base ); + + // Counter used as upcounter. + clear_reg_bit( &hal_ll_hw_reg->cr1, HAL_LL_TIM_CR1_DIR_BIT ); + + // Get clock speed. + ck_psc = _hal_ll_tim_get_clock_speed( map->base ) / map->freq_hz; + + // This should not be the case. ck_psc should not be greater than 65535, which is max value. + if( ck_psc > UINT16_MAX ) { + // In case of duty period beeing greater than 65535 set ck_psc to max value. + ck_psc = UINT16_MAX - 1; // Because of ( ck_psc / UINT16_MAX + 1 ) ), has to be minus 1. + }else if ( ck_psc < 1 ) { + ck_psc = 1; + } + + // Write prescale value. + hal_ll_hw_reg->psc = ( uint16_t )( ck_psc / UINT16_MAX ); + + // Write max count value. + hal_ll_hw_reg->arr = ( uint16_t )( ck_psc/( ck_psc / UINT16_MAX + 1 ) ); + + // Write max period to global array. + map->max_period = ( uint16_t )ck_psc; +} + +static void _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_t *map ) { + + _hal_ll_tim_set_clock( map->base, true ); + + _hal_ll_tim_alternate_functions_set_state( map, true ); + + _hal_ll_tim_hw_init( map ); +} +// ------------------------------------------------------------------------- END + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/uart/CMakeLists.txt b/targets/arm/mikroe/ai_generated/stm32/src/uart/CMakeLists.txt new file mode 100644 index 000000000..afe97a083 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/uart/CMakeLists.txt @@ -0,0 +1,75 @@ +## ./targets/arm/mikroe/ai_generated/stm32/src/uart/CMakeLists.txt + +## Check if current module is generated or not +set(MODULE_IS_GENERATED false) +get_files_recurse(${CMAKE_CURRENT_LIST_DIR}/implementations CMAKE_FILES cmake) +check_if_module_is_generated(MODULE_IS_GENERATED "${CMAKE_FILES}") + +## If current MCU has this module, add it +if(MODULE_IS_GENERATED) + set(hal_ll_def_list "") + set(mcu_header_path "") + + find_cortex(hal_ll_def_list) + list(APPEND hal_ll_def_list ${MCU_NAME}) + set(mcu_header_path ${MCU_NAME}_${_MSDK_PACKAGE_ID_}) + + ## BEGIN UART + list(APPEND hal_ll_def_list "MACRO_USAGE_UART") + + ## i.e "if (${MCU_NAME} MATCHES "^STM32C011F6$|^STM32C011C6$")" + ## List all MCUs and or them in the regex + foreach(cmakeFile ${CMAKE_FILES}) + include(${cmakeFile}) + endforeach() + ## END UART + + mikrosdk_add_library(lib_hal_ll_uart MikroSDK.HalLowLevel.UART + ${rcc_subimplementation}/hal_ll_rcc.h + ../../include/hal_ll_target.h + # BEGIN UART + ${uart_subimplementation} + ../../include/uart/hal_ll_uart.h + ${uart_pin_map}/hal_ll_uart_pin_map.h + # END UART + ) + + target_compile_definitions(lib_hal_ll_uart PUBLIC + ${hal_ll_def_list} + ) + + target_link_libraries(lib_hal_ll_uart PUBLIC + MikroC.Core + MikroSDK.HalLowLevelCore + MikroSDK.HalLowLevelCommon + ) + + string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) + target_include_directories(lib_hal_ll_uart + PRIVATE + ../../include + ../../include/gpio + ${gpio_subimplementation_include_dir} + # BEGIN UART + ../../include/uart + ${uart_pin_map} + # END UART + # BEGIN RCC + ${rcc_subimplementation} + # END RCC + INTERFACE + # BUILD + $ + $ + $ + $ + $ + $ + # INSTALL + $ + $ + ) + + mikrosdk_install(MikroSDK.HalLowLevel.UART) + install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.UART ../../include/uart/hal_ll_uart.h) +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_1/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_1/CMakeLists.cmake new file mode 100644 index 000000000..a32c7a72b --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_1/CMakeLists.cmake @@ -0,0 +1,9 @@ +if(${MCU_NAME} MATCHES "^STM32C011F4$|^STM32C011J4$|^STM32C011F6$|^STM32C011J6$|^STM32C011D6$") + set(uart_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_uart.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_1") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_1") + list(APPEND hal_ll_def_list "STM32C0xx") + list(APPEND hal_ll_def_list "STM32C01xx") + list(APPEND hal_ll_def_list "STM32C011xx") + set(uart_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/uart/hal_ll_uart_pin_map/implementations/doc_ds_1") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_1/hal_ll_uart.c b/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_1/hal_ll_uart.c new file mode 100644 index 000000000..37120f16a --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_1/hal_ll_uart.c @@ -0,0 +1,1079 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_uart.c + * @brief UART HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_rcc.h" +#include "hal_ll_uart.h" +#include "hal_ll_gpio.h" +#include "hal_ll_core.h" +#include "hal_ll_core_defines.h" +#include "hal_ll_uart_pin_map.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_uart_handle_register_t hal_ll_module_state[UART_MODULE_COUNT] = { (handle_t *)NULL, (handle_t *)NULL, false }; + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_uart_get_module_state_address ((hal_ll_uart_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_uart_get_handle (hal_ll_uart_handle_register_t *)hal_ll_uart_get_module_state_address->hal_ll_uart_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_uart_get_base_struct(_handle) ((hal_ll_uart_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_uart_get_base_from_hal_handle ((hal_ll_uart_hw_specifics_map_t *)((hal_ll_uart_handle_register_t *)\ + (((hal_ll_uart_handle_register_t *)(handle))->hal_ll_uart_handle))->hal_ll_uart_handle)->base + +/*!< @brief Macros used for calculating actual baud rate value and error value */ +#define HAL_LL_UART_ACCEPTABLE_ERROR (float)1.0 +#define hal_ll_uart_get_baud(_clock,_baud,_div) (((_clock/(float)_baud)/_div)-1) +#define hal_ll_uart_get_real_baud(_clock,_baud,_div) (_clock/(_div*(_baud+1))) +#define hal_ll_uart_get_baud_error(_baud_real,_baud) (((float)(abs(_baud_real-_baud))/_baud)*100) + +/*!< @brief Macros defining bit location */ +#define HAL_LL_USART1EN 14 + +#define HAL_LL_USART2EN 17 + + +#define HAL_LL_UART_CR1_UE 0 +#define HAL_LL_UART_CR1_TE 3 +#define HAL_LL_UART_CR1_RE 2 + +#define HAL_LL_UART_SR_RXNE 5 +#define HAL_LL_UART_SR_TXE 7 + +/*!< @brief Macros defining register bit values */ +#define STOP_BITS_HALF 0x1000U +#define STOP_BITS_ONE 0x00U +#define STOP_BITS_ONE_AND_A_HALF 0x3000U +#define STOP_BITS_TWO 0x2000U + +#define DATA_BIT_7 0x10000000U +#define DATA_BIT_8 0x00U +#define DATA_BIT_9 0x1000U + +#define PARITY_NO 0x00U +#define PARITY_ENABLED 0x400U + +#define PARITY_EVEN 0x00U +#define PARITY_ODD 0x200U + +/*!< @brief Macro used for setting pin alternate functions */ +#define HAL_LL_UART_AF_CONFIG (GPIO_CFG_MODE_ALT_FUNCTION | GPIO_CFG_SPEED_HIGH | GPIO_CFG_OTYPE_PP) + +/*!< @brief Macros used for interrupts */ +#define HAL_LL_UART_IT_MASK 0xFFFFUL +#define HAL_LL_UART_IT_CLEAR_MASK 0x123bffU +#define HAL_LL_UART_IT_CR1_MASK 0x1f0U +#define HAL_LL_UART_IT_CR2_MASK 0x40U +#define HAL_LL_UART_IT_CR3_MASK 0x401U + +#define HAL_LL_UART_CR1_REG_INDEX 1 +#define HAL_LL_UART_CR2_REG_INDEX 2 +#define HAL_LL_UART_CR3_REG_INDEX 3 + +#define HAL_LL_UART_IT_PE 0x100U +#define HAL_LL_UART_IT_TXE (0x10000000 | 0x80U) +#define HAL_LL_UART_IT_TC 0x40U +#define HAL_LL_UART_IT_RXNE (0x10000000 | 0x20U) +#define HAL_LL_UART_IT_IDLE 0x10U +#define HAL_LL_UART_IT_LBD 0x40U +#define HAL_LL_UART_IT_CTS 0x400U +#define HAL_LL_UART_IT_ERR 0x01U + +#define HAL_LL_UART_STATUS_RXNE_FLAG 0x20U +#define HAL_LL_UART_STATUS_TXE_FLAG 0x80U + +/*!< @brief Macro used for status registed flag check + * Used in interrupt handlers. + */ +#define hal_ll_uart_get_status_flags(_handle,_flag) (((hal_ll_uart_base_handle_t *)_handle)->isr & _flag) + +/*!< @brief Macro used for status register flag clearing + * Used in interrupt handlers. + */ +#define hal_ll_uart_clear_status_flag(_handle,_flag) (set_reg_bit( &(((hal_ll_uart_base_handle_t *)_handle)->icr), ( _flag & HAL_LL_UART_IT_CLEAR_MASK ) ) ) + +/*!< @brief Macro used for module interrupt enabling. + * Used in interrupt handlers. + */ +#define __HAL_LL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__ >> 28UL) == HAL_LL_UART_CR1_REG_INDEX)? (__HANDLE__->cr1 |= (__INTERRUPT__ & HAL_LL_UART_IT_MASK)): \ + ((__INTERRUPT__ >> 28UL) == HAL_LL_UART_CR2_REG_INDEX)? (__HANDLE__->cr2 |= (__INTERRUPT__ & HAL_LL_UART_IT_MASK)): \ + (__HANDLE__->cr3 |= (__INTERRUPT__ & HAL_LL_UART_IT_MASK))) + +/*!< @brief Macro used for module interrupt disabling. + * Used in interrupt handlers. + */ +#define __HAL_LL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__ >> 28UL) == HAL_LL_UART_CR1_REG_INDEX)? (__HANDLE__->cr1 &= ~(__INTERRUPT__ & HAL_LL_UART_IT_MASK)): \ + ((__INTERRUPT__ >> 28UL) == HAL_LL_UART_CR2_REG_INDEX)? (__HANDLE__->cr2 &= ~(__INTERRUPT__ & HAL_LL_UART_IT_MASK)): \ + (__HANDLE__->cr3 &= ~ (__INTERRUPT__ & HAL_LL_UART_IT_MASK))) + +/*!< @brief Macro used for module interrupt source check. + * Used in interrupt handlers. + */ +#define __HAL_LL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__ >> 28UL) == 1UL)? ((hal_ll_uart_base_handle_t *)__HANDLE__)->cr1:((((uint32_t)__INTERRUPT__ >> 28UL) == 2UL)? \ + ((hal_ll_uart_base_handle_t *)__HANDLE__)->cr2 : ((hal_ll_uart_base_handle_t *)__HANDLE__)->cr3)) & ((uint32_t)__INTERRUPT__ & HAL_LL_UART_IT_MASK)) + +/*!< @brief UART HW register structure */ +typedef struct +{ + hal_ll_base_addr_t cr1; + hal_ll_base_addr_t cr2; + hal_ll_base_addr_t cr3; + hal_ll_base_addr_t brr; + hal_ll_base_addr_t gtpr; + hal_ll_base_addr_t rtor; + hal_ll_base_addr_t rqr; + hal_ll_base_addr_t isr; + hal_ll_base_addr_t icr; + hal_ll_base_addr_t rdr; + hal_ll_base_addr_t tdr; + hal_ll_base_addr_t presc; +} hal_ll_uart_base_handle_t; + +/*!< @brief UART baud rate structure */ +typedef struct +{ + uint32_t baud; + uint32_t real_baud; +} hal_ll_uart_baud_t; + +/*!< @brief UART hw specific structure */ +typedef struct +{ + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + hal_ll_uart_pins_t pins; + hal_ll_uart_baud_t baud_rate; + hal_ll_uart_parity_t parity; + hal_ll_uart_stop_bits_t stop_bit; + hal_ll_uart_data_bits_t data_bit; +} hal_ll_uart_hw_specifics_map_t; + +/*!< @brief UART hw specific module values */ +typedef struct +{ + uint16_t pin_tx; + uint16_t pin_rx; +} hal_ll_uart_pin_id; + +/*!< @brief UART hw specific error values */ +typedef enum +{ + HAL_LL_UART_SUCCESS = 0, + HAL_LL_UART_WRONG_PINS, + HAL_LL_UART_MODULE_ERROR, + + HAL_LL_UART_ERROR = (-1) +} hal_ll_uart_err_t; + +/*!< @brief UART module state selection */ +typedef enum +{ + HAL_LL_UART_DISABLE = 0, + HAL_LL_UART_ENABLE +} hal_ll_uart_state_t; + +// ------------------------------------------------------------------ VARIABLES +/*!< @brief UART hardware specific info */ +static hal_ll_uart_hw_specifics_map_t hal_ll_uart_hw_specifics_map[] = +{ + #ifdef UART_MODULE_1 + {HAL_LL_UART1_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_1), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + #ifdef UART_MODULE_2 + {HAL_LL_UART2_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_2), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {0, 0}, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR} +}; + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_uart_handle_register_t *low_level_handle; +static volatile hal_ll_uart_hw_specifics_map_t *hal_ll_uart_hw_specifics_map_local; + +/*!< @brief Global interrupt handlers used in functions */ +static hal_ll_uart_isr_t irq_handler; +static handle_t objects[UART_MODULE_COUNT]; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Check if pins are adequate. + * + * Checks tx and rx pins the user has passed with pre-defined + * pins in tx and rx maps. Take into consideration that module + * index numbers have to be the same for both pins. + * + * @param[in] tx_pin - TX pre-defined pin name. + * @param[in] rx_pin - RX pre-defined pin name. + * @param[in] *index_list - Array containing map index numbers. + * @return hal_ll_pin_name_t Module index based on pins. + * + * Returns pre-defined module index from pin maps, if pins + * are adequate. + */ +static hal_ll_pin_name_t hal_ll_uart_check_pins( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_uart_pin_id *index_list, hal_ll_uart_handle_register_t *handle_map ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * TX and RX pins. + * + * @param[in] module_index UART HW module index -- 0,1,2... + * @param[in] *index_list Array with TX and RX map index values + * and module number + * + * @return None + */ +static void hal_ll_uart_map_pins( uint8_t module_index, hal_ll_uart_pin_id *index_list ); + +/** + * @brief Sets UART pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if UART is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_state - Init/De-init + * + * @return void None. + */ +static void hal_ll_uart_alternate_functions_set_state( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_uart_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_uart_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_uart_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Enable clock for UART module on hardware level. + * + * Initializes UART module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_stat - True(enable clock)/False(disable clock). + * + * @return void None. + */ +static void hal_ll_uart_set_clock( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Finds UART module index. + * + * Finds UART index(module number) based on + * handle value. + * + * @param[in] handle - Object specific context handler. + * + * @return uint8_t Module number. + * Returns values from 0 to 9. + */ +static uint8_t hal_ll_uart_find_index( handle_t *handle ); + +/** + * @brief Get UART module clock speed. + * + * Returns adequate clock speed based on + * UART module base address. + * + * @param[in] module_index - UART module index number. + * + * @return uint8_t Module number. + * Returns clock value. + */ +static uint32_t hal_ll_uart_get_clock_speed( hal_ll_pin_name_t module_index ); + +/** + * @brief Clears UART registers. + * + * Clears UART module configuration + * registers, effectively disabling the module itself. + * Take into consideration that any IRQ bits + * are not cleared. + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * + * @return void None. + */ +static void hal_ll_uart_clear_regs( hal_ll_uart_base_handle_t *hal_ll_hw_reg ); + +/** + * @brief Sets desired baud rate on hardware level. + * + * Initializes module with specified baud rate value. + * Take into consideration that if the difference + * between desired baud rate and actual baud + * rate the hw was initialized to is greater than + * 1%, baud rate shall not be set. + * If this occurs, return value shall be + * the error percentage. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_set_baud_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Sets desired stop bits. + * + * Initializes module on hardware level + * with specified stop bit value. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_set_stop_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Sets desired data bits. + * + * Initializes module on hardware level + * with specified data bit bit value. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_set_data_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Sets desired parity. + * + * Initializes module on hardware level + * with specified parity value. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_set_parity_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Sets module clock value. + * + * Enables/disables specific UART module + * clock gate. + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * @param[in] pin_state - true(enable clock) / false(disable clock) + * + * @return void None. + */ +static void hal_ll_uart_set_module( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ); + +/** + * @brief Sets module TX line state. + * + * Enables/disables specific UART module + * TX pin state + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * @param[in] pin_state - true(enable transmitter pin) / false(disable transmitter pin) + * + * @return void None. + */ +static void hal_ll_uart_set_transmitter( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ); + +/** + * @brief Sets module RX line state. + * + * Enables/disables specific UART module + * RX pin state + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * @param[in] pin_state - true(enable receive pin) / false(disable receive pin) + * + * @return void None. + */ +static void hal_ll_uart_set_receiver( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ); + +/** + * @brief Initialize UART module. + * + * Enables UART module clogk gate first. + * Sets pin alternate function state. + * Initializes specific UART module. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_init( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Initialize UART module on the hardware level. + * + * Performs UART module initialization on + * the hardware level. + * + * Procedure: + * 1. Clears control registers + * 2. Sets data bit value + * 3. Sets parity value + * 4. Sets stop bit value + * 5. Sets baud rate value + * 6. Enables transmit pin + * 7. Enables receive pin + * 8. Enables clock gate for specific module + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_hw_init( hal_ll_uart_hw_specifics_map_t *map ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_uart_register_handle( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_uart_handle_register_t *handle_map, uint8_t *hal_module_id ) { + + hal_ll_uart_pin_id index_list[UART_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + uint16_t pin_check_result; + + // Check if pins are valid + if ( (pin_check_result = hal_ll_uart_check_pins( tx_pin, rx_pin, &index_list, handle_map )) == HAL_LL_PIN_NC ) { + return HAL_LL_UART_WRONG_PINS; + }; + + if ( (hal_ll_uart_hw_specifics_map[pin_check_result].pins.tx_pin.pin_name != tx_pin) || + (hal_ll_uart_hw_specifics_map[pin_check_result].pins.rx_pin.pin_name != rx_pin) ) + { + hal_ll_uart_alternate_functions_set_state( &hal_ll_uart_hw_specifics_map[ pin_check_result ], false ); + + hal_ll_uart_map_pins( pin_check_result, &index_list ); + + hal_ll_uart_alternate_functions_set_state( &hal_ll_uart_hw_specifics_map[ pin_check_result ], true ); + + handle_map[pin_check_result].init_ll_state = false; + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[pin_check_result].hal_ll_uart_handle = (handle_t *)&hal_ll_uart_hw_specifics_map[pin_check_result].base; + + handle_map[pin_check_result].hal_ll_uart_handle = (handle_t *)&hal_ll_module_state[pin_check_result].hal_ll_uart_handle; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_uart( handle_t *handle ) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + hal_ll_uart_pin_id index_list[UART_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + uint16_t pin_check_result; + + if ( (pin_check_result = hal_ll_uart_check_pins( hal_ll_uart_hw_specifics_map_local->pins.tx_pin.pin_name, + hal_ll_uart_hw_specifics_map_local->pins.rx_pin.pin_name, &index_list, (void *)0 ) ) == HAL_LL_PIN_NC ) { + return HAL_LL_UART_WRONG_PINS; + }; + + hal_ll_uart_init( hal_ll_uart_hw_specifics_map_local ); + + hal_ll_module_state[pin_check_result].hal_ll_uart_handle = (handle_t *)&hal_ll_uart_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_uart_set_baud( handle_t *handle, uint32_t baud ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->baud_rate.baud = baud; + + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return hal_ll_uart_hw_specifics_map_local->baud_rate.real_baud; +} + +hal_ll_err_t hal_ll_uart_set_parity( handle_t *handle, hal_ll_uart_parity_t parity ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->parity = parity; + + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_uart_set_stop_bits( handle_t *handle, hal_ll_uart_stop_bits_t stop_bit ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->stop_bit = stop_bit; + + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_uart_set_data_bits( handle_t *handle, hal_ll_uart_data_bits_t data_bit ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + // Chips using implementation 1 do not support 7 bit data + if( data_bit == HAL_LL_UART_DATA_BITS_7 ) { + return HAL_LL_UART_MODULE_ERROR; + } + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->data_bit = data_bit; + + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +void hal_ll_uart_close( handle_t *handle ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + if( low_level_handle->hal_ll_uart_handle != NULL ) { + hal_ll_uart_alternate_functions_set_state( hal_ll_uart_hw_specifics_map_local, false ); + + hal_ll_uart_irq_disable(handle, HAL_LL_UART_IRQ_RX); + hal_ll_uart_irq_disable(handle, HAL_LL_UART_IRQ_TX); + + hal_ll_uart_clear_regs(hal_ll_uart_hw_specifics_map_local->base); + hal_ll_uart_set_clock(hal_ll_uart_hw_specifics_map_local, false); + + hal_ll_uart_hw_specifics_map_local->pins.tx_pin.pin_name = HAL_LL_PIN_NC; + hal_ll_uart_hw_specifics_map_local->pins.tx_pin.pin_af = 0; + hal_ll_uart_hw_specifics_map_local->pins.rx_pin.pin_name = HAL_LL_PIN_NC; + hal_ll_uart_hw_specifics_map_local->pins.rx_pin.pin_af = 0; + + hal_ll_uart_hw_specifics_map_local->baud_rate.baud = 115200UL; + hal_ll_uart_hw_specifics_map_local->baud_rate.real_baud = 0; + + irq_handler = NULL; + objects[ hal_ll_uart_find_index( handle ) ] = NULL; + + low_level_handle->hal_ll_uart_handle = NULL; + low_level_handle->hal_drv_uart_handle = NULL; + + low_level_handle->init_ll_state = false; + } +} + +void hal_ll_uart_register_irq_handler( handle_t *handle, hal_ll_uart_isr_t handler, handle_t obj ) +{ + irq_handler = handler; + objects[ hal_ll_uart_find_index( handle ) ] = obj; +} + +void hal_ll_uart_irq_enable( handle_t *handle, hal_ll_uart_irq_t irq ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + switch ( irq ) { + case HAL_LL_UART_IRQ_RX: + __HAL_LL_UART_ENABLE_IT( hal_ll_hw_reg, HAL_LL_UART_IT_RXNE ); + break; + + case HAL_LL_UART_IRQ_TX: + __HAL_LL_UART_ENABLE_IT( hal_ll_hw_reg, HAL_LL_UART_IT_TXE ); + break; + + default: + break; + } + + switch ( hal_ll_uart_hw_specifics_map_local->module_index ) + { + #if defined(UART_MODULE_1) && defined(UART1_NVIC) + case hal_ll_uart_module_num(UART_MODULE_1): + hal_ll_core_enable_irq( UART1_NVIC ); + break; + #endif + + #if defined(UART_MODULE_2) && defined(UART2_NVIC) + case hal_ll_uart_module_num(UART_MODULE_2): + hal_ll_core_enable_irq( UART2_NVIC ); + break; + #endif + + + default: + break; + } +} + +void hal_ll_uart_irq_disable( handle_t *handle, hal_ll_uart_irq_t irq ) +{ + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + switch ( irq ) { + case HAL_LL_UART_IRQ_RX: + __HAL_LL_UART_DISABLE_IT( hal_ll_hw_reg, HAL_LL_UART_IT_RXNE ); + break; + + case HAL_LL_UART_IRQ_TX: + __HAL_LL_UART_DISABLE_IT( hal_ll_hw_reg, HAL_LL_UART_IT_TXE ); + break; + + default: + break; + } + + // Check if module interrupt flags are set or not + if ( ( !check_reg_bit( &hal_ll_hw_reg->cr1, HAL_LL_UART_SR_RXNE ) ) && + ( !check_reg_bit( &hal_ll_hw_reg->cr1, HAL_LL_UART_SR_TXE ) ) ) + { + switch ( hal_ll_uart_hw_specifics_map_local->module_index ) + { + #if defined(UART_MODULE_1) && defined(UART1_NVIC) + case hal_ll_uart_module_num(UART_MODULE_1): + hal_ll_core_disable_irq( UART1_NVIC ); + break; + #endif + + #if defined(UART_MODULE_2) && defined(UART2_NVIC) + case hal_ll_uart_module_num(UART_MODULE_2): + hal_ll_core_disable_irq( UART2_NVIC ); + break; + #endif + + + default: + break; + } + } +} + +void hal_ll_uart_write( handle_t *handle, uint8_t wr_data) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + hal_ll_hw_reg->tdr = wr_data; +} + +uint8_t hal_ll_uart_read( handle_t *handle ) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + return ( hal_ll_hw_reg->rdr ); +} + +// ------------------------------------------------------------- DEFAULT EXCEPTION HANDLERS +#if defined(UART_MODULE_1) && defined(UART1_NVIC) +void MARK_AS_IRQ_HANDLER UART1_IRQHandler() MIKROC_IV(UART1_NVIC) { + if( hal_ll_uart_get_status_flags( HAL_LL_UART1_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_UART1_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_UART1_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(UART_MODULE_1) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_UART1_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_UART1_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_UART1_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(UART_MODULE_1) ], HAL_LL_UART_IRQ_TX ); + } + } +} +#endif + +#if defined(UART_MODULE_2) && defined(UART2_NVIC) +void MARK_AS_IRQ_HANDLER UART2_IRQHandler() MIKROC_IV(UART2_NVIC) { + if( hal_ll_uart_get_status_flags( HAL_LL_UART2_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_UART2_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_UART2_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(UART_MODULE_2) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_UART2_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_UART2_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_UART2_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(UART_MODULE_2) ], HAL_LL_UART_IRQ_TX ); + } + } +} +#endif + + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static uint8_t hal_ll_uart_find_index( handle_t *handle ) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + if( hal_ll_uart_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + return hal_ll_uart_hw_specifics_map_local->module_index; + } else { + return NULL; + } +} + +static hal_ll_pin_name_t hal_ll_uart_check_pins( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_uart_pin_id *index_list, hal_ll_uart_handle_register_t *handle_map ) { + static const uint16_t tx_map_size = ( sizeof( hal_ll_uart_tx_map ) / sizeof( hal_ll_uart_pin_map_t ) ); + static const uint16_t rx_map_size = ( sizeof( hal_ll_uart_rx_map ) / sizeof( hal_ll_uart_pin_map_t ) ); + uint8_t hal_ll_module_id = 0; + uint8_t index_counter = 0; + uint16_t tx_index; + uint16_t rx_index; + + if ( (HAL_LL_PIN_NC == tx_pin) || (HAL_LL_PIN_NC == rx_pin) ) { + return HAL_LL_PIN_NC; + } + + for ( tx_index = 0; tx_index < tx_map_size; tx_index++ ) + { + if ( hal_ll_uart_tx_map[ tx_index ].pin == tx_pin ) + { + for ( rx_index = 0; rx_index < rx_map_size; rx_index++ ) + { + if ( hal_ll_uart_rx_map[ rx_index ].pin == rx_pin ) + { + if ( hal_ll_uart_tx_map[ tx_index ].base == hal_ll_uart_rx_map[ rx_index ].base ) { + // Get module number + hal_ll_module_id = hal_ll_uart_tx_map[ tx_index ].module_index; + + // Map pin names + index_list[hal_ll_module_id].pin_tx = tx_index; + index_list[hal_ll_module_id].pin_rx = rx_index; + + // Check if module is taken + if ( NULL == handle_map[ hal_ll_module_id ].hal_drv_uart_handle ) { + return hal_ll_module_id; + } else if ( UART_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static hal_ll_uart_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof(hal_ll_uart_handle_register_t)); + static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof(hal_ll_uart_handle_register_t)); + + while( hal_ll_module_count-- ) { + if (hal_ll_uart_get_base_from_hal_handle == hal_ll_uart_hw_specifics_map[hal_ll_module_count].base) { + return &hal_ll_uart_hw_specifics_map[hal_ll_module_count]; + } + } + + return &hal_ll_uart_hw_specifics_map[hal_ll_module_error]; +} + +static void hal_ll_uart_set_clock( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ) { + switch ( map->module_index ) + { + #ifdef UART_MODULE_1 + case ( hal_ll_uart_module_num(UART_MODULE_1) ): + (hal_ll_state == true)?(set_reg_bit( _RCC_APBENR2, HAL_LL_USART1EN )):(clear_reg_bit( _RCC_APBENR2, HAL_LL_USART1EN )); + break; + #endif + + #ifdef UART_MODULE_2 + case ( hal_ll_uart_module_num(UART_MODULE_2) ): + (hal_ll_state == true)?(set_reg_bit( _RCC_APBENR1, HAL_LL_USART2EN )):(clear_reg_bit( _RCC_APBENR1, HAL_LL_USART2EN )); + break; + #endif + + + default: + break; + } +} + +static void hal_ll_uart_map_pins( uint8_t module_index, hal_ll_uart_pin_id *index_list ) { + // Map new pins + hal_ll_uart_hw_specifics_map[module_index].pins.tx_pin.pin_name = hal_ll_uart_tx_map[ index_list[module_index].pin_tx ].pin; + hal_ll_uart_hw_specifics_map[module_index].pins.rx_pin.pin_name = hal_ll_uart_rx_map[ index_list[module_index].pin_rx ].pin; + // TX and RX could have different alternate function settings, hence save both AF values + hal_ll_uart_hw_specifics_map[module_index].pins.tx_pin.pin_af = hal_ll_uart_tx_map[ index_list[module_index].pin_tx ].af; + hal_ll_uart_hw_specifics_map[module_index].pins.rx_pin.pin_af = hal_ll_uart_rx_map[ index_list[module_index].pin_rx ].af; +} + +static void hal_ll_uart_alternate_functions_set_state( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ) { + module_struct module; + + if ( (map->pins.tx_pin.pin_name != HAL_LL_PIN_NC) && map->pins.rx_pin.pin_name != HAL_LL_PIN_NC ) { + module.pins[0] = VALUE( map->pins.tx_pin.pin_name, map->pins.tx_pin.pin_af ); + module.pins[1] = VALUE( map->pins.rx_pin.pin_name, map->pins.rx_pin.pin_af ); + module.pins[2] = GPIO_MODULE_STRUCT_END; + + module.configs[0] = HAL_LL_UART_AF_CONFIG; + module.configs[1] = HAL_LL_UART_AF_CONFIG; + module.configs[2] = GPIO_MODULE_STRUCT_END; + + /* STM32F1xx specific */ + module.gpio_remap = map->pins.tx_pin.pin_af; + + hal_ll_gpio_module_struct_init( &module, hal_ll_state ); + } +} + +static void hal_ll_uart_set_baud_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + uint32_t reg = 0; + uint32_t integer_divider = 0; + uint32_t fractional_divider = 0; + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); + uint32_t hal_ll_baud_value = hal_ll_uart_get_baud(hal_ll_uart_get_clock_speed(map->module_index),map->baud_rate.baud,4); + uint32_t hal_ll_baud_real_value = hal_ll_uart_get_real_baud(hal_ll_uart_get_clock_speed(map->module_index),hal_ll_baud_value,4); + + // if error greater than specified, cancel setting baud rate + if( (hal_ll_uart_get_baud_error(hal_ll_baud_real_value,map->baud_rate.baud)) > HAL_LL_UART_ACCEPTABLE_ERROR ) { + map->baud_rate.real_baud = hal_ll_uart_get_baud_error(hal_ll_baud_real_value,map->baud_rate.baud); + } else { + map->baud_rate.real_baud = hal_ll_baud_real_value; + + integer_divider = ( ( 25 * hal_ll_uart_get_clock_speed( map->module_index ) ) / ( 4 * ( map->baud_rate.baud ) ) ); + reg = ( integer_divider / 100 ) << 4; + + fractional_divider = integer_divider - ( 100 * ( reg >> 4 ) ); + reg |= ( ( ( ( fractional_divider * 16 ) + 50 ) / 100 ) ) & 0x0F; + + hal_ll_hw_reg->brr = ( uint16_t )reg; + } +} + +static uint32_t hal_ll_uart_get_clock_speed( hal_ll_pin_name_t module_index ) { + rcc_clocks_t rcc_clocks; + + RCC_GetClocksFrequency( &rcc_clocks ); + + switch ( module_index ) + { + #ifdef UART_MODULE_1 + case ( hal_ll_uart_module_num(UART_MODULE_1) ): + return rcc_clocks.pclk; + break; + #endif + + #ifdef UART_MODULE_2 + case ( hal_ll_uart_module_num(UART_MODULE_2) ): + return rcc_clocks.pclk; + break; + #endif + + default: + break; + } + + return NULL; +} + +static void hal_ll_uart_set_stop_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); + + switch ( map->stop_bit ) + { + case HAL_LL_UART_STOP_BITS_HALF: + hal_ll_hw_reg->cr2 |= STOP_BITS_HALF; + break; + case HAL_LL_UART_STOP_BITS_ONE: + hal_ll_hw_reg->cr2 |= STOP_BITS_ONE; + break; + case HAL_LL_UART_STOP_BITS_ONE_AND_A_HALF: + hal_ll_hw_reg->cr2 |= STOP_BITS_ONE_AND_A_HALF; + break; + case HAL_LL_UART_STOP_BITS_TWO: + hal_ll_hw_reg->cr2 |= STOP_BITS_TWO; + break; + + default: + break; + } +} + +static void hal_ll_uart_set_data_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); + + switch ( map->data_bit ) + { + case HAL_LL_UART_DATA_BITS_7: + hal_ll_hw_reg->cr1 |= DATA_BIT_7; + break; + + case HAL_LL_UART_DATA_BITS_8: + hal_ll_hw_reg->cr1 |= DATA_BIT_8; + break; + + case HAL_LL_UART_DATA_BITS_9: + hal_ll_hw_reg->cr1 |= DATA_BIT_9; + break; + + + default: + break; + } +} + +static void hal_ll_uart_set_parity_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); + + switch ( map->parity ) + { + case HAL_LL_UART_PARITY_NONE: + hal_ll_hw_reg->cr1 |= PARITY_NO; + break; + case HAL_LL_UART_PARITY_EVEN: + hal_ll_hw_reg->cr1 |= PARITY_ENABLED | PARITY_EVEN; + break; + case HAL_LL_UART_PARITY_ODD: + hal_ll_hw_reg->cr1 |= PARITY_ENABLED | PARITY_ODD; + break; + + default: + break; + } +} + +static void hal_ll_uart_set_module( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ) { + switch ( pin_state ) + { + case HAL_LL_UART_DISABLE: + clear_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_UE ); + break; + + case HAL_LL_UART_ENABLE: + set_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_UE ); + break; + + default: + break; + } +} + +static void hal_ll_uart_set_transmitter( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ) { + switch ( pin_state ) + { + case HAL_LL_UART_DISABLE: + clear_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_TE ); + break; + + case HAL_LL_UART_ENABLE: + set_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_TE ); + break; + + default: + break; + } +} + +static void hal_ll_uart_set_receiver( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ) { + switch ( pin_state ) + { + case HAL_LL_UART_DISABLE: + clear_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_RE ); + break; + + case HAL_LL_UART_ENABLE: + set_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_RE ); + break; + + default: + break; + } +} + +static void hal_ll_uart_clear_regs( hal_ll_uart_base_handle_t *hal_ll_hw_reg ) { + hal_ll_hw_reg->cr1 &= HAL_LL_UART_IT_CR1_MASK; + hal_ll_hw_reg->cr2 &= HAL_LL_UART_IT_CR2_MASK; + hal_ll_hw_reg->cr3 &= HAL_LL_UART_IT_CR3_MASK; +} + +static void hal_ll_uart_hw_init( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_clear_regs( map->base ); + + hal_ll_uart_set_data_bits_bare_metal( map ); + + hal_ll_uart_set_parity_bare_metal( map ); + + hal_ll_uart_set_stop_bits_bare_metal( map ); + + hal_ll_uart_set_baud_bare_metal( map ); + + hal_ll_uart_set_transmitter( map->base, HAL_LL_UART_ENABLE ); + + hal_ll_uart_set_receiver( map->base, HAL_LL_UART_ENABLE ); + + hal_ll_uart_set_module( map->base, HAL_LL_UART_ENABLE ); +} + +static void hal_ll_uart_init( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_set_clock( map, true ); + + hal_ll_uart_alternate_functions_set_state( map, true ); + + hal_ll_uart_hw_init( map ); +} +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_160/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_160/CMakeLists.cmake new file mode 100644 index 000000000..251c122af --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_160/CMakeLists.cmake @@ -0,0 +1,9 @@ +if(${MCU_NAME} MATCHES "^STM32L4P5AE$|^STM32L4P5AG$|^STM32L4P5CE$|^STM32L4P5CG$|^STM32L4P5QE$|^STM32L4P5QG$|^STM32L4P5RE$|^STM32L4P5RG$|^STM32L4P5VE$|^STM32L4P5VG$|^STM32L4P5ZE$|^STM32L4P5ZG$") + set(uart_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_uart.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_160") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_160") + list(APPEND hal_ll_def_list "STM32L4xx") + list(APPEND hal_ll_def_list "STM32L4Pxx") + list(APPEND hal_ll_def_list "STM32L4P5xx") + set(uart_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/uart/hal_ll_uart_pin_map/implementations/doc_ds_160") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_160/hal_ll_uart.c b/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_160/hal_ll_uart.c new file mode 100644 index 000000000..e62378c5f --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_160/hal_ll_uart.c @@ -0,0 +1,1213 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_uart.c + * @brief UART HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_rcc.h" +#include "hal_ll_uart.h" +#include "hal_ll_gpio.h" +#include "hal_ll_core.h" +#include "hal_ll_core_defines.h" +#include "hal_ll_uart_pin_map.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_uart_handle_register_t hal_ll_module_state[UART_MODULE_COUNT] = { (handle_t *)NULL, (handle_t *)NULL, false }; + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_uart_get_module_state_address ((hal_ll_uart_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_uart_get_handle (hal_ll_uart_handle_register_t *)hal_ll_uart_get_module_state_address->hal_ll_uart_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_uart_get_base_struct(_handle) ((hal_ll_uart_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_uart_get_base_from_hal_handle ((hal_ll_uart_hw_specifics_map_t *)((hal_ll_uart_handle_register_t *)\ + (((hal_ll_uart_handle_register_t *)(handle))->hal_ll_uart_handle))->hal_ll_uart_handle)->base + +/*!< @brief Macros used for calculating actual baud rate value and error value */ +#define HAL_LL_UART_ACCEPTABLE_ERROR (float)1.0 +#define hal_ll_uart_get_baud(_clock,_baud,_div) (((_clock/(float)_baud)/_div)-1) +#define hal_ll_uart_get_real_baud(_clock,_baud,_div) (_clock/(_div*(_baud+1))) +#define hal_ll_uart_get_baud_error(_baud_real,_baud) (((float)(abs(_baud_real-_baud))/_baud)*100) + +/*!< @brief Macros defining bit location */ +#define HAL_LL_USART1EN 14 +#define HAL_LL_USART2EN 17 +#define HAL_LL_USART3EN 18 +#define HAL_LL_USART4EN 19 +#define HAL_LL_USART5EN 20 + +#define HAL_LL_UART_CR1_UE 0 +#define HAL_LL_UART_CR1_TE 3 +#define HAL_LL_UART_CR1_RE 2 + +#define HAL_LL_UART_SR_RXNE 5 +#define HAL_LL_UART_SR_TXE 7 + +/*!< @brief Macros defining register bit values */ +#define STOP_BITS_HALF 0x1000U +#define STOP_BITS_ONE 0x00U +#define STOP_BITS_ONE_AND_A_HALF 0x3000U +#define STOP_BITS_TWO 0x2000U + +#define DATA_BIT_7 0x10000000U +#define DATA_BIT_8 0x00U +#define DATA_BIT_9 0x1000U + +#define PARITY_NO 0x00U +#define PARITY_ENABLED 0x400U + +#define PARITY_EVEN 0x00U +#define PARITY_ODD 0x200U + +/*!< @brief Macro used for setting pin alternate functions */ +#define HAL_LL_UART_AF_CONFIG (GPIO_CFG_MODE_ALT_FUNCTION | GPIO_CFG_SPEED_HIGH | GPIO_CFG_OTYPE_PP) + +/*!< @brief Macros used for interrupts */ +#define HAL_LL_UART_IT_MASK 0xFFFFUL +#define HAL_LL_UART_IT_CLEAR_MASK 0x123bffU +#define HAL_LL_UART_IT_CR1_MASK 0x1f0U +#define HAL_LL_UART_IT_CR2_MASK 0x40U +#define HAL_LL_UART_IT_CR3_MASK 0x401U + +#define HAL_LL_UART_CR1_REG_INDEX 1 +#define HAL_LL_UART_CR2_REG_INDEX 2 +#define HAL_LL_UART_CR3_REG_INDEX 3 + +#define HAL_LL_UART_IT_PE 0x100U +#define HAL_LL_UART_IT_TXE (0x10000000 | 0x80U) +#define HAL_LL_UART_IT_TC 0x40U +#define HAL_LL_UART_IT_RXNE (0x10000000 | 0x20U) +#define HAL_LL_UART_IT_IDLE 0x10U +#define HAL_LL_UART_IT_LBD 0x40U +#define HAL_LL_UART_IT_CTS 0x400U +#define HAL_LL_UART_IT_ERR 0x01U + +#define HAL_LL_UART_STATUS_RXNE_FLAG 0x20U +#define HAL_LL_UART_STATUS_TXE_FLAG 0x80U + +/*!< @brief Macro used for status registed flag check + * Used in interrupt handlers. + */ +#define hal_ll_uart_get_status_flags(_handle,_flag) (((hal_ll_uart_base_handle_t *)_handle)->isr & _flag) + +/*!< @brief Macro used for status register flag clearing + * Used in interrupt handlers. + */ +#define hal_ll_uart_clear_status_flag(_handle,_flag) (set_reg_bit( &(((hal_ll_uart_base_handle_t *)_handle)->icr), ( _flag & HAL_LL_UART_IT_CLEAR_MASK ) ) ) + +/*!< @brief Macro used for module interrupt enabling. + * Used in interrupt handlers. + */ +#define __HAL_LL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__ >> 28UL) == HAL_LL_UART_CR1_REG_INDEX)? (__HANDLE__->cr1 |= (__INTERRUPT__ & HAL_LL_UART_IT_MASK)): \ + ((__INTERRUPT__ >> 28UL) == HAL_LL_UART_CR2_REG_INDEX)? (__HANDLE__->cr2 |= (__INTERRUPT__ & HAL_LL_UART_IT_MASK)): \ + (__HANDLE__->cr3 |= (__INTERRUPT__ & HAL_LL_UART_IT_MASK))) + +/*!< @brief Macro used for module interrupt disabling. + * Used in interrupt handlers. + */ +#define __HAL_LL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__ >> 28UL) == HAL_LL_UART_CR1_REG_INDEX)? (__HANDLE__->cr1 &= ~(__INTERRUPT__ & HAL_LL_UART_IT_MASK)): \ + ((__INTERRUPT__ >> 28UL) == HAL_LL_UART_CR2_REG_INDEX)? (__HANDLE__->cr2 &= ~(__INTERRUPT__ & HAL_LL_UART_IT_MASK)): \ + (__HANDLE__->cr3 &= ~ (__INTERRUPT__ & HAL_LL_UART_IT_MASK))) + +/*!< @brief Macro used for module interrupt source check. + * Used in interrupt handlers. + */ +#define __HAL_LL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__ >> 28UL) == 1UL)? ((hal_ll_uart_base_handle_t *)__HANDLE__)->cr1:((((uint32_t)__INTERRUPT__ >> 28UL) == 2UL)? \ + ((hal_ll_uart_base_handle_t *)__HANDLE__)->cr2 : ((hal_ll_uart_base_handle_t *)__HANDLE__)->cr3)) & ((uint32_t)__INTERRUPT__ & HAL_LL_UART_IT_MASK)) + +/*!< @brief UART HW register structure */ +typedef struct +{ + hal_ll_base_addr_t cr1; + hal_ll_base_addr_t cr2; + hal_ll_base_addr_t cr3; + hal_ll_base_addr_t brr; + hal_ll_base_addr_t gtpr; + hal_ll_base_addr_t rtor; + hal_ll_base_addr_t rqr; + hal_ll_base_addr_t isr; + hal_ll_base_addr_t icr; + hal_ll_base_addr_t rdr; + hal_ll_base_addr_t tdr; + hal_ll_base_addr_t presc; +} hal_ll_uart_base_handle_t; + +/*!< @brief UART baud rate structure */ +typedef struct +{ + uint32_t baud; + uint32_t real_baud; +} hal_ll_uart_baud_t; + +/*!< @brief UART hw specific structure */ +typedef struct +{ + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + hal_ll_uart_pins_t pins; + hal_ll_uart_baud_t baud_rate; + hal_ll_uart_parity_t parity; + hal_ll_uart_stop_bits_t stop_bit; + hal_ll_uart_data_bits_t data_bit; +} hal_ll_uart_hw_specifics_map_t; + +/*!< @brief UART hw specific module values */ +typedef struct +{ + uint16_t pin_tx; + uint16_t pin_rx; +} hal_ll_uart_pin_id; + +/*!< @brief UART hw specific error values */ +typedef enum +{ + HAL_LL_UART_SUCCESS = 0, + HAL_LL_UART_WRONG_PINS, + HAL_LL_UART_MODULE_ERROR, + + HAL_LL_UART_ERROR = (-1) +} hal_ll_uart_err_t; + +/*!< @brief UART module state selection */ +typedef enum +{ + HAL_LL_UART_DISABLE = 0, + HAL_LL_UART_ENABLE +} hal_ll_uart_state_t; + +// ------------------------------------------------------------------ VARIABLES +/*!< @brief UART hardware specific info */ +static hal_ll_uart_hw_specifics_map_t hal_ll_uart_hw_specifics_map[] = +{ + #ifdef UART_MODULE_1 + {HAL_LL_UART1_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_1), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + #ifdef UART_MODULE_2 + {HAL_LL_UART2_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_2), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + #ifdef UART_MODULE_3 + {HAL_LL_UART3_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_3), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + #ifdef UART_MODULE_4 + {HAL_LL_UART4_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_4), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + #ifdef UART_MODULE_5 + {HAL_LL_UART5_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_5), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {0, 0}, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR} +}; + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_uart_handle_register_t *low_level_handle; +static volatile hal_ll_uart_hw_specifics_map_t *hal_ll_uart_hw_specifics_map_local; + +/*!< @brief Global interrupt handlers used in functions */ +static hal_ll_uart_isr_t irq_handler; +static handle_t objects[UART_MODULE_COUNT]; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Check if pins are adequate. + * + * Checks tx and rx pins the user has passed with pre-defined + * pins in tx and rx maps. Take into consideration that module + * index numbers have to be the same for both pins. + * + * @param[in] tx_pin - TX pre-defined pin name. + * @param[in] rx_pin - RX pre-defined pin name. + * @param[in] *index_list - Array containing map index numbers. + * @return hal_ll_pin_name_t Module index based on pins. + * + * Returns pre-defined module index from pin maps, if pins + * are adequate. + */ +static hal_ll_pin_name_t hal_ll_uart_check_pins( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_uart_pin_id *index_list, hal_ll_uart_handle_register_t *handle_map ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * TX and RX pins. + * + * @param[in] module_index UART HW module index -- 0,1,2... + * @param[in] *index_list Array with TX and RX map index values + * and module number + * + * @return None + */ +static void hal_ll_uart_map_pins( uint8_t module_index, hal_ll_uart_pin_id *index_list ); + +/** + * @brief Sets UART pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if UART is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_state - Init/De-init + * + * @return void None. + */ +static void hal_ll_uart_alternate_functions_set_state( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_uart_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_uart_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_uart_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Enable clock for UART module on hardware level. + * + * Initializes UART module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_stat - True(enable clock)/False(disable clock). + * + * @return void None. + */ +static void hal_ll_uart_set_clock( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Finds UART module index. + * + * Finds UART index(module number) based on + * handle value. + * + * @param[in] handle - Object specific context handler. + * + * @return uint8_t Module number. + * Returns values from 0 to 9. + */ +static uint8_t hal_ll_uart_find_index( handle_t *handle ); + +/** + * @brief Get UART module clock speed. + * + * Returns adequate clock speed based on + * UART module base address. + * + * @param[in] module_index - UART module index number. + * + * @return uint8_t Module number. + * Returns clock value. + */ +static uint32_t hal_ll_uart_get_clock_speed( hal_ll_pin_name_t module_index ); + +/** + * @brief Clears UART registers. + * + * Clears UART module configuration + * registers, effectively disabling the module itself. + * Take into consideration that any IRQ bits + * are not cleared. + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * + * @return void None. + */ +static void hal_ll_uart_clear_regs( hal_ll_uart_base_handle_t *hal_ll_hw_reg ); + +/** + * @brief Sets desired baud rate on hardware level. + * + * Initializes module with specified baud rate value. + * Take into consideration that if the difference + * between desired baud rate and actual baud + * rate the hw was initialized to is greater than + * 1%, baud rate shall not be set. + * If this occurs, return value shall be + * the error percentage. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_set_baud_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Sets desired stop bits. + * + * Initializes module on hardware level + * with specified stop bit value. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_set_stop_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Sets desired data bits. + * + * Initializes module on hardware level + * with specified data bit bit value. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_set_data_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Sets desired parity. + * + * Initializes module on hardware level + * with specified parity value. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_set_parity_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Sets module clock value. + * + * Enables/disables specific UART module + * clock gate. + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * @param[in] pin_state - true(enable clock) / false(disable clock) + * + * @return void None. + */ +static void hal_ll_uart_set_module( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ); + +/** + * @brief Sets module TX line state. + * + * Enables/disables specific UART module + * TX pin state + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * @param[in] pin_state - true(enable transmitter pin) / false(disable transmitter pin) + * + * @return void None. + */ +static void hal_ll_uart_set_transmitter( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ); + +/** + * @brief Sets module RX line state. + * + * Enables/disables specific UART module + * RX pin state + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * @param[in] pin_state - true(enable receive pin) / false(disable receive pin) + * + * @return void None. + */ +static void hal_ll_uart_set_receiver( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ); + +/** + * @brief Initialize UART module. + * + * Enables UART module clogk gate first. + * Sets pin alternate function state. + * Initializes specific UART module. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_init( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Initialize UART module on the hardware level. + * + * Performs UART module initialization on + * the hardware level. + * + * Procedure: + * 1. Clears control registers + * 2. Sets data bit value + * 3. Sets parity value + * 4. Sets stop bit value + * 5. Sets baud rate value + * 6. Enables transmit pin + * 7. Enables receive pin + * 8. Enables clock gate for specific module + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_hw_init( hal_ll_uart_hw_specifics_map_t *map ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_uart_register_handle( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_uart_handle_register_t *handle_map, uint8_t *hal_module_id ) { + + hal_ll_uart_pin_id index_list[UART_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + uint16_t pin_check_result; + + // Check if pins are valid + if ( (pin_check_result = hal_ll_uart_check_pins( tx_pin, rx_pin, &index_list, handle_map )) == HAL_LL_PIN_NC ) { + return HAL_LL_UART_WRONG_PINS; + }; + + if ( (hal_ll_uart_hw_specifics_map[pin_check_result].pins.tx_pin.pin_name != tx_pin) || + (hal_ll_uart_hw_specifics_map[pin_check_result].pins.rx_pin.pin_name != rx_pin) ) + { + hal_ll_uart_alternate_functions_set_state( &hal_ll_uart_hw_specifics_map[ pin_check_result ], false ); + + hal_ll_uart_map_pins( pin_check_result, &index_list ); + + hal_ll_uart_alternate_functions_set_state( &hal_ll_uart_hw_specifics_map[ pin_check_result ], true ); + + handle_map[pin_check_result].init_ll_state = false; + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[pin_check_result].hal_ll_uart_handle = (handle_t *)&hal_ll_uart_hw_specifics_map[pin_check_result].base; + + handle_map[pin_check_result].hal_ll_uart_handle = (handle_t *)&hal_ll_module_state[pin_check_result].hal_ll_uart_handle; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_uart( handle_t *handle ) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + hal_ll_uart_pin_id index_list[UART_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + uint16_t pin_check_result; + + if ( (pin_check_result = hal_ll_uart_check_pins( hal_ll_uart_hw_specifics_map_local->pins.tx_pin.pin_name, + hal_ll_uart_hw_specifics_map_local->pins.rx_pin.pin_name, &index_list, (void *)0 ) ) == HAL_LL_PIN_NC ) { + return HAL_LL_UART_WRONG_PINS; + }; + + hal_ll_uart_init( hal_ll_uart_hw_specifics_map_local ); + + hal_ll_module_state[pin_check_result].hal_ll_uart_handle = (handle_t *)&hal_ll_uart_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_uart_set_baud( handle_t *handle, uint32_t baud ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->baud_rate.baud = baud; + + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return hal_ll_uart_hw_specifics_map_local->baud_rate.real_baud; +} + +hal_ll_err_t hal_ll_uart_set_parity( handle_t *handle, hal_ll_uart_parity_t parity ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->parity = parity; + + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_uart_set_stop_bits( handle_t *handle, hal_ll_uart_stop_bits_t stop_bit ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->stop_bit = stop_bit; + + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_uart_set_data_bits( handle_t *handle, hal_ll_uart_data_bits_t data_bit ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + // Chips using implementation 1 do not support 7 bit data + if( data_bit == HAL_LL_UART_DATA_BITS_7 ) { + return HAL_LL_UART_MODULE_ERROR; + } + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->data_bit = data_bit; + + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +void hal_ll_uart_close( handle_t *handle ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + if( low_level_handle->hal_ll_uart_handle != NULL ) { + hal_ll_uart_alternate_functions_set_state( hal_ll_uart_hw_specifics_map_local, false ); + + hal_ll_uart_irq_disable(handle, HAL_LL_UART_IRQ_RX); + hal_ll_uart_irq_disable(handle, HAL_LL_UART_IRQ_TX); + + hal_ll_uart_clear_regs(hal_ll_uart_hw_specifics_map_local->base); + hal_ll_uart_set_clock(hal_ll_uart_hw_specifics_map_local, false); + + hal_ll_uart_hw_specifics_map_local->pins.tx_pin.pin_name = HAL_LL_PIN_NC; + hal_ll_uart_hw_specifics_map_local->pins.tx_pin.pin_af = 0; + hal_ll_uart_hw_specifics_map_local->pins.rx_pin.pin_name = HAL_LL_PIN_NC; + hal_ll_uart_hw_specifics_map_local->pins.rx_pin.pin_af = 0; + + hal_ll_uart_hw_specifics_map_local->baud_rate.baud = 115200UL; + hal_ll_uart_hw_specifics_map_local->baud_rate.real_baud = 0; + + irq_handler = NULL; + objects[ hal_ll_uart_find_index( handle ) ] = NULL; + + low_level_handle->hal_ll_uart_handle = NULL; + low_level_handle->hal_drv_uart_handle = NULL; + + low_level_handle->init_ll_state = false; + } +} + +void hal_ll_uart_register_irq_handler( handle_t *handle, hal_ll_uart_isr_t handler, handle_t obj ) +{ + irq_handler = handler; + objects[ hal_ll_uart_find_index( handle ) ] = obj; +} + +void hal_ll_uart_irq_enable( handle_t *handle, hal_ll_uart_irq_t irq ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + switch ( irq ) { + case HAL_LL_UART_IRQ_RX: + __HAL_LL_UART_ENABLE_IT( hal_ll_hw_reg, HAL_LL_UART_IT_RXNE ); + break; + + case HAL_LL_UART_IRQ_TX: + __HAL_LL_UART_ENABLE_IT( hal_ll_hw_reg, HAL_LL_UART_IT_TXE ); + break; + + default: + break; + } + + switch ( hal_ll_uart_hw_specifics_map_local->module_index ) + { + #if defined(UART_MODULE_1) && defined(UART1_NVIC) + case hal_ll_uart_module_num(UART_MODULE_1): + hal_ll_core_enable_irq( UART1_NVIC ); + break; + #endif + + #if defined(UART_MODULE_2) && defined(UART2_NVIC) + case hal_ll_uart_module_num(UART_MODULE_2): + hal_ll_core_enable_irq( UART2_NVIC ); + break; + #endif + + #if defined(UART_MODULE_3) && defined(UART3_NVIC) + case hal_ll_uart_module_num(UART_MODULE_3): + hal_ll_core_enable_irq( UART3_NVIC ); + break; + #endif + + #if defined(UART_MODULE_4) && defined(UART4_NVIC) + case hal_ll_uart_module_num(UART_MODULE_4): + hal_ll_core_enable_irq( UART4_NVIC ); + break; + #endif + + #if defined(UART_MODULE_5) && defined(UART5_NVIC) + case hal_ll_uart_module_num(UART_MODULE_5): + hal_ll_core_enable_irq( UART5_NVIC ); + break; + #endif + + + default: + break; + } +} + +void hal_ll_uart_irq_disable( handle_t *handle, hal_ll_uart_irq_t irq ) +{ + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + switch ( irq ) { + case HAL_LL_UART_IRQ_RX: + __HAL_LL_UART_DISABLE_IT( hal_ll_hw_reg, HAL_LL_UART_IT_RXNE ); + break; + + case HAL_LL_UART_IRQ_TX: + __HAL_LL_UART_DISABLE_IT( hal_ll_hw_reg, HAL_LL_UART_IT_TXE ); + break; + + default: + break; + } + + // Check if module interrupt flags are set or not + if ( ( !check_reg_bit( &hal_ll_hw_reg->cr1, HAL_LL_UART_SR_RXNE ) ) && + ( !check_reg_bit( &hal_ll_hw_reg->cr1, HAL_LL_UART_SR_TXE ) ) ) + { + switch ( hal_ll_uart_hw_specifics_map_local->module_index ) + { + #if defined(UART_MODULE_1) && defined(UART1_NVIC) + case hal_ll_uart_module_num(UART_MODULE_1): + hal_ll_core_disable_irq( UART1_NVIC ); + break; + #endif + + #if defined(UART_MODULE_2) && defined(UART2_NVIC) + case hal_ll_uart_module_num(UART_MODULE_2): + hal_ll_core_disable_irq( UART2_NVIC ); + break; + #endif + + #if defined(UART_MODULE_3) && defined(UART3_NVIC) + case hal_ll_uart_module_num(UART_MODULE_3): + hal_ll_core_disable_irq( UART3_NVIC ); + break; + #endif + + #if defined(UART_MODULE_4) && defined(UART4_NVIC) + case hal_ll_uart_module_num(UART_MODULE_4): + hal_ll_core_disable_irq( UART4_NVIC ); + break; + #endif + + #if defined(UART_MODULE_5) && defined(UART5_NVIC) + case hal_ll_uart_module_num(UART_MODULE_5): + hal_ll_core_disable_irq( UART5_NVIC ); + break; + #endif + + + default: + break; + } + } +} + +void hal_ll_uart_write( handle_t *handle, uint8_t wr_data) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + hal_ll_hw_reg->tdr = wr_data; +} + +uint8_t hal_ll_uart_read( handle_t *handle ) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + return ( hal_ll_hw_reg->rdr ); +} + +// ------------------------------------------------------------- DEFAULT EXCEPTION HANDLERS +#if defined(UART_MODULE_1) && defined(UART1_NVIC) +void MARK_AS_IRQ_HANDLER UART1_IRQHandler() MIKROC_IV(UART1_NVIC) { + if( hal_ll_uart_get_status_flags( HAL_LL_UART1_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_UART1_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_UART1_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(UART_MODULE_1) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_UART1_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_UART1_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_UART1_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(UART_MODULE_1) ], HAL_LL_UART_IRQ_TX ); + } + } +} +#endif + +#if defined(UART_MODULE_2) && defined(UART2_NVIC) +void MARK_AS_IRQ_HANDLER UART2_IRQHandler() MIKROC_IV(UART2_NVIC) { + if( hal_ll_uart_get_status_flags( HAL_LL_UART2_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_UART2_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_UART2_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(UART_MODULE_2) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_UART2_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_UART2_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_UART2_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(UART_MODULE_2) ], HAL_LL_UART_IRQ_TX ); + } + } +} +#endif + +#if defined(UART_MODULE_3) && defined(UART3_NVIC) +void MARK_AS_IRQ_HANDLER UART3_IRQHandler() MIKROC_IV(UART3_NVIC) { + if( hal_ll_uart_get_status_flags( HAL_LL_UART3_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_UART3_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_UART3_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(UART_MODULE_3) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_UART3_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_UART3_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_UART3_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(UART_MODULE_3) ], HAL_LL_UART_IRQ_TX ); + } + } +} +#endif + +#if defined(UART_MODULE_4) && defined(UART4_NVIC) +void MARK_AS_IRQ_HANDLER UART4_IRQHandler() MIKROC_IV(UART4_NVIC) { + if( hal_ll_uart_get_status_flags( HAL_LL_UART4_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_UART4_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_UART4_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(UART_MODULE_4) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_UART4_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_UART4_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_UART4_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(UART_MODULE_4) ], HAL_LL_UART_IRQ_TX ); + } + } +} +#endif + +#if defined(UART_MODULE_5) && defined(UART5_NVIC) +void MARK_AS_IRQ_HANDLER UART5_IRQHandler() MIKROC_IV(UART5_NVIC) { + if( hal_ll_uart_get_status_flags( HAL_LL_UART5_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_UART5_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_UART5_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(UART_MODULE_5) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_UART5_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_UART5_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_UART5_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(UART_MODULE_5) ], HAL_LL_UART_IRQ_TX ); + } + } +} +#endif + + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static uint8_t hal_ll_uart_find_index( handle_t *handle ) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + if( hal_ll_uart_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + return hal_ll_uart_hw_specifics_map_local->module_index; + } else { + return NULL; + } +} + +static hal_ll_pin_name_t hal_ll_uart_check_pins( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_uart_pin_id *index_list, hal_ll_uart_handle_register_t *handle_map ) { + static const uint16_t tx_map_size = ( sizeof( hal_ll_uart_tx_map ) / sizeof( hal_ll_uart_pin_map_t ) ); + static const uint16_t rx_map_size = ( sizeof( hal_ll_uart_rx_map ) / sizeof( hal_ll_uart_pin_map_t ) ); + uint8_t hal_ll_module_id = 0; + uint8_t index_counter = 0; + uint16_t tx_index; + uint16_t rx_index; + + if ( (HAL_LL_PIN_NC == tx_pin) || (HAL_LL_PIN_NC == rx_pin) ) { + return HAL_LL_PIN_NC; + } + + for ( tx_index = 0; tx_index < tx_map_size; tx_index++ ) + { + if ( hal_ll_uart_tx_map[ tx_index ].pin == tx_pin ) + { + for ( rx_index = 0; rx_index < rx_map_size; rx_index++ ) + { + if ( hal_ll_uart_rx_map[ rx_index ].pin == rx_pin ) + { + if ( hal_ll_uart_tx_map[ tx_index ].base == hal_ll_uart_rx_map[ rx_index ].base ) { + // Get module number + hal_ll_module_id = hal_ll_uart_tx_map[ tx_index ].module_index; + + // Map pin names + index_list[hal_ll_module_id].pin_tx = tx_index; + index_list[hal_ll_module_id].pin_rx = rx_index; + + // Check if module is taken + if ( NULL == handle_map[ hal_ll_module_id ].hal_drv_uart_handle ) { + return hal_ll_module_id; + } else if ( UART_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static hal_ll_uart_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof(hal_ll_uart_handle_register_t)); + static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof(hal_ll_uart_handle_register_t)); + + while( hal_ll_module_count-- ) { + if (hal_ll_uart_get_base_from_hal_handle == hal_ll_uart_hw_specifics_map[hal_ll_module_count].base) { + return &hal_ll_uart_hw_specifics_map[hal_ll_module_count]; + } + } + + return &hal_ll_uart_hw_specifics_map[hal_ll_module_error]; +} + +static void hal_ll_uart_set_clock( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ) { + switch ( map->module_index ) + { + #ifdef UART_MODULE_1 + case ( hal_ll_uart_module_num(UART_MODULE_1) ): + (hal_ll_state == true)?(set_reg_bit( _RCC_APB2ENR, HAL_LL_USART1EN )):(clear_reg_bit( _RCC_APB2ENR, HAL_LL_USART1EN )); + break; + #endif + + #ifdef UART_MODULE_2 + case ( hal_ll_uart_module_num(UART_MODULE_2) ): + (hal_ll_state == true)?(set_reg_bit( _RCC_APB1ENR1, HAL_LL_USART2EN )):(clear_reg_bit( _RCC_APB1ENR1, HAL_LL_USART2EN )); + break; + #endif + + #ifdef UART_MODULE_3 + case ( hal_ll_uart_module_num(UART_MODULE_3) ): + (hal_ll_state == true)?(set_reg_bit( _RCC_APB1ENR1, HAL_LL_USART3EN )):(clear_reg_bit( _RCC_APB1ENR1, HAL_LL_USART3EN )); + break; + #endif + + #ifdef UART_MODULE_4 + case ( hal_ll_uart_module_num(UART_MODULE_4) ): + (hal_ll_state == true)?(set_reg_bit( _RCC_APB1ENR1, HAL_LL_USART4EN )):(clear_reg_bit( _RCC_APB1ENR1, HAL_LL_USART4EN )); + break; + #endif + + #ifdef UART_MODULE_5 + case ( hal_ll_uart_module_num(UART_MODULE_5) ): + (hal_ll_state == true)?(set_reg_bit( _RCC_APB1ENR1, HAL_LL_USART5EN )):(clear_reg_bit( _RCC_APB1ENR1, HAL_LL_USART5EN )); + break; + #endif + + + default: + break; + } +} + +static void hal_ll_uart_map_pins( uint8_t module_index, hal_ll_uart_pin_id *index_list ) { + // Map new pins + hal_ll_uart_hw_specifics_map[module_index].pins.tx_pin.pin_name = hal_ll_uart_tx_map[ index_list[module_index].pin_tx ].pin; + hal_ll_uart_hw_specifics_map[module_index].pins.rx_pin.pin_name = hal_ll_uart_rx_map[ index_list[module_index].pin_rx ].pin; + // TX and RX could have different alternate function settings, hence save both AF values + hal_ll_uart_hw_specifics_map[module_index].pins.tx_pin.pin_af = hal_ll_uart_tx_map[ index_list[module_index].pin_tx ].af; + hal_ll_uart_hw_specifics_map[module_index].pins.rx_pin.pin_af = hal_ll_uart_rx_map[ index_list[module_index].pin_rx ].af; +} + +static void hal_ll_uart_alternate_functions_set_state( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ) { + module_struct module; + + if ( (map->pins.tx_pin.pin_name != HAL_LL_PIN_NC) && map->pins.rx_pin.pin_name != HAL_LL_PIN_NC ) { + module.pins[0] = VALUE( map->pins.tx_pin.pin_name, map->pins.tx_pin.pin_af ); + module.pins[1] = VALUE( map->pins.rx_pin.pin_name, map->pins.rx_pin.pin_af ); + module.pins[2] = GPIO_MODULE_STRUCT_END; + + module.configs[0] = HAL_LL_UART_AF_CONFIG; + module.configs[1] = HAL_LL_UART_AF_CONFIG; + module.configs[2] = GPIO_MODULE_STRUCT_END; + + /* STM32F1xx specific */ + module.gpio_remap = map->pins.tx_pin.pin_af; + + hal_ll_gpio_module_struct_init( &module, hal_ll_state ); + } +} + +static void hal_ll_uart_set_baud_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + uint32_t reg = 0; + uint32_t integer_divider = 0; + uint32_t fractional_divider = 0; + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); + uint32_t hal_ll_baud_value = hal_ll_uart_get_baud(hal_ll_uart_get_clock_speed(map->module_index),map->baud_rate.baud,4); + uint32_t hal_ll_baud_real_value = hal_ll_uart_get_real_baud(hal_ll_uart_get_clock_speed(map->module_index),hal_ll_baud_value,4); + + // if error greater than specified, cancel setting baud rate + if( (hal_ll_uart_get_baud_error(hal_ll_baud_real_value,map->baud_rate.baud)) > HAL_LL_UART_ACCEPTABLE_ERROR ) { + map->baud_rate.real_baud = hal_ll_uart_get_baud_error(hal_ll_baud_real_value,map->baud_rate.baud); + } else { + map->baud_rate.real_baud = hal_ll_baud_real_value; + + integer_divider = ( ( 25 * hal_ll_uart_get_clock_speed( map->module_index ) ) / ( 4 * ( map->baud_rate.baud ) ) ); + reg = ( integer_divider / 100 ) << 4; + + fractional_divider = integer_divider - ( 100 * ( reg >> 4 ) ); + reg |= ( ( ( ( fractional_divider * 16 ) + 50 ) / 100 ) ) & 0x0F; + + hal_ll_hw_reg->brr = ( uint16_t )reg; + } +} + +static uint32_t hal_ll_uart_get_clock_speed( hal_ll_pin_name_t module_index ) { + rcc_clocks_t rcc_clocks; + + RCC_GetClocksFrequency( &rcc_clocks ); + + switch ( module_index ) + { + #ifdef UART_MODULE_1 + case ( hal_ll_uart_module_num(UART_MODULE_1) ): + return rcc_clocks.pclk2; + break; + #endif + + #ifdef UART_MODULE_2 + case ( hal_ll_uart_module_num(UART_MODULE_2) ): + return rcc_clocks.pclk1; + break; + #endif + + #ifdef UART_MODULE_3 + case ( hal_ll_uart_module_num(UART_MODULE_3) ): + return rcc_clocks.pclk1; + break; + #endif + + #ifdef UART_MODULE_4 + case ( hal_ll_uart_module_num(UART_MODULE_4) ): + return rcc_clocks.pclk1; + break; + #endif + + #ifdef UART_MODULE_5 + case ( hal_ll_uart_module_num(UART_MODULE_5) ): + return rcc_clocks.pclk1; + break; + #endif + + + default: + break; + } + + return NULL; +} + +static void hal_ll_uart_set_stop_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); + + switch ( map->stop_bit ) + { + case HAL_LL_UART_STOP_BITS_HALF: + hal_ll_hw_reg->cr2 |= STOP_BITS_HALF; + break; + case HAL_LL_UART_STOP_BITS_ONE: + hal_ll_hw_reg->cr2 |= STOP_BITS_ONE; + break; + case HAL_LL_UART_STOP_BITS_ONE_AND_A_HALF: + hal_ll_hw_reg->cr2 |= STOP_BITS_ONE_AND_A_HALF; + break; + case HAL_LL_UART_STOP_BITS_TWO: + hal_ll_hw_reg->cr2 |= STOP_BITS_TWO; + break; + + default: + break; + } +} + +static void hal_ll_uart_set_data_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); + + switch ( map->data_bit ) + { + case HAL_LL_UART_DATA_BITS_7: + hal_ll_hw_reg->cr1 |= DATA_BIT_7; + break; + + case HAL_LL_UART_DATA_BITS_8: + hal_ll_hw_reg->cr1 |= DATA_BIT_8; + break; + + case HAL_LL_UART_DATA_BITS_9: + hal_ll_hw_reg->cr1 |= DATA_BIT_9; + break; + + + default: + break; + } +} + +static void hal_ll_uart_set_parity_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); + + switch ( map->parity ) + { + case HAL_LL_UART_PARITY_NONE: + hal_ll_hw_reg->cr1 |= PARITY_NO; + break; + case HAL_LL_UART_PARITY_EVEN: + hal_ll_hw_reg->cr1 |= PARITY_ENABLED | PARITY_EVEN; + break; + case HAL_LL_UART_PARITY_ODD: + hal_ll_hw_reg->cr1 |= PARITY_ENABLED | PARITY_ODD; + break; + + default: + break; + } +} + +static void hal_ll_uart_set_module( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ) { + switch ( pin_state ) + { + case HAL_LL_UART_DISABLE: + clear_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_UE ); + break; + + case HAL_LL_UART_ENABLE: + set_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_UE ); + break; + + default: + break; + } +} + +static void hal_ll_uart_set_transmitter( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ) { + switch ( pin_state ) + { + case HAL_LL_UART_DISABLE: + clear_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_TE ); + break; + + case HAL_LL_UART_ENABLE: + set_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_TE ); + break; + + default: + break; + } +} + +static void hal_ll_uart_set_receiver( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ) { + switch ( pin_state ) + { + case HAL_LL_UART_DISABLE: + clear_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_RE ); + break; + + case HAL_LL_UART_ENABLE: + set_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_RE ); + break; + + default: + break; + } +} + +static void hal_ll_uart_clear_regs( hal_ll_uart_base_handle_t *hal_ll_hw_reg ) { + hal_ll_hw_reg->cr1 &= HAL_LL_UART_IT_CR1_MASK; + hal_ll_hw_reg->cr2 &= HAL_LL_UART_IT_CR2_MASK; + hal_ll_hw_reg->cr3 &= HAL_LL_UART_IT_CR3_MASK; +} + +static void hal_ll_uart_hw_init( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_clear_regs( map->base ); + + hal_ll_uart_set_data_bits_bare_metal( map ); + + hal_ll_uart_set_parity_bare_metal( map ); + + hal_ll_uart_set_stop_bits_bare_metal( map ); + + hal_ll_uart_set_baud_bare_metal( map ); + + hal_ll_uart_set_transmitter( map->base, HAL_LL_UART_ENABLE ); + + hal_ll_uart_set_receiver( map->base, HAL_LL_UART_ENABLE ); + + hal_ll_uart_set_module( map->base, HAL_LL_UART_ENABLE ); +} + +static void hal_ll_uart_init( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_set_clock( map, true ); + + hal_ll_uart_alternate_functions_set_state( map, true ); + + hal_ll_uart_hw_init( map ); +} +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_161/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_161/CMakeLists.cmake new file mode 100644 index 000000000..47ed6cf36 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_161/CMakeLists.cmake @@ -0,0 +1,9 @@ +if(${MCU_NAME} MATCHES "^STM32L4Q5AG$|^STM32L4Q5CG$|^STM32L4Q5QG$|^STM32L4Q5RG$|^STM32L4Q5VG$|^STM32L4Q5ZG$") + set(uart_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_uart.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_161") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_161") + list(APPEND hal_ll_def_list "STM32L4xx") + list(APPEND hal_ll_def_list "STM32L4Qxx") + list(APPEND hal_ll_def_list "STM32L4Q5xx") + set(uart_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/uart/hal_ll_uart_pin_map/implementations/doc_ds_161") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_161/hal_ll_uart.c b/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_161/hal_ll_uart.c new file mode 100644 index 000000000..fb479e1bb --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_161/hal_ll_uart.c @@ -0,0 +1,1255 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_uart.c + * @brief UART HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_rcc.h" +#include "hal_ll_uart.h" +#include "hal_ll_gpio.h" +#include "hal_ll_core.h" +#include "hal_ll_core_defines.h" +#include "hal_ll_uart_pin_map.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_uart_handle_register_t hal_ll_module_state[UART_MODULE_COUNT] = { (handle_t *)NULL, (handle_t *)NULL, false }; + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_uart_get_module_state_address ((hal_ll_uart_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_uart_get_handle (hal_ll_uart_handle_register_t *)hal_ll_uart_get_module_state_address->hal_ll_uart_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_uart_get_base_struct(_handle) ((hal_ll_uart_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_uart_get_base_from_hal_handle ((hal_ll_uart_hw_specifics_map_t *)((hal_ll_uart_handle_register_t *)\ + (((hal_ll_uart_handle_register_t *)(handle))->hal_ll_uart_handle))->hal_ll_uart_handle)->base + +/*!< @brief Macros used for calculating actual baud rate value and error value */ +#define HAL_LL_UART_ACCEPTABLE_ERROR (float)1.0 +#define hal_ll_uart_get_baud(_clock,_baud,_div) (((_clock/(float)_baud)/_div)-1) +#define hal_ll_uart_get_real_baud(_clock,_baud,_div) (_clock/(_div*(_baud+1))) +#define hal_ll_uart_get_baud_error(_baud_real,_baud) (((float)(abs(_baud_real-_baud))/_baud)*100) + +/*!< @brief Macros defining bit location */ +#define HAL_LL_USART1EN 14 + +#define HAL_LL_USART2EN 17 + +#define HAL_LL_USART3EN 18 + +#define HAL_LL_USART4EN 19 + +#define HAL_LL_USART5EN 20 + + +#define HAL_LL_UART_CR1_UE 0 +#define HAL_LL_UART_CR1_TE 3 +#define HAL_LL_UART_CR1_RE 2 + +#define HAL_LL_UART_SR_RXNE 5 +#define HAL_LL_UART_SR_TXE 7 + +/*!< @brief Macros defining register bit values */ +#define STOP_BITS_HALF 0x1000U +#define STOP_BITS_ONE 0x00U +#define STOP_BITS_ONE_AND_A_HALF 0x3000U +#define STOP_BITS_TWO 0x2000U + +#define DATA_BIT_7 0x10000000U +#define DATA_BIT_8 0x00U +#define DATA_BIT_9 0x1000U + +#define PARITY_NO 0x00U +#define PARITY_ENABLED 0x400U + +#define PARITY_EVEN 0x00U +#define PARITY_ODD 0x200U + +/*!< @brief Macro used for setting pin alternate functions */ +#define HAL_LL_UART_AF_CONFIG (GPIO_CFG_MODE_ALT_FUNCTION | GPIO_CFG_SPEED_HIGH | GPIO_CFG_OTYPE_PP) + +/*!< @brief Macros used for interrupts */ +#define HAL_LL_UART_IT_MASK 0xFFFFUL +#define HAL_LL_UART_IT_CLEAR_MASK 0x123bffU +#define HAL_LL_UART_IT_CR1_MASK 0x1f0U +#define HAL_LL_UART_IT_CR2_MASK 0x40U +#define HAL_LL_UART_IT_CR3_MASK 0x401U + +#define HAL_LL_UART_CR1_REG_INDEX 1 +#define HAL_LL_UART_CR2_REG_INDEX 2 +#define HAL_LL_UART_CR3_REG_INDEX 3 + +#define HAL_LL_UART_IT_PE 0x100U +#define HAL_LL_UART_IT_TXE (0x10000000 | 0x80U) +#define HAL_LL_UART_IT_TC 0x40U +#define HAL_LL_UART_IT_RXNE (0x10000000 | 0x20U) +#define HAL_LL_UART_IT_IDLE 0x10U +#define HAL_LL_UART_IT_LBD 0x40U +#define HAL_LL_UART_IT_CTS 0x400U +#define HAL_LL_UART_IT_ERR 0x01U + +#define HAL_LL_UART_STATUS_RXNE_FLAG 0x20U +#define HAL_LL_UART_STATUS_TXE_FLAG 0x80U + +/*!< @brief Macro used for status registed flag check + * Used in interrupt handlers. + */ +#define hal_ll_uart_get_status_flags(_handle,_flag) (((hal_ll_uart_base_handle_t *)_handle)->isr & _flag) + +/*!< @brief Macro used for status register flag clearing + * Used in interrupt handlers. + */ +#define hal_ll_uart_clear_status_flag(_handle,_flag) (set_reg_bit( &(((hal_ll_uart_base_handle_t *)_handle)->icr), ( _flag & HAL_LL_UART_IT_CLEAR_MASK ) ) ) + +/*!< @brief Macro used for module interrupt enabling. + * Used in interrupt handlers. + */ +#define __HAL_LL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__ >> 28UL) == HAL_LL_UART_CR1_REG_INDEX)? (__HANDLE__->cr1 |= (__INTERRUPT__ & HAL_LL_UART_IT_MASK)): \ + ((__INTERRUPT__ >> 28UL) == HAL_LL_UART_CR2_REG_INDEX)? (__HANDLE__->cr2 |= (__INTERRUPT__ & HAL_LL_UART_IT_MASK)): \ + (__HANDLE__->cr3 |= (__INTERRUPT__ & HAL_LL_UART_IT_MASK))) + +/*!< @brief Macro used for module interrupt disabling. + * Used in interrupt handlers. + */ +#define __HAL_LL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__ >> 28UL) == HAL_LL_UART_CR1_REG_INDEX)? (__HANDLE__->cr1 &= ~(__INTERRUPT__ & HAL_LL_UART_IT_MASK)): \ + ((__INTERRUPT__ >> 28UL) == HAL_LL_UART_CR2_REG_INDEX)? (__HANDLE__->cr2 &= ~(__INTERRUPT__ & HAL_LL_UART_IT_MASK)): \ + (__HANDLE__->cr3 &= ~ (__INTERRUPT__ & HAL_LL_UART_IT_MASK))) + +/*!< @brief Macro used for module interrupt source check. + * Used in interrupt handlers. + */ +#define __HAL_LL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__ >> 28UL) == 1UL)? ((hal_ll_uart_base_handle_t *)__HANDLE__)->cr1:((((uint32_t)__INTERRUPT__ >> 28UL) == 2UL)? \ + ((hal_ll_uart_base_handle_t *)__HANDLE__)->cr2 : ((hal_ll_uart_base_handle_t *)__HANDLE__)->cr3)) & ((uint32_t)__INTERRUPT__ & HAL_LL_UART_IT_MASK)) + +/*!< @brief UART HW register structure */ +typedef struct +{ + hal_ll_base_addr_t cr1; + hal_ll_base_addr_t cr2; + hal_ll_base_addr_t cr3; + hal_ll_base_addr_t brr; + hal_ll_base_addr_t gtpr; + hal_ll_base_addr_t rtor; + hal_ll_base_addr_t rqr; + hal_ll_base_addr_t isr; + hal_ll_base_addr_t icr; + hal_ll_base_addr_t rdr; + hal_ll_base_addr_t tdr; + hal_ll_base_addr_t presc; + +} hal_ll_uart_base_handle_t; + +/*!< @brief UART baud rate structure */ +typedef struct +{ + uint32_t baud; + uint32_t real_baud; +} hal_ll_uart_baud_t; + +/*!< @brief UART hw specific structure */ +typedef struct +{ + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + hal_ll_uart_pins_t pins; + hal_ll_uart_baud_t baud_rate; + hal_ll_uart_parity_t parity; + hal_ll_uart_stop_bits_t stop_bit; + hal_ll_uart_data_bits_t data_bit; +} hal_ll_uart_hw_specifics_map_t; + +/*!< @brief UART hw specific module values */ +typedef struct +{ + uint16_t pin_tx; + uint16_t pin_rx; +} hal_ll_uart_pin_id; + +/*!< @brief UART hw specific error values */ +typedef enum +{ + HAL_LL_UART_SUCCESS = 0, + HAL_LL_UART_WRONG_PINS, + HAL_LL_UART_MODULE_ERROR, + + HAL_LL_UART_ERROR = (-1) +} hal_ll_uart_err_t; + +/*!< @brief UART module state selection */ +typedef enum +{ + HAL_LL_UART_DISABLE = 0, + HAL_LL_UART_ENABLE +} hal_ll_uart_state_t; + +// ------------------------------------------------------------------ VARIABLES +/*!< @brief UART hardware specific info */ +static hal_ll_uart_hw_specifics_map_t hal_ll_uart_hw_specifics_map[] = +{ + #ifdef UART_MODULE_1 + {HAL_LL_UART1_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_1), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + + #ifdef UART_MODULE_2 + {HAL_LL_UART2_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_2), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + + #ifdef UART_MODULE_3 + {HAL_LL_UART3_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_3), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + + #ifdef UART_MODULE_4 + {HAL_LL_UART4_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_4), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + + #ifdef UART_MODULE_5 + {HAL_LL_UART5_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_5), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + + + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {0, 0}, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR} +}; + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_uart_handle_register_t *low_level_handle; +static volatile hal_ll_uart_hw_specifics_map_t *hal_ll_uart_hw_specifics_map_local; + +/*!< @brief Global interrupt handlers used in functions */ +static hal_ll_uart_isr_t irq_handler; +static handle_t objects[UART_MODULE_COUNT]; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Check if pins are adequate. + * + * Checks tx and rx pins the user has passed with pre-defined + * pins in tx and rx maps. Take into consideration that module + * index numbers have to be the same for both pins. + * + * @param[in] tx_pin - TX pre-defined pin name. + * @param[in] rx_pin - RX pre-defined pin name. + * @param[in] *index_list - Array containing map index numbers. + * @return hal_ll_pin_name_t Module index based on pins. + * + * Returns pre-defined module index from pin maps, if pins + * are adequate. + */ +static hal_ll_pin_name_t hal_ll_uart_check_pins( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_uart_pin_id *index_list, hal_ll_uart_handle_register_t *handle_map ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * TX and RX pins. + * + * @param[in] module_index UART HW module index -- 0,1,2... + * @param[in] *index_list Array with TX and RX map index values + * and module number + * + * @return None + */ +static void hal_ll_uart_map_pins( uint8_t module_index, hal_ll_uart_pin_id *index_list ); + +/** + * @brief Sets UART pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if UART is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_state - Init/De-init + * + * @return void None. + */ +static void hal_ll_uart_alternate_functions_set_state( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_uart_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_uart_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_uart_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Enable clock for UART module on hardware level. + * + * Initializes UART module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_stat - True(enable clock)/False(disable clock). + * + * @return void None. + */ +static void hal_ll_uart_set_clock( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Finds UART module index. + * + * Finds UART index(module number) based on + * handle value. + * + * @param[in] handle - Object specific context handler. + * + * @return uint8_t Module number. + * Returns values from 0 to 9. + */ +static uint8_t hal_ll_uart_find_index( handle_t *handle ); + +/** + * @brief Get UART module clock speed. + * + * Returns adequate clock speed based on + * UART module base address. + * + * @param[in] module_index - UART module index number. + * + * @return uint8_t Module number. + * Returns clock value. + */ +static uint32_t hal_ll_uart_get_clock_speed( hal_ll_pin_name_t module_index ); + +/** + * @brief Clears UART registers. + * + * Clears UART module configuration + * registers, effectively disabling the module itself. + * Take into consideration that any IRQ bits + * are not cleared. + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * + * @return void None. + */ +static void hal_ll_uart_clear_regs( hal_ll_uart_base_handle_t *hal_ll_hw_reg ); + +/** + * @brief Sets desired baud rate on hardware level. + * + * Initializes module with specified baud rate value. + * Take into consideration that if the difference + * between desired baud rate and actual baud + * rate the hw was initialized to is greater than + * 1%, baud rate shall not be set. + * If this occurs, return value shall be + * the error percentage. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_set_baud_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Sets desired stop bits. + * + * Initializes module on hardware level + * with specified stop bit value. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_set_stop_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Sets desired data bits. + * + * Initializes module on hardware level + * with specified data bit bit value. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_set_data_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Sets desired parity. + * + * Initializes module on hardware level + * with specified parity value. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_set_parity_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Sets module clock value. + * + * Enables/disables specific UART module + * clock gate. + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * @param[in] pin_state - true(enable clock) / false(disable clock) + * + * @return void None. + */ +static void hal_ll_uart_set_module( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ); + +/** + * @brief Sets module TX line state. + * + * Enables/disables specific UART module + * TX pin state + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * @param[in] pin_state - true(enable transmitter pin) / false(disable transmitter pin) + * + * @return void None. + */ +static void hal_ll_uart_set_transmitter( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ); + +/** + * @brief Sets module RX line state. + * + * Enables/disables specific UART module + * RX pin state + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * @param[in] pin_state - true(enable receive pin) / false(disable receive pin) + * + * @return void None. + */ +static void hal_ll_uart_set_receiver( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ); + +/** + * @brief Initialize UART module. + * + * Enables UART module clogk gate first. + * Sets pin alternate function state. + * Initializes specific UART module. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_init( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Initialize UART module on the hardware level. + * + * Performs UART module initialization on + * the hardware level. + * + * Procedure: + * 1. Clears control registers + * 2. Sets data bit value + * 3. Sets parity value + * 4. Sets stop bit value + * 5. Sets baud rate value + * 6. Enables transmit pin + * 7. Enables receive pin + * 8. Enables clock gate for specific module + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_hw_init( hal_ll_uart_hw_specifics_map_t *map ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_uart_register_handle( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_uart_handle_register_t *handle_map, uint8_t *hal_module_id ) { + + hal_ll_uart_pin_id index_list[UART_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + uint16_t pin_check_result; + + // Check if pins are valid + if ( (pin_check_result = hal_ll_uart_check_pins( tx_pin, rx_pin, &index_list, handle_map )) == HAL_LL_PIN_NC ) { + return HAL_LL_UART_WRONG_PINS; + }; + + if ( (hal_ll_uart_hw_specifics_map[pin_check_result].pins.tx_pin.pin_name != tx_pin) || + (hal_ll_uart_hw_specifics_map[pin_check_result].pins.rx_pin.pin_name != rx_pin) ) + { + hal_ll_uart_alternate_functions_set_state( &hal_ll_uart_hw_specifics_map[ pin_check_result ], false ); + + hal_ll_uart_map_pins( pin_check_result, &index_list ); + + hal_ll_uart_alternate_functions_set_state( &hal_ll_uart_hw_specifics_map[ pin_check_result ], true ); + + handle_map[pin_check_result].init_ll_state = false; + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[pin_check_result].hal_ll_uart_handle = (handle_t *)&hal_ll_uart_hw_specifics_map[pin_check_result].base; + + handle_map[pin_check_result].hal_ll_uart_handle = (handle_t *)&hal_ll_module_state[pin_check_result].hal_ll_uart_handle; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_uart( handle_t *handle ) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + hal_ll_uart_pin_id index_list[UART_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + uint16_t pin_check_result; + + if ( (pin_check_result = hal_ll_uart_check_pins( hal_ll_uart_hw_specifics_map_local->pins.tx_pin.pin_name, + hal_ll_uart_hw_specifics_map_local->pins.rx_pin.pin_name, &index_list, (void *)0 ) ) == HAL_LL_PIN_NC ) { + return HAL_LL_UART_WRONG_PINS; + }; + + hal_ll_uart_init( hal_ll_uart_hw_specifics_map_local ); + + hal_ll_module_state[pin_check_result].hal_ll_uart_handle = (handle_t *)&hal_ll_uart_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_uart_set_baud( handle_t *handle, uint32_t baud ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->baud_rate.baud = baud; + + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return hal_ll_uart_hw_specifics_map_local->baud_rate.real_baud; +} + +hal_ll_err_t hal_ll_uart_set_parity( handle_t *handle, hal_ll_uart_parity_t parity ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->parity = parity; + + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_uart_set_stop_bits( handle_t *handle, hal_ll_uart_stop_bits_t stop_bit ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->stop_bit = stop_bit; + + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_uart_set_data_bits( handle_t *handle, hal_ll_uart_data_bits_t data_bit ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + // Chips using implementation 1 do not support 7 bit data + if( data_bit == HAL_LL_UART_DATA_BITS_7 ) { + return HAL_LL_UART_MODULE_ERROR; + } + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->data_bit = data_bit; + + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +void hal_ll_uart_close( handle_t *handle ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + if( low_level_handle->hal_ll_uart_handle != NULL ) { + hal_ll_uart_alternate_functions_set_state( hal_ll_uart_hw_specifics_map_local, false ); + + hal_ll_uart_irq_disable(handle, HAL_LL_UART_IRQ_RX); + hal_ll_uart_irq_disable(handle, HAL_LL_UART_IRQ_TX); + + hal_ll_uart_clear_regs(hal_ll_uart_hw_specifics_map_local->base); + hal_ll_uart_set_clock(hal_ll_uart_hw_specifics_map_local, false); + + hal_ll_uart_hw_specifics_map_local->pins.tx_pin.pin_name = HAL_LL_PIN_NC; + hal_ll_uart_hw_specifics_map_local->pins.tx_pin.pin_af = 0; + hal_ll_uart_hw_specifics_map_local->pins.rx_pin.pin_name = HAL_LL_PIN_NC; + hal_ll_uart_hw_specifics_map_local->pins.rx_pin.pin_af = 0; + + hal_ll_uart_hw_specifics_map_local->baud_rate.baud = 115200UL; + hal_ll_uart_hw_specifics_map_local->baud_rate.real_baud = 0; + + irq_handler = NULL; + objects[ hal_ll_uart_find_index( handle ) ] = NULL; + + low_level_handle->hal_ll_uart_handle = NULL; + low_level_handle->hal_drv_uart_handle = NULL; + + low_level_handle->init_ll_state = false; + } +} + +void hal_ll_uart_register_irq_handler( handle_t *handle, hal_ll_uart_isr_t handler, handle_t obj ) +{ + irq_handler = handler; + objects[ hal_ll_uart_find_index( handle ) ] = obj; +} + +void hal_ll_uart_irq_enable( handle_t *handle, hal_ll_uart_irq_t irq ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + switch ( irq ) { + case HAL_LL_UART_IRQ_RX: + __HAL_LL_UART_ENABLE_IT( hal_ll_hw_reg, HAL_LL_UART_IT_RXNE ); + break; + + case HAL_LL_UART_IRQ_TX: + __HAL_LL_UART_ENABLE_IT( hal_ll_hw_reg, HAL_LL_UART_IT_TXE ); + break; + + default: + break; + } + + switch ( hal_ll_uart_hw_specifics_map_local->module_index ) + { + #if defined(UART_MODULE_1) && defined(UART1_NVIC) + case hal_ll_uart_module_num(UART_MODULE_1): + hal_ll_core_enable_irq( UART1_NVIC ); + break; + #endif + + #if defined(UART_MODULE_2) && defined(UART2_NVIC) + case hal_ll_uart_module_num(UART_MODULE_2): + hal_ll_core_enable_irq( UART2_NVIC ); + break; + #endif + + #if defined(UART_MODULE_3) && defined(UART3_NVIC) + case hal_ll_uart_module_num(UART_MODULE_3): + hal_ll_core_enable_irq( UART3_NVIC ); + break; + #endif + + #if defined(UART_MODULE_4) && defined(UART4_NVIC) + case hal_ll_uart_module_num(UART_MODULE_4): + hal_ll_core_enable_irq( UART4_NVIC ); + break; + #endif + + #if defined(UART_MODULE_5) && defined(UART5_NVIC) + case hal_ll_uart_module_num(UART_MODULE_5): + hal_ll_core_enable_irq( UART5_NVIC ); + break; + #endif + + + default: + break; + } +} + +void hal_ll_uart_irq_disable( handle_t *handle, hal_ll_uart_irq_t irq ) +{ + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + switch ( irq ) { + case HAL_LL_UART_IRQ_RX: + __HAL_LL_UART_DISABLE_IT( hal_ll_hw_reg, HAL_LL_UART_IT_RXNE ); + break; + + case HAL_LL_UART_IRQ_TX: + __HAL_LL_UART_DISABLE_IT( hal_ll_hw_reg, HAL_LL_UART_IT_TXE ); + break; + + default: + break; + } + + // Check if module interrupt flags are set or not + if ( ( !check_reg_bit( &hal_ll_hw_reg->cr1, HAL_LL_UART_SR_RXNE ) ) && + ( !check_reg_bit( &hal_ll_hw_reg->cr1, HAL_LL_UART_SR_TXE ) ) ) + { + switch ( hal_ll_uart_hw_specifics_map_local->module_index ) + { + #if defined(UART_MODULE_1) && defined(UART1_NVIC) + case hal_ll_uart_module_num(UART_MODULE_1): + hal_ll_core_disable_irq( UART1_NVIC ); + break; + #endif + + #if defined(UART_MODULE_2) && defined(UART2_NVIC) + case hal_ll_uart_module_num(UART_MODULE_2): + hal_ll_core_disable_irq( UART2_NVIC ); + break; + #endif + + #if defined(UART_MODULE_3) && defined(UART3_NVIC) + case hal_ll_uart_module_num(UART_MODULE_3): + hal_ll_core_disable_irq( UART3_NVIC ); + break; + #endif + + #if defined(UART_MODULE_4) && defined(UART4_NVIC) + case hal_ll_uart_module_num(UART_MODULE_4): + hal_ll_core_disable_irq( UART4_NVIC ); + break; + #endif + + #if defined(UART_MODULE_5) && defined(UART5_NVIC) + case hal_ll_uart_module_num(UART_MODULE_5): + hal_ll_core_disable_irq( UART5_NVIC ); + break; + #endif + + + default: + break; + } + } +} + +void hal_ll_uart_write( handle_t *handle, uint8_t wr_data) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + hal_ll_hw_reg->tdr = wr_data; +} + +uint8_t hal_ll_uart_read( handle_t *handle ) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + return ( hal_ll_hw_reg->rdr ); +} + +// ------------------------------------------------------------- DEFAULT EXCEPTION HANDLERS + +#if defined(USART_MODULE_1) +void MARK_AS_IRQ_HANDLER UART1_IRQHandler() MIKROC_IV(UART1_NVIC) { + #ifdef USART_MODULE_1 + if( hal_ll_uart_get_status_flags( HAL_LL_USART1_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART1_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART1_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_1) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_USART1_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART1_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART1_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_1) ], HAL_LL_UART_IRQ_TX ); + } + } + #endif +} +#endif + +#if defined(USART_MODULE_2) +void MARK_AS_IRQ_HANDLER UART2_IRQHandler() MIKROC_IV(UART2_NVIC) { + #ifdef USART_MODULE_2 + if( hal_ll_uart_get_status_flags( HAL_LL_USART2_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART2_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART2_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_2) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_USART2_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART2_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART2_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_2) ], HAL_LL_UART_IRQ_TX ); + } + } + #endif +} +#endif + +#if defined(USART_MODULE_3) +void MARK_AS_IRQ_HANDLER UART3_IRQHandler() MIKROC_IV(UART3_NVIC) { + #ifdef USART_MODULE_3 + if( hal_ll_uart_get_status_flags( HAL_LL_USART3_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART3_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART3_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_3) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_USART3_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART3_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART3_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_3) ], HAL_LL_UART_IRQ_TX ); + } + } + #endif +} +#endif + +#if defined(UART_MODULE_4) +void MARK_AS_IRQ_HANDLER UART4_IRQHandler() MIKROC_IV(UART4_NVIC) { + #ifdef UART_MODULE_4 + if( hal_ll_uart_get_status_flags( HAL_LL_UART4_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_UART4_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_UART4_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(UART_MODULE_4) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_UART4_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_UART4_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_UART4_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(UART_MODULE_4) ], HAL_LL_UART_IRQ_TX ); + } + } + #endif +} +#endif + +#if defined(UART_MODULE_5) +void MARK_AS_IRQ_HANDLER UART5_IRQHandler() MIKROC_IV(UART5_NVIC) { + #ifdef UART_MODULE_5 + if( hal_ll_uart_get_status_flags( HAL_LL_UART5_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_UART5_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_UART5_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(UART_MODULE_5) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_UART5_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_UART5_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_UART5_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(UART_MODULE_5) ], HAL_LL_UART_IRQ_TX ); + } + } + #endif +} +#endif + +#if defined(LPUART_MODULE_1) +void MARK_AS_IRQ_HANDLER LPUART1_IRQHandler() MIKROC_IV(LPUART1_NVIC) { + #ifdef LPUART_MODULE_1 + if( hal_ll_uart_get_status_flags( HAL_LL_LPUART1_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_LPUART1_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_LPUART1_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(LPUART_MODULE_1) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_LPUART1_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_LPUART1_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_LPUART1_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(LPUART_MODULE_1) ], HAL_LL_UART_IRQ_TX ); + } + } + #endif +} +#endif + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static uint8_t hal_ll_uart_find_index( handle_t *handle ) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + if( hal_ll_uart_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + return hal_ll_uart_hw_specifics_map_local->module_index; + } else { + return NULL; + } +} + +static hal_ll_pin_name_t hal_ll_uart_check_pins( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_uart_pin_id *index_list, hal_ll_uart_handle_register_t *handle_map ) { + static const uint16_t tx_map_size = ( sizeof( hal_ll_uart_tx_map ) / sizeof( hal_ll_uart_pin_map_t ) ); + static const uint16_t rx_map_size = ( sizeof( hal_ll_uart_rx_map ) / sizeof( hal_ll_uart_pin_map_t ) ); + uint8_t hal_ll_module_id = 0; + uint8_t index_counter = 0; + uint16_t tx_index; + uint16_t rx_index; + + if ( (HAL_LL_PIN_NC == tx_pin) || (HAL_LL_PIN_NC == rx_pin) ) { + return HAL_LL_PIN_NC; + } + + for ( tx_index = 0; tx_index < tx_map_size; tx_index++ ) + { + if ( hal_ll_uart_tx_map[ tx_index ].pin == tx_pin ) + { + for ( rx_index = 0; rx_index < rx_map_size; rx_index++ ) + { + if ( hal_ll_uart_rx_map[ rx_index ].pin == rx_pin ) + { + if ( hal_ll_uart_tx_map[ tx_index ].base == hal_ll_uart_rx_map[ rx_index ].base ) { + // Get module number + hal_ll_module_id = hal_ll_uart_tx_map[ tx_index ].module_index; + + // Map pin names + index_list[hal_ll_module_id].pin_tx = tx_index; + index_list[hal_ll_module_id].pin_rx = rx_index; + + // Check if module is taken + if ( NULL == handle_map[ hal_ll_module_id ].hal_drv_uart_handle ) { + return hal_ll_module_id; + } else if ( UART_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static hal_ll_uart_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof(hal_ll_uart_handle_register_t)); + static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof(hal_ll_uart_handle_register_t)); + + while( hal_ll_module_count-- ) { + if (hal_ll_uart_get_base_from_hal_handle == hal_ll_uart_hw_specifics_map[hal_ll_module_count].base) { + return &hal_ll_uart_hw_specifics_map[hal_ll_module_count]; + } + } + + return &hal_ll_uart_hw_specifics_map[hal_ll_module_error]; +} + +static void hal_ll_uart_set_clock( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ) { + switch ( map->module_index ) + { + #ifdef UART_MODULE_1 + case ( hal_ll_uart_module_num(UART_MODULE_1) ): + (hal_ll_state == true)?(set_reg_bit( _RCC_APB2ENR, HAL_LL_USART1EN )):(clear_reg_bit( _RCC_APB2ENR, HAL_LL_USART1EN )); + break; + #endif + + #ifdef UART_MODULE_2 + case ( hal_ll_uart_module_num(UART_MODULE_2) ): + (hal_ll_state == true)?(set_reg_bit( _RCC_APB1ENR1, HAL_LL_USART2EN )):(clear_reg_bit( _RCC_APB1ENR1, HAL_LL_USART2EN )); + break; + #endif + + #ifdef UART_MODULE_3 + case ( hal_ll_uart_module_num(UART_MODULE_3) ): + (hal_ll_state == true)?(set_reg_bit( _RCC_APB1ENR1, HAL_LL_USART3EN )):(clear_reg_bit( _RCC_APB1ENR1, HAL_LL_USART3EN )); + break; + #endif + + #ifdef UART_MODULE_4 + case ( hal_ll_uart_module_num(UART_MODULE_4) ): + (hal_ll_state == true)?(set_reg_bit( _RCC_APB1ENR1, HAL_LL_USART4EN )):(clear_reg_bit( _RCC_APB1ENR1, HAL_LL_USART4EN )); + break; + #endif + + #ifdef UART_MODULE_5 + case ( hal_ll_uart_module_num(UART_MODULE_5) ): + (hal_ll_state == true)?(set_reg_bit( _RCC_APB1ENR1, HAL_LL_USART5EN )):(clear_reg_bit( _RCC_APB1ENR1, HAL_LL_USART5EN )); + break; + #endif + + + default: + break; + } +} + +static void hal_ll_uart_map_pins( uint8_t module_index, hal_ll_uart_pin_id *index_list ) { + // Map new pins + hal_ll_uart_hw_specifics_map[module_index].pins.tx_pin.pin_name = hal_ll_uart_tx_map[ index_list[module_index].pin_tx ].pin; + hal_ll_uart_hw_specifics_map[module_index].pins.rx_pin.pin_name = hal_ll_uart_rx_map[ index_list[module_index].pin_rx ].pin; + // TX and RX could have different alternate function settings, hence save both AF values + hal_ll_uart_hw_specifics_map[module_index].pins.tx_pin.pin_af = hal_ll_uart_tx_map[ index_list[module_index].pin_tx ].af; + hal_ll_uart_hw_specifics_map[module_index].pins.rx_pin.pin_af = hal_ll_uart_rx_map[ index_list[module_index].pin_rx ].af; +} + +static void hal_ll_uart_alternate_functions_set_state( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ) { + module_struct module; + + if ( (map->pins.tx_pin.pin_name != HAL_LL_PIN_NC) && map->pins.rx_pin.pin_name != HAL_LL_PIN_NC ) { + module.pins[0] = VALUE( map->pins.tx_pin.pin_name, map->pins.tx_pin.pin_af ); + module.pins[1] = VALUE( map->pins.rx_pin.pin_name, map->pins.rx_pin.pin_af ); + module.pins[2] = GPIO_MODULE_STRUCT_END; + + module.configs[0] = HAL_LL_UART_AF_CONFIG; + module.configs[1] = HAL_LL_UART_AF_CONFIG; + module.configs[2] = GPIO_MODULE_STRUCT_END; + + /* STM32F1xx specific */ + module.gpio_remap = map->pins.tx_pin.pin_af; + + hal_ll_gpio_module_struct_init( &module, hal_ll_state ); + } +} + +static void hal_ll_uart_set_baud_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + uint32_t reg = 0; + uint32_t integer_divider = 0; + uint32_t fractional_divider = 0; + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); + uint32_t hal_ll_baud_value = hal_ll_uart_get_baud(hal_ll_uart_get_clock_speed(map->module_index),map->baud_rate.baud,4); + uint32_t hal_ll_baud_real_value = hal_ll_uart_get_real_baud(hal_ll_uart_get_clock_speed(map->module_index),hal_ll_baud_value,4); + + // if error greater than specified, cancel setting baud rate + if( (hal_ll_uart_get_baud_error(hal_ll_baud_real_value,map->baud_rate.baud)) > HAL_LL_UART_ACCEPTABLE_ERROR ) { + map->baud_rate.real_baud = hal_ll_uart_get_baud_error(hal_ll_baud_real_value,map->baud_rate.baud); + } else { + map->baud_rate.real_baud = hal_ll_baud_real_value; + + integer_divider = ( ( 25 * hal_ll_uart_get_clock_speed( map->module_index ) ) / ( 4 * ( map->baud_rate.baud ) ) ); + reg = ( integer_divider / 100 ) << 4; + + fractional_divider = integer_divider - ( 100 * ( reg >> 4 ) ); + reg |= ( ( ( ( fractional_divider * 16 ) + 50 ) / 100 ) ) & 0x0F; + + hal_ll_hw_reg->brr = ( uint16_t )reg; + } +} + +static uint32_t hal_ll_uart_get_clock_speed( hal_ll_pin_name_t module_index ) { + rcc_clocks_t rcc_clocks; + + RCC_GetClocksFrequency( &rcc_clocks ); + + switch ( module_index ) + { + #ifdef UART_MODULE_1 + case ( hal_ll_uart_module_num(UART_MODULE_1) ): + return rcc_clocks.pclk2; + break; + #endif + + #ifdef UART_MODULE_2 + case ( hal_ll_uart_module_num(UART_MODULE_2) ): + return rcc_clocks.pclk1; + break; + #endif + + #ifdef UART_MODULE_3 + case ( hal_ll_uart_module_num(UART_MODULE_3) ): + return rcc_clocks.pclk1; + break; + #endif + + #ifdef UART_MODULE_4 + case ( hal_ll_uart_module_num(UART_MODULE_4) ): + return rcc_clocks.pclk1; + break; + #endif + + #ifdef UART_MODULE_5 + case ( hal_ll_uart_module_num(UART_MODULE_5) ): + return rcc_clocks.pclk1; + break; + #endif + + + default: + break; + } + + return NULL; +} + +static void hal_ll_uart_set_stop_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); + + switch ( map->stop_bit ) + { + case HAL_LL_UART_STOP_BITS_HALF: + hal_ll_hw_reg->cr2 |= STOP_BITS_HALF; + break; + case HAL_LL_UART_STOP_BITS_ONE: + hal_ll_hw_reg->cr2 |= STOP_BITS_ONE; + break; + case HAL_LL_UART_STOP_BITS_ONE_AND_A_HALF: + hal_ll_hw_reg->cr2 |= STOP_BITS_ONE_AND_A_HALF; + break; + case HAL_LL_UART_STOP_BITS_TWO: + hal_ll_hw_reg->cr2 |= STOP_BITS_TWO; + break; + + default: + break; + } +} + +static void hal_ll_uart_set_data_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); + + switch ( map->data_bit ) + { + case HAL_LL_UART_DATA_BITS_7: + hal_ll_hw_reg->cr1 |= DATA_BIT_7; + break; + + case HAL_LL_UART_DATA_BITS_8: + hal_ll_hw_reg->cr1 |= DATA_BIT_8; + break; + + case HAL_LL_UART_DATA_BITS_9: + hal_ll_hw_reg->cr1 |= DATA_BIT_9; + break; + + + default: + break; + } +} + +static void hal_ll_uart_set_parity_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); + + switch ( map->parity ) + { + case HAL_LL_UART_PARITY_NONE: + hal_ll_hw_reg->cr1 |= PARITY_NO; + break; + case HAL_LL_UART_PARITY_EVEN: + hal_ll_hw_reg->cr1 |= PARITY_ENABLED | PARITY_EVEN; + break; + case HAL_LL_UART_PARITY_ODD: + hal_ll_hw_reg->cr1 |= PARITY_ENABLED | PARITY_ODD; + break; + + default: + break; + } +} + +static void hal_ll_uart_set_module( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ) { + switch ( pin_state ) + { + case HAL_LL_UART_DISABLE: + clear_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_UE ); + break; + + case HAL_LL_UART_ENABLE: + set_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_UE ); + break; + + default: + break; + } +} + +static void hal_ll_uart_set_transmitter( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ) { + switch ( pin_state ) + { + case HAL_LL_UART_DISABLE: + clear_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_TE ); + break; + + case HAL_LL_UART_ENABLE: + set_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_TE ); + break; + + default: + break; + } +} + +static void hal_ll_uart_set_receiver( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ) { + switch ( pin_state ) + { + case HAL_LL_UART_DISABLE: + clear_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_RE ); + break; + + case HAL_LL_UART_ENABLE: + set_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_RE ); + break; + + default: + break; + } +} + +static void hal_ll_uart_clear_regs( hal_ll_uart_base_handle_t *hal_ll_hw_reg ) { + hal_ll_hw_reg->cr1 &= HAL_LL_UART_IT_CR1_MASK; + hal_ll_hw_reg->cr2 &= HAL_LL_UART_IT_CR2_MASK; + hal_ll_hw_reg->cr3 &= HAL_LL_UART_IT_CR3_MASK; +} + +static void hal_ll_uart_hw_init( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_clear_regs( map->base ); + + hal_ll_uart_set_data_bits_bare_metal( map ); + + hal_ll_uart_set_parity_bare_metal( map ); + + hal_ll_uart_set_stop_bits_bare_metal( map ); + + hal_ll_uart_set_baud_bare_metal( map ); + + hal_ll_uart_set_transmitter( map->base, HAL_LL_UART_ENABLE ); + + hal_ll_uart_set_receiver( map->base, HAL_LL_UART_ENABLE ); + + hal_ll_uart_set_module( map->base, HAL_LL_UART_ENABLE ); +} + +static void hal_ll_uart_init( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_set_clock( map, true ); + + hal_ll_uart_alternate_functions_set_state( map, true ); + + hal_ll_uart_hw_init( map ); +} +// ------------------------------------------------------------------------- END + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_2/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_2/CMakeLists.cmake new file mode 100644 index 000000000..702bb9878 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_2/CMakeLists.cmake @@ -0,0 +1,9 @@ +if(${MCU_NAME} MATCHES "^STM32C031C4$|^STM32C031F4$|^STM32C031G4$|^STM32C031K4$|^STM32C031C6$|^STM32C031F6$|^STM32C031G6$|^STM32C031K6$") + set(uart_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_uart.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_2") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_2") + list(APPEND hal_ll_def_list "STM32C0xx") + list(APPEND hal_ll_def_list "STM32C03xx") + list(APPEND hal_ll_def_list "STM32C031xx") + set(uart_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/uart/hal_ll_uart_pin_map/implementations/doc_ds_2") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_2/hal_ll_uart.c b/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_2/hal_ll_uart.c new file mode 100644 index 000000000..258b79661 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_2/hal_ll_uart.c @@ -0,0 +1,1089 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_uart.c + * @brief UART HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_rcc.h" +#include "hal_ll_uart.h" +#include "hal_ll_gpio.h" +#include "hal_ll_core.h" +#include "hal_ll_core_defines.h" +#include "hal_ll_uart_pin_map.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_uart_handle_register_t hal_ll_module_state[UART_MODULE_COUNT] = { (handle_t *)NULL, (handle_t *)NULL, false }; + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_uart_get_module_state_address ((hal_ll_uart_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_uart_get_handle (hal_ll_uart_handle_register_t *)hal_ll_uart_get_module_state_address->hal_ll_uart_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_uart_get_base_struct(_handle) ((hal_ll_uart_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_uart_get_base_from_hal_handle ((hal_ll_uart_hw_specifics_map_t *)((hal_ll_uart_handle_register_t *)\ + (((hal_ll_uart_handle_register_t *)(handle))->hal_ll_uart_handle))->hal_ll_uart_handle)->base + +/*!< @brief Macros used for calculating actual baud rate value and error value */ +#define HAL_LL_UART_ACCEPTABLE_ERROR (float)1.0 +#define hal_ll_uart_get_baud(_clock,_baud,_div) (((_clock/(float)_baud)/_div)-1) +#define hal_ll_uart_get_real_baud(_clock,_baud,_div) (_clock/(_div*(_baud+1))) +#define hal_ll_uart_get_baud_error(_baud_real,_baud) (((float)(abs(_baud_real-_baud))/_baud)*100) + +/*!< @brief Macros defining bit location */ +#define HAL_LL_USART1EN 14 + +#define HAL_LL_USART2EN 17 + + +#define HAL_LL_UART_CR1_UE 0 +#define HAL_LL_UART_CR1_TE 3 +#define HAL_LL_UART_CR1_RE 2 + +#define HAL_LL_UART_SR_RXNE 5 +#define HAL_LL_UART_SR_TXE 7 + +/*!< @brief Macros defining register bit values */ +#define STOP_BITS_HALF 0x1000U +#define STOP_BITS_ONE 0x00U +#define STOP_BITS_ONE_AND_A_HALF 0x3000U +#define STOP_BITS_TWO 0x2000U + +#define DATA_BIT_7 0x10000000U +#define DATA_BIT_8 0x00U +#define DATA_BIT_9 0x1000U + +#define PARITY_NO 0x00U +#define PARITY_ENABLED 0x400U + +#define PARITY_EVEN 0x00U +#define PARITY_ODD 0x200U + +/*!< @brief Macro used for setting pin alternate functions */ +#define HAL_LL_UART_AF_CONFIG (GPIO_CFG_MODE_ALT_FUNCTION | GPIO_CFG_SPEED_HIGH | GPIO_CFG_OTYPE_PP) + +/*!< @brief Macros used for interrupts */ +#define HAL_LL_UART_IT_MASK 0xFFFFUL +#define HAL_LL_UART_IT_CLEAR_MASK 0x123bffU +#define HAL_LL_UART_IT_CR1_MASK 0x1f0U +#define HAL_LL_UART_IT_CR2_MASK 0x40U +#define HAL_LL_UART_IT_CR3_MASK 0x401U + +#define HAL_LL_UART_CR1_REG_INDEX 1 +#define HAL_LL_UART_CR2_REG_INDEX 2 +#define HAL_LL_UART_CR3_REG_INDEX 3 + +#define HAL_LL_UART_IT_PE 0x100U +#define HAL_LL_UART_IT_TXE (0x10000000 | 0x80U) +#define HAL_LL_UART_IT_TC 0x40U +#define HAL_LL_UART_IT_RXNE (0x10000000 | 0x20U) +#define HAL_LL_UART_IT_IDLE 0x10U +#define HAL_LL_UART_IT_LBD 0x40U +#define HAL_LL_UART_IT_CTS 0x400U +#define HAL_LL_UART_IT_ERR 0x01U + +#define HAL_LL_UART_STATUS_RXNE_FLAG 0x20U +#define HAL_LL_UART_STATUS_TXE_FLAG 0x80U + +/*!< @brief Macro used for status registed flag check + * Used in interrupt handlers. + */ +#define hal_ll_uart_get_status_flags(_handle,_flag) (((hal_ll_uart_base_handle_t *)_handle)->isr & _flag) + +/*!< @brief Macro used for status register flag clearing + * Used in interrupt handlers. + */ +#define hal_ll_uart_clear_status_flag(_handle,_flag) (set_reg_bit( &(((hal_ll_uart_base_handle_t *)_handle)->icr), ( _flag & HAL_LL_UART_IT_CLEAR_MASK ) ) ) + +/*!< @brief Macro used for module interrupt enabling. + * Used in interrupt handlers. + */ +#define __HAL_LL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__ >> 28UL) == HAL_LL_UART_CR1_REG_INDEX)? (__HANDLE__->cr1 |= (__INTERRUPT__ & HAL_LL_UART_IT_MASK)): \ + ((__INTERRUPT__ >> 28UL) == HAL_LL_UART_CR2_REG_INDEX)? (__HANDLE__->cr2 |= (__INTERRUPT__ & HAL_LL_UART_IT_MASK)): \ + (__HANDLE__->cr3 |= (__INTERRUPT__ & HAL_LL_UART_IT_MASK))) + +/*!< @brief Macro used for module interrupt disabling. + * Used in interrupt handlers. + */ +#define __HAL_LL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__ >> 28UL) == HAL_LL_UART_CR1_REG_INDEX)? (__HANDLE__->cr1 &= ~(__INTERRUPT__ & HAL_LL_UART_IT_MASK)): \ + ((__INTERRUPT__ >> 28UL) == HAL_LL_UART_CR2_REG_INDEX)? (__HANDLE__->cr2 &= ~(__INTERRUPT__ & HAL_LL_UART_IT_MASK)): \ + (__HANDLE__->cr3 &= ~ (__INTERRUPT__ & HAL_LL_UART_IT_MASK))) + +/*!< @brief Macro used for module interrupt source check. + * Used in interrupt handlers. + */ +#define __HAL_LL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__ >> 28UL) == 1UL)? ((hal_ll_uart_base_handle_t *)__HANDLE__)->cr1:((((uint32_t)__INTERRUPT__ >> 28UL) == 2UL)? \ + ((hal_ll_uart_base_handle_t *)__HANDLE__)->cr2 : ((hal_ll_uart_base_handle_t *)__HANDLE__)->cr3)) & ((uint32_t)__INTERRUPT__ & HAL_LL_UART_IT_MASK)) + +/*!< @brief UART HW register structure */ +typedef struct +{ + hal_ll_base_addr_t cr1; + hal_ll_base_addr_t cr2; + hal_ll_base_addr_t cr3; + hal_ll_base_addr_t brr; + hal_ll_base_addr_t gtpr; + hal_ll_base_addr_t rtor; + hal_ll_base_addr_t rqr; + hal_ll_base_addr_t isr; + hal_ll_base_addr_t icr; + hal_ll_base_addr_t rdr; + hal_ll_base_addr_t tdr; + hal_ll_base_addr_t presc; + +} hal_ll_uart_base_handle_t; + +/*!< @brief UART baud rate structure */ +typedef struct +{ + uint32_t baud; + uint32_t real_baud; +} hal_ll_uart_baud_t; + +/*!< @brief UART hw specific structure */ +typedef struct +{ + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + hal_ll_uart_pins_t pins; + hal_ll_uart_baud_t baud_rate; + hal_ll_uart_parity_t parity; + hal_ll_uart_stop_bits_t stop_bit; + hal_ll_uart_data_bits_t data_bit; +} hal_ll_uart_hw_specifics_map_t; + +/*!< @brief UART hw specific module values */ +typedef struct +{ + uint16_t pin_tx; + uint16_t pin_rx; +} hal_ll_uart_pin_id; + +/*!< @brief UART hw specific error values */ +typedef enum +{ + HAL_LL_UART_SUCCESS = 0, + HAL_LL_UART_WRONG_PINS, + HAL_LL_UART_MODULE_ERROR, + + HAL_LL_UART_ERROR = (-1) +} hal_ll_uart_err_t; + +/*!< @brief UART module state selection */ +typedef enum +{ + HAL_LL_UART_DISABLE = 0, + HAL_LL_UART_ENABLE +} hal_ll_uart_state_t; + +// ------------------------------------------------------------------ VARIABLES +/*!< @brief UART hardware specific info */ +static hal_ll_uart_hw_specifics_map_t hal_ll_uart_hw_specifics_map[] = +{ + #ifdef UART_MODULE_1 + {HAL_LL_UART1_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_1), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + + #ifdef UART_MODULE_2 + {HAL_LL_UART2_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_2), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + + + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {0, 0}, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR} +}; + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_uart_handle_register_t *low_level_handle; +static volatile hal_ll_uart_hw_specifics_map_t *hal_ll_uart_hw_specifics_map_local; + +/*!< @brief Global interrupt handlers used in functions */ +static hal_ll_uart_isr_t irq_handler; +static handle_t objects[UART_MODULE_COUNT]; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Check if pins are adequate. + * + * Checks tx and rx pins the user has passed with pre-defined + * pins in tx and rx maps. Take into consideration that module + * index numbers have to be the same for both pins. + * + * @param[in] tx_pin - TX pre-defined pin name. + * @param[in] rx_pin - RX pre-defined pin name. + * @param[in] *index_list - Array containing map index numbers. + * @return hal_ll_pin_name_t Module index based on pins. + * + * Returns pre-defined module index from pin maps, if pins + * are adequate. + */ +static hal_ll_pin_name_t hal_ll_uart_check_pins( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_uart_pin_id *index_list, hal_ll_uart_handle_register_t *handle_map ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * TX and RX pins. + * + * @param[in] module_index UART HW module index -- 0,1,2... + * @param[in] *index_list Array with TX and RX map index values + * and module number + * + * @return None + */ +static void hal_ll_uart_map_pins( uint8_t module_index, hal_ll_uart_pin_id *index_list ); + +/** + * @brief Sets UART pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if UART is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_state - Init/De-init + * + * @return void None. + */ +static void hal_ll_uart_alternate_functions_set_state( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_uart_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_uart_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_uart_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Enable clock for UART module on hardware level. + * + * Initializes UART module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_stat - True(enable clock)/False(disable clock). + * + * @return void None. + */ +static void hal_ll_uart_set_clock( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Finds UART module index. + * + * Finds UART index(module number) based on + * handle value. + * + * @param[in] handle - Object specific context handler. + * + * @return uint8_t Module number. + * Returns values from 0 to 9. + */ +static uint8_t hal_ll_uart_find_index( handle_t *handle ); + +/** + * @brief Get UART module clock speed. + * + * Returns adequate clock speed based on + * UART module base address. + * + * @param[in] module_index - UART module index number. + * + * @return uint8_t Module number. + * Returns clock value. + */ +static uint32_t hal_ll_uart_get_clock_speed( hal_ll_pin_name_t module_index ); + +/** + * @brief Clears UART registers. + * + * Clears UART module configuration + * registers, effectively disabling the module itself. + * Take into consideration that any IRQ bits + * are not cleared. + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * + * @return void None. + */ +static void hal_ll_uart_clear_regs( hal_ll_uart_base_handle_t *hal_ll_hw_reg ); + +/** + * @brief Sets desired baud rate on hardware level. + * + * Initializes module with specified baud rate value. + * Take into consideration that if the difference + * between desired baud rate and actual baud + * rate the hw was initialized to is greater than + * 1%, baud rate shall not be set. + * If this occurs, return value shall be + * the error percentage. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_set_baud_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Sets desired stop bits. + * + * Initializes module on hardware level + * with specified stop bit value. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_set_stop_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Sets desired data bits. + * + * Initializes module on hardware level + * with specified data bit bit value. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_set_data_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Sets desired parity. + * + * Initializes module on hardware level + * with specified parity value. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_set_parity_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Sets module clock value. + * + * Enables/disables specific UART module + * clock gate. + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * @param[in] pin_state - true(enable clock) / false(disable clock) + * + * @return void None. + */ +static void hal_ll_uart_set_module( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ); + +/** + * @brief Sets module TX line state. + * + * Enables/disables specific UART module + * TX pin state + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * @param[in] pin_state - true(enable transmitter pin) / false(disable transmitter pin) + * + * @return void None. + */ +static void hal_ll_uart_set_transmitter( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ); + +/** + * @brief Sets module RX line state. + * + * Enables/disables specific UART module + * RX pin state + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * @param[in] pin_state - true(enable receive pin) / false(disable receive pin) + * + * @return void None. + */ +static void hal_ll_uart_set_receiver( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ); + +/** + * @brief Initialize UART module. + * + * Enables UART module clogk gate first. + * Sets pin alternate function state. + * Initializes specific UART module. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_init( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Initialize UART module on the hardware level. + * + * Performs UART module initialization on + * the hardware level. + * + * Procedure: + * 1. Clears control registers + * 2. Sets data bit value + * 3. Sets parity value + * 4. Sets stop bit value + * 5. Sets baud rate value + * 6. Enables transmit pin + * 7. Enables receive pin + * 8. Enables clock gate for specific module + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_hw_init( hal_ll_uart_hw_specifics_map_t *map ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_uart_register_handle( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_uart_handle_register_t *handle_map, uint8_t *hal_module_id ) { + + hal_ll_uart_pin_id index_list[UART_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + uint16_t pin_check_result; + + // Check if pins are valid + if ( (pin_check_result = hal_ll_uart_check_pins( tx_pin, rx_pin, &index_list, handle_map )) == HAL_LL_PIN_NC ) { + return HAL_LL_UART_WRONG_PINS; + }; + + if ( (hal_ll_uart_hw_specifics_map[pin_check_result].pins.tx_pin.pin_name != tx_pin) || + (hal_ll_uart_hw_specifics_map[pin_check_result].pins.rx_pin.pin_name != rx_pin) ) + { + hal_ll_uart_alternate_functions_set_state( &hal_ll_uart_hw_specifics_map[ pin_check_result ], false ); + + hal_ll_uart_map_pins( pin_check_result, &index_list ); + + hal_ll_uart_alternate_functions_set_state( &hal_ll_uart_hw_specifics_map[ pin_check_result ], true ); + + handle_map[pin_check_result].init_ll_state = false; + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[pin_check_result].hal_ll_uart_handle = (handle_t *)&hal_ll_uart_hw_specifics_map[pin_check_result].base; + + handle_map[pin_check_result].hal_ll_uart_handle = (handle_t *)&hal_ll_module_state[pin_check_result].hal_ll_uart_handle; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_uart( handle_t *handle ) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + hal_ll_uart_pin_id index_list[UART_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + uint16_t pin_check_result; + + if ( (pin_check_result = hal_ll_uart_check_pins( hal_ll_uart_hw_specifics_map_local->pins.tx_pin.pin_name, + hal_ll_uart_hw_specifics_map_local->pins.rx_pin.pin_name, &index_list, (void *)0 ) ) == HAL_LL_PIN_NC ) { + return HAL_LL_UART_WRONG_PINS; + }; + + hal_ll_uart_init( hal_ll_uart_hw_specifics_map_local ); + + hal_ll_module_state[pin_check_result].hal_ll_uart_handle = (handle_t *)&hal_ll_uart_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_uart_set_baud( handle_t *handle, uint32_t baud ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->baud_rate.baud = baud; + + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return hal_ll_uart_hw_specifics_map_local->baud_rate.real_baud; +} + +hal_ll_err_t hal_ll_uart_set_parity( handle_t *handle, hal_ll_uart_parity_t parity ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->parity = parity; + + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_uart_set_stop_bits( handle_t *handle, hal_ll_uart_stop_bits_t stop_bit ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->stop_bit = stop_bit; + + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_uart_set_data_bits( handle_t *handle, hal_ll_uart_data_bits_t data_bit ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + // Chips using implementation 1 do not support 7 bit data + if( data_bit == HAL_LL_UART_DATA_BITS_7 ) { + return HAL_LL_UART_MODULE_ERROR; + } + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->data_bit = data_bit; + + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +void hal_ll_uart_close( handle_t *handle ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + if( low_level_handle->hal_ll_uart_handle != NULL ) { + hal_ll_uart_alternate_functions_set_state( hal_ll_uart_hw_specifics_map_local, false ); + + hal_ll_uart_irq_disable(handle, HAL_LL_UART_IRQ_RX); + hal_ll_uart_irq_disable(handle, HAL_LL_UART_IRQ_TX); + + hal_ll_uart_clear_regs(hal_ll_uart_hw_specifics_map_local->base); + hal_ll_uart_set_clock(hal_ll_uart_hw_specifics_map_local, false); + + hal_ll_uart_hw_specifics_map_local->pins.tx_pin.pin_name = HAL_LL_PIN_NC; + hal_ll_uart_hw_specifics_map_local->pins.tx_pin.pin_af = 0; + hal_ll_uart_hw_specifics_map_local->pins.rx_pin.pin_name = HAL_LL_PIN_NC; + hal_ll_uart_hw_specifics_map_local->pins.rx_pin.pin_af = 0; + + hal_ll_uart_hw_specifics_map_local->baud_rate.baud = 115200UL; + hal_ll_uart_hw_specifics_map_local->baud_rate.real_baud = 0; + + irq_handler = NULL; + objects[ hal_ll_uart_find_index( handle ) ] = NULL; + + low_level_handle->hal_ll_uart_handle = NULL; + low_level_handle->hal_drv_uart_handle = NULL; + + low_level_handle->init_ll_state = false; + } +} + +void hal_ll_uart_register_irq_handler( handle_t *handle, hal_ll_uart_isr_t handler, handle_t obj ) +{ + irq_handler = handler; + objects[ hal_ll_uart_find_index( handle ) ] = obj; +} + +void hal_ll_uart_irq_enable( handle_t *handle, hal_ll_uart_irq_t irq ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + switch ( irq ) { + case HAL_LL_UART_IRQ_RX: + __HAL_LL_UART_ENABLE_IT( hal_ll_hw_reg, HAL_LL_UART_IT_RXNE ); + break; + + case HAL_LL_UART_IRQ_TX: + __HAL_LL_UART_ENABLE_IT( hal_ll_hw_reg, HAL_LL_UART_IT_TXE ); + break; + + default: + break; + } + + switch ( hal_ll_uart_hw_specifics_map_local->module_index ) + { + #if defined(UART_MODULE_1) && defined(UART1_NVIC) + case hal_ll_uart_module_num(UART_MODULE_1): + hal_ll_core_enable_irq( UART1_NVIC ); + break; + #endif + + #if defined(UART_MODULE_2) && defined(UART2_NVIC) + case hal_ll_uart_module_num(UART_MODULE_2): + hal_ll_core_enable_irq( UART2_NVIC ); + break; + #endif + + + default: + break; + } +} + +void hal_ll_uart_irq_disable( handle_t *handle, hal_ll_uart_irq_t irq ) +{ + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + switch ( irq ) { + case HAL_LL_UART_IRQ_RX: + __HAL_LL_UART_DISABLE_IT( hal_ll_hw_reg, HAL_LL_UART_IT_RXNE ); + break; + + case HAL_LL_UART_IRQ_TX: + __HAL_LL_UART_DISABLE_IT( hal_ll_hw_reg, HAL_LL_UART_IT_TXE ); + break; + + default: + break; + } + + // Check if module interrupt flags are set or not + if ( ( !check_reg_bit( &hal_ll_hw_reg->cr1, HAL_LL_UART_SR_RXNE ) ) && + ( !check_reg_bit( &hal_ll_hw_reg->cr1, HAL_LL_UART_SR_TXE ) ) ) + { + switch ( hal_ll_uart_hw_specifics_map_local->module_index ) + { + #if defined(UART_MODULE_1) && defined(UART1_NVIC) + case hal_ll_uart_module_num(UART_MODULE_1): + hal_ll_core_disable_irq( UART1_NVIC ); + break; + #endif + + #if defined(UART_MODULE_2) && defined(UART2_NVIC) + case hal_ll_uart_module_num(UART_MODULE_2): + hal_ll_core_disable_irq( UART2_NVIC ); + break; + #endif + + + default: + break; + } + } +} + +void hal_ll_uart_write( handle_t *handle, uint8_t wr_data) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + hal_ll_hw_reg->tdr = wr_data; +} + +uint8_t hal_ll_uart_read( handle_t *handle ) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + return ( hal_ll_hw_reg->rdr ); +} + +// ------------------------------------------------------------- DEFAULT EXCEPTION HANDLERS + +#if defined(USART_MODULE_1) +void MARK_AS_IRQ_HANDLER UART1_IRQHandler() MIKROC_IV(UART1_NVIC) { + #ifdef USART_MODULE_1 + if( hal_ll_uart_get_status_flags( HAL_LL_USART1_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART1_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART1_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_1) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_USART1_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART1_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART1_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_1) ], HAL_LL_UART_IRQ_TX ); + } + } + #endif +} +#endif + +#if defined(USART_MODULE_2) +void MARK_AS_IRQ_HANDLER UART2_IRQHandler() MIKROC_IV(UART2_NVIC) { + #ifdef USART_MODULE_2 + if( hal_ll_uart_get_status_flags( HAL_LL_USART2_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART2_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART2_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_2) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_USART2_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART2_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART2_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_2) ], HAL_LL_UART_IRQ_TX ); + } + } + #endif +} +#endif + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static uint8_t hal_ll_uart_find_index( handle_t *handle ) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + if( hal_ll_uart_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + return hal_ll_uart_hw_specifics_map_local->module_index; + } else { + return NULL; + } +} + +static hal_ll_pin_name_t hal_ll_uart_check_pins( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_uart_pin_id *index_list, hal_ll_uart_handle_register_t *handle_map ) { + static const uint16_t tx_map_size = ( sizeof( hal_ll_uart_tx_map ) / sizeof( hal_ll_uart_pin_map_t ) ); + static const uint16_t rx_map_size = ( sizeof( hal_ll_uart_rx_map ) / sizeof( hal_ll_uart_pin_map_t ) ); + uint8_t hal_ll_module_id = 0; + uint8_t index_counter = 0; + uint16_t tx_index; + uint16_t rx_index; + + if ( (HAL_LL_PIN_NC == tx_pin) || (HAL_LL_PIN_NC == rx_pin) ) { + return HAL_LL_PIN_NC; + } + + for ( tx_index = 0; tx_index < tx_map_size; tx_index++ ) + { + if ( hal_ll_uart_tx_map[ tx_index ].pin == tx_pin ) + { + for ( rx_index = 0; rx_index < rx_map_size; rx_index++ ) + { + if ( hal_ll_uart_rx_map[ rx_index ].pin == rx_pin ) + { + if ( hal_ll_uart_tx_map[ tx_index ].base == hal_ll_uart_rx_map[ rx_index ].base ) { + // Get module number + hal_ll_module_id = hal_ll_uart_tx_map[ tx_index ].module_index; + + // Map pin names + index_list[hal_ll_module_id].pin_tx = tx_index; + index_list[hal_ll_module_id].pin_rx = rx_index; + + // Check if module is taken + if ( NULL == handle_map[ hal_ll_module_id ].hal_drv_uart_handle ) { + return hal_ll_module_id; + } else if ( UART_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static hal_ll_uart_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof(hal_ll_uart_handle_register_t)); + static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof(hal_ll_uart_handle_register_t)); + + while( hal_ll_module_count-- ) { + if (hal_ll_uart_get_base_from_hal_handle == hal_ll_uart_hw_specifics_map[hal_ll_module_count].base) { + return &hal_ll_uart_hw_specifics_map[hal_ll_module_count]; + } + } + + return &hal_ll_uart_hw_specifics_map[hal_ll_module_error]; +} + +static void hal_ll_uart_set_clock( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ) { + switch ( map->module_index ) + { + #ifdef UART_MODULE_1 + case ( hal_ll_uart_module_num(UART_MODULE_1) ): + (hal_ll_state == true)?(set_reg_bit( _RCC_APBENR2, HAL_LL_USART1EN )):(clear_reg_bit( _RCC_APBENR2, HAL_LL_USART1EN )); + break; + #endif + + #ifdef UART_MODULE_2 + case ( hal_ll_uart_module_num(UART_MODULE_2) ): + (hal_ll_state == true)?(set_reg_bit( _RCC_APBENR1, HAL_LL_USART2EN )):(clear_reg_bit( _RCC_APBENR1, HAL_LL_USART2EN )); + break; + #endif + + + default: + break; + } +} + +static void hal_ll_uart_map_pins( uint8_t module_index, hal_ll_uart_pin_id *index_list ) { + // Map new pins + hal_ll_uart_hw_specifics_map[module_index].pins.tx_pin.pin_name = hal_ll_uart_tx_map[ index_list[module_index].pin_tx ].pin; + hal_ll_uart_hw_specifics_map[module_index].pins.rx_pin.pin_name = hal_ll_uart_rx_map[ index_list[module_index].pin_rx ].pin; + // TX and RX could have different alternate function settings, hence save both AF values + hal_ll_uart_hw_specifics_map[module_index].pins.tx_pin.pin_af = hal_ll_uart_tx_map[ index_list[module_index].pin_tx ].af; + hal_ll_uart_hw_specifics_map[module_index].pins.rx_pin.pin_af = hal_ll_uart_rx_map[ index_list[module_index].pin_rx ].af; +} + +static void hal_ll_uart_alternate_functions_set_state( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ) { + module_struct module; + + if ( (map->pins.tx_pin.pin_name != HAL_LL_PIN_NC) && map->pins.rx_pin.pin_name != HAL_LL_PIN_NC ) { + module.pins[0] = VALUE( map->pins.tx_pin.pin_name, map->pins.tx_pin.pin_af ); + module.pins[1] = VALUE( map->pins.rx_pin.pin_name, map->pins.rx_pin.pin_af ); + module.pins[2] = GPIO_MODULE_STRUCT_END; + + module.configs[0] = HAL_LL_UART_AF_CONFIG; + module.configs[1] = HAL_LL_UART_AF_CONFIG; + module.configs[2] = GPIO_MODULE_STRUCT_END; + + /* STM32F1xx specific */ + module.gpio_remap = map->pins.tx_pin.pin_af; + + hal_ll_gpio_module_struct_init( &module, hal_ll_state ); + } +} + +static void hal_ll_uart_set_baud_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + uint32_t reg = 0; + uint32_t integer_divider = 0; + uint32_t fractional_divider = 0; + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); + uint32_t hal_ll_baud_value = hal_ll_uart_get_baud(hal_ll_uart_get_clock_speed(map->module_index),map->baud_rate.baud,4); + uint32_t hal_ll_baud_real_value = hal_ll_uart_get_real_baud(hal_ll_uart_get_clock_speed(map->module_index),hal_ll_baud_value,4); + + // if error greater than specified, cancel setting baud rate + if( (hal_ll_uart_get_baud_error(hal_ll_baud_real_value,map->baud_rate.baud)) > HAL_LL_UART_ACCEPTABLE_ERROR ) { + map->baud_rate.real_baud = hal_ll_uart_get_baud_error(hal_ll_baud_real_value,map->baud_rate.baud); + } else { + map->baud_rate.real_baud = hal_ll_baud_real_value; + + integer_divider = ( ( 25 * hal_ll_uart_get_clock_speed( map->module_index ) ) / ( 4 * ( map->baud_rate.baud ) ) ); + reg = ( integer_divider / 100 ) << 4; + + fractional_divider = integer_divider - ( 100 * ( reg >> 4 ) ); + reg |= ( ( ( ( fractional_divider * 16 ) + 50 ) / 100 ) ) & 0x0F; + + hal_ll_hw_reg->brr = ( uint16_t )reg; + } +} + +static uint32_t hal_ll_uart_get_clock_speed( hal_ll_pin_name_t module_index ) { + rcc_clocks_t rcc_clocks; + + RCC_GetClocksFrequency( &rcc_clocks ); + + switch ( module_index ) + { + #ifdef UART_MODULE_1 + case ( hal_ll_uart_module_num(UART_MODULE_1) ): + return rcc_clocks.pclk; + break; + #endif + + #ifdef UART_MODULE_2 + case ( hal_ll_uart_module_num(UART_MODULE_2) ): + return rcc_clocks.pclk; + break; + #endif + + + default: + break; + } + + return NULL; +} + +static void hal_ll_uart_set_stop_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); + + switch ( map->stop_bit ) + { + case HAL_LL_UART_STOP_BITS_HALF: + hal_ll_hw_reg->cr2 |= STOP_BITS_HALF; + break; + case HAL_LL_UART_STOP_BITS_ONE: + hal_ll_hw_reg->cr2 |= STOP_BITS_ONE; + break; + case HAL_LL_UART_STOP_BITS_ONE_AND_A_HALF: + hal_ll_hw_reg->cr2 |= STOP_BITS_ONE_AND_A_HALF; + break; + case HAL_LL_UART_STOP_BITS_TWO: + hal_ll_hw_reg->cr2 |= STOP_BITS_TWO; + break; + + default: + break; + } +} + +static void hal_ll_uart_set_data_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); + + switch ( map->data_bit ) + { + case HAL_LL_UART_DATA_BITS_7: + hal_ll_hw_reg->cr1 |= DATA_BIT_7; + break; + + case HAL_LL_UART_DATA_BITS_8: + hal_ll_hw_reg->cr1 |= DATA_BIT_8; + break; + + case HAL_LL_UART_DATA_BITS_9: + hal_ll_hw_reg->cr1 |= DATA_BIT_9; + break; + + + default: + break; + } +} + +static void hal_ll_uart_set_parity_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); + + switch ( map->parity ) + { + case HAL_LL_UART_PARITY_NONE: + hal_ll_hw_reg->cr1 |= PARITY_NO; + break; + case HAL_LL_UART_PARITY_EVEN: + hal_ll_hw_reg->cr1 |= PARITY_ENABLED | PARITY_EVEN; + break; + case HAL_LL_UART_PARITY_ODD: + hal_ll_hw_reg->cr1 |= PARITY_ENABLED | PARITY_ODD; + break; + + default: + break; + } +} + +static void hal_ll_uart_set_module( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ) { + switch ( pin_state ) + { + case HAL_LL_UART_DISABLE: + clear_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_UE ); + break; + + case HAL_LL_UART_ENABLE: + set_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_UE ); + break; + + default: + break; + } +} + +static void hal_ll_uart_set_transmitter( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ) { + switch ( pin_state ) + { + case HAL_LL_UART_DISABLE: + clear_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_TE ); + break; + + case HAL_LL_UART_ENABLE: + set_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_TE ); + break; + + default: + break; + } +} + +static void hal_ll_uart_set_receiver( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ) { + switch ( pin_state ) + { + case HAL_LL_UART_DISABLE: + clear_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_RE ); + break; + + case HAL_LL_UART_ENABLE: + set_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_RE ); + break; + + default: + break; + } +} + +static void hal_ll_uart_clear_regs( hal_ll_uart_base_handle_t *hal_ll_hw_reg ) { + hal_ll_hw_reg->cr1 &= HAL_LL_UART_IT_CR1_MASK; + hal_ll_hw_reg->cr2 &= HAL_LL_UART_IT_CR2_MASK; + hal_ll_hw_reg->cr3 &= HAL_LL_UART_IT_CR3_MASK; +} + +static void hal_ll_uart_hw_init( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_clear_regs( map->base ); + + hal_ll_uart_set_data_bits_bare_metal( map ); + + hal_ll_uart_set_parity_bare_metal( map ); + + hal_ll_uart_set_stop_bits_bare_metal( map ); + + hal_ll_uart_set_baud_bare_metal( map ); + + hal_ll_uart_set_transmitter( map->base, HAL_LL_UART_ENABLE ); + + hal_ll_uart_set_receiver( map->base, HAL_LL_UART_ENABLE ); + + hal_ll_uart_set_module( map->base, HAL_LL_UART_ENABLE ); +} + +static void hal_ll_uart_init( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_set_clock( map, true ); + + hal_ll_uart_alternate_functions_set_state( map, true ); + + hal_ll_uart_hw_init( map ); +} +// ------------------------------------------------------------------------- END + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_74/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_74/CMakeLists.cmake new file mode 100644 index 000000000..03e366e95 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_74/CMakeLists.cmake @@ -0,0 +1,9 @@ +if(${MCU_NAME} MATCHES "^STM32G051C6$|^STM32G051F6$|^STM32G051G6$|^STM32G051K6$|^STM32G051C8$|^STM32G051F8$|^STM32G051G8$|^STM32G051K8$") + set(uart_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_uart.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_74") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_74") + list(APPEND hal_ll_def_list "STM32G0xx") + list(APPEND hal_ll_def_list "STM32G05xx") + list(APPEND hal_ll_def_list "STM32G051xx") + set(uart_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/uart/hal_ll_uart_pin_map/implementations/doc_ds_74") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_74/hal_ll_uart.c b/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_74/hal_ll_uart.c new file mode 100644 index 000000000..132180af8 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_74/hal_ll_uart.c @@ -0,0 +1,1108 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_uart.c + * @brief UART HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_rcc.h" +#include "hal_ll_uart.h" +#include "hal_ll_gpio.h" +#include "hal_ll_core.h" +#include "hal_ll_core_defines.h" +#include "hal_ll_uart_pin_map.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_uart_handle_register_t hal_ll_module_state[UART_MODULE_COUNT] = { (handle_t *)NULL, (handle_t *)NULL, false }; + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_uart_get_module_state_address ((hal_ll_uart_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_uart_get_handle (hal_ll_uart_handle_register_t *)hal_ll_uart_get_module_state_address->hal_ll_uart_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_uart_get_base_struct(_handle) ((hal_ll_uart_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_uart_get_base_from_hal_handle ((hal_ll_uart_hw_specifics_map_t *)((hal_ll_uart_handle_register_t *)\ + (((hal_ll_uart_handle_register_t *)(handle))->hal_ll_uart_handle))->hal_ll_uart_handle)->base + +/*!< @brief Macros used for calculating actual baud rate value and error value */ +#define HAL_LL_UART_ACCEPTABLE_ERROR (float)1.0 +#define hal_ll_uart_get_baud(_clock,_baud,_div) (((_clock/(float)_baud)/_div)-1) +#define hal_ll_uart_get_real_baud(_clock,_baud,_div) (_clock/(_div*(_baud+1))) +#define hal_ll_uart_get_baud_error(_baud_real,_baud) (((float)(abs(_baud_real-_baud))/_baud)*100) + +/*!< @brief Macros defining bit location */ +#define HAL_LL_USART1EN 14 + +#define HAL_LL_USART2EN 17 + + +#define HAL_LL_UART_CR1_UE 0 +#define HAL_LL_UART_CR1_TE 3 +#define HAL_LL_UART_CR1_RE 2 + +#define HAL_LL_UART_SR_RXNE 5 +#define HAL_LL_UART_SR_TXE 7 + +/*!< @brief Macros defining register bit values */ +#define STOP_BITS_HALF 0x1000U +#define STOP_BITS_ONE 0x00U +#define STOP_BITS_ONE_AND_A_HALF 0x3000U +#define STOP_BITS_TWO 0x2000U + +#define DATA_BIT_7 0x10000000U +#define DATA_BIT_8 0x00U +#define DATA_BIT_9 0x1000U + +#define PARITY_NO 0x00U +#define PARITY_ENABLED 0x400U + +#define PARITY_EVEN 0x00U +#define PARITY_ODD 0x200U + +/*!< @brief Macro used for setting pin alternate functions */ +#define HAL_LL_UART_AF_CONFIG (GPIO_CFG_MODE_ALT_FUNCTION | GPIO_CFG_SPEED_HIGH | GPIO_CFG_OTYPE_PP) + +/*!< @brief Macros used for interrupts */ +#define HAL_LL_UART_IT_MASK 0xFFFFUL +#define HAL_LL_UART_IT_CLEAR_MASK 0x123bffU +#define HAL_LL_UART_IT_CR1_MASK 0x1f0U +#define HAL_LL_UART_IT_CR2_MASK 0x40U +#define HAL_LL_UART_IT_CR3_MASK 0x401U + +#define HAL_LL_UART_CR1_REG_INDEX 1 +#define HAL_LL_UART_CR2_REG_INDEX 2 +#define HAL_LL_UART_CR3_REG_INDEX 3 + +#define HAL_LL_UART_IT_PE 0x100U +#define HAL_LL_UART_IT_TXE (0x10000000 | 0x80U) +#define HAL_LL_UART_IT_TC 0x40U +#define HAL_LL_UART_IT_RXNE (0x10000000 | 0x20U) +#define HAL_LL_UART_IT_IDLE 0x10U +#define HAL_LL_UART_IT_LBD 0x40U +#define HAL_LL_UART_IT_CTS 0x400U +#define HAL_LL_UART_IT_ERR 0x01U + +#define HAL_LL_UART_STATUS_RXNE_FLAG 0x20U +#define HAL_LL_UART_STATUS_TXE_FLAG 0x80U + +/*!< @brief Macro used for status registed flag check + * Used in interrupt handlers. + */ +#define hal_ll_uart_get_status_flags(_handle,_flag) (((hal_ll_uart_base_handle_t *)_handle)->isr & _flag) + +/*!< @brief Macro used for status register flag clearing + * Used in interrupt handlers. + */ +#define hal_ll_uart_clear_status_flag(_handle,_flag) (set_reg_bit( &(((hal_ll_uart_base_handle_t *)_handle)->icr), ( _flag & HAL_LL_UART_IT_CLEAR_MASK ) ) ) + +/*!< @brief Macro used for module interrupt enabling. + * Used in interrupt handlers. + */ +#define __HAL_LL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__ >> 28UL) == HAL_LL_UART_CR1_REG_INDEX)? (__HANDLE__->cr1 |= (__INTERRUPT__ & HAL_LL_UART_IT_MASK)): \ + ((__INTERRUPT__ >> 28UL) == HAL_LL_UART_CR2_REG_INDEX)? (__HANDLE__->cr2 |= (__INTERRUPT__ & HAL_LL_UART_IT_MASK)): \ + (__HANDLE__->cr3 |= (__INTERRUPT__ & HAL_LL_UART_IT_MASK))) + +/*!< @brief Macro used for module interrupt disabling. + * Used in interrupt handlers. + */ +#define __HAL_LL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__ >> 28UL) == HAL_LL_UART_CR1_REG_INDEX)? (__HANDLE__->cr1 &= ~(__INTERRUPT__ & HAL_LL_UART_IT_MASK)): \ + ((__INTERRUPT__ >> 28UL) == HAL_LL_UART_CR2_REG_INDEX)? (__HANDLE__->cr2 &= ~(__INTERRUPT__ & HAL_LL_UART_IT_MASK)): \ + (__HANDLE__->cr3 &= ~ (__INTERRUPT__ & HAL_LL_UART_IT_MASK))) + +/*!< @brief Macro used for module interrupt source check. + * Used in interrupt handlers. + */ +#define __HAL_LL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__ >> 28UL) == 1UL)? ((hal_ll_uart_base_handle_t *)__HANDLE__)->cr1:((((uint32_t)__INTERRUPT__ >> 28UL) == 2UL)? \ + ((hal_ll_uart_base_handle_t *)__HANDLE__)->cr2 : ((hal_ll_uart_base_handle_t *)__HANDLE__)->cr3)) & ((uint32_t)__INTERRUPT__ & HAL_LL_UART_IT_MASK)) + +/*!< @brief UART HW register structure */ +typedef struct +{ + hal_ll_base_addr_t cr1; + hal_ll_base_addr_t cr2; + hal_ll_base_addr_t cr3; + hal_ll_base_addr_t brr; + hal_ll_base_addr_t gtpr; + hal_ll_base_addr_t rtor; + hal_ll_base_addr_t rqr; + hal_ll_base_addr_t isr; + hal_ll_base_addr_t icr; + hal_ll_base_addr_t rdr; + hal_ll_base_addr_t tdr; + hal_ll_base_addr_t presc; + +} hal_ll_uart_base_handle_t; + +/*!< @brief UART baud rate structure */ +typedef struct +{ + uint32_t baud; + uint32_t real_baud; +} hal_ll_uart_baud_t; + +/*!< @brief UART hw specific structure */ +typedef struct +{ + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + hal_ll_uart_pins_t pins; + hal_ll_uart_baud_t baud_rate; + hal_ll_uart_parity_t parity; + hal_ll_uart_stop_bits_t stop_bit; + hal_ll_uart_data_bits_t data_bit; +} hal_ll_uart_hw_specifics_map_t; + +/*!< @brief UART hw specific module values */ +typedef struct +{ + uint16_t pin_tx; + uint16_t pin_rx; +} hal_ll_uart_pin_id; + +/*!< @brief UART hw specific error values */ +typedef enum +{ + HAL_LL_UART_SUCCESS = 0, + HAL_LL_UART_WRONG_PINS, + HAL_LL_UART_MODULE_ERROR, + + HAL_LL_UART_ERROR = (-1) +} hal_ll_uart_err_t; + +/*!< @brief UART module state selection */ +typedef enum +{ + HAL_LL_UART_DISABLE = 0, + HAL_LL_UART_ENABLE +} hal_ll_uart_state_t; + +// ------------------------------------------------------------------ VARIABLES +/*!< @brief UART hardware specific info */ +static hal_ll_uart_hw_specifics_map_t hal_ll_uart_hw_specifics_map[] = +{ + #ifdef UART_MODULE_1 + {HAL_LL_UART1_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_1), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + + #ifdef UART_MODULE_2 + {HAL_LL_UART2_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_2), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + + + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {0, 0}, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR} +}; + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_uart_handle_register_t *low_level_handle; +static volatile hal_ll_uart_hw_specifics_map_t *hal_ll_uart_hw_specifics_map_local; + +/*!< @brief Global interrupt handlers used in functions */ +static hal_ll_uart_isr_t irq_handler; +static handle_t objects[UART_MODULE_COUNT]; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Check if pins are adequate. + * + * Checks tx and rx pins the user has passed with pre-defined + * pins in tx and rx maps. Take into consideration that module + * index numbers have to be the same for both pins. + * + * @param[in] tx_pin - TX pre-defined pin name. + * @param[in] rx_pin - RX pre-defined pin name. + * @param[in] *index_list - Array containing map index numbers. + * @return hal_ll_pin_name_t Module index based on pins. + * + * Returns pre-defined module index from pin maps, if pins + * are adequate. + */ +static hal_ll_pin_name_t hal_ll_uart_check_pins( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_uart_pin_id *index_list, hal_ll_uart_handle_register_t *handle_map ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * TX and RX pins. + * + * @param[in] module_index UART HW module index -- 0,1,2... + * @param[in] *index_list Array with TX and RX map index values + * and module number + * + * @return None + */ +static void hal_ll_uart_map_pins( uint8_t module_index, hal_ll_uart_pin_id *index_list ); + +/** + * @brief Sets UART pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if UART is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_state - Init/De-init + * + * @return void None. + */ +static void hal_ll_uart_alternate_functions_set_state( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_uart_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_uart_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_uart_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Enable clock for UART module on hardware level. + * + * Initializes UART module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_stat - True(enable clock)/False(disable clock). + * + * @return void None. + */ +static void hal_ll_uart_set_clock( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Finds UART module index. + * + * Finds UART index(module number) based on + * handle value. + * + * @param[in] handle - Object specific context handler. + * + * @return uint8_t Module number. + * Returns values from 0 to 9. + */ +static uint8_t hal_ll_uart_find_index( handle_t *handle ); + +/** + * @brief Get UART module clock speed. + * + * Returns adequate clock speed based on + * UART module base address. + * + * @param[in] module_index - UART module index number. + * + * @return uint8_t Module number. + * Returns clock value. + */ +static uint32_t hal_ll_uart_get_clock_speed( hal_ll_pin_name_t module_index ); + +/** + * @brief Clears UART registers. + * + * Clears UART module configuration + * registers, effectively disabling the module itself. + * Take into consideration that any IRQ bits + * are not cleared. + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * + * @return void None. + */ +static void hal_ll_uart_clear_regs( hal_ll_uart_base_handle_t *hal_ll_hw_reg ); + +/** + * @brief Sets desired baud rate on hardware level. + * + * Initializes module with specified baud rate value. + * Take into consideration that if the difference + * between desired baud rate and actual baud + * rate the hw was initialized to is greater than + * 1%, baud rate shall not be set. + * If this occurs, return value shall be + * the error percentage. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_set_baud_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Sets desired stop bits. + * + * Initializes module on hardware level + * with specified stop bit value. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_set_stop_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Sets desired data bits. + * + * Initializes module on hardware level + * with specified data bit bit value. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_set_data_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Sets desired parity. + * + * Initializes module on hardware level + * with specified parity value. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_set_parity_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Sets module clock value. + * + * Enables/disables specific UART module + * clock gate. + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * @param[in] pin_state - true(enable clock) / false(disable clock) + * + * @return void None. + */ +static void hal_ll_uart_set_module( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ); + +/** + * @brief Sets module TX line state. + * + * Enables/disables specific UART module + * TX pin state + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * @param[in] pin_state - true(enable transmitter pin) / false(disable transmitter pin) + * + * @return void None. + */ +static void hal_ll_uart_set_transmitter( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ); + +/** + * @brief Sets module RX line state. + * + * Enables/disables specific UART module + * RX pin state + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * @param[in] pin_state - true(enable receive pin) / false(disable receive pin) + * + * @return void None. + */ +static void hal_ll_uart_set_receiver( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ); + +/** + * @brief Initialize UART module. + * + * Enables UART module clogk gate first. + * Sets pin alternate function state. + * Initializes specific UART module. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_init( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Initialize UART module on the hardware level. + * + * Performs UART module initialization on + * the hardware level. + * + * Procedure: + * 1. Clears control registers + * 2. Sets data bit value + * 3. Sets parity value + * 4. Sets stop bit value + * 5. Sets baud rate value + * 6. Enables transmit pin + * 7. Enables receive pin + * 8. Enables clock gate for specific module + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_hw_init( hal_ll_uart_hw_specifics_map_t *map ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_uart_register_handle( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_uart_handle_register_t *handle_map, uint8_t *hal_module_id ) { + + hal_ll_uart_pin_id index_list[UART_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + uint16_t pin_check_result; + + // Check if pins are valid + if ( (pin_check_result = hal_ll_uart_check_pins( tx_pin, rx_pin, &index_list, handle_map )) == HAL_LL_PIN_NC ) { + return HAL_LL_UART_WRONG_PINS; + }; + + if ( (hal_ll_uart_hw_specifics_map[pin_check_result].pins.tx_pin.pin_name != tx_pin) || + (hal_ll_uart_hw_specifics_map[pin_check_result].pins.rx_pin.pin_name != rx_pin) ) + { + hal_ll_uart_alternate_functions_set_state( &hal_ll_uart_hw_specifics_map[ pin_check_result ], false ); + + hal_ll_uart_map_pins( pin_check_result, &index_list ); + + hal_ll_uart_alternate_functions_set_state( &hal_ll_uart_hw_specifics_map[ pin_check_result ], true ); + + handle_map[pin_check_result].init_ll_state = false; + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[pin_check_result].hal_ll_uart_handle = (handle_t *)&hal_ll_uart_hw_specifics_map[pin_check_result].base; + + handle_map[pin_check_result].hal_ll_uart_handle = (handle_t *)&hal_ll_module_state[pin_check_result].hal_ll_uart_handle; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_uart( handle_t *handle ) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + hal_ll_uart_pin_id index_list[UART_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + uint16_t pin_check_result; + + if ( (pin_check_result = hal_ll_uart_check_pins( hal_ll_uart_hw_specifics_map_local->pins.tx_pin.pin_name, + hal_ll_uart_hw_specifics_map_local->pins.rx_pin.pin_name, &index_list, (void *)0 ) ) == HAL_LL_PIN_NC ) { + return HAL_LL_UART_WRONG_PINS; + }; + + hal_ll_uart_init( hal_ll_uart_hw_specifics_map_local ); + + hal_ll_module_state[pin_check_result].hal_ll_uart_handle = (handle_t *)&hal_ll_uart_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_uart_set_baud( handle_t *handle, uint32_t baud ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->baud_rate.baud = baud; + + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return hal_ll_uart_hw_specifics_map_local->baud_rate.real_baud; +} + +hal_ll_err_t hal_ll_uart_set_parity( handle_t *handle, hal_ll_uart_parity_t parity ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->parity = parity; + + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_uart_set_stop_bits( handle_t *handle, hal_ll_uart_stop_bits_t stop_bit ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->stop_bit = stop_bit; + + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_uart_set_data_bits( handle_t *handle, hal_ll_uart_data_bits_t data_bit ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + // Chips using implementation 1 do not support 7 bit data + if( data_bit == HAL_LL_UART_DATA_BITS_7 ) { + return HAL_LL_UART_MODULE_ERROR; + } + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->data_bit = data_bit; + + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +void hal_ll_uart_close( handle_t *handle ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + if( low_level_handle->hal_ll_uart_handle != NULL ) { + hal_ll_uart_alternate_functions_set_state( hal_ll_uart_hw_specifics_map_local, false ); + + hal_ll_uart_irq_disable(handle, HAL_LL_UART_IRQ_RX); + hal_ll_uart_irq_disable(handle, HAL_LL_UART_IRQ_TX); + + hal_ll_uart_clear_regs(hal_ll_uart_hw_specifics_map_local->base); + hal_ll_uart_set_clock(hal_ll_uart_hw_specifics_map_local, false); + + hal_ll_uart_hw_specifics_map_local->pins.tx_pin.pin_name = HAL_LL_PIN_NC; + hal_ll_uart_hw_specifics_map_local->pins.tx_pin.pin_af = 0; + hal_ll_uart_hw_specifics_map_local->pins.rx_pin.pin_name = HAL_LL_PIN_NC; + hal_ll_uart_hw_specifics_map_local->pins.rx_pin.pin_af = 0; + + hal_ll_uart_hw_specifics_map_local->baud_rate.baud = 115200UL; + hal_ll_uart_hw_specifics_map_local->baud_rate.real_baud = 0; + + irq_handler = NULL; + objects[ hal_ll_uart_find_index( handle ) ] = NULL; + + low_level_handle->hal_ll_uart_handle = NULL; + low_level_handle->hal_drv_uart_handle = NULL; + + low_level_handle->init_ll_state = false; + } +} + +void hal_ll_uart_register_irq_handler( handle_t *handle, hal_ll_uart_isr_t handler, handle_t obj ) +{ + irq_handler = handler; + objects[ hal_ll_uart_find_index( handle ) ] = obj; +} + +void hal_ll_uart_irq_enable( handle_t *handle, hal_ll_uart_irq_t irq ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + switch ( irq ) { + case HAL_LL_UART_IRQ_RX: + __HAL_LL_UART_ENABLE_IT( hal_ll_hw_reg, HAL_LL_UART_IT_RXNE ); + break; + + case HAL_LL_UART_IRQ_TX: + __HAL_LL_UART_ENABLE_IT( hal_ll_hw_reg, HAL_LL_UART_IT_TXE ); + break; + + default: + break; + } + + switch ( hal_ll_uart_hw_specifics_map_local->module_index ) + { + #if defined(UART_MODULE_1) && defined(UART1_NVIC) + case hal_ll_uart_module_num(UART_MODULE_1): + hal_ll_core_enable_irq( UART1_NVIC ); + break; + #endif + + #if defined(UART_MODULE_2) && defined(UART2_NVIC) + case hal_ll_uart_module_num(UART_MODULE_2): + hal_ll_core_enable_irq( UART2_NVIC ); + break; + #endif + + + default: + break; + } +} + +void hal_ll_uart_irq_disable( handle_t *handle, hal_ll_uart_irq_t irq ) +{ + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + switch ( irq ) { + case HAL_LL_UART_IRQ_RX: + __HAL_LL_UART_DISABLE_IT( hal_ll_hw_reg, HAL_LL_UART_IT_RXNE ); + break; + + case HAL_LL_UART_IRQ_TX: + __HAL_LL_UART_DISABLE_IT( hal_ll_hw_reg, HAL_LL_UART_IT_TXE ); + break; + + default: + break; + } + + // Check if module interrupt flags are set or not + if ( ( !check_reg_bit( &hal_ll_hw_reg->cr1, HAL_LL_UART_SR_RXNE ) ) && + ( !check_reg_bit( &hal_ll_hw_reg->cr1, HAL_LL_UART_SR_TXE ) ) ) + { + switch ( hal_ll_uart_hw_specifics_map_local->module_index ) + { + #if defined(UART_MODULE_1) && defined(UART1_NVIC) + case hal_ll_uart_module_num(UART_MODULE_1): + hal_ll_core_disable_irq( UART1_NVIC ); + break; + #endif + + #if defined(UART_MODULE_2) && defined(UART2_NVIC) + case hal_ll_uart_module_num(UART_MODULE_2): + hal_ll_core_disable_irq( UART2_NVIC ); + break; + #endif + + + default: + break; + } + } +} + +void hal_ll_uart_write( handle_t *handle, uint8_t wr_data) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + hal_ll_hw_reg->tdr = wr_data; +} + +uint8_t hal_ll_uart_read( handle_t *handle ) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + return ( hal_ll_hw_reg->rdr ); +} + +// ------------------------------------------------------------- DEFAULT EXCEPTION HANDLERS + +#if defined(USART_MODULE_1) +void MARK_AS_IRQ_HANDLER UART1_IRQHandler() MIKROC_IV(UART1_NVIC) { + #ifdef USART_MODULE_1 + if( hal_ll_uart_get_status_flags( HAL_LL_USART1_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART1_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART1_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_1) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_USART1_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART1_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART1_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_1) ], HAL_LL_UART_IRQ_TX ); + } + } + #endif +} +#endif + +#if defined(USART_MODULE_2) +void MARK_AS_IRQ_HANDLER UART2_IRQHandler() MIKROC_IV(UART2_NVIC) { + #ifdef USART_MODULE_2 + if( hal_ll_uart_get_status_flags( HAL_LL_USART2_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART2_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART2_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_2) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_USART2_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART2_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART2_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_2) ], HAL_LL_UART_IRQ_TX ); + } + } + #endif +} +#endif + +#if defined(LPUART_MODULE_1) +void MARK_AS_IRQ_HANDLER LPUART1_IRQHandler() MIKROC_IV(LPUART1_NVIC) { + #ifdef LPUART_MODULE_1 + if( hal_ll_uart_get_status_flags( HAL_LL_LPUART1_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_LPUART1_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_LPUART1_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(LPUART_MODULE_1) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_LPUART1_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_LPUART1_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_LPUART1_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(LPUART_MODULE_1) ], HAL_LL_UART_IRQ_TX ); + } + } + #endif +} +#endif + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static uint8_t hal_ll_uart_find_index( handle_t *handle ) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + if( hal_ll_uart_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + return hal_ll_uart_hw_specifics_map_local->module_index; + } else { + return NULL; + } +} + +static hal_ll_pin_name_t hal_ll_uart_check_pins( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_uart_pin_id *index_list, hal_ll_uart_handle_register_t *handle_map ) { + static const uint16_t tx_map_size = ( sizeof( hal_ll_uart_tx_map ) / sizeof( hal_ll_uart_pin_map_t ) ); + static const uint16_t rx_map_size = ( sizeof( hal_ll_uart_rx_map ) / sizeof( hal_ll_uart_pin_map_t ) ); + uint8_t hal_ll_module_id = 0; + uint8_t index_counter = 0; + uint16_t tx_index; + uint16_t rx_index; + + if ( (HAL_LL_PIN_NC == tx_pin) || (HAL_LL_PIN_NC == rx_pin) ) { + return HAL_LL_PIN_NC; + } + + for ( tx_index = 0; tx_index < tx_map_size; tx_index++ ) + { + if ( hal_ll_uart_tx_map[ tx_index ].pin == tx_pin ) + { + for ( rx_index = 0; rx_index < rx_map_size; rx_index++ ) + { + if ( hal_ll_uart_rx_map[ rx_index ].pin == rx_pin ) + { + if ( hal_ll_uart_tx_map[ tx_index ].base == hal_ll_uart_rx_map[ rx_index ].base ) { + // Get module number + hal_ll_module_id = hal_ll_uart_tx_map[ tx_index ].module_index; + + // Map pin names + index_list[hal_ll_module_id].pin_tx = tx_index; + index_list[hal_ll_module_id].pin_rx = rx_index; + + // Check if module is taken + if ( NULL == handle_map[ hal_ll_module_id ].hal_drv_uart_handle ) { + return hal_ll_module_id; + } else if ( UART_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static hal_ll_uart_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof(hal_ll_uart_handle_register_t)); + static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof(hal_ll_uart_handle_register_t)); + + while( hal_ll_module_count-- ) { + if (hal_ll_uart_get_base_from_hal_handle == hal_ll_uart_hw_specifics_map[hal_ll_module_count].base) { + return &hal_ll_uart_hw_specifics_map[hal_ll_module_count]; + } + } + + return &hal_ll_uart_hw_specifics_map[hal_ll_module_error]; +} + +static void hal_ll_uart_set_clock( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ) { + switch ( map->module_index ) + { + #ifdef UART_MODULE_1 + case ( hal_ll_uart_module_num(UART_MODULE_1) ): + (hal_ll_state == true)?(set_reg_bit( _RCC_APBENR2, HAL_LL_USART1EN )):(clear_reg_bit( _RCC_APBENR2, HAL_LL_USART1EN )); + break; + #endif + + #ifdef UART_MODULE_2 + case ( hal_ll_uart_module_num(UART_MODULE_2) ): + (hal_ll_state == true)?(set_reg_bit( _RCC_APBENR1, HAL_LL_USART2EN )):(clear_reg_bit( _RCC_APBENR1, HAL_LL_USART2EN )); + break; + #endif + + + default: + break; + } +} + +static void hal_ll_uart_map_pins( uint8_t module_index, hal_ll_uart_pin_id *index_list ) { + // Map new pins + hal_ll_uart_hw_specifics_map[module_index].pins.tx_pin.pin_name = hal_ll_uart_tx_map[ index_list[module_index].pin_tx ].pin; + hal_ll_uart_hw_specifics_map[module_index].pins.rx_pin.pin_name = hal_ll_uart_rx_map[ index_list[module_index].pin_rx ].pin; + // TX and RX could have different alternate function settings, hence save both AF values + hal_ll_uart_hw_specifics_map[module_index].pins.tx_pin.pin_af = hal_ll_uart_tx_map[ index_list[module_index].pin_tx ].af; + hal_ll_uart_hw_specifics_map[module_index].pins.rx_pin.pin_af = hal_ll_uart_rx_map[ index_list[module_index].pin_rx ].af; +} + +static void hal_ll_uart_alternate_functions_set_state( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ) { + module_struct module; + + if ( (map->pins.tx_pin.pin_name != HAL_LL_PIN_NC) && map->pins.rx_pin.pin_name != HAL_LL_PIN_NC ) { + module.pins[0] = VALUE( map->pins.tx_pin.pin_name, map->pins.tx_pin.pin_af ); + module.pins[1] = VALUE( map->pins.rx_pin.pin_name, map->pins.rx_pin.pin_af ); + module.pins[2] = GPIO_MODULE_STRUCT_END; + + module.configs[0] = HAL_LL_UART_AF_CONFIG; + module.configs[1] = HAL_LL_UART_AF_CONFIG; + module.configs[2] = GPIO_MODULE_STRUCT_END; + + /* STM32F1xx specific */ + module.gpio_remap = map->pins.tx_pin.pin_af; + + hal_ll_gpio_module_struct_init( &module, hal_ll_state ); + } +} + +static void hal_ll_uart_set_baud_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + uint32_t reg = 0; + uint32_t integer_divider = 0; + uint32_t fractional_divider = 0; + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); + uint32_t hal_ll_baud_value = hal_ll_uart_get_baud(hal_ll_uart_get_clock_speed(map->module_index),map->baud_rate.baud,4); + uint32_t hal_ll_baud_real_value = hal_ll_uart_get_real_baud(hal_ll_uart_get_clock_speed(map->module_index),hal_ll_baud_value,4); + + // if error greater than specified, cancel setting baud rate + if( (hal_ll_uart_get_baud_error(hal_ll_baud_real_value,map->baud_rate.baud)) > HAL_LL_UART_ACCEPTABLE_ERROR ) { + map->baud_rate.real_baud = hal_ll_uart_get_baud_error(hal_ll_baud_real_value,map->baud_rate.baud); + } else { + map->baud_rate.real_baud = hal_ll_baud_real_value; + + integer_divider = ( ( 25 * hal_ll_uart_get_clock_speed( map->module_index ) ) / ( 4 * ( map->baud_rate.baud ) ) ); + reg = ( integer_divider / 100 ) << 4; + + fractional_divider = integer_divider - ( 100 * ( reg >> 4 ) ); + reg |= ( ( ( ( fractional_divider * 16 ) + 50 ) / 100 ) ) & 0x0F; + + hal_ll_hw_reg->brr = ( uint16_t )reg; + } +} + +static uint32_t hal_ll_uart_get_clock_speed( hal_ll_pin_name_t module_index ) { + rcc_clocks_t rcc_clocks; + + RCC_GetClocksFrequency( &rcc_clocks ); + + switch ( module_index ) + { + #ifdef UART_MODULE_1 + case ( hal_ll_uart_module_num(UART_MODULE_1) ): + return rcc_clocks.pclk; + break; + #endif + + #ifdef UART_MODULE_2 + case ( hal_ll_uart_module_num(UART_MODULE_2) ): + return rcc_clocks.pclk; + break; + #endif + + + default: + break; + } + + return NULL; +} + +static void hal_ll_uart_set_stop_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); + + switch ( map->stop_bit ) + { + case HAL_LL_UART_STOP_BITS_HALF: + hal_ll_hw_reg->cr2 |= STOP_BITS_HALF; + break; + case HAL_LL_UART_STOP_BITS_ONE: + hal_ll_hw_reg->cr2 |= STOP_BITS_ONE; + break; + case HAL_LL_UART_STOP_BITS_ONE_AND_A_HALF: + hal_ll_hw_reg->cr2 |= STOP_BITS_ONE_AND_A_HALF; + break; + case HAL_LL_UART_STOP_BITS_TWO: + hal_ll_hw_reg->cr2 |= STOP_BITS_TWO; + break; + + default: + break; + } +} + +static void hal_ll_uart_set_data_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); + + switch ( map->data_bit ) + { + case HAL_LL_UART_DATA_BITS_7: + hal_ll_hw_reg->cr1 |= DATA_BIT_7; + break; + + case HAL_LL_UART_DATA_BITS_8: + hal_ll_hw_reg->cr1 |= DATA_BIT_8; + break; + + case HAL_LL_UART_DATA_BITS_9: + hal_ll_hw_reg->cr1 |= DATA_BIT_9; + break; + + + default: + break; + } +} + +static void hal_ll_uart_set_parity_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); + + switch ( map->parity ) + { + case HAL_LL_UART_PARITY_NONE: + hal_ll_hw_reg->cr1 |= PARITY_NO; + break; + case HAL_LL_UART_PARITY_EVEN: + hal_ll_hw_reg->cr1 |= PARITY_ENABLED | PARITY_EVEN; + break; + case HAL_LL_UART_PARITY_ODD: + hal_ll_hw_reg->cr1 |= PARITY_ENABLED | PARITY_ODD; + break; + + default: + break; + } +} + +static void hal_ll_uart_set_module( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ) { + switch ( pin_state ) + { + case HAL_LL_UART_DISABLE: + clear_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_UE ); + break; + + case HAL_LL_UART_ENABLE: + set_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_UE ); + break; + + default: + break; + } +} + +static void hal_ll_uart_set_transmitter( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ) { + switch ( pin_state ) + { + case HAL_LL_UART_DISABLE: + clear_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_TE ); + break; + + case HAL_LL_UART_ENABLE: + set_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_TE ); + break; + + default: + break; + } +} + +static void hal_ll_uart_set_receiver( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ) { + switch ( pin_state ) + { + case HAL_LL_UART_DISABLE: + clear_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_RE ); + break; + + case HAL_LL_UART_ENABLE: + set_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_RE ); + break; + + default: + break; + } +} + +static void hal_ll_uart_clear_regs( hal_ll_uart_base_handle_t *hal_ll_hw_reg ) { + hal_ll_hw_reg->cr1 &= HAL_LL_UART_IT_CR1_MASK; + hal_ll_hw_reg->cr2 &= HAL_LL_UART_IT_CR2_MASK; + hal_ll_hw_reg->cr3 &= HAL_LL_UART_IT_CR3_MASK; +} + +static void hal_ll_uart_hw_init( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_clear_regs( map->base ); + + hal_ll_uart_set_data_bits_bare_metal( map ); + + hal_ll_uart_set_parity_bare_metal( map ); + + hal_ll_uart_set_stop_bits_bare_metal( map ); + + hal_ll_uart_set_baud_bare_metal( map ); + + hal_ll_uart_set_transmitter( map->base, HAL_LL_UART_ENABLE ); + + hal_ll_uart_set_receiver( map->base, HAL_LL_UART_ENABLE ); + + hal_ll_uart_set_module( map->base, HAL_LL_UART_ENABLE ); +} + +static void hal_ll_uart_init( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_set_clock( map, true ); + + hal_ll_uart_alternate_functions_set_state( map, true ); + + hal_ll_uart_hw_init( map ); +} +// ------------------------------------------------------------------------- END + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_75/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_75/CMakeLists.cmake new file mode 100644 index 000000000..979f9febb --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_75/CMakeLists.cmake @@ -0,0 +1,9 @@ +if(${MCU_NAME} MATCHES "^STM32G061C6$|^STM32G061F6$|^STM32G061G6$|^STM32G061K6$|^STM32G061C8$|^STM32G061F8$|^STM32G061G8$|^STM32G061K8$") + set(uart_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_uart.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_75") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_75") + list(APPEND hal_ll_def_list "STM32G0xx") + list(APPEND hal_ll_def_list "STM32G06xx") + list(APPEND hal_ll_def_list "STM32G061xx") + set(uart_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/uart/hal_ll_uart_pin_map/implementations/doc_ds_75") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_75/hal_ll_uart.c b/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_75/hal_ll_uart.c new file mode 100644 index 000000000..132180af8 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_75/hal_ll_uart.c @@ -0,0 +1,1108 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_uart.c + * @brief UART HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_rcc.h" +#include "hal_ll_uart.h" +#include "hal_ll_gpio.h" +#include "hal_ll_core.h" +#include "hal_ll_core_defines.h" +#include "hal_ll_uart_pin_map.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_uart_handle_register_t hal_ll_module_state[UART_MODULE_COUNT] = { (handle_t *)NULL, (handle_t *)NULL, false }; + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_uart_get_module_state_address ((hal_ll_uart_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_uart_get_handle (hal_ll_uart_handle_register_t *)hal_ll_uart_get_module_state_address->hal_ll_uart_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_uart_get_base_struct(_handle) ((hal_ll_uart_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_uart_get_base_from_hal_handle ((hal_ll_uart_hw_specifics_map_t *)((hal_ll_uart_handle_register_t *)\ + (((hal_ll_uart_handle_register_t *)(handle))->hal_ll_uart_handle))->hal_ll_uart_handle)->base + +/*!< @brief Macros used for calculating actual baud rate value and error value */ +#define HAL_LL_UART_ACCEPTABLE_ERROR (float)1.0 +#define hal_ll_uart_get_baud(_clock,_baud,_div) (((_clock/(float)_baud)/_div)-1) +#define hal_ll_uart_get_real_baud(_clock,_baud,_div) (_clock/(_div*(_baud+1))) +#define hal_ll_uart_get_baud_error(_baud_real,_baud) (((float)(abs(_baud_real-_baud))/_baud)*100) + +/*!< @brief Macros defining bit location */ +#define HAL_LL_USART1EN 14 + +#define HAL_LL_USART2EN 17 + + +#define HAL_LL_UART_CR1_UE 0 +#define HAL_LL_UART_CR1_TE 3 +#define HAL_LL_UART_CR1_RE 2 + +#define HAL_LL_UART_SR_RXNE 5 +#define HAL_LL_UART_SR_TXE 7 + +/*!< @brief Macros defining register bit values */ +#define STOP_BITS_HALF 0x1000U +#define STOP_BITS_ONE 0x00U +#define STOP_BITS_ONE_AND_A_HALF 0x3000U +#define STOP_BITS_TWO 0x2000U + +#define DATA_BIT_7 0x10000000U +#define DATA_BIT_8 0x00U +#define DATA_BIT_9 0x1000U + +#define PARITY_NO 0x00U +#define PARITY_ENABLED 0x400U + +#define PARITY_EVEN 0x00U +#define PARITY_ODD 0x200U + +/*!< @brief Macro used for setting pin alternate functions */ +#define HAL_LL_UART_AF_CONFIG (GPIO_CFG_MODE_ALT_FUNCTION | GPIO_CFG_SPEED_HIGH | GPIO_CFG_OTYPE_PP) + +/*!< @brief Macros used for interrupts */ +#define HAL_LL_UART_IT_MASK 0xFFFFUL +#define HAL_LL_UART_IT_CLEAR_MASK 0x123bffU +#define HAL_LL_UART_IT_CR1_MASK 0x1f0U +#define HAL_LL_UART_IT_CR2_MASK 0x40U +#define HAL_LL_UART_IT_CR3_MASK 0x401U + +#define HAL_LL_UART_CR1_REG_INDEX 1 +#define HAL_LL_UART_CR2_REG_INDEX 2 +#define HAL_LL_UART_CR3_REG_INDEX 3 + +#define HAL_LL_UART_IT_PE 0x100U +#define HAL_LL_UART_IT_TXE (0x10000000 | 0x80U) +#define HAL_LL_UART_IT_TC 0x40U +#define HAL_LL_UART_IT_RXNE (0x10000000 | 0x20U) +#define HAL_LL_UART_IT_IDLE 0x10U +#define HAL_LL_UART_IT_LBD 0x40U +#define HAL_LL_UART_IT_CTS 0x400U +#define HAL_LL_UART_IT_ERR 0x01U + +#define HAL_LL_UART_STATUS_RXNE_FLAG 0x20U +#define HAL_LL_UART_STATUS_TXE_FLAG 0x80U + +/*!< @brief Macro used for status registed flag check + * Used in interrupt handlers. + */ +#define hal_ll_uart_get_status_flags(_handle,_flag) (((hal_ll_uart_base_handle_t *)_handle)->isr & _flag) + +/*!< @brief Macro used for status register flag clearing + * Used in interrupt handlers. + */ +#define hal_ll_uart_clear_status_flag(_handle,_flag) (set_reg_bit( &(((hal_ll_uart_base_handle_t *)_handle)->icr), ( _flag & HAL_LL_UART_IT_CLEAR_MASK ) ) ) + +/*!< @brief Macro used for module interrupt enabling. + * Used in interrupt handlers. + */ +#define __HAL_LL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__ >> 28UL) == HAL_LL_UART_CR1_REG_INDEX)? (__HANDLE__->cr1 |= (__INTERRUPT__ & HAL_LL_UART_IT_MASK)): \ + ((__INTERRUPT__ >> 28UL) == HAL_LL_UART_CR2_REG_INDEX)? (__HANDLE__->cr2 |= (__INTERRUPT__ & HAL_LL_UART_IT_MASK)): \ + (__HANDLE__->cr3 |= (__INTERRUPT__ & HAL_LL_UART_IT_MASK))) + +/*!< @brief Macro used for module interrupt disabling. + * Used in interrupt handlers. + */ +#define __HAL_LL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__ >> 28UL) == HAL_LL_UART_CR1_REG_INDEX)? (__HANDLE__->cr1 &= ~(__INTERRUPT__ & HAL_LL_UART_IT_MASK)): \ + ((__INTERRUPT__ >> 28UL) == HAL_LL_UART_CR2_REG_INDEX)? (__HANDLE__->cr2 &= ~(__INTERRUPT__ & HAL_LL_UART_IT_MASK)): \ + (__HANDLE__->cr3 &= ~ (__INTERRUPT__ & HAL_LL_UART_IT_MASK))) + +/*!< @brief Macro used for module interrupt source check. + * Used in interrupt handlers. + */ +#define __HAL_LL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__ >> 28UL) == 1UL)? ((hal_ll_uart_base_handle_t *)__HANDLE__)->cr1:((((uint32_t)__INTERRUPT__ >> 28UL) == 2UL)? \ + ((hal_ll_uart_base_handle_t *)__HANDLE__)->cr2 : ((hal_ll_uart_base_handle_t *)__HANDLE__)->cr3)) & ((uint32_t)__INTERRUPT__ & HAL_LL_UART_IT_MASK)) + +/*!< @brief UART HW register structure */ +typedef struct +{ + hal_ll_base_addr_t cr1; + hal_ll_base_addr_t cr2; + hal_ll_base_addr_t cr3; + hal_ll_base_addr_t brr; + hal_ll_base_addr_t gtpr; + hal_ll_base_addr_t rtor; + hal_ll_base_addr_t rqr; + hal_ll_base_addr_t isr; + hal_ll_base_addr_t icr; + hal_ll_base_addr_t rdr; + hal_ll_base_addr_t tdr; + hal_ll_base_addr_t presc; + +} hal_ll_uart_base_handle_t; + +/*!< @brief UART baud rate structure */ +typedef struct +{ + uint32_t baud; + uint32_t real_baud; +} hal_ll_uart_baud_t; + +/*!< @brief UART hw specific structure */ +typedef struct +{ + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + hal_ll_uart_pins_t pins; + hal_ll_uart_baud_t baud_rate; + hal_ll_uart_parity_t parity; + hal_ll_uart_stop_bits_t stop_bit; + hal_ll_uart_data_bits_t data_bit; +} hal_ll_uart_hw_specifics_map_t; + +/*!< @brief UART hw specific module values */ +typedef struct +{ + uint16_t pin_tx; + uint16_t pin_rx; +} hal_ll_uart_pin_id; + +/*!< @brief UART hw specific error values */ +typedef enum +{ + HAL_LL_UART_SUCCESS = 0, + HAL_LL_UART_WRONG_PINS, + HAL_LL_UART_MODULE_ERROR, + + HAL_LL_UART_ERROR = (-1) +} hal_ll_uart_err_t; + +/*!< @brief UART module state selection */ +typedef enum +{ + HAL_LL_UART_DISABLE = 0, + HAL_LL_UART_ENABLE +} hal_ll_uart_state_t; + +// ------------------------------------------------------------------ VARIABLES +/*!< @brief UART hardware specific info */ +static hal_ll_uart_hw_specifics_map_t hal_ll_uart_hw_specifics_map[] = +{ + #ifdef UART_MODULE_1 + {HAL_LL_UART1_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_1), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + + #ifdef UART_MODULE_2 + {HAL_LL_UART2_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_2), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + + + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {0, 0}, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR} +}; + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_uart_handle_register_t *low_level_handle; +static volatile hal_ll_uart_hw_specifics_map_t *hal_ll_uart_hw_specifics_map_local; + +/*!< @brief Global interrupt handlers used in functions */ +static hal_ll_uart_isr_t irq_handler; +static handle_t objects[UART_MODULE_COUNT]; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Check if pins are adequate. + * + * Checks tx and rx pins the user has passed with pre-defined + * pins in tx and rx maps. Take into consideration that module + * index numbers have to be the same for both pins. + * + * @param[in] tx_pin - TX pre-defined pin name. + * @param[in] rx_pin - RX pre-defined pin name. + * @param[in] *index_list - Array containing map index numbers. + * @return hal_ll_pin_name_t Module index based on pins. + * + * Returns pre-defined module index from pin maps, if pins + * are adequate. + */ +static hal_ll_pin_name_t hal_ll_uart_check_pins( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_uart_pin_id *index_list, hal_ll_uart_handle_register_t *handle_map ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * TX and RX pins. + * + * @param[in] module_index UART HW module index -- 0,1,2... + * @param[in] *index_list Array with TX and RX map index values + * and module number + * + * @return None + */ +static void hal_ll_uart_map_pins( uint8_t module_index, hal_ll_uart_pin_id *index_list ); + +/** + * @brief Sets UART pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if UART is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_state - Init/De-init + * + * @return void None. + */ +static void hal_ll_uart_alternate_functions_set_state( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_uart_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_uart_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_uart_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Enable clock for UART module on hardware level. + * + * Initializes UART module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_stat - True(enable clock)/False(disable clock). + * + * @return void None. + */ +static void hal_ll_uart_set_clock( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Finds UART module index. + * + * Finds UART index(module number) based on + * handle value. + * + * @param[in] handle - Object specific context handler. + * + * @return uint8_t Module number. + * Returns values from 0 to 9. + */ +static uint8_t hal_ll_uart_find_index( handle_t *handle ); + +/** + * @brief Get UART module clock speed. + * + * Returns adequate clock speed based on + * UART module base address. + * + * @param[in] module_index - UART module index number. + * + * @return uint8_t Module number. + * Returns clock value. + */ +static uint32_t hal_ll_uart_get_clock_speed( hal_ll_pin_name_t module_index ); + +/** + * @brief Clears UART registers. + * + * Clears UART module configuration + * registers, effectively disabling the module itself. + * Take into consideration that any IRQ bits + * are not cleared. + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * + * @return void None. + */ +static void hal_ll_uart_clear_regs( hal_ll_uart_base_handle_t *hal_ll_hw_reg ); + +/** + * @brief Sets desired baud rate on hardware level. + * + * Initializes module with specified baud rate value. + * Take into consideration that if the difference + * between desired baud rate and actual baud + * rate the hw was initialized to is greater than + * 1%, baud rate shall not be set. + * If this occurs, return value shall be + * the error percentage. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_set_baud_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Sets desired stop bits. + * + * Initializes module on hardware level + * with specified stop bit value. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_set_stop_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Sets desired data bits. + * + * Initializes module on hardware level + * with specified data bit bit value. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_set_data_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Sets desired parity. + * + * Initializes module on hardware level + * with specified parity value. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_set_parity_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Sets module clock value. + * + * Enables/disables specific UART module + * clock gate. + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * @param[in] pin_state - true(enable clock) / false(disable clock) + * + * @return void None. + */ +static void hal_ll_uart_set_module( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ); + +/** + * @brief Sets module TX line state. + * + * Enables/disables specific UART module + * TX pin state + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * @param[in] pin_state - true(enable transmitter pin) / false(disable transmitter pin) + * + * @return void None. + */ +static void hal_ll_uart_set_transmitter( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ); + +/** + * @brief Sets module RX line state. + * + * Enables/disables specific UART module + * RX pin state + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * @param[in] pin_state - true(enable receive pin) / false(disable receive pin) + * + * @return void None. + */ +static void hal_ll_uart_set_receiver( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ); + +/** + * @brief Initialize UART module. + * + * Enables UART module clogk gate first. + * Sets pin alternate function state. + * Initializes specific UART module. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_init( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Initialize UART module on the hardware level. + * + * Performs UART module initialization on + * the hardware level. + * + * Procedure: + * 1. Clears control registers + * 2. Sets data bit value + * 3. Sets parity value + * 4. Sets stop bit value + * 5. Sets baud rate value + * 6. Enables transmit pin + * 7. Enables receive pin + * 8. Enables clock gate for specific module + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_hw_init( hal_ll_uart_hw_specifics_map_t *map ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_uart_register_handle( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_uart_handle_register_t *handle_map, uint8_t *hal_module_id ) { + + hal_ll_uart_pin_id index_list[UART_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + uint16_t pin_check_result; + + // Check if pins are valid + if ( (pin_check_result = hal_ll_uart_check_pins( tx_pin, rx_pin, &index_list, handle_map )) == HAL_LL_PIN_NC ) { + return HAL_LL_UART_WRONG_PINS; + }; + + if ( (hal_ll_uart_hw_specifics_map[pin_check_result].pins.tx_pin.pin_name != tx_pin) || + (hal_ll_uart_hw_specifics_map[pin_check_result].pins.rx_pin.pin_name != rx_pin) ) + { + hal_ll_uart_alternate_functions_set_state( &hal_ll_uart_hw_specifics_map[ pin_check_result ], false ); + + hal_ll_uart_map_pins( pin_check_result, &index_list ); + + hal_ll_uart_alternate_functions_set_state( &hal_ll_uart_hw_specifics_map[ pin_check_result ], true ); + + handle_map[pin_check_result].init_ll_state = false; + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[pin_check_result].hal_ll_uart_handle = (handle_t *)&hal_ll_uart_hw_specifics_map[pin_check_result].base; + + handle_map[pin_check_result].hal_ll_uart_handle = (handle_t *)&hal_ll_module_state[pin_check_result].hal_ll_uart_handle; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_uart( handle_t *handle ) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + hal_ll_uart_pin_id index_list[UART_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + uint16_t pin_check_result; + + if ( (pin_check_result = hal_ll_uart_check_pins( hal_ll_uart_hw_specifics_map_local->pins.tx_pin.pin_name, + hal_ll_uart_hw_specifics_map_local->pins.rx_pin.pin_name, &index_list, (void *)0 ) ) == HAL_LL_PIN_NC ) { + return HAL_LL_UART_WRONG_PINS; + }; + + hal_ll_uart_init( hal_ll_uart_hw_specifics_map_local ); + + hal_ll_module_state[pin_check_result].hal_ll_uart_handle = (handle_t *)&hal_ll_uart_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_uart_set_baud( handle_t *handle, uint32_t baud ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->baud_rate.baud = baud; + + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return hal_ll_uart_hw_specifics_map_local->baud_rate.real_baud; +} + +hal_ll_err_t hal_ll_uart_set_parity( handle_t *handle, hal_ll_uart_parity_t parity ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->parity = parity; + + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_uart_set_stop_bits( handle_t *handle, hal_ll_uart_stop_bits_t stop_bit ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->stop_bit = stop_bit; + + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_uart_set_data_bits( handle_t *handle, hal_ll_uart_data_bits_t data_bit ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + // Chips using implementation 1 do not support 7 bit data + if( data_bit == HAL_LL_UART_DATA_BITS_7 ) { + return HAL_LL_UART_MODULE_ERROR; + } + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->data_bit = data_bit; + + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +void hal_ll_uart_close( handle_t *handle ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + if( low_level_handle->hal_ll_uart_handle != NULL ) { + hal_ll_uart_alternate_functions_set_state( hal_ll_uart_hw_specifics_map_local, false ); + + hal_ll_uart_irq_disable(handle, HAL_LL_UART_IRQ_RX); + hal_ll_uart_irq_disable(handle, HAL_LL_UART_IRQ_TX); + + hal_ll_uart_clear_regs(hal_ll_uart_hw_specifics_map_local->base); + hal_ll_uart_set_clock(hal_ll_uart_hw_specifics_map_local, false); + + hal_ll_uart_hw_specifics_map_local->pins.tx_pin.pin_name = HAL_LL_PIN_NC; + hal_ll_uart_hw_specifics_map_local->pins.tx_pin.pin_af = 0; + hal_ll_uart_hw_specifics_map_local->pins.rx_pin.pin_name = HAL_LL_PIN_NC; + hal_ll_uart_hw_specifics_map_local->pins.rx_pin.pin_af = 0; + + hal_ll_uart_hw_specifics_map_local->baud_rate.baud = 115200UL; + hal_ll_uart_hw_specifics_map_local->baud_rate.real_baud = 0; + + irq_handler = NULL; + objects[ hal_ll_uart_find_index( handle ) ] = NULL; + + low_level_handle->hal_ll_uart_handle = NULL; + low_level_handle->hal_drv_uart_handle = NULL; + + low_level_handle->init_ll_state = false; + } +} + +void hal_ll_uart_register_irq_handler( handle_t *handle, hal_ll_uart_isr_t handler, handle_t obj ) +{ + irq_handler = handler; + objects[ hal_ll_uart_find_index( handle ) ] = obj; +} + +void hal_ll_uart_irq_enable( handle_t *handle, hal_ll_uart_irq_t irq ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + switch ( irq ) { + case HAL_LL_UART_IRQ_RX: + __HAL_LL_UART_ENABLE_IT( hal_ll_hw_reg, HAL_LL_UART_IT_RXNE ); + break; + + case HAL_LL_UART_IRQ_TX: + __HAL_LL_UART_ENABLE_IT( hal_ll_hw_reg, HAL_LL_UART_IT_TXE ); + break; + + default: + break; + } + + switch ( hal_ll_uart_hw_specifics_map_local->module_index ) + { + #if defined(UART_MODULE_1) && defined(UART1_NVIC) + case hal_ll_uart_module_num(UART_MODULE_1): + hal_ll_core_enable_irq( UART1_NVIC ); + break; + #endif + + #if defined(UART_MODULE_2) && defined(UART2_NVIC) + case hal_ll_uart_module_num(UART_MODULE_2): + hal_ll_core_enable_irq( UART2_NVIC ); + break; + #endif + + + default: + break; + } +} + +void hal_ll_uart_irq_disable( handle_t *handle, hal_ll_uart_irq_t irq ) +{ + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + switch ( irq ) { + case HAL_LL_UART_IRQ_RX: + __HAL_LL_UART_DISABLE_IT( hal_ll_hw_reg, HAL_LL_UART_IT_RXNE ); + break; + + case HAL_LL_UART_IRQ_TX: + __HAL_LL_UART_DISABLE_IT( hal_ll_hw_reg, HAL_LL_UART_IT_TXE ); + break; + + default: + break; + } + + // Check if module interrupt flags are set or not + if ( ( !check_reg_bit( &hal_ll_hw_reg->cr1, HAL_LL_UART_SR_RXNE ) ) && + ( !check_reg_bit( &hal_ll_hw_reg->cr1, HAL_LL_UART_SR_TXE ) ) ) + { + switch ( hal_ll_uart_hw_specifics_map_local->module_index ) + { + #if defined(UART_MODULE_1) && defined(UART1_NVIC) + case hal_ll_uart_module_num(UART_MODULE_1): + hal_ll_core_disable_irq( UART1_NVIC ); + break; + #endif + + #if defined(UART_MODULE_2) && defined(UART2_NVIC) + case hal_ll_uart_module_num(UART_MODULE_2): + hal_ll_core_disable_irq( UART2_NVIC ); + break; + #endif + + + default: + break; + } + } +} + +void hal_ll_uart_write( handle_t *handle, uint8_t wr_data) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + hal_ll_hw_reg->tdr = wr_data; +} + +uint8_t hal_ll_uart_read( handle_t *handle ) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + return ( hal_ll_hw_reg->rdr ); +} + +// ------------------------------------------------------------- DEFAULT EXCEPTION HANDLERS + +#if defined(USART_MODULE_1) +void MARK_AS_IRQ_HANDLER UART1_IRQHandler() MIKROC_IV(UART1_NVIC) { + #ifdef USART_MODULE_1 + if( hal_ll_uart_get_status_flags( HAL_LL_USART1_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART1_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART1_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_1) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_USART1_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART1_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART1_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_1) ], HAL_LL_UART_IRQ_TX ); + } + } + #endif +} +#endif + +#if defined(USART_MODULE_2) +void MARK_AS_IRQ_HANDLER UART2_IRQHandler() MIKROC_IV(UART2_NVIC) { + #ifdef USART_MODULE_2 + if( hal_ll_uart_get_status_flags( HAL_LL_USART2_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART2_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART2_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_2) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_USART2_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART2_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART2_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_2) ], HAL_LL_UART_IRQ_TX ); + } + } + #endif +} +#endif + +#if defined(LPUART_MODULE_1) +void MARK_AS_IRQ_HANDLER LPUART1_IRQHandler() MIKROC_IV(LPUART1_NVIC) { + #ifdef LPUART_MODULE_1 + if( hal_ll_uart_get_status_flags( HAL_LL_LPUART1_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_LPUART1_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_LPUART1_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(LPUART_MODULE_1) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_LPUART1_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_LPUART1_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_LPUART1_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(LPUART_MODULE_1) ], HAL_LL_UART_IRQ_TX ); + } + } + #endif +} +#endif + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static uint8_t hal_ll_uart_find_index( handle_t *handle ) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + if( hal_ll_uart_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + return hal_ll_uart_hw_specifics_map_local->module_index; + } else { + return NULL; + } +} + +static hal_ll_pin_name_t hal_ll_uart_check_pins( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_uart_pin_id *index_list, hal_ll_uart_handle_register_t *handle_map ) { + static const uint16_t tx_map_size = ( sizeof( hal_ll_uart_tx_map ) / sizeof( hal_ll_uart_pin_map_t ) ); + static const uint16_t rx_map_size = ( sizeof( hal_ll_uart_rx_map ) / sizeof( hal_ll_uart_pin_map_t ) ); + uint8_t hal_ll_module_id = 0; + uint8_t index_counter = 0; + uint16_t tx_index; + uint16_t rx_index; + + if ( (HAL_LL_PIN_NC == tx_pin) || (HAL_LL_PIN_NC == rx_pin) ) { + return HAL_LL_PIN_NC; + } + + for ( tx_index = 0; tx_index < tx_map_size; tx_index++ ) + { + if ( hal_ll_uart_tx_map[ tx_index ].pin == tx_pin ) + { + for ( rx_index = 0; rx_index < rx_map_size; rx_index++ ) + { + if ( hal_ll_uart_rx_map[ rx_index ].pin == rx_pin ) + { + if ( hal_ll_uart_tx_map[ tx_index ].base == hal_ll_uart_rx_map[ rx_index ].base ) { + // Get module number + hal_ll_module_id = hal_ll_uart_tx_map[ tx_index ].module_index; + + // Map pin names + index_list[hal_ll_module_id].pin_tx = tx_index; + index_list[hal_ll_module_id].pin_rx = rx_index; + + // Check if module is taken + if ( NULL == handle_map[ hal_ll_module_id ].hal_drv_uart_handle ) { + return hal_ll_module_id; + } else if ( UART_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static hal_ll_uart_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof(hal_ll_uart_handle_register_t)); + static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof(hal_ll_uart_handle_register_t)); + + while( hal_ll_module_count-- ) { + if (hal_ll_uart_get_base_from_hal_handle == hal_ll_uart_hw_specifics_map[hal_ll_module_count].base) { + return &hal_ll_uart_hw_specifics_map[hal_ll_module_count]; + } + } + + return &hal_ll_uart_hw_specifics_map[hal_ll_module_error]; +} + +static void hal_ll_uart_set_clock( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ) { + switch ( map->module_index ) + { + #ifdef UART_MODULE_1 + case ( hal_ll_uart_module_num(UART_MODULE_1) ): + (hal_ll_state == true)?(set_reg_bit( _RCC_APBENR2, HAL_LL_USART1EN )):(clear_reg_bit( _RCC_APBENR2, HAL_LL_USART1EN )); + break; + #endif + + #ifdef UART_MODULE_2 + case ( hal_ll_uart_module_num(UART_MODULE_2) ): + (hal_ll_state == true)?(set_reg_bit( _RCC_APBENR1, HAL_LL_USART2EN )):(clear_reg_bit( _RCC_APBENR1, HAL_LL_USART2EN )); + break; + #endif + + + default: + break; + } +} + +static void hal_ll_uart_map_pins( uint8_t module_index, hal_ll_uart_pin_id *index_list ) { + // Map new pins + hal_ll_uart_hw_specifics_map[module_index].pins.tx_pin.pin_name = hal_ll_uart_tx_map[ index_list[module_index].pin_tx ].pin; + hal_ll_uart_hw_specifics_map[module_index].pins.rx_pin.pin_name = hal_ll_uart_rx_map[ index_list[module_index].pin_rx ].pin; + // TX and RX could have different alternate function settings, hence save both AF values + hal_ll_uart_hw_specifics_map[module_index].pins.tx_pin.pin_af = hal_ll_uart_tx_map[ index_list[module_index].pin_tx ].af; + hal_ll_uart_hw_specifics_map[module_index].pins.rx_pin.pin_af = hal_ll_uart_rx_map[ index_list[module_index].pin_rx ].af; +} + +static void hal_ll_uart_alternate_functions_set_state( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ) { + module_struct module; + + if ( (map->pins.tx_pin.pin_name != HAL_LL_PIN_NC) && map->pins.rx_pin.pin_name != HAL_LL_PIN_NC ) { + module.pins[0] = VALUE( map->pins.tx_pin.pin_name, map->pins.tx_pin.pin_af ); + module.pins[1] = VALUE( map->pins.rx_pin.pin_name, map->pins.rx_pin.pin_af ); + module.pins[2] = GPIO_MODULE_STRUCT_END; + + module.configs[0] = HAL_LL_UART_AF_CONFIG; + module.configs[1] = HAL_LL_UART_AF_CONFIG; + module.configs[2] = GPIO_MODULE_STRUCT_END; + + /* STM32F1xx specific */ + module.gpio_remap = map->pins.tx_pin.pin_af; + + hal_ll_gpio_module_struct_init( &module, hal_ll_state ); + } +} + +static void hal_ll_uart_set_baud_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + uint32_t reg = 0; + uint32_t integer_divider = 0; + uint32_t fractional_divider = 0; + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); + uint32_t hal_ll_baud_value = hal_ll_uart_get_baud(hal_ll_uart_get_clock_speed(map->module_index),map->baud_rate.baud,4); + uint32_t hal_ll_baud_real_value = hal_ll_uart_get_real_baud(hal_ll_uart_get_clock_speed(map->module_index),hal_ll_baud_value,4); + + // if error greater than specified, cancel setting baud rate + if( (hal_ll_uart_get_baud_error(hal_ll_baud_real_value,map->baud_rate.baud)) > HAL_LL_UART_ACCEPTABLE_ERROR ) { + map->baud_rate.real_baud = hal_ll_uart_get_baud_error(hal_ll_baud_real_value,map->baud_rate.baud); + } else { + map->baud_rate.real_baud = hal_ll_baud_real_value; + + integer_divider = ( ( 25 * hal_ll_uart_get_clock_speed( map->module_index ) ) / ( 4 * ( map->baud_rate.baud ) ) ); + reg = ( integer_divider / 100 ) << 4; + + fractional_divider = integer_divider - ( 100 * ( reg >> 4 ) ); + reg |= ( ( ( ( fractional_divider * 16 ) + 50 ) / 100 ) ) & 0x0F; + + hal_ll_hw_reg->brr = ( uint16_t )reg; + } +} + +static uint32_t hal_ll_uart_get_clock_speed( hal_ll_pin_name_t module_index ) { + rcc_clocks_t rcc_clocks; + + RCC_GetClocksFrequency( &rcc_clocks ); + + switch ( module_index ) + { + #ifdef UART_MODULE_1 + case ( hal_ll_uart_module_num(UART_MODULE_1) ): + return rcc_clocks.pclk; + break; + #endif + + #ifdef UART_MODULE_2 + case ( hal_ll_uart_module_num(UART_MODULE_2) ): + return rcc_clocks.pclk; + break; + #endif + + + default: + break; + } + + return NULL; +} + +static void hal_ll_uart_set_stop_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); + + switch ( map->stop_bit ) + { + case HAL_LL_UART_STOP_BITS_HALF: + hal_ll_hw_reg->cr2 |= STOP_BITS_HALF; + break; + case HAL_LL_UART_STOP_BITS_ONE: + hal_ll_hw_reg->cr2 |= STOP_BITS_ONE; + break; + case HAL_LL_UART_STOP_BITS_ONE_AND_A_HALF: + hal_ll_hw_reg->cr2 |= STOP_BITS_ONE_AND_A_HALF; + break; + case HAL_LL_UART_STOP_BITS_TWO: + hal_ll_hw_reg->cr2 |= STOP_BITS_TWO; + break; + + default: + break; + } +} + +static void hal_ll_uart_set_data_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); + + switch ( map->data_bit ) + { + case HAL_LL_UART_DATA_BITS_7: + hal_ll_hw_reg->cr1 |= DATA_BIT_7; + break; + + case HAL_LL_UART_DATA_BITS_8: + hal_ll_hw_reg->cr1 |= DATA_BIT_8; + break; + + case HAL_LL_UART_DATA_BITS_9: + hal_ll_hw_reg->cr1 |= DATA_BIT_9; + break; + + + default: + break; + } +} + +static void hal_ll_uart_set_parity_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); + + switch ( map->parity ) + { + case HAL_LL_UART_PARITY_NONE: + hal_ll_hw_reg->cr1 |= PARITY_NO; + break; + case HAL_LL_UART_PARITY_EVEN: + hal_ll_hw_reg->cr1 |= PARITY_ENABLED | PARITY_EVEN; + break; + case HAL_LL_UART_PARITY_ODD: + hal_ll_hw_reg->cr1 |= PARITY_ENABLED | PARITY_ODD; + break; + + default: + break; + } +} + +static void hal_ll_uart_set_module( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ) { + switch ( pin_state ) + { + case HAL_LL_UART_DISABLE: + clear_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_UE ); + break; + + case HAL_LL_UART_ENABLE: + set_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_UE ); + break; + + default: + break; + } +} + +static void hal_ll_uart_set_transmitter( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ) { + switch ( pin_state ) + { + case HAL_LL_UART_DISABLE: + clear_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_TE ); + break; + + case HAL_LL_UART_ENABLE: + set_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_TE ); + break; + + default: + break; + } +} + +static void hal_ll_uart_set_receiver( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ) { + switch ( pin_state ) + { + case HAL_LL_UART_DISABLE: + clear_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_RE ); + break; + + case HAL_LL_UART_ENABLE: + set_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_RE ); + break; + + default: + break; + } +} + +static void hal_ll_uart_clear_regs( hal_ll_uart_base_handle_t *hal_ll_hw_reg ) { + hal_ll_hw_reg->cr1 &= HAL_LL_UART_IT_CR1_MASK; + hal_ll_hw_reg->cr2 &= HAL_LL_UART_IT_CR2_MASK; + hal_ll_hw_reg->cr3 &= HAL_LL_UART_IT_CR3_MASK; +} + +static void hal_ll_uart_hw_init( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_clear_regs( map->base ); + + hal_ll_uart_set_data_bits_bare_metal( map ); + + hal_ll_uart_set_parity_bare_metal( map ); + + hal_ll_uart_set_stop_bits_bare_metal( map ); + + hal_ll_uart_set_baud_bare_metal( map ); + + hal_ll_uart_set_transmitter( map->base, HAL_LL_UART_ENABLE ); + + hal_ll_uart_set_receiver( map->base, HAL_LL_UART_ENABLE ); + + hal_ll_uart_set_module( map->base, HAL_LL_UART_ENABLE ); +} + +static void hal_ll_uart_init( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_set_clock( map, true ); + + hal_ll_uart_alternate_functions_set_state( map, true ); + + hal_ll_uart_hw_init( map ); +} +// ------------------------------------------------------------------------- END + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_80/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_80/CMakeLists.cmake new file mode 100644 index 000000000..3a9d86f65 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_80/CMakeLists.cmake @@ -0,0 +1,9 @@ +if(${MCU_NAME} MATCHES "^STM32G0B1CB$|^STM32G0B1KB$|^STM32G0B1MB$|^STM32G0B1RB$|^STM32G0B1VB$|^STM32G0B1CC$|^STM32G0B1KC$|^STM32G0B1MC$|^STM32G0B1RC$|^STM32G0B1VC$|^STM32G0B1CE$|^STM32G0B1KE$|^STM32G0B1ME$|^STM32G0B1NE$|^STM32G0B1RE$|^STM32G0B1VE$") + set(uart_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_uart.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_80") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_80") + list(APPEND hal_ll_def_list "STM32G0xx") + list(APPEND hal_ll_def_list "STM32G0Bxx") + list(APPEND hal_ll_def_list "STM32G0B1xx") + set(uart_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/uart/hal_ll_uart_pin_map/implementations/doc_ds_80") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_80/hal_ll_uart.c b/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_80/hal_ll_uart.c new file mode 100644 index 000000000..daea2ec59 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_80/hal_ll_uart.c @@ -0,0 +1,1288 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_uart.c + * @brief UART HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_rcc.h" +#include "hal_ll_uart.h" +#include "hal_ll_gpio.h" +#include "hal_ll_core.h" +#include "hal_ll_core_defines.h" +#include "hal_ll_uart_pin_map.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_uart_handle_register_t hal_ll_module_state[UART_MODULE_COUNT] = { (handle_t *)NULL, (handle_t *)NULL, false }; + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_uart_get_module_state_address ((hal_ll_uart_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_uart_get_handle (hal_ll_uart_handle_register_t *)hal_ll_uart_get_module_state_address->hal_ll_uart_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_uart_get_base_struct(_handle) ((hal_ll_uart_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_uart_get_base_from_hal_handle ((hal_ll_uart_hw_specifics_map_t *)((hal_ll_uart_handle_register_t *)\ + (((hal_ll_uart_handle_register_t *)(handle))->hal_ll_uart_handle))->hal_ll_uart_handle)->base + +/*!< @brief Macros used for calculating actual baud rate value and error value */ +#define HAL_LL_UART_ACCEPTABLE_ERROR (float)1.0 +#define hal_ll_uart_get_baud(_clock,_baud,_div) (((_clock/(float)_baud)/_div)-1) +#define hal_ll_uart_get_real_baud(_clock,_baud,_div) (_clock/(_div*(_baud+1))) +#define hal_ll_uart_get_baud_error(_baud_real,_baud) (((float)(abs(_baud_real-_baud))/_baud)*100) + +/*!< @brief Macros defining bit location */ +#define HAL_LL_USART1EN 14 +#define HAL_LL_USART2EN 17 +#define HAL_LL_USART3EN 18 +#define HAL_LL_USART4EN 19 +#define HAL_LL_USART5EN 8 +#define HAL_LL_USART6EN 9 + +#define HAL_LL_UART_CR1_UE 0 +#define HAL_LL_UART_CR1_TE 3 +#define HAL_LL_UART_CR1_RE 2 + +#define HAL_LL_UART_SR_RXNE 5 +#define HAL_LL_UART_SR_TXE 7 + +/*!< @brief Macros defining register bit values */ +#define STOP_BITS_HALF 0x1000U +#define STOP_BITS_ONE 0x00U +#define STOP_BITS_ONE_AND_A_HALF 0x3000U +#define STOP_BITS_TWO 0x2000U + +#define DATA_BIT_7 0x10000000U +#define DATA_BIT_8 0x00U +#define DATA_BIT_9 0x1000U + +#define PARITY_NO 0x00U +#define PARITY_ENABLED 0x400U + +#define PARITY_EVEN 0x00U +#define PARITY_ODD 0x200U + +/*!< @brief Macro used for setting pin alternate functions */ +#define HAL_LL_UART_AF_CONFIG (GPIO_CFG_MODE_ALT_FUNCTION | GPIO_CFG_SPEED_HIGH | GPIO_CFG_OTYPE_PP) + +/*!< @brief Macros used for interrupts */ +#define HAL_LL_UART_IT_MASK 0xFFFFUL +#define HAL_LL_UART_IT_CLEAR_MASK 0x123bffU +#define HAL_LL_UART_IT_CR1_MASK 0x1f0U +#define HAL_LL_UART_IT_CR2_MASK 0x40U +#define HAL_LL_UART_IT_CR3_MASK 0x401U + +#define HAL_LL_UART_CR1_REG_INDEX 1 +#define HAL_LL_UART_CR2_REG_INDEX 2 +#define HAL_LL_UART_CR3_REG_INDEX 3 + +#define HAL_LL_UART_IT_PE 0x100U +#define HAL_LL_UART_IT_TXE (0x10000000 | 0x80U) +#define HAL_LL_UART_IT_TC 0x40U +#define HAL_LL_UART_IT_RXNE (0x10000000 | 0x20U) +#define HAL_LL_UART_IT_IDLE 0x10U +#define HAL_LL_UART_IT_LBD 0x40U +#define HAL_LL_UART_IT_CTS 0x400U +#define HAL_LL_UART_IT_ERR 0x01U + +#define HAL_LL_UART_STATUS_RXNE_FLAG 0x20U +#define HAL_LL_UART_STATUS_TXE_FLAG 0x80U + +/*!< @brief Macro used for status registed flag check + * Used in interrupt handlers. + */ +#define hal_ll_uart_get_status_flags(_handle,_flag) (((hal_ll_uart_base_handle_t *)_handle)->isr & _flag) + +/*!< @brief Macro used for status register flag clearing + * Used in interrupt handlers. + */ +#define hal_ll_uart_clear_status_flag(_handle,_flag) (set_reg_bit( &(((hal_ll_uart_base_handle_t *)_handle)->icr), ( _flag & HAL_LL_UART_IT_CLEAR_MASK ) ) ) + +/*!< @brief Macro used for module interrupt enabling. + * Used in interrupt handlers. + */ +#define __HAL_LL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__ >> 28UL) == HAL_LL_UART_CR1_REG_INDEX)? (__HANDLE__->cr1 |= (__INTERRUPT__ & HAL_LL_UART_IT_MASK)): \ + ((__INTERRUPT__ >> 28UL) == HAL_LL_UART_CR2_REG_INDEX)? (__HANDLE__->cr2 |= (__INTERRUPT__ & HAL_LL_UART_IT_MASK)): \ + (__HANDLE__->cr3 |= (__INTERRUPT__ & HAL_LL_UART_IT_MASK))) + +/*!< @brief Macro used for module interrupt disabling. + * Used in interrupt handlers. + */ +#define __HAL_LL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__ >> 28UL) == HAL_LL_UART_CR1_REG_INDEX)? (__HANDLE__->cr1 &= ~(__INTERRUPT__ & HAL_LL_UART_IT_MASK)): \ + ((__INTERRUPT__ >> 28UL) == HAL_LL_UART_CR2_REG_INDEX)? (__HANDLE__->cr2 &= ~(__INTERRUPT__ & HAL_LL_UART_IT_MASK)): \ + (__HANDLE__->cr3 &= ~ (__INTERRUPT__ & HAL_LL_UART_IT_MASK))) + +/*!< @brief Macro used for module interrupt source check. + * Used in interrupt handlers. + */ +#define __HAL_LL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__ >> 28UL) == 1UL)? ((hal_ll_uart_base_handle_t *)__HANDLE__)->cr1:((((uint32_t)__INTERRUPT__ >> 28UL) == 2UL)? \ + ((hal_ll_uart_base_handle_t *)__HANDLE__)->cr2 : ((hal_ll_uart_base_handle_t *)__HANDLE__)->cr3)) & ((uint32_t)__INTERRUPT__ & HAL_LL_UART_IT_MASK)) + +/*!< @brief UART HW register structure */ +typedef struct +{ + hal_ll_base_addr_t cr1; + hal_ll_base_addr_t cr2; + hal_ll_base_addr_t cr3; + hal_ll_base_addr_t brr; + hal_ll_base_addr_t gtpr; + hal_ll_base_addr_t rtor; + hal_ll_base_addr_t rqr; + hal_ll_base_addr_t isr; + hal_ll_base_addr_t icr; + hal_ll_base_addr_t rdr; + hal_ll_base_addr_t tdr; + hal_ll_base_addr_t presc; +} hal_ll_uart_base_handle_t; + +/*!< @brief UART baud rate structure */ +typedef struct +{ + uint32_t baud; + uint32_t real_baud; +} hal_ll_uart_baud_t; + +/*!< @brief UART hw specific structure */ +typedef struct +{ + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + hal_ll_uart_pins_t pins; + hal_ll_uart_baud_t baud_rate; + hal_ll_uart_parity_t parity; + hal_ll_uart_stop_bits_t stop_bit; + hal_ll_uart_data_bits_t data_bit; +} hal_ll_uart_hw_specifics_map_t; + +/*!< @brief UART hw specific module values */ +typedef struct +{ + uint16_t pin_tx; + uint16_t pin_rx; +} hal_ll_uart_pin_id; + +/*!< @brief UART hw specific error values */ +typedef enum +{ + HAL_LL_UART_SUCCESS = 0, + HAL_LL_UART_WRONG_PINS, + HAL_LL_UART_MODULE_ERROR, + + HAL_LL_UART_ERROR = (-1) +} hal_ll_uart_err_t; + +/*!< @brief UART module state selection */ +typedef enum +{ + HAL_LL_UART_DISABLE = 0, + HAL_LL_UART_ENABLE +} hal_ll_uart_state_t; + +// ------------------------------------------------------------------ VARIABLES +/*!< @brief UART hardware specific info */ +static hal_ll_uart_hw_specifics_map_t hal_ll_uart_hw_specifics_map[] = +{ + #ifdef UART_MODULE_1 + {HAL_LL_UART1_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_1), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + #ifdef UART_MODULE_2 + {HAL_LL_UART2_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_2), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + #ifdef UART_MODULE_3 + {HAL_LL_UART3_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_3), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + #ifdef UART_MODULE_4 + {HAL_LL_UART4_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_4), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + #ifdef UART_MODULE_5 + {HAL_LL_UART5_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_5), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + #ifdef UART_MODULE_6 + {HAL_LL_UART6_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_6), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {0, 0}, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR} +}; + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_uart_handle_register_t *low_level_handle; +static volatile hal_ll_uart_hw_specifics_map_t *hal_ll_uart_hw_specifics_map_local; + +/*!< @brief Global interrupt handlers used in functions */ +static hal_ll_uart_isr_t irq_handler; +static handle_t objects[UART_MODULE_COUNT]; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Check if pins are adequate. + * + * Checks tx and rx pins the user has passed with pre-defined + * pins in tx and rx maps. Take into consideration that module + * index numbers have to be the same for both pins. + * + * @param[in] tx_pin - TX pre-defined pin name. + * @param[in] rx_pin - RX pre-defined pin name. + * @param[in] *index_list - Array containing map index numbers. + * @return hal_ll_pin_name_t Module index based on pins. + * + * Returns pre-defined module index from pin maps, if pins + * are adequate. + */ +static hal_ll_pin_name_t hal_ll_uart_check_pins( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_uart_pin_id *index_list, hal_ll_uart_handle_register_t *handle_map ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * TX and RX pins. + * + * @param[in] module_index UART HW module index -- 0,1,2... + * @param[in] *index_list Array with TX and RX map index values + * and module number + * + * @return None + */ +static void hal_ll_uart_map_pins( uint8_t module_index, hal_ll_uart_pin_id *index_list ); + +/** + * @brief Sets UART pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if UART is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_state - Init/De-init + * + * @return void None. + */ +static void hal_ll_uart_alternate_functions_set_state( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_uart_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_uart_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_uart_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Enable clock for UART module on hardware level. + * + * Initializes UART module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_stat - True(enable clock)/False(disable clock). + * + * @return void None. + */ +static void hal_ll_uart_set_clock( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Finds UART module index. + * + * Finds UART index(module number) based on + * handle value. + * + * @param[in] handle - Object specific context handler. + * + * @return uint8_t Module number. + * Returns values from 0 to 9. + */ +static uint8_t hal_ll_uart_find_index( handle_t *handle ); + +/** + * @brief Get UART module clock speed. + * + * Returns adequate clock speed based on + * UART module base address. + * + * @param[in] module_index - UART module index number. + * + * @return uint8_t Module number. + * Returns clock value. + */ +static uint32_t hal_ll_uart_get_clock_speed( hal_ll_pin_name_t module_index ); + +/** + * @brief Clears UART registers. + * + * Clears UART module configuration + * registers, effectively disabling the module itself. + * Take into consideration that any IRQ bits + * are not cleared. + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * + * @return void None. + */ +static void hal_ll_uart_clear_regs( hal_ll_uart_base_handle_t *hal_ll_hw_reg ); + +/** + * @brief Sets desired baud rate on hardware level. + * + * Initializes module with specified baud rate value. + * Take into consideration that if the difference + * between desired baud rate and actual baud + * rate the hw was initialized to is greater than + * 1%, baud rate shall not be set. + * If this occurs, return value shall be + * the error percentage. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_set_baud_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Sets desired stop bits. + * + * Initializes module on hardware level + * with specified stop bit value. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_set_stop_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Sets desired data bits. + * + * Initializes module on hardware level + * with specified data bit bit value. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_set_data_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Sets desired parity. + * + * Initializes module on hardware level + * with specified parity value. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_set_parity_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Sets module clock value. + * + * Enables/disables specific UART module + * clock gate. + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * @param[in] pin_state - true(enable clock) / false(disable clock) + * + * @return void None. + */ +static void hal_ll_uart_set_module( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ); + +/** + * @brief Sets module TX line state. + * + * Enables/disables specific UART module + * TX pin state + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * @param[in] pin_state - true(enable transmitter pin) / false(disable transmitter pin) + * + * @return void None. + */ +static void hal_ll_uart_set_transmitter( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ); + +/** + * @brief Sets module RX line state. + * + * Enables/disables specific UART module + * RX pin state + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * @param[in] pin_state - true(enable receive pin) / false(disable receive pin) + * + * @return void None. + */ +static void hal_ll_uart_set_receiver( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ); + +/** + * @brief Initialize UART module. + * + * Enables UART module clogk gate first. + * Sets pin alternate function state. + * Initializes specific UART module. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_init( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Initialize UART module on the hardware level. + * + * Performs UART module initialization on + * the hardware level. + * + * Procedure: + * 1. Clears control registers + * 2. Sets data bit value + * 3. Sets parity value + * 4. Sets stop bit value + * 5. Sets baud rate value + * 6. Enables transmit pin + * 7. Enables receive pin + * 8. Enables clock gate for specific module + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_hw_init( hal_ll_uart_hw_specifics_map_t *map ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_uart_register_handle( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_uart_handle_register_t *handle_map, uint8_t *hal_module_id ) { + + hal_ll_uart_pin_id index_list[UART_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + uint16_t pin_check_result; + + // Check if pins are valid + if ( (pin_check_result = hal_ll_uart_check_pins( tx_pin, rx_pin, &index_list, handle_map )) == HAL_LL_PIN_NC ) { + return HAL_LL_UART_WRONG_PINS; + }; + + if ( (hal_ll_uart_hw_specifics_map[pin_check_result].pins.tx_pin.pin_name != tx_pin) || + (hal_ll_uart_hw_specifics_map[pin_check_result].pins.rx_pin.pin_name != rx_pin) ) + { + hal_ll_uart_alternate_functions_set_state( &hal_ll_uart_hw_specifics_map[ pin_check_result ], false ); + + hal_ll_uart_map_pins( pin_check_result, &index_list ); + + hal_ll_uart_alternate_functions_set_state( &hal_ll_uart_hw_specifics_map[ pin_check_result ], true ); + + handle_map[pin_check_result].init_ll_state = false; + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[pin_check_result].hal_ll_uart_handle = (handle_t *)&hal_ll_uart_hw_specifics_map[pin_check_result].base; + + handle_map[pin_check_result].hal_ll_uart_handle = (handle_t *)&hal_ll_module_state[pin_check_result].hal_ll_uart_handle; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_uart( handle_t *handle ) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + hal_ll_uart_pin_id index_list[UART_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + uint16_t pin_check_result; + + if ( (pin_check_result = hal_ll_uart_check_pins( hal_ll_uart_hw_specifics_map_local->pins.tx_pin.pin_name, + hal_ll_uart_hw_specifics_map_local->pins.rx_pin.pin_name, &index_list, (void *)0 ) ) == HAL_LL_PIN_NC ) { + return HAL_LL_UART_WRONG_PINS; + }; + + hal_ll_uart_init( hal_ll_uart_hw_specifics_map_local ); + + hal_ll_module_state[pin_check_result].hal_ll_uart_handle = (handle_t *)&hal_ll_uart_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_uart_set_baud( handle_t *handle, uint32_t baud ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->baud_rate.baud = baud; + + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return hal_ll_uart_hw_specifics_map_local->baud_rate.real_baud; +} + +hal_ll_err_t hal_ll_uart_set_parity( handle_t *handle, hal_ll_uart_parity_t parity ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->parity = parity; + + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_uart_set_stop_bits( handle_t *handle, hal_ll_uart_stop_bits_t stop_bit ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->stop_bit = stop_bit; + + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_uart_set_data_bits( handle_t *handle, hal_ll_uart_data_bits_t data_bit ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + // Chips using implementation 1 do not support 7 bit data + if( data_bit == HAL_LL_UART_DATA_BITS_7 ) { + return HAL_LL_UART_MODULE_ERROR; + } + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->data_bit = data_bit; + + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +void hal_ll_uart_close( handle_t *handle ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + if( low_level_handle->hal_ll_uart_handle != NULL ) { + hal_ll_uart_alternate_functions_set_state( hal_ll_uart_hw_specifics_map_local, false ); + + hal_ll_uart_irq_disable(handle, HAL_LL_UART_IRQ_RX); + hal_ll_uart_irq_disable(handle, HAL_LL_UART_IRQ_TX); + + hal_ll_uart_clear_regs(hal_ll_uart_hw_specifics_map_local->base); + hal_ll_uart_set_clock(hal_ll_uart_hw_specifics_map_local, false); + + hal_ll_uart_hw_specifics_map_local->pins.tx_pin.pin_name = HAL_LL_PIN_NC; + hal_ll_uart_hw_specifics_map_local->pins.tx_pin.pin_af = 0; + hal_ll_uart_hw_specifics_map_local->pins.rx_pin.pin_name = HAL_LL_PIN_NC; + hal_ll_uart_hw_specifics_map_local->pins.rx_pin.pin_af = 0; + + hal_ll_uart_hw_specifics_map_local->baud_rate.baud = 115200UL; + hal_ll_uart_hw_specifics_map_local->baud_rate.real_baud = 0; + + irq_handler = NULL; + objects[ hal_ll_uart_find_index( handle ) ] = NULL; + + low_level_handle->hal_ll_uart_handle = NULL; + low_level_handle->hal_drv_uart_handle = NULL; + + low_level_handle->init_ll_state = false; + } +} + +void hal_ll_uart_register_irq_handler( handle_t *handle, hal_ll_uart_isr_t handler, handle_t obj ) +{ + irq_handler = handler; + objects[ hal_ll_uart_find_index( handle ) ] = obj; +} + +void hal_ll_uart_irq_enable( handle_t *handle, hal_ll_uart_irq_t irq ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + switch ( irq ) { + case HAL_LL_UART_IRQ_RX: + __HAL_LL_UART_ENABLE_IT( hal_ll_hw_reg, HAL_LL_UART_IT_RXNE ); + break; + + case HAL_LL_UART_IRQ_TX: + __HAL_LL_UART_ENABLE_IT( hal_ll_hw_reg, HAL_LL_UART_IT_TXE ); + break; + + default: + break; + } + + switch ( hal_ll_uart_hw_specifics_map_local->module_index ) + { + #if defined(UART_MODULE_1) && defined(UART1_NVIC) + case hal_ll_uart_module_num(UART_MODULE_1): + hal_ll_core_enable_irq( UART1_NVIC ); + break; + #endif + + #if defined(UART_MODULE_2) && defined(UART2_NVIC) + case hal_ll_uart_module_num(UART_MODULE_2): + hal_ll_core_enable_irq( UART2_NVIC ); + break; + #endif + + #if defined(UART_MODULE_3) && defined(UART3_NVIC) + case hal_ll_uart_module_num(UART_MODULE_3): + hal_ll_core_enable_irq( UART3_NVIC ); + break; + #endif + + #if defined(UART_MODULE_4) && defined(UART4_NVIC) + case hal_ll_uart_module_num(UART_MODULE_4): + hal_ll_core_enable_irq( UART4_NVIC ); + break; + #endif + + #if defined(UART_MODULE_5) && defined(UART5_NVIC) + case hal_ll_uart_module_num(UART_MODULE_5): + hal_ll_core_enable_irq( UART5_NVIC ); + break; + #endif + + #if defined(UART_MODULE_6) && defined(UART6_NVIC) + case hal_ll_uart_module_num(UART_MODULE_6): + hal_ll_core_enable_irq( UART6_NVIC ); + break; + #endif + + + default: + break; + } +} + +void hal_ll_uart_irq_disable( handle_t *handle, hal_ll_uart_irq_t irq ) +{ + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + switch ( irq ) { + case HAL_LL_UART_IRQ_RX: + __HAL_LL_UART_DISABLE_IT( hal_ll_hw_reg, HAL_LL_UART_IT_RXNE ); + break; + + case HAL_LL_UART_IRQ_TX: + __HAL_LL_UART_DISABLE_IT( hal_ll_hw_reg, HAL_LL_UART_IT_TXE ); + break; + + default: + break; + } + + // Check if module interrupt flags are set or not + if ( ( !check_reg_bit( &hal_ll_hw_reg->cr1, HAL_LL_UART_SR_RXNE ) ) && + ( !check_reg_bit( &hal_ll_hw_reg->cr1, HAL_LL_UART_SR_TXE ) ) ) + { + switch ( hal_ll_uart_hw_specifics_map_local->module_index ) + { + #if defined(UART_MODULE_1) && defined(UART1_NVIC) + case hal_ll_uart_module_num(UART_MODULE_1): + hal_ll_core_disable_irq( UART1_NVIC ); + break; + #endif + + #if defined(UART_MODULE_2) && defined(UART2_NVIC) + case hal_ll_uart_module_num(UART_MODULE_2): + hal_ll_core_disable_irq( UART2_NVIC ); + break; + #endif + + #if defined(UART_MODULE_3) && defined(UART3_NVIC) + case hal_ll_uart_module_num(UART_MODULE_3): + hal_ll_core_disable_irq( UART3_NVIC ); + break; + #endif + + #if defined(UART_MODULE_4) && defined(UART4_NVIC) + case hal_ll_uart_module_num(UART_MODULE_4): + hal_ll_core_disable_irq( UART4_NVIC ); + break; + #endif + + #if defined(UART_MODULE_5) && defined(UART5_NVIC) + case hal_ll_uart_module_num(UART_MODULE_5): + hal_ll_core_disable_irq( UART5_NVIC ); + break; + #endif + + #if defined(UART_MODULE_6) && defined(UART6_NVIC) + case hal_ll_uart_module_num(UART_MODULE_6): + hal_ll_core_disable_irq( UART6_NVIC ); + break; + #endif + + + default: + break; + } + } +} + +void hal_ll_uart_write( handle_t *handle, uint8_t wr_data) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + hal_ll_hw_reg->tdr = wr_data; +} + +uint8_t hal_ll_uart_read( handle_t *handle ) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + return ( hal_ll_hw_reg->rdr ); +} + +// ------------------------------------------------------------- DEFAULT EXCEPTION HANDLERS + +#if defined(USART_MODULE_1) +void MARK_AS_IRQ_HANDLER UART1_IRQHandler() MIKROC_IV(UART1_NVIC) { + #ifdef USART_MODULE_1 + if( hal_ll_uart_get_status_flags( HAL_LL_USART1_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART1_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART1_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_1) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_USART1_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART1_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART1_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_1) ], HAL_LL_UART_IRQ_TX ); + } + } + #endif +} +#endif + +#if defined(USART_MODULE_2) || defined(LPUART_MODULE_2) +void MARK_AS_IRQ_HANDLER UART2_LPUART2_IRQHandler() MIKROC_IV(UART2_NVIC) { + #ifdef USART_MODULE_2 + if( hal_ll_uart_get_status_flags( HAL_LL_USART2_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART2_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART2_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_2) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_USART2_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART2_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART2_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_2) ], HAL_LL_UART_IRQ_TX ); + } + } + #endif + + #ifdef LPUART_MODULE_2 + if( hal_ll_uart_get_status_flags( HAL_LL_LPUART2_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_LPUART2_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_LPUART2_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(LPUART_MODULE_2) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_LPUART2_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_LPUART2_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_LPUART2_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(LPUART_MODULE_2) ], HAL_LL_UART_IRQ_TX ); + } + } + #endif +} +#endif + +#if defined(USART_MODULE_3) || defined(USART_MODULE_4) || defined(USART_MODULE_5) || defined(USART_MODULE_6) || defined(LPUART_MODULE_1) +void MARK_AS_IRQ_HANDLER UART3_4_5_6_LPUART1_IRQHandler() MIKROC_IV(UART3_NVIC) { + #ifdef USART_MODULE_3 + if( hal_ll_uart_get_status_flags( HAL_LL_USART3_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART3_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART3_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_3) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_USART3_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART3_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART3_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_3) ], HAL_LL_UART_IRQ_TX ); + } + } + #endif + + #ifdef USART_MODULE_4 + if( hal_ll_uart_get_status_flags( HAL_LL_USART4_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART4_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART4_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_4) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_USART4_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART4_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART4_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_4) ], HAL_LL_UART_IRQ_TX ); + } + } + #endif + + #ifdef USART_MODULE_5 + if( hal_ll_uart_get_status_flags( HAL_LL_USART5_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART5_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART5_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_5) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_USART5_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART5_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART5_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_5) ], HAL_LL_UART_IRQ_TX ); + } + } + #endif + + #ifdef USART_MODULE_6 + if( hal_ll_uart_get_status_flags( HAL_LL_USART6_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART6_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART6_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_6) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_USART6_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART6_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART6_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_6) ], HAL_LL_UART_IRQ_TX ); + } + } + #endif + + #ifdef LPUART_MODULE_1 + if( hal_ll_uart_get_status_flags( HAL_LL_LPUART1_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_LPUART1_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_LPUART1_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(LPUART_MODULE_1) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_LPUART1_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_LPUART1_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_LPUART1_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(LPUART_MODULE_1) ], HAL_LL_UART_IRQ_TX ); + } + } + #endif +} +#endif + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static uint8_t hal_ll_uart_find_index( handle_t *handle ) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + if( hal_ll_uart_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + return hal_ll_uart_hw_specifics_map_local->module_index; + } else { + return NULL; + } +} + +static hal_ll_pin_name_t hal_ll_uart_check_pins( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_uart_pin_id *index_list, hal_ll_uart_handle_register_t *handle_map ) { + static const uint16_t tx_map_size = ( sizeof( hal_ll_uart_tx_map ) / sizeof( hal_ll_uart_pin_map_t ) ); + static const uint16_t rx_map_size = ( sizeof( hal_ll_uart_rx_map ) / sizeof( hal_ll_uart_pin_map_t ) ); + uint8_t hal_ll_module_id = 0; + uint8_t index_counter = 0; + uint16_t tx_index; + uint16_t rx_index; + + if ( (HAL_LL_PIN_NC == tx_pin) || (HAL_LL_PIN_NC == rx_pin) ) { + return HAL_LL_PIN_NC; + } + + for ( tx_index = 0; tx_index < tx_map_size; tx_index++ ) + { + if ( hal_ll_uart_tx_map[ tx_index ].pin == tx_pin ) + { + for ( rx_index = 0; rx_index < rx_map_size; rx_index++ ) + { + if ( hal_ll_uart_rx_map[ rx_index ].pin == rx_pin ) + { + if ( hal_ll_uart_tx_map[ tx_index ].base == hal_ll_uart_rx_map[ rx_index ].base ) { + // Get module number + hal_ll_module_id = hal_ll_uart_tx_map[ tx_index ].module_index; + + // Map pin names + index_list[hal_ll_module_id].pin_tx = tx_index; + index_list[hal_ll_module_id].pin_rx = rx_index; + + // Check if module is taken + if ( NULL == handle_map[ hal_ll_module_id ].hal_drv_uart_handle ) { + return hal_ll_module_id; + } else if ( UART_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static hal_ll_uart_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof(hal_ll_uart_handle_register_t)); + static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof(hal_ll_uart_handle_register_t)); + + while( hal_ll_module_count-- ) { + if (hal_ll_uart_get_base_from_hal_handle == hal_ll_uart_hw_specifics_map[hal_ll_module_count].base) { + return &hal_ll_uart_hw_specifics_map[hal_ll_module_count]; + } + } + + return &hal_ll_uart_hw_specifics_map[hal_ll_module_error]; +} + +static void hal_ll_uart_set_clock( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ) { + switch ( map->module_index ) + { + #ifdef UART_MODULE_1 + case ( hal_ll_uart_module_num(UART_MODULE_1) ): + (hal_ll_state == true)?(set_reg_bit( _RCC_APBENR2, HAL_LL_USART1EN )):(clear_reg_bit( _RCC_APBENR2, HAL_LL_USART1EN )); + break; + #endif + + #ifdef UART_MODULE_2 + case ( hal_ll_uart_module_num(UART_MODULE_2) ): + (hal_ll_state == true)?(set_reg_bit( _RCC_APBENR1, HAL_LL_USART2EN )):(clear_reg_bit( _RCC_APBENR1, HAL_LL_USART2EN )); + break; + #endif + + #ifdef UART_MODULE_3 + case ( hal_ll_uart_module_num(UART_MODULE_3) ): + (hal_ll_state == true)?(set_reg_bit( _RCC_APBENR1, HAL_LL_USART3EN )):(clear_reg_bit( _RCC_APBENR1, HAL_LL_USART3EN )); + break; + #endif + + #ifdef UART_MODULE_4 + case ( hal_ll_uart_module_num(UART_MODULE_4) ): + (hal_ll_state == true)?(set_reg_bit( _RCC_APBENR1, HAL_LL_USART4EN )):(clear_reg_bit( _RCC_APBENR1, HAL_LL_USART4EN )); + break; + #endif + + #ifdef UART_MODULE_5 + case ( hal_ll_uart_module_num(UART_MODULE_5) ): + (hal_ll_state == true)?(set_reg_bit( _RCC_APBENR1, HAL_LL_USART5EN )):(clear_reg_bit( _RCC_APBENR1, HAL_LL_USART5EN )); + break; + #endif + + #ifdef UART_MODULE_6 + case ( hal_ll_uart_module_num(UART_MODULE_6) ): + (hal_ll_state == true)?(set_reg_bit( _RCC_APBENR1, HAL_LL_USART6EN )):(clear_reg_bit( _RCC_APBENR1, HAL_LL_USART6EN )); + break; + #endif + + + default: + break; + } +} + +static void hal_ll_uart_map_pins( uint8_t module_index, hal_ll_uart_pin_id *index_list ) { + // Map new pins + hal_ll_uart_hw_specifics_map[module_index].pins.tx_pin.pin_name = hal_ll_uart_tx_map[ index_list[module_index].pin_tx ].pin; + hal_ll_uart_hw_specifics_map[module_index].pins.rx_pin.pin_name = hal_ll_uart_rx_map[ index_list[module_index].pin_rx ].pin; + // TX and RX could have different alternate function settings, hence save both AF values + hal_ll_uart_hw_specifics_map[module_index].pins.tx_pin.pin_af = hal_ll_uart_tx_map[ index_list[module_index].pin_tx ].af; + hal_ll_uart_hw_specifics_map[module_index].pins.rx_pin.pin_af = hal_ll_uart_rx_map[ index_list[module_index].pin_rx ].af; +} + +static void hal_ll_uart_alternate_functions_set_state( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ) { + module_struct module; + + if ( (map->pins.tx_pin.pin_name != HAL_LL_PIN_NC) && map->pins.rx_pin.pin_name != HAL_LL_PIN_NC ) { + module.pins[0] = VALUE( map->pins.tx_pin.pin_name, map->pins.tx_pin.pin_af ); + module.pins[1] = VALUE( map->pins.rx_pin.pin_name, map->pins.rx_pin.pin_af ); + module.pins[2] = GPIO_MODULE_STRUCT_END; + + module.configs[0] = HAL_LL_UART_AF_CONFIG; + module.configs[1] = HAL_LL_UART_AF_CONFIG; + module.configs[2] = GPIO_MODULE_STRUCT_END; + + /* STM32F1xx specific */ + module.gpio_remap = map->pins.tx_pin.pin_af; + + hal_ll_gpio_module_struct_init( &module, hal_ll_state ); + } +} + +static void hal_ll_uart_set_baud_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + uint32_t reg = 0; + uint32_t integer_divider = 0; + uint32_t fractional_divider = 0; + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); + uint32_t hal_ll_baud_value = hal_ll_uart_get_baud(hal_ll_uart_get_clock_speed(map->module_index),map->baud_rate.baud,4); + uint32_t hal_ll_baud_real_value = hal_ll_uart_get_real_baud(hal_ll_uart_get_clock_speed(map->module_index),hal_ll_baud_value,4); + + // if error greater than specified, cancel setting baud rate + if( (hal_ll_uart_get_baud_error(hal_ll_baud_real_value,map->baud_rate.baud)) > HAL_LL_UART_ACCEPTABLE_ERROR ) { + map->baud_rate.real_baud = hal_ll_uart_get_baud_error(hal_ll_baud_real_value,map->baud_rate.baud); + } else { + map->baud_rate.real_baud = hal_ll_baud_real_value; + + integer_divider = ( ( 25 * hal_ll_uart_get_clock_speed( map->module_index ) ) / ( 4 * ( map->baud_rate.baud ) ) ); + reg = ( integer_divider / 100 ) << 4; + + fractional_divider = integer_divider - ( 100 * ( reg >> 4 ) ); + reg |= ( ( ( ( fractional_divider * 16 ) + 50 ) / 100 ) ) & 0x0F; + + hal_ll_hw_reg->brr = ( uint16_t )reg; + } +} + +static uint32_t hal_ll_uart_get_clock_speed( hal_ll_pin_name_t module_index ) { + rcc_clocks_t rcc_clocks; + + RCC_GetClocksFrequency( &rcc_clocks ); + + switch ( module_index ) + { + #ifdef UART_MODULE_1 + case ( hal_ll_uart_module_num(UART_MODULE_1) ): + return rcc_clocks.pclk; + break; + #endif + + #ifdef UART_MODULE_2 + case ( hal_ll_uart_module_num(UART_MODULE_2) ): + return rcc_clocks.pclk; + break; + #endif + + #ifdef UART_MODULE_3 + case ( hal_ll_uart_module_num(UART_MODULE_3) ): + return rcc_clocks.pclk; + break; + #endif + + #ifdef UART_MODULE_4 + case ( hal_ll_uart_module_num(UART_MODULE_4) ): + return rcc_clocks.pclk; + break; + #endif + + #ifdef UART_MODULE_5 + case ( hal_ll_uart_module_num(UART_MODULE_5) ): + return rcc_clocks.pclk; + break; + #endif + + #ifdef UART_MODULE_6 + case ( hal_ll_uart_module_num(UART_MODULE_6) ): + return rcc_clocks.pclk; + break; + #endif + + + default: + break; + } + + return NULL; +} + +static void hal_ll_uart_set_stop_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); + + switch ( map->stop_bit ) + { + case HAL_LL_UART_STOP_BITS_HALF: + hal_ll_hw_reg->cr2 |= STOP_BITS_HALF; + break; + case HAL_LL_UART_STOP_BITS_ONE: + hal_ll_hw_reg->cr2 |= STOP_BITS_ONE; + break; + case HAL_LL_UART_STOP_BITS_ONE_AND_A_HALF: + hal_ll_hw_reg->cr2 |= STOP_BITS_ONE_AND_A_HALF; + break; + case HAL_LL_UART_STOP_BITS_TWO: + hal_ll_hw_reg->cr2 |= STOP_BITS_TWO; + break; + + default: + break; + } +} + +static void hal_ll_uart_set_data_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); + + switch ( map->data_bit ) + { + case HAL_LL_UART_DATA_BITS_7: + hal_ll_hw_reg->cr1 |= DATA_BIT_7; + break; + + case HAL_LL_UART_DATA_BITS_8: + hal_ll_hw_reg->cr1 |= DATA_BIT_8; + break; + + case HAL_LL_UART_DATA_BITS_9: + hal_ll_hw_reg->cr1 |= DATA_BIT_9; + break; + + + default: + break; + } +} + +static void hal_ll_uart_set_parity_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); + + switch ( map->parity ) + { + case HAL_LL_UART_PARITY_NONE: + hal_ll_hw_reg->cr1 |= PARITY_NO; + break; + case HAL_LL_UART_PARITY_EVEN: + hal_ll_hw_reg->cr1 |= PARITY_ENABLED | PARITY_EVEN; + break; + case HAL_LL_UART_PARITY_ODD: + hal_ll_hw_reg->cr1 |= PARITY_ENABLED | PARITY_ODD; + break; + + default: + break; + } +} + +static void hal_ll_uart_set_module( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ) { + switch ( pin_state ) + { + case HAL_LL_UART_DISABLE: + clear_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_UE ); + break; + + case HAL_LL_UART_ENABLE: + set_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_UE ); + break; + + default: + break; + } +} + +static void hal_ll_uart_set_transmitter( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ) { + switch ( pin_state ) + { + case HAL_LL_UART_DISABLE: + clear_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_TE ); + break; + + case HAL_LL_UART_ENABLE: + set_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_TE ); + break; + + default: + break; + } +} + +static void hal_ll_uart_set_receiver( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ) { + switch ( pin_state ) + { + case HAL_LL_UART_DISABLE: + clear_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_RE ); + break; + + case HAL_LL_UART_ENABLE: + set_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_RE ); + break; + + default: + break; + } +} + +static void hal_ll_uart_clear_regs( hal_ll_uart_base_handle_t *hal_ll_hw_reg ) { + hal_ll_hw_reg->cr1 &= HAL_LL_UART_IT_CR1_MASK; + hal_ll_hw_reg->cr2 &= HAL_LL_UART_IT_CR2_MASK; + hal_ll_hw_reg->cr3 &= HAL_LL_UART_IT_CR3_MASK; +} + +static void hal_ll_uart_hw_init( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_clear_regs( map->base ); + + hal_ll_uart_set_data_bits_bare_metal( map ); + + hal_ll_uart_set_parity_bare_metal( map ); + + hal_ll_uart_set_stop_bits_bare_metal( map ); + + hal_ll_uart_set_baud_bare_metal( map ); + + hal_ll_uart_set_transmitter( map->base, HAL_LL_UART_ENABLE ); + + hal_ll_uart_set_receiver( map->base, HAL_LL_UART_ENABLE ); + + hal_ll_uart_set_module( map->base, HAL_LL_UART_ENABLE ); +} + +static void hal_ll_uart_init( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_set_clock( map, true ); + + hal_ll_uart_alternate_functions_set_state( map, true ); + + hal_ll_uart_hw_init( map ); +} +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_81/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_81/CMakeLists.cmake new file mode 100644 index 000000000..2e6ba8a31 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_81/CMakeLists.cmake @@ -0,0 +1,9 @@ +if(${MCU_NAME} MATCHES "^STM32G0C1CC$|^STM32G0C1KC$|^STM32G0C1MC$|^STM32G0C1RC$|^STM32G0C1VC$|^STM32G0C1CE$|^STM32G0C1KE$|^STM32G0C1ME$|^STM32G0C1NE$|^STM32G0C1RE$|^STM32G0C1VE$") + set(uart_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_uart.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_81") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_81") + list(APPEND hal_ll_def_list "STM32G0xx") + list(APPEND hal_ll_def_list "STM32G0Cxx") + list(APPEND hal_ll_def_list "STM32G0C1xx") + set(uart_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/uart/hal_ll_uart_pin_map/implementations/doc_ds_81") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_81/hal_ll_uart.c b/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_81/hal_ll_uart.c new file mode 100644 index 000000000..51e1d5b15 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_81/hal_ll_uart.c @@ -0,0 +1,1303 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_uart.c + * @brief UART HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_rcc.h" +#include "hal_ll_uart.h" +#include "hal_ll_gpio.h" +#include "hal_ll_core.h" +#include "hal_ll_core_defines.h" +#include "hal_ll_uart_pin_map.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_uart_handle_register_t hal_ll_module_state[UART_MODULE_COUNT] = { (handle_t *)NULL, (handle_t *)NULL, false }; + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_uart_get_module_state_address ((hal_ll_uart_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_uart_get_handle (hal_ll_uart_handle_register_t *)hal_ll_uart_get_module_state_address->hal_ll_uart_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_uart_get_base_struct(_handle) ((hal_ll_uart_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_uart_get_base_from_hal_handle ((hal_ll_uart_hw_specifics_map_t *)((hal_ll_uart_handle_register_t *)\ + (((hal_ll_uart_handle_register_t *)(handle))->hal_ll_uart_handle))->hal_ll_uart_handle)->base + +/*!< @brief Macros used for calculating actual baud rate value and error value */ +#define HAL_LL_UART_ACCEPTABLE_ERROR (float)1.0 +#define hal_ll_uart_get_baud(_clock,_baud,_div) (((_clock/(float)_baud)/_div)-1) +#define hal_ll_uart_get_real_baud(_clock,_baud,_div) (_clock/(_div*(_baud+1))) +#define hal_ll_uart_get_baud_error(_baud_real,_baud) (((float)(abs(_baud_real-_baud))/_baud)*100) + +/*!< @brief Macros defining bit location */ +#define HAL_LL_USART1EN 14 + +#define HAL_LL_USART2EN 17 + +#define HAL_LL_USART3EN 18 + +#define HAL_LL_USART4EN 19 + +#define HAL_LL_USART5EN 8 + +#define HAL_LL_USART6EN 9 + + +#define HAL_LL_UART_CR1_UE 0 +#define HAL_LL_UART_CR1_TE 3 +#define HAL_LL_UART_CR1_RE 2 + +#define HAL_LL_UART_SR_RXNE 5 +#define HAL_LL_UART_SR_TXE 7 + +/*!< @brief Macros defining register bit values */ +#define STOP_BITS_HALF 0x1000U +#define STOP_BITS_ONE 0x00U +#define STOP_BITS_ONE_AND_A_HALF 0x3000U +#define STOP_BITS_TWO 0x2000U + +#define DATA_BIT_7 0x10000000U +#define DATA_BIT_8 0x00U +#define DATA_BIT_9 0x1000U + +#define PARITY_NO 0x00U +#define PARITY_ENABLED 0x400U + +#define PARITY_EVEN 0x00U +#define PARITY_ODD 0x200U + +/*!< @brief Macro used for setting pin alternate functions */ +#define HAL_LL_UART_AF_CONFIG (GPIO_CFG_MODE_ALT_FUNCTION | GPIO_CFG_SPEED_HIGH | GPIO_CFG_OTYPE_PP) + +/*!< @brief Macros used for interrupts */ +#define HAL_LL_UART_IT_MASK 0xFFFFUL +#define HAL_LL_UART_IT_CLEAR_MASK 0x123bffU +#define HAL_LL_UART_IT_CR1_MASK 0x1f0U +#define HAL_LL_UART_IT_CR2_MASK 0x40U +#define HAL_LL_UART_IT_CR3_MASK 0x401U + +#define HAL_LL_UART_CR1_REG_INDEX 1 +#define HAL_LL_UART_CR2_REG_INDEX 2 +#define HAL_LL_UART_CR3_REG_INDEX 3 + +#define HAL_LL_UART_IT_PE 0x100U +#define HAL_LL_UART_IT_TXE (0x10000000 | 0x80U) +#define HAL_LL_UART_IT_TC 0x40U +#define HAL_LL_UART_IT_RXNE (0x10000000 | 0x20U) +#define HAL_LL_UART_IT_IDLE 0x10U +#define HAL_LL_UART_IT_LBD 0x40U +#define HAL_LL_UART_IT_CTS 0x400U +#define HAL_LL_UART_IT_ERR 0x01U + +#define HAL_LL_UART_STATUS_RXNE_FLAG 0x20U +#define HAL_LL_UART_STATUS_TXE_FLAG 0x80U + +/*!< @brief Macro used for status registed flag check + * Used in interrupt handlers. + */ +#define hal_ll_uart_get_status_flags(_handle,_flag) (((hal_ll_uart_base_handle_t *)_handle)->isr & _flag) + +/*!< @brief Macro used for status register flag clearing + * Used in interrupt handlers. + */ +#define hal_ll_uart_clear_status_flag(_handle,_flag) (set_reg_bit( &(((hal_ll_uart_base_handle_t *)_handle)->icr), ( _flag & HAL_LL_UART_IT_CLEAR_MASK ) ) ) + +/*!< @brief Macro used for module interrupt enabling. + * Used in interrupt handlers. + */ +#define __HAL_LL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__ >> 28UL) == HAL_LL_UART_CR1_REG_INDEX)? (__HANDLE__->cr1 |= (__INTERRUPT__ & HAL_LL_UART_IT_MASK)): \ + ((__INTERRUPT__ >> 28UL) == HAL_LL_UART_CR2_REG_INDEX)? (__HANDLE__->cr2 |= (__INTERRUPT__ & HAL_LL_UART_IT_MASK)): \ + (__HANDLE__->cr3 |= (__INTERRUPT__ & HAL_LL_UART_IT_MASK))) + +/*!< @brief Macro used for module interrupt disabling. + * Used in interrupt handlers. + */ +#define __HAL_LL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__ >> 28UL) == HAL_LL_UART_CR1_REG_INDEX)? (__HANDLE__->cr1 &= ~(__INTERRUPT__ & HAL_LL_UART_IT_MASK)): \ + ((__INTERRUPT__ >> 28UL) == HAL_LL_UART_CR2_REG_INDEX)? (__HANDLE__->cr2 &= ~(__INTERRUPT__ & HAL_LL_UART_IT_MASK)): \ + (__HANDLE__->cr3 &= ~ (__INTERRUPT__ & HAL_LL_UART_IT_MASK))) + +/*!< @brief Macro used for module interrupt source check. + * Used in interrupt handlers. + */ +#define __HAL_LL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__ >> 28UL) == 1UL)? ((hal_ll_uart_base_handle_t *)__HANDLE__)->cr1:((((uint32_t)__INTERRUPT__ >> 28UL) == 2UL)? \ + ((hal_ll_uart_base_handle_t *)__HANDLE__)->cr2 : ((hal_ll_uart_base_handle_t *)__HANDLE__)->cr3)) & ((uint32_t)__INTERRUPT__ & HAL_LL_UART_IT_MASK)) + +/*!< @brief UART HW register structure */ +typedef struct +{ + hal_ll_base_addr_t cr1; + hal_ll_base_addr_t cr2; + hal_ll_base_addr_t cr3; + hal_ll_base_addr_t brr; + hal_ll_base_addr_t gtpr; + hal_ll_base_addr_t rtor; + hal_ll_base_addr_t rqr; + hal_ll_base_addr_t isr; + hal_ll_base_addr_t icr; + hal_ll_base_addr_t rdr; + hal_ll_base_addr_t tdr; + hal_ll_base_addr_t presc; + +} hal_ll_uart_base_handle_t; + +/*!< @brief UART baud rate structure */ +typedef struct +{ + uint32_t baud; + uint32_t real_baud; +} hal_ll_uart_baud_t; + +/*!< @brief UART hw specific structure */ +typedef struct +{ + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + hal_ll_uart_pins_t pins; + hal_ll_uart_baud_t baud_rate; + hal_ll_uart_parity_t parity; + hal_ll_uart_stop_bits_t stop_bit; + hal_ll_uart_data_bits_t data_bit; +} hal_ll_uart_hw_specifics_map_t; + +/*!< @brief UART hw specific module values */ +typedef struct +{ + uint16_t pin_tx; + uint16_t pin_rx; +} hal_ll_uart_pin_id; + +/*!< @brief UART hw specific error values */ +typedef enum +{ + HAL_LL_UART_SUCCESS = 0, + HAL_LL_UART_WRONG_PINS, + HAL_LL_UART_MODULE_ERROR, + + HAL_LL_UART_ERROR = (-1) +} hal_ll_uart_err_t; + +/*!< @brief UART module state selection */ +typedef enum +{ + HAL_LL_UART_DISABLE = 0, + HAL_LL_UART_ENABLE +} hal_ll_uart_state_t; + +// ------------------------------------------------------------------ VARIABLES +/*!< @brief UART hardware specific info */ +static hal_ll_uart_hw_specifics_map_t hal_ll_uart_hw_specifics_map[] = +{ + #ifdef UART_MODULE_1 + {HAL_LL_UART1_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_1), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + + #ifdef UART_MODULE_2 + {HAL_LL_UART2_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_2), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + + #ifdef UART_MODULE_3 + {HAL_LL_UART3_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_3), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + + #ifdef UART_MODULE_4 + {HAL_LL_UART4_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_4), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + + #ifdef UART_MODULE_5 + {HAL_LL_UART5_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_5), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + + #ifdef UART_MODULE_6 + {HAL_LL_UART6_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_6), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + + + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {0, 0}, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR} +}; + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_uart_handle_register_t *low_level_handle; +static volatile hal_ll_uart_hw_specifics_map_t *hal_ll_uart_hw_specifics_map_local; + +/*!< @brief Global interrupt handlers used in functions */ +static hal_ll_uart_isr_t irq_handler; +static handle_t objects[UART_MODULE_COUNT]; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Check if pins are adequate. + * + * Checks tx and rx pins the user has passed with pre-defined + * pins in tx and rx maps. Take into consideration that module + * index numbers have to be the same for both pins. + * + * @param[in] tx_pin - TX pre-defined pin name. + * @param[in] rx_pin - RX pre-defined pin name. + * @param[in] *index_list - Array containing map index numbers. + * @return hal_ll_pin_name_t Module index based on pins. + * + * Returns pre-defined module index from pin maps, if pins + * are adequate. + */ +static hal_ll_pin_name_t hal_ll_uart_check_pins( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_uart_pin_id *index_list, hal_ll_uart_handle_register_t *handle_map ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * TX and RX pins. + * + * @param[in] module_index UART HW module index -- 0,1,2... + * @param[in] *index_list Array with TX and RX map index values + * and module number + * + * @return None + */ +static void hal_ll_uart_map_pins( uint8_t module_index, hal_ll_uart_pin_id *index_list ); + +/** + * @brief Sets UART pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if UART is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_state - Init/De-init + * + * @return void None. + */ +static void hal_ll_uart_alternate_functions_set_state( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_uart_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_uart_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_uart_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Enable clock for UART module on hardware level. + * + * Initializes UART module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_stat - True(enable clock)/False(disable clock). + * + * @return void None. + */ +static void hal_ll_uart_set_clock( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Finds UART module index. + * + * Finds UART index(module number) based on + * handle value. + * + * @param[in] handle - Object specific context handler. + * + * @return uint8_t Module number. + * Returns values from 0 to 9. + */ +static uint8_t hal_ll_uart_find_index( handle_t *handle ); + +/** + * @brief Get UART module clock speed. + * + * Returns adequate clock speed based on + * UART module base address. + * + * @param[in] module_index - UART module index number. + * + * @return uint8_t Module number. + * Returns clock value. + */ +static uint32_t hal_ll_uart_get_clock_speed( hal_ll_pin_name_t module_index ); + +/** + * @brief Clears UART registers. + * + * Clears UART module configuration + * registers, effectively disabling the module itself. + * Take into consideration that any IRQ bits + * are not cleared. + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * + * @return void None. + */ +static void hal_ll_uart_clear_regs( hal_ll_uart_base_handle_t *hal_ll_hw_reg ); + +/** + * @brief Sets desired baud rate on hardware level. + * + * Initializes module with specified baud rate value. + * Take into consideration that if the difference + * between desired baud rate and actual baud + * rate the hw was initialized to is greater than + * 1%, baud rate shall not be set. + * If this occurs, return value shall be + * the error percentage. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_set_baud_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Sets desired stop bits. + * + * Initializes module on hardware level + * with specified stop bit value. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_set_stop_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Sets desired data bits. + * + * Initializes module on hardware level + * with specified data bit bit value. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_set_data_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Sets desired parity. + * + * Initializes module on hardware level + * with specified parity value. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_set_parity_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Sets module clock value. + * + * Enables/disables specific UART module + * clock gate. + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * @param[in] pin_state - true(enable clock) / false(disable clock) + * + * @return void None. + */ +static void hal_ll_uart_set_module( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ); + +/** + * @brief Sets module TX line state. + * + * Enables/disables specific UART module + * TX pin state + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * @param[in] pin_state - true(enable transmitter pin) / false(disable transmitter pin) + * + * @return void None. + */ +static void hal_ll_uart_set_transmitter( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ); + +/** + * @brief Sets module RX line state. + * + * Enables/disables specific UART module + * RX pin state + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * @param[in] pin_state - true(enable receive pin) / false(disable receive pin) + * + * @return void None. + */ +static void hal_ll_uart_set_receiver( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ); + +/** + * @brief Initialize UART module. + * + * Enables UART module clogk gate first. + * Sets pin alternate function state. + * Initializes specific UART module. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_init( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Initialize UART module on the hardware level. + * + * Performs UART module initialization on + * the hardware level. + * + * Procedure: + * 1. Clears control registers + * 2. Sets data bit value + * 3. Sets parity value + * 4. Sets stop bit value + * 5. Sets baud rate value + * 6. Enables transmit pin + * 7. Enables receive pin + * 8. Enables clock gate for specific module + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_hw_init( hal_ll_uart_hw_specifics_map_t *map ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_uart_register_handle( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_uart_handle_register_t *handle_map, uint8_t *hal_module_id ) { + + hal_ll_uart_pin_id index_list[UART_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + uint16_t pin_check_result; + + // Check if pins are valid + if ( (pin_check_result = hal_ll_uart_check_pins( tx_pin, rx_pin, &index_list, handle_map )) == HAL_LL_PIN_NC ) { + return HAL_LL_UART_WRONG_PINS; + }; + + if ( (hal_ll_uart_hw_specifics_map[pin_check_result].pins.tx_pin.pin_name != tx_pin) || + (hal_ll_uart_hw_specifics_map[pin_check_result].pins.rx_pin.pin_name != rx_pin) ) + { + hal_ll_uart_alternate_functions_set_state( &hal_ll_uart_hw_specifics_map[ pin_check_result ], false ); + + hal_ll_uart_map_pins( pin_check_result, &index_list ); + + hal_ll_uart_alternate_functions_set_state( &hal_ll_uart_hw_specifics_map[ pin_check_result ], true ); + + handle_map[pin_check_result].init_ll_state = false; + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[pin_check_result].hal_ll_uart_handle = (handle_t *)&hal_ll_uart_hw_specifics_map[pin_check_result].base; + + handle_map[pin_check_result].hal_ll_uart_handle = (handle_t *)&hal_ll_module_state[pin_check_result].hal_ll_uart_handle; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_uart( handle_t *handle ) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + hal_ll_uart_pin_id index_list[UART_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + uint16_t pin_check_result; + + if ( (pin_check_result = hal_ll_uart_check_pins( hal_ll_uart_hw_specifics_map_local->pins.tx_pin.pin_name, + hal_ll_uart_hw_specifics_map_local->pins.rx_pin.pin_name, &index_list, (void *)0 ) ) == HAL_LL_PIN_NC ) { + return HAL_LL_UART_WRONG_PINS; + }; + + hal_ll_uart_init( hal_ll_uart_hw_specifics_map_local ); + + hal_ll_module_state[pin_check_result].hal_ll_uart_handle = (handle_t *)&hal_ll_uart_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_uart_set_baud( handle_t *handle, uint32_t baud ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->baud_rate.baud = baud; + + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return hal_ll_uart_hw_specifics_map_local->baud_rate.real_baud; +} + +hal_ll_err_t hal_ll_uart_set_parity( handle_t *handle, hal_ll_uart_parity_t parity ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->parity = parity; + + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_uart_set_stop_bits( handle_t *handle, hal_ll_uart_stop_bits_t stop_bit ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->stop_bit = stop_bit; + + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_uart_set_data_bits( handle_t *handle, hal_ll_uart_data_bits_t data_bit ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + // Chips using implementation 1 do not support 7 bit data + if( data_bit == HAL_LL_UART_DATA_BITS_7 ) { + return HAL_LL_UART_MODULE_ERROR; + } + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->data_bit = data_bit; + + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +void hal_ll_uart_close( handle_t *handle ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + if( low_level_handle->hal_ll_uart_handle != NULL ) { + hal_ll_uart_alternate_functions_set_state( hal_ll_uart_hw_specifics_map_local, false ); + + hal_ll_uart_irq_disable(handle, HAL_LL_UART_IRQ_RX); + hal_ll_uart_irq_disable(handle, HAL_LL_UART_IRQ_TX); + + hal_ll_uart_clear_regs(hal_ll_uart_hw_specifics_map_local->base); + hal_ll_uart_set_clock(hal_ll_uart_hw_specifics_map_local, false); + + hal_ll_uart_hw_specifics_map_local->pins.tx_pin.pin_name = HAL_LL_PIN_NC; + hal_ll_uart_hw_specifics_map_local->pins.tx_pin.pin_af = 0; + hal_ll_uart_hw_specifics_map_local->pins.rx_pin.pin_name = HAL_LL_PIN_NC; + hal_ll_uart_hw_specifics_map_local->pins.rx_pin.pin_af = 0; + + hal_ll_uart_hw_specifics_map_local->baud_rate.baud = 115200UL; + hal_ll_uart_hw_specifics_map_local->baud_rate.real_baud = 0; + + irq_handler = NULL; + objects[ hal_ll_uart_find_index( handle ) ] = NULL; + + low_level_handle->hal_ll_uart_handle = NULL; + low_level_handle->hal_drv_uart_handle = NULL; + + low_level_handle->init_ll_state = false; + } +} + +void hal_ll_uart_register_irq_handler( handle_t *handle, hal_ll_uart_isr_t handler, handle_t obj ) +{ + irq_handler = handler; + objects[ hal_ll_uart_find_index( handle ) ] = obj; +} + +void hal_ll_uart_irq_enable( handle_t *handle, hal_ll_uart_irq_t irq ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + switch ( irq ) { + case HAL_LL_UART_IRQ_RX: + __HAL_LL_UART_ENABLE_IT( hal_ll_hw_reg, HAL_LL_UART_IT_RXNE ); + break; + + case HAL_LL_UART_IRQ_TX: + __HAL_LL_UART_ENABLE_IT( hal_ll_hw_reg, HAL_LL_UART_IT_TXE ); + break; + + default: + break; + } + + switch ( hal_ll_uart_hw_specifics_map_local->module_index ) + { + #if defined(UART_MODULE_1) && defined(UART1_NVIC) + case hal_ll_uart_module_num(UART_MODULE_1): + hal_ll_core_enable_irq( UART1_NVIC ); + break; + #endif + + #if defined(UART_MODULE_2) && defined(UART2_NVIC) + case hal_ll_uart_module_num(UART_MODULE_2): + hal_ll_core_enable_irq( UART2_NVIC ); + break; + #endif + + #if defined(UART_MODULE_3) && defined(UART3_NVIC) + case hal_ll_uart_module_num(UART_MODULE_3): + hal_ll_core_enable_irq( UART3_NVIC ); + break; + #endif + + #if defined(UART_MODULE_4) && defined(UART4_NVIC) + case hal_ll_uart_module_num(UART_MODULE_4): + hal_ll_core_enable_irq( UART4_NVIC ); + break; + #endif + + #if defined(UART_MODULE_5) && defined(UART5_NVIC) + case hal_ll_uart_module_num(UART_MODULE_5): + hal_ll_core_enable_irq( UART5_NVIC ); + break; + #endif + + #if defined(UART_MODULE_6) && defined(UART6_NVIC) + case hal_ll_uart_module_num(UART_MODULE_6): + hal_ll_core_enable_irq( UART6_NVIC ); + break; + #endif + + + default: + break; + } +} + +void hal_ll_uart_irq_disable( handle_t *handle, hal_ll_uart_irq_t irq ) +{ + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + switch ( irq ) { + case HAL_LL_UART_IRQ_RX: + __HAL_LL_UART_DISABLE_IT( hal_ll_hw_reg, HAL_LL_UART_IT_RXNE ); + break; + + case HAL_LL_UART_IRQ_TX: + __HAL_LL_UART_DISABLE_IT( hal_ll_hw_reg, HAL_LL_UART_IT_TXE ); + break; + + default: + break; + } + + // Check if module interrupt flags are set or not + if ( ( !check_reg_bit( &hal_ll_hw_reg->cr1, HAL_LL_UART_SR_RXNE ) ) && + ( !check_reg_bit( &hal_ll_hw_reg->cr1, HAL_LL_UART_SR_TXE ) ) ) + { + switch ( hal_ll_uart_hw_specifics_map_local->module_index ) + { + #if defined(UART_MODULE_1) && defined(UART1_NVIC) + case hal_ll_uart_module_num(UART_MODULE_1): + hal_ll_core_disable_irq( UART1_NVIC ); + break; + #endif + + #if defined(UART_MODULE_2) && defined(UART2_NVIC) + case hal_ll_uart_module_num(UART_MODULE_2): + hal_ll_core_disable_irq( UART2_NVIC ); + break; + #endif + + #if defined(UART_MODULE_3) && defined(UART3_NVIC) + case hal_ll_uart_module_num(UART_MODULE_3): + hal_ll_core_disable_irq( UART3_NVIC ); + break; + #endif + + #if defined(UART_MODULE_4) && defined(UART4_NVIC) + case hal_ll_uart_module_num(UART_MODULE_4): + hal_ll_core_disable_irq( UART4_NVIC ); + break; + #endif + + #if defined(UART_MODULE_5) && defined(UART5_NVIC) + case hal_ll_uart_module_num(UART_MODULE_5): + hal_ll_core_disable_irq( UART5_NVIC ); + break; + #endif + + #if defined(UART_MODULE_6) && defined(UART6_NVIC) + case hal_ll_uart_module_num(UART_MODULE_6): + hal_ll_core_disable_irq( UART6_NVIC ); + break; + #endif + + + default: + break; + } + } +} + +void hal_ll_uart_write( handle_t *handle, uint8_t wr_data) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + hal_ll_hw_reg->tdr = wr_data; +} + +uint8_t hal_ll_uart_read( handle_t *handle ) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + return ( hal_ll_hw_reg->rdr ); +} + +// ------------------------------------------------------------- DEFAULT EXCEPTION HANDLERS + +#if defined(USART_MODULE_1) +void MARK_AS_IRQ_HANDLER UART1_IRQHandler() MIKROC_IV(UART1_NVIC) { + #ifdef USART_MODULE_1 + if( hal_ll_uart_get_status_flags( HAL_LL_USART1_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART1_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART1_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_1) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_USART1_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART1_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART1_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_1) ], HAL_LL_UART_IRQ_TX ); + } + } + #endif +} +#endif + +#if defined(USART_MODULE_2) || defined(LPUART_MODULE_2) +void MARK_AS_IRQ_HANDLER UART2_LPUART2_IRQHandler() MIKROC_IV(UART2_NVIC) { + #ifdef USART_MODULE_2 + if( hal_ll_uart_get_status_flags( HAL_LL_USART2_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART2_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART2_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_2) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_USART2_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART2_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART2_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_2) ], HAL_LL_UART_IRQ_TX ); + } + } + #endif + + #ifdef LPUART_MODULE_2 + if( hal_ll_uart_get_status_flags( HAL_LL_LPUART2_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_LPUART2_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_LPUART2_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(LPUART_MODULE_2) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_LPUART2_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_LPUART2_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_LPUART2_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(LPUART_MODULE_2) ], HAL_LL_UART_IRQ_TX ); + } + } + #endif +} +#endif + +#if defined(USART_MODULE_3) || defined(USART_MODULE_4) || defined(USART_MODULE_5) || defined(USART_MODULE_6) || defined(LPUART_MODULE_1) +void MARK_AS_IRQ_HANDLER UART3_4_5_6_LPUART1_IRQHandler() MIKROC_IV(UART3_NVIC) { + #ifdef USART_MODULE_3 + if( hal_ll_uart_get_status_flags( HAL_LL_USART3_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART3_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART3_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_3) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_USART3_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART3_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART3_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_3) ], HAL_LL_UART_IRQ_TX ); + } + } + #endif + + #ifdef USART_MODULE_4 + if( hal_ll_uart_get_status_flags( HAL_LL_USART4_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART4_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART4_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_4) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_USART4_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART4_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART4_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_4) ], HAL_LL_UART_IRQ_TX ); + } + } + #endif + + #ifdef USART_MODULE_5 + if( hal_ll_uart_get_status_flags( HAL_LL_USART5_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART5_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART5_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_5) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_USART5_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART5_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART5_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_5) ], HAL_LL_UART_IRQ_TX ); + } + } + #endif + + #ifdef USART_MODULE_6 + if( hal_ll_uart_get_status_flags( HAL_LL_USART6_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART6_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART6_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_6) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_USART6_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART6_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART6_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_6) ], HAL_LL_UART_IRQ_TX ); + } + } + #endif + + #ifdef LPUART_MODULE_1 + if( hal_ll_uart_get_status_flags( HAL_LL_LPUART1_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_LPUART1_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_LPUART1_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(LPUART_MODULE_1) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_LPUART1_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_LPUART1_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_LPUART1_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(LPUART_MODULE_1) ], HAL_LL_UART_IRQ_TX ); + } + } + #endif +} +#endif + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static uint8_t hal_ll_uart_find_index( handle_t *handle ) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + if( hal_ll_uart_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + return hal_ll_uart_hw_specifics_map_local->module_index; + } else { + return NULL; + } +} + +static hal_ll_pin_name_t hal_ll_uart_check_pins( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_uart_pin_id *index_list, hal_ll_uart_handle_register_t *handle_map ) { + static const uint16_t tx_map_size = ( sizeof( hal_ll_uart_tx_map ) / sizeof( hal_ll_uart_pin_map_t ) ); + static const uint16_t rx_map_size = ( sizeof( hal_ll_uart_rx_map ) / sizeof( hal_ll_uart_pin_map_t ) ); + uint8_t hal_ll_module_id = 0; + uint8_t index_counter = 0; + uint16_t tx_index; + uint16_t rx_index; + + if ( (HAL_LL_PIN_NC == tx_pin) || (HAL_LL_PIN_NC == rx_pin) ) { + return HAL_LL_PIN_NC; + } + + for ( tx_index = 0; tx_index < tx_map_size; tx_index++ ) + { + if ( hal_ll_uart_tx_map[ tx_index ].pin == tx_pin ) + { + for ( rx_index = 0; rx_index < rx_map_size; rx_index++ ) + { + if ( hal_ll_uart_rx_map[ rx_index ].pin == rx_pin ) + { + if ( hal_ll_uart_tx_map[ tx_index ].base == hal_ll_uart_rx_map[ rx_index ].base ) { + // Get module number + hal_ll_module_id = hal_ll_uart_tx_map[ tx_index ].module_index; + + // Map pin names + index_list[hal_ll_module_id].pin_tx = tx_index; + index_list[hal_ll_module_id].pin_rx = rx_index; + + // Check if module is taken + if ( NULL == handle_map[ hal_ll_module_id ].hal_drv_uart_handle ) { + return hal_ll_module_id; + } else if ( UART_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static hal_ll_uart_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof(hal_ll_uart_handle_register_t)); + static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof(hal_ll_uart_handle_register_t)); + + while( hal_ll_module_count-- ) { + if (hal_ll_uart_get_base_from_hal_handle == hal_ll_uart_hw_specifics_map[hal_ll_module_count].base) { + return &hal_ll_uart_hw_specifics_map[hal_ll_module_count]; + } + } + + return &hal_ll_uart_hw_specifics_map[hal_ll_module_error]; +} + +static void hal_ll_uart_set_clock( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ) { + switch ( map->module_index ) + { + #ifdef UART_MODULE_1 + case ( hal_ll_uart_module_num(UART_MODULE_1) ): + (hal_ll_state == true)?(set_reg_bit( _RCC_APBENR2, HAL_LL_USART1EN )):(clear_reg_bit( _RCC_APBENR2, HAL_LL_USART1EN )); + break; + #endif + + #ifdef UART_MODULE_2 + case ( hal_ll_uart_module_num(UART_MODULE_2) ): + (hal_ll_state == true)?(set_reg_bit( _RCC_APBENR1, HAL_LL_USART2EN )):(clear_reg_bit( _RCC_APBENR1, HAL_LL_USART2EN )); + break; + #endif + + #ifdef UART_MODULE_3 + case ( hal_ll_uart_module_num(UART_MODULE_3) ): + (hal_ll_state == true)?(set_reg_bit( _RCC_APBENR1, HAL_LL_USART3EN )):(clear_reg_bit( _RCC_APBENR1, HAL_LL_USART3EN )); + break; + #endif + + #ifdef UART_MODULE_4 + case ( hal_ll_uart_module_num(UART_MODULE_4) ): + (hal_ll_state == true)?(set_reg_bit( _RCC_APBENR1, HAL_LL_USART4EN )):(clear_reg_bit( _RCC_APBENR1, HAL_LL_USART4EN )); + break; + #endif + + #ifdef UART_MODULE_5 + case ( hal_ll_uart_module_num(UART_MODULE_5) ): + (hal_ll_state == true)?(set_reg_bit( _RCC_APBENR1, HAL_LL_USART5EN )):(clear_reg_bit( _RCC_APBENR1, HAL_LL_USART5EN )); + break; + #endif + + #ifdef UART_MODULE_6 + case ( hal_ll_uart_module_num(UART_MODULE_6) ): + (hal_ll_state == true)?(set_reg_bit( _RCC_APBENR1, HAL_LL_USART6EN )):(clear_reg_bit( _RCC_APBENR1, HAL_LL_USART6EN )); + break; + #endif + + + default: + break; + } +} + +static void hal_ll_uart_map_pins( uint8_t module_index, hal_ll_uart_pin_id *index_list ) { + // Map new pins + hal_ll_uart_hw_specifics_map[module_index].pins.tx_pin.pin_name = hal_ll_uart_tx_map[ index_list[module_index].pin_tx ].pin; + hal_ll_uart_hw_specifics_map[module_index].pins.rx_pin.pin_name = hal_ll_uart_rx_map[ index_list[module_index].pin_rx ].pin; + // TX and RX could have different alternate function settings, hence save both AF values + hal_ll_uart_hw_specifics_map[module_index].pins.tx_pin.pin_af = hal_ll_uart_tx_map[ index_list[module_index].pin_tx ].af; + hal_ll_uart_hw_specifics_map[module_index].pins.rx_pin.pin_af = hal_ll_uart_rx_map[ index_list[module_index].pin_rx ].af; +} + +static void hal_ll_uart_alternate_functions_set_state( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ) { + module_struct module; + + if ( (map->pins.tx_pin.pin_name != HAL_LL_PIN_NC) && map->pins.rx_pin.pin_name != HAL_LL_PIN_NC ) { + module.pins[0] = VALUE( map->pins.tx_pin.pin_name, map->pins.tx_pin.pin_af ); + module.pins[1] = VALUE( map->pins.rx_pin.pin_name, map->pins.rx_pin.pin_af ); + module.pins[2] = GPIO_MODULE_STRUCT_END; + + module.configs[0] = HAL_LL_UART_AF_CONFIG; + module.configs[1] = HAL_LL_UART_AF_CONFIG; + module.configs[2] = GPIO_MODULE_STRUCT_END; + + /* STM32F1xx specific */ + module.gpio_remap = map->pins.tx_pin.pin_af; + + hal_ll_gpio_module_struct_init( &module, hal_ll_state ); + } +} + +static void hal_ll_uart_set_baud_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + uint32_t reg = 0; + uint32_t integer_divider = 0; + uint32_t fractional_divider = 0; + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); + uint32_t hal_ll_baud_value = hal_ll_uart_get_baud(hal_ll_uart_get_clock_speed(map->module_index),map->baud_rate.baud,4); + uint32_t hal_ll_baud_real_value = hal_ll_uart_get_real_baud(hal_ll_uart_get_clock_speed(map->module_index),hal_ll_baud_value,4); + + // if error greater than specified, cancel setting baud rate + if( (hal_ll_uart_get_baud_error(hal_ll_baud_real_value,map->baud_rate.baud)) > HAL_LL_UART_ACCEPTABLE_ERROR ) { + map->baud_rate.real_baud = hal_ll_uart_get_baud_error(hal_ll_baud_real_value,map->baud_rate.baud); + } else { + map->baud_rate.real_baud = hal_ll_baud_real_value; + + integer_divider = ( ( 25 * hal_ll_uart_get_clock_speed( map->module_index ) ) / ( 4 * ( map->baud_rate.baud ) ) ); + reg = ( integer_divider / 100 ) << 4; + + fractional_divider = integer_divider - ( 100 * ( reg >> 4 ) ); + reg |= ( ( ( ( fractional_divider * 16 ) + 50 ) / 100 ) ) & 0x0F; + + hal_ll_hw_reg->brr = ( uint16_t )reg; + } +} + +static uint32_t hal_ll_uart_get_clock_speed( hal_ll_pin_name_t module_index ) { + rcc_clocks_t rcc_clocks; + + RCC_GetClocksFrequency( &rcc_clocks ); + + switch ( module_index ) + { + #ifdef UART_MODULE_1 + case ( hal_ll_uart_module_num(UART_MODULE_1) ): + return rcc_clocks.pclk; + break; + #endif + + #ifdef UART_MODULE_2 + case ( hal_ll_uart_module_num(UART_MODULE_2) ): + return rcc_clocks.pclk; + break; + #endif + + #ifdef UART_MODULE_3 + case ( hal_ll_uart_module_num(UART_MODULE_3) ): + return rcc_clocks.pclk; + break; + #endif + + #ifdef UART_MODULE_4 + case ( hal_ll_uart_module_num(UART_MODULE_4) ): + return rcc_clocks.pclk; + break; + #endif + + #ifdef UART_MODULE_5 + case ( hal_ll_uart_module_num(UART_MODULE_5) ): + return rcc_clocks.pclk; + break; + #endif + + #ifdef UART_MODULE_6 + case ( hal_ll_uart_module_num(UART_MODULE_6) ): + return rcc_clocks.pclk; + break; + #endif + + + default: + break; + } + + return NULL; +} + +static void hal_ll_uart_set_stop_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); + + switch ( map->stop_bit ) + { + case HAL_LL_UART_STOP_BITS_HALF: + hal_ll_hw_reg->cr2 |= STOP_BITS_HALF; + break; + case HAL_LL_UART_STOP_BITS_ONE: + hal_ll_hw_reg->cr2 |= STOP_BITS_ONE; + break; + case HAL_LL_UART_STOP_BITS_ONE_AND_A_HALF: + hal_ll_hw_reg->cr2 |= STOP_BITS_ONE_AND_A_HALF; + break; + case HAL_LL_UART_STOP_BITS_TWO: + hal_ll_hw_reg->cr2 |= STOP_BITS_TWO; + break; + + default: + break; + } +} + +static void hal_ll_uart_set_data_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); + + switch ( map->data_bit ) + { + case HAL_LL_UART_DATA_BITS_7: + hal_ll_hw_reg->cr1 |= DATA_BIT_7; + break; + + case HAL_LL_UART_DATA_BITS_8: + hal_ll_hw_reg->cr1 |= DATA_BIT_8; + break; + + case HAL_LL_UART_DATA_BITS_9: + hal_ll_hw_reg->cr1 |= DATA_BIT_9; + break; + + + default: + break; + } +} + +static void hal_ll_uart_set_parity_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); + + switch ( map->parity ) + { + case HAL_LL_UART_PARITY_NONE: + hal_ll_hw_reg->cr1 |= PARITY_NO; + break; + case HAL_LL_UART_PARITY_EVEN: + hal_ll_hw_reg->cr1 |= PARITY_ENABLED | PARITY_EVEN; + break; + case HAL_LL_UART_PARITY_ODD: + hal_ll_hw_reg->cr1 |= PARITY_ENABLED | PARITY_ODD; + break; + + default: + break; + } +} + +static void hal_ll_uart_set_module( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ) { + switch ( pin_state ) + { + case HAL_LL_UART_DISABLE: + clear_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_UE ); + break; + + case HAL_LL_UART_ENABLE: + set_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_UE ); + break; + + default: + break; + } +} + +static void hal_ll_uart_set_transmitter( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ) { + switch ( pin_state ) + { + case HAL_LL_UART_DISABLE: + clear_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_TE ); + break; + + case HAL_LL_UART_ENABLE: + set_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_TE ); + break; + + default: + break; + } +} + +static void hal_ll_uart_set_receiver( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ) { + switch ( pin_state ) + { + case HAL_LL_UART_DISABLE: + clear_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_RE ); + break; + + case HAL_LL_UART_ENABLE: + set_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_RE ); + break; + + default: + break; + } +} + +static void hal_ll_uart_clear_regs( hal_ll_uart_base_handle_t *hal_ll_hw_reg ) { + hal_ll_hw_reg->cr1 &= HAL_LL_UART_IT_CR1_MASK; + hal_ll_hw_reg->cr2 &= HAL_LL_UART_IT_CR2_MASK; + hal_ll_hw_reg->cr3 &= HAL_LL_UART_IT_CR3_MASK; +} + +static void hal_ll_uart_hw_init( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_clear_regs( map->base ); + + hal_ll_uart_set_data_bits_bare_metal( map ); + + hal_ll_uart_set_parity_bare_metal( map ); + + hal_ll_uart_set_stop_bits_bare_metal( map ); + + hal_ll_uart_set_baud_bare_metal( map ); + + hal_ll_uart_set_transmitter( map->base, HAL_LL_UART_ENABLE ); + + hal_ll_uart_set_receiver( map->base, HAL_LL_UART_ENABLE ); + + hal_ll_uart_set_module( map->base, HAL_LL_UART_ENABLE ); +} + +static void hal_ll_uart_init( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_set_clock( map, true ); + + hal_ll_uart_alternate_functions_set_state( map, true ); + + hal_ll_uart_hw_init( map ); +} +// ------------------------------------------------------------------------- END + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_82/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_82/CMakeLists.cmake new file mode 100644 index 000000000..37a2ef8ad --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_82/CMakeLists.cmake @@ -0,0 +1,9 @@ +if(${MCU_NAME} MATCHES "^STM32G431C6$|^STM32G431K6$|^STM32G431R6$|^STM32G431V6$|^STM32G431M6$|^STM32G431C8$|^STM32G431K8$|^STM32G431R8$|^STM32G431V8$|^STM32G431M8$|^STM32G431CB$|^STM32G431KB$|^STM32G431RB$|^STM32G431VB$|^STM32G431MB$") + set(uart_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_uart.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_82") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_82") + list(APPEND hal_ll_def_list "STM32G4xx") + list(APPEND hal_ll_def_list "STM32G43xx") + list(APPEND hal_ll_def_list "STM32G431xx") + set(uart_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/uart/hal_ll_uart_pin_map/implementations/doc_ds_82") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_82/hal_ll_uart.c b/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_82/hal_ll_uart.c new file mode 100644 index 000000000..76ef8c96f --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_82/hal_ll_uart.c @@ -0,0 +1,1168 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_uart.c + * @brief UART HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_rcc.h" +#include "hal_ll_uart.h" +#include "hal_ll_gpio.h" +#include "hal_ll_core.h" +#include "hal_ll_core_defines.h" +#include "hal_ll_uart_pin_map.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_uart_handle_register_t hal_ll_module_state[UART_MODULE_COUNT] = { (handle_t *)NULL, (handle_t *)NULL, false }; + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_uart_get_module_state_address ((hal_ll_uart_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_uart_get_handle (hal_ll_uart_handle_register_t *)hal_ll_uart_get_module_state_address->hal_ll_uart_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_uart_get_base_struct(_handle) ((hal_ll_uart_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_uart_get_base_from_hal_handle ((hal_ll_uart_hw_specifics_map_t *)((hal_ll_uart_handle_register_t *)\ + (((hal_ll_uart_handle_register_t *)(handle))->hal_ll_uart_handle))->hal_ll_uart_handle)->base + +/*!< @brief Macros used for calculating actual baud rate value and error value */ +#define HAL_LL_UART_ACCEPTABLE_ERROR (float)1.0 +#define hal_ll_uart_get_baud(_clock,_baud,_div) (((_clock/(float)_baud)/_div)-1) +#define hal_ll_uart_get_real_baud(_clock,_baud,_div) (_clock/(_div*(_baud+1))) +#define hal_ll_uart_get_baud_error(_baud_real,_baud) (((float)(abs(_baud_real-_baud))/_baud)*100) + +/*!< @brief Macros defining bit location */ +#define HAL_LL_USART1EN 14 +#define HAL_LL_USART2EN 17 +#define HAL_LL_USART3EN 18 +#define HAL_LL_USART4EN 19 + +#define HAL_LL_UART_CR1_UE 0 +#define HAL_LL_UART_CR1_TE 3 +#define HAL_LL_UART_CR1_RE 2 + +#define HAL_LL_UART_SR_RXNE 5 +#define HAL_LL_UART_SR_TXE 7 + +/*!< @brief Macros defining register bit values */ +#define STOP_BITS_HALF 0x1000U +#define STOP_BITS_ONE 0x00U +#define STOP_BITS_ONE_AND_A_HALF 0x3000U +#define STOP_BITS_TWO 0x2000U + +#define DATA_BIT_7 0x10000000U +#define DATA_BIT_8 0x00U +#define DATA_BIT_9 0x1000U + +#define PARITY_NO 0x00U +#define PARITY_ENABLED 0x400U + +#define PARITY_EVEN 0x00U +#define PARITY_ODD 0x200U + +/*!< @brief Macro used for setting pin alternate functions */ +#define HAL_LL_UART_AF_CONFIG (GPIO_CFG_MODE_ALT_FUNCTION | GPIO_CFG_SPEED_HIGH | GPIO_CFG_OTYPE_PP) + +/*!< @brief Macros used for interrupts */ +#define HAL_LL_UART_IT_MASK 0xFFFFUL +#define HAL_LL_UART_IT_CLEAR_MASK 0x123afeU +#define HAL_LL_UART_IT_CR1_MASK 0x1f0U +#define HAL_LL_UART_IT_CR2_MASK 0x40U +#define HAL_LL_UART_IT_CR3_MASK 0x401U + +#define HAL_LL_UART_CR1_REG_INDEX 1 +#define HAL_LL_UART_CR2_REG_INDEX 2 +#define HAL_LL_UART_CR3_REG_INDEX 3 + +#define HAL_LL_UART_IT_PE 0x100U +#define HAL_LL_UART_IT_TXE (0x10000000 | 0x80U) +#define HAL_LL_UART_IT_TC 0x40U +#define HAL_LL_UART_IT_RXNE (0x10000000 | 0x20U) +#define HAL_LL_UART_IT_IDLE 0x10U +#define HAL_LL_UART_IT_LBD 0x40U +#define HAL_LL_UART_IT_CTS 0x400U +#define HAL_LL_UART_IT_ERR 0x01U + +#define HAL_LL_UART_STATUS_RXNE_FLAG 0x20U +#define HAL_LL_UART_STATUS_TXE_FLAG 0x80U + +/*!< @brief Macro used for status registed flag check + * Used in interrupt handlers. + */ +#define hal_ll_uart_get_status_flags(_handle,_flag) (((hal_ll_uart_base_handle_t *)_handle)->isr & _flag) + +/*!< @brief Macro used for status register flag clearing + * Used in interrupt handlers. + */ +#define hal_ll_uart_clear_status_flag(_handle,_flag) (set_reg_bit( &(((hal_ll_uart_base_handle_t *)_handle)->icr), ( _flag & HAL_LL_UART_IT_CLEAR_MASK ) ) ) + +/*!< @brief Macro used for module interrupt enabling. + * Used in interrupt handlers. + */ +#define __HAL_LL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__ >> 28UL) == HAL_LL_UART_CR1_REG_INDEX)? (__HANDLE__->cr1 |= (__INTERRUPT__ & HAL_LL_UART_IT_MASK)): \ + ((__INTERRUPT__ >> 28UL) == HAL_LL_UART_CR2_REG_INDEX)? (__HANDLE__->cr2 |= (__INTERRUPT__ & HAL_LL_UART_IT_MASK)): \ + (__HANDLE__->cr3 |= (__INTERRUPT__ & HAL_LL_UART_IT_MASK))) + +/*!< @brief Macro used for module interrupt disabling. + * Used in interrupt handlers. + */ +#define __HAL_LL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__ >> 28UL) == HAL_LL_UART_CR1_REG_INDEX)? (__HANDLE__->cr1 &= ~(__INTERRUPT__ & HAL_LL_UART_IT_MASK)): \ + ((__INTERRUPT__ >> 28UL) == HAL_LL_UART_CR2_REG_INDEX)? (__HANDLE__->cr2 &= ~(__INTERRUPT__ & HAL_LL_UART_IT_MASK)): \ + (__HANDLE__->cr3 &= ~ (__INTERRUPT__ & HAL_LL_UART_IT_MASK))) + +/*!< @brief Macro used for module interrupt source check. + * Used in interrupt handlers. + */ +#define __HAL_LL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__ >> 28UL) == 1UL)? ((hal_ll_uart_base_handle_t *)__HANDLE__)->cr1:((((uint32_t)__INTERRUPT__ >> 28UL) == 2UL)? \ + ((hal_ll_uart_base_handle_t *)__HANDLE__)->cr2 : ((hal_ll_uart_base_handle_t *)__HANDLE__)->cr3)) & ((uint32_t)__INTERRUPT__ & HAL_LL_UART_IT_MASK)) + +/*!< @brief UART HW register structure */ +typedef struct +{ + hal_ll_base_addr_t cr1; + hal_ll_base_addr_t cr2; + hal_ll_base_addr_t cr3; + hal_ll_base_addr_t brr; + hal_ll_base_addr_t gtpr; + hal_ll_base_addr_t rtor; + hal_ll_base_addr_t rqr; + hal_ll_base_addr_t isr; + hal_ll_base_addr_t icr; + hal_ll_base_addr_t rdr; + hal_ll_base_addr_t tdr; + hal_ll_base_addr_t presc; +} hal_ll_uart_base_handle_t; + +/*!< @brief UART baud rate structure */ +typedef struct +{ + uint32_t baud; + uint32_t real_baud; +} hal_ll_uart_baud_t; + +/*!< @brief UART hw specific structure */ +typedef struct +{ + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + hal_ll_uart_pins_t pins; + hal_ll_uart_baud_t baud_rate; + hal_ll_uart_parity_t parity; + hal_ll_uart_stop_bits_t stop_bit; + hal_ll_uart_data_bits_t data_bit; +} hal_ll_uart_hw_specifics_map_t; + +/*!< @brief UART hw specific module values */ +typedef struct +{ + uint16_t pin_tx; + uint16_t pin_rx; +} hal_ll_uart_pin_id; + +/*!< @brief UART hw specific error values */ +typedef enum +{ + HAL_LL_UART_SUCCESS = 0, + HAL_LL_UART_WRONG_PINS, + HAL_LL_UART_MODULE_ERROR, + + HAL_LL_UART_ERROR = (-1) +} hal_ll_uart_err_t; + +/*!< @brief UART module state selection */ +typedef enum +{ + HAL_LL_UART_DISABLE = 0, + HAL_LL_UART_ENABLE +} hal_ll_uart_state_t; + +// ------------------------------------------------------------------ VARIABLES +/*!< @brief UART hardware specific info */ +static hal_ll_uart_hw_specifics_map_t hal_ll_uart_hw_specifics_map[] = +{ + #ifdef UART_MODULE_1 + {HAL_LL_UART1_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_1), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + #ifdef UART_MODULE_2 + {HAL_LL_UART2_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_2), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + #ifdef UART_MODULE_3 + {HAL_LL_UART3_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_3), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + #ifdef UART_MODULE_4 + {HAL_LL_UART4_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_4), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {0, 0}, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR} +}; + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_uart_handle_register_t *low_level_handle; +static volatile hal_ll_uart_hw_specifics_map_t *hal_ll_uart_hw_specifics_map_local; + +/*!< @brief Global interrupt handlers used in functions */ +static hal_ll_uart_isr_t irq_handler; +static handle_t objects[UART_MODULE_COUNT]; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Check if pins are adequate. + * + * Checks tx and rx pins the user has passed with pre-defined + * pins in tx and rx maps. Take into consideration that module + * index numbers have to be the same for both pins. + * + * @param[in] tx_pin - TX pre-defined pin name. + * @param[in] rx_pin - RX pre-defined pin name. + * @param[in] *index_list - Array containing map index numbers. + * @return hal_ll_pin_name_t Module index based on pins. + * + * Returns pre-defined module index from pin maps, if pins + * are adequate. + */ +static hal_ll_pin_name_t hal_ll_uart_check_pins( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_uart_pin_id *index_list, hal_ll_uart_handle_register_t *handle_map ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * TX and RX pins. + * + * @param[in] module_index UART HW module index -- 0,1,2... + * @param[in] *index_list Array with TX and RX map index values + * and module number + * + * @return None + */ +static void hal_ll_uart_map_pins( uint8_t module_index, hal_ll_uart_pin_id *index_list ); + +/** + * @brief Sets UART pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if UART is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_state - Init/De-init + * + * @return void None. + */ +static void hal_ll_uart_alternate_functions_set_state( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_uart_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_uart_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_uart_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Enable clock for UART module on hardware level. + * + * Initializes UART module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_stat - True(enable clock)/False(disable clock). + * + * @return void None. + */ +static void hal_ll_uart_set_clock( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Finds UART module index. + * + * Finds UART index(module number) based on + * handle value. + * + * @param[in] handle - Object specific context handler. + * + * @return uint8_t Module number. + * Returns values from 0 to 9. + */ +static uint8_t hal_ll_uart_find_index( handle_t *handle ); + +/** + * @brief Get UART module clock speed. + * + * Returns adequate clock speed based on + * UART module base address. + * + * @param[in] module_index - UART module index number. + * + * @return uint8_t Module number. + * Returns clock value. + */ +static uint32_t hal_ll_uart_get_clock_speed( hal_ll_pin_name_t module_index ); + +/** + * @brief Clears UART registers. + * + * Clears UART module configuration + * registers, effectively disabling the module itself. + * Take into consideration that any IRQ bits + * are not cleared. + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * + * @return void None. + */ +static void hal_ll_uart_clear_regs( hal_ll_uart_base_handle_t *hal_ll_hw_reg ); + +/** + * @brief Sets desired baud rate on hardware level. + * + * Initializes module with specified baud rate value. + * Take into consideration that if the difference + * between desired baud rate and actual baud + * rate the hw was initialized to is greater than + * 1%, baud rate shall not be set. + * If this occurs, return value shall be + * the error percentage. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_set_baud_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Sets desired stop bits. + * + * Initializes module on hardware level + * with specified stop bit value. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_set_stop_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Sets desired data bits. + * + * Initializes module on hardware level + * with specified data bit bit value. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_set_data_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Sets desired parity. + * + * Initializes module on hardware level + * with specified parity value. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_set_parity_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Sets module clock value. + * + * Enables/disables specific UART module + * clock gate. + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * @param[in] pin_state - true(enable clock) / false(disable clock) + * + * @return void None. + */ +static void hal_ll_uart_set_module( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ); + +/** + * @brief Sets module TX line state. + * + * Enables/disables specific UART module + * TX pin state + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * @param[in] pin_state - true(enable transmitter pin) / false(disable transmitter pin) + * + * @return void None. + */ +static void hal_ll_uart_set_transmitter( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ); + +/** + * @brief Sets module RX line state. + * + * Enables/disables specific UART module + * RX pin state + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * @param[in] pin_state - true(enable receive pin) / false(disable receive pin) + * + * @return void None. + */ +static void hal_ll_uart_set_receiver( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ); + +/** + * @brief Initialize UART module. + * + * Enables UART module clogk gate first. + * Sets pin alternate function state. + * Initializes specific UART module. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_init( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Initialize UART module on the hardware level. + * + * Performs UART module initialization on + * the hardware level. + * + * Procedure: + * 1. Clears control registers + * 2. Sets data bit value + * 3. Sets parity value + * 4. Sets stop bit value + * 5. Sets baud rate value + * 6. Enables transmit pin + * 7. Enables receive pin + * 8. Enables clock gate for specific module + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_hw_init( hal_ll_uart_hw_specifics_map_t *map ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_uart_register_handle( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_uart_handle_register_t *handle_map, uint8_t *hal_module_id ) { + + hal_ll_uart_pin_id index_list[UART_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + uint16_t pin_check_result; + + // Check if pins are valid + if ( (pin_check_result = hal_ll_uart_check_pins( tx_pin, rx_pin, &index_list, handle_map )) == HAL_LL_PIN_NC ) { + return HAL_LL_UART_WRONG_PINS; + }; + + if ( (hal_ll_uart_hw_specifics_map[pin_check_result].pins.tx_pin.pin_name != tx_pin) || + (hal_ll_uart_hw_specifics_map[pin_check_result].pins.rx_pin.pin_name != rx_pin) ) + { + hal_ll_uart_alternate_functions_set_state( &hal_ll_uart_hw_specifics_map[ pin_check_result ], false ); + + hal_ll_uart_map_pins( pin_check_result, &index_list ); + + hal_ll_uart_alternate_functions_set_state( &hal_ll_uart_hw_specifics_map[ pin_check_result ], true ); + + handle_map[pin_check_result].init_ll_state = false; + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[pin_check_result].hal_ll_uart_handle = (handle_t *)&hal_ll_uart_hw_specifics_map[pin_check_result].base; + + handle_map[pin_check_result].hal_ll_uart_handle = (handle_t *)&hal_ll_module_state[pin_check_result].hal_ll_uart_handle; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_uart( handle_t *handle ) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + hal_ll_uart_pin_id index_list[UART_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + uint16_t pin_check_result; + + if ( (pin_check_result = hal_ll_uart_check_pins( hal_ll_uart_hw_specifics_map_local->pins.tx_pin.pin_name, + hal_ll_uart_hw_specifics_map_local->pins.rx_pin.pin_name, &index_list, (void *)0 ) ) == HAL_LL_PIN_NC ) { + return HAL_LL_UART_WRONG_PINS; + }; + + hal_ll_uart_init( hal_ll_uart_hw_specifics_map_local ); + + hal_ll_module_state[pin_check_result].hal_ll_uart_handle = (handle_t *)&hal_ll_uart_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_uart_set_baud( handle_t *handle, uint32_t baud ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->baud_rate.baud = baud; + + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return hal_ll_uart_hw_specifics_map_local->baud_rate.real_baud; +} + +hal_ll_err_t hal_ll_uart_set_parity( handle_t *handle, hal_ll_uart_parity_t parity ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->parity = parity; + + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_uart_set_stop_bits( handle_t *handle, hal_ll_uart_stop_bits_t stop_bit ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->stop_bit = stop_bit; + + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_uart_set_data_bits( handle_t *handle, hal_ll_uart_data_bits_t data_bit ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + // Chips using implementation 1 do not support 7 bit data + if( data_bit == HAL_LL_UART_DATA_BITS_7 ) { + return HAL_LL_UART_MODULE_ERROR; + } + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->data_bit = data_bit; + + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +void hal_ll_uart_close( handle_t *handle ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + if( low_level_handle->hal_ll_uart_handle != NULL ) { + hal_ll_uart_alternate_functions_set_state( hal_ll_uart_hw_specifics_map_local, false ); + + hal_ll_uart_irq_disable(handle, HAL_LL_UART_IRQ_RX); + hal_ll_uart_irq_disable(handle, HAL_LL_UART_IRQ_TX); + + hal_ll_uart_clear_regs(hal_ll_uart_hw_specifics_map_local->base); + hal_ll_uart_set_clock(hal_ll_uart_hw_specifics_map_local, false); + + hal_ll_uart_hw_specifics_map_local->pins.tx_pin.pin_name = HAL_LL_PIN_NC; + hal_ll_uart_hw_specifics_map_local->pins.tx_pin.pin_af = 0; + hal_ll_uart_hw_specifics_map_local->pins.rx_pin.pin_name = HAL_LL_PIN_NC; + hal_ll_uart_hw_specifics_map_local->pins.rx_pin.pin_af = 0; + + hal_ll_uart_hw_specifics_map_local->baud_rate.baud = 115200UL; + hal_ll_uart_hw_specifics_map_local->baud_rate.real_baud = 0; + + irq_handler = NULL; + objects[ hal_ll_uart_find_index( handle ) ] = NULL; + + low_level_handle->hal_ll_uart_handle = NULL; + low_level_handle->hal_drv_uart_handle = NULL; + + low_level_handle->init_ll_state = false; + } +} + +void hal_ll_uart_register_irq_handler( handle_t *handle, hal_ll_uart_isr_t handler, handle_t obj ) +{ + irq_handler = handler; + objects[ hal_ll_uart_find_index( handle ) ] = obj; +} + +void hal_ll_uart_irq_enable( handle_t *handle, hal_ll_uart_irq_t irq ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + switch ( irq ) { + case HAL_LL_UART_IRQ_RX: + __HAL_LL_UART_ENABLE_IT( hal_ll_hw_reg, HAL_LL_UART_IT_RXNE ); + break; + + case HAL_LL_UART_IRQ_TX: + __HAL_LL_UART_ENABLE_IT( hal_ll_hw_reg, HAL_LL_UART_IT_TXE ); + break; + + default: + break; + } + + switch ( hal_ll_uart_hw_specifics_map_local->module_index ) + { + #if defined(UART_MODULE_1) && defined(UART1_NVIC) + case hal_ll_uart_module_num(UART_MODULE_1): + hal_ll_core_enable_irq( UART1_NVIC ); + break; + #endif + + #if defined(UART_MODULE_2) && defined(UART2_NVIC) + case hal_ll_uart_module_num(UART_MODULE_2): + hal_ll_core_enable_irq( UART2_NVIC ); + break; + #endif + + #if defined(UART_MODULE_3) && defined(UART3_NVIC) + case hal_ll_uart_module_num(UART_MODULE_3): + hal_ll_core_enable_irq( UART3_NVIC ); + break; + #endif + + #if defined(UART_MODULE_4) && defined(UART4_NVIC) + case hal_ll_uart_module_num(UART_MODULE_4): + hal_ll_core_enable_irq( UART4_NVIC ); + break; + #endif + + + default: + break; + } +} + +void hal_ll_uart_irq_disable( handle_t *handle, hal_ll_uart_irq_t irq ) +{ + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + switch ( irq ) { + case HAL_LL_UART_IRQ_RX: + __HAL_LL_UART_DISABLE_IT( hal_ll_hw_reg, HAL_LL_UART_IT_RXNE ); + break; + + case HAL_LL_UART_IRQ_TX: + __HAL_LL_UART_DISABLE_IT( hal_ll_hw_reg, HAL_LL_UART_IT_TXE ); + break; + + default: + break; + } + + // Check if module interrupt flags are set or not + if ( ( !check_reg_bit( &hal_ll_hw_reg->cr1, HAL_LL_UART_SR_RXNE ) ) && + ( !check_reg_bit( &hal_ll_hw_reg->cr1, HAL_LL_UART_SR_TXE ) ) ) + { + switch ( hal_ll_uart_hw_specifics_map_local->module_index ) + { + #if defined(UART_MODULE_1) && defined(UART1_NVIC) + case hal_ll_uart_module_num(UART_MODULE_1): + hal_ll_core_disable_irq( UART1_NVIC ); + break; + #endif + + #if defined(UART_MODULE_2) && defined(UART2_NVIC) + case hal_ll_uart_module_num(UART_MODULE_2): + hal_ll_core_disable_irq( UART2_NVIC ); + break; + #endif + + #if defined(UART_MODULE_3) && defined(UART3_NVIC) + case hal_ll_uart_module_num(UART_MODULE_3): + hal_ll_core_disable_irq( UART3_NVIC ); + break; + #endif + + #if defined(UART_MODULE_4) && defined(UART4_NVIC) + case hal_ll_uart_module_num(UART_MODULE_4): + hal_ll_core_disable_irq( UART4_NVIC ); + break; + #endif + + + default: + break; + } + } +} + +void hal_ll_uart_write( handle_t *handle, uint8_t wr_data) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + hal_ll_hw_reg->tdr = wr_data; +} + +uint8_t hal_ll_uart_read( handle_t *handle ) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + return ( hal_ll_hw_reg->rdr ); +} + +// ------------------------------------------------------------- DEFAULT EXCEPTION HANDLERS +#if defined(UART_MODULE_1) && defined(UART1_NVIC) +void MARK_AS_IRQ_HANDLER UART1_IRQHandler() MIKROC_IV(UART1_NVIC) { + if( hal_ll_uart_get_status_flags( HAL_LL_UART1_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_UART1_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_UART1_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(UART_MODULE_1) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_UART1_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_UART1_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_UART1_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(UART_MODULE_1) ], HAL_LL_UART_IRQ_TX ); + } + } +} +#endif + +#if defined(UART_MODULE_2) && defined(UART2_NVIC) +void MARK_AS_IRQ_HANDLER UART2_IRQHandler() MIKROC_IV(UART2_NVIC) { + if( hal_ll_uart_get_status_flags( HAL_LL_UART2_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_UART2_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_UART2_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(UART_MODULE_2) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_UART2_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_UART2_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_UART2_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(UART_MODULE_2) ], HAL_LL_UART_IRQ_TX ); + } + } +} +#endif + +#if defined(UART_MODULE_3) && defined(UART3_NVIC) +void MARK_AS_IRQ_HANDLER UART3_IRQHandler() MIKROC_IV(UART3_NVIC) { + if( hal_ll_uart_get_status_flags( HAL_LL_UART3_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_UART3_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_UART3_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(UART_MODULE_3) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_UART3_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_UART3_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_UART3_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(UART_MODULE_3) ], HAL_LL_UART_IRQ_TX ); + } + } +} +#endif + +#if defined(UART_MODULE_4) && defined(UART4_NVIC) +void MARK_AS_IRQ_HANDLER UART4_IRQHandler() MIKROC_IV(UART4_NVIC) { + if( hal_ll_uart_get_status_flags( HAL_LL_UART4_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_UART4_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_UART4_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(UART_MODULE_4) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_UART4_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_UART4_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_UART4_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(UART_MODULE_4) ], HAL_LL_UART_IRQ_TX ); + } + } +} +#endif + + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static uint8_t hal_ll_uart_find_index( handle_t *handle ) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + if( hal_ll_uart_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + return hal_ll_uart_hw_specifics_map_local->module_index; + } else { + return NULL; + } +} + +static hal_ll_pin_name_t hal_ll_uart_check_pins( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_uart_pin_id *index_list, hal_ll_uart_handle_register_t *handle_map ) { + static const uint16_t tx_map_size = ( sizeof( hal_ll_uart_tx_map ) / sizeof( hal_ll_uart_pin_map_t ) ); + static const uint16_t rx_map_size = ( sizeof( hal_ll_uart_rx_map ) / sizeof( hal_ll_uart_pin_map_t ) ); + uint8_t hal_ll_module_id = 0; + uint8_t index_counter = 0; + uint16_t tx_index; + uint16_t rx_index; + + if ( (HAL_LL_PIN_NC == tx_pin) || (HAL_LL_PIN_NC == rx_pin) ) { + return HAL_LL_PIN_NC; + } + + for ( tx_index = 0; tx_index < tx_map_size; tx_index++ ) + { + if ( hal_ll_uart_tx_map[ tx_index ].pin == tx_pin ) + { + for ( rx_index = 0; rx_index < rx_map_size; rx_index++ ) + { + if ( hal_ll_uart_rx_map[ rx_index ].pin == rx_pin ) + { + if ( hal_ll_uart_tx_map[ tx_index ].base == hal_ll_uart_rx_map[ rx_index ].base ) { + // Get module number + hal_ll_module_id = hal_ll_uart_tx_map[ tx_index ].module_index; + + // Map pin names + index_list[hal_ll_module_id].pin_tx = tx_index; + index_list[hal_ll_module_id].pin_rx = rx_index; + + // Check if module is taken + if ( NULL == handle_map[ hal_ll_module_id ].hal_drv_uart_handle ) { + return hal_ll_module_id; + } else if ( UART_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static hal_ll_uart_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof(hal_ll_uart_handle_register_t)); + static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof(hal_ll_uart_handle_register_t)); + + while( hal_ll_module_count-- ) { + if (hal_ll_uart_get_base_from_hal_handle == hal_ll_uart_hw_specifics_map[hal_ll_module_count].base) { + return &hal_ll_uart_hw_specifics_map[hal_ll_module_count]; + } + } + + return &hal_ll_uart_hw_specifics_map[hal_ll_module_error]; +} + +static void hal_ll_uart_set_clock( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ) { + switch ( map->module_index ) + { + #ifdef UART_MODULE_1 + case ( hal_ll_uart_module_num(UART_MODULE_1) ): + (hal_ll_state == true)?(set_reg_bit( _RCC_APB2ENR, HAL_LL_USART1EN )):(clear_reg_bit( _RCC_APB2ENR, HAL_LL_USART1EN )); + break; + #endif + + #ifdef UART_MODULE_2 + case ( hal_ll_uart_module_num(UART_MODULE_2) ): + (hal_ll_state == true)?(set_reg_bit( _RCC_APB1ENR1, HAL_LL_USART2EN )):(clear_reg_bit( _RCC_APB1ENR1, HAL_LL_USART2EN )); + break; + #endif + + #ifdef UART_MODULE_3 + case ( hal_ll_uart_module_num(UART_MODULE_3) ): + (hal_ll_state == true)?(set_reg_bit( _RCC_APB1ENR1, HAL_LL_USART3EN )):(clear_reg_bit( _RCC_APB1ENR1, HAL_LL_USART3EN )); + break; + #endif + + #ifdef UART_MODULE_4 + case ( hal_ll_uart_module_num(UART_MODULE_4) ): + (hal_ll_state == true)?(set_reg_bit( _RCC_APB1ENR1, HAL_LL_USART4EN )):(clear_reg_bit( _RCC_APB1ENR1, HAL_LL_USART4EN )); + break; + #endif + + + default: + break; + } +} + +static void hal_ll_uart_map_pins( uint8_t module_index, hal_ll_uart_pin_id *index_list ) { + // Map new pins + hal_ll_uart_hw_specifics_map[module_index].pins.tx_pin.pin_name = hal_ll_uart_tx_map[ index_list[module_index].pin_tx ].pin; + hal_ll_uart_hw_specifics_map[module_index].pins.rx_pin.pin_name = hal_ll_uart_rx_map[ index_list[module_index].pin_rx ].pin; + // TX and RX could have different alternate function settings, hence save both AF values + hal_ll_uart_hw_specifics_map[module_index].pins.tx_pin.pin_af = hal_ll_uart_tx_map[ index_list[module_index].pin_tx ].af; + hal_ll_uart_hw_specifics_map[module_index].pins.rx_pin.pin_af = hal_ll_uart_rx_map[ index_list[module_index].pin_rx ].af; +} + +static void hal_ll_uart_alternate_functions_set_state( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ) { + module_struct module; + + if ( (map->pins.tx_pin.pin_name != HAL_LL_PIN_NC) && map->pins.rx_pin.pin_name != HAL_LL_PIN_NC ) { + module.pins[0] = VALUE( map->pins.tx_pin.pin_name, map->pins.tx_pin.pin_af ); + module.pins[1] = VALUE( map->pins.rx_pin.pin_name, map->pins.rx_pin.pin_af ); + module.pins[2] = GPIO_MODULE_STRUCT_END; + + module.configs[0] = HAL_LL_UART_AF_CONFIG; + module.configs[1] = HAL_LL_UART_AF_CONFIG; + module.configs[2] = GPIO_MODULE_STRUCT_END; + + /* STM32F1xx specific */ + module.gpio_remap = map->pins.tx_pin.pin_af; + + hal_ll_gpio_module_struct_init( &module, hal_ll_state ); + } +} + +static void hal_ll_uart_set_baud_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + uint32_t reg = 0; + uint32_t integer_divider = 0; + uint32_t fractional_divider = 0; + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); + uint32_t hal_ll_baud_value = hal_ll_uart_get_baud(hal_ll_uart_get_clock_speed(map->module_index),map->baud_rate.baud,4); + uint32_t hal_ll_baud_real_value = hal_ll_uart_get_real_baud(hal_ll_uart_get_clock_speed(map->module_index),hal_ll_baud_value,4); + + // if error greater than specified, cancel setting baud rate + if( (hal_ll_uart_get_baud_error(hal_ll_baud_real_value,map->baud_rate.baud)) > HAL_LL_UART_ACCEPTABLE_ERROR ) { + map->baud_rate.real_baud = hal_ll_uart_get_baud_error(hal_ll_baud_real_value,map->baud_rate.baud); + } else { + map->baud_rate.real_baud = hal_ll_baud_real_value; + + integer_divider = ( ( 25 * hal_ll_uart_get_clock_speed( map->module_index ) ) / ( 4 * ( map->baud_rate.baud ) ) ); + reg = ( integer_divider / 100 ) << 4; + + fractional_divider = integer_divider - ( 100 * ( reg >> 4 ) ); + reg |= ( ( ( ( fractional_divider * 16 ) + 50 ) / 100 ) ) & 0x0F; + + hal_ll_hw_reg->brr = ( uint16_t )reg; + } +} + +static uint32_t hal_ll_uart_get_clock_speed( hal_ll_pin_name_t module_index ) { + rcc_clocks_t rcc_clocks; + + RCC_GetClocksFrequency( &rcc_clocks ); + + switch ( module_index ) + { + #ifdef UART_MODULE_1 + case ( hal_ll_uart_module_num(UART_MODULE_1) ): + return rcc_clocks.pclk2; + break; + #endif + + #ifdef UART_MODULE_2 + case ( hal_ll_uart_module_num(UART_MODULE_2) ): + return rcc_clocks.pclk1; + break; + #endif + + #ifdef UART_MODULE_3 + case ( hal_ll_uart_module_num(UART_MODULE_3) ): + return rcc_clocks.pclk1; + break; + #endif + + #ifdef UART_MODULE_4 + case ( hal_ll_uart_module_num(UART_MODULE_4) ): + return rcc_clocks.pclk1; + break; + #endif + + + default: + break; + } + + return NULL; +} + +static void hal_ll_uart_set_stop_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); + + switch ( map->stop_bit ) + { + case HAL_LL_UART_STOP_BITS_HALF: + hal_ll_hw_reg->cr2 |= STOP_BITS_HALF; + break; + case HAL_LL_UART_STOP_BITS_ONE: + hal_ll_hw_reg->cr2 |= STOP_BITS_ONE; + break; + case HAL_LL_UART_STOP_BITS_ONE_AND_A_HALF: + hal_ll_hw_reg->cr2 |= STOP_BITS_ONE_AND_A_HALF; + break; + case HAL_LL_UART_STOP_BITS_TWO: + hal_ll_hw_reg->cr2 |= STOP_BITS_TWO; + break; + + default: + break; + } +} + +static void hal_ll_uart_set_data_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); + + switch ( map->data_bit ) + { + case HAL_LL_UART_DATA_BITS_7: + hal_ll_hw_reg->cr1 |= DATA_BIT_7; + break; + + case HAL_LL_UART_DATA_BITS_8: + hal_ll_hw_reg->cr1 |= DATA_BIT_8; + break; + + case HAL_LL_UART_DATA_BITS_9: + hal_ll_hw_reg->cr1 |= DATA_BIT_9; + break; + + + default: + break; + } +} + +static void hal_ll_uart_set_parity_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); + + switch ( map->parity ) + { + case HAL_LL_UART_PARITY_NONE: + hal_ll_hw_reg->cr1 |= PARITY_NO; + break; + case HAL_LL_UART_PARITY_EVEN: + hal_ll_hw_reg->cr1 |= PARITY_ENABLED | PARITY_EVEN; + break; + case HAL_LL_UART_PARITY_ODD: + hal_ll_hw_reg->cr1 |= PARITY_ENABLED | PARITY_ODD; + break; + + default: + break; + } +} + +static void hal_ll_uart_set_module( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ) { + switch ( pin_state ) + { + case HAL_LL_UART_DISABLE: + clear_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_UE ); + break; + + case HAL_LL_UART_ENABLE: + set_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_UE ); + break; + + default: + break; + } +} + +static void hal_ll_uart_set_transmitter( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ) { + switch ( pin_state ) + { + case HAL_LL_UART_DISABLE: + clear_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_TE ); + break; + + case HAL_LL_UART_ENABLE: + set_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_TE ); + break; + + default: + break; + } +} + +static void hal_ll_uart_set_receiver( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ) { + switch ( pin_state ) + { + case HAL_LL_UART_DISABLE: + clear_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_RE ); + break; + + case HAL_LL_UART_ENABLE: + set_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_RE ); + break; + + default: + break; + } +} + +static void hal_ll_uart_clear_regs( hal_ll_uart_base_handle_t *hal_ll_hw_reg ) { + hal_ll_hw_reg->cr1 &= HAL_LL_UART_IT_CR1_MASK; + hal_ll_hw_reg->cr2 &= HAL_LL_UART_IT_CR2_MASK; + hal_ll_hw_reg->cr3 &= HAL_LL_UART_IT_CR3_MASK; +} + +static void hal_ll_uart_hw_init( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_clear_regs( map->base ); + + hal_ll_uart_set_data_bits_bare_metal( map ); + + hal_ll_uart_set_parity_bare_metal( map ); + + hal_ll_uart_set_stop_bits_bare_metal( map ); + + hal_ll_uart_set_baud_bare_metal( map ); + + hal_ll_uart_set_transmitter( map->base, HAL_LL_UART_ENABLE ); + + hal_ll_uart_set_receiver( map->base, HAL_LL_UART_ENABLE ); + + hal_ll_uart_set_module( map->base, HAL_LL_UART_ENABLE ); +} + +static void hal_ll_uart_init( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_set_clock( map, true ); + + hal_ll_uart_alternate_functions_set_state( map, true ); + + hal_ll_uart_hw_init( map ); +} +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_83/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_83/CMakeLists.cmake new file mode 100644 index 000000000..aae4f9122 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_83/CMakeLists.cmake @@ -0,0 +1,9 @@ +if(${MCU_NAME} MATCHES "^STM32G441CB$|^STM32G441KB$|^STM32G441RB$|^STM32G441MB$|^STM32G441VB$") + set(uart_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_uart.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_83") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_83") + list(APPEND hal_ll_def_list "STM32G4xx") + list(APPEND hal_ll_def_list "STM32G44xx") + list(APPEND hal_ll_def_list "STM32G441xx") + set(uart_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/uart/hal_ll_uart_pin_map/implementations/doc_ds_83") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_83/hal_ll_uart.c b/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_83/hal_ll_uart.c new file mode 100644 index 000000000..256031e90 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_83/hal_ll_uart.c @@ -0,0 +1,1206 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_uart.c + * @brief UART HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_rcc.h" +#include "hal_ll_uart.h" +#include "hal_ll_gpio.h" +#include "hal_ll_core.h" +#include "hal_ll_core_defines.h" +#include "hal_ll_uart_pin_map.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_uart_handle_register_t hal_ll_module_state[UART_MODULE_COUNT] = { (handle_t *)NULL, (handle_t *)NULL, false }; + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_uart_get_module_state_address ((hal_ll_uart_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_uart_get_handle (hal_ll_uart_handle_register_t *)hal_ll_uart_get_module_state_address->hal_ll_uart_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_uart_get_base_struct(_handle) ((hal_ll_uart_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_uart_get_base_from_hal_handle ((hal_ll_uart_hw_specifics_map_t *)((hal_ll_uart_handle_register_t *)\ + (((hal_ll_uart_handle_register_t *)(handle))->hal_ll_uart_handle))->hal_ll_uart_handle)->base + +/*!< @brief Macros used for calculating actual baud rate value and error value */ +#define HAL_LL_UART_ACCEPTABLE_ERROR (float)1.0 +#define hal_ll_uart_get_baud(_clock,_baud,_div) (((_clock/(float)_baud)/_div)-1) +#define hal_ll_uart_get_real_baud(_clock,_baud,_div) (_clock/(_div*(_baud+1))) +#define hal_ll_uart_get_baud_error(_baud_real,_baud) (((float)(abs(_baud_real-_baud))/_baud)*100) + +/*!< @brief Macros defining bit location */ +#define HAL_LL_USART1EN 14 + +#define HAL_LL_USART2EN 17 + +#define HAL_LL_USART3EN 18 + +#define HAL_LL_USART4EN 19 + + +#define HAL_LL_UART_CR1_UE 0 +#define HAL_LL_UART_CR1_TE 3 +#define HAL_LL_UART_CR1_RE 2 + +#define HAL_LL_UART_SR_RXNE 5 +#define HAL_LL_UART_SR_TXE 7 + +/*!< @brief Macros defining register bit values */ +#define STOP_BITS_HALF 0x1000U +#define STOP_BITS_ONE 0x00U +#define STOP_BITS_ONE_AND_A_HALF 0x3000U +#define STOP_BITS_TWO 0x2000U + +#define DATA_BIT_7 0x10000000U +#define DATA_BIT_8 0x00U +#define DATA_BIT_9 0x1000U + +#define PARITY_NO 0x00U +#define PARITY_ENABLED 0x400U + +#define PARITY_EVEN 0x00U +#define PARITY_ODD 0x200U + +/*!< @brief Macro used for setting pin alternate functions */ +#define HAL_LL_UART_AF_CONFIG (GPIO_CFG_MODE_ALT_FUNCTION | GPIO_CFG_SPEED_HIGH | GPIO_CFG_OTYPE_PP) + +/*!< @brief Macros used for interrupts */ +#define HAL_LL_UART_IT_MASK 0xFFFFUL +#define HAL_LL_UART_IT_CLEAR_MASK 0x123afeU +#define HAL_LL_UART_IT_CR1_MASK 0x1f0U +#define HAL_LL_UART_IT_CR2_MASK 0x40U +#define HAL_LL_UART_IT_CR3_MASK 0x401U + +#define HAL_LL_UART_CR1_REG_INDEX 1 +#define HAL_LL_UART_CR2_REG_INDEX 2 +#define HAL_LL_UART_CR3_REG_INDEX 3 + +#define HAL_LL_UART_IT_PE 0x100U +#define HAL_LL_UART_IT_TXE (0x10000000 | 0x80U) +#define HAL_LL_UART_IT_TC 0x40U +#define HAL_LL_UART_IT_RXNE (0x10000000 | 0x20U) +#define HAL_LL_UART_IT_IDLE 0x10U +#define HAL_LL_UART_IT_LBD 0x40U +#define HAL_LL_UART_IT_CTS 0x400U +#define HAL_LL_UART_IT_ERR 0x01U + +#define HAL_LL_UART_STATUS_RXNE_FLAG 0x20U +#define HAL_LL_UART_STATUS_TXE_FLAG 0x80U + +/*!< @brief Macro used for status registed flag check + * Used in interrupt handlers. + */ +#define hal_ll_uart_get_status_flags(_handle,_flag) (((hal_ll_uart_base_handle_t *)_handle)->isr & _flag) + +/*!< @brief Macro used for status register flag clearing + * Used in interrupt handlers. + */ +#define hal_ll_uart_clear_status_flag(_handle,_flag) (set_reg_bit( &(((hal_ll_uart_base_handle_t *)_handle)->icr), ( _flag & HAL_LL_UART_IT_CLEAR_MASK ) ) ) + +/*!< @brief Macro used for module interrupt enabling. + * Used in interrupt handlers. + */ +#define __HAL_LL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__ >> 28UL) == HAL_LL_UART_CR1_REG_INDEX)? (__HANDLE__->cr1 |= (__INTERRUPT__ & HAL_LL_UART_IT_MASK)): \ + ((__INTERRUPT__ >> 28UL) == HAL_LL_UART_CR2_REG_INDEX)? (__HANDLE__->cr2 |= (__INTERRUPT__ & HAL_LL_UART_IT_MASK)): \ + (__HANDLE__->cr3 |= (__INTERRUPT__ & HAL_LL_UART_IT_MASK))) + +/*!< @brief Macro used for module interrupt disabling. + * Used in interrupt handlers. + */ +#define __HAL_LL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__ >> 28UL) == HAL_LL_UART_CR1_REG_INDEX)? (__HANDLE__->cr1 &= ~(__INTERRUPT__ & HAL_LL_UART_IT_MASK)): \ + ((__INTERRUPT__ >> 28UL) == HAL_LL_UART_CR2_REG_INDEX)? (__HANDLE__->cr2 &= ~(__INTERRUPT__ & HAL_LL_UART_IT_MASK)): \ + (__HANDLE__->cr3 &= ~ (__INTERRUPT__ & HAL_LL_UART_IT_MASK))) + +/*!< @brief Macro used for module interrupt source check. + * Used in interrupt handlers. + */ +#define __HAL_LL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__ >> 28UL) == 1UL)? ((hal_ll_uart_base_handle_t *)__HANDLE__)->cr1:((((uint32_t)__INTERRUPT__ >> 28UL) == 2UL)? \ + ((hal_ll_uart_base_handle_t *)__HANDLE__)->cr2 : ((hal_ll_uart_base_handle_t *)__HANDLE__)->cr3)) & ((uint32_t)__INTERRUPT__ & HAL_LL_UART_IT_MASK)) + +/*!< @brief UART HW register structure */ +typedef struct +{ + hal_ll_base_addr_t cr1; + hal_ll_base_addr_t cr2; + hal_ll_base_addr_t cr3; + hal_ll_base_addr_t brr; + hal_ll_base_addr_t gtpr; + hal_ll_base_addr_t rtor; + hal_ll_base_addr_t rqr; + hal_ll_base_addr_t isr; + hal_ll_base_addr_t icr; + hal_ll_base_addr_t rdr; + hal_ll_base_addr_t tdr; + hal_ll_base_addr_t presc; + +} hal_ll_uart_base_handle_t; + +/*!< @brief UART baud rate structure */ +typedef struct +{ + uint32_t baud; + uint32_t real_baud; +} hal_ll_uart_baud_t; + +/*!< @brief UART hw specific structure */ +typedef struct +{ + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + hal_ll_uart_pins_t pins; + hal_ll_uart_baud_t baud_rate; + hal_ll_uart_parity_t parity; + hal_ll_uart_stop_bits_t stop_bit; + hal_ll_uart_data_bits_t data_bit; +} hal_ll_uart_hw_specifics_map_t; + +/*!< @brief UART hw specific module values */ +typedef struct +{ + uint16_t pin_tx; + uint16_t pin_rx; +} hal_ll_uart_pin_id; + +/*!< @brief UART hw specific error values */ +typedef enum +{ + HAL_LL_UART_SUCCESS = 0, + HAL_LL_UART_WRONG_PINS, + HAL_LL_UART_MODULE_ERROR, + + HAL_LL_UART_ERROR = (-1) +} hal_ll_uart_err_t; + +/*!< @brief UART module state selection */ +typedef enum +{ + HAL_LL_UART_DISABLE = 0, + HAL_LL_UART_ENABLE +} hal_ll_uart_state_t; + +// ------------------------------------------------------------------ VARIABLES +/*!< @brief UART hardware specific info */ +static hal_ll_uart_hw_specifics_map_t hal_ll_uart_hw_specifics_map[] = +{ + #ifdef UART_MODULE_1 + {HAL_LL_UART1_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_1), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + + #ifdef UART_MODULE_2 + {HAL_LL_UART2_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_2), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + + #ifdef UART_MODULE_3 + {HAL_LL_UART3_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_3), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + + #ifdef UART_MODULE_4 + {HAL_LL_UART4_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_4), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + + + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {0, 0}, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR} +}; + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_uart_handle_register_t *low_level_handle; +static volatile hal_ll_uart_hw_specifics_map_t *hal_ll_uart_hw_specifics_map_local; + +/*!< @brief Global interrupt handlers used in functions */ +static hal_ll_uart_isr_t irq_handler; +static handle_t objects[UART_MODULE_COUNT]; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Check if pins are adequate. + * + * Checks tx and rx pins the user has passed with pre-defined + * pins in tx and rx maps. Take into consideration that module + * index numbers have to be the same for both pins. + * + * @param[in] tx_pin - TX pre-defined pin name. + * @param[in] rx_pin - RX pre-defined pin name. + * @param[in] *index_list - Array containing map index numbers. + * @return hal_ll_pin_name_t Module index based on pins. + * + * Returns pre-defined module index from pin maps, if pins + * are adequate. + */ +static hal_ll_pin_name_t hal_ll_uart_check_pins( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_uart_pin_id *index_list, hal_ll_uart_handle_register_t *handle_map ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * TX and RX pins. + * + * @param[in] module_index UART HW module index -- 0,1,2... + * @param[in] *index_list Array with TX and RX map index values + * and module number + * + * @return None + */ +static void hal_ll_uart_map_pins( uint8_t module_index, hal_ll_uart_pin_id *index_list ); + +/** + * @brief Sets UART pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if UART is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_state - Init/De-init + * + * @return void None. + */ +static void hal_ll_uart_alternate_functions_set_state( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_uart_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_uart_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_uart_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Enable clock for UART module on hardware level. + * + * Initializes UART module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_stat - True(enable clock)/False(disable clock). + * + * @return void None. + */ +static void hal_ll_uart_set_clock( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Finds UART module index. + * + * Finds UART index(module number) based on + * handle value. + * + * @param[in] handle - Object specific context handler. + * + * @return uint8_t Module number. + * Returns values from 0 to 9. + */ +static uint8_t hal_ll_uart_find_index( handle_t *handle ); + +/** + * @brief Get UART module clock speed. + * + * Returns adequate clock speed based on + * UART module base address. + * + * @param[in] module_index - UART module index number. + * + * @return uint8_t Module number. + * Returns clock value. + */ +static uint32_t hal_ll_uart_get_clock_speed( hal_ll_pin_name_t module_index ); + +/** + * @brief Clears UART registers. + * + * Clears UART module configuration + * registers, effectively disabling the module itself. + * Take into consideration that any IRQ bits + * are not cleared. + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * + * @return void None. + */ +static void hal_ll_uart_clear_regs( hal_ll_uart_base_handle_t *hal_ll_hw_reg ); + +/** + * @brief Sets desired baud rate on hardware level. + * + * Initializes module with specified baud rate value. + * Take into consideration that if the difference + * between desired baud rate and actual baud + * rate the hw was initialized to is greater than + * 1%, baud rate shall not be set. + * If this occurs, return value shall be + * the error percentage. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_set_baud_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Sets desired stop bits. + * + * Initializes module on hardware level + * with specified stop bit value. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_set_stop_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Sets desired data bits. + * + * Initializes module on hardware level + * with specified data bit bit value. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_set_data_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Sets desired parity. + * + * Initializes module on hardware level + * with specified parity value. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_set_parity_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Sets module clock value. + * + * Enables/disables specific UART module + * clock gate. + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * @param[in] pin_state - true(enable clock) / false(disable clock) + * + * @return void None. + */ +static void hal_ll_uart_set_module( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ); + +/** + * @brief Sets module TX line state. + * + * Enables/disables specific UART module + * TX pin state + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * @param[in] pin_state - true(enable transmitter pin) / false(disable transmitter pin) + * + * @return void None. + */ +static void hal_ll_uart_set_transmitter( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ); + +/** + * @brief Sets module RX line state. + * + * Enables/disables specific UART module + * RX pin state + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * @param[in] pin_state - true(enable receive pin) / false(disable receive pin) + * + * @return void None. + */ +static void hal_ll_uart_set_receiver( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ); + +/** + * @brief Initialize UART module. + * + * Enables UART module clogk gate first. + * Sets pin alternate function state. + * Initializes specific UART module. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_init( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Initialize UART module on the hardware level. + * + * Performs UART module initialization on + * the hardware level. + * + * Procedure: + * 1. Clears control registers + * 2. Sets data bit value + * 3. Sets parity value + * 4. Sets stop bit value + * 5. Sets baud rate value + * 6. Enables transmit pin + * 7. Enables receive pin + * 8. Enables clock gate for specific module + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_hw_init( hal_ll_uart_hw_specifics_map_t *map ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_uart_register_handle( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_uart_handle_register_t *handle_map, uint8_t *hal_module_id ) { + + hal_ll_uart_pin_id index_list[UART_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + uint16_t pin_check_result; + + // Check if pins are valid + if ( (pin_check_result = hal_ll_uart_check_pins( tx_pin, rx_pin, &index_list, handle_map )) == HAL_LL_PIN_NC ) { + return HAL_LL_UART_WRONG_PINS; + }; + + if ( (hal_ll_uart_hw_specifics_map[pin_check_result].pins.tx_pin.pin_name != tx_pin) || + (hal_ll_uart_hw_specifics_map[pin_check_result].pins.rx_pin.pin_name != rx_pin) ) + { + hal_ll_uart_alternate_functions_set_state( &hal_ll_uart_hw_specifics_map[ pin_check_result ], false ); + + hal_ll_uart_map_pins( pin_check_result, &index_list ); + + hal_ll_uart_alternate_functions_set_state( &hal_ll_uart_hw_specifics_map[ pin_check_result ], true ); + + handle_map[pin_check_result].init_ll_state = false; + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[pin_check_result].hal_ll_uart_handle = (handle_t *)&hal_ll_uart_hw_specifics_map[pin_check_result].base; + + handle_map[pin_check_result].hal_ll_uart_handle = (handle_t *)&hal_ll_module_state[pin_check_result].hal_ll_uart_handle; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_uart( handle_t *handle ) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + hal_ll_uart_pin_id index_list[UART_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + uint16_t pin_check_result; + + if ( (pin_check_result = hal_ll_uart_check_pins( hal_ll_uart_hw_specifics_map_local->pins.tx_pin.pin_name, + hal_ll_uart_hw_specifics_map_local->pins.rx_pin.pin_name, &index_list, (void *)0 ) ) == HAL_LL_PIN_NC ) { + return HAL_LL_UART_WRONG_PINS; + }; + + hal_ll_uart_init( hal_ll_uart_hw_specifics_map_local ); + + hal_ll_module_state[pin_check_result].hal_ll_uart_handle = (handle_t *)&hal_ll_uart_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_uart_set_baud( handle_t *handle, uint32_t baud ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->baud_rate.baud = baud; + + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return hal_ll_uart_hw_specifics_map_local->baud_rate.real_baud; +} + +hal_ll_err_t hal_ll_uart_set_parity( handle_t *handle, hal_ll_uart_parity_t parity ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->parity = parity; + + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_uart_set_stop_bits( handle_t *handle, hal_ll_uart_stop_bits_t stop_bit ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->stop_bit = stop_bit; + + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_uart_set_data_bits( handle_t *handle, hal_ll_uart_data_bits_t data_bit ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + // Chips using implementation 1 do not support 7 bit data + if( data_bit == HAL_LL_UART_DATA_BITS_7 ) { + return HAL_LL_UART_MODULE_ERROR; + } + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->data_bit = data_bit; + + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +void hal_ll_uart_close( handle_t *handle ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + if( low_level_handle->hal_ll_uart_handle != NULL ) { + hal_ll_uart_alternate_functions_set_state( hal_ll_uart_hw_specifics_map_local, false ); + + hal_ll_uart_irq_disable(handle, HAL_LL_UART_IRQ_RX); + hal_ll_uart_irq_disable(handle, HAL_LL_UART_IRQ_TX); + + hal_ll_uart_clear_regs(hal_ll_uart_hw_specifics_map_local->base); + hal_ll_uart_set_clock(hal_ll_uart_hw_specifics_map_local, false); + + hal_ll_uart_hw_specifics_map_local->pins.tx_pin.pin_name = HAL_LL_PIN_NC; + hal_ll_uart_hw_specifics_map_local->pins.tx_pin.pin_af = 0; + hal_ll_uart_hw_specifics_map_local->pins.rx_pin.pin_name = HAL_LL_PIN_NC; + hal_ll_uart_hw_specifics_map_local->pins.rx_pin.pin_af = 0; + + hal_ll_uart_hw_specifics_map_local->baud_rate.baud = 115200UL; + hal_ll_uart_hw_specifics_map_local->baud_rate.real_baud = 0; + + irq_handler = NULL; + objects[ hal_ll_uart_find_index( handle ) ] = NULL; + + low_level_handle->hal_ll_uart_handle = NULL; + low_level_handle->hal_drv_uart_handle = NULL; + + low_level_handle->init_ll_state = false; + } +} + +void hal_ll_uart_register_irq_handler( handle_t *handle, hal_ll_uart_isr_t handler, handle_t obj ) +{ + irq_handler = handler; + objects[ hal_ll_uart_find_index( handle ) ] = obj; +} + +void hal_ll_uart_irq_enable( handle_t *handle, hal_ll_uart_irq_t irq ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + switch ( irq ) { + case HAL_LL_UART_IRQ_RX: + __HAL_LL_UART_ENABLE_IT( hal_ll_hw_reg, HAL_LL_UART_IT_RXNE ); + break; + + case HAL_LL_UART_IRQ_TX: + __HAL_LL_UART_ENABLE_IT( hal_ll_hw_reg, HAL_LL_UART_IT_TXE ); + break; + + default: + break; + } + + switch ( hal_ll_uart_hw_specifics_map_local->module_index ) + { + #if defined(UART_MODULE_1) && defined(UART1_NVIC) + case hal_ll_uart_module_num(UART_MODULE_1): + hal_ll_core_enable_irq( UART1_NVIC ); + break; + #endif + + #if defined(UART_MODULE_2) && defined(UART2_NVIC) + case hal_ll_uart_module_num(UART_MODULE_2): + hal_ll_core_enable_irq( UART2_NVIC ); + break; + #endif + + #if defined(UART_MODULE_3) && defined(UART3_NVIC) + case hal_ll_uart_module_num(UART_MODULE_3): + hal_ll_core_enable_irq( UART3_NVIC ); + break; + #endif + + #if defined(UART_MODULE_4) && defined(UART4_NVIC) + case hal_ll_uart_module_num(UART_MODULE_4): + hal_ll_core_enable_irq( UART4_NVIC ); + break; + #endif + + + default: + break; + } +} + +void hal_ll_uart_irq_disable( handle_t *handle, hal_ll_uart_irq_t irq ) +{ + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + switch ( irq ) { + case HAL_LL_UART_IRQ_RX: + __HAL_LL_UART_DISABLE_IT( hal_ll_hw_reg, HAL_LL_UART_IT_RXNE ); + break; + + case HAL_LL_UART_IRQ_TX: + __HAL_LL_UART_DISABLE_IT( hal_ll_hw_reg, HAL_LL_UART_IT_TXE ); + break; + + default: + break; + } + + // Check if module interrupt flags are set or not + if ( ( !check_reg_bit( &hal_ll_hw_reg->cr1, HAL_LL_UART_SR_RXNE ) ) && + ( !check_reg_bit( &hal_ll_hw_reg->cr1, HAL_LL_UART_SR_TXE ) ) ) + { + switch ( hal_ll_uart_hw_specifics_map_local->module_index ) + { + #if defined(UART_MODULE_1) && defined(UART1_NVIC) + case hal_ll_uart_module_num(UART_MODULE_1): + hal_ll_core_disable_irq( UART1_NVIC ); + break; + #endif + + #if defined(UART_MODULE_2) && defined(UART2_NVIC) + case hal_ll_uart_module_num(UART_MODULE_2): + hal_ll_core_disable_irq( UART2_NVIC ); + break; + #endif + + #if defined(UART_MODULE_3) && defined(UART3_NVIC) + case hal_ll_uart_module_num(UART_MODULE_3): + hal_ll_core_disable_irq( UART3_NVIC ); + break; + #endif + + #if defined(UART_MODULE_4) && defined(UART4_NVIC) + case hal_ll_uart_module_num(UART_MODULE_4): + hal_ll_core_disable_irq( UART4_NVIC ); + break; + #endif + + + default: + break; + } + } +} + +void hal_ll_uart_write( handle_t *handle, uint8_t wr_data) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + hal_ll_hw_reg->tdr = wr_data; +} + +uint8_t hal_ll_uart_read( handle_t *handle ) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + return ( hal_ll_hw_reg->rdr ); +} + +// ------------------------------------------------------------- DEFAULT EXCEPTION HANDLERS + +#if defined(USART_MODULE_1) +void MARK_AS_IRQ_HANDLER UART1_IRQHandler() MIKROC_IV(UART1_NVIC) { + #ifdef USART_MODULE_1 + if( hal_ll_uart_get_status_flags( HAL_LL_USART1_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART1_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART1_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_1) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_USART1_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART1_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART1_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_1) ], HAL_LL_UART_IRQ_TX ); + } + } + #endif +} +#endif + +#if defined(USART_MODULE_2) +void MARK_AS_IRQ_HANDLER UART2_IRQHandler() MIKROC_IV(UART2_NVIC) { + #ifdef USART_MODULE_2 + if( hal_ll_uart_get_status_flags( HAL_LL_USART2_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART2_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART2_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_2) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_USART2_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART2_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART2_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_2) ], HAL_LL_UART_IRQ_TX ); + } + } + #endif +} +#endif + +#if defined(USART_MODULE_3) +void MARK_AS_IRQ_HANDLER UART3_IRQHandler() MIKROC_IV(UART3_NVIC) { + #ifdef USART_MODULE_3 + if( hal_ll_uart_get_status_flags( HAL_LL_USART3_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART3_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART3_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_3) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_USART3_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART3_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART3_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_3) ], HAL_LL_UART_IRQ_TX ); + } + } + #endif +} +#endif + +#if defined(UART_MODULE_4) +void MARK_AS_IRQ_HANDLER UART4_IRQHandler() MIKROC_IV(UART4_NVIC) { + #ifdef UART_MODULE_4 + if( hal_ll_uart_get_status_flags( HAL_LL_UART4_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_UART4_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_UART4_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(UART_MODULE_4) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_UART4_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_UART4_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_UART4_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(UART_MODULE_4) ], HAL_LL_UART_IRQ_TX ); + } + } + #endif +} +#endif + +#if defined(LPUART_MODULE_1) +void MARK_AS_IRQ_HANDLER LPUART1_IRQHandler() MIKROC_IV(LPUART1_NVIC) { + #ifdef LPUART_MODULE_1 + if( hal_ll_uart_get_status_flags( HAL_LL_LPUART1_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_LPUART1_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_LPUART1_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(LPUART_MODULE_1) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_LPUART1_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_LPUART1_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_LPUART1_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(LPUART_MODULE_1) ], HAL_LL_UART_IRQ_TX ); + } + } + #endif +} +#endif + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static uint8_t hal_ll_uart_find_index( handle_t *handle ) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + if( hal_ll_uart_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + return hal_ll_uart_hw_specifics_map_local->module_index; + } else { + return NULL; + } +} + +static hal_ll_pin_name_t hal_ll_uart_check_pins( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_uart_pin_id *index_list, hal_ll_uart_handle_register_t *handle_map ) { + static const uint16_t tx_map_size = ( sizeof( hal_ll_uart_tx_map ) / sizeof( hal_ll_uart_pin_map_t ) ); + static const uint16_t rx_map_size = ( sizeof( hal_ll_uart_rx_map ) / sizeof( hal_ll_uart_pin_map_t ) ); + uint8_t hal_ll_module_id = 0; + uint8_t index_counter = 0; + uint16_t tx_index; + uint16_t rx_index; + + if ( (HAL_LL_PIN_NC == tx_pin) || (HAL_LL_PIN_NC == rx_pin) ) { + return HAL_LL_PIN_NC; + } + + for ( tx_index = 0; tx_index < tx_map_size; tx_index++ ) + { + if ( hal_ll_uart_tx_map[ tx_index ].pin == tx_pin ) + { + for ( rx_index = 0; rx_index < rx_map_size; rx_index++ ) + { + if ( hal_ll_uart_rx_map[ rx_index ].pin == rx_pin ) + { + if ( hal_ll_uart_tx_map[ tx_index ].base == hal_ll_uart_rx_map[ rx_index ].base ) { + // Get module number + hal_ll_module_id = hal_ll_uart_tx_map[ tx_index ].module_index; + + // Map pin names + index_list[hal_ll_module_id].pin_tx = tx_index; + index_list[hal_ll_module_id].pin_rx = rx_index; + + // Check if module is taken + if ( NULL == handle_map[ hal_ll_module_id ].hal_drv_uart_handle ) { + return hal_ll_module_id; + } else if ( UART_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static hal_ll_uart_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof(hal_ll_uart_handle_register_t)); + static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof(hal_ll_uart_handle_register_t)); + + while( hal_ll_module_count-- ) { + if (hal_ll_uart_get_base_from_hal_handle == hal_ll_uart_hw_specifics_map[hal_ll_module_count].base) { + return &hal_ll_uart_hw_specifics_map[hal_ll_module_count]; + } + } + + return &hal_ll_uart_hw_specifics_map[hal_ll_module_error]; +} + +static void hal_ll_uart_set_clock( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ) { + switch ( map->module_index ) + { + #ifdef UART_MODULE_1 + case ( hal_ll_uart_module_num(UART_MODULE_1) ): + (hal_ll_state == true)?(set_reg_bit( _RCC_APB2ENR, HAL_LL_USART1EN )):(clear_reg_bit( _RCC_APB2ENR, HAL_LL_USART1EN )); + break; + #endif + + #ifdef UART_MODULE_2 + case ( hal_ll_uart_module_num(UART_MODULE_2) ): + (hal_ll_state == true)?(set_reg_bit( _RCC_APB1ENR1, HAL_LL_USART2EN )):(clear_reg_bit( _RCC_APB1ENR1, HAL_LL_USART2EN )); + break; + #endif + + #ifdef UART_MODULE_3 + case ( hal_ll_uart_module_num(UART_MODULE_3) ): + (hal_ll_state == true)?(set_reg_bit( _RCC_APB1ENR1, HAL_LL_USART3EN )):(clear_reg_bit( _RCC_APB1ENR1, HAL_LL_USART3EN )); + break; + #endif + + #ifdef UART_MODULE_4 + case ( hal_ll_uart_module_num(UART_MODULE_4) ): + (hal_ll_state == true)?(set_reg_bit( _RCC_APB1ENR1, HAL_LL_USART4EN )):(clear_reg_bit( _RCC_APB1ENR1, HAL_LL_USART4EN )); + break; + #endif + + + default: + break; + } +} + +static void hal_ll_uart_map_pins( uint8_t module_index, hal_ll_uart_pin_id *index_list ) { + // Map new pins + hal_ll_uart_hw_specifics_map[module_index].pins.tx_pin.pin_name = hal_ll_uart_tx_map[ index_list[module_index].pin_tx ].pin; + hal_ll_uart_hw_specifics_map[module_index].pins.rx_pin.pin_name = hal_ll_uart_rx_map[ index_list[module_index].pin_rx ].pin; + // TX and RX could have different alternate function settings, hence save both AF values + hal_ll_uart_hw_specifics_map[module_index].pins.tx_pin.pin_af = hal_ll_uart_tx_map[ index_list[module_index].pin_tx ].af; + hal_ll_uart_hw_specifics_map[module_index].pins.rx_pin.pin_af = hal_ll_uart_rx_map[ index_list[module_index].pin_rx ].af; +} + +static void hal_ll_uart_alternate_functions_set_state( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ) { + module_struct module; + + if ( (map->pins.tx_pin.pin_name != HAL_LL_PIN_NC) && map->pins.rx_pin.pin_name != HAL_LL_PIN_NC ) { + module.pins[0] = VALUE( map->pins.tx_pin.pin_name, map->pins.tx_pin.pin_af ); + module.pins[1] = VALUE( map->pins.rx_pin.pin_name, map->pins.rx_pin.pin_af ); + module.pins[2] = GPIO_MODULE_STRUCT_END; + + module.configs[0] = HAL_LL_UART_AF_CONFIG; + module.configs[1] = HAL_LL_UART_AF_CONFIG; + module.configs[2] = GPIO_MODULE_STRUCT_END; + + /* STM32F1xx specific */ + module.gpio_remap = map->pins.tx_pin.pin_af; + + hal_ll_gpio_module_struct_init( &module, hal_ll_state ); + } +} + +static void hal_ll_uart_set_baud_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + uint32_t reg = 0; + uint32_t integer_divider = 0; + uint32_t fractional_divider = 0; + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); + uint32_t hal_ll_baud_value = hal_ll_uart_get_baud(hal_ll_uart_get_clock_speed(map->module_index),map->baud_rate.baud,4); + uint32_t hal_ll_baud_real_value = hal_ll_uart_get_real_baud(hal_ll_uart_get_clock_speed(map->module_index),hal_ll_baud_value,4); + + // if error greater than specified, cancel setting baud rate + if( (hal_ll_uart_get_baud_error(hal_ll_baud_real_value,map->baud_rate.baud)) > HAL_LL_UART_ACCEPTABLE_ERROR ) { + map->baud_rate.real_baud = hal_ll_uart_get_baud_error(hal_ll_baud_real_value,map->baud_rate.baud); + } else { + map->baud_rate.real_baud = hal_ll_baud_real_value; + + integer_divider = ( ( 25 * hal_ll_uart_get_clock_speed( map->module_index ) ) / ( 4 * ( map->baud_rate.baud ) ) ); + reg = ( integer_divider / 100 ) << 4; + + fractional_divider = integer_divider - ( 100 * ( reg >> 4 ) ); + reg |= ( ( ( ( fractional_divider * 16 ) + 50 ) / 100 ) ) & 0x0F; + + hal_ll_hw_reg->brr = ( uint16_t )reg; + } +} + +static uint32_t hal_ll_uart_get_clock_speed( hal_ll_pin_name_t module_index ) { + rcc_clocks_t rcc_clocks; + + RCC_GetClocksFrequency( &rcc_clocks ); + + switch ( module_index ) + { + #ifdef UART_MODULE_1 + case ( hal_ll_uart_module_num(UART_MODULE_1) ): + return rcc_clocks.pclk2; + break; + #endif + + #ifdef UART_MODULE_2 + case ( hal_ll_uart_module_num(UART_MODULE_2) ): + return rcc_clocks.pclk1; + break; + #endif + + #ifdef UART_MODULE_3 + case ( hal_ll_uart_module_num(UART_MODULE_3) ): + return rcc_clocks.pclk1; + break; + #endif + + #ifdef UART_MODULE_4 + case ( hal_ll_uart_module_num(UART_MODULE_4) ): + return rcc_clocks.pclk1; + break; + #endif + + + default: + break; + } + + return NULL; +} + +static void hal_ll_uart_set_stop_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); + + switch ( map->stop_bit ) + { + case HAL_LL_UART_STOP_BITS_HALF: + hal_ll_hw_reg->cr2 |= STOP_BITS_HALF; + break; + case HAL_LL_UART_STOP_BITS_ONE: + hal_ll_hw_reg->cr2 |= STOP_BITS_ONE; + break; + case HAL_LL_UART_STOP_BITS_ONE_AND_A_HALF: + hal_ll_hw_reg->cr2 |= STOP_BITS_ONE_AND_A_HALF; + break; + case HAL_LL_UART_STOP_BITS_TWO: + hal_ll_hw_reg->cr2 |= STOP_BITS_TWO; + break; + + default: + break; + } +} + +static void hal_ll_uart_set_data_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); + + switch ( map->data_bit ) + { + case HAL_LL_UART_DATA_BITS_7: + hal_ll_hw_reg->cr1 |= DATA_BIT_7; + break; + + case HAL_LL_UART_DATA_BITS_8: + hal_ll_hw_reg->cr1 |= DATA_BIT_8; + break; + + case HAL_LL_UART_DATA_BITS_9: + hal_ll_hw_reg->cr1 |= DATA_BIT_9; + break; + + + default: + break; + } +} + +static void hal_ll_uart_set_parity_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); + + switch ( map->parity ) + { + case HAL_LL_UART_PARITY_NONE: + hal_ll_hw_reg->cr1 |= PARITY_NO; + break; + case HAL_LL_UART_PARITY_EVEN: + hal_ll_hw_reg->cr1 |= PARITY_ENABLED | PARITY_EVEN; + break; + case HAL_LL_UART_PARITY_ODD: + hal_ll_hw_reg->cr1 |= PARITY_ENABLED | PARITY_ODD; + break; + + default: + break; + } +} + +static void hal_ll_uart_set_module( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ) { + switch ( pin_state ) + { + case HAL_LL_UART_DISABLE: + clear_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_UE ); + break; + + case HAL_LL_UART_ENABLE: + set_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_UE ); + break; + + default: + break; + } +} + +static void hal_ll_uart_set_transmitter( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ) { + switch ( pin_state ) + { + case HAL_LL_UART_DISABLE: + clear_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_TE ); + break; + + case HAL_LL_UART_ENABLE: + set_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_TE ); + break; + + default: + break; + } +} + +static void hal_ll_uart_set_receiver( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ) { + switch ( pin_state ) + { + case HAL_LL_UART_DISABLE: + clear_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_RE ); + break; + + case HAL_LL_UART_ENABLE: + set_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_RE ); + break; + + default: + break; + } +} + +static void hal_ll_uart_clear_regs( hal_ll_uart_base_handle_t *hal_ll_hw_reg ) { + hal_ll_hw_reg->cr1 &= HAL_LL_UART_IT_CR1_MASK; + hal_ll_hw_reg->cr2 &= HAL_LL_UART_IT_CR2_MASK; + hal_ll_hw_reg->cr3 &= HAL_LL_UART_IT_CR3_MASK; +} + +static void hal_ll_uart_hw_init( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_clear_regs( map->base ); + + hal_ll_uart_set_data_bits_bare_metal( map ); + + hal_ll_uart_set_parity_bare_metal( map ); + + hal_ll_uart_set_stop_bits_bare_metal( map ); + + hal_ll_uart_set_baud_bare_metal( map ); + + hal_ll_uart_set_transmitter( map->base, HAL_LL_UART_ENABLE ); + + hal_ll_uart_set_receiver( map->base, HAL_LL_UART_ENABLE ); + + hal_ll_uart_set_module( map->base, HAL_LL_UART_ENABLE ); +} + +static void hal_ll_uart_init( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_set_clock( map, true ); + + hal_ll_uart_alternate_functions_set_state( map, true ); + + hal_ll_uart_hw_init( map ); +} +// ------------------------------------------------------------------------- END + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_84/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_84/CMakeLists.cmake new file mode 100644 index 000000000..27191b695 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_84/CMakeLists.cmake @@ -0,0 +1,9 @@ +if(${MCU_NAME} MATCHES "^STM32G473CB$|^STM32G473MB$|^STM32G473PB$|^STM32G473RB$|^STM32G473VB$|^STM32G473QB$|^STM32G473CC$|^STM32G473MC$|^STM32G473PC$|^STM32G473RC$|^STM32G473VC$|^STM32G473QC$|^STM32G473CE$|^STM32G473ME$|^STM32G473PE$|^STM32G473RE$|^STM32G473VE$|^STM32G473QE$") + set(uart_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_uart.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_84") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_84") + list(APPEND hal_ll_def_list "STM32G4xx") + list(APPEND hal_ll_def_list "STM32G47xx") + list(APPEND hal_ll_def_list "STM32G473xx") + set(uart_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/uart/hal_ll_uart_pin_map/implementations/doc_ds_84") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_84/hal_ll_uart.c b/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_84/hal_ll_uart.c new file mode 100644 index 000000000..f6304e601 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_84/hal_ll_uart.c @@ -0,0 +1,1255 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_uart.c + * @brief UART HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_rcc.h" +#include "hal_ll_uart.h" +#include "hal_ll_gpio.h" +#include "hal_ll_core.h" +#include "hal_ll_core_defines.h" +#include "hal_ll_uart_pin_map.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_uart_handle_register_t hal_ll_module_state[UART_MODULE_COUNT] = { (handle_t *)NULL, (handle_t *)NULL, false }; + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_uart_get_module_state_address ((hal_ll_uart_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_uart_get_handle (hal_ll_uart_handle_register_t *)hal_ll_uart_get_module_state_address->hal_ll_uart_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_uart_get_base_struct(_handle) ((hal_ll_uart_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_uart_get_base_from_hal_handle ((hal_ll_uart_hw_specifics_map_t *)((hal_ll_uart_handle_register_t *)\ + (((hal_ll_uart_handle_register_t *)(handle))->hal_ll_uart_handle))->hal_ll_uart_handle)->base + +/*!< @brief Macros used for calculating actual baud rate value and error value */ +#define HAL_LL_UART_ACCEPTABLE_ERROR (float)1.0 +#define hal_ll_uart_get_baud(_clock,_baud,_div) (((_clock/(float)_baud)/_div)-1) +#define hal_ll_uart_get_real_baud(_clock,_baud,_div) (_clock/(_div*(_baud+1))) +#define hal_ll_uart_get_baud_error(_baud_real,_baud) (((float)(abs(_baud_real-_baud))/_baud)*100) + +/*!< @brief Macros defining bit location */ +#define HAL_LL_USART1EN 14 + +#define HAL_LL_USART2EN 17 + +#define HAL_LL_USART3EN 18 + +#define HAL_LL_USART4EN 19 + +#define HAL_LL_USART5EN 20 + + +#define HAL_LL_UART_CR1_UE 0 +#define HAL_LL_UART_CR1_TE 3 +#define HAL_LL_UART_CR1_RE 2 + +#define HAL_LL_UART_SR_RXNE 5 +#define HAL_LL_UART_SR_TXE 7 + +/*!< @brief Macros defining register bit values */ +#define STOP_BITS_HALF 0x1000U +#define STOP_BITS_ONE 0x00U +#define STOP_BITS_ONE_AND_A_HALF 0x3000U +#define STOP_BITS_TWO 0x2000U + +#define DATA_BIT_7 0x10000000U +#define DATA_BIT_8 0x00U +#define DATA_BIT_9 0x1000U + +#define PARITY_NO 0x00U +#define PARITY_ENABLED 0x400U + +#define PARITY_EVEN 0x00U +#define PARITY_ODD 0x200U + +/*!< @brief Macro used for setting pin alternate functions */ +#define HAL_LL_UART_AF_CONFIG (GPIO_CFG_MODE_ALT_FUNCTION | GPIO_CFG_SPEED_HIGH | GPIO_CFG_OTYPE_PP) + +/*!< @brief Macros used for interrupts */ +#define HAL_LL_UART_IT_MASK 0xFFFFUL +#define HAL_LL_UART_IT_CLEAR_MASK 0x123afeU +#define HAL_LL_UART_IT_CR1_MASK 0x1f0U +#define HAL_LL_UART_IT_CR2_MASK 0x40U +#define HAL_LL_UART_IT_CR3_MASK 0x401U + +#define HAL_LL_UART_CR1_REG_INDEX 1 +#define HAL_LL_UART_CR2_REG_INDEX 2 +#define HAL_LL_UART_CR3_REG_INDEX 3 + +#define HAL_LL_UART_IT_PE 0x100U +#define HAL_LL_UART_IT_TXE (0x10000000 | 0x80U) +#define HAL_LL_UART_IT_TC 0x40U +#define HAL_LL_UART_IT_RXNE (0x10000000 | 0x20U) +#define HAL_LL_UART_IT_IDLE 0x10U +#define HAL_LL_UART_IT_LBD 0x40U +#define HAL_LL_UART_IT_CTS 0x400U +#define HAL_LL_UART_IT_ERR 0x01U + +#define HAL_LL_UART_STATUS_RXNE_FLAG 0x20U +#define HAL_LL_UART_STATUS_TXE_FLAG 0x80U + +/*!< @brief Macro used for status registed flag check + * Used in interrupt handlers. + */ +#define hal_ll_uart_get_status_flags(_handle,_flag) (((hal_ll_uart_base_handle_t *)_handle)->isr & _flag) + +/*!< @brief Macro used for status register flag clearing + * Used in interrupt handlers. + */ +#define hal_ll_uart_clear_status_flag(_handle,_flag) (set_reg_bit( &(((hal_ll_uart_base_handle_t *)_handle)->icr), ( _flag & HAL_LL_UART_IT_CLEAR_MASK ) ) ) + +/*!< @brief Macro used for module interrupt enabling. + * Used in interrupt handlers. + */ +#define __HAL_LL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__ >> 28UL) == HAL_LL_UART_CR1_REG_INDEX)? (__HANDLE__->cr1 |= (__INTERRUPT__ & HAL_LL_UART_IT_MASK)): \ + ((__INTERRUPT__ >> 28UL) == HAL_LL_UART_CR2_REG_INDEX)? (__HANDLE__->cr2 |= (__INTERRUPT__ & HAL_LL_UART_IT_MASK)): \ + (__HANDLE__->cr3 |= (__INTERRUPT__ & HAL_LL_UART_IT_MASK))) + +/*!< @brief Macro used for module interrupt disabling. + * Used in interrupt handlers. + */ +#define __HAL_LL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__ >> 28UL) == HAL_LL_UART_CR1_REG_INDEX)? (__HANDLE__->cr1 &= ~(__INTERRUPT__ & HAL_LL_UART_IT_MASK)): \ + ((__INTERRUPT__ >> 28UL) == HAL_LL_UART_CR2_REG_INDEX)? (__HANDLE__->cr2 &= ~(__INTERRUPT__ & HAL_LL_UART_IT_MASK)): \ + (__HANDLE__->cr3 &= ~ (__INTERRUPT__ & HAL_LL_UART_IT_MASK))) + +/*!< @brief Macro used for module interrupt source check. + * Used in interrupt handlers. + */ +#define __HAL_LL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__ >> 28UL) == 1UL)? ((hal_ll_uart_base_handle_t *)__HANDLE__)->cr1:((((uint32_t)__INTERRUPT__ >> 28UL) == 2UL)? \ + ((hal_ll_uart_base_handle_t *)__HANDLE__)->cr2 : ((hal_ll_uart_base_handle_t *)__HANDLE__)->cr3)) & ((uint32_t)__INTERRUPT__ & HAL_LL_UART_IT_MASK)) + +/*!< @brief UART HW register structure */ +typedef struct +{ + hal_ll_base_addr_t cr1; + hal_ll_base_addr_t cr2; + hal_ll_base_addr_t cr3; + hal_ll_base_addr_t brr; + hal_ll_base_addr_t gtpr; + hal_ll_base_addr_t rtor; + hal_ll_base_addr_t rqr; + hal_ll_base_addr_t isr; + hal_ll_base_addr_t icr; + hal_ll_base_addr_t rdr; + hal_ll_base_addr_t tdr; + hal_ll_base_addr_t presc; + +} hal_ll_uart_base_handle_t; + +/*!< @brief UART baud rate structure */ +typedef struct +{ + uint32_t baud; + uint32_t real_baud; +} hal_ll_uart_baud_t; + +/*!< @brief UART hw specific structure */ +typedef struct +{ + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + hal_ll_uart_pins_t pins; + hal_ll_uart_baud_t baud_rate; + hal_ll_uart_parity_t parity; + hal_ll_uart_stop_bits_t stop_bit; + hal_ll_uart_data_bits_t data_bit; +} hal_ll_uart_hw_specifics_map_t; + +/*!< @brief UART hw specific module values */ +typedef struct +{ + uint16_t pin_tx; + uint16_t pin_rx; +} hal_ll_uart_pin_id; + +/*!< @brief UART hw specific error values */ +typedef enum +{ + HAL_LL_UART_SUCCESS = 0, + HAL_LL_UART_WRONG_PINS, + HAL_LL_UART_MODULE_ERROR, + + HAL_LL_UART_ERROR = (-1) +} hal_ll_uart_err_t; + +/*!< @brief UART module state selection */ +typedef enum +{ + HAL_LL_UART_DISABLE = 0, + HAL_LL_UART_ENABLE +} hal_ll_uart_state_t; + +// ------------------------------------------------------------------ VARIABLES +/*!< @brief UART hardware specific info */ +static hal_ll_uart_hw_specifics_map_t hal_ll_uart_hw_specifics_map[] = +{ + #ifdef UART_MODULE_1 + {HAL_LL_UART1_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_1), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + + #ifdef UART_MODULE_2 + {HAL_LL_UART2_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_2), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + + #ifdef UART_MODULE_3 + {HAL_LL_UART3_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_3), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + + #ifdef UART_MODULE_4 + {HAL_LL_UART4_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_4), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + + #ifdef UART_MODULE_5 + {HAL_LL_UART5_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_5), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + + + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {0, 0}, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR} +}; + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_uart_handle_register_t *low_level_handle; +static volatile hal_ll_uart_hw_specifics_map_t *hal_ll_uart_hw_specifics_map_local; + +/*!< @brief Global interrupt handlers used in functions */ +static hal_ll_uart_isr_t irq_handler; +static handle_t objects[UART_MODULE_COUNT]; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Check if pins are adequate. + * + * Checks tx and rx pins the user has passed with pre-defined + * pins in tx and rx maps. Take into consideration that module + * index numbers have to be the same for both pins. + * + * @param[in] tx_pin - TX pre-defined pin name. + * @param[in] rx_pin - RX pre-defined pin name. + * @param[in] *index_list - Array containing map index numbers. + * @return hal_ll_pin_name_t Module index based on pins. + * + * Returns pre-defined module index from pin maps, if pins + * are adequate. + */ +static hal_ll_pin_name_t hal_ll_uart_check_pins( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_uart_pin_id *index_list, hal_ll_uart_handle_register_t *handle_map ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * TX and RX pins. + * + * @param[in] module_index UART HW module index -- 0,1,2... + * @param[in] *index_list Array with TX and RX map index values + * and module number + * + * @return None + */ +static void hal_ll_uart_map_pins( uint8_t module_index, hal_ll_uart_pin_id *index_list ); + +/** + * @brief Sets UART pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if UART is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_state - Init/De-init + * + * @return void None. + */ +static void hal_ll_uart_alternate_functions_set_state( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_uart_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_uart_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_uart_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Enable clock for UART module on hardware level. + * + * Initializes UART module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_stat - True(enable clock)/False(disable clock). + * + * @return void None. + */ +static void hal_ll_uart_set_clock( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Finds UART module index. + * + * Finds UART index(module number) based on + * handle value. + * + * @param[in] handle - Object specific context handler. + * + * @return uint8_t Module number. + * Returns values from 0 to 9. + */ +static uint8_t hal_ll_uart_find_index( handle_t *handle ); + +/** + * @brief Get UART module clock speed. + * + * Returns adequate clock speed based on + * UART module base address. + * + * @param[in] module_index - UART module index number. + * + * @return uint8_t Module number. + * Returns clock value. + */ +static uint32_t hal_ll_uart_get_clock_speed( hal_ll_pin_name_t module_index ); + +/** + * @brief Clears UART registers. + * + * Clears UART module configuration + * registers, effectively disabling the module itself. + * Take into consideration that any IRQ bits + * are not cleared. + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * + * @return void None. + */ +static void hal_ll_uart_clear_regs( hal_ll_uart_base_handle_t *hal_ll_hw_reg ); + +/** + * @brief Sets desired baud rate on hardware level. + * + * Initializes module with specified baud rate value. + * Take into consideration that if the difference + * between desired baud rate and actual baud + * rate the hw was initialized to is greater than + * 1%, baud rate shall not be set. + * If this occurs, return value shall be + * the error percentage. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_set_baud_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Sets desired stop bits. + * + * Initializes module on hardware level + * with specified stop bit value. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_set_stop_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Sets desired data bits. + * + * Initializes module on hardware level + * with specified data bit bit value. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_set_data_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Sets desired parity. + * + * Initializes module on hardware level + * with specified parity value. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_set_parity_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Sets module clock value. + * + * Enables/disables specific UART module + * clock gate. + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * @param[in] pin_state - true(enable clock) / false(disable clock) + * + * @return void None. + */ +static void hal_ll_uart_set_module( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ); + +/** + * @brief Sets module TX line state. + * + * Enables/disables specific UART module + * TX pin state + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * @param[in] pin_state - true(enable transmitter pin) / false(disable transmitter pin) + * + * @return void None. + */ +static void hal_ll_uart_set_transmitter( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ); + +/** + * @brief Sets module RX line state. + * + * Enables/disables specific UART module + * RX pin state + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * @param[in] pin_state - true(enable receive pin) / false(disable receive pin) + * + * @return void None. + */ +static void hal_ll_uart_set_receiver( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ); + +/** + * @brief Initialize UART module. + * + * Enables UART module clogk gate first. + * Sets pin alternate function state. + * Initializes specific UART module. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_init( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Initialize UART module on the hardware level. + * + * Performs UART module initialization on + * the hardware level. + * + * Procedure: + * 1. Clears control registers + * 2. Sets data bit value + * 3. Sets parity value + * 4. Sets stop bit value + * 5. Sets baud rate value + * 6. Enables transmit pin + * 7. Enables receive pin + * 8. Enables clock gate for specific module + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_hw_init( hal_ll_uart_hw_specifics_map_t *map ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_uart_register_handle( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_uart_handle_register_t *handle_map, uint8_t *hal_module_id ) { + + hal_ll_uart_pin_id index_list[UART_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + uint16_t pin_check_result; + + // Check if pins are valid + if ( (pin_check_result = hal_ll_uart_check_pins( tx_pin, rx_pin, &index_list, handle_map )) == HAL_LL_PIN_NC ) { + return HAL_LL_UART_WRONG_PINS; + }; + + if ( (hal_ll_uart_hw_specifics_map[pin_check_result].pins.tx_pin.pin_name != tx_pin) || + (hal_ll_uart_hw_specifics_map[pin_check_result].pins.rx_pin.pin_name != rx_pin) ) + { + hal_ll_uart_alternate_functions_set_state( &hal_ll_uart_hw_specifics_map[ pin_check_result ], false ); + + hal_ll_uart_map_pins( pin_check_result, &index_list ); + + hal_ll_uart_alternate_functions_set_state( &hal_ll_uart_hw_specifics_map[ pin_check_result ], true ); + + handle_map[pin_check_result].init_ll_state = false; + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[pin_check_result].hal_ll_uart_handle = (handle_t *)&hal_ll_uart_hw_specifics_map[pin_check_result].base; + + handle_map[pin_check_result].hal_ll_uart_handle = (handle_t *)&hal_ll_module_state[pin_check_result].hal_ll_uart_handle; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_uart( handle_t *handle ) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + hal_ll_uart_pin_id index_list[UART_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + uint16_t pin_check_result; + + if ( (pin_check_result = hal_ll_uart_check_pins( hal_ll_uart_hw_specifics_map_local->pins.tx_pin.pin_name, + hal_ll_uart_hw_specifics_map_local->pins.rx_pin.pin_name, &index_list, (void *)0 ) ) == HAL_LL_PIN_NC ) { + return HAL_LL_UART_WRONG_PINS; + }; + + hal_ll_uart_init( hal_ll_uart_hw_specifics_map_local ); + + hal_ll_module_state[pin_check_result].hal_ll_uart_handle = (handle_t *)&hal_ll_uart_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_uart_set_baud( handle_t *handle, uint32_t baud ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->baud_rate.baud = baud; + + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return hal_ll_uart_hw_specifics_map_local->baud_rate.real_baud; +} + +hal_ll_err_t hal_ll_uart_set_parity( handle_t *handle, hal_ll_uart_parity_t parity ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->parity = parity; + + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_uart_set_stop_bits( handle_t *handle, hal_ll_uart_stop_bits_t stop_bit ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->stop_bit = stop_bit; + + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_uart_set_data_bits( handle_t *handle, hal_ll_uart_data_bits_t data_bit ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + // Chips using implementation 1 do not support 7 bit data + if( data_bit == HAL_LL_UART_DATA_BITS_7 ) { + return HAL_LL_UART_MODULE_ERROR; + } + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->data_bit = data_bit; + + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +void hal_ll_uart_close( handle_t *handle ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + if( low_level_handle->hal_ll_uart_handle != NULL ) { + hal_ll_uart_alternate_functions_set_state( hal_ll_uart_hw_specifics_map_local, false ); + + hal_ll_uart_irq_disable(handle, HAL_LL_UART_IRQ_RX); + hal_ll_uart_irq_disable(handle, HAL_LL_UART_IRQ_TX); + + hal_ll_uart_clear_regs(hal_ll_uart_hw_specifics_map_local->base); + hal_ll_uart_set_clock(hal_ll_uart_hw_specifics_map_local, false); + + hal_ll_uart_hw_specifics_map_local->pins.tx_pin.pin_name = HAL_LL_PIN_NC; + hal_ll_uart_hw_specifics_map_local->pins.tx_pin.pin_af = 0; + hal_ll_uart_hw_specifics_map_local->pins.rx_pin.pin_name = HAL_LL_PIN_NC; + hal_ll_uart_hw_specifics_map_local->pins.rx_pin.pin_af = 0; + + hal_ll_uart_hw_specifics_map_local->baud_rate.baud = 115200UL; + hal_ll_uart_hw_specifics_map_local->baud_rate.real_baud = 0; + + irq_handler = NULL; + objects[ hal_ll_uart_find_index( handle ) ] = NULL; + + low_level_handle->hal_ll_uart_handle = NULL; + low_level_handle->hal_drv_uart_handle = NULL; + + low_level_handle->init_ll_state = false; + } +} + +void hal_ll_uart_register_irq_handler( handle_t *handle, hal_ll_uart_isr_t handler, handle_t obj ) +{ + irq_handler = handler; + objects[ hal_ll_uart_find_index( handle ) ] = obj; +} + +void hal_ll_uart_irq_enable( handle_t *handle, hal_ll_uart_irq_t irq ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + switch ( irq ) { + case HAL_LL_UART_IRQ_RX: + __HAL_LL_UART_ENABLE_IT( hal_ll_hw_reg, HAL_LL_UART_IT_RXNE ); + break; + + case HAL_LL_UART_IRQ_TX: + __HAL_LL_UART_ENABLE_IT( hal_ll_hw_reg, HAL_LL_UART_IT_TXE ); + break; + + default: + break; + } + + switch ( hal_ll_uart_hw_specifics_map_local->module_index ) + { + #if defined(UART_MODULE_1) && defined(UART1_NVIC) + case hal_ll_uart_module_num(UART_MODULE_1): + hal_ll_core_enable_irq( UART1_NVIC ); + break; + #endif + + #if defined(UART_MODULE_2) && defined(UART2_NVIC) + case hal_ll_uart_module_num(UART_MODULE_2): + hal_ll_core_enable_irq( UART2_NVIC ); + break; + #endif + + #if defined(UART_MODULE_3) && defined(UART3_NVIC) + case hal_ll_uart_module_num(UART_MODULE_3): + hal_ll_core_enable_irq( UART3_NVIC ); + break; + #endif + + #if defined(UART_MODULE_4) && defined(UART4_NVIC) + case hal_ll_uart_module_num(UART_MODULE_4): + hal_ll_core_enable_irq( UART4_NVIC ); + break; + #endif + + #if defined(UART_MODULE_5) && defined(UART5_NVIC) + case hal_ll_uart_module_num(UART_MODULE_5): + hal_ll_core_enable_irq( UART5_NVIC ); + break; + #endif + + + default: + break; + } +} + +void hal_ll_uart_irq_disable( handle_t *handle, hal_ll_uart_irq_t irq ) +{ + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + switch ( irq ) { + case HAL_LL_UART_IRQ_RX: + __HAL_LL_UART_DISABLE_IT( hal_ll_hw_reg, HAL_LL_UART_IT_RXNE ); + break; + + case HAL_LL_UART_IRQ_TX: + __HAL_LL_UART_DISABLE_IT( hal_ll_hw_reg, HAL_LL_UART_IT_TXE ); + break; + + default: + break; + } + + // Check if module interrupt flags are set or not + if ( ( !check_reg_bit( &hal_ll_hw_reg->cr1, HAL_LL_UART_SR_RXNE ) ) && + ( !check_reg_bit( &hal_ll_hw_reg->cr1, HAL_LL_UART_SR_TXE ) ) ) + { + switch ( hal_ll_uart_hw_specifics_map_local->module_index ) + { + #if defined(UART_MODULE_1) && defined(UART1_NVIC) + case hal_ll_uart_module_num(UART_MODULE_1): + hal_ll_core_disable_irq( UART1_NVIC ); + break; + #endif + + #if defined(UART_MODULE_2) && defined(UART2_NVIC) + case hal_ll_uart_module_num(UART_MODULE_2): + hal_ll_core_disable_irq( UART2_NVIC ); + break; + #endif + + #if defined(UART_MODULE_3) && defined(UART3_NVIC) + case hal_ll_uart_module_num(UART_MODULE_3): + hal_ll_core_disable_irq( UART3_NVIC ); + break; + #endif + + #if defined(UART_MODULE_4) && defined(UART4_NVIC) + case hal_ll_uart_module_num(UART_MODULE_4): + hal_ll_core_disable_irq( UART4_NVIC ); + break; + #endif + + #if defined(UART_MODULE_5) && defined(UART5_NVIC) + case hal_ll_uart_module_num(UART_MODULE_5): + hal_ll_core_disable_irq( UART5_NVIC ); + break; + #endif + + + default: + break; + } + } +} + +void hal_ll_uart_write( handle_t *handle, uint8_t wr_data) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + hal_ll_hw_reg->tdr = wr_data; +} + +uint8_t hal_ll_uart_read( handle_t *handle ) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + return ( hal_ll_hw_reg->rdr ); +} + +// ------------------------------------------------------------- DEFAULT EXCEPTION HANDLERS + +#if defined(USART_MODULE_1) +void MARK_AS_IRQ_HANDLER UART1_IRQHandler() MIKROC_IV(UART1_NVIC) { + #ifdef USART_MODULE_1 + if( hal_ll_uart_get_status_flags( HAL_LL_USART1_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART1_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART1_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_1) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_USART1_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART1_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART1_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_1) ], HAL_LL_UART_IRQ_TX ); + } + } + #endif +} +#endif + +#if defined(USART_MODULE_2) +void MARK_AS_IRQ_HANDLER UART2_IRQHandler() MIKROC_IV(UART2_NVIC) { + #ifdef USART_MODULE_2 + if( hal_ll_uart_get_status_flags( HAL_LL_USART2_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART2_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART2_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_2) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_USART2_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART2_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART2_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_2) ], HAL_LL_UART_IRQ_TX ); + } + } + #endif +} +#endif + +#if defined(USART_MODULE_3) +void MARK_AS_IRQ_HANDLER UART3_IRQHandler() MIKROC_IV(UART3_NVIC) { + #ifdef USART_MODULE_3 + if( hal_ll_uart_get_status_flags( HAL_LL_USART3_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART3_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART3_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_3) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_USART3_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART3_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART3_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_3) ], HAL_LL_UART_IRQ_TX ); + } + } + #endif +} +#endif + +#if defined(UART_MODULE_4) +void MARK_AS_IRQ_HANDLER UART4_IRQHandler() MIKROC_IV(UART4_NVIC) { + #ifdef UART_MODULE_4 + if( hal_ll_uart_get_status_flags( HAL_LL_UART4_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_UART4_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_UART4_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(UART_MODULE_4) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_UART4_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_UART4_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_UART4_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(UART_MODULE_4) ], HAL_LL_UART_IRQ_TX ); + } + } + #endif +} +#endif + +#if defined(UART_MODULE_5) +void MARK_AS_IRQ_HANDLER UART5_IRQHandler() MIKROC_IV(UART5_NVIC) { + #ifdef UART_MODULE_5 + if( hal_ll_uart_get_status_flags( HAL_LL_UART5_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_UART5_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_UART5_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(UART_MODULE_5) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_UART5_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_UART5_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_UART5_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(UART_MODULE_5) ], HAL_LL_UART_IRQ_TX ); + } + } + #endif +} +#endif + +#if defined(LPUART_MODULE_1) +void MARK_AS_IRQ_HANDLER LPUART1_IRQHandler() MIKROC_IV(LPUART1_NVIC) { + #ifdef LPUART_MODULE_1 + if( hal_ll_uart_get_status_flags( HAL_LL_LPUART1_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_LPUART1_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_LPUART1_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(LPUART_MODULE_1) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_LPUART1_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_LPUART1_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_LPUART1_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(LPUART_MODULE_1) ], HAL_LL_UART_IRQ_TX ); + } + } + #endif +} +#endif + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static uint8_t hal_ll_uart_find_index( handle_t *handle ) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + if( hal_ll_uart_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + return hal_ll_uart_hw_specifics_map_local->module_index; + } else { + return NULL; + } +} + +static hal_ll_pin_name_t hal_ll_uart_check_pins( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_uart_pin_id *index_list, hal_ll_uart_handle_register_t *handle_map ) { + static const uint16_t tx_map_size = ( sizeof( hal_ll_uart_tx_map ) / sizeof( hal_ll_uart_pin_map_t ) ); + static const uint16_t rx_map_size = ( sizeof( hal_ll_uart_rx_map ) / sizeof( hal_ll_uart_pin_map_t ) ); + uint8_t hal_ll_module_id = 0; + uint8_t index_counter = 0; + uint16_t tx_index; + uint16_t rx_index; + + if ( (HAL_LL_PIN_NC == tx_pin) || (HAL_LL_PIN_NC == rx_pin) ) { + return HAL_LL_PIN_NC; + } + + for ( tx_index = 0; tx_index < tx_map_size; tx_index++ ) + { + if ( hal_ll_uart_tx_map[ tx_index ].pin == tx_pin ) + { + for ( rx_index = 0; rx_index < rx_map_size; rx_index++ ) + { + if ( hal_ll_uart_rx_map[ rx_index ].pin == rx_pin ) + { + if ( hal_ll_uart_tx_map[ tx_index ].base == hal_ll_uart_rx_map[ rx_index ].base ) { + // Get module number + hal_ll_module_id = hal_ll_uart_tx_map[ tx_index ].module_index; + + // Map pin names + index_list[hal_ll_module_id].pin_tx = tx_index; + index_list[hal_ll_module_id].pin_rx = rx_index; + + // Check if module is taken + if ( NULL == handle_map[ hal_ll_module_id ].hal_drv_uart_handle ) { + return hal_ll_module_id; + } else if ( UART_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static hal_ll_uart_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof(hal_ll_uart_handle_register_t)); + static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof(hal_ll_uart_handle_register_t)); + + while( hal_ll_module_count-- ) { + if (hal_ll_uart_get_base_from_hal_handle == hal_ll_uart_hw_specifics_map[hal_ll_module_count].base) { + return &hal_ll_uart_hw_specifics_map[hal_ll_module_count]; + } + } + + return &hal_ll_uart_hw_specifics_map[hal_ll_module_error]; +} + +static void hal_ll_uart_set_clock( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ) { + switch ( map->module_index ) + { + #ifdef UART_MODULE_1 + case ( hal_ll_uart_module_num(UART_MODULE_1) ): + (hal_ll_state == true)?(set_reg_bit( _RCC_APB2ENR, HAL_LL_USART1EN )):(clear_reg_bit( _RCC_APB2ENR, HAL_LL_USART1EN )); + break; + #endif + + #ifdef UART_MODULE_2 + case ( hal_ll_uart_module_num(UART_MODULE_2) ): + (hal_ll_state == true)?(set_reg_bit( _RCC_APB1ENR1, HAL_LL_USART2EN )):(clear_reg_bit( _RCC_APB1ENR1, HAL_LL_USART2EN )); + break; + #endif + + #ifdef UART_MODULE_3 + case ( hal_ll_uart_module_num(UART_MODULE_3) ): + (hal_ll_state == true)?(set_reg_bit( _RCC_APB1ENR1, HAL_LL_USART3EN )):(clear_reg_bit( _RCC_APB1ENR1, HAL_LL_USART3EN )); + break; + #endif + + #ifdef UART_MODULE_4 + case ( hal_ll_uart_module_num(UART_MODULE_4) ): + (hal_ll_state == true)?(set_reg_bit( _RCC_APB1ENR1, HAL_LL_USART4EN )):(clear_reg_bit( _RCC_APB1ENR1, HAL_LL_USART4EN )); + break; + #endif + + #ifdef UART_MODULE_5 + case ( hal_ll_uart_module_num(UART_MODULE_5) ): + (hal_ll_state == true)?(set_reg_bit( _RCC_APB1ENR1, HAL_LL_USART5EN )):(clear_reg_bit( _RCC_APB1ENR1, HAL_LL_USART5EN )); + break; + #endif + + + default: + break; + } +} + +static void hal_ll_uart_map_pins( uint8_t module_index, hal_ll_uart_pin_id *index_list ) { + // Map new pins + hal_ll_uart_hw_specifics_map[module_index].pins.tx_pin.pin_name = hal_ll_uart_tx_map[ index_list[module_index].pin_tx ].pin; + hal_ll_uart_hw_specifics_map[module_index].pins.rx_pin.pin_name = hal_ll_uart_rx_map[ index_list[module_index].pin_rx ].pin; + // TX and RX could have different alternate function settings, hence save both AF values + hal_ll_uart_hw_specifics_map[module_index].pins.tx_pin.pin_af = hal_ll_uart_tx_map[ index_list[module_index].pin_tx ].af; + hal_ll_uart_hw_specifics_map[module_index].pins.rx_pin.pin_af = hal_ll_uart_rx_map[ index_list[module_index].pin_rx ].af; +} + +static void hal_ll_uart_alternate_functions_set_state( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ) { + module_struct module; + + if ( (map->pins.tx_pin.pin_name != HAL_LL_PIN_NC) && map->pins.rx_pin.pin_name != HAL_LL_PIN_NC ) { + module.pins[0] = VALUE( map->pins.tx_pin.pin_name, map->pins.tx_pin.pin_af ); + module.pins[1] = VALUE( map->pins.rx_pin.pin_name, map->pins.rx_pin.pin_af ); + module.pins[2] = GPIO_MODULE_STRUCT_END; + + module.configs[0] = HAL_LL_UART_AF_CONFIG; + module.configs[1] = HAL_LL_UART_AF_CONFIG; + module.configs[2] = GPIO_MODULE_STRUCT_END; + + /* STM32F1xx specific */ + module.gpio_remap = map->pins.tx_pin.pin_af; + + hal_ll_gpio_module_struct_init( &module, hal_ll_state ); + } +} + +static void hal_ll_uart_set_baud_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + uint32_t reg = 0; + uint32_t integer_divider = 0; + uint32_t fractional_divider = 0; + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); + uint32_t hal_ll_baud_value = hal_ll_uart_get_baud(hal_ll_uart_get_clock_speed(map->module_index),map->baud_rate.baud,4); + uint32_t hal_ll_baud_real_value = hal_ll_uart_get_real_baud(hal_ll_uart_get_clock_speed(map->module_index),hal_ll_baud_value,4); + + // if error greater than specified, cancel setting baud rate + if( (hal_ll_uart_get_baud_error(hal_ll_baud_real_value,map->baud_rate.baud)) > HAL_LL_UART_ACCEPTABLE_ERROR ) { + map->baud_rate.real_baud = hal_ll_uart_get_baud_error(hal_ll_baud_real_value,map->baud_rate.baud); + } else { + map->baud_rate.real_baud = hal_ll_baud_real_value; + + integer_divider = ( ( 25 * hal_ll_uart_get_clock_speed( map->module_index ) ) / ( 4 * ( map->baud_rate.baud ) ) ); + reg = ( integer_divider / 100 ) << 4; + + fractional_divider = integer_divider - ( 100 * ( reg >> 4 ) ); + reg |= ( ( ( ( fractional_divider * 16 ) + 50 ) / 100 ) ) & 0x0F; + + hal_ll_hw_reg->brr = ( uint16_t )reg; + } +} + +static uint32_t hal_ll_uart_get_clock_speed( hal_ll_pin_name_t module_index ) { + rcc_clocks_t rcc_clocks; + + RCC_GetClocksFrequency( &rcc_clocks ); + + switch ( module_index ) + { + #ifdef UART_MODULE_1 + case ( hal_ll_uart_module_num(UART_MODULE_1) ): + return rcc_clocks.pclk2; + break; + #endif + + #ifdef UART_MODULE_2 + case ( hal_ll_uart_module_num(UART_MODULE_2) ): + return rcc_clocks.pclk1; + break; + #endif + + #ifdef UART_MODULE_3 + case ( hal_ll_uart_module_num(UART_MODULE_3) ): + return rcc_clocks.pclk1; + break; + #endif + + #ifdef UART_MODULE_4 + case ( hal_ll_uart_module_num(UART_MODULE_4) ): + return rcc_clocks.pclk1; + break; + #endif + + #ifdef UART_MODULE_5 + case ( hal_ll_uart_module_num(UART_MODULE_5) ): + return rcc_clocks.pclk1; + break; + #endif + + + default: + break; + } + + return NULL; +} + +static void hal_ll_uart_set_stop_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); + + switch ( map->stop_bit ) + { + case HAL_LL_UART_STOP_BITS_HALF: + hal_ll_hw_reg->cr2 |= STOP_BITS_HALF; + break; + case HAL_LL_UART_STOP_BITS_ONE: + hal_ll_hw_reg->cr2 |= STOP_BITS_ONE; + break; + case HAL_LL_UART_STOP_BITS_ONE_AND_A_HALF: + hal_ll_hw_reg->cr2 |= STOP_BITS_ONE_AND_A_HALF; + break; + case HAL_LL_UART_STOP_BITS_TWO: + hal_ll_hw_reg->cr2 |= STOP_BITS_TWO; + break; + + default: + break; + } +} + +static void hal_ll_uart_set_data_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); + + switch ( map->data_bit ) + { + case HAL_LL_UART_DATA_BITS_7: + hal_ll_hw_reg->cr1 |= DATA_BIT_7; + break; + + case HAL_LL_UART_DATA_BITS_8: + hal_ll_hw_reg->cr1 |= DATA_BIT_8; + break; + + case HAL_LL_UART_DATA_BITS_9: + hal_ll_hw_reg->cr1 |= DATA_BIT_9; + break; + + + default: + break; + } +} + +static void hal_ll_uart_set_parity_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); + + switch ( map->parity ) + { + case HAL_LL_UART_PARITY_NONE: + hal_ll_hw_reg->cr1 |= PARITY_NO; + break; + case HAL_LL_UART_PARITY_EVEN: + hal_ll_hw_reg->cr1 |= PARITY_ENABLED | PARITY_EVEN; + break; + case HAL_LL_UART_PARITY_ODD: + hal_ll_hw_reg->cr1 |= PARITY_ENABLED | PARITY_ODD; + break; + + default: + break; + } +} + +static void hal_ll_uart_set_module( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ) { + switch ( pin_state ) + { + case HAL_LL_UART_DISABLE: + clear_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_UE ); + break; + + case HAL_LL_UART_ENABLE: + set_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_UE ); + break; + + default: + break; + } +} + +static void hal_ll_uart_set_transmitter( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ) { + switch ( pin_state ) + { + case HAL_LL_UART_DISABLE: + clear_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_TE ); + break; + + case HAL_LL_UART_ENABLE: + set_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_TE ); + break; + + default: + break; + } +} + +static void hal_ll_uart_set_receiver( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ) { + switch ( pin_state ) + { + case HAL_LL_UART_DISABLE: + clear_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_RE ); + break; + + case HAL_LL_UART_ENABLE: + set_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_RE ); + break; + + default: + break; + } +} + +static void hal_ll_uart_clear_regs( hal_ll_uart_base_handle_t *hal_ll_hw_reg ) { + hal_ll_hw_reg->cr1 &= HAL_LL_UART_IT_CR1_MASK; + hal_ll_hw_reg->cr2 &= HAL_LL_UART_IT_CR2_MASK; + hal_ll_hw_reg->cr3 &= HAL_LL_UART_IT_CR3_MASK; +} + +static void hal_ll_uart_hw_init( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_clear_regs( map->base ); + + hal_ll_uart_set_data_bits_bare_metal( map ); + + hal_ll_uart_set_parity_bare_metal( map ); + + hal_ll_uart_set_stop_bits_bare_metal( map ); + + hal_ll_uart_set_baud_bare_metal( map ); + + hal_ll_uart_set_transmitter( map->base, HAL_LL_UART_ENABLE ); + + hal_ll_uart_set_receiver( map->base, HAL_LL_UART_ENABLE ); + + hal_ll_uart_set_module( map->base, HAL_LL_UART_ENABLE ); +} + +static void hal_ll_uart_init( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_set_clock( map, true ); + + hal_ll_uart_alternate_functions_set_state( map, true ); + + hal_ll_uart_hw_init( map ); +} +// ------------------------------------------------------------------------- END + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_85/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_85/CMakeLists.cmake new file mode 100644 index 000000000..dfe6e7848 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_85/CMakeLists.cmake @@ -0,0 +1,9 @@ +if(${MCU_NAME} MATCHES "^STM32G474CB$|^STM32G474MB$|^STM32G474RB$|^STM32G474VB$|^STM32G474QB$|^STM32G474PB$|^STM32G474CC$|^STM32G474MC$|^STM32G474RC$|^STM32G474VC$|^STM32G474QC$|^STM32G474PC$|^STM32G474CE$|^STM32G474ME$|^STM32G474RE$|^STM32G474VE$|^STM32G474QE$|^STM32G474PE$") + set(uart_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_uart.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_85") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_85") + list(APPEND hal_ll_def_list "STM32G4xx") + list(APPEND hal_ll_def_list "STM32G47xx") + list(APPEND hal_ll_def_list "STM32G474xx") + set(uart_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/uart/hal_ll_uart_pin_map/implementations/doc_ds_85") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_85/hal_ll_uart.c b/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_85/hal_ll_uart.c new file mode 100644 index 000000000..f6304e601 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_85/hal_ll_uart.c @@ -0,0 +1,1255 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_uart.c + * @brief UART HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_rcc.h" +#include "hal_ll_uart.h" +#include "hal_ll_gpio.h" +#include "hal_ll_core.h" +#include "hal_ll_core_defines.h" +#include "hal_ll_uart_pin_map.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_uart_handle_register_t hal_ll_module_state[UART_MODULE_COUNT] = { (handle_t *)NULL, (handle_t *)NULL, false }; + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_uart_get_module_state_address ((hal_ll_uart_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_uart_get_handle (hal_ll_uart_handle_register_t *)hal_ll_uart_get_module_state_address->hal_ll_uart_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_uart_get_base_struct(_handle) ((hal_ll_uart_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_uart_get_base_from_hal_handle ((hal_ll_uart_hw_specifics_map_t *)((hal_ll_uart_handle_register_t *)\ + (((hal_ll_uart_handle_register_t *)(handle))->hal_ll_uart_handle))->hal_ll_uart_handle)->base + +/*!< @brief Macros used for calculating actual baud rate value and error value */ +#define HAL_LL_UART_ACCEPTABLE_ERROR (float)1.0 +#define hal_ll_uart_get_baud(_clock,_baud,_div) (((_clock/(float)_baud)/_div)-1) +#define hal_ll_uart_get_real_baud(_clock,_baud,_div) (_clock/(_div*(_baud+1))) +#define hal_ll_uart_get_baud_error(_baud_real,_baud) (((float)(abs(_baud_real-_baud))/_baud)*100) + +/*!< @brief Macros defining bit location */ +#define HAL_LL_USART1EN 14 + +#define HAL_LL_USART2EN 17 + +#define HAL_LL_USART3EN 18 + +#define HAL_LL_USART4EN 19 + +#define HAL_LL_USART5EN 20 + + +#define HAL_LL_UART_CR1_UE 0 +#define HAL_LL_UART_CR1_TE 3 +#define HAL_LL_UART_CR1_RE 2 + +#define HAL_LL_UART_SR_RXNE 5 +#define HAL_LL_UART_SR_TXE 7 + +/*!< @brief Macros defining register bit values */ +#define STOP_BITS_HALF 0x1000U +#define STOP_BITS_ONE 0x00U +#define STOP_BITS_ONE_AND_A_HALF 0x3000U +#define STOP_BITS_TWO 0x2000U + +#define DATA_BIT_7 0x10000000U +#define DATA_BIT_8 0x00U +#define DATA_BIT_9 0x1000U + +#define PARITY_NO 0x00U +#define PARITY_ENABLED 0x400U + +#define PARITY_EVEN 0x00U +#define PARITY_ODD 0x200U + +/*!< @brief Macro used for setting pin alternate functions */ +#define HAL_LL_UART_AF_CONFIG (GPIO_CFG_MODE_ALT_FUNCTION | GPIO_CFG_SPEED_HIGH | GPIO_CFG_OTYPE_PP) + +/*!< @brief Macros used for interrupts */ +#define HAL_LL_UART_IT_MASK 0xFFFFUL +#define HAL_LL_UART_IT_CLEAR_MASK 0x123afeU +#define HAL_LL_UART_IT_CR1_MASK 0x1f0U +#define HAL_LL_UART_IT_CR2_MASK 0x40U +#define HAL_LL_UART_IT_CR3_MASK 0x401U + +#define HAL_LL_UART_CR1_REG_INDEX 1 +#define HAL_LL_UART_CR2_REG_INDEX 2 +#define HAL_LL_UART_CR3_REG_INDEX 3 + +#define HAL_LL_UART_IT_PE 0x100U +#define HAL_LL_UART_IT_TXE (0x10000000 | 0x80U) +#define HAL_LL_UART_IT_TC 0x40U +#define HAL_LL_UART_IT_RXNE (0x10000000 | 0x20U) +#define HAL_LL_UART_IT_IDLE 0x10U +#define HAL_LL_UART_IT_LBD 0x40U +#define HAL_LL_UART_IT_CTS 0x400U +#define HAL_LL_UART_IT_ERR 0x01U + +#define HAL_LL_UART_STATUS_RXNE_FLAG 0x20U +#define HAL_LL_UART_STATUS_TXE_FLAG 0x80U + +/*!< @brief Macro used for status registed flag check + * Used in interrupt handlers. + */ +#define hal_ll_uart_get_status_flags(_handle,_flag) (((hal_ll_uart_base_handle_t *)_handle)->isr & _flag) + +/*!< @brief Macro used for status register flag clearing + * Used in interrupt handlers. + */ +#define hal_ll_uart_clear_status_flag(_handle,_flag) (set_reg_bit( &(((hal_ll_uart_base_handle_t *)_handle)->icr), ( _flag & HAL_LL_UART_IT_CLEAR_MASK ) ) ) + +/*!< @brief Macro used for module interrupt enabling. + * Used in interrupt handlers. + */ +#define __HAL_LL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__ >> 28UL) == HAL_LL_UART_CR1_REG_INDEX)? (__HANDLE__->cr1 |= (__INTERRUPT__ & HAL_LL_UART_IT_MASK)): \ + ((__INTERRUPT__ >> 28UL) == HAL_LL_UART_CR2_REG_INDEX)? (__HANDLE__->cr2 |= (__INTERRUPT__ & HAL_LL_UART_IT_MASK)): \ + (__HANDLE__->cr3 |= (__INTERRUPT__ & HAL_LL_UART_IT_MASK))) + +/*!< @brief Macro used for module interrupt disabling. + * Used in interrupt handlers. + */ +#define __HAL_LL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__ >> 28UL) == HAL_LL_UART_CR1_REG_INDEX)? (__HANDLE__->cr1 &= ~(__INTERRUPT__ & HAL_LL_UART_IT_MASK)): \ + ((__INTERRUPT__ >> 28UL) == HAL_LL_UART_CR2_REG_INDEX)? (__HANDLE__->cr2 &= ~(__INTERRUPT__ & HAL_LL_UART_IT_MASK)): \ + (__HANDLE__->cr3 &= ~ (__INTERRUPT__ & HAL_LL_UART_IT_MASK))) + +/*!< @brief Macro used for module interrupt source check. + * Used in interrupt handlers. + */ +#define __HAL_LL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__ >> 28UL) == 1UL)? ((hal_ll_uart_base_handle_t *)__HANDLE__)->cr1:((((uint32_t)__INTERRUPT__ >> 28UL) == 2UL)? \ + ((hal_ll_uart_base_handle_t *)__HANDLE__)->cr2 : ((hal_ll_uart_base_handle_t *)__HANDLE__)->cr3)) & ((uint32_t)__INTERRUPT__ & HAL_LL_UART_IT_MASK)) + +/*!< @brief UART HW register structure */ +typedef struct +{ + hal_ll_base_addr_t cr1; + hal_ll_base_addr_t cr2; + hal_ll_base_addr_t cr3; + hal_ll_base_addr_t brr; + hal_ll_base_addr_t gtpr; + hal_ll_base_addr_t rtor; + hal_ll_base_addr_t rqr; + hal_ll_base_addr_t isr; + hal_ll_base_addr_t icr; + hal_ll_base_addr_t rdr; + hal_ll_base_addr_t tdr; + hal_ll_base_addr_t presc; + +} hal_ll_uart_base_handle_t; + +/*!< @brief UART baud rate structure */ +typedef struct +{ + uint32_t baud; + uint32_t real_baud; +} hal_ll_uart_baud_t; + +/*!< @brief UART hw specific structure */ +typedef struct +{ + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + hal_ll_uart_pins_t pins; + hal_ll_uart_baud_t baud_rate; + hal_ll_uart_parity_t parity; + hal_ll_uart_stop_bits_t stop_bit; + hal_ll_uart_data_bits_t data_bit; +} hal_ll_uart_hw_specifics_map_t; + +/*!< @brief UART hw specific module values */ +typedef struct +{ + uint16_t pin_tx; + uint16_t pin_rx; +} hal_ll_uart_pin_id; + +/*!< @brief UART hw specific error values */ +typedef enum +{ + HAL_LL_UART_SUCCESS = 0, + HAL_LL_UART_WRONG_PINS, + HAL_LL_UART_MODULE_ERROR, + + HAL_LL_UART_ERROR = (-1) +} hal_ll_uart_err_t; + +/*!< @brief UART module state selection */ +typedef enum +{ + HAL_LL_UART_DISABLE = 0, + HAL_LL_UART_ENABLE +} hal_ll_uart_state_t; + +// ------------------------------------------------------------------ VARIABLES +/*!< @brief UART hardware specific info */ +static hal_ll_uart_hw_specifics_map_t hal_ll_uart_hw_specifics_map[] = +{ + #ifdef UART_MODULE_1 + {HAL_LL_UART1_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_1), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + + #ifdef UART_MODULE_2 + {HAL_LL_UART2_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_2), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + + #ifdef UART_MODULE_3 + {HAL_LL_UART3_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_3), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + + #ifdef UART_MODULE_4 + {HAL_LL_UART4_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_4), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + + #ifdef UART_MODULE_5 + {HAL_LL_UART5_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_5), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + + + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {0, 0}, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR} +}; + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_uart_handle_register_t *low_level_handle; +static volatile hal_ll_uart_hw_specifics_map_t *hal_ll_uart_hw_specifics_map_local; + +/*!< @brief Global interrupt handlers used in functions */ +static hal_ll_uart_isr_t irq_handler; +static handle_t objects[UART_MODULE_COUNT]; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Check if pins are adequate. + * + * Checks tx and rx pins the user has passed with pre-defined + * pins in tx and rx maps. Take into consideration that module + * index numbers have to be the same for both pins. + * + * @param[in] tx_pin - TX pre-defined pin name. + * @param[in] rx_pin - RX pre-defined pin name. + * @param[in] *index_list - Array containing map index numbers. + * @return hal_ll_pin_name_t Module index based on pins. + * + * Returns pre-defined module index from pin maps, if pins + * are adequate. + */ +static hal_ll_pin_name_t hal_ll_uart_check_pins( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_uart_pin_id *index_list, hal_ll_uart_handle_register_t *handle_map ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * TX and RX pins. + * + * @param[in] module_index UART HW module index -- 0,1,2... + * @param[in] *index_list Array with TX and RX map index values + * and module number + * + * @return None + */ +static void hal_ll_uart_map_pins( uint8_t module_index, hal_ll_uart_pin_id *index_list ); + +/** + * @brief Sets UART pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if UART is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_state - Init/De-init + * + * @return void None. + */ +static void hal_ll_uart_alternate_functions_set_state( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_uart_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_uart_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_uart_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Enable clock for UART module on hardware level. + * + * Initializes UART module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_stat - True(enable clock)/False(disable clock). + * + * @return void None. + */ +static void hal_ll_uart_set_clock( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Finds UART module index. + * + * Finds UART index(module number) based on + * handle value. + * + * @param[in] handle - Object specific context handler. + * + * @return uint8_t Module number. + * Returns values from 0 to 9. + */ +static uint8_t hal_ll_uart_find_index( handle_t *handle ); + +/** + * @brief Get UART module clock speed. + * + * Returns adequate clock speed based on + * UART module base address. + * + * @param[in] module_index - UART module index number. + * + * @return uint8_t Module number. + * Returns clock value. + */ +static uint32_t hal_ll_uart_get_clock_speed( hal_ll_pin_name_t module_index ); + +/** + * @brief Clears UART registers. + * + * Clears UART module configuration + * registers, effectively disabling the module itself. + * Take into consideration that any IRQ bits + * are not cleared. + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * + * @return void None. + */ +static void hal_ll_uart_clear_regs( hal_ll_uart_base_handle_t *hal_ll_hw_reg ); + +/** + * @brief Sets desired baud rate on hardware level. + * + * Initializes module with specified baud rate value. + * Take into consideration that if the difference + * between desired baud rate and actual baud + * rate the hw was initialized to is greater than + * 1%, baud rate shall not be set. + * If this occurs, return value shall be + * the error percentage. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_set_baud_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Sets desired stop bits. + * + * Initializes module on hardware level + * with specified stop bit value. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_set_stop_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Sets desired data bits. + * + * Initializes module on hardware level + * with specified data bit bit value. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_set_data_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Sets desired parity. + * + * Initializes module on hardware level + * with specified parity value. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_set_parity_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Sets module clock value. + * + * Enables/disables specific UART module + * clock gate. + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * @param[in] pin_state - true(enable clock) / false(disable clock) + * + * @return void None. + */ +static void hal_ll_uart_set_module( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ); + +/** + * @brief Sets module TX line state. + * + * Enables/disables specific UART module + * TX pin state + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * @param[in] pin_state - true(enable transmitter pin) / false(disable transmitter pin) + * + * @return void None. + */ +static void hal_ll_uart_set_transmitter( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ); + +/** + * @brief Sets module RX line state. + * + * Enables/disables specific UART module + * RX pin state + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * @param[in] pin_state - true(enable receive pin) / false(disable receive pin) + * + * @return void None. + */ +static void hal_ll_uart_set_receiver( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ); + +/** + * @brief Initialize UART module. + * + * Enables UART module clogk gate first. + * Sets pin alternate function state. + * Initializes specific UART module. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_init( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Initialize UART module on the hardware level. + * + * Performs UART module initialization on + * the hardware level. + * + * Procedure: + * 1. Clears control registers + * 2. Sets data bit value + * 3. Sets parity value + * 4. Sets stop bit value + * 5. Sets baud rate value + * 6. Enables transmit pin + * 7. Enables receive pin + * 8. Enables clock gate for specific module + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_hw_init( hal_ll_uart_hw_specifics_map_t *map ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_uart_register_handle( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_uart_handle_register_t *handle_map, uint8_t *hal_module_id ) { + + hal_ll_uart_pin_id index_list[UART_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + uint16_t pin_check_result; + + // Check if pins are valid + if ( (pin_check_result = hal_ll_uart_check_pins( tx_pin, rx_pin, &index_list, handle_map )) == HAL_LL_PIN_NC ) { + return HAL_LL_UART_WRONG_PINS; + }; + + if ( (hal_ll_uart_hw_specifics_map[pin_check_result].pins.tx_pin.pin_name != tx_pin) || + (hal_ll_uart_hw_specifics_map[pin_check_result].pins.rx_pin.pin_name != rx_pin) ) + { + hal_ll_uart_alternate_functions_set_state( &hal_ll_uart_hw_specifics_map[ pin_check_result ], false ); + + hal_ll_uart_map_pins( pin_check_result, &index_list ); + + hal_ll_uart_alternate_functions_set_state( &hal_ll_uart_hw_specifics_map[ pin_check_result ], true ); + + handle_map[pin_check_result].init_ll_state = false; + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[pin_check_result].hal_ll_uart_handle = (handle_t *)&hal_ll_uart_hw_specifics_map[pin_check_result].base; + + handle_map[pin_check_result].hal_ll_uart_handle = (handle_t *)&hal_ll_module_state[pin_check_result].hal_ll_uart_handle; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_uart( handle_t *handle ) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + hal_ll_uart_pin_id index_list[UART_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + uint16_t pin_check_result; + + if ( (pin_check_result = hal_ll_uart_check_pins( hal_ll_uart_hw_specifics_map_local->pins.tx_pin.pin_name, + hal_ll_uart_hw_specifics_map_local->pins.rx_pin.pin_name, &index_list, (void *)0 ) ) == HAL_LL_PIN_NC ) { + return HAL_LL_UART_WRONG_PINS; + }; + + hal_ll_uart_init( hal_ll_uart_hw_specifics_map_local ); + + hal_ll_module_state[pin_check_result].hal_ll_uart_handle = (handle_t *)&hal_ll_uart_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_uart_set_baud( handle_t *handle, uint32_t baud ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->baud_rate.baud = baud; + + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return hal_ll_uart_hw_specifics_map_local->baud_rate.real_baud; +} + +hal_ll_err_t hal_ll_uart_set_parity( handle_t *handle, hal_ll_uart_parity_t parity ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->parity = parity; + + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_uart_set_stop_bits( handle_t *handle, hal_ll_uart_stop_bits_t stop_bit ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->stop_bit = stop_bit; + + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_uart_set_data_bits( handle_t *handle, hal_ll_uart_data_bits_t data_bit ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + // Chips using implementation 1 do not support 7 bit data + if( data_bit == HAL_LL_UART_DATA_BITS_7 ) { + return HAL_LL_UART_MODULE_ERROR; + } + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->data_bit = data_bit; + + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +void hal_ll_uart_close( handle_t *handle ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + if( low_level_handle->hal_ll_uart_handle != NULL ) { + hal_ll_uart_alternate_functions_set_state( hal_ll_uart_hw_specifics_map_local, false ); + + hal_ll_uart_irq_disable(handle, HAL_LL_UART_IRQ_RX); + hal_ll_uart_irq_disable(handle, HAL_LL_UART_IRQ_TX); + + hal_ll_uart_clear_regs(hal_ll_uart_hw_specifics_map_local->base); + hal_ll_uart_set_clock(hal_ll_uart_hw_specifics_map_local, false); + + hal_ll_uart_hw_specifics_map_local->pins.tx_pin.pin_name = HAL_LL_PIN_NC; + hal_ll_uart_hw_specifics_map_local->pins.tx_pin.pin_af = 0; + hal_ll_uart_hw_specifics_map_local->pins.rx_pin.pin_name = HAL_LL_PIN_NC; + hal_ll_uart_hw_specifics_map_local->pins.rx_pin.pin_af = 0; + + hal_ll_uart_hw_specifics_map_local->baud_rate.baud = 115200UL; + hal_ll_uart_hw_specifics_map_local->baud_rate.real_baud = 0; + + irq_handler = NULL; + objects[ hal_ll_uart_find_index( handle ) ] = NULL; + + low_level_handle->hal_ll_uart_handle = NULL; + low_level_handle->hal_drv_uart_handle = NULL; + + low_level_handle->init_ll_state = false; + } +} + +void hal_ll_uart_register_irq_handler( handle_t *handle, hal_ll_uart_isr_t handler, handle_t obj ) +{ + irq_handler = handler; + objects[ hal_ll_uart_find_index( handle ) ] = obj; +} + +void hal_ll_uart_irq_enable( handle_t *handle, hal_ll_uart_irq_t irq ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + switch ( irq ) { + case HAL_LL_UART_IRQ_RX: + __HAL_LL_UART_ENABLE_IT( hal_ll_hw_reg, HAL_LL_UART_IT_RXNE ); + break; + + case HAL_LL_UART_IRQ_TX: + __HAL_LL_UART_ENABLE_IT( hal_ll_hw_reg, HAL_LL_UART_IT_TXE ); + break; + + default: + break; + } + + switch ( hal_ll_uart_hw_specifics_map_local->module_index ) + { + #if defined(UART_MODULE_1) && defined(UART1_NVIC) + case hal_ll_uart_module_num(UART_MODULE_1): + hal_ll_core_enable_irq( UART1_NVIC ); + break; + #endif + + #if defined(UART_MODULE_2) && defined(UART2_NVIC) + case hal_ll_uart_module_num(UART_MODULE_2): + hal_ll_core_enable_irq( UART2_NVIC ); + break; + #endif + + #if defined(UART_MODULE_3) && defined(UART3_NVIC) + case hal_ll_uart_module_num(UART_MODULE_3): + hal_ll_core_enable_irq( UART3_NVIC ); + break; + #endif + + #if defined(UART_MODULE_4) && defined(UART4_NVIC) + case hal_ll_uart_module_num(UART_MODULE_4): + hal_ll_core_enable_irq( UART4_NVIC ); + break; + #endif + + #if defined(UART_MODULE_5) && defined(UART5_NVIC) + case hal_ll_uart_module_num(UART_MODULE_5): + hal_ll_core_enable_irq( UART5_NVIC ); + break; + #endif + + + default: + break; + } +} + +void hal_ll_uart_irq_disable( handle_t *handle, hal_ll_uart_irq_t irq ) +{ + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + switch ( irq ) { + case HAL_LL_UART_IRQ_RX: + __HAL_LL_UART_DISABLE_IT( hal_ll_hw_reg, HAL_LL_UART_IT_RXNE ); + break; + + case HAL_LL_UART_IRQ_TX: + __HAL_LL_UART_DISABLE_IT( hal_ll_hw_reg, HAL_LL_UART_IT_TXE ); + break; + + default: + break; + } + + // Check if module interrupt flags are set or not + if ( ( !check_reg_bit( &hal_ll_hw_reg->cr1, HAL_LL_UART_SR_RXNE ) ) && + ( !check_reg_bit( &hal_ll_hw_reg->cr1, HAL_LL_UART_SR_TXE ) ) ) + { + switch ( hal_ll_uart_hw_specifics_map_local->module_index ) + { + #if defined(UART_MODULE_1) && defined(UART1_NVIC) + case hal_ll_uart_module_num(UART_MODULE_1): + hal_ll_core_disable_irq( UART1_NVIC ); + break; + #endif + + #if defined(UART_MODULE_2) && defined(UART2_NVIC) + case hal_ll_uart_module_num(UART_MODULE_2): + hal_ll_core_disable_irq( UART2_NVIC ); + break; + #endif + + #if defined(UART_MODULE_3) && defined(UART3_NVIC) + case hal_ll_uart_module_num(UART_MODULE_3): + hal_ll_core_disable_irq( UART3_NVIC ); + break; + #endif + + #if defined(UART_MODULE_4) && defined(UART4_NVIC) + case hal_ll_uart_module_num(UART_MODULE_4): + hal_ll_core_disable_irq( UART4_NVIC ); + break; + #endif + + #if defined(UART_MODULE_5) && defined(UART5_NVIC) + case hal_ll_uart_module_num(UART_MODULE_5): + hal_ll_core_disable_irq( UART5_NVIC ); + break; + #endif + + + default: + break; + } + } +} + +void hal_ll_uart_write( handle_t *handle, uint8_t wr_data) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + hal_ll_hw_reg->tdr = wr_data; +} + +uint8_t hal_ll_uart_read( handle_t *handle ) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + return ( hal_ll_hw_reg->rdr ); +} + +// ------------------------------------------------------------- DEFAULT EXCEPTION HANDLERS + +#if defined(USART_MODULE_1) +void MARK_AS_IRQ_HANDLER UART1_IRQHandler() MIKROC_IV(UART1_NVIC) { + #ifdef USART_MODULE_1 + if( hal_ll_uart_get_status_flags( HAL_LL_USART1_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART1_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART1_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_1) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_USART1_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART1_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART1_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_1) ], HAL_LL_UART_IRQ_TX ); + } + } + #endif +} +#endif + +#if defined(USART_MODULE_2) +void MARK_AS_IRQ_HANDLER UART2_IRQHandler() MIKROC_IV(UART2_NVIC) { + #ifdef USART_MODULE_2 + if( hal_ll_uart_get_status_flags( HAL_LL_USART2_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART2_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART2_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_2) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_USART2_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART2_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART2_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_2) ], HAL_LL_UART_IRQ_TX ); + } + } + #endif +} +#endif + +#if defined(USART_MODULE_3) +void MARK_AS_IRQ_HANDLER UART3_IRQHandler() MIKROC_IV(UART3_NVIC) { + #ifdef USART_MODULE_3 + if( hal_ll_uart_get_status_flags( HAL_LL_USART3_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART3_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART3_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_3) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_USART3_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART3_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART3_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_3) ], HAL_LL_UART_IRQ_TX ); + } + } + #endif +} +#endif + +#if defined(UART_MODULE_4) +void MARK_AS_IRQ_HANDLER UART4_IRQHandler() MIKROC_IV(UART4_NVIC) { + #ifdef UART_MODULE_4 + if( hal_ll_uart_get_status_flags( HAL_LL_UART4_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_UART4_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_UART4_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(UART_MODULE_4) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_UART4_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_UART4_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_UART4_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(UART_MODULE_4) ], HAL_LL_UART_IRQ_TX ); + } + } + #endif +} +#endif + +#if defined(UART_MODULE_5) +void MARK_AS_IRQ_HANDLER UART5_IRQHandler() MIKROC_IV(UART5_NVIC) { + #ifdef UART_MODULE_5 + if( hal_ll_uart_get_status_flags( HAL_LL_UART5_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_UART5_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_UART5_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(UART_MODULE_5) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_UART5_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_UART5_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_UART5_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(UART_MODULE_5) ], HAL_LL_UART_IRQ_TX ); + } + } + #endif +} +#endif + +#if defined(LPUART_MODULE_1) +void MARK_AS_IRQ_HANDLER LPUART1_IRQHandler() MIKROC_IV(LPUART1_NVIC) { + #ifdef LPUART_MODULE_1 + if( hal_ll_uart_get_status_flags( HAL_LL_LPUART1_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_LPUART1_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_LPUART1_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(LPUART_MODULE_1) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_LPUART1_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_LPUART1_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_LPUART1_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(LPUART_MODULE_1) ], HAL_LL_UART_IRQ_TX ); + } + } + #endif +} +#endif + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static uint8_t hal_ll_uart_find_index( handle_t *handle ) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + if( hal_ll_uart_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + return hal_ll_uart_hw_specifics_map_local->module_index; + } else { + return NULL; + } +} + +static hal_ll_pin_name_t hal_ll_uart_check_pins( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_uart_pin_id *index_list, hal_ll_uart_handle_register_t *handle_map ) { + static const uint16_t tx_map_size = ( sizeof( hal_ll_uart_tx_map ) / sizeof( hal_ll_uart_pin_map_t ) ); + static const uint16_t rx_map_size = ( sizeof( hal_ll_uart_rx_map ) / sizeof( hal_ll_uart_pin_map_t ) ); + uint8_t hal_ll_module_id = 0; + uint8_t index_counter = 0; + uint16_t tx_index; + uint16_t rx_index; + + if ( (HAL_LL_PIN_NC == tx_pin) || (HAL_LL_PIN_NC == rx_pin) ) { + return HAL_LL_PIN_NC; + } + + for ( tx_index = 0; tx_index < tx_map_size; tx_index++ ) + { + if ( hal_ll_uart_tx_map[ tx_index ].pin == tx_pin ) + { + for ( rx_index = 0; rx_index < rx_map_size; rx_index++ ) + { + if ( hal_ll_uart_rx_map[ rx_index ].pin == rx_pin ) + { + if ( hal_ll_uart_tx_map[ tx_index ].base == hal_ll_uart_rx_map[ rx_index ].base ) { + // Get module number + hal_ll_module_id = hal_ll_uart_tx_map[ tx_index ].module_index; + + // Map pin names + index_list[hal_ll_module_id].pin_tx = tx_index; + index_list[hal_ll_module_id].pin_rx = rx_index; + + // Check if module is taken + if ( NULL == handle_map[ hal_ll_module_id ].hal_drv_uart_handle ) { + return hal_ll_module_id; + } else if ( UART_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static hal_ll_uart_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof(hal_ll_uart_handle_register_t)); + static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof(hal_ll_uart_handle_register_t)); + + while( hal_ll_module_count-- ) { + if (hal_ll_uart_get_base_from_hal_handle == hal_ll_uart_hw_specifics_map[hal_ll_module_count].base) { + return &hal_ll_uart_hw_specifics_map[hal_ll_module_count]; + } + } + + return &hal_ll_uart_hw_specifics_map[hal_ll_module_error]; +} + +static void hal_ll_uart_set_clock( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ) { + switch ( map->module_index ) + { + #ifdef UART_MODULE_1 + case ( hal_ll_uart_module_num(UART_MODULE_1) ): + (hal_ll_state == true)?(set_reg_bit( _RCC_APB2ENR, HAL_LL_USART1EN )):(clear_reg_bit( _RCC_APB2ENR, HAL_LL_USART1EN )); + break; + #endif + + #ifdef UART_MODULE_2 + case ( hal_ll_uart_module_num(UART_MODULE_2) ): + (hal_ll_state == true)?(set_reg_bit( _RCC_APB1ENR1, HAL_LL_USART2EN )):(clear_reg_bit( _RCC_APB1ENR1, HAL_LL_USART2EN )); + break; + #endif + + #ifdef UART_MODULE_3 + case ( hal_ll_uart_module_num(UART_MODULE_3) ): + (hal_ll_state == true)?(set_reg_bit( _RCC_APB1ENR1, HAL_LL_USART3EN )):(clear_reg_bit( _RCC_APB1ENR1, HAL_LL_USART3EN )); + break; + #endif + + #ifdef UART_MODULE_4 + case ( hal_ll_uart_module_num(UART_MODULE_4) ): + (hal_ll_state == true)?(set_reg_bit( _RCC_APB1ENR1, HAL_LL_USART4EN )):(clear_reg_bit( _RCC_APB1ENR1, HAL_LL_USART4EN )); + break; + #endif + + #ifdef UART_MODULE_5 + case ( hal_ll_uart_module_num(UART_MODULE_5) ): + (hal_ll_state == true)?(set_reg_bit( _RCC_APB1ENR1, HAL_LL_USART5EN )):(clear_reg_bit( _RCC_APB1ENR1, HAL_LL_USART5EN )); + break; + #endif + + + default: + break; + } +} + +static void hal_ll_uart_map_pins( uint8_t module_index, hal_ll_uart_pin_id *index_list ) { + // Map new pins + hal_ll_uart_hw_specifics_map[module_index].pins.tx_pin.pin_name = hal_ll_uart_tx_map[ index_list[module_index].pin_tx ].pin; + hal_ll_uart_hw_specifics_map[module_index].pins.rx_pin.pin_name = hal_ll_uart_rx_map[ index_list[module_index].pin_rx ].pin; + // TX and RX could have different alternate function settings, hence save both AF values + hal_ll_uart_hw_specifics_map[module_index].pins.tx_pin.pin_af = hal_ll_uart_tx_map[ index_list[module_index].pin_tx ].af; + hal_ll_uart_hw_specifics_map[module_index].pins.rx_pin.pin_af = hal_ll_uart_rx_map[ index_list[module_index].pin_rx ].af; +} + +static void hal_ll_uart_alternate_functions_set_state( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ) { + module_struct module; + + if ( (map->pins.tx_pin.pin_name != HAL_LL_PIN_NC) && map->pins.rx_pin.pin_name != HAL_LL_PIN_NC ) { + module.pins[0] = VALUE( map->pins.tx_pin.pin_name, map->pins.tx_pin.pin_af ); + module.pins[1] = VALUE( map->pins.rx_pin.pin_name, map->pins.rx_pin.pin_af ); + module.pins[2] = GPIO_MODULE_STRUCT_END; + + module.configs[0] = HAL_LL_UART_AF_CONFIG; + module.configs[1] = HAL_LL_UART_AF_CONFIG; + module.configs[2] = GPIO_MODULE_STRUCT_END; + + /* STM32F1xx specific */ + module.gpio_remap = map->pins.tx_pin.pin_af; + + hal_ll_gpio_module_struct_init( &module, hal_ll_state ); + } +} + +static void hal_ll_uart_set_baud_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + uint32_t reg = 0; + uint32_t integer_divider = 0; + uint32_t fractional_divider = 0; + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); + uint32_t hal_ll_baud_value = hal_ll_uart_get_baud(hal_ll_uart_get_clock_speed(map->module_index),map->baud_rate.baud,4); + uint32_t hal_ll_baud_real_value = hal_ll_uart_get_real_baud(hal_ll_uart_get_clock_speed(map->module_index),hal_ll_baud_value,4); + + // if error greater than specified, cancel setting baud rate + if( (hal_ll_uart_get_baud_error(hal_ll_baud_real_value,map->baud_rate.baud)) > HAL_LL_UART_ACCEPTABLE_ERROR ) { + map->baud_rate.real_baud = hal_ll_uart_get_baud_error(hal_ll_baud_real_value,map->baud_rate.baud); + } else { + map->baud_rate.real_baud = hal_ll_baud_real_value; + + integer_divider = ( ( 25 * hal_ll_uart_get_clock_speed( map->module_index ) ) / ( 4 * ( map->baud_rate.baud ) ) ); + reg = ( integer_divider / 100 ) << 4; + + fractional_divider = integer_divider - ( 100 * ( reg >> 4 ) ); + reg |= ( ( ( ( fractional_divider * 16 ) + 50 ) / 100 ) ) & 0x0F; + + hal_ll_hw_reg->brr = ( uint16_t )reg; + } +} + +static uint32_t hal_ll_uart_get_clock_speed( hal_ll_pin_name_t module_index ) { + rcc_clocks_t rcc_clocks; + + RCC_GetClocksFrequency( &rcc_clocks ); + + switch ( module_index ) + { + #ifdef UART_MODULE_1 + case ( hal_ll_uart_module_num(UART_MODULE_1) ): + return rcc_clocks.pclk2; + break; + #endif + + #ifdef UART_MODULE_2 + case ( hal_ll_uart_module_num(UART_MODULE_2) ): + return rcc_clocks.pclk1; + break; + #endif + + #ifdef UART_MODULE_3 + case ( hal_ll_uart_module_num(UART_MODULE_3) ): + return rcc_clocks.pclk1; + break; + #endif + + #ifdef UART_MODULE_4 + case ( hal_ll_uart_module_num(UART_MODULE_4) ): + return rcc_clocks.pclk1; + break; + #endif + + #ifdef UART_MODULE_5 + case ( hal_ll_uart_module_num(UART_MODULE_5) ): + return rcc_clocks.pclk1; + break; + #endif + + + default: + break; + } + + return NULL; +} + +static void hal_ll_uart_set_stop_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); + + switch ( map->stop_bit ) + { + case HAL_LL_UART_STOP_BITS_HALF: + hal_ll_hw_reg->cr2 |= STOP_BITS_HALF; + break; + case HAL_LL_UART_STOP_BITS_ONE: + hal_ll_hw_reg->cr2 |= STOP_BITS_ONE; + break; + case HAL_LL_UART_STOP_BITS_ONE_AND_A_HALF: + hal_ll_hw_reg->cr2 |= STOP_BITS_ONE_AND_A_HALF; + break; + case HAL_LL_UART_STOP_BITS_TWO: + hal_ll_hw_reg->cr2 |= STOP_BITS_TWO; + break; + + default: + break; + } +} + +static void hal_ll_uart_set_data_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); + + switch ( map->data_bit ) + { + case HAL_LL_UART_DATA_BITS_7: + hal_ll_hw_reg->cr1 |= DATA_BIT_7; + break; + + case HAL_LL_UART_DATA_BITS_8: + hal_ll_hw_reg->cr1 |= DATA_BIT_8; + break; + + case HAL_LL_UART_DATA_BITS_9: + hal_ll_hw_reg->cr1 |= DATA_BIT_9; + break; + + + default: + break; + } +} + +static void hal_ll_uart_set_parity_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); + + switch ( map->parity ) + { + case HAL_LL_UART_PARITY_NONE: + hal_ll_hw_reg->cr1 |= PARITY_NO; + break; + case HAL_LL_UART_PARITY_EVEN: + hal_ll_hw_reg->cr1 |= PARITY_ENABLED | PARITY_EVEN; + break; + case HAL_LL_UART_PARITY_ODD: + hal_ll_hw_reg->cr1 |= PARITY_ENABLED | PARITY_ODD; + break; + + default: + break; + } +} + +static void hal_ll_uart_set_module( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ) { + switch ( pin_state ) + { + case HAL_LL_UART_DISABLE: + clear_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_UE ); + break; + + case HAL_LL_UART_ENABLE: + set_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_UE ); + break; + + default: + break; + } +} + +static void hal_ll_uart_set_transmitter( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ) { + switch ( pin_state ) + { + case HAL_LL_UART_DISABLE: + clear_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_TE ); + break; + + case HAL_LL_UART_ENABLE: + set_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_TE ); + break; + + default: + break; + } +} + +static void hal_ll_uart_set_receiver( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ) { + switch ( pin_state ) + { + case HAL_LL_UART_DISABLE: + clear_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_RE ); + break; + + case HAL_LL_UART_ENABLE: + set_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_RE ); + break; + + default: + break; + } +} + +static void hal_ll_uart_clear_regs( hal_ll_uart_base_handle_t *hal_ll_hw_reg ) { + hal_ll_hw_reg->cr1 &= HAL_LL_UART_IT_CR1_MASK; + hal_ll_hw_reg->cr2 &= HAL_LL_UART_IT_CR2_MASK; + hal_ll_hw_reg->cr3 &= HAL_LL_UART_IT_CR3_MASK; +} + +static void hal_ll_uart_hw_init( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_clear_regs( map->base ); + + hal_ll_uart_set_data_bits_bare_metal( map ); + + hal_ll_uart_set_parity_bare_metal( map ); + + hal_ll_uart_set_stop_bits_bare_metal( map ); + + hal_ll_uart_set_baud_bare_metal( map ); + + hal_ll_uart_set_transmitter( map->base, HAL_LL_UART_ENABLE ); + + hal_ll_uart_set_receiver( map->base, HAL_LL_UART_ENABLE ); + + hal_ll_uart_set_module( map->base, HAL_LL_UART_ENABLE ); +} + +static void hal_ll_uart_init( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_set_clock( map, true ); + + hal_ll_uart_alternate_functions_set_state( map, true ); + + hal_ll_uart_hw_init( map ); +} +// ------------------------------------------------------------------------- END + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_86/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_86/CMakeLists.cmake new file mode 100644 index 000000000..a6cab2e45 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_86/CMakeLists.cmake @@ -0,0 +1,9 @@ +if(${MCU_NAME} MATCHES "^STM32G483CE$|^STM32G483RE$|^STM32G483ME$|^STM32G483PE$|^STM32G483VE$|^STM32G483QE$") + set(uart_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_uart.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_86") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_86") + list(APPEND hal_ll_def_list "STM32G4xx") + list(APPEND hal_ll_def_list "STM32G48xx") + list(APPEND hal_ll_def_list "STM32G483xx") + set(uart_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/uart/hal_ll_uart_pin_map/implementations/doc_ds_86") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_86/hal_ll_uart.c b/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_86/hal_ll_uart.c new file mode 100644 index 000000000..f6304e601 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_86/hal_ll_uart.c @@ -0,0 +1,1255 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_uart.c + * @brief UART HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_rcc.h" +#include "hal_ll_uart.h" +#include "hal_ll_gpio.h" +#include "hal_ll_core.h" +#include "hal_ll_core_defines.h" +#include "hal_ll_uart_pin_map.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_uart_handle_register_t hal_ll_module_state[UART_MODULE_COUNT] = { (handle_t *)NULL, (handle_t *)NULL, false }; + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_uart_get_module_state_address ((hal_ll_uart_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_uart_get_handle (hal_ll_uart_handle_register_t *)hal_ll_uart_get_module_state_address->hal_ll_uart_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_uart_get_base_struct(_handle) ((hal_ll_uart_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_uart_get_base_from_hal_handle ((hal_ll_uart_hw_specifics_map_t *)((hal_ll_uart_handle_register_t *)\ + (((hal_ll_uart_handle_register_t *)(handle))->hal_ll_uart_handle))->hal_ll_uart_handle)->base + +/*!< @brief Macros used for calculating actual baud rate value and error value */ +#define HAL_LL_UART_ACCEPTABLE_ERROR (float)1.0 +#define hal_ll_uart_get_baud(_clock,_baud,_div) (((_clock/(float)_baud)/_div)-1) +#define hal_ll_uart_get_real_baud(_clock,_baud,_div) (_clock/(_div*(_baud+1))) +#define hal_ll_uart_get_baud_error(_baud_real,_baud) (((float)(abs(_baud_real-_baud))/_baud)*100) + +/*!< @brief Macros defining bit location */ +#define HAL_LL_USART1EN 14 + +#define HAL_LL_USART2EN 17 + +#define HAL_LL_USART3EN 18 + +#define HAL_LL_USART4EN 19 + +#define HAL_LL_USART5EN 20 + + +#define HAL_LL_UART_CR1_UE 0 +#define HAL_LL_UART_CR1_TE 3 +#define HAL_LL_UART_CR1_RE 2 + +#define HAL_LL_UART_SR_RXNE 5 +#define HAL_LL_UART_SR_TXE 7 + +/*!< @brief Macros defining register bit values */ +#define STOP_BITS_HALF 0x1000U +#define STOP_BITS_ONE 0x00U +#define STOP_BITS_ONE_AND_A_HALF 0x3000U +#define STOP_BITS_TWO 0x2000U + +#define DATA_BIT_7 0x10000000U +#define DATA_BIT_8 0x00U +#define DATA_BIT_9 0x1000U + +#define PARITY_NO 0x00U +#define PARITY_ENABLED 0x400U + +#define PARITY_EVEN 0x00U +#define PARITY_ODD 0x200U + +/*!< @brief Macro used for setting pin alternate functions */ +#define HAL_LL_UART_AF_CONFIG (GPIO_CFG_MODE_ALT_FUNCTION | GPIO_CFG_SPEED_HIGH | GPIO_CFG_OTYPE_PP) + +/*!< @brief Macros used for interrupts */ +#define HAL_LL_UART_IT_MASK 0xFFFFUL +#define HAL_LL_UART_IT_CLEAR_MASK 0x123afeU +#define HAL_LL_UART_IT_CR1_MASK 0x1f0U +#define HAL_LL_UART_IT_CR2_MASK 0x40U +#define HAL_LL_UART_IT_CR3_MASK 0x401U + +#define HAL_LL_UART_CR1_REG_INDEX 1 +#define HAL_LL_UART_CR2_REG_INDEX 2 +#define HAL_LL_UART_CR3_REG_INDEX 3 + +#define HAL_LL_UART_IT_PE 0x100U +#define HAL_LL_UART_IT_TXE (0x10000000 | 0x80U) +#define HAL_LL_UART_IT_TC 0x40U +#define HAL_LL_UART_IT_RXNE (0x10000000 | 0x20U) +#define HAL_LL_UART_IT_IDLE 0x10U +#define HAL_LL_UART_IT_LBD 0x40U +#define HAL_LL_UART_IT_CTS 0x400U +#define HAL_LL_UART_IT_ERR 0x01U + +#define HAL_LL_UART_STATUS_RXNE_FLAG 0x20U +#define HAL_LL_UART_STATUS_TXE_FLAG 0x80U + +/*!< @brief Macro used for status registed flag check + * Used in interrupt handlers. + */ +#define hal_ll_uart_get_status_flags(_handle,_flag) (((hal_ll_uart_base_handle_t *)_handle)->isr & _flag) + +/*!< @brief Macro used for status register flag clearing + * Used in interrupt handlers. + */ +#define hal_ll_uart_clear_status_flag(_handle,_flag) (set_reg_bit( &(((hal_ll_uart_base_handle_t *)_handle)->icr), ( _flag & HAL_LL_UART_IT_CLEAR_MASK ) ) ) + +/*!< @brief Macro used for module interrupt enabling. + * Used in interrupt handlers. + */ +#define __HAL_LL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__ >> 28UL) == HAL_LL_UART_CR1_REG_INDEX)? (__HANDLE__->cr1 |= (__INTERRUPT__ & HAL_LL_UART_IT_MASK)): \ + ((__INTERRUPT__ >> 28UL) == HAL_LL_UART_CR2_REG_INDEX)? (__HANDLE__->cr2 |= (__INTERRUPT__ & HAL_LL_UART_IT_MASK)): \ + (__HANDLE__->cr3 |= (__INTERRUPT__ & HAL_LL_UART_IT_MASK))) + +/*!< @brief Macro used for module interrupt disabling. + * Used in interrupt handlers. + */ +#define __HAL_LL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__ >> 28UL) == HAL_LL_UART_CR1_REG_INDEX)? (__HANDLE__->cr1 &= ~(__INTERRUPT__ & HAL_LL_UART_IT_MASK)): \ + ((__INTERRUPT__ >> 28UL) == HAL_LL_UART_CR2_REG_INDEX)? (__HANDLE__->cr2 &= ~(__INTERRUPT__ & HAL_LL_UART_IT_MASK)): \ + (__HANDLE__->cr3 &= ~ (__INTERRUPT__ & HAL_LL_UART_IT_MASK))) + +/*!< @brief Macro used for module interrupt source check. + * Used in interrupt handlers. + */ +#define __HAL_LL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__ >> 28UL) == 1UL)? ((hal_ll_uart_base_handle_t *)__HANDLE__)->cr1:((((uint32_t)__INTERRUPT__ >> 28UL) == 2UL)? \ + ((hal_ll_uart_base_handle_t *)__HANDLE__)->cr2 : ((hal_ll_uart_base_handle_t *)__HANDLE__)->cr3)) & ((uint32_t)__INTERRUPT__ & HAL_LL_UART_IT_MASK)) + +/*!< @brief UART HW register structure */ +typedef struct +{ + hal_ll_base_addr_t cr1; + hal_ll_base_addr_t cr2; + hal_ll_base_addr_t cr3; + hal_ll_base_addr_t brr; + hal_ll_base_addr_t gtpr; + hal_ll_base_addr_t rtor; + hal_ll_base_addr_t rqr; + hal_ll_base_addr_t isr; + hal_ll_base_addr_t icr; + hal_ll_base_addr_t rdr; + hal_ll_base_addr_t tdr; + hal_ll_base_addr_t presc; + +} hal_ll_uart_base_handle_t; + +/*!< @brief UART baud rate structure */ +typedef struct +{ + uint32_t baud; + uint32_t real_baud; +} hal_ll_uart_baud_t; + +/*!< @brief UART hw specific structure */ +typedef struct +{ + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + hal_ll_uart_pins_t pins; + hal_ll_uart_baud_t baud_rate; + hal_ll_uart_parity_t parity; + hal_ll_uart_stop_bits_t stop_bit; + hal_ll_uart_data_bits_t data_bit; +} hal_ll_uart_hw_specifics_map_t; + +/*!< @brief UART hw specific module values */ +typedef struct +{ + uint16_t pin_tx; + uint16_t pin_rx; +} hal_ll_uart_pin_id; + +/*!< @brief UART hw specific error values */ +typedef enum +{ + HAL_LL_UART_SUCCESS = 0, + HAL_LL_UART_WRONG_PINS, + HAL_LL_UART_MODULE_ERROR, + + HAL_LL_UART_ERROR = (-1) +} hal_ll_uart_err_t; + +/*!< @brief UART module state selection */ +typedef enum +{ + HAL_LL_UART_DISABLE = 0, + HAL_LL_UART_ENABLE +} hal_ll_uart_state_t; + +// ------------------------------------------------------------------ VARIABLES +/*!< @brief UART hardware specific info */ +static hal_ll_uart_hw_specifics_map_t hal_ll_uart_hw_specifics_map[] = +{ + #ifdef UART_MODULE_1 + {HAL_LL_UART1_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_1), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + + #ifdef UART_MODULE_2 + {HAL_LL_UART2_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_2), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + + #ifdef UART_MODULE_3 + {HAL_LL_UART3_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_3), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + + #ifdef UART_MODULE_4 + {HAL_LL_UART4_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_4), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + + #ifdef UART_MODULE_5 + {HAL_LL_UART5_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_5), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + + + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {0, 0}, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR} +}; + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_uart_handle_register_t *low_level_handle; +static volatile hal_ll_uart_hw_specifics_map_t *hal_ll_uart_hw_specifics_map_local; + +/*!< @brief Global interrupt handlers used in functions */ +static hal_ll_uart_isr_t irq_handler; +static handle_t objects[UART_MODULE_COUNT]; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Check if pins are adequate. + * + * Checks tx and rx pins the user has passed with pre-defined + * pins in tx and rx maps. Take into consideration that module + * index numbers have to be the same for both pins. + * + * @param[in] tx_pin - TX pre-defined pin name. + * @param[in] rx_pin - RX pre-defined pin name. + * @param[in] *index_list - Array containing map index numbers. + * @return hal_ll_pin_name_t Module index based on pins. + * + * Returns pre-defined module index from pin maps, if pins + * are adequate. + */ +static hal_ll_pin_name_t hal_ll_uart_check_pins( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_uart_pin_id *index_list, hal_ll_uart_handle_register_t *handle_map ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * TX and RX pins. + * + * @param[in] module_index UART HW module index -- 0,1,2... + * @param[in] *index_list Array with TX and RX map index values + * and module number + * + * @return None + */ +static void hal_ll_uart_map_pins( uint8_t module_index, hal_ll_uart_pin_id *index_list ); + +/** + * @brief Sets UART pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if UART is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_state - Init/De-init + * + * @return void None. + */ +static void hal_ll_uart_alternate_functions_set_state( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_uart_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_uart_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_uart_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Enable clock for UART module on hardware level. + * + * Initializes UART module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_stat - True(enable clock)/False(disable clock). + * + * @return void None. + */ +static void hal_ll_uart_set_clock( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Finds UART module index. + * + * Finds UART index(module number) based on + * handle value. + * + * @param[in] handle - Object specific context handler. + * + * @return uint8_t Module number. + * Returns values from 0 to 9. + */ +static uint8_t hal_ll_uart_find_index( handle_t *handle ); + +/** + * @brief Get UART module clock speed. + * + * Returns adequate clock speed based on + * UART module base address. + * + * @param[in] module_index - UART module index number. + * + * @return uint8_t Module number. + * Returns clock value. + */ +static uint32_t hal_ll_uart_get_clock_speed( hal_ll_pin_name_t module_index ); + +/** + * @brief Clears UART registers. + * + * Clears UART module configuration + * registers, effectively disabling the module itself. + * Take into consideration that any IRQ bits + * are not cleared. + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * + * @return void None. + */ +static void hal_ll_uart_clear_regs( hal_ll_uart_base_handle_t *hal_ll_hw_reg ); + +/** + * @brief Sets desired baud rate on hardware level. + * + * Initializes module with specified baud rate value. + * Take into consideration that if the difference + * between desired baud rate and actual baud + * rate the hw was initialized to is greater than + * 1%, baud rate shall not be set. + * If this occurs, return value shall be + * the error percentage. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_set_baud_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Sets desired stop bits. + * + * Initializes module on hardware level + * with specified stop bit value. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_set_stop_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Sets desired data bits. + * + * Initializes module on hardware level + * with specified data bit bit value. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_set_data_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Sets desired parity. + * + * Initializes module on hardware level + * with specified parity value. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_set_parity_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Sets module clock value. + * + * Enables/disables specific UART module + * clock gate. + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * @param[in] pin_state - true(enable clock) / false(disable clock) + * + * @return void None. + */ +static void hal_ll_uart_set_module( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ); + +/** + * @brief Sets module TX line state. + * + * Enables/disables specific UART module + * TX pin state + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * @param[in] pin_state - true(enable transmitter pin) / false(disable transmitter pin) + * + * @return void None. + */ +static void hal_ll_uart_set_transmitter( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ); + +/** + * @brief Sets module RX line state. + * + * Enables/disables specific UART module + * RX pin state + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * @param[in] pin_state - true(enable receive pin) / false(disable receive pin) + * + * @return void None. + */ +static void hal_ll_uart_set_receiver( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ); + +/** + * @brief Initialize UART module. + * + * Enables UART module clogk gate first. + * Sets pin alternate function state. + * Initializes specific UART module. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_init( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Initialize UART module on the hardware level. + * + * Performs UART module initialization on + * the hardware level. + * + * Procedure: + * 1. Clears control registers + * 2. Sets data bit value + * 3. Sets parity value + * 4. Sets stop bit value + * 5. Sets baud rate value + * 6. Enables transmit pin + * 7. Enables receive pin + * 8. Enables clock gate for specific module + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_hw_init( hal_ll_uart_hw_specifics_map_t *map ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_uart_register_handle( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_uart_handle_register_t *handle_map, uint8_t *hal_module_id ) { + + hal_ll_uart_pin_id index_list[UART_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + uint16_t pin_check_result; + + // Check if pins are valid + if ( (pin_check_result = hal_ll_uart_check_pins( tx_pin, rx_pin, &index_list, handle_map )) == HAL_LL_PIN_NC ) { + return HAL_LL_UART_WRONG_PINS; + }; + + if ( (hal_ll_uart_hw_specifics_map[pin_check_result].pins.tx_pin.pin_name != tx_pin) || + (hal_ll_uart_hw_specifics_map[pin_check_result].pins.rx_pin.pin_name != rx_pin) ) + { + hal_ll_uart_alternate_functions_set_state( &hal_ll_uart_hw_specifics_map[ pin_check_result ], false ); + + hal_ll_uart_map_pins( pin_check_result, &index_list ); + + hal_ll_uart_alternate_functions_set_state( &hal_ll_uart_hw_specifics_map[ pin_check_result ], true ); + + handle_map[pin_check_result].init_ll_state = false; + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[pin_check_result].hal_ll_uart_handle = (handle_t *)&hal_ll_uart_hw_specifics_map[pin_check_result].base; + + handle_map[pin_check_result].hal_ll_uart_handle = (handle_t *)&hal_ll_module_state[pin_check_result].hal_ll_uart_handle; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_uart( handle_t *handle ) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + hal_ll_uart_pin_id index_list[UART_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + uint16_t pin_check_result; + + if ( (pin_check_result = hal_ll_uart_check_pins( hal_ll_uart_hw_specifics_map_local->pins.tx_pin.pin_name, + hal_ll_uart_hw_specifics_map_local->pins.rx_pin.pin_name, &index_list, (void *)0 ) ) == HAL_LL_PIN_NC ) { + return HAL_LL_UART_WRONG_PINS; + }; + + hal_ll_uart_init( hal_ll_uart_hw_specifics_map_local ); + + hal_ll_module_state[pin_check_result].hal_ll_uart_handle = (handle_t *)&hal_ll_uart_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_uart_set_baud( handle_t *handle, uint32_t baud ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->baud_rate.baud = baud; + + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return hal_ll_uart_hw_specifics_map_local->baud_rate.real_baud; +} + +hal_ll_err_t hal_ll_uart_set_parity( handle_t *handle, hal_ll_uart_parity_t parity ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->parity = parity; + + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_uart_set_stop_bits( handle_t *handle, hal_ll_uart_stop_bits_t stop_bit ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->stop_bit = stop_bit; + + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_uart_set_data_bits( handle_t *handle, hal_ll_uart_data_bits_t data_bit ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + // Chips using implementation 1 do not support 7 bit data + if( data_bit == HAL_LL_UART_DATA_BITS_7 ) { + return HAL_LL_UART_MODULE_ERROR; + } + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->data_bit = data_bit; + + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +void hal_ll_uart_close( handle_t *handle ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + if( low_level_handle->hal_ll_uart_handle != NULL ) { + hal_ll_uart_alternate_functions_set_state( hal_ll_uart_hw_specifics_map_local, false ); + + hal_ll_uart_irq_disable(handle, HAL_LL_UART_IRQ_RX); + hal_ll_uart_irq_disable(handle, HAL_LL_UART_IRQ_TX); + + hal_ll_uart_clear_regs(hal_ll_uart_hw_specifics_map_local->base); + hal_ll_uart_set_clock(hal_ll_uart_hw_specifics_map_local, false); + + hal_ll_uart_hw_specifics_map_local->pins.tx_pin.pin_name = HAL_LL_PIN_NC; + hal_ll_uart_hw_specifics_map_local->pins.tx_pin.pin_af = 0; + hal_ll_uart_hw_specifics_map_local->pins.rx_pin.pin_name = HAL_LL_PIN_NC; + hal_ll_uart_hw_specifics_map_local->pins.rx_pin.pin_af = 0; + + hal_ll_uart_hw_specifics_map_local->baud_rate.baud = 115200UL; + hal_ll_uart_hw_specifics_map_local->baud_rate.real_baud = 0; + + irq_handler = NULL; + objects[ hal_ll_uart_find_index( handle ) ] = NULL; + + low_level_handle->hal_ll_uart_handle = NULL; + low_level_handle->hal_drv_uart_handle = NULL; + + low_level_handle->init_ll_state = false; + } +} + +void hal_ll_uart_register_irq_handler( handle_t *handle, hal_ll_uart_isr_t handler, handle_t obj ) +{ + irq_handler = handler; + objects[ hal_ll_uart_find_index( handle ) ] = obj; +} + +void hal_ll_uart_irq_enable( handle_t *handle, hal_ll_uart_irq_t irq ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + switch ( irq ) { + case HAL_LL_UART_IRQ_RX: + __HAL_LL_UART_ENABLE_IT( hal_ll_hw_reg, HAL_LL_UART_IT_RXNE ); + break; + + case HAL_LL_UART_IRQ_TX: + __HAL_LL_UART_ENABLE_IT( hal_ll_hw_reg, HAL_LL_UART_IT_TXE ); + break; + + default: + break; + } + + switch ( hal_ll_uart_hw_specifics_map_local->module_index ) + { + #if defined(UART_MODULE_1) && defined(UART1_NVIC) + case hal_ll_uart_module_num(UART_MODULE_1): + hal_ll_core_enable_irq( UART1_NVIC ); + break; + #endif + + #if defined(UART_MODULE_2) && defined(UART2_NVIC) + case hal_ll_uart_module_num(UART_MODULE_2): + hal_ll_core_enable_irq( UART2_NVIC ); + break; + #endif + + #if defined(UART_MODULE_3) && defined(UART3_NVIC) + case hal_ll_uart_module_num(UART_MODULE_3): + hal_ll_core_enable_irq( UART3_NVIC ); + break; + #endif + + #if defined(UART_MODULE_4) && defined(UART4_NVIC) + case hal_ll_uart_module_num(UART_MODULE_4): + hal_ll_core_enable_irq( UART4_NVIC ); + break; + #endif + + #if defined(UART_MODULE_5) && defined(UART5_NVIC) + case hal_ll_uart_module_num(UART_MODULE_5): + hal_ll_core_enable_irq( UART5_NVIC ); + break; + #endif + + + default: + break; + } +} + +void hal_ll_uart_irq_disable( handle_t *handle, hal_ll_uart_irq_t irq ) +{ + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + switch ( irq ) { + case HAL_LL_UART_IRQ_RX: + __HAL_LL_UART_DISABLE_IT( hal_ll_hw_reg, HAL_LL_UART_IT_RXNE ); + break; + + case HAL_LL_UART_IRQ_TX: + __HAL_LL_UART_DISABLE_IT( hal_ll_hw_reg, HAL_LL_UART_IT_TXE ); + break; + + default: + break; + } + + // Check if module interrupt flags are set or not + if ( ( !check_reg_bit( &hal_ll_hw_reg->cr1, HAL_LL_UART_SR_RXNE ) ) && + ( !check_reg_bit( &hal_ll_hw_reg->cr1, HAL_LL_UART_SR_TXE ) ) ) + { + switch ( hal_ll_uart_hw_specifics_map_local->module_index ) + { + #if defined(UART_MODULE_1) && defined(UART1_NVIC) + case hal_ll_uart_module_num(UART_MODULE_1): + hal_ll_core_disable_irq( UART1_NVIC ); + break; + #endif + + #if defined(UART_MODULE_2) && defined(UART2_NVIC) + case hal_ll_uart_module_num(UART_MODULE_2): + hal_ll_core_disable_irq( UART2_NVIC ); + break; + #endif + + #if defined(UART_MODULE_3) && defined(UART3_NVIC) + case hal_ll_uart_module_num(UART_MODULE_3): + hal_ll_core_disable_irq( UART3_NVIC ); + break; + #endif + + #if defined(UART_MODULE_4) && defined(UART4_NVIC) + case hal_ll_uart_module_num(UART_MODULE_4): + hal_ll_core_disable_irq( UART4_NVIC ); + break; + #endif + + #if defined(UART_MODULE_5) && defined(UART5_NVIC) + case hal_ll_uart_module_num(UART_MODULE_5): + hal_ll_core_disable_irq( UART5_NVIC ); + break; + #endif + + + default: + break; + } + } +} + +void hal_ll_uart_write( handle_t *handle, uint8_t wr_data) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + hal_ll_hw_reg->tdr = wr_data; +} + +uint8_t hal_ll_uart_read( handle_t *handle ) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + return ( hal_ll_hw_reg->rdr ); +} + +// ------------------------------------------------------------- DEFAULT EXCEPTION HANDLERS + +#if defined(USART_MODULE_1) +void MARK_AS_IRQ_HANDLER UART1_IRQHandler() MIKROC_IV(UART1_NVIC) { + #ifdef USART_MODULE_1 + if( hal_ll_uart_get_status_flags( HAL_LL_USART1_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART1_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART1_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_1) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_USART1_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART1_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART1_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_1) ], HAL_LL_UART_IRQ_TX ); + } + } + #endif +} +#endif + +#if defined(USART_MODULE_2) +void MARK_AS_IRQ_HANDLER UART2_IRQHandler() MIKROC_IV(UART2_NVIC) { + #ifdef USART_MODULE_2 + if( hal_ll_uart_get_status_flags( HAL_LL_USART2_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART2_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART2_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_2) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_USART2_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART2_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART2_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_2) ], HAL_LL_UART_IRQ_TX ); + } + } + #endif +} +#endif + +#if defined(USART_MODULE_3) +void MARK_AS_IRQ_HANDLER UART3_IRQHandler() MIKROC_IV(UART3_NVIC) { + #ifdef USART_MODULE_3 + if( hal_ll_uart_get_status_flags( HAL_LL_USART3_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART3_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART3_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_3) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_USART3_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART3_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART3_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_3) ], HAL_LL_UART_IRQ_TX ); + } + } + #endif +} +#endif + +#if defined(UART_MODULE_4) +void MARK_AS_IRQ_HANDLER UART4_IRQHandler() MIKROC_IV(UART4_NVIC) { + #ifdef UART_MODULE_4 + if( hal_ll_uart_get_status_flags( HAL_LL_UART4_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_UART4_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_UART4_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(UART_MODULE_4) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_UART4_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_UART4_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_UART4_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(UART_MODULE_4) ], HAL_LL_UART_IRQ_TX ); + } + } + #endif +} +#endif + +#if defined(UART_MODULE_5) +void MARK_AS_IRQ_HANDLER UART5_IRQHandler() MIKROC_IV(UART5_NVIC) { + #ifdef UART_MODULE_5 + if( hal_ll_uart_get_status_flags( HAL_LL_UART5_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_UART5_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_UART5_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(UART_MODULE_5) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_UART5_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_UART5_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_UART5_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(UART_MODULE_5) ], HAL_LL_UART_IRQ_TX ); + } + } + #endif +} +#endif + +#if defined(LPUART_MODULE_1) +void MARK_AS_IRQ_HANDLER LPUART1_IRQHandler() MIKROC_IV(LPUART1_NVIC) { + #ifdef LPUART_MODULE_1 + if( hal_ll_uart_get_status_flags( HAL_LL_LPUART1_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_LPUART1_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_LPUART1_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(LPUART_MODULE_1) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_LPUART1_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_LPUART1_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_LPUART1_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(LPUART_MODULE_1) ], HAL_LL_UART_IRQ_TX ); + } + } + #endif +} +#endif + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static uint8_t hal_ll_uart_find_index( handle_t *handle ) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + if( hal_ll_uart_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + return hal_ll_uart_hw_specifics_map_local->module_index; + } else { + return NULL; + } +} + +static hal_ll_pin_name_t hal_ll_uart_check_pins( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_uart_pin_id *index_list, hal_ll_uart_handle_register_t *handle_map ) { + static const uint16_t tx_map_size = ( sizeof( hal_ll_uart_tx_map ) / sizeof( hal_ll_uart_pin_map_t ) ); + static const uint16_t rx_map_size = ( sizeof( hal_ll_uart_rx_map ) / sizeof( hal_ll_uart_pin_map_t ) ); + uint8_t hal_ll_module_id = 0; + uint8_t index_counter = 0; + uint16_t tx_index; + uint16_t rx_index; + + if ( (HAL_LL_PIN_NC == tx_pin) || (HAL_LL_PIN_NC == rx_pin) ) { + return HAL_LL_PIN_NC; + } + + for ( tx_index = 0; tx_index < tx_map_size; tx_index++ ) + { + if ( hal_ll_uart_tx_map[ tx_index ].pin == tx_pin ) + { + for ( rx_index = 0; rx_index < rx_map_size; rx_index++ ) + { + if ( hal_ll_uart_rx_map[ rx_index ].pin == rx_pin ) + { + if ( hal_ll_uart_tx_map[ tx_index ].base == hal_ll_uart_rx_map[ rx_index ].base ) { + // Get module number + hal_ll_module_id = hal_ll_uart_tx_map[ tx_index ].module_index; + + // Map pin names + index_list[hal_ll_module_id].pin_tx = tx_index; + index_list[hal_ll_module_id].pin_rx = rx_index; + + // Check if module is taken + if ( NULL == handle_map[ hal_ll_module_id ].hal_drv_uart_handle ) { + return hal_ll_module_id; + } else if ( UART_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static hal_ll_uart_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof(hal_ll_uart_handle_register_t)); + static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof(hal_ll_uart_handle_register_t)); + + while( hal_ll_module_count-- ) { + if (hal_ll_uart_get_base_from_hal_handle == hal_ll_uart_hw_specifics_map[hal_ll_module_count].base) { + return &hal_ll_uart_hw_specifics_map[hal_ll_module_count]; + } + } + + return &hal_ll_uart_hw_specifics_map[hal_ll_module_error]; +} + +static void hal_ll_uart_set_clock( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ) { + switch ( map->module_index ) + { + #ifdef UART_MODULE_1 + case ( hal_ll_uart_module_num(UART_MODULE_1) ): + (hal_ll_state == true)?(set_reg_bit( _RCC_APB2ENR, HAL_LL_USART1EN )):(clear_reg_bit( _RCC_APB2ENR, HAL_LL_USART1EN )); + break; + #endif + + #ifdef UART_MODULE_2 + case ( hal_ll_uart_module_num(UART_MODULE_2) ): + (hal_ll_state == true)?(set_reg_bit( _RCC_APB1ENR1, HAL_LL_USART2EN )):(clear_reg_bit( _RCC_APB1ENR1, HAL_LL_USART2EN )); + break; + #endif + + #ifdef UART_MODULE_3 + case ( hal_ll_uart_module_num(UART_MODULE_3) ): + (hal_ll_state == true)?(set_reg_bit( _RCC_APB1ENR1, HAL_LL_USART3EN )):(clear_reg_bit( _RCC_APB1ENR1, HAL_LL_USART3EN )); + break; + #endif + + #ifdef UART_MODULE_4 + case ( hal_ll_uart_module_num(UART_MODULE_4) ): + (hal_ll_state == true)?(set_reg_bit( _RCC_APB1ENR1, HAL_LL_USART4EN )):(clear_reg_bit( _RCC_APB1ENR1, HAL_LL_USART4EN )); + break; + #endif + + #ifdef UART_MODULE_5 + case ( hal_ll_uart_module_num(UART_MODULE_5) ): + (hal_ll_state == true)?(set_reg_bit( _RCC_APB1ENR1, HAL_LL_USART5EN )):(clear_reg_bit( _RCC_APB1ENR1, HAL_LL_USART5EN )); + break; + #endif + + + default: + break; + } +} + +static void hal_ll_uart_map_pins( uint8_t module_index, hal_ll_uart_pin_id *index_list ) { + // Map new pins + hal_ll_uart_hw_specifics_map[module_index].pins.tx_pin.pin_name = hal_ll_uart_tx_map[ index_list[module_index].pin_tx ].pin; + hal_ll_uart_hw_specifics_map[module_index].pins.rx_pin.pin_name = hal_ll_uart_rx_map[ index_list[module_index].pin_rx ].pin; + // TX and RX could have different alternate function settings, hence save both AF values + hal_ll_uart_hw_specifics_map[module_index].pins.tx_pin.pin_af = hal_ll_uart_tx_map[ index_list[module_index].pin_tx ].af; + hal_ll_uart_hw_specifics_map[module_index].pins.rx_pin.pin_af = hal_ll_uart_rx_map[ index_list[module_index].pin_rx ].af; +} + +static void hal_ll_uart_alternate_functions_set_state( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ) { + module_struct module; + + if ( (map->pins.tx_pin.pin_name != HAL_LL_PIN_NC) && map->pins.rx_pin.pin_name != HAL_LL_PIN_NC ) { + module.pins[0] = VALUE( map->pins.tx_pin.pin_name, map->pins.tx_pin.pin_af ); + module.pins[1] = VALUE( map->pins.rx_pin.pin_name, map->pins.rx_pin.pin_af ); + module.pins[2] = GPIO_MODULE_STRUCT_END; + + module.configs[0] = HAL_LL_UART_AF_CONFIG; + module.configs[1] = HAL_LL_UART_AF_CONFIG; + module.configs[2] = GPIO_MODULE_STRUCT_END; + + /* STM32F1xx specific */ + module.gpio_remap = map->pins.tx_pin.pin_af; + + hal_ll_gpio_module_struct_init( &module, hal_ll_state ); + } +} + +static void hal_ll_uart_set_baud_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + uint32_t reg = 0; + uint32_t integer_divider = 0; + uint32_t fractional_divider = 0; + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); + uint32_t hal_ll_baud_value = hal_ll_uart_get_baud(hal_ll_uart_get_clock_speed(map->module_index),map->baud_rate.baud,4); + uint32_t hal_ll_baud_real_value = hal_ll_uart_get_real_baud(hal_ll_uart_get_clock_speed(map->module_index),hal_ll_baud_value,4); + + // if error greater than specified, cancel setting baud rate + if( (hal_ll_uart_get_baud_error(hal_ll_baud_real_value,map->baud_rate.baud)) > HAL_LL_UART_ACCEPTABLE_ERROR ) { + map->baud_rate.real_baud = hal_ll_uart_get_baud_error(hal_ll_baud_real_value,map->baud_rate.baud); + } else { + map->baud_rate.real_baud = hal_ll_baud_real_value; + + integer_divider = ( ( 25 * hal_ll_uart_get_clock_speed( map->module_index ) ) / ( 4 * ( map->baud_rate.baud ) ) ); + reg = ( integer_divider / 100 ) << 4; + + fractional_divider = integer_divider - ( 100 * ( reg >> 4 ) ); + reg |= ( ( ( ( fractional_divider * 16 ) + 50 ) / 100 ) ) & 0x0F; + + hal_ll_hw_reg->brr = ( uint16_t )reg; + } +} + +static uint32_t hal_ll_uart_get_clock_speed( hal_ll_pin_name_t module_index ) { + rcc_clocks_t rcc_clocks; + + RCC_GetClocksFrequency( &rcc_clocks ); + + switch ( module_index ) + { + #ifdef UART_MODULE_1 + case ( hal_ll_uart_module_num(UART_MODULE_1) ): + return rcc_clocks.pclk2; + break; + #endif + + #ifdef UART_MODULE_2 + case ( hal_ll_uart_module_num(UART_MODULE_2) ): + return rcc_clocks.pclk1; + break; + #endif + + #ifdef UART_MODULE_3 + case ( hal_ll_uart_module_num(UART_MODULE_3) ): + return rcc_clocks.pclk1; + break; + #endif + + #ifdef UART_MODULE_4 + case ( hal_ll_uart_module_num(UART_MODULE_4) ): + return rcc_clocks.pclk1; + break; + #endif + + #ifdef UART_MODULE_5 + case ( hal_ll_uart_module_num(UART_MODULE_5) ): + return rcc_clocks.pclk1; + break; + #endif + + + default: + break; + } + + return NULL; +} + +static void hal_ll_uart_set_stop_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); + + switch ( map->stop_bit ) + { + case HAL_LL_UART_STOP_BITS_HALF: + hal_ll_hw_reg->cr2 |= STOP_BITS_HALF; + break; + case HAL_LL_UART_STOP_BITS_ONE: + hal_ll_hw_reg->cr2 |= STOP_BITS_ONE; + break; + case HAL_LL_UART_STOP_BITS_ONE_AND_A_HALF: + hal_ll_hw_reg->cr2 |= STOP_BITS_ONE_AND_A_HALF; + break; + case HAL_LL_UART_STOP_BITS_TWO: + hal_ll_hw_reg->cr2 |= STOP_BITS_TWO; + break; + + default: + break; + } +} + +static void hal_ll_uart_set_data_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); + + switch ( map->data_bit ) + { + case HAL_LL_UART_DATA_BITS_7: + hal_ll_hw_reg->cr1 |= DATA_BIT_7; + break; + + case HAL_LL_UART_DATA_BITS_8: + hal_ll_hw_reg->cr1 |= DATA_BIT_8; + break; + + case HAL_LL_UART_DATA_BITS_9: + hal_ll_hw_reg->cr1 |= DATA_BIT_9; + break; + + + default: + break; + } +} + +static void hal_ll_uart_set_parity_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); + + switch ( map->parity ) + { + case HAL_LL_UART_PARITY_NONE: + hal_ll_hw_reg->cr1 |= PARITY_NO; + break; + case HAL_LL_UART_PARITY_EVEN: + hal_ll_hw_reg->cr1 |= PARITY_ENABLED | PARITY_EVEN; + break; + case HAL_LL_UART_PARITY_ODD: + hal_ll_hw_reg->cr1 |= PARITY_ENABLED | PARITY_ODD; + break; + + default: + break; + } +} + +static void hal_ll_uart_set_module( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ) { + switch ( pin_state ) + { + case HAL_LL_UART_DISABLE: + clear_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_UE ); + break; + + case HAL_LL_UART_ENABLE: + set_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_UE ); + break; + + default: + break; + } +} + +static void hal_ll_uart_set_transmitter( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ) { + switch ( pin_state ) + { + case HAL_LL_UART_DISABLE: + clear_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_TE ); + break; + + case HAL_LL_UART_ENABLE: + set_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_TE ); + break; + + default: + break; + } +} + +static void hal_ll_uart_set_receiver( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ) { + switch ( pin_state ) + { + case HAL_LL_UART_DISABLE: + clear_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_RE ); + break; + + case HAL_LL_UART_ENABLE: + set_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_RE ); + break; + + default: + break; + } +} + +static void hal_ll_uart_clear_regs( hal_ll_uart_base_handle_t *hal_ll_hw_reg ) { + hal_ll_hw_reg->cr1 &= HAL_LL_UART_IT_CR1_MASK; + hal_ll_hw_reg->cr2 &= HAL_LL_UART_IT_CR2_MASK; + hal_ll_hw_reg->cr3 &= HAL_LL_UART_IT_CR3_MASK; +} + +static void hal_ll_uart_hw_init( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_clear_regs( map->base ); + + hal_ll_uart_set_data_bits_bare_metal( map ); + + hal_ll_uart_set_parity_bare_metal( map ); + + hal_ll_uart_set_stop_bits_bare_metal( map ); + + hal_ll_uart_set_baud_bare_metal( map ); + + hal_ll_uart_set_transmitter( map->base, HAL_LL_UART_ENABLE ); + + hal_ll_uart_set_receiver( map->base, HAL_LL_UART_ENABLE ); + + hal_ll_uart_set_module( map->base, HAL_LL_UART_ENABLE ); +} + +static void hal_ll_uart_init( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_set_clock( map, true ); + + hal_ll_uart_alternate_functions_set_state( map, true ); + + hal_ll_uart_hw_init( map ); +} +// ------------------------------------------------------------------------- END + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_87/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_87/CMakeLists.cmake new file mode 100644 index 000000000..664aff18f --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_87/CMakeLists.cmake @@ -0,0 +1,9 @@ +if(${MCU_NAME} MATCHES "^STM32G484CE$|^STM32G484ME$|^STM32G484PE$|^STM32G484RE$|^STM32G484QE$|^STM32G484VE$") + set(uart_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_uart.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_87") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_87") + list(APPEND hal_ll_def_list "STM32G4xx") + list(APPEND hal_ll_def_list "STM32G48xx") + list(APPEND hal_ll_def_list "STM32G484xx") + set(uart_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/uart/hal_ll_uart_pin_map/implementations/doc_ds_87") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_87/hal_ll_uart.c b/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_87/hal_ll_uart.c new file mode 100644 index 000000000..f6304e601 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_87/hal_ll_uart.c @@ -0,0 +1,1255 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_uart.c + * @brief UART HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_rcc.h" +#include "hal_ll_uart.h" +#include "hal_ll_gpio.h" +#include "hal_ll_core.h" +#include "hal_ll_core_defines.h" +#include "hal_ll_uart_pin_map.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_uart_handle_register_t hal_ll_module_state[UART_MODULE_COUNT] = { (handle_t *)NULL, (handle_t *)NULL, false }; + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_uart_get_module_state_address ((hal_ll_uart_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_uart_get_handle (hal_ll_uart_handle_register_t *)hal_ll_uart_get_module_state_address->hal_ll_uart_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_uart_get_base_struct(_handle) ((hal_ll_uart_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_uart_get_base_from_hal_handle ((hal_ll_uart_hw_specifics_map_t *)((hal_ll_uart_handle_register_t *)\ + (((hal_ll_uart_handle_register_t *)(handle))->hal_ll_uart_handle))->hal_ll_uart_handle)->base + +/*!< @brief Macros used for calculating actual baud rate value and error value */ +#define HAL_LL_UART_ACCEPTABLE_ERROR (float)1.0 +#define hal_ll_uart_get_baud(_clock,_baud,_div) (((_clock/(float)_baud)/_div)-1) +#define hal_ll_uart_get_real_baud(_clock,_baud,_div) (_clock/(_div*(_baud+1))) +#define hal_ll_uart_get_baud_error(_baud_real,_baud) (((float)(abs(_baud_real-_baud))/_baud)*100) + +/*!< @brief Macros defining bit location */ +#define HAL_LL_USART1EN 14 + +#define HAL_LL_USART2EN 17 + +#define HAL_LL_USART3EN 18 + +#define HAL_LL_USART4EN 19 + +#define HAL_LL_USART5EN 20 + + +#define HAL_LL_UART_CR1_UE 0 +#define HAL_LL_UART_CR1_TE 3 +#define HAL_LL_UART_CR1_RE 2 + +#define HAL_LL_UART_SR_RXNE 5 +#define HAL_LL_UART_SR_TXE 7 + +/*!< @brief Macros defining register bit values */ +#define STOP_BITS_HALF 0x1000U +#define STOP_BITS_ONE 0x00U +#define STOP_BITS_ONE_AND_A_HALF 0x3000U +#define STOP_BITS_TWO 0x2000U + +#define DATA_BIT_7 0x10000000U +#define DATA_BIT_8 0x00U +#define DATA_BIT_9 0x1000U + +#define PARITY_NO 0x00U +#define PARITY_ENABLED 0x400U + +#define PARITY_EVEN 0x00U +#define PARITY_ODD 0x200U + +/*!< @brief Macro used for setting pin alternate functions */ +#define HAL_LL_UART_AF_CONFIG (GPIO_CFG_MODE_ALT_FUNCTION | GPIO_CFG_SPEED_HIGH | GPIO_CFG_OTYPE_PP) + +/*!< @brief Macros used for interrupts */ +#define HAL_LL_UART_IT_MASK 0xFFFFUL +#define HAL_LL_UART_IT_CLEAR_MASK 0x123afeU +#define HAL_LL_UART_IT_CR1_MASK 0x1f0U +#define HAL_LL_UART_IT_CR2_MASK 0x40U +#define HAL_LL_UART_IT_CR3_MASK 0x401U + +#define HAL_LL_UART_CR1_REG_INDEX 1 +#define HAL_LL_UART_CR2_REG_INDEX 2 +#define HAL_LL_UART_CR3_REG_INDEX 3 + +#define HAL_LL_UART_IT_PE 0x100U +#define HAL_LL_UART_IT_TXE (0x10000000 | 0x80U) +#define HAL_LL_UART_IT_TC 0x40U +#define HAL_LL_UART_IT_RXNE (0x10000000 | 0x20U) +#define HAL_LL_UART_IT_IDLE 0x10U +#define HAL_LL_UART_IT_LBD 0x40U +#define HAL_LL_UART_IT_CTS 0x400U +#define HAL_LL_UART_IT_ERR 0x01U + +#define HAL_LL_UART_STATUS_RXNE_FLAG 0x20U +#define HAL_LL_UART_STATUS_TXE_FLAG 0x80U + +/*!< @brief Macro used for status registed flag check + * Used in interrupt handlers. + */ +#define hal_ll_uart_get_status_flags(_handle,_flag) (((hal_ll_uart_base_handle_t *)_handle)->isr & _flag) + +/*!< @brief Macro used for status register flag clearing + * Used in interrupt handlers. + */ +#define hal_ll_uart_clear_status_flag(_handle,_flag) (set_reg_bit( &(((hal_ll_uart_base_handle_t *)_handle)->icr), ( _flag & HAL_LL_UART_IT_CLEAR_MASK ) ) ) + +/*!< @brief Macro used for module interrupt enabling. + * Used in interrupt handlers. + */ +#define __HAL_LL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__ >> 28UL) == HAL_LL_UART_CR1_REG_INDEX)? (__HANDLE__->cr1 |= (__INTERRUPT__ & HAL_LL_UART_IT_MASK)): \ + ((__INTERRUPT__ >> 28UL) == HAL_LL_UART_CR2_REG_INDEX)? (__HANDLE__->cr2 |= (__INTERRUPT__ & HAL_LL_UART_IT_MASK)): \ + (__HANDLE__->cr3 |= (__INTERRUPT__ & HAL_LL_UART_IT_MASK))) + +/*!< @brief Macro used for module interrupt disabling. + * Used in interrupt handlers. + */ +#define __HAL_LL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__ >> 28UL) == HAL_LL_UART_CR1_REG_INDEX)? (__HANDLE__->cr1 &= ~(__INTERRUPT__ & HAL_LL_UART_IT_MASK)): \ + ((__INTERRUPT__ >> 28UL) == HAL_LL_UART_CR2_REG_INDEX)? (__HANDLE__->cr2 &= ~(__INTERRUPT__ & HAL_LL_UART_IT_MASK)): \ + (__HANDLE__->cr3 &= ~ (__INTERRUPT__ & HAL_LL_UART_IT_MASK))) + +/*!< @brief Macro used for module interrupt source check. + * Used in interrupt handlers. + */ +#define __HAL_LL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__ >> 28UL) == 1UL)? ((hal_ll_uart_base_handle_t *)__HANDLE__)->cr1:((((uint32_t)__INTERRUPT__ >> 28UL) == 2UL)? \ + ((hal_ll_uart_base_handle_t *)__HANDLE__)->cr2 : ((hal_ll_uart_base_handle_t *)__HANDLE__)->cr3)) & ((uint32_t)__INTERRUPT__ & HAL_LL_UART_IT_MASK)) + +/*!< @brief UART HW register structure */ +typedef struct +{ + hal_ll_base_addr_t cr1; + hal_ll_base_addr_t cr2; + hal_ll_base_addr_t cr3; + hal_ll_base_addr_t brr; + hal_ll_base_addr_t gtpr; + hal_ll_base_addr_t rtor; + hal_ll_base_addr_t rqr; + hal_ll_base_addr_t isr; + hal_ll_base_addr_t icr; + hal_ll_base_addr_t rdr; + hal_ll_base_addr_t tdr; + hal_ll_base_addr_t presc; + +} hal_ll_uart_base_handle_t; + +/*!< @brief UART baud rate structure */ +typedef struct +{ + uint32_t baud; + uint32_t real_baud; +} hal_ll_uart_baud_t; + +/*!< @brief UART hw specific structure */ +typedef struct +{ + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + hal_ll_uart_pins_t pins; + hal_ll_uart_baud_t baud_rate; + hal_ll_uart_parity_t parity; + hal_ll_uart_stop_bits_t stop_bit; + hal_ll_uart_data_bits_t data_bit; +} hal_ll_uart_hw_specifics_map_t; + +/*!< @brief UART hw specific module values */ +typedef struct +{ + uint16_t pin_tx; + uint16_t pin_rx; +} hal_ll_uart_pin_id; + +/*!< @brief UART hw specific error values */ +typedef enum +{ + HAL_LL_UART_SUCCESS = 0, + HAL_LL_UART_WRONG_PINS, + HAL_LL_UART_MODULE_ERROR, + + HAL_LL_UART_ERROR = (-1) +} hal_ll_uart_err_t; + +/*!< @brief UART module state selection */ +typedef enum +{ + HAL_LL_UART_DISABLE = 0, + HAL_LL_UART_ENABLE +} hal_ll_uart_state_t; + +// ------------------------------------------------------------------ VARIABLES +/*!< @brief UART hardware specific info */ +static hal_ll_uart_hw_specifics_map_t hal_ll_uart_hw_specifics_map[] = +{ + #ifdef UART_MODULE_1 + {HAL_LL_UART1_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_1), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + + #ifdef UART_MODULE_2 + {HAL_LL_UART2_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_2), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + + #ifdef UART_MODULE_3 + {HAL_LL_UART3_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_3), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + + #ifdef UART_MODULE_4 + {HAL_LL_UART4_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_4), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + + #ifdef UART_MODULE_5 + {HAL_LL_UART5_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_5), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + + + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {0, 0}, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR} +}; + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_uart_handle_register_t *low_level_handle; +static volatile hal_ll_uart_hw_specifics_map_t *hal_ll_uart_hw_specifics_map_local; + +/*!< @brief Global interrupt handlers used in functions */ +static hal_ll_uart_isr_t irq_handler; +static handle_t objects[UART_MODULE_COUNT]; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Check if pins are adequate. + * + * Checks tx and rx pins the user has passed with pre-defined + * pins in tx and rx maps. Take into consideration that module + * index numbers have to be the same for both pins. + * + * @param[in] tx_pin - TX pre-defined pin name. + * @param[in] rx_pin - RX pre-defined pin name. + * @param[in] *index_list - Array containing map index numbers. + * @return hal_ll_pin_name_t Module index based on pins. + * + * Returns pre-defined module index from pin maps, if pins + * are adequate. + */ +static hal_ll_pin_name_t hal_ll_uart_check_pins( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_uart_pin_id *index_list, hal_ll_uart_handle_register_t *handle_map ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * TX and RX pins. + * + * @param[in] module_index UART HW module index -- 0,1,2... + * @param[in] *index_list Array with TX and RX map index values + * and module number + * + * @return None + */ +static void hal_ll_uart_map_pins( uint8_t module_index, hal_ll_uart_pin_id *index_list ); + +/** + * @brief Sets UART pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if UART is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_state - Init/De-init + * + * @return void None. + */ +static void hal_ll_uart_alternate_functions_set_state( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_uart_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_uart_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_uart_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Enable clock for UART module on hardware level. + * + * Initializes UART module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_stat - True(enable clock)/False(disable clock). + * + * @return void None. + */ +static void hal_ll_uart_set_clock( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Finds UART module index. + * + * Finds UART index(module number) based on + * handle value. + * + * @param[in] handle - Object specific context handler. + * + * @return uint8_t Module number. + * Returns values from 0 to 9. + */ +static uint8_t hal_ll_uart_find_index( handle_t *handle ); + +/** + * @brief Get UART module clock speed. + * + * Returns adequate clock speed based on + * UART module base address. + * + * @param[in] module_index - UART module index number. + * + * @return uint8_t Module number. + * Returns clock value. + */ +static uint32_t hal_ll_uart_get_clock_speed( hal_ll_pin_name_t module_index ); + +/** + * @brief Clears UART registers. + * + * Clears UART module configuration + * registers, effectively disabling the module itself. + * Take into consideration that any IRQ bits + * are not cleared. + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * + * @return void None. + */ +static void hal_ll_uart_clear_regs( hal_ll_uart_base_handle_t *hal_ll_hw_reg ); + +/** + * @brief Sets desired baud rate on hardware level. + * + * Initializes module with specified baud rate value. + * Take into consideration that if the difference + * between desired baud rate and actual baud + * rate the hw was initialized to is greater than + * 1%, baud rate shall not be set. + * If this occurs, return value shall be + * the error percentage. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_set_baud_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Sets desired stop bits. + * + * Initializes module on hardware level + * with specified stop bit value. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_set_stop_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Sets desired data bits. + * + * Initializes module on hardware level + * with specified data bit bit value. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_set_data_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Sets desired parity. + * + * Initializes module on hardware level + * with specified parity value. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_set_parity_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Sets module clock value. + * + * Enables/disables specific UART module + * clock gate. + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * @param[in] pin_state - true(enable clock) / false(disable clock) + * + * @return void None. + */ +static void hal_ll_uart_set_module( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ); + +/** + * @brief Sets module TX line state. + * + * Enables/disables specific UART module + * TX pin state + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * @param[in] pin_state - true(enable transmitter pin) / false(disable transmitter pin) + * + * @return void None. + */ +static void hal_ll_uart_set_transmitter( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ); + +/** + * @brief Sets module RX line state. + * + * Enables/disables specific UART module + * RX pin state + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * @param[in] pin_state - true(enable receive pin) / false(disable receive pin) + * + * @return void None. + */ +static void hal_ll_uart_set_receiver( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ); + +/** + * @brief Initialize UART module. + * + * Enables UART module clogk gate first. + * Sets pin alternate function state. + * Initializes specific UART module. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_init( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Initialize UART module on the hardware level. + * + * Performs UART module initialization on + * the hardware level. + * + * Procedure: + * 1. Clears control registers + * 2. Sets data bit value + * 3. Sets parity value + * 4. Sets stop bit value + * 5. Sets baud rate value + * 6. Enables transmit pin + * 7. Enables receive pin + * 8. Enables clock gate for specific module + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_hw_init( hal_ll_uart_hw_specifics_map_t *map ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_uart_register_handle( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_uart_handle_register_t *handle_map, uint8_t *hal_module_id ) { + + hal_ll_uart_pin_id index_list[UART_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + uint16_t pin_check_result; + + // Check if pins are valid + if ( (pin_check_result = hal_ll_uart_check_pins( tx_pin, rx_pin, &index_list, handle_map )) == HAL_LL_PIN_NC ) { + return HAL_LL_UART_WRONG_PINS; + }; + + if ( (hal_ll_uart_hw_specifics_map[pin_check_result].pins.tx_pin.pin_name != tx_pin) || + (hal_ll_uart_hw_specifics_map[pin_check_result].pins.rx_pin.pin_name != rx_pin) ) + { + hal_ll_uart_alternate_functions_set_state( &hal_ll_uart_hw_specifics_map[ pin_check_result ], false ); + + hal_ll_uart_map_pins( pin_check_result, &index_list ); + + hal_ll_uart_alternate_functions_set_state( &hal_ll_uart_hw_specifics_map[ pin_check_result ], true ); + + handle_map[pin_check_result].init_ll_state = false; + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[pin_check_result].hal_ll_uart_handle = (handle_t *)&hal_ll_uart_hw_specifics_map[pin_check_result].base; + + handle_map[pin_check_result].hal_ll_uart_handle = (handle_t *)&hal_ll_module_state[pin_check_result].hal_ll_uart_handle; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_uart( handle_t *handle ) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + hal_ll_uart_pin_id index_list[UART_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + uint16_t pin_check_result; + + if ( (pin_check_result = hal_ll_uart_check_pins( hal_ll_uart_hw_specifics_map_local->pins.tx_pin.pin_name, + hal_ll_uart_hw_specifics_map_local->pins.rx_pin.pin_name, &index_list, (void *)0 ) ) == HAL_LL_PIN_NC ) { + return HAL_LL_UART_WRONG_PINS; + }; + + hal_ll_uart_init( hal_ll_uart_hw_specifics_map_local ); + + hal_ll_module_state[pin_check_result].hal_ll_uart_handle = (handle_t *)&hal_ll_uart_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_uart_set_baud( handle_t *handle, uint32_t baud ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->baud_rate.baud = baud; + + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return hal_ll_uart_hw_specifics_map_local->baud_rate.real_baud; +} + +hal_ll_err_t hal_ll_uart_set_parity( handle_t *handle, hal_ll_uart_parity_t parity ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->parity = parity; + + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_uart_set_stop_bits( handle_t *handle, hal_ll_uart_stop_bits_t stop_bit ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->stop_bit = stop_bit; + + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_uart_set_data_bits( handle_t *handle, hal_ll_uart_data_bits_t data_bit ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + // Chips using implementation 1 do not support 7 bit data + if( data_bit == HAL_LL_UART_DATA_BITS_7 ) { + return HAL_LL_UART_MODULE_ERROR; + } + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->data_bit = data_bit; + + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +void hal_ll_uart_close( handle_t *handle ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + if( low_level_handle->hal_ll_uart_handle != NULL ) { + hal_ll_uart_alternate_functions_set_state( hal_ll_uart_hw_specifics_map_local, false ); + + hal_ll_uart_irq_disable(handle, HAL_LL_UART_IRQ_RX); + hal_ll_uart_irq_disable(handle, HAL_LL_UART_IRQ_TX); + + hal_ll_uart_clear_regs(hal_ll_uart_hw_specifics_map_local->base); + hal_ll_uart_set_clock(hal_ll_uart_hw_specifics_map_local, false); + + hal_ll_uart_hw_specifics_map_local->pins.tx_pin.pin_name = HAL_LL_PIN_NC; + hal_ll_uart_hw_specifics_map_local->pins.tx_pin.pin_af = 0; + hal_ll_uart_hw_specifics_map_local->pins.rx_pin.pin_name = HAL_LL_PIN_NC; + hal_ll_uart_hw_specifics_map_local->pins.rx_pin.pin_af = 0; + + hal_ll_uart_hw_specifics_map_local->baud_rate.baud = 115200UL; + hal_ll_uart_hw_specifics_map_local->baud_rate.real_baud = 0; + + irq_handler = NULL; + objects[ hal_ll_uart_find_index( handle ) ] = NULL; + + low_level_handle->hal_ll_uart_handle = NULL; + low_level_handle->hal_drv_uart_handle = NULL; + + low_level_handle->init_ll_state = false; + } +} + +void hal_ll_uart_register_irq_handler( handle_t *handle, hal_ll_uart_isr_t handler, handle_t obj ) +{ + irq_handler = handler; + objects[ hal_ll_uart_find_index( handle ) ] = obj; +} + +void hal_ll_uart_irq_enable( handle_t *handle, hal_ll_uart_irq_t irq ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + switch ( irq ) { + case HAL_LL_UART_IRQ_RX: + __HAL_LL_UART_ENABLE_IT( hal_ll_hw_reg, HAL_LL_UART_IT_RXNE ); + break; + + case HAL_LL_UART_IRQ_TX: + __HAL_LL_UART_ENABLE_IT( hal_ll_hw_reg, HAL_LL_UART_IT_TXE ); + break; + + default: + break; + } + + switch ( hal_ll_uart_hw_specifics_map_local->module_index ) + { + #if defined(UART_MODULE_1) && defined(UART1_NVIC) + case hal_ll_uart_module_num(UART_MODULE_1): + hal_ll_core_enable_irq( UART1_NVIC ); + break; + #endif + + #if defined(UART_MODULE_2) && defined(UART2_NVIC) + case hal_ll_uart_module_num(UART_MODULE_2): + hal_ll_core_enable_irq( UART2_NVIC ); + break; + #endif + + #if defined(UART_MODULE_3) && defined(UART3_NVIC) + case hal_ll_uart_module_num(UART_MODULE_3): + hal_ll_core_enable_irq( UART3_NVIC ); + break; + #endif + + #if defined(UART_MODULE_4) && defined(UART4_NVIC) + case hal_ll_uart_module_num(UART_MODULE_4): + hal_ll_core_enable_irq( UART4_NVIC ); + break; + #endif + + #if defined(UART_MODULE_5) && defined(UART5_NVIC) + case hal_ll_uart_module_num(UART_MODULE_5): + hal_ll_core_enable_irq( UART5_NVIC ); + break; + #endif + + + default: + break; + } +} + +void hal_ll_uart_irq_disable( handle_t *handle, hal_ll_uart_irq_t irq ) +{ + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + switch ( irq ) { + case HAL_LL_UART_IRQ_RX: + __HAL_LL_UART_DISABLE_IT( hal_ll_hw_reg, HAL_LL_UART_IT_RXNE ); + break; + + case HAL_LL_UART_IRQ_TX: + __HAL_LL_UART_DISABLE_IT( hal_ll_hw_reg, HAL_LL_UART_IT_TXE ); + break; + + default: + break; + } + + // Check if module interrupt flags are set or not + if ( ( !check_reg_bit( &hal_ll_hw_reg->cr1, HAL_LL_UART_SR_RXNE ) ) && + ( !check_reg_bit( &hal_ll_hw_reg->cr1, HAL_LL_UART_SR_TXE ) ) ) + { + switch ( hal_ll_uart_hw_specifics_map_local->module_index ) + { + #if defined(UART_MODULE_1) && defined(UART1_NVIC) + case hal_ll_uart_module_num(UART_MODULE_1): + hal_ll_core_disable_irq( UART1_NVIC ); + break; + #endif + + #if defined(UART_MODULE_2) && defined(UART2_NVIC) + case hal_ll_uart_module_num(UART_MODULE_2): + hal_ll_core_disable_irq( UART2_NVIC ); + break; + #endif + + #if defined(UART_MODULE_3) && defined(UART3_NVIC) + case hal_ll_uart_module_num(UART_MODULE_3): + hal_ll_core_disable_irq( UART3_NVIC ); + break; + #endif + + #if defined(UART_MODULE_4) && defined(UART4_NVIC) + case hal_ll_uart_module_num(UART_MODULE_4): + hal_ll_core_disable_irq( UART4_NVIC ); + break; + #endif + + #if defined(UART_MODULE_5) && defined(UART5_NVIC) + case hal_ll_uart_module_num(UART_MODULE_5): + hal_ll_core_disable_irq( UART5_NVIC ); + break; + #endif + + + default: + break; + } + } +} + +void hal_ll_uart_write( handle_t *handle, uint8_t wr_data) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + hal_ll_hw_reg->tdr = wr_data; +} + +uint8_t hal_ll_uart_read( handle_t *handle ) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + return ( hal_ll_hw_reg->rdr ); +} + +// ------------------------------------------------------------- DEFAULT EXCEPTION HANDLERS + +#if defined(USART_MODULE_1) +void MARK_AS_IRQ_HANDLER UART1_IRQHandler() MIKROC_IV(UART1_NVIC) { + #ifdef USART_MODULE_1 + if( hal_ll_uart_get_status_flags( HAL_LL_USART1_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART1_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART1_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_1) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_USART1_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART1_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART1_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_1) ], HAL_LL_UART_IRQ_TX ); + } + } + #endif +} +#endif + +#if defined(USART_MODULE_2) +void MARK_AS_IRQ_HANDLER UART2_IRQHandler() MIKROC_IV(UART2_NVIC) { + #ifdef USART_MODULE_2 + if( hal_ll_uart_get_status_flags( HAL_LL_USART2_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART2_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART2_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_2) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_USART2_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART2_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART2_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_2) ], HAL_LL_UART_IRQ_TX ); + } + } + #endif +} +#endif + +#if defined(USART_MODULE_3) +void MARK_AS_IRQ_HANDLER UART3_IRQHandler() MIKROC_IV(UART3_NVIC) { + #ifdef USART_MODULE_3 + if( hal_ll_uart_get_status_flags( HAL_LL_USART3_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART3_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART3_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_3) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_USART3_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART3_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART3_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_3) ], HAL_LL_UART_IRQ_TX ); + } + } + #endif +} +#endif + +#if defined(UART_MODULE_4) +void MARK_AS_IRQ_HANDLER UART4_IRQHandler() MIKROC_IV(UART4_NVIC) { + #ifdef UART_MODULE_4 + if( hal_ll_uart_get_status_flags( HAL_LL_UART4_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_UART4_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_UART4_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(UART_MODULE_4) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_UART4_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_UART4_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_UART4_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(UART_MODULE_4) ], HAL_LL_UART_IRQ_TX ); + } + } + #endif +} +#endif + +#if defined(UART_MODULE_5) +void MARK_AS_IRQ_HANDLER UART5_IRQHandler() MIKROC_IV(UART5_NVIC) { + #ifdef UART_MODULE_5 + if( hal_ll_uart_get_status_flags( HAL_LL_UART5_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_UART5_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_UART5_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(UART_MODULE_5) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_UART5_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_UART5_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_UART5_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(UART_MODULE_5) ], HAL_LL_UART_IRQ_TX ); + } + } + #endif +} +#endif + +#if defined(LPUART_MODULE_1) +void MARK_AS_IRQ_HANDLER LPUART1_IRQHandler() MIKROC_IV(LPUART1_NVIC) { + #ifdef LPUART_MODULE_1 + if( hal_ll_uart_get_status_flags( HAL_LL_LPUART1_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_LPUART1_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_LPUART1_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(LPUART_MODULE_1) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_LPUART1_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_LPUART1_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_LPUART1_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(LPUART_MODULE_1) ], HAL_LL_UART_IRQ_TX ); + } + } + #endif +} +#endif + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static uint8_t hal_ll_uart_find_index( handle_t *handle ) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + if( hal_ll_uart_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + return hal_ll_uart_hw_specifics_map_local->module_index; + } else { + return NULL; + } +} + +static hal_ll_pin_name_t hal_ll_uart_check_pins( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_uart_pin_id *index_list, hal_ll_uart_handle_register_t *handle_map ) { + static const uint16_t tx_map_size = ( sizeof( hal_ll_uart_tx_map ) / sizeof( hal_ll_uart_pin_map_t ) ); + static const uint16_t rx_map_size = ( sizeof( hal_ll_uart_rx_map ) / sizeof( hal_ll_uart_pin_map_t ) ); + uint8_t hal_ll_module_id = 0; + uint8_t index_counter = 0; + uint16_t tx_index; + uint16_t rx_index; + + if ( (HAL_LL_PIN_NC == tx_pin) || (HAL_LL_PIN_NC == rx_pin) ) { + return HAL_LL_PIN_NC; + } + + for ( tx_index = 0; tx_index < tx_map_size; tx_index++ ) + { + if ( hal_ll_uart_tx_map[ tx_index ].pin == tx_pin ) + { + for ( rx_index = 0; rx_index < rx_map_size; rx_index++ ) + { + if ( hal_ll_uart_rx_map[ rx_index ].pin == rx_pin ) + { + if ( hal_ll_uart_tx_map[ tx_index ].base == hal_ll_uart_rx_map[ rx_index ].base ) { + // Get module number + hal_ll_module_id = hal_ll_uart_tx_map[ tx_index ].module_index; + + // Map pin names + index_list[hal_ll_module_id].pin_tx = tx_index; + index_list[hal_ll_module_id].pin_rx = rx_index; + + // Check if module is taken + if ( NULL == handle_map[ hal_ll_module_id ].hal_drv_uart_handle ) { + return hal_ll_module_id; + } else if ( UART_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static hal_ll_uart_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof(hal_ll_uart_handle_register_t)); + static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof(hal_ll_uart_handle_register_t)); + + while( hal_ll_module_count-- ) { + if (hal_ll_uart_get_base_from_hal_handle == hal_ll_uart_hw_specifics_map[hal_ll_module_count].base) { + return &hal_ll_uart_hw_specifics_map[hal_ll_module_count]; + } + } + + return &hal_ll_uart_hw_specifics_map[hal_ll_module_error]; +} + +static void hal_ll_uart_set_clock( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ) { + switch ( map->module_index ) + { + #ifdef UART_MODULE_1 + case ( hal_ll_uart_module_num(UART_MODULE_1) ): + (hal_ll_state == true)?(set_reg_bit( _RCC_APB2ENR, HAL_LL_USART1EN )):(clear_reg_bit( _RCC_APB2ENR, HAL_LL_USART1EN )); + break; + #endif + + #ifdef UART_MODULE_2 + case ( hal_ll_uart_module_num(UART_MODULE_2) ): + (hal_ll_state == true)?(set_reg_bit( _RCC_APB1ENR1, HAL_LL_USART2EN )):(clear_reg_bit( _RCC_APB1ENR1, HAL_LL_USART2EN )); + break; + #endif + + #ifdef UART_MODULE_3 + case ( hal_ll_uart_module_num(UART_MODULE_3) ): + (hal_ll_state == true)?(set_reg_bit( _RCC_APB1ENR1, HAL_LL_USART3EN )):(clear_reg_bit( _RCC_APB1ENR1, HAL_LL_USART3EN )); + break; + #endif + + #ifdef UART_MODULE_4 + case ( hal_ll_uart_module_num(UART_MODULE_4) ): + (hal_ll_state == true)?(set_reg_bit( _RCC_APB1ENR1, HAL_LL_USART4EN )):(clear_reg_bit( _RCC_APB1ENR1, HAL_LL_USART4EN )); + break; + #endif + + #ifdef UART_MODULE_5 + case ( hal_ll_uart_module_num(UART_MODULE_5) ): + (hal_ll_state == true)?(set_reg_bit( _RCC_APB1ENR1, HAL_LL_USART5EN )):(clear_reg_bit( _RCC_APB1ENR1, HAL_LL_USART5EN )); + break; + #endif + + + default: + break; + } +} + +static void hal_ll_uart_map_pins( uint8_t module_index, hal_ll_uart_pin_id *index_list ) { + // Map new pins + hal_ll_uart_hw_specifics_map[module_index].pins.tx_pin.pin_name = hal_ll_uart_tx_map[ index_list[module_index].pin_tx ].pin; + hal_ll_uart_hw_specifics_map[module_index].pins.rx_pin.pin_name = hal_ll_uart_rx_map[ index_list[module_index].pin_rx ].pin; + // TX and RX could have different alternate function settings, hence save both AF values + hal_ll_uart_hw_specifics_map[module_index].pins.tx_pin.pin_af = hal_ll_uart_tx_map[ index_list[module_index].pin_tx ].af; + hal_ll_uart_hw_specifics_map[module_index].pins.rx_pin.pin_af = hal_ll_uart_rx_map[ index_list[module_index].pin_rx ].af; +} + +static void hal_ll_uart_alternate_functions_set_state( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ) { + module_struct module; + + if ( (map->pins.tx_pin.pin_name != HAL_LL_PIN_NC) && map->pins.rx_pin.pin_name != HAL_LL_PIN_NC ) { + module.pins[0] = VALUE( map->pins.tx_pin.pin_name, map->pins.tx_pin.pin_af ); + module.pins[1] = VALUE( map->pins.rx_pin.pin_name, map->pins.rx_pin.pin_af ); + module.pins[2] = GPIO_MODULE_STRUCT_END; + + module.configs[0] = HAL_LL_UART_AF_CONFIG; + module.configs[1] = HAL_LL_UART_AF_CONFIG; + module.configs[2] = GPIO_MODULE_STRUCT_END; + + /* STM32F1xx specific */ + module.gpio_remap = map->pins.tx_pin.pin_af; + + hal_ll_gpio_module_struct_init( &module, hal_ll_state ); + } +} + +static void hal_ll_uart_set_baud_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + uint32_t reg = 0; + uint32_t integer_divider = 0; + uint32_t fractional_divider = 0; + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); + uint32_t hal_ll_baud_value = hal_ll_uart_get_baud(hal_ll_uart_get_clock_speed(map->module_index),map->baud_rate.baud,4); + uint32_t hal_ll_baud_real_value = hal_ll_uart_get_real_baud(hal_ll_uart_get_clock_speed(map->module_index),hal_ll_baud_value,4); + + // if error greater than specified, cancel setting baud rate + if( (hal_ll_uart_get_baud_error(hal_ll_baud_real_value,map->baud_rate.baud)) > HAL_LL_UART_ACCEPTABLE_ERROR ) { + map->baud_rate.real_baud = hal_ll_uart_get_baud_error(hal_ll_baud_real_value,map->baud_rate.baud); + } else { + map->baud_rate.real_baud = hal_ll_baud_real_value; + + integer_divider = ( ( 25 * hal_ll_uart_get_clock_speed( map->module_index ) ) / ( 4 * ( map->baud_rate.baud ) ) ); + reg = ( integer_divider / 100 ) << 4; + + fractional_divider = integer_divider - ( 100 * ( reg >> 4 ) ); + reg |= ( ( ( ( fractional_divider * 16 ) + 50 ) / 100 ) ) & 0x0F; + + hal_ll_hw_reg->brr = ( uint16_t )reg; + } +} + +static uint32_t hal_ll_uart_get_clock_speed( hal_ll_pin_name_t module_index ) { + rcc_clocks_t rcc_clocks; + + RCC_GetClocksFrequency( &rcc_clocks ); + + switch ( module_index ) + { + #ifdef UART_MODULE_1 + case ( hal_ll_uart_module_num(UART_MODULE_1) ): + return rcc_clocks.pclk2; + break; + #endif + + #ifdef UART_MODULE_2 + case ( hal_ll_uart_module_num(UART_MODULE_2) ): + return rcc_clocks.pclk1; + break; + #endif + + #ifdef UART_MODULE_3 + case ( hal_ll_uart_module_num(UART_MODULE_3) ): + return rcc_clocks.pclk1; + break; + #endif + + #ifdef UART_MODULE_4 + case ( hal_ll_uart_module_num(UART_MODULE_4) ): + return rcc_clocks.pclk1; + break; + #endif + + #ifdef UART_MODULE_5 + case ( hal_ll_uart_module_num(UART_MODULE_5) ): + return rcc_clocks.pclk1; + break; + #endif + + + default: + break; + } + + return NULL; +} + +static void hal_ll_uart_set_stop_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); + + switch ( map->stop_bit ) + { + case HAL_LL_UART_STOP_BITS_HALF: + hal_ll_hw_reg->cr2 |= STOP_BITS_HALF; + break; + case HAL_LL_UART_STOP_BITS_ONE: + hal_ll_hw_reg->cr2 |= STOP_BITS_ONE; + break; + case HAL_LL_UART_STOP_BITS_ONE_AND_A_HALF: + hal_ll_hw_reg->cr2 |= STOP_BITS_ONE_AND_A_HALF; + break; + case HAL_LL_UART_STOP_BITS_TWO: + hal_ll_hw_reg->cr2 |= STOP_BITS_TWO; + break; + + default: + break; + } +} + +static void hal_ll_uart_set_data_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); + + switch ( map->data_bit ) + { + case HAL_LL_UART_DATA_BITS_7: + hal_ll_hw_reg->cr1 |= DATA_BIT_7; + break; + + case HAL_LL_UART_DATA_BITS_8: + hal_ll_hw_reg->cr1 |= DATA_BIT_8; + break; + + case HAL_LL_UART_DATA_BITS_9: + hal_ll_hw_reg->cr1 |= DATA_BIT_9; + break; + + + default: + break; + } +} + +static void hal_ll_uart_set_parity_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); + + switch ( map->parity ) + { + case HAL_LL_UART_PARITY_NONE: + hal_ll_hw_reg->cr1 |= PARITY_NO; + break; + case HAL_LL_UART_PARITY_EVEN: + hal_ll_hw_reg->cr1 |= PARITY_ENABLED | PARITY_EVEN; + break; + case HAL_LL_UART_PARITY_ODD: + hal_ll_hw_reg->cr1 |= PARITY_ENABLED | PARITY_ODD; + break; + + default: + break; + } +} + +static void hal_ll_uart_set_module( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ) { + switch ( pin_state ) + { + case HAL_LL_UART_DISABLE: + clear_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_UE ); + break; + + case HAL_LL_UART_ENABLE: + set_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_UE ); + break; + + default: + break; + } +} + +static void hal_ll_uart_set_transmitter( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ) { + switch ( pin_state ) + { + case HAL_LL_UART_DISABLE: + clear_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_TE ); + break; + + case HAL_LL_UART_ENABLE: + set_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_TE ); + break; + + default: + break; + } +} + +static void hal_ll_uart_set_receiver( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ) { + switch ( pin_state ) + { + case HAL_LL_UART_DISABLE: + clear_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_RE ); + break; + + case HAL_LL_UART_ENABLE: + set_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_RE ); + break; + + default: + break; + } +} + +static void hal_ll_uart_clear_regs( hal_ll_uart_base_handle_t *hal_ll_hw_reg ) { + hal_ll_hw_reg->cr1 &= HAL_LL_UART_IT_CR1_MASK; + hal_ll_hw_reg->cr2 &= HAL_LL_UART_IT_CR2_MASK; + hal_ll_hw_reg->cr3 &= HAL_LL_UART_IT_CR3_MASK; +} + +static void hal_ll_uart_hw_init( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_clear_regs( map->base ); + + hal_ll_uart_set_data_bits_bare_metal( map ); + + hal_ll_uart_set_parity_bare_metal( map ); + + hal_ll_uart_set_stop_bits_bare_metal( map ); + + hal_ll_uart_set_baud_bare_metal( map ); + + hal_ll_uart_set_transmitter( map->base, HAL_LL_UART_ENABLE ); + + hal_ll_uart_set_receiver( map->base, HAL_LL_UART_ENABLE ); + + hal_ll_uart_set_module( map->base, HAL_LL_UART_ENABLE ); +} + +static void hal_ll_uart_init( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_set_clock( map, true ); + + hal_ll_uart_alternate_functions_set_state( map, true ); + + hal_ll_uart_hw_init( map ); +} +// ------------------------------------------------------------------------- END + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_88/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_88/CMakeLists.cmake new file mode 100644 index 000000000..c84369daf --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_88/CMakeLists.cmake @@ -0,0 +1,9 @@ +if(${MCU_NAME} MATCHES "^STM32G491CC$|^STM32G491KC$|^STM32G491RC$|^STM32G491VC$|^STM32G491MC$|^STM32G491CE$|^STM32G491KE$|^STM32G491RE$|^STM32G491VE$|^STM32G491ME$") + set(uart_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_uart.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_88") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_88") + list(APPEND hal_ll_def_list "STM32G4xx") + list(APPEND hal_ll_def_list "STM32G49xx") + list(APPEND hal_ll_def_list "STM32G491xx") + set(uart_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/uart/hal_ll_uart_pin_map/implementations/doc_ds_88") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_88/hal_ll_uart.c b/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_88/hal_ll_uart.c new file mode 100644 index 000000000..f6304e601 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_88/hal_ll_uart.c @@ -0,0 +1,1255 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_uart.c + * @brief UART HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_rcc.h" +#include "hal_ll_uart.h" +#include "hal_ll_gpio.h" +#include "hal_ll_core.h" +#include "hal_ll_core_defines.h" +#include "hal_ll_uart_pin_map.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_uart_handle_register_t hal_ll_module_state[UART_MODULE_COUNT] = { (handle_t *)NULL, (handle_t *)NULL, false }; + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_uart_get_module_state_address ((hal_ll_uart_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_uart_get_handle (hal_ll_uart_handle_register_t *)hal_ll_uart_get_module_state_address->hal_ll_uart_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_uart_get_base_struct(_handle) ((hal_ll_uart_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_uart_get_base_from_hal_handle ((hal_ll_uart_hw_specifics_map_t *)((hal_ll_uart_handle_register_t *)\ + (((hal_ll_uart_handle_register_t *)(handle))->hal_ll_uart_handle))->hal_ll_uart_handle)->base + +/*!< @brief Macros used for calculating actual baud rate value and error value */ +#define HAL_LL_UART_ACCEPTABLE_ERROR (float)1.0 +#define hal_ll_uart_get_baud(_clock,_baud,_div) (((_clock/(float)_baud)/_div)-1) +#define hal_ll_uart_get_real_baud(_clock,_baud,_div) (_clock/(_div*(_baud+1))) +#define hal_ll_uart_get_baud_error(_baud_real,_baud) (((float)(abs(_baud_real-_baud))/_baud)*100) + +/*!< @brief Macros defining bit location */ +#define HAL_LL_USART1EN 14 + +#define HAL_LL_USART2EN 17 + +#define HAL_LL_USART3EN 18 + +#define HAL_LL_USART4EN 19 + +#define HAL_LL_USART5EN 20 + + +#define HAL_LL_UART_CR1_UE 0 +#define HAL_LL_UART_CR1_TE 3 +#define HAL_LL_UART_CR1_RE 2 + +#define HAL_LL_UART_SR_RXNE 5 +#define HAL_LL_UART_SR_TXE 7 + +/*!< @brief Macros defining register bit values */ +#define STOP_BITS_HALF 0x1000U +#define STOP_BITS_ONE 0x00U +#define STOP_BITS_ONE_AND_A_HALF 0x3000U +#define STOP_BITS_TWO 0x2000U + +#define DATA_BIT_7 0x10000000U +#define DATA_BIT_8 0x00U +#define DATA_BIT_9 0x1000U + +#define PARITY_NO 0x00U +#define PARITY_ENABLED 0x400U + +#define PARITY_EVEN 0x00U +#define PARITY_ODD 0x200U + +/*!< @brief Macro used for setting pin alternate functions */ +#define HAL_LL_UART_AF_CONFIG (GPIO_CFG_MODE_ALT_FUNCTION | GPIO_CFG_SPEED_HIGH | GPIO_CFG_OTYPE_PP) + +/*!< @brief Macros used for interrupts */ +#define HAL_LL_UART_IT_MASK 0xFFFFUL +#define HAL_LL_UART_IT_CLEAR_MASK 0x123afeU +#define HAL_LL_UART_IT_CR1_MASK 0x1f0U +#define HAL_LL_UART_IT_CR2_MASK 0x40U +#define HAL_LL_UART_IT_CR3_MASK 0x401U + +#define HAL_LL_UART_CR1_REG_INDEX 1 +#define HAL_LL_UART_CR2_REG_INDEX 2 +#define HAL_LL_UART_CR3_REG_INDEX 3 + +#define HAL_LL_UART_IT_PE 0x100U +#define HAL_LL_UART_IT_TXE (0x10000000 | 0x80U) +#define HAL_LL_UART_IT_TC 0x40U +#define HAL_LL_UART_IT_RXNE (0x10000000 | 0x20U) +#define HAL_LL_UART_IT_IDLE 0x10U +#define HAL_LL_UART_IT_LBD 0x40U +#define HAL_LL_UART_IT_CTS 0x400U +#define HAL_LL_UART_IT_ERR 0x01U + +#define HAL_LL_UART_STATUS_RXNE_FLAG 0x20U +#define HAL_LL_UART_STATUS_TXE_FLAG 0x80U + +/*!< @brief Macro used for status registed flag check + * Used in interrupt handlers. + */ +#define hal_ll_uart_get_status_flags(_handle,_flag) (((hal_ll_uart_base_handle_t *)_handle)->isr & _flag) + +/*!< @brief Macro used for status register flag clearing + * Used in interrupt handlers. + */ +#define hal_ll_uart_clear_status_flag(_handle,_flag) (set_reg_bit( &(((hal_ll_uart_base_handle_t *)_handle)->icr), ( _flag & HAL_LL_UART_IT_CLEAR_MASK ) ) ) + +/*!< @brief Macro used for module interrupt enabling. + * Used in interrupt handlers. + */ +#define __HAL_LL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__ >> 28UL) == HAL_LL_UART_CR1_REG_INDEX)? (__HANDLE__->cr1 |= (__INTERRUPT__ & HAL_LL_UART_IT_MASK)): \ + ((__INTERRUPT__ >> 28UL) == HAL_LL_UART_CR2_REG_INDEX)? (__HANDLE__->cr2 |= (__INTERRUPT__ & HAL_LL_UART_IT_MASK)): \ + (__HANDLE__->cr3 |= (__INTERRUPT__ & HAL_LL_UART_IT_MASK))) + +/*!< @brief Macro used for module interrupt disabling. + * Used in interrupt handlers. + */ +#define __HAL_LL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__ >> 28UL) == HAL_LL_UART_CR1_REG_INDEX)? (__HANDLE__->cr1 &= ~(__INTERRUPT__ & HAL_LL_UART_IT_MASK)): \ + ((__INTERRUPT__ >> 28UL) == HAL_LL_UART_CR2_REG_INDEX)? (__HANDLE__->cr2 &= ~(__INTERRUPT__ & HAL_LL_UART_IT_MASK)): \ + (__HANDLE__->cr3 &= ~ (__INTERRUPT__ & HAL_LL_UART_IT_MASK))) + +/*!< @brief Macro used for module interrupt source check. + * Used in interrupt handlers. + */ +#define __HAL_LL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__ >> 28UL) == 1UL)? ((hal_ll_uart_base_handle_t *)__HANDLE__)->cr1:((((uint32_t)__INTERRUPT__ >> 28UL) == 2UL)? \ + ((hal_ll_uart_base_handle_t *)__HANDLE__)->cr2 : ((hal_ll_uart_base_handle_t *)__HANDLE__)->cr3)) & ((uint32_t)__INTERRUPT__ & HAL_LL_UART_IT_MASK)) + +/*!< @brief UART HW register structure */ +typedef struct +{ + hal_ll_base_addr_t cr1; + hal_ll_base_addr_t cr2; + hal_ll_base_addr_t cr3; + hal_ll_base_addr_t brr; + hal_ll_base_addr_t gtpr; + hal_ll_base_addr_t rtor; + hal_ll_base_addr_t rqr; + hal_ll_base_addr_t isr; + hal_ll_base_addr_t icr; + hal_ll_base_addr_t rdr; + hal_ll_base_addr_t tdr; + hal_ll_base_addr_t presc; + +} hal_ll_uart_base_handle_t; + +/*!< @brief UART baud rate structure */ +typedef struct +{ + uint32_t baud; + uint32_t real_baud; +} hal_ll_uart_baud_t; + +/*!< @brief UART hw specific structure */ +typedef struct +{ + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + hal_ll_uart_pins_t pins; + hal_ll_uart_baud_t baud_rate; + hal_ll_uart_parity_t parity; + hal_ll_uart_stop_bits_t stop_bit; + hal_ll_uart_data_bits_t data_bit; +} hal_ll_uart_hw_specifics_map_t; + +/*!< @brief UART hw specific module values */ +typedef struct +{ + uint16_t pin_tx; + uint16_t pin_rx; +} hal_ll_uart_pin_id; + +/*!< @brief UART hw specific error values */ +typedef enum +{ + HAL_LL_UART_SUCCESS = 0, + HAL_LL_UART_WRONG_PINS, + HAL_LL_UART_MODULE_ERROR, + + HAL_LL_UART_ERROR = (-1) +} hal_ll_uart_err_t; + +/*!< @brief UART module state selection */ +typedef enum +{ + HAL_LL_UART_DISABLE = 0, + HAL_LL_UART_ENABLE +} hal_ll_uart_state_t; + +// ------------------------------------------------------------------ VARIABLES +/*!< @brief UART hardware specific info */ +static hal_ll_uart_hw_specifics_map_t hal_ll_uart_hw_specifics_map[] = +{ + #ifdef UART_MODULE_1 + {HAL_LL_UART1_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_1), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + + #ifdef UART_MODULE_2 + {HAL_LL_UART2_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_2), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + + #ifdef UART_MODULE_3 + {HAL_LL_UART3_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_3), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + + #ifdef UART_MODULE_4 + {HAL_LL_UART4_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_4), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + + #ifdef UART_MODULE_5 + {HAL_LL_UART5_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_5), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + + + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {0, 0}, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR} +}; + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_uart_handle_register_t *low_level_handle; +static volatile hal_ll_uart_hw_specifics_map_t *hal_ll_uart_hw_specifics_map_local; + +/*!< @brief Global interrupt handlers used in functions */ +static hal_ll_uart_isr_t irq_handler; +static handle_t objects[UART_MODULE_COUNT]; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Check if pins are adequate. + * + * Checks tx and rx pins the user has passed with pre-defined + * pins in tx and rx maps. Take into consideration that module + * index numbers have to be the same for both pins. + * + * @param[in] tx_pin - TX pre-defined pin name. + * @param[in] rx_pin - RX pre-defined pin name. + * @param[in] *index_list - Array containing map index numbers. + * @return hal_ll_pin_name_t Module index based on pins. + * + * Returns pre-defined module index from pin maps, if pins + * are adequate. + */ +static hal_ll_pin_name_t hal_ll_uart_check_pins( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_uart_pin_id *index_list, hal_ll_uart_handle_register_t *handle_map ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * TX and RX pins. + * + * @param[in] module_index UART HW module index -- 0,1,2... + * @param[in] *index_list Array with TX and RX map index values + * and module number + * + * @return None + */ +static void hal_ll_uart_map_pins( uint8_t module_index, hal_ll_uart_pin_id *index_list ); + +/** + * @brief Sets UART pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if UART is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_state - Init/De-init + * + * @return void None. + */ +static void hal_ll_uart_alternate_functions_set_state( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_uart_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_uart_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_uart_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Enable clock for UART module on hardware level. + * + * Initializes UART module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_stat - True(enable clock)/False(disable clock). + * + * @return void None. + */ +static void hal_ll_uart_set_clock( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Finds UART module index. + * + * Finds UART index(module number) based on + * handle value. + * + * @param[in] handle - Object specific context handler. + * + * @return uint8_t Module number. + * Returns values from 0 to 9. + */ +static uint8_t hal_ll_uart_find_index( handle_t *handle ); + +/** + * @brief Get UART module clock speed. + * + * Returns adequate clock speed based on + * UART module base address. + * + * @param[in] module_index - UART module index number. + * + * @return uint8_t Module number. + * Returns clock value. + */ +static uint32_t hal_ll_uart_get_clock_speed( hal_ll_pin_name_t module_index ); + +/** + * @brief Clears UART registers. + * + * Clears UART module configuration + * registers, effectively disabling the module itself. + * Take into consideration that any IRQ bits + * are not cleared. + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * + * @return void None. + */ +static void hal_ll_uart_clear_regs( hal_ll_uart_base_handle_t *hal_ll_hw_reg ); + +/** + * @brief Sets desired baud rate on hardware level. + * + * Initializes module with specified baud rate value. + * Take into consideration that if the difference + * between desired baud rate and actual baud + * rate the hw was initialized to is greater than + * 1%, baud rate shall not be set. + * If this occurs, return value shall be + * the error percentage. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_set_baud_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Sets desired stop bits. + * + * Initializes module on hardware level + * with specified stop bit value. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_set_stop_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Sets desired data bits. + * + * Initializes module on hardware level + * with specified data bit bit value. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_set_data_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Sets desired parity. + * + * Initializes module on hardware level + * with specified parity value. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_set_parity_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Sets module clock value. + * + * Enables/disables specific UART module + * clock gate. + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * @param[in] pin_state - true(enable clock) / false(disable clock) + * + * @return void None. + */ +static void hal_ll_uart_set_module( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ); + +/** + * @brief Sets module TX line state. + * + * Enables/disables specific UART module + * TX pin state + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * @param[in] pin_state - true(enable transmitter pin) / false(disable transmitter pin) + * + * @return void None. + */ +static void hal_ll_uart_set_transmitter( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ); + +/** + * @brief Sets module RX line state. + * + * Enables/disables specific UART module + * RX pin state + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * @param[in] pin_state - true(enable receive pin) / false(disable receive pin) + * + * @return void None. + */ +static void hal_ll_uart_set_receiver( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ); + +/** + * @brief Initialize UART module. + * + * Enables UART module clogk gate first. + * Sets pin alternate function state. + * Initializes specific UART module. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_init( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Initialize UART module on the hardware level. + * + * Performs UART module initialization on + * the hardware level. + * + * Procedure: + * 1. Clears control registers + * 2. Sets data bit value + * 3. Sets parity value + * 4. Sets stop bit value + * 5. Sets baud rate value + * 6. Enables transmit pin + * 7. Enables receive pin + * 8. Enables clock gate for specific module + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_hw_init( hal_ll_uart_hw_specifics_map_t *map ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_uart_register_handle( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_uart_handle_register_t *handle_map, uint8_t *hal_module_id ) { + + hal_ll_uart_pin_id index_list[UART_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + uint16_t pin_check_result; + + // Check if pins are valid + if ( (pin_check_result = hal_ll_uart_check_pins( tx_pin, rx_pin, &index_list, handle_map )) == HAL_LL_PIN_NC ) { + return HAL_LL_UART_WRONG_PINS; + }; + + if ( (hal_ll_uart_hw_specifics_map[pin_check_result].pins.tx_pin.pin_name != tx_pin) || + (hal_ll_uart_hw_specifics_map[pin_check_result].pins.rx_pin.pin_name != rx_pin) ) + { + hal_ll_uart_alternate_functions_set_state( &hal_ll_uart_hw_specifics_map[ pin_check_result ], false ); + + hal_ll_uart_map_pins( pin_check_result, &index_list ); + + hal_ll_uart_alternate_functions_set_state( &hal_ll_uart_hw_specifics_map[ pin_check_result ], true ); + + handle_map[pin_check_result].init_ll_state = false; + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[pin_check_result].hal_ll_uart_handle = (handle_t *)&hal_ll_uart_hw_specifics_map[pin_check_result].base; + + handle_map[pin_check_result].hal_ll_uart_handle = (handle_t *)&hal_ll_module_state[pin_check_result].hal_ll_uart_handle; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_uart( handle_t *handle ) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + hal_ll_uart_pin_id index_list[UART_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + uint16_t pin_check_result; + + if ( (pin_check_result = hal_ll_uart_check_pins( hal_ll_uart_hw_specifics_map_local->pins.tx_pin.pin_name, + hal_ll_uart_hw_specifics_map_local->pins.rx_pin.pin_name, &index_list, (void *)0 ) ) == HAL_LL_PIN_NC ) { + return HAL_LL_UART_WRONG_PINS; + }; + + hal_ll_uart_init( hal_ll_uart_hw_specifics_map_local ); + + hal_ll_module_state[pin_check_result].hal_ll_uart_handle = (handle_t *)&hal_ll_uart_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_uart_set_baud( handle_t *handle, uint32_t baud ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->baud_rate.baud = baud; + + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return hal_ll_uart_hw_specifics_map_local->baud_rate.real_baud; +} + +hal_ll_err_t hal_ll_uart_set_parity( handle_t *handle, hal_ll_uart_parity_t parity ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->parity = parity; + + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_uart_set_stop_bits( handle_t *handle, hal_ll_uart_stop_bits_t stop_bit ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->stop_bit = stop_bit; + + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_uart_set_data_bits( handle_t *handle, hal_ll_uart_data_bits_t data_bit ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + // Chips using implementation 1 do not support 7 bit data + if( data_bit == HAL_LL_UART_DATA_BITS_7 ) { + return HAL_LL_UART_MODULE_ERROR; + } + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->data_bit = data_bit; + + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +void hal_ll_uart_close( handle_t *handle ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + if( low_level_handle->hal_ll_uart_handle != NULL ) { + hal_ll_uart_alternate_functions_set_state( hal_ll_uart_hw_specifics_map_local, false ); + + hal_ll_uart_irq_disable(handle, HAL_LL_UART_IRQ_RX); + hal_ll_uart_irq_disable(handle, HAL_LL_UART_IRQ_TX); + + hal_ll_uart_clear_regs(hal_ll_uart_hw_specifics_map_local->base); + hal_ll_uart_set_clock(hal_ll_uart_hw_specifics_map_local, false); + + hal_ll_uart_hw_specifics_map_local->pins.tx_pin.pin_name = HAL_LL_PIN_NC; + hal_ll_uart_hw_specifics_map_local->pins.tx_pin.pin_af = 0; + hal_ll_uart_hw_specifics_map_local->pins.rx_pin.pin_name = HAL_LL_PIN_NC; + hal_ll_uart_hw_specifics_map_local->pins.rx_pin.pin_af = 0; + + hal_ll_uart_hw_specifics_map_local->baud_rate.baud = 115200UL; + hal_ll_uart_hw_specifics_map_local->baud_rate.real_baud = 0; + + irq_handler = NULL; + objects[ hal_ll_uart_find_index( handle ) ] = NULL; + + low_level_handle->hal_ll_uart_handle = NULL; + low_level_handle->hal_drv_uart_handle = NULL; + + low_level_handle->init_ll_state = false; + } +} + +void hal_ll_uart_register_irq_handler( handle_t *handle, hal_ll_uart_isr_t handler, handle_t obj ) +{ + irq_handler = handler; + objects[ hal_ll_uart_find_index( handle ) ] = obj; +} + +void hal_ll_uart_irq_enable( handle_t *handle, hal_ll_uart_irq_t irq ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + switch ( irq ) { + case HAL_LL_UART_IRQ_RX: + __HAL_LL_UART_ENABLE_IT( hal_ll_hw_reg, HAL_LL_UART_IT_RXNE ); + break; + + case HAL_LL_UART_IRQ_TX: + __HAL_LL_UART_ENABLE_IT( hal_ll_hw_reg, HAL_LL_UART_IT_TXE ); + break; + + default: + break; + } + + switch ( hal_ll_uart_hw_specifics_map_local->module_index ) + { + #if defined(UART_MODULE_1) && defined(UART1_NVIC) + case hal_ll_uart_module_num(UART_MODULE_1): + hal_ll_core_enable_irq( UART1_NVIC ); + break; + #endif + + #if defined(UART_MODULE_2) && defined(UART2_NVIC) + case hal_ll_uart_module_num(UART_MODULE_2): + hal_ll_core_enable_irq( UART2_NVIC ); + break; + #endif + + #if defined(UART_MODULE_3) && defined(UART3_NVIC) + case hal_ll_uart_module_num(UART_MODULE_3): + hal_ll_core_enable_irq( UART3_NVIC ); + break; + #endif + + #if defined(UART_MODULE_4) && defined(UART4_NVIC) + case hal_ll_uart_module_num(UART_MODULE_4): + hal_ll_core_enable_irq( UART4_NVIC ); + break; + #endif + + #if defined(UART_MODULE_5) && defined(UART5_NVIC) + case hal_ll_uart_module_num(UART_MODULE_5): + hal_ll_core_enable_irq( UART5_NVIC ); + break; + #endif + + + default: + break; + } +} + +void hal_ll_uart_irq_disable( handle_t *handle, hal_ll_uart_irq_t irq ) +{ + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + switch ( irq ) { + case HAL_LL_UART_IRQ_RX: + __HAL_LL_UART_DISABLE_IT( hal_ll_hw_reg, HAL_LL_UART_IT_RXNE ); + break; + + case HAL_LL_UART_IRQ_TX: + __HAL_LL_UART_DISABLE_IT( hal_ll_hw_reg, HAL_LL_UART_IT_TXE ); + break; + + default: + break; + } + + // Check if module interrupt flags are set or not + if ( ( !check_reg_bit( &hal_ll_hw_reg->cr1, HAL_LL_UART_SR_RXNE ) ) && + ( !check_reg_bit( &hal_ll_hw_reg->cr1, HAL_LL_UART_SR_TXE ) ) ) + { + switch ( hal_ll_uart_hw_specifics_map_local->module_index ) + { + #if defined(UART_MODULE_1) && defined(UART1_NVIC) + case hal_ll_uart_module_num(UART_MODULE_1): + hal_ll_core_disable_irq( UART1_NVIC ); + break; + #endif + + #if defined(UART_MODULE_2) && defined(UART2_NVIC) + case hal_ll_uart_module_num(UART_MODULE_2): + hal_ll_core_disable_irq( UART2_NVIC ); + break; + #endif + + #if defined(UART_MODULE_3) && defined(UART3_NVIC) + case hal_ll_uart_module_num(UART_MODULE_3): + hal_ll_core_disable_irq( UART3_NVIC ); + break; + #endif + + #if defined(UART_MODULE_4) && defined(UART4_NVIC) + case hal_ll_uart_module_num(UART_MODULE_4): + hal_ll_core_disable_irq( UART4_NVIC ); + break; + #endif + + #if defined(UART_MODULE_5) && defined(UART5_NVIC) + case hal_ll_uart_module_num(UART_MODULE_5): + hal_ll_core_disable_irq( UART5_NVIC ); + break; + #endif + + + default: + break; + } + } +} + +void hal_ll_uart_write( handle_t *handle, uint8_t wr_data) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + hal_ll_hw_reg->tdr = wr_data; +} + +uint8_t hal_ll_uart_read( handle_t *handle ) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + return ( hal_ll_hw_reg->rdr ); +} + +// ------------------------------------------------------------- DEFAULT EXCEPTION HANDLERS + +#if defined(USART_MODULE_1) +void MARK_AS_IRQ_HANDLER UART1_IRQHandler() MIKROC_IV(UART1_NVIC) { + #ifdef USART_MODULE_1 + if( hal_ll_uart_get_status_flags( HAL_LL_USART1_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART1_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART1_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_1) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_USART1_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART1_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART1_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_1) ], HAL_LL_UART_IRQ_TX ); + } + } + #endif +} +#endif + +#if defined(USART_MODULE_2) +void MARK_AS_IRQ_HANDLER UART2_IRQHandler() MIKROC_IV(UART2_NVIC) { + #ifdef USART_MODULE_2 + if( hal_ll_uart_get_status_flags( HAL_LL_USART2_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART2_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART2_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_2) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_USART2_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART2_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART2_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_2) ], HAL_LL_UART_IRQ_TX ); + } + } + #endif +} +#endif + +#if defined(USART_MODULE_3) +void MARK_AS_IRQ_HANDLER UART3_IRQHandler() MIKROC_IV(UART3_NVIC) { + #ifdef USART_MODULE_3 + if( hal_ll_uart_get_status_flags( HAL_LL_USART3_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART3_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART3_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_3) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_USART3_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART3_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART3_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_3) ], HAL_LL_UART_IRQ_TX ); + } + } + #endif +} +#endif + +#if defined(UART_MODULE_4) +void MARK_AS_IRQ_HANDLER UART4_IRQHandler() MIKROC_IV(UART4_NVIC) { + #ifdef UART_MODULE_4 + if( hal_ll_uart_get_status_flags( HAL_LL_UART4_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_UART4_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_UART4_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(UART_MODULE_4) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_UART4_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_UART4_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_UART4_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(UART_MODULE_4) ], HAL_LL_UART_IRQ_TX ); + } + } + #endif +} +#endif + +#if defined(UART_MODULE_5) +void MARK_AS_IRQ_HANDLER UART5_IRQHandler() MIKROC_IV(UART5_NVIC) { + #ifdef UART_MODULE_5 + if( hal_ll_uart_get_status_flags( HAL_LL_UART5_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_UART5_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_UART5_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(UART_MODULE_5) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_UART5_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_UART5_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_UART5_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(UART_MODULE_5) ], HAL_LL_UART_IRQ_TX ); + } + } + #endif +} +#endif + +#if defined(LPUART_MODULE_1) +void MARK_AS_IRQ_HANDLER LPUART1_IRQHandler() MIKROC_IV(LPUART1_NVIC) { + #ifdef LPUART_MODULE_1 + if( hal_ll_uart_get_status_flags( HAL_LL_LPUART1_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_LPUART1_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_LPUART1_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(LPUART_MODULE_1) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_LPUART1_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_LPUART1_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_LPUART1_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(LPUART_MODULE_1) ], HAL_LL_UART_IRQ_TX ); + } + } + #endif +} +#endif + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static uint8_t hal_ll_uart_find_index( handle_t *handle ) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + if( hal_ll_uart_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + return hal_ll_uart_hw_specifics_map_local->module_index; + } else { + return NULL; + } +} + +static hal_ll_pin_name_t hal_ll_uart_check_pins( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_uart_pin_id *index_list, hal_ll_uart_handle_register_t *handle_map ) { + static const uint16_t tx_map_size = ( sizeof( hal_ll_uart_tx_map ) / sizeof( hal_ll_uart_pin_map_t ) ); + static const uint16_t rx_map_size = ( sizeof( hal_ll_uart_rx_map ) / sizeof( hal_ll_uart_pin_map_t ) ); + uint8_t hal_ll_module_id = 0; + uint8_t index_counter = 0; + uint16_t tx_index; + uint16_t rx_index; + + if ( (HAL_LL_PIN_NC == tx_pin) || (HAL_LL_PIN_NC == rx_pin) ) { + return HAL_LL_PIN_NC; + } + + for ( tx_index = 0; tx_index < tx_map_size; tx_index++ ) + { + if ( hal_ll_uart_tx_map[ tx_index ].pin == tx_pin ) + { + for ( rx_index = 0; rx_index < rx_map_size; rx_index++ ) + { + if ( hal_ll_uart_rx_map[ rx_index ].pin == rx_pin ) + { + if ( hal_ll_uart_tx_map[ tx_index ].base == hal_ll_uart_rx_map[ rx_index ].base ) { + // Get module number + hal_ll_module_id = hal_ll_uart_tx_map[ tx_index ].module_index; + + // Map pin names + index_list[hal_ll_module_id].pin_tx = tx_index; + index_list[hal_ll_module_id].pin_rx = rx_index; + + // Check if module is taken + if ( NULL == handle_map[ hal_ll_module_id ].hal_drv_uart_handle ) { + return hal_ll_module_id; + } else if ( UART_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static hal_ll_uart_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof(hal_ll_uart_handle_register_t)); + static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof(hal_ll_uart_handle_register_t)); + + while( hal_ll_module_count-- ) { + if (hal_ll_uart_get_base_from_hal_handle == hal_ll_uart_hw_specifics_map[hal_ll_module_count].base) { + return &hal_ll_uart_hw_specifics_map[hal_ll_module_count]; + } + } + + return &hal_ll_uart_hw_specifics_map[hal_ll_module_error]; +} + +static void hal_ll_uart_set_clock( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ) { + switch ( map->module_index ) + { + #ifdef UART_MODULE_1 + case ( hal_ll_uart_module_num(UART_MODULE_1) ): + (hal_ll_state == true)?(set_reg_bit( _RCC_APB2ENR, HAL_LL_USART1EN )):(clear_reg_bit( _RCC_APB2ENR, HAL_LL_USART1EN )); + break; + #endif + + #ifdef UART_MODULE_2 + case ( hal_ll_uart_module_num(UART_MODULE_2) ): + (hal_ll_state == true)?(set_reg_bit( _RCC_APB1ENR1, HAL_LL_USART2EN )):(clear_reg_bit( _RCC_APB1ENR1, HAL_LL_USART2EN )); + break; + #endif + + #ifdef UART_MODULE_3 + case ( hal_ll_uart_module_num(UART_MODULE_3) ): + (hal_ll_state == true)?(set_reg_bit( _RCC_APB1ENR1, HAL_LL_USART3EN )):(clear_reg_bit( _RCC_APB1ENR1, HAL_LL_USART3EN )); + break; + #endif + + #ifdef UART_MODULE_4 + case ( hal_ll_uart_module_num(UART_MODULE_4) ): + (hal_ll_state == true)?(set_reg_bit( _RCC_APB1ENR1, HAL_LL_USART4EN )):(clear_reg_bit( _RCC_APB1ENR1, HAL_LL_USART4EN )); + break; + #endif + + #ifdef UART_MODULE_5 + case ( hal_ll_uart_module_num(UART_MODULE_5) ): + (hal_ll_state == true)?(set_reg_bit( _RCC_APB1ENR1, HAL_LL_USART5EN )):(clear_reg_bit( _RCC_APB1ENR1, HAL_LL_USART5EN )); + break; + #endif + + + default: + break; + } +} + +static void hal_ll_uart_map_pins( uint8_t module_index, hal_ll_uart_pin_id *index_list ) { + // Map new pins + hal_ll_uart_hw_specifics_map[module_index].pins.tx_pin.pin_name = hal_ll_uart_tx_map[ index_list[module_index].pin_tx ].pin; + hal_ll_uart_hw_specifics_map[module_index].pins.rx_pin.pin_name = hal_ll_uart_rx_map[ index_list[module_index].pin_rx ].pin; + // TX and RX could have different alternate function settings, hence save both AF values + hal_ll_uart_hw_specifics_map[module_index].pins.tx_pin.pin_af = hal_ll_uart_tx_map[ index_list[module_index].pin_tx ].af; + hal_ll_uart_hw_specifics_map[module_index].pins.rx_pin.pin_af = hal_ll_uart_rx_map[ index_list[module_index].pin_rx ].af; +} + +static void hal_ll_uart_alternate_functions_set_state( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ) { + module_struct module; + + if ( (map->pins.tx_pin.pin_name != HAL_LL_PIN_NC) && map->pins.rx_pin.pin_name != HAL_LL_PIN_NC ) { + module.pins[0] = VALUE( map->pins.tx_pin.pin_name, map->pins.tx_pin.pin_af ); + module.pins[1] = VALUE( map->pins.rx_pin.pin_name, map->pins.rx_pin.pin_af ); + module.pins[2] = GPIO_MODULE_STRUCT_END; + + module.configs[0] = HAL_LL_UART_AF_CONFIG; + module.configs[1] = HAL_LL_UART_AF_CONFIG; + module.configs[2] = GPIO_MODULE_STRUCT_END; + + /* STM32F1xx specific */ + module.gpio_remap = map->pins.tx_pin.pin_af; + + hal_ll_gpio_module_struct_init( &module, hal_ll_state ); + } +} + +static void hal_ll_uart_set_baud_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + uint32_t reg = 0; + uint32_t integer_divider = 0; + uint32_t fractional_divider = 0; + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); + uint32_t hal_ll_baud_value = hal_ll_uart_get_baud(hal_ll_uart_get_clock_speed(map->module_index),map->baud_rate.baud,4); + uint32_t hal_ll_baud_real_value = hal_ll_uart_get_real_baud(hal_ll_uart_get_clock_speed(map->module_index),hal_ll_baud_value,4); + + // if error greater than specified, cancel setting baud rate + if( (hal_ll_uart_get_baud_error(hal_ll_baud_real_value,map->baud_rate.baud)) > HAL_LL_UART_ACCEPTABLE_ERROR ) { + map->baud_rate.real_baud = hal_ll_uart_get_baud_error(hal_ll_baud_real_value,map->baud_rate.baud); + } else { + map->baud_rate.real_baud = hal_ll_baud_real_value; + + integer_divider = ( ( 25 * hal_ll_uart_get_clock_speed( map->module_index ) ) / ( 4 * ( map->baud_rate.baud ) ) ); + reg = ( integer_divider / 100 ) << 4; + + fractional_divider = integer_divider - ( 100 * ( reg >> 4 ) ); + reg |= ( ( ( ( fractional_divider * 16 ) + 50 ) / 100 ) ) & 0x0F; + + hal_ll_hw_reg->brr = ( uint16_t )reg; + } +} + +static uint32_t hal_ll_uart_get_clock_speed( hal_ll_pin_name_t module_index ) { + rcc_clocks_t rcc_clocks; + + RCC_GetClocksFrequency( &rcc_clocks ); + + switch ( module_index ) + { + #ifdef UART_MODULE_1 + case ( hal_ll_uart_module_num(UART_MODULE_1) ): + return rcc_clocks.pclk2; + break; + #endif + + #ifdef UART_MODULE_2 + case ( hal_ll_uart_module_num(UART_MODULE_2) ): + return rcc_clocks.pclk1; + break; + #endif + + #ifdef UART_MODULE_3 + case ( hal_ll_uart_module_num(UART_MODULE_3) ): + return rcc_clocks.pclk1; + break; + #endif + + #ifdef UART_MODULE_4 + case ( hal_ll_uart_module_num(UART_MODULE_4) ): + return rcc_clocks.pclk1; + break; + #endif + + #ifdef UART_MODULE_5 + case ( hal_ll_uart_module_num(UART_MODULE_5) ): + return rcc_clocks.pclk1; + break; + #endif + + + default: + break; + } + + return NULL; +} + +static void hal_ll_uart_set_stop_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); + + switch ( map->stop_bit ) + { + case HAL_LL_UART_STOP_BITS_HALF: + hal_ll_hw_reg->cr2 |= STOP_BITS_HALF; + break; + case HAL_LL_UART_STOP_BITS_ONE: + hal_ll_hw_reg->cr2 |= STOP_BITS_ONE; + break; + case HAL_LL_UART_STOP_BITS_ONE_AND_A_HALF: + hal_ll_hw_reg->cr2 |= STOP_BITS_ONE_AND_A_HALF; + break; + case HAL_LL_UART_STOP_BITS_TWO: + hal_ll_hw_reg->cr2 |= STOP_BITS_TWO; + break; + + default: + break; + } +} + +static void hal_ll_uart_set_data_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); + + switch ( map->data_bit ) + { + case HAL_LL_UART_DATA_BITS_7: + hal_ll_hw_reg->cr1 |= DATA_BIT_7; + break; + + case HAL_LL_UART_DATA_BITS_8: + hal_ll_hw_reg->cr1 |= DATA_BIT_8; + break; + + case HAL_LL_UART_DATA_BITS_9: + hal_ll_hw_reg->cr1 |= DATA_BIT_9; + break; + + + default: + break; + } +} + +static void hal_ll_uart_set_parity_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); + + switch ( map->parity ) + { + case HAL_LL_UART_PARITY_NONE: + hal_ll_hw_reg->cr1 |= PARITY_NO; + break; + case HAL_LL_UART_PARITY_EVEN: + hal_ll_hw_reg->cr1 |= PARITY_ENABLED | PARITY_EVEN; + break; + case HAL_LL_UART_PARITY_ODD: + hal_ll_hw_reg->cr1 |= PARITY_ENABLED | PARITY_ODD; + break; + + default: + break; + } +} + +static void hal_ll_uart_set_module( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ) { + switch ( pin_state ) + { + case HAL_LL_UART_DISABLE: + clear_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_UE ); + break; + + case HAL_LL_UART_ENABLE: + set_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_UE ); + break; + + default: + break; + } +} + +static void hal_ll_uart_set_transmitter( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ) { + switch ( pin_state ) + { + case HAL_LL_UART_DISABLE: + clear_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_TE ); + break; + + case HAL_LL_UART_ENABLE: + set_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_TE ); + break; + + default: + break; + } +} + +static void hal_ll_uart_set_receiver( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ) { + switch ( pin_state ) + { + case HAL_LL_UART_DISABLE: + clear_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_RE ); + break; + + case HAL_LL_UART_ENABLE: + set_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_RE ); + break; + + default: + break; + } +} + +static void hal_ll_uart_clear_regs( hal_ll_uart_base_handle_t *hal_ll_hw_reg ) { + hal_ll_hw_reg->cr1 &= HAL_LL_UART_IT_CR1_MASK; + hal_ll_hw_reg->cr2 &= HAL_LL_UART_IT_CR2_MASK; + hal_ll_hw_reg->cr3 &= HAL_LL_UART_IT_CR3_MASK; +} + +static void hal_ll_uart_hw_init( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_clear_regs( map->base ); + + hal_ll_uart_set_data_bits_bare_metal( map ); + + hal_ll_uart_set_parity_bare_metal( map ); + + hal_ll_uart_set_stop_bits_bare_metal( map ); + + hal_ll_uart_set_baud_bare_metal( map ); + + hal_ll_uart_set_transmitter( map->base, HAL_LL_UART_ENABLE ); + + hal_ll_uart_set_receiver( map->base, HAL_LL_UART_ENABLE ); + + hal_ll_uart_set_module( map->base, HAL_LL_UART_ENABLE ); +} + +static void hal_ll_uart_init( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_set_clock( map, true ); + + hal_ll_uart_alternate_functions_set_state( map, true ); + + hal_ll_uart_hw_init( map ); +} +// ------------------------------------------------------------------------- END + diff --git a/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_89/CMakeLists.cmake b/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_89/CMakeLists.cmake new file mode 100644 index 000000000..ae048cf2e --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_89/CMakeLists.cmake @@ -0,0 +1,9 @@ +if(${MCU_NAME} MATCHES "^STM32G4A1CE$|^STM32G4A1KE$|^STM32G4A1ME$|^STM32G4A1RE$|^STM32G4A1VE$") + set(uart_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_uart.c") + set(rcc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/rcc/implementations/doc_ds_89") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/doc_ds_89") + list(APPEND hal_ll_def_list "STM32G4xx") + list(APPEND hal_ll_def_list "STM32G4Axx") + list(APPEND hal_ll_def_list "STM32G4A1xx") + set(uart_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/uart/hal_ll_uart_pin_map/implementations/doc_ds_89") +endif() diff --git a/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_89/hal_ll_uart.c b/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_89/hal_ll_uart.c new file mode 100644 index 000000000..f6304e601 --- /dev/null +++ b/targets/arm/mikroe/ai_generated/stm32/src/uart/implementations/doc_ds_89/hal_ll_uart.c @@ -0,0 +1,1255 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_uart.c + * @brief UART HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_rcc.h" +#include "hal_ll_uart.h" +#include "hal_ll_gpio.h" +#include "hal_ll_core.h" +#include "hal_ll_core_defines.h" +#include "hal_ll_uart_pin_map.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_uart_handle_register_t hal_ll_module_state[UART_MODULE_COUNT] = { (handle_t *)NULL, (handle_t *)NULL, false }; + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_uart_get_module_state_address ((hal_ll_uart_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_uart_get_handle (hal_ll_uart_handle_register_t *)hal_ll_uart_get_module_state_address->hal_ll_uart_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_uart_get_base_struct(_handle) ((hal_ll_uart_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_uart_get_base_from_hal_handle ((hal_ll_uart_hw_specifics_map_t *)((hal_ll_uart_handle_register_t *)\ + (((hal_ll_uart_handle_register_t *)(handle))->hal_ll_uart_handle))->hal_ll_uart_handle)->base + +/*!< @brief Macros used for calculating actual baud rate value and error value */ +#define HAL_LL_UART_ACCEPTABLE_ERROR (float)1.0 +#define hal_ll_uart_get_baud(_clock,_baud,_div) (((_clock/(float)_baud)/_div)-1) +#define hal_ll_uart_get_real_baud(_clock,_baud,_div) (_clock/(_div*(_baud+1))) +#define hal_ll_uart_get_baud_error(_baud_real,_baud) (((float)(abs(_baud_real-_baud))/_baud)*100) + +/*!< @brief Macros defining bit location */ +#define HAL_LL_USART1EN 14 + +#define HAL_LL_USART2EN 17 + +#define HAL_LL_USART3EN 18 + +#define HAL_LL_USART4EN 19 + +#define HAL_LL_USART5EN 20 + + +#define HAL_LL_UART_CR1_UE 0 +#define HAL_LL_UART_CR1_TE 3 +#define HAL_LL_UART_CR1_RE 2 + +#define HAL_LL_UART_SR_RXNE 5 +#define HAL_LL_UART_SR_TXE 7 + +/*!< @brief Macros defining register bit values */ +#define STOP_BITS_HALF 0x1000U +#define STOP_BITS_ONE 0x00U +#define STOP_BITS_ONE_AND_A_HALF 0x3000U +#define STOP_BITS_TWO 0x2000U + +#define DATA_BIT_7 0x10000000U +#define DATA_BIT_8 0x00U +#define DATA_BIT_9 0x1000U + +#define PARITY_NO 0x00U +#define PARITY_ENABLED 0x400U + +#define PARITY_EVEN 0x00U +#define PARITY_ODD 0x200U + +/*!< @brief Macro used for setting pin alternate functions */ +#define HAL_LL_UART_AF_CONFIG (GPIO_CFG_MODE_ALT_FUNCTION | GPIO_CFG_SPEED_HIGH | GPIO_CFG_OTYPE_PP) + +/*!< @brief Macros used for interrupts */ +#define HAL_LL_UART_IT_MASK 0xFFFFUL +#define HAL_LL_UART_IT_CLEAR_MASK 0x123afeU +#define HAL_LL_UART_IT_CR1_MASK 0x1f0U +#define HAL_LL_UART_IT_CR2_MASK 0x40U +#define HAL_LL_UART_IT_CR3_MASK 0x401U + +#define HAL_LL_UART_CR1_REG_INDEX 1 +#define HAL_LL_UART_CR2_REG_INDEX 2 +#define HAL_LL_UART_CR3_REG_INDEX 3 + +#define HAL_LL_UART_IT_PE 0x100U +#define HAL_LL_UART_IT_TXE (0x10000000 | 0x80U) +#define HAL_LL_UART_IT_TC 0x40U +#define HAL_LL_UART_IT_RXNE (0x10000000 | 0x20U) +#define HAL_LL_UART_IT_IDLE 0x10U +#define HAL_LL_UART_IT_LBD 0x40U +#define HAL_LL_UART_IT_CTS 0x400U +#define HAL_LL_UART_IT_ERR 0x01U + +#define HAL_LL_UART_STATUS_RXNE_FLAG 0x20U +#define HAL_LL_UART_STATUS_TXE_FLAG 0x80U + +/*!< @brief Macro used for status registed flag check + * Used in interrupt handlers. + */ +#define hal_ll_uart_get_status_flags(_handle,_flag) (((hal_ll_uart_base_handle_t *)_handle)->isr & _flag) + +/*!< @brief Macro used for status register flag clearing + * Used in interrupt handlers. + */ +#define hal_ll_uart_clear_status_flag(_handle,_flag) (set_reg_bit( &(((hal_ll_uart_base_handle_t *)_handle)->icr), ( _flag & HAL_LL_UART_IT_CLEAR_MASK ) ) ) + +/*!< @brief Macro used for module interrupt enabling. + * Used in interrupt handlers. + */ +#define __HAL_LL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__ >> 28UL) == HAL_LL_UART_CR1_REG_INDEX)? (__HANDLE__->cr1 |= (__INTERRUPT__ & HAL_LL_UART_IT_MASK)): \ + ((__INTERRUPT__ >> 28UL) == HAL_LL_UART_CR2_REG_INDEX)? (__HANDLE__->cr2 |= (__INTERRUPT__ & HAL_LL_UART_IT_MASK)): \ + (__HANDLE__->cr3 |= (__INTERRUPT__ & HAL_LL_UART_IT_MASK))) + +/*!< @brief Macro used for module interrupt disabling. + * Used in interrupt handlers. + */ +#define __HAL_LL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__ >> 28UL) == HAL_LL_UART_CR1_REG_INDEX)? (__HANDLE__->cr1 &= ~(__INTERRUPT__ & HAL_LL_UART_IT_MASK)): \ + ((__INTERRUPT__ >> 28UL) == HAL_LL_UART_CR2_REG_INDEX)? (__HANDLE__->cr2 &= ~(__INTERRUPT__ & HAL_LL_UART_IT_MASK)): \ + (__HANDLE__->cr3 &= ~ (__INTERRUPT__ & HAL_LL_UART_IT_MASK))) + +/*!< @brief Macro used for module interrupt source check. + * Used in interrupt handlers. + */ +#define __HAL_LL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__ >> 28UL) == 1UL)? ((hal_ll_uart_base_handle_t *)__HANDLE__)->cr1:((((uint32_t)__INTERRUPT__ >> 28UL) == 2UL)? \ + ((hal_ll_uart_base_handle_t *)__HANDLE__)->cr2 : ((hal_ll_uart_base_handle_t *)__HANDLE__)->cr3)) & ((uint32_t)__INTERRUPT__ & HAL_LL_UART_IT_MASK)) + +/*!< @brief UART HW register structure */ +typedef struct +{ + hal_ll_base_addr_t cr1; + hal_ll_base_addr_t cr2; + hal_ll_base_addr_t cr3; + hal_ll_base_addr_t brr; + hal_ll_base_addr_t gtpr; + hal_ll_base_addr_t rtor; + hal_ll_base_addr_t rqr; + hal_ll_base_addr_t isr; + hal_ll_base_addr_t icr; + hal_ll_base_addr_t rdr; + hal_ll_base_addr_t tdr; + hal_ll_base_addr_t presc; + +} hal_ll_uart_base_handle_t; + +/*!< @brief UART baud rate structure */ +typedef struct +{ + uint32_t baud; + uint32_t real_baud; +} hal_ll_uart_baud_t; + +/*!< @brief UART hw specific structure */ +typedef struct +{ + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + hal_ll_uart_pins_t pins; + hal_ll_uart_baud_t baud_rate; + hal_ll_uart_parity_t parity; + hal_ll_uart_stop_bits_t stop_bit; + hal_ll_uart_data_bits_t data_bit; +} hal_ll_uart_hw_specifics_map_t; + +/*!< @brief UART hw specific module values */ +typedef struct +{ + uint16_t pin_tx; + uint16_t pin_rx; +} hal_ll_uart_pin_id; + +/*!< @brief UART hw specific error values */ +typedef enum +{ + HAL_LL_UART_SUCCESS = 0, + HAL_LL_UART_WRONG_PINS, + HAL_LL_UART_MODULE_ERROR, + + HAL_LL_UART_ERROR = (-1) +} hal_ll_uart_err_t; + +/*!< @brief UART module state selection */ +typedef enum +{ + HAL_LL_UART_DISABLE = 0, + HAL_LL_UART_ENABLE +} hal_ll_uart_state_t; + +// ------------------------------------------------------------------ VARIABLES +/*!< @brief UART hardware specific info */ +static hal_ll_uart_hw_specifics_map_t hal_ll_uart_hw_specifics_map[] = +{ + #ifdef UART_MODULE_1 + {HAL_LL_UART1_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_1), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + + #ifdef UART_MODULE_2 + {HAL_LL_UART2_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_2), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + + #ifdef UART_MODULE_3 + {HAL_LL_UART3_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_3), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + + #ifdef UART_MODULE_4 + {HAL_LL_UART4_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_4), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + + #ifdef UART_MODULE_5 + {HAL_LL_UART5_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_5), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + + + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {0, 0}, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR} +}; + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_uart_handle_register_t *low_level_handle; +static volatile hal_ll_uart_hw_specifics_map_t *hal_ll_uart_hw_specifics_map_local; + +/*!< @brief Global interrupt handlers used in functions */ +static hal_ll_uart_isr_t irq_handler; +static handle_t objects[UART_MODULE_COUNT]; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Check if pins are adequate. + * + * Checks tx and rx pins the user has passed with pre-defined + * pins in tx and rx maps. Take into consideration that module + * index numbers have to be the same for both pins. + * + * @param[in] tx_pin - TX pre-defined pin name. + * @param[in] rx_pin - RX pre-defined pin name. + * @param[in] *index_list - Array containing map index numbers. + * @return hal_ll_pin_name_t Module index based on pins. + * + * Returns pre-defined module index from pin maps, if pins + * are adequate. + */ +static hal_ll_pin_name_t hal_ll_uart_check_pins( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_uart_pin_id *index_list, hal_ll_uart_handle_register_t *handle_map ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * TX and RX pins. + * + * @param[in] module_index UART HW module index -- 0,1,2... + * @param[in] *index_list Array with TX and RX map index values + * and module number + * + * @return None + */ +static void hal_ll_uart_map_pins( uint8_t module_index, hal_ll_uart_pin_id *index_list ); + +/** + * @brief Sets UART pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if UART is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_state - Init/De-init + * + * @return void None. + */ +static void hal_ll_uart_alternate_functions_set_state( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_uart_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_uart_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_uart_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Enable clock for UART module on hardware level. + * + * Initializes UART module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_stat - True(enable clock)/False(disable clock). + * + * @return void None. + */ +static void hal_ll_uart_set_clock( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Finds UART module index. + * + * Finds UART index(module number) based on + * handle value. + * + * @param[in] handle - Object specific context handler. + * + * @return uint8_t Module number. + * Returns values from 0 to 9. + */ +static uint8_t hal_ll_uart_find_index( handle_t *handle ); + +/** + * @brief Get UART module clock speed. + * + * Returns adequate clock speed based on + * UART module base address. + * + * @param[in] module_index - UART module index number. + * + * @return uint8_t Module number. + * Returns clock value. + */ +static uint32_t hal_ll_uart_get_clock_speed( hal_ll_pin_name_t module_index ); + +/** + * @brief Clears UART registers. + * + * Clears UART module configuration + * registers, effectively disabling the module itself. + * Take into consideration that any IRQ bits + * are not cleared. + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * + * @return void None. + */ +static void hal_ll_uart_clear_regs( hal_ll_uart_base_handle_t *hal_ll_hw_reg ); + +/** + * @brief Sets desired baud rate on hardware level. + * + * Initializes module with specified baud rate value. + * Take into consideration that if the difference + * between desired baud rate and actual baud + * rate the hw was initialized to is greater than + * 1%, baud rate shall not be set. + * If this occurs, return value shall be + * the error percentage. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_set_baud_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Sets desired stop bits. + * + * Initializes module on hardware level + * with specified stop bit value. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_set_stop_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Sets desired data bits. + * + * Initializes module on hardware level + * with specified data bit bit value. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_set_data_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Sets desired parity. + * + * Initializes module on hardware level + * with specified parity value. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_set_parity_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Sets module clock value. + * + * Enables/disables specific UART module + * clock gate. + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * @param[in] pin_state - true(enable clock) / false(disable clock) + * + * @return void None. + */ +static void hal_ll_uart_set_module( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ); + +/** + * @brief Sets module TX line state. + * + * Enables/disables specific UART module + * TX pin state + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * @param[in] pin_state - true(enable transmitter pin) / false(disable transmitter pin) + * + * @return void None. + */ +static void hal_ll_uart_set_transmitter( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ); + +/** + * @brief Sets module RX line state. + * + * Enables/disables specific UART module + * RX pin state + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * @param[in] pin_state - true(enable receive pin) / false(disable receive pin) + * + * @return void None. + */ +static void hal_ll_uart_set_receiver( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ); + +/** + * @brief Initialize UART module. + * + * Enables UART module clogk gate first. + * Sets pin alternate function state. + * Initializes specific UART module. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_init( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Initialize UART module on the hardware level. + * + * Performs UART module initialization on + * the hardware level. + * + * Procedure: + * 1. Clears control registers + * 2. Sets data bit value + * 3. Sets parity value + * 4. Sets stop bit value + * 5. Sets baud rate value + * 6. Enables transmit pin + * 7. Enables receive pin + * 8. Enables clock gate for specific module + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_hw_init( hal_ll_uart_hw_specifics_map_t *map ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_uart_register_handle( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_uart_handle_register_t *handle_map, uint8_t *hal_module_id ) { + + hal_ll_uart_pin_id index_list[UART_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + uint16_t pin_check_result; + + // Check if pins are valid + if ( (pin_check_result = hal_ll_uart_check_pins( tx_pin, rx_pin, &index_list, handle_map )) == HAL_LL_PIN_NC ) { + return HAL_LL_UART_WRONG_PINS; + }; + + if ( (hal_ll_uart_hw_specifics_map[pin_check_result].pins.tx_pin.pin_name != tx_pin) || + (hal_ll_uart_hw_specifics_map[pin_check_result].pins.rx_pin.pin_name != rx_pin) ) + { + hal_ll_uart_alternate_functions_set_state( &hal_ll_uart_hw_specifics_map[ pin_check_result ], false ); + + hal_ll_uart_map_pins( pin_check_result, &index_list ); + + hal_ll_uart_alternate_functions_set_state( &hal_ll_uart_hw_specifics_map[ pin_check_result ], true ); + + handle_map[pin_check_result].init_ll_state = false; + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[pin_check_result].hal_ll_uart_handle = (handle_t *)&hal_ll_uart_hw_specifics_map[pin_check_result].base; + + handle_map[pin_check_result].hal_ll_uart_handle = (handle_t *)&hal_ll_module_state[pin_check_result].hal_ll_uart_handle; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_uart( handle_t *handle ) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + hal_ll_uart_pin_id index_list[UART_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + uint16_t pin_check_result; + + if ( (pin_check_result = hal_ll_uart_check_pins( hal_ll_uart_hw_specifics_map_local->pins.tx_pin.pin_name, + hal_ll_uart_hw_specifics_map_local->pins.rx_pin.pin_name, &index_list, (void *)0 ) ) == HAL_LL_PIN_NC ) { + return HAL_LL_UART_WRONG_PINS; + }; + + hal_ll_uart_init( hal_ll_uart_hw_specifics_map_local ); + + hal_ll_module_state[pin_check_result].hal_ll_uart_handle = (handle_t *)&hal_ll_uart_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_uart_set_baud( handle_t *handle, uint32_t baud ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->baud_rate.baud = baud; + + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return hal_ll_uart_hw_specifics_map_local->baud_rate.real_baud; +} + +hal_ll_err_t hal_ll_uart_set_parity( handle_t *handle, hal_ll_uart_parity_t parity ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->parity = parity; + + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_uart_set_stop_bits( handle_t *handle, hal_ll_uart_stop_bits_t stop_bit ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->stop_bit = stop_bit; + + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_uart_set_data_bits( handle_t *handle, hal_ll_uart_data_bits_t data_bit ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + // Chips using implementation 1 do not support 7 bit data + if( data_bit == HAL_LL_UART_DATA_BITS_7 ) { + return HAL_LL_UART_MODULE_ERROR; + } + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->data_bit = data_bit; + + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +void hal_ll_uart_close( handle_t *handle ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + if( low_level_handle->hal_ll_uart_handle != NULL ) { + hal_ll_uart_alternate_functions_set_state( hal_ll_uart_hw_specifics_map_local, false ); + + hal_ll_uart_irq_disable(handle, HAL_LL_UART_IRQ_RX); + hal_ll_uart_irq_disable(handle, HAL_LL_UART_IRQ_TX); + + hal_ll_uart_clear_regs(hal_ll_uart_hw_specifics_map_local->base); + hal_ll_uart_set_clock(hal_ll_uart_hw_specifics_map_local, false); + + hal_ll_uart_hw_specifics_map_local->pins.tx_pin.pin_name = HAL_LL_PIN_NC; + hal_ll_uart_hw_specifics_map_local->pins.tx_pin.pin_af = 0; + hal_ll_uart_hw_specifics_map_local->pins.rx_pin.pin_name = HAL_LL_PIN_NC; + hal_ll_uart_hw_specifics_map_local->pins.rx_pin.pin_af = 0; + + hal_ll_uart_hw_specifics_map_local->baud_rate.baud = 115200UL; + hal_ll_uart_hw_specifics_map_local->baud_rate.real_baud = 0; + + irq_handler = NULL; + objects[ hal_ll_uart_find_index( handle ) ] = NULL; + + low_level_handle->hal_ll_uart_handle = NULL; + low_level_handle->hal_drv_uart_handle = NULL; + + low_level_handle->init_ll_state = false; + } +} + +void hal_ll_uart_register_irq_handler( handle_t *handle, hal_ll_uart_isr_t handler, handle_t obj ) +{ + irq_handler = handler; + objects[ hal_ll_uart_find_index( handle ) ] = obj; +} + +void hal_ll_uart_irq_enable( handle_t *handle, hal_ll_uart_irq_t irq ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + switch ( irq ) { + case HAL_LL_UART_IRQ_RX: + __HAL_LL_UART_ENABLE_IT( hal_ll_hw_reg, HAL_LL_UART_IT_RXNE ); + break; + + case HAL_LL_UART_IRQ_TX: + __HAL_LL_UART_ENABLE_IT( hal_ll_hw_reg, HAL_LL_UART_IT_TXE ); + break; + + default: + break; + } + + switch ( hal_ll_uart_hw_specifics_map_local->module_index ) + { + #if defined(UART_MODULE_1) && defined(UART1_NVIC) + case hal_ll_uart_module_num(UART_MODULE_1): + hal_ll_core_enable_irq( UART1_NVIC ); + break; + #endif + + #if defined(UART_MODULE_2) && defined(UART2_NVIC) + case hal_ll_uart_module_num(UART_MODULE_2): + hal_ll_core_enable_irq( UART2_NVIC ); + break; + #endif + + #if defined(UART_MODULE_3) && defined(UART3_NVIC) + case hal_ll_uart_module_num(UART_MODULE_3): + hal_ll_core_enable_irq( UART3_NVIC ); + break; + #endif + + #if defined(UART_MODULE_4) && defined(UART4_NVIC) + case hal_ll_uart_module_num(UART_MODULE_4): + hal_ll_core_enable_irq( UART4_NVIC ); + break; + #endif + + #if defined(UART_MODULE_5) && defined(UART5_NVIC) + case hal_ll_uart_module_num(UART_MODULE_5): + hal_ll_core_enable_irq( UART5_NVIC ); + break; + #endif + + + default: + break; + } +} + +void hal_ll_uart_irq_disable( handle_t *handle, hal_ll_uart_irq_t irq ) +{ + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + switch ( irq ) { + case HAL_LL_UART_IRQ_RX: + __HAL_LL_UART_DISABLE_IT( hal_ll_hw_reg, HAL_LL_UART_IT_RXNE ); + break; + + case HAL_LL_UART_IRQ_TX: + __HAL_LL_UART_DISABLE_IT( hal_ll_hw_reg, HAL_LL_UART_IT_TXE ); + break; + + default: + break; + } + + // Check if module interrupt flags are set or not + if ( ( !check_reg_bit( &hal_ll_hw_reg->cr1, HAL_LL_UART_SR_RXNE ) ) && + ( !check_reg_bit( &hal_ll_hw_reg->cr1, HAL_LL_UART_SR_TXE ) ) ) + { + switch ( hal_ll_uart_hw_specifics_map_local->module_index ) + { + #if defined(UART_MODULE_1) && defined(UART1_NVIC) + case hal_ll_uart_module_num(UART_MODULE_1): + hal_ll_core_disable_irq( UART1_NVIC ); + break; + #endif + + #if defined(UART_MODULE_2) && defined(UART2_NVIC) + case hal_ll_uart_module_num(UART_MODULE_2): + hal_ll_core_disable_irq( UART2_NVIC ); + break; + #endif + + #if defined(UART_MODULE_3) && defined(UART3_NVIC) + case hal_ll_uart_module_num(UART_MODULE_3): + hal_ll_core_disable_irq( UART3_NVIC ); + break; + #endif + + #if defined(UART_MODULE_4) && defined(UART4_NVIC) + case hal_ll_uart_module_num(UART_MODULE_4): + hal_ll_core_disable_irq( UART4_NVIC ); + break; + #endif + + #if defined(UART_MODULE_5) && defined(UART5_NVIC) + case hal_ll_uart_module_num(UART_MODULE_5): + hal_ll_core_disable_irq( UART5_NVIC ); + break; + #endif + + + default: + break; + } + } +} + +void hal_ll_uart_write( handle_t *handle, uint8_t wr_data) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + hal_ll_hw_reg->tdr = wr_data; +} + +uint8_t hal_ll_uart_read( handle_t *handle ) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + return ( hal_ll_hw_reg->rdr ); +} + +// ------------------------------------------------------------- DEFAULT EXCEPTION HANDLERS + +#if defined(USART_MODULE_1) +void MARK_AS_IRQ_HANDLER UART1_IRQHandler() MIKROC_IV(UART1_NVIC) { + #ifdef USART_MODULE_1 + if( hal_ll_uart_get_status_flags( HAL_LL_USART1_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART1_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART1_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_1) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_USART1_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART1_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART1_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_1) ], HAL_LL_UART_IRQ_TX ); + } + } + #endif +} +#endif + +#if defined(USART_MODULE_2) +void MARK_AS_IRQ_HANDLER UART2_IRQHandler() MIKROC_IV(UART2_NVIC) { + #ifdef USART_MODULE_2 + if( hal_ll_uart_get_status_flags( HAL_LL_USART2_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART2_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART2_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_2) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_USART2_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART2_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART2_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_2) ], HAL_LL_UART_IRQ_TX ); + } + } + #endif +} +#endif + +#if defined(USART_MODULE_3) +void MARK_AS_IRQ_HANDLER UART3_IRQHandler() MIKROC_IV(UART3_NVIC) { + #ifdef USART_MODULE_3 + if( hal_ll_uart_get_status_flags( HAL_LL_USART3_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART3_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART3_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_3) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_USART3_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_USART3_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_USART3_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(USART_MODULE_3) ], HAL_LL_UART_IRQ_TX ); + } + } + #endif +} +#endif + +#if defined(UART_MODULE_4) +void MARK_AS_IRQ_HANDLER UART4_IRQHandler() MIKROC_IV(UART4_NVIC) { + #ifdef UART_MODULE_4 + if( hal_ll_uart_get_status_flags( HAL_LL_UART4_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_UART4_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_UART4_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(UART_MODULE_4) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_UART4_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_UART4_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_UART4_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(UART_MODULE_4) ], HAL_LL_UART_IRQ_TX ); + } + } + #endif +} +#endif + +#if defined(UART_MODULE_5) +void MARK_AS_IRQ_HANDLER UART5_IRQHandler() MIKROC_IV(UART5_NVIC) { + #ifdef UART_MODULE_5 + if( hal_ll_uart_get_status_flags( HAL_LL_UART5_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_UART5_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_UART5_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(UART_MODULE_5) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_UART5_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_UART5_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_UART5_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(UART_MODULE_5) ], HAL_LL_UART_IRQ_TX ); + } + } + #endif +} +#endif + +#if defined(LPUART_MODULE_1) +void MARK_AS_IRQ_HANDLER LPUART1_IRQHandler() MIKROC_IV(LPUART1_NVIC) { + #ifdef LPUART_MODULE_1 + if( hal_ll_uart_get_status_flags( HAL_LL_LPUART1_BASE_ADDRESS , HAL_LL_UART_STATUS_RXNE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_LPUART1_BASE_ADDRESS, HAL_LL_UART_IT_RXNE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_LPUART1_BASE_ADDRESS, HAL_LL_UART_STATUS_RXNE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(LPUART_MODULE_1) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_LPUART1_BASE_ADDRESS , HAL_LL_UART_STATUS_TXE_FLAG ) ) { + if( ( __HAL_LL_UART_GET_IT_SOURCE( HAL_LL_LPUART1_BASE_ADDRESS, HAL_LL_UART_IT_TXE ) ) != 0 ) { + hal_ll_uart_clear_status_flag( HAL_LL_LPUART1_BASE_ADDRESS, HAL_LL_UART_STATUS_TXE_FLAG ); + irq_handler( objects[ hal_ll_uart_module_num(LPUART_MODULE_1) ], HAL_LL_UART_IRQ_TX ); + } + } + #endif +} +#endif + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static uint8_t hal_ll_uart_find_index( handle_t *handle ) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + if( hal_ll_uart_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + return hal_ll_uart_hw_specifics_map_local->module_index; + } else { + return NULL; + } +} + +static hal_ll_pin_name_t hal_ll_uart_check_pins( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_uart_pin_id *index_list, hal_ll_uart_handle_register_t *handle_map ) { + static const uint16_t tx_map_size = ( sizeof( hal_ll_uart_tx_map ) / sizeof( hal_ll_uart_pin_map_t ) ); + static const uint16_t rx_map_size = ( sizeof( hal_ll_uart_rx_map ) / sizeof( hal_ll_uart_pin_map_t ) ); + uint8_t hal_ll_module_id = 0; + uint8_t index_counter = 0; + uint16_t tx_index; + uint16_t rx_index; + + if ( (HAL_LL_PIN_NC == tx_pin) || (HAL_LL_PIN_NC == rx_pin) ) { + return HAL_LL_PIN_NC; + } + + for ( tx_index = 0; tx_index < tx_map_size; tx_index++ ) + { + if ( hal_ll_uart_tx_map[ tx_index ].pin == tx_pin ) + { + for ( rx_index = 0; rx_index < rx_map_size; rx_index++ ) + { + if ( hal_ll_uart_rx_map[ rx_index ].pin == rx_pin ) + { + if ( hal_ll_uart_tx_map[ tx_index ].base == hal_ll_uart_rx_map[ rx_index ].base ) { + // Get module number + hal_ll_module_id = hal_ll_uart_tx_map[ tx_index ].module_index; + + // Map pin names + index_list[hal_ll_module_id].pin_tx = tx_index; + index_list[hal_ll_module_id].pin_rx = rx_index; + + // Check if module is taken + if ( NULL == handle_map[ hal_ll_module_id ].hal_drv_uart_handle ) { + return hal_ll_module_id; + } else if ( UART_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static hal_ll_uart_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof(hal_ll_uart_handle_register_t)); + static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof(hal_ll_uart_handle_register_t)); + + while( hal_ll_module_count-- ) { + if (hal_ll_uart_get_base_from_hal_handle == hal_ll_uart_hw_specifics_map[hal_ll_module_count].base) { + return &hal_ll_uart_hw_specifics_map[hal_ll_module_count]; + } + } + + return &hal_ll_uart_hw_specifics_map[hal_ll_module_error]; +} + +static void hal_ll_uart_set_clock( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ) { + switch ( map->module_index ) + { + #ifdef UART_MODULE_1 + case ( hal_ll_uart_module_num(UART_MODULE_1) ): + (hal_ll_state == true)?(set_reg_bit( _RCC_APB2ENR, HAL_LL_USART1EN )):(clear_reg_bit( _RCC_APB2ENR, HAL_LL_USART1EN )); + break; + #endif + + #ifdef UART_MODULE_2 + case ( hal_ll_uart_module_num(UART_MODULE_2) ): + (hal_ll_state == true)?(set_reg_bit( _RCC_APB1ENR1, HAL_LL_USART2EN )):(clear_reg_bit( _RCC_APB1ENR1, HAL_LL_USART2EN )); + break; + #endif + + #ifdef UART_MODULE_3 + case ( hal_ll_uart_module_num(UART_MODULE_3) ): + (hal_ll_state == true)?(set_reg_bit( _RCC_APB1ENR1, HAL_LL_USART3EN )):(clear_reg_bit( _RCC_APB1ENR1, HAL_LL_USART3EN )); + break; + #endif + + #ifdef UART_MODULE_4 + case ( hal_ll_uart_module_num(UART_MODULE_4) ): + (hal_ll_state == true)?(set_reg_bit( _RCC_APB1ENR1, HAL_LL_USART4EN )):(clear_reg_bit( _RCC_APB1ENR1, HAL_LL_USART4EN )); + break; + #endif + + #ifdef UART_MODULE_5 + case ( hal_ll_uart_module_num(UART_MODULE_5) ): + (hal_ll_state == true)?(set_reg_bit( _RCC_APB1ENR1, HAL_LL_USART5EN )):(clear_reg_bit( _RCC_APB1ENR1, HAL_LL_USART5EN )); + break; + #endif + + + default: + break; + } +} + +static void hal_ll_uart_map_pins( uint8_t module_index, hal_ll_uart_pin_id *index_list ) { + // Map new pins + hal_ll_uart_hw_specifics_map[module_index].pins.tx_pin.pin_name = hal_ll_uart_tx_map[ index_list[module_index].pin_tx ].pin; + hal_ll_uart_hw_specifics_map[module_index].pins.rx_pin.pin_name = hal_ll_uart_rx_map[ index_list[module_index].pin_rx ].pin; + // TX and RX could have different alternate function settings, hence save both AF values + hal_ll_uart_hw_specifics_map[module_index].pins.tx_pin.pin_af = hal_ll_uart_tx_map[ index_list[module_index].pin_tx ].af; + hal_ll_uart_hw_specifics_map[module_index].pins.rx_pin.pin_af = hal_ll_uart_rx_map[ index_list[module_index].pin_rx ].af; +} + +static void hal_ll_uart_alternate_functions_set_state( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ) { + module_struct module; + + if ( (map->pins.tx_pin.pin_name != HAL_LL_PIN_NC) && map->pins.rx_pin.pin_name != HAL_LL_PIN_NC ) { + module.pins[0] = VALUE( map->pins.tx_pin.pin_name, map->pins.tx_pin.pin_af ); + module.pins[1] = VALUE( map->pins.rx_pin.pin_name, map->pins.rx_pin.pin_af ); + module.pins[2] = GPIO_MODULE_STRUCT_END; + + module.configs[0] = HAL_LL_UART_AF_CONFIG; + module.configs[1] = HAL_LL_UART_AF_CONFIG; + module.configs[2] = GPIO_MODULE_STRUCT_END; + + /* STM32F1xx specific */ + module.gpio_remap = map->pins.tx_pin.pin_af; + + hal_ll_gpio_module_struct_init( &module, hal_ll_state ); + } +} + +static void hal_ll_uart_set_baud_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + uint32_t reg = 0; + uint32_t integer_divider = 0; + uint32_t fractional_divider = 0; + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); + uint32_t hal_ll_baud_value = hal_ll_uart_get_baud(hal_ll_uart_get_clock_speed(map->module_index),map->baud_rate.baud,4); + uint32_t hal_ll_baud_real_value = hal_ll_uart_get_real_baud(hal_ll_uart_get_clock_speed(map->module_index),hal_ll_baud_value,4); + + // if error greater than specified, cancel setting baud rate + if( (hal_ll_uart_get_baud_error(hal_ll_baud_real_value,map->baud_rate.baud)) > HAL_LL_UART_ACCEPTABLE_ERROR ) { + map->baud_rate.real_baud = hal_ll_uart_get_baud_error(hal_ll_baud_real_value,map->baud_rate.baud); + } else { + map->baud_rate.real_baud = hal_ll_baud_real_value; + + integer_divider = ( ( 25 * hal_ll_uart_get_clock_speed( map->module_index ) ) / ( 4 * ( map->baud_rate.baud ) ) ); + reg = ( integer_divider / 100 ) << 4; + + fractional_divider = integer_divider - ( 100 * ( reg >> 4 ) ); + reg |= ( ( ( ( fractional_divider * 16 ) + 50 ) / 100 ) ) & 0x0F; + + hal_ll_hw_reg->brr = ( uint16_t )reg; + } +} + +static uint32_t hal_ll_uart_get_clock_speed( hal_ll_pin_name_t module_index ) { + rcc_clocks_t rcc_clocks; + + RCC_GetClocksFrequency( &rcc_clocks ); + + switch ( module_index ) + { + #ifdef UART_MODULE_1 + case ( hal_ll_uart_module_num(UART_MODULE_1) ): + return rcc_clocks.pclk2; + break; + #endif + + #ifdef UART_MODULE_2 + case ( hal_ll_uart_module_num(UART_MODULE_2) ): + return rcc_clocks.pclk1; + break; + #endif + + #ifdef UART_MODULE_3 + case ( hal_ll_uart_module_num(UART_MODULE_3) ): + return rcc_clocks.pclk1; + break; + #endif + + #ifdef UART_MODULE_4 + case ( hal_ll_uart_module_num(UART_MODULE_4) ): + return rcc_clocks.pclk1; + break; + #endif + + #ifdef UART_MODULE_5 + case ( hal_ll_uart_module_num(UART_MODULE_5) ): + return rcc_clocks.pclk1; + break; + #endif + + + default: + break; + } + + return NULL; +} + +static void hal_ll_uart_set_stop_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); + + switch ( map->stop_bit ) + { + case HAL_LL_UART_STOP_BITS_HALF: + hal_ll_hw_reg->cr2 |= STOP_BITS_HALF; + break; + case HAL_LL_UART_STOP_BITS_ONE: + hal_ll_hw_reg->cr2 |= STOP_BITS_ONE; + break; + case HAL_LL_UART_STOP_BITS_ONE_AND_A_HALF: + hal_ll_hw_reg->cr2 |= STOP_BITS_ONE_AND_A_HALF; + break; + case HAL_LL_UART_STOP_BITS_TWO: + hal_ll_hw_reg->cr2 |= STOP_BITS_TWO; + break; + + default: + break; + } +} + +static void hal_ll_uart_set_data_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); + + switch ( map->data_bit ) + { + case HAL_LL_UART_DATA_BITS_7: + hal_ll_hw_reg->cr1 |= DATA_BIT_7; + break; + + case HAL_LL_UART_DATA_BITS_8: + hal_ll_hw_reg->cr1 |= DATA_BIT_8; + break; + + case HAL_LL_UART_DATA_BITS_9: + hal_ll_hw_reg->cr1 |= DATA_BIT_9; + break; + + + default: + break; + } +} + +static void hal_ll_uart_set_parity_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); + + switch ( map->parity ) + { + case HAL_LL_UART_PARITY_NONE: + hal_ll_hw_reg->cr1 |= PARITY_NO; + break; + case HAL_LL_UART_PARITY_EVEN: + hal_ll_hw_reg->cr1 |= PARITY_ENABLED | PARITY_EVEN; + break; + case HAL_LL_UART_PARITY_ODD: + hal_ll_hw_reg->cr1 |= PARITY_ENABLED | PARITY_ODD; + break; + + default: + break; + } +} + +static void hal_ll_uart_set_module( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ) { + switch ( pin_state ) + { + case HAL_LL_UART_DISABLE: + clear_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_UE ); + break; + + case HAL_LL_UART_ENABLE: + set_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_UE ); + break; + + default: + break; + } +} + +static void hal_ll_uart_set_transmitter( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ) { + switch ( pin_state ) + { + case HAL_LL_UART_DISABLE: + clear_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_TE ); + break; + + case HAL_LL_UART_ENABLE: + set_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_TE ); + break; + + default: + break; + } +} + +static void hal_ll_uart_set_receiver( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ) { + switch ( pin_state ) + { + case HAL_LL_UART_DISABLE: + clear_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_RE ); + break; + + case HAL_LL_UART_ENABLE: + set_reg_bit( &( hal_ll_hw_reg->cr1 ), HAL_LL_UART_CR1_RE ); + break; + + default: + break; + } +} + +static void hal_ll_uart_clear_regs( hal_ll_uart_base_handle_t *hal_ll_hw_reg ) { + hal_ll_hw_reg->cr1 &= HAL_LL_UART_IT_CR1_MASK; + hal_ll_hw_reg->cr2 &= HAL_LL_UART_IT_CR2_MASK; + hal_ll_hw_reg->cr3 &= HAL_LL_UART_IT_CR3_MASK; +} + +static void hal_ll_uart_hw_init( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_clear_regs( map->base ); + + hal_ll_uart_set_data_bits_bare_metal( map ); + + hal_ll_uart_set_parity_bare_metal( map ); + + hal_ll_uart_set_stop_bits_bare_metal( map ); + + hal_ll_uart_set_baud_bare_metal( map ); + + hal_ll_uart_set_transmitter( map->base, HAL_LL_UART_ENABLE ); + + hal_ll_uart_set_receiver( map->base, HAL_LL_UART_ENABLE ); + + hal_ll_uart_set_module( map->base, HAL_LL_UART_ENABLE ); +} + +static void hal_ll_uart_init( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_set_clock( map, true ); + + hal_ll_uart_alternate_functions_set_state( map, true ); + + hal_ll_uart_hw_init( map ); +} +// ------------------------------------------------------------------------- END + diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32C011D6/WLCSP12/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32C011D6/WLCSP12/mcu_definitions.h new file mode 100644 index 000000000..1f914da9e --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32C011D6/WLCSP12/mcu_definitions.h @@ -0,0 +1,253 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32C011D6_WLCSP12. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA11_CH11 +#define ADC1_PA12_CH12 +#define ADC1_PA13_CH13 +#define ADC1_PA14_CH14 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PA8_CH8 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN + +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (54) +#define DMA_NUM_OF_CHANNELS_FAMILY (54) +#define DMA_NUM_OF_MODULES (1) +#define DMA_NUM_OF_STREAMS (3) +#define DMA_NUM_OF_STREAMS_FAMILY (3) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB7_AF14 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PC14_AF14 + +#define I2C_MODULE_1 (1) + +#define I2C_MODULE_COUNT (1) +// EOF I2C + +// U(S)ART +#define USART1_RX_PA10_AF1 +#define USART1_RX_PA1_AF4 +#define USART1_RX_PA8_AF14 +#define USART1_RX_PB7_AF0 +#define USART1_TX_PA0_AF4 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART1_TX_PC14_AF0 +#define USART2_RX_PA13_AF4 +#define USART2_RX_PA14_AF9 +#define USART2_RX_PA3_AF1 +#define USART2_RX_PA5_AF1 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 +#define USART2_TX_PA4_AF1 +#define USART2_TX_PA8_AF1 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (2) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB6_AF9 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB6_AF8 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB6_AF10 + +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// TIM +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PA8_AF13 +#define TIM16_BKIN_PB6_AF14 +#define TIM16_CH1N_PA2_AF2 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA0_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB7_AF10 +#define TIM17_BKIN_PA10_AF5 +#define TIM17_BKIN_PB6_AF15 +#define TIM17_CH1N_PA4_AF5 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA1_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PC14_AF10 +#define TIM1_BKIN2_PA11_AF5 +#define TIM1_BKIN2_PC14_AF2 +#define TIM1_BKIN_PA6_AF2 +#define TIM1_CH1N_PA3_AF2 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1_PA0_AF5 +#define TIM1_CH1_PA14_AF10 +#define TIM1_CH1_PA5_AF5 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH2N_PA4_AF2 +#define TIM1_CH2N_PA8_AF9 +#define TIM1_CH2_PA1_AF5 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB6_AF11 +#define TIM1_CH3N_PA5_AF2 +#define TIM1_CH3N_PA8_AF10 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PA2_AF5 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_CH4_PA3_AF5 +#define TIM1_CH4_PB7_AF1 +#define TIM1_CH4_PF2_AF1 +#define TIM1_ETR_PA12_AF2 +#define TIM1_ETR_PC14_AF1 +#define TIM1_ETR_PC15_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB6_AF12 +#define TIM3_CH1_PB7_AF11 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB6_AF13 +#define TIM3_CH2_PC14_AF11 +#define TIM3_CH3_PA8_AF11 +#define TIM3_CH3_PB6_AF3 +#define TIM3_CH3_PC15_AF3 +#define TIM3_CH4_PA8_AF12 +#define TIM3_CH4_PB7_AF3 +#define TIM3_ETR_PA13_AF3 +#define TIM3_ETR_PA2_AF3 +#define TIM3_ETR_PA9_AF3 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_3 (2) +#define TIM_MODULE_14 (3) +#define TIM_MODULE_16 (4) +#define TIM_MODULE_17 (5) + +#define TIM_MODULE_COUNT (5) + +#define TIM1_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB6_CN +#define __PB7_CN +#define __PC14_CN +#define __PC15_CN +#define __PF2_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN + +#define PORT_COUNT (4) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32C011F4/TSSOP20/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32C011F4/TSSOP20/mcu_definitions.h new file mode 100644 index 000000000..88204514a --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32C011F4/TSSOP20/mcu_definitions.h @@ -0,0 +1,253 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32C011F4_TSSOP20. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA11_CH11 +#define ADC1_PA12_CH12 +#define ADC1_PA13_CH13 +#define ADC1_PA14_CH14 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PA8_CH8 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN + +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (54) +#define DMA_NUM_OF_CHANNELS_FAMILY (54) +#define DMA_NUM_OF_MODULES (1) +#define DMA_NUM_OF_STREAMS (3) +#define DMA_NUM_OF_STREAMS_FAMILY (3) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB7_AF14 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PC14_AF14 + +#define I2C_MODULE_1 (1) + +#define I2C_MODULE_COUNT (1) +// EOF I2C + +// U(S)ART +#define USART1_RX_PA10_AF1 +#define USART1_RX_PA1_AF4 +#define USART1_RX_PA8_AF14 +#define USART1_RX_PB7_AF0 +#define USART1_TX_PA0_AF4 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART1_TX_PC14_AF0 +#define USART2_RX_PA13_AF4 +#define USART2_RX_PA14_AF9 +#define USART2_RX_PA3_AF1 +#define USART2_RX_PA5_AF1 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 +#define USART2_TX_PA4_AF1 +#define USART2_TX_PA8_AF1 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (2) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB6_AF9 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB6_AF8 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB6_AF10 + +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// TIM +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PA8_AF13 +#define TIM16_BKIN_PB6_AF14 +#define TIM16_CH1N_PA2_AF2 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA0_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB7_AF10 +#define TIM17_BKIN_PA10_AF5 +#define TIM17_BKIN_PB6_AF15 +#define TIM17_CH1N_PA4_AF5 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA1_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PC14_AF10 +#define TIM1_BKIN2_PA11_AF5 +#define TIM1_BKIN2_PC14_AF2 +#define TIM1_BKIN_PA6_AF2 +#define TIM1_CH1N_PA3_AF2 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1_PA0_AF5 +#define TIM1_CH1_PA14_AF10 +#define TIM1_CH1_PA5_AF5 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH2N_PA4_AF2 +#define TIM1_CH2N_PA8_AF9 +#define TIM1_CH2_PA1_AF5 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB6_AF11 +#define TIM1_CH3N_PA5_AF2 +#define TIM1_CH3N_PA8_AF10 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PA2_AF5 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_CH4_PA3_AF5 +#define TIM1_CH4_PB7_AF1 +#define TIM1_CH4_PF2_AF1 +#define TIM1_ETR_PA12_AF2 +#define TIM1_ETR_PC14_AF1 +#define TIM1_ETR_PC15_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB6_AF12 +#define TIM3_CH1_PB7_AF11 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB6_AF13 +#define TIM3_CH2_PC14_AF11 +#define TIM3_CH3_PA8_AF11 +#define TIM3_CH3_PB6_AF3 +#define TIM3_CH3_PC15_AF3 +#define TIM3_CH4_PA8_AF12 +#define TIM3_CH4_PB7_AF3 +#define TIM3_ETR_PA13_AF3 +#define TIM3_ETR_PA2_AF3 +#define TIM3_ETR_PA9_AF3 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_3 (2) +#define TIM_MODULE_14 (3) +#define TIM_MODULE_16 (4) +#define TIM_MODULE_17 (5) + +#define TIM_MODULE_COUNT (5) + +#define TIM1_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB6_CN +#define __PB7_CN +#define __PC14_CN +#define __PC15_CN +#define __PF2_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN + +#define PORT_COUNT (4) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32C011F4/UFQFPN20/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32C011F4/UFQFPN20/mcu_definitions.h new file mode 100644 index 000000000..640067e7d --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32C011F4/UFQFPN20/mcu_definitions.h @@ -0,0 +1,253 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32C011F4_UFQFPN20. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA11_CH11 +#define ADC1_PA12_CH12 +#define ADC1_PA13_CH13 +#define ADC1_PA14_CH14 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PA8_CH8 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN + +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (54) +#define DMA_NUM_OF_CHANNELS_FAMILY (54) +#define DMA_NUM_OF_MODULES (1) +#define DMA_NUM_OF_STREAMS (3) +#define DMA_NUM_OF_STREAMS_FAMILY (3) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB7_AF14 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PC14_AF14 + +#define I2C_MODULE_1 (1) + +#define I2C_MODULE_COUNT (1) +// EOF I2C + +// U(S)ART +#define USART1_RX_PA10_AF1 +#define USART1_RX_PA1_AF4 +#define USART1_RX_PA8_AF14 +#define USART1_RX_PB7_AF0 +#define USART1_TX_PA0_AF4 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART1_TX_PC14_AF0 +#define USART2_RX_PA13_AF4 +#define USART2_RX_PA14_AF9 +#define USART2_RX_PA3_AF1 +#define USART2_RX_PA5_AF1 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 +#define USART2_TX_PA4_AF1 +#define USART2_TX_PA8_AF1 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (2) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB6_AF9 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB6_AF8 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB6_AF10 + +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// TIM +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PA8_AF13 +#define TIM16_BKIN_PB6_AF14 +#define TIM16_CH1N_PA2_AF2 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA0_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB7_AF10 +#define TIM17_BKIN_PA10_AF5 +#define TIM17_BKIN_PB6_AF15 +#define TIM17_CH1N_PA4_AF5 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA1_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PC14_AF10 +#define TIM1_BKIN2_PA11_AF5 +#define TIM1_BKIN2_PC14_AF2 +#define TIM1_BKIN_PA6_AF2 +#define TIM1_CH1N_PA3_AF2 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1_PA0_AF5 +#define TIM1_CH1_PA14_AF10 +#define TIM1_CH1_PA5_AF5 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH2N_PA4_AF2 +#define TIM1_CH2N_PA8_AF9 +#define TIM1_CH2_PA1_AF5 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB6_AF11 +#define TIM1_CH3N_PA5_AF2 +#define TIM1_CH3N_PA8_AF10 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PA2_AF5 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_CH4_PA3_AF5 +#define TIM1_CH4_PB7_AF1 +#define TIM1_CH4_PF2_AF1 +#define TIM1_ETR_PA12_AF2 +#define TIM1_ETR_PC14_AF1 +#define TIM1_ETR_PC15_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB6_AF12 +#define TIM3_CH1_PB7_AF11 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB6_AF13 +#define TIM3_CH2_PC14_AF11 +#define TIM3_CH3_PA8_AF11 +#define TIM3_CH3_PB6_AF3 +#define TIM3_CH3_PC15_AF3 +#define TIM3_CH4_PA8_AF12 +#define TIM3_CH4_PB7_AF3 +#define TIM3_ETR_PA13_AF3 +#define TIM3_ETR_PA2_AF3 +#define TIM3_ETR_PA9_AF3 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_3 (2) +#define TIM_MODULE_14 (3) +#define TIM_MODULE_16 (4) +#define TIM_MODULE_17 (5) + +#define TIM_MODULE_COUNT (5) + +#define TIM1_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB6_CN +#define __PB7_CN +#define __PC14_CN +#define __PC15_CN +#define __PF2_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN + +#define PORT_COUNT (4) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32C011F6/TSSOP20/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32C011F6/TSSOP20/mcu_definitions.h new file mode 100644 index 000000000..16a220302 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32C011F6/TSSOP20/mcu_definitions.h @@ -0,0 +1,253 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32C011F6_TSSOP20. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA11_CH11 +#define ADC1_PA12_CH12 +#define ADC1_PA13_CH13 +#define ADC1_PA14_CH14 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PA8_CH8 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN + +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (54) +#define DMA_NUM_OF_CHANNELS_FAMILY (54) +#define DMA_NUM_OF_MODULES (1) +#define DMA_NUM_OF_STREAMS (3) +#define DMA_NUM_OF_STREAMS_FAMILY (3) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB7_AF14 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PC14_AF14 + +#define I2C_MODULE_1 (1) + +#define I2C_MODULE_COUNT (1) +// EOF I2C + +// U(S)ART +#define USART1_RX_PA10_AF1 +#define USART1_RX_PA1_AF4 +#define USART1_RX_PA8_AF14 +#define USART1_RX_PB7_AF0 +#define USART1_TX_PA0_AF4 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART1_TX_PC14_AF0 +#define USART2_RX_PA13_AF4 +#define USART2_RX_PA14_AF9 +#define USART2_RX_PA3_AF1 +#define USART2_RX_PA5_AF1 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 +#define USART2_TX_PA4_AF1 +#define USART2_TX_PA8_AF1 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (2) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB6_AF9 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB6_AF8 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB6_AF10 + +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// TIM +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PA8_AF13 +#define TIM16_BKIN_PB6_AF14 +#define TIM16_CH1N_PA2_AF2 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA0_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB7_AF10 +#define TIM17_BKIN_PA10_AF5 +#define TIM17_BKIN_PB6_AF15 +#define TIM17_CH1N_PA4_AF5 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA1_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PC14_AF10 +#define TIM1_BKIN2_PA11_AF5 +#define TIM1_BKIN2_PC14_AF2 +#define TIM1_BKIN_PA6_AF2 +#define TIM1_CH1N_PA3_AF2 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1_PA0_AF5 +#define TIM1_CH1_PA14_AF10 +#define TIM1_CH1_PA5_AF5 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH2N_PA4_AF2 +#define TIM1_CH2N_PA8_AF9 +#define TIM1_CH2_PA1_AF5 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB6_AF11 +#define TIM1_CH3N_PA5_AF2 +#define TIM1_CH3N_PA8_AF10 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PA2_AF5 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_CH4_PA3_AF5 +#define TIM1_CH4_PB7_AF1 +#define TIM1_CH4_PF2_AF1 +#define TIM1_ETR_PA12_AF2 +#define TIM1_ETR_PC14_AF1 +#define TIM1_ETR_PC15_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB6_AF12 +#define TIM3_CH1_PB7_AF11 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB6_AF13 +#define TIM3_CH2_PC14_AF11 +#define TIM3_CH3_PA8_AF11 +#define TIM3_CH3_PB6_AF3 +#define TIM3_CH3_PC15_AF3 +#define TIM3_CH4_PA8_AF12 +#define TIM3_CH4_PB7_AF3 +#define TIM3_ETR_PA13_AF3 +#define TIM3_ETR_PA2_AF3 +#define TIM3_ETR_PA9_AF3 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_3 (2) +#define TIM_MODULE_14 (3) +#define TIM_MODULE_16 (4) +#define TIM_MODULE_17 (5) + +#define TIM_MODULE_COUNT (5) + +#define TIM1_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB6_CN +#define __PB7_CN +#define __PC14_CN +#define __PC15_CN +#define __PF2_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN + +#define PORT_COUNT (4) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32C011F6/UFQFPN20/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32C011F6/UFQFPN20/mcu_definitions.h new file mode 100644 index 000000000..4b7de11a5 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32C011F6/UFQFPN20/mcu_definitions.h @@ -0,0 +1,253 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32C011F6_UFQFPN20. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA11_CH11 +#define ADC1_PA12_CH12 +#define ADC1_PA13_CH13 +#define ADC1_PA14_CH14 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PA8_CH8 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN + +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (54) +#define DMA_NUM_OF_CHANNELS_FAMILY (54) +#define DMA_NUM_OF_MODULES (1) +#define DMA_NUM_OF_STREAMS (3) +#define DMA_NUM_OF_STREAMS_FAMILY (3) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB7_AF14 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PC14_AF14 + +#define I2C_MODULE_1 (1) + +#define I2C_MODULE_COUNT (1) +// EOF I2C + +// U(S)ART +#define USART1_RX_PA10_AF1 +#define USART1_RX_PA1_AF4 +#define USART1_RX_PA8_AF14 +#define USART1_RX_PB7_AF0 +#define USART1_TX_PA0_AF4 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART1_TX_PC14_AF0 +#define USART2_RX_PA13_AF4 +#define USART2_RX_PA14_AF9 +#define USART2_RX_PA3_AF1 +#define USART2_RX_PA5_AF1 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 +#define USART2_TX_PA4_AF1 +#define USART2_TX_PA8_AF1 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (2) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB6_AF9 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB6_AF8 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB6_AF10 + +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// TIM +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PA8_AF13 +#define TIM16_BKIN_PB6_AF14 +#define TIM16_CH1N_PA2_AF2 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA0_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB7_AF10 +#define TIM17_BKIN_PA10_AF5 +#define TIM17_BKIN_PB6_AF15 +#define TIM17_CH1N_PA4_AF5 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA1_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PC14_AF10 +#define TIM1_BKIN2_PA11_AF5 +#define TIM1_BKIN2_PC14_AF2 +#define TIM1_BKIN_PA6_AF2 +#define TIM1_CH1N_PA3_AF2 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1_PA0_AF5 +#define TIM1_CH1_PA14_AF10 +#define TIM1_CH1_PA5_AF5 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH2N_PA4_AF2 +#define TIM1_CH2N_PA8_AF9 +#define TIM1_CH2_PA1_AF5 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB6_AF11 +#define TIM1_CH3N_PA5_AF2 +#define TIM1_CH3N_PA8_AF10 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PA2_AF5 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_CH4_PA3_AF5 +#define TIM1_CH4_PB7_AF1 +#define TIM1_CH4_PF2_AF1 +#define TIM1_ETR_PA12_AF2 +#define TIM1_ETR_PC14_AF1 +#define TIM1_ETR_PC15_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB6_AF12 +#define TIM3_CH1_PB7_AF11 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB6_AF13 +#define TIM3_CH2_PC14_AF11 +#define TIM3_CH3_PA8_AF11 +#define TIM3_CH3_PB6_AF3 +#define TIM3_CH3_PC15_AF3 +#define TIM3_CH4_PA8_AF12 +#define TIM3_CH4_PB7_AF3 +#define TIM3_ETR_PA13_AF3 +#define TIM3_ETR_PA2_AF3 +#define TIM3_ETR_PA9_AF3 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_3 (2) +#define TIM_MODULE_14 (3) +#define TIM_MODULE_16 (4) +#define TIM_MODULE_17 (5) + +#define TIM_MODULE_COUNT (5) + +#define TIM1_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB6_CN +#define __PB7_CN +#define __PC14_CN +#define __PC15_CN +#define __PF2_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN + +#define PORT_COUNT (4) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32C011J4/SO8N/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32C011J4/SO8N/mcu_definitions.h new file mode 100644 index 000000000..3cc2df4fd --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32C011J4/SO8N/mcu_definitions.h @@ -0,0 +1,223 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32C011J4_SO8N. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA11_CH11 +#define ADC1_PA12_CH12 +#define ADC1_PA13_CH13 +#define ADC1_PA14_CH14 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA8_CH8 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN + +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (54) +#define DMA_NUM_OF_CHANNELS_FAMILY (54) +#define DMA_NUM_OF_MODULES (1) +#define DMA_NUM_OF_STREAMS (3) +#define DMA_NUM_OF_STREAMS_FAMILY (3) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB7_AF14 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PC14_AF14 + +#define I2C_MODULE_1 (1) + +#define I2C_MODULE_COUNT (1) +// EOF I2C + +// U(S)ART +#define USART1_RX_PA10_AF1 +#define USART1_RX_PA1_AF4 +#define USART1_RX_PA8_AF14 +#define USART1_RX_PB7_AF0 +#define USART1_TX_PA0_AF4 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART1_TX_PC14_AF0 +#define USART2_RX_PA13_AF4 +#define USART2_RX_PA14_AF9 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 +#define USART2_TX_PA8_AF1 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (2) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PB6_AF9 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PB6_AF8 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PB6_AF10 + +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// TIM +#define TIM14_CH1_PA8_AF13 +#define TIM16_BKIN_PB6_AF14 +#define TIM16_CH1N_PA2_AF2 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA0_AF2 +#define TIM16_CH1_PB7_AF10 +#define TIM17_BKIN_PA10_AF5 +#define TIM17_BKIN_PB6_AF15 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA1_AF2 +#define TIM17_CH1_PC14_AF10 +#define TIM1_BKIN2_PA11_AF5 +#define TIM1_BKIN2_PC14_AF2 +#define TIM1_CH1_PA0_AF5 +#define TIM1_CH1_PA14_AF10 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH2N_PA8_AF9 +#define TIM1_CH2_PA1_AF5 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB6_AF11 +#define TIM1_CH3N_PA8_AF10 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PA2_AF5 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_CH4_PB7_AF1 +#define TIM1_CH4_PF2_AF1 +#define TIM1_ETR_PA12_AF2 +#define TIM1_ETR_PC14_AF1 +#define TIM1_ETR_PC15_AF2 +#define TIM3_CH1_PB6_AF12 +#define TIM3_CH1_PB7_AF11 +#define TIM3_CH2_PB6_AF13 +#define TIM3_CH2_PC14_AF11 +#define TIM3_CH3_PA8_AF11 +#define TIM3_CH3_PB6_AF3 +#define TIM3_CH3_PC15_AF3 +#define TIM3_CH4_PA8_AF12 +#define TIM3_CH4_PB7_AF3 +#define TIM3_ETR_PA13_AF3 +#define TIM3_ETR_PA2_AF3 +#define TIM3_ETR_PA9_AF3 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_3 (2) +#define TIM_MODULE_14 (3) +#define TIM_MODULE_16 (4) +#define TIM_MODULE_17 (5) + +#define TIM_MODULE_COUNT (5) + +#define TIM1_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA2_CN +#define __PA8_CN +#define __PA9_CN +#define __PB6_CN +#define __PB7_CN +#define __PC14_CN +#define __PC15_CN +#define __PF2_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN + +#define PORT_COUNT (4) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32C011J6/SO8N/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32C011J6/SO8N/mcu_definitions.h new file mode 100644 index 000000000..d00e4990b --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32C011J6/SO8N/mcu_definitions.h @@ -0,0 +1,223 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32C011J6_SO8N. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA11_CH11 +#define ADC1_PA12_CH12 +#define ADC1_PA13_CH13 +#define ADC1_PA14_CH14 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA8_CH8 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN + +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (54) +#define DMA_NUM_OF_CHANNELS_FAMILY (54) +#define DMA_NUM_OF_MODULES (1) +#define DMA_NUM_OF_STREAMS (3) +#define DMA_NUM_OF_STREAMS_FAMILY (3) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB7_AF14 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PC14_AF14 + +#define I2C_MODULE_1 (1) + +#define I2C_MODULE_COUNT (1) +// EOF I2C + +// U(S)ART +#define USART1_RX_PA10_AF1 +#define USART1_RX_PA1_AF4 +#define USART1_RX_PA8_AF14 +#define USART1_RX_PB7_AF0 +#define USART1_TX_PA0_AF4 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART1_TX_PC14_AF0 +#define USART2_RX_PA13_AF4 +#define USART2_RX_PA14_AF9 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 +#define USART2_TX_PA8_AF1 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (2) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PB6_AF9 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PB6_AF8 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PB6_AF10 + +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// TIM +#define TIM14_CH1_PA8_AF13 +#define TIM16_BKIN_PB6_AF14 +#define TIM16_CH1N_PA2_AF2 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA0_AF2 +#define TIM16_CH1_PB7_AF10 +#define TIM17_BKIN_PA10_AF5 +#define TIM17_BKIN_PB6_AF15 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA1_AF2 +#define TIM17_CH1_PC14_AF10 +#define TIM1_BKIN2_PA11_AF5 +#define TIM1_BKIN2_PC14_AF2 +#define TIM1_CH1_PA0_AF5 +#define TIM1_CH1_PA14_AF10 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH2N_PA8_AF9 +#define TIM1_CH2_PA1_AF5 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB6_AF11 +#define TIM1_CH3N_PA8_AF10 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PA2_AF5 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_CH4_PB7_AF1 +#define TIM1_CH4_PF2_AF1 +#define TIM1_ETR_PA12_AF2 +#define TIM1_ETR_PC14_AF1 +#define TIM1_ETR_PC15_AF2 +#define TIM3_CH1_PB6_AF12 +#define TIM3_CH1_PB7_AF11 +#define TIM3_CH2_PB6_AF13 +#define TIM3_CH2_PC14_AF11 +#define TIM3_CH3_PA8_AF11 +#define TIM3_CH3_PB6_AF3 +#define TIM3_CH3_PC15_AF3 +#define TIM3_CH4_PA8_AF12 +#define TIM3_CH4_PB7_AF3 +#define TIM3_ETR_PA13_AF3 +#define TIM3_ETR_PA2_AF3 +#define TIM3_ETR_PA9_AF3 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_3 (2) +#define TIM_MODULE_14 (3) +#define TIM_MODULE_16 (4) +#define TIM_MODULE_17 (5) + +#define TIM_MODULE_COUNT (5) + +#define TIM1_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA2_CN +#define __PA8_CN +#define __PA9_CN +#define __PB6_CN +#define __PB7_CN +#define __PC14_CN +#define __PC15_CN +#define __PF2_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN + +#define PORT_COUNT (4) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32C031C4/LQFP48/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32C031C4/LQFP48/mcu_definitions.h new file mode 100644 index 000000000..1cdf8356e --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32C031C4/LQFP48/mcu_definitions.h @@ -0,0 +1,325 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32C031C4_LQFP48. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA11_CH11 +#define ADC1_PA12_CH12 +#define ADC1_PA13_CH13 +#define ADC1_PA14_CH14 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PA8_CH8 +#define ADC1_PB0_CH17 +#define ADC1_PB10_CH20 +#define ADC1_PB11_CH21 +#define ADC1_PB12_CH22 +#define ADC1_PB1_CH18 +#define ADC1_PB2_CH19 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN + +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (54) +#define DMA_NUM_OF_CHANNELS_FAMILY (54) +#define DMA_NUM_OF_MODULES (1) +#define DMA_NUM_OF_STREAMS (3) +#define DMA_NUM_OF_STREAMS_FAMILY (3) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB7_AF14 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PB9_AF6 +#define I2C1_SDA_PC14_AF14 + +#define I2C_MODULE_1 (1) + +#define I2C_MODULE_COUNT (1) +// EOF I2C + +// U(S)ART +#define USART1_RX_PA10_AF1 +#define USART1_RX_PA1_AF4 +#define USART1_RX_PA8_AF14 +#define USART1_RX_PB2_AF0 +#define USART1_RX_PB7_AF0 +#define USART1_TX_PA0_AF4 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART1_TX_PC14_AF0 +#define USART2_RX_PA13_AF4 +#define USART2_RX_PA14_AF9 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_RX_PA5_AF1 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 +#define USART2_TX_PA4_AF1 +#define USART2_TX_PA8_AF1 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (2) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MISO_PB6_AF9 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_MOSI_PB6_AF8 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI1_SCK_PB6_AF10 + +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// TIM +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PA8_AF13 +#define TIM14_CH1_PB1_AF0 +#define TIM14_CH1_PF0_AF2 +#define TIM16_BKIN_PB5_AF2 +#define TIM16_BKIN_PB6_AF14 +#define TIM16_CH1N_PA2_AF2 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA0_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB7_AF10 +#define TIM16_CH1_PB8_AF2 +#define TIM16_CH1_PD0_AF2 +#define TIM17_BKIN_PA10_AF5 +#define TIM17_BKIN_PB4_AF5 +#define TIM17_BKIN_PB6_AF15 +#define TIM17_CH1N_PA4_AF5 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA1_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PB9_AF2 +#define TIM17_CH1_PC14_AF10 +#define TIM17_CH1_PD1_AF2 +#define TIM1_BKIN2_PA11_AF5 +#define TIM1_BKIN2_PB12_AF1 +#define TIM1_BKIN2_PC14_AF2 +#define TIM1_BKIN_PA6_AF2 +#define TIM1_BKIN_PB12_AF2 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_CH1N_PA3_AF2 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1N_PB13_AF2 +#define TIM1_CH1N_PD2_AF2 +#define TIM1_CH1_PA0_AF5 +#define TIM1_CH1_PA14_AF10 +#define TIM1_CH1_PA15_AF2 +#define TIM1_CH1_PA5_AF5 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH2N_PA4_AF2 +#define TIM1_CH2N_PA8_AF9 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2N_PB14_AF2 +#define TIM1_CH2N_PB1_AF5 +#define TIM1_CH2N_PD3_AF2 +#define TIM1_CH2_PA1_AF5 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH2_PB6_AF11 +#define TIM1_CH3N_PA5_AF2 +#define TIM1_CH3N_PA8_AF10 +#define TIM1_CH3N_PB15_AF2 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PA2_AF5 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_CH4_PA3_AF5 +#define TIM1_CH4_PB7_AF1 +#define TIM1_CH4_PF2_AF1 +#define TIM1_ETR_PA12_AF2 +#define TIM1_ETR_PC13_AF1 +#define TIM1_ETR_PC14_AF1 +#define TIM1_ETR_PC15_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH1_PB6_AF12 +#define TIM3_CH1_PB7_AF11 +#define TIM3_CH1_PB8_AF3 +#define TIM3_CH1_PC6_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB3_AF3 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH2_PB6_AF13 +#define TIM3_CH2_PB9_AF3 +#define TIM3_CH2_PC14_AF11 +#define TIM3_CH2_PC7_AF1 +#define TIM3_CH3_PA8_AF11 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH3_PB5_AF3 +#define TIM3_CH3_PB6_AF3 +#define TIM3_CH3_PC15_AF3 +#define TIM3_CH4_PA8_AF12 +#define TIM3_CH4_PB1_AF1 +#define TIM3_CH4_PB7_AF3 +#define TIM3_ETR_PA13_AF3 +#define TIM3_ETR_PA2_AF3 +#define TIM3_ETR_PA9_AF3 +#define TIM3_ETR_PD2_AF1 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_3 (2) +#define TIM_MODULE_14 (3) +#define TIM_MODULE_16 (4) +#define TIM_MODULE_17 (5) + +#define TIM_MODULE_COUNT (5) + +#define TIM1_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC6_CN +#define __PC7_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PF0_CN +#define __PF1_CN +#define __PF2_CN +#define __PF3_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_F_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32C031C4/UFQFPN48/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32C031C4/UFQFPN48/mcu_definitions.h new file mode 100644 index 000000000..cd30e6469 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32C031C4/UFQFPN48/mcu_definitions.h @@ -0,0 +1,325 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32C031C4_UFQFPN48. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA11_CH11 +#define ADC1_PA12_CH12 +#define ADC1_PA13_CH13 +#define ADC1_PA14_CH14 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PA8_CH8 +#define ADC1_PB0_CH17 +#define ADC1_PB10_CH20 +#define ADC1_PB11_CH21 +#define ADC1_PB12_CH22 +#define ADC1_PB1_CH18 +#define ADC1_PB2_CH19 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN + +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (54) +#define DMA_NUM_OF_CHANNELS_FAMILY (54) +#define DMA_NUM_OF_MODULES (1) +#define DMA_NUM_OF_STREAMS (3) +#define DMA_NUM_OF_STREAMS_FAMILY (3) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB7_AF14 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PB9_AF6 +#define I2C1_SDA_PC14_AF14 + +#define I2C_MODULE_1 (1) + +#define I2C_MODULE_COUNT (1) +// EOF I2C + +// U(S)ART +#define USART1_RX_PA10_AF1 +#define USART1_RX_PA1_AF4 +#define USART1_RX_PA8_AF14 +#define USART1_RX_PB2_AF0 +#define USART1_RX_PB7_AF0 +#define USART1_TX_PA0_AF4 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART1_TX_PC14_AF0 +#define USART2_RX_PA13_AF4 +#define USART2_RX_PA14_AF9 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_RX_PA5_AF1 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 +#define USART2_TX_PA4_AF1 +#define USART2_TX_PA8_AF1 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (2) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MISO_PB6_AF9 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_MOSI_PB6_AF8 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI1_SCK_PB6_AF10 + +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// TIM +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PA8_AF13 +#define TIM14_CH1_PB1_AF0 +#define TIM14_CH1_PF0_AF2 +#define TIM16_BKIN_PB5_AF2 +#define TIM16_BKIN_PB6_AF14 +#define TIM16_CH1N_PA2_AF2 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA0_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB7_AF10 +#define TIM16_CH1_PB8_AF2 +#define TIM16_CH1_PD0_AF2 +#define TIM17_BKIN_PA10_AF5 +#define TIM17_BKIN_PB4_AF5 +#define TIM17_BKIN_PB6_AF15 +#define TIM17_CH1N_PA4_AF5 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA1_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PB9_AF2 +#define TIM17_CH1_PC14_AF10 +#define TIM17_CH1_PD1_AF2 +#define TIM1_BKIN2_PA11_AF5 +#define TIM1_BKIN2_PB12_AF1 +#define TIM1_BKIN2_PC14_AF2 +#define TIM1_BKIN_PA6_AF2 +#define TIM1_BKIN_PB12_AF2 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_CH1N_PA3_AF2 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1N_PB13_AF2 +#define TIM1_CH1N_PD2_AF2 +#define TIM1_CH1_PA0_AF5 +#define TIM1_CH1_PA14_AF10 +#define TIM1_CH1_PA15_AF2 +#define TIM1_CH1_PA5_AF5 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH2N_PA4_AF2 +#define TIM1_CH2N_PA8_AF9 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2N_PB14_AF2 +#define TIM1_CH2N_PB1_AF5 +#define TIM1_CH2N_PD3_AF2 +#define TIM1_CH2_PA1_AF5 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH2_PB6_AF11 +#define TIM1_CH3N_PA5_AF2 +#define TIM1_CH3N_PA8_AF10 +#define TIM1_CH3N_PB15_AF2 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PA2_AF5 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_CH4_PA3_AF5 +#define TIM1_CH4_PB7_AF1 +#define TIM1_CH4_PF2_AF1 +#define TIM1_ETR_PA12_AF2 +#define TIM1_ETR_PC13_AF1 +#define TIM1_ETR_PC14_AF1 +#define TIM1_ETR_PC15_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH1_PB6_AF12 +#define TIM3_CH1_PB7_AF11 +#define TIM3_CH1_PB8_AF3 +#define TIM3_CH1_PC6_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB3_AF3 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH2_PB6_AF13 +#define TIM3_CH2_PB9_AF3 +#define TIM3_CH2_PC14_AF11 +#define TIM3_CH2_PC7_AF1 +#define TIM3_CH3_PA8_AF11 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH3_PB5_AF3 +#define TIM3_CH3_PB6_AF3 +#define TIM3_CH3_PC15_AF3 +#define TIM3_CH4_PA8_AF12 +#define TIM3_CH4_PB1_AF1 +#define TIM3_CH4_PB7_AF3 +#define TIM3_ETR_PA13_AF3 +#define TIM3_ETR_PA2_AF3 +#define TIM3_ETR_PA9_AF3 +#define TIM3_ETR_PD2_AF1 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_3 (2) +#define TIM_MODULE_14 (3) +#define TIM_MODULE_16 (4) +#define TIM_MODULE_17 (5) + +#define TIM_MODULE_COUNT (5) + +#define TIM1_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC6_CN +#define __PC7_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PF0_CN +#define __PF1_CN +#define __PF2_CN +#define __PF3_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_F_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32C031C6/LQFP48/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32C031C6/LQFP48/mcu_definitions.h new file mode 100644 index 000000000..74da9ad59 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32C031C6/LQFP48/mcu_definitions.h @@ -0,0 +1,325 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32C031C6_LQFP48. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA11_CH11 +#define ADC1_PA12_CH12 +#define ADC1_PA13_CH13 +#define ADC1_PA14_CH14 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PA8_CH8 +#define ADC1_PB0_CH17 +#define ADC1_PB10_CH20 +#define ADC1_PB11_CH21 +#define ADC1_PB12_CH22 +#define ADC1_PB1_CH18 +#define ADC1_PB2_CH19 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN + +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (54) +#define DMA_NUM_OF_CHANNELS_FAMILY (54) +#define DMA_NUM_OF_MODULES (1) +#define DMA_NUM_OF_STREAMS (3) +#define DMA_NUM_OF_STREAMS_FAMILY (3) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB7_AF14 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PB9_AF6 +#define I2C1_SDA_PC14_AF14 + +#define I2C_MODULE_1 (1) + +#define I2C_MODULE_COUNT (1) +// EOF I2C + +// U(S)ART +#define USART1_RX_PA10_AF1 +#define USART1_RX_PA1_AF4 +#define USART1_RX_PA8_AF14 +#define USART1_RX_PB2_AF0 +#define USART1_RX_PB7_AF0 +#define USART1_TX_PA0_AF4 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART1_TX_PC14_AF0 +#define USART2_RX_PA13_AF4 +#define USART2_RX_PA14_AF9 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_RX_PA5_AF1 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 +#define USART2_TX_PA4_AF1 +#define USART2_TX_PA8_AF1 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (2) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MISO_PB6_AF9 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_MOSI_PB6_AF8 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI1_SCK_PB6_AF10 + +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// TIM +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PA8_AF13 +#define TIM14_CH1_PB1_AF0 +#define TIM14_CH1_PF0_AF2 +#define TIM16_BKIN_PB5_AF2 +#define TIM16_BKIN_PB6_AF14 +#define TIM16_CH1N_PA2_AF2 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA0_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB7_AF10 +#define TIM16_CH1_PB8_AF2 +#define TIM16_CH1_PD0_AF2 +#define TIM17_BKIN_PA10_AF5 +#define TIM17_BKIN_PB4_AF5 +#define TIM17_BKIN_PB6_AF15 +#define TIM17_CH1N_PA4_AF5 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA1_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PB9_AF2 +#define TIM17_CH1_PC14_AF10 +#define TIM17_CH1_PD1_AF2 +#define TIM1_BKIN2_PA11_AF5 +#define TIM1_BKIN2_PB12_AF1 +#define TIM1_BKIN2_PC14_AF2 +#define TIM1_BKIN_PA6_AF2 +#define TIM1_BKIN_PB12_AF2 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_CH1N_PA3_AF2 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1N_PB13_AF2 +#define TIM1_CH1N_PD2_AF2 +#define TIM1_CH1_PA0_AF5 +#define TIM1_CH1_PA14_AF10 +#define TIM1_CH1_PA15_AF2 +#define TIM1_CH1_PA5_AF5 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH2N_PA4_AF2 +#define TIM1_CH2N_PA8_AF9 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2N_PB14_AF2 +#define TIM1_CH2N_PB1_AF5 +#define TIM1_CH2N_PD3_AF2 +#define TIM1_CH2_PA1_AF5 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH2_PB6_AF11 +#define TIM1_CH3N_PA5_AF2 +#define TIM1_CH3N_PA8_AF10 +#define TIM1_CH3N_PB15_AF2 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PA2_AF5 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_CH4_PA3_AF5 +#define TIM1_CH4_PB7_AF1 +#define TIM1_CH4_PF2_AF1 +#define TIM1_ETR_PA12_AF2 +#define TIM1_ETR_PC13_AF1 +#define TIM1_ETR_PC14_AF1 +#define TIM1_ETR_PC15_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH1_PB6_AF12 +#define TIM3_CH1_PB7_AF11 +#define TIM3_CH1_PB8_AF3 +#define TIM3_CH1_PC6_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB3_AF3 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH2_PB6_AF13 +#define TIM3_CH2_PB9_AF3 +#define TIM3_CH2_PC14_AF11 +#define TIM3_CH2_PC7_AF1 +#define TIM3_CH3_PA8_AF11 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH3_PB5_AF3 +#define TIM3_CH3_PB6_AF3 +#define TIM3_CH3_PC15_AF3 +#define TIM3_CH4_PA8_AF12 +#define TIM3_CH4_PB1_AF1 +#define TIM3_CH4_PB7_AF3 +#define TIM3_ETR_PA13_AF3 +#define TIM3_ETR_PA2_AF3 +#define TIM3_ETR_PA9_AF3 +#define TIM3_ETR_PD2_AF1 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_3 (2) +#define TIM_MODULE_14 (3) +#define TIM_MODULE_16 (4) +#define TIM_MODULE_17 (5) + +#define TIM_MODULE_COUNT (5) + +#define TIM1_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC6_CN +#define __PC7_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PF0_CN +#define __PF1_CN +#define __PF2_CN +#define __PF3_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_F_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32C031C6/UFQFPN48/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32C031C6/UFQFPN48/mcu_definitions.h new file mode 100644 index 000000000..eb8f57fb5 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32C031C6/UFQFPN48/mcu_definitions.h @@ -0,0 +1,325 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32C031C6_UFQFPN48. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA11_CH11 +#define ADC1_PA12_CH12 +#define ADC1_PA13_CH13 +#define ADC1_PA14_CH14 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PA8_CH8 +#define ADC1_PB0_CH17 +#define ADC1_PB10_CH20 +#define ADC1_PB11_CH21 +#define ADC1_PB12_CH22 +#define ADC1_PB1_CH18 +#define ADC1_PB2_CH19 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN + +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (54) +#define DMA_NUM_OF_CHANNELS_FAMILY (54) +#define DMA_NUM_OF_MODULES (1) +#define DMA_NUM_OF_STREAMS (3) +#define DMA_NUM_OF_STREAMS_FAMILY (3) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB7_AF14 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PB9_AF6 +#define I2C1_SDA_PC14_AF14 + +#define I2C_MODULE_1 (1) + +#define I2C_MODULE_COUNT (1) +// EOF I2C + +// U(S)ART +#define USART1_RX_PA10_AF1 +#define USART1_RX_PA1_AF4 +#define USART1_RX_PA8_AF14 +#define USART1_RX_PB2_AF0 +#define USART1_RX_PB7_AF0 +#define USART1_TX_PA0_AF4 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART1_TX_PC14_AF0 +#define USART2_RX_PA13_AF4 +#define USART2_RX_PA14_AF9 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_RX_PA5_AF1 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 +#define USART2_TX_PA4_AF1 +#define USART2_TX_PA8_AF1 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (2) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MISO_PB6_AF9 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_MOSI_PB6_AF8 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI1_SCK_PB6_AF10 + +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// TIM +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PA8_AF13 +#define TIM14_CH1_PB1_AF0 +#define TIM14_CH1_PF0_AF2 +#define TIM16_BKIN_PB5_AF2 +#define TIM16_BKIN_PB6_AF14 +#define TIM16_CH1N_PA2_AF2 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA0_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB7_AF10 +#define TIM16_CH1_PB8_AF2 +#define TIM16_CH1_PD0_AF2 +#define TIM17_BKIN_PA10_AF5 +#define TIM17_BKIN_PB4_AF5 +#define TIM17_BKIN_PB6_AF15 +#define TIM17_CH1N_PA4_AF5 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA1_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PB9_AF2 +#define TIM17_CH1_PC14_AF10 +#define TIM17_CH1_PD1_AF2 +#define TIM1_BKIN2_PA11_AF5 +#define TIM1_BKIN2_PB12_AF1 +#define TIM1_BKIN2_PC14_AF2 +#define TIM1_BKIN_PA6_AF2 +#define TIM1_BKIN_PB12_AF2 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_CH1N_PA3_AF2 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1N_PB13_AF2 +#define TIM1_CH1N_PD2_AF2 +#define TIM1_CH1_PA0_AF5 +#define TIM1_CH1_PA14_AF10 +#define TIM1_CH1_PA15_AF2 +#define TIM1_CH1_PA5_AF5 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH2N_PA4_AF2 +#define TIM1_CH2N_PA8_AF9 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2N_PB14_AF2 +#define TIM1_CH2N_PB1_AF5 +#define TIM1_CH2N_PD3_AF2 +#define TIM1_CH2_PA1_AF5 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH2_PB6_AF11 +#define TIM1_CH3N_PA5_AF2 +#define TIM1_CH3N_PA8_AF10 +#define TIM1_CH3N_PB15_AF2 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PA2_AF5 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_CH4_PA3_AF5 +#define TIM1_CH4_PB7_AF1 +#define TIM1_CH4_PF2_AF1 +#define TIM1_ETR_PA12_AF2 +#define TIM1_ETR_PC13_AF1 +#define TIM1_ETR_PC14_AF1 +#define TIM1_ETR_PC15_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH1_PB6_AF12 +#define TIM3_CH1_PB7_AF11 +#define TIM3_CH1_PB8_AF3 +#define TIM3_CH1_PC6_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB3_AF3 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH2_PB6_AF13 +#define TIM3_CH2_PB9_AF3 +#define TIM3_CH2_PC14_AF11 +#define TIM3_CH2_PC7_AF1 +#define TIM3_CH3_PA8_AF11 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH3_PB5_AF3 +#define TIM3_CH3_PB6_AF3 +#define TIM3_CH3_PC15_AF3 +#define TIM3_CH4_PA8_AF12 +#define TIM3_CH4_PB1_AF1 +#define TIM3_CH4_PB7_AF3 +#define TIM3_ETR_PA13_AF3 +#define TIM3_ETR_PA2_AF3 +#define TIM3_ETR_PA9_AF3 +#define TIM3_ETR_PD2_AF1 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_3 (2) +#define TIM_MODULE_14 (3) +#define TIM_MODULE_16 (4) +#define TIM_MODULE_17 (5) + +#define TIM_MODULE_COUNT (5) + +#define TIM1_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC6_CN +#define __PC7_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PF0_CN +#define __PF1_CN +#define __PF2_CN +#define __PF3_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_F_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32C031F4/TSSOP20/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32C031F4/TSSOP20/mcu_definitions.h new file mode 100644 index 000000000..942430c6e --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32C031F4/TSSOP20/mcu_definitions.h @@ -0,0 +1,253 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32C031F4_TSSOP20. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA11_CH11 +#define ADC1_PA12_CH12 +#define ADC1_PA13_CH13 +#define ADC1_PA14_CH14 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PA8_CH8 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN + +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (54) +#define DMA_NUM_OF_CHANNELS_FAMILY (54) +#define DMA_NUM_OF_MODULES (1) +#define DMA_NUM_OF_STREAMS (3) +#define DMA_NUM_OF_STREAMS_FAMILY (3) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB7_AF14 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PC14_AF14 + +#define I2C_MODULE_1 (1) + +#define I2C_MODULE_COUNT (1) +// EOF I2C + +// U(S)ART +#define USART1_RX_PA10_AF1 +#define USART1_RX_PA1_AF4 +#define USART1_RX_PA8_AF14 +#define USART1_RX_PB7_AF0 +#define USART1_TX_PA0_AF4 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART1_TX_PC14_AF0 +#define USART2_RX_PA13_AF4 +#define USART2_RX_PA14_AF9 +#define USART2_RX_PA3_AF1 +#define USART2_RX_PA5_AF1 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 +#define USART2_TX_PA4_AF1 +#define USART2_TX_PA8_AF1 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (2) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB6_AF9 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB6_AF8 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB6_AF10 + +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// TIM +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PA8_AF13 +#define TIM16_BKIN_PB6_AF14 +#define TIM16_CH1N_PA2_AF2 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA0_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB7_AF10 +#define TIM17_BKIN_PA10_AF5 +#define TIM17_BKIN_PB6_AF15 +#define TIM17_CH1N_PA4_AF5 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA1_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PC14_AF10 +#define TIM1_BKIN2_PA11_AF5 +#define TIM1_BKIN2_PC14_AF2 +#define TIM1_BKIN_PA6_AF2 +#define TIM1_CH1N_PA3_AF2 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1_PA0_AF5 +#define TIM1_CH1_PA14_AF10 +#define TIM1_CH1_PA5_AF5 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH2N_PA4_AF2 +#define TIM1_CH2N_PA8_AF9 +#define TIM1_CH2_PA1_AF5 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB6_AF11 +#define TIM1_CH3N_PA5_AF2 +#define TIM1_CH3N_PA8_AF10 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PA2_AF5 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_CH4_PA3_AF5 +#define TIM1_CH4_PB7_AF1 +#define TIM1_CH4_PF2_AF1 +#define TIM1_ETR_PA12_AF2 +#define TIM1_ETR_PC14_AF1 +#define TIM1_ETR_PC15_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB6_AF12 +#define TIM3_CH1_PB7_AF11 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB6_AF13 +#define TIM3_CH2_PC14_AF11 +#define TIM3_CH3_PA8_AF11 +#define TIM3_CH3_PB6_AF3 +#define TIM3_CH3_PC15_AF3 +#define TIM3_CH4_PA8_AF12 +#define TIM3_CH4_PB7_AF3 +#define TIM3_ETR_PA13_AF3 +#define TIM3_ETR_PA2_AF3 +#define TIM3_ETR_PA9_AF3 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_3 (2) +#define TIM_MODULE_14 (3) +#define TIM_MODULE_16 (4) +#define TIM_MODULE_17 (5) + +#define TIM_MODULE_COUNT (5) + +#define TIM1_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB6_CN +#define __PB7_CN +#define __PC14_CN +#define __PC15_CN +#define __PF2_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN + +#define PORT_COUNT (4) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32C031F6/TSSOP20/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32C031F6/TSSOP20/mcu_definitions.h new file mode 100644 index 000000000..bf1ae6464 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32C031F6/TSSOP20/mcu_definitions.h @@ -0,0 +1,253 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32C031F6_TSSOP20. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA11_CH11 +#define ADC1_PA12_CH12 +#define ADC1_PA13_CH13 +#define ADC1_PA14_CH14 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PA8_CH8 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN + +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (54) +#define DMA_NUM_OF_CHANNELS_FAMILY (54) +#define DMA_NUM_OF_MODULES (1) +#define DMA_NUM_OF_STREAMS (3) +#define DMA_NUM_OF_STREAMS_FAMILY (3) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB7_AF14 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PC14_AF14 + +#define I2C_MODULE_1 (1) + +#define I2C_MODULE_COUNT (1) +// EOF I2C + +// U(S)ART +#define USART1_RX_PA10_AF1 +#define USART1_RX_PA1_AF4 +#define USART1_RX_PA8_AF14 +#define USART1_RX_PB7_AF0 +#define USART1_TX_PA0_AF4 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART1_TX_PC14_AF0 +#define USART2_RX_PA13_AF4 +#define USART2_RX_PA14_AF9 +#define USART2_RX_PA3_AF1 +#define USART2_RX_PA5_AF1 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 +#define USART2_TX_PA4_AF1 +#define USART2_TX_PA8_AF1 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (2) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB6_AF9 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB6_AF8 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB6_AF10 + +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// TIM +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PA8_AF13 +#define TIM16_BKIN_PB6_AF14 +#define TIM16_CH1N_PA2_AF2 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA0_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB7_AF10 +#define TIM17_BKIN_PA10_AF5 +#define TIM17_BKIN_PB6_AF15 +#define TIM17_CH1N_PA4_AF5 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA1_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PC14_AF10 +#define TIM1_BKIN2_PA11_AF5 +#define TIM1_BKIN2_PC14_AF2 +#define TIM1_BKIN_PA6_AF2 +#define TIM1_CH1N_PA3_AF2 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1_PA0_AF5 +#define TIM1_CH1_PA14_AF10 +#define TIM1_CH1_PA5_AF5 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH2N_PA4_AF2 +#define TIM1_CH2N_PA8_AF9 +#define TIM1_CH2_PA1_AF5 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB6_AF11 +#define TIM1_CH3N_PA5_AF2 +#define TIM1_CH3N_PA8_AF10 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PA2_AF5 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_CH4_PA3_AF5 +#define TIM1_CH4_PB7_AF1 +#define TIM1_CH4_PF2_AF1 +#define TIM1_ETR_PA12_AF2 +#define TIM1_ETR_PC14_AF1 +#define TIM1_ETR_PC15_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB6_AF12 +#define TIM3_CH1_PB7_AF11 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB6_AF13 +#define TIM3_CH2_PC14_AF11 +#define TIM3_CH3_PA8_AF11 +#define TIM3_CH3_PB6_AF3 +#define TIM3_CH3_PC15_AF3 +#define TIM3_CH4_PA8_AF12 +#define TIM3_CH4_PB7_AF3 +#define TIM3_ETR_PA13_AF3 +#define TIM3_ETR_PA2_AF3 +#define TIM3_ETR_PA9_AF3 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_3 (2) +#define TIM_MODULE_14 (3) +#define TIM_MODULE_16 (4) +#define TIM_MODULE_17 (5) + +#define TIM_MODULE_COUNT (5) + +#define TIM1_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB6_CN +#define __PB7_CN +#define __PC14_CN +#define __PC15_CN +#define __PF2_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN + +#define PORT_COUNT (4) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32C031G4/UFQFPN28/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32C031G4/UFQFPN28/mcu_definitions.h new file mode 100644 index 000000000..1e2b1d5cb --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32C031G4/UFQFPN28/mcu_definitions.h @@ -0,0 +1,275 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32C031G4_UFQFPN28. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA11_CH11 +#define ADC1_PA12_CH12 +#define ADC1_PA13_CH13 +#define ADC1_PA14_CH14 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PA8_CH8 +#define ADC1_PB0_CH17 +#define ADC1_PB1_CH18 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN + +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (54) +#define DMA_NUM_OF_CHANNELS_FAMILY (54) +#define DMA_NUM_OF_MODULES (1) +#define DMA_NUM_OF_STREAMS (3) +#define DMA_NUM_OF_STREAMS_FAMILY (3) +// EOF DMA + +// I2C +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB7_AF14 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PC14_AF14 + +#define I2C_MODULE_1 (1) + +#define I2C_MODULE_COUNT (1) +// EOF I2C + +// U(S)ART +#define USART1_RX_PA1_AF4 +#define USART1_RX_PA8_AF14 +#define USART1_RX_PB7_AF0 +#define USART1_TX_PA0_AF4 +#define USART1_TX_PB6_AF0 +#define USART1_TX_PC14_AF0 +#define USART2_RX_PA13_AF4 +#define USART2_RX_PA14_AF9 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_RX_PA5_AF1 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 +#define USART2_TX_PA4_AF1 +#define USART2_TX_PA8_AF1 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (2) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MISO_PB6_AF9 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_MOSI_PB6_AF8 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI1_SCK_PB6_AF10 + +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// TIM +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PA8_AF13 +#define TIM14_CH1_PB1_AF0 +#define TIM16_BKIN_PB5_AF2 +#define TIM16_BKIN_PB6_AF14 +#define TIM16_CH1N_PA2_AF2 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA0_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB7_AF10 +#define TIM16_CH1_PB8_AF2 +#define TIM17_BKIN_PB4_AF5 +#define TIM17_BKIN_PB6_AF15 +#define TIM17_CH1N_PA4_AF5 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA1_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PC14_AF10 +#define TIM1_BKIN2_PA11_AF5 +#define TIM1_BKIN2_PC14_AF2 +#define TIM1_BKIN_PA6_AF2 +#define TIM1_CH1N_PA3_AF2 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1_PA0_AF5 +#define TIM1_CH1_PA14_AF10 +#define TIM1_CH1_PA15_AF2 +#define TIM1_CH1_PA5_AF5 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH2N_PA4_AF2 +#define TIM1_CH2N_PA8_AF9 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2N_PB1_AF5 +#define TIM1_CH2_PA1_AF5 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH2_PB6_AF11 +#define TIM1_CH3N_PA5_AF2 +#define TIM1_CH3N_PA8_AF10 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3_PA2_AF5 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_CH4_PA3_AF5 +#define TIM1_CH4_PB7_AF1 +#define TIM1_CH4_PF2_AF1 +#define TIM1_ETR_PA12_AF2 +#define TIM1_ETR_PC14_AF1 +#define TIM1_ETR_PC15_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH1_PB6_AF12 +#define TIM3_CH1_PB7_AF11 +#define TIM3_CH1_PB8_AF3 +#define TIM3_CH1_PC6_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB3_AF3 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH2_PB6_AF13 +#define TIM3_CH2_PC14_AF11 +#define TIM3_CH3_PA8_AF11 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH3_PB5_AF3 +#define TIM3_CH3_PB6_AF3 +#define TIM3_CH3_PC15_AF3 +#define TIM3_CH4_PA8_AF12 +#define TIM3_CH4_PB1_AF1 +#define TIM3_CH4_PB7_AF3 +#define TIM3_ETR_PA13_AF3 +#define TIM3_ETR_PA2_AF3 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_3 (2) +#define TIM_MODULE_14 (3) +#define TIM_MODULE_16 (4) +#define TIM_MODULE_17 (5) + +#define TIM_MODULE_COUNT (5) + +#define TIM1_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PB0_CN +#define __PB1_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PC14_CN +#define __PC15_CN +#define __PC6_CN +#define __PF2_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN + +#define PORT_COUNT (4) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32C031G6/UFQFPN28/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32C031G6/UFQFPN28/mcu_definitions.h new file mode 100644 index 000000000..c55c8d34d --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32C031G6/UFQFPN28/mcu_definitions.h @@ -0,0 +1,275 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32C031G6_UFQFPN28. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA11_CH11 +#define ADC1_PA12_CH12 +#define ADC1_PA13_CH13 +#define ADC1_PA14_CH14 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PA8_CH8 +#define ADC1_PB0_CH17 +#define ADC1_PB1_CH18 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN + +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (54) +#define DMA_NUM_OF_CHANNELS_FAMILY (54) +#define DMA_NUM_OF_MODULES (1) +#define DMA_NUM_OF_STREAMS (3) +#define DMA_NUM_OF_STREAMS_FAMILY (3) +// EOF DMA + +// I2C +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB7_AF14 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PC14_AF14 + +#define I2C_MODULE_1 (1) + +#define I2C_MODULE_COUNT (1) +// EOF I2C + +// U(S)ART +#define USART1_RX_PA1_AF4 +#define USART1_RX_PA8_AF14 +#define USART1_RX_PB7_AF0 +#define USART1_TX_PA0_AF4 +#define USART1_TX_PB6_AF0 +#define USART1_TX_PC14_AF0 +#define USART2_RX_PA13_AF4 +#define USART2_RX_PA14_AF9 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_RX_PA5_AF1 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 +#define USART2_TX_PA4_AF1 +#define USART2_TX_PA8_AF1 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (2) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MISO_PB6_AF9 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_MOSI_PB6_AF8 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI1_SCK_PB6_AF10 + +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// TIM +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PA8_AF13 +#define TIM14_CH1_PB1_AF0 +#define TIM16_BKIN_PB5_AF2 +#define TIM16_BKIN_PB6_AF14 +#define TIM16_CH1N_PA2_AF2 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA0_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB7_AF10 +#define TIM16_CH1_PB8_AF2 +#define TIM17_BKIN_PB4_AF5 +#define TIM17_BKIN_PB6_AF15 +#define TIM17_CH1N_PA4_AF5 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA1_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PC14_AF10 +#define TIM1_BKIN2_PA11_AF5 +#define TIM1_BKIN2_PC14_AF2 +#define TIM1_BKIN_PA6_AF2 +#define TIM1_CH1N_PA3_AF2 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1_PA0_AF5 +#define TIM1_CH1_PA14_AF10 +#define TIM1_CH1_PA15_AF2 +#define TIM1_CH1_PA5_AF5 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH2N_PA4_AF2 +#define TIM1_CH2N_PA8_AF9 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2N_PB1_AF5 +#define TIM1_CH2_PA1_AF5 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH2_PB6_AF11 +#define TIM1_CH3N_PA5_AF2 +#define TIM1_CH3N_PA8_AF10 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3_PA2_AF5 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_CH4_PA3_AF5 +#define TIM1_CH4_PB7_AF1 +#define TIM1_CH4_PF2_AF1 +#define TIM1_ETR_PA12_AF2 +#define TIM1_ETR_PC14_AF1 +#define TIM1_ETR_PC15_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH1_PB6_AF12 +#define TIM3_CH1_PB7_AF11 +#define TIM3_CH1_PB8_AF3 +#define TIM3_CH1_PC6_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB3_AF3 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH2_PB6_AF13 +#define TIM3_CH2_PC14_AF11 +#define TIM3_CH3_PA8_AF11 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH3_PB5_AF3 +#define TIM3_CH3_PB6_AF3 +#define TIM3_CH3_PC15_AF3 +#define TIM3_CH4_PA8_AF12 +#define TIM3_CH4_PB1_AF1 +#define TIM3_CH4_PB7_AF3 +#define TIM3_ETR_PA13_AF3 +#define TIM3_ETR_PA2_AF3 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_3 (2) +#define TIM_MODULE_14 (3) +#define TIM_MODULE_16 (4) +#define TIM_MODULE_17 (5) + +#define TIM_MODULE_COUNT (5) + +#define TIM1_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PB0_CN +#define __PB1_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PC14_CN +#define __PC15_CN +#define __PC6_CN +#define __PF2_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN + +#define PORT_COUNT (4) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32C031K4/LQFP32/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32C031K4/LQFP32/mcu_definitions.h new file mode 100644 index 000000000..b3d1fc3de --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32C031K4/LQFP32/mcu_definitions.h @@ -0,0 +1,292 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32C031K4_LQFP32. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA11_CH11 +#define ADC1_PA12_CH12 +#define ADC1_PA13_CH13 +#define ADC1_PA14_CH14 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PA8_CH8 +#define ADC1_PB0_CH17 +#define ADC1_PB1_CH18 +#define ADC1_PB2_CH19 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN + +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (54) +#define DMA_NUM_OF_CHANNELS_FAMILY (54) +#define DMA_NUM_OF_MODULES (1) +#define DMA_NUM_OF_STREAMS (3) +#define DMA_NUM_OF_STREAMS_FAMILY (3) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB7_AF14 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PB9_AF6 +#define I2C1_SDA_PC14_AF14 + +#define I2C_MODULE_1 (1) + +#define I2C_MODULE_COUNT (1) +// EOF I2C + +// U(S)ART +#define USART1_RX_PA10_AF1 +#define USART1_RX_PA1_AF4 +#define USART1_RX_PA8_AF14 +#define USART1_RX_PB2_AF0 +#define USART1_RX_PB7_AF0 +#define USART1_TX_PA0_AF4 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART1_TX_PC14_AF0 +#define USART2_RX_PA13_AF4 +#define USART2_RX_PA14_AF9 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_RX_PA5_AF1 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 +#define USART2_TX_PA4_AF1 +#define USART2_TX_PA8_AF1 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (2) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MISO_PB6_AF9 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_MOSI_PB6_AF8 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI1_SCK_PB6_AF10 + +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// TIM +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PA8_AF13 +#define TIM14_CH1_PB1_AF0 +#define TIM16_BKIN_PB5_AF2 +#define TIM16_BKIN_PB6_AF14 +#define TIM16_CH1N_PA2_AF2 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA0_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB7_AF10 +#define TIM16_CH1_PB8_AF2 +#define TIM17_BKIN_PA10_AF5 +#define TIM17_BKIN_PB4_AF5 +#define TIM17_BKIN_PB6_AF15 +#define TIM17_CH1N_PA4_AF5 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA1_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PB9_AF2 +#define TIM17_CH1_PC14_AF10 +#define TIM1_BKIN2_PA11_AF5 +#define TIM1_BKIN2_PC14_AF2 +#define TIM1_BKIN_PA6_AF2 +#define TIM1_CH1N_PA3_AF2 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1_PA0_AF5 +#define TIM1_CH1_PA14_AF10 +#define TIM1_CH1_PA15_AF2 +#define TIM1_CH1_PA5_AF5 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH2N_PA4_AF2 +#define TIM1_CH2N_PA8_AF9 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2N_PB1_AF5 +#define TIM1_CH2_PA1_AF5 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH2_PB6_AF11 +#define TIM1_CH3N_PA5_AF2 +#define TIM1_CH3N_PA8_AF10 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PA2_AF5 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_CH4_PA3_AF5 +#define TIM1_CH4_PB7_AF1 +#define TIM1_CH4_PF2_AF1 +#define TIM1_ETR_PA12_AF2 +#define TIM1_ETR_PC14_AF1 +#define TIM1_ETR_PC15_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH1_PB6_AF12 +#define TIM3_CH1_PB7_AF11 +#define TIM3_CH1_PB8_AF3 +#define TIM3_CH1_PC6_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB3_AF3 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH2_PB6_AF13 +#define TIM3_CH2_PB9_AF3 +#define TIM3_CH2_PC14_AF11 +#define TIM3_CH3_PA8_AF11 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH3_PB5_AF3 +#define TIM3_CH3_PB6_AF3 +#define TIM3_CH3_PC15_AF3 +#define TIM3_CH4_PA8_AF12 +#define TIM3_CH4_PB1_AF1 +#define TIM3_CH4_PB7_AF3 +#define TIM3_ETR_PA13_AF3 +#define TIM3_ETR_PA2_AF3 +#define TIM3_ETR_PA9_AF3 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_3 (2) +#define TIM_MODULE_14 (3) +#define TIM_MODULE_16 (4) +#define TIM_MODULE_17 (5) + +#define TIM_MODULE_COUNT (5) + +#define TIM1_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC14_CN +#define __PC15_CN +#define __PC6_CN +#define __PF2_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN + +#define PORT_COUNT (4) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32C031K4/UFQFPN32/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32C031K4/UFQFPN32/mcu_definitions.h new file mode 100644 index 000000000..df0a510bc --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32C031K4/UFQFPN32/mcu_definitions.h @@ -0,0 +1,292 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32C031K4_UFQFPN32. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA11_CH11 +#define ADC1_PA12_CH12 +#define ADC1_PA13_CH13 +#define ADC1_PA14_CH14 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PA8_CH8 +#define ADC1_PB0_CH17 +#define ADC1_PB1_CH18 +#define ADC1_PB2_CH19 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN + +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (54) +#define DMA_NUM_OF_CHANNELS_FAMILY (54) +#define DMA_NUM_OF_MODULES (1) +#define DMA_NUM_OF_STREAMS (3) +#define DMA_NUM_OF_STREAMS_FAMILY (3) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB7_AF14 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PB9_AF6 +#define I2C1_SDA_PC14_AF14 + +#define I2C_MODULE_1 (1) + +#define I2C_MODULE_COUNT (1) +// EOF I2C + +// U(S)ART +#define USART1_RX_PA10_AF1 +#define USART1_RX_PA1_AF4 +#define USART1_RX_PA8_AF14 +#define USART1_RX_PB2_AF0 +#define USART1_RX_PB7_AF0 +#define USART1_TX_PA0_AF4 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART1_TX_PC14_AF0 +#define USART2_RX_PA13_AF4 +#define USART2_RX_PA14_AF9 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_RX_PA5_AF1 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 +#define USART2_TX_PA4_AF1 +#define USART2_TX_PA8_AF1 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (2) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MISO_PB6_AF9 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_MOSI_PB6_AF8 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI1_SCK_PB6_AF10 + +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// TIM +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PA8_AF13 +#define TIM14_CH1_PB1_AF0 +#define TIM16_BKIN_PB5_AF2 +#define TIM16_BKIN_PB6_AF14 +#define TIM16_CH1N_PA2_AF2 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA0_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB7_AF10 +#define TIM16_CH1_PB8_AF2 +#define TIM17_BKIN_PA10_AF5 +#define TIM17_BKIN_PB4_AF5 +#define TIM17_BKIN_PB6_AF15 +#define TIM17_CH1N_PA4_AF5 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA1_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PB9_AF2 +#define TIM17_CH1_PC14_AF10 +#define TIM1_BKIN2_PA11_AF5 +#define TIM1_BKIN2_PC14_AF2 +#define TIM1_BKIN_PA6_AF2 +#define TIM1_CH1N_PA3_AF2 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1_PA0_AF5 +#define TIM1_CH1_PA14_AF10 +#define TIM1_CH1_PA15_AF2 +#define TIM1_CH1_PA5_AF5 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH2N_PA4_AF2 +#define TIM1_CH2N_PA8_AF9 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2N_PB1_AF5 +#define TIM1_CH2_PA1_AF5 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH2_PB6_AF11 +#define TIM1_CH3N_PA5_AF2 +#define TIM1_CH3N_PA8_AF10 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PA2_AF5 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_CH4_PA3_AF5 +#define TIM1_CH4_PB7_AF1 +#define TIM1_CH4_PF2_AF1 +#define TIM1_ETR_PA12_AF2 +#define TIM1_ETR_PC14_AF1 +#define TIM1_ETR_PC15_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH1_PB6_AF12 +#define TIM3_CH1_PB7_AF11 +#define TIM3_CH1_PB8_AF3 +#define TIM3_CH1_PC6_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB3_AF3 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH2_PB6_AF13 +#define TIM3_CH2_PB9_AF3 +#define TIM3_CH2_PC14_AF11 +#define TIM3_CH3_PA8_AF11 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH3_PB5_AF3 +#define TIM3_CH3_PB6_AF3 +#define TIM3_CH3_PC15_AF3 +#define TIM3_CH4_PA8_AF12 +#define TIM3_CH4_PB1_AF1 +#define TIM3_CH4_PB7_AF3 +#define TIM3_ETR_PA13_AF3 +#define TIM3_ETR_PA2_AF3 +#define TIM3_ETR_PA9_AF3 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_3 (2) +#define TIM_MODULE_14 (3) +#define TIM_MODULE_16 (4) +#define TIM_MODULE_17 (5) + +#define TIM_MODULE_COUNT (5) + +#define TIM1_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC14_CN +#define __PC15_CN +#define __PC6_CN +#define __PF2_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN + +#define PORT_COUNT (4) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32C031K6/LQFP32/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32C031K6/LQFP32/mcu_definitions.h new file mode 100644 index 000000000..bb55217bd --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32C031K6/LQFP32/mcu_definitions.h @@ -0,0 +1,292 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32C031K6_LQFP32. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA11_CH11 +#define ADC1_PA12_CH12 +#define ADC1_PA13_CH13 +#define ADC1_PA14_CH14 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PA8_CH8 +#define ADC1_PB0_CH17 +#define ADC1_PB1_CH18 +#define ADC1_PB2_CH19 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN + +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (54) +#define DMA_NUM_OF_CHANNELS_FAMILY (54) +#define DMA_NUM_OF_MODULES (1) +#define DMA_NUM_OF_STREAMS (3) +#define DMA_NUM_OF_STREAMS_FAMILY (3) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB7_AF14 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PB9_AF6 +#define I2C1_SDA_PC14_AF14 + +#define I2C_MODULE_1 (1) + +#define I2C_MODULE_COUNT (1) +// EOF I2C + +// U(S)ART +#define USART1_RX_PA10_AF1 +#define USART1_RX_PA1_AF4 +#define USART1_RX_PA8_AF14 +#define USART1_RX_PB2_AF0 +#define USART1_RX_PB7_AF0 +#define USART1_TX_PA0_AF4 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART1_TX_PC14_AF0 +#define USART2_RX_PA13_AF4 +#define USART2_RX_PA14_AF9 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_RX_PA5_AF1 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 +#define USART2_TX_PA4_AF1 +#define USART2_TX_PA8_AF1 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (2) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MISO_PB6_AF9 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_MOSI_PB6_AF8 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI1_SCK_PB6_AF10 + +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// TIM +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PA8_AF13 +#define TIM14_CH1_PB1_AF0 +#define TIM16_BKIN_PB5_AF2 +#define TIM16_BKIN_PB6_AF14 +#define TIM16_CH1N_PA2_AF2 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA0_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB7_AF10 +#define TIM16_CH1_PB8_AF2 +#define TIM17_BKIN_PA10_AF5 +#define TIM17_BKIN_PB4_AF5 +#define TIM17_BKIN_PB6_AF15 +#define TIM17_CH1N_PA4_AF5 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA1_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PB9_AF2 +#define TIM17_CH1_PC14_AF10 +#define TIM1_BKIN2_PA11_AF5 +#define TIM1_BKIN2_PC14_AF2 +#define TIM1_BKIN_PA6_AF2 +#define TIM1_CH1N_PA3_AF2 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1_PA0_AF5 +#define TIM1_CH1_PA14_AF10 +#define TIM1_CH1_PA15_AF2 +#define TIM1_CH1_PA5_AF5 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH2N_PA4_AF2 +#define TIM1_CH2N_PA8_AF9 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2N_PB1_AF5 +#define TIM1_CH2_PA1_AF5 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH2_PB6_AF11 +#define TIM1_CH3N_PA5_AF2 +#define TIM1_CH3N_PA8_AF10 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PA2_AF5 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_CH4_PA3_AF5 +#define TIM1_CH4_PB7_AF1 +#define TIM1_CH4_PF2_AF1 +#define TIM1_ETR_PA12_AF2 +#define TIM1_ETR_PC14_AF1 +#define TIM1_ETR_PC15_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH1_PB6_AF12 +#define TIM3_CH1_PB7_AF11 +#define TIM3_CH1_PB8_AF3 +#define TIM3_CH1_PC6_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB3_AF3 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH2_PB6_AF13 +#define TIM3_CH2_PB9_AF3 +#define TIM3_CH2_PC14_AF11 +#define TIM3_CH3_PA8_AF11 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH3_PB5_AF3 +#define TIM3_CH3_PB6_AF3 +#define TIM3_CH3_PC15_AF3 +#define TIM3_CH4_PA8_AF12 +#define TIM3_CH4_PB1_AF1 +#define TIM3_CH4_PB7_AF3 +#define TIM3_ETR_PA13_AF3 +#define TIM3_ETR_PA2_AF3 +#define TIM3_ETR_PA9_AF3 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_3 (2) +#define TIM_MODULE_14 (3) +#define TIM_MODULE_16 (4) +#define TIM_MODULE_17 (5) + +#define TIM_MODULE_COUNT (5) + +#define TIM1_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC14_CN +#define __PC15_CN +#define __PC6_CN +#define __PF2_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN + +#define PORT_COUNT (4) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32C031K6/UFQFPN32/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32C031K6/UFQFPN32/mcu_definitions.h new file mode 100644 index 000000000..c6caae8ad --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32C031K6/UFQFPN32/mcu_definitions.h @@ -0,0 +1,292 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32C031K6_UFQFPN32. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA11_CH11 +#define ADC1_PA12_CH12 +#define ADC1_PA13_CH13 +#define ADC1_PA14_CH14 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PA8_CH8 +#define ADC1_PB0_CH17 +#define ADC1_PB1_CH18 +#define ADC1_PB2_CH19 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN + +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (54) +#define DMA_NUM_OF_CHANNELS_FAMILY (54) +#define DMA_NUM_OF_MODULES (1) +#define DMA_NUM_OF_STREAMS (3) +#define DMA_NUM_OF_STREAMS_FAMILY (3) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB7_AF14 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PB9_AF6 +#define I2C1_SDA_PC14_AF14 + +#define I2C_MODULE_1 (1) + +#define I2C_MODULE_COUNT (1) +// EOF I2C + +// U(S)ART +#define USART1_RX_PA10_AF1 +#define USART1_RX_PA1_AF4 +#define USART1_RX_PA8_AF14 +#define USART1_RX_PB2_AF0 +#define USART1_RX_PB7_AF0 +#define USART1_TX_PA0_AF4 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART1_TX_PC14_AF0 +#define USART2_RX_PA13_AF4 +#define USART2_RX_PA14_AF9 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_RX_PA5_AF1 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 +#define USART2_TX_PA4_AF1 +#define USART2_TX_PA8_AF1 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (2) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MISO_PB6_AF9 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_MOSI_PB6_AF8 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI1_SCK_PB6_AF10 + +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// TIM +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PA8_AF13 +#define TIM14_CH1_PB1_AF0 +#define TIM16_BKIN_PB5_AF2 +#define TIM16_BKIN_PB6_AF14 +#define TIM16_CH1N_PA2_AF2 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA0_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB7_AF10 +#define TIM16_CH1_PB8_AF2 +#define TIM17_BKIN_PA10_AF5 +#define TIM17_BKIN_PB4_AF5 +#define TIM17_BKIN_PB6_AF15 +#define TIM17_CH1N_PA4_AF5 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA1_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PB9_AF2 +#define TIM17_CH1_PC14_AF10 +#define TIM1_BKIN2_PA11_AF5 +#define TIM1_BKIN2_PC14_AF2 +#define TIM1_BKIN_PA6_AF2 +#define TIM1_CH1N_PA3_AF2 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1_PA0_AF5 +#define TIM1_CH1_PA14_AF10 +#define TIM1_CH1_PA15_AF2 +#define TIM1_CH1_PA5_AF5 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH2N_PA4_AF2 +#define TIM1_CH2N_PA8_AF9 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2N_PB1_AF5 +#define TIM1_CH2_PA1_AF5 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH2_PB6_AF11 +#define TIM1_CH3N_PA5_AF2 +#define TIM1_CH3N_PA8_AF10 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PA2_AF5 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_CH4_PA3_AF5 +#define TIM1_CH4_PB7_AF1 +#define TIM1_CH4_PF2_AF1 +#define TIM1_ETR_PA12_AF2 +#define TIM1_ETR_PC14_AF1 +#define TIM1_ETR_PC15_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH1_PB6_AF12 +#define TIM3_CH1_PB7_AF11 +#define TIM3_CH1_PB8_AF3 +#define TIM3_CH1_PC6_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB3_AF3 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH2_PB6_AF13 +#define TIM3_CH2_PB9_AF3 +#define TIM3_CH2_PC14_AF11 +#define TIM3_CH3_PA8_AF11 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH3_PB5_AF3 +#define TIM3_CH3_PB6_AF3 +#define TIM3_CH3_PC15_AF3 +#define TIM3_CH4_PA8_AF12 +#define TIM3_CH4_PB1_AF1 +#define TIM3_CH4_PB7_AF3 +#define TIM3_ETR_PA13_AF3 +#define TIM3_ETR_PA2_AF3 +#define TIM3_ETR_PA9_AF3 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_3 (2) +#define TIM_MODULE_14 (3) +#define TIM_MODULE_16 (4) +#define TIM_MODULE_17 (5) + +#define TIM_MODULE_COUNT (5) + +#define TIM1_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC14_CN +#define __PC15_CN +#define __PC6_CN +#define __PF2_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN + +#define PORT_COUNT (4) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G051C6/LQFP48/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G051C6/LQFP48/mcu_definitions.h new file mode 100644 index 000000000..f86d4ee96 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G051C6/LQFP48/mcu_definitions.h @@ -0,0 +1,309 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G051C6_LQFP48. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA13_CH17 +#define ADC1_PA14_CH18 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PB0_CH8 +#define ADC1_PB10_CH11 +#define ADC1_PB11_CH15 +#define ADC1_PB12_CH16 +#define ADC1_PB1_CH9 +#define ADC1_PB2_CH10 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN + +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (62) +#define DMA_NUM_OF_CHANNELS_FAMILY (62) +#define DMA_NUM_OF_MODULES (1) +#define DMA_NUM_OF_STREAMS (7) +#define DMA_NUM_OF_STREAMS_FAMILY (7) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PB9_AF6 +#define I2C2_SCL_PA11_AF6 +#define I2C2_SCL_PB10_AF6 +#define I2C2_SCL_PB13_AF6 +#define I2C2_SDA_PA12_AF6 +#define I2C2_SDA_PB11_AF6 +#define I2C2_SDA_PB14_AF6 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (2) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF6 +#define LPUART1_RX_PB10_AF1 +#define LPUART1_TX_PA2_AF6 +#define LPUART1_TX_PB11_AF1 +#define USART1_RX_PA10_AF1 +#define USART1_RX_PB7_AF0 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (2) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI2_MISO_PA3_AF0 +#define SPI2_MISO_PA9_AF4 +#define SPI2_MISO_PB14_AF0 +#define SPI2_MISO_PB2_AF1 +#define SPI2_MISO_PB6_AF4 +#define SPI2_MISO_PD3_AF1 +#define SPI2_MOSI_PA10_AF0 +#define SPI2_MOSI_PA4_AF1 +#define SPI2_MOSI_PB11_AF0 +#define SPI2_MOSI_PB15_AF0 +#define SPI2_MOSI_PB7_AF1 +#define SPI2_SCK_PA0_AF0 +#define SPI2_SCK_PB10_AF5 +#define SPI2_SCK_PB13_AF0 +#define SPI2_SCK_PB8_AF1 +#define SPI2_SCK_PD1_AF1 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF5 +#define LPTIM2_ETR_PA5_AF5 +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PB1_AF0 +#define TIM14_CH1_PF0_AF2 +#define TIM15_CH1N_PA1_AF5 +#define TIM15_CH1N_PB13_AF5 +#define TIM15_CH1N_PB15_AF4 +#define TIM15_CH1N_PF1_AF2 +#define TIM15_CH1_PA2_AF5 +#define TIM15_CH1_PB14_AF5 +#define TIM15_CH2_PA3_AF5 +#define TIM15_CH2_PB15_AF5 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB8_AF2 +#define TIM16_CH1_PD0_AF2 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PB9_AF2 +#define TIM17_CH1_PD1_AF2 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1N_PB13_AF2 +#define TIM1_CH1N_PD2_AF2 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2N_PB14_AF2 +#define TIM1_CH2N_PD3_AF2 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH3N_PB15_AF2 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_ETR_PA12_AF2 +#define TIM2_CH1_PA0_AF2 +#define TIM2_CH1_PA15_AF2 +#define TIM2_CH1_PA5_AF2 +#define TIM2_CH2_PA1_AF2 +#define TIM2_CH2_PB3_AF2 +#define TIM2_CH3_PA2_AF2 +#define TIM2_CH3_PB10_AF2 +#define TIM2_CH3_PC6_AF2 +#define TIM2_CH4_PA3_AF2 +#define TIM2_CH4_PB11_AF2 +#define TIM2_CH4_PC7_AF2 +#define TIM2_ETR_PA0_AF2 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH1_PC6_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH2_PC7_AF1 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH4_PB1_AF1 +#define TIM3_ETR_PD2_AF1 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_14 (4) +#define TIM_MODULE_15 (5) +#define TIM_MODULE_16 (6) +#define TIM_MODULE_17 (7) + +#define TIM_MODULE_COUNT (7) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +#define TIM1_BUS (1) +#define TIM15_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC6_CN +#define __PC7_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PF0_CN +#define __PF1_CN +#define __PF2_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_F_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G051C6/UFQFPN48/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G051C6/UFQFPN48/mcu_definitions.h new file mode 100644 index 000000000..b43a5b7ba --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G051C6/UFQFPN48/mcu_definitions.h @@ -0,0 +1,309 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G051C6_UFQFPN48. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA13_CH17 +#define ADC1_PA14_CH18 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PB0_CH8 +#define ADC1_PB10_CH11 +#define ADC1_PB11_CH15 +#define ADC1_PB12_CH16 +#define ADC1_PB1_CH9 +#define ADC1_PB2_CH10 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN + +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (62) +#define DMA_NUM_OF_CHANNELS_FAMILY (62) +#define DMA_NUM_OF_MODULES (1) +#define DMA_NUM_OF_STREAMS (7) +#define DMA_NUM_OF_STREAMS_FAMILY (7) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PB9_AF6 +#define I2C2_SCL_PA11_AF6 +#define I2C2_SCL_PB10_AF6 +#define I2C2_SCL_PB13_AF6 +#define I2C2_SDA_PA12_AF6 +#define I2C2_SDA_PB11_AF6 +#define I2C2_SDA_PB14_AF6 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (2) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF6 +#define LPUART1_RX_PB10_AF1 +#define LPUART1_TX_PA2_AF6 +#define LPUART1_TX_PB11_AF1 +#define USART1_RX_PA10_AF1 +#define USART1_RX_PB7_AF0 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (2) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI2_MISO_PA3_AF0 +#define SPI2_MISO_PA9_AF4 +#define SPI2_MISO_PB14_AF0 +#define SPI2_MISO_PB2_AF1 +#define SPI2_MISO_PB6_AF4 +#define SPI2_MISO_PD3_AF1 +#define SPI2_MOSI_PA10_AF0 +#define SPI2_MOSI_PA4_AF1 +#define SPI2_MOSI_PB11_AF0 +#define SPI2_MOSI_PB15_AF0 +#define SPI2_MOSI_PB7_AF1 +#define SPI2_SCK_PA0_AF0 +#define SPI2_SCK_PB10_AF5 +#define SPI2_SCK_PB13_AF0 +#define SPI2_SCK_PB8_AF1 +#define SPI2_SCK_PD1_AF1 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF5 +#define LPTIM2_ETR_PA5_AF5 +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PB1_AF0 +#define TIM14_CH1_PF0_AF2 +#define TIM15_CH1N_PA1_AF5 +#define TIM15_CH1N_PB13_AF5 +#define TIM15_CH1N_PB15_AF4 +#define TIM15_CH1N_PF1_AF2 +#define TIM15_CH1_PA2_AF5 +#define TIM15_CH1_PB14_AF5 +#define TIM15_CH2_PA3_AF5 +#define TIM15_CH2_PB15_AF5 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB8_AF2 +#define TIM16_CH1_PD0_AF2 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PB9_AF2 +#define TIM17_CH1_PD1_AF2 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1N_PB13_AF2 +#define TIM1_CH1N_PD2_AF2 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2N_PB14_AF2 +#define TIM1_CH2N_PD3_AF2 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH3N_PB15_AF2 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_ETR_PA12_AF2 +#define TIM2_CH1_PA0_AF2 +#define TIM2_CH1_PA15_AF2 +#define TIM2_CH1_PA5_AF2 +#define TIM2_CH2_PA1_AF2 +#define TIM2_CH2_PB3_AF2 +#define TIM2_CH3_PA2_AF2 +#define TIM2_CH3_PB10_AF2 +#define TIM2_CH3_PC6_AF2 +#define TIM2_CH4_PA3_AF2 +#define TIM2_CH4_PB11_AF2 +#define TIM2_CH4_PC7_AF2 +#define TIM2_ETR_PA0_AF2 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH1_PC6_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH2_PC7_AF1 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH4_PB1_AF1 +#define TIM3_ETR_PD2_AF1 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_14 (4) +#define TIM_MODULE_15 (5) +#define TIM_MODULE_16 (6) +#define TIM_MODULE_17 (7) + +#define TIM_MODULE_COUNT (7) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +#define TIM1_BUS (1) +#define TIM15_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC6_CN +#define __PC7_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PF0_CN +#define __PF1_CN +#define __PF2_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_F_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G051C8/LQFP48/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G051C8/LQFP48/mcu_definitions.h new file mode 100644 index 000000000..db5c614db --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G051C8/LQFP48/mcu_definitions.h @@ -0,0 +1,309 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G051C8_LQFP48. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA13_CH17 +#define ADC1_PA14_CH18 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PB0_CH8 +#define ADC1_PB10_CH11 +#define ADC1_PB11_CH15 +#define ADC1_PB12_CH16 +#define ADC1_PB1_CH9 +#define ADC1_PB2_CH10 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN + +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (62) +#define DMA_NUM_OF_CHANNELS_FAMILY (62) +#define DMA_NUM_OF_MODULES (1) +#define DMA_NUM_OF_STREAMS (7) +#define DMA_NUM_OF_STREAMS_FAMILY (7) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PB9_AF6 +#define I2C2_SCL_PA11_AF6 +#define I2C2_SCL_PB10_AF6 +#define I2C2_SCL_PB13_AF6 +#define I2C2_SDA_PA12_AF6 +#define I2C2_SDA_PB11_AF6 +#define I2C2_SDA_PB14_AF6 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (2) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF6 +#define LPUART1_RX_PB10_AF1 +#define LPUART1_TX_PA2_AF6 +#define LPUART1_TX_PB11_AF1 +#define USART1_RX_PA10_AF1 +#define USART1_RX_PB7_AF0 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (2) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI2_MISO_PA3_AF0 +#define SPI2_MISO_PA9_AF4 +#define SPI2_MISO_PB14_AF0 +#define SPI2_MISO_PB2_AF1 +#define SPI2_MISO_PB6_AF4 +#define SPI2_MISO_PD3_AF1 +#define SPI2_MOSI_PA10_AF0 +#define SPI2_MOSI_PA4_AF1 +#define SPI2_MOSI_PB11_AF0 +#define SPI2_MOSI_PB15_AF0 +#define SPI2_MOSI_PB7_AF1 +#define SPI2_SCK_PA0_AF0 +#define SPI2_SCK_PB10_AF5 +#define SPI2_SCK_PB13_AF0 +#define SPI2_SCK_PB8_AF1 +#define SPI2_SCK_PD1_AF1 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF5 +#define LPTIM2_ETR_PA5_AF5 +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PB1_AF0 +#define TIM14_CH1_PF0_AF2 +#define TIM15_CH1N_PA1_AF5 +#define TIM15_CH1N_PB13_AF5 +#define TIM15_CH1N_PB15_AF4 +#define TIM15_CH1N_PF1_AF2 +#define TIM15_CH1_PA2_AF5 +#define TIM15_CH1_PB14_AF5 +#define TIM15_CH2_PA3_AF5 +#define TIM15_CH2_PB15_AF5 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB8_AF2 +#define TIM16_CH1_PD0_AF2 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PB9_AF2 +#define TIM17_CH1_PD1_AF2 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1N_PB13_AF2 +#define TIM1_CH1N_PD2_AF2 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2N_PB14_AF2 +#define TIM1_CH2N_PD3_AF2 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH3N_PB15_AF2 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_ETR_PA12_AF2 +#define TIM2_CH1_PA0_AF2 +#define TIM2_CH1_PA15_AF2 +#define TIM2_CH1_PA5_AF2 +#define TIM2_CH2_PA1_AF2 +#define TIM2_CH2_PB3_AF2 +#define TIM2_CH3_PA2_AF2 +#define TIM2_CH3_PB10_AF2 +#define TIM2_CH3_PC6_AF2 +#define TIM2_CH4_PA3_AF2 +#define TIM2_CH4_PB11_AF2 +#define TIM2_CH4_PC7_AF2 +#define TIM2_ETR_PA0_AF2 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH1_PC6_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH2_PC7_AF1 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH4_PB1_AF1 +#define TIM3_ETR_PD2_AF1 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_14 (4) +#define TIM_MODULE_15 (5) +#define TIM_MODULE_16 (6) +#define TIM_MODULE_17 (7) + +#define TIM_MODULE_COUNT (7) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +#define TIM1_BUS (1) +#define TIM15_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC6_CN +#define __PC7_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PF0_CN +#define __PF1_CN +#define __PF2_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_F_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G051C8/UFQFPN48/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G051C8/UFQFPN48/mcu_definitions.h new file mode 100644 index 000000000..8b87774e3 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G051C8/UFQFPN48/mcu_definitions.h @@ -0,0 +1,309 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G051C8_UFQFPN48. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA13_CH17 +#define ADC1_PA14_CH18 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PB0_CH8 +#define ADC1_PB10_CH11 +#define ADC1_PB11_CH15 +#define ADC1_PB12_CH16 +#define ADC1_PB1_CH9 +#define ADC1_PB2_CH10 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN + +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (62) +#define DMA_NUM_OF_CHANNELS_FAMILY (62) +#define DMA_NUM_OF_MODULES (1) +#define DMA_NUM_OF_STREAMS (7) +#define DMA_NUM_OF_STREAMS_FAMILY (7) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PB9_AF6 +#define I2C2_SCL_PA11_AF6 +#define I2C2_SCL_PB10_AF6 +#define I2C2_SCL_PB13_AF6 +#define I2C2_SDA_PA12_AF6 +#define I2C2_SDA_PB11_AF6 +#define I2C2_SDA_PB14_AF6 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (2) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF6 +#define LPUART1_RX_PB10_AF1 +#define LPUART1_TX_PA2_AF6 +#define LPUART1_TX_PB11_AF1 +#define USART1_RX_PA10_AF1 +#define USART1_RX_PB7_AF0 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (2) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI2_MISO_PA3_AF0 +#define SPI2_MISO_PA9_AF4 +#define SPI2_MISO_PB14_AF0 +#define SPI2_MISO_PB2_AF1 +#define SPI2_MISO_PB6_AF4 +#define SPI2_MISO_PD3_AF1 +#define SPI2_MOSI_PA10_AF0 +#define SPI2_MOSI_PA4_AF1 +#define SPI2_MOSI_PB11_AF0 +#define SPI2_MOSI_PB15_AF0 +#define SPI2_MOSI_PB7_AF1 +#define SPI2_SCK_PA0_AF0 +#define SPI2_SCK_PB10_AF5 +#define SPI2_SCK_PB13_AF0 +#define SPI2_SCK_PB8_AF1 +#define SPI2_SCK_PD1_AF1 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF5 +#define LPTIM2_ETR_PA5_AF5 +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PB1_AF0 +#define TIM14_CH1_PF0_AF2 +#define TIM15_CH1N_PA1_AF5 +#define TIM15_CH1N_PB13_AF5 +#define TIM15_CH1N_PB15_AF4 +#define TIM15_CH1N_PF1_AF2 +#define TIM15_CH1_PA2_AF5 +#define TIM15_CH1_PB14_AF5 +#define TIM15_CH2_PA3_AF5 +#define TIM15_CH2_PB15_AF5 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB8_AF2 +#define TIM16_CH1_PD0_AF2 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PB9_AF2 +#define TIM17_CH1_PD1_AF2 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1N_PB13_AF2 +#define TIM1_CH1N_PD2_AF2 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2N_PB14_AF2 +#define TIM1_CH2N_PD3_AF2 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH3N_PB15_AF2 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_ETR_PA12_AF2 +#define TIM2_CH1_PA0_AF2 +#define TIM2_CH1_PA15_AF2 +#define TIM2_CH1_PA5_AF2 +#define TIM2_CH2_PA1_AF2 +#define TIM2_CH2_PB3_AF2 +#define TIM2_CH3_PA2_AF2 +#define TIM2_CH3_PB10_AF2 +#define TIM2_CH3_PC6_AF2 +#define TIM2_CH4_PA3_AF2 +#define TIM2_CH4_PB11_AF2 +#define TIM2_CH4_PC7_AF2 +#define TIM2_ETR_PA0_AF2 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH1_PC6_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH2_PC7_AF1 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH4_PB1_AF1 +#define TIM3_ETR_PD2_AF1 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_14 (4) +#define TIM_MODULE_15 (5) +#define TIM_MODULE_16 (6) +#define TIM_MODULE_17 (7) + +#define TIM_MODULE_COUNT (7) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +#define TIM1_BUS (1) +#define TIM15_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC6_CN +#define __PC7_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PF0_CN +#define __PF1_CN +#define __PF2_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_F_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G051F6/TSSOP20/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G051F6/TSSOP20/mcu_definitions.h new file mode 100644 index 000000000..9236502ba --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G051F6/TSSOP20/mcu_definitions.h @@ -0,0 +1,260 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G051F6_TSSOP20. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA11_CH15 +#define ADC1_PA12_CH16 +#define ADC1_PA13_CH17 +#define ADC1_PA14_CH18 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PB0_CH8 +#define ADC1_PB1_CH9 +#define ADC1_PB2_CH10 +#define ADC1_PB7_CH11 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN + +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (62) +#define DMA_NUM_OF_CHANNELS_FAMILY (62) +#define DMA_NUM_OF_MODULES (1) +#define DMA_NUM_OF_STREAMS (7) +#define DMA_NUM_OF_STREAMS_FAMILY (7) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PB9_AF6 +#define I2C2_SCL_PA11_AF6 +#define I2C2_SDA_PA12_AF6 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (2) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF6 +#define LPUART1_TX_PA2_AF6 +#define USART1_RX_PA10_AF1 +#define USART1_RX_PB7_AF0 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (2) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI2_MISO_PA3_AF0 +#define SPI2_MISO_PA9_AF4 +#define SPI2_MISO_PB2_AF1 +#define SPI2_MISO_PB6_AF4 +#define SPI2_MOSI_PA10_AF0 +#define SPI2_MOSI_PA4_AF1 +#define SPI2_MOSI_PB7_AF1 +#define SPI2_SCK_PA0_AF0 +#define SPI2_SCK_PB8_AF1 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF5 +#define LPTIM2_ETR_PA5_AF5 +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PB1_AF0 +#define TIM15_CH1N_PA1_AF5 +#define TIM15_CH1_PA2_AF5 +#define TIM15_CH2_PA3_AF5 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB8_AF2 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PB9_AF2 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_ETR_PA12_AF2 +#define TIM2_CH1_PA0_AF2 +#define TIM2_CH1_PA15_AF2 +#define TIM2_CH1_PA5_AF2 +#define TIM2_CH2_PA1_AF2 +#define TIM2_CH2_PB3_AF2 +#define TIM2_CH3_PA2_AF2 +#define TIM2_CH4_PA3_AF2 +#define TIM2_ETR_PA0_AF2 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH4_PB1_AF1 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_14 (4) +#define TIM_MODULE_15 (5) +#define TIM_MODULE_16 (6) +#define TIM_MODULE_17 (7) + +#define TIM_MODULE_COUNT (7) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +#define TIM1_BUS (1) +#define TIM15_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC14_CN +#define __PC15_CN +#define __PF2_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN + +#define PORT_COUNT (4) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G051F8/TSSOP20/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G051F8/TSSOP20/mcu_definitions.h new file mode 100644 index 000000000..c31e3f631 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G051F8/TSSOP20/mcu_definitions.h @@ -0,0 +1,260 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G051F8_TSSOP20. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA11_CH15 +#define ADC1_PA12_CH16 +#define ADC1_PA13_CH17 +#define ADC1_PA14_CH18 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PB0_CH8 +#define ADC1_PB1_CH9 +#define ADC1_PB2_CH10 +#define ADC1_PB7_CH11 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN + +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (62) +#define DMA_NUM_OF_CHANNELS_FAMILY (62) +#define DMA_NUM_OF_MODULES (1) +#define DMA_NUM_OF_STREAMS (7) +#define DMA_NUM_OF_STREAMS_FAMILY (7) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PB9_AF6 +#define I2C2_SCL_PA11_AF6 +#define I2C2_SDA_PA12_AF6 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (2) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF6 +#define LPUART1_TX_PA2_AF6 +#define USART1_RX_PA10_AF1 +#define USART1_RX_PB7_AF0 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (2) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI2_MISO_PA3_AF0 +#define SPI2_MISO_PA9_AF4 +#define SPI2_MISO_PB2_AF1 +#define SPI2_MISO_PB6_AF4 +#define SPI2_MOSI_PA10_AF0 +#define SPI2_MOSI_PA4_AF1 +#define SPI2_MOSI_PB7_AF1 +#define SPI2_SCK_PA0_AF0 +#define SPI2_SCK_PB8_AF1 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF5 +#define LPTIM2_ETR_PA5_AF5 +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PB1_AF0 +#define TIM15_CH1N_PA1_AF5 +#define TIM15_CH1_PA2_AF5 +#define TIM15_CH2_PA3_AF5 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB8_AF2 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PB9_AF2 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_ETR_PA12_AF2 +#define TIM2_CH1_PA0_AF2 +#define TIM2_CH1_PA15_AF2 +#define TIM2_CH1_PA5_AF2 +#define TIM2_CH2_PA1_AF2 +#define TIM2_CH2_PB3_AF2 +#define TIM2_CH3_PA2_AF2 +#define TIM2_CH4_PA3_AF2 +#define TIM2_ETR_PA0_AF2 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH4_PB1_AF1 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_14 (4) +#define TIM_MODULE_15 (5) +#define TIM_MODULE_16 (6) +#define TIM_MODULE_17 (7) + +#define TIM_MODULE_COUNT (7) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +#define TIM1_BUS (1) +#define TIM15_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC14_CN +#define __PC15_CN +#define __PF2_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN + +#define PORT_COUNT (4) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G051F8/WLCSP20/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G051F8/WLCSP20/mcu_definitions.h new file mode 100644 index 000000000..f0052c2b1 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G051F8/WLCSP20/mcu_definitions.h @@ -0,0 +1,260 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G051F8_WLCSP20. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA11_CH15 +#define ADC1_PA12_CH16 +#define ADC1_PA13_CH17 +#define ADC1_PA14_CH18 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PB0_CH8 +#define ADC1_PB1_CH9 +#define ADC1_PB2_CH10 +#define ADC1_PB7_CH11 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN + +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (62) +#define DMA_NUM_OF_CHANNELS_FAMILY (62) +#define DMA_NUM_OF_MODULES (1) +#define DMA_NUM_OF_STREAMS (7) +#define DMA_NUM_OF_STREAMS_FAMILY (7) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PB9_AF6 +#define I2C2_SCL_PA11_AF6 +#define I2C2_SDA_PA12_AF6 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (2) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF6 +#define LPUART1_TX_PA2_AF6 +#define USART1_RX_PA10_AF1 +#define USART1_RX_PB7_AF0 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (2) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI2_MISO_PA3_AF0 +#define SPI2_MISO_PA9_AF4 +#define SPI2_MISO_PB2_AF1 +#define SPI2_MISO_PB6_AF4 +#define SPI2_MOSI_PA10_AF0 +#define SPI2_MOSI_PA4_AF1 +#define SPI2_MOSI_PB7_AF1 +#define SPI2_SCK_PA0_AF0 +#define SPI2_SCK_PB8_AF1 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF5 +#define LPTIM2_ETR_PA5_AF5 +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PB1_AF0 +#define TIM15_CH1N_PA1_AF5 +#define TIM15_CH1_PA2_AF5 +#define TIM15_CH2_PA3_AF5 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB8_AF2 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PB9_AF2 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_ETR_PA12_AF2 +#define TIM2_CH1_PA0_AF2 +#define TIM2_CH1_PA15_AF2 +#define TIM2_CH1_PA5_AF2 +#define TIM2_CH2_PA1_AF2 +#define TIM2_CH2_PB3_AF2 +#define TIM2_CH3_PA2_AF2 +#define TIM2_CH4_PA3_AF2 +#define TIM2_ETR_PA0_AF2 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH4_PB1_AF1 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_14 (4) +#define TIM_MODULE_15 (5) +#define TIM_MODULE_16 (6) +#define TIM_MODULE_17 (7) + +#define TIM_MODULE_COUNT (7) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +#define TIM1_BUS (1) +#define TIM15_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC14_CN +#define __PC15_CN +#define __PF2_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN + +#define PORT_COUNT (4) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G051G6/UFQFPN28/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G051G6/UFQFPN28/mcu_definitions.h new file mode 100644 index 000000000..4d1108bdc --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G051G6/UFQFPN28/mcu_definitions.h @@ -0,0 +1,257 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G051G6_UFQFPN28. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA11_CH15 +#define ADC1_PA12_CH16 +#define ADC1_PA13_CH17 +#define ADC1_PA14_CH18 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PB0_CH8 +#define ADC1_PB1_CH9 +#define ADC1_PB7_CH11 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN + +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (62) +#define DMA_NUM_OF_CHANNELS_FAMILY (62) +#define DMA_NUM_OF_MODULES (1) +#define DMA_NUM_OF_STREAMS (7) +#define DMA_NUM_OF_STREAMS_FAMILY (7) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C2_SCL_PA11_AF6 +#define I2C2_SDA_PA12_AF6 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (2) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF6 +#define LPUART1_TX_PA2_AF6 +#define USART1_RX_PA10_AF1 +#define USART1_RX_PB7_AF0 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (2) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI2_MISO_PA3_AF0 +#define SPI2_MISO_PA9_AF4 +#define SPI2_MISO_PB6_AF4 +#define SPI2_MOSI_PA10_AF0 +#define SPI2_MOSI_PA4_AF1 +#define SPI2_MOSI_PB7_AF1 +#define SPI2_SCK_PA0_AF0 +#define SPI2_SCK_PB8_AF1 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF5 +#define LPTIM2_ETR_PA5_AF5 +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PB1_AF0 +#define TIM15_CH1N_PA1_AF5 +#define TIM15_CH1_PA2_AF5 +#define TIM15_CH2_PA3_AF5 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB8_AF2 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_ETR_PA12_AF2 +#define TIM2_CH1_PA0_AF2 +#define TIM2_CH1_PA15_AF2 +#define TIM2_CH1_PA5_AF2 +#define TIM2_CH2_PA1_AF2 +#define TIM2_CH2_PB3_AF2 +#define TIM2_CH3_PA2_AF2 +#define TIM2_CH3_PC6_AF2 +#define TIM2_CH4_PA3_AF2 +#define TIM2_ETR_PA0_AF2 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH1_PC6_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH4_PB1_AF1 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_14 (4) +#define TIM_MODULE_15 (5) +#define TIM_MODULE_16 (6) +#define TIM_MODULE_17 (7) + +#define TIM_MODULE_COUNT (7) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +#define TIM1_BUS (1) +#define TIM15_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PC14_CN +#define __PC15_CN +#define __PC6_CN +#define __PF2_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN + +#define PORT_COUNT (4) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G051G8/UFQFPN28/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G051G8/UFQFPN28/mcu_definitions.h new file mode 100644 index 000000000..c1a63bbac --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G051G8/UFQFPN28/mcu_definitions.h @@ -0,0 +1,257 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G051G8_UFQFPN28. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA11_CH15 +#define ADC1_PA12_CH16 +#define ADC1_PA13_CH17 +#define ADC1_PA14_CH18 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PB0_CH8 +#define ADC1_PB1_CH9 +#define ADC1_PB7_CH11 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN + +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (62) +#define DMA_NUM_OF_CHANNELS_FAMILY (62) +#define DMA_NUM_OF_MODULES (1) +#define DMA_NUM_OF_STREAMS (7) +#define DMA_NUM_OF_STREAMS_FAMILY (7) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C2_SCL_PA11_AF6 +#define I2C2_SDA_PA12_AF6 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (2) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF6 +#define LPUART1_TX_PA2_AF6 +#define USART1_RX_PA10_AF1 +#define USART1_RX_PB7_AF0 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (2) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI2_MISO_PA3_AF0 +#define SPI2_MISO_PA9_AF4 +#define SPI2_MISO_PB6_AF4 +#define SPI2_MOSI_PA10_AF0 +#define SPI2_MOSI_PA4_AF1 +#define SPI2_MOSI_PB7_AF1 +#define SPI2_SCK_PA0_AF0 +#define SPI2_SCK_PB8_AF1 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF5 +#define LPTIM2_ETR_PA5_AF5 +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PB1_AF0 +#define TIM15_CH1N_PA1_AF5 +#define TIM15_CH1_PA2_AF5 +#define TIM15_CH2_PA3_AF5 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB8_AF2 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_ETR_PA12_AF2 +#define TIM2_CH1_PA0_AF2 +#define TIM2_CH1_PA15_AF2 +#define TIM2_CH1_PA5_AF2 +#define TIM2_CH2_PA1_AF2 +#define TIM2_CH2_PB3_AF2 +#define TIM2_CH3_PA2_AF2 +#define TIM2_CH3_PC6_AF2 +#define TIM2_CH4_PA3_AF2 +#define TIM2_ETR_PA0_AF2 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH1_PC6_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH4_PB1_AF1 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_14 (4) +#define TIM_MODULE_15 (5) +#define TIM_MODULE_16 (6) +#define TIM_MODULE_17 (7) + +#define TIM_MODULE_COUNT (7) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +#define TIM1_BUS (1) +#define TIM15_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PC14_CN +#define __PC15_CN +#define __PC6_CN +#define __PF2_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN + +#define PORT_COUNT (4) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G051K6/LQFP32/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G051K6/LQFP32/mcu_definitions.h new file mode 100644 index 000000000..c7a5728ac --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G051K6/LQFP32/mcu_definitions.h @@ -0,0 +1,263 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G051K6_LQFP32. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA11_CH15 +#define ADC1_PA12_CH16 +#define ADC1_PA13_CH17 +#define ADC1_PA14_CH18 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PB0_CH8 +#define ADC1_PB1_CH9 +#define ADC1_PB2_CH10 +#define ADC1_PB7_CH11 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN + +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (62) +#define DMA_NUM_OF_CHANNELS_FAMILY (62) +#define DMA_NUM_OF_MODULES (1) +#define DMA_NUM_OF_STREAMS (7) +#define DMA_NUM_OF_STREAMS_FAMILY (7) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PB9_AF6 +#define I2C2_SCL_PA11_AF6 +#define I2C2_SDA_PA12_AF6 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (2) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF6 +#define LPUART1_TX_PA2_AF6 +#define USART1_RX_PA10_AF1 +#define USART1_RX_PB7_AF0 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (2) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI2_MISO_PA3_AF0 +#define SPI2_MISO_PA9_AF4 +#define SPI2_MISO_PB2_AF1 +#define SPI2_MISO_PB6_AF4 +#define SPI2_MOSI_PA10_AF0 +#define SPI2_MOSI_PA4_AF1 +#define SPI2_MOSI_PB7_AF1 +#define SPI2_SCK_PA0_AF0 +#define SPI2_SCK_PB8_AF1 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF5 +#define LPTIM2_ETR_PA5_AF5 +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PB1_AF0 +#define TIM15_CH1N_PA1_AF5 +#define TIM15_CH1_PA2_AF5 +#define TIM15_CH2_PA3_AF5 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB8_AF2 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PB9_AF2 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_ETR_PA12_AF2 +#define TIM2_CH1_PA0_AF2 +#define TIM2_CH1_PA15_AF2 +#define TIM2_CH1_PA5_AF2 +#define TIM2_CH2_PA1_AF2 +#define TIM2_CH2_PB3_AF2 +#define TIM2_CH3_PA2_AF2 +#define TIM2_CH3_PC6_AF2 +#define TIM2_CH4_PA3_AF2 +#define TIM2_ETR_PA0_AF2 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH1_PC6_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH4_PB1_AF1 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_14 (4) +#define TIM_MODULE_15 (5) +#define TIM_MODULE_16 (6) +#define TIM_MODULE_17 (7) + +#define TIM_MODULE_COUNT (7) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +#define TIM1_BUS (1) +#define TIM15_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC14_CN +#define __PC15_CN +#define __PC6_CN +#define __PF2_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN + +#define PORT_COUNT (4) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G051K6/UFQFPN32/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G051K6/UFQFPN32/mcu_definitions.h new file mode 100644 index 000000000..4354e4df2 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G051K6/UFQFPN32/mcu_definitions.h @@ -0,0 +1,263 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G051K6_UFQFPN32. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA11_CH15 +#define ADC1_PA12_CH16 +#define ADC1_PA13_CH17 +#define ADC1_PA14_CH18 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PB0_CH8 +#define ADC1_PB1_CH9 +#define ADC1_PB2_CH10 +#define ADC1_PB7_CH11 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN + +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (62) +#define DMA_NUM_OF_CHANNELS_FAMILY (62) +#define DMA_NUM_OF_MODULES (1) +#define DMA_NUM_OF_STREAMS (7) +#define DMA_NUM_OF_STREAMS_FAMILY (7) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PB9_AF6 +#define I2C2_SCL_PA11_AF6 +#define I2C2_SDA_PA12_AF6 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (2) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF6 +#define LPUART1_TX_PA2_AF6 +#define USART1_RX_PA10_AF1 +#define USART1_RX_PB7_AF0 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (2) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI2_MISO_PA3_AF0 +#define SPI2_MISO_PA9_AF4 +#define SPI2_MISO_PB2_AF1 +#define SPI2_MISO_PB6_AF4 +#define SPI2_MOSI_PA10_AF0 +#define SPI2_MOSI_PA4_AF1 +#define SPI2_MOSI_PB7_AF1 +#define SPI2_SCK_PA0_AF0 +#define SPI2_SCK_PB8_AF1 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF5 +#define LPTIM2_ETR_PA5_AF5 +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PB1_AF0 +#define TIM15_CH1N_PA1_AF5 +#define TIM15_CH1_PA2_AF5 +#define TIM15_CH2_PA3_AF5 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB8_AF2 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PB9_AF2 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_ETR_PA12_AF2 +#define TIM2_CH1_PA0_AF2 +#define TIM2_CH1_PA15_AF2 +#define TIM2_CH1_PA5_AF2 +#define TIM2_CH2_PA1_AF2 +#define TIM2_CH2_PB3_AF2 +#define TIM2_CH3_PA2_AF2 +#define TIM2_CH3_PC6_AF2 +#define TIM2_CH4_PA3_AF2 +#define TIM2_ETR_PA0_AF2 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH1_PC6_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH4_PB1_AF1 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_14 (4) +#define TIM_MODULE_15 (5) +#define TIM_MODULE_16 (6) +#define TIM_MODULE_17 (7) + +#define TIM_MODULE_COUNT (7) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +#define TIM1_BUS (1) +#define TIM15_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC14_CN +#define __PC15_CN +#define __PC6_CN +#define __PF2_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN + +#define PORT_COUNT (4) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G051K8/LQFP32/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G051K8/LQFP32/mcu_definitions.h new file mode 100644 index 000000000..4ab7fcc1e --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G051K8/LQFP32/mcu_definitions.h @@ -0,0 +1,263 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G051K8_LQFP32. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA11_CH15 +#define ADC1_PA12_CH16 +#define ADC1_PA13_CH17 +#define ADC1_PA14_CH18 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PB0_CH8 +#define ADC1_PB1_CH9 +#define ADC1_PB2_CH10 +#define ADC1_PB7_CH11 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN + +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (62) +#define DMA_NUM_OF_CHANNELS_FAMILY (62) +#define DMA_NUM_OF_MODULES (1) +#define DMA_NUM_OF_STREAMS (7) +#define DMA_NUM_OF_STREAMS_FAMILY (7) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PB9_AF6 +#define I2C2_SCL_PA11_AF6 +#define I2C2_SDA_PA12_AF6 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (2) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF6 +#define LPUART1_TX_PA2_AF6 +#define USART1_RX_PA10_AF1 +#define USART1_RX_PB7_AF0 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (2) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI2_MISO_PA3_AF0 +#define SPI2_MISO_PA9_AF4 +#define SPI2_MISO_PB2_AF1 +#define SPI2_MISO_PB6_AF4 +#define SPI2_MOSI_PA10_AF0 +#define SPI2_MOSI_PA4_AF1 +#define SPI2_MOSI_PB7_AF1 +#define SPI2_SCK_PA0_AF0 +#define SPI2_SCK_PB8_AF1 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF5 +#define LPTIM2_ETR_PA5_AF5 +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PB1_AF0 +#define TIM15_CH1N_PA1_AF5 +#define TIM15_CH1_PA2_AF5 +#define TIM15_CH2_PA3_AF5 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB8_AF2 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PB9_AF2 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_ETR_PA12_AF2 +#define TIM2_CH1_PA0_AF2 +#define TIM2_CH1_PA15_AF2 +#define TIM2_CH1_PA5_AF2 +#define TIM2_CH2_PA1_AF2 +#define TIM2_CH2_PB3_AF2 +#define TIM2_CH3_PA2_AF2 +#define TIM2_CH3_PC6_AF2 +#define TIM2_CH4_PA3_AF2 +#define TIM2_ETR_PA0_AF2 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH1_PC6_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH4_PB1_AF1 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_14 (4) +#define TIM_MODULE_15 (5) +#define TIM_MODULE_16 (6) +#define TIM_MODULE_17 (7) + +#define TIM_MODULE_COUNT (7) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +#define TIM1_BUS (1) +#define TIM15_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC14_CN +#define __PC15_CN +#define __PC6_CN +#define __PF2_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN + +#define PORT_COUNT (4) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G051K8/UFQFPN32/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G051K8/UFQFPN32/mcu_definitions.h new file mode 100644 index 000000000..3add04d54 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G051K8/UFQFPN32/mcu_definitions.h @@ -0,0 +1,263 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G051K8_UFQFPN32. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA11_CH15 +#define ADC1_PA12_CH16 +#define ADC1_PA13_CH17 +#define ADC1_PA14_CH18 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PB0_CH8 +#define ADC1_PB1_CH9 +#define ADC1_PB2_CH10 +#define ADC1_PB7_CH11 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN + +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (62) +#define DMA_NUM_OF_CHANNELS_FAMILY (62) +#define DMA_NUM_OF_MODULES (1) +#define DMA_NUM_OF_STREAMS (7) +#define DMA_NUM_OF_STREAMS_FAMILY (7) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PB9_AF6 +#define I2C2_SCL_PA11_AF6 +#define I2C2_SDA_PA12_AF6 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (2) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF6 +#define LPUART1_TX_PA2_AF6 +#define USART1_RX_PA10_AF1 +#define USART1_RX_PB7_AF0 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (2) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI2_MISO_PA3_AF0 +#define SPI2_MISO_PA9_AF4 +#define SPI2_MISO_PB2_AF1 +#define SPI2_MISO_PB6_AF4 +#define SPI2_MOSI_PA10_AF0 +#define SPI2_MOSI_PA4_AF1 +#define SPI2_MOSI_PB7_AF1 +#define SPI2_SCK_PA0_AF0 +#define SPI2_SCK_PB8_AF1 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF5 +#define LPTIM2_ETR_PA5_AF5 +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PB1_AF0 +#define TIM15_CH1N_PA1_AF5 +#define TIM15_CH1_PA2_AF5 +#define TIM15_CH2_PA3_AF5 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB8_AF2 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PB9_AF2 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_ETR_PA12_AF2 +#define TIM2_CH1_PA0_AF2 +#define TIM2_CH1_PA15_AF2 +#define TIM2_CH1_PA5_AF2 +#define TIM2_CH2_PA1_AF2 +#define TIM2_CH2_PB3_AF2 +#define TIM2_CH3_PA2_AF2 +#define TIM2_CH3_PC6_AF2 +#define TIM2_CH4_PA3_AF2 +#define TIM2_ETR_PA0_AF2 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH1_PC6_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH4_PB1_AF1 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_14 (4) +#define TIM_MODULE_15 (5) +#define TIM_MODULE_16 (6) +#define TIM_MODULE_17 (7) + +#define TIM_MODULE_COUNT (7) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +#define TIM1_BUS (1) +#define TIM15_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC14_CN +#define __PC15_CN +#define __PC6_CN +#define __PF2_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN + +#define PORT_COUNT (4) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G061C6/LQFP48/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G061C6/LQFP48/mcu_definitions.h new file mode 100644 index 000000000..fc131e51a --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G061C6/LQFP48/mcu_definitions.h @@ -0,0 +1,309 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G061C6_LQFP48. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA13_CH17 +#define ADC1_PA14_CH18 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PB0_CH8 +#define ADC1_PB10_CH11 +#define ADC1_PB11_CH15 +#define ADC1_PB12_CH16 +#define ADC1_PB1_CH9 +#define ADC1_PB2_CH10 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN + +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (62) +#define DMA_NUM_OF_CHANNELS_FAMILY (62) +#define DMA_NUM_OF_MODULES (1) +#define DMA_NUM_OF_STREAMS (7) +#define DMA_NUM_OF_STREAMS_FAMILY (7) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PB9_AF6 +#define I2C2_SCL_PA11_AF6 +#define I2C2_SCL_PB10_AF6 +#define I2C2_SCL_PB13_AF6 +#define I2C2_SDA_PA12_AF6 +#define I2C2_SDA_PB11_AF6 +#define I2C2_SDA_PB14_AF6 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (2) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF6 +#define LPUART1_RX_PB10_AF1 +#define LPUART1_TX_PA2_AF6 +#define LPUART1_TX_PB11_AF1 +#define USART1_RX_PA10_AF1 +#define USART1_RX_PB7_AF0 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (2) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI2_MISO_PA3_AF0 +#define SPI2_MISO_PA9_AF4 +#define SPI2_MISO_PB14_AF0 +#define SPI2_MISO_PB2_AF1 +#define SPI2_MISO_PB6_AF4 +#define SPI2_MISO_PD3_AF1 +#define SPI2_MOSI_PA10_AF0 +#define SPI2_MOSI_PA4_AF1 +#define SPI2_MOSI_PB11_AF0 +#define SPI2_MOSI_PB15_AF0 +#define SPI2_MOSI_PB7_AF1 +#define SPI2_SCK_PA0_AF0 +#define SPI2_SCK_PB10_AF5 +#define SPI2_SCK_PB13_AF0 +#define SPI2_SCK_PB8_AF1 +#define SPI2_SCK_PD1_AF1 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF5 +#define LPTIM2_ETR_PA5_AF5 +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PB1_AF0 +#define TIM14_CH1_PF0_AF2 +#define TIM15_CH1N_PA1_AF5 +#define TIM15_CH1N_PB13_AF5 +#define TIM15_CH1N_PB15_AF4 +#define TIM15_CH1N_PF1_AF2 +#define TIM15_CH1_PA2_AF5 +#define TIM15_CH1_PB14_AF5 +#define TIM15_CH2_PA3_AF5 +#define TIM15_CH2_PB15_AF5 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB8_AF2 +#define TIM16_CH1_PD0_AF2 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PB9_AF2 +#define TIM17_CH1_PD1_AF2 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1N_PB13_AF2 +#define TIM1_CH1N_PD2_AF2 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2N_PB14_AF2 +#define TIM1_CH2N_PD3_AF2 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH3N_PB15_AF2 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_ETR_PA12_AF2 +#define TIM2_CH1_PA0_AF2 +#define TIM2_CH1_PA15_AF2 +#define TIM2_CH1_PA5_AF2 +#define TIM2_CH2_PA1_AF2 +#define TIM2_CH2_PB3_AF2 +#define TIM2_CH3_PA2_AF2 +#define TIM2_CH3_PB10_AF2 +#define TIM2_CH3_PC6_AF2 +#define TIM2_CH4_PA3_AF2 +#define TIM2_CH4_PB11_AF2 +#define TIM2_CH4_PC7_AF2 +#define TIM2_ETR_PA0_AF2 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH1_PC6_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH2_PC7_AF1 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH4_PB1_AF1 +#define TIM3_ETR_PD2_AF1 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_14 (4) +#define TIM_MODULE_15 (5) +#define TIM_MODULE_16 (6) +#define TIM_MODULE_17 (7) + +#define TIM_MODULE_COUNT (7) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +#define TIM1_BUS (1) +#define TIM15_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC6_CN +#define __PC7_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PF0_CN +#define __PF1_CN +#define __PF2_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_F_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G061C6/UFQFPN48/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G061C6/UFQFPN48/mcu_definitions.h new file mode 100644 index 000000000..b66cc57f0 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G061C6/UFQFPN48/mcu_definitions.h @@ -0,0 +1,309 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G061C6_UFQFPN48. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA13_CH17 +#define ADC1_PA14_CH18 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PB0_CH8 +#define ADC1_PB10_CH11 +#define ADC1_PB11_CH15 +#define ADC1_PB12_CH16 +#define ADC1_PB1_CH9 +#define ADC1_PB2_CH10 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN + +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (62) +#define DMA_NUM_OF_CHANNELS_FAMILY (62) +#define DMA_NUM_OF_MODULES (1) +#define DMA_NUM_OF_STREAMS (7) +#define DMA_NUM_OF_STREAMS_FAMILY (7) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PB9_AF6 +#define I2C2_SCL_PA11_AF6 +#define I2C2_SCL_PB10_AF6 +#define I2C2_SCL_PB13_AF6 +#define I2C2_SDA_PA12_AF6 +#define I2C2_SDA_PB11_AF6 +#define I2C2_SDA_PB14_AF6 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (2) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF6 +#define LPUART1_RX_PB10_AF1 +#define LPUART1_TX_PA2_AF6 +#define LPUART1_TX_PB11_AF1 +#define USART1_RX_PA10_AF1 +#define USART1_RX_PB7_AF0 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (2) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI2_MISO_PA3_AF0 +#define SPI2_MISO_PA9_AF4 +#define SPI2_MISO_PB14_AF0 +#define SPI2_MISO_PB2_AF1 +#define SPI2_MISO_PB6_AF4 +#define SPI2_MISO_PD3_AF1 +#define SPI2_MOSI_PA10_AF0 +#define SPI2_MOSI_PA4_AF1 +#define SPI2_MOSI_PB11_AF0 +#define SPI2_MOSI_PB15_AF0 +#define SPI2_MOSI_PB7_AF1 +#define SPI2_SCK_PA0_AF0 +#define SPI2_SCK_PB10_AF5 +#define SPI2_SCK_PB13_AF0 +#define SPI2_SCK_PB8_AF1 +#define SPI2_SCK_PD1_AF1 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF5 +#define LPTIM2_ETR_PA5_AF5 +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PB1_AF0 +#define TIM14_CH1_PF0_AF2 +#define TIM15_CH1N_PA1_AF5 +#define TIM15_CH1N_PB13_AF5 +#define TIM15_CH1N_PB15_AF4 +#define TIM15_CH1N_PF1_AF2 +#define TIM15_CH1_PA2_AF5 +#define TIM15_CH1_PB14_AF5 +#define TIM15_CH2_PA3_AF5 +#define TIM15_CH2_PB15_AF5 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB8_AF2 +#define TIM16_CH1_PD0_AF2 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PB9_AF2 +#define TIM17_CH1_PD1_AF2 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1N_PB13_AF2 +#define TIM1_CH1N_PD2_AF2 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2N_PB14_AF2 +#define TIM1_CH2N_PD3_AF2 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH3N_PB15_AF2 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_ETR_PA12_AF2 +#define TIM2_CH1_PA0_AF2 +#define TIM2_CH1_PA15_AF2 +#define TIM2_CH1_PA5_AF2 +#define TIM2_CH2_PA1_AF2 +#define TIM2_CH2_PB3_AF2 +#define TIM2_CH3_PA2_AF2 +#define TIM2_CH3_PB10_AF2 +#define TIM2_CH3_PC6_AF2 +#define TIM2_CH4_PA3_AF2 +#define TIM2_CH4_PB11_AF2 +#define TIM2_CH4_PC7_AF2 +#define TIM2_ETR_PA0_AF2 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH1_PC6_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH2_PC7_AF1 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH4_PB1_AF1 +#define TIM3_ETR_PD2_AF1 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_14 (4) +#define TIM_MODULE_15 (5) +#define TIM_MODULE_16 (6) +#define TIM_MODULE_17 (7) + +#define TIM_MODULE_COUNT (7) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +#define TIM1_BUS (1) +#define TIM15_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC6_CN +#define __PC7_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PF0_CN +#define __PF1_CN +#define __PF2_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_F_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G061C8/LQFP48/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G061C8/LQFP48/mcu_definitions.h new file mode 100644 index 000000000..9e1ad4326 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G061C8/LQFP48/mcu_definitions.h @@ -0,0 +1,309 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G061C8_LQFP48. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA13_CH17 +#define ADC1_PA14_CH18 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PB0_CH8 +#define ADC1_PB10_CH11 +#define ADC1_PB11_CH15 +#define ADC1_PB12_CH16 +#define ADC1_PB1_CH9 +#define ADC1_PB2_CH10 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN + +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (62) +#define DMA_NUM_OF_CHANNELS_FAMILY (62) +#define DMA_NUM_OF_MODULES (1) +#define DMA_NUM_OF_STREAMS (7) +#define DMA_NUM_OF_STREAMS_FAMILY (7) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PB9_AF6 +#define I2C2_SCL_PA11_AF6 +#define I2C2_SCL_PB10_AF6 +#define I2C2_SCL_PB13_AF6 +#define I2C2_SDA_PA12_AF6 +#define I2C2_SDA_PB11_AF6 +#define I2C2_SDA_PB14_AF6 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (2) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF6 +#define LPUART1_RX_PB10_AF1 +#define LPUART1_TX_PA2_AF6 +#define LPUART1_TX_PB11_AF1 +#define USART1_RX_PA10_AF1 +#define USART1_RX_PB7_AF0 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (2) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI2_MISO_PA3_AF0 +#define SPI2_MISO_PA9_AF4 +#define SPI2_MISO_PB14_AF0 +#define SPI2_MISO_PB2_AF1 +#define SPI2_MISO_PB6_AF4 +#define SPI2_MISO_PD3_AF1 +#define SPI2_MOSI_PA10_AF0 +#define SPI2_MOSI_PA4_AF1 +#define SPI2_MOSI_PB11_AF0 +#define SPI2_MOSI_PB15_AF0 +#define SPI2_MOSI_PB7_AF1 +#define SPI2_SCK_PA0_AF0 +#define SPI2_SCK_PB10_AF5 +#define SPI2_SCK_PB13_AF0 +#define SPI2_SCK_PB8_AF1 +#define SPI2_SCK_PD1_AF1 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF5 +#define LPTIM2_ETR_PA5_AF5 +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PB1_AF0 +#define TIM14_CH1_PF0_AF2 +#define TIM15_CH1N_PA1_AF5 +#define TIM15_CH1N_PB13_AF5 +#define TIM15_CH1N_PB15_AF4 +#define TIM15_CH1N_PF1_AF2 +#define TIM15_CH1_PA2_AF5 +#define TIM15_CH1_PB14_AF5 +#define TIM15_CH2_PA3_AF5 +#define TIM15_CH2_PB15_AF5 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB8_AF2 +#define TIM16_CH1_PD0_AF2 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PB9_AF2 +#define TIM17_CH1_PD1_AF2 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1N_PB13_AF2 +#define TIM1_CH1N_PD2_AF2 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2N_PB14_AF2 +#define TIM1_CH2N_PD3_AF2 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH3N_PB15_AF2 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_ETR_PA12_AF2 +#define TIM2_CH1_PA0_AF2 +#define TIM2_CH1_PA15_AF2 +#define TIM2_CH1_PA5_AF2 +#define TIM2_CH2_PA1_AF2 +#define TIM2_CH2_PB3_AF2 +#define TIM2_CH3_PA2_AF2 +#define TIM2_CH3_PB10_AF2 +#define TIM2_CH3_PC6_AF2 +#define TIM2_CH4_PA3_AF2 +#define TIM2_CH4_PB11_AF2 +#define TIM2_CH4_PC7_AF2 +#define TIM2_ETR_PA0_AF2 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH1_PC6_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH2_PC7_AF1 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH4_PB1_AF1 +#define TIM3_ETR_PD2_AF1 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_14 (4) +#define TIM_MODULE_15 (5) +#define TIM_MODULE_16 (6) +#define TIM_MODULE_17 (7) + +#define TIM_MODULE_COUNT (7) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +#define TIM1_BUS (1) +#define TIM15_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC6_CN +#define __PC7_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PF0_CN +#define __PF1_CN +#define __PF2_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_F_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G061C8/UFQFPN48/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G061C8/UFQFPN48/mcu_definitions.h new file mode 100644 index 000000000..ea2659c5b --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G061C8/UFQFPN48/mcu_definitions.h @@ -0,0 +1,309 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G061C8_UFQFPN48. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA13_CH17 +#define ADC1_PA14_CH18 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PB0_CH8 +#define ADC1_PB10_CH11 +#define ADC1_PB11_CH15 +#define ADC1_PB12_CH16 +#define ADC1_PB1_CH9 +#define ADC1_PB2_CH10 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN + +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (62) +#define DMA_NUM_OF_CHANNELS_FAMILY (62) +#define DMA_NUM_OF_MODULES (1) +#define DMA_NUM_OF_STREAMS (7) +#define DMA_NUM_OF_STREAMS_FAMILY (7) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PB9_AF6 +#define I2C2_SCL_PA11_AF6 +#define I2C2_SCL_PB10_AF6 +#define I2C2_SCL_PB13_AF6 +#define I2C2_SDA_PA12_AF6 +#define I2C2_SDA_PB11_AF6 +#define I2C2_SDA_PB14_AF6 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (2) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF6 +#define LPUART1_RX_PB10_AF1 +#define LPUART1_TX_PA2_AF6 +#define LPUART1_TX_PB11_AF1 +#define USART1_RX_PA10_AF1 +#define USART1_RX_PB7_AF0 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (2) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI2_MISO_PA3_AF0 +#define SPI2_MISO_PA9_AF4 +#define SPI2_MISO_PB14_AF0 +#define SPI2_MISO_PB2_AF1 +#define SPI2_MISO_PB6_AF4 +#define SPI2_MISO_PD3_AF1 +#define SPI2_MOSI_PA10_AF0 +#define SPI2_MOSI_PA4_AF1 +#define SPI2_MOSI_PB11_AF0 +#define SPI2_MOSI_PB15_AF0 +#define SPI2_MOSI_PB7_AF1 +#define SPI2_SCK_PA0_AF0 +#define SPI2_SCK_PB10_AF5 +#define SPI2_SCK_PB13_AF0 +#define SPI2_SCK_PB8_AF1 +#define SPI2_SCK_PD1_AF1 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF5 +#define LPTIM2_ETR_PA5_AF5 +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PB1_AF0 +#define TIM14_CH1_PF0_AF2 +#define TIM15_CH1N_PA1_AF5 +#define TIM15_CH1N_PB13_AF5 +#define TIM15_CH1N_PB15_AF4 +#define TIM15_CH1N_PF1_AF2 +#define TIM15_CH1_PA2_AF5 +#define TIM15_CH1_PB14_AF5 +#define TIM15_CH2_PA3_AF5 +#define TIM15_CH2_PB15_AF5 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB8_AF2 +#define TIM16_CH1_PD0_AF2 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PB9_AF2 +#define TIM17_CH1_PD1_AF2 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1N_PB13_AF2 +#define TIM1_CH1N_PD2_AF2 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2N_PB14_AF2 +#define TIM1_CH2N_PD3_AF2 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH3N_PB15_AF2 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_ETR_PA12_AF2 +#define TIM2_CH1_PA0_AF2 +#define TIM2_CH1_PA15_AF2 +#define TIM2_CH1_PA5_AF2 +#define TIM2_CH2_PA1_AF2 +#define TIM2_CH2_PB3_AF2 +#define TIM2_CH3_PA2_AF2 +#define TIM2_CH3_PB10_AF2 +#define TIM2_CH3_PC6_AF2 +#define TIM2_CH4_PA3_AF2 +#define TIM2_CH4_PB11_AF2 +#define TIM2_CH4_PC7_AF2 +#define TIM2_ETR_PA0_AF2 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH1_PC6_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH2_PC7_AF1 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH4_PB1_AF1 +#define TIM3_ETR_PD2_AF1 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_14 (4) +#define TIM_MODULE_15 (5) +#define TIM_MODULE_16 (6) +#define TIM_MODULE_17 (7) + +#define TIM_MODULE_COUNT (7) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +#define TIM1_BUS (1) +#define TIM15_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC6_CN +#define __PC7_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PF0_CN +#define __PF1_CN +#define __PF2_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_F_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G061F6/TSSOP20/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G061F6/TSSOP20/mcu_definitions.h new file mode 100644 index 000000000..5bc0d7b61 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G061F6/TSSOP20/mcu_definitions.h @@ -0,0 +1,260 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G061F6_TSSOP20. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA11_CH15 +#define ADC1_PA12_CH16 +#define ADC1_PA13_CH17 +#define ADC1_PA14_CH18 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PB0_CH8 +#define ADC1_PB1_CH9 +#define ADC1_PB2_CH10 +#define ADC1_PB7_CH11 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN + +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (62) +#define DMA_NUM_OF_CHANNELS_FAMILY (62) +#define DMA_NUM_OF_MODULES (1) +#define DMA_NUM_OF_STREAMS (7) +#define DMA_NUM_OF_STREAMS_FAMILY (7) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PB9_AF6 +#define I2C2_SCL_PA11_AF6 +#define I2C2_SDA_PA12_AF6 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (2) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF6 +#define LPUART1_TX_PA2_AF6 +#define USART1_RX_PA10_AF1 +#define USART1_RX_PB7_AF0 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (2) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI2_MISO_PA3_AF0 +#define SPI2_MISO_PA9_AF4 +#define SPI2_MISO_PB2_AF1 +#define SPI2_MISO_PB6_AF4 +#define SPI2_MOSI_PA10_AF0 +#define SPI2_MOSI_PA4_AF1 +#define SPI2_MOSI_PB7_AF1 +#define SPI2_SCK_PA0_AF0 +#define SPI2_SCK_PB8_AF1 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF5 +#define LPTIM2_ETR_PA5_AF5 +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PB1_AF0 +#define TIM15_CH1N_PA1_AF5 +#define TIM15_CH1_PA2_AF5 +#define TIM15_CH2_PA3_AF5 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB8_AF2 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PB9_AF2 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_ETR_PA12_AF2 +#define TIM2_CH1_PA0_AF2 +#define TIM2_CH1_PA15_AF2 +#define TIM2_CH1_PA5_AF2 +#define TIM2_CH2_PA1_AF2 +#define TIM2_CH2_PB3_AF2 +#define TIM2_CH3_PA2_AF2 +#define TIM2_CH4_PA3_AF2 +#define TIM2_ETR_PA0_AF2 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH4_PB1_AF1 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_14 (4) +#define TIM_MODULE_15 (5) +#define TIM_MODULE_16 (6) +#define TIM_MODULE_17 (7) + +#define TIM_MODULE_COUNT (7) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +#define TIM1_BUS (1) +#define TIM15_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC14_CN +#define __PC15_CN +#define __PF2_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN + +#define PORT_COUNT (4) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G061F8/TSSOP20/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G061F8/TSSOP20/mcu_definitions.h new file mode 100644 index 000000000..62d319237 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G061F8/TSSOP20/mcu_definitions.h @@ -0,0 +1,260 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G061F8_TSSOP20. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA11_CH15 +#define ADC1_PA12_CH16 +#define ADC1_PA13_CH17 +#define ADC1_PA14_CH18 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PB0_CH8 +#define ADC1_PB1_CH9 +#define ADC1_PB2_CH10 +#define ADC1_PB7_CH11 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN + +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (62) +#define DMA_NUM_OF_CHANNELS_FAMILY (62) +#define DMA_NUM_OF_MODULES (1) +#define DMA_NUM_OF_STREAMS (7) +#define DMA_NUM_OF_STREAMS_FAMILY (7) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PB9_AF6 +#define I2C2_SCL_PA11_AF6 +#define I2C2_SDA_PA12_AF6 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (2) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF6 +#define LPUART1_TX_PA2_AF6 +#define USART1_RX_PA10_AF1 +#define USART1_RX_PB7_AF0 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (2) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI2_MISO_PA3_AF0 +#define SPI2_MISO_PA9_AF4 +#define SPI2_MISO_PB2_AF1 +#define SPI2_MISO_PB6_AF4 +#define SPI2_MOSI_PA10_AF0 +#define SPI2_MOSI_PA4_AF1 +#define SPI2_MOSI_PB7_AF1 +#define SPI2_SCK_PA0_AF0 +#define SPI2_SCK_PB8_AF1 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF5 +#define LPTIM2_ETR_PA5_AF5 +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PB1_AF0 +#define TIM15_CH1N_PA1_AF5 +#define TIM15_CH1_PA2_AF5 +#define TIM15_CH2_PA3_AF5 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB8_AF2 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PB9_AF2 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_ETR_PA12_AF2 +#define TIM2_CH1_PA0_AF2 +#define TIM2_CH1_PA15_AF2 +#define TIM2_CH1_PA5_AF2 +#define TIM2_CH2_PA1_AF2 +#define TIM2_CH2_PB3_AF2 +#define TIM2_CH3_PA2_AF2 +#define TIM2_CH4_PA3_AF2 +#define TIM2_ETR_PA0_AF2 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH4_PB1_AF1 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_14 (4) +#define TIM_MODULE_15 (5) +#define TIM_MODULE_16 (6) +#define TIM_MODULE_17 (7) + +#define TIM_MODULE_COUNT (7) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +#define TIM1_BUS (1) +#define TIM15_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC14_CN +#define __PC15_CN +#define __PF2_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN + +#define PORT_COUNT (4) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G061F8/WLCSP20/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G061F8/WLCSP20/mcu_definitions.h new file mode 100644 index 000000000..4772d0665 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G061F8/WLCSP20/mcu_definitions.h @@ -0,0 +1,260 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G061F8_WLCSP20. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA11_CH15 +#define ADC1_PA12_CH16 +#define ADC1_PA13_CH17 +#define ADC1_PA14_CH18 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PB0_CH8 +#define ADC1_PB1_CH9 +#define ADC1_PB2_CH10 +#define ADC1_PB7_CH11 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN + +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (62) +#define DMA_NUM_OF_CHANNELS_FAMILY (62) +#define DMA_NUM_OF_MODULES (1) +#define DMA_NUM_OF_STREAMS (7) +#define DMA_NUM_OF_STREAMS_FAMILY (7) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PB9_AF6 +#define I2C2_SCL_PA11_AF6 +#define I2C2_SDA_PA12_AF6 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (2) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF6 +#define LPUART1_TX_PA2_AF6 +#define USART1_RX_PA10_AF1 +#define USART1_RX_PB7_AF0 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (2) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI2_MISO_PA3_AF0 +#define SPI2_MISO_PA9_AF4 +#define SPI2_MISO_PB2_AF1 +#define SPI2_MISO_PB6_AF4 +#define SPI2_MOSI_PA10_AF0 +#define SPI2_MOSI_PA4_AF1 +#define SPI2_MOSI_PB7_AF1 +#define SPI2_SCK_PA0_AF0 +#define SPI2_SCK_PB8_AF1 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF5 +#define LPTIM2_ETR_PA5_AF5 +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PB1_AF0 +#define TIM15_CH1N_PA1_AF5 +#define TIM15_CH1_PA2_AF5 +#define TIM15_CH2_PA3_AF5 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB8_AF2 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PB9_AF2 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_ETR_PA12_AF2 +#define TIM2_CH1_PA0_AF2 +#define TIM2_CH1_PA15_AF2 +#define TIM2_CH1_PA5_AF2 +#define TIM2_CH2_PA1_AF2 +#define TIM2_CH2_PB3_AF2 +#define TIM2_CH3_PA2_AF2 +#define TIM2_CH4_PA3_AF2 +#define TIM2_ETR_PA0_AF2 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH4_PB1_AF1 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_14 (4) +#define TIM_MODULE_15 (5) +#define TIM_MODULE_16 (6) +#define TIM_MODULE_17 (7) + +#define TIM_MODULE_COUNT (7) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +#define TIM1_BUS (1) +#define TIM15_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC14_CN +#define __PC15_CN +#define __PF2_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN + +#define PORT_COUNT (4) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G061G6/UFQFPN28/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G061G6/UFQFPN28/mcu_definitions.h new file mode 100644 index 000000000..7b8a123d2 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G061G6/UFQFPN28/mcu_definitions.h @@ -0,0 +1,257 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G061G6_UFQFPN28. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA11_CH15 +#define ADC1_PA12_CH16 +#define ADC1_PA13_CH17 +#define ADC1_PA14_CH18 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PB0_CH8 +#define ADC1_PB1_CH9 +#define ADC1_PB7_CH11 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN + +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (62) +#define DMA_NUM_OF_CHANNELS_FAMILY (62) +#define DMA_NUM_OF_MODULES (1) +#define DMA_NUM_OF_STREAMS (7) +#define DMA_NUM_OF_STREAMS_FAMILY (7) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C2_SCL_PA11_AF6 +#define I2C2_SDA_PA12_AF6 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (2) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF6 +#define LPUART1_TX_PA2_AF6 +#define USART1_RX_PA10_AF1 +#define USART1_RX_PB7_AF0 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (2) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI2_MISO_PA3_AF0 +#define SPI2_MISO_PA9_AF4 +#define SPI2_MISO_PB6_AF4 +#define SPI2_MOSI_PA10_AF0 +#define SPI2_MOSI_PA4_AF1 +#define SPI2_MOSI_PB7_AF1 +#define SPI2_SCK_PA0_AF0 +#define SPI2_SCK_PB8_AF1 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF5 +#define LPTIM2_ETR_PA5_AF5 +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PB1_AF0 +#define TIM15_CH1N_PA1_AF5 +#define TIM15_CH1_PA2_AF5 +#define TIM15_CH2_PA3_AF5 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB8_AF2 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_ETR_PA12_AF2 +#define TIM2_CH1_PA0_AF2 +#define TIM2_CH1_PA15_AF2 +#define TIM2_CH1_PA5_AF2 +#define TIM2_CH2_PA1_AF2 +#define TIM2_CH2_PB3_AF2 +#define TIM2_CH3_PA2_AF2 +#define TIM2_CH3_PC6_AF2 +#define TIM2_CH4_PA3_AF2 +#define TIM2_ETR_PA0_AF2 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH1_PC6_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH4_PB1_AF1 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_14 (4) +#define TIM_MODULE_15 (5) +#define TIM_MODULE_16 (6) +#define TIM_MODULE_17 (7) + +#define TIM_MODULE_COUNT (7) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +#define TIM1_BUS (1) +#define TIM15_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PC14_CN +#define __PC15_CN +#define __PC6_CN +#define __PF2_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN + +#define PORT_COUNT (4) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G061G8/UFQFPN28/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G061G8/UFQFPN28/mcu_definitions.h new file mode 100644 index 000000000..ff4486c90 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G061G8/UFQFPN28/mcu_definitions.h @@ -0,0 +1,257 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G061G8_UFQFPN28. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA11_CH15 +#define ADC1_PA12_CH16 +#define ADC1_PA13_CH17 +#define ADC1_PA14_CH18 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PB0_CH8 +#define ADC1_PB1_CH9 +#define ADC1_PB7_CH11 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN + +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (62) +#define DMA_NUM_OF_CHANNELS_FAMILY (62) +#define DMA_NUM_OF_MODULES (1) +#define DMA_NUM_OF_STREAMS (7) +#define DMA_NUM_OF_STREAMS_FAMILY (7) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C2_SCL_PA11_AF6 +#define I2C2_SDA_PA12_AF6 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (2) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF6 +#define LPUART1_TX_PA2_AF6 +#define USART1_RX_PA10_AF1 +#define USART1_RX_PB7_AF0 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (2) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI2_MISO_PA3_AF0 +#define SPI2_MISO_PA9_AF4 +#define SPI2_MISO_PB6_AF4 +#define SPI2_MOSI_PA10_AF0 +#define SPI2_MOSI_PA4_AF1 +#define SPI2_MOSI_PB7_AF1 +#define SPI2_SCK_PA0_AF0 +#define SPI2_SCK_PB8_AF1 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF5 +#define LPTIM2_ETR_PA5_AF5 +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PB1_AF0 +#define TIM15_CH1N_PA1_AF5 +#define TIM15_CH1_PA2_AF5 +#define TIM15_CH2_PA3_AF5 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB8_AF2 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_ETR_PA12_AF2 +#define TIM2_CH1_PA0_AF2 +#define TIM2_CH1_PA15_AF2 +#define TIM2_CH1_PA5_AF2 +#define TIM2_CH2_PA1_AF2 +#define TIM2_CH2_PB3_AF2 +#define TIM2_CH3_PA2_AF2 +#define TIM2_CH3_PC6_AF2 +#define TIM2_CH4_PA3_AF2 +#define TIM2_ETR_PA0_AF2 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH1_PC6_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH4_PB1_AF1 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_14 (4) +#define TIM_MODULE_15 (5) +#define TIM_MODULE_16 (6) +#define TIM_MODULE_17 (7) + +#define TIM_MODULE_COUNT (7) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +#define TIM1_BUS (1) +#define TIM15_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PC14_CN +#define __PC15_CN +#define __PC6_CN +#define __PF2_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN + +#define PORT_COUNT (4) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G061K6/LQFP32/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G061K6/LQFP32/mcu_definitions.h new file mode 100644 index 000000000..9936e9a09 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G061K6/LQFP32/mcu_definitions.h @@ -0,0 +1,263 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G061K6_LQFP32. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA11_CH15 +#define ADC1_PA12_CH16 +#define ADC1_PA13_CH17 +#define ADC1_PA14_CH18 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PB0_CH8 +#define ADC1_PB1_CH9 +#define ADC1_PB2_CH10 +#define ADC1_PB7_CH11 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN + +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (62) +#define DMA_NUM_OF_CHANNELS_FAMILY (62) +#define DMA_NUM_OF_MODULES (1) +#define DMA_NUM_OF_STREAMS (7) +#define DMA_NUM_OF_STREAMS_FAMILY (7) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PB9_AF6 +#define I2C2_SCL_PA11_AF6 +#define I2C2_SDA_PA12_AF6 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (2) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF6 +#define LPUART1_TX_PA2_AF6 +#define USART1_RX_PA10_AF1 +#define USART1_RX_PB7_AF0 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (2) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI2_MISO_PA3_AF0 +#define SPI2_MISO_PA9_AF4 +#define SPI2_MISO_PB2_AF1 +#define SPI2_MISO_PB6_AF4 +#define SPI2_MOSI_PA10_AF0 +#define SPI2_MOSI_PA4_AF1 +#define SPI2_MOSI_PB7_AF1 +#define SPI2_SCK_PA0_AF0 +#define SPI2_SCK_PB8_AF1 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF5 +#define LPTIM2_ETR_PA5_AF5 +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PB1_AF0 +#define TIM15_CH1N_PA1_AF5 +#define TIM15_CH1_PA2_AF5 +#define TIM15_CH2_PA3_AF5 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB8_AF2 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PB9_AF2 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_ETR_PA12_AF2 +#define TIM2_CH1_PA0_AF2 +#define TIM2_CH1_PA15_AF2 +#define TIM2_CH1_PA5_AF2 +#define TIM2_CH2_PA1_AF2 +#define TIM2_CH2_PB3_AF2 +#define TIM2_CH3_PA2_AF2 +#define TIM2_CH3_PC6_AF2 +#define TIM2_CH4_PA3_AF2 +#define TIM2_ETR_PA0_AF2 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH1_PC6_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH4_PB1_AF1 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_14 (4) +#define TIM_MODULE_15 (5) +#define TIM_MODULE_16 (6) +#define TIM_MODULE_17 (7) + +#define TIM_MODULE_COUNT (7) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +#define TIM1_BUS (1) +#define TIM15_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC14_CN +#define __PC15_CN +#define __PC6_CN +#define __PF2_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN + +#define PORT_COUNT (4) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G061K6/UFQFPN32/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G061K6/UFQFPN32/mcu_definitions.h new file mode 100644 index 000000000..40a85088d --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G061K6/UFQFPN32/mcu_definitions.h @@ -0,0 +1,263 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G061K6_UFQFPN32. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA11_CH15 +#define ADC1_PA12_CH16 +#define ADC1_PA13_CH17 +#define ADC1_PA14_CH18 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PB0_CH8 +#define ADC1_PB1_CH9 +#define ADC1_PB2_CH10 +#define ADC1_PB7_CH11 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN + +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (62) +#define DMA_NUM_OF_CHANNELS_FAMILY (62) +#define DMA_NUM_OF_MODULES (1) +#define DMA_NUM_OF_STREAMS (7) +#define DMA_NUM_OF_STREAMS_FAMILY (7) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PB9_AF6 +#define I2C2_SCL_PA11_AF6 +#define I2C2_SDA_PA12_AF6 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (2) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF6 +#define LPUART1_TX_PA2_AF6 +#define USART1_RX_PA10_AF1 +#define USART1_RX_PB7_AF0 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (2) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI2_MISO_PA3_AF0 +#define SPI2_MISO_PA9_AF4 +#define SPI2_MISO_PB2_AF1 +#define SPI2_MISO_PB6_AF4 +#define SPI2_MOSI_PA10_AF0 +#define SPI2_MOSI_PA4_AF1 +#define SPI2_MOSI_PB7_AF1 +#define SPI2_SCK_PA0_AF0 +#define SPI2_SCK_PB8_AF1 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF5 +#define LPTIM2_ETR_PA5_AF5 +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PB1_AF0 +#define TIM15_CH1N_PA1_AF5 +#define TIM15_CH1_PA2_AF5 +#define TIM15_CH2_PA3_AF5 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB8_AF2 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PB9_AF2 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_ETR_PA12_AF2 +#define TIM2_CH1_PA0_AF2 +#define TIM2_CH1_PA15_AF2 +#define TIM2_CH1_PA5_AF2 +#define TIM2_CH2_PA1_AF2 +#define TIM2_CH2_PB3_AF2 +#define TIM2_CH3_PA2_AF2 +#define TIM2_CH3_PC6_AF2 +#define TIM2_CH4_PA3_AF2 +#define TIM2_ETR_PA0_AF2 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH1_PC6_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH4_PB1_AF1 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_14 (4) +#define TIM_MODULE_15 (5) +#define TIM_MODULE_16 (6) +#define TIM_MODULE_17 (7) + +#define TIM_MODULE_COUNT (7) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +#define TIM1_BUS (1) +#define TIM15_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC14_CN +#define __PC15_CN +#define __PC6_CN +#define __PF2_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN + +#define PORT_COUNT (4) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G061K8/LQFP32/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G061K8/LQFP32/mcu_definitions.h new file mode 100644 index 000000000..9e6a909ea --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G061K8/LQFP32/mcu_definitions.h @@ -0,0 +1,263 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G061K8_LQFP32. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA11_CH15 +#define ADC1_PA12_CH16 +#define ADC1_PA13_CH17 +#define ADC1_PA14_CH18 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PB0_CH8 +#define ADC1_PB1_CH9 +#define ADC1_PB2_CH10 +#define ADC1_PB7_CH11 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN + +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (62) +#define DMA_NUM_OF_CHANNELS_FAMILY (62) +#define DMA_NUM_OF_MODULES (1) +#define DMA_NUM_OF_STREAMS (7) +#define DMA_NUM_OF_STREAMS_FAMILY (7) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PB9_AF6 +#define I2C2_SCL_PA11_AF6 +#define I2C2_SDA_PA12_AF6 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (2) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF6 +#define LPUART1_TX_PA2_AF6 +#define USART1_RX_PA10_AF1 +#define USART1_RX_PB7_AF0 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (2) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI2_MISO_PA3_AF0 +#define SPI2_MISO_PA9_AF4 +#define SPI2_MISO_PB2_AF1 +#define SPI2_MISO_PB6_AF4 +#define SPI2_MOSI_PA10_AF0 +#define SPI2_MOSI_PA4_AF1 +#define SPI2_MOSI_PB7_AF1 +#define SPI2_SCK_PA0_AF0 +#define SPI2_SCK_PB8_AF1 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF5 +#define LPTIM2_ETR_PA5_AF5 +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PB1_AF0 +#define TIM15_CH1N_PA1_AF5 +#define TIM15_CH1_PA2_AF5 +#define TIM15_CH2_PA3_AF5 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB8_AF2 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PB9_AF2 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_ETR_PA12_AF2 +#define TIM2_CH1_PA0_AF2 +#define TIM2_CH1_PA15_AF2 +#define TIM2_CH1_PA5_AF2 +#define TIM2_CH2_PA1_AF2 +#define TIM2_CH2_PB3_AF2 +#define TIM2_CH3_PA2_AF2 +#define TIM2_CH3_PC6_AF2 +#define TIM2_CH4_PA3_AF2 +#define TIM2_ETR_PA0_AF2 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH1_PC6_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH4_PB1_AF1 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_14 (4) +#define TIM_MODULE_15 (5) +#define TIM_MODULE_16 (6) +#define TIM_MODULE_17 (7) + +#define TIM_MODULE_COUNT (7) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +#define TIM1_BUS (1) +#define TIM15_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC14_CN +#define __PC15_CN +#define __PC6_CN +#define __PF2_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN + +#define PORT_COUNT (4) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G061K8/UFQFPN32/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G061K8/UFQFPN32/mcu_definitions.h new file mode 100644 index 000000000..d539554bb --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G061K8/UFQFPN32/mcu_definitions.h @@ -0,0 +1,263 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G061K8_UFQFPN32. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA11_CH15 +#define ADC1_PA12_CH16 +#define ADC1_PA13_CH17 +#define ADC1_PA14_CH18 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PB0_CH8 +#define ADC1_PB1_CH9 +#define ADC1_PB2_CH10 +#define ADC1_PB7_CH11 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN + +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (62) +#define DMA_NUM_OF_CHANNELS_FAMILY (62) +#define DMA_NUM_OF_MODULES (1) +#define DMA_NUM_OF_STREAMS (7) +#define DMA_NUM_OF_STREAMS_FAMILY (7) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PB9_AF6 +#define I2C2_SCL_PA11_AF6 +#define I2C2_SDA_PA12_AF6 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (2) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF6 +#define LPUART1_TX_PA2_AF6 +#define USART1_RX_PA10_AF1 +#define USART1_RX_PB7_AF0 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (2) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI2_MISO_PA3_AF0 +#define SPI2_MISO_PA9_AF4 +#define SPI2_MISO_PB2_AF1 +#define SPI2_MISO_PB6_AF4 +#define SPI2_MOSI_PA10_AF0 +#define SPI2_MOSI_PA4_AF1 +#define SPI2_MOSI_PB7_AF1 +#define SPI2_SCK_PA0_AF0 +#define SPI2_SCK_PB8_AF1 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF5 +#define LPTIM2_ETR_PA5_AF5 +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PB1_AF0 +#define TIM15_CH1N_PA1_AF5 +#define TIM15_CH1_PA2_AF5 +#define TIM15_CH2_PA3_AF5 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB8_AF2 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PB9_AF2 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_ETR_PA12_AF2 +#define TIM2_CH1_PA0_AF2 +#define TIM2_CH1_PA15_AF2 +#define TIM2_CH1_PA5_AF2 +#define TIM2_CH2_PA1_AF2 +#define TIM2_CH2_PB3_AF2 +#define TIM2_CH3_PA2_AF2 +#define TIM2_CH3_PC6_AF2 +#define TIM2_CH4_PA3_AF2 +#define TIM2_ETR_PA0_AF2 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH1_PC6_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH4_PB1_AF1 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_14 (4) +#define TIM_MODULE_15 (5) +#define TIM_MODULE_16 (6) +#define TIM_MODULE_17 (7) + +#define TIM_MODULE_COUNT (7) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +#define TIM1_BUS (1) +#define TIM15_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC14_CN +#define __PC15_CN +#define __PC6_CN +#define __PF2_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN + +#define PORT_COUNT (4) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1CB/LQFP48/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1CB/LQFP48/mcu_definitions.h new file mode 100644 index 000000000..e70ebd4e3 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1CB/LQFP48/mcu_definitions.h @@ -0,0 +1,385 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G0B1CB_LQFP48. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PB0_CH8 +#define ADC1_PB10_CH11 +#define ADC1_PB11_CH15 +#define ADC1_PB12_CH16 +#define ADC1_PB1_CH9 +#define ADC1_PB2_CH10 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF3 +#define FDCAN1_RX_PB8_AF3 +#define FDCAN1_RX_PD0_AF3 +#define FDCAN1_TX_PA12_AF3 +#define FDCAN1_TX_PB9_AF3 +#define FDCAN1_TX_PD1_AF3 +#define FDCAN2_RX_PB0_AF3 +#define FDCAN2_RX_PB12_AF3 +#define FDCAN2_RX_PB5_AF3 +#define FDCAN2_TX_PB13_AF3 +#define FDCAN2_TX_PB1_AF3 +#define FDCAN2_TX_PB6_AF3 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) + +#define CAN_MODULE_COUNT (2) + +#define HAL_LL_FDCAN1_GPIO_AF3 (3) +#define HAL_LL_FDCAN2_GPIO_AF3 (3) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (78) +#define DMA_NUM_OF_CHANNELS_FAMILY (78) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (12) +#define DMA_NUM_OF_STREAMS_FAMILY (12) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PB9_AF6 +#define I2C2_SCL_PA11_AF6 +#define I2C2_SCL_PA7_AF8 +#define I2C2_SCL_PA9_AF8 +#define I2C2_SCL_PB10_AF6 +#define I2C2_SCL_PB13_AF6 +#define I2C2_SCL_PB3_AF8 +#define I2C2_SDA_PA10_AF8 +#define I2C2_SDA_PA12_AF6 +#define I2C2_SDA_PA6_AF8 +#define I2C2_SDA_PB11_AF6 +#define I2C2_SDA_PB14_AF6 +#define I2C2_SDA_PB4_AF8 +#define I2C3_SCL_PA7_AF9 +#define I2C3_SCL_PB3_AF6 +#define I2C3_SDA_PA6_AF9 +#define I2C3_SDA_PB4_AF6 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF6 +#define LPUART1_RX_PB10_AF1 +#define LPUART1_TX_PA2_AF6 +#define LPUART1_TX_PB11_AF1 +#define LPUART2_RX_PA13_AF10 +#define LPUART2_RX_PB7_AF10 +#define LPUART2_RX_PC7_AF3 +#define LPUART2_TX_PA14_AF10 +#define LPUART2_TX_PB6_AF10 +#define LPUART2_TX_PC6_AF3 +#define LPUART2_TX_PF2_AF1 +#define USART1_RX_PA10_AF1 +#define USART1_RX_PB7_AF0 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 +#define USART3_RX_PB0_AF4 +#define USART3_RX_PB11_AF4 +#define USART3_RX_PB9_AF4 +#define USART3_TX_PA5_AF4 +#define USART3_TX_PB10_AF4 +#define USART3_TX_PB2_AF4 +#define USART3_TX_PB8_AF4 +#define USART4_RX_PA1_AF4 +#define USART4_TX_PA0_AF4 +#define USART5_RX_PB1_AF8 +#define USART5_RX_PB4_AF3 +#define USART5_RX_PD2_AF3 +#define USART5_TX_PB0_AF8 +#define USART5_TX_PB3_AF3 +#define USART5_TX_PD3_AF3 +#define USART6_RX_PA5_AF3 +#define USART6_RX_PB9_AF8 +#define USART6_TX_PA4_AF3 +#define USART6_TX_PB8_AF8 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) +#define UART_MODULE_6 (6) + +#define UART_MODULE_COUNT (6) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI2_MISO_PA3_AF0 +#define SPI2_MISO_PA9_AF4 +#define SPI2_MISO_PB14_AF0 +#define SPI2_MISO_PB2_AF1 +#define SPI2_MISO_PB6_AF4 +#define SPI2_MISO_PD3_AF1 +#define SPI2_MOSI_PA10_AF0 +#define SPI2_MOSI_PA4_AF1 +#define SPI2_MOSI_PB11_AF0 +#define SPI2_MOSI_PB15_AF0 +#define SPI2_MOSI_PB7_AF1 +#define SPI2_SCK_PA0_AF0 +#define SPI2_SCK_PB10_AF5 +#define SPI2_SCK_PB13_AF0 +#define SPI2_SCK_PB8_AF1 +#define SPI2_SCK_PD1_AF1 +#define SPI3_MISO_PB4_AF9 +#define SPI3_MOSI_PB5_AF9 +#define SPI3_SCK_PB3_AF9 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF5 +#define LPTIM2_ETR_PA5_AF5 +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PB1_AF0 +#define TIM14_CH1_PF0_AF2 +#define TIM15_CH1N_PA1_AF5 +#define TIM15_CH1N_PB13_AF5 +#define TIM15_CH1N_PB15_AF4 +#define TIM15_CH1N_PF1_AF2 +#define TIM15_CH1_PA2_AF5 +#define TIM15_CH1_PB14_AF5 +#define TIM15_CH2_PA3_AF5 +#define TIM15_CH2_PB15_AF5 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB8_AF2 +#define TIM16_CH1_PD0_AF2 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PB9_AF2 +#define TIM17_CH1_PD1_AF2 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1N_PB13_AF2 +#define TIM1_CH1N_PD2_AF2 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2N_PB14_AF2 +#define TIM1_CH2N_PD3_AF2 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH3N_PB15_AF2 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_ETR_PA12_AF2 +#define TIM2_CH1_PA0_AF2 +#define TIM2_CH1_PA15_AF2 +#define TIM2_CH1_PA5_AF2 +#define TIM2_CH2_PA1_AF2 +#define TIM2_CH2_PB3_AF2 +#define TIM2_CH3_PA2_AF2 +#define TIM2_CH3_PB10_AF2 +#define TIM2_CH3_PC6_AF2 +#define TIM2_CH4_PA3_AF2 +#define TIM2_CH4_PB11_AF2 +#define TIM2_CH4_PC7_AF2 +#define TIM2_ETR_PA0_AF2 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH1_PC6_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH2_PC7_AF1 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH4_PB1_AF1 +#define TIM3_ETR_PD2_AF1 +#define TIM4_CH1_PB6_AF9 +#define TIM4_CH2_PB7_AF9 +#define TIM4_CH3_PB8_AF9 +#define TIM4_CH4_PB9_AF9 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_14 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +#define TIM1_BUS (1) +#define TIM4_BUS (1) +#define TIM15_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC6_CN +#define __PC7_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PF0_CN +#define __PF1_CN +#define __PF2_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_F_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +#define UART3_IVT (29) +#define UART3_NVIC (45) +#define UART4_IVT (29) +#define UART4_NVIC (45) +#define UART5_IVT (29) +#define UART5_NVIC (45) +#define UART6_IVT (29) +#define UART6_NVIC (45) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1CB/UFQFPN48/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1CB/UFQFPN48/mcu_definitions.h new file mode 100644 index 000000000..96e40937a --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1CB/UFQFPN48/mcu_definitions.h @@ -0,0 +1,385 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G0B1CB_UFQFPN48. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PB0_CH8 +#define ADC1_PB10_CH11 +#define ADC1_PB11_CH15 +#define ADC1_PB12_CH16 +#define ADC1_PB1_CH9 +#define ADC1_PB2_CH10 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF3 +#define FDCAN1_RX_PB8_AF3 +#define FDCAN1_RX_PD0_AF3 +#define FDCAN1_TX_PA12_AF3 +#define FDCAN1_TX_PB9_AF3 +#define FDCAN1_TX_PD1_AF3 +#define FDCAN2_RX_PB0_AF3 +#define FDCAN2_RX_PB12_AF3 +#define FDCAN2_RX_PB5_AF3 +#define FDCAN2_TX_PB13_AF3 +#define FDCAN2_TX_PB1_AF3 +#define FDCAN2_TX_PB6_AF3 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) + +#define CAN_MODULE_COUNT (2) + +#define HAL_LL_FDCAN1_GPIO_AF3 (3) +#define HAL_LL_FDCAN2_GPIO_AF3 (3) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (78) +#define DMA_NUM_OF_CHANNELS_FAMILY (78) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (12) +#define DMA_NUM_OF_STREAMS_FAMILY (12) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PB9_AF6 +#define I2C2_SCL_PA11_AF6 +#define I2C2_SCL_PA7_AF8 +#define I2C2_SCL_PA9_AF8 +#define I2C2_SCL_PB10_AF6 +#define I2C2_SCL_PB13_AF6 +#define I2C2_SCL_PB3_AF8 +#define I2C2_SDA_PA10_AF8 +#define I2C2_SDA_PA12_AF6 +#define I2C2_SDA_PA6_AF8 +#define I2C2_SDA_PB11_AF6 +#define I2C2_SDA_PB14_AF6 +#define I2C2_SDA_PB4_AF8 +#define I2C3_SCL_PA7_AF9 +#define I2C3_SCL_PB3_AF6 +#define I2C3_SDA_PA6_AF9 +#define I2C3_SDA_PB4_AF6 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF6 +#define LPUART1_RX_PB10_AF1 +#define LPUART1_TX_PA2_AF6 +#define LPUART1_TX_PB11_AF1 +#define LPUART2_RX_PA13_AF10 +#define LPUART2_RX_PB7_AF10 +#define LPUART2_RX_PC7_AF3 +#define LPUART2_TX_PA14_AF10 +#define LPUART2_TX_PB6_AF10 +#define LPUART2_TX_PC6_AF3 +#define LPUART2_TX_PF2_AF1 +#define USART1_RX_PA10_AF1 +#define USART1_RX_PB7_AF0 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 +#define USART3_RX_PB0_AF4 +#define USART3_RX_PB11_AF4 +#define USART3_RX_PB9_AF4 +#define USART3_TX_PA5_AF4 +#define USART3_TX_PB10_AF4 +#define USART3_TX_PB2_AF4 +#define USART3_TX_PB8_AF4 +#define USART4_RX_PA1_AF4 +#define USART4_TX_PA0_AF4 +#define USART5_RX_PB1_AF8 +#define USART5_RX_PB4_AF3 +#define USART5_RX_PD2_AF3 +#define USART5_TX_PB0_AF8 +#define USART5_TX_PB3_AF3 +#define USART5_TX_PD3_AF3 +#define USART6_RX_PA5_AF3 +#define USART6_RX_PB9_AF8 +#define USART6_TX_PA4_AF3 +#define USART6_TX_PB8_AF8 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) +#define UART_MODULE_6 (6) + +#define UART_MODULE_COUNT (6) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI2_MISO_PA3_AF0 +#define SPI2_MISO_PA9_AF4 +#define SPI2_MISO_PB14_AF0 +#define SPI2_MISO_PB2_AF1 +#define SPI2_MISO_PB6_AF4 +#define SPI2_MISO_PD3_AF1 +#define SPI2_MOSI_PA10_AF0 +#define SPI2_MOSI_PA4_AF1 +#define SPI2_MOSI_PB11_AF0 +#define SPI2_MOSI_PB15_AF0 +#define SPI2_MOSI_PB7_AF1 +#define SPI2_SCK_PA0_AF0 +#define SPI2_SCK_PB10_AF5 +#define SPI2_SCK_PB13_AF0 +#define SPI2_SCK_PB8_AF1 +#define SPI2_SCK_PD1_AF1 +#define SPI3_MISO_PB4_AF9 +#define SPI3_MOSI_PB5_AF9 +#define SPI3_SCK_PB3_AF9 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF5 +#define LPTIM2_ETR_PA5_AF5 +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PB1_AF0 +#define TIM14_CH1_PF0_AF2 +#define TIM15_CH1N_PA1_AF5 +#define TIM15_CH1N_PB13_AF5 +#define TIM15_CH1N_PB15_AF4 +#define TIM15_CH1N_PF1_AF2 +#define TIM15_CH1_PA2_AF5 +#define TIM15_CH1_PB14_AF5 +#define TIM15_CH2_PA3_AF5 +#define TIM15_CH2_PB15_AF5 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB8_AF2 +#define TIM16_CH1_PD0_AF2 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PB9_AF2 +#define TIM17_CH1_PD1_AF2 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1N_PB13_AF2 +#define TIM1_CH1N_PD2_AF2 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2N_PB14_AF2 +#define TIM1_CH2N_PD3_AF2 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH3N_PB15_AF2 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_ETR_PA12_AF2 +#define TIM2_CH1_PA0_AF2 +#define TIM2_CH1_PA15_AF2 +#define TIM2_CH1_PA5_AF2 +#define TIM2_CH2_PA1_AF2 +#define TIM2_CH2_PB3_AF2 +#define TIM2_CH3_PA2_AF2 +#define TIM2_CH3_PB10_AF2 +#define TIM2_CH3_PC6_AF2 +#define TIM2_CH4_PA3_AF2 +#define TIM2_CH4_PB11_AF2 +#define TIM2_CH4_PC7_AF2 +#define TIM2_ETR_PA0_AF2 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH1_PC6_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH2_PC7_AF1 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH4_PB1_AF1 +#define TIM3_ETR_PD2_AF1 +#define TIM4_CH1_PB6_AF9 +#define TIM4_CH2_PB7_AF9 +#define TIM4_CH3_PB8_AF9 +#define TIM4_CH4_PB9_AF9 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_14 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +#define TIM1_BUS (1) +#define TIM4_BUS (1) +#define TIM15_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC6_CN +#define __PC7_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PF0_CN +#define __PF1_CN +#define __PF2_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_F_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +#define UART3_IVT (29) +#define UART3_NVIC (45) +#define UART4_IVT (29) +#define UART4_NVIC (45) +#define UART5_IVT (29) +#define UART5_NVIC (45) +#define UART6_IVT (29) +#define UART6_NVIC (45) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1CC/LQFP48/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1CC/LQFP48/mcu_definitions.h new file mode 100644 index 000000000..8c654ff36 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1CC/LQFP48/mcu_definitions.h @@ -0,0 +1,385 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G0B1CC_LQFP48. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PB0_CH8 +#define ADC1_PB10_CH11 +#define ADC1_PB11_CH15 +#define ADC1_PB12_CH16 +#define ADC1_PB1_CH9 +#define ADC1_PB2_CH10 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF3 +#define FDCAN1_RX_PB8_AF3 +#define FDCAN1_RX_PD0_AF3 +#define FDCAN1_TX_PA12_AF3 +#define FDCAN1_TX_PB9_AF3 +#define FDCAN1_TX_PD1_AF3 +#define FDCAN2_RX_PB0_AF3 +#define FDCAN2_RX_PB12_AF3 +#define FDCAN2_RX_PB5_AF3 +#define FDCAN2_TX_PB13_AF3 +#define FDCAN2_TX_PB1_AF3 +#define FDCAN2_TX_PB6_AF3 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) + +#define CAN_MODULE_COUNT (2) + +#define HAL_LL_FDCAN1_GPIO_AF3 (3) +#define HAL_LL_FDCAN2_GPIO_AF3 (3) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (78) +#define DMA_NUM_OF_CHANNELS_FAMILY (78) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (12) +#define DMA_NUM_OF_STREAMS_FAMILY (12) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PB9_AF6 +#define I2C2_SCL_PA11_AF6 +#define I2C2_SCL_PA7_AF8 +#define I2C2_SCL_PA9_AF8 +#define I2C2_SCL_PB10_AF6 +#define I2C2_SCL_PB13_AF6 +#define I2C2_SCL_PB3_AF8 +#define I2C2_SDA_PA10_AF8 +#define I2C2_SDA_PA12_AF6 +#define I2C2_SDA_PA6_AF8 +#define I2C2_SDA_PB11_AF6 +#define I2C2_SDA_PB14_AF6 +#define I2C2_SDA_PB4_AF8 +#define I2C3_SCL_PA7_AF9 +#define I2C3_SCL_PB3_AF6 +#define I2C3_SDA_PA6_AF9 +#define I2C3_SDA_PB4_AF6 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF6 +#define LPUART1_RX_PB10_AF1 +#define LPUART1_TX_PA2_AF6 +#define LPUART1_TX_PB11_AF1 +#define LPUART2_RX_PA13_AF10 +#define LPUART2_RX_PB7_AF10 +#define LPUART2_RX_PC7_AF3 +#define LPUART2_TX_PA14_AF10 +#define LPUART2_TX_PB6_AF10 +#define LPUART2_TX_PC6_AF3 +#define LPUART2_TX_PF2_AF1 +#define USART1_RX_PA10_AF1 +#define USART1_RX_PB7_AF0 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 +#define USART3_RX_PB0_AF4 +#define USART3_RX_PB11_AF4 +#define USART3_RX_PB9_AF4 +#define USART3_TX_PA5_AF4 +#define USART3_TX_PB10_AF4 +#define USART3_TX_PB2_AF4 +#define USART3_TX_PB8_AF4 +#define USART4_RX_PA1_AF4 +#define USART4_TX_PA0_AF4 +#define USART5_RX_PB1_AF8 +#define USART5_RX_PB4_AF3 +#define USART5_RX_PD2_AF3 +#define USART5_TX_PB0_AF8 +#define USART5_TX_PB3_AF3 +#define USART5_TX_PD3_AF3 +#define USART6_RX_PA5_AF3 +#define USART6_RX_PB9_AF8 +#define USART6_TX_PA4_AF3 +#define USART6_TX_PB8_AF8 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) +#define UART_MODULE_6 (6) + +#define UART_MODULE_COUNT (6) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI2_MISO_PA3_AF0 +#define SPI2_MISO_PA9_AF4 +#define SPI2_MISO_PB14_AF0 +#define SPI2_MISO_PB2_AF1 +#define SPI2_MISO_PB6_AF4 +#define SPI2_MISO_PD3_AF1 +#define SPI2_MOSI_PA10_AF0 +#define SPI2_MOSI_PA4_AF1 +#define SPI2_MOSI_PB11_AF0 +#define SPI2_MOSI_PB15_AF0 +#define SPI2_MOSI_PB7_AF1 +#define SPI2_SCK_PA0_AF0 +#define SPI2_SCK_PB10_AF5 +#define SPI2_SCK_PB13_AF0 +#define SPI2_SCK_PB8_AF1 +#define SPI2_SCK_PD1_AF1 +#define SPI3_MISO_PB4_AF9 +#define SPI3_MOSI_PB5_AF9 +#define SPI3_SCK_PB3_AF9 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF5 +#define LPTIM2_ETR_PA5_AF5 +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PB1_AF0 +#define TIM14_CH1_PF0_AF2 +#define TIM15_CH1N_PA1_AF5 +#define TIM15_CH1N_PB13_AF5 +#define TIM15_CH1N_PB15_AF4 +#define TIM15_CH1N_PF1_AF2 +#define TIM15_CH1_PA2_AF5 +#define TIM15_CH1_PB14_AF5 +#define TIM15_CH2_PA3_AF5 +#define TIM15_CH2_PB15_AF5 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB8_AF2 +#define TIM16_CH1_PD0_AF2 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PB9_AF2 +#define TIM17_CH1_PD1_AF2 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1N_PB13_AF2 +#define TIM1_CH1N_PD2_AF2 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2N_PB14_AF2 +#define TIM1_CH2N_PD3_AF2 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH3N_PB15_AF2 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_ETR_PA12_AF2 +#define TIM2_CH1_PA0_AF2 +#define TIM2_CH1_PA15_AF2 +#define TIM2_CH1_PA5_AF2 +#define TIM2_CH2_PA1_AF2 +#define TIM2_CH2_PB3_AF2 +#define TIM2_CH3_PA2_AF2 +#define TIM2_CH3_PB10_AF2 +#define TIM2_CH3_PC6_AF2 +#define TIM2_CH4_PA3_AF2 +#define TIM2_CH4_PB11_AF2 +#define TIM2_CH4_PC7_AF2 +#define TIM2_ETR_PA0_AF2 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH1_PC6_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH2_PC7_AF1 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH4_PB1_AF1 +#define TIM3_ETR_PD2_AF1 +#define TIM4_CH1_PB6_AF9 +#define TIM4_CH2_PB7_AF9 +#define TIM4_CH3_PB8_AF9 +#define TIM4_CH4_PB9_AF9 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_14 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +#define TIM1_BUS (1) +#define TIM4_BUS (1) +#define TIM15_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC6_CN +#define __PC7_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PF0_CN +#define __PF1_CN +#define __PF2_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_F_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +#define UART3_IVT (29) +#define UART3_NVIC (45) +#define UART4_IVT (29) +#define UART4_NVIC (45) +#define UART5_IVT (29) +#define UART5_NVIC (45) +#define UART6_IVT (29) +#define UART6_NVIC (45) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1CC/UFQFPN48/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1CC/UFQFPN48/mcu_definitions.h new file mode 100644 index 000000000..cc224a4d7 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1CC/UFQFPN48/mcu_definitions.h @@ -0,0 +1,385 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G0B1CC_UFQFPN48. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PB0_CH8 +#define ADC1_PB10_CH11 +#define ADC1_PB11_CH15 +#define ADC1_PB12_CH16 +#define ADC1_PB1_CH9 +#define ADC1_PB2_CH10 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF3 +#define FDCAN1_RX_PB8_AF3 +#define FDCAN1_RX_PD0_AF3 +#define FDCAN1_TX_PA12_AF3 +#define FDCAN1_TX_PB9_AF3 +#define FDCAN1_TX_PD1_AF3 +#define FDCAN2_RX_PB0_AF3 +#define FDCAN2_RX_PB12_AF3 +#define FDCAN2_RX_PB5_AF3 +#define FDCAN2_TX_PB13_AF3 +#define FDCAN2_TX_PB1_AF3 +#define FDCAN2_TX_PB6_AF3 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) + +#define CAN_MODULE_COUNT (2) + +#define HAL_LL_FDCAN1_GPIO_AF3 (3) +#define HAL_LL_FDCAN2_GPIO_AF3 (3) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (78) +#define DMA_NUM_OF_CHANNELS_FAMILY (78) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (12) +#define DMA_NUM_OF_STREAMS_FAMILY (12) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PB9_AF6 +#define I2C2_SCL_PA11_AF6 +#define I2C2_SCL_PA7_AF8 +#define I2C2_SCL_PA9_AF8 +#define I2C2_SCL_PB10_AF6 +#define I2C2_SCL_PB13_AF6 +#define I2C2_SCL_PB3_AF8 +#define I2C2_SDA_PA10_AF8 +#define I2C2_SDA_PA12_AF6 +#define I2C2_SDA_PA6_AF8 +#define I2C2_SDA_PB11_AF6 +#define I2C2_SDA_PB14_AF6 +#define I2C2_SDA_PB4_AF8 +#define I2C3_SCL_PA7_AF9 +#define I2C3_SCL_PB3_AF6 +#define I2C3_SDA_PA6_AF9 +#define I2C3_SDA_PB4_AF6 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF6 +#define LPUART1_RX_PB10_AF1 +#define LPUART1_TX_PA2_AF6 +#define LPUART1_TX_PB11_AF1 +#define LPUART2_RX_PA13_AF10 +#define LPUART2_RX_PB7_AF10 +#define LPUART2_RX_PC7_AF3 +#define LPUART2_TX_PA14_AF10 +#define LPUART2_TX_PB6_AF10 +#define LPUART2_TX_PC6_AF3 +#define LPUART2_TX_PF2_AF1 +#define USART1_RX_PA10_AF1 +#define USART1_RX_PB7_AF0 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 +#define USART3_RX_PB0_AF4 +#define USART3_RX_PB11_AF4 +#define USART3_RX_PB9_AF4 +#define USART3_TX_PA5_AF4 +#define USART3_TX_PB10_AF4 +#define USART3_TX_PB2_AF4 +#define USART3_TX_PB8_AF4 +#define USART4_RX_PA1_AF4 +#define USART4_TX_PA0_AF4 +#define USART5_RX_PB1_AF8 +#define USART5_RX_PB4_AF3 +#define USART5_RX_PD2_AF3 +#define USART5_TX_PB0_AF8 +#define USART5_TX_PB3_AF3 +#define USART5_TX_PD3_AF3 +#define USART6_RX_PA5_AF3 +#define USART6_RX_PB9_AF8 +#define USART6_TX_PA4_AF3 +#define USART6_TX_PB8_AF8 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) +#define UART_MODULE_6 (6) + +#define UART_MODULE_COUNT (6) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI2_MISO_PA3_AF0 +#define SPI2_MISO_PA9_AF4 +#define SPI2_MISO_PB14_AF0 +#define SPI2_MISO_PB2_AF1 +#define SPI2_MISO_PB6_AF4 +#define SPI2_MISO_PD3_AF1 +#define SPI2_MOSI_PA10_AF0 +#define SPI2_MOSI_PA4_AF1 +#define SPI2_MOSI_PB11_AF0 +#define SPI2_MOSI_PB15_AF0 +#define SPI2_MOSI_PB7_AF1 +#define SPI2_SCK_PA0_AF0 +#define SPI2_SCK_PB10_AF5 +#define SPI2_SCK_PB13_AF0 +#define SPI2_SCK_PB8_AF1 +#define SPI2_SCK_PD1_AF1 +#define SPI3_MISO_PB4_AF9 +#define SPI3_MOSI_PB5_AF9 +#define SPI3_SCK_PB3_AF9 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF5 +#define LPTIM2_ETR_PA5_AF5 +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PB1_AF0 +#define TIM14_CH1_PF0_AF2 +#define TIM15_CH1N_PA1_AF5 +#define TIM15_CH1N_PB13_AF5 +#define TIM15_CH1N_PB15_AF4 +#define TIM15_CH1N_PF1_AF2 +#define TIM15_CH1_PA2_AF5 +#define TIM15_CH1_PB14_AF5 +#define TIM15_CH2_PA3_AF5 +#define TIM15_CH2_PB15_AF5 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB8_AF2 +#define TIM16_CH1_PD0_AF2 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PB9_AF2 +#define TIM17_CH1_PD1_AF2 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1N_PB13_AF2 +#define TIM1_CH1N_PD2_AF2 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2N_PB14_AF2 +#define TIM1_CH2N_PD3_AF2 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH3N_PB15_AF2 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_ETR_PA12_AF2 +#define TIM2_CH1_PA0_AF2 +#define TIM2_CH1_PA15_AF2 +#define TIM2_CH1_PA5_AF2 +#define TIM2_CH2_PA1_AF2 +#define TIM2_CH2_PB3_AF2 +#define TIM2_CH3_PA2_AF2 +#define TIM2_CH3_PB10_AF2 +#define TIM2_CH3_PC6_AF2 +#define TIM2_CH4_PA3_AF2 +#define TIM2_CH4_PB11_AF2 +#define TIM2_CH4_PC7_AF2 +#define TIM2_ETR_PA0_AF2 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH1_PC6_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH2_PC7_AF1 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH4_PB1_AF1 +#define TIM3_ETR_PD2_AF1 +#define TIM4_CH1_PB6_AF9 +#define TIM4_CH2_PB7_AF9 +#define TIM4_CH3_PB8_AF9 +#define TIM4_CH4_PB9_AF9 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_14 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +#define TIM1_BUS (1) +#define TIM4_BUS (1) +#define TIM15_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC6_CN +#define __PC7_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PF0_CN +#define __PF1_CN +#define __PF2_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_F_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +#define UART3_IVT (29) +#define UART3_NVIC (45) +#define UART4_IVT (29) +#define UART4_NVIC (45) +#define UART5_IVT (29) +#define UART5_NVIC (45) +#define UART6_IVT (29) +#define UART6_NVIC (45) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1CE/LQFP48/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1CE/LQFP48/mcu_definitions.h new file mode 100644 index 000000000..8f222d5e4 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1CE/LQFP48/mcu_definitions.h @@ -0,0 +1,385 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G0B1CE_LQFP48. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PB0_CH8 +#define ADC1_PB10_CH11 +#define ADC1_PB11_CH15 +#define ADC1_PB12_CH16 +#define ADC1_PB1_CH9 +#define ADC1_PB2_CH10 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF3 +#define FDCAN1_RX_PB8_AF3 +#define FDCAN1_RX_PD0_AF3 +#define FDCAN1_TX_PA12_AF3 +#define FDCAN1_TX_PB9_AF3 +#define FDCAN1_TX_PD1_AF3 +#define FDCAN2_RX_PB0_AF3 +#define FDCAN2_RX_PB12_AF3 +#define FDCAN2_RX_PB5_AF3 +#define FDCAN2_TX_PB13_AF3 +#define FDCAN2_TX_PB1_AF3 +#define FDCAN2_TX_PB6_AF3 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) + +#define CAN_MODULE_COUNT (2) + +#define HAL_LL_FDCAN1_GPIO_AF3 (3) +#define HAL_LL_FDCAN2_GPIO_AF3 (3) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (78) +#define DMA_NUM_OF_CHANNELS_FAMILY (78) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (12) +#define DMA_NUM_OF_STREAMS_FAMILY (12) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PB9_AF6 +#define I2C2_SCL_PA11_AF6 +#define I2C2_SCL_PA7_AF8 +#define I2C2_SCL_PA9_AF8 +#define I2C2_SCL_PB10_AF6 +#define I2C2_SCL_PB13_AF6 +#define I2C2_SCL_PB3_AF8 +#define I2C2_SDA_PA10_AF8 +#define I2C2_SDA_PA12_AF6 +#define I2C2_SDA_PA6_AF8 +#define I2C2_SDA_PB11_AF6 +#define I2C2_SDA_PB14_AF6 +#define I2C2_SDA_PB4_AF8 +#define I2C3_SCL_PA7_AF9 +#define I2C3_SCL_PB3_AF6 +#define I2C3_SDA_PA6_AF9 +#define I2C3_SDA_PB4_AF6 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF6 +#define LPUART1_RX_PB10_AF1 +#define LPUART1_TX_PA2_AF6 +#define LPUART1_TX_PB11_AF1 +#define LPUART2_RX_PA13_AF10 +#define LPUART2_RX_PB7_AF10 +#define LPUART2_RX_PC7_AF3 +#define LPUART2_TX_PA14_AF10 +#define LPUART2_TX_PB6_AF10 +#define LPUART2_TX_PC6_AF3 +#define LPUART2_TX_PF2_AF1 +#define USART1_RX_PA10_AF1 +#define USART1_RX_PB7_AF0 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 +#define USART3_RX_PB0_AF4 +#define USART3_RX_PB11_AF4 +#define USART3_RX_PB9_AF4 +#define USART3_TX_PA5_AF4 +#define USART3_TX_PB10_AF4 +#define USART3_TX_PB2_AF4 +#define USART3_TX_PB8_AF4 +#define USART4_RX_PA1_AF4 +#define USART4_TX_PA0_AF4 +#define USART5_RX_PB1_AF8 +#define USART5_RX_PB4_AF3 +#define USART5_RX_PD2_AF3 +#define USART5_TX_PB0_AF8 +#define USART5_TX_PB3_AF3 +#define USART5_TX_PD3_AF3 +#define USART6_RX_PA5_AF3 +#define USART6_RX_PB9_AF8 +#define USART6_TX_PA4_AF3 +#define USART6_TX_PB8_AF8 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) +#define UART_MODULE_6 (6) + +#define UART_MODULE_COUNT (6) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI2_MISO_PA3_AF0 +#define SPI2_MISO_PA9_AF4 +#define SPI2_MISO_PB14_AF0 +#define SPI2_MISO_PB2_AF1 +#define SPI2_MISO_PB6_AF4 +#define SPI2_MISO_PD3_AF1 +#define SPI2_MOSI_PA10_AF0 +#define SPI2_MOSI_PA4_AF1 +#define SPI2_MOSI_PB11_AF0 +#define SPI2_MOSI_PB15_AF0 +#define SPI2_MOSI_PB7_AF1 +#define SPI2_SCK_PA0_AF0 +#define SPI2_SCK_PB10_AF5 +#define SPI2_SCK_PB13_AF0 +#define SPI2_SCK_PB8_AF1 +#define SPI2_SCK_PD1_AF1 +#define SPI3_MISO_PB4_AF9 +#define SPI3_MOSI_PB5_AF9 +#define SPI3_SCK_PB3_AF9 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF5 +#define LPTIM2_ETR_PA5_AF5 +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PB1_AF0 +#define TIM14_CH1_PF0_AF2 +#define TIM15_CH1N_PA1_AF5 +#define TIM15_CH1N_PB13_AF5 +#define TIM15_CH1N_PB15_AF4 +#define TIM15_CH1N_PF1_AF2 +#define TIM15_CH1_PA2_AF5 +#define TIM15_CH1_PB14_AF5 +#define TIM15_CH2_PA3_AF5 +#define TIM15_CH2_PB15_AF5 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB8_AF2 +#define TIM16_CH1_PD0_AF2 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PB9_AF2 +#define TIM17_CH1_PD1_AF2 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1N_PB13_AF2 +#define TIM1_CH1N_PD2_AF2 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2N_PB14_AF2 +#define TIM1_CH2N_PD3_AF2 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH3N_PB15_AF2 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_ETR_PA12_AF2 +#define TIM2_CH1_PA0_AF2 +#define TIM2_CH1_PA15_AF2 +#define TIM2_CH1_PA5_AF2 +#define TIM2_CH2_PA1_AF2 +#define TIM2_CH2_PB3_AF2 +#define TIM2_CH3_PA2_AF2 +#define TIM2_CH3_PB10_AF2 +#define TIM2_CH3_PC6_AF2 +#define TIM2_CH4_PA3_AF2 +#define TIM2_CH4_PB11_AF2 +#define TIM2_CH4_PC7_AF2 +#define TIM2_ETR_PA0_AF2 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH1_PC6_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH2_PC7_AF1 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH4_PB1_AF1 +#define TIM3_ETR_PD2_AF1 +#define TIM4_CH1_PB6_AF9 +#define TIM4_CH2_PB7_AF9 +#define TIM4_CH3_PB8_AF9 +#define TIM4_CH4_PB9_AF9 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_14 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +#define TIM1_BUS (1) +#define TIM4_BUS (1) +#define TIM15_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC6_CN +#define __PC7_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PF0_CN +#define __PF1_CN +#define __PF2_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_F_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +#define UART3_IVT (29) +#define UART3_NVIC (45) +#define UART4_IVT (29) +#define UART4_NVIC (45) +#define UART5_IVT (29) +#define UART5_NVIC (45) +#define UART6_IVT (29) +#define UART6_NVIC (45) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1CE/UFQFPN48/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1CE/UFQFPN48/mcu_definitions.h new file mode 100644 index 000000000..0fc65e221 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1CE/UFQFPN48/mcu_definitions.h @@ -0,0 +1,385 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G0B1CE_UFQFPN48. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PB0_CH8 +#define ADC1_PB10_CH11 +#define ADC1_PB11_CH15 +#define ADC1_PB12_CH16 +#define ADC1_PB1_CH9 +#define ADC1_PB2_CH10 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF3 +#define FDCAN1_RX_PB8_AF3 +#define FDCAN1_RX_PD0_AF3 +#define FDCAN1_TX_PA12_AF3 +#define FDCAN1_TX_PB9_AF3 +#define FDCAN1_TX_PD1_AF3 +#define FDCAN2_RX_PB0_AF3 +#define FDCAN2_RX_PB12_AF3 +#define FDCAN2_RX_PB5_AF3 +#define FDCAN2_TX_PB13_AF3 +#define FDCAN2_TX_PB1_AF3 +#define FDCAN2_TX_PB6_AF3 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) + +#define CAN_MODULE_COUNT (2) + +#define HAL_LL_FDCAN1_GPIO_AF3 (3) +#define HAL_LL_FDCAN2_GPIO_AF3 (3) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (78) +#define DMA_NUM_OF_CHANNELS_FAMILY (78) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (12) +#define DMA_NUM_OF_STREAMS_FAMILY (12) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PB9_AF6 +#define I2C2_SCL_PA11_AF6 +#define I2C2_SCL_PA7_AF8 +#define I2C2_SCL_PA9_AF8 +#define I2C2_SCL_PB10_AF6 +#define I2C2_SCL_PB13_AF6 +#define I2C2_SCL_PB3_AF8 +#define I2C2_SDA_PA10_AF8 +#define I2C2_SDA_PA12_AF6 +#define I2C2_SDA_PA6_AF8 +#define I2C2_SDA_PB11_AF6 +#define I2C2_SDA_PB14_AF6 +#define I2C2_SDA_PB4_AF8 +#define I2C3_SCL_PA7_AF9 +#define I2C3_SCL_PB3_AF6 +#define I2C3_SDA_PA6_AF9 +#define I2C3_SDA_PB4_AF6 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF6 +#define LPUART1_RX_PB10_AF1 +#define LPUART1_TX_PA2_AF6 +#define LPUART1_TX_PB11_AF1 +#define LPUART2_RX_PA13_AF10 +#define LPUART2_RX_PB7_AF10 +#define LPUART2_RX_PC7_AF3 +#define LPUART2_TX_PA14_AF10 +#define LPUART2_TX_PB6_AF10 +#define LPUART2_TX_PC6_AF3 +#define LPUART2_TX_PF2_AF1 +#define USART1_RX_PA10_AF1 +#define USART1_RX_PB7_AF0 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 +#define USART3_RX_PB0_AF4 +#define USART3_RX_PB11_AF4 +#define USART3_RX_PB9_AF4 +#define USART3_TX_PA5_AF4 +#define USART3_TX_PB10_AF4 +#define USART3_TX_PB2_AF4 +#define USART3_TX_PB8_AF4 +#define USART4_RX_PA1_AF4 +#define USART4_TX_PA0_AF4 +#define USART5_RX_PB1_AF8 +#define USART5_RX_PB4_AF3 +#define USART5_RX_PD2_AF3 +#define USART5_TX_PB0_AF8 +#define USART5_TX_PB3_AF3 +#define USART5_TX_PD3_AF3 +#define USART6_RX_PA5_AF3 +#define USART6_RX_PB9_AF8 +#define USART6_TX_PA4_AF3 +#define USART6_TX_PB8_AF8 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) +#define UART_MODULE_6 (6) + +#define UART_MODULE_COUNT (6) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI2_MISO_PA3_AF0 +#define SPI2_MISO_PA9_AF4 +#define SPI2_MISO_PB14_AF0 +#define SPI2_MISO_PB2_AF1 +#define SPI2_MISO_PB6_AF4 +#define SPI2_MISO_PD3_AF1 +#define SPI2_MOSI_PA10_AF0 +#define SPI2_MOSI_PA4_AF1 +#define SPI2_MOSI_PB11_AF0 +#define SPI2_MOSI_PB15_AF0 +#define SPI2_MOSI_PB7_AF1 +#define SPI2_SCK_PA0_AF0 +#define SPI2_SCK_PB10_AF5 +#define SPI2_SCK_PB13_AF0 +#define SPI2_SCK_PB8_AF1 +#define SPI2_SCK_PD1_AF1 +#define SPI3_MISO_PB4_AF9 +#define SPI3_MOSI_PB5_AF9 +#define SPI3_SCK_PB3_AF9 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF5 +#define LPTIM2_ETR_PA5_AF5 +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PB1_AF0 +#define TIM14_CH1_PF0_AF2 +#define TIM15_CH1N_PA1_AF5 +#define TIM15_CH1N_PB13_AF5 +#define TIM15_CH1N_PB15_AF4 +#define TIM15_CH1N_PF1_AF2 +#define TIM15_CH1_PA2_AF5 +#define TIM15_CH1_PB14_AF5 +#define TIM15_CH2_PA3_AF5 +#define TIM15_CH2_PB15_AF5 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB8_AF2 +#define TIM16_CH1_PD0_AF2 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PB9_AF2 +#define TIM17_CH1_PD1_AF2 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1N_PB13_AF2 +#define TIM1_CH1N_PD2_AF2 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2N_PB14_AF2 +#define TIM1_CH2N_PD3_AF2 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH3N_PB15_AF2 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_ETR_PA12_AF2 +#define TIM2_CH1_PA0_AF2 +#define TIM2_CH1_PA15_AF2 +#define TIM2_CH1_PA5_AF2 +#define TIM2_CH2_PA1_AF2 +#define TIM2_CH2_PB3_AF2 +#define TIM2_CH3_PA2_AF2 +#define TIM2_CH3_PB10_AF2 +#define TIM2_CH3_PC6_AF2 +#define TIM2_CH4_PA3_AF2 +#define TIM2_CH4_PB11_AF2 +#define TIM2_CH4_PC7_AF2 +#define TIM2_ETR_PA0_AF2 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH1_PC6_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH2_PC7_AF1 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH4_PB1_AF1 +#define TIM3_ETR_PD2_AF1 +#define TIM4_CH1_PB6_AF9 +#define TIM4_CH2_PB7_AF9 +#define TIM4_CH3_PB8_AF9 +#define TIM4_CH4_PB9_AF9 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_14 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +#define TIM1_BUS (1) +#define TIM4_BUS (1) +#define TIM15_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC6_CN +#define __PC7_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PF0_CN +#define __PF1_CN +#define __PF2_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_F_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +#define UART3_IVT (29) +#define UART3_NVIC (45) +#define UART4_IVT (29) +#define UART4_NVIC (45) +#define UART5_IVT (29) +#define UART5_NVIC (45) +#define UART6_IVT (29) +#define UART6_NVIC (45) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1KB/LQFP32/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1KB/LQFP32/mcu_definitions.h new file mode 100644 index 000000000..5aaeea6d8 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1KB/LQFP32/mcu_definitions.h @@ -0,0 +1,327 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G0B1KB_LQFP32. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PB0_CH8 +#define ADC1_PB1_CH9 +#define ADC1_PB2_CH10 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF3 +#define FDCAN1_RX_PB8_AF3 +#define FDCAN1_TX_PA12_AF3 +#define FDCAN1_TX_PB9_AF3 +#define FDCAN2_RX_PB0_AF3 +#define FDCAN2_RX_PB5_AF3 +#define FDCAN2_TX_PB1_AF3 +#define FDCAN2_TX_PB6_AF3 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) + +#define CAN_MODULE_COUNT (2) + +#define HAL_LL_FDCAN1_GPIO_AF3 (3) +#define HAL_LL_FDCAN2_GPIO_AF3 (3) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (78) +#define DMA_NUM_OF_CHANNELS_FAMILY (78) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (12) +#define DMA_NUM_OF_STREAMS_FAMILY (12) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PB9_AF6 +#define I2C2_SCL_PA11_AF6 +#define I2C2_SCL_PA7_AF8 +#define I2C2_SCL_PA9_AF8 +#define I2C2_SCL_PB3_AF8 +#define I2C2_SDA_PA10_AF8 +#define I2C2_SDA_PA12_AF6 +#define I2C2_SDA_PA6_AF8 +#define I2C2_SDA_PB4_AF8 +#define I2C3_SCL_PA7_AF9 +#define I2C3_SCL_PB3_AF6 +#define I2C3_SDA_PA6_AF9 +#define I2C3_SDA_PB4_AF6 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF6 +#define LPUART1_TX_PA2_AF6 +#define LPUART2_RX_PA13_AF10 +#define LPUART2_RX_PB7_AF10 +#define LPUART2_TX_PA14_AF10 +#define LPUART2_TX_PB6_AF10 +#define LPUART2_TX_PC6_AF3 +#define LPUART2_TX_PF2_AF1 +#define USART1_RX_PA10_AF1 +#define USART1_RX_PB7_AF0 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 +#define USART3_RX_PB0_AF4 +#define USART3_RX_PB9_AF4 +#define USART3_TX_PA5_AF4 +#define USART3_TX_PB2_AF4 +#define USART3_TX_PB8_AF4 +#define USART4_RX_PA1_AF4 +#define USART4_TX_PA0_AF4 +#define USART5_RX_PB1_AF8 +#define USART5_RX_PB4_AF3 +#define USART5_TX_PB0_AF8 +#define USART5_TX_PB3_AF3 +#define USART6_RX_PA5_AF3 +#define USART6_RX_PB9_AF8 +#define USART6_TX_PA4_AF3 +#define USART6_TX_PB8_AF8 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) +#define UART_MODULE_6 (6) + +#define UART_MODULE_COUNT (6) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI2_MISO_PA3_AF0 +#define SPI2_MISO_PA9_AF4 +#define SPI2_MISO_PB2_AF1 +#define SPI2_MISO_PB6_AF4 +#define SPI2_MOSI_PA10_AF0 +#define SPI2_MOSI_PA4_AF1 +#define SPI2_MOSI_PB7_AF1 +#define SPI2_SCK_PA0_AF0 +#define SPI2_SCK_PB8_AF1 +#define SPI3_MISO_PB4_AF9 +#define SPI3_MOSI_PB5_AF9 +#define SPI3_SCK_PB3_AF9 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF5 +#define LPTIM2_ETR_PA5_AF5 +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PB1_AF0 +#define TIM15_CH1N_PA1_AF5 +#define TIM15_CH1_PA2_AF5 +#define TIM15_CH2_PA3_AF5 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB8_AF2 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PB9_AF2 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_ETR_PA12_AF2 +#define TIM2_CH1_PA0_AF2 +#define TIM2_CH1_PA15_AF2 +#define TIM2_CH1_PA5_AF2 +#define TIM2_CH2_PA1_AF2 +#define TIM2_CH2_PB3_AF2 +#define TIM2_CH3_PA2_AF2 +#define TIM2_CH3_PC6_AF2 +#define TIM2_CH4_PA3_AF2 +#define TIM2_ETR_PA0_AF2 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH1_PC6_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH4_PB1_AF1 +#define TIM4_CH1_PB6_AF9 +#define TIM4_CH2_PB7_AF9 +#define TIM4_CH3_PB8_AF9 +#define TIM4_CH4_PB9_AF9 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_14 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +#define TIM1_BUS (1) +#define TIM4_BUS (1) +#define TIM15_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC14_CN +#define __PC15_CN +#define __PC6_CN +#define __PF2_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN + +#define PORT_COUNT (4) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +#define UART3_IVT (29) +#define UART3_NVIC (45) +#define UART4_IVT (29) +#define UART4_NVIC (45) +#define UART5_IVT (29) +#define UART5_NVIC (45) +#define UART6_IVT (29) +#define UART6_NVIC (45) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1KB/UFQFPN32/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1KB/UFQFPN32/mcu_definitions.h new file mode 100644 index 000000000..4b6b935f7 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1KB/UFQFPN32/mcu_definitions.h @@ -0,0 +1,327 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G0B1KB_UFQFPN32. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PB0_CH8 +#define ADC1_PB1_CH9 +#define ADC1_PB2_CH10 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF3 +#define FDCAN1_RX_PB8_AF3 +#define FDCAN1_TX_PA12_AF3 +#define FDCAN1_TX_PB9_AF3 +#define FDCAN2_RX_PB0_AF3 +#define FDCAN2_RX_PB5_AF3 +#define FDCAN2_TX_PB1_AF3 +#define FDCAN2_TX_PB6_AF3 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) + +#define CAN_MODULE_COUNT (2) + +#define HAL_LL_FDCAN1_GPIO_AF3 (3) +#define HAL_LL_FDCAN2_GPIO_AF3 (3) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (78) +#define DMA_NUM_OF_CHANNELS_FAMILY (78) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (12) +#define DMA_NUM_OF_STREAMS_FAMILY (12) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PB9_AF6 +#define I2C2_SCL_PA11_AF6 +#define I2C2_SCL_PA7_AF8 +#define I2C2_SCL_PA9_AF8 +#define I2C2_SCL_PB3_AF8 +#define I2C2_SDA_PA10_AF8 +#define I2C2_SDA_PA12_AF6 +#define I2C2_SDA_PA6_AF8 +#define I2C2_SDA_PB4_AF8 +#define I2C3_SCL_PA7_AF9 +#define I2C3_SCL_PB3_AF6 +#define I2C3_SDA_PA6_AF9 +#define I2C3_SDA_PB4_AF6 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF6 +#define LPUART1_TX_PA2_AF6 +#define LPUART2_RX_PA13_AF10 +#define LPUART2_RX_PB7_AF10 +#define LPUART2_TX_PA14_AF10 +#define LPUART2_TX_PB6_AF10 +#define LPUART2_TX_PC6_AF3 +#define LPUART2_TX_PF2_AF1 +#define USART1_RX_PA10_AF1 +#define USART1_RX_PB7_AF0 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 +#define USART3_RX_PB0_AF4 +#define USART3_RX_PB9_AF4 +#define USART3_TX_PA5_AF4 +#define USART3_TX_PB2_AF4 +#define USART3_TX_PB8_AF4 +#define USART4_RX_PA1_AF4 +#define USART4_TX_PA0_AF4 +#define USART5_RX_PB1_AF8 +#define USART5_RX_PB4_AF3 +#define USART5_TX_PB0_AF8 +#define USART5_TX_PB3_AF3 +#define USART6_RX_PA5_AF3 +#define USART6_RX_PB9_AF8 +#define USART6_TX_PA4_AF3 +#define USART6_TX_PB8_AF8 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) +#define UART_MODULE_6 (6) + +#define UART_MODULE_COUNT (6) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI2_MISO_PA3_AF0 +#define SPI2_MISO_PA9_AF4 +#define SPI2_MISO_PB2_AF1 +#define SPI2_MISO_PB6_AF4 +#define SPI2_MOSI_PA10_AF0 +#define SPI2_MOSI_PA4_AF1 +#define SPI2_MOSI_PB7_AF1 +#define SPI2_SCK_PA0_AF0 +#define SPI2_SCK_PB8_AF1 +#define SPI3_MISO_PB4_AF9 +#define SPI3_MOSI_PB5_AF9 +#define SPI3_SCK_PB3_AF9 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF5 +#define LPTIM2_ETR_PA5_AF5 +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PB1_AF0 +#define TIM15_CH1N_PA1_AF5 +#define TIM15_CH1_PA2_AF5 +#define TIM15_CH2_PA3_AF5 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB8_AF2 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PB9_AF2 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_ETR_PA12_AF2 +#define TIM2_CH1_PA0_AF2 +#define TIM2_CH1_PA15_AF2 +#define TIM2_CH1_PA5_AF2 +#define TIM2_CH2_PA1_AF2 +#define TIM2_CH2_PB3_AF2 +#define TIM2_CH3_PA2_AF2 +#define TIM2_CH3_PC6_AF2 +#define TIM2_CH4_PA3_AF2 +#define TIM2_ETR_PA0_AF2 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH1_PC6_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH4_PB1_AF1 +#define TIM4_CH1_PB6_AF9 +#define TIM4_CH2_PB7_AF9 +#define TIM4_CH3_PB8_AF9 +#define TIM4_CH4_PB9_AF9 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_14 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +#define TIM1_BUS (1) +#define TIM4_BUS (1) +#define TIM15_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC14_CN +#define __PC15_CN +#define __PC6_CN +#define __PF2_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN + +#define PORT_COUNT (4) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +#define UART3_IVT (29) +#define UART3_NVIC (45) +#define UART4_IVT (29) +#define UART4_NVIC (45) +#define UART5_IVT (29) +#define UART5_NVIC (45) +#define UART6_IVT (29) +#define UART6_NVIC (45) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1KC/LQFP32/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1KC/LQFP32/mcu_definitions.h new file mode 100644 index 000000000..d5a1b526e --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1KC/LQFP32/mcu_definitions.h @@ -0,0 +1,327 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G0B1KC_LQFP32. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PB0_CH8 +#define ADC1_PB1_CH9 +#define ADC1_PB2_CH10 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF3 +#define FDCAN1_RX_PB8_AF3 +#define FDCAN1_TX_PA12_AF3 +#define FDCAN1_TX_PB9_AF3 +#define FDCAN2_RX_PB0_AF3 +#define FDCAN2_RX_PB5_AF3 +#define FDCAN2_TX_PB1_AF3 +#define FDCAN2_TX_PB6_AF3 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) + +#define CAN_MODULE_COUNT (2) + +#define HAL_LL_FDCAN1_GPIO_AF3 (3) +#define HAL_LL_FDCAN2_GPIO_AF3 (3) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (78) +#define DMA_NUM_OF_CHANNELS_FAMILY (78) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (12) +#define DMA_NUM_OF_STREAMS_FAMILY (12) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PB9_AF6 +#define I2C2_SCL_PA11_AF6 +#define I2C2_SCL_PA7_AF8 +#define I2C2_SCL_PA9_AF8 +#define I2C2_SCL_PB3_AF8 +#define I2C2_SDA_PA10_AF8 +#define I2C2_SDA_PA12_AF6 +#define I2C2_SDA_PA6_AF8 +#define I2C2_SDA_PB4_AF8 +#define I2C3_SCL_PA7_AF9 +#define I2C3_SCL_PB3_AF6 +#define I2C3_SDA_PA6_AF9 +#define I2C3_SDA_PB4_AF6 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF6 +#define LPUART1_TX_PA2_AF6 +#define LPUART2_RX_PA13_AF10 +#define LPUART2_RX_PB7_AF10 +#define LPUART2_TX_PA14_AF10 +#define LPUART2_TX_PB6_AF10 +#define LPUART2_TX_PC6_AF3 +#define LPUART2_TX_PF2_AF1 +#define USART1_RX_PA10_AF1 +#define USART1_RX_PB7_AF0 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 +#define USART3_RX_PB0_AF4 +#define USART3_RX_PB9_AF4 +#define USART3_TX_PA5_AF4 +#define USART3_TX_PB2_AF4 +#define USART3_TX_PB8_AF4 +#define USART4_RX_PA1_AF4 +#define USART4_TX_PA0_AF4 +#define USART5_RX_PB1_AF8 +#define USART5_RX_PB4_AF3 +#define USART5_TX_PB0_AF8 +#define USART5_TX_PB3_AF3 +#define USART6_RX_PA5_AF3 +#define USART6_RX_PB9_AF8 +#define USART6_TX_PA4_AF3 +#define USART6_TX_PB8_AF8 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) +#define UART_MODULE_6 (6) + +#define UART_MODULE_COUNT (6) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI2_MISO_PA3_AF0 +#define SPI2_MISO_PA9_AF4 +#define SPI2_MISO_PB2_AF1 +#define SPI2_MISO_PB6_AF4 +#define SPI2_MOSI_PA10_AF0 +#define SPI2_MOSI_PA4_AF1 +#define SPI2_MOSI_PB7_AF1 +#define SPI2_SCK_PA0_AF0 +#define SPI2_SCK_PB8_AF1 +#define SPI3_MISO_PB4_AF9 +#define SPI3_MOSI_PB5_AF9 +#define SPI3_SCK_PB3_AF9 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF5 +#define LPTIM2_ETR_PA5_AF5 +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PB1_AF0 +#define TIM15_CH1N_PA1_AF5 +#define TIM15_CH1_PA2_AF5 +#define TIM15_CH2_PA3_AF5 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB8_AF2 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PB9_AF2 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_ETR_PA12_AF2 +#define TIM2_CH1_PA0_AF2 +#define TIM2_CH1_PA15_AF2 +#define TIM2_CH1_PA5_AF2 +#define TIM2_CH2_PA1_AF2 +#define TIM2_CH2_PB3_AF2 +#define TIM2_CH3_PA2_AF2 +#define TIM2_CH3_PC6_AF2 +#define TIM2_CH4_PA3_AF2 +#define TIM2_ETR_PA0_AF2 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH1_PC6_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH4_PB1_AF1 +#define TIM4_CH1_PB6_AF9 +#define TIM4_CH2_PB7_AF9 +#define TIM4_CH3_PB8_AF9 +#define TIM4_CH4_PB9_AF9 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_14 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +#define TIM1_BUS (1) +#define TIM4_BUS (1) +#define TIM15_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC14_CN +#define __PC15_CN +#define __PC6_CN +#define __PF2_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN + +#define PORT_COUNT (4) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +#define UART3_IVT (29) +#define UART3_NVIC (45) +#define UART4_IVT (29) +#define UART4_NVIC (45) +#define UART5_IVT (29) +#define UART5_NVIC (45) +#define UART6_IVT (29) +#define UART6_NVIC (45) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1KC/UFQFPN32/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1KC/UFQFPN32/mcu_definitions.h new file mode 100644 index 000000000..1db48e823 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1KC/UFQFPN32/mcu_definitions.h @@ -0,0 +1,327 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G0B1KC_UFQFPN32. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PB0_CH8 +#define ADC1_PB1_CH9 +#define ADC1_PB2_CH10 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF3 +#define FDCAN1_RX_PB8_AF3 +#define FDCAN1_TX_PA12_AF3 +#define FDCAN1_TX_PB9_AF3 +#define FDCAN2_RX_PB0_AF3 +#define FDCAN2_RX_PB5_AF3 +#define FDCAN2_TX_PB1_AF3 +#define FDCAN2_TX_PB6_AF3 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) + +#define CAN_MODULE_COUNT (2) + +#define HAL_LL_FDCAN1_GPIO_AF3 (3) +#define HAL_LL_FDCAN2_GPIO_AF3 (3) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (78) +#define DMA_NUM_OF_CHANNELS_FAMILY (78) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (12) +#define DMA_NUM_OF_STREAMS_FAMILY (12) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PB9_AF6 +#define I2C2_SCL_PA11_AF6 +#define I2C2_SCL_PA7_AF8 +#define I2C2_SCL_PA9_AF8 +#define I2C2_SCL_PB3_AF8 +#define I2C2_SDA_PA10_AF8 +#define I2C2_SDA_PA12_AF6 +#define I2C2_SDA_PA6_AF8 +#define I2C2_SDA_PB4_AF8 +#define I2C3_SCL_PA7_AF9 +#define I2C3_SCL_PB3_AF6 +#define I2C3_SDA_PA6_AF9 +#define I2C3_SDA_PB4_AF6 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF6 +#define LPUART1_TX_PA2_AF6 +#define LPUART2_RX_PA13_AF10 +#define LPUART2_RX_PB7_AF10 +#define LPUART2_TX_PA14_AF10 +#define LPUART2_TX_PB6_AF10 +#define LPUART2_TX_PC6_AF3 +#define LPUART2_TX_PF2_AF1 +#define USART1_RX_PA10_AF1 +#define USART1_RX_PB7_AF0 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 +#define USART3_RX_PB0_AF4 +#define USART3_RX_PB9_AF4 +#define USART3_TX_PA5_AF4 +#define USART3_TX_PB2_AF4 +#define USART3_TX_PB8_AF4 +#define USART4_RX_PA1_AF4 +#define USART4_TX_PA0_AF4 +#define USART5_RX_PB1_AF8 +#define USART5_RX_PB4_AF3 +#define USART5_TX_PB0_AF8 +#define USART5_TX_PB3_AF3 +#define USART6_RX_PA5_AF3 +#define USART6_RX_PB9_AF8 +#define USART6_TX_PA4_AF3 +#define USART6_TX_PB8_AF8 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) +#define UART_MODULE_6 (6) + +#define UART_MODULE_COUNT (6) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI2_MISO_PA3_AF0 +#define SPI2_MISO_PA9_AF4 +#define SPI2_MISO_PB2_AF1 +#define SPI2_MISO_PB6_AF4 +#define SPI2_MOSI_PA10_AF0 +#define SPI2_MOSI_PA4_AF1 +#define SPI2_MOSI_PB7_AF1 +#define SPI2_SCK_PA0_AF0 +#define SPI2_SCK_PB8_AF1 +#define SPI3_MISO_PB4_AF9 +#define SPI3_MOSI_PB5_AF9 +#define SPI3_SCK_PB3_AF9 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF5 +#define LPTIM2_ETR_PA5_AF5 +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PB1_AF0 +#define TIM15_CH1N_PA1_AF5 +#define TIM15_CH1_PA2_AF5 +#define TIM15_CH2_PA3_AF5 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB8_AF2 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PB9_AF2 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_ETR_PA12_AF2 +#define TIM2_CH1_PA0_AF2 +#define TIM2_CH1_PA15_AF2 +#define TIM2_CH1_PA5_AF2 +#define TIM2_CH2_PA1_AF2 +#define TIM2_CH2_PB3_AF2 +#define TIM2_CH3_PA2_AF2 +#define TIM2_CH3_PC6_AF2 +#define TIM2_CH4_PA3_AF2 +#define TIM2_ETR_PA0_AF2 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH1_PC6_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH4_PB1_AF1 +#define TIM4_CH1_PB6_AF9 +#define TIM4_CH2_PB7_AF9 +#define TIM4_CH3_PB8_AF9 +#define TIM4_CH4_PB9_AF9 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_14 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +#define TIM1_BUS (1) +#define TIM4_BUS (1) +#define TIM15_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC14_CN +#define __PC15_CN +#define __PC6_CN +#define __PF2_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN + +#define PORT_COUNT (4) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +#define UART3_IVT (29) +#define UART3_NVIC (45) +#define UART4_IVT (29) +#define UART4_NVIC (45) +#define UART5_IVT (29) +#define UART5_NVIC (45) +#define UART6_IVT (29) +#define UART6_NVIC (45) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1KE/LQFP32/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1KE/LQFP32/mcu_definitions.h new file mode 100644 index 000000000..5131d9956 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1KE/LQFP32/mcu_definitions.h @@ -0,0 +1,327 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G0B1KE_LQFP32. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PB0_CH8 +#define ADC1_PB1_CH9 +#define ADC1_PB2_CH10 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF3 +#define FDCAN1_RX_PB8_AF3 +#define FDCAN1_TX_PA12_AF3 +#define FDCAN1_TX_PB9_AF3 +#define FDCAN2_RX_PB0_AF3 +#define FDCAN2_RX_PB5_AF3 +#define FDCAN2_TX_PB1_AF3 +#define FDCAN2_TX_PB6_AF3 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) + +#define CAN_MODULE_COUNT (2) + +#define HAL_LL_FDCAN1_GPIO_AF3 (3) +#define HAL_LL_FDCAN2_GPIO_AF3 (3) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (78) +#define DMA_NUM_OF_CHANNELS_FAMILY (78) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (12) +#define DMA_NUM_OF_STREAMS_FAMILY (12) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PB9_AF6 +#define I2C2_SCL_PA11_AF6 +#define I2C2_SCL_PA7_AF8 +#define I2C2_SCL_PA9_AF8 +#define I2C2_SCL_PB3_AF8 +#define I2C2_SDA_PA10_AF8 +#define I2C2_SDA_PA12_AF6 +#define I2C2_SDA_PA6_AF8 +#define I2C2_SDA_PB4_AF8 +#define I2C3_SCL_PA7_AF9 +#define I2C3_SCL_PB3_AF6 +#define I2C3_SDA_PA6_AF9 +#define I2C3_SDA_PB4_AF6 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF6 +#define LPUART1_TX_PA2_AF6 +#define LPUART2_RX_PA13_AF10 +#define LPUART2_RX_PB7_AF10 +#define LPUART2_TX_PA14_AF10 +#define LPUART2_TX_PB6_AF10 +#define LPUART2_TX_PC6_AF3 +#define LPUART2_TX_PF2_AF1 +#define USART1_RX_PA10_AF1 +#define USART1_RX_PB7_AF0 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 +#define USART3_RX_PB0_AF4 +#define USART3_RX_PB9_AF4 +#define USART3_TX_PA5_AF4 +#define USART3_TX_PB2_AF4 +#define USART3_TX_PB8_AF4 +#define USART4_RX_PA1_AF4 +#define USART4_TX_PA0_AF4 +#define USART5_RX_PB1_AF8 +#define USART5_RX_PB4_AF3 +#define USART5_TX_PB0_AF8 +#define USART5_TX_PB3_AF3 +#define USART6_RX_PA5_AF3 +#define USART6_RX_PB9_AF8 +#define USART6_TX_PA4_AF3 +#define USART6_TX_PB8_AF8 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) +#define UART_MODULE_6 (6) + +#define UART_MODULE_COUNT (6) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI2_MISO_PA3_AF0 +#define SPI2_MISO_PA9_AF4 +#define SPI2_MISO_PB2_AF1 +#define SPI2_MISO_PB6_AF4 +#define SPI2_MOSI_PA10_AF0 +#define SPI2_MOSI_PA4_AF1 +#define SPI2_MOSI_PB7_AF1 +#define SPI2_SCK_PA0_AF0 +#define SPI2_SCK_PB8_AF1 +#define SPI3_MISO_PB4_AF9 +#define SPI3_MOSI_PB5_AF9 +#define SPI3_SCK_PB3_AF9 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF5 +#define LPTIM2_ETR_PA5_AF5 +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PB1_AF0 +#define TIM15_CH1N_PA1_AF5 +#define TIM15_CH1_PA2_AF5 +#define TIM15_CH2_PA3_AF5 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB8_AF2 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PB9_AF2 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_ETR_PA12_AF2 +#define TIM2_CH1_PA0_AF2 +#define TIM2_CH1_PA15_AF2 +#define TIM2_CH1_PA5_AF2 +#define TIM2_CH2_PA1_AF2 +#define TIM2_CH2_PB3_AF2 +#define TIM2_CH3_PA2_AF2 +#define TIM2_CH3_PC6_AF2 +#define TIM2_CH4_PA3_AF2 +#define TIM2_ETR_PA0_AF2 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH1_PC6_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH4_PB1_AF1 +#define TIM4_CH1_PB6_AF9 +#define TIM4_CH2_PB7_AF9 +#define TIM4_CH3_PB8_AF9 +#define TIM4_CH4_PB9_AF9 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_14 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +#define TIM1_BUS (1) +#define TIM4_BUS (1) +#define TIM15_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC14_CN +#define __PC15_CN +#define __PC6_CN +#define __PF2_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN + +#define PORT_COUNT (4) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +#define UART3_IVT (29) +#define UART3_NVIC (45) +#define UART4_IVT (29) +#define UART4_NVIC (45) +#define UART5_IVT (29) +#define UART5_NVIC (45) +#define UART6_IVT (29) +#define UART6_NVIC (45) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1KE/UFQFPN32/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1KE/UFQFPN32/mcu_definitions.h new file mode 100644 index 000000000..fe2e2388e --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1KE/UFQFPN32/mcu_definitions.h @@ -0,0 +1,327 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G0B1KE_UFQFPN32. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PB0_CH8 +#define ADC1_PB1_CH9 +#define ADC1_PB2_CH10 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF3 +#define FDCAN1_RX_PB8_AF3 +#define FDCAN1_TX_PA12_AF3 +#define FDCAN1_TX_PB9_AF3 +#define FDCAN2_RX_PB0_AF3 +#define FDCAN2_RX_PB5_AF3 +#define FDCAN2_TX_PB1_AF3 +#define FDCAN2_TX_PB6_AF3 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) + +#define CAN_MODULE_COUNT (2) + +#define HAL_LL_FDCAN1_GPIO_AF3 (3) +#define HAL_LL_FDCAN2_GPIO_AF3 (3) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (78) +#define DMA_NUM_OF_CHANNELS_FAMILY (78) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (12) +#define DMA_NUM_OF_STREAMS_FAMILY (12) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PB9_AF6 +#define I2C2_SCL_PA11_AF6 +#define I2C2_SCL_PA7_AF8 +#define I2C2_SCL_PA9_AF8 +#define I2C2_SCL_PB3_AF8 +#define I2C2_SDA_PA10_AF8 +#define I2C2_SDA_PA12_AF6 +#define I2C2_SDA_PA6_AF8 +#define I2C2_SDA_PB4_AF8 +#define I2C3_SCL_PA7_AF9 +#define I2C3_SCL_PB3_AF6 +#define I2C3_SDA_PA6_AF9 +#define I2C3_SDA_PB4_AF6 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF6 +#define LPUART1_TX_PA2_AF6 +#define LPUART2_RX_PA13_AF10 +#define LPUART2_RX_PB7_AF10 +#define LPUART2_TX_PA14_AF10 +#define LPUART2_TX_PB6_AF10 +#define LPUART2_TX_PC6_AF3 +#define LPUART2_TX_PF2_AF1 +#define USART1_RX_PA10_AF1 +#define USART1_RX_PB7_AF0 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 +#define USART3_RX_PB0_AF4 +#define USART3_RX_PB9_AF4 +#define USART3_TX_PA5_AF4 +#define USART3_TX_PB2_AF4 +#define USART3_TX_PB8_AF4 +#define USART4_RX_PA1_AF4 +#define USART4_TX_PA0_AF4 +#define USART5_RX_PB1_AF8 +#define USART5_RX_PB4_AF3 +#define USART5_TX_PB0_AF8 +#define USART5_TX_PB3_AF3 +#define USART6_RX_PA5_AF3 +#define USART6_RX_PB9_AF8 +#define USART6_TX_PA4_AF3 +#define USART6_TX_PB8_AF8 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) +#define UART_MODULE_6 (6) + +#define UART_MODULE_COUNT (6) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI2_MISO_PA3_AF0 +#define SPI2_MISO_PA9_AF4 +#define SPI2_MISO_PB2_AF1 +#define SPI2_MISO_PB6_AF4 +#define SPI2_MOSI_PA10_AF0 +#define SPI2_MOSI_PA4_AF1 +#define SPI2_MOSI_PB7_AF1 +#define SPI2_SCK_PA0_AF0 +#define SPI2_SCK_PB8_AF1 +#define SPI3_MISO_PB4_AF9 +#define SPI3_MOSI_PB5_AF9 +#define SPI3_SCK_PB3_AF9 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF5 +#define LPTIM2_ETR_PA5_AF5 +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PB1_AF0 +#define TIM15_CH1N_PA1_AF5 +#define TIM15_CH1_PA2_AF5 +#define TIM15_CH2_PA3_AF5 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB8_AF2 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PB9_AF2 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_ETR_PA12_AF2 +#define TIM2_CH1_PA0_AF2 +#define TIM2_CH1_PA15_AF2 +#define TIM2_CH1_PA5_AF2 +#define TIM2_CH2_PA1_AF2 +#define TIM2_CH2_PB3_AF2 +#define TIM2_CH3_PA2_AF2 +#define TIM2_CH3_PC6_AF2 +#define TIM2_CH4_PA3_AF2 +#define TIM2_ETR_PA0_AF2 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH1_PC6_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH4_PB1_AF1 +#define TIM4_CH1_PB6_AF9 +#define TIM4_CH2_PB7_AF9 +#define TIM4_CH3_PB8_AF9 +#define TIM4_CH4_PB9_AF9 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_14 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +#define TIM1_BUS (1) +#define TIM4_BUS (1) +#define TIM15_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC14_CN +#define __PC15_CN +#define __PC6_CN +#define __PF2_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN + +#define PORT_COUNT (4) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +#define UART3_IVT (29) +#define UART3_NVIC (45) +#define UART4_IVT (29) +#define UART4_NVIC (45) +#define UART5_IVT (29) +#define UART5_NVIC (45) +#define UART6_IVT (29) +#define UART6_NVIC (45) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1MB/LQFP80/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1MB/LQFP80/mcu_definitions.h new file mode 100644 index 000000000..f824622c5 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1MB/LQFP80/mcu_definitions.h @@ -0,0 +1,487 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G0B1MB_LQFP80. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PB0_CH8 +#define ADC1_PB10_CH11 +#define ADC1_PB11_CH15 +#define ADC1_PB12_CH16 +#define ADC1_PB1_CH9 +#define ADC1_PB2_CH10 +#define ADC1_PC4_CH17 +#define ADC1_PC5_CH18 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF3 +#define FDCAN1_RX_PB8_AF3 +#define FDCAN1_RX_PC4_AF3 +#define FDCAN1_RX_PD0_AF3 +#define FDCAN1_RX_PD12_AF3 +#define FDCAN1_TX_PA12_AF3 +#define FDCAN1_TX_PB9_AF3 +#define FDCAN1_TX_PC5_AF3 +#define FDCAN1_TX_PD13_AF3 +#define FDCAN1_TX_PD1_AF3 +#define FDCAN2_RX_PB0_AF3 +#define FDCAN2_RX_PB12_AF3 +#define FDCAN2_RX_PB5_AF3 +#define FDCAN2_RX_PC2_AF3 +#define FDCAN2_RX_PD14_AF3 +#define FDCAN2_TX_PB13_AF3 +#define FDCAN2_TX_PB1_AF3 +#define FDCAN2_TX_PB6_AF3 +#define FDCAN2_TX_PC3_AF3 +#define FDCAN2_TX_PD15_AF3 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) + +#define CAN_MODULE_COUNT (2) + +#define HAL_LL_FDCAN1_GPIO_AF3 (3) +#define HAL_LL_FDCAN2_GPIO_AF3 (3) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (78) +#define DMA_NUM_OF_CHANNELS_FAMILY (78) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (12) +#define DMA_NUM_OF_STREAMS_FAMILY (12) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PB9_AF6 +#define I2C2_SCL_PA11_AF6 +#define I2C2_SCL_PA7_AF8 +#define I2C2_SCL_PA9_AF8 +#define I2C2_SCL_PB10_AF6 +#define I2C2_SCL_PB13_AF6 +#define I2C2_SCL_PB3_AF8 +#define I2C2_SDA_PA10_AF8 +#define I2C2_SDA_PA12_AF6 +#define I2C2_SDA_PA6_AF8 +#define I2C2_SDA_PB11_AF6 +#define I2C2_SDA_PB14_AF6 +#define I2C2_SDA_PB4_AF8 +#define I2C3_SCL_PA7_AF9 +#define I2C3_SCL_PB3_AF6 +#define I2C3_SCL_PC0_AF6 +#define I2C3_SDA_PA6_AF9 +#define I2C3_SDA_PB4_AF6 +#define I2C3_SDA_PC1_AF6 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF6 +#define LPUART1_RX_PB10_AF1 +#define LPUART1_RX_PC0_AF1 +#define LPUART1_TX_PA2_AF6 +#define LPUART1_TX_PB11_AF1 +#define LPUART1_TX_PC1_AF1 +#define LPUART2_RX_PA13_AF10 +#define LPUART2_RX_PB7_AF10 +#define LPUART2_RX_PC1_AF3 +#define LPUART2_RX_PC7_AF3 +#define LPUART2_TX_PA14_AF10 +#define LPUART2_TX_PB6_AF10 +#define LPUART2_TX_PC0_AF3 +#define LPUART2_TX_PC6_AF3 +#define LPUART2_TX_PF2_AF1 +#define USART1_RX_PA10_AF1 +#define USART1_RX_PB7_AF0 +#define USART1_RX_PC5_AF1 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART1_TX_PC4_AF1 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_RX_PD6_AF0 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 +#define USART2_TX_PD5_AF0 +#define USART3_RX_PB0_AF4 +#define USART3_RX_PB11_AF4 +#define USART3_RX_PB9_AF4 +#define USART3_RX_PC11_AF0 +#define USART3_RX_PC5_AF0 +#define USART3_RX_PD9_AF0 +#define USART3_TX_PA5_AF4 +#define USART3_TX_PB10_AF4 +#define USART3_TX_PB2_AF4 +#define USART3_TX_PB8_AF4 +#define USART3_TX_PC10_AF0 +#define USART3_TX_PC4_AF0 +#define USART3_TX_PD8_AF0 +#define USART4_RX_PA1_AF4 +#define USART4_RX_PC11_AF1 +#define USART4_RX_PE9_AF0 +#define USART4_TX_PA0_AF4 +#define USART4_TX_PC10_AF1 +#define USART4_TX_PE8_AF0 +#define USART5_RX_PB1_AF8 +#define USART5_RX_PB4_AF3 +#define USART5_RX_PD2_AF3 +#define USART5_TX_PB0_AF8 +#define USART5_TX_PB3_AF3 +#define USART5_TX_PC12_AF3 +#define USART5_TX_PD3_AF3 +#define USART5_TX_PE10_AF3 +#define USART6_RX_PA5_AF3 +#define USART6_RX_PB9_AF8 +#define USART6_RX_PC1_AF4 +#define USART6_TX_PA4_AF3 +#define USART6_TX_PB8_AF8 +#define USART6_TX_PC0_AF4 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) +#define UART_MODULE_6 (6) + +#define UART_MODULE_COUNT (6) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MISO_PD5_AF1 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_MOSI_PD6_AF1 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI1_SCK_PD8_AF1 +#define SPI2_MISO_PA3_AF0 +#define SPI2_MISO_PA9_AF4 +#define SPI2_MISO_PB14_AF0 +#define SPI2_MISO_PB2_AF1 +#define SPI2_MISO_PB6_AF4 +#define SPI2_MISO_PC2_AF1 +#define SPI2_MISO_PD3_AF1 +#define SPI2_MOSI_PA10_AF0 +#define SPI2_MOSI_PA4_AF1 +#define SPI2_MOSI_PB11_AF0 +#define SPI2_MOSI_PB15_AF0 +#define SPI2_MOSI_PB7_AF1 +#define SPI2_MOSI_PC3_AF1 +#define SPI2_MOSI_PD4_AF1 +#define SPI2_SCK_PA0_AF0 +#define SPI2_SCK_PB10_AF5 +#define SPI2_SCK_PB13_AF0 +#define SPI2_SCK_PB8_AF1 +#define SPI2_SCK_PD1_AF1 +#define SPI3_MISO_PB4_AF9 +#define SPI3_MISO_PC11_AF4 +#define SPI3_MOSI_PB5_AF9 +#define SPI3_MOSI_PC12_AF4 +#define SPI3_SCK_PB3_AF9 +#define SPI3_SCK_PC10_AF4 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF5 +#define LPTIM1_ETR_PC3_AF0 +#define LPTIM2_ETR_PA5_AF5 +#define LPTIM2_ETR_PC3_AF2 +#define LPTIM2_ETR_PD11_AF1 +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PB1_AF0 +#define TIM14_CH1_PC12_AF2 +#define TIM14_CH1_PF0_AF2 +#define TIM15_CH1N_PA1_AF5 +#define TIM15_CH1N_PB13_AF5 +#define TIM15_CH1N_PB15_AF4 +#define TIM15_CH1N_PF1_AF2 +#define TIM15_CH1_PA2_AF5 +#define TIM15_CH1_PB14_AF5 +#define TIM15_CH1_PC1_AF2 +#define TIM15_CH2_PA3_AF5 +#define TIM15_CH2_PB15_AF5 +#define TIM15_CH2_PC2_AF2 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB8_AF2 +#define TIM16_CH1_PD0_AF2 +#define TIM16_CH1_PE0_AF0 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PB9_AF2 +#define TIM17_CH1_PD1_AF2 +#define TIM17_CH1_PE1_AF0 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1N_PB13_AF2 +#define TIM1_CH1N_PD2_AF2 +#define TIM1_CH1N_PE8_AF1 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH1_PC8_AF2 +#define TIM1_CH1_PE9_AF1 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2N_PB14_AF2 +#define TIM1_CH2N_PD3_AF2 +#define TIM1_CH2N_PE10_AF1 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH2_PC9_AF2 +#define TIM1_CH3N_PB15_AF2 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3N_PD4_AF2 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH3_PC10_AF2 +#define TIM1_CH4_PA11_AF2 +#define TIM1_CH4_PC11_AF2 +#define TIM1_ETR_PA12_AF2 +#define TIM1_ETR_PE7_AF1 +#define TIM2_CH1_PA0_AF2 +#define TIM2_CH1_PA15_AF2 +#define TIM2_CH1_PA5_AF2 +#define TIM2_CH1_PC4_AF2 +#define TIM2_CH2_PA1_AF2 +#define TIM2_CH2_PB3_AF2 +#define TIM2_CH2_PC5_AF2 +#define TIM2_CH3_PA2_AF2 +#define TIM2_CH3_PB10_AF2 +#define TIM2_CH3_PC6_AF2 +#define TIM2_CH4_PA3_AF2 +#define TIM2_CH4_PB11_AF2 +#define TIM2_CH4_PC7_AF2 +#define TIM2_ETR_PA0_AF2 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM2_ETR_PC4_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH1_PC6_AF1 +#define TIM3_CH1_PE3_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH2_PC7_AF1 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH3_PC8_AF1 +#define TIM3_CH4_PB1_AF1 +#define TIM3_CH4_PC9_AF1 +#define TIM3_ETR_PD2_AF1 +#define TIM4_CH1_PB6_AF9 +#define TIM4_CH1_PD12_AF2 +#define TIM4_CH2_PB7_AF9 +#define TIM4_CH2_PD13_AF2 +#define TIM4_CH3_PB8_AF9 +#define TIM4_CH3_PD14_AF2 +#define TIM4_CH4_PB9_AF9 +#define TIM4_CH4_PD15_AF2 +#define TIM4_ETR_PE0_AF2 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_14 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +#define TIM1_BUS (1) +#define TIM4_BUS (1) +#define TIM15_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PE0_CN +#define __PE1_CN +#define __PE10_CN +#define __PE3_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PF2_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN + +#define PORT_COUNT (6) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +#define UART3_IVT (29) +#define UART3_NVIC (45) +#define UART4_IVT (29) +#define UART4_NVIC (45) +#define UART5_IVT (29) +#define UART5_NVIC (45) +#define UART6_IVT (29) +#define UART6_NVIC (45) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1MC/LQFP80/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1MC/LQFP80/mcu_definitions.h new file mode 100644 index 000000000..bf50194c0 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1MC/LQFP80/mcu_definitions.h @@ -0,0 +1,487 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G0B1MC_LQFP80. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PB0_CH8 +#define ADC1_PB10_CH11 +#define ADC1_PB11_CH15 +#define ADC1_PB12_CH16 +#define ADC1_PB1_CH9 +#define ADC1_PB2_CH10 +#define ADC1_PC4_CH17 +#define ADC1_PC5_CH18 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF3 +#define FDCAN1_RX_PB8_AF3 +#define FDCAN1_RX_PC4_AF3 +#define FDCAN1_RX_PD0_AF3 +#define FDCAN1_RX_PD12_AF3 +#define FDCAN1_TX_PA12_AF3 +#define FDCAN1_TX_PB9_AF3 +#define FDCAN1_TX_PC5_AF3 +#define FDCAN1_TX_PD13_AF3 +#define FDCAN1_TX_PD1_AF3 +#define FDCAN2_RX_PB0_AF3 +#define FDCAN2_RX_PB12_AF3 +#define FDCAN2_RX_PB5_AF3 +#define FDCAN2_RX_PC2_AF3 +#define FDCAN2_RX_PD14_AF3 +#define FDCAN2_TX_PB13_AF3 +#define FDCAN2_TX_PB1_AF3 +#define FDCAN2_TX_PB6_AF3 +#define FDCAN2_TX_PC3_AF3 +#define FDCAN2_TX_PD15_AF3 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) + +#define CAN_MODULE_COUNT (2) + +#define HAL_LL_FDCAN1_GPIO_AF3 (3) +#define HAL_LL_FDCAN2_GPIO_AF3 (3) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (78) +#define DMA_NUM_OF_CHANNELS_FAMILY (78) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (12) +#define DMA_NUM_OF_STREAMS_FAMILY (12) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PB9_AF6 +#define I2C2_SCL_PA11_AF6 +#define I2C2_SCL_PA7_AF8 +#define I2C2_SCL_PA9_AF8 +#define I2C2_SCL_PB10_AF6 +#define I2C2_SCL_PB13_AF6 +#define I2C2_SCL_PB3_AF8 +#define I2C2_SDA_PA10_AF8 +#define I2C2_SDA_PA12_AF6 +#define I2C2_SDA_PA6_AF8 +#define I2C2_SDA_PB11_AF6 +#define I2C2_SDA_PB14_AF6 +#define I2C2_SDA_PB4_AF8 +#define I2C3_SCL_PA7_AF9 +#define I2C3_SCL_PB3_AF6 +#define I2C3_SCL_PC0_AF6 +#define I2C3_SDA_PA6_AF9 +#define I2C3_SDA_PB4_AF6 +#define I2C3_SDA_PC1_AF6 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF6 +#define LPUART1_RX_PB10_AF1 +#define LPUART1_RX_PC0_AF1 +#define LPUART1_TX_PA2_AF6 +#define LPUART1_TX_PB11_AF1 +#define LPUART1_TX_PC1_AF1 +#define LPUART2_RX_PA13_AF10 +#define LPUART2_RX_PB7_AF10 +#define LPUART2_RX_PC1_AF3 +#define LPUART2_RX_PC7_AF3 +#define LPUART2_TX_PA14_AF10 +#define LPUART2_TX_PB6_AF10 +#define LPUART2_TX_PC0_AF3 +#define LPUART2_TX_PC6_AF3 +#define LPUART2_TX_PF2_AF1 +#define USART1_RX_PA10_AF1 +#define USART1_RX_PB7_AF0 +#define USART1_RX_PC5_AF1 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART1_TX_PC4_AF1 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_RX_PD6_AF0 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 +#define USART2_TX_PD5_AF0 +#define USART3_RX_PB0_AF4 +#define USART3_RX_PB11_AF4 +#define USART3_RX_PB9_AF4 +#define USART3_RX_PC11_AF0 +#define USART3_RX_PC5_AF0 +#define USART3_RX_PD9_AF0 +#define USART3_TX_PA5_AF4 +#define USART3_TX_PB10_AF4 +#define USART3_TX_PB2_AF4 +#define USART3_TX_PB8_AF4 +#define USART3_TX_PC10_AF0 +#define USART3_TX_PC4_AF0 +#define USART3_TX_PD8_AF0 +#define USART4_RX_PA1_AF4 +#define USART4_RX_PC11_AF1 +#define USART4_RX_PE9_AF0 +#define USART4_TX_PA0_AF4 +#define USART4_TX_PC10_AF1 +#define USART4_TX_PE8_AF0 +#define USART5_RX_PB1_AF8 +#define USART5_RX_PB4_AF3 +#define USART5_RX_PD2_AF3 +#define USART5_TX_PB0_AF8 +#define USART5_TX_PB3_AF3 +#define USART5_TX_PC12_AF3 +#define USART5_TX_PD3_AF3 +#define USART5_TX_PE10_AF3 +#define USART6_RX_PA5_AF3 +#define USART6_RX_PB9_AF8 +#define USART6_RX_PC1_AF4 +#define USART6_TX_PA4_AF3 +#define USART6_TX_PB8_AF8 +#define USART6_TX_PC0_AF4 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) +#define UART_MODULE_6 (6) + +#define UART_MODULE_COUNT (6) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MISO_PD5_AF1 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_MOSI_PD6_AF1 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI1_SCK_PD8_AF1 +#define SPI2_MISO_PA3_AF0 +#define SPI2_MISO_PA9_AF4 +#define SPI2_MISO_PB14_AF0 +#define SPI2_MISO_PB2_AF1 +#define SPI2_MISO_PB6_AF4 +#define SPI2_MISO_PC2_AF1 +#define SPI2_MISO_PD3_AF1 +#define SPI2_MOSI_PA10_AF0 +#define SPI2_MOSI_PA4_AF1 +#define SPI2_MOSI_PB11_AF0 +#define SPI2_MOSI_PB15_AF0 +#define SPI2_MOSI_PB7_AF1 +#define SPI2_MOSI_PC3_AF1 +#define SPI2_MOSI_PD4_AF1 +#define SPI2_SCK_PA0_AF0 +#define SPI2_SCK_PB10_AF5 +#define SPI2_SCK_PB13_AF0 +#define SPI2_SCK_PB8_AF1 +#define SPI2_SCK_PD1_AF1 +#define SPI3_MISO_PB4_AF9 +#define SPI3_MISO_PC11_AF4 +#define SPI3_MOSI_PB5_AF9 +#define SPI3_MOSI_PC12_AF4 +#define SPI3_SCK_PB3_AF9 +#define SPI3_SCK_PC10_AF4 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF5 +#define LPTIM1_ETR_PC3_AF0 +#define LPTIM2_ETR_PA5_AF5 +#define LPTIM2_ETR_PC3_AF2 +#define LPTIM2_ETR_PD11_AF1 +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PB1_AF0 +#define TIM14_CH1_PC12_AF2 +#define TIM14_CH1_PF0_AF2 +#define TIM15_CH1N_PA1_AF5 +#define TIM15_CH1N_PB13_AF5 +#define TIM15_CH1N_PB15_AF4 +#define TIM15_CH1N_PF1_AF2 +#define TIM15_CH1_PA2_AF5 +#define TIM15_CH1_PB14_AF5 +#define TIM15_CH1_PC1_AF2 +#define TIM15_CH2_PA3_AF5 +#define TIM15_CH2_PB15_AF5 +#define TIM15_CH2_PC2_AF2 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB8_AF2 +#define TIM16_CH1_PD0_AF2 +#define TIM16_CH1_PE0_AF0 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PB9_AF2 +#define TIM17_CH1_PD1_AF2 +#define TIM17_CH1_PE1_AF0 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1N_PB13_AF2 +#define TIM1_CH1N_PD2_AF2 +#define TIM1_CH1N_PE8_AF1 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH1_PC8_AF2 +#define TIM1_CH1_PE9_AF1 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2N_PB14_AF2 +#define TIM1_CH2N_PD3_AF2 +#define TIM1_CH2N_PE10_AF1 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH2_PC9_AF2 +#define TIM1_CH3N_PB15_AF2 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3N_PD4_AF2 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH3_PC10_AF2 +#define TIM1_CH4_PA11_AF2 +#define TIM1_CH4_PC11_AF2 +#define TIM1_ETR_PA12_AF2 +#define TIM1_ETR_PE7_AF1 +#define TIM2_CH1_PA0_AF2 +#define TIM2_CH1_PA15_AF2 +#define TIM2_CH1_PA5_AF2 +#define TIM2_CH1_PC4_AF2 +#define TIM2_CH2_PA1_AF2 +#define TIM2_CH2_PB3_AF2 +#define TIM2_CH2_PC5_AF2 +#define TIM2_CH3_PA2_AF2 +#define TIM2_CH3_PB10_AF2 +#define TIM2_CH3_PC6_AF2 +#define TIM2_CH4_PA3_AF2 +#define TIM2_CH4_PB11_AF2 +#define TIM2_CH4_PC7_AF2 +#define TIM2_ETR_PA0_AF2 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM2_ETR_PC4_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH1_PC6_AF1 +#define TIM3_CH1_PE3_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH2_PC7_AF1 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH3_PC8_AF1 +#define TIM3_CH4_PB1_AF1 +#define TIM3_CH4_PC9_AF1 +#define TIM3_ETR_PD2_AF1 +#define TIM4_CH1_PB6_AF9 +#define TIM4_CH1_PD12_AF2 +#define TIM4_CH2_PB7_AF9 +#define TIM4_CH2_PD13_AF2 +#define TIM4_CH3_PB8_AF9 +#define TIM4_CH3_PD14_AF2 +#define TIM4_CH4_PB9_AF9 +#define TIM4_CH4_PD15_AF2 +#define TIM4_ETR_PE0_AF2 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_14 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +#define TIM1_BUS (1) +#define TIM4_BUS (1) +#define TIM15_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PE0_CN +#define __PE1_CN +#define __PE10_CN +#define __PE3_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PF2_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN + +#define PORT_COUNT (6) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +#define UART3_IVT (29) +#define UART3_NVIC (45) +#define UART4_IVT (29) +#define UART4_NVIC (45) +#define UART5_IVT (29) +#define UART5_NVIC (45) +#define UART6_IVT (29) +#define UART6_NVIC (45) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1ME/LQFP80/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1ME/LQFP80/mcu_definitions.h new file mode 100644 index 000000000..fc0fcf45e --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1ME/LQFP80/mcu_definitions.h @@ -0,0 +1,487 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G0B1ME_LQFP80. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PB0_CH8 +#define ADC1_PB10_CH11 +#define ADC1_PB11_CH15 +#define ADC1_PB12_CH16 +#define ADC1_PB1_CH9 +#define ADC1_PB2_CH10 +#define ADC1_PC4_CH17 +#define ADC1_PC5_CH18 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF3 +#define FDCAN1_RX_PB8_AF3 +#define FDCAN1_RX_PC4_AF3 +#define FDCAN1_RX_PD0_AF3 +#define FDCAN1_RX_PD12_AF3 +#define FDCAN1_TX_PA12_AF3 +#define FDCAN1_TX_PB9_AF3 +#define FDCAN1_TX_PC5_AF3 +#define FDCAN1_TX_PD13_AF3 +#define FDCAN1_TX_PD1_AF3 +#define FDCAN2_RX_PB0_AF3 +#define FDCAN2_RX_PB12_AF3 +#define FDCAN2_RX_PB5_AF3 +#define FDCAN2_RX_PC2_AF3 +#define FDCAN2_RX_PD14_AF3 +#define FDCAN2_TX_PB13_AF3 +#define FDCAN2_TX_PB1_AF3 +#define FDCAN2_TX_PB6_AF3 +#define FDCAN2_TX_PC3_AF3 +#define FDCAN2_TX_PD15_AF3 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) + +#define CAN_MODULE_COUNT (2) + +#define HAL_LL_FDCAN1_GPIO_AF3 (3) +#define HAL_LL_FDCAN2_GPIO_AF3 (3) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (78) +#define DMA_NUM_OF_CHANNELS_FAMILY (78) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (12) +#define DMA_NUM_OF_STREAMS_FAMILY (12) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PB9_AF6 +#define I2C2_SCL_PA11_AF6 +#define I2C2_SCL_PA7_AF8 +#define I2C2_SCL_PA9_AF8 +#define I2C2_SCL_PB10_AF6 +#define I2C2_SCL_PB13_AF6 +#define I2C2_SCL_PB3_AF8 +#define I2C2_SDA_PA10_AF8 +#define I2C2_SDA_PA12_AF6 +#define I2C2_SDA_PA6_AF8 +#define I2C2_SDA_PB11_AF6 +#define I2C2_SDA_PB14_AF6 +#define I2C2_SDA_PB4_AF8 +#define I2C3_SCL_PA7_AF9 +#define I2C3_SCL_PB3_AF6 +#define I2C3_SCL_PC0_AF6 +#define I2C3_SDA_PA6_AF9 +#define I2C3_SDA_PB4_AF6 +#define I2C3_SDA_PC1_AF6 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF6 +#define LPUART1_RX_PB10_AF1 +#define LPUART1_RX_PC0_AF1 +#define LPUART1_TX_PA2_AF6 +#define LPUART1_TX_PB11_AF1 +#define LPUART1_TX_PC1_AF1 +#define LPUART2_RX_PA13_AF10 +#define LPUART2_RX_PB7_AF10 +#define LPUART2_RX_PC1_AF3 +#define LPUART2_RX_PC7_AF3 +#define LPUART2_TX_PA14_AF10 +#define LPUART2_TX_PB6_AF10 +#define LPUART2_TX_PC0_AF3 +#define LPUART2_TX_PC6_AF3 +#define LPUART2_TX_PF2_AF1 +#define USART1_RX_PA10_AF1 +#define USART1_RX_PB7_AF0 +#define USART1_RX_PC5_AF1 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART1_TX_PC4_AF1 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_RX_PD6_AF0 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 +#define USART2_TX_PD5_AF0 +#define USART3_RX_PB0_AF4 +#define USART3_RX_PB11_AF4 +#define USART3_RX_PB9_AF4 +#define USART3_RX_PC11_AF0 +#define USART3_RX_PC5_AF0 +#define USART3_RX_PD9_AF0 +#define USART3_TX_PA5_AF4 +#define USART3_TX_PB10_AF4 +#define USART3_TX_PB2_AF4 +#define USART3_TX_PB8_AF4 +#define USART3_TX_PC10_AF0 +#define USART3_TX_PC4_AF0 +#define USART3_TX_PD8_AF0 +#define USART4_RX_PA1_AF4 +#define USART4_RX_PC11_AF1 +#define USART4_RX_PE9_AF0 +#define USART4_TX_PA0_AF4 +#define USART4_TX_PC10_AF1 +#define USART4_TX_PE8_AF0 +#define USART5_RX_PB1_AF8 +#define USART5_RX_PB4_AF3 +#define USART5_RX_PD2_AF3 +#define USART5_TX_PB0_AF8 +#define USART5_TX_PB3_AF3 +#define USART5_TX_PC12_AF3 +#define USART5_TX_PD3_AF3 +#define USART5_TX_PE10_AF3 +#define USART6_RX_PA5_AF3 +#define USART6_RX_PB9_AF8 +#define USART6_RX_PC1_AF4 +#define USART6_TX_PA4_AF3 +#define USART6_TX_PB8_AF8 +#define USART6_TX_PC0_AF4 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) +#define UART_MODULE_6 (6) + +#define UART_MODULE_COUNT (6) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MISO_PD5_AF1 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_MOSI_PD6_AF1 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI1_SCK_PD8_AF1 +#define SPI2_MISO_PA3_AF0 +#define SPI2_MISO_PA9_AF4 +#define SPI2_MISO_PB14_AF0 +#define SPI2_MISO_PB2_AF1 +#define SPI2_MISO_PB6_AF4 +#define SPI2_MISO_PC2_AF1 +#define SPI2_MISO_PD3_AF1 +#define SPI2_MOSI_PA10_AF0 +#define SPI2_MOSI_PA4_AF1 +#define SPI2_MOSI_PB11_AF0 +#define SPI2_MOSI_PB15_AF0 +#define SPI2_MOSI_PB7_AF1 +#define SPI2_MOSI_PC3_AF1 +#define SPI2_MOSI_PD4_AF1 +#define SPI2_SCK_PA0_AF0 +#define SPI2_SCK_PB10_AF5 +#define SPI2_SCK_PB13_AF0 +#define SPI2_SCK_PB8_AF1 +#define SPI2_SCK_PD1_AF1 +#define SPI3_MISO_PB4_AF9 +#define SPI3_MISO_PC11_AF4 +#define SPI3_MOSI_PB5_AF9 +#define SPI3_MOSI_PC12_AF4 +#define SPI3_SCK_PB3_AF9 +#define SPI3_SCK_PC10_AF4 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF5 +#define LPTIM1_ETR_PC3_AF0 +#define LPTIM2_ETR_PA5_AF5 +#define LPTIM2_ETR_PC3_AF2 +#define LPTIM2_ETR_PD11_AF1 +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PB1_AF0 +#define TIM14_CH1_PC12_AF2 +#define TIM14_CH1_PF0_AF2 +#define TIM15_CH1N_PA1_AF5 +#define TIM15_CH1N_PB13_AF5 +#define TIM15_CH1N_PB15_AF4 +#define TIM15_CH1N_PF1_AF2 +#define TIM15_CH1_PA2_AF5 +#define TIM15_CH1_PB14_AF5 +#define TIM15_CH1_PC1_AF2 +#define TIM15_CH2_PA3_AF5 +#define TIM15_CH2_PB15_AF5 +#define TIM15_CH2_PC2_AF2 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB8_AF2 +#define TIM16_CH1_PD0_AF2 +#define TIM16_CH1_PE0_AF0 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PB9_AF2 +#define TIM17_CH1_PD1_AF2 +#define TIM17_CH1_PE1_AF0 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1N_PB13_AF2 +#define TIM1_CH1N_PD2_AF2 +#define TIM1_CH1N_PE8_AF1 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH1_PC8_AF2 +#define TIM1_CH1_PE9_AF1 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2N_PB14_AF2 +#define TIM1_CH2N_PD3_AF2 +#define TIM1_CH2N_PE10_AF1 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH2_PC9_AF2 +#define TIM1_CH3N_PB15_AF2 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3N_PD4_AF2 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH3_PC10_AF2 +#define TIM1_CH4_PA11_AF2 +#define TIM1_CH4_PC11_AF2 +#define TIM1_ETR_PA12_AF2 +#define TIM1_ETR_PE7_AF1 +#define TIM2_CH1_PA0_AF2 +#define TIM2_CH1_PA15_AF2 +#define TIM2_CH1_PA5_AF2 +#define TIM2_CH1_PC4_AF2 +#define TIM2_CH2_PA1_AF2 +#define TIM2_CH2_PB3_AF2 +#define TIM2_CH2_PC5_AF2 +#define TIM2_CH3_PA2_AF2 +#define TIM2_CH3_PB10_AF2 +#define TIM2_CH3_PC6_AF2 +#define TIM2_CH4_PA3_AF2 +#define TIM2_CH4_PB11_AF2 +#define TIM2_CH4_PC7_AF2 +#define TIM2_ETR_PA0_AF2 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM2_ETR_PC4_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH1_PC6_AF1 +#define TIM3_CH1_PE3_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH2_PC7_AF1 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH3_PC8_AF1 +#define TIM3_CH4_PB1_AF1 +#define TIM3_CH4_PC9_AF1 +#define TIM3_ETR_PD2_AF1 +#define TIM4_CH1_PB6_AF9 +#define TIM4_CH1_PD12_AF2 +#define TIM4_CH2_PB7_AF9 +#define TIM4_CH2_PD13_AF2 +#define TIM4_CH3_PB8_AF9 +#define TIM4_CH3_PD14_AF2 +#define TIM4_CH4_PB9_AF9 +#define TIM4_CH4_PD15_AF2 +#define TIM4_ETR_PE0_AF2 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_14 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +#define TIM1_BUS (1) +#define TIM4_BUS (1) +#define TIM15_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PE0_CN +#define __PE1_CN +#define __PE10_CN +#define __PE3_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PF2_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN + +#define PORT_COUNT (6) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +#define UART3_IVT (29) +#define UART3_NVIC (45) +#define UART4_IVT (29) +#define UART4_NVIC (45) +#define UART5_IVT (29) +#define UART5_NVIC (45) +#define UART6_IVT (29) +#define UART6_NVIC (45) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1NE/WLCSP52/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1NE/WLCSP52/mcu_definitions.h new file mode 100644 index 000000000..f92ea25cc --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1NE/WLCSP52/mcu_definitions.h @@ -0,0 +1,398 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G0B1NE_WLCSP52. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PB0_CH8 +#define ADC1_PB10_CH11 +#define ADC1_PB11_CH15 +#define ADC1_PB12_CH16 +#define ADC1_PB1_CH9 +#define ADC1_PB2_CH10 +#define ADC1_PC4_CH17 +#define ADC1_PC5_CH18 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF3 +#define FDCAN1_RX_PB8_AF3 +#define FDCAN1_RX_PC4_AF3 +#define FDCAN1_RX_PD0_AF3 +#define FDCAN1_TX_PA12_AF3 +#define FDCAN1_TX_PB9_AF3 +#define FDCAN1_TX_PC5_AF3 +#define FDCAN1_TX_PD1_AF3 +#define FDCAN2_RX_PB0_AF3 +#define FDCAN2_RX_PB12_AF3 +#define FDCAN2_RX_PB5_AF3 +#define FDCAN2_TX_PB13_AF3 +#define FDCAN2_TX_PB1_AF3 +#define FDCAN2_TX_PB6_AF3 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) + +#define CAN_MODULE_COUNT (2) + +#define HAL_LL_FDCAN1_GPIO_AF3 (3) +#define HAL_LL_FDCAN2_GPIO_AF3 (3) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (78) +#define DMA_NUM_OF_CHANNELS_FAMILY (78) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (12) +#define DMA_NUM_OF_STREAMS_FAMILY (12) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PB9_AF6 +#define I2C2_SCL_PA11_AF6 +#define I2C2_SCL_PA7_AF8 +#define I2C2_SCL_PA9_AF8 +#define I2C2_SCL_PB10_AF6 +#define I2C2_SCL_PB13_AF6 +#define I2C2_SCL_PB3_AF8 +#define I2C2_SDA_PA10_AF8 +#define I2C2_SDA_PA12_AF6 +#define I2C2_SDA_PA6_AF8 +#define I2C2_SDA_PB11_AF6 +#define I2C2_SDA_PB14_AF6 +#define I2C2_SDA_PB4_AF8 +#define I2C3_SCL_PA7_AF9 +#define I2C3_SCL_PB3_AF6 +#define I2C3_SDA_PA6_AF9 +#define I2C3_SDA_PB4_AF6 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF6 +#define LPUART1_RX_PB10_AF1 +#define LPUART1_TX_PA2_AF6 +#define LPUART1_TX_PB11_AF1 +#define LPUART2_RX_PA13_AF10 +#define LPUART2_RX_PB7_AF10 +#define LPUART2_RX_PC7_AF3 +#define LPUART2_TX_PA14_AF10 +#define LPUART2_TX_PB6_AF10 +#define LPUART2_TX_PC6_AF3 +#define LPUART2_TX_PF2_AF1 +#define USART1_RX_PA10_AF1 +#define USART1_RX_PB7_AF0 +#define USART1_RX_PC5_AF1 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART1_TX_PC4_AF1 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 +#define USART3_RX_PB0_AF4 +#define USART3_RX_PB11_AF4 +#define USART3_RX_PB9_AF4 +#define USART3_RX_PC5_AF0 +#define USART3_TX_PA5_AF4 +#define USART3_TX_PB10_AF4 +#define USART3_TX_PB2_AF4 +#define USART3_TX_PB8_AF4 +#define USART3_TX_PC4_AF0 +#define USART4_RX_PA1_AF4 +#define USART4_TX_PA0_AF4 +#define USART5_RX_PB1_AF8 +#define USART5_RX_PB4_AF3 +#define USART5_RX_PD2_AF3 +#define USART5_TX_PB0_AF8 +#define USART5_TX_PB3_AF3 +#define USART5_TX_PD3_AF3 +#define USART6_RX_PA5_AF3 +#define USART6_RX_PB9_AF8 +#define USART6_TX_PA4_AF3 +#define USART6_TX_PB8_AF8 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) +#define UART_MODULE_6 (6) + +#define UART_MODULE_COUNT (6) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI2_MISO_PA3_AF0 +#define SPI2_MISO_PA9_AF4 +#define SPI2_MISO_PB14_AF0 +#define SPI2_MISO_PB2_AF1 +#define SPI2_MISO_PB6_AF4 +#define SPI2_MISO_PD3_AF1 +#define SPI2_MOSI_PA10_AF0 +#define SPI2_MOSI_PA4_AF1 +#define SPI2_MOSI_PB11_AF0 +#define SPI2_MOSI_PB15_AF0 +#define SPI2_MOSI_PB7_AF1 +#define SPI2_SCK_PA0_AF0 +#define SPI2_SCK_PB10_AF5 +#define SPI2_SCK_PB13_AF0 +#define SPI2_SCK_PB8_AF1 +#define SPI2_SCK_PD1_AF1 +#define SPI3_MISO_PB4_AF9 +#define SPI3_MOSI_PB5_AF9 +#define SPI3_SCK_PB3_AF9 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF5 +#define LPTIM2_ETR_PA5_AF5 +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PB1_AF0 +#define TIM14_CH1_PF0_AF2 +#define TIM15_CH1N_PA1_AF5 +#define TIM15_CH1N_PB13_AF5 +#define TIM15_CH1N_PB15_AF4 +#define TIM15_CH1N_PF1_AF2 +#define TIM15_CH1_PA2_AF5 +#define TIM15_CH1_PB14_AF5 +#define TIM15_CH2_PA3_AF5 +#define TIM15_CH2_PB15_AF5 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB8_AF2 +#define TIM16_CH1_PD0_AF2 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PB9_AF2 +#define TIM17_CH1_PD1_AF2 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1N_PB13_AF2 +#define TIM1_CH1N_PD2_AF2 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2N_PB14_AF2 +#define TIM1_CH2N_PD3_AF2 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH3N_PB15_AF2 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_ETR_PA12_AF2 +#define TIM2_CH1_PA0_AF2 +#define TIM2_CH1_PA15_AF2 +#define TIM2_CH1_PA5_AF2 +#define TIM2_CH1_PC4_AF2 +#define TIM2_CH2_PA1_AF2 +#define TIM2_CH2_PB3_AF2 +#define TIM2_CH2_PC5_AF2 +#define TIM2_CH3_PA2_AF2 +#define TIM2_CH3_PB10_AF2 +#define TIM2_CH3_PC6_AF2 +#define TIM2_CH4_PA3_AF2 +#define TIM2_CH4_PB11_AF2 +#define TIM2_CH4_PC7_AF2 +#define TIM2_ETR_PA0_AF2 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM2_ETR_PC4_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH1_PC6_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH2_PC7_AF1 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH4_PB1_AF1 +#define TIM3_ETR_PD2_AF1 +#define TIM4_CH1_PB6_AF9 +#define TIM4_CH2_PB7_AF9 +#define TIM4_CH3_PB8_AF9 +#define TIM4_CH4_PB9_AF9 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_14 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +#define TIM1_BUS (1) +#define TIM4_BUS (1) +#define TIM15_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PF0_CN +#define __PF1_CN +#define __PF2_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_F_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +#define UART3_IVT (29) +#define UART3_NVIC (45) +#define UART4_IVT (29) +#define UART4_NVIC (45) +#define UART5_IVT (29) +#define UART5_NVIC (45) +#define UART6_IVT (29) +#define UART6_NVIC (45) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1RB/LQFP64/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1RB/LQFP64/mcu_definitions.h new file mode 100644 index 000000000..361d53e46 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1RB/LQFP64/mcu_definitions.h @@ -0,0 +1,452 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G0B1RB_LQFP64. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PB0_CH8 +#define ADC1_PB10_CH11 +#define ADC1_PB11_CH15 +#define ADC1_PB12_CH16 +#define ADC1_PB1_CH9 +#define ADC1_PB2_CH10 +#define ADC1_PC4_CH17 +#define ADC1_PC5_CH18 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF3 +#define FDCAN1_RX_PB8_AF3 +#define FDCAN1_RX_PC4_AF3 +#define FDCAN1_RX_PD0_AF3 +#define FDCAN1_TX_PA12_AF3 +#define FDCAN1_TX_PB9_AF3 +#define FDCAN1_TX_PC5_AF3 +#define FDCAN1_TX_PD1_AF3 +#define FDCAN2_RX_PB0_AF3 +#define FDCAN2_RX_PB12_AF3 +#define FDCAN2_RX_PB5_AF3 +#define FDCAN2_RX_PC2_AF3 +#define FDCAN2_TX_PB13_AF3 +#define FDCAN2_TX_PB1_AF3 +#define FDCAN2_TX_PB6_AF3 +#define FDCAN2_TX_PC3_AF3 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) + +#define CAN_MODULE_COUNT (2) + +#define HAL_LL_FDCAN1_GPIO_AF3 (3) +#define HAL_LL_FDCAN2_GPIO_AF3 (3) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (78) +#define DMA_NUM_OF_CHANNELS_FAMILY (78) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (12) +#define DMA_NUM_OF_STREAMS_FAMILY (12) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PB9_AF6 +#define I2C2_SCL_PA11_AF6 +#define I2C2_SCL_PA7_AF8 +#define I2C2_SCL_PA9_AF8 +#define I2C2_SCL_PB10_AF6 +#define I2C2_SCL_PB13_AF6 +#define I2C2_SCL_PB3_AF8 +#define I2C2_SDA_PA10_AF8 +#define I2C2_SDA_PA12_AF6 +#define I2C2_SDA_PA6_AF8 +#define I2C2_SDA_PB11_AF6 +#define I2C2_SDA_PB14_AF6 +#define I2C2_SDA_PB4_AF8 +#define I2C3_SCL_PA7_AF9 +#define I2C3_SCL_PB3_AF6 +#define I2C3_SCL_PC0_AF6 +#define I2C3_SDA_PA6_AF9 +#define I2C3_SDA_PB4_AF6 +#define I2C3_SDA_PC1_AF6 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF6 +#define LPUART1_RX_PB10_AF1 +#define LPUART1_RX_PC0_AF1 +#define LPUART1_TX_PA2_AF6 +#define LPUART1_TX_PB11_AF1 +#define LPUART1_TX_PC1_AF1 +#define LPUART2_RX_PA13_AF10 +#define LPUART2_RX_PB7_AF10 +#define LPUART2_RX_PC1_AF3 +#define LPUART2_RX_PC7_AF3 +#define LPUART2_TX_PA14_AF10 +#define LPUART2_TX_PB6_AF10 +#define LPUART2_TX_PC0_AF3 +#define LPUART2_TX_PC6_AF3 +#define LPUART2_TX_PF2_AF1 +#define USART1_RX_PA10_AF1 +#define USART1_RX_PB7_AF0 +#define USART1_RX_PC5_AF1 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART1_TX_PC4_AF1 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_RX_PD6_AF0 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 +#define USART2_TX_PD5_AF0 +#define USART3_RX_PB0_AF4 +#define USART3_RX_PB11_AF4 +#define USART3_RX_PB9_AF4 +#define USART3_RX_PC11_AF0 +#define USART3_RX_PC5_AF0 +#define USART3_RX_PD9_AF0 +#define USART3_TX_PA5_AF4 +#define USART3_TX_PB10_AF4 +#define USART3_TX_PB2_AF4 +#define USART3_TX_PB8_AF4 +#define USART3_TX_PC10_AF0 +#define USART3_TX_PC4_AF0 +#define USART3_TX_PD8_AF0 +#define USART4_RX_PA1_AF4 +#define USART4_RX_PC11_AF1 +#define USART4_TX_PA0_AF4 +#define USART4_TX_PC10_AF1 +#define USART5_RX_PB1_AF8 +#define USART5_RX_PB4_AF3 +#define USART5_RX_PD2_AF3 +#define USART5_TX_PB0_AF8 +#define USART5_TX_PB3_AF3 +#define USART5_TX_PC12_AF3 +#define USART5_TX_PD3_AF3 +#define USART6_RX_PA5_AF3 +#define USART6_RX_PB9_AF8 +#define USART6_RX_PC1_AF4 +#define USART6_TX_PA4_AF3 +#define USART6_TX_PB8_AF8 +#define USART6_TX_PC0_AF4 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) +#define UART_MODULE_6 (6) + +#define UART_MODULE_COUNT (6) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MISO_PD5_AF1 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_MOSI_PD6_AF1 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI1_SCK_PD8_AF1 +#define SPI2_MISO_PA3_AF0 +#define SPI2_MISO_PA9_AF4 +#define SPI2_MISO_PB14_AF0 +#define SPI2_MISO_PB2_AF1 +#define SPI2_MISO_PB6_AF4 +#define SPI2_MISO_PC2_AF1 +#define SPI2_MISO_PD3_AF1 +#define SPI2_MOSI_PA10_AF0 +#define SPI2_MOSI_PA4_AF1 +#define SPI2_MOSI_PB11_AF0 +#define SPI2_MOSI_PB15_AF0 +#define SPI2_MOSI_PB7_AF1 +#define SPI2_MOSI_PC3_AF1 +#define SPI2_MOSI_PD4_AF1 +#define SPI2_SCK_PA0_AF0 +#define SPI2_SCK_PB10_AF5 +#define SPI2_SCK_PB13_AF0 +#define SPI2_SCK_PB8_AF1 +#define SPI2_SCK_PD1_AF1 +#define SPI3_MISO_PB4_AF9 +#define SPI3_MISO_PC11_AF4 +#define SPI3_MOSI_PB5_AF9 +#define SPI3_MOSI_PC12_AF4 +#define SPI3_SCK_PB3_AF9 +#define SPI3_SCK_PC10_AF4 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF5 +#define LPTIM1_ETR_PC3_AF0 +#define LPTIM2_ETR_PA5_AF5 +#define LPTIM2_ETR_PC3_AF2 +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PB1_AF0 +#define TIM14_CH1_PC12_AF2 +#define TIM14_CH1_PF0_AF2 +#define TIM15_CH1N_PA1_AF5 +#define TIM15_CH1N_PB13_AF5 +#define TIM15_CH1N_PB15_AF4 +#define TIM15_CH1N_PF1_AF2 +#define TIM15_CH1_PA2_AF5 +#define TIM15_CH1_PB14_AF5 +#define TIM15_CH1_PC1_AF2 +#define TIM15_CH2_PA3_AF5 +#define TIM15_CH2_PB15_AF5 +#define TIM15_CH2_PC2_AF2 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB8_AF2 +#define TIM16_CH1_PD0_AF2 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PB9_AF2 +#define TIM17_CH1_PD1_AF2 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1N_PB13_AF2 +#define TIM1_CH1N_PD2_AF2 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH1_PC8_AF2 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2N_PB14_AF2 +#define TIM1_CH2N_PD3_AF2 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH2_PC9_AF2 +#define TIM1_CH3N_PB15_AF2 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3N_PD4_AF2 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH3_PC10_AF2 +#define TIM1_CH4_PA11_AF2 +#define TIM1_CH4_PC11_AF2 +#define TIM1_ETR_PA12_AF2 +#define TIM2_CH1_PA0_AF2 +#define TIM2_CH1_PA15_AF2 +#define TIM2_CH1_PA5_AF2 +#define TIM2_CH1_PC4_AF2 +#define TIM2_CH2_PA1_AF2 +#define TIM2_CH2_PB3_AF2 +#define TIM2_CH2_PC5_AF2 +#define TIM2_CH3_PA2_AF2 +#define TIM2_CH3_PB10_AF2 +#define TIM2_CH3_PC6_AF2 +#define TIM2_CH4_PA3_AF2 +#define TIM2_CH4_PB11_AF2 +#define TIM2_CH4_PC7_AF2 +#define TIM2_ETR_PA0_AF2 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM2_ETR_PC4_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH1_PC6_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH2_PC7_AF1 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH3_PC8_AF1 +#define TIM3_CH4_PB1_AF1 +#define TIM3_CH4_PC9_AF1 +#define TIM3_ETR_PD2_AF1 +#define TIM4_CH1_PB6_AF9 +#define TIM4_CH2_PB7_AF9 +#define TIM4_CH3_PB8_AF9 +#define TIM4_CH4_PB9_AF9 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_14 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +#define TIM1_BUS (1) +#define TIM4_BUS (1) +#define TIM15_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD8_CN +#define __PD9_CN +#define __PF0_CN +#define __PF1_CN +#define __PF2_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_F_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +#define UART3_IVT (29) +#define UART3_NVIC (45) +#define UART4_IVT (29) +#define UART4_NVIC (45) +#define UART5_IVT (29) +#define UART5_NVIC (45) +#define UART6_IVT (29) +#define UART6_NVIC (45) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1RC/LQFP64/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1RC/LQFP64/mcu_definitions.h new file mode 100644 index 000000000..810c8d875 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1RC/LQFP64/mcu_definitions.h @@ -0,0 +1,452 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G0B1RC_LQFP64. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PB0_CH8 +#define ADC1_PB10_CH11 +#define ADC1_PB11_CH15 +#define ADC1_PB12_CH16 +#define ADC1_PB1_CH9 +#define ADC1_PB2_CH10 +#define ADC1_PC4_CH17 +#define ADC1_PC5_CH18 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF3 +#define FDCAN1_RX_PB8_AF3 +#define FDCAN1_RX_PC4_AF3 +#define FDCAN1_RX_PD0_AF3 +#define FDCAN1_TX_PA12_AF3 +#define FDCAN1_TX_PB9_AF3 +#define FDCAN1_TX_PC5_AF3 +#define FDCAN1_TX_PD1_AF3 +#define FDCAN2_RX_PB0_AF3 +#define FDCAN2_RX_PB12_AF3 +#define FDCAN2_RX_PB5_AF3 +#define FDCAN2_RX_PC2_AF3 +#define FDCAN2_TX_PB13_AF3 +#define FDCAN2_TX_PB1_AF3 +#define FDCAN2_TX_PB6_AF3 +#define FDCAN2_TX_PC3_AF3 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) + +#define CAN_MODULE_COUNT (2) + +#define HAL_LL_FDCAN1_GPIO_AF3 (3) +#define HAL_LL_FDCAN2_GPIO_AF3 (3) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (78) +#define DMA_NUM_OF_CHANNELS_FAMILY (78) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (12) +#define DMA_NUM_OF_STREAMS_FAMILY (12) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PB9_AF6 +#define I2C2_SCL_PA11_AF6 +#define I2C2_SCL_PA7_AF8 +#define I2C2_SCL_PA9_AF8 +#define I2C2_SCL_PB10_AF6 +#define I2C2_SCL_PB13_AF6 +#define I2C2_SCL_PB3_AF8 +#define I2C2_SDA_PA10_AF8 +#define I2C2_SDA_PA12_AF6 +#define I2C2_SDA_PA6_AF8 +#define I2C2_SDA_PB11_AF6 +#define I2C2_SDA_PB14_AF6 +#define I2C2_SDA_PB4_AF8 +#define I2C3_SCL_PA7_AF9 +#define I2C3_SCL_PB3_AF6 +#define I2C3_SCL_PC0_AF6 +#define I2C3_SDA_PA6_AF9 +#define I2C3_SDA_PB4_AF6 +#define I2C3_SDA_PC1_AF6 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF6 +#define LPUART1_RX_PB10_AF1 +#define LPUART1_RX_PC0_AF1 +#define LPUART1_TX_PA2_AF6 +#define LPUART1_TX_PB11_AF1 +#define LPUART1_TX_PC1_AF1 +#define LPUART2_RX_PA13_AF10 +#define LPUART2_RX_PB7_AF10 +#define LPUART2_RX_PC1_AF3 +#define LPUART2_RX_PC7_AF3 +#define LPUART2_TX_PA14_AF10 +#define LPUART2_TX_PB6_AF10 +#define LPUART2_TX_PC0_AF3 +#define LPUART2_TX_PC6_AF3 +#define LPUART2_TX_PF2_AF1 +#define USART1_RX_PA10_AF1 +#define USART1_RX_PB7_AF0 +#define USART1_RX_PC5_AF1 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART1_TX_PC4_AF1 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_RX_PD6_AF0 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 +#define USART2_TX_PD5_AF0 +#define USART3_RX_PB0_AF4 +#define USART3_RX_PB11_AF4 +#define USART3_RX_PB9_AF4 +#define USART3_RX_PC11_AF0 +#define USART3_RX_PC5_AF0 +#define USART3_RX_PD9_AF0 +#define USART3_TX_PA5_AF4 +#define USART3_TX_PB10_AF4 +#define USART3_TX_PB2_AF4 +#define USART3_TX_PB8_AF4 +#define USART3_TX_PC10_AF0 +#define USART3_TX_PC4_AF0 +#define USART3_TX_PD8_AF0 +#define USART4_RX_PA1_AF4 +#define USART4_RX_PC11_AF1 +#define USART4_TX_PA0_AF4 +#define USART4_TX_PC10_AF1 +#define USART5_RX_PB1_AF8 +#define USART5_RX_PB4_AF3 +#define USART5_RX_PD2_AF3 +#define USART5_TX_PB0_AF8 +#define USART5_TX_PB3_AF3 +#define USART5_TX_PC12_AF3 +#define USART5_TX_PD3_AF3 +#define USART6_RX_PA5_AF3 +#define USART6_RX_PB9_AF8 +#define USART6_RX_PC1_AF4 +#define USART6_TX_PA4_AF3 +#define USART6_TX_PB8_AF8 +#define USART6_TX_PC0_AF4 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) +#define UART_MODULE_6 (6) + +#define UART_MODULE_COUNT (6) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MISO_PD5_AF1 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_MOSI_PD6_AF1 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI1_SCK_PD8_AF1 +#define SPI2_MISO_PA3_AF0 +#define SPI2_MISO_PA9_AF4 +#define SPI2_MISO_PB14_AF0 +#define SPI2_MISO_PB2_AF1 +#define SPI2_MISO_PB6_AF4 +#define SPI2_MISO_PC2_AF1 +#define SPI2_MISO_PD3_AF1 +#define SPI2_MOSI_PA10_AF0 +#define SPI2_MOSI_PA4_AF1 +#define SPI2_MOSI_PB11_AF0 +#define SPI2_MOSI_PB15_AF0 +#define SPI2_MOSI_PB7_AF1 +#define SPI2_MOSI_PC3_AF1 +#define SPI2_MOSI_PD4_AF1 +#define SPI2_SCK_PA0_AF0 +#define SPI2_SCK_PB10_AF5 +#define SPI2_SCK_PB13_AF0 +#define SPI2_SCK_PB8_AF1 +#define SPI2_SCK_PD1_AF1 +#define SPI3_MISO_PB4_AF9 +#define SPI3_MISO_PC11_AF4 +#define SPI3_MOSI_PB5_AF9 +#define SPI3_MOSI_PC12_AF4 +#define SPI3_SCK_PB3_AF9 +#define SPI3_SCK_PC10_AF4 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF5 +#define LPTIM1_ETR_PC3_AF0 +#define LPTIM2_ETR_PA5_AF5 +#define LPTIM2_ETR_PC3_AF2 +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PB1_AF0 +#define TIM14_CH1_PC12_AF2 +#define TIM14_CH1_PF0_AF2 +#define TIM15_CH1N_PA1_AF5 +#define TIM15_CH1N_PB13_AF5 +#define TIM15_CH1N_PB15_AF4 +#define TIM15_CH1N_PF1_AF2 +#define TIM15_CH1_PA2_AF5 +#define TIM15_CH1_PB14_AF5 +#define TIM15_CH1_PC1_AF2 +#define TIM15_CH2_PA3_AF5 +#define TIM15_CH2_PB15_AF5 +#define TIM15_CH2_PC2_AF2 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB8_AF2 +#define TIM16_CH1_PD0_AF2 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PB9_AF2 +#define TIM17_CH1_PD1_AF2 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1N_PB13_AF2 +#define TIM1_CH1N_PD2_AF2 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH1_PC8_AF2 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2N_PB14_AF2 +#define TIM1_CH2N_PD3_AF2 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH2_PC9_AF2 +#define TIM1_CH3N_PB15_AF2 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3N_PD4_AF2 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH3_PC10_AF2 +#define TIM1_CH4_PA11_AF2 +#define TIM1_CH4_PC11_AF2 +#define TIM1_ETR_PA12_AF2 +#define TIM2_CH1_PA0_AF2 +#define TIM2_CH1_PA15_AF2 +#define TIM2_CH1_PA5_AF2 +#define TIM2_CH1_PC4_AF2 +#define TIM2_CH2_PA1_AF2 +#define TIM2_CH2_PB3_AF2 +#define TIM2_CH2_PC5_AF2 +#define TIM2_CH3_PA2_AF2 +#define TIM2_CH3_PB10_AF2 +#define TIM2_CH3_PC6_AF2 +#define TIM2_CH4_PA3_AF2 +#define TIM2_CH4_PB11_AF2 +#define TIM2_CH4_PC7_AF2 +#define TIM2_ETR_PA0_AF2 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM2_ETR_PC4_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH1_PC6_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH2_PC7_AF1 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH3_PC8_AF1 +#define TIM3_CH4_PB1_AF1 +#define TIM3_CH4_PC9_AF1 +#define TIM3_ETR_PD2_AF1 +#define TIM4_CH1_PB6_AF9 +#define TIM4_CH2_PB7_AF9 +#define TIM4_CH3_PB8_AF9 +#define TIM4_CH4_PB9_AF9 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_14 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +#define TIM1_BUS (1) +#define TIM4_BUS (1) +#define TIM15_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD8_CN +#define __PD9_CN +#define __PF0_CN +#define __PF1_CN +#define __PF2_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_F_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +#define UART3_IVT (29) +#define UART3_NVIC (45) +#define UART4_IVT (29) +#define UART4_NVIC (45) +#define UART5_IVT (29) +#define UART5_NVIC (45) +#define UART6_IVT (29) +#define UART6_NVIC (45) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1RE/LQFP64/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1RE/LQFP64/mcu_definitions.h new file mode 100644 index 000000000..93fc46e0c --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1RE/LQFP64/mcu_definitions.h @@ -0,0 +1,452 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G0B1RE_LQFP64. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PB0_CH8 +#define ADC1_PB10_CH11 +#define ADC1_PB11_CH15 +#define ADC1_PB12_CH16 +#define ADC1_PB1_CH9 +#define ADC1_PB2_CH10 +#define ADC1_PC4_CH17 +#define ADC1_PC5_CH18 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF3 +#define FDCAN1_RX_PB8_AF3 +#define FDCAN1_RX_PC4_AF3 +#define FDCAN1_RX_PD0_AF3 +#define FDCAN1_TX_PA12_AF3 +#define FDCAN1_TX_PB9_AF3 +#define FDCAN1_TX_PC5_AF3 +#define FDCAN1_TX_PD1_AF3 +#define FDCAN2_RX_PB0_AF3 +#define FDCAN2_RX_PB12_AF3 +#define FDCAN2_RX_PB5_AF3 +#define FDCAN2_RX_PC2_AF3 +#define FDCAN2_TX_PB13_AF3 +#define FDCAN2_TX_PB1_AF3 +#define FDCAN2_TX_PB6_AF3 +#define FDCAN2_TX_PC3_AF3 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) + +#define CAN_MODULE_COUNT (2) + +#define HAL_LL_FDCAN1_GPIO_AF3 (3) +#define HAL_LL_FDCAN2_GPIO_AF3 (3) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (78) +#define DMA_NUM_OF_CHANNELS_FAMILY (78) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (12) +#define DMA_NUM_OF_STREAMS_FAMILY (12) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PB9_AF6 +#define I2C2_SCL_PA11_AF6 +#define I2C2_SCL_PA7_AF8 +#define I2C2_SCL_PA9_AF8 +#define I2C2_SCL_PB10_AF6 +#define I2C2_SCL_PB13_AF6 +#define I2C2_SCL_PB3_AF8 +#define I2C2_SDA_PA10_AF8 +#define I2C2_SDA_PA12_AF6 +#define I2C2_SDA_PA6_AF8 +#define I2C2_SDA_PB11_AF6 +#define I2C2_SDA_PB14_AF6 +#define I2C2_SDA_PB4_AF8 +#define I2C3_SCL_PA7_AF9 +#define I2C3_SCL_PB3_AF6 +#define I2C3_SCL_PC0_AF6 +#define I2C3_SDA_PA6_AF9 +#define I2C3_SDA_PB4_AF6 +#define I2C3_SDA_PC1_AF6 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF6 +#define LPUART1_RX_PB10_AF1 +#define LPUART1_RX_PC0_AF1 +#define LPUART1_TX_PA2_AF6 +#define LPUART1_TX_PB11_AF1 +#define LPUART1_TX_PC1_AF1 +#define LPUART2_RX_PA13_AF10 +#define LPUART2_RX_PB7_AF10 +#define LPUART2_RX_PC1_AF3 +#define LPUART2_RX_PC7_AF3 +#define LPUART2_TX_PA14_AF10 +#define LPUART2_TX_PB6_AF10 +#define LPUART2_TX_PC0_AF3 +#define LPUART2_TX_PC6_AF3 +#define LPUART2_TX_PF2_AF1 +#define USART1_RX_PA10_AF1 +#define USART1_RX_PB7_AF0 +#define USART1_RX_PC5_AF1 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART1_TX_PC4_AF1 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_RX_PD6_AF0 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 +#define USART2_TX_PD5_AF0 +#define USART3_RX_PB0_AF4 +#define USART3_RX_PB11_AF4 +#define USART3_RX_PB9_AF4 +#define USART3_RX_PC11_AF0 +#define USART3_RX_PC5_AF0 +#define USART3_RX_PD9_AF0 +#define USART3_TX_PA5_AF4 +#define USART3_TX_PB10_AF4 +#define USART3_TX_PB2_AF4 +#define USART3_TX_PB8_AF4 +#define USART3_TX_PC10_AF0 +#define USART3_TX_PC4_AF0 +#define USART3_TX_PD8_AF0 +#define USART4_RX_PA1_AF4 +#define USART4_RX_PC11_AF1 +#define USART4_TX_PA0_AF4 +#define USART4_TX_PC10_AF1 +#define USART5_RX_PB1_AF8 +#define USART5_RX_PB4_AF3 +#define USART5_RX_PD2_AF3 +#define USART5_TX_PB0_AF8 +#define USART5_TX_PB3_AF3 +#define USART5_TX_PC12_AF3 +#define USART5_TX_PD3_AF3 +#define USART6_RX_PA5_AF3 +#define USART6_RX_PB9_AF8 +#define USART6_RX_PC1_AF4 +#define USART6_TX_PA4_AF3 +#define USART6_TX_PB8_AF8 +#define USART6_TX_PC0_AF4 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) +#define UART_MODULE_6 (6) + +#define UART_MODULE_COUNT (6) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MISO_PD5_AF1 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_MOSI_PD6_AF1 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI1_SCK_PD8_AF1 +#define SPI2_MISO_PA3_AF0 +#define SPI2_MISO_PA9_AF4 +#define SPI2_MISO_PB14_AF0 +#define SPI2_MISO_PB2_AF1 +#define SPI2_MISO_PB6_AF4 +#define SPI2_MISO_PC2_AF1 +#define SPI2_MISO_PD3_AF1 +#define SPI2_MOSI_PA10_AF0 +#define SPI2_MOSI_PA4_AF1 +#define SPI2_MOSI_PB11_AF0 +#define SPI2_MOSI_PB15_AF0 +#define SPI2_MOSI_PB7_AF1 +#define SPI2_MOSI_PC3_AF1 +#define SPI2_MOSI_PD4_AF1 +#define SPI2_SCK_PA0_AF0 +#define SPI2_SCK_PB10_AF5 +#define SPI2_SCK_PB13_AF0 +#define SPI2_SCK_PB8_AF1 +#define SPI2_SCK_PD1_AF1 +#define SPI3_MISO_PB4_AF9 +#define SPI3_MISO_PC11_AF4 +#define SPI3_MOSI_PB5_AF9 +#define SPI3_MOSI_PC12_AF4 +#define SPI3_SCK_PB3_AF9 +#define SPI3_SCK_PC10_AF4 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF5 +#define LPTIM1_ETR_PC3_AF0 +#define LPTIM2_ETR_PA5_AF5 +#define LPTIM2_ETR_PC3_AF2 +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PB1_AF0 +#define TIM14_CH1_PC12_AF2 +#define TIM14_CH1_PF0_AF2 +#define TIM15_CH1N_PA1_AF5 +#define TIM15_CH1N_PB13_AF5 +#define TIM15_CH1N_PB15_AF4 +#define TIM15_CH1N_PF1_AF2 +#define TIM15_CH1_PA2_AF5 +#define TIM15_CH1_PB14_AF5 +#define TIM15_CH1_PC1_AF2 +#define TIM15_CH2_PA3_AF5 +#define TIM15_CH2_PB15_AF5 +#define TIM15_CH2_PC2_AF2 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB8_AF2 +#define TIM16_CH1_PD0_AF2 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PB9_AF2 +#define TIM17_CH1_PD1_AF2 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1N_PB13_AF2 +#define TIM1_CH1N_PD2_AF2 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH1_PC8_AF2 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2N_PB14_AF2 +#define TIM1_CH2N_PD3_AF2 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH2_PC9_AF2 +#define TIM1_CH3N_PB15_AF2 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3N_PD4_AF2 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH3_PC10_AF2 +#define TIM1_CH4_PA11_AF2 +#define TIM1_CH4_PC11_AF2 +#define TIM1_ETR_PA12_AF2 +#define TIM2_CH1_PA0_AF2 +#define TIM2_CH1_PA15_AF2 +#define TIM2_CH1_PA5_AF2 +#define TIM2_CH1_PC4_AF2 +#define TIM2_CH2_PA1_AF2 +#define TIM2_CH2_PB3_AF2 +#define TIM2_CH2_PC5_AF2 +#define TIM2_CH3_PA2_AF2 +#define TIM2_CH3_PB10_AF2 +#define TIM2_CH3_PC6_AF2 +#define TIM2_CH4_PA3_AF2 +#define TIM2_CH4_PB11_AF2 +#define TIM2_CH4_PC7_AF2 +#define TIM2_ETR_PA0_AF2 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM2_ETR_PC4_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH1_PC6_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH2_PC7_AF1 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH3_PC8_AF1 +#define TIM3_CH4_PB1_AF1 +#define TIM3_CH4_PC9_AF1 +#define TIM3_ETR_PD2_AF1 +#define TIM4_CH1_PB6_AF9 +#define TIM4_CH2_PB7_AF9 +#define TIM4_CH3_PB8_AF9 +#define TIM4_CH4_PB9_AF9 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_14 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +#define TIM1_BUS (1) +#define TIM4_BUS (1) +#define TIM15_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD8_CN +#define __PD9_CN +#define __PF0_CN +#define __PF1_CN +#define __PF2_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_F_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +#define UART3_IVT (29) +#define UART3_NVIC (45) +#define UART4_IVT (29) +#define UART4_NVIC (45) +#define UART5_IVT (29) +#define UART5_NVIC (45) +#define UART6_IVT (29) +#define UART6_NVIC (45) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1VB/LQFP100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1VB/LQFP100/mcu_definitions.h new file mode 100644 index 000000000..036cbe595 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1VB/LQFP100/mcu_definitions.h @@ -0,0 +1,526 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G0B1VB_LQFP100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PB0_CH8 +#define ADC1_PB10_CH11 +#define ADC1_PB11_CH15 +#define ADC1_PB12_CH16 +#define ADC1_PB1_CH9 +#define ADC1_PB2_CH10 +#define ADC1_PC4_CH17 +#define ADC1_PC5_CH18 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF3 +#define FDCAN1_RX_PB8_AF3 +#define FDCAN1_RX_PC4_AF3 +#define FDCAN1_RX_PD0_AF3 +#define FDCAN1_RX_PD12_AF3 +#define FDCAN1_TX_PA12_AF3 +#define FDCAN1_TX_PB9_AF3 +#define FDCAN1_TX_PC5_AF3 +#define FDCAN1_TX_PD13_AF3 +#define FDCAN1_TX_PD1_AF3 +#define FDCAN2_RX_PB0_AF3 +#define FDCAN2_RX_PB12_AF3 +#define FDCAN2_RX_PB5_AF3 +#define FDCAN2_RX_PC2_AF3 +#define FDCAN2_RX_PD14_AF3 +#define FDCAN2_TX_PB13_AF3 +#define FDCAN2_TX_PB1_AF3 +#define FDCAN2_TX_PB6_AF3 +#define FDCAN2_TX_PC3_AF3 +#define FDCAN2_TX_PD15_AF3 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) + +#define CAN_MODULE_COUNT (2) + +#define HAL_LL_FDCAN1_GPIO_AF3 (3) +#define HAL_LL_FDCAN2_GPIO_AF3 (3) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (78) +#define DMA_NUM_OF_CHANNELS_FAMILY (78) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (12) +#define DMA_NUM_OF_STREAMS_FAMILY (12) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PB9_AF6 +#define I2C2_SCL_PA11_AF6 +#define I2C2_SCL_PA7_AF8 +#define I2C2_SCL_PA9_AF8 +#define I2C2_SCL_PB10_AF6 +#define I2C2_SCL_PB13_AF6 +#define I2C2_SCL_PB3_AF8 +#define I2C2_SDA_PA10_AF8 +#define I2C2_SDA_PA12_AF6 +#define I2C2_SDA_PA6_AF8 +#define I2C2_SDA_PB11_AF6 +#define I2C2_SDA_PB14_AF6 +#define I2C2_SDA_PB4_AF8 +#define I2C3_SCL_PA7_AF9 +#define I2C3_SCL_PB3_AF6 +#define I2C3_SCL_PC0_AF6 +#define I2C3_SDA_PA6_AF9 +#define I2C3_SDA_PB4_AF6 +#define I2C3_SDA_PC1_AF6 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF6 +#define LPUART1_RX_PB10_AF1 +#define LPUART1_RX_PC0_AF1 +#define LPUART1_RX_PF5_AF1 +#define LPUART1_TX_PA2_AF6 +#define LPUART1_TX_PB11_AF1 +#define LPUART1_TX_PC1_AF1 +#define LPUART1_TX_PF4_AF1 +#define LPUART2_RX_PA13_AF10 +#define LPUART2_RX_PB7_AF10 +#define LPUART2_RX_PC1_AF3 +#define LPUART2_RX_PC7_AF3 +#define LPUART2_RX_PF3_AF1 +#define LPUART2_TX_PA14_AF10 +#define LPUART2_TX_PB6_AF10 +#define LPUART2_TX_PC0_AF3 +#define LPUART2_TX_PC6_AF3 +#define LPUART2_TX_PF2_AF1 +#define USART1_RX_PA10_AF1 +#define USART1_RX_PB7_AF0 +#define USART1_RX_PC5_AF1 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART1_TX_PC4_AF1 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_RX_PD6_AF0 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 +#define USART2_TX_PD5_AF0 +#define USART3_RX_PB0_AF4 +#define USART3_RX_PB11_AF4 +#define USART3_RX_PB9_AF4 +#define USART3_RX_PC11_AF0 +#define USART3_RX_PC5_AF0 +#define USART3_RX_PD9_AF0 +#define USART3_TX_PA5_AF4 +#define USART3_TX_PB10_AF4 +#define USART3_TX_PB2_AF4 +#define USART3_TX_PB8_AF4 +#define USART3_TX_PC10_AF0 +#define USART3_TX_PC4_AF0 +#define USART3_TX_PD8_AF0 +#define USART4_RX_PA1_AF4 +#define USART4_RX_PC11_AF1 +#define USART4_RX_PE9_AF0 +#define USART4_TX_PA0_AF4 +#define USART4_TX_PC10_AF1 +#define USART4_TX_PE8_AF0 +#define USART5_RX_PB1_AF8 +#define USART5_RX_PB4_AF3 +#define USART5_RX_PD2_AF3 +#define USART5_RX_PE11_AF3 +#define USART5_TX_PB0_AF8 +#define USART5_TX_PB3_AF3 +#define USART5_TX_PC12_AF3 +#define USART5_TX_PD3_AF3 +#define USART5_TX_PE10_AF3 +#define USART6_RX_PA5_AF3 +#define USART6_RX_PB9_AF8 +#define USART6_RX_PC1_AF4 +#define USART6_RX_PF10_AF3 +#define USART6_TX_PA4_AF3 +#define USART6_TX_PB8_AF8 +#define USART6_TX_PC0_AF4 +#define USART6_TX_PF9_AF3 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) +#define UART_MODULE_6 (6) + +#define UART_MODULE_COUNT (6) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MISO_PD5_AF1 +#define SPI1_MISO_PE14_AF0 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_MOSI_PD6_AF1 +#define SPI1_MOSI_PE15_AF0 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI1_SCK_PD8_AF1 +#define SPI1_SCK_PE13_AF0 +#define SPI2_MISO_PA3_AF0 +#define SPI2_MISO_PA9_AF4 +#define SPI2_MISO_PB14_AF0 +#define SPI2_MISO_PB2_AF1 +#define SPI2_MISO_PB6_AF4 +#define SPI2_MISO_PC2_AF1 +#define SPI2_MISO_PD3_AF1 +#define SPI2_MOSI_PA10_AF0 +#define SPI2_MOSI_PA4_AF1 +#define SPI2_MOSI_PB11_AF0 +#define SPI2_MOSI_PB15_AF0 +#define SPI2_MOSI_PB7_AF1 +#define SPI2_MOSI_PC3_AF1 +#define SPI2_MOSI_PD4_AF1 +#define SPI2_SCK_PA0_AF0 +#define SPI2_SCK_PB10_AF5 +#define SPI2_SCK_PB13_AF0 +#define SPI2_SCK_PB8_AF1 +#define SPI2_SCK_PD1_AF1 +#define SPI3_MISO_PB4_AF9 +#define SPI3_MISO_PC11_AF4 +#define SPI3_MOSI_PB5_AF9 +#define SPI3_MOSI_PC12_AF4 +#define SPI3_SCK_PB3_AF9 +#define SPI3_SCK_PC10_AF4 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF5 +#define LPTIM1_ETR_PC3_AF0 +#define LPTIM2_ETR_PA5_AF5 +#define LPTIM2_ETR_PC3_AF2 +#define LPTIM2_ETR_PD11_AF1 +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PB1_AF0 +#define TIM14_CH1_PC12_AF2 +#define TIM14_CH1_PF0_AF2 +#define TIM15_CH1N_PA1_AF5 +#define TIM15_CH1N_PB13_AF5 +#define TIM15_CH1N_PB15_AF4 +#define TIM15_CH1N_PF1_AF2 +#define TIM15_CH1_PA2_AF5 +#define TIM15_CH1_PB14_AF5 +#define TIM15_CH1_PC1_AF2 +#define TIM15_CH1_PF12_AF0 +#define TIM15_CH2_PA3_AF5 +#define TIM15_CH2_PB15_AF5 +#define TIM15_CH2_PC2_AF2 +#define TIM15_CH2_PF13_AF0 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB8_AF2 +#define TIM16_CH1_PD0_AF2 +#define TIM16_CH1_PE0_AF0 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PB9_AF2 +#define TIM17_CH1_PD1_AF2 +#define TIM17_CH1_PE1_AF0 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1N_PB13_AF2 +#define TIM1_CH1N_PD2_AF2 +#define TIM1_CH1N_PE8_AF1 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH1_PC8_AF2 +#define TIM1_CH1_PE9_AF1 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2N_PB14_AF2 +#define TIM1_CH2N_PD3_AF2 +#define TIM1_CH2N_PE10_AF1 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH2_PC9_AF2 +#define TIM1_CH2_PE11_AF1 +#define TIM1_CH3N_PB15_AF2 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3N_PD4_AF2 +#define TIM1_CH3N_PE12_AF1 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH3_PC10_AF2 +#define TIM1_CH3_PE13_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_CH4_PC11_AF2 +#define TIM1_CH4_PE14_AF1 +#define TIM1_ETR_PA12_AF2 +#define TIM1_ETR_PE7_AF1 +#define TIM2_CH1_PA0_AF2 +#define TIM2_CH1_PA15_AF2 +#define TIM2_CH1_PA5_AF2 +#define TIM2_CH1_PC4_AF2 +#define TIM2_CH2_PA1_AF2 +#define TIM2_CH2_PB3_AF2 +#define TIM2_CH2_PC5_AF2 +#define TIM2_CH3_PA2_AF2 +#define TIM2_CH3_PB10_AF2 +#define TIM2_CH3_PC6_AF2 +#define TIM2_CH4_PA3_AF2 +#define TIM2_CH4_PB11_AF2 +#define TIM2_CH4_PC7_AF2 +#define TIM2_ETR_PA0_AF2 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM2_ETR_PC4_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH1_PC6_AF1 +#define TIM3_CH1_PE3_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH2_PC7_AF1 +#define TIM3_CH2_PE4_AF1 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH3_PC8_AF1 +#define TIM3_CH3_PE5_AF1 +#define TIM3_CH4_PB1_AF1 +#define TIM3_CH4_PC9_AF1 +#define TIM3_CH4_PE6_AF1 +#define TIM3_ETR_PD2_AF1 +#define TIM3_ETR_PE2_AF1 +#define TIM4_CH1_PB6_AF9 +#define TIM4_CH1_PD12_AF2 +#define TIM4_CH2_PB7_AF9 +#define TIM4_CH2_PD13_AF2 +#define TIM4_CH3_PB8_AF9 +#define TIM4_CH3_PD14_AF2 +#define TIM4_CH4_PB9_AF9 +#define TIM4_CH4_PD15_AF2 +#define TIM4_ETR_PE0_AF2 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_14 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +#define TIM1_BUS (1) +#define TIM4_BUS (1) +#define TIM15_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PE0_CN +#define __PE1_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN +#define __PE6_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PF10_CN +#define __PF11_CN +#define __PF12_CN +#define __PF13_CN +#define __PF2_CN +#define __PF3_CN +#define __PF4_CN +#define __PF5_CN +#define __PF6_CN +#define __PF7_CN +#define __PF8_CN +#define __PF9_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN + +#define PORT_COUNT (6) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +#define UART3_IVT (29) +#define UART3_NVIC (45) +#define UART4_IVT (29) +#define UART4_NVIC (45) +#define UART5_IVT (29) +#define UART5_NVIC (45) +#define UART6_IVT (29) +#define UART6_NVIC (45) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1VB/UFBGA100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1VB/UFBGA100/mcu_definitions.h new file mode 100644 index 000000000..54e5b69fd --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1VB/UFBGA100/mcu_definitions.h @@ -0,0 +1,526 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G0B1VB_UFBGA100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PB0_CH8 +#define ADC1_PB10_CH11 +#define ADC1_PB11_CH15 +#define ADC1_PB12_CH16 +#define ADC1_PB1_CH9 +#define ADC1_PB2_CH10 +#define ADC1_PC4_CH17 +#define ADC1_PC5_CH18 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF3 +#define FDCAN1_RX_PB8_AF3 +#define FDCAN1_RX_PC4_AF3 +#define FDCAN1_RX_PD0_AF3 +#define FDCAN1_RX_PD12_AF3 +#define FDCAN1_TX_PA12_AF3 +#define FDCAN1_TX_PB9_AF3 +#define FDCAN1_TX_PC5_AF3 +#define FDCAN1_TX_PD13_AF3 +#define FDCAN1_TX_PD1_AF3 +#define FDCAN2_RX_PB0_AF3 +#define FDCAN2_RX_PB12_AF3 +#define FDCAN2_RX_PB5_AF3 +#define FDCAN2_RX_PC2_AF3 +#define FDCAN2_RX_PD14_AF3 +#define FDCAN2_TX_PB13_AF3 +#define FDCAN2_TX_PB1_AF3 +#define FDCAN2_TX_PB6_AF3 +#define FDCAN2_TX_PC3_AF3 +#define FDCAN2_TX_PD15_AF3 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) + +#define CAN_MODULE_COUNT (2) + +#define HAL_LL_FDCAN1_GPIO_AF3 (3) +#define HAL_LL_FDCAN2_GPIO_AF3 (3) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (78) +#define DMA_NUM_OF_CHANNELS_FAMILY (78) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (12) +#define DMA_NUM_OF_STREAMS_FAMILY (12) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PB9_AF6 +#define I2C2_SCL_PA11_AF6 +#define I2C2_SCL_PA7_AF8 +#define I2C2_SCL_PA9_AF8 +#define I2C2_SCL_PB10_AF6 +#define I2C2_SCL_PB13_AF6 +#define I2C2_SCL_PB3_AF8 +#define I2C2_SDA_PA10_AF8 +#define I2C2_SDA_PA12_AF6 +#define I2C2_SDA_PA6_AF8 +#define I2C2_SDA_PB11_AF6 +#define I2C2_SDA_PB14_AF6 +#define I2C2_SDA_PB4_AF8 +#define I2C3_SCL_PA7_AF9 +#define I2C3_SCL_PB3_AF6 +#define I2C3_SCL_PC0_AF6 +#define I2C3_SDA_PA6_AF9 +#define I2C3_SDA_PB4_AF6 +#define I2C3_SDA_PC1_AF6 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF6 +#define LPUART1_RX_PB10_AF1 +#define LPUART1_RX_PC0_AF1 +#define LPUART1_RX_PF5_AF1 +#define LPUART1_TX_PA2_AF6 +#define LPUART1_TX_PB11_AF1 +#define LPUART1_TX_PC1_AF1 +#define LPUART1_TX_PF4_AF1 +#define LPUART2_RX_PA13_AF10 +#define LPUART2_RX_PB7_AF10 +#define LPUART2_RX_PC1_AF3 +#define LPUART2_RX_PC7_AF3 +#define LPUART2_RX_PF3_AF1 +#define LPUART2_TX_PA14_AF10 +#define LPUART2_TX_PB6_AF10 +#define LPUART2_TX_PC0_AF3 +#define LPUART2_TX_PC6_AF3 +#define LPUART2_TX_PF2_AF1 +#define USART1_RX_PA10_AF1 +#define USART1_RX_PB7_AF0 +#define USART1_RX_PC5_AF1 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART1_TX_PC4_AF1 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_RX_PD6_AF0 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 +#define USART2_TX_PD5_AF0 +#define USART3_RX_PB0_AF4 +#define USART3_RX_PB11_AF4 +#define USART3_RX_PB9_AF4 +#define USART3_RX_PC11_AF0 +#define USART3_RX_PC5_AF0 +#define USART3_RX_PD9_AF0 +#define USART3_TX_PA5_AF4 +#define USART3_TX_PB10_AF4 +#define USART3_TX_PB2_AF4 +#define USART3_TX_PB8_AF4 +#define USART3_TX_PC10_AF0 +#define USART3_TX_PC4_AF0 +#define USART3_TX_PD8_AF0 +#define USART4_RX_PA1_AF4 +#define USART4_RX_PC11_AF1 +#define USART4_RX_PE9_AF0 +#define USART4_TX_PA0_AF4 +#define USART4_TX_PC10_AF1 +#define USART4_TX_PE8_AF0 +#define USART5_RX_PB1_AF8 +#define USART5_RX_PB4_AF3 +#define USART5_RX_PD2_AF3 +#define USART5_RX_PE11_AF3 +#define USART5_TX_PB0_AF8 +#define USART5_TX_PB3_AF3 +#define USART5_TX_PC12_AF3 +#define USART5_TX_PD3_AF3 +#define USART5_TX_PE10_AF3 +#define USART6_RX_PA5_AF3 +#define USART6_RX_PB9_AF8 +#define USART6_RX_PC1_AF4 +#define USART6_RX_PF10_AF3 +#define USART6_TX_PA4_AF3 +#define USART6_TX_PB8_AF8 +#define USART6_TX_PC0_AF4 +#define USART6_TX_PF9_AF3 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) +#define UART_MODULE_6 (6) + +#define UART_MODULE_COUNT (6) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MISO_PD5_AF1 +#define SPI1_MISO_PE14_AF0 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_MOSI_PD6_AF1 +#define SPI1_MOSI_PE15_AF0 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI1_SCK_PD8_AF1 +#define SPI1_SCK_PE13_AF0 +#define SPI2_MISO_PA3_AF0 +#define SPI2_MISO_PA9_AF4 +#define SPI2_MISO_PB14_AF0 +#define SPI2_MISO_PB2_AF1 +#define SPI2_MISO_PB6_AF4 +#define SPI2_MISO_PC2_AF1 +#define SPI2_MISO_PD3_AF1 +#define SPI2_MOSI_PA10_AF0 +#define SPI2_MOSI_PA4_AF1 +#define SPI2_MOSI_PB11_AF0 +#define SPI2_MOSI_PB15_AF0 +#define SPI2_MOSI_PB7_AF1 +#define SPI2_MOSI_PC3_AF1 +#define SPI2_MOSI_PD4_AF1 +#define SPI2_SCK_PA0_AF0 +#define SPI2_SCK_PB10_AF5 +#define SPI2_SCK_PB13_AF0 +#define SPI2_SCK_PB8_AF1 +#define SPI2_SCK_PD1_AF1 +#define SPI3_MISO_PB4_AF9 +#define SPI3_MISO_PC11_AF4 +#define SPI3_MOSI_PB5_AF9 +#define SPI3_MOSI_PC12_AF4 +#define SPI3_SCK_PB3_AF9 +#define SPI3_SCK_PC10_AF4 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF5 +#define LPTIM1_ETR_PC3_AF0 +#define LPTIM2_ETR_PA5_AF5 +#define LPTIM2_ETR_PC3_AF2 +#define LPTIM2_ETR_PD11_AF1 +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PB1_AF0 +#define TIM14_CH1_PC12_AF2 +#define TIM14_CH1_PF0_AF2 +#define TIM15_CH1N_PA1_AF5 +#define TIM15_CH1N_PB13_AF5 +#define TIM15_CH1N_PB15_AF4 +#define TIM15_CH1N_PF1_AF2 +#define TIM15_CH1_PA2_AF5 +#define TIM15_CH1_PB14_AF5 +#define TIM15_CH1_PC1_AF2 +#define TIM15_CH1_PF12_AF0 +#define TIM15_CH2_PA3_AF5 +#define TIM15_CH2_PB15_AF5 +#define TIM15_CH2_PC2_AF2 +#define TIM15_CH2_PF13_AF0 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB8_AF2 +#define TIM16_CH1_PD0_AF2 +#define TIM16_CH1_PE0_AF0 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PB9_AF2 +#define TIM17_CH1_PD1_AF2 +#define TIM17_CH1_PE1_AF0 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1N_PB13_AF2 +#define TIM1_CH1N_PD2_AF2 +#define TIM1_CH1N_PE8_AF1 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH1_PC8_AF2 +#define TIM1_CH1_PE9_AF1 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2N_PB14_AF2 +#define TIM1_CH2N_PD3_AF2 +#define TIM1_CH2N_PE10_AF1 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH2_PC9_AF2 +#define TIM1_CH2_PE11_AF1 +#define TIM1_CH3N_PB15_AF2 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3N_PD4_AF2 +#define TIM1_CH3N_PE12_AF1 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH3_PC10_AF2 +#define TIM1_CH3_PE13_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_CH4_PC11_AF2 +#define TIM1_CH4_PE14_AF1 +#define TIM1_ETR_PA12_AF2 +#define TIM1_ETR_PE7_AF1 +#define TIM2_CH1_PA0_AF2 +#define TIM2_CH1_PA15_AF2 +#define TIM2_CH1_PA5_AF2 +#define TIM2_CH1_PC4_AF2 +#define TIM2_CH2_PA1_AF2 +#define TIM2_CH2_PB3_AF2 +#define TIM2_CH2_PC5_AF2 +#define TIM2_CH3_PA2_AF2 +#define TIM2_CH3_PB10_AF2 +#define TIM2_CH3_PC6_AF2 +#define TIM2_CH4_PA3_AF2 +#define TIM2_CH4_PB11_AF2 +#define TIM2_CH4_PC7_AF2 +#define TIM2_ETR_PA0_AF2 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM2_ETR_PC4_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH1_PC6_AF1 +#define TIM3_CH1_PE3_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH2_PC7_AF1 +#define TIM3_CH2_PE4_AF1 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH3_PC8_AF1 +#define TIM3_CH3_PE5_AF1 +#define TIM3_CH4_PB1_AF1 +#define TIM3_CH4_PC9_AF1 +#define TIM3_CH4_PE6_AF1 +#define TIM3_ETR_PD2_AF1 +#define TIM3_ETR_PE2_AF1 +#define TIM4_CH1_PB6_AF9 +#define TIM4_CH1_PD12_AF2 +#define TIM4_CH2_PB7_AF9 +#define TIM4_CH2_PD13_AF2 +#define TIM4_CH3_PB8_AF9 +#define TIM4_CH3_PD14_AF2 +#define TIM4_CH4_PB9_AF9 +#define TIM4_CH4_PD15_AF2 +#define TIM4_ETR_PE0_AF2 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_14 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +#define TIM1_BUS (1) +#define TIM4_BUS (1) +#define TIM15_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PE0_CN +#define __PE1_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN +#define __PE6_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PF10_CN +#define __PF11_CN +#define __PF12_CN +#define __PF13_CN +#define __PF2_CN +#define __PF3_CN +#define __PF4_CN +#define __PF5_CN +#define __PF6_CN +#define __PF7_CN +#define __PF8_CN +#define __PF9_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN + +#define PORT_COUNT (6) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +#define UART3_IVT (29) +#define UART3_NVIC (45) +#define UART4_IVT (29) +#define UART4_NVIC (45) +#define UART5_IVT (29) +#define UART5_NVIC (45) +#define UART6_IVT (29) +#define UART6_NVIC (45) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1VC/LQFP100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1VC/LQFP100/mcu_definitions.h new file mode 100644 index 000000000..1a75fa392 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1VC/LQFP100/mcu_definitions.h @@ -0,0 +1,526 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G0B1VC_LQFP100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PB0_CH8 +#define ADC1_PB10_CH11 +#define ADC1_PB11_CH15 +#define ADC1_PB12_CH16 +#define ADC1_PB1_CH9 +#define ADC1_PB2_CH10 +#define ADC1_PC4_CH17 +#define ADC1_PC5_CH18 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF3 +#define FDCAN1_RX_PB8_AF3 +#define FDCAN1_RX_PC4_AF3 +#define FDCAN1_RX_PD0_AF3 +#define FDCAN1_RX_PD12_AF3 +#define FDCAN1_TX_PA12_AF3 +#define FDCAN1_TX_PB9_AF3 +#define FDCAN1_TX_PC5_AF3 +#define FDCAN1_TX_PD13_AF3 +#define FDCAN1_TX_PD1_AF3 +#define FDCAN2_RX_PB0_AF3 +#define FDCAN2_RX_PB12_AF3 +#define FDCAN2_RX_PB5_AF3 +#define FDCAN2_RX_PC2_AF3 +#define FDCAN2_RX_PD14_AF3 +#define FDCAN2_TX_PB13_AF3 +#define FDCAN2_TX_PB1_AF3 +#define FDCAN2_TX_PB6_AF3 +#define FDCAN2_TX_PC3_AF3 +#define FDCAN2_TX_PD15_AF3 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) + +#define CAN_MODULE_COUNT (2) + +#define HAL_LL_FDCAN1_GPIO_AF3 (3) +#define HAL_LL_FDCAN2_GPIO_AF3 (3) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (78) +#define DMA_NUM_OF_CHANNELS_FAMILY (78) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (12) +#define DMA_NUM_OF_STREAMS_FAMILY (12) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PB9_AF6 +#define I2C2_SCL_PA11_AF6 +#define I2C2_SCL_PA7_AF8 +#define I2C2_SCL_PA9_AF8 +#define I2C2_SCL_PB10_AF6 +#define I2C2_SCL_PB13_AF6 +#define I2C2_SCL_PB3_AF8 +#define I2C2_SDA_PA10_AF8 +#define I2C2_SDA_PA12_AF6 +#define I2C2_SDA_PA6_AF8 +#define I2C2_SDA_PB11_AF6 +#define I2C2_SDA_PB14_AF6 +#define I2C2_SDA_PB4_AF8 +#define I2C3_SCL_PA7_AF9 +#define I2C3_SCL_PB3_AF6 +#define I2C3_SCL_PC0_AF6 +#define I2C3_SDA_PA6_AF9 +#define I2C3_SDA_PB4_AF6 +#define I2C3_SDA_PC1_AF6 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF6 +#define LPUART1_RX_PB10_AF1 +#define LPUART1_RX_PC0_AF1 +#define LPUART1_RX_PF5_AF1 +#define LPUART1_TX_PA2_AF6 +#define LPUART1_TX_PB11_AF1 +#define LPUART1_TX_PC1_AF1 +#define LPUART1_TX_PF4_AF1 +#define LPUART2_RX_PA13_AF10 +#define LPUART2_RX_PB7_AF10 +#define LPUART2_RX_PC1_AF3 +#define LPUART2_RX_PC7_AF3 +#define LPUART2_RX_PF3_AF1 +#define LPUART2_TX_PA14_AF10 +#define LPUART2_TX_PB6_AF10 +#define LPUART2_TX_PC0_AF3 +#define LPUART2_TX_PC6_AF3 +#define LPUART2_TX_PF2_AF1 +#define USART1_RX_PA10_AF1 +#define USART1_RX_PB7_AF0 +#define USART1_RX_PC5_AF1 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART1_TX_PC4_AF1 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_RX_PD6_AF0 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 +#define USART2_TX_PD5_AF0 +#define USART3_RX_PB0_AF4 +#define USART3_RX_PB11_AF4 +#define USART3_RX_PB9_AF4 +#define USART3_RX_PC11_AF0 +#define USART3_RX_PC5_AF0 +#define USART3_RX_PD9_AF0 +#define USART3_TX_PA5_AF4 +#define USART3_TX_PB10_AF4 +#define USART3_TX_PB2_AF4 +#define USART3_TX_PB8_AF4 +#define USART3_TX_PC10_AF0 +#define USART3_TX_PC4_AF0 +#define USART3_TX_PD8_AF0 +#define USART4_RX_PA1_AF4 +#define USART4_RX_PC11_AF1 +#define USART4_RX_PE9_AF0 +#define USART4_TX_PA0_AF4 +#define USART4_TX_PC10_AF1 +#define USART4_TX_PE8_AF0 +#define USART5_RX_PB1_AF8 +#define USART5_RX_PB4_AF3 +#define USART5_RX_PD2_AF3 +#define USART5_RX_PE11_AF3 +#define USART5_TX_PB0_AF8 +#define USART5_TX_PB3_AF3 +#define USART5_TX_PC12_AF3 +#define USART5_TX_PD3_AF3 +#define USART5_TX_PE10_AF3 +#define USART6_RX_PA5_AF3 +#define USART6_RX_PB9_AF8 +#define USART6_RX_PC1_AF4 +#define USART6_RX_PF10_AF3 +#define USART6_TX_PA4_AF3 +#define USART6_TX_PB8_AF8 +#define USART6_TX_PC0_AF4 +#define USART6_TX_PF9_AF3 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) +#define UART_MODULE_6 (6) + +#define UART_MODULE_COUNT (6) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MISO_PD5_AF1 +#define SPI1_MISO_PE14_AF0 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_MOSI_PD6_AF1 +#define SPI1_MOSI_PE15_AF0 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI1_SCK_PD8_AF1 +#define SPI1_SCK_PE13_AF0 +#define SPI2_MISO_PA3_AF0 +#define SPI2_MISO_PA9_AF4 +#define SPI2_MISO_PB14_AF0 +#define SPI2_MISO_PB2_AF1 +#define SPI2_MISO_PB6_AF4 +#define SPI2_MISO_PC2_AF1 +#define SPI2_MISO_PD3_AF1 +#define SPI2_MOSI_PA10_AF0 +#define SPI2_MOSI_PA4_AF1 +#define SPI2_MOSI_PB11_AF0 +#define SPI2_MOSI_PB15_AF0 +#define SPI2_MOSI_PB7_AF1 +#define SPI2_MOSI_PC3_AF1 +#define SPI2_MOSI_PD4_AF1 +#define SPI2_SCK_PA0_AF0 +#define SPI2_SCK_PB10_AF5 +#define SPI2_SCK_PB13_AF0 +#define SPI2_SCK_PB8_AF1 +#define SPI2_SCK_PD1_AF1 +#define SPI3_MISO_PB4_AF9 +#define SPI3_MISO_PC11_AF4 +#define SPI3_MOSI_PB5_AF9 +#define SPI3_MOSI_PC12_AF4 +#define SPI3_SCK_PB3_AF9 +#define SPI3_SCK_PC10_AF4 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF5 +#define LPTIM1_ETR_PC3_AF0 +#define LPTIM2_ETR_PA5_AF5 +#define LPTIM2_ETR_PC3_AF2 +#define LPTIM2_ETR_PD11_AF1 +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PB1_AF0 +#define TIM14_CH1_PC12_AF2 +#define TIM14_CH1_PF0_AF2 +#define TIM15_CH1N_PA1_AF5 +#define TIM15_CH1N_PB13_AF5 +#define TIM15_CH1N_PB15_AF4 +#define TIM15_CH1N_PF1_AF2 +#define TIM15_CH1_PA2_AF5 +#define TIM15_CH1_PB14_AF5 +#define TIM15_CH1_PC1_AF2 +#define TIM15_CH1_PF12_AF0 +#define TIM15_CH2_PA3_AF5 +#define TIM15_CH2_PB15_AF5 +#define TIM15_CH2_PC2_AF2 +#define TIM15_CH2_PF13_AF0 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB8_AF2 +#define TIM16_CH1_PD0_AF2 +#define TIM16_CH1_PE0_AF0 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PB9_AF2 +#define TIM17_CH1_PD1_AF2 +#define TIM17_CH1_PE1_AF0 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1N_PB13_AF2 +#define TIM1_CH1N_PD2_AF2 +#define TIM1_CH1N_PE8_AF1 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH1_PC8_AF2 +#define TIM1_CH1_PE9_AF1 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2N_PB14_AF2 +#define TIM1_CH2N_PD3_AF2 +#define TIM1_CH2N_PE10_AF1 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH2_PC9_AF2 +#define TIM1_CH2_PE11_AF1 +#define TIM1_CH3N_PB15_AF2 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3N_PD4_AF2 +#define TIM1_CH3N_PE12_AF1 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH3_PC10_AF2 +#define TIM1_CH3_PE13_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_CH4_PC11_AF2 +#define TIM1_CH4_PE14_AF1 +#define TIM1_ETR_PA12_AF2 +#define TIM1_ETR_PE7_AF1 +#define TIM2_CH1_PA0_AF2 +#define TIM2_CH1_PA15_AF2 +#define TIM2_CH1_PA5_AF2 +#define TIM2_CH1_PC4_AF2 +#define TIM2_CH2_PA1_AF2 +#define TIM2_CH2_PB3_AF2 +#define TIM2_CH2_PC5_AF2 +#define TIM2_CH3_PA2_AF2 +#define TIM2_CH3_PB10_AF2 +#define TIM2_CH3_PC6_AF2 +#define TIM2_CH4_PA3_AF2 +#define TIM2_CH4_PB11_AF2 +#define TIM2_CH4_PC7_AF2 +#define TIM2_ETR_PA0_AF2 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM2_ETR_PC4_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH1_PC6_AF1 +#define TIM3_CH1_PE3_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH2_PC7_AF1 +#define TIM3_CH2_PE4_AF1 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH3_PC8_AF1 +#define TIM3_CH3_PE5_AF1 +#define TIM3_CH4_PB1_AF1 +#define TIM3_CH4_PC9_AF1 +#define TIM3_CH4_PE6_AF1 +#define TIM3_ETR_PD2_AF1 +#define TIM3_ETR_PE2_AF1 +#define TIM4_CH1_PB6_AF9 +#define TIM4_CH1_PD12_AF2 +#define TIM4_CH2_PB7_AF9 +#define TIM4_CH2_PD13_AF2 +#define TIM4_CH3_PB8_AF9 +#define TIM4_CH3_PD14_AF2 +#define TIM4_CH4_PB9_AF9 +#define TIM4_CH4_PD15_AF2 +#define TIM4_ETR_PE0_AF2 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_14 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +#define TIM1_BUS (1) +#define TIM4_BUS (1) +#define TIM15_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PE0_CN +#define __PE1_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN +#define __PE6_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PF10_CN +#define __PF11_CN +#define __PF12_CN +#define __PF13_CN +#define __PF2_CN +#define __PF3_CN +#define __PF4_CN +#define __PF5_CN +#define __PF6_CN +#define __PF7_CN +#define __PF8_CN +#define __PF9_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN + +#define PORT_COUNT (6) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +#define UART3_IVT (29) +#define UART3_NVIC (45) +#define UART4_IVT (29) +#define UART4_NVIC (45) +#define UART5_IVT (29) +#define UART5_NVIC (45) +#define UART6_IVT (29) +#define UART6_NVIC (45) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1VC/UFBGA100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1VC/UFBGA100/mcu_definitions.h new file mode 100644 index 000000000..3782db314 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1VC/UFBGA100/mcu_definitions.h @@ -0,0 +1,526 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G0B1VC_UFBGA100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PB0_CH8 +#define ADC1_PB10_CH11 +#define ADC1_PB11_CH15 +#define ADC1_PB12_CH16 +#define ADC1_PB1_CH9 +#define ADC1_PB2_CH10 +#define ADC1_PC4_CH17 +#define ADC1_PC5_CH18 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF3 +#define FDCAN1_RX_PB8_AF3 +#define FDCAN1_RX_PC4_AF3 +#define FDCAN1_RX_PD0_AF3 +#define FDCAN1_RX_PD12_AF3 +#define FDCAN1_TX_PA12_AF3 +#define FDCAN1_TX_PB9_AF3 +#define FDCAN1_TX_PC5_AF3 +#define FDCAN1_TX_PD13_AF3 +#define FDCAN1_TX_PD1_AF3 +#define FDCAN2_RX_PB0_AF3 +#define FDCAN2_RX_PB12_AF3 +#define FDCAN2_RX_PB5_AF3 +#define FDCAN2_RX_PC2_AF3 +#define FDCAN2_RX_PD14_AF3 +#define FDCAN2_TX_PB13_AF3 +#define FDCAN2_TX_PB1_AF3 +#define FDCAN2_TX_PB6_AF3 +#define FDCAN2_TX_PC3_AF3 +#define FDCAN2_TX_PD15_AF3 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) + +#define CAN_MODULE_COUNT (2) + +#define HAL_LL_FDCAN1_GPIO_AF3 (3) +#define HAL_LL_FDCAN2_GPIO_AF3 (3) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (78) +#define DMA_NUM_OF_CHANNELS_FAMILY (78) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (12) +#define DMA_NUM_OF_STREAMS_FAMILY (12) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PB9_AF6 +#define I2C2_SCL_PA11_AF6 +#define I2C2_SCL_PA7_AF8 +#define I2C2_SCL_PA9_AF8 +#define I2C2_SCL_PB10_AF6 +#define I2C2_SCL_PB13_AF6 +#define I2C2_SCL_PB3_AF8 +#define I2C2_SDA_PA10_AF8 +#define I2C2_SDA_PA12_AF6 +#define I2C2_SDA_PA6_AF8 +#define I2C2_SDA_PB11_AF6 +#define I2C2_SDA_PB14_AF6 +#define I2C2_SDA_PB4_AF8 +#define I2C3_SCL_PA7_AF9 +#define I2C3_SCL_PB3_AF6 +#define I2C3_SCL_PC0_AF6 +#define I2C3_SDA_PA6_AF9 +#define I2C3_SDA_PB4_AF6 +#define I2C3_SDA_PC1_AF6 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF6 +#define LPUART1_RX_PB10_AF1 +#define LPUART1_RX_PC0_AF1 +#define LPUART1_RX_PF5_AF1 +#define LPUART1_TX_PA2_AF6 +#define LPUART1_TX_PB11_AF1 +#define LPUART1_TX_PC1_AF1 +#define LPUART1_TX_PF4_AF1 +#define LPUART2_RX_PA13_AF10 +#define LPUART2_RX_PB7_AF10 +#define LPUART2_RX_PC1_AF3 +#define LPUART2_RX_PC7_AF3 +#define LPUART2_RX_PF3_AF1 +#define LPUART2_TX_PA14_AF10 +#define LPUART2_TX_PB6_AF10 +#define LPUART2_TX_PC0_AF3 +#define LPUART2_TX_PC6_AF3 +#define LPUART2_TX_PF2_AF1 +#define USART1_RX_PA10_AF1 +#define USART1_RX_PB7_AF0 +#define USART1_RX_PC5_AF1 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART1_TX_PC4_AF1 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_RX_PD6_AF0 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 +#define USART2_TX_PD5_AF0 +#define USART3_RX_PB0_AF4 +#define USART3_RX_PB11_AF4 +#define USART3_RX_PB9_AF4 +#define USART3_RX_PC11_AF0 +#define USART3_RX_PC5_AF0 +#define USART3_RX_PD9_AF0 +#define USART3_TX_PA5_AF4 +#define USART3_TX_PB10_AF4 +#define USART3_TX_PB2_AF4 +#define USART3_TX_PB8_AF4 +#define USART3_TX_PC10_AF0 +#define USART3_TX_PC4_AF0 +#define USART3_TX_PD8_AF0 +#define USART4_RX_PA1_AF4 +#define USART4_RX_PC11_AF1 +#define USART4_RX_PE9_AF0 +#define USART4_TX_PA0_AF4 +#define USART4_TX_PC10_AF1 +#define USART4_TX_PE8_AF0 +#define USART5_RX_PB1_AF8 +#define USART5_RX_PB4_AF3 +#define USART5_RX_PD2_AF3 +#define USART5_RX_PE11_AF3 +#define USART5_TX_PB0_AF8 +#define USART5_TX_PB3_AF3 +#define USART5_TX_PC12_AF3 +#define USART5_TX_PD3_AF3 +#define USART5_TX_PE10_AF3 +#define USART6_RX_PA5_AF3 +#define USART6_RX_PB9_AF8 +#define USART6_RX_PC1_AF4 +#define USART6_RX_PF10_AF3 +#define USART6_TX_PA4_AF3 +#define USART6_TX_PB8_AF8 +#define USART6_TX_PC0_AF4 +#define USART6_TX_PF9_AF3 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) +#define UART_MODULE_6 (6) + +#define UART_MODULE_COUNT (6) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MISO_PD5_AF1 +#define SPI1_MISO_PE14_AF0 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_MOSI_PD6_AF1 +#define SPI1_MOSI_PE15_AF0 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI1_SCK_PD8_AF1 +#define SPI1_SCK_PE13_AF0 +#define SPI2_MISO_PA3_AF0 +#define SPI2_MISO_PA9_AF4 +#define SPI2_MISO_PB14_AF0 +#define SPI2_MISO_PB2_AF1 +#define SPI2_MISO_PB6_AF4 +#define SPI2_MISO_PC2_AF1 +#define SPI2_MISO_PD3_AF1 +#define SPI2_MOSI_PA10_AF0 +#define SPI2_MOSI_PA4_AF1 +#define SPI2_MOSI_PB11_AF0 +#define SPI2_MOSI_PB15_AF0 +#define SPI2_MOSI_PB7_AF1 +#define SPI2_MOSI_PC3_AF1 +#define SPI2_MOSI_PD4_AF1 +#define SPI2_SCK_PA0_AF0 +#define SPI2_SCK_PB10_AF5 +#define SPI2_SCK_PB13_AF0 +#define SPI2_SCK_PB8_AF1 +#define SPI2_SCK_PD1_AF1 +#define SPI3_MISO_PB4_AF9 +#define SPI3_MISO_PC11_AF4 +#define SPI3_MOSI_PB5_AF9 +#define SPI3_MOSI_PC12_AF4 +#define SPI3_SCK_PB3_AF9 +#define SPI3_SCK_PC10_AF4 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF5 +#define LPTIM1_ETR_PC3_AF0 +#define LPTIM2_ETR_PA5_AF5 +#define LPTIM2_ETR_PC3_AF2 +#define LPTIM2_ETR_PD11_AF1 +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PB1_AF0 +#define TIM14_CH1_PC12_AF2 +#define TIM14_CH1_PF0_AF2 +#define TIM15_CH1N_PA1_AF5 +#define TIM15_CH1N_PB13_AF5 +#define TIM15_CH1N_PB15_AF4 +#define TIM15_CH1N_PF1_AF2 +#define TIM15_CH1_PA2_AF5 +#define TIM15_CH1_PB14_AF5 +#define TIM15_CH1_PC1_AF2 +#define TIM15_CH1_PF12_AF0 +#define TIM15_CH2_PA3_AF5 +#define TIM15_CH2_PB15_AF5 +#define TIM15_CH2_PC2_AF2 +#define TIM15_CH2_PF13_AF0 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB8_AF2 +#define TIM16_CH1_PD0_AF2 +#define TIM16_CH1_PE0_AF0 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PB9_AF2 +#define TIM17_CH1_PD1_AF2 +#define TIM17_CH1_PE1_AF0 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1N_PB13_AF2 +#define TIM1_CH1N_PD2_AF2 +#define TIM1_CH1N_PE8_AF1 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH1_PC8_AF2 +#define TIM1_CH1_PE9_AF1 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2N_PB14_AF2 +#define TIM1_CH2N_PD3_AF2 +#define TIM1_CH2N_PE10_AF1 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH2_PC9_AF2 +#define TIM1_CH2_PE11_AF1 +#define TIM1_CH3N_PB15_AF2 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3N_PD4_AF2 +#define TIM1_CH3N_PE12_AF1 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH3_PC10_AF2 +#define TIM1_CH3_PE13_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_CH4_PC11_AF2 +#define TIM1_CH4_PE14_AF1 +#define TIM1_ETR_PA12_AF2 +#define TIM1_ETR_PE7_AF1 +#define TIM2_CH1_PA0_AF2 +#define TIM2_CH1_PA15_AF2 +#define TIM2_CH1_PA5_AF2 +#define TIM2_CH1_PC4_AF2 +#define TIM2_CH2_PA1_AF2 +#define TIM2_CH2_PB3_AF2 +#define TIM2_CH2_PC5_AF2 +#define TIM2_CH3_PA2_AF2 +#define TIM2_CH3_PB10_AF2 +#define TIM2_CH3_PC6_AF2 +#define TIM2_CH4_PA3_AF2 +#define TIM2_CH4_PB11_AF2 +#define TIM2_CH4_PC7_AF2 +#define TIM2_ETR_PA0_AF2 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM2_ETR_PC4_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH1_PC6_AF1 +#define TIM3_CH1_PE3_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH2_PC7_AF1 +#define TIM3_CH2_PE4_AF1 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH3_PC8_AF1 +#define TIM3_CH3_PE5_AF1 +#define TIM3_CH4_PB1_AF1 +#define TIM3_CH4_PC9_AF1 +#define TIM3_CH4_PE6_AF1 +#define TIM3_ETR_PD2_AF1 +#define TIM3_ETR_PE2_AF1 +#define TIM4_CH1_PB6_AF9 +#define TIM4_CH1_PD12_AF2 +#define TIM4_CH2_PB7_AF9 +#define TIM4_CH2_PD13_AF2 +#define TIM4_CH3_PB8_AF9 +#define TIM4_CH3_PD14_AF2 +#define TIM4_CH4_PB9_AF9 +#define TIM4_CH4_PD15_AF2 +#define TIM4_ETR_PE0_AF2 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_14 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +#define TIM1_BUS (1) +#define TIM4_BUS (1) +#define TIM15_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PE0_CN +#define __PE1_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN +#define __PE6_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PF10_CN +#define __PF11_CN +#define __PF12_CN +#define __PF13_CN +#define __PF2_CN +#define __PF3_CN +#define __PF4_CN +#define __PF5_CN +#define __PF6_CN +#define __PF7_CN +#define __PF8_CN +#define __PF9_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN + +#define PORT_COUNT (6) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +#define UART3_IVT (29) +#define UART3_NVIC (45) +#define UART4_IVT (29) +#define UART4_NVIC (45) +#define UART5_IVT (29) +#define UART5_NVIC (45) +#define UART6_IVT (29) +#define UART6_NVIC (45) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1VE/LQFP100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1VE/LQFP100/mcu_definitions.h new file mode 100644 index 000000000..67ca77216 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1VE/LQFP100/mcu_definitions.h @@ -0,0 +1,526 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G0B1VE_LQFP100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PB0_CH8 +#define ADC1_PB10_CH11 +#define ADC1_PB11_CH15 +#define ADC1_PB12_CH16 +#define ADC1_PB1_CH9 +#define ADC1_PB2_CH10 +#define ADC1_PC4_CH17 +#define ADC1_PC5_CH18 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF3 +#define FDCAN1_RX_PB8_AF3 +#define FDCAN1_RX_PC4_AF3 +#define FDCAN1_RX_PD0_AF3 +#define FDCAN1_RX_PD12_AF3 +#define FDCAN1_TX_PA12_AF3 +#define FDCAN1_TX_PB9_AF3 +#define FDCAN1_TX_PC5_AF3 +#define FDCAN1_TX_PD13_AF3 +#define FDCAN1_TX_PD1_AF3 +#define FDCAN2_RX_PB0_AF3 +#define FDCAN2_RX_PB12_AF3 +#define FDCAN2_RX_PB5_AF3 +#define FDCAN2_RX_PC2_AF3 +#define FDCAN2_RX_PD14_AF3 +#define FDCAN2_TX_PB13_AF3 +#define FDCAN2_TX_PB1_AF3 +#define FDCAN2_TX_PB6_AF3 +#define FDCAN2_TX_PC3_AF3 +#define FDCAN2_TX_PD15_AF3 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) + +#define CAN_MODULE_COUNT (2) + +#define HAL_LL_FDCAN1_GPIO_AF3 (3) +#define HAL_LL_FDCAN2_GPIO_AF3 (3) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (78) +#define DMA_NUM_OF_CHANNELS_FAMILY (78) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (12) +#define DMA_NUM_OF_STREAMS_FAMILY (12) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PB9_AF6 +#define I2C2_SCL_PA11_AF6 +#define I2C2_SCL_PA7_AF8 +#define I2C2_SCL_PA9_AF8 +#define I2C2_SCL_PB10_AF6 +#define I2C2_SCL_PB13_AF6 +#define I2C2_SCL_PB3_AF8 +#define I2C2_SDA_PA10_AF8 +#define I2C2_SDA_PA12_AF6 +#define I2C2_SDA_PA6_AF8 +#define I2C2_SDA_PB11_AF6 +#define I2C2_SDA_PB14_AF6 +#define I2C2_SDA_PB4_AF8 +#define I2C3_SCL_PA7_AF9 +#define I2C3_SCL_PB3_AF6 +#define I2C3_SCL_PC0_AF6 +#define I2C3_SDA_PA6_AF9 +#define I2C3_SDA_PB4_AF6 +#define I2C3_SDA_PC1_AF6 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF6 +#define LPUART1_RX_PB10_AF1 +#define LPUART1_RX_PC0_AF1 +#define LPUART1_RX_PF5_AF1 +#define LPUART1_TX_PA2_AF6 +#define LPUART1_TX_PB11_AF1 +#define LPUART1_TX_PC1_AF1 +#define LPUART1_TX_PF4_AF1 +#define LPUART2_RX_PA13_AF10 +#define LPUART2_RX_PB7_AF10 +#define LPUART2_RX_PC1_AF3 +#define LPUART2_RX_PC7_AF3 +#define LPUART2_RX_PF3_AF1 +#define LPUART2_TX_PA14_AF10 +#define LPUART2_TX_PB6_AF10 +#define LPUART2_TX_PC0_AF3 +#define LPUART2_TX_PC6_AF3 +#define LPUART2_TX_PF2_AF1 +#define USART1_RX_PA10_AF1 +#define USART1_RX_PB7_AF0 +#define USART1_RX_PC5_AF1 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART1_TX_PC4_AF1 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_RX_PD6_AF0 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 +#define USART2_TX_PD5_AF0 +#define USART3_RX_PB0_AF4 +#define USART3_RX_PB11_AF4 +#define USART3_RX_PB9_AF4 +#define USART3_RX_PC11_AF0 +#define USART3_RX_PC5_AF0 +#define USART3_RX_PD9_AF0 +#define USART3_TX_PA5_AF4 +#define USART3_TX_PB10_AF4 +#define USART3_TX_PB2_AF4 +#define USART3_TX_PB8_AF4 +#define USART3_TX_PC10_AF0 +#define USART3_TX_PC4_AF0 +#define USART3_TX_PD8_AF0 +#define USART4_RX_PA1_AF4 +#define USART4_RX_PC11_AF1 +#define USART4_RX_PE9_AF0 +#define USART4_TX_PA0_AF4 +#define USART4_TX_PC10_AF1 +#define USART4_TX_PE8_AF0 +#define USART5_RX_PB1_AF8 +#define USART5_RX_PB4_AF3 +#define USART5_RX_PD2_AF3 +#define USART5_RX_PE11_AF3 +#define USART5_TX_PB0_AF8 +#define USART5_TX_PB3_AF3 +#define USART5_TX_PC12_AF3 +#define USART5_TX_PD3_AF3 +#define USART5_TX_PE10_AF3 +#define USART6_RX_PA5_AF3 +#define USART6_RX_PB9_AF8 +#define USART6_RX_PC1_AF4 +#define USART6_RX_PF10_AF3 +#define USART6_TX_PA4_AF3 +#define USART6_TX_PB8_AF8 +#define USART6_TX_PC0_AF4 +#define USART6_TX_PF9_AF3 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) +#define UART_MODULE_6 (6) + +#define UART_MODULE_COUNT (6) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MISO_PD5_AF1 +#define SPI1_MISO_PE14_AF0 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_MOSI_PD6_AF1 +#define SPI1_MOSI_PE15_AF0 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI1_SCK_PD8_AF1 +#define SPI1_SCK_PE13_AF0 +#define SPI2_MISO_PA3_AF0 +#define SPI2_MISO_PA9_AF4 +#define SPI2_MISO_PB14_AF0 +#define SPI2_MISO_PB2_AF1 +#define SPI2_MISO_PB6_AF4 +#define SPI2_MISO_PC2_AF1 +#define SPI2_MISO_PD3_AF1 +#define SPI2_MOSI_PA10_AF0 +#define SPI2_MOSI_PA4_AF1 +#define SPI2_MOSI_PB11_AF0 +#define SPI2_MOSI_PB15_AF0 +#define SPI2_MOSI_PB7_AF1 +#define SPI2_MOSI_PC3_AF1 +#define SPI2_MOSI_PD4_AF1 +#define SPI2_SCK_PA0_AF0 +#define SPI2_SCK_PB10_AF5 +#define SPI2_SCK_PB13_AF0 +#define SPI2_SCK_PB8_AF1 +#define SPI2_SCK_PD1_AF1 +#define SPI3_MISO_PB4_AF9 +#define SPI3_MISO_PC11_AF4 +#define SPI3_MOSI_PB5_AF9 +#define SPI3_MOSI_PC12_AF4 +#define SPI3_SCK_PB3_AF9 +#define SPI3_SCK_PC10_AF4 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF5 +#define LPTIM1_ETR_PC3_AF0 +#define LPTIM2_ETR_PA5_AF5 +#define LPTIM2_ETR_PC3_AF2 +#define LPTIM2_ETR_PD11_AF1 +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PB1_AF0 +#define TIM14_CH1_PC12_AF2 +#define TIM14_CH1_PF0_AF2 +#define TIM15_CH1N_PA1_AF5 +#define TIM15_CH1N_PB13_AF5 +#define TIM15_CH1N_PB15_AF4 +#define TIM15_CH1N_PF1_AF2 +#define TIM15_CH1_PA2_AF5 +#define TIM15_CH1_PB14_AF5 +#define TIM15_CH1_PC1_AF2 +#define TIM15_CH1_PF12_AF0 +#define TIM15_CH2_PA3_AF5 +#define TIM15_CH2_PB15_AF5 +#define TIM15_CH2_PC2_AF2 +#define TIM15_CH2_PF13_AF0 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB8_AF2 +#define TIM16_CH1_PD0_AF2 +#define TIM16_CH1_PE0_AF0 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PB9_AF2 +#define TIM17_CH1_PD1_AF2 +#define TIM17_CH1_PE1_AF0 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1N_PB13_AF2 +#define TIM1_CH1N_PD2_AF2 +#define TIM1_CH1N_PE8_AF1 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH1_PC8_AF2 +#define TIM1_CH1_PE9_AF1 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2N_PB14_AF2 +#define TIM1_CH2N_PD3_AF2 +#define TIM1_CH2N_PE10_AF1 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH2_PC9_AF2 +#define TIM1_CH2_PE11_AF1 +#define TIM1_CH3N_PB15_AF2 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3N_PD4_AF2 +#define TIM1_CH3N_PE12_AF1 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH3_PC10_AF2 +#define TIM1_CH3_PE13_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_CH4_PC11_AF2 +#define TIM1_CH4_PE14_AF1 +#define TIM1_ETR_PA12_AF2 +#define TIM1_ETR_PE7_AF1 +#define TIM2_CH1_PA0_AF2 +#define TIM2_CH1_PA15_AF2 +#define TIM2_CH1_PA5_AF2 +#define TIM2_CH1_PC4_AF2 +#define TIM2_CH2_PA1_AF2 +#define TIM2_CH2_PB3_AF2 +#define TIM2_CH2_PC5_AF2 +#define TIM2_CH3_PA2_AF2 +#define TIM2_CH3_PB10_AF2 +#define TIM2_CH3_PC6_AF2 +#define TIM2_CH4_PA3_AF2 +#define TIM2_CH4_PB11_AF2 +#define TIM2_CH4_PC7_AF2 +#define TIM2_ETR_PA0_AF2 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM2_ETR_PC4_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH1_PC6_AF1 +#define TIM3_CH1_PE3_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH2_PC7_AF1 +#define TIM3_CH2_PE4_AF1 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH3_PC8_AF1 +#define TIM3_CH3_PE5_AF1 +#define TIM3_CH4_PB1_AF1 +#define TIM3_CH4_PC9_AF1 +#define TIM3_CH4_PE6_AF1 +#define TIM3_ETR_PD2_AF1 +#define TIM3_ETR_PE2_AF1 +#define TIM4_CH1_PB6_AF9 +#define TIM4_CH1_PD12_AF2 +#define TIM4_CH2_PB7_AF9 +#define TIM4_CH2_PD13_AF2 +#define TIM4_CH3_PB8_AF9 +#define TIM4_CH3_PD14_AF2 +#define TIM4_CH4_PB9_AF9 +#define TIM4_CH4_PD15_AF2 +#define TIM4_ETR_PE0_AF2 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_14 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +#define TIM1_BUS (1) +#define TIM4_BUS (1) +#define TIM15_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PE0_CN +#define __PE1_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN +#define __PE6_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PF10_CN +#define __PF11_CN +#define __PF12_CN +#define __PF13_CN +#define __PF2_CN +#define __PF3_CN +#define __PF4_CN +#define __PF5_CN +#define __PF6_CN +#define __PF7_CN +#define __PF8_CN +#define __PF9_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN + +#define PORT_COUNT (6) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +#define UART3_IVT (29) +#define UART3_NVIC (45) +#define UART4_IVT (29) +#define UART4_NVIC (45) +#define UART5_IVT (29) +#define UART5_NVIC (45) +#define UART6_IVT (29) +#define UART6_NVIC (45) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1VE/UFBGA100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1VE/UFBGA100/mcu_definitions.h new file mode 100644 index 000000000..95846778d --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0B1VE/UFBGA100/mcu_definitions.h @@ -0,0 +1,526 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G0B1VE_UFBGA100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PB0_CH8 +#define ADC1_PB10_CH11 +#define ADC1_PB11_CH15 +#define ADC1_PB12_CH16 +#define ADC1_PB1_CH9 +#define ADC1_PB2_CH10 +#define ADC1_PC4_CH17 +#define ADC1_PC5_CH18 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF3 +#define FDCAN1_RX_PB8_AF3 +#define FDCAN1_RX_PC4_AF3 +#define FDCAN1_RX_PD0_AF3 +#define FDCAN1_RX_PD12_AF3 +#define FDCAN1_TX_PA12_AF3 +#define FDCAN1_TX_PB9_AF3 +#define FDCAN1_TX_PC5_AF3 +#define FDCAN1_TX_PD13_AF3 +#define FDCAN1_TX_PD1_AF3 +#define FDCAN2_RX_PB0_AF3 +#define FDCAN2_RX_PB12_AF3 +#define FDCAN2_RX_PB5_AF3 +#define FDCAN2_RX_PC2_AF3 +#define FDCAN2_RX_PD14_AF3 +#define FDCAN2_TX_PB13_AF3 +#define FDCAN2_TX_PB1_AF3 +#define FDCAN2_TX_PB6_AF3 +#define FDCAN2_TX_PC3_AF3 +#define FDCAN2_TX_PD15_AF3 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) + +#define CAN_MODULE_COUNT (2) + +#define HAL_LL_FDCAN1_GPIO_AF3 (3) +#define HAL_LL_FDCAN2_GPIO_AF3 (3) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (78) +#define DMA_NUM_OF_CHANNELS_FAMILY (78) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (12) +#define DMA_NUM_OF_STREAMS_FAMILY (12) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PB9_AF6 +#define I2C2_SCL_PA11_AF6 +#define I2C2_SCL_PA7_AF8 +#define I2C2_SCL_PA9_AF8 +#define I2C2_SCL_PB10_AF6 +#define I2C2_SCL_PB13_AF6 +#define I2C2_SCL_PB3_AF8 +#define I2C2_SDA_PA10_AF8 +#define I2C2_SDA_PA12_AF6 +#define I2C2_SDA_PA6_AF8 +#define I2C2_SDA_PB11_AF6 +#define I2C2_SDA_PB14_AF6 +#define I2C2_SDA_PB4_AF8 +#define I2C3_SCL_PA7_AF9 +#define I2C3_SCL_PB3_AF6 +#define I2C3_SCL_PC0_AF6 +#define I2C3_SDA_PA6_AF9 +#define I2C3_SDA_PB4_AF6 +#define I2C3_SDA_PC1_AF6 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF6 +#define LPUART1_RX_PB10_AF1 +#define LPUART1_RX_PC0_AF1 +#define LPUART1_RX_PF5_AF1 +#define LPUART1_TX_PA2_AF6 +#define LPUART1_TX_PB11_AF1 +#define LPUART1_TX_PC1_AF1 +#define LPUART1_TX_PF4_AF1 +#define LPUART2_RX_PA13_AF10 +#define LPUART2_RX_PB7_AF10 +#define LPUART2_RX_PC1_AF3 +#define LPUART2_RX_PC7_AF3 +#define LPUART2_RX_PF3_AF1 +#define LPUART2_TX_PA14_AF10 +#define LPUART2_TX_PB6_AF10 +#define LPUART2_TX_PC0_AF3 +#define LPUART2_TX_PC6_AF3 +#define LPUART2_TX_PF2_AF1 +#define USART1_RX_PA10_AF1 +#define USART1_RX_PB7_AF0 +#define USART1_RX_PC5_AF1 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART1_TX_PC4_AF1 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_RX_PD6_AF0 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 +#define USART2_TX_PD5_AF0 +#define USART3_RX_PB0_AF4 +#define USART3_RX_PB11_AF4 +#define USART3_RX_PB9_AF4 +#define USART3_RX_PC11_AF0 +#define USART3_RX_PC5_AF0 +#define USART3_RX_PD9_AF0 +#define USART3_TX_PA5_AF4 +#define USART3_TX_PB10_AF4 +#define USART3_TX_PB2_AF4 +#define USART3_TX_PB8_AF4 +#define USART3_TX_PC10_AF0 +#define USART3_TX_PC4_AF0 +#define USART3_TX_PD8_AF0 +#define USART4_RX_PA1_AF4 +#define USART4_RX_PC11_AF1 +#define USART4_RX_PE9_AF0 +#define USART4_TX_PA0_AF4 +#define USART4_TX_PC10_AF1 +#define USART4_TX_PE8_AF0 +#define USART5_RX_PB1_AF8 +#define USART5_RX_PB4_AF3 +#define USART5_RX_PD2_AF3 +#define USART5_RX_PE11_AF3 +#define USART5_TX_PB0_AF8 +#define USART5_TX_PB3_AF3 +#define USART5_TX_PC12_AF3 +#define USART5_TX_PD3_AF3 +#define USART5_TX_PE10_AF3 +#define USART6_RX_PA5_AF3 +#define USART6_RX_PB9_AF8 +#define USART6_RX_PC1_AF4 +#define USART6_RX_PF10_AF3 +#define USART6_TX_PA4_AF3 +#define USART6_TX_PB8_AF8 +#define USART6_TX_PC0_AF4 +#define USART6_TX_PF9_AF3 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) +#define UART_MODULE_6 (6) + +#define UART_MODULE_COUNT (6) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MISO_PD5_AF1 +#define SPI1_MISO_PE14_AF0 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_MOSI_PD6_AF1 +#define SPI1_MOSI_PE15_AF0 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI1_SCK_PD8_AF1 +#define SPI1_SCK_PE13_AF0 +#define SPI2_MISO_PA3_AF0 +#define SPI2_MISO_PA9_AF4 +#define SPI2_MISO_PB14_AF0 +#define SPI2_MISO_PB2_AF1 +#define SPI2_MISO_PB6_AF4 +#define SPI2_MISO_PC2_AF1 +#define SPI2_MISO_PD3_AF1 +#define SPI2_MOSI_PA10_AF0 +#define SPI2_MOSI_PA4_AF1 +#define SPI2_MOSI_PB11_AF0 +#define SPI2_MOSI_PB15_AF0 +#define SPI2_MOSI_PB7_AF1 +#define SPI2_MOSI_PC3_AF1 +#define SPI2_MOSI_PD4_AF1 +#define SPI2_SCK_PA0_AF0 +#define SPI2_SCK_PB10_AF5 +#define SPI2_SCK_PB13_AF0 +#define SPI2_SCK_PB8_AF1 +#define SPI2_SCK_PD1_AF1 +#define SPI3_MISO_PB4_AF9 +#define SPI3_MISO_PC11_AF4 +#define SPI3_MOSI_PB5_AF9 +#define SPI3_MOSI_PC12_AF4 +#define SPI3_SCK_PB3_AF9 +#define SPI3_SCK_PC10_AF4 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF5 +#define LPTIM1_ETR_PC3_AF0 +#define LPTIM2_ETR_PA5_AF5 +#define LPTIM2_ETR_PC3_AF2 +#define LPTIM2_ETR_PD11_AF1 +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PB1_AF0 +#define TIM14_CH1_PC12_AF2 +#define TIM14_CH1_PF0_AF2 +#define TIM15_CH1N_PA1_AF5 +#define TIM15_CH1N_PB13_AF5 +#define TIM15_CH1N_PB15_AF4 +#define TIM15_CH1N_PF1_AF2 +#define TIM15_CH1_PA2_AF5 +#define TIM15_CH1_PB14_AF5 +#define TIM15_CH1_PC1_AF2 +#define TIM15_CH1_PF12_AF0 +#define TIM15_CH2_PA3_AF5 +#define TIM15_CH2_PB15_AF5 +#define TIM15_CH2_PC2_AF2 +#define TIM15_CH2_PF13_AF0 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB8_AF2 +#define TIM16_CH1_PD0_AF2 +#define TIM16_CH1_PE0_AF0 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PB9_AF2 +#define TIM17_CH1_PD1_AF2 +#define TIM17_CH1_PE1_AF0 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1N_PB13_AF2 +#define TIM1_CH1N_PD2_AF2 +#define TIM1_CH1N_PE8_AF1 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH1_PC8_AF2 +#define TIM1_CH1_PE9_AF1 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2N_PB14_AF2 +#define TIM1_CH2N_PD3_AF2 +#define TIM1_CH2N_PE10_AF1 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH2_PC9_AF2 +#define TIM1_CH2_PE11_AF1 +#define TIM1_CH3N_PB15_AF2 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3N_PD4_AF2 +#define TIM1_CH3N_PE12_AF1 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH3_PC10_AF2 +#define TIM1_CH3_PE13_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_CH4_PC11_AF2 +#define TIM1_CH4_PE14_AF1 +#define TIM1_ETR_PA12_AF2 +#define TIM1_ETR_PE7_AF1 +#define TIM2_CH1_PA0_AF2 +#define TIM2_CH1_PA15_AF2 +#define TIM2_CH1_PA5_AF2 +#define TIM2_CH1_PC4_AF2 +#define TIM2_CH2_PA1_AF2 +#define TIM2_CH2_PB3_AF2 +#define TIM2_CH2_PC5_AF2 +#define TIM2_CH3_PA2_AF2 +#define TIM2_CH3_PB10_AF2 +#define TIM2_CH3_PC6_AF2 +#define TIM2_CH4_PA3_AF2 +#define TIM2_CH4_PB11_AF2 +#define TIM2_CH4_PC7_AF2 +#define TIM2_ETR_PA0_AF2 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM2_ETR_PC4_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH1_PC6_AF1 +#define TIM3_CH1_PE3_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH2_PC7_AF1 +#define TIM3_CH2_PE4_AF1 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH3_PC8_AF1 +#define TIM3_CH3_PE5_AF1 +#define TIM3_CH4_PB1_AF1 +#define TIM3_CH4_PC9_AF1 +#define TIM3_CH4_PE6_AF1 +#define TIM3_ETR_PD2_AF1 +#define TIM3_ETR_PE2_AF1 +#define TIM4_CH1_PB6_AF9 +#define TIM4_CH1_PD12_AF2 +#define TIM4_CH2_PB7_AF9 +#define TIM4_CH2_PD13_AF2 +#define TIM4_CH3_PB8_AF9 +#define TIM4_CH3_PD14_AF2 +#define TIM4_CH4_PB9_AF9 +#define TIM4_CH4_PD15_AF2 +#define TIM4_ETR_PE0_AF2 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_14 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +#define TIM1_BUS (1) +#define TIM4_BUS (1) +#define TIM15_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PE0_CN +#define __PE1_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN +#define __PE6_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PF10_CN +#define __PF11_CN +#define __PF12_CN +#define __PF13_CN +#define __PF2_CN +#define __PF3_CN +#define __PF4_CN +#define __PF5_CN +#define __PF6_CN +#define __PF7_CN +#define __PF8_CN +#define __PF9_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN + +#define PORT_COUNT (6) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +#define UART3_IVT (29) +#define UART3_NVIC (45) +#define UART4_IVT (29) +#define UART4_NVIC (45) +#define UART5_IVT (29) +#define UART5_NVIC (45) +#define UART6_IVT (29) +#define UART6_NVIC (45) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0C1CC/LQFP48/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0C1CC/LQFP48/mcu_definitions.h new file mode 100644 index 000000000..2ef403f47 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0C1CC/LQFP48/mcu_definitions.h @@ -0,0 +1,385 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G0C1CC_LQFP48. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PB0_CH8 +#define ADC1_PB10_CH11 +#define ADC1_PB11_CH15 +#define ADC1_PB12_CH16 +#define ADC1_PB1_CH9 +#define ADC1_PB2_CH10 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF3 +#define FDCAN1_RX_PB8_AF3 +#define FDCAN1_RX_PD0_AF3 +#define FDCAN1_TX_PA12_AF3 +#define FDCAN1_TX_PB9_AF3 +#define FDCAN1_TX_PD1_AF3 +#define FDCAN2_RX_PB0_AF3 +#define FDCAN2_RX_PB12_AF3 +#define FDCAN2_RX_PB5_AF3 +#define FDCAN2_TX_PB13_AF3 +#define FDCAN2_TX_PB1_AF3 +#define FDCAN2_TX_PB6_AF3 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) + +#define CAN_MODULE_COUNT (2) + +#define HAL_LL_FDCAN1_GPIO_AF3 (3) +#define HAL_LL_FDCAN2_GPIO_AF3 (3) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (78) +#define DMA_NUM_OF_CHANNELS_FAMILY (78) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (12) +#define DMA_NUM_OF_STREAMS_FAMILY (12) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PB9_AF6 +#define I2C2_SCL_PA11_AF6 +#define I2C2_SCL_PA7_AF8 +#define I2C2_SCL_PA9_AF8 +#define I2C2_SCL_PB10_AF6 +#define I2C2_SCL_PB13_AF6 +#define I2C2_SCL_PB3_AF8 +#define I2C2_SDA_PA10_AF8 +#define I2C2_SDA_PA12_AF6 +#define I2C2_SDA_PA6_AF8 +#define I2C2_SDA_PB11_AF6 +#define I2C2_SDA_PB14_AF6 +#define I2C2_SDA_PB4_AF8 +#define I2C3_SCL_PA7_AF9 +#define I2C3_SCL_PB3_AF6 +#define I2C3_SDA_PA6_AF9 +#define I2C3_SDA_PB4_AF6 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF6 +#define LPUART1_RX_PB10_AF1 +#define LPUART1_TX_PA2_AF6 +#define LPUART1_TX_PB11_AF1 +#define LPUART2_RX_PA13_AF10 +#define LPUART2_RX_PB7_AF10 +#define LPUART2_RX_PC7_AF3 +#define LPUART2_TX_PA14_AF10 +#define LPUART2_TX_PB6_AF10 +#define LPUART2_TX_PC6_AF3 +#define LPUART2_TX_PF2_AF1 +#define USART1_RX_PA10_AF1 +#define USART1_RX_PB7_AF0 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 +#define USART3_RX_PB0_AF4 +#define USART3_RX_PB11_AF4 +#define USART3_RX_PB9_AF4 +#define USART3_TX_PA5_AF4 +#define USART3_TX_PB10_AF4 +#define USART3_TX_PB2_AF4 +#define USART3_TX_PB8_AF4 +#define USART4_RX_PA1_AF4 +#define USART4_TX_PA0_AF4 +#define USART5_RX_PB1_AF8 +#define USART5_RX_PB4_AF3 +#define USART5_RX_PD2_AF3 +#define USART5_TX_PB0_AF8 +#define USART5_TX_PB3_AF3 +#define USART5_TX_PD3_AF3 +#define USART6_RX_PA5_AF3 +#define USART6_RX_PB9_AF8 +#define USART6_TX_PA4_AF3 +#define USART6_TX_PB8_AF8 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) +#define UART_MODULE_6 (6) + +#define UART_MODULE_COUNT (6) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI2_MISO_PA3_AF0 +#define SPI2_MISO_PA9_AF4 +#define SPI2_MISO_PB14_AF0 +#define SPI2_MISO_PB2_AF1 +#define SPI2_MISO_PB6_AF4 +#define SPI2_MISO_PD3_AF1 +#define SPI2_MOSI_PA10_AF0 +#define SPI2_MOSI_PA4_AF1 +#define SPI2_MOSI_PB11_AF0 +#define SPI2_MOSI_PB15_AF0 +#define SPI2_MOSI_PB7_AF1 +#define SPI2_SCK_PA0_AF0 +#define SPI2_SCK_PB10_AF5 +#define SPI2_SCK_PB13_AF0 +#define SPI2_SCK_PB8_AF1 +#define SPI2_SCK_PD1_AF1 +#define SPI3_MISO_PB4_AF9 +#define SPI3_MOSI_PB5_AF9 +#define SPI3_SCK_PB3_AF9 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF5 +#define LPTIM2_ETR_PA5_AF5 +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PB1_AF0 +#define TIM14_CH1_PF0_AF2 +#define TIM15_CH1N_PA1_AF5 +#define TIM15_CH1N_PB13_AF5 +#define TIM15_CH1N_PB15_AF4 +#define TIM15_CH1N_PF1_AF2 +#define TIM15_CH1_PA2_AF5 +#define TIM15_CH1_PB14_AF5 +#define TIM15_CH2_PA3_AF5 +#define TIM15_CH2_PB15_AF5 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB8_AF2 +#define TIM16_CH1_PD0_AF2 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PB9_AF2 +#define TIM17_CH1_PD1_AF2 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1N_PB13_AF2 +#define TIM1_CH1N_PD2_AF2 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2N_PB14_AF2 +#define TIM1_CH2N_PD3_AF2 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH3N_PB15_AF2 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_ETR_PA12_AF2 +#define TIM2_CH1_PA0_AF2 +#define TIM2_CH1_PA15_AF2 +#define TIM2_CH1_PA5_AF2 +#define TIM2_CH2_PA1_AF2 +#define TIM2_CH2_PB3_AF2 +#define TIM2_CH3_PA2_AF2 +#define TIM2_CH3_PB10_AF2 +#define TIM2_CH3_PC6_AF2 +#define TIM2_CH4_PA3_AF2 +#define TIM2_CH4_PB11_AF2 +#define TIM2_CH4_PC7_AF2 +#define TIM2_ETR_PA0_AF2 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH1_PC6_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH2_PC7_AF1 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH4_PB1_AF1 +#define TIM3_ETR_PD2_AF1 +#define TIM4_CH1_PB6_AF9 +#define TIM4_CH2_PB7_AF9 +#define TIM4_CH3_PB8_AF9 +#define TIM4_CH4_PB9_AF9 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_14 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +#define TIM1_BUS (1) +#define TIM4_BUS (1) +#define TIM15_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC6_CN +#define __PC7_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PF0_CN +#define __PF1_CN +#define __PF2_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_F_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +#define UART3_IVT (29) +#define UART3_NVIC (45) +#define UART4_IVT (29) +#define UART4_NVIC (45) +#define UART5_IVT (29) +#define UART5_NVIC (45) +#define UART6_IVT (29) +#define UART6_NVIC (45) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0C1CC/UFQFPN48/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0C1CC/UFQFPN48/mcu_definitions.h new file mode 100644 index 000000000..0d1e85f03 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0C1CC/UFQFPN48/mcu_definitions.h @@ -0,0 +1,385 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G0C1CC_UFQFPN48. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PB0_CH8 +#define ADC1_PB10_CH11 +#define ADC1_PB11_CH15 +#define ADC1_PB12_CH16 +#define ADC1_PB1_CH9 +#define ADC1_PB2_CH10 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF3 +#define FDCAN1_RX_PB8_AF3 +#define FDCAN1_RX_PD0_AF3 +#define FDCAN1_TX_PA12_AF3 +#define FDCAN1_TX_PB9_AF3 +#define FDCAN1_TX_PD1_AF3 +#define FDCAN2_RX_PB0_AF3 +#define FDCAN2_RX_PB12_AF3 +#define FDCAN2_RX_PB5_AF3 +#define FDCAN2_TX_PB13_AF3 +#define FDCAN2_TX_PB1_AF3 +#define FDCAN2_TX_PB6_AF3 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) + +#define CAN_MODULE_COUNT (2) + +#define HAL_LL_FDCAN1_GPIO_AF3 (3) +#define HAL_LL_FDCAN2_GPIO_AF3 (3) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (78) +#define DMA_NUM_OF_CHANNELS_FAMILY (78) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (12) +#define DMA_NUM_OF_STREAMS_FAMILY (12) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PB9_AF6 +#define I2C2_SCL_PA11_AF6 +#define I2C2_SCL_PA7_AF8 +#define I2C2_SCL_PA9_AF8 +#define I2C2_SCL_PB10_AF6 +#define I2C2_SCL_PB13_AF6 +#define I2C2_SCL_PB3_AF8 +#define I2C2_SDA_PA10_AF8 +#define I2C2_SDA_PA12_AF6 +#define I2C2_SDA_PA6_AF8 +#define I2C2_SDA_PB11_AF6 +#define I2C2_SDA_PB14_AF6 +#define I2C2_SDA_PB4_AF8 +#define I2C3_SCL_PA7_AF9 +#define I2C3_SCL_PB3_AF6 +#define I2C3_SDA_PA6_AF9 +#define I2C3_SDA_PB4_AF6 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF6 +#define LPUART1_RX_PB10_AF1 +#define LPUART1_TX_PA2_AF6 +#define LPUART1_TX_PB11_AF1 +#define LPUART2_RX_PA13_AF10 +#define LPUART2_RX_PB7_AF10 +#define LPUART2_RX_PC7_AF3 +#define LPUART2_TX_PA14_AF10 +#define LPUART2_TX_PB6_AF10 +#define LPUART2_TX_PC6_AF3 +#define LPUART2_TX_PF2_AF1 +#define USART1_RX_PA10_AF1 +#define USART1_RX_PB7_AF0 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 +#define USART3_RX_PB0_AF4 +#define USART3_RX_PB11_AF4 +#define USART3_RX_PB9_AF4 +#define USART3_TX_PA5_AF4 +#define USART3_TX_PB10_AF4 +#define USART3_TX_PB2_AF4 +#define USART3_TX_PB8_AF4 +#define USART4_RX_PA1_AF4 +#define USART4_TX_PA0_AF4 +#define USART5_RX_PB1_AF8 +#define USART5_RX_PB4_AF3 +#define USART5_RX_PD2_AF3 +#define USART5_TX_PB0_AF8 +#define USART5_TX_PB3_AF3 +#define USART5_TX_PD3_AF3 +#define USART6_RX_PA5_AF3 +#define USART6_RX_PB9_AF8 +#define USART6_TX_PA4_AF3 +#define USART6_TX_PB8_AF8 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) +#define UART_MODULE_6 (6) + +#define UART_MODULE_COUNT (6) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI2_MISO_PA3_AF0 +#define SPI2_MISO_PA9_AF4 +#define SPI2_MISO_PB14_AF0 +#define SPI2_MISO_PB2_AF1 +#define SPI2_MISO_PB6_AF4 +#define SPI2_MISO_PD3_AF1 +#define SPI2_MOSI_PA10_AF0 +#define SPI2_MOSI_PA4_AF1 +#define SPI2_MOSI_PB11_AF0 +#define SPI2_MOSI_PB15_AF0 +#define SPI2_MOSI_PB7_AF1 +#define SPI2_SCK_PA0_AF0 +#define SPI2_SCK_PB10_AF5 +#define SPI2_SCK_PB13_AF0 +#define SPI2_SCK_PB8_AF1 +#define SPI2_SCK_PD1_AF1 +#define SPI3_MISO_PB4_AF9 +#define SPI3_MOSI_PB5_AF9 +#define SPI3_SCK_PB3_AF9 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF5 +#define LPTIM2_ETR_PA5_AF5 +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PB1_AF0 +#define TIM14_CH1_PF0_AF2 +#define TIM15_CH1N_PA1_AF5 +#define TIM15_CH1N_PB13_AF5 +#define TIM15_CH1N_PB15_AF4 +#define TIM15_CH1N_PF1_AF2 +#define TIM15_CH1_PA2_AF5 +#define TIM15_CH1_PB14_AF5 +#define TIM15_CH2_PA3_AF5 +#define TIM15_CH2_PB15_AF5 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB8_AF2 +#define TIM16_CH1_PD0_AF2 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PB9_AF2 +#define TIM17_CH1_PD1_AF2 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1N_PB13_AF2 +#define TIM1_CH1N_PD2_AF2 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2N_PB14_AF2 +#define TIM1_CH2N_PD3_AF2 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH3N_PB15_AF2 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_ETR_PA12_AF2 +#define TIM2_CH1_PA0_AF2 +#define TIM2_CH1_PA15_AF2 +#define TIM2_CH1_PA5_AF2 +#define TIM2_CH2_PA1_AF2 +#define TIM2_CH2_PB3_AF2 +#define TIM2_CH3_PA2_AF2 +#define TIM2_CH3_PB10_AF2 +#define TIM2_CH3_PC6_AF2 +#define TIM2_CH4_PA3_AF2 +#define TIM2_CH4_PB11_AF2 +#define TIM2_CH4_PC7_AF2 +#define TIM2_ETR_PA0_AF2 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH1_PC6_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH2_PC7_AF1 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH4_PB1_AF1 +#define TIM3_ETR_PD2_AF1 +#define TIM4_CH1_PB6_AF9 +#define TIM4_CH2_PB7_AF9 +#define TIM4_CH3_PB8_AF9 +#define TIM4_CH4_PB9_AF9 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_14 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +#define TIM1_BUS (1) +#define TIM4_BUS (1) +#define TIM15_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC6_CN +#define __PC7_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PF0_CN +#define __PF1_CN +#define __PF2_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_F_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +#define UART3_IVT (29) +#define UART3_NVIC (45) +#define UART4_IVT (29) +#define UART4_NVIC (45) +#define UART5_IVT (29) +#define UART5_NVIC (45) +#define UART6_IVT (29) +#define UART6_NVIC (45) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0C1CE/LQFP48/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0C1CE/LQFP48/mcu_definitions.h new file mode 100644 index 000000000..4d508d322 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0C1CE/LQFP48/mcu_definitions.h @@ -0,0 +1,385 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G0C1CE_LQFP48. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PB0_CH8 +#define ADC1_PB10_CH11 +#define ADC1_PB11_CH15 +#define ADC1_PB12_CH16 +#define ADC1_PB1_CH9 +#define ADC1_PB2_CH10 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF3 +#define FDCAN1_RX_PB8_AF3 +#define FDCAN1_RX_PD0_AF3 +#define FDCAN1_TX_PA12_AF3 +#define FDCAN1_TX_PB9_AF3 +#define FDCAN1_TX_PD1_AF3 +#define FDCAN2_RX_PB0_AF3 +#define FDCAN2_RX_PB12_AF3 +#define FDCAN2_RX_PB5_AF3 +#define FDCAN2_TX_PB13_AF3 +#define FDCAN2_TX_PB1_AF3 +#define FDCAN2_TX_PB6_AF3 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) + +#define CAN_MODULE_COUNT (2) + +#define HAL_LL_FDCAN1_GPIO_AF3 (3) +#define HAL_LL_FDCAN2_GPIO_AF3 (3) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (78) +#define DMA_NUM_OF_CHANNELS_FAMILY (78) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (12) +#define DMA_NUM_OF_STREAMS_FAMILY (12) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PB9_AF6 +#define I2C2_SCL_PA11_AF6 +#define I2C2_SCL_PA7_AF8 +#define I2C2_SCL_PA9_AF8 +#define I2C2_SCL_PB10_AF6 +#define I2C2_SCL_PB13_AF6 +#define I2C2_SCL_PB3_AF8 +#define I2C2_SDA_PA10_AF8 +#define I2C2_SDA_PA12_AF6 +#define I2C2_SDA_PA6_AF8 +#define I2C2_SDA_PB11_AF6 +#define I2C2_SDA_PB14_AF6 +#define I2C2_SDA_PB4_AF8 +#define I2C3_SCL_PA7_AF9 +#define I2C3_SCL_PB3_AF6 +#define I2C3_SDA_PA6_AF9 +#define I2C3_SDA_PB4_AF6 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF6 +#define LPUART1_RX_PB10_AF1 +#define LPUART1_TX_PA2_AF6 +#define LPUART1_TX_PB11_AF1 +#define LPUART2_RX_PA13_AF10 +#define LPUART2_RX_PB7_AF10 +#define LPUART2_RX_PC7_AF3 +#define LPUART2_TX_PA14_AF10 +#define LPUART2_TX_PB6_AF10 +#define LPUART2_TX_PC6_AF3 +#define LPUART2_TX_PF2_AF1 +#define USART1_RX_PA10_AF1 +#define USART1_RX_PB7_AF0 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 +#define USART3_RX_PB0_AF4 +#define USART3_RX_PB11_AF4 +#define USART3_RX_PB9_AF4 +#define USART3_TX_PA5_AF4 +#define USART3_TX_PB10_AF4 +#define USART3_TX_PB2_AF4 +#define USART3_TX_PB8_AF4 +#define USART4_RX_PA1_AF4 +#define USART4_TX_PA0_AF4 +#define USART5_RX_PB1_AF8 +#define USART5_RX_PB4_AF3 +#define USART5_RX_PD2_AF3 +#define USART5_TX_PB0_AF8 +#define USART5_TX_PB3_AF3 +#define USART5_TX_PD3_AF3 +#define USART6_RX_PA5_AF3 +#define USART6_RX_PB9_AF8 +#define USART6_TX_PA4_AF3 +#define USART6_TX_PB8_AF8 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) +#define UART_MODULE_6 (6) + +#define UART_MODULE_COUNT (6) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI2_MISO_PA3_AF0 +#define SPI2_MISO_PA9_AF4 +#define SPI2_MISO_PB14_AF0 +#define SPI2_MISO_PB2_AF1 +#define SPI2_MISO_PB6_AF4 +#define SPI2_MISO_PD3_AF1 +#define SPI2_MOSI_PA10_AF0 +#define SPI2_MOSI_PA4_AF1 +#define SPI2_MOSI_PB11_AF0 +#define SPI2_MOSI_PB15_AF0 +#define SPI2_MOSI_PB7_AF1 +#define SPI2_SCK_PA0_AF0 +#define SPI2_SCK_PB10_AF5 +#define SPI2_SCK_PB13_AF0 +#define SPI2_SCK_PB8_AF1 +#define SPI2_SCK_PD1_AF1 +#define SPI3_MISO_PB4_AF9 +#define SPI3_MOSI_PB5_AF9 +#define SPI3_SCK_PB3_AF9 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF5 +#define LPTIM2_ETR_PA5_AF5 +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PB1_AF0 +#define TIM14_CH1_PF0_AF2 +#define TIM15_CH1N_PA1_AF5 +#define TIM15_CH1N_PB13_AF5 +#define TIM15_CH1N_PB15_AF4 +#define TIM15_CH1N_PF1_AF2 +#define TIM15_CH1_PA2_AF5 +#define TIM15_CH1_PB14_AF5 +#define TIM15_CH2_PA3_AF5 +#define TIM15_CH2_PB15_AF5 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB8_AF2 +#define TIM16_CH1_PD0_AF2 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PB9_AF2 +#define TIM17_CH1_PD1_AF2 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1N_PB13_AF2 +#define TIM1_CH1N_PD2_AF2 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2N_PB14_AF2 +#define TIM1_CH2N_PD3_AF2 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH3N_PB15_AF2 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_ETR_PA12_AF2 +#define TIM2_CH1_PA0_AF2 +#define TIM2_CH1_PA15_AF2 +#define TIM2_CH1_PA5_AF2 +#define TIM2_CH2_PA1_AF2 +#define TIM2_CH2_PB3_AF2 +#define TIM2_CH3_PA2_AF2 +#define TIM2_CH3_PB10_AF2 +#define TIM2_CH3_PC6_AF2 +#define TIM2_CH4_PA3_AF2 +#define TIM2_CH4_PB11_AF2 +#define TIM2_CH4_PC7_AF2 +#define TIM2_ETR_PA0_AF2 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH1_PC6_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH2_PC7_AF1 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH4_PB1_AF1 +#define TIM3_ETR_PD2_AF1 +#define TIM4_CH1_PB6_AF9 +#define TIM4_CH2_PB7_AF9 +#define TIM4_CH3_PB8_AF9 +#define TIM4_CH4_PB9_AF9 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_14 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +#define TIM1_BUS (1) +#define TIM4_BUS (1) +#define TIM15_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC6_CN +#define __PC7_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PF0_CN +#define __PF1_CN +#define __PF2_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_F_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +#define UART3_IVT (29) +#define UART3_NVIC (45) +#define UART4_IVT (29) +#define UART4_NVIC (45) +#define UART5_IVT (29) +#define UART5_NVIC (45) +#define UART6_IVT (29) +#define UART6_NVIC (45) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0C1CE/UFQFPN48/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0C1CE/UFQFPN48/mcu_definitions.h new file mode 100644 index 000000000..2bf5920ed --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0C1CE/UFQFPN48/mcu_definitions.h @@ -0,0 +1,385 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G0C1CE_UFQFPN48. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PB0_CH8 +#define ADC1_PB10_CH11 +#define ADC1_PB11_CH15 +#define ADC1_PB12_CH16 +#define ADC1_PB1_CH9 +#define ADC1_PB2_CH10 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF3 +#define FDCAN1_RX_PB8_AF3 +#define FDCAN1_RX_PD0_AF3 +#define FDCAN1_TX_PA12_AF3 +#define FDCAN1_TX_PB9_AF3 +#define FDCAN1_TX_PD1_AF3 +#define FDCAN2_RX_PB0_AF3 +#define FDCAN2_RX_PB12_AF3 +#define FDCAN2_RX_PB5_AF3 +#define FDCAN2_TX_PB13_AF3 +#define FDCAN2_TX_PB1_AF3 +#define FDCAN2_TX_PB6_AF3 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) + +#define CAN_MODULE_COUNT (2) + +#define HAL_LL_FDCAN1_GPIO_AF3 (3) +#define HAL_LL_FDCAN2_GPIO_AF3 (3) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (78) +#define DMA_NUM_OF_CHANNELS_FAMILY (78) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (12) +#define DMA_NUM_OF_STREAMS_FAMILY (12) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PB9_AF6 +#define I2C2_SCL_PA11_AF6 +#define I2C2_SCL_PA7_AF8 +#define I2C2_SCL_PA9_AF8 +#define I2C2_SCL_PB10_AF6 +#define I2C2_SCL_PB13_AF6 +#define I2C2_SCL_PB3_AF8 +#define I2C2_SDA_PA10_AF8 +#define I2C2_SDA_PA12_AF6 +#define I2C2_SDA_PA6_AF8 +#define I2C2_SDA_PB11_AF6 +#define I2C2_SDA_PB14_AF6 +#define I2C2_SDA_PB4_AF8 +#define I2C3_SCL_PA7_AF9 +#define I2C3_SCL_PB3_AF6 +#define I2C3_SDA_PA6_AF9 +#define I2C3_SDA_PB4_AF6 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF6 +#define LPUART1_RX_PB10_AF1 +#define LPUART1_TX_PA2_AF6 +#define LPUART1_TX_PB11_AF1 +#define LPUART2_RX_PA13_AF10 +#define LPUART2_RX_PB7_AF10 +#define LPUART2_RX_PC7_AF3 +#define LPUART2_TX_PA14_AF10 +#define LPUART2_TX_PB6_AF10 +#define LPUART2_TX_PC6_AF3 +#define LPUART2_TX_PF2_AF1 +#define USART1_RX_PA10_AF1 +#define USART1_RX_PB7_AF0 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 +#define USART3_RX_PB0_AF4 +#define USART3_RX_PB11_AF4 +#define USART3_RX_PB9_AF4 +#define USART3_TX_PA5_AF4 +#define USART3_TX_PB10_AF4 +#define USART3_TX_PB2_AF4 +#define USART3_TX_PB8_AF4 +#define USART4_RX_PA1_AF4 +#define USART4_TX_PA0_AF4 +#define USART5_RX_PB1_AF8 +#define USART5_RX_PB4_AF3 +#define USART5_RX_PD2_AF3 +#define USART5_TX_PB0_AF8 +#define USART5_TX_PB3_AF3 +#define USART5_TX_PD3_AF3 +#define USART6_RX_PA5_AF3 +#define USART6_RX_PB9_AF8 +#define USART6_TX_PA4_AF3 +#define USART6_TX_PB8_AF8 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) +#define UART_MODULE_6 (6) + +#define UART_MODULE_COUNT (6) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI2_MISO_PA3_AF0 +#define SPI2_MISO_PA9_AF4 +#define SPI2_MISO_PB14_AF0 +#define SPI2_MISO_PB2_AF1 +#define SPI2_MISO_PB6_AF4 +#define SPI2_MISO_PD3_AF1 +#define SPI2_MOSI_PA10_AF0 +#define SPI2_MOSI_PA4_AF1 +#define SPI2_MOSI_PB11_AF0 +#define SPI2_MOSI_PB15_AF0 +#define SPI2_MOSI_PB7_AF1 +#define SPI2_SCK_PA0_AF0 +#define SPI2_SCK_PB10_AF5 +#define SPI2_SCK_PB13_AF0 +#define SPI2_SCK_PB8_AF1 +#define SPI2_SCK_PD1_AF1 +#define SPI3_MISO_PB4_AF9 +#define SPI3_MOSI_PB5_AF9 +#define SPI3_SCK_PB3_AF9 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF5 +#define LPTIM2_ETR_PA5_AF5 +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PB1_AF0 +#define TIM14_CH1_PF0_AF2 +#define TIM15_CH1N_PA1_AF5 +#define TIM15_CH1N_PB13_AF5 +#define TIM15_CH1N_PB15_AF4 +#define TIM15_CH1N_PF1_AF2 +#define TIM15_CH1_PA2_AF5 +#define TIM15_CH1_PB14_AF5 +#define TIM15_CH2_PA3_AF5 +#define TIM15_CH2_PB15_AF5 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB8_AF2 +#define TIM16_CH1_PD0_AF2 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PB9_AF2 +#define TIM17_CH1_PD1_AF2 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1N_PB13_AF2 +#define TIM1_CH1N_PD2_AF2 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2N_PB14_AF2 +#define TIM1_CH2N_PD3_AF2 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH3N_PB15_AF2 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_ETR_PA12_AF2 +#define TIM2_CH1_PA0_AF2 +#define TIM2_CH1_PA15_AF2 +#define TIM2_CH1_PA5_AF2 +#define TIM2_CH2_PA1_AF2 +#define TIM2_CH2_PB3_AF2 +#define TIM2_CH3_PA2_AF2 +#define TIM2_CH3_PB10_AF2 +#define TIM2_CH3_PC6_AF2 +#define TIM2_CH4_PA3_AF2 +#define TIM2_CH4_PB11_AF2 +#define TIM2_CH4_PC7_AF2 +#define TIM2_ETR_PA0_AF2 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH1_PC6_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH2_PC7_AF1 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH4_PB1_AF1 +#define TIM3_ETR_PD2_AF1 +#define TIM4_CH1_PB6_AF9 +#define TIM4_CH2_PB7_AF9 +#define TIM4_CH3_PB8_AF9 +#define TIM4_CH4_PB9_AF9 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_14 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +#define TIM1_BUS (1) +#define TIM4_BUS (1) +#define TIM15_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC6_CN +#define __PC7_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PF0_CN +#define __PF1_CN +#define __PF2_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_F_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +#define UART3_IVT (29) +#define UART3_NVIC (45) +#define UART4_IVT (29) +#define UART4_NVIC (45) +#define UART5_IVT (29) +#define UART5_NVIC (45) +#define UART6_IVT (29) +#define UART6_NVIC (45) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0C1KC/LQFP32/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0C1KC/LQFP32/mcu_definitions.h new file mode 100644 index 000000000..bedf1b8fa --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0C1KC/LQFP32/mcu_definitions.h @@ -0,0 +1,327 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G0C1KC_LQFP32. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PB0_CH8 +#define ADC1_PB1_CH9 +#define ADC1_PB2_CH10 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF3 +#define FDCAN1_RX_PB8_AF3 +#define FDCAN1_TX_PA12_AF3 +#define FDCAN1_TX_PB9_AF3 +#define FDCAN2_RX_PB0_AF3 +#define FDCAN2_RX_PB5_AF3 +#define FDCAN2_TX_PB1_AF3 +#define FDCAN2_TX_PB6_AF3 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) + +#define CAN_MODULE_COUNT (2) + +#define HAL_LL_FDCAN1_GPIO_AF3 (3) +#define HAL_LL_FDCAN2_GPIO_AF3 (3) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (78) +#define DMA_NUM_OF_CHANNELS_FAMILY (78) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (12) +#define DMA_NUM_OF_STREAMS_FAMILY (12) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PB9_AF6 +#define I2C2_SCL_PA11_AF6 +#define I2C2_SCL_PA7_AF8 +#define I2C2_SCL_PA9_AF8 +#define I2C2_SCL_PB3_AF8 +#define I2C2_SDA_PA10_AF8 +#define I2C2_SDA_PA12_AF6 +#define I2C2_SDA_PA6_AF8 +#define I2C2_SDA_PB4_AF8 +#define I2C3_SCL_PA7_AF9 +#define I2C3_SCL_PB3_AF6 +#define I2C3_SDA_PA6_AF9 +#define I2C3_SDA_PB4_AF6 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF6 +#define LPUART1_TX_PA2_AF6 +#define LPUART2_RX_PA13_AF10 +#define LPUART2_RX_PB7_AF10 +#define LPUART2_TX_PA14_AF10 +#define LPUART2_TX_PB6_AF10 +#define LPUART2_TX_PC6_AF3 +#define LPUART2_TX_PF2_AF1 +#define USART1_RX_PA10_AF1 +#define USART1_RX_PB7_AF0 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 +#define USART3_RX_PB0_AF4 +#define USART3_RX_PB9_AF4 +#define USART3_TX_PA5_AF4 +#define USART3_TX_PB2_AF4 +#define USART3_TX_PB8_AF4 +#define USART4_RX_PA1_AF4 +#define USART4_TX_PA0_AF4 +#define USART5_RX_PB1_AF8 +#define USART5_RX_PB4_AF3 +#define USART5_TX_PB0_AF8 +#define USART5_TX_PB3_AF3 +#define USART6_RX_PA5_AF3 +#define USART6_RX_PB9_AF8 +#define USART6_TX_PA4_AF3 +#define USART6_TX_PB8_AF8 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) +#define UART_MODULE_6 (6) + +#define UART_MODULE_COUNT (6) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI2_MISO_PA3_AF0 +#define SPI2_MISO_PA9_AF4 +#define SPI2_MISO_PB2_AF1 +#define SPI2_MISO_PB6_AF4 +#define SPI2_MOSI_PA10_AF0 +#define SPI2_MOSI_PA4_AF1 +#define SPI2_MOSI_PB7_AF1 +#define SPI2_SCK_PA0_AF0 +#define SPI2_SCK_PB8_AF1 +#define SPI3_MISO_PB4_AF9 +#define SPI3_MOSI_PB5_AF9 +#define SPI3_SCK_PB3_AF9 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF5 +#define LPTIM2_ETR_PA5_AF5 +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PB1_AF0 +#define TIM15_CH1N_PA1_AF5 +#define TIM15_CH1_PA2_AF5 +#define TIM15_CH2_PA3_AF5 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB8_AF2 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PB9_AF2 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_ETR_PA12_AF2 +#define TIM2_CH1_PA0_AF2 +#define TIM2_CH1_PA15_AF2 +#define TIM2_CH1_PA5_AF2 +#define TIM2_CH2_PA1_AF2 +#define TIM2_CH2_PB3_AF2 +#define TIM2_CH3_PA2_AF2 +#define TIM2_CH3_PC6_AF2 +#define TIM2_CH4_PA3_AF2 +#define TIM2_ETR_PA0_AF2 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH1_PC6_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH4_PB1_AF1 +#define TIM4_CH1_PB6_AF9 +#define TIM4_CH2_PB7_AF9 +#define TIM4_CH3_PB8_AF9 +#define TIM4_CH4_PB9_AF9 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_14 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +#define TIM1_BUS (1) +#define TIM4_BUS (1) +#define TIM15_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC14_CN +#define __PC15_CN +#define __PC6_CN +#define __PF2_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN + +#define PORT_COUNT (4) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +#define UART3_IVT (29) +#define UART3_NVIC (45) +#define UART4_IVT (29) +#define UART4_NVIC (45) +#define UART5_IVT (29) +#define UART5_NVIC (45) +#define UART6_IVT (29) +#define UART6_NVIC (45) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0C1KC/UFQFPN32/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0C1KC/UFQFPN32/mcu_definitions.h new file mode 100644 index 000000000..6c28aa943 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0C1KC/UFQFPN32/mcu_definitions.h @@ -0,0 +1,327 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G0C1KC_UFQFPN32. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PB0_CH8 +#define ADC1_PB1_CH9 +#define ADC1_PB2_CH10 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF3 +#define FDCAN1_RX_PB8_AF3 +#define FDCAN1_TX_PA12_AF3 +#define FDCAN1_TX_PB9_AF3 +#define FDCAN2_RX_PB0_AF3 +#define FDCAN2_RX_PB5_AF3 +#define FDCAN2_TX_PB1_AF3 +#define FDCAN2_TX_PB6_AF3 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) + +#define CAN_MODULE_COUNT (2) + +#define HAL_LL_FDCAN1_GPIO_AF3 (3) +#define HAL_LL_FDCAN2_GPIO_AF3 (3) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (78) +#define DMA_NUM_OF_CHANNELS_FAMILY (78) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (12) +#define DMA_NUM_OF_STREAMS_FAMILY (12) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PB9_AF6 +#define I2C2_SCL_PA11_AF6 +#define I2C2_SCL_PA7_AF8 +#define I2C2_SCL_PA9_AF8 +#define I2C2_SCL_PB3_AF8 +#define I2C2_SDA_PA10_AF8 +#define I2C2_SDA_PA12_AF6 +#define I2C2_SDA_PA6_AF8 +#define I2C2_SDA_PB4_AF8 +#define I2C3_SCL_PA7_AF9 +#define I2C3_SCL_PB3_AF6 +#define I2C3_SDA_PA6_AF9 +#define I2C3_SDA_PB4_AF6 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF6 +#define LPUART1_TX_PA2_AF6 +#define LPUART2_RX_PA13_AF10 +#define LPUART2_RX_PB7_AF10 +#define LPUART2_TX_PA14_AF10 +#define LPUART2_TX_PB6_AF10 +#define LPUART2_TX_PC6_AF3 +#define LPUART2_TX_PF2_AF1 +#define USART1_RX_PA10_AF1 +#define USART1_RX_PB7_AF0 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 +#define USART3_RX_PB0_AF4 +#define USART3_RX_PB9_AF4 +#define USART3_TX_PA5_AF4 +#define USART3_TX_PB2_AF4 +#define USART3_TX_PB8_AF4 +#define USART4_RX_PA1_AF4 +#define USART4_TX_PA0_AF4 +#define USART5_RX_PB1_AF8 +#define USART5_RX_PB4_AF3 +#define USART5_TX_PB0_AF8 +#define USART5_TX_PB3_AF3 +#define USART6_RX_PA5_AF3 +#define USART6_RX_PB9_AF8 +#define USART6_TX_PA4_AF3 +#define USART6_TX_PB8_AF8 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) +#define UART_MODULE_6 (6) + +#define UART_MODULE_COUNT (6) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI2_MISO_PA3_AF0 +#define SPI2_MISO_PA9_AF4 +#define SPI2_MISO_PB2_AF1 +#define SPI2_MISO_PB6_AF4 +#define SPI2_MOSI_PA10_AF0 +#define SPI2_MOSI_PA4_AF1 +#define SPI2_MOSI_PB7_AF1 +#define SPI2_SCK_PA0_AF0 +#define SPI2_SCK_PB8_AF1 +#define SPI3_MISO_PB4_AF9 +#define SPI3_MOSI_PB5_AF9 +#define SPI3_SCK_PB3_AF9 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF5 +#define LPTIM2_ETR_PA5_AF5 +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PB1_AF0 +#define TIM15_CH1N_PA1_AF5 +#define TIM15_CH1_PA2_AF5 +#define TIM15_CH2_PA3_AF5 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB8_AF2 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PB9_AF2 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_ETR_PA12_AF2 +#define TIM2_CH1_PA0_AF2 +#define TIM2_CH1_PA15_AF2 +#define TIM2_CH1_PA5_AF2 +#define TIM2_CH2_PA1_AF2 +#define TIM2_CH2_PB3_AF2 +#define TIM2_CH3_PA2_AF2 +#define TIM2_CH3_PC6_AF2 +#define TIM2_CH4_PA3_AF2 +#define TIM2_ETR_PA0_AF2 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH1_PC6_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH4_PB1_AF1 +#define TIM4_CH1_PB6_AF9 +#define TIM4_CH2_PB7_AF9 +#define TIM4_CH3_PB8_AF9 +#define TIM4_CH4_PB9_AF9 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_14 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +#define TIM1_BUS (1) +#define TIM4_BUS (1) +#define TIM15_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC14_CN +#define __PC15_CN +#define __PC6_CN +#define __PF2_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN + +#define PORT_COUNT (4) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +#define UART3_IVT (29) +#define UART3_NVIC (45) +#define UART4_IVT (29) +#define UART4_NVIC (45) +#define UART5_IVT (29) +#define UART5_NVIC (45) +#define UART6_IVT (29) +#define UART6_NVIC (45) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0C1KE/LQFP32/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0C1KE/LQFP32/mcu_definitions.h new file mode 100644 index 000000000..540d7e47b --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0C1KE/LQFP32/mcu_definitions.h @@ -0,0 +1,327 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G0C1KE_LQFP32. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PB0_CH8 +#define ADC1_PB1_CH9 +#define ADC1_PB2_CH10 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF3 +#define FDCAN1_RX_PB8_AF3 +#define FDCAN1_TX_PA12_AF3 +#define FDCAN1_TX_PB9_AF3 +#define FDCAN2_RX_PB0_AF3 +#define FDCAN2_RX_PB5_AF3 +#define FDCAN2_TX_PB1_AF3 +#define FDCAN2_TX_PB6_AF3 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) + +#define CAN_MODULE_COUNT (2) + +#define HAL_LL_FDCAN1_GPIO_AF3 (3) +#define HAL_LL_FDCAN2_GPIO_AF3 (3) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (78) +#define DMA_NUM_OF_CHANNELS_FAMILY (78) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (12) +#define DMA_NUM_OF_STREAMS_FAMILY (12) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PB9_AF6 +#define I2C2_SCL_PA11_AF6 +#define I2C2_SCL_PA7_AF8 +#define I2C2_SCL_PA9_AF8 +#define I2C2_SCL_PB3_AF8 +#define I2C2_SDA_PA10_AF8 +#define I2C2_SDA_PA12_AF6 +#define I2C2_SDA_PA6_AF8 +#define I2C2_SDA_PB4_AF8 +#define I2C3_SCL_PA7_AF9 +#define I2C3_SCL_PB3_AF6 +#define I2C3_SDA_PA6_AF9 +#define I2C3_SDA_PB4_AF6 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF6 +#define LPUART1_TX_PA2_AF6 +#define LPUART2_RX_PA13_AF10 +#define LPUART2_RX_PB7_AF10 +#define LPUART2_TX_PA14_AF10 +#define LPUART2_TX_PB6_AF10 +#define LPUART2_TX_PC6_AF3 +#define LPUART2_TX_PF2_AF1 +#define USART1_RX_PA10_AF1 +#define USART1_RX_PB7_AF0 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 +#define USART3_RX_PB0_AF4 +#define USART3_RX_PB9_AF4 +#define USART3_TX_PA5_AF4 +#define USART3_TX_PB2_AF4 +#define USART3_TX_PB8_AF4 +#define USART4_RX_PA1_AF4 +#define USART4_TX_PA0_AF4 +#define USART5_RX_PB1_AF8 +#define USART5_RX_PB4_AF3 +#define USART5_TX_PB0_AF8 +#define USART5_TX_PB3_AF3 +#define USART6_RX_PA5_AF3 +#define USART6_RX_PB9_AF8 +#define USART6_TX_PA4_AF3 +#define USART6_TX_PB8_AF8 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) +#define UART_MODULE_6 (6) + +#define UART_MODULE_COUNT (6) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI2_MISO_PA3_AF0 +#define SPI2_MISO_PA9_AF4 +#define SPI2_MISO_PB2_AF1 +#define SPI2_MISO_PB6_AF4 +#define SPI2_MOSI_PA10_AF0 +#define SPI2_MOSI_PA4_AF1 +#define SPI2_MOSI_PB7_AF1 +#define SPI2_SCK_PA0_AF0 +#define SPI2_SCK_PB8_AF1 +#define SPI3_MISO_PB4_AF9 +#define SPI3_MOSI_PB5_AF9 +#define SPI3_SCK_PB3_AF9 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF5 +#define LPTIM2_ETR_PA5_AF5 +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PB1_AF0 +#define TIM15_CH1N_PA1_AF5 +#define TIM15_CH1_PA2_AF5 +#define TIM15_CH2_PA3_AF5 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB8_AF2 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PB9_AF2 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_ETR_PA12_AF2 +#define TIM2_CH1_PA0_AF2 +#define TIM2_CH1_PA15_AF2 +#define TIM2_CH1_PA5_AF2 +#define TIM2_CH2_PA1_AF2 +#define TIM2_CH2_PB3_AF2 +#define TIM2_CH3_PA2_AF2 +#define TIM2_CH3_PC6_AF2 +#define TIM2_CH4_PA3_AF2 +#define TIM2_ETR_PA0_AF2 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH1_PC6_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH4_PB1_AF1 +#define TIM4_CH1_PB6_AF9 +#define TIM4_CH2_PB7_AF9 +#define TIM4_CH3_PB8_AF9 +#define TIM4_CH4_PB9_AF9 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_14 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +#define TIM1_BUS (1) +#define TIM4_BUS (1) +#define TIM15_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC14_CN +#define __PC15_CN +#define __PC6_CN +#define __PF2_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN + +#define PORT_COUNT (4) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +#define UART3_IVT (29) +#define UART3_NVIC (45) +#define UART4_IVT (29) +#define UART4_NVIC (45) +#define UART5_IVT (29) +#define UART5_NVIC (45) +#define UART6_IVT (29) +#define UART6_NVIC (45) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0C1KE/UFQFPN32/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0C1KE/UFQFPN32/mcu_definitions.h new file mode 100644 index 000000000..c05348ce4 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0C1KE/UFQFPN32/mcu_definitions.h @@ -0,0 +1,327 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G0C1KE_UFQFPN32. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PB0_CH8 +#define ADC1_PB1_CH9 +#define ADC1_PB2_CH10 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF3 +#define FDCAN1_RX_PB8_AF3 +#define FDCAN1_TX_PA12_AF3 +#define FDCAN1_TX_PB9_AF3 +#define FDCAN2_RX_PB0_AF3 +#define FDCAN2_RX_PB5_AF3 +#define FDCAN2_TX_PB1_AF3 +#define FDCAN2_TX_PB6_AF3 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) + +#define CAN_MODULE_COUNT (2) + +#define HAL_LL_FDCAN1_GPIO_AF3 (3) +#define HAL_LL_FDCAN2_GPIO_AF3 (3) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (78) +#define DMA_NUM_OF_CHANNELS_FAMILY (78) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (12) +#define DMA_NUM_OF_STREAMS_FAMILY (12) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PB9_AF6 +#define I2C2_SCL_PA11_AF6 +#define I2C2_SCL_PA7_AF8 +#define I2C2_SCL_PA9_AF8 +#define I2C2_SCL_PB3_AF8 +#define I2C2_SDA_PA10_AF8 +#define I2C2_SDA_PA12_AF6 +#define I2C2_SDA_PA6_AF8 +#define I2C2_SDA_PB4_AF8 +#define I2C3_SCL_PA7_AF9 +#define I2C3_SCL_PB3_AF6 +#define I2C3_SDA_PA6_AF9 +#define I2C3_SDA_PB4_AF6 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF6 +#define LPUART1_TX_PA2_AF6 +#define LPUART2_RX_PA13_AF10 +#define LPUART2_RX_PB7_AF10 +#define LPUART2_TX_PA14_AF10 +#define LPUART2_TX_PB6_AF10 +#define LPUART2_TX_PC6_AF3 +#define LPUART2_TX_PF2_AF1 +#define USART1_RX_PA10_AF1 +#define USART1_RX_PB7_AF0 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 +#define USART3_RX_PB0_AF4 +#define USART3_RX_PB9_AF4 +#define USART3_TX_PA5_AF4 +#define USART3_TX_PB2_AF4 +#define USART3_TX_PB8_AF4 +#define USART4_RX_PA1_AF4 +#define USART4_TX_PA0_AF4 +#define USART5_RX_PB1_AF8 +#define USART5_RX_PB4_AF3 +#define USART5_TX_PB0_AF8 +#define USART5_TX_PB3_AF3 +#define USART6_RX_PA5_AF3 +#define USART6_RX_PB9_AF8 +#define USART6_TX_PA4_AF3 +#define USART6_TX_PB8_AF8 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) +#define UART_MODULE_6 (6) + +#define UART_MODULE_COUNT (6) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI2_MISO_PA3_AF0 +#define SPI2_MISO_PA9_AF4 +#define SPI2_MISO_PB2_AF1 +#define SPI2_MISO_PB6_AF4 +#define SPI2_MOSI_PA10_AF0 +#define SPI2_MOSI_PA4_AF1 +#define SPI2_MOSI_PB7_AF1 +#define SPI2_SCK_PA0_AF0 +#define SPI2_SCK_PB8_AF1 +#define SPI3_MISO_PB4_AF9 +#define SPI3_MOSI_PB5_AF9 +#define SPI3_SCK_PB3_AF9 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF5 +#define LPTIM2_ETR_PA5_AF5 +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PB1_AF0 +#define TIM15_CH1N_PA1_AF5 +#define TIM15_CH1_PA2_AF5 +#define TIM15_CH2_PA3_AF5 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB8_AF2 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PB9_AF2 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_ETR_PA12_AF2 +#define TIM2_CH1_PA0_AF2 +#define TIM2_CH1_PA15_AF2 +#define TIM2_CH1_PA5_AF2 +#define TIM2_CH2_PA1_AF2 +#define TIM2_CH2_PB3_AF2 +#define TIM2_CH3_PA2_AF2 +#define TIM2_CH3_PC6_AF2 +#define TIM2_CH4_PA3_AF2 +#define TIM2_ETR_PA0_AF2 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH1_PC6_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH4_PB1_AF1 +#define TIM4_CH1_PB6_AF9 +#define TIM4_CH2_PB7_AF9 +#define TIM4_CH3_PB8_AF9 +#define TIM4_CH4_PB9_AF9 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_14 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +#define TIM1_BUS (1) +#define TIM4_BUS (1) +#define TIM15_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC14_CN +#define __PC15_CN +#define __PC6_CN +#define __PF2_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN + +#define PORT_COUNT (4) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +#define UART3_IVT (29) +#define UART3_NVIC (45) +#define UART4_IVT (29) +#define UART4_NVIC (45) +#define UART5_IVT (29) +#define UART5_NVIC (45) +#define UART6_IVT (29) +#define UART6_NVIC (45) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0C1MC/LQFP80/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0C1MC/LQFP80/mcu_definitions.h new file mode 100644 index 000000000..4f1b34fb4 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0C1MC/LQFP80/mcu_definitions.h @@ -0,0 +1,487 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G0C1MC_LQFP80. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PB0_CH8 +#define ADC1_PB10_CH11 +#define ADC1_PB11_CH15 +#define ADC1_PB12_CH16 +#define ADC1_PB1_CH9 +#define ADC1_PB2_CH10 +#define ADC1_PC4_CH17 +#define ADC1_PC5_CH18 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF3 +#define FDCAN1_RX_PB8_AF3 +#define FDCAN1_RX_PC4_AF3 +#define FDCAN1_RX_PD0_AF3 +#define FDCAN1_RX_PD12_AF3 +#define FDCAN1_TX_PA12_AF3 +#define FDCAN1_TX_PB9_AF3 +#define FDCAN1_TX_PC5_AF3 +#define FDCAN1_TX_PD13_AF3 +#define FDCAN1_TX_PD1_AF3 +#define FDCAN2_RX_PB0_AF3 +#define FDCAN2_RX_PB12_AF3 +#define FDCAN2_RX_PB5_AF3 +#define FDCAN2_RX_PC2_AF3 +#define FDCAN2_RX_PD14_AF3 +#define FDCAN2_TX_PB13_AF3 +#define FDCAN2_TX_PB1_AF3 +#define FDCAN2_TX_PB6_AF3 +#define FDCAN2_TX_PC3_AF3 +#define FDCAN2_TX_PD15_AF3 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) + +#define CAN_MODULE_COUNT (2) + +#define HAL_LL_FDCAN1_GPIO_AF3 (3) +#define HAL_LL_FDCAN2_GPIO_AF3 (3) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (78) +#define DMA_NUM_OF_CHANNELS_FAMILY (78) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (12) +#define DMA_NUM_OF_STREAMS_FAMILY (12) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PB9_AF6 +#define I2C2_SCL_PA11_AF6 +#define I2C2_SCL_PA7_AF8 +#define I2C2_SCL_PA9_AF8 +#define I2C2_SCL_PB10_AF6 +#define I2C2_SCL_PB13_AF6 +#define I2C2_SCL_PB3_AF8 +#define I2C2_SDA_PA10_AF8 +#define I2C2_SDA_PA12_AF6 +#define I2C2_SDA_PA6_AF8 +#define I2C2_SDA_PB11_AF6 +#define I2C2_SDA_PB14_AF6 +#define I2C2_SDA_PB4_AF8 +#define I2C3_SCL_PA7_AF9 +#define I2C3_SCL_PB3_AF6 +#define I2C3_SCL_PC0_AF6 +#define I2C3_SDA_PA6_AF9 +#define I2C3_SDA_PB4_AF6 +#define I2C3_SDA_PC1_AF6 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF6 +#define LPUART1_RX_PB10_AF1 +#define LPUART1_RX_PC0_AF1 +#define LPUART1_TX_PA2_AF6 +#define LPUART1_TX_PB11_AF1 +#define LPUART1_TX_PC1_AF1 +#define LPUART2_RX_PA13_AF10 +#define LPUART2_RX_PB7_AF10 +#define LPUART2_RX_PC1_AF3 +#define LPUART2_RX_PC7_AF3 +#define LPUART2_TX_PA14_AF10 +#define LPUART2_TX_PB6_AF10 +#define LPUART2_TX_PC0_AF3 +#define LPUART2_TX_PC6_AF3 +#define LPUART2_TX_PF2_AF1 +#define USART1_RX_PA10_AF1 +#define USART1_RX_PB7_AF0 +#define USART1_RX_PC5_AF1 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART1_TX_PC4_AF1 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_RX_PD6_AF0 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 +#define USART2_TX_PD5_AF0 +#define USART3_RX_PB0_AF4 +#define USART3_RX_PB11_AF4 +#define USART3_RX_PB9_AF4 +#define USART3_RX_PC11_AF0 +#define USART3_RX_PC5_AF0 +#define USART3_RX_PD9_AF0 +#define USART3_TX_PA5_AF4 +#define USART3_TX_PB10_AF4 +#define USART3_TX_PB2_AF4 +#define USART3_TX_PB8_AF4 +#define USART3_TX_PC10_AF0 +#define USART3_TX_PC4_AF0 +#define USART3_TX_PD8_AF0 +#define USART4_RX_PA1_AF4 +#define USART4_RX_PC11_AF1 +#define USART4_RX_PE9_AF0 +#define USART4_TX_PA0_AF4 +#define USART4_TX_PC10_AF1 +#define USART4_TX_PE8_AF0 +#define USART5_RX_PB1_AF8 +#define USART5_RX_PB4_AF3 +#define USART5_RX_PD2_AF3 +#define USART5_TX_PB0_AF8 +#define USART5_TX_PB3_AF3 +#define USART5_TX_PC12_AF3 +#define USART5_TX_PD3_AF3 +#define USART5_TX_PE10_AF3 +#define USART6_RX_PA5_AF3 +#define USART6_RX_PB9_AF8 +#define USART6_RX_PC1_AF4 +#define USART6_TX_PA4_AF3 +#define USART6_TX_PB8_AF8 +#define USART6_TX_PC0_AF4 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) +#define UART_MODULE_6 (6) + +#define UART_MODULE_COUNT (6) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MISO_PD5_AF1 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_MOSI_PD6_AF1 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI1_SCK_PD8_AF1 +#define SPI2_MISO_PA3_AF0 +#define SPI2_MISO_PA9_AF4 +#define SPI2_MISO_PB14_AF0 +#define SPI2_MISO_PB2_AF1 +#define SPI2_MISO_PB6_AF4 +#define SPI2_MISO_PC2_AF1 +#define SPI2_MISO_PD3_AF1 +#define SPI2_MOSI_PA10_AF0 +#define SPI2_MOSI_PA4_AF1 +#define SPI2_MOSI_PB11_AF0 +#define SPI2_MOSI_PB15_AF0 +#define SPI2_MOSI_PB7_AF1 +#define SPI2_MOSI_PC3_AF1 +#define SPI2_MOSI_PD4_AF1 +#define SPI2_SCK_PA0_AF0 +#define SPI2_SCK_PB10_AF5 +#define SPI2_SCK_PB13_AF0 +#define SPI2_SCK_PB8_AF1 +#define SPI2_SCK_PD1_AF1 +#define SPI3_MISO_PB4_AF9 +#define SPI3_MISO_PC11_AF4 +#define SPI3_MOSI_PB5_AF9 +#define SPI3_MOSI_PC12_AF4 +#define SPI3_SCK_PB3_AF9 +#define SPI3_SCK_PC10_AF4 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF5 +#define LPTIM1_ETR_PC3_AF0 +#define LPTIM2_ETR_PA5_AF5 +#define LPTIM2_ETR_PC3_AF2 +#define LPTIM2_ETR_PD11_AF1 +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PB1_AF0 +#define TIM14_CH1_PC12_AF2 +#define TIM14_CH1_PF0_AF2 +#define TIM15_CH1N_PA1_AF5 +#define TIM15_CH1N_PB13_AF5 +#define TIM15_CH1N_PB15_AF4 +#define TIM15_CH1N_PF1_AF2 +#define TIM15_CH1_PA2_AF5 +#define TIM15_CH1_PB14_AF5 +#define TIM15_CH1_PC1_AF2 +#define TIM15_CH2_PA3_AF5 +#define TIM15_CH2_PB15_AF5 +#define TIM15_CH2_PC2_AF2 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB8_AF2 +#define TIM16_CH1_PD0_AF2 +#define TIM16_CH1_PE0_AF0 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PB9_AF2 +#define TIM17_CH1_PD1_AF2 +#define TIM17_CH1_PE1_AF0 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1N_PB13_AF2 +#define TIM1_CH1N_PD2_AF2 +#define TIM1_CH1N_PE8_AF1 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH1_PC8_AF2 +#define TIM1_CH1_PE9_AF1 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2N_PB14_AF2 +#define TIM1_CH2N_PD3_AF2 +#define TIM1_CH2N_PE10_AF1 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH2_PC9_AF2 +#define TIM1_CH3N_PB15_AF2 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3N_PD4_AF2 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH3_PC10_AF2 +#define TIM1_CH4_PA11_AF2 +#define TIM1_CH4_PC11_AF2 +#define TIM1_ETR_PA12_AF2 +#define TIM1_ETR_PE7_AF1 +#define TIM2_CH1_PA0_AF2 +#define TIM2_CH1_PA15_AF2 +#define TIM2_CH1_PA5_AF2 +#define TIM2_CH1_PC4_AF2 +#define TIM2_CH2_PA1_AF2 +#define TIM2_CH2_PB3_AF2 +#define TIM2_CH2_PC5_AF2 +#define TIM2_CH3_PA2_AF2 +#define TIM2_CH3_PB10_AF2 +#define TIM2_CH3_PC6_AF2 +#define TIM2_CH4_PA3_AF2 +#define TIM2_CH4_PB11_AF2 +#define TIM2_CH4_PC7_AF2 +#define TIM2_ETR_PA0_AF2 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM2_ETR_PC4_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH1_PC6_AF1 +#define TIM3_CH1_PE3_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH2_PC7_AF1 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH3_PC8_AF1 +#define TIM3_CH4_PB1_AF1 +#define TIM3_CH4_PC9_AF1 +#define TIM3_ETR_PD2_AF1 +#define TIM4_CH1_PB6_AF9 +#define TIM4_CH1_PD12_AF2 +#define TIM4_CH2_PB7_AF9 +#define TIM4_CH2_PD13_AF2 +#define TIM4_CH3_PB8_AF9 +#define TIM4_CH3_PD14_AF2 +#define TIM4_CH4_PB9_AF9 +#define TIM4_CH4_PD15_AF2 +#define TIM4_ETR_PE0_AF2 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_14 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +#define TIM1_BUS (1) +#define TIM4_BUS (1) +#define TIM15_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PE0_CN +#define __PE1_CN +#define __PE10_CN +#define __PE3_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PF2_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN + +#define PORT_COUNT (6) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +#define UART3_IVT (29) +#define UART3_NVIC (45) +#define UART4_IVT (29) +#define UART4_NVIC (45) +#define UART5_IVT (29) +#define UART5_NVIC (45) +#define UART6_IVT (29) +#define UART6_NVIC (45) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0C1ME/LQFP80/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0C1ME/LQFP80/mcu_definitions.h new file mode 100644 index 000000000..79d6073da --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0C1ME/LQFP80/mcu_definitions.h @@ -0,0 +1,487 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G0C1ME_LQFP80. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PB0_CH8 +#define ADC1_PB10_CH11 +#define ADC1_PB11_CH15 +#define ADC1_PB12_CH16 +#define ADC1_PB1_CH9 +#define ADC1_PB2_CH10 +#define ADC1_PC4_CH17 +#define ADC1_PC5_CH18 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF3 +#define FDCAN1_RX_PB8_AF3 +#define FDCAN1_RX_PC4_AF3 +#define FDCAN1_RX_PD0_AF3 +#define FDCAN1_RX_PD12_AF3 +#define FDCAN1_TX_PA12_AF3 +#define FDCAN1_TX_PB9_AF3 +#define FDCAN1_TX_PC5_AF3 +#define FDCAN1_TX_PD13_AF3 +#define FDCAN1_TX_PD1_AF3 +#define FDCAN2_RX_PB0_AF3 +#define FDCAN2_RX_PB12_AF3 +#define FDCAN2_RX_PB5_AF3 +#define FDCAN2_RX_PC2_AF3 +#define FDCAN2_RX_PD14_AF3 +#define FDCAN2_TX_PB13_AF3 +#define FDCAN2_TX_PB1_AF3 +#define FDCAN2_TX_PB6_AF3 +#define FDCAN2_TX_PC3_AF3 +#define FDCAN2_TX_PD15_AF3 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) + +#define CAN_MODULE_COUNT (2) + +#define HAL_LL_FDCAN1_GPIO_AF3 (3) +#define HAL_LL_FDCAN2_GPIO_AF3 (3) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (78) +#define DMA_NUM_OF_CHANNELS_FAMILY (78) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (12) +#define DMA_NUM_OF_STREAMS_FAMILY (12) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PB9_AF6 +#define I2C2_SCL_PA11_AF6 +#define I2C2_SCL_PA7_AF8 +#define I2C2_SCL_PA9_AF8 +#define I2C2_SCL_PB10_AF6 +#define I2C2_SCL_PB13_AF6 +#define I2C2_SCL_PB3_AF8 +#define I2C2_SDA_PA10_AF8 +#define I2C2_SDA_PA12_AF6 +#define I2C2_SDA_PA6_AF8 +#define I2C2_SDA_PB11_AF6 +#define I2C2_SDA_PB14_AF6 +#define I2C2_SDA_PB4_AF8 +#define I2C3_SCL_PA7_AF9 +#define I2C3_SCL_PB3_AF6 +#define I2C3_SCL_PC0_AF6 +#define I2C3_SDA_PA6_AF9 +#define I2C3_SDA_PB4_AF6 +#define I2C3_SDA_PC1_AF6 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF6 +#define LPUART1_RX_PB10_AF1 +#define LPUART1_RX_PC0_AF1 +#define LPUART1_TX_PA2_AF6 +#define LPUART1_TX_PB11_AF1 +#define LPUART1_TX_PC1_AF1 +#define LPUART2_RX_PA13_AF10 +#define LPUART2_RX_PB7_AF10 +#define LPUART2_RX_PC1_AF3 +#define LPUART2_RX_PC7_AF3 +#define LPUART2_TX_PA14_AF10 +#define LPUART2_TX_PB6_AF10 +#define LPUART2_TX_PC0_AF3 +#define LPUART2_TX_PC6_AF3 +#define LPUART2_TX_PF2_AF1 +#define USART1_RX_PA10_AF1 +#define USART1_RX_PB7_AF0 +#define USART1_RX_PC5_AF1 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART1_TX_PC4_AF1 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_RX_PD6_AF0 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 +#define USART2_TX_PD5_AF0 +#define USART3_RX_PB0_AF4 +#define USART3_RX_PB11_AF4 +#define USART3_RX_PB9_AF4 +#define USART3_RX_PC11_AF0 +#define USART3_RX_PC5_AF0 +#define USART3_RX_PD9_AF0 +#define USART3_TX_PA5_AF4 +#define USART3_TX_PB10_AF4 +#define USART3_TX_PB2_AF4 +#define USART3_TX_PB8_AF4 +#define USART3_TX_PC10_AF0 +#define USART3_TX_PC4_AF0 +#define USART3_TX_PD8_AF0 +#define USART4_RX_PA1_AF4 +#define USART4_RX_PC11_AF1 +#define USART4_RX_PE9_AF0 +#define USART4_TX_PA0_AF4 +#define USART4_TX_PC10_AF1 +#define USART4_TX_PE8_AF0 +#define USART5_RX_PB1_AF8 +#define USART5_RX_PB4_AF3 +#define USART5_RX_PD2_AF3 +#define USART5_TX_PB0_AF8 +#define USART5_TX_PB3_AF3 +#define USART5_TX_PC12_AF3 +#define USART5_TX_PD3_AF3 +#define USART5_TX_PE10_AF3 +#define USART6_RX_PA5_AF3 +#define USART6_RX_PB9_AF8 +#define USART6_RX_PC1_AF4 +#define USART6_TX_PA4_AF3 +#define USART6_TX_PB8_AF8 +#define USART6_TX_PC0_AF4 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) +#define UART_MODULE_6 (6) + +#define UART_MODULE_COUNT (6) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MISO_PD5_AF1 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_MOSI_PD6_AF1 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI1_SCK_PD8_AF1 +#define SPI2_MISO_PA3_AF0 +#define SPI2_MISO_PA9_AF4 +#define SPI2_MISO_PB14_AF0 +#define SPI2_MISO_PB2_AF1 +#define SPI2_MISO_PB6_AF4 +#define SPI2_MISO_PC2_AF1 +#define SPI2_MISO_PD3_AF1 +#define SPI2_MOSI_PA10_AF0 +#define SPI2_MOSI_PA4_AF1 +#define SPI2_MOSI_PB11_AF0 +#define SPI2_MOSI_PB15_AF0 +#define SPI2_MOSI_PB7_AF1 +#define SPI2_MOSI_PC3_AF1 +#define SPI2_MOSI_PD4_AF1 +#define SPI2_SCK_PA0_AF0 +#define SPI2_SCK_PB10_AF5 +#define SPI2_SCK_PB13_AF0 +#define SPI2_SCK_PB8_AF1 +#define SPI2_SCK_PD1_AF1 +#define SPI3_MISO_PB4_AF9 +#define SPI3_MISO_PC11_AF4 +#define SPI3_MOSI_PB5_AF9 +#define SPI3_MOSI_PC12_AF4 +#define SPI3_SCK_PB3_AF9 +#define SPI3_SCK_PC10_AF4 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF5 +#define LPTIM1_ETR_PC3_AF0 +#define LPTIM2_ETR_PA5_AF5 +#define LPTIM2_ETR_PC3_AF2 +#define LPTIM2_ETR_PD11_AF1 +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PB1_AF0 +#define TIM14_CH1_PC12_AF2 +#define TIM14_CH1_PF0_AF2 +#define TIM15_CH1N_PA1_AF5 +#define TIM15_CH1N_PB13_AF5 +#define TIM15_CH1N_PB15_AF4 +#define TIM15_CH1N_PF1_AF2 +#define TIM15_CH1_PA2_AF5 +#define TIM15_CH1_PB14_AF5 +#define TIM15_CH1_PC1_AF2 +#define TIM15_CH2_PA3_AF5 +#define TIM15_CH2_PB15_AF5 +#define TIM15_CH2_PC2_AF2 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB8_AF2 +#define TIM16_CH1_PD0_AF2 +#define TIM16_CH1_PE0_AF0 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PB9_AF2 +#define TIM17_CH1_PD1_AF2 +#define TIM17_CH1_PE1_AF0 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1N_PB13_AF2 +#define TIM1_CH1N_PD2_AF2 +#define TIM1_CH1N_PE8_AF1 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH1_PC8_AF2 +#define TIM1_CH1_PE9_AF1 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2N_PB14_AF2 +#define TIM1_CH2N_PD3_AF2 +#define TIM1_CH2N_PE10_AF1 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH2_PC9_AF2 +#define TIM1_CH3N_PB15_AF2 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3N_PD4_AF2 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH3_PC10_AF2 +#define TIM1_CH4_PA11_AF2 +#define TIM1_CH4_PC11_AF2 +#define TIM1_ETR_PA12_AF2 +#define TIM1_ETR_PE7_AF1 +#define TIM2_CH1_PA0_AF2 +#define TIM2_CH1_PA15_AF2 +#define TIM2_CH1_PA5_AF2 +#define TIM2_CH1_PC4_AF2 +#define TIM2_CH2_PA1_AF2 +#define TIM2_CH2_PB3_AF2 +#define TIM2_CH2_PC5_AF2 +#define TIM2_CH3_PA2_AF2 +#define TIM2_CH3_PB10_AF2 +#define TIM2_CH3_PC6_AF2 +#define TIM2_CH4_PA3_AF2 +#define TIM2_CH4_PB11_AF2 +#define TIM2_CH4_PC7_AF2 +#define TIM2_ETR_PA0_AF2 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM2_ETR_PC4_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH1_PC6_AF1 +#define TIM3_CH1_PE3_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH2_PC7_AF1 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH3_PC8_AF1 +#define TIM3_CH4_PB1_AF1 +#define TIM3_CH4_PC9_AF1 +#define TIM3_ETR_PD2_AF1 +#define TIM4_CH1_PB6_AF9 +#define TIM4_CH1_PD12_AF2 +#define TIM4_CH2_PB7_AF9 +#define TIM4_CH2_PD13_AF2 +#define TIM4_CH3_PB8_AF9 +#define TIM4_CH3_PD14_AF2 +#define TIM4_CH4_PB9_AF9 +#define TIM4_CH4_PD15_AF2 +#define TIM4_ETR_PE0_AF2 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_14 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +#define TIM1_BUS (1) +#define TIM4_BUS (1) +#define TIM15_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PE0_CN +#define __PE1_CN +#define __PE10_CN +#define __PE3_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PF2_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN + +#define PORT_COUNT (6) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +#define UART3_IVT (29) +#define UART3_NVIC (45) +#define UART4_IVT (29) +#define UART4_NVIC (45) +#define UART5_IVT (29) +#define UART5_NVIC (45) +#define UART6_IVT (29) +#define UART6_NVIC (45) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0C1NE/WLCSP52/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0C1NE/WLCSP52/mcu_definitions.h new file mode 100644 index 000000000..157e49201 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0C1NE/WLCSP52/mcu_definitions.h @@ -0,0 +1,398 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G0C1NE_WLCSP52. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PB0_CH8 +#define ADC1_PB10_CH11 +#define ADC1_PB11_CH15 +#define ADC1_PB12_CH16 +#define ADC1_PB1_CH9 +#define ADC1_PB2_CH10 +#define ADC1_PC4_CH17 +#define ADC1_PC5_CH18 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF3 +#define FDCAN1_RX_PB8_AF3 +#define FDCAN1_RX_PC4_AF3 +#define FDCAN1_RX_PD0_AF3 +#define FDCAN1_TX_PA12_AF3 +#define FDCAN1_TX_PB9_AF3 +#define FDCAN1_TX_PC5_AF3 +#define FDCAN1_TX_PD1_AF3 +#define FDCAN2_RX_PB0_AF3 +#define FDCAN2_RX_PB12_AF3 +#define FDCAN2_RX_PB5_AF3 +#define FDCAN2_TX_PB13_AF3 +#define FDCAN2_TX_PB1_AF3 +#define FDCAN2_TX_PB6_AF3 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) + +#define CAN_MODULE_COUNT (2) + +#define HAL_LL_FDCAN1_GPIO_AF3 (3) +#define HAL_LL_FDCAN2_GPIO_AF3 (3) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (78) +#define DMA_NUM_OF_CHANNELS_FAMILY (78) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (12) +#define DMA_NUM_OF_STREAMS_FAMILY (12) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PB9_AF6 +#define I2C2_SCL_PA11_AF6 +#define I2C2_SCL_PA7_AF8 +#define I2C2_SCL_PA9_AF8 +#define I2C2_SCL_PB10_AF6 +#define I2C2_SCL_PB13_AF6 +#define I2C2_SCL_PB3_AF8 +#define I2C2_SDA_PA10_AF8 +#define I2C2_SDA_PA12_AF6 +#define I2C2_SDA_PA6_AF8 +#define I2C2_SDA_PB11_AF6 +#define I2C2_SDA_PB14_AF6 +#define I2C2_SDA_PB4_AF8 +#define I2C3_SCL_PA7_AF9 +#define I2C3_SCL_PB3_AF6 +#define I2C3_SDA_PA6_AF9 +#define I2C3_SDA_PB4_AF6 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF6 +#define LPUART1_RX_PB10_AF1 +#define LPUART1_TX_PA2_AF6 +#define LPUART1_TX_PB11_AF1 +#define LPUART2_RX_PA13_AF10 +#define LPUART2_RX_PB7_AF10 +#define LPUART2_RX_PC7_AF3 +#define LPUART2_TX_PA14_AF10 +#define LPUART2_TX_PB6_AF10 +#define LPUART2_TX_PC6_AF3 +#define LPUART2_TX_PF2_AF1 +#define USART1_RX_PA10_AF1 +#define USART1_RX_PB7_AF0 +#define USART1_RX_PC5_AF1 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART1_TX_PC4_AF1 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 +#define USART3_RX_PB0_AF4 +#define USART3_RX_PB11_AF4 +#define USART3_RX_PB9_AF4 +#define USART3_RX_PC5_AF0 +#define USART3_TX_PA5_AF4 +#define USART3_TX_PB10_AF4 +#define USART3_TX_PB2_AF4 +#define USART3_TX_PB8_AF4 +#define USART3_TX_PC4_AF0 +#define USART4_RX_PA1_AF4 +#define USART4_TX_PA0_AF4 +#define USART5_RX_PB1_AF8 +#define USART5_RX_PB4_AF3 +#define USART5_RX_PD2_AF3 +#define USART5_TX_PB0_AF8 +#define USART5_TX_PB3_AF3 +#define USART5_TX_PD3_AF3 +#define USART6_RX_PA5_AF3 +#define USART6_RX_PB9_AF8 +#define USART6_TX_PA4_AF3 +#define USART6_TX_PB8_AF8 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) +#define UART_MODULE_6 (6) + +#define UART_MODULE_COUNT (6) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI2_MISO_PA3_AF0 +#define SPI2_MISO_PA9_AF4 +#define SPI2_MISO_PB14_AF0 +#define SPI2_MISO_PB2_AF1 +#define SPI2_MISO_PB6_AF4 +#define SPI2_MISO_PD3_AF1 +#define SPI2_MOSI_PA10_AF0 +#define SPI2_MOSI_PA4_AF1 +#define SPI2_MOSI_PB11_AF0 +#define SPI2_MOSI_PB15_AF0 +#define SPI2_MOSI_PB7_AF1 +#define SPI2_SCK_PA0_AF0 +#define SPI2_SCK_PB10_AF5 +#define SPI2_SCK_PB13_AF0 +#define SPI2_SCK_PB8_AF1 +#define SPI2_SCK_PD1_AF1 +#define SPI3_MISO_PB4_AF9 +#define SPI3_MOSI_PB5_AF9 +#define SPI3_SCK_PB3_AF9 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF5 +#define LPTIM2_ETR_PA5_AF5 +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PB1_AF0 +#define TIM14_CH1_PF0_AF2 +#define TIM15_CH1N_PA1_AF5 +#define TIM15_CH1N_PB13_AF5 +#define TIM15_CH1N_PB15_AF4 +#define TIM15_CH1N_PF1_AF2 +#define TIM15_CH1_PA2_AF5 +#define TIM15_CH1_PB14_AF5 +#define TIM15_CH2_PA3_AF5 +#define TIM15_CH2_PB15_AF5 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB8_AF2 +#define TIM16_CH1_PD0_AF2 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PB9_AF2 +#define TIM17_CH1_PD1_AF2 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1N_PB13_AF2 +#define TIM1_CH1N_PD2_AF2 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2N_PB14_AF2 +#define TIM1_CH2N_PD3_AF2 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH3N_PB15_AF2 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_ETR_PA12_AF2 +#define TIM2_CH1_PA0_AF2 +#define TIM2_CH1_PA15_AF2 +#define TIM2_CH1_PA5_AF2 +#define TIM2_CH1_PC4_AF2 +#define TIM2_CH2_PA1_AF2 +#define TIM2_CH2_PB3_AF2 +#define TIM2_CH2_PC5_AF2 +#define TIM2_CH3_PA2_AF2 +#define TIM2_CH3_PB10_AF2 +#define TIM2_CH3_PC6_AF2 +#define TIM2_CH4_PA3_AF2 +#define TIM2_CH4_PB11_AF2 +#define TIM2_CH4_PC7_AF2 +#define TIM2_ETR_PA0_AF2 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM2_ETR_PC4_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH1_PC6_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH2_PC7_AF1 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH4_PB1_AF1 +#define TIM3_ETR_PD2_AF1 +#define TIM4_CH1_PB6_AF9 +#define TIM4_CH2_PB7_AF9 +#define TIM4_CH3_PB8_AF9 +#define TIM4_CH4_PB9_AF9 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_14 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +#define TIM1_BUS (1) +#define TIM4_BUS (1) +#define TIM15_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PF0_CN +#define __PF1_CN +#define __PF2_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_F_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +#define UART3_IVT (29) +#define UART3_NVIC (45) +#define UART4_IVT (29) +#define UART4_NVIC (45) +#define UART5_IVT (29) +#define UART5_NVIC (45) +#define UART6_IVT (29) +#define UART6_NVIC (45) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0C1RC/LQFP64/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0C1RC/LQFP64/mcu_definitions.h new file mode 100644 index 000000000..39ec89b78 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0C1RC/LQFP64/mcu_definitions.h @@ -0,0 +1,452 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G0C1RC_LQFP64. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PB0_CH8 +#define ADC1_PB10_CH11 +#define ADC1_PB11_CH15 +#define ADC1_PB12_CH16 +#define ADC1_PB1_CH9 +#define ADC1_PB2_CH10 +#define ADC1_PC4_CH17 +#define ADC1_PC5_CH18 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF3 +#define FDCAN1_RX_PB8_AF3 +#define FDCAN1_RX_PC4_AF3 +#define FDCAN1_RX_PD0_AF3 +#define FDCAN1_TX_PA12_AF3 +#define FDCAN1_TX_PB9_AF3 +#define FDCAN1_TX_PC5_AF3 +#define FDCAN1_TX_PD1_AF3 +#define FDCAN2_RX_PB0_AF3 +#define FDCAN2_RX_PB12_AF3 +#define FDCAN2_RX_PB5_AF3 +#define FDCAN2_RX_PC2_AF3 +#define FDCAN2_TX_PB13_AF3 +#define FDCAN2_TX_PB1_AF3 +#define FDCAN2_TX_PB6_AF3 +#define FDCAN2_TX_PC3_AF3 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) + +#define CAN_MODULE_COUNT (2) + +#define HAL_LL_FDCAN1_GPIO_AF3 (3) +#define HAL_LL_FDCAN2_GPIO_AF3 (3) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (78) +#define DMA_NUM_OF_CHANNELS_FAMILY (78) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (12) +#define DMA_NUM_OF_STREAMS_FAMILY (12) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PB9_AF6 +#define I2C2_SCL_PA11_AF6 +#define I2C2_SCL_PA7_AF8 +#define I2C2_SCL_PA9_AF8 +#define I2C2_SCL_PB10_AF6 +#define I2C2_SCL_PB13_AF6 +#define I2C2_SCL_PB3_AF8 +#define I2C2_SDA_PA10_AF8 +#define I2C2_SDA_PA12_AF6 +#define I2C2_SDA_PA6_AF8 +#define I2C2_SDA_PB11_AF6 +#define I2C2_SDA_PB14_AF6 +#define I2C2_SDA_PB4_AF8 +#define I2C3_SCL_PA7_AF9 +#define I2C3_SCL_PB3_AF6 +#define I2C3_SCL_PC0_AF6 +#define I2C3_SDA_PA6_AF9 +#define I2C3_SDA_PB4_AF6 +#define I2C3_SDA_PC1_AF6 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF6 +#define LPUART1_RX_PB10_AF1 +#define LPUART1_RX_PC0_AF1 +#define LPUART1_TX_PA2_AF6 +#define LPUART1_TX_PB11_AF1 +#define LPUART1_TX_PC1_AF1 +#define LPUART2_RX_PA13_AF10 +#define LPUART2_RX_PB7_AF10 +#define LPUART2_RX_PC1_AF3 +#define LPUART2_RX_PC7_AF3 +#define LPUART2_TX_PA14_AF10 +#define LPUART2_TX_PB6_AF10 +#define LPUART2_TX_PC0_AF3 +#define LPUART2_TX_PC6_AF3 +#define LPUART2_TX_PF2_AF1 +#define USART1_RX_PA10_AF1 +#define USART1_RX_PB7_AF0 +#define USART1_RX_PC5_AF1 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART1_TX_PC4_AF1 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_RX_PD6_AF0 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 +#define USART2_TX_PD5_AF0 +#define USART3_RX_PB0_AF4 +#define USART3_RX_PB11_AF4 +#define USART3_RX_PB9_AF4 +#define USART3_RX_PC11_AF0 +#define USART3_RX_PC5_AF0 +#define USART3_RX_PD9_AF0 +#define USART3_TX_PA5_AF4 +#define USART3_TX_PB10_AF4 +#define USART3_TX_PB2_AF4 +#define USART3_TX_PB8_AF4 +#define USART3_TX_PC10_AF0 +#define USART3_TX_PC4_AF0 +#define USART3_TX_PD8_AF0 +#define USART4_RX_PA1_AF4 +#define USART4_RX_PC11_AF1 +#define USART4_TX_PA0_AF4 +#define USART4_TX_PC10_AF1 +#define USART5_RX_PB1_AF8 +#define USART5_RX_PB4_AF3 +#define USART5_RX_PD2_AF3 +#define USART5_TX_PB0_AF8 +#define USART5_TX_PB3_AF3 +#define USART5_TX_PC12_AF3 +#define USART5_TX_PD3_AF3 +#define USART6_RX_PA5_AF3 +#define USART6_RX_PB9_AF8 +#define USART6_RX_PC1_AF4 +#define USART6_TX_PA4_AF3 +#define USART6_TX_PB8_AF8 +#define USART6_TX_PC0_AF4 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) +#define UART_MODULE_6 (6) + +#define UART_MODULE_COUNT (6) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MISO_PD5_AF1 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_MOSI_PD6_AF1 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI1_SCK_PD8_AF1 +#define SPI2_MISO_PA3_AF0 +#define SPI2_MISO_PA9_AF4 +#define SPI2_MISO_PB14_AF0 +#define SPI2_MISO_PB2_AF1 +#define SPI2_MISO_PB6_AF4 +#define SPI2_MISO_PC2_AF1 +#define SPI2_MISO_PD3_AF1 +#define SPI2_MOSI_PA10_AF0 +#define SPI2_MOSI_PA4_AF1 +#define SPI2_MOSI_PB11_AF0 +#define SPI2_MOSI_PB15_AF0 +#define SPI2_MOSI_PB7_AF1 +#define SPI2_MOSI_PC3_AF1 +#define SPI2_MOSI_PD4_AF1 +#define SPI2_SCK_PA0_AF0 +#define SPI2_SCK_PB10_AF5 +#define SPI2_SCK_PB13_AF0 +#define SPI2_SCK_PB8_AF1 +#define SPI2_SCK_PD1_AF1 +#define SPI3_MISO_PB4_AF9 +#define SPI3_MISO_PC11_AF4 +#define SPI3_MOSI_PB5_AF9 +#define SPI3_MOSI_PC12_AF4 +#define SPI3_SCK_PB3_AF9 +#define SPI3_SCK_PC10_AF4 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF5 +#define LPTIM1_ETR_PC3_AF0 +#define LPTIM2_ETR_PA5_AF5 +#define LPTIM2_ETR_PC3_AF2 +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PB1_AF0 +#define TIM14_CH1_PC12_AF2 +#define TIM14_CH1_PF0_AF2 +#define TIM15_CH1N_PA1_AF5 +#define TIM15_CH1N_PB13_AF5 +#define TIM15_CH1N_PB15_AF4 +#define TIM15_CH1N_PF1_AF2 +#define TIM15_CH1_PA2_AF5 +#define TIM15_CH1_PB14_AF5 +#define TIM15_CH1_PC1_AF2 +#define TIM15_CH2_PA3_AF5 +#define TIM15_CH2_PB15_AF5 +#define TIM15_CH2_PC2_AF2 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB8_AF2 +#define TIM16_CH1_PD0_AF2 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PB9_AF2 +#define TIM17_CH1_PD1_AF2 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1N_PB13_AF2 +#define TIM1_CH1N_PD2_AF2 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH1_PC8_AF2 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2N_PB14_AF2 +#define TIM1_CH2N_PD3_AF2 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH2_PC9_AF2 +#define TIM1_CH3N_PB15_AF2 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3N_PD4_AF2 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH3_PC10_AF2 +#define TIM1_CH4_PA11_AF2 +#define TIM1_CH4_PC11_AF2 +#define TIM1_ETR_PA12_AF2 +#define TIM2_CH1_PA0_AF2 +#define TIM2_CH1_PA15_AF2 +#define TIM2_CH1_PA5_AF2 +#define TIM2_CH1_PC4_AF2 +#define TIM2_CH2_PA1_AF2 +#define TIM2_CH2_PB3_AF2 +#define TIM2_CH2_PC5_AF2 +#define TIM2_CH3_PA2_AF2 +#define TIM2_CH3_PB10_AF2 +#define TIM2_CH3_PC6_AF2 +#define TIM2_CH4_PA3_AF2 +#define TIM2_CH4_PB11_AF2 +#define TIM2_CH4_PC7_AF2 +#define TIM2_ETR_PA0_AF2 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM2_ETR_PC4_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH1_PC6_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH2_PC7_AF1 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH3_PC8_AF1 +#define TIM3_CH4_PB1_AF1 +#define TIM3_CH4_PC9_AF1 +#define TIM3_ETR_PD2_AF1 +#define TIM4_CH1_PB6_AF9 +#define TIM4_CH2_PB7_AF9 +#define TIM4_CH3_PB8_AF9 +#define TIM4_CH4_PB9_AF9 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_14 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +#define TIM1_BUS (1) +#define TIM4_BUS (1) +#define TIM15_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD8_CN +#define __PD9_CN +#define __PF0_CN +#define __PF1_CN +#define __PF2_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_F_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +#define UART3_IVT (29) +#define UART3_NVIC (45) +#define UART4_IVT (29) +#define UART4_NVIC (45) +#define UART5_IVT (29) +#define UART5_NVIC (45) +#define UART6_IVT (29) +#define UART6_NVIC (45) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0C1RE/LQFP64/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0C1RE/LQFP64/mcu_definitions.h new file mode 100644 index 000000000..cdc3feb85 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0C1RE/LQFP64/mcu_definitions.h @@ -0,0 +1,452 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G0C1RE_LQFP64. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PB0_CH8 +#define ADC1_PB10_CH11 +#define ADC1_PB11_CH15 +#define ADC1_PB12_CH16 +#define ADC1_PB1_CH9 +#define ADC1_PB2_CH10 +#define ADC1_PC4_CH17 +#define ADC1_PC5_CH18 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF3 +#define FDCAN1_RX_PB8_AF3 +#define FDCAN1_RX_PC4_AF3 +#define FDCAN1_RX_PD0_AF3 +#define FDCAN1_TX_PA12_AF3 +#define FDCAN1_TX_PB9_AF3 +#define FDCAN1_TX_PC5_AF3 +#define FDCAN1_TX_PD1_AF3 +#define FDCAN2_RX_PB0_AF3 +#define FDCAN2_RX_PB12_AF3 +#define FDCAN2_RX_PB5_AF3 +#define FDCAN2_RX_PC2_AF3 +#define FDCAN2_TX_PB13_AF3 +#define FDCAN2_TX_PB1_AF3 +#define FDCAN2_TX_PB6_AF3 +#define FDCAN2_TX_PC3_AF3 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) + +#define CAN_MODULE_COUNT (2) + +#define HAL_LL_FDCAN1_GPIO_AF3 (3) +#define HAL_LL_FDCAN2_GPIO_AF3 (3) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (78) +#define DMA_NUM_OF_CHANNELS_FAMILY (78) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (12) +#define DMA_NUM_OF_STREAMS_FAMILY (12) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PB9_AF6 +#define I2C2_SCL_PA11_AF6 +#define I2C2_SCL_PA7_AF8 +#define I2C2_SCL_PA9_AF8 +#define I2C2_SCL_PB10_AF6 +#define I2C2_SCL_PB13_AF6 +#define I2C2_SCL_PB3_AF8 +#define I2C2_SDA_PA10_AF8 +#define I2C2_SDA_PA12_AF6 +#define I2C2_SDA_PA6_AF8 +#define I2C2_SDA_PB11_AF6 +#define I2C2_SDA_PB14_AF6 +#define I2C2_SDA_PB4_AF8 +#define I2C3_SCL_PA7_AF9 +#define I2C3_SCL_PB3_AF6 +#define I2C3_SCL_PC0_AF6 +#define I2C3_SDA_PA6_AF9 +#define I2C3_SDA_PB4_AF6 +#define I2C3_SDA_PC1_AF6 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF6 +#define LPUART1_RX_PB10_AF1 +#define LPUART1_RX_PC0_AF1 +#define LPUART1_TX_PA2_AF6 +#define LPUART1_TX_PB11_AF1 +#define LPUART1_TX_PC1_AF1 +#define LPUART2_RX_PA13_AF10 +#define LPUART2_RX_PB7_AF10 +#define LPUART2_RX_PC1_AF3 +#define LPUART2_RX_PC7_AF3 +#define LPUART2_TX_PA14_AF10 +#define LPUART2_TX_PB6_AF10 +#define LPUART2_TX_PC0_AF3 +#define LPUART2_TX_PC6_AF3 +#define LPUART2_TX_PF2_AF1 +#define USART1_RX_PA10_AF1 +#define USART1_RX_PB7_AF0 +#define USART1_RX_PC5_AF1 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART1_TX_PC4_AF1 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_RX_PD6_AF0 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 +#define USART2_TX_PD5_AF0 +#define USART3_RX_PB0_AF4 +#define USART3_RX_PB11_AF4 +#define USART3_RX_PB9_AF4 +#define USART3_RX_PC11_AF0 +#define USART3_RX_PC5_AF0 +#define USART3_RX_PD9_AF0 +#define USART3_TX_PA5_AF4 +#define USART3_TX_PB10_AF4 +#define USART3_TX_PB2_AF4 +#define USART3_TX_PB8_AF4 +#define USART3_TX_PC10_AF0 +#define USART3_TX_PC4_AF0 +#define USART3_TX_PD8_AF0 +#define USART4_RX_PA1_AF4 +#define USART4_RX_PC11_AF1 +#define USART4_TX_PA0_AF4 +#define USART4_TX_PC10_AF1 +#define USART5_RX_PB1_AF8 +#define USART5_RX_PB4_AF3 +#define USART5_RX_PD2_AF3 +#define USART5_TX_PB0_AF8 +#define USART5_TX_PB3_AF3 +#define USART5_TX_PC12_AF3 +#define USART5_TX_PD3_AF3 +#define USART6_RX_PA5_AF3 +#define USART6_RX_PB9_AF8 +#define USART6_RX_PC1_AF4 +#define USART6_TX_PA4_AF3 +#define USART6_TX_PB8_AF8 +#define USART6_TX_PC0_AF4 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) +#define UART_MODULE_6 (6) + +#define UART_MODULE_COUNT (6) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MISO_PD5_AF1 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_MOSI_PD6_AF1 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI1_SCK_PD8_AF1 +#define SPI2_MISO_PA3_AF0 +#define SPI2_MISO_PA9_AF4 +#define SPI2_MISO_PB14_AF0 +#define SPI2_MISO_PB2_AF1 +#define SPI2_MISO_PB6_AF4 +#define SPI2_MISO_PC2_AF1 +#define SPI2_MISO_PD3_AF1 +#define SPI2_MOSI_PA10_AF0 +#define SPI2_MOSI_PA4_AF1 +#define SPI2_MOSI_PB11_AF0 +#define SPI2_MOSI_PB15_AF0 +#define SPI2_MOSI_PB7_AF1 +#define SPI2_MOSI_PC3_AF1 +#define SPI2_MOSI_PD4_AF1 +#define SPI2_SCK_PA0_AF0 +#define SPI2_SCK_PB10_AF5 +#define SPI2_SCK_PB13_AF0 +#define SPI2_SCK_PB8_AF1 +#define SPI2_SCK_PD1_AF1 +#define SPI3_MISO_PB4_AF9 +#define SPI3_MISO_PC11_AF4 +#define SPI3_MOSI_PB5_AF9 +#define SPI3_MOSI_PC12_AF4 +#define SPI3_SCK_PB3_AF9 +#define SPI3_SCK_PC10_AF4 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF5 +#define LPTIM1_ETR_PC3_AF0 +#define LPTIM2_ETR_PA5_AF5 +#define LPTIM2_ETR_PC3_AF2 +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PB1_AF0 +#define TIM14_CH1_PC12_AF2 +#define TIM14_CH1_PF0_AF2 +#define TIM15_CH1N_PA1_AF5 +#define TIM15_CH1N_PB13_AF5 +#define TIM15_CH1N_PB15_AF4 +#define TIM15_CH1N_PF1_AF2 +#define TIM15_CH1_PA2_AF5 +#define TIM15_CH1_PB14_AF5 +#define TIM15_CH1_PC1_AF2 +#define TIM15_CH2_PA3_AF5 +#define TIM15_CH2_PB15_AF5 +#define TIM15_CH2_PC2_AF2 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB8_AF2 +#define TIM16_CH1_PD0_AF2 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PB9_AF2 +#define TIM17_CH1_PD1_AF2 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1N_PB13_AF2 +#define TIM1_CH1N_PD2_AF2 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH1_PC8_AF2 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2N_PB14_AF2 +#define TIM1_CH2N_PD3_AF2 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH2_PC9_AF2 +#define TIM1_CH3N_PB15_AF2 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3N_PD4_AF2 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH3_PC10_AF2 +#define TIM1_CH4_PA11_AF2 +#define TIM1_CH4_PC11_AF2 +#define TIM1_ETR_PA12_AF2 +#define TIM2_CH1_PA0_AF2 +#define TIM2_CH1_PA15_AF2 +#define TIM2_CH1_PA5_AF2 +#define TIM2_CH1_PC4_AF2 +#define TIM2_CH2_PA1_AF2 +#define TIM2_CH2_PB3_AF2 +#define TIM2_CH2_PC5_AF2 +#define TIM2_CH3_PA2_AF2 +#define TIM2_CH3_PB10_AF2 +#define TIM2_CH3_PC6_AF2 +#define TIM2_CH4_PA3_AF2 +#define TIM2_CH4_PB11_AF2 +#define TIM2_CH4_PC7_AF2 +#define TIM2_ETR_PA0_AF2 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM2_ETR_PC4_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH1_PC6_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH2_PC7_AF1 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH3_PC8_AF1 +#define TIM3_CH4_PB1_AF1 +#define TIM3_CH4_PC9_AF1 +#define TIM3_ETR_PD2_AF1 +#define TIM4_CH1_PB6_AF9 +#define TIM4_CH2_PB7_AF9 +#define TIM4_CH3_PB8_AF9 +#define TIM4_CH4_PB9_AF9 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_14 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +#define TIM1_BUS (1) +#define TIM4_BUS (1) +#define TIM15_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD8_CN +#define __PD9_CN +#define __PF0_CN +#define __PF1_CN +#define __PF2_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_F_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +#define UART3_IVT (29) +#define UART3_NVIC (45) +#define UART4_IVT (29) +#define UART4_NVIC (45) +#define UART5_IVT (29) +#define UART5_NVIC (45) +#define UART6_IVT (29) +#define UART6_NVIC (45) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0C1VC/LQFP100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0C1VC/LQFP100/mcu_definitions.h new file mode 100644 index 000000000..3be2e9505 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0C1VC/LQFP100/mcu_definitions.h @@ -0,0 +1,526 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G0C1VC_LQFP100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PB0_CH8 +#define ADC1_PB10_CH11 +#define ADC1_PB11_CH15 +#define ADC1_PB12_CH16 +#define ADC1_PB1_CH9 +#define ADC1_PB2_CH10 +#define ADC1_PC4_CH17 +#define ADC1_PC5_CH18 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF3 +#define FDCAN1_RX_PB8_AF3 +#define FDCAN1_RX_PC4_AF3 +#define FDCAN1_RX_PD0_AF3 +#define FDCAN1_RX_PD12_AF3 +#define FDCAN1_TX_PA12_AF3 +#define FDCAN1_TX_PB9_AF3 +#define FDCAN1_TX_PC5_AF3 +#define FDCAN1_TX_PD13_AF3 +#define FDCAN1_TX_PD1_AF3 +#define FDCAN2_RX_PB0_AF3 +#define FDCAN2_RX_PB12_AF3 +#define FDCAN2_RX_PB5_AF3 +#define FDCAN2_RX_PC2_AF3 +#define FDCAN2_RX_PD14_AF3 +#define FDCAN2_TX_PB13_AF3 +#define FDCAN2_TX_PB1_AF3 +#define FDCAN2_TX_PB6_AF3 +#define FDCAN2_TX_PC3_AF3 +#define FDCAN2_TX_PD15_AF3 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) + +#define CAN_MODULE_COUNT (2) + +#define HAL_LL_FDCAN1_GPIO_AF3 (3) +#define HAL_LL_FDCAN2_GPIO_AF3 (3) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (78) +#define DMA_NUM_OF_CHANNELS_FAMILY (78) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (12) +#define DMA_NUM_OF_STREAMS_FAMILY (12) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PB9_AF6 +#define I2C2_SCL_PA11_AF6 +#define I2C2_SCL_PA7_AF8 +#define I2C2_SCL_PA9_AF8 +#define I2C2_SCL_PB10_AF6 +#define I2C2_SCL_PB13_AF6 +#define I2C2_SCL_PB3_AF8 +#define I2C2_SDA_PA10_AF8 +#define I2C2_SDA_PA12_AF6 +#define I2C2_SDA_PA6_AF8 +#define I2C2_SDA_PB11_AF6 +#define I2C2_SDA_PB14_AF6 +#define I2C2_SDA_PB4_AF8 +#define I2C3_SCL_PA7_AF9 +#define I2C3_SCL_PB3_AF6 +#define I2C3_SCL_PC0_AF6 +#define I2C3_SDA_PA6_AF9 +#define I2C3_SDA_PB4_AF6 +#define I2C3_SDA_PC1_AF6 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF6 +#define LPUART1_RX_PB10_AF1 +#define LPUART1_RX_PC0_AF1 +#define LPUART1_RX_PF5_AF1 +#define LPUART1_TX_PA2_AF6 +#define LPUART1_TX_PB11_AF1 +#define LPUART1_TX_PC1_AF1 +#define LPUART1_TX_PF4_AF1 +#define LPUART2_RX_PA13_AF10 +#define LPUART2_RX_PB7_AF10 +#define LPUART2_RX_PC1_AF3 +#define LPUART2_RX_PC7_AF3 +#define LPUART2_RX_PF3_AF1 +#define LPUART2_TX_PA14_AF10 +#define LPUART2_TX_PB6_AF10 +#define LPUART2_TX_PC0_AF3 +#define LPUART2_TX_PC6_AF3 +#define LPUART2_TX_PF2_AF1 +#define USART1_RX_PA10_AF1 +#define USART1_RX_PB7_AF0 +#define USART1_RX_PC5_AF1 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART1_TX_PC4_AF1 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_RX_PD6_AF0 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 +#define USART2_TX_PD5_AF0 +#define USART3_RX_PB0_AF4 +#define USART3_RX_PB11_AF4 +#define USART3_RX_PB9_AF4 +#define USART3_RX_PC11_AF0 +#define USART3_RX_PC5_AF0 +#define USART3_RX_PD9_AF0 +#define USART3_TX_PA5_AF4 +#define USART3_TX_PB10_AF4 +#define USART3_TX_PB2_AF4 +#define USART3_TX_PB8_AF4 +#define USART3_TX_PC10_AF0 +#define USART3_TX_PC4_AF0 +#define USART3_TX_PD8_AF0 +#define USART4_RX_PA1_AF4 +#define USART4_RX_PC11_AF1 +#define USART4_RX_PE9_AF0 +#define USART4_TX_PA0_AF4 +#define USART4_TX_PC10_AF1 +#define USART4_TX_PE8_AF0 +#define USART5_RX_PB1_AF8 +#define USART5_RX_PB4_AF3 +#define USART5_RX_PD2_AF3 +#define USART5_RX_PE11_AF3 +#define USART5_TX_PB0_AF8 +#define USART5_TX_PB3_AF3 +#define USART5_TX_PC12_AF3 +#define USART5_TX_PD3_AF3 +#define USART5_TX_PE10_AF3 +#define USART6_RX_PA5_AF3 +#define USART6_RX_PB9_AF8 +#define USART6_RX_PC1_AF4 +#define USART6_RX_PF10_AF3 +#define USART6_TX_PA4_AF3 +#define USART6_TX_PB8_AF8 +#define USART6_TX_PC0_AF4 +#define USART6_TX_PF9_AF3 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) +#define UART_MODULE_6 (6) + +#define UART_MODULE_COUNT (6) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MISO_PD5_AF1 +#define SPI1_MISO_PE14_AF0 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_MOSI_PD6_AF1 +#define SPI1_MOSI_PE15_AF0 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI1_SCK_PD8_AF1 +#define SPI1_SCK_PE13_AF0 +#define SPI2_MISO_PA3_AF0 +#define SPI2_MISO_PA9_AF4 +#define SPI2_MISO_PB14_AF0 +#define SPI2_MISO_PB2_AF1 +#define SPI2_MISO_PB6_AF4 +#define SPI2_MISO_PC2_AF1 +#define SPI2_MISO_PD3_AF1 +#define SPI2_MOSI_PA10_AF0 +#define SPI2_MOSI_PA4_AF1 +#define SPI2_MOSI_PB11_AF0 +#define SPI2_MOSI_PB15_AF0 +#define SPI2_MOSI_PB7_AF1 +#define SPI2_MOSI_PC3_AF1 +#define SPI2_MOSI_PD4_AF1 +#define SPI2_SCK_PA0_AF0 +#define SPI2_SCK_PB10_AF5 +#define SPI2_SCK_PB13_AF0 +#define SPI2_SCK_PB8_AF1 +#define SPI2_SCK_PD1_AF1 +#define SPI3_MISO_PB4_AF9 +#define SPI3_MISO_PC11_AF4 +#define SPI3_MOSI_PB5_AF9 +#define SPI3_MOSI_PC12_AF4 +#define SPI3_SCK_PB3_AF9 +#define SPI3_SCK_PC10_AF4 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF5 +#define LPTIM1_ETR_PC3_AF0 +#define LPTIM2_ETR_PA5_AF5 +#define LPTIM2_ETR_PC3_AF2 +#define LPTIM2_ETR_PD11_AF1 +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PB1_AF0 +#define TIM14_CH1_PC12_AF2 +#define TIM14_CH1_PF0_AF2 +#define TIM15_CH1N_PA1_AF5 +#define TIM15_CH1N_PB13_AF5 +#define TIM15_CH1N_PB15_AF4 +#define TIM15_CH1N_PF1_AF2 +#define TIM15_CH1_PA2_AF5 +#define TIM15_CH1_PB14_AF5 +#define TIM15_CH1_PC1_AF2 +#define TIM15_CH1_PF12_AF0 +#define TIM15_CH2_PA3_AF5 +#define TIM15_CH2_PB15_AF5 +#define TIM15_CH2_PC2_AF2 +#define TIM15_CH2_PF13_AF0 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB8_AF2 +#define TIM16_CH1_PD0_AF2 +#define TIM16_CH1_PE0_AF0 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PB9_AF2 +#define TIM17_CH1_PD1_AF2 +#define TIM17_CH1_PE1_AF0 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1N_PB13_AF2 +#define TIM1_CH1N_PD2_AF2 +#define TIM1_CH1N_PE8_AF1 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH1_PC8_AF2 +#define TIM1_CH1_PE9_AF1 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2N_PB14_AF2 +#define TIM1_CH2N_PD3_AF2 +#define TIM1_CH2N_PE10_AF1 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH2_PC9_AF2 +#define TIM1_CH2_PE11_AF1 +#define TIM1_CH3N_PB15_AF2 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3N_PD4_AF2 +#define TIM1_CH3N_PE12_AF1 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH3_PC10_AF2 +#define TIM1_CH3_PE13_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_CH4_PC11_AF2 +#define TIM1_CH4_PE14_AF1 +#define TIM1_ETR_PA12_AF2 +#define TIM1_ETR_PE7_AF1 +#define TIM2_CH1_PA0_AF2 +#define TIM2_CH1_PA15_AF2 +#define TIM2_CH1_PA5_AF2 +#define TIM2_CH1_PC4_AF2 +#define TIM2_CH2_PA1_AF2 +#define TIM2_CH2_PB3_AF2 +#define TIM2_CH2_PC5_AF2 +#define TIM2_CH3_PA2_AF2 +#define TIM2_CH3_PB10_AF2 +#define TIM2_CH3_PC6_AF2 +#define TIM2_CH4_PA3_AF2 +#define TIM2_CH4_PB11_AF2 +#define TIM2_CH4_PC7_AF2 +#define TIM2_ETR_PA0_AF2 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM2_ETR_PC4_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH1_PC6_AF1 +#define TIM3_CH1_PE3_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH2_PC7_AF1 +#define TIM3_CH2_PE4_AF1 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH3_PC8_AF1 +#define TIM3_CH3_PE5_AF1 +#define TIM3_CH4_PB1_AF1 +#define TIM3_CH4_PC9_AF1 +#define TIM3_CH4_PE6_AF1 +#define TIM3_ETR_PD2_AF1 +#define TIM3_ETR_PE2_AF1 +#define TIM4_CH1_PB6_AF9 +#define TIM4_CH1_PD12_AF2 +#define TIM4_CH2_PB7_AF9 +#define TIM4_CH2_PD13_AF2 +#define TIM4_CH3_PB8_AF9 +#define TIM4_CH3_PD14_AF2 +#define TIM4_CH4_PB9_AF9 +#define TIM4_CH4_PD15_AF2 +#define TIM4_ETR_PE0_AF2 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_14 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +#define TIM1_BUS (1) +#define TIM4_BUS (1) +#define TIM15_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PE0_CN +#define __PE1_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN +#define __PE6_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PF10_CN +#define __PF11_CN +#define __PF12_CN +#define __PF13_CN +#define __PF2_CN +#define __PF3_CN +#define __PF4_CN +#define __PF5_CN +#define __PF6_CN +#define __PF7_CN +#define __PF8_CN +#define __PF9_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN + +#define PORT_COUNT (6) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +#define UART3_IVT (29) +#define UART3_NVIC (45) +#define UART4_IVT (29) +#define UART4_NVIC (45) +#define UART5_IVT (29) +#define UART5_NVIC (45) +#define UART6_IVT (29) +#define UART6_NVIC (45) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0C1VC/UFBGA100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0C1VC/UFBGA100/mcu_definitions.h new file mode 100644 index 000000000..a57fc7b38 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0C1VC/UFBGA100/mcu_definitions.h @@ -0,0 +1,526 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G0C1VC_UFBGA100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PB0_CH8 +#define ADC1_PB10_CH11 +#define ADC1_PB11_CH15 +#define ADC1_PB12_CH16 +#define ADC1_PB1_CH9 +#define ADC1_PB2_CH10 +#define ADC1_PC4_CH17 +#define ADC1_PC5_CH18 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF3 +#define FDCAN1_RX_PB8_AF3 +#define FDCAN1_RX_PC4_AF3 +#define FDCAN1_RX_PD0_AF3 +#define FDCAN1_RX_PD12_AF3 +#define FDCAN1_TX_PA12_AF3 +#define FDCAN1_TX_PB9_AF3 +#define FDCAN1_TX_PC5_AF3 +#define FDCAN1_TX_PD13_AF3 +#define FDCAN1_TX_PD1_AF3 +#define FDCAN2_RX_PB0_AF3 +#define FDCAN2_RX_PB12_AF3 +#define FDCAN2_RX_PB5_AF3 +#define FDCAN2_RX_PC2_AF3 +#define FDCAN2_RX_PD14_AF3 +#define FDCAN2_TX_PB13_AF3 +#define FDCAN2_TX_PB1_AF3 +#define FDCAN2_TX_PB6_AF3 +#define FDCAN2_TX_PC3_AF3 +#define FDCAN2_TX_PD15_AF3 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) + +#define CAN_MODULE_COUNT (2) + +#define HAL_LL_FDCAN1_GPIO_AF3 (3) +#define HAL_LL_FDCAN2_GPIO_AF3 (3) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (78) +#define DMA_NUM_OF_CHANNELS_FAMILY (78) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (12) +#define DMA_NUM_OF_STREAMS_FAMILY (12) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PB9_AF6 +#define I2C2_SCL_PA11_AF6 +#define I2C2_SCL_PA7_AF8 +#define I2C2_SCL_PA9_AF8 +#define I2C2_SCL_PB10_AF6 +#define I2C2_SCL_PB13_AF6 +#define I2C2_SCL_PB3_AF8 +#define I2C2_SDA_PA10_AF8 +#define I2C2_SDA_PA12_AF6 +#define I2C2_SDA_PA6_AF8 +#define I2C2_SDA_PB11_AF6 +#define I2C2_SDA_PB14_AF6 +#define I2C2_SDA_PB4_AF8 +#define I2C3_SCL_PA7_AF9 +#define I2C3_SCL_PB3_AF6 +#define I2C3_SCL_PC0_AF6 +#define I2C3_SDA_PA6_AF9 +#define I2C3_SDA_PB4_AF6 +#define I2C3_SDA_PC1_AF6 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF6 +#define LPUART1_RX_PB10_AF1 +#define LPUART1_RX_PC0_AF1 +#define LPUART1_RX_PF5_AF1 +#define LPUART1_TX_PA2_AF6 +#define LPUART1_TX_PB11_AF1 +#define LPUART1_TX_PC1_AF1 +#define LPUART1_TX_PF4_AF1 +#define LPUART2_RX_PA13_AF10 +#define LPUART2_RX_PB7_AF10 +#define LPUART2_RX_PC1_AF3 +#define LPUART2_RX_PC7_AF3 +#define LPUART2_RX_PF3_AF1 +#define LPUART2_TX_PA14_AF10 +#define LPUART2_TX_PB6_AF10 +#define LPUART2_TX_PC0_AF3 +#define LPUART2_TX_PC6_AF3 +#define LPUART2_TX_PF2_AF1 +#define USART1_RX_PA10_AF1 +#define USART1_RX_PB7_AF0 +#define USART1_RX_PC5_AF1 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART1_TX_PC4_AF1 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_RX_PD6_AF0 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 +#define USART2_TX_PD5_AF0 +#define USART3_RX_PB0_AF4 +#define USART3_RX_PB11_AF4 +#define USART3_RX_PB9_AF4 +#define USART3_RX_PC11_AF0 +#define USART3_RX_PC5_AF0 +#define USART3_RX_PD9_AF0 +#define USART3_TX_PA5_AF4 +#define USART3_TX_PB10_AF4 +#define USART3_TX_PB2_AF4 +#define USART3_TX_PB8_AF4 +#define USART3_TX_PC10_AF0 +#define USART3_TX_PC4_AF0 +#define USART3_TX_PD8_AF0 +#define USART4_RX_PA1_AF4 +#define USART4_RX_PC11_AF1 +#define USART4_RX_PE9_AF0 +#define USART4_TX_PA0_AF4 +#define USART4_TX_PC10_AF1 +#define USART4_TX_PE8_AF0 +#define USART5_RX_PB1_AF8 +#define USART5_RX_PB4_AF3 +#define USART5_RX_PD2_AF3 +#define USART5_RX_PE11_AF3 +#define USART5_TX_PB0_AF8 +#define USART5_TX_PB3_AF3 +#define USART5_TX_PC12_AF3 +#define USART5_TX_PD3_AF3 +#define USART5_TX_PE10_AF3 +#define USART6_RX_PA5_AF3 +#define USART6_RX_PB9_AF8 +#define USART6_RX_PC1_AF4 +#define USART6_RX_PF10_AF3 +#define USART6_TX_PA4_AF3 +#define USART6_TX_PB8_AF8 +#define USART6_TX_PC0_AF4 +#define USART6_TX_PF9_AF3 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) +#define UART_MODULE_6 (6) + +#define UART_MODULE_COUNT (6) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MISO_PD5_AF1 +#define SPI1_MISO_PE14_AF0 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_MOSI_PD6_AF1 +#define SPI1_MOSI_PE15_AF0 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI1_SCK_PD8_AF1 +#define SPI1_SCK_PE13_AF0 +#define SPI2_MISO_PA3_AF0 +#define SPI2_MISO_PA9_AF4 +#define SPI2_MISO_PB14_AF0 +#define SPI2_MISO_PB2_AF1 +#define SPI2_MISO_PB6_AF4 +#define SPI2_MISO_PC2_AF1 +#define SPI2_MISO_PD3_AF1 +#define SPI2_MOSI_PA10_AF0 +#define SPI2_MOSI_PA4_AF1 +#define SPI2_MOSI_PB11_AF0 +#define SPI2_MOSI_PB15_AF0 +#define SPI2_MOSI_PB7_AF1 +#define SPI2_MOSI_PC3_AF1 +#define SPI2_MOSI_PD4_AF1 +#define SPI2_SCK_PA0_AF0 +#define SPI2_SCK_PB10_AF5 +#define SPI2_SCK_PB13_AF0 +#define SPI2_SCK_PB8_AF1 +#define SPI2_SCK_PD1_AF1 +#define SPI3_MISO_PB4_AF9 +#define SPI3_MISO_PC11_AF4 +#define SPI3_MOSI_PB5_AF9 +#define SPI3_MOSI_PC12_AF4 +#define SPI3_SCK_PB3_AF9 +#define SPI3_SCK_PC10_AF4 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF5 +#define LPTIM1_ETR_PC3_AF0 +#define LPTIM2_ETR_PA5_AF5 +#define LPTIM2_ETR_PC3_AF2 +#define LPTIM2_ETR_PD11_AF1 +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PB1_AF0 +#define TIM14_CH1_PC12_AF2 +#define TIM14_CH1_PF0_AF2 +#define TIM15_CH1N_PA1_AF5 +#define TIM15_CH1N_PB13_AF5 +#define TIM15_CH1N_PB15_AF4 +#define TIM15_CH1N_PF1_AF2 +#define TIM15_CH1_PA2_AF5 +#define TIM15_CH1_PB14_AF5 +#define TIM15_CH1_PC1_AF2 +#define TIM15_CH1_PF12_AF0 +#define TIM15_CH2_PA3_AF5 +#define TIM15_CH2_PB15_AF5 +#define TIM15_CH2_PC2_AF2 +#define TIM15_CH2_PF13_AF0 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB8_AF2 +#define TIM16_CH1_PD0_AF2 +#define TIM16_CH1_PE0_AF0 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PB9_AF2 +#define TIM17_CH1_PD1_AF2 +#define TIM17_CH1_PE1_AF0 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1N_PB13_AF2 +#define TIM1_CH1N_PD2_AF2 +#define TIM1_CH1N_PE8_AF1 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH1_PC8_AF2 +#define TIM1_CH1_PE9_AF1 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2N_PB14_AF2 +#define TIM1_CH2N_PD3_AF2 +#define TIM1_CH2N_PE10_AF1 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH2_PC9_AF2 +#define TIM1_CH2_PE11_AF1 +#define TIM1_CH3N_PB15_AF2 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3N_PD4_AF2 +#define TIM1_CH3N_PE12_AF1 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH3_PC10_AF2 +#define TIM1_CH3_PE13_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_CH4_PC11_AF2 +#define TIM1_CH4_PE14_AF1 +#define TIM1_ETR_PA12_AF2 +#define TIM1_ETR_PE7_AF1 +#define TIM2_CH1_PA0_AF2 +#define TIM2_CH1_PA15_AF2 +#define TIM2_CH1_PA5_AF2 +#define TIM2_CH1_PC4_AF2 +#define TIM2_CH2_PA1_AF2 +#define TIM2_CH2_PB3_AF2 +#define TIM2_CH2_PC5_AF2 +#define TIM2_CH3_PA2_AF2 +#define TIM2_CH3_PB10_AF2 +#define TIM2_CH3_PC6_AF2 +#define TIM2_CH4_PA3_AF2 +#define TIM2_CH4_PB11_AF2 +#define TIM2_CH4_PC7_AF2 +#define TIM2_ETR_PA0_AF2 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM2_ETR_PC4_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH1_PC6_AF1 +#define TIM3_CH1_PE3_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH2_PC7_AF1 +#define TIM3_CH2_PE4_AF1 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH3_PC8_AF1 +#define TIM3_CH3_PE5_AF1 +#define TIM3_CH4_PB1_AF1 +#define TIM3_CH4_PC9_AF1 +#define TIM3_CH4_PE6_AF1 +#define TIM3_ETR_PD2_AF1 +#define TIM3_ETR_PE2_AF1 +#define TIM4_CH1_PB6_AF9 +#define TIM4_CH1_PD12_AF2 +#define TIM4_CH2_PB7_AF9 +#define TIM4_CH2_PD13_AF2 +#define TIM4_CH3_PB8_AF9 +#define TIM4_CH3_PD14_AF2 +#define TIM4_CH4_PB9_AF9 +#define TIM4_CH4_PD15_AF2 +#define TIM4_ETR_PE0_AF2 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_14 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +#define TIM1_BUS (1) +#define TIM4_BUS (1) +#define TIM15_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PE0_CN +#define __PE1_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN +#define __PE6_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PF10_CN +#define __PF11_CN +#define __PF12_CN +#define __PF13_CN +#define __PF2_CN +#define __PF3_CN +#define __PF4_CN +#define __PF5_CN +#define __PF6_CN +#define __PF7_CN +#define __PF8_CN +#define __PF9_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN + +#define PORT_COUNT (6) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +#define UART3_IVT (29) +#define UART3_NVIC (45) +#define UART4_IVT (29) +#define UART4_NVIC (45) +#define UART5_IVT (29) +#define UART5_NVIC (45) +#define UART6_IVT (29) +#define UART6_NVIC (45) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0C1VE/LQFP100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0C1VE/LQFP100/mcu_definitions.h new file mode 100644 index 000000000..37df7e6c7 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0C1VE/LQFP100/mcu_definitions.h @@ -0,0 +1,526 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G0C1VE_LQFP100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PB0_CH8 +#define ADC1_PB10_CH11 +#define ADC1_PB11_CH15 +#define ADC1_PB12_CH16 +#define ADC1_PB1_CH9 +#define ADC1_PB2_CH10 +#define ADC1_PC4_CH17 +#define ADC1_PC5_CH18 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF3 +#define FDCAN1_RX_PB8_AF3 +#define FDCAN1_RX_PC4_AF3 +#define FDCAN1_RX_PD0_AF3 +#define FDCAN1_RX_PD12_AF3 +#define FDCAN1_TX_PA12_AF3 +#define FDCAN1_TX_PB9_AF3 +#define FDCAN1_TX_PC5_AF3 +#define FDCAN1_TX_PD13_AF3 +#define FDCAN1_TX_PD1_AF3 +#define FDCAN2_RX_PB0_AF3 +#define FDCAN2_RX_PB12_AF3 +#define FDCAN2_RX_PB5_AF3 +#define FDCAN2_RX_PC2_AF3 +#define FDCAN2_RX_PD14_AF3 +#define FDCAN2_TX_PB13_AF3 +#define FDCAN2_TX_PB1_AF3 +#define FDCAN2_TX_PB6_AF3 +#define FDCAN2_TX_PC3_AF3 +#define FDCAN2_TX_PD15_AF3 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) + +#define CAN_MODULE_COUNT (2) + +#define HAL_LL_FDCAN1_GPIO_AF3 (3) +#define HAL_LL_FDCAN2_GPIO_AF3 (3) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (78) +#define DMA_NUM_OF_CHANNELS_FAMILY (78) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (12) +#define DMA_NUM_OF_STREAMS_FAMILY (12) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PB9_AF6 +#define I2C2_SCL_PA11_AF6 +#define I2C2_SCL_PA7_AF8 +#define I2C2_SCL_PA9_AF8 +#define I2C2_SCL_PB10_AF6 +#define I2C2_SCL_PB13_AF6 +#define I2C2_SCL_PB3_AF8 +#define I2C2_SDA_PA10_AF8 +#define I2C2_SDA_PA12_AF6 +#define I2C2_SDA_PA6_AF8 +#define I2C2_SDA_PB11_AF6 +#define I2C2_SDA_PB14_AF6 +#define I2C2_SDA_PB4_AF8 +#define I2C3_SCL_PA7_AF9 +#define I2C3_SCL_PB3_AF6 +#define I2C3_SCL_PC0_AF6 +#define I2C3_SDA_PA6_AF9 +#define I2C3_SDA_PB4_AF6 +#define I2C3_SDA_PC1_AF6 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF6 +#define LPUART1_RX_PB10_AF1 +#define LPUART1_RX_PC0_AF1 +#define LPUART1_RX_PF5_AF1 +#define LPUART1_TX_PA2_AF6 +#define LPUART1_TX_PB11_AF1 +#define LPUART1_TX_PC1_AF1 +#define LPUART1_TX_PF4_AF1 +#define LPUART2_RX_PA13_AF10 +#define LPUART2_RX_PB7_AF10 +#define LPUART2_RX_PC1_AF3 +#define LPUART2_RX_PC7_AF3 +#define LPUART2_RX_PF3_AF1 +#define LPUART2_TX_PA14_AF10 +#define LPUART2_TX_PB6_AF10 +#define LPUART2_TX_PC0_AF3 +#define LPUART2_TX_PC6_AF3 +#define LPUART2_TX_PF2_AF1 +#define USART1_RX_PA10_AF1 +#define USART1_RX_PB7_AF0 +#define USART1_RX_PC5_AF1 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART1_TX_PC4_AF1 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_RX_PD6_AF0 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 +#define USART2_TX_PD5_AF0 +#define USART3_RX_PB0_AF4 +#define USART3_RX_PB11_AF4 +#define USART3_RX_PB9_AF4 +#define USART3_RX_PC11_AF0 +#define USART3_RX_PC5_AF0 +#define USART3_RX_PD9_AF0 +#define USART3_TX_PA5_AF4 +#define USART3_TX_PB10_AF4 +#define USART3_TX_PB2_AF4 +#define USART3_TX_PB8_AF4 +#define USART3_TX_PC10_AF0 +#define USART3_TX_PC4_AF0 +#define USART3_TX_PD8_AF0 +#define USART4_RX_PA1_AF4 +#define USART4_RX_PC11_AF1 +#define USART4_RX_PE9_AF0 +#define USART4_TX_PA0_AF4 +#define USART4_TX_PC10_AF1 +#define USART4_TX_PE8_AF0 +#define USART5_RX_PB1_AF8 +#define USART5_RX_PB4_AF3 +#define USART5_RX_PD2_AF3 +#define USART5_RX_PE11_AF3 +#define USART5_TX_PB0_AF8 +#define USART5_TX_PB3_AF3 +#define USART5_TX_PC12_AF3 +#define USART5_TX_PD3_AF3 +#define USART5_TX_PE10_AF3 +#define USART6_RX_PA5_AF3 +#define USART6_RX_PB9_AF8 +#define USART6_RX_PC1_AF4 +#define USART6_RX_PF10_AF3 +#define USART6_TX_PA4_AF3 +#define USART6_TX_PB8_AF8 +#define USART6_TX_PC0_AF4 +#define USART6_TX_PF9_AF3 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) +#define UART_MODULE_6 (6) + +#define UART_MODULE_COUNT (6) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MISO_PD5_AF1 +#define SPI1_MISO_PE14_AF0 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_MOSI_PD6_AF1 +#define SPI1_MOSI_PE15_AF0 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI1_SCK_PD8_AF1 +#define SPI1_SCK_PE13_AF0 +#define SPI2_MISO_PA3_AF0 +#define SPI2_MISO_PA9_AF4 +#define SPI2_MISO_PB14_AF0 +#define SPI2_MISO_PB2_AF1 +#define SPI2_MISO_PB6_AF4 +#define SPI2_MISO_PC2_AF1 +#define SPI2_MISO_PD3_AF1 +#define SPI2_MOSI_PA10_AF0 +#define SPI2_MOSI_PA4_AF1 +#define SPI2_MOSI_PB11_AF0 +#define SPI2_MOSI_PB15_AF0 +#define SPI2_MOSI_PB7_AF1 +#define SPI2_MOSI_PC3_AF1 +#define SPI2_MOSI_PD4_AF1 +#define SPI2_SCK_PA0_AF0 +#define SPI2_SCK_PB10_AF5 +#define SPI2_SCK_PB13_AF0 +#define SPI2_SCK_PB8_AF1 +#define SPI2_SCK_PD1_AF1 +#define SPI3_MISO_PB4_AF9 +#define SPI3_MISO_PC11_AF4 +#define SPI3_MOSI_PB5_AF9 +#define SPI3_MOSI_PC12_AF4 +#define SPI3_SCK_PB3_AF9 +#define SPI3_SCK_PC10_AF4 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF5 +#define LPTIM1_ETR_PC3_AF0 +#define LPTIM2_ETR_PA5_AF5 +#define LPTIM2_ETR_PC3_AF2 +#define LPTIM2_ETR_PD11_AF1 +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PB1_AF0 +#define TIM14_CH1_PC12_AF2 +#define TIM14_CH1_PF0_AF2 +#define TIM15_CH1N_PA1_AF5 +#define TIM15_CH1N_PB13_AF5 +#define TIM15_CH1N_PB15_AF4 +#define TIM15_CH1N_PF1_AF2 +#define TIM15_CH1_PA2_AF5 +#define TIM15_CH1_PB14_AF5 +#define TIM15_CH1_PC1_AF2 +#define TIM15_CH1_PF12_AF0 +#define TIM15_CH2_PA3_AF5 +#define TIM15_CH2_PB15_AF5 +#define TIM15_CH2_PC2_AF2 +#define TIM15_CH2_PF13_AF0 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB8_AF2 +#define TIM16_CH1_PD0_AF2 +#define TIM16_CH1_PE0_AF0 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PB9_AF2 +#define TIM17_CH1_PD1_AF2 +#define TIM17_CH1_PE1_AF0 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1N_PB13_AF2 +#define TIM1_CH1N_PD2_AF2 +#define TIM1_CH1N_PE8_AF1 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH1_PC8_AF2 +#define TIM1_CH1_PE9_AF1 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2N_PB14_AF2 +#define TIM1_CH2N_PD3_AF2 +#define TIM1_CH2N_PE10_AF1 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH2_PC9_AF2 +#define TIM1_CH2_PE11_AF1 +#define TIM1_CH3N_PB15_AF2 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3N_PD4_AF2 +#define TIM1_CH3N_PE12_AF1 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH3_PC10_AF2 +#define TIM1_CH3_PE13_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_CH4_PC11_AF2 +#define TIM1_CH4_PE14_AF1 +#define TIM1_ETR_PA12_AF2 +#define TIM1_ETR_PE7_AF1 +#define TIM2_CH1_PA0_AF2 +#define TIM2_CH1_PA15_AF2 +#define TIM2_CH1_PA5_AF2 +#define TIM2_CH1_PC4_AF2 +#define TIM2_CH2_PA1_AF2 +#define TIM2_CH2_PB3_AF2 +#define TIM2_CH2_PC5_AF2 +#define TIM2_CH3_PA2_AF2 +#define TIM2_CH3_PB10_AF2 +#define TIM2_CH3_PC6_AF2 +#define TIM2_CH4_PA3_AF2 +#define TIM2_CH4_PB11_AF2 +#define TIM2_CH4_PC7_AF2 +#define TIM2_ETR_PA0_AF2 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM2_ETR_PC4_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH1_PC6_AF1 +#define TIM3_CH1_PE3_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH2_PC7_AF1 +#define TIM3_CH2_PE4_AF1 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH3_PC8_AF1 +#define TIM3_CH3_PE5_AF1 +#define TIM3_CH4_PB1_AF1 +#define TIM3_CH4_PC9_AF1 +#define TIM3_CH4_PE6_AF1 +#define TIM3_ETR_PD2_AF1 +#define TIM3_ETR_PE2_AF1 +#define TIM4_CH1_PB6_AF9 +#define TIM4_CH1_PD12_AF2 +#define TIM4_CH2_PB7_AF9 +#define TIM4_CH2_PD13_AF2 +#define TIM4_CH3_PB8_AF9 +#define TIM4_CH3_PD14_AF2 +#define TIM4_CH4_PB9_AF9 +#define TIM4_CH4_PD15_AF2 +#define TIM4_ETR_PE0_AF2 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_14 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +#define TIM1_BUS (1) +#define TIM4_BUS (1) +#define TIM15_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PE0_CN +#define __PE1_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN +#define __PE6_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PF10_CN +#define __PF11_CN +#define __PF12_CN +#define __PF13_CN +#define __PF2_CN +#define __PF3_CN +#define __PF4_CN +#define __PF5_CN +#define __PF6_CN +#define __PF7_CN +#define __PF8_CN +#define __PF9_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN + +#define PORT_COUNT (6) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +#define UART3_IVT (29) +#define UART3_NVIC (45) +#define UART4_IVT (29) +#define UART4_NVIC (45) +#define UART5_IVT (29) +#define UART5_NVIC (45) +#define UART6_IVT (29) +#define UART6_NVIC (45) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0C1VE/UFBGA100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0C1VE/UFBGA100/mcu_definitions.h new file mode 100644 index 000000000..f28e2c4a6 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G0C1VE/UFBGA100/mcu_definitions.h @@ -0,0 +1,526 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G0C1VE_UFBGA100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH0 +#define ADC1_PA1_CH1 +#define ADC1_PA2_CH2 +#define ADC1_PA3_CH3 +#define ADC1_PA4_CH4 +#define ADC1_PA5_CH5 +#define ADC1_PA6_CH6 +#define ADC1_PA7_CH7 +#define ADC1_PB0_CH8 +#define ADC1_PB10_CH11 +#define ADC1_PB11_CH15 +#define ADC1_PB12_CH16 +#define ADC1_PB1_CH9 +#define ADC1_PB2_CH10 +#define ADC1_PC4_CH17 +#define ADC1_PC5_CH18 + +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (1) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF3 +#define FDCAN1_RX_PB8_AF3 +#define FDCAN1_RX_PC4_AF3 +#define FDCAN1_RX_PD0_AF3 +#define FDCAN1_RX_PD12_AF3 +#define FDCAN1_TX_PA12_AF3 +#define FDCAN1_TX_PB9_AF3 +#define FDCAN1_TX_PC5_AF3 +#define FDCAN1_TX_PD13_AF3 +#define FDCAN1_TX_PD1_AF3 +#define FDCAN2_RX_PB0_AF3 +#define FDCAN2_RX_PB12_AF3 +#define FDCAN2_RX_PB5_AF3 +#define FDCAN2_RX_PC2_AF3 +#define FDCAN2_RX_PD14_AF3 +#define FDCAN2_TX_PB13_AF3 +#define FDCAN2_TX_PB1_AF3 +#define FDCAN2_TX_PB6_AF3 +#define FDCAN2_TX_PC3_AF3 +#define FDCAN2_TX_PD15_AF3 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) + +#define CAN_MODULE_COUNT (2) + +#define HAL_LL_FDCAN1_GPIO_AF3 (3) +#define HAL_LL_FDCAN2_GPIO_AF3 (3) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (78) +#define DMA_NUM_OF_CHANNELS_FAMILY (78) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (12) +#define DMA_NUM_OF_STREAMS_FAMILY (12) +// EOF DMA + +// I2C +#define I2C1_SCL_PA9_AF6 +#define I2C1_SCL_PB6_AF6 +#define I2C1_SCL_PB8_AF6 +#define I2C1_SDA_PA10_AF6 +#define I2C1_SDA_PB7_AF6 +#define I2C1_SDA_PB9_AF6 +#define I2C2_SCL_PA11_AF6 +#define I2C2_SCL_PA7_AF8 +#define I2C2_SCL_PA9_AF8 +#define I2C2_SCL_PB10_AF6 +#define I2C2_SCL_PB13_AF6 +#define I2C2_SCL_PB3_AF8 +#define I2C2_SDA_PA10_AF8 +#define I2C2_SDA_PA12_AF6 +#define I2C2_SDA_PA6_AF8 +#define I2C2_SDA_PB11_AF6 +#define I2C2_SDA_PB14_AF6 +#define I2C2_SDA_PB4_AF8 +#define I2C3_SCL_PA7_AF9 +#define I2C3_SCL_PB3_AF6 +#define I2C3_SCL_PC0_AF6 +#define I2C3_SDA_PA6_AF9 +#define I2C3_SDA_PB4_AF6 +#define I2C3_SDA_PC1_AF6 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF6 +#define LPUART1_RX_PB10_AF1 +#define LPUART1_RX_PC0_AF1 +#define LPUART1_RX_PF5_AF1 +#define LPUART1_TX_PA2_AF6 +#define LPUART1_TX_PB11_AF1 +#define LPUART1_TX_PC1_AF1 +#define LPUART1_TX_PF4_AF1 +#define LPUART2_RX_PA13_AF10 +#define LPUART2_RX_PB7_AF10 +#define LPUART2_RX_PC1_AF3 +#define LPUART2_RX_PC7_AF3 +#define LPUART2_RX_PF3_AF1 +#define LPUART2_TX_PA14_AF10 +#define LPUART2_TX_PB6_AF10 +#define LPUART2_TX_PC0_AF3 +#define LPUART2_TX_PC6_AF3 +#define LPUART2_TX_PF2_AF1 +#define USART1_RX_PA10_AF1 +#define USART1_RX_PB7_AF0 +#define USART1_RX_PC5_AF1 +#define USART1_TX_PA9_AF1 +#define USART1_TX_PB6_AF0 +#define USART1_TX_PC4_AF1 +#define USART2_RX_PA15_AF1 +#define USART2_RX_PA3_AF1 +#define USART2_RX_PD6_AF0 +#define USART2_TX_PA14_AF1 +#define USART2_TX_PA2_AF1 +#define USART2_TX_PD5_AF0 +#define USART3_RX_PB0_AF4 +#define USART3_RX_PB11_AF4 +#define USART3_RX_PB9_AF4 +#define USART3_RX_PC11_AF0 +#define USART3_RX_PC5_AF0 +#define USART3_RX_PD9_AF0 +#define USART3_TX_PA5_AF4 +#define USART3_TX_PB10_AF4 +#define USART3_TX_PB2_AF4 +#define USART3_TX_PB8_AF4 +#define USART3_TX_PC10_AF0 +#define USART3_TX_PC4_AF0 +#define USART3_TX_PD8_AF0 +#define USART4_RX_PA1_AF4 +#define USART4_RX_PC11_AF1 +#define USART4_RX_PE9_AF0 +#define USART4_TX_PA0_AF4 +#define USART4_TX_PC10_AF1 +#define USART4_TX_PE8_AF0 +#define USART5_RX_PB1_AF8 +#define USART5_RX_PB4_AF3 +#define USART5_RX_PD2_AF3 +#define USART5_RX_PE11_AF3 +#define USART5_TX_PB0_AF8 +#define USART5_TX_PB3_AF3 +#define USART5_TX_PC12_AF3 +#define USART5_TX_PD3_AF3 +#define USART5_TX_PE10_AF3 +#define USART6_RX_PA5_AF3 +#define USART6_RX_PB9_AF8 +#define USART6_RX_PC1_AF4 +#define USART6_RX_PF10_AF3 +#define USART6_TX_PA4_AF3 +#define USART6_TX_PB8_AF8 +#define USART6_TX_PC0_AF4 +#define USART6_TX_PF9_AF3 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) +#define UART_MODULE_6 (6) + +#define UART_MODULE_COUNT (6) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF0 +#define SPI1_MISO_PA6_AF0 +#define SPI1_MISO_PB4_AF0 +#define SPI1_MISO_PD5_AF1 +#define SPI1_MISO_PE14_AF0 +#define SPI1_MOSI_PA12_AF0 +#define SPI1_MOSI_PA2_AF0 +#define SPI1_MOSI_PA7_AF0 +#define SPI1_MOSI_PB5_AF0 +#define SPI1_MOSI_PD6_AF1 +#define SPI1_MOSI_PE15_AF0 +#define SPI1_SCK_PA1_AF0 +#define SPI1_SCK_PA5_AF0 +#define SPI1_SCK_PB3_AF0 +#define SPI1_SCK_PD8_AF1 +#define SPI1_SCK_PE13_AF0 +#define SPI2_MISO_PA3_AF0 +#define SPI2_MISO_PA9_AF4 +#define SPI2_MISO_PB14_AF0 +#define SPI2_MISO_PB2_AF1 +#define SPI2_MISO_PB6_AF4 +#define SPI2_MISO_PC2_AF1 +#define SPI2_MISO_PD3_AF1 +#define SPI2_MOSI_PA10_AF0 +#define SPI2_MOSI_PA4_AF1 +#define SPI2_MOSI_PB11_AF0 +#define SPI2_MOSI_PB15_AF0 +#define SPI2_MOSI_PB7_AF1 +#define SPI2_MOSI_PC3_AF1 +#define SPI2_MOSI_PD4_AF1 +#define SPI2_SCK_PA0_AF0 +#define SPI2_SCK_PB10_AF5 +#define SPI2_SCK_PB13_AF0 +#define SPI2_SCK_PB8_AF1 +#define SPI2_SCK_PD1_AF1 +#define SPI3_MISO_PB4_AF9 +#define SPI3_MISO_PC11_AF4 +#define SPI3_MOSI_PB5_AF9 +#define SPI3_MOSI_PC12_AF4 +#define SPI3_SCK_PB3_AF9 +#define SPI3_SCK_PC10_AF4 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF5 +#define LPTIM1_ETR_PC3_AF0 +#define LPTIM2_ETR_PA5_AF5 +#define LPTIM2_ETR_PC3_AF2 +#define LPTIM2_ETR_PD11_AF1 +#define TIM14_CH1_PA4_AF4 +#define TIM14_CH1_PA7_AF4 +#define TIM14_CH1_PB1_AF0 +#define TIM14_CH1_PC12_AF2 +#define TIM14_CH1_PF0_AF2 +#define TIM15_CH1N_PA1_AF5 +#define TIM15_CH1N_PB13_AF5 +#define TIM15_CH1N_PB15_AF4 +#define TIM15_CH1N_PF1_AF2 +#define TIM15_CH1_PA2_AF5 +#define TIM15_CH1_PB14_AF5 +#define TIM15_CH1_PC1_AF2 +#define TIM15_CH1_PF12_AF0 +#define TIM15_CH2_PA3_AF5 +#define TIM15_CH2_PB15_AF5 +#define TIM15_CH2_PC2_AF2 +#define TIM15_CH2_PF13_AF0 +#define TIM16_CH1N_PB6_AF2 +#define TIM16_CH1_PA6_AF5 +#define TIM16_CH1_PB8_AF2 +#define TIM16_CH1_PD0_AF2 +#define TIM16_CH1_PE0_AF0 +#define TIM17_CH1N_PB7_AF2 +#define TIM17_CH1_PA7_AF5 +#define TIM17_CH1_PB9_AF2 +#define TIM17_CH1_PD1_AF2 +#define TIM17_CH1_PE1_AF0 +#define TIM1_CH1N_PA7_AF2 +#define TIM1_CH1N_PB13_AF2 +#define TIM1_CH1N_PD2_AF2 +#define TIM1_CH1N_PE8_AF1 +#define TIM1_CH1_PA8_AF2 +#define TIM1_CH1_PC8_AF2 +#define TIM1_CH1_PE9_AF1 +#define TIM1_CH2N_PB0_AF2 +#define TIM1_CH2N_PB14_AF2 +#define TIM1_CH2N_PD3_AF2 +#define TIM1_CH2N_PE10_AF1 +#define TIM1_CH2_PA9_AF2 +#define TIM1_CH2_PB3_AF1 +#define TIM1_CH2_PC9_AF2 +#define TIM1_CH2_PE11_AF1 +#define TIM1_CH3N_PB15_AF2 +#define TIM1_CH3N_PB1_AF2 +#define TIM1_CH3N_PD4_AF2 +#define TIM1_CH3N_PE12_AF1 +#define TIM1_CH3_PA10_AF2 +#define TIM1_CH3_PB6_AF1 +#define TIM1_CH3_PC10_AF2 +#define TIM1_CH3_PE13_AF1 +#define TIM1_CH4_PA11_AF2 +#define TIM1_CH4_PC11_AF2 +#define TIM1_CH4_PE14_AF1 +#define TIM1_ETR_PA12_AF2 +#define TIM1_ETR_PE7_AF1 +#define TIM2_CH1_PA0_AF2 +#define TIM2_CH1_PA15_AF2 +#define TIM2_CH1_PA5_AF2 +#define TIM2_CH1_PC4_AF2 +#define TIM2_CH2_PA1_AF2 +#define TIM2_CH2_PB3_AF2 +#define TIM2_CH2_PC5_AF2 +#define TIM2_CH3_PA2_AF2 +#define TIM2_CH3_PB10_AF2 +#define TIM2_CH3_PC6_AF2 +#define TIM2_CH4_PA3_AF2 +#define TIM2_CH4_PB11_AF2 +#define TIM2_CH4_PC7_AF2 +#define TIM2_ETR_PA0_AF2 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM2_ETR_PC4_AF2 +#define TIM3_CH1_PA6_AF1 +#define TIM3_CH1_PB4_AF1 +#define TIM3_CH1_PC6_AF1 +#define TIM3_CH1_PE3_AF1 +#define TIM3_CH2_PA7_AF1 +#define TIM3_CH2_PB5_AF1 +#define TIM3_CH2_PC7_AF1 +#define TIM3_CH2_PE4_AF1 +#define TIM3_CH3_PB0_AF1 +#define TIM3_CH3_PC8_AF1 +#define TIM3_CH3_PE5_AF1 +#define TIM3_CH4_PB1_AF1 +#define TIM3_CH4_PC9_AF1 +#define TIM3_CH4_PE6_AF1 +#define TIM3_ETR_PD2_AF1 +#define TIM3_ETR_PE2_AF1 +#define TIM4_CH1_PB6_AF9 +#define TIM4_CH1_PD12_AF2 +#define TIM4_CH2_PB7_AF9 +#define TIM4_CH2_PD13_AF2 +#define TIM4_CH3_PB8_AF9 +#define TIM4_CH3_PD14_AF2 +#define TIM4_CH4_PB9_AF9 +#define TIM4_CH4_PD15_AF2 +#define TIM4_ETR_PE0_AF2 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_14 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM14_BUS (1) +#define TIM16_BUS (1) +#define TIM17_BUS (1) +#define TIM1_BUS (1) +#define TIM4_BUS (1) +#define TIM15_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PE0_CN +#define __PE1_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN +#define __PE6_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PF10_CN +#define __PF11_CN +#define __PF12_CN +#define __PF13_CN +#define __PF2_CN +#define __PF3_CN +#define __PF4_CN +#define __PF5_CN +#define __PF6_CN +#define __PF7_CN +#define __PF8_CN +#define __PF9_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN + +#define PORT_COUNT (6) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (27) +#define UART1_NVIC (43) +#define UART2_IVT (28) +#define UART2_NVIC (44) +#define UART3_IVT (29) +#define UART3_NVIC (45) +#define UART4_IVT (29) +#define UART4_NVIC (45) +#define UART5_IVT (29) +#define UART5_NVIC (45) +#define UART6_IVT (29) +#define UART6_NVIC (45) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431C6/LQFP48/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431C6/LQFP48/mcu_definitions.h new file mode 100644 index 000000000..ae816d792 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431C6/LQFP48/mcu_definitions.h @@ -0,0 +1,354 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G431C6_LQFP48. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PF1_CH10 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 + +#define CAN_MODULE_1 (1) + +#define CAN_MODULE_COUNT (1) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (6) +#define DMA_NUM_OF_STREAMS_FAMILY (6) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SDA_PB5_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) + +#define UART_MODULE_COUNT (3) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_SCK_PB3_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_ETR_PA12_AF11 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_ETR_PB3_AF10 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_8 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431C6/UFQFPN48/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431C6/UFQFPN48/mcu_definitions.h new file mode 100644 index 000000000..138cf6769 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431C6/UFQFPN48/mcu_definitions.h @@ -0,0 +1,376 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G431C6_UFQFPN48. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC4_CH5 +#define ADC2_PF1_CH10 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 + +#define CAN_MODULE_1 (1) + +#define CAN_MODULE_COUNT (1) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (6) +#define DMA_NUM_OF_STREAMS_FAMILY (6) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (4) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_ETR_PB3_AF10 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_8 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC10_CN +#define __PC11_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC4_CN +#define __PC6_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431C8/LQFP48/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431C8/LQFP48/mcu_definitions.h new file mode 100644 index 000000000..610b68cb3 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431C8/LQFP48/mcu_definitions.h @@ -0,0 +1,354 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G431C8_LQFP48. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PF1_CH10 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 + +#define CAN_MODULE_1 (1) + +#define CAN_MODULE_COUNT (1) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (6) +#define DMA_NUM_OF_STREAMS_FAMILY (6) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SDA_PB5_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) + +#define UART_MODULE_COUNT (3) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_SCK_PB3_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_ETR_PA12_AF11 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_ETR_PB3_AF10 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_8 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431C8/UFQFPN48/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431C8/UFQFPN48/mcu_definitions.h new file mode 100644 index 000000000..0837de841 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431C8/UFQFPN48/mcu_definitions.h @@ -0,0 +1,376 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G431C8_UFQFPN48. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC4_CH5 +#define ADC2_PF1_CH10 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 + +#define CAN_MODULE_1 (1) + +#define CAN_MODULE_COUNT (1) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (6) +#define DMA_NUM_OF_STREAMS_FAMILY (6) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (4) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_ETR_PB3_AF10 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_8 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC10_CN +#define __PC11_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC4_CN +#define __PC6_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431CB/LQFP48/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431CB/LQFP48/mcu_definitions.h new file mode 100644 index 000000000..c669e1c0e --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431CB/LQFP48/mcu_definitions.h @@ -0,0 +1,354 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G431CB_LQFP48. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PF1_CH10 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 + +#define CAN_MODULE_1 (1) + +#define CAN_MODULE_COUNT (1) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (6) +#define DMA_NUM_OF_STREAMS_FAMILY (6) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SDA_PB5_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) + +#define UART_MODULE_COUNT (3) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_SCK_PB3_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_ETR_PA12_AF11 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_ETR_PB3_AF10 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_8 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431CB/UFQFPN48/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431CB/UFQFPN48/mcu_definitions.h new file mode 100644 index 000000000..987f8a6de --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431CB/UFQFPN48/mcu_definitions.h @@ -0,0 +1,376 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G431CB_UFQFPN48. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC4_CH5 +#define ADC2_PF1_CH10 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 + +#define CAN_MODULE_1 (1) + +#define CAN_MODULE_COUNT (1) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (6) +#define DMA_NUM_OF_STREAMS_FAMILY (6) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (4) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_ETR_PB3_AF10 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_8 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC10_CN +#define __PC11_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC4_CN +#define __PC6_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431CB/WLCSP49/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431CB/WLCSP49/mcu_definitions.h new file mode 100644 index 000000000..2c8234b95 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431CB/WLCSP49/mcu_definitions.h @@ -0,0 +1,367 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G431CB_WLCSP49. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC4_CH5 +#define ADC2_PF1_CH10 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 + +#define CAN_MODULE_1 (1) + +#define CAN_MODULE_COUNT (1) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (6) +#define DMA_NUM_OF_STREAMS_FAMILY (6) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) + +#define UART_MODULE_COUNT (3) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_SCK_PB3_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_ETR_PB3_AF10 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_8 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC11_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC4_CN +#define __PC6_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431K6/LQFP32/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431K6/LQFP32/mcu_definitions.h new file mode 100644 index 000000000..13ff197fe --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431K6/LQFP32/mcu_definitions.h @@ -0,0 +1,300 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G431K6_LQFP32. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PF1_CH10 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_TX_PA12_AF9 + +#define CAN_MODULE_1 (1) + +#define CAN_MODULE_COUNT (1) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (6) +#define DMA_NUM_OF_STREAMS_FAMILY (6) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SDA_PB5_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_TX_PA2_AF12 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (2) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_SCK_PB3_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH2_PA3_AF9 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_ETR_PA12_AF11 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_ETR_PB3_AF10 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_8 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (4) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431K6/UFQFPN32/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431K6/UFQFPN32/mcu_definitions.h new file mode 100644 index 000000000..4c49c777e --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431K6/UFQFPN32/mcu_definitions.h @@ -0,0 +1,300 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G431K6_UFQFPN32. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PF1_CH10 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_TX_PA12_AF9 + +#define CAN_MODULE_1 (1) + +#define CAN_MODULE_COUNT (1) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (6) +#define DMA_NUM_OF_STREAMS_FAMILY (6) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SDA_PB5_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_TX_PA2_AF12 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (2) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_SCK_PB3_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH2_PA3_AF9 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_ETR_PA12_AF11 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_ETR_PB3_AF10 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_8 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (4) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431K8/LQFP32/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431K8/LQFP32/mcu_definitions.h new file mode 100644 index 000000000..c6611eadf --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431K8/LQFP32/mcu_definitions.h @@ -0,0 +1,300 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G431K8_LQFP32. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PF1_CH10 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_TX_PA12_AF9 + +#define CAN_MODULE_1 (1) + +#define CAN_MODULE_COUNT (1) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (6) +#define DMA_NUM_OF_STREAMS_FAMILY (6) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SDA_PB5_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_TX_PA2_AF12 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (2) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_SCK_PB3_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH2_PA3_AF9 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_ETR_PA12_AF11 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_ETR_PB3_AF10 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_8 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (4) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431K8/UFQFPN32/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431K8/UFQFPN32/mcu_definitions.h new file mode 100644 index 000000000..2d8b7f25e --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431K8/UFQFPN32/mcu_definitions.h @@ -0,0 +1,300 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G431K8_UFQFPN32. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PF1_CH10 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_TX_PA12_AF9 + +#define CAN_MODULE_1 (1) + +#define CAN_MODULE_COUNT (1) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (6) +#define DMA_NUM_OF_STREAMS_FAMILY (6) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SDA_PB5_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_TX_PA2_AF12 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (2) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_SCK_PB3_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH2_PA3_AF9 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_ETR_PA12_AF11 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_ETR_PB3_AF10 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_8 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (4) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431KB/LQFP32/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431KB/LQFP32/mcu_definitions.h new file mode 100644 index 000000000..ecf9beba1 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431KB/LQFP32/mcu_definitions.h @@ -0,0 +1,300 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G431KB_LQFP32. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PF1_CH10 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_TX_PA12_AF9 + +#define CAN_MODULE_1 (1) + +#define CAN_MODULE_COUNT (1) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (6) +#define DMA_NUM_OF_STREAMS_FAMILY (6) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SDA_PB5_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_TX_PA2_AF12 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (2) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_SCK_PB3_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH2_PA3_AF9 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_ETR_PA12_AF11 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_ETR_PB3_AF10 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_8 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (4) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431KB/UFQFPN32/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431KB/UFQFPN32/mcu_definitions.h new file mode 100644 index 000000000..0a0d1c5b5 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431KB/UFQFPN32/mcu_definitions.h @@ -0,0 +1,300 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G431KB_UFQFPN32. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PF1_CH10 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_TX_PA12_AF9 + +#define CAN_MODULE_1 (1) + +#define CAN_MODULE_COUNT (1) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (6) +#define DMA_NUM_OF_STREAMS_FAMILY (6) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SDA_PB5_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_TX_PA2_AF12 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (2) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_SCK_PB3_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH2_PA3_AF9 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_ETR_PA12_AF11 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_ETR_PB3_AF10 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_8 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (4) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431M6/LQFP80/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431M6/LQFP80/mcu_definitions.h new file mode 100644 index 000000000..ac6cc86df --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431M6/LQFP80/mcu_definitions.h @@ -0,0 +1,454 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G431M6_LQFP80. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_RX_PD0_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN1_TX_PD1_AF9 + +#define CAN_MODULE_1 (1) + +#define CAN_MODULE_COUNT (1) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (6) +#define DMA_NUM_OF_STREAMS_FAMILY (6) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PD9_AF7 +#define USART3_RX_PE15_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PD8_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (4) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN2_PE14_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_BKIN_PE15_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1N_PE8_AF2 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH1_PE9_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2N_PE10_AF2 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH2_PE11_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PE12_AF2 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH3_PE13_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4N_PE15_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_CH4_PE14_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM1_ETR_PE7_AF2 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN2_PD1_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4N_PD0_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_CH4_PD1_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_8 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD2_CN +#define __PD8_CN +#define __PD9_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (7) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431M8/LQFP80/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431M8/LQFP80/mcu_definitions.h new file mode 100644 index 000000000..d6bd11b02 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431M8/LQFP80/mcu_definitions.h @@ -0,0 +1,454 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G431M8_LQFP80. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_RX_PD0_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN1_TX_PD1_AF9 + +#define CAN_MODULE_1 (1) + +#define CAN_MODULE_COUNT (1) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (6) +#define DMA_NUM_OF_STREAMS_FAMILY (6) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PD9_AF7 +#define USART3_RX_PE15_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PD8_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (4) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN2_PE14_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_BKIN_PE15_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1N_PE8_AF2 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH1_PE9_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2N_PE10_AF2 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH2_PE11_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PE12_AF2 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH3_PE13_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4N_PE15_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_CH4_PE14_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM1_ETR_PE7_AF2 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN2_PD1_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4N_PD0_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_CH4_PD1_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_8 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD2_CN +#define __PD8_CN +#define __PD9_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (7) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431MB/LQFP80/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431MB/LQFP80/mcu_definitions.h new file mode 100644 index 000000000..85de6e579 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431MB/LQFP80/mcu_definitions.h @@ -0,0 +1,454 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G431MB_LQFP80. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_RX_PD0_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN1_TX_PD1_AF9 + +#define CAN_MODULE_1 (1) + +#define CAN_MODULE_COUNT (1) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (6) +#define DMA_NUM_OF_STREAMS_FAMILY (6) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PD9_AF7 +#define USART3_RX_PE15_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PD8_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (4) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN2_PE14_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_BKIN_PE15_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1N_PE8_AF2 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH1_PE9_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2N_PE10_AF2 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH2_PE11_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PE12_AF2 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH3_PE13_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4N_PE15_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_CH4_PE14_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM1_ETR_PE7_AF2 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN2_PD1_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4N_PD0_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_CH4_PD1_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_8 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD2_CN +#define __PD8_CN +#define __PD9_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (7) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431R6/LQFP64/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431R6/LQFP64/mcu_definitions.h new file mode 100644 index 000000000..75b047363 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431R6/LQFP64/mcu_definitions.h @@ -0,0 +1,420 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G431R6_LQFP64. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 + +#define CAN_MODULE_1 (1) + +#define CAN_MODULE_COUNT (1) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (6) +#define DMA_NUM_OF_STREAMS_FAMILY (6) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (4) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_8 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD2_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (6) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431R6/UFBGA64/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431R6/UFBGA64/mcu_definitions.h new file mode 100644 index 000000000..6faab65ae --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431R6/UFBGA64/mcu_definitions.h @@ -0,0 +1,420 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G431R6_UFBGA64. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 + +#define CAN_MODULE_1 (1) + +#define CAN_MODULE_COUNT (1) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (6) +#define DMA_NUM_OF_STREAMS_FAMILY (6) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (4) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_8 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD2_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (6) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431R8/LQFP64/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431R8/LQFP64/mcu_definitions.h new file mode 100644 index 000000000..b656dfc45 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431R8/LQFP64/mcu_definitions.h @@ -0,0 +1,420 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G431R8_LQFP64. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 + +#define CAN_MODULE_1 (1) + +#define CAN_MODULE_COUNT (1) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (6) +#define DMA_NUM_OF_STREAMS_FAMILY (6) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (4) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_8 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD2_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (6) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431R8/UFBGA64/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431R8/UFBGA64/mcu_definitions.h new file mode 100644 index 000000000..a073aa7f7 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431R8/UFBGA64/mcu_definitions.h @@ -0,0 +1,420 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G431R8_UFBGA64. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 + +#define CAN_MODULE_1 (1) + +#define CAN_MODULE_COUNT (1) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (6) +#define DMA_NUM_OF_STREAMS_FAMILY (6) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (4) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_8 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD2_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (6) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431RB/LQFP64/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431RB/LQFP64/mcu_definitions.h new file mode 100644 index 000000000..d7c56f5bd --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431RB/LQFP64/mcu_definitions.h @@ -0,0 +1,420 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G431RB_LQFP64. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 + +#define CAN_MODULE_1 (1) + +#define CAN_MODULE_COUNT (1) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (6) +#define DMA_NUM_OF_STREAMS_FAMILY (6) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (4) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_8 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD2_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (6) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431RB/UFBGA64/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431RB/UFBGA64/mcu_definitions.h new file mode 100644 index 000000000..ecb703f45 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431RB/UFBGA64/mcu_definitions.h @@ -0,0 +1,420 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G431RB_UFBGA64. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 + +#define CAN_MODULE_1 (1) + +#define CAN_MODULE_COUNT (1) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (6) +#define DMA_NUM_OF_STREAMS_FAMILY (6) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (4) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_8 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD2_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (6) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431V6/LQFP100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431V6/LQFP100/mcu_definitions.h new file mode 100644 index 000000000..7236a5c53 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431V6/LQFP100/mcu_definitions.h @@ -0,0 +1,498 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G431V6_LQFP100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_RX_PD0_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN1_TX_PD1_AF9 + +#define CAN_MODULE_1 (1) + +#define CAN_MODULE_COUNT (1) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (6) +#define DMA_NUM_OF_STREAMS_FAMILY (6) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_RX_PE1_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART1_TX_PE0_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_RX_PD6_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART2_TX_PD5_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PD9_AF7 +#define USART3_RX_PE15_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PD8_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (4) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF10_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI2_SCK_PF9_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH1_PF9_AF3 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM15_CH2_PF10_AF3 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM16_CH1_PE0_AF4 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM17_CH1_PE1_AF4 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN2_PE14_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_BKIN_PE15_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1N_PE8_AF2 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH1_PE9_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2N_PE10_AF2 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH2_PE11_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PE12_AF2 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH3_PE13_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4N_PE15_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_CH4_PE14_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM1_ETR_PE7_AF2 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH1_PD3_AF2 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH2_PD4_AF2 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH3_PD7_AF2 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_CH4_PD6_AF2 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM2_ETR_PD3_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH1_PE2_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH2_PE3_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH3_PE4_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_CH4_PE5_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH1_PD12_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH2_PD13_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH3_PD14_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_CH4_PD15_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM4_ETR_PE0_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN2_PD1_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4N_PD0_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_CH4_PD1_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_8 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PE0_CN +#define __PE1_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN +#define __PE6_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PF10_CN +#define __PF2_CN +#define __PF9_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (7) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431V8/LQFP100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431V8/LQFP100/mcu_definitions.h new file mode 100644 index 000000000..0c7ee908e --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431V8/LQFP100/mcu_definitions.h @@ -0,0 +1,498 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G431V8_LQFP100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_RX_PD0_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN1_TX_PD1_AF9 + +#define CAN_MODULE_1 (1) + +#define CAN_MODULE_COUNT (1) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (6) +#define DMA_NUM_OF_STREAMS_FAMILY (6) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_RX_PE1_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART1_TX_PE0_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_RX_PD6_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART2_TX_PD5_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PD9_AF7 +#define USART3_RX_PE15_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PD8_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (4) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF10_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI2_SCK_PF9_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH1_PF9_AF3 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM15_CH2_PF10_AF3 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM16_CH1_PE0_AF4 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM17_CH1_PE1_AF4 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN2_PE14_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_BKIN_PE15_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1N_PE8_AF2 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH1_PE9_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2N_PE10_AF2 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH2_PE11_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PE12_AF2 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH3_PE13_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4N_PE15_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_CH4_PE14_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM1_ETR_PE7_AF2 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH1_PD3_AF2 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH2_PD4_AF2 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH3_PD7_AF2 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_CH4_PD6_AF2 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM2_ETR_PD3_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH1_PE2_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH2_PE3_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH3_PE4_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_CH4_PE5_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH1_PD12_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH2_PD13_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH3_PD14_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_CH4_PD15_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM4_ETR_PE0_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN2_PD1_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4N_PD0_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_CH4_PD1_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_8 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PE0_CN +#define __PE1_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN +#define __PE6_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PF10_CN +#define __PF2_CN +#define __PF9_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (7) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431VB/LQFP100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431VB/LQFP100/mcu_definitions.h new file mode 100644 index 000000000..3aea3444e --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G431VB/LQFP100/mcu_definitions.h @@ -0,0 +1,498 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G431VB_LQFP100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_RX_PD0_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN1_TX_PD1_AF9 + +#define CAN_MODULE_1 (1) + +#define CAN_MODULE_COUNT (1) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (6) +#define DMA_NUM_OF_STREAMS_FAMILY (6) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_RX_PE1_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART1_TX_PE0_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_RX_PD6_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART2_TX_PD5_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PD9_AF7 +#define USART3_RX_PE15_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PD8_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (4) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF10_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI2_SCK_PF9_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH1_PF9_AF3 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM15_CH2_PF10_AF3 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM16_CH1_PE0_AF4 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM17_CH1_PE1_AF4 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN2_PE14_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_BKIN_PE15_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1N_PE8_AF2 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH1_PE9_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2N_PE10_AF2 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH2_PE11_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PE12_AF2 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH3_PE13_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4N_PE15_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_CH4_PE14_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM1_ETR_PE7_AF2 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH1_PD3_AF2 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH2_PD4_AF2 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH3_PD7_AF2 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_CH4_PD6_AF2 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM2_ETR_PD3_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH1_PE2_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH2_PE3_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH3_PE4_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_CH4_PE5_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH1_PD12_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH2_PD13_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH3_PD14_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_CH4_PD15_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM4_ETR_PE0_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN2_PD1_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4N_PD0_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_CH4_PD1_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_8 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PE0_CN +#define __PE1_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN +#define __PE6_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PF10_CN +#define __PF2_CN +#define __PF9_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (7) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G441CB/LQFP48/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G441CB/LQFP48/mcu_definitions.h new file mode 100644 index 000000000..bcb4b8623 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G441CB/LQFP48/mcu_definitions.h @@ -0,0 +1,354 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G441CB_LQFP48. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PF1_CH10 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 + +#define CAN_MODULE_1 (1) + +#define CAN_MODULE_COUNT (1) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (6) +#define DMA_NUM_OF_STREAMS_FAMILY (6) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SDA_PB5_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) + +#define UART_MODULE_COUNT (3) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_SCK_PB3_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_ETR_PA12_AF11 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_ETR_PB3_AF10 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_8 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G441CB/UFQFPN48/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G441CB/UFQFPN48/mcu_definitions.h new file mode 100644 index 000000000..c04e40cca --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G441CB/UFQFPN48/mcu_definitions.h @@ -0,0 +1,376 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G441CB_UFQFPN48. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC4_CH5 +#define ADC2_PF1_CH10 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 + +#define CAN_MODULE_1 (1) + +#define CAN_MODULE_COUNT (1) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (6) +#define DMA_NUM_OF_STREAMS_FAMILY (6) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (4) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_ETR_PB3_AF10 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_8 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC10_CN +#define __PC11_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC4_CN +#define __PC6_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G441CB/WLCSP49/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G441CB/WLCSP49/mcu_definitions.h new file mode 100644 index 000000000..e17f514fb --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G441CB/WLCSP49/mcu_definitions.h @@ -0,0 +1,367 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G441CB_WLCSP49. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC4_CH5 +#define ADC2_PF1_CH10 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 + +#define CAN_MODULE_1 (1) + +#define CAN_MODULE_COUNT (1) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (6) +#define DMA_NUM_OF_STREAMS_FAMILY (6) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) + +#define UART_MODULE_COUNT (3) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_SCK_PB3_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_ETR_PB3_AF10 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_8 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC11_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC4_CN +#define __PC6_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G441KB/LQFP32/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G441KB/LQFP32/mcu_definitions.h new file mode 100644 index 000000000..ca5c826a0 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G441KB/LQFP32/mcu_definitions.h @@ -0,0 +1,300 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G441KB_LQFP32. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PF1_CH10 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_TX_PA12_AF9 + +#define CAN_MODULE_1 (1) + +#define CAN_MODULE_COUNT (1) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (6) +#define DMA_NUM_OF_STREAMS_FAMILY (6) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SDA_PB5_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_TX_PA2_AF12 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (2) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_SCK_PB3_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH2_PA3_AF9 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_ETR_PA12_AF11 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_ETR_PB3_AF10 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_8 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (4) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G441KB/UFQFPN32/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G441KB/UFQFPN32/mcu_definitions.h new file mode 100644 index 000000000..782d80f10 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G441KB/UFQFPN32/mcu_definitions.h @@ -0,0 +1,300 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G441KB_UFQFPN32. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PF1_CH10 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_TX_PA12_AF9 + +#define CAN_MODULE_1 (1) + +#define CAN_MODULE_COUNT (1) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (6) +#define DMA_NUM_OF_STREAMS_FAMILY (6) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SDA_PB5_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_TX_PA2_AF12 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (2) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_SCK_PB3_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH2_PA3_AF9 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_ETR_PA12_AF11 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_ETR_PB3_AF10 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_8 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (4) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G441MB/LQFP80/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G441MB/LQFP80/mcu_definitions.h new file mode 100644 index 000000000..b806261c4 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G441MB/LQFP80/mcu_definitions.h @@ -0,0 +1,454 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G441MB_LQFP80. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_RX_PD0_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN1_TX_PD1_AF9 + +#define CAN_MODULE_1 (1) + +#define CAN_MODULE_COUNT (1) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (6) +#define DMA_NUM_OF_STREAMS_FAMILY (6) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PD9_AF7 +#define USART3_RX_PE15_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PD8_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (4) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN2_PE14_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_BKIN_PE15_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1N_PE8_AF2 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH1_PE9_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2N_PE10_AF2 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH2_PE11_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PE12_AF2 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH3_PE13_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4N_PE15_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_CH4_PE14_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM1_ETR_PE7_AF2 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN2_PD1_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4N_PD0_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_CH4_PD1_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_8 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD2_CN +#define __PD8_CN +#define __PD9_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (7) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G441RB/LQFP64/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G441RB/LQFP64/mcu_definitions.h new file mode 100644 index 000000000..17cb6f764 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G441RB/LQFP64/mcu_definitions.h @@ -0,0 +1,420 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G441RB_LQFP64. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 + +#define CAN_MODULE_1 (1) + +#define CAN_MODULE_COUNT (1) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (6) +#define DMA_NUM_OF_STREAMS_FAMILY (6) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (4) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_8 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD2_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (6) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G441RB/UFBGA64/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G441RB/UFBGA64/mcu_definitions.h new file mode 100644 index 000000000..a72723407 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G441RB/UFBGA64/mcu_definitions.h @@ -0,0 +1,420 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G441RB_UFBGA64. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 + +#define CAN_MODULE_1 (1) + +#define CAN_MODULE_COUNT (1) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (6) +#define DMA_NUM_OF_STREAMS_FAMILY (6) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (4) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_8 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD2_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (6) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G441VB/LQFP100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G441VB/LQFP100/mcu_definitions.h new file mode 100644 index 000000000..18972176d --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G441VB/LQFP100/mcu_definitions.h @@ -0,0 +1,498 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G441VB_LQFP100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_RX_PD0_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN1_TX_PD1_AF9 + +#define CAN_MODULE_1 (1) + +#define CAN_MODULE_COUNT (1) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (6) +#define DMA_NUM_OF_STREAMS_FAMILY (6) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_RX_PE1_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART1_TX_PE0_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_RX_PD6_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART2_TX_PD5_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PD9_AF7 +#define USART3_RX_PE15_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PD8_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (4) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF10_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI2_SCK_PF9_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH1_PF9_AF3 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM15_CH2_PF10_AF3 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM16_CH1_PE0_AF4 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM17_CH1_PE1_AF4 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN2_PE14_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_BKIN_PE15_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1N_PE8_AF2 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH1_PE9_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2N_PE10_AF2 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH2_PE11_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PE12_AF2 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH3_PE13_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4N_PE15_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_CH4_PE14_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM1_ETR_PE7_AF2 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH1_PD3_AF2 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH2_PD4_AF2 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH3_PD7_AF2 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_CH4_PD6_AF2 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM2_ETR_PD3_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH1_PE2_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH2_PE3_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH3_PE4_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_CH4_PE5_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH1_PD12_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH2_PD13_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH3_PD14_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_CH4_PD15_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM4_ETR_PE0_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN2_PD1_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4N_PD0_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_CH4_PD1_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_8 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) + +#define TIM_MODULE_COUNT (8) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PE0_CN +#define __PE1_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN +#define __PE6_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PF10_CN +#define __PF2_CN +#define __PF9_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (7) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473CB/LQFP48/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473CB/LQFP48/mcu_definitions.h new file mode 100644 index 000000000..4acf05623 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473CB/LQFP48/mcu_definitions.h @@ -0,0 +1,391 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G473CB_LQFP48. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 +#define ADC4_PB12_CH3 +#define ADC4_PB14_CH4 +#define ADC4_PB15_CH5 +#define ADC5_PA8_CH1 +#define ADC5_PA9_CH2 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) +#define ADC_MODULE_4 (4) +#define ADC_MODULE_5 (5) + +#define ADC_MODULE_COUNT (5) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 +#define FDCAN3_RX_PA8_AF11 +#define FDCAN3_RX_PB3_AF11 +#define FDCAN3_TX_PA15_AF11 +#define FDCAN3_TX_PB4_AF11 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) +#define CAN_MODULE_3 (3) + +#define CAN_MODULE_COUNT (3) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +#define HAL_LL_FDCAN3_GPIO_AF11 (11) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SDA_PB5_AF8 +#define I2C4_SCL_PA13_AF3 +#define I2C4_SDA_PB7_AF3 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) + +#define UART_MODULE_COUNT (3) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_SCK_PB3_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_ETR_PA12_AF11 +#define TIM20_CH1_PB2_AF3 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_ETR_PB3_AF10 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH1_PB2_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH4_PA3_AF2 +#define TIM5_ETR_PB12_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) +#define TIM_MODULE_20 (10) + +#define TIM_MODULE_COUNT (10) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473CB/UFQFPN48/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473CB/UFQFPN48/mcu_definitions.h new file mode 100644 index 000000000..0672ca1aa --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473CB/UFQFPN48/mcu_definitions.h @@ -0,0 +1,414 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G473CB_UFQFPN48. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC4_CH5 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 +#define ADC4_PB12_CH3 +#define ADC4_PB14_CH4 +#define ADC4_PB15_CH5 +#define ADC5_PA8_CH1 +#define ADC5_PA9_CH2 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) +#define ADC_MODULE_4 (4) +#define ADC_MODULE_5 (5) + +#define ADC_MODULE_COUNT (5) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 +#define FDCAN3_RX_PA8_AF11 +#define FDCAN3_RX_PB3_AF11 +#define FDCAN3_TX_PA15_AF11 +#define FDCAN3_TX_PB4_AF11 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) +#define CAN_MODULE_3 (3) + +#define CAN_MODULE_COUNT (3) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +#define HAL_LL_FDCAN3_GPIO_AF11 (11) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C4_SCL_PA13_AF3 +#define I2C4_SCL_PC6_AF8 +#define I2C4_SDA_PB7_AF3 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (4) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM20_CH1_PB2_AF3 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_ETR_PB3_AF10 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH1_PB2_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH4_PA3_AF2 +#define TIM5_ETR_PB12_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) +#define TIM_MODULE_20 (10) + +#define TIM_MODULE_COUNT (10) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC10_CN +#define __PC11_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC4_CN +#define __PC6_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473CC/LQFP48/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473CC/LQFP48/mcu_definitions.h new file mode 100644 index 000000000..6446444bd --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473CC/LQFP48/mcu_definitions.h @@ -0,0 +1,391 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G473CC_LQFP48. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 +#define ADC4_PB12_CH3 +#define ADC4_PB14_CH4 +#define ADC4_PB15_CH5 +#define ADC5_PA8_CH1 +#define ADC5_PA9_CH2 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) +#define ADC_MODULE_4 (4) +#define ADC_MODULE_5 (5) + +#define ADC_MODULE_COUNT (5) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 +#define FDCAN3_RX_PA8_AF11 +#define FDCAN3_RX_PB3_AF11 +#define FDCAN3_TX_PA15_AF11 +#define FDCAN3_TX_PB4_AF11 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) +#define CAN_MODULE_3 (3) + +#define CAN_MODULE_COUNT (3) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +#define HAL_LL_FDCAN3_GPIO_AF11 (11) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SDA_PB5_AF8 +#define I2C4_SCL_PA13_AF3 +#define I2C4_SDA_PB7_AF3 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) + +#define UART_MODULE_COUNT (3) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_SCK_PB3_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_ETR_PA12_AF11 +#define TIM20_CH1_PB2_AF3 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_ETR_PB3_AF10 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH1_PB2_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH4_PA3_AF2 +#define TIM5_ETR_PB12_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) +#define TIM_MODULE_20 (10) + +#define TIM_MODULE_COUNT (10) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473CC/UFQFPN48/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473CC/UFQFPN48/mcu_definitions.h new file mode 100644 index 000000000..b9153a9f4 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473CC/UFQFPN48/mcu_definitions.h @@ -0,0 +1,414 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G473CC_UFQFPN48. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC4_CH5 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 +#define ADC4_PB12_CH3 +#define ADC4_PB14_CH4 +#define ADC4_PB15_CH5 +#define ADC5_PA8_CH1 +#define ADC5_PA9_CH2 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) +#define ADC_MODULE_4 (4) +#define ADC_MODULE_5 (5) + +#define ADC_MODULE_COUNT (5) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 +#define FDCAN3_RX_PA8_AF11 +#define FDCAN3_RX_PB3_AF11 +#define FDCAN3_TX_PA15_AF11 +#define FDCAN3_TX_PB4_AF11 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) +#define CAN_MODULE_3 (3) + +#define CAN_MODULE_COUNT (3) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +#define HAL_LL_FDCAN3_GPIO_AF11 (11) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C4_SCL_PA13_AF3 +#define I2C4_SCL_PC6_AF8 +#define I2C4_SDA_PB7_AF3 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (4) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM20_CH1_PB2_AF3 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_ETR_PB3_AF10 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH1_PB2_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH4_PA3_AF2 +#define TIM5_ETR_PB12_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) +#define TIM_MODULE_20 (10) + +#define TIM_MODULE_COUNT (10) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC10_CN +#define __PC11_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC4_CN +#define __PC6_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473CE/LQFP48/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473CE/LQFP48/mcu_definitions.h new file mode 100644 index 000000000..d2320c827 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473CE/LQFP48/mcu_definitions.h @@ -0,0 +1,391 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G473CE_LQFP48. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 +#define ADC4_PB12_CH3 +#define ADC4_PB14_CH4 +#define ADC4_PB15_CH5 +#define ADC5_PA8_CH1 +#define ADC5_PA9_CH2 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) +#define ADC_MODULE_4 (4) +#define ADC_MODULE_5 (5) + +#define ADC_MODULE_COUNT (5) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 +#define FDCAN3_RX_PA8_AF11 +#define FDCAN3_RX_PB3_AF11 +#define FDCAN3_TX_PA15_AF11 +#define FDCAN3_TX_PB4_AF11 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) +#define CAN_MODULE_3 (3) + +#define CAN_MODULE_COUNT (3) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +#define HAL_LL_FDCAN3_GPIO_AF11 (11) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SDA_PB5_AF8 +#define I2C4_SCL_PA13_AF3 +#define I2C4_SDA_PB7_AF3 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) + +#define UART_MODULE_COUNT (3) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_SCK_PB3_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_ETR_PA12_AF11 +#define TIM20_CH1_PB2_AF3 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_ETR_PB3_AF10 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH1_PB2_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH4_PA3_AF2 +#define TIM5_ETR_PB12_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) +#define TIM_MODULE_20 (10) + +#define TIM_MODULE_COUNT (10) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473CE/UFQFPN48/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473CE/UFQFPN48/mcu_definitions.h new file mode 100644 index 000000000..ae6ef9840 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473CE/UFQFPN48/mcu_definitions.h @@ -0,0 +1,414 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G473CE_UFQFPN48. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC4_CH5 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 +#define ADC4_PB12_CH3 +#define ADC4_PB14_CH4 +#define ADC4_PB15_CH5 +#define ADC5_PA8_CH1 +#define ADC5_PA9_CH2 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) +#define ADC_MODULE_4 (4) +#define ADC_MODULE_5 (5) + +#define ADC_MODULE_COUNT (5) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 +#define FDCAN3_RX_PA8_AF11 +#define FDCAN3_RX_PB3_AF11 +#define FDCAN3_TX_PA15_AF11 +#define FDCAN3_TX_PB4_AF11 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) +#define CAN_MODULE_3 (3) + +#define CAN_MODULE_COUNT (3) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +#define HAL_LL_FDCAN3_GPIO_AF11 (11) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C4_SCL_PA13_AF3 +#define I2C4_SCL_PC6_AF8 +#define I2C4_SDA_PB7_AF3 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (4) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM20_CH1_PB2_AF3 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_ETR_PB3_AF10 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH1_PB2_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH4_PA3_AF2 +#define TIM5_ETR_PB12_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) +#define TIM_MODULE_20 (10) + +#define TIM_MODULE_COUNT (10) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC10_CN +#define __PC11_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC4_CN +#define __PC6_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473MB/LQFP80/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473MB/LQFP80/mcu_definitions.h new file mode 100644 index 000000000..c02f3b8fe --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473MB/LQFP80/mcu_definitions.h @@ -0,0 +1,531 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G473MB_LQFP80. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 +#define ADC3_PD10_CH7 +#define ADC3_PE10_CH14 +#define ADC3_PE11_CH15 +#define ADC3_PE12_CH16 +#define ADC3_PE13_CH3 +#define ADC3_PE7_CH4 +#define ADC3_PE8_CH6 +#define ADC3_PE9_CH2 +#define ADC4_PB12_CH3 +#define ADC4_PB14_CH4 +#define ADC4_PB15_CH5 +#define ADC4_PD10_CH7 +#define ADC4_PD8_CH12 +#define ADC4_PD9_CH13 +#define ADC4_PE10_CH14 +#define ADC4_PE11_CH15 +#define ADC4_PE12_CH16 +#define ADC4_PE14_CH1 +#define ADC4_PE15_CH2 +#define ADC4_PE8_CH6 +#define ADC5_PA8_CH1 +#define ADC5_PA9_CH2 +#define ADC5_PD10_CH7 +#define ADC5_PD8_CH12 +#define ADC5_PD9_CH13 +#define ADC5_PE10_CH14 +#define ADC5_PE11_CH15 +#define ADC5_PE12_CH16 +#define ADC5_PE8_CH6 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) +#define ADC_MODULE_4 (4) +#define ADC_MODULE_5 (5) + +#define ADC_MODULE_COUNT (5) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_RX_PD0_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN1_TX_PD1_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 +#define FDCAN3_RX_PA8_AF11 +#define FDCAN3_RX_PB3_AF11 +#define FDCAN3_TX_PA15_AF11 +#define FDCAN3_TX_PB4_AF11 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) +#define CAN_MODULE_3 (3) + +#define CAN_MODULE_COUNT (3) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +#define HAL_LL_FDCAN3_GPIO_AF11 (11) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 +#define I2C4_SCL_PA13_AF3 +#define I2C4_SCL_PC6_AF8 +#define I2C4_SDA_PB7_AF3 +#define I2C4_SDA_PC7_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define UART5_RX_PD2_AF5 +#define UART5_TX_PC12_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PD9_AF7 +#define USART3_RX_PE15_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PD8_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 +#define SPI4_MISO_PE13_AF5 +#define SPI4_MOSI_PE14_AF5 +#define SPI4_SCK_PE12_AF5 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) +#define SPI_MODULE_4 (4) + +#define SPI_MODULE_COUNT (4) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN2_PE14_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_BKIN_PE15_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1N_PE8_AF2 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH1_PE9_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2N_PE10_AF2 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH2_PE11_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PE12_AF2 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH3_PE13_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4N_PE15_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_CH4_PE14_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM1_ETR_PE7_AF2 +#define TIM20_CH1_PB2_AF3 +#define TIM20_CH2_PC2_AF6 +#define TIM20_CH3_PC8_AF6 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH1_PB2_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH2_PC12_AF1 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH3_PE8_AF1 +#define TIM5_CH4_PA3_AF2 +#define TIM5_CH4_PE9_AF1 +#define TIM5_ETR_PB12_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN2_PD1_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4N_PD0_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_CH4_PD1_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) +#define TIM_MODULE_20 (10) + +#define TIM_MODULE_COUNT (10) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD2_CN +#define __PD8_CN +#define __PD9_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (7) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473MC/LQFP80/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473MC/LQFP80/mcu_definitions.h new file mode 100644 index 000000000..d3d7a64b6 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473MC/LQFP80/mcu_definitions.h @@ -0,0 +1,531 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G473MC_LQFP80. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 +#define ADC3_PD10_CH7 +#define ADC3_PE10_CH14 +#define ADC3_PE11_CH15 +#define ADC3_PE12_CH16 +#define ADC3_PE13_CH3 +#define ADC3_PE7_CH4 +#define ADC3_PE8_CH6 +#define ADC3_PE9_CH2 +#define ADC4_PB12_CH3 +#define ADC4_PB14_CH4 +#define ADC4_PB15_CH5 +#define ADC4_PD10_CH7 +#define ADC4_PD8_CH12 +#define ADC4_PD9_CH13 +#define ADC4_PE10_CH14 +#define ADC4_PE11_CH15 +#define ADC4_PE12_CH16 +#define ADC4_PE14_CH1 +#define ADC4_PE15_CH2 +#define ADC4_PE8_CH6 +#define ADC5_PA8_CH1 +#define ADC5_PA9_CH2 +#define ADC5_PD10_CH7 +#define ADC5_PD8_CH12 +#define ADC5_PD9_CH13 +#define ADC5_PE10_CH14 +#define ADC5_PE11_CH15 +#define ADC5_PE12_CH16 +#define ADC5_PE8_CH6 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) +#define ADC_MODULE_4 (4) +#define ADC_MODULE_5 (5) + +#define ADC_MODULE_COUNT (5) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_RX_PD0_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN1_TX_PD1_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 +#define FDCAN3_RX_PA8_AF11 +#define FDCAN3_RX_PB3_AF11 +#define FDCAN3_TX_PA15_AF11 +#define FDCAN3_TX_PB4_AF11 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) +#define CAN_MODULE_3 (3) + +#define CAN_MODULE_COUNT (3) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +#define HAL_LL_FDCAN3_GPIO_AF11 (11) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 +#define I2C4_SCL_PA13_AF3 +#define I2C4_SCL_PC6_AF8 +#define I2C4_SDA_PB7_AF3 +#define I2C4_SDA_PC7_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define UART5_RX_PD2_AF5 +#define UART5_TX_PC12_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PD9_AF7 +#define USART3_RX_PE15_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PD8_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 +#define SPI4_MISO_PE13_AF5 +#define SPI4_MOSI_PE14_AF5 +#define SPI4_SCK_PE12_AF5 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) +#define SPI_MODULE_4 (4) + +#define SPI_MODULE_COUNT (4) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN2_PE14_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_BKIN_PE15_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1N_PE8_AF2 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH1_PE9_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2N_PE10_AF2 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH2_PE11_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PE12_AF2 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH3_PE13_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4N_PE15_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_CH4_PE14_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM1_ETR_PE7_AF2 +#define TIM20_CH1_PB2_AF3 +#define TIM20_CH2_PC2_AF6 +#define TIM20_CH3_PC8_AF6 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH1_PB2_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH2_PC12_AF1 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH3_PE8_AF1 +#define TIM5_CH4_PA3_AF2 +#define TIM5_CH4_PE9_AF1 +#define TIM5_ETR_PB12_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN2_PD1_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4N_PD0_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_CH4_PD1_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) +#define TIM_MODULE_20 (10) + +#define TIM_MODULE_COUNT (10) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD2_CN +#define __PD8_CN +#define __PD9_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (7) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473ME/LQFP80/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473ME/LQFP80/mcu_definitions.h new file mode 100644 index 000000000..409ff8ba7 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473ME/LQFP80/mcu_definitions.h @@ -0,0 +1,531 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G473ME_LQFP80. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 +#define ADC3_PD10_CH7 +#define ADC3_PE10_CH14 +#define ADC3_PE11_CH15 +#define ADC3_PE12_CH16 +#define ADC3_PE13_CH3 +#define ADC3_PE7_CH4 +#define ADC3_PE8_CH6 +#define ADC3_PE9_CH2 +#define ADC4_PB12_CH3 +#define ADC4_PB14_CH4 +#define ADC4_PB15_CH5 +#define ADC4_PD10_CH7 +#define ADC4_PD8_CH12 +#define ADC4_PD9_CH13 +#define ADC4_PE10_CH14 +#define ADC4_PE11_CH15 +#define ADC4_PE12_CH16 +#define ADC4_PE14_CH1 +#define ADC4_PE15_CH2 +#define ADC4_PE8_CH6 +#define ADC5_PA8_CH1 +#define ADC5_PA9_CH2 +#define ADC5_PD10_CH7 +#define ADC5_PD8_CH12 +#define ADC5_PD9_CH13 +#define ADC5_PE10_CH14 +#define ADC5_PE11_CH15 +#define ADC5_PE12_CH16 +#define ADC5_PE8_CH6 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) +#define ADC_MODULE_4 (4) +#define ADC_MODULE_5 (5) + +#define ADC_MODULE_COUNT (5) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_RX_PD0_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN1_TX_PD1_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 +#define FDCAN3_RX_PA8_AF11 +#define FDCAN3_RX_PB3_AF11 +#define FDCAN3_TX_PA15_AF11 +#define FDCAN3_TX_PB4_AF11 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) +#define CAN_MODULE_3 (3) + +#define CAN_MODULE_COUNT (3) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +#define HAL_LL_FDCAN3_GPIO_AF11 (11) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 +#define I2C4_SCL_PA13_AF3 +#define I2C4_SCL_PC6_AF8 +#define I2C4_SDA_PB7_AF3 +#define I2C4_SDA_PC7_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define UART5_RX_PD2_AF5 +#define UART5_TX_PC12_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PD9_AF7 +#define USART3_RX_PE15_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PD8_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 +#define SPI4_MISO_PE13_AF5 +#define SPI4_MOSI_PE14_AF5 +#define SPI4_SCK_PE12_AF5 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) +#define SPI_MODULE_4 (4) + +#define SPI_MODULE_COUNT (4) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN2_PE14_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_BKIN_PE15_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1N_PE8_AF2 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH1_PE9_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2N_PE10_AF2 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH2_PE11_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PE12_AF2 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH3_PE13_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4N_PE15_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_CH4_PE14_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM1_ETR_PE7_AF2 +#define TIM20_CH1_PB2_AF3 +#define TIM20_CH2_PC2_AF6 +#define TIM20_CH3_PC8_AF6 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH1_PB2_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH2_PC12_AF1 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH3_PE8_AF1 +#define TIM5_CH4_PA3_AF2 +#define TIM5_CH4_PE9_AF1 +#define TIM5_ETR_PB12_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN2_PD1_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4N_PD0_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_CH4_PD1_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) +#define TIM_MODULE_20 (10) + +#define TIM_MODULE_COUNT (10) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD2_CN +#define __PD8_CN +#define __PD9_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (7) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473ME/WLCSP81/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473ME/WLCSP81/mcu_definitions.h new file mode 100644 index 000000000..f59610ef2 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473ME/WLCSP81/mcu_definitions.h @@ -0,0 +1,536 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G473ME_WLCSP81. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 +#define ADC3_PD10_CH7 +#define ADC3_PD11_CH8 +#define ADC3_PE10_CH14 +#define ADC3_PE11_CH15 +#define ADC3_PE12_CH16 +#define ADC3_PE13_CH3 +#define ADC3_PE7_CH4 +#define ADC3_PE8_CH6 +#define ADC3_PE9_CH2 +#define ADC4_PB12_CH3 +#define ADC4_PB14_CH4 +#define ADC4_PB15_CH5 +#define ADC4_PD10_CH7 +#define ADC4_PD11_CH8 +#define ADC4_PD8_CH12 +#define ADC4_PD9_CH13 +#define ADC4_PE10_CH14 +#define ADC4_PE11_CH15 +#define ADC4_PE12_CH16 +#define ADC4_PE14_CH1 +#define ADC4_PE15_CH2 +#define ADC4_PE8_CH6 +#define ADC5_PA8_CH1 +#define ADC5_PA9_CH2 +#define ADC5_PD10_CH7 +#define ADC5_PD11_CH8 +#define ADC5_PD8_CH12 +#define ADC5_PD9_CH13 +#define ADC5_PE10_CH14 +#define ADC5_PE11_CH15 +#define ADC5_PE12_CH16 +#define ADC5_PE8_CH6 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) +#define ADC_MODULE_4 (4) +#define ADC_MODULE_5 (5) + +#define ADC_MODULE_COUNT (5) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_RX_PD0_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN1_TX_PD1_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 +#define FDCAN3_RX_PA8_AF11 +#define FDCAN3_RX_PB3_AF11 +#define FDCAN3_TX_PA15_AF11 +#define FDCAN3_TX_PB4_AF11 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) +#define CAN_MODULE_3 (3) + +#define CAN_MODULE_COUNT (3) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +#define HAL_LL_FDCAN3_GPIO_AF11 (11) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 +#define I2C4_SCL_PA13_AF3 +#define I2C4_SCL_PC6_AF8 +#define I2C4_SDA_PB7_AF3 +#define I2C4_SDA_PC7_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define UART5_RX_PD2_AF5 +#define UART5_TX_PC12_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PD9_AF7 +#define USART3_RX_PE15_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PD8_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 +#define SPI4_MISO_PE13_AF5 +#define SPI4_MOSI_PE14_AF5 +#define SPI4_SCK_PE12_AF5 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) +#define SPI_MODULE_4 (4) + +#define SPI_MODULE_COUNT (4) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN2_PE14_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_BKIN_PE15_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1N_PE8_AF2 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH1_PE9_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2N_PE10_AF2 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH2_PE11_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PE12_AF2 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH3_PE13_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4N_PE15_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_CH4_PE14_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM1_ETR_PE7_AF2 +#define TIM20_CH1_PB2_AF3 +#define TIM20_CH2_PC2_AF6 +#define TIM20_CH3_PC8_AF6 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH1_PB2_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH2_PC12_AF1 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH3_PE8_AF1 +#define TIM5_CH4_PA3_AF2 +#define TIM5_CH4_PE9_AF1 +#define TIM5_ETR_PB12_AF2 +#define TIM5_ETR_PD11_AF1 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN2_PD1_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4N_PD0_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_CH4_PD1_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) +#define TIM_MODULE_20 (10) + +#define TIM_MODULE_COUNT (10) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD11_CN +#define __PD2_CN +#define __PD8_CN +#define __PD9_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (7) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473PB/UFBGA121/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473PB/UFBGA121/mcu_definitions.h new file mode 100644 index 000000000..fcd2a9aa8 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473PB/UFBGA121/mcu_definitions.h @@ -0,0 +1,650 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G473PB_UFBGA121. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 +#define ADC3_PD10_CH7 +#define ADC3_PD11_CH8 +#define ADC3_PD12_CH9 +#define ADC3_PD13_CH10 +#define ADC3_PD14_CH11 +#define ADC3_PE10_CH14 +#define ADC3_PE11_CH15 +#define ADC3_PE12_CH16 +#define ADC3_PE13_CH3 +#define ADC3_PE7_CH4 +#define ADC3_PE8_CH6 +#define ADC3_PE9_CH2 +#define ADC4_PB12_CH3 +#define ADC4_PB14_CH4 +#define ADC4_PB15_CH5 +#define ADC4_PD10_CH7 +#define ADC4_PD11_CH8 +#define ADC4_PD12_CH9 +#define ADC4_PD13_CH10 +#define ADC4_PD14_CH11 +#define ADC4_PD8_CH12 +#define ADC4_PD9_CH13 +#define ADC4_PE10_CH14 +#define ADC4_PE11_CH15 +#define ADC4_PE12_CH16 +#define ADC4_PE14_CH1 +#define ADC4_PE15_CH2 +#define ADC4_PE8_CH6 +#define ADC5_PA8_CH1 +#define ADC5_PA9_CH2 +#define ADC5_PD10_CH7 +#define ADC5_PD11_CH8 +#define ADC5_PD12_CH9 +#define ADC5_PD13_CH10 +#define ADC5_PD14_CH11 +#define ADC5_PD8_CH12 +#define ADC5_PD9_CH13 +#define ADC5_PE10_CH14 +#define ADC5_PE11_CH15 +#define ADC5_PE12_CH16 +#define ADC5_PE8_CH6 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) +#define ADC_MODULE_4 (4) +#define ADC_MODULE_5 (5) + +#define ADC_MODULE_COUNT (5) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_RX_PD0_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN1_TX_PD1_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 +#define FDCAN3_RX_PA8_AF11 +#define FDCAN3_RX_PB3_AF11 +#define FDCAN3_TX_PA15_AF11 +#define FDCAN3_TX_PB4_AF11 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) +#define CAN_MODULE_3 (3) + +#define CAN_MODULE_COUNT (3) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +#define HAL_LL_FDCAN3_GPIO_AF11 (11) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SCL_PF6_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SCL_PF3_AF4 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 +#define I2C3_SDA_PF4_AF4 +#define I2C4_SCL_PA13_AF3 +#define I2C4_SCL_PC6_AF8 +#define I2C4_SCL_PF14_AF4 +#define I2C4_SCL_PG3_AF4 +#define I2C4_SDA_PB7_AF3 +#define I2C4_SDA_PC7_AF8 +#define I2C4_SDA_PF15_AF4 +#define I2C4_SDA_PG4_AF4 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define UART5_RX_PD2_AF5 +#define UART5_TX_PC12_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_RX_PE1_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART1_TX_PE0_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_RX_PD6_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART2_TX_PD5_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PD9_AF7 +#define USART3_RX_PE15_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PD8_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MISO_PG3_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_MOSI_PG4_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI1_SCK_PG2_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF10_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI2_SCK_PF9_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 +#define SPI4_MISO_PE13_AF5 +#define SPI4_MISO_PE5_AF5 +#define SPI4_MOSI_PE14_AF5 +#define SPI4_MOSI_PE6_AF5 +#define SPI4_SCK_PE12_AF5 +#define SPI4_SCK_PE2_AF5 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) +#define SPI_MODULE_4 (4) + +#define SPI_MODULE_COUNT (4) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH1_PF9_AF3 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM15_CH2_PF10_AF3 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM16_CH1_PE0_AF4 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM17_CH1_PE1_AF4 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN2_PE14_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_BKIN_PE15_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1N_PE8_AF2 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH1_PE9_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2N_PE10_AF2 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH2_PE11_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PE12_AF2 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH3_PE13_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4N_PE15_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_CH4_PE14_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM1_ETR_PE7_AF2 +#define TIM20_BKIN2_PF10_AF2 +#define TIM20_BKIN2_PF8_AF2 +#define TIM20_BKIN2_PG4_AF2 +#define TIM20_BKIN_PF7_AF2 +#define TIM20_BKIN_PF9_AF2 +#define TIM20_BKIN_PG3_AF2 +#define TIM20_CH1N_PE4_AF6 +#define TIM20_CH1N_PF4_AF3 +#define TIM20_CH1N_PG0_AF2 +#define TIM20_CH1_PB2_AF3 +#define TIM20_CH1_PE2_AF6 +#define TIM20_CH1_PF12_AF2 +#define TIM20_CH2N_PE5_AF6 +#define TIM20_CH2N_PF5_AF2 +#define TIM20_CH2N_PG1_AF2 +#define TIM20_CH2_PC2_AF6 +#define TIM20_CH2_PE3_AF6 +#define TIM20_CH2_PF13_AF2 +#define TIM20_CH3N_PE6_AF6 +#define TIM20_CH3N_PG2_AF2 +#define TIM20_CH3_PC8_AF6 +#define TIM20_CH3_PF14_AF2 +#define TIM20_CH3_PF2_AF2 +#define TIM20_CH4N_PE0_AF3 +#define TIM20_CH4N_PG3_AF6 +#define TIM20_CH4_PE1_AF6 +#define TIM20_CH4_PF15_AF2 +#define TIM20_CH4_PF3_AF2 +#define TIM20_ETR_PE0_AF6 +#define TIM20_ETR_PF11_AF2 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH1_PD3_AF2 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH2_PD4_AF2 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH3_PD7_AF2 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_CH4_PD6_AF2 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM2_ETR_PD3_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH1_PE2_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH2_PE3_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH3_PE4_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_CH4_PE5_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH1_PD12_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH2_PD13_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH3_PD14_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_CH4_PD15_AF2 +#define TIM4_CH4_PF6_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM4_ETR_PE0_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH1_PB2_AF2 +#define TIM5_CH1_PF6_AF6 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH2_PC12_AF1 +#define TIM5_CH2_PF7_AF6 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH3_PE8_AF1 +#define TIM5_CH3_PF8_AF6 +#define TIM5_CH4_PA3_AF2 +#define TIM5_CH4_PE9_AF1 +#define TIM5_CH4_PF9_AF6 +#define TIM5_ETR_PB12_AF2 +#define TIM5_ETR_PD11_AF1 +#define TIM5_ETR_PF6_AF1 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN2_PD1_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4N_PD0_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_CH4_PD1_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) +#define TIM_MODULE_20 (10) + +#define TIM_MODULE_COUNT (10) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PE0_CN +#define __PE1_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN +#define __PE6_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PF10_CN +#define __PF11_CN +#define __PF12_CN +#define __PF13_CN +#define __PF14_CN +#define __PF15_CN +#define __PF2_CN +#define __PF3_CN +#define __PF4_CN +#define __PF5_CN +#define __PF6_CN +#define __PF7_CN +#define __PF8_CN +#define __PF9_CN +#define __PG0_CN +#define __PG1_CN +#define __PG10_CN +#define __PG2_CN +#define __PG3_CN +#define __PG4_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (7) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473PC/UFBGA121/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473PC/UFBGA121/mcu_definitions.h new file mode 100644 index 000000000..51c2b712e --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473PC/UFBGA121/mcu_definitions.h @@ -0,0 +1,650 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G473PC_UFBGA121. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 +#define ADC3_PD10_CH7 +#define ADC3_PD11_CH8 +#define ADC3_PD12_CH9 +#define ADC3_PD13_CH10 +#define ADC3_PD14_CH11 +#define ADC3_PE10_CH14 +#define ADC3_PE11_CH15 +#define ADC3_PE12_CH16 +#define ADC3_PE13_CH3 +#define ADC3_PE7_CH4 +#define ADC3_PE8_CH6 +#define ADC3_PE9_CH2 +#define ADC4_PB12_CH3 +#define ADC4_PB14_CH4 +#define ADC4_PB15_CH5 +#define ADC4_PD10_CH7 +#define ADC4_PD11_CH8 +#define ADC4_PD12_CH9 +#define ADC4_PD13_CH10 +#define ADC4_PD14_CH11 +#define ADC4_PD8_CH12 +#define ADC4_PD9_CH13 +#define ADC4_PE10_CH14 +#define ADC4_PE11_CH15 +#define ADC4_PE12_CH16 +#define ADC4_PE14_CH1 +#define ADC4_PE15_CH2 +#define ADC4_PE8_CH6 +#define ADC5_PA8_CH1 +#define ADC5_PA9_CH2 +#define ADC5_PD10_CH7 +#define ADC5_PD11_CH8 +#define ADC5_PD12_CH9 +#define ADC5_PD13_CH10 +#define ADC5_PD14_CH11 +#define ADC5_PD8_CH12 +#define ADC5_PD9_CH13 +#define ADC5_PE10_CH14 +#define ADC5_PE11_CH15 +#define ADC5_PE12_CH16 +#define ADC5_PE8_CH6 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) +#define ADC_MODULE_4 (4) +#define ADC_MODULE_5 (5) + +#define ADC_MODULE_COUNT (5) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_RX_PD0_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN1_TX_PD1_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 +#define FDCAN3_RX_PA8_AF11 +#define FDCAN3_RX_PB3_AF11 +#define FDCAN3_TX_PA15_AF11 +#define FDCAN3_TX_PB4_AF11 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) +#define CAN_MODULE_3 (3) + +#define CAN_MODULE_COUNT (3) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +#define HAL_LL_FDCAN3_GPIO_AF11 (11) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SCL_PF6_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SCL_PF3_AF4 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 +#define I2C3_SDA_PF4_AF4 +#define I2C4_SCL_PA13_AF3 +#define I2C4_SCL_PC6_AF8 +#define I2C4_SCL_PF14_AF4 +#define I2C4_SCL_PG3_AF4 +#define I2C4_SDA_PB7_AF3 +#define I2C4_SDA_PC7_AF8 +#define I2C4_SDA_PF15_AF4 +#define I2C4_SDA_PG4_AF4 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define UART5_RX_PD2_AF5 +#define UART5_TX_PC12_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_RX_PE1_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART1_TX_PE0_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_RX_PD6_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART2_TX_PD5_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PD9_AF7 +#define USART3_RX_PE15_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PD8_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MISO_PG3_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_MOSI_PG4_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI1_SCK_PG2_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF10_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI2_SCK_PF9_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 +#define SPI4_MISO_PE13_AF5 +#define SPI4_MISO_PE5_AF5 +#define SPI4_MOSI_PE14_AF5 +#define SPI4_MOSI_PE6_AF5 +#define SPI4_SCK_PE12_AF5 +#define SPI4_SCK_PE2_AF5 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) +#define SPI_MODULE_4 (4) + +#define SPI_MODULE_COUNT (4) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH1_PF9_AF3 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM15_CH2_PF10_AF3 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM16_CH1_PE0_AF4 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM17_CH1_PE1_AF4 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN2_PE14_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_BKIN_PE15_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1N_PE8_AF2 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH1_PE9_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2N_PE10_AF2 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH2_PE11_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PE12_AF2 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH3_PE13_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4N_PE15_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_CH4_PE14_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM1_ETR_PE7_AF2 +#define TIM20_BKIN2_PF10_AF2 +#define TIM20_BKIN2_PF8_AF2 +#define TIM20_BKIN2_PG4_AF2 +#define TIM20_BKIN_PF7_AF2 +#define TIM20_BKIN_PF9_AF2 +#define TIM20_BKIN_PG3_AF2 +#define TIM20_CH1N_PE4_AF6 +#define TIM20_CH1N_PF4_AF3 +#define TIM20_CH1N_PG0_AF2 +#define TIM20_CH1_PB2_AF3 +#define TIM20_CH1_PE2_AF6 +#define TIM20_CH1_PF12_AF2 +#define TIM20_CH2N_PE5_AF6 +#define TIM20_CH2N_PF5_AF2 +#define TIM20_CH2N_PG1_AF2 +#define TIM20_CH2_PC2_AF6 +#define TIM20_CH2_PE3_AF6 +#define TIM20_CH2_PF13_AF2 +#define TIM20_CH3N_PE6_AF6 +#define TIM20_CH3N_PG2_AF2 +#define TIM20_CH3_PC8_AF6 +#define TIM20_CH3_PF14_AF2 +#define TIM20_CH3_PF2_AF2 +#define TIM20_CH4N_PE0_AF3 +#define TIM20_CH4N_PG3_AF6 +#define TIM20_CH4_PE1_AF6 +#define TIM20_CH4_PF15_AF2 +#define TIM20_CH4_PF3_AF2 +#define TIM20_ETR_PE0_AF6 +#define TIM20_ETR_PF11_AF2 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH1_PD3_AF2 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH2_PD4_AF2 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH3_PD7_AF2 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_CH4_PD6_AF2 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM2_ETR_PD3_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH1_PE2_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH2_PE3_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH3_PE4_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_CH4_PE5_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH1_PD12_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH2_PD13_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH3_PD14_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_CH4_PD15_AF2 +#define TIM4_CH4_PF6_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM4_ETR_PE0_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH1_PB2_AF2 +#define TIM5_CH1_PF6_AF6 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH2_PC12_AF1 +#define TIM5_CH2_PF7_AF6 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH3_PE8_AF1 +#define TIM5_CH3_PF8_AF6 +#define TIM5_CH4_PA3_AF2 +#define TIM5_CH4_PE9_AF1 +#define TIM5_CH4_PF9_AF6 +#define TIM5_ETR_PB12_AF2 +#define TIM5_ETR_PD11_AF1 +#define TIM5_ETR_PF6_AF1 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN2_PD1_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4N_PD0_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_CH4_PD1_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) +#define TIM_MODULE_20 (10) + +#define TIM_MODULE_COUNT (10) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PE0_CN +#define __PE1_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN +#define __PE6_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PF10_CN +#define __PF11_CN +#define __PF12_CN +#define __PF13_CN +#define __PF14_CN +#define __PF15_CN +#define __PF2_CN +#define __PF3_CN +#define __PF4_CN +#define __PF5_CN +#define __PF6_CN +#define __PF7_CN +#define __PF8_CN +#define __PF9_CN +#define __PG0_CN +#define __PG1_CN +#define __PG10_CN +#define __PG2_CN +#define __PG3_CN +#define __PG4_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (7) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473PE/UFBGA121/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473PE/UFBGA121/mcu_definitions.h new file mode 100644 index 000000000..38e32a94a --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473PE/UFBGA121/mcu_definitions.h @@ -0,0 +1,650 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G473PE_UFBGA121. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 +#define ADC3_PD10_CH7 +#define ADC3_PD11_CH8 +#define ADC3_PD12_CH9 +#define ADC3_PD13_CH10 +#define ADC3_PD14_CH11 +#define ADC3_PE10_CH14 +#define ADC3_PE11_CH15 +#define ADC3_PE12_CH16 +#define ADC3_PE13_CH3 +#define ADC3_PE7_CH4 +#define ADC3_PE8_CH6 +#define ADC3_PE9_CH2 +#define ADC4_PB12_CH3 +#define ADC4_PB14_CH4 +#define ADC4_PB15_CH5 +#define ADC4_PD10_CH7 +#define ADC4_PD11_CH8 +#define ADC4_PD12_CH9 +#define ADC4_PD13_CH10 +#define ADC4_PD14_CH11 +#define ADC4_PD8_CH12 +#define ADC4_PD9_CH13 +#define ADC4_PE10_CH14 +#define ADC4_PE11_CH15 +#define ADC4_PE12_CH16 +#define ADC4_PE14_CH1 +#define ADC4_PE15_CH2 +#define ADC4_PE8_CH6 +#define ADC5_PA8_CH1 +#define ADC5_PA9_CH2 +#define ADC5_PD10_CH7 +#define ADC5_PD11_CH8 +#define ADC5_PD12_CH9 +#define ADC5_PD13_CH10 +#define ADC5_PD14_CH11 +#define ADC5_PD8_CH12 +#define ADC5_PD9_CH13 +#define ADC5_PE10_CH14 +#define ADC5_PE11_CH15 +#define ADC5_PE12_CH16 +#define ADC5_PE8_CH6 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) +#define ADC_MODULE_4 (4) +#define ADC_MODULE_5 (5) + +#define ADC_MODULE_COUNT (5) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_RX_PD0_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN1_TX_PD1_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 +#define FDCAN3_RX_PA8_AF11 +#define FDCAN3_RX_PB3_AF11 +#define FDCAN3_TX_PA15_AF11 +#define FDCAN3_TX_PB4_AF11 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) +#define CAN_MODULE_3 (3) + +#define CAN_MODULE_COUNT (3) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +#define HAL_LL_FDCAN3_GPIO_AF11 (11) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SCL_PF6_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SCL_PF3_AF4 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 +#define I2C3_SDA_PF4_AF4 +#define I2C4_SCL_PA13_AF3 +#define I2C4_SCL_PC6_AF8 +#define I2C4_SCL_PF14_AF4 +#define I2C4_SCL_PG3_AF4 +#define I2C4_SDA_PB7_AF3 +#define I2C4_SDA_PC7_AF8 +#define I2C4_SDA_PF15_AF4 +#define I2C4_SDA_PG4_AF4 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define UART5_RX_PD2_AF5 +#define UART5_TX_PC12_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_RX_PE1_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART1_TX_PE0_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_RX_PD6_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART2_TX_PD5_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PD9_AF7 +#define USART3_RX_PE15_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PD8_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MISO_PG3_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_MOSI_PG4_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI1_SCK_PG2_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF10_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI2_SCK_PF9_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 +#define SPI4_MISO_PE13_AF5 +#define SPI4_MISO_PE5_AF5 +#define SPI4_MOSI_PE14_AF5 +#define SPI4_MOSI_PE6_AF5 +#define SPI4_SCK_PE12_AF5 +#define SPI4_SCK_PE2_AF5 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) +#define SPI_MODULE_4 (4) + +#define SPI_MODULE_COUNT (4) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH1_PF9_AF3 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM15_CH2_PF10_AF3 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM16_CH1_PE0_AF4 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM17_CH1_PE1_AF4 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN2_PE14_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_BKIN_PE15_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1N_PE8_AF2 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH1_PE9_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2N_PE10_AF2 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH2_PE11_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PE12_AF2 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH3_PE13_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4N_PE15_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_CH4_PE14_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM1_ETR_PE7_AF2 +#define TIM20_BKIN2_PF10_AF2 +#define TIM20_BKIN2_PF8_AF2 +#define TIM20_BKIN2_PG4_AF2 +#define TIM20_BKIN_PF7_AF2 +#define TIM20_BKIN_PF9_AF2 +#define TIM20_BKIN_PG3_AF2 +#define TIM20_CH1N_PE4_AF6 +#define TIM20_CH1N_PF4_AF3 +#define TIM20_CH1N_PG0_AF2 +#define TIM20_CH1_PB2_AF3 +#define TIM20_CH1_PE2_AF6 +#define TIM20_CH1_PF12_AF2 +#define TIM20_CH2N_PE5_AF6 +#define TIM20_CH2N_PF5_AF2 +#define TIM20_CH2N_PG1_AF2 +#define TIM20_CH2_PC2_AF6 +#define TIM20_CH2_PE3_AF6 +#define TIM20_CH2_PF13_AF2 +#define TIM20_CH3N_PE6_AF6 +#define TIM20_CH3N_PG2_AF2 +#define TIM20_CH3_PC8_AF6 +#define TIM20_CH3_PF14_AF2 +#define TIM20_CH3_PF2_AF2 +#define TIM20_CH4N_PE0_AF3 +#define TIM20_CH4N_PG3_AF6 +#define TIM20_CH4_PE1_AF6 +#define TIM20_CH4_PF15_AF2 +#define TIM20_CH4_PF3_AF2 +#define TIM20_ETR_PE0_AF6 +#define TIM20_ETR_PF11_AF2 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH1_PD3_AF2 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH2_PD4_AF2 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH3_PD7_AF2 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_CH4_PD6_AF2 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM2_ETR_PD3_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH1_PE2_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH2_PE3_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH3_PE4_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_CH4_PE5_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH1_PD12_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH2_PD13_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH3_PD14_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_CH4_PD15_AF2 +#define TIM4_CH4_PF6_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM4_ETR_PE0_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH1_PB2_AF2 +#define TIM5_CH1_PF6_AF6 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH2_PC12_AF1 +#define TIM5_CH2_PF7_AF6 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH3_PE8_AF1 +#define TIM5_CH3_PF8_AF6 +#define TIM5_CH4_PA3_AF2 +#define TIM5_CH4_PE9_AF1 +#define TIM5_CH4_PF9_AF6 +#define TIM5_ETR_PB12_AF2 +#define TIM5_ETR_PD11_AF1 +#define TIM5_ETR_PF6_AF1 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN2_PD1_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4N_PD0_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_CH4_PD1_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) +#define TIM_MODULE_20 (10) + +#define TIM_MODULE_COUNT (10) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PE0_CN +#define __PE1_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN +#define __PE6_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PF10_CN +#define __PF11_CN +#define __PF12_CN +#define __PF13_CN +#define __PF14_CN +#define __PF15_CN +#define __PF2_CN +#define __PF3_CN +#define __PF4_CN +#define __PF5_CN +#define __PF6_CN +#define __PF7_CN +#define __PF8_CN +#define __PF9_CN +#define __PG0_CN +#define __PG1_CN +#define __PG10_CN +#define __PG2_CN +#define __PG3_CN +#define __PG4_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (7) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473QB/LQFP128/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473QB/LQFP128/mcu_definitions.h new file mode 100644 index 000000000..97aa3c632 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473QB/LQFP128/mcu_definitions.h @@ -0,0 +1,664 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G473QB_LQFP128. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 +#define ADC3_PD10_CH7 +#define ADC3_PD11_CH8 +#define ADC3_PD12_CH9 +#define ADC3_PD13_CH10 +#define ADC3_PD14_CH11 +#define ADC3_PE10_CH14 +#define ADC3_PE11_CH15 +#define ADC3_PE12_CH16 +#define ADC3_PE13_CH3 +#define ADC3_PE7_CH4 +#define ADC3_PE8_CH6 +#define ADC3_PE9_CH2 +#define ADC4_PB12_CH3 +#define ADC4_PB14_CH4 +#define ADC4_PB15_CH5 +#define ADC4_PD10_CH7 +#define ADC4_PD11_CH8 +#define ADC4_PD12_CH9 +#define ADC4_PD13_CH10 +#define ADC4_PD14_CH11 +#define ADC4_PD8_CH12 +#define ADC4_PD9_CH13 +#define ADC4_PE10_CH14 +#define ADC4_PE11_CH15 +#define ADC4_PE12_CH16 +#define ADC4_PE14_CH1 +#define ADC4_PE15_CH2 +#define ADC4_PE8_CH6 +#define ADC5_PA8_CH1 +#define ADC5_PA9_CH2 +#define ADC5_PD10_CH7 +#define ADC5_PD11_CH8 +#define ADC5_PD12_CH9 +#define ADC5_PD13_CH10 +#define ADC5_PD14_CH11 +#define ADC5_PD8_CH12 +#define ADC5_PD9_CH13 +#define ADC5_PE10_CH14 +#define ADC5_PE11_CH15 +#define ADC5_PE12_CH16 +#define ADC5_PE8_CH6 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) +#define ADC_MODULE_4 (4) +#define ADC_MODULE_5 (5) + +#define ADC_MODULE_COUNT (5) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_RX_PD0_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN1_TX_PD1_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 +#define FDCAN3_RX_PA8_AF11 +#define FDCAN3_RX_PB3_AF11 +#define FDCAN3_TX_PA15_AF11 +#define FDCAN3_TX_PB4_AF11 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) +#define CAN_MODULE_3 (3) + +#define CAN_MODULE_COUNT (3) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +#define HAL_LL_FDCAN3_GPIO_AF11 (11) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SCL_PF6_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SCL_PF3_AF4 +#define I2C3_SCL_PG7_AF4 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 +#define I2C3_SDA_PF4_AF4 +#define I2C3_SDA_PG8_AF4 +#define I2C4_SCL_PA13_AF3 +#define I2C4_SCL_PC6_AF8 +#define I2C4_SCL_PF14_AF4 +#define I2C4_SCL_PG3_AF4 +#define I2C4_SDA_PB7_AF3 +#define I2C4_SDA_PC7_AF8 +#define I2C4_SDA_PF15_AF4 +#define I2C4_SDA_PG4_AF4 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_RX_PG8_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define LPUART1_TX_PG7_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define UART5_RX_PD2_AF5 +#define UART5_TX_PC12_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_RX_PE1_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART1_TX_PE0_AF7 +#define USART1_TX_PG9_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_RX_PD6_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART2_TX_PD5_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PD9_AF7 +#define USART3_RX_PE15_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PD8_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MISO_PG3_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_MOSI_PG4_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI1_SCK_PG2_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF10_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI2_SCK_PF9_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 +#define SPI3_SCK_PG9_AF6 +#define SPI4_MISO_PE13_AF5 +#define SPI4_MISO_PE5_AF5 +#define SPI4_MOSI_PE14_AF5 +#define SPI4_MOSI_PE6_AF5 +#define SPI4_SCK_PE12_AF5 +#define SPI4_SCK_PE2_AF5 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) +#define SPI_MODULE_4 (4) + +#define SPI_MODULE_COUNT (4) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1N_PG9_AF14 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH1_PF9_AF3 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM15_CH2_PF10_AF3 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM16_CH1_PE0_AF4 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM17_CH1_PE1_AF4 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN2_PE14_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_BKIN_PE15_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1N_PE8_AF2 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH1_PE9_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2N_PE10_AF2 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH2_PE11_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PE12_AF2 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH3_PE13_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4N_PE15_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_CH4_PE14_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM1_ETR_PE7_AF2 +#define TIM20_BKIN2_PF10_AF2 +#define TIM20_BKIN2_PF8_AF2 +#define TIM20_BKIN2_PG4_AF2 +#define TIM20_BKIN_PF7_AF2 +#define TIM20_BKIN_PF9_AF2 +#define TIM20_BKIN_PG3_AF2 +#define TIM20_BKIN_PG6_AF2 +#define TIM20_CH1N_PE4_AF6 +#define TIM20_CH1N_PF4_AF3 +#define TIM20_CH1N_PG0_AF2 +#define TIM20_CH1_PB2_AF3 +#define TIM20_CH1_PE2_AF6 +#define TIM20_CH1_PF12_AF2 +#define TIM20_CH2N_PE5_AF6 +#define TIM20_CH2N_PF5_AF2 +#define TIM20_CH2N_PG1_AF2 +#define TIM20_CH2_PC2_AF6 +#define TIM20_CH2_PE3_AF6 +#define TIM20_CH2_PF13_AF2 +#define TIM20_CH3N_PE6_AF6 +#define TIM20_CH3N_PG2_AF2 +#define TIM20_CH3_PC8_AF6 +#define TIM20_CH3_PF14_AF2 +#define TIM20_CH3_PF2_AF2 +#define TIM20_CH4N_PE0_AF3 +#define TIM20_CH4N_PG3_AF6 +#define TIM20_CH4_PE1_AF6 +#define TIM20_CH4_PF15_AF2 +#define TIM20_CH4_PF3_AF2 +#define TIM20_ETR_PE0_AF6 +#define TIM20_ETR_PF11_AF2 +#define TIM20_ETR_PG5_AF2 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH1_PD3_AF2 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH2_PD4_AF2 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH3_PD7_AF2 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_CH4_PD6_AF2 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM2_ETR_PD3_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH1_PE2_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH2_PE3_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH3_PE4_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_CH4_PE5_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH1_PD12_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH2_PD13_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH3_PD14_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_CH4_PD15_AF2 +#define TIM4_CH4_PF6_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM4_ETR_PE0_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH1_PB2_AF2 +#define TIM5_CH1_PF6_AF6 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH2_PC12_AF1 +#define TIM5_CH2_PF7_AF6 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH3_PE8_AF1 +#define TIM5_CH3_PF8_AF6 +#define TIM5_CH4_PA3_AF2 +#define TIM5_CH4_PE9_AF1 +#define TIM5_CH4_PF9_AF6 +#define TIM5_ETR_PB12_AF2 +#define TIM5_ETR_PD11_AF1 +#define TIM5_ETR_PF6_AF1 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN2_PD1_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4N_PD0_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_CH4_PD1_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) +#define TIM_MODULE_20 (10) + +#define TIM_MODULE_COUNT (10) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PE0_CN +#define __PE1_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN +#define __PE6_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PF10_CN +#define __PF11_CN +#define __PF12_CN +#define __PF13_CN +#define __PF14_CN +#define __PF15_CN +#define __PF2_CN +#define __PF3_CN +#define __PF4_CN +#define __PF5_CN +#define __PF6_CN +#define __PF7_CN +#define __PF8_CN +#define __PF9_CN +#define __PG0_CN +#define __PG1_CN +#define __PG10_CN +#define __PG2_CN +#define __PG3_CN +#define __PG4_CN +#define __PG5_CN +#define __PG6_CN +#define __PG7_CN +#define __PG8_CN +#define __PG9_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (7) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473QC/LQFP128/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473QC/LQFP128/mcu_definitions.h new file mode 100644 index 000000000..076b1ecf6 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473QC/LQFP128/mcu_definitions.h @@ -0,0 +1,664 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G473QC_LQFP128. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 +#define ADC3_PD10_CH7 +#define ADC3_PD11_CH8 +#define ADC3_PD12_CH9 +#define ADC3_PD13_CH10 +#define ADC3_PD14_CH11 +#define ADC3_PE10_CH14 +#define ADC3_PE11_CH15 +#define ADC3_PE12_CH16 +#define ADC3_PE13_CH3 +#define ADC3_PE7_CH4 +#define ADC3_PE8_CH6 +#define ADC3_PE9_CH2 +#define ADC4_PB12_CH3 +#define ADC4_PB14_CH4 +#define ADC4_PB15_CH5 +#define ADC4_PD10_CH7 +#define ADC4_PD11_CH8 +#define ADC4_PD12_CH9 +#define ADC4_PD13_CH10 +#define ADC4_PD14_CH11 +#define ADC4_PD8_CH12 +#define ADC4_PD9_CH13 +#define ADC4_PE10_CH14 +#define ADC4_PE11_CH15 +#define ADC4_PE12_CH16 +#define ADC4_PE14_CH1 +#define ADC4_PE15_CH2 +#define ADC4_PE8_CH6 +#define ADC5_PA8_CH1 +#define ADC5_PA9_CH2 +#define ADC5_PD10_CH7 +#define ADC5_PD11_CH8 +#define ADC5_PD12_CH9 +#define ADC5_PD13_CH10 +#define ADC5_PD14_CH11 +#define ADC5_PD8_CH12 +#define ADC5_PD9_CH13 +#define ADC5_PE10_CH14 +#define ADC5_PE11_CH15 +#define ADC5_PE12_CH16 +#define ADC5_PE8_CH6 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) +#define ADC_MODULE_4 (4) +#define ADC_MODULE_5 (5) + +#define ADC_MODULE_COUNT (5) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_RX_PD0_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN1_TX_PD1_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 +#define FDCAN3_RX_PA8_AF11 +#define FDCAN3_RX_PB3_AF11 +#define FDCAN3_TX_PA15_AF11 +#define FDCAN3_TX_PB4_AF11 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) +#define CAN_MODULE_3 (3) + +#define CAN_MODULE_COUNT (3) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +#define HAL_LL_FDCAN3_GPIO_AF11 (11) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SCL_PF6_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SCL_PF3_AF4 +#define I2C3_SCL_PG7_AF4 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 +#define I2C3_SDA_PF4_AF4 +#define I2C3_SDA_PG8_AF4 +#define I2C4_SCL_PA13_AF3 +#define I2C4_SCL_PC6_AF8 +#define I2C4_SCL_PF14_AF4 +#define I2C4_SCL_PG3_AF4 +#define I2C4_SDA_PB7_AF3 +#define I2C4_SDA_PC7_AF8 +#define I2C4_SDA_PF15_AF4 +#define I2C4_SDA_PG4_AF4 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_RX_PG8_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define LPUART1_TX_PG7_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define UART5_RX_PD2_AF5 +#define UART5_TX_PC12_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_RX_PE1_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART1_TX_PE0_AF7 +#define USART1_TX_PG9_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_RX_PD6_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART2_TX_PD5_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PD9_AF7 +#define USART3_RX_PE15_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PD8_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MISO_PG3_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_MOSI_PG4_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI1_SCK_PG2_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF10_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI2_SCK_PF9_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 +#define SPI3_SCK_PG9_AF6 +#define SPI4_MISO_PE13_AF5 +#define SPI4_MISO_PE5_AF5 +#define SPI4_MOSI_PE14_AF5 +#define SPI4_MOSI_PE6_AF5 +#define SPI4_SCK_PE12_AF5 +#define SPI4_SCK_PE2_AF5 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) +#define SPI_MODULE_4 (4) + +#define SPI_MODULE_COUNT (4) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1N_PG9_AF14 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH1_PF9_AF3 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM15_CH2_PF10_AF3 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM16_CH1_PE0_AF4 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM17_CH1_PE1_AF4 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN2_PE14_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_BKIN_PE15_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1N_PE8_AF2 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH1_PE9_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2N_PE10_AF2 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH2_PE11_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PE12_AF2 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH3_PE13_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4N_PE15_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_CH4_PE14_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM1_ETR_PE7_AF2 +#define TIM20_BKIN2_PF10_AF2 +#define TIM20_BKIN2_PF8_AF2 +#define TIM20_BKIN2_PG4_AF2 +#define TIM20_BKIN_PF7_AF2 +#define TIM20_BKIN_PF9_AF2 +#define TIM20_BKIN_PG3_AF2 +#define TIM20_BKIN_PG6_AF2 +#define TIM20_CH1N_PE4_AF6 +#define TIM20_CH1N_PF4_AF3 +#define TIM20_CH1N_PG0_AF2 +#define TIM20_CH1_PB2_AF3 +#define TIM20_CH1_PE2_AF6 +#define TIM20_CH1_PF12_AF2 +#define TIM20_CH2N_PE5_AF6 +#define TIM20_CH2N_PF5_AF2 +#define TIM20_CH2N_PG1_AF2 +#define TIM20_CH2_PC2_AF6 +#define TIM20_CH2_PE3_AF6 +#define TIM20_CH2_PF13_AF2 +#define TIM20_CH3N_PE6_AF6 +#define TIM20_CH3N_PG2_AF2 +#define TIM20_CH3_PC8_AF6 +#define TIM20_CH3_PF14_AF2 +#define TIM20_CH3_PF2_AF2 +#define TIM20_CH4N_PE0_AF3 +#define TIM20_CH4N_PG3_AF6 +#define TIM20_CH4_PE1_AF6 +#define TIM20_CH4_PF15_AF2 +#define TIM20_CH4_PF3_AF2 +#define TIM20_ETR_PE0_AF6 +#define TIM20_ETR_PF11_AF2 +#define TIM20_ETR_PG5_AF2 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH1_PD3_AF2 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH2_PD4_AF2 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH3_PD7_AF2 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_CH4_PD6_AF2 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM2_ETR_PD3_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH1_PE2_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH2_PE3_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH3_PE4_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_CH4_PE5_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH1_PD12_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH2_PD13_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH3_PD14_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_CH4_PD15_AF2 +#define TIM4_CH4_PF6_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM4_ETR_PE0_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH1_PB2_AF2 +#define TIM5_CH1_PF6_AF6 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH2_PC12_AF1 +#define TIM5_CH2_PF7_AF6 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH3_PE8_AF1 +#define TIM5_CH3_PF8_AF6 +#define TIM5_CH4_PA3_AF2 +#define TIM5_CH4_PE9_AF1 +#define TIM5_CH4_PF9_AF6 +#define TIM5_ETR_PB12_AF2 +#define TIM5_ETR_PD11_AF1 +#define TIM5_ETR_PF6_AF1 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN2_PD1_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4N_PD0_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_CH4_PD1_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) +#define TIM_MODULE_20 (10) + +#define TIM_MODULE_COUNT (10) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PE0_CN +#define __PE1_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN +#define __PE6_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PF10_CN +#define __PF11_CN +#define __PF12_CN +#define __PF13_CN +#define __PF14_CN +#define __PF15_CN +#define __PF2_CN +#define __PF3_CN +#define __PF4_CN +#define __PF5_CN +#define __PF6_CN +#define __PF7_CN +#define __PF8_CN +#define __PF9_CN +#define __PG0_CN +#define __PG1_CN +#define __PG10_CN +#define __PG2_CN +#define __PG3_CN +#define __PG4_CN +#define __PG5_CN +#define __PG6_CN +#define __PG7_CN +#define __PG8_CN +#define __PG9_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (7) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473QE/LQFP128/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473QE/LQFP128/mcu_definitions.h new file mode 100644 index 000000000..66962c42d --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473QE/LQFP128/mcu_definitions.h @@ -0,0 +1,664 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G473QE_LQFP128. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 +#define ADC3_PD10_CH7 +#define ADC3_PD11_CH8 +#define ADC3_PD12_CH9 +#define ADC3_PD13_CH10 +#define ADC3_PD14_CH11 +#define ADC3_PE10_CH14 +#define ADC3_PE11_CH15 +#define ADC3_PE12_CH16 +#define ADC3_PE13_CH3 +#define ADC3_PE7_CH4 +#define ADC3_PE8_CH6 +#define ADC3_PE9_CH2 +#define ADC4_PB12_CH3 +#define ADC4_PB14_CH4 +#define ADC4_PB15_CH5 +#define ADC4_PD10_CH7 +#define ADC4_PD11_CH8 +#define ADC4_PD12_CH9 +#define ADC4_PD13_CH10 +#define ADC4_PD14_CH11 +#define ADC4_PD8_CH12 +#define ADC4_PD9_CH13 +#define ADC4_PE10_CH14 +#define ADC4_PE11_CH15 +#define ADC4_PE12_CH16 +#define ADC4_PE14_CH1 +#define ADC4_PE15_CH2 +#define ADC4_PE8_CH6 +#define ADC5_PA8_CH1 +#define ADC5_PA9_CH2 +#define ADC5_PD10_CH7 +#define ADC5_PD11_CH8 +#define ADC5_PD12_CH9 +#define ADC5_PD13_CH10 +#define ADC5_PD14_CH11 +#define ADC5_PD8_CH12 +#define ADC5_PD9_CH13 +#define ADC5_PE10_CH14 +#define ADC5_PE11_CH15 +#define ADC5_PE12_CH16 +#define ADC5_PE8_CH6 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) +#define ADC_MODULE_4 (4) +#define ADC_MODULE_5 (5) + +#define ADC_MODULE_COUNT (5) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_RX_PD0_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN1_TX_PD1_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 +#define FDCAN3_RX_PA8_AF11 +#define FDCAN3_RX_PB3_AF11 +#define FDCAN3_TX_PA15_AF11 +#define FDCAN3_TX_PB4_AF11 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) +#define CAN_MODULE_3 (3) + +#define CAN_MODULE_COUNT (3) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +#define HAL_LL_FDCAN3_GPIO_AF11 (11) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SCL_PF6_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SCL_PF3_AF4 +#define I2C3_SCL_PG7_AF4 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 +#define I2C3_SDA_PF4_AF4 +#define I2C3_SDA_PG8_AF4 +#define I2C4_SCL_PA13_AF3 +#define I2C4_SCL_PC6_AF8 +#define I2C4_SCL_PF14_AF4 +#define I2C4_SCL_PG3_AF4 +#define I2C4_SDA_PB7_AF3 +#define I2C4_SDA_PC7_AF8 +#define I2C4_SDA_PF15_AF4 +#define I2C4_SDA_PG4_AF4 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_RX_PG8_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define LPUART1_TX_PG7_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define UART5_RX_PD2_AF5 +#define UART5_TX_PC12_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_RX_PE1_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART1_TX_PE0_AF7 +#define USART1_TX_PG9_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_RX_PD6_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART2_TX_PD5_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PD9_AF7 +#define USART3_RX_PE15_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PD8_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MISO_PG3_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_MOSI_PG4_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI1_SCK_PG2_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF10_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI2_SCK_PF9_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 +#define SPI3_SCK_PG9_AF6 +#define SPI4_MISO_PE13_AF5 +#define SPI4_MISO_PE5_AF5 +#define SPI4_MOSI_PE14_AF5 +#define SPI4_MOSI_PE6_AF5 +#define SPI4_SCK_PE12_AF5 +#define SPI4_SCK_PE2_AF5 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) +#define SPI_MODULE_4 (4) + +#define SPI_MODULE_COUNT (4) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1N_PG9_AF14 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH1_PF9_AF3 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM15_CH2_PF10_AF3 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM16_CH1_PE0_AF4 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM17_CH1_PE1_AF4 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN2_PE14_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_BKIN_PE15_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1N_PE8_AF2 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH1_PE9_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2N_PE10_AF2 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH2_PE11_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PE12_AF2 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH3_PE13_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4N_PE15_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_CH4_PE14_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM1_ETR_PE7_AF2 +#define TIM20_BKIN2_PF10_AF2 +#define TIM20_BKIN2_PF8_AF2 +#define TIM20_BKIN2_PG4_AF2 +#define TIM20_BKIN_PF7_AF2 +#define TIM20_BKIN_PF9_AF2 +#define TIM20_BKIN_PG3_AF2 +#define TIM20_BKIN_PG6_AF2 +#define TIM20_CH1N_PE4_AF6 +#define TIM20_CH1N_PF4_AF3 +#define TIM20_CH1N_PG0_AF2 +#define TIM20_CH1_PB2_AF3 +#define TIM20_CH1_PE2_AF6 +#define TIM20_CH1_PF12_AF2 +#define TIM20_CH2N_PE5_AF6 +#define TIM20_CH2N_PF5_AF2 +#define TIM20_CH2N_PG1_AF2 +#define TIM20_CH2_PC2_AF6 +#define TIM20_CH2_PE3_AF6 +#define TIM20_CH2_PF13_AF2 +#define TIM20_CH3N_PE6_AF6 +#define TIM20_CH3N_PG2_AF2 +#define TIM20_CH3_PC8_AF6 +#define TIM20_CH3_PF14_AF2 +#define TIM20_CH3_PF2_AF2 +#define TIM20_CH4N_PE0_AF3 +#define TIM20_CH4N_PG3_AF6 +#define TIM20_CH4_PE1_AF6 +#define TIM20_CH4_PF15_AF2 +#define TIM20_CH4_PF3_AF2 +#define TIM20_ETR_PE0_AF6 +#define TIM20_ETR_PF11_AF2 +#define TIM20_ETR_PG5_AF2 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH1_PD3_AF2 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH2_PD4_AF2 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH3_PD7_AF2 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_CH4_PD6_AF2 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM2_ETR_PD3_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH1_PE2_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH2_PE3_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH3_PE4_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_CH4_PE5_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH1_PD12_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH2_PD13_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH3_PD14_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_CH4_PD15_AF2 +#define TIM4_CH4_PF6_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM4_ETR_PE0_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH1_PB2_AF2 +#define TIM5_CH1_PF6_AF6 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH2_PC12_AF1 +#define TIM5_CH2_PF7_AF6 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH3_PE8_AF1 +#define TIM5_CH3_PF8_AF6 +#define TIM5_CH4_PA3_AF2 +#define TIM5_CH4_PE9_AF1 +#define TIM5_CH4_PF9_AF6 +#define TIM5_ETR_PB12_AF2 +#define TIM5_ETR_PD11_AF1 +#define TIM5_ETR_PF6_AF1 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN2_PD1_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4N_PD0_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_CH4_PD1_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) +#define TIM_MODULE_20 (10) + +#define TIM_MODULE_COUNT (10) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PE0_CN +#define __PE1_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN +#define __PE6_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PF10_CN +#define __PF11_CN +#define __PF12_CN +#define __PF13_CN +#define __PF14_CN +#define __PF15_CN +#define __PF2_CN +#define __PF3_CN +#define __PF4_CN +#define __PF5_CN +#define __PF6_CN +#define __PF7_CN +#define __PF8_CN +#define __PF9_CN +#define __PG0_CN +#define __PG1_CN +#define __PG10_CN +#define __PG2_CN +#define __PG3_CN +#define __PG4_CN +#define __PG5_CN +#define __PG6_CN +#define __PG7_CN +#define __PG8_CN +#define __PG9_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (7) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473RB/LQFP64/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473RB/LQFP64/mcu_definitions.h new file mode 100644 index 000000000..0ea1e3944 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473RB/LQFP64/mcu_definitions.h @@ -0,0 +1,467 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G473RB_LQFP64. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 +#define ADC4_PB12_CH3 +#define ADC4_PB14_CH4 +#define ADC4_PB15_CH5 +#define ADC5_PA8_CH1 +#define ADC5_PA9_CH2 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) +#define ADC_MODULE_4 (4) +#define ADC_MODULE_5 (5) + +#define ADC_MODULE_COUNT (5) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 +#define FDCAN3_RX_PA8_AF11 +#define FDCAN3_RX_PB3_AF11 +#define FDCAN3_TX_PA15_AF11 +#define FDCAN3_TX_PB4_AF11 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) +#define CAN_MODULE_3 (3) + +#define CAN_MODULE_COUNT (3) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +#define HAL_LL_FDCAN3_GPIO_AF11 (11) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 +#define I2C4_SCL_PA13_AF3 +#define I2C4_SCL_PC6_AF8 +#define I2C4_SDA_PB7_AF3 +#define I2C4_SDA_PC7_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define UART5_RX_PD2_AF5 +#define UART5_TX_PC12_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM20_CH1_PB2_AF3 +#define TIM20_CH2_PC2_AF6 +#define TIM20_CH3_PC8_AF6 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH1_PB2_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH2_PC12_AF1 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH4_PA3_AF2 +#define TIM5_ETR_PB12_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) +#define TIM_MODULE_20 (10) + +#define TIM_MODULE_COUNT (10) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD2_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (6) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473RC/LQFP64/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473RC/LQFP64/mcu_definitions.h new file mode 100644 index 000000000..7fe2f44cb --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473RC/LQFP64/mcu_definitions.h @@ -0,0 +1,467 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G473RC_LQFP64. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 +#define ADC4_PB12_CH3 +#define ADC4_PB14_CH4 +#define ADC4_PB15_CH5 +#define ADC5_PA8_CH1 +#define ADC5_PA9_CH2 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) +#define ADC_MODULE_4 (4) +#define ADC_MODULE_5 (5) + +#define ADC_MODULE_COUNT (5) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 +#define FDCAN3_RX_PA8_AF11 +#define FDCAN3_RX_PB3_AF11 +#define FDCAN3_TX_PA15_AF11 +#define FDCAN3_TX_PB4_AF11 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) +#define CAN_MODULE_3 (3) + +#define CAN_MODULE_COUNT (3) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +#define HAL_LL_FDCAN3_GPIO_AF11 (11) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 +#define I2C4_SCL_PA13_AF3 +#define I2C4_SCL_PC6_AF8 +#define I2C4_SDA_PB7_AF3 +#define I2C4_SDA_PC7_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define UART5_RX_PD2_AF5 +#define UART5_TX_PC12_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM20_CH1_PB2_AF3 +#define TIM20_CH2_PC2_AF6 +#define TIM20_CH3_PC8_AF6 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH1_PB2_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH2_PC12_AF1 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH4_PA3_AF2 +#define TIM5_ETR_PB12_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) +#define TIM_MODULE_20 (10) + +#define TIM_MODULE_COUNT (10) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD2_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (6) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473RE/LQFP64/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473RE/LQFP64/mcu_definitions.h new file mode 100644 index 000000000..dbec13fe0 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473RE/LQFP64/mcu_definitions.h @@ -0,0 +1,467 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G473RE_LQFP64. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 +#define ADC4_PB12_CH3 +#define ADC4_PB14_CH4 +#define ADC4_PB15_CH5 +#define ADC5_PA8_CH1 +#define ADC5_PA9_CH2 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) +#define ADC_MODULE_4 (4) +#define ADC_MODULE_5 (5) + +#define ADC_MODULE_COUNT (5) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 +#define FDCAN3_RX_PA8_AF11 +#define FDCAN3_RX_PB3_AF11 +#define FDCAN3_TX_PA15_AF11 +#define FDCAN3_TX_PB4_AF11 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) +#define CAN_MODULE_3 (3) + +#define CAN_MODULE_COUNT (3) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +#define HAL_LL_FDCAN3_GPIO_AF11 (11) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 +#define I2C4_SCL_PA13_AF3 +#define I2C4_SCL_PC6_AF8 +#define I2C4_SDA_PB7_AF3 +#define I2C4_SDA_PC7_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define UART5_RX_PD2_AF5 +#define UART5_TX_PC12_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM20_CH1_PB2_AF3 +#define TIM20_CH2_PC2_AF6 +#define TIM20_CH3_PC8_AF6 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH1_PB2_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH2_PC12_AF1 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH4_PA3_AF2 +#define TIM5_ETR_PB12_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) +#define TIM_MODULE_20 (10) + +#define TIM_MODULE_COUNT (10) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD2_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (6) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473VB/LQFP100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473VB/LQFP100/mcu_definitions.h new file mode 100644 index 000000000..b1e0e13b1 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473VB/LQFP100/mcu_definitions.h @@ -0,0 +1,603 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G473VB_LQFP100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 +#define ADC3_PD10_CH7 +#define ADC3_PD11_CH8 +#define ADC3_PD12_CH9 +#define ADC3_PD13_CH10 +#define ADC3_PD14_CH11 +#define ADC3_PE10_CH14 +#define ADC3_PE11_CH15 +#define ADC3_PE12_CH16 +#define ADC3_PE13_CH3 +#define ADC3_PE7_CH4 +#define ADC3_PE8_CH6 +#define ADC3_PE9_CH2 +#define ADC4_PB12_CH3 +#define ADC4_PB14_CH4 +#define ADC4_PB15_CH5 +#define ADC4_PD10_CH7 +#define ADC4_PD11_CH8 +#define ADC4_PD12_CH9 +#define ADC4_PD13_CH10 +#define ADC4_PD14_CH11 +#define ADC4_PD8_CH12 +#define ADC4_PD9_CH13 +#define ADC4_PE10_CH14 +#define ADC4_PE11_CH15 +#define ADC4_PE12_CH16 +#define ADC4_PE14_CH1 +#define ADC4_PE15_CH2 +#define ADC4_PE8_CH6 +#define ADC5_PA8_CH1 +#define ADC5_PA9_CH2 +#define ADC5_PD10_CH7 +#define ADC5_PD11_CH8 +#define ADC5_PD12_CH9 +#define ADC5_PD13_CH10 +#define ADC5_PD14_CH11 +#define ADC5_PD8_CH12 +#define ADC5_PD9_CH13 +#define ADC5_PE10_CH14 +#define ADC5_PE11_CH15 +#define ADC5_PE12_CH16 +#define ADC5_PE8_CH6 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) +#define ADC_MODULE_4 (4) +#define ADC_MODULE_5 (5) + +#define ADC_MODULE_COUNT (5) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_RX_PD0_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN1_TX_PD1_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 +#define FDCAN3_RX_PA8_AF11 +#define FDCAN3_RX_PB3_AF11 +#define FDCAN3_TX_PA15_AF11 +#define FDCAN3_TX_PB4_AF11 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) +#define CAN_MODULE_3 (3) + +#define CAN_MODULE_COUNT (3) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +#define HAL_LL_FDCAN3_GPIO_AF11 (11) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 +#define I2C4_SCL_PA13_AF3 +#define I2C4_SCL_PC6_AF8 +#define I2C4_SDA_PB7_AF3 +#define I2C4_SDA_PC7_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define UART5_RX_PD2_AF5 +#define UART5_TX_PC12_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_RX_PE1_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART1_TX_PE0_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_RX_PD6_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART2_TX_PD5_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PD9_AF7 +#define USART3_RX_PE15_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PD8_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF10_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI2_SCK_PF9_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 +#define SPI4_MISO_PE13_AF5 +#define SPI4_MISO_PE5_AF5 +#define SPI4_MOSI_PE14_AF5 +#define SPI4_MOSI_PE6_AF5 +#define SPI4_SCK_PE12_AF5 +#define SPI4_SCK_PE2_AF5 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) +#define SPI_MODULE_4 (4) + +#define SPI_MODULE_COUNT (4) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH1_PF9_AF3 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM15_CH2_PF10_AF3 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM16_CH1_PE0_AF4 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM17_CH1_PE1_AF4 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN2_PE14_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_BKIN_PE15_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1N_PE8_AF2 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH1_PE9_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2N_PE10_AF2 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH2_PE11_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PE12_AF2 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH3_PE13_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4N_PE15_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_CH4_PE14_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM1_ETR_PE7_AF2 +#define TIM20_BKIN2_PF10_AF2 +#define TIM20_BKIN_PF9_AF2 +#define TIM20_CH1N_PE4_AF6 +#define TIM20_CH1_PB2_AF3 +#define TIM20_CH1_PE2_AF6 +#define TIM20_CH2N_PE5_AF6 +#define TIM20_CH2_PC2_AF6 +#define TIM20_CH2_PE3_AF6 +#define TIM20_CH3N_PE6_AF6 +#define TIM20_CH3_PC8_AF6 +#define TIM20_CH3_PF2_AF2 +#define TIM20_CH4N_PE0_AF3 +#define TIM20_CH4_PE1_AF6 +#define TIM20_ETR_PE0_AF6 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH1_PD3_AF2 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH2_PD4_AF2 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH3_PD7_AF2 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_CH4_PD6_AF2 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM2_ETR_PD3_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH1_PE2_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH2_PE3_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH3_PE4_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_CH4_PE5_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH1_PD12_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH2_PD13_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH3_PD14_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_CH4_PD15_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM4_ETR_PE0_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH1_PB2_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH2_PC12_AF1 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH3_PE8_AF1 +#define TIM5_CH4_PA3_AF2 +#define TIM5_CH4_PE9_AF1 +#define TIM5_CH4_PF9_AF6 +#define TIM5_ETR_PB12_AF2 +#define TIM5_ETR_PD11_AF1 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN2_PD1_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4N_PD0_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_CH4_PD1_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) +#define TIM_MODULE_20 (10) + +#define TIM_MODULE_COUNT (10) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PE0_CN +#define __PE1_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN +#define __PE6_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PF10_CN +#define __PF2_CN +#define __PF9_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (7) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473VB/TFBGA100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473VB/TFBGA100/mcu_definitions.h new file mode 100644 index 000000000..0c06d9d74 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473VB/TFBGA100/mcu_definitions.h @@ -0,0 +1,603 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G473VB_TFBGA100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 +#define ADC3_PD10_CH7 +#define ADC3_PD11_CH8 +#define ADC3_PD12_CH9 +#define ADC3_PD13_CH10 +#define ADC3_PD14_CH11 +#define ADC3_PE10_CH14 +#define ADC3_PE11_CH15 +#define ADC3_PE12_CH16 +#define ADC3_PE13_CH3 +#define ADC3_PE7_CH4 +#define ADC3_PE8_CH6 +#define ADC3_PE9_CH2 +#define ADC4_PB12_CH3 +#define ADC4_PB14_CH4 +#define ADC4_PB15_CH5 +#define ADC4_PD10_CH7 +#define ADC4_PD11_CH8 +#define ADC4_PD12_CH9 +#define ADC4_PD13_CH10 +#define ADC4_PD14_CH11 +#define ADC4_PD8_CH12 +#define ADC4_PD9_CH13 +#define ADC4_PE10_CH14 +#define ADC4_PE11_CH15 +#define ADC4_PE12_CH16 +#define ADC4_PE14_CH1 +#define ADC4_PE15_CH2 +#define ADC4_PE8_CH6 +#define ADC5_PA8_CH1 +#define ADC5_PA9_CH2 +#define ADC5_PD10_CH7 +#define ADC5_PD11_CH8 +#define ADC5_PD12_CH9 +#define ADC5_PD13_CH10 +#define ADC5_PD14_CH11 +#define ADC5_PD8_CH12 +#define ADC5_PD9_CH13 +#define ADC5_PE10_CH14 +#define ADC5_PE11_CH15 +#define ADC5_PE12_CH16 +#define ADC5_PE8_CH6 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) +#define ADC_MODULE_4 (4) +#define ADC_MODULE_5 (5) + +#define ADC_MODULE_COUNT (5) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_RX_PD0_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN1_TX_PD1_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 +#define FDCAN3_RX_PA8_AF11 +#define FDCAN3_RX_PB3_AF11 +#define FDCAN3_TX_PA15_AF11 +#define FDCAN3_TX_PB4_AF11 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) +#define CAN_MODULE_3 (3) + +#define CAN_MODULE_COUNT (3) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +#define HAL_LL_FDCAN3_GPIO_AF11 (11) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 +#define I2C4_SCL_PA13_AF3 +#define I2C4_SCL_PC6_AF8 +#define I2C4_SDA_PB7_AF3 +#define I2C4_SDA_PC7_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define UART5_RX_PD2_AF5 +#define UART5_TX_PC12_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_RX_PE1_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART1_TX_PE0_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_RX_PD6_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART2_TX_PD5_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PD9_AF7 +#define USART3_RX_PE15_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PD8_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF10_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI2_SCK_PF9_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 +#define SPI4_MISO_PE13_AF5 +#define SPI4_MISO_PE5_AF5 +#define SPI4_MOSI_PE14_AF5 +#define SPI4_MOSI_PE6_AF5 +#define SPI4_SCK_PE12_AF5 +#define SPI4_SCK_PE2_AF5 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) +#define SPI_MODULE_4 (4) + +#define SPI_MODULE_COUNT (4) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH1_PF9_AF3 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM15_CH2_PF10_AF3 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM16_CH1_PE0_AF4 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM17_CH1_PE1_AF4 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN2_PE14_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_BKIN_PE15_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1N_PE8_AF2 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH1_PE9_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2N_PE10_AF2 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH2_PE11_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PE12_AF2 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH3_PE13_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4N_PE15_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_CH4_PE14_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM1_ETR_PE7_AF2 +#define TIM20_BKIN2_PF10_AF2 +#define TIM20_BKIN_PF9_AF2 +#define TIM20_CH1N_PE4_AF6 +#define TIM20_CH1_PB2_AF3 +#define TIM20_CH1_PE2_AF6 +#define TIM20_CH2N_PE5_AF6 +#define TIM20_CH2_PC2_AF6 +#define TIM20_CH2_PE3_AF6 +#define TIM20_CH3N_PE6_AF6 +#define TIM20_CH3_PC8_AF6 +#define TIM20_CH3_PF2_AF2 +#define TIM20_CH4N_PE0_AF3 +#define TIM20_CH4_PE1_AF6 +#define TIM20_ETR_PE0_AF6 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH1_PD3_AF2 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH2_PD4_AF2 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH3_PD7_AF2 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_CH4_PD6_AF2 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM2_ETR_PD3_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH1_PE2_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH2_PE3_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH3_PE4_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_CH4_PE5_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH1_PD12_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH2_PD13_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH3_PD14_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_CH4_PD15_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM4_ETR_PE0_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH1_PB2_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH2_PC12_AF1 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH3_PE8_AF1 +#define TIM5_CH4_PA3_AF2 +#define TIM5_CH4_PE9_AF1 +#define TIM5_CH4_PF9_AF6 +#define TIM5_ETR_PB12_AF2 +#define TIM5_ETR_PD11_AF1 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN2_PD1_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4N_PD0_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_CH4_PD1_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) +#define TIM_MODULE_20 (10) + +#define TIM_MODULE_COUNT (10) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PE0_CN +#define __PE1_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN +#define __PE6_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PF10_CN +#define __PF2_CN +#define __PF9_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (7) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473VC/LQFP100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473VC/LQFP100/mcu_definitions.h new file mode 100644 index 000000000..6ca5f61f9 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473VC/LQFP100/mcu_definitions.h @@ -0,0 +1,603 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G473VC_LQFP100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 +#define ADC3_PD10_CH7 +#define ADC3_PD11_CH8 +#define ADC3_PD12_CH9 +#define ADC3_PD13_CH10 +#define ADC3_PD14_CH11 +#define ADC3_PE10_CH14 +#define ADC3_PE11_CH15 +#define ADC3_PE12_CH16 +#define ADC3_PE13_CH3 +#define ADC3_PE7_CH4 +#define ADC3_PE8_CH6 +#define ADC3_PE9_CH2 +#define ADC4_PB12_CH3 +#define ADC4_PB14_CH4 +#define ADC4_PB15_CH5 +#define ADC4_PD10_CH7 +#define ADC4_PD11_CH8 +#define ADC4_PD12_CH9 +#define ADC4_PD13_CH10 +#define ADC4_PD14_CH11 +#define ADC4_PD8_CH12 +#define ADC4_PD9_CH13 +#define ADC4_PE10_CH14 +#define ADC4_PE11_CH15 +#define ADC4_PE12_CH16 +#define ADC4_PE14_CH1 +#define ADC4_PE15_CH2 +#define ADC4_PE8_CH6 +#define ADC5_PA8_CH1 +#define ADC5_PA9_CH2 +#define ADC5_PD10_CH7 +#define ADC5_PD11_CH8 +#define ADC5_PD12_CH9 +#define ADC5_PD13_CH10 +#define ADC5_PD14_CH11 +#define ADC5_PD8_CH12 +#define ADC5_PD9_CH13 +#define ADC5_PE10_CH14 +#define ADC5_PE11_CH15 +#define ADC5_PE12_CH16 +#define ADC5_PE8_CH6 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) +#define ADC_MODULE_4 (4) +#define ADC_MODULE_5 (5) + +#define ADC_MODULE_COUNT (5) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_RX_PD0_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN1_TX_PD1_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 +#define FDCAN3_RX_PA8_AF11 +#define FDCAN3_RX_PB3_AF11 +#define FDCAN3_TX_PA15_AF11 +#define FDCAN3_TX_PB4_AF11 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) +#define CAN_MODULE_3 (3) + +#define CAN_MODULE_COUNT (3) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +#define HAL_LL_FDCAN3_GPIO_AF11 (11) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 +#define I2C4_SCL_PA13_AF3 +#define I2C4_SCL_PC6_AF8 +#define I2C4_SDA_PB7_AF3 +#define I2C4_SDA_PC7_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define UART5_RX_PD2_AF5 +#define UART5_TX_PC12_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_RX_PE1_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART1_TX_PE0_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_RX_PD6_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART2_TX_PD5_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PD9_AF7 +#define USART3_RX_PE15_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PD8_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF10_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI2_SCK_PF9_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 +#define SPI4_MISO_PE13_AF5 +#define SPI4_MISO_PE5_AF5 +#define SPI4_MOSI_PE14_AF5 +#define SPI4_MOSI_PE6_AF5 +#define SPI4_SCK_PE12_AF5 +#define SPI4_SCK_PE2_AF5 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) +#define SPI_MODULE_4 (4) + +#define SPI_MODULE_COUNT (4) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH1_PF9_AF3 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM15_CH2_PF10_AF3 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM16_CH1_PE0_AF4 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM17_CH1_PE1_AF4 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN2_PE14_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_BKIN_PE15_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1N_PE8_AF2 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH1_PE9_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2N_PE10_AF2 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH2_PE11_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PE12_AF2 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH3_PE13_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4N_PE15_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_CH4_PE14_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM1_ETR_PE7_AF2 +#define TIM20_BKIN2_PF10_AF2 +#define TIM20_BKIN_PF9_AF2 +#define TIM20_CH1N_PE4_AF6 +#define TIM20_CH1_PB2_AF3 +#define TIM20_CH1_PE2_AF6 +#define TIM20_CH2N_PE5_AF6 +#define TIM20_CH2_PC2_AF6 +#define TIM20_CH2_PE3_AF6 +#define TIM20_CH3N_PE6_AF6 +#define TIM20_CH3_PC8_AF6 +#define TIM20_CH3_PF2_AF2 +#define TIM20_CH4N_PE0_AF3 +#define TIM20_CH4_PE1_AF6 +#define TIM20_ETR_PE0_AF6 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH1_PD3_AF2 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH2_PD4_AF2 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH3_PD7_AF2 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_CH4_PD6_AF2 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM2_ETR_PD3_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH1_PE2_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH2_PE3_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH3_PE4_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_CH4_PE5_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH1_PD12_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH2_PD13_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH3_PD14_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_CH4_PD15_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM4_ETR_PE0_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH1_PB2_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH2_PC12_AF1 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH3_PE8_AF1 +#define TIM5_CH4_PA3_AF2 +#define TIM5_CH4_PE9_AF1 +#define TIM5_CH4_PF9_AF6 +#define TIM5_ETR_PB12_AF2 +#define TIM5_ETR_PD11_AF1 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN2_PD1_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4N_PD0_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_CH4_PD1_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) +#define TIM_MODULE_20 (10) + +#define TIM_MODULE_COUNT (10) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PE0_CN +#define __PE1_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN +#define __PE6_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PF10_CN +#define __PF2_CN +#define __PF9_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (7) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473VC/TFBGA100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473VC/TFBGA100/mcu_definitions.h new file mode 100644 index 000000000..86a31ea66 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473VC/TFBGA100/mcu_definitions.h @@ -0,0 +1,603 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G473VC_TFBGA100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 +#define ADC3_PD10_CH7 +#define ADC3_PD11_CH8 +#define ADC3_PD12_CH9 +#define ADC3_PD13_CH10 +#define ADC3_PD14_CH11 +#define ADC3_PE10_CH14 +#define ADC3_PE11_CH15 +#define ADC3_PE12_CH16 +#define ADC3_PE13_CH3 +#define ADC3_PE7_CH4 +#define ADC3_PE8_CH6 +#define ADC3_PE9_CH2 +#define ADC4_PB12_CH3 +#define ADC4_PB14_CH4 +#define ADC4_PB15_CH5 +#define ADC4_PD10_CH7 +#define ADC4_PD11_CH8 +#define ADC4_PD12_CH9 +#define ADC4_PD13_CH10 +#define ADC4_PD14_CH11 +#define ADC4_PD8_CH12 +#define ADC4_PD9_CH13 +#define ADC4_PE10_CH14 +#define ADC4_PE11_CH15 +#define ADC4_PE12_CH16 +#define ADC4_PE14_CH1 +#define ADC4_PE15_CH2 +#define ADC4_PE8_CH6 +#define ADC5_PA8_CH1 +#define ADC5_PA9_CH2 +#define ADC5_PD10_CH7 +#define ADC5_PD11_CH8 +#define ADC5_PD12_CH9 +#define ADC5_PD13_CH10 +#define ADC5_PD14_CH11 +#define ADC5_PD8_CH12 +#define ADC5_PD9_CH13 +#define ADC5_PE10_CH14 +#define ADC5_PE11_CH15 +#define ADC5_PE12_CH16 +#define ADC5_PE8_CH6 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) +#define ADC_MODULE_4 (4) +#define ADC_MODULE_5 (5) + +#define ADC_MODULE_COUNT (5) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_RX_PD0_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN1_TX_PD1_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 +#define FDCAN3_RX_PA8_AF11 +#define FDCAN3_RX_PB3_AF11 +#define FDCAN3_TX_PA15_AF11 +#define FDCAN3_TX_PB4_AF11 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) +#define CAN_MODULE_3 (3) + +#define CAN_MODULE_COUNT (3) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +#define HAL_LL_FDCAN3_GPIO_AF11 (11) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 +#define I2C4_SCL_PA13_AF3 +#define I2C4_SCL_PC6_AF8 +#define I2C4_SDA_PB7_AF3 +#define I2C4_SDA_PC7_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define UART5_RX_PD2_AF5 +#define UART5_TX_PC12_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_RX_PE1_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART1_TX_PE0_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_RX_PD6_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART2_TX_PD5_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PD9_AF7 +#define USART3_RX_PE15_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PD8_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF10_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI2_SCK_PF9_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 +#define SPI4_MISO_PE13_AF5 +#define SPI4_MISO_PE5_AF5 +#define SPI4_MOSI_PE14_AF5 +#define SPI4_MOSI_PE6_AF5 +#define SPI4_SCK_PE12_AF5 +#define SPI4_SCK_PE2_AF5 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) +#define SPI_MODULE_4 (4) + +#define SPI_MODULE_COUNT (4) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH1_PF9_AF3 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM15_CH2_PF10_AF3 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM16_CH1_PE0_AF4 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM17_CH1_PE1_AF4 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN2_PE14_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_BKIN_PE15_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1N_PE8_AF2 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH1_PE9_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2N_PE10_AF2 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH2_PE11_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PE12_AF2 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH3_PE13_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4N_PE15_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_CH4_PE14_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM1_ETR_PE7_AF2 +#define TIM20_BKIN2_PF10_AF2 +#define TIM20_BKIN_PF9_AF2 +#define TIM20_CH1N_PE4_AF6 +#define TIM20_CH1_PB2_AF3 +#define TIM20_CH1_PE2_AF6 +#define TIM20_CH2N_PE5_AF6 +#define TIM20_CH2_PC2_AF6 +#define TIM20_CH2_PE3_AF6 +#define TIM20_CH3N_PE6_AF6 +#define TIM20_CH3_PC8_AF6 +#define TIM20_CH3_PF2_AF2 +#define TIM20_CH4N_PE0_AF3 +#define TIM20_CH4_PE1_AF6 +#define TIM20_ETR_PE0_AF6 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH1_PD3_AF2 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH2_PD4_AF2 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH3_PD7_AF2 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_CH4_PD6_AF2 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM2_ETR_PD3_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH1_PE2_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH2_PE3_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH3_PE4_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_CH4_PE5_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH1_PD12_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH2_PD13_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH3_PD14_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_CH4_PD15_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM4_ETR_PE0_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH1_PB2_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH2_PC12_AF1 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH3_PE8_AF1 +#define TIM5_CH4_PA3_AF2 +#define TIM5_CH4_PE9_AF1 +#define TIM5_CH4_PF9_AF6 +#define TIM5_ETR_PB12_AF2 +#define TIM5_ETR_PD11_AF1 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN2_PD1_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4N_PD0_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_CH4_PD1_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) +#define TIM_MODULE_20 (10) + +#define TIM_MODULE_COUNT (10) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PE0_CN +#define __PE1_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN +#define __PE6_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PF10_CN +#define __PF2_CN +#define __PF9_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (7) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473VE/LQFP100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473VE/LQFP100/mcu_definitions.h new file mode 100644 index 000000000..bea77ff27 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473VE/LQFP100/mcu_definitions.h @@ -0,0 +1,603 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G473VE_LQFP100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 +#define ADC3_PD10_CH7 +#define ADC3_PD11_CH8 +#define ADC3_PD12_CH9 +#define ADC3_PD13_CH10 +#define ADC3_PD14_CH11 +#define ADC3_PE10_CH14 +#define ADC3_PE11_CH15 +#define ADC3_PE12_CH16 +#define ADC3_PE13_CH3 +#define ADC3_PE7_CH4 +#define ADC3_PE8_CH6 +#define ADC3_PE9_CH2 +#define ADC4_PB12_CH3 +#define ADC4_PB14_CH4 +#define ADC4_PB15_CH5 +#define ADC4_PD10_CH7 +#define ADC4_PD11_CH8 +#define ADC4_PD12_CH9 +#define ADC4_PD13_CH10 +#define ADC4_PD14_CH11 +#define ADC4_PD8_CH12 +#define ADC4_PD9_CH13 +#define ADC4_PE10_CH14 +#define ADC4_PE11_CH15 +#define ADC4_PE12_CH16 +#define ADC4_PE14_CH1 +#define ADC4_PE15_CH2 +#define ADC4_PE8_CH6 +#define ADC5_PA8_CH1 +#define ADC5_PA9_CH2 +#define ADC5_PD10_CH7 +#define ADC5_PD11_CH8 +#define ADC5_PD12_CH9 +#define ADC5_PD13_CH10 +#define ADC5_PD14_CH11 +#define ADC5_PD8_CH12 +#define ADC5_PD9_CH13 +#define ADC5_PE10_CH14 +#define ADC5_PE11_CH15 +#define ADC5_PE12_CH16 +#define ADC5_PE8_CH6 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) +#define ADC_MODULE_4 (4) +#define ADC_MODULE_5 (5) + +#define ADC_MODULE_COUNT (5) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_RX_PD0_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN1_TX_PD1_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 +#define FDCAN3_RX_PA8_AF11 +#define FDCAN3_RX_PB3_AF11 +#define FDCAN3_TX_PA15_AF11 +#define FDCAN3_TX_PB4_AF11 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) +#define CAN_MODULE_3 (3) + +#define CAN_MODULE_COUNT (3) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +#define HAL_LL_FDCAN3_GPIO_AF11 (11) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 +#define I2C4_SCL_PA13_AF3 +#define I2C4_SCL_PC6_AF8 +#define I2C4_SDA_PB7_AF3 +#define I2C4_SDA_PC7_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define UART5_RX_PD2_AF5 +#define UART5_TX_PC12_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_RX_PE1_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART1_TX_PE0_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_RX_PD6_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART2_TX_PD5_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PD9_AF7 +#define USART3_RX_PE15_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PD8_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF10_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI2_SCK_PF9_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 +#define SPI4_MISO_PE13_AF5 +#define SPI4_MISO_PE5_AF5 +#define SPI4_MOSI_PE14_AF5 +#define SPI4_MOSI_PE6_AF5 +#define SPI4_SCK_PE12_AF5 +#define SPI4_SCK_PE2_AF5 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) +#define SPI_MODULE_4 (4) + +#define SPI_MODULE_COUNT (4) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH1_PF9_AF3 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM15_CH2_PF10_AF3 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM16_CH1_PE0_AF4 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM17_CH1_PE1_AF4 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN2_PE14_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_BKIN_PE15_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1N_PE8_AF2 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH1_PE9_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2N_PE10_AF2 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH2_PE11_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PE12_AF2 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH3_PE13_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4N_PE15_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_CH4_PE14_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM1_ETR_PE7_AF2 +#define TIM20_BKIN2_PF10_AF2 +#define TIM20_BKIN_PF9_AF2 +#define TIM20_CH1N_PE4_AF6 +#define TIM20_CH1_PB2_AF3 +#define TIM20_CH1_PE2_AF6 +#define TIM20_CH2N_PE5_AF6 +#define TIM20_CH2_PC2_AF6 +#define TIM20_CH2_PE3_AF6 +#define TIM20_CH3N_PE6_AF6 +#define TIM20_CH3_PC8_AF6 +#define TIM20_CH3_PF2_AF2 +#define TIM20_CH4N_PE0_AF3 +#define TIM20_CH4_PE1_AF6 +#define TIM20_ETR_PE0_AF6 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH1_PD3_AF2 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH2_PD4_AF2 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH3_PD7_AF2 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_CH4_PD6_AF2 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM2_ETR_PD3_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH1_PE2_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH2_PE3_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH3_PE4_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_CH4_PE5_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH1_PD12_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH2_PD13_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH3_PD14_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_CH4_PD15_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM4_ETR_PE0_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH1_PB2_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH2_PC12_AF1 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH3_PE8_AF1 +#define TIM5_CH4_PA3_AF2 +#define TIM5_CH4_PE9_AF1 +#define TIM5_CH4_PF9_AF6 +#define TIM5_ETR_PB12_AF2 +#define TIM5_ETR_PD11_AF1 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN2_PD1_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4N_PD0_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_CH4_PD1_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) +#define TIM_MODULE_20 (10) + +#define TIM_MODULE_COUNT (10) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PE0_CN +#define __PE1_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN +#define __PE6_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PF10_CN +#define __PF2_CN +#define __PF9_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (7) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473VE/TFBGA100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473VE/TFBGA100/mcu_definitions.h new file mode 100644 index 000000000..671f8ca5d --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G473VE/TFBGA100/mcu_definitions.h @@ -0,0 +1,603 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G473VE_TFBGA100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 +#define ADC3_PD10_CH7 +#define ADC3_PD11_CH8 +#define ADC3_PD12_CH9 +#define ADC3_PD13_CH10 +#define ADC3_PD14_CH11 +#define ADC3_PE10_CH14 +#define ADC3_PE11_CH15 +#define ADC3_PE12_CH16 +#define ADC3_PE13_CH3 +#define ADC3_PE7_CH4 +#define ADC3_PE8_CH6 +#define ADC3_PE9_CH2 +#define ADC4_PB12_CH3 +#define ADC4_PB14_CH4 +#define ADC4_PB15_CH5 +#define ADC4_PD10_CH7 +#define ADC4_PD11_CH8 +#define ADC4_PD12_CH9 +#define ADC4_PD13_CH10 +#define ADC4_PD14_CH11 +#define ADC4_PD8_CH12 +#define ADC4_PD9_CH13 +#define ADC4_PE10_CH14 +#define ADC4_PE11_CH15 +#define ADC4_PE12_CH16 +#define ADC4_PE14_CH1 +#define ADC4_PE15_CH2 +#define ADC4_PE8_CH6 +#define ADC5_PA8_CH1 +#define ADC5_PA9_CH2 +#define ADC5_PD10_CH7 +#define ADC5_PD11_CH8 +#define ADC5_PD12_CH9 +#define ADC5_PD13_CH10 +#define ADC5_PD14_CH11 +#define ADC5_PD8_CH12 +#define ADC5_PD9_CH13 +#define ADC5_PE10_CH14 +#define ADC5_PE11_CH15 +#define ADC5_PE12_CH16 +#define ADC5_PE8_CH6 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) +#define ADC_MODULE_4 (4) +#define ADC_MODULE_5 (5) + +#define ADC_MODULE_COUNT (5) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_RX_PD0_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN1_TX_PD1_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 +#define FDCAN3_RX_PA8_AF11 +#define FDCAN3_RX_PB3_AF11 +#define FDCAN3_TX_PA15_AF11 +#define FDCAN3_TX_PB4_AF11 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) +#define CAN_MODULE_3 (3) + +#define CAN_MODULE_COUNT (3) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +#define HAL_LL_FDCAN3_GPIO_AF11 (11) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 +#define I2C4_SCL_PA13_AF3 +#define I2C4_SCL_PC6_AF8 +#define I2C4_SDA_PB7_AF3 +#define I2C4_SDA_PC7_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define UART5_RX_PD2_AF5 +#define UART5_TX_PC12_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_RX_PE1_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART1_TX_PE0_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_RX_PD6_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART2_TX_PD5_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PD9_AF7 +#define USART3_RX_PE15_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PD8_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF10_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI2_SCK_PF9_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 +#define SPI4_MISO_PE13_AF5 +#define SPI4_MISO_PE5_AF5 +#define SPI4_MOSI_PE14_AF5 +#define SPI4_MOSI_PE6_AF5 +#define SPI4_SCK_PE12_AF5 +#define SPI4_SCK_PE2_AF5 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) +#define SPI_MODULE_4 (4) + +#define SPI_MODULE_COUNT (4) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH1_PF9_AF3 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM15_CH2_PF10_AF3 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM16_CH1_PE0_AF4 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM17_CH1_PE1_AF4 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN2_PE14_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_BKIN_PE15_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1N_PE8_AF2 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH1_PE9_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2N_PE10_AF2 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH2_PE11_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PE12_AF2 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH3_PE13_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4N_PE15_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_CH4_PE14_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM1_ETR_PE7_AF2 +#define TIM20_BKIN2_PF10_AF2 +#define TIM20_BKIN_PF9_AF2 +#define TIM20_CH1N_PE4_AF6 +#define TIM20_CH1_PB2_AF3 +#define TIM20_CH1_PE2_AF6 +#define TIM20_CH2N_PE5_AF6 +#define TIM20_CH2_PC2_AF6 +#define TIM20_CH2_PE3_AF6 +#define TIM20_CH3N_PE6_AF6 +#define TIM20_CH3_PC8_AF6 +#define TIM20_CH3_PF2_AF2 +#define TIM20_CH4N_PE0_AF3 +#define TIM20_CH4_PE1_AF6 +#define TIM20_ETR_PE0_AF6 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH1_PD3_AF2 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH2_PD4_AF2 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH3_PD7_AF2 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_CH4_PD6_AF2 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM2_ETR_PD3_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH1_PE2_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH2_PE3_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH3_PE4_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_CH4_PE5_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH1_PD12_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH2_PD13_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH3_PD14_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_CH4_PD15_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM4_ETR_PE0_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH1_PB2_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH2_PC12_AF1 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH3_PE8_AF1 +#define TIM5_CH4_PA3_AF2 +#define TIM5_CH4_PE9_AF1 +#define TIM5_CH4_PF9_AF6 +#define TIM5_ETR_PB12_AF2 +#define TIM5_ETR_PD11_AF1 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN2_PD1_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4N_PD0_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_CH4_PD1_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) +#define TIM_MODULE_20 (10) + +#define TIM_MODULE_COUNT (10) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PE0_CN +#define __PE1_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN +#define __PE6_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PF10_CN +#define __PF2_CN +#define __PF9_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (7) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474CB/LQFP48/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474CB/LQFP48/mcu_definitions.h new file mode 100644 index 000000000..7302a4b71 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474CB/LQFP48/mcu_definitions.h @@ -0,0 +1,399 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G474CB_LQFP48. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 +#define ADC4_PB12_CH3 +#define ADC4_PB14_CH4 +#define ADC4_PB15_CH5 +#define ADC5_PA8_CH1 +#define ADC5_PA9_CH2 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) +#define ADC_MODULE_4 (4) +#define ADC_MODULE_5 (5) + +#define ADC_MODULE_COUNT (5) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 +#define FDCAN3_RX_PA8_AF11 +#define FDCAN3_RX_PB3_AF11 +#define FDCAN3_TX_PA15_AF11 +#define FDCAN3_TX_PB4_AF11 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) +#define CAN_MODULE_3 (3) + +#define CAN_MODULE_COUNT (3) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +#define HAL_LL_FDCAN3_GPIO_AF11 (11) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SDA_PB5_AF8 +#define I2C4_SCL_PA13_AF3 +#define I2C4_SDA_PB7_AF3 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) + +#define UART_MODULE_COUNT (3) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_SCK_PB3_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define HRTIM1_CHA1_PA8_AF13 +#define HRTIM1_CHA2_PA9_AF13 +#define HRTIM1_CHB1_PA10_AF13 +#define HRTIM1_CHB2_PA11_AF13 +#define HRTIM1_CHC1_PB12_AF13 +#define HRTIM1_CHC2_PB13_AF13 +#define HRTIM1_CHD1_PB14_AF13 +#define HRTIM1_CHD2_PB15_AF13 +#define LPTIM1_ETR_PB6_AF11 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_ETR_PA12_AF11 +#define TIM20_CH1_PB2_AF3 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_ETR_PB3_AF10 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH1_PB2_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH4_PA3_AF2 +#define TIM5_ETR_PB12_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) +#define TIM_MODULE_20 (10) + +#define TIM_MODULE_COUNT (10) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474CB/UFQFPN48/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474CB/UFQFPN48/mcu_definitions.h new file mode 100644 index 000000000..39ace152a --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474CB/UFQFPN48/mcu_definitions.h @@ -0,0 +1,423 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G474CB_UFQFPN48. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC4_CH5 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 +#define ADC4_PB12_CH3 +#define ADC4_PB14_CH4 +#define ADC4_PB15_CH5 +#define ADC5_PA8_CH1 +#define ADC5_PA9_CH2 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) +#define ADC_MODULE_4 (4) +#define ADC_MODULE_5 (5) + +#define ADC_MODULE_COUNT (5) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 +#define FDCAN3_RX_PA8_AF11 +#define FDCAN3_RX_PB3_AF11 +#define FDCAN3_TX_PA15_AF11 +#define FDCAN3_TX_PB4_AF11 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) +#define CAN_MODULE_3 (3) + +#define CAN_MODULE_COUNT (3) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +#define HAL_LL_FDCAN3_GPIO_AF11 (11) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C4_SCL_PA13_AF3 +#define I2C4_SCL_PC6_AF8 +#define I2C4_SDA_PB7_AF3 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (4) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define HRTIM1_CHA1_PA8_AF13 +#define HRTIM1_CHA2_PA9_AF13 +#define HRTIM1_CHB1_PA10_AF13 +#define HRTIM1_CHB2_PA11_AF13 +#define HRTIM1_CHC1_PB12_AF13 +#define HRTIM1_CHC2_PB13_AF13 +#define HRTIM1_CHD1_PB14_AF13 +#define HRTIM1_CHD2_PB15_AF13 +#define HRTIM1_CHF1_PC6_AF13 +#define LPTIM1_ETR_PB6_AF11 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM20_CH1_PB2_AF3 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_ETR_PB3_AF10 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH1_PB2_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH4_PA3_AF2 +#define TIM5_ETR_PB12_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) +#define TIM_MODULE_20 (10) + +#define TIM_MODULE_COUNT (10) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC10_CN +#define __PC11_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC4_CN +#define __PC6_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474CC/LQFP48/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474CC/LQFP48/mcu_definitions.h new file mode 100644 index 000000000..e8175ff9c --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474CC/LQFP48/mcu_definitions.h @@ -0,0 +1,399 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G474CC_LQFP48. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 +#define ADC4_PB12_CH3 +#define ADC4_PB14_CH4 +#define ADC4_PB15_CH5 +#define ADC5_PA8_CH1 +#define ADC5_PA9_CH2 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) +#define ADC_MODULE_4 (4) +#define ADC_MODULE_5 (5) + +#define ADC_MODULE_COUNT (5) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 +#define FDCAN3_RX_PA8_AF11 +#define FDCAN3_RX_PB3_AF11 +#define FDCAN3_TX_PA15_AF11 +#define FDCAN3_TX_PB4_AF11 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) +#define CAN_MODULE_3 (3) + +#define CAN_MODULE_COUNT (3) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +#define HAL_LL_FDCAN3_GPIO_AF11 (11) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SDA_PB5_AF8 +#define I2C4_SCL_PA13_AF3 +#define I2C4_SDA_PB7_AF3 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) + +#define UART_MODULE_COUNT (3) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_SCK_PB3_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define HRTIM1_CHA1_PA8_AF13 +#define HRTIM1_CHA2_PA9_AF13 +#define HRTIM1_CHB1_PA10_AF13 +#define HRTIM1_CHB2_PA11_AF13 +#define HRTIM1_CHC1_PB12_AF13 +#define HRTIM1_CHC2_PB13_AF13 +#define HRTIM1_CHD1_PB14_AF13 +#define HRTIM1_CHD2_PB15_AF13 +#define LPTIM1_ETR_PB6_AF11 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_ETR_PA12_AF11 +#define TIM20_CH1_PB2_AF3 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_ETR_PB3_AF10 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH1_PB2_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH4_PA3_AF2 +#define TIM5_ETR_PB12_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) +#define TIM_MODULE_20 (10) + +#define TIM_MODULE_COUNT (10) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474CC/UFQFPN48/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474CC/UFQFPN48/mcu_definitions.h new file mode 100644 index 000000000..c1d951661 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474CC/UFQFPN48/mcu_definitions.h @@ -0,0 +1,423 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G474CC_UFQFPN48. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC4_CH5 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 +#define ADC4_PB12_CH3 +#define ADC4_PB14_CH4 +#define ADC4_PB15_CH5 +#define ADC5_PA8_CH1 +#define ADC5_PA9_CH2 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) +#define ADC_MODULE_4 (4) +#define ADC_MODULE_5 (5) + +#define ADC_MODULE_COUNT (5) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 +#define FDCAN3_RX_PA8_AF11 +#define FDCAN3_RX_PB3_AF11 +#define FDCAN3_TX_PA15_AF11 +#define FDCAN3_TX_PB4_AF11 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) +#define CAN_MODULE_3 (3) + +#define CAN_MODULE_COUNT (3) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +#define HAL_LL_FDCAN3_GPIO_AF11 (11) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C4_SCL_PA13_AF3 +#define I2C4_SCL_PC6_AF8 +#define I2C4_SDA_PB7_AF3 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (4) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define HRTIM1_CHA1_PA8_AF13 +#define HRTIM1_CHA2_PA9_AF13 +#define HRTIM1_CHB1_PA10_AF13 +#define HRTIM1_CHB2_PA11_AF13 +#define HRTIM1_CHC1_PB12_AF13 +#define HRTIM1_CHC2_PB13_AF13 +#define HRTIM1_CHD1_PB14_AF13 +#define HRTIM1_CHD2_PB15_AF13 +#define HRTIM1_CHF1_PC6_AF13 +#define LPTIM1_ETR_PB6_AF11 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM20_CH1_PB2_AF3 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_ETR_PB3_AF10 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH1_PB2_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH4_PA3_AF2 +#define TIM5_ETR_PB12_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) +#define TIM_MODULE_20 (10) + +#define TIM_MODULE_COUNT (10) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC10_CN +#define __PC11_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC4_CN +#define __PC6_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474CE/LQFP48/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474CE/LQFP48/mcu_definitions.h new file mode 100644 index 000000000..c30af38ee --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474CE/LQFP48/mcu_definitions.h @@ -0,0 +1,399 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G474CE_LQFP48. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 +#define ADC4_PB12_CH3 +#define ADC4_PB14_CH4 +#define ADC4_PB15_CH5 +#define ADC5_PA8_CH1 +#define ADC5_PA9_CH2 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) +#define ADC_MODULE_4 (4) +#define ADC_MODULE_5 (5) + +#define ADC_MODULE_COUNT (5) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 +#define FDCAN3_RX_PA8_AF11 +#define FDCAN3_RX_PB3_AF11 +#define FDCAN3_TX_PA15_AF11 +#define FDCAN3_TX_PB4_AF11 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) +#define CAN_MODULE_3 (3) + +#define CAN_MODULE_COUNT (3) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +#define HAL_LL_FDCAN3_GPIO_AF11 (11) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SDA_PB5_AF8 +#define I2C4_SCL_PA13_AF3 +#define I2C4_SDA_PB7_AF3 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) + +#define UART_MODULE_COUNT (3) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_SCK_PB3_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define HRTIM1_CHA1_PA8_AF13 +#define HRTIM1_CHA2_PA9_AF13 +#define HRTIM1_CHB1_PA10_AF13 +#define HRTIM1_CHB2_PA11_AF13 +#define HRTIM1_CHC1_PB12_AF13 +#define HRTIM1_CHC2_PB13_AF13 +#define HRTIM1_CHD1_PB14_AF13 +#define HRTIM1_CHD2_PB15_AF13 +#define LPTIM1_ETR_PB6_AF11 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_ETR_PA12_AF11 +#define TIM20_CH1_PB2_AF3 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_ETR_PB3_AF10 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH1_PB2_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH4_PA3_AF2 +#define TIM5_ETR_PB12_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) +#define TIM_MODULE_20 (10) + +#define TIM_MODULE_COUNT (10) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474CE/UFQFPN48/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474CE/UFQFPN48/mcu_definitions.h new file mode 100644 index 000000000..f3d6937a6 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474CE/UFQFPN48/mcu_definitions.h @@ -0,0 +1,423 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G474CE_UFQFPN48. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC4_CH5 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 +#define ADC4_PB12_CH3 +#define ADC4_PB14_CH4 +#define ADC4_PB15_CH5 +#define ADC5_PA8_CH1 +#define ADC5_PA9_CH2 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) +#define ADC_MODULE_4 (4) +#define ADC_MODULE_5 (5) + +#define ADC_MODULE_COUNT (5) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 +#define FDCAN3_RX_PA8_AF11 +#define FDCAN3_RX_PB3_AF11 +#define FDCAN3_TX_PA15_AF11 +#define FDCAN3_TX_PB4_AF11 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) +#define CAN_MODULE_3 (3) + +#define CAN_MODULE_COUNT (3) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +#define HAL_LL_FDCAN3_GPIO_AF11 (11) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C4_SCL_PA13_AF3 +#define I2C4_SCL_PC6_AF8 +#define I2C4_SDA_PB7_AF3 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (4) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define HRTIM1_CHA1_PA8_AF13 +#define HRTIM1_CHA2_PA9_AF13 +#define HRTIM1_CHB1_PA10_AF13 +#define HRTIM1_CHB2_PA11_AF13 +#define HRTIM1_CHC1_PB12_AF13 +#define HRTIM1_CHC2_PB13_AF13 +#define HRTIM1_CHD1_PB14_AF13 +#define HRTIM1_CHD2_PB15_AF13 +#define HRTIM1_CHF1_PC6_AF13 +#define LPTIM1_ETR_PB6_AF11 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM20_CH1_PB2_AF3 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_ETR_PB3_AF10 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH1_PB2_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH4_PA3_AF2 +#define TIM5_ETR_PB12_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) +#define TIM_MODULE_20 (10) + +#define TIM_MODULE_COUNT (10) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC10_CN +#define __PC11_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC4_CN +#define __PC6_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474MB/LQFP80/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474MB/LQFP80/mcu_definitions.h new file mode 100644 index 000000000..06d7c5d02 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474MB/LQFP80/mcu_definitions.h @@ -0,0 +1,543 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G474MB_LQFP80. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 +#define ADC3_PD10_CH7 +#define ADC3_PE10_CH14 +#define ADC3_PE11_CH15 +#define ADC3_PE12_CH16 +#define ADC3_PE13_CH3 +#define ADC3_PE7_CH4 +#define ADC3_PE8_CH6 +#define ADC3_PE9_CH2 +#define ADC4_PB12_CH3 +#define ADC4_PB14_CH4 +#define ADC4_PB15_CH5 +#define ADC4_PD10_CH7 +#define ADC4_PD8_CH12 +#define ADC4_PD9_CH13 +#define ADC4_PE10_CH14 +#define ADC4_PE11_CH15 +#define ADC4_PE12_CH16 +#define ADC4_PE14_CH1 +#define ADC4_PE15_CH2 +#define ADC4_PE8_CH6 +#define ADC5_PA8_CH1 +#define ADC5_PA9_CH2 +#define ADC5_PD10_CH7 +#define ADC5_PD8_CH12 +#define ADC5_PD9_CH13 +#define ADC5_PE10_CH14 +#define ADC5_PE11_CH15 +#define ADC5_PE12_CH16 +#define ADC5_PE8_CH6 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) +#define ADC_MODULE_4 (4) +#define ADC_MODULE_5 (5) + +#define ADC_MODULE_COUNT (5) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_RX_PD0_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN1_TX_PD1_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 +#define FDCAN3_RX_PA8_AF11 +#define FDCAN3_RX_PB3_AF11 +#define FDCAN3_TX_PA15_AF11 +#define FDCAN3_TX_PB4_AF11 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) +#define CAN_MODULE_3 (3) + +#define CAN_MODULE_COUNT (3) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +#define HAL_LL_FDCAN3_GPIO_AF11 (11) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 +#define I2C4_SCL_PA13_AF3 +#define I2C4_SCL_PC6_AF8 +#define I2C4_SDA_PB7_AF3 +#define I2C4_SDA_PC7_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define UART5_RX_PD2_AF5 +#define UART5_TX_PC12_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PD9_AF7 +#define USART3_RX_PE15_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PD8_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 +#define SPI4_MISO_PE13_AF5 +#define SPI4_MOSI_PE14_AF5 +#define SPI4_SCK_PE12_AF5 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) +#define SPI_MODULE_4 (4) + +#define SPI_MODULE_COUNT (4) +// EOF SPI + +// TIM +#define HRTIM1_CHA1_PA8_AF13 +#define HRTIM1_CHA2_PA9_AF13 +#define HRTIM1_CHB1_PA10_AF13 +#define HRTIM1_CHB2_PA11_AF13 +#define HRTIM1_CHC1_PB12_AF13 +#define HRTIM1_CHC2_PB13_AF13 +#define HRTIM1_CHD1_PB14_AF13 +#define HRTIM1_CHD2_PB15_AF13 +#define HRTIM1_CHE1_PC8_AF3 +#define HRTIM1_CHE2_PC9_AF3 +#define HRTIM1_CHF1_PC6_AF13 +#define HRTIM1_CHF2_PC7_AF13 +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN2_PE14_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_BKIN_PE15_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1N_PE8_AF2 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH1_PE9_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2N_PE10_AF2 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH2_PE11_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PE12_AF2 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH3_PE13_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4N_PE15_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_CH4_PE14_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM1_ETR_PE7_AF2 +#define TIM20_CH1_PB2_AF3 +#define TIM20_CH2_PC2_AF6 +#define TIM20_CH3_PC8_AF6 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH1_PB2_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH2_PC12_AF1 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH3_PE8_AF1 +#define TIM5_CH4_PA3_AF2 +#define TIM5_CH4_PE9_AF1 +#define TIM5_ETR_PB12_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN2_PD1_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4N_PD0_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_CH4_PD1_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) +#define TIM_MODULE_20 (10) + +#define TIM_MODULE_COUNT (10) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD2_CN +#define __PD8_CN +#define __PD9_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (7) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474MC/LQFP80/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474MC/LQFP80/mcu_definitions.h new file mode 100644 index 000000000..63349b209 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474MC/LQFP80/mcu_definitions.h @@ -0,0 +1,543 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G474MC_LQFP80. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 +#define ADC3_PD10_CH7 +#define ADC3_PE10_CH14 +#define ADC3_PE11_CH15 +#define ADC3_PE12_CH16 +#define ADC3_PE13_CH3 +#define ADC3_PE7_CH4 +#define ADC3_PE8_CH6 +#define ADC3_PE9_CH2 +#define ADC4_PB12_CH3 +#define ADC4_PB14_CH4 +#define ADC4_PB15_CH5 +#define ADC4_PD10_CH7 +#define ADC4_PD8_CH12 +#define ADC4_PD9_CH13 +#define ADC4_PE10_CH14 +#define ADC4_PE11_CH15 +#define ADC4_PE12_CH16 +#define ADC4_PE14_CH1 +#define ADC4_PE15_CH2 +#define ADC4_PE8_CH6 +#define ADC5_PA8_CH1 +#define ADC5_PA9_CH2 +#define ADC5_PD10_CH7 +#define ADC5_PD8_CH12 +#define ADC5_PD9_CH13 +#define ADC5_PE10_CH14 +#define ADC5_PE11_CH15 +#define ADC5_PE12_CH16 +#define ADC5_PE8_CH6 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) +#define ADC_MODULE_4 (4) +#define ADC_MODULE_5 (5) + +#define ADC_MODULE_COUNT (5) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_RX_PD0_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN1_TX_PD1_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 +#define FDCAN3_RX_PA8_AF11 +#define FDCAN3_RX_PB3_AF11 +#define FDCAN3_TX_PA15_AF11 +#define FDCAN3_TX_PB4_AF11 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) +#define CAN_MODULE_3 (3) + +#define CAN_MODULE_COUNT (3) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +#define HAL_LL_FDCAN3_GPIO_AF11 (11) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 +#define I2C4_SCL_PA13_AF3 +#define I2C4_SCL_PC6_AF8 +#define I2C4_SDA_PB7_AF3 +#define I2C4_SDA_PC7_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define UART5_RX_PD2_AF5 +#define UART5_TX_PC12_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PD9_AF7 +#define USART3_RX_PE15_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PD8_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 +#define SPI4_MISO_PE13_AF5 +#define SPI4_MOSI_PE14_AF5 +#define SPI4_SCK_PE12_AF5 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) +#define SPI_MODULE_4 (4) + +#define SPI_MODULE_COUNT (4) +// EOF SPI + +// TIM +#define HRTIM1_CHA1_PA8_AF13 +#define HRTIM1_CHA2_PA9_AF13 +#define HRTIM1_CHB1_PA10_AF13 +#define HRTIM1_CHB2_PA11_AF13 +#define HRTIM1_CHC1_PB12_AF13 +#define HRTIM1_CHC2_PB13_AF13 +#define HRTIM1_CHD1_PB14_AF13 +#define HRTIM1_CHD2_PB15_AF13 +#define HRTIM1_CHE1_PC8_AF3 +#define HRTIM1_CHE2_PC9_AF3 +#define HRTIM1_CHF1_PC6_AF13 +#define HRTIM1_CHF2_PC7_AF13 +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN2_PE14_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_BKIN_PE15_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1N_PE8_AF2 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH1_PE9_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2N_PE10_AF2 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH2_PE11_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PE12_AF2 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH3_PE13_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4N_PE15_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_CH4_PE14_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM1_ETR_PE7_AF2 +#define TIM20_CH1_PB2_AF3 +#define TIM20_CH2_PC2_AF6 +#define TIM20_CH3_PC8_AF6 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH1_PB2_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH2_PC12_AF1 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH3_PE8_AF1 +#define TIM5_CH4_PA3_AF2 +#define TIM5_CH4_PE9_AF1 +#define TIM5_ETR_PB12_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN2_PD1_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4N_PD0_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_CH4_PD1_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) +#define TIM_MODULE_20 (10) + +#define TIM_MODULE_COUNT (10) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD2_CN +#define __PD8_CN +#define __PD9_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (7) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474ME/LQFP80/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474ME/LQFP80/mcu_definitions.h new file mode 100644 index 000000000..12abb4154 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474ME/LQFP80/mcu_definitions.h @@ -0,0 +1,543 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G474ME_LQFP80. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 +#define ADC3_PD10_CH7 +#define ADC3_PE10_CH14 +#define ADC3_PE11_CH15 +#define ADC3_PE12_CH16 +#define ADC3_PE13_CH3 +#define ADC3_PE7_CH4 +#define ADC3_PE8_CH6 +#define ADC3_PE9_CH2 +#define ADC4_PB12_CH3 +#define ADC4_PB14_CH4 +#define ADC4_PB15_CH5 +#define ADC4_PD10_CH7 +#define ADC4_PD8_CH12 +#define ADC4_PD9_CH13 +#define ADC4_PE10_CH14 +#define ADC4_PE11_CH15 +#define ADC4_PE12_CH16 +#define ADC4_PE14_CH1 +#define ADC4_PE15_CH2 +#define ADC4_PE8_CH6 +#define ADC5_PA8_CH1 +#define ADC5_PA9_CH2 +#define ADC5_PD10_CH7 +#define ADC5_PD8_CH12 +#define ADC5_PD9_CH13 +#define ADC5_PE10_CH14 +#define ADC5_PE11_CH15 +#define ADC5_PE12_CH16 +#define ADC5_PE8_CH6 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) +#define ADC_MODULE_4 (4) +#define ADC_MODULE_5 (5) + +#define ADC_MODULE_COUNT (5) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_RX_PD0_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN1_TX_PD1_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 +#define FDCAN3_RX_PA8_AF11 +#define FDCAN3_RX_PB3_AF11 +#define FDCAN3_TX_PA15_AF11 +#define FDCAN3_TX_PB4_AF11 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) +#define CAN_MODULE_3 (3) + +#define CAN_MODULE_COUNT (3) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +#define HAL_LL_FDCAN3_GPIO_AF11 (11) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 +#define I2C4_SCL_PA13_AF3 +#define I2C4_SCL_PC6_AF8 +#define I2C4_SDA_PB7_AF3 +#define I2C4_SDA_PC7_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define UART5_RX_PD2_AF5 +#define UART5_TX_PC12_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PD9_AF7 +#define USART3_RX_PE15_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PD8_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 +#define SPI4_MISO_PE13_AF5 +#define SPI4_MOSI_PE14_AF5 +#define SPI4_SCK_PE12_AF5 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) +#define SPI_MODULE_4 (4) + +#define SPI_MODULE_COUNT (4) +// EOF SPI + +// TIM +#define HRTIM1_CHA1_PA8_AF13 +#define HRTIM1_CHA2_PA9_AF13 +#define HRTIM1_CHB1_PA10_AF13 +#define HRTIM1_CHB2_PA11_AF13 +#define HRTIM1_CHC1_PB12_AF13 +#define HRTIM1_CHC2_PB13_AF13 +#define HRTIM1_CHD1_PB14_AF13 +#define HRTIM1_CHD2_PB15_AF13 +#define HRTIM1_CHE1_PC8_AF3 +#define HRTIM1_CHE2_PC9_AF3 +#define HRTIM1_CHF1_PC6_AF13 +#define HRTIM1_CHF2_PC7_AF13 +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN2_PE14_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_BKIN_PE15_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1N_PE8_AF2 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH1_PE9_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2N_PE10_AF2 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH2_PE11_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PE12_AF2 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH3_PE13_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4N_PE15_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_CH4_PE14_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM1_ETR_PE7_AF2 +#define TIM20_CH1_PB2_AF3 +#define TIM20_CH2_PC2_AF6 +#define TIM20_CH3_PC8_AF6 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH1_PB2_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH2_PC12_AF1 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH3_PE8_AF1 +#define TIM5_CH4_PA3_AF2 +#define TIM5_CH4_PE9_AF1 +#define TIM5_ETR_PB12_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN2_PD1_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4N_PD0_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_CH4_PD1_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) +#define TIM_MODULE_20 (10) + +#define TIM_MODULE_COUNT (10) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD2_CN +#define __PD8_CN +#define __PD9_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (7) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474ME/WLCSP81/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474ME/WLCSP81/mcu_definitions.h new file mode 100644 index 000000000..be4667104 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474ME/WLCSP81/mcu_definitions.h @@ -0,0 +1,548 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G474ME_WLCSP81. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 +#define ADC3_PD10_CH7 +#define ADC3_PD11_CH8 +#define ADC3_PE10_CH14 +#define ADC3_PE11_CH15 +#define ADC3_PE12_CH16 +#define ADC3_PE13_CH3 +#define ADC3_PE7_CH4 +#define ADC3_PE8_CH6 +#define ADC3_PE9_CH2 +#define ADC4_PB12_CH3 +#define ADC4_PB14_CH4 +#define ADC4_PB15_CH5 +#define ADC4_PD10_CH7 +#define ADC4_PD11_CH8 +#define ADC4_PD8_CH12 +#define ADC4_PD9_CH13 +#define ADC4_PE10_CH14 +#define ADC4_PE11_CH15 +#define ADC4_PE12_CH16 +#define ADC4_PE14_CH1 +#define ADC4_PE15_CH2 +#define ADC4_PE8_CH6 +#define ADC5_PA8_CH1 +#define ADC5_PA9_CH2 +#define ADC5_PD10_CH7 +#define ADC5_PD11_CH8 +#define ADC5_PD8_CH12 +#define ADC5_PD9_CH13 +#define ADC5_PE10_CH14 +#define ADC5_PE11_CH15 +#define ADC5_PE12_CH16 +#define ADC5_PE8_CH6 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) +#define ADC_MODULE_4 (4) +#define ADC_MODULE_5 (5) + +#define ADC_MODULE_COUNT (5) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_RX_PD0_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN1_TX_PD1_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 +#define FDCAN3_RX_PA8_AF11 +#define FDCAN3_RX_PB3_AF11 +#define FDCAN3_TX_PA15_AF11 +#define FDCAN3_TX_PB4_AF11 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) +#define CAN_MODULE_3 (3) + +#define CAN_MODULE_COUNT (3) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +#define HAL_LL_FDCAN3_GPIO_AF11 (11) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 +#define I2C4_SCL_PA13_AF3 +#define I2C4_SCL_PC6_AF8 +#define I2C4_SDA_PB7_AF3 +#define I2C4_SDA_PC7_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define UART5_RX_PD2_AF5 +#define UART5_TX_PC12_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PD9_AF7 +#define USART3_RX_PE15_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PD8_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 +#define SPI4_MISO_PE13_AF5 +#define SPI4_MOSI_PE14_AF5 +#define SPI4_SCK_PE12_AF5 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) +#define SPI_MODULE_4 (4) + +#define SPI_MODULE_COUNT (4) +// EOF SPI + +// TIM +#define HRTIM1_CHA1_PA8_AF13 +#define HRTIM1_CHA2_PA9_AF13 +#define HRTIM1_CHB1_PA10_AF13 +#define HRTIM1_CHB2_PA11_AF13 +#define HRTIM1_CHC1_PB12_AF13 +#define HRTIM1_CHC2_PB13_AF13 +#define HRTIM1_CHD1_PB14_AF13 +#define HRTIM1_CHD2_PB15_AF13 +#define HRTIM1_CHE1_PC8_AF3 +#define HRTIM1_CHE2_PC9_AF3 +#define HRTIM1_CHF1_PC6_AF13 +#define HRTIM1_CHF2_PC7_AF13 +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN2_PE14_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_BKIN_PE15_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1N_PE8_AF2 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH1_PE9_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2N_PE10_AF2 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH2_PE11_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PE12_AF2 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH3_PE13_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4N_PE15_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_CH4_PE14_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM1_ETR_PE7_AF2 +#define TIM20_CH1_PB2_AF3 +#define TIM20_CH2_PC2_AF6 +#define TIM20_CH3_PC8_AF6 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH1_PB2_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH2_PC12_AF1 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH3_PE8_AF1 +#define TIM5_CH4_PA3_AF2 +#define TIM5_CH4_PE9_AF1 +#define TIM5_ETR_PB12_AF2 +#define TIM5_ETR_PD11_AF1 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN2_PD1_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4N_PD0_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_CH4_PD1_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) +#define TIM_MODULE_20 (10) + +#define TIM_MODULE_COUNT (10) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD11_CN +#define __PD2_CN +#define __PD8_CN +#define __PD9_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (7) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474PB/UFBGA121/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474PB/UFBGA121/mcu_definitions.h new file mode 100644 index 000000000..905bf43f3 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474PB/UFBGA121/mcu_definitions.h @@ -0,0 +1,662 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G474PB_UFBGA121. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 +#define ADC3_PD10_CH7 +#define ADC3_PD11_CH8 +#define ADC3_PD12_CH9 +#define ADC3_PD13_CH10 +#define ADC3_PD14_CH11 +#define ADC3_PE10_CH14 +#define ADC3_PE11_CH15 +#define ADC3_PE12_CH16 +#define ADC3_PE13_CH3 +#define ADC3_PE7_CH4 +#define ADC3_PE8_CH6 +#define ADC3_PE9_CH2 +#define ADC4_PB12_CH3 +#define ADC4_PB14_CH4 +#define ADC4_PB15_CH5 +#define ADC4_PD10_CH7 +#define ADC4_PD11_CH8 +#define ADC4_PD12_CH9 +#define ADC4_PD13_CH10 +#define ADC4_PD14_CH11 +#define ADC4_PD8_CH12 +#define ADC4_PD9_CH13 +#define ADC4_PE10_CH14 +#define ADC4_PE11_CH15 +#define ADC4_PE12_CH16 +#define ADC4_PE14_CH1 +#define ADC4_PE15_CH2 +#define ADC4_PE8_CH6 +#define ADC5_PA8_CH1 +#define ADC5_PA9_CH2 +#define ADC5_PD10_CH7 +#define ADC5_PD11_CH8 +#define ADC5_PD12_CH9 +#define ADC5_PD13_CH10 +#define ADC5_PD14_CH11 +#define ADC5_PD8_CH12 +#define ADC5_PD9_CH13 +#define ADC5_PE10_CH14 +#define ADC5_PE11_CH15 +#define ADC5_PE12_CH16 +#define ADC5_PE8_CH6 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) +#define ADC_MODULE_4 (4) +#define ADC_MODULE_5 (5) + +#define ADC_MODULE_COUNT (5) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_RX_PD0_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN1_TX_PD1_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 +#define FDCAN3_RX_PA8_AF11 +#define FDCAN3_RX_PB3_AF11 +#define FDCAN3_TX_PA15_AF11 +#define FDCAN3_TX_PB4_AF11 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) +#define CAN_MODULE_3 (3) + +#define CAN_MODULE_COUNT (3) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +#define HAL_LL_FDCAN3_GPIO_AF11 (11) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SCL_PF6_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SCL_PF3_AF4 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 +#define I2C3_SDA_PF4_AF4 +#define I2C4_SCL_PA13_AF3 +#define I2C4_SCL_PC6_AF8 +#define I2C4_SCL_PF14_AF4 +#define I2C4_SCL_PG3_AF4 +#define I2C4_SDA_PB7_AF3 +#define I2C4_SDA_PC7_AF8 +#define I2C4_SDA_PF15_AF4 +#define I2C4_SDA_PG4_AF4 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define UART5_RX_PD2_AF5 +#define UART5_TX_PC12_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_RX_PE1_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART1_TX_PE0_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_RX_PD6_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART2_TX_PD5_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PD9_AF7 +#define USART3_RX_PE15_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PD8_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MISO_PG3_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_MOSI_PG4_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI1_SCK_PG2_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF10_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI2_SCK_PF9_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 +#define SPI4_MISO_PE13_AF5 +#define SPI4_MISO_PE5_AF5 +#define SPI4_MOSI_PE14_AF5 +#define SPI4_MOSI_PE6_AF5 +#define SPI4_SCK_PE12_AF5 +#define SPI4_SCK_PE2_AF5 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) +#define SPI_MODULE_4 (4) + +#define SPI_MODULE_COUNT (4) +// EOF SPI + +// TIM +#define HRTIM1_CHA1_PA8_AF13 +#define HRTIM1_CHA2_PA9_AF13 +#define HRTIM1_CHB1_PA10_AF13 +#define HRTIM1_CHB2_PA11_AF13 +#define HRTIM1_CHC1_PB12_AF13 +#define HRTIM1_CHC2_PB13_AF13 +#define HRTIM1_CHD1_PB14_AF13 +#define HRTIM1_CHD2_PB15_AF13 +#define HRTIM1_CHE1_PC8_AF3 +#define HRTIM1_CHE2_PC9_AF3 +#define HRTIM1_CHF1_PC6_AF13 +#define HRTIM1_CHF2_PC7_AF13 +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH1_PF9_AF3 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM15_CH2_PF10_AF3 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM16_CH1_PE0_AF4 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM17_CH1_PE1_AF4 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN2_PE14_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_BKIN_PE15_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1N_PE8_AF2 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH1_PE9_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2N_PE10_AF2 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH2_PE11_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PE12_AF2 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH3_PE13_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4N_PE15_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_CH4_PE14_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM1_ETR_PE7_AF2 +#define TIM20_BKIN2_PF10_AF2 +#define TIM20_BKIN2_PF8_AF2 +#define TIM20_BKIN2_PG4_AF2 +#define TIM20_BKIN_PF7_AF2 +#define TIM20_BKIN_PF9_AF2 +#define TIM20_BKIN_PG3_AF2 +#define TIM20_CH1N_PE4_AF6 +#define TIM20_CH1N_PF4_AF3 +#define TIM20_CH1N_PG0_AF2 +#define TIM20_CH1_PB2_AF3 +#define TIM20_CH1_PE2_AF6 +#define TIM20_CH1_PF12_AF2 +#define TIM20_CH2N_PE5_AF6 +#define TIM20_CH2N_PF5_AF2 +#define TIM20_CH2N_PG1_AF2 +#define TIM20_CH2_PC2_AF6 +#define TIM20_CH2_PE3_AF6 +#define TIM20_CH2_PF13_AF2 +#define TIM20_CH3N_PE6_AF6 +#define TIM20_CH3N_PG2_AF2 +#define TIM20_CH3_PC8_AF6 +#define TIM20_CH3_PF14_AF2 +#define TIM20_CH3_PF2_AF2 +#define TIM20_CH4N_PE0_AF3 +#define TIM20_CH4N_PG3_AF6 +#define TIM20_CH4_PE1_AF6 +#define TIM20_CH4_PF15_AF2 +#define TIM20_CH4_PF3_AF2 +#define TIM20_ETR_PE0_AF6 +#define TIM20_ETR_PF11_AF2 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH1_PD3_AF2 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH2_PD4_AF2 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH3_PD7_AF2 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_CH4_PD6_AF2 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM2_ETR_PD3_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH1_PE2_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH2_PE3_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH3_PE4_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_CH4_PE5_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH1_PD12_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH2_PD13_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH3_PD14_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_CH4_PD15_AF2 +#define TIM4_CH4_PF6_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM4_ETR_PE0_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH1_PB2_AF2 +#define TIM5_CH1_PF6_AF6 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH2_PC12_AF1 +#define TIM5_CH2_PF7_AF6 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH3_PE8_AF1 +#define TIM5_CH3_PF8_AF6 +#define TIM5_CH4_PA3_AF2 +#define TIM5_CH4_PE9_AF1 +#define TIM5_CH4_PF9_AF6 +#define TIM5_ETR_PB12_AF2 +#define TIM5_ETR_PD11_AF1 +#define TIM5_ETR_PF6_AF1 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN2_PD1_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4N_PD0_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_CH4_PD1_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) +#define TIM_MODULE_20 (10) + +#define TIM_MODULE_COUNT (10) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PE0_CN +#define __PE1_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN +#define __PE6_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PF10_CN +#define __PF11_CN +#define __PF12_CN +#define __PF13_CN +#define __PF14_CN +#define __PF15_CN +#define __PF2_CN +#define __PF3_CN +#define __PF4_CN +#define __PF5_CN +#define __PF6_CN +#define __PF7_CN +#define __PF8_CN +#define __PF9_CN +#define __PG0_CN +#define __PG1_CN +#define __PG10_CN +#define __PG2_CN +#define __PG3_CN +#define __PG4_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (7) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474PC/UFBGA121/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474PC/UFBGA121/mcu_definitions.h new file mode 100644 index 000000000..8e83e34b3 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474PC/UFBGA121/mcu_definitions.h @@ -0,0 +1,662 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G474PC_UFBGA121. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 +#define ADC3_PD10_CH7 +#define ADC3_PD11_CH8 +#define ADC3_PD12_CH9 +#define ADC3_PD13_CH10 +#define ADC3_PD14_CH11 +#define ADC3_PE10_CH14 +#define ADC3_PE11_CH15 +#define ADC3_PE12_CH16 +#define ADC3_PE13_CH3 +#define ADC3_PE7_CH4 +#define ADC3_PE8_CH6 +#define ADC3_PE9_CH2 +#define ADC4_PB12_CH3 +#define ADC4_PB14_CH4 +#define ADC4_PB15_CH5 +#define ADC4_PD10_CH7 +#define ADC4_PD11_CH8 +#define ADC4_PD12_CH9 +#define ADC4_PD13_CH10 +#define ADC4_PD14_CH11 +#define ADC4_PD8_CH12 +#define ADC4_PD9_CH13 +#define ADC4_PE10_CH14 +#define ADC4_PE11_CH15 +#define ADC4_PE12_CH16 +#define ADC4_PE14_CH1 +#define ADC4_PE15_CH2 +#define ADC4_PE8_CH6 +#define ADC5_PA8_CH1 +#define ADC5_PA9_CH2 +#define ADC5_PD10_CH7 +#define ADC5_PD11_CH8 +#define ADC5_PD12_CH9 +#define ADC5_PD13_CH10 +#define ADC5_PD14_CH11 +#define ADC5_PD8_CH12 +#define ADC5_PD9_CH13 +#define ADC5_PE10_CH14 +#define ADC5_PE11_CH15 +#define ADC5_PE12_CH16 +#define ADC5_PE8_CH6 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) +#define ADC_MODULE_4 (4) +#define ADC_MODULE_5 (5) + +#define ADC_MODULE_COUNT (5) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_RX_PD0_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN1_TX_PD1_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 +#define FDCAN3_RX_PA8_AF11 +#define FDCAN3_RX_PB3_AF11 +#define FDCAN3_TX_PA15_AF11 +#define FDCAN3_TX_PB4_AF11 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) +#define CAN_MODULE_3 (3) + +#define CAN_MODULE_COUNT (3) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +#define HAL_LL_FDCAN3_GPIO_AF11 (11) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SCL_PF6_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SCL_PF3_AF4 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 +#define I2C3_SDA_PF4_AF4 +#define I2C4_SCL_PA13_AF3 +#define I2C4_SCL_PC6_AF8 +#define I2C4_SCL_PF14_AF4 +#define I2C4_SCL_PG3_AF4 +#define I2C4_SDA_PB7_AF3 +#define I2C4_SDA_PC7_AF8 +#define I2C4_SDA_PF15_AF4 +#define I2C4_SDA_PG4_AF4 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define UART5_RX_PD2_AF5 +#define UART5_TX_PC12_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_RX_PE1_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART1_TX_PE0_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_RX_PD6_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART2_TX_PD5_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PD9_AF7 +#define USART3_RX_PE15_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PD8_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MISO_PG3_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_MOSI_PG4_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI1_SCK_PG2_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF10_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI2_SCK_PF9_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 +#define SPI4_MISO_PE13_AF5 +#define SPI4_MISO_PE5_AF5 +#define SPI4_MOSI_PE14_AF5 +#define SPI4_MOSI_PE6_AF5 +#define SPI4_SCK_PE12_AF5 +#define SPI4_SCK_PE2_AF5 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) +#define SPI_MODULE_4 (4) + +#define SPI_MODULE_COUNT (4) +// EOF SPI + +// TIM +#define HRTIM1_CHA1_PA8_AF13 +#define HRTIM1_CHA2_PA9_AF13 +#define HRTIM1_CHB1_PA10_AF13 +#define HRTIM1_CHB2_PA11_AF13 +#define HRTIM1_CHC1_PB12_AF13 +#define HRTIM1_CHC2_PB13_AF13 +#define HRTIM1_CHD1_PB14_AF13 +#define HRTIM1_CHD2_PB15_AF13 +#define HRTIM1_CHE1_PC8_AF3 +#define HRTIM1_CHE2_PC9_AF3 +#define HRTIM1_CHF1_PC6_AF13 +#define HRTIM1_CHF2_PC7_AF13 +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH1_PF9_AF3 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM15_CH2_PF10_AF3 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM16_CH1_PE0_AF4 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM17_CH1_PE1_AF4 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN2_PE14_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_BKIN_PE15_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1N_PE8_AF2 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH1_PE9_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2N_PE10_AF2 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH2_PE11_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PE12_AF2 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH3_PE13_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4N_PE15_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_CH4_PE14_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM1_ETR_PE7_AF2 +#define TIM20_BKIN2_PF10_AF2 +#define TIM20_BKIN2_PF8_AF2 +#define TIM20_BKIN2_PG4_AF2 +#define TIM20_BKIN_PF7_AF2 +#define TIM20_BKIN_PF9_AF2 +#define TIM20_BKIN_PG3_AF2 +#define TIM20_CH1N_PE4_AF6 +#define TIM20_CH1N_PF4_AF3 +#define TIM20_CH1N_PG0_AF2 +#define TIM20_CH1_PB2_AF3 +#define TIM20_CH1_PE2_AF6 +#define TIM20_CH1_PF12_AF2 +#define TIM20_CH2N_PE5_AF6 +#define TIM20_CH2N_PF5_AF2 +#define TIM20_CH2N_PG1_AF2 +#define TIM20_CH2_PC2_AF6 +#define TIM20_CH2_PE3_AF6 +#define TIM20_CH2_PF13_AF2 +#define TIM20_CH3N_PE6_AF6 +#define TIM20_CH3N_PG2_AF2 +#define TIM20_CH3_PC8_AF6 +#define TIM20_CH3_PF14_AF2 +#define TIM20_CH3_PF2_AF2 +#define TIM20_CH4N_PE0_AF3 +#define TIM20_CH4N_PG3_AF6 +#define TIM20_CH4_PE1_AF6 +#define TIM20_CH4_PF15_AF2 +#define TIM20_CH4_PF3_AF2 +#define TIM20_ETR_PE0_AF6 +#define TIM20_ETR_PF11_AF2 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH1_PD3_AF2 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH2_PD4_AF2 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH3_PD7_AF2 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_CH4_PD6_AF2 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM2_ETR_PD3_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH1_PE2_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH2_PE3_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH3_PE4_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_CH4_PE5_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH1_PD12_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH2_PD13_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH3_PD14_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_CH4_PD15_AF2 +#define TIM4_CH4_PF6_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM4_ETR_PE0_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH1_PB2_AF2 +#define TIM5_CH1_PF6_AF6 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH2_PC12_AF1 +#define TIM5_CH2_PF7_AF6 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH3_PE8_AF1 +#define TIM5_CH3_PF8_AF6 +#define TIM5_CH4_PA3_AF2 +#define TIM5_CH4_PE9_AF1 +#define TIM5_CH4_PF9_AF6 +#define TIM5_ETR_PB12_AF2 +#define TIM5_ETR_PD11_AF1 +#define TIM5_ETR_PF6_AF1 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN2_PD1_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4N_PD0_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_CH4_PD1_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) +#define TIM_MODULE_20 (10) + +#define TIM_MODULE_COUNT (10) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PE0_CN +#define __PE1_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN +#define __PE6_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PF10_CN +#define __PF11_CN +#define __PF12_CN +#define __PF13_CN +#define __PF14_CN +#define __PF15_CN +#define __PF2_CN +#define __PF3_CN +#define __PF4_CN +#define __PF5_CN +#define __PF6_CN +#define __PF7_CN +#define __PF8_CN +#define __PF9_CN +#define __PG0_CN +#define __PG1_CN +#define __PG10_CN +#define __PG2_CN +#define __PG3_CN +#define __PG4_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (7) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474PE/UFBGA121/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474PE/UFBGA121/mcu_definitions.h new file mode 100644 index 000000000..4a4870ee7 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474PE/UFBGA121/mcu_definitions.h @@ -0,0 +1,662 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G474PE_UFBGA121. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 +#define ADC3_PD10_CH7 +#define ADC3_PD11_CH8 +#define ADC3_PD12_CH9 +#define ADC3_PD13_CH10 +#define ADC3_PD14_CH11 +#define ADC3_PE10_CH14 +#define ADC3_PE11_CH15 +#define ADC3_PE12_CH16 +#define ADC3_PE13_CH3 +#define ADC3_PE7_CH4 +#define ADC3_PE8_CH6 +#define ADC3_PE9_CH2 +#define ADC4_PB12_CH3 +#define ADC4_PB14_CH4 +#define ADC4_PB15_CH5 +#define ADC4_PD10_CH7 +#define ADC4_PD11_CH8 +#define ADC4_PD12_CH9 +#define ADC4_PD13_CH10 +#define ADC4_PD14_CH11 +#define ADC4_PD8_CH12 +#define ADC4_PD9_CH13 +#define ADC4_PE10_CH14 +#define ADC4_PE11_CH15 +#define ADC4_PE12_CH16 +#define ADC4_PE14_CH1 +#define ADC4_PE15_CH2 +#define ADC4_PE8_CH6 +#define ADC5_PA8_CH1 +#define ADC5_PA9_CH2 +#define ADC5_PD10_CH7 +#define ADC5_PD11_CH8 +#define ADC5_PD12_CH9 +#define ADC5_PD13_CH10 +#define ADC5_PD14_CH11 +#define ADC5_PD8_CH12 +#define ADC5_PD9_CH13 +#define ADC5_PE10_CH14 +#define ADC5_PE11_CH15 +#define ADC5_PE12_CH16 +#define ADC5_PE8_CH6 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) +#define ADC_MODULE_4 (4) +#define ADC_MODULE_5 (5) + +#define ADC_MODULE_COUNT (5) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_RX_PD0_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN1_TX_PD1_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 +#define FDCAN3_RX_PA8_AF11 +#define FDCAN3_RX_PB3_AF11 +#define FDCAN3_TX_PA15_AF11 +#define FDCAN3_TX_PB4_AF11 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) +#define CAN_MODULE_3 (3) + +#define CAN_MODULE_COUNT (3) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +#define HAL_LL_FDCAN3_GPIO_AF11 (11) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SCL_PF6_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SCL_PF3_AF4 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 +#define I2C3_SDA_PF4_AF4 +#define I2C4_SCL_PA13_AF3 +#define I2C4_SCL_PC6_AF8 +#define I2C4_SCL_PF14_AF4 +#define I2C4_SCL_PG3_AF4 +#define I2C4_SDA_PB7_AF3 +#define I2C4_SDA_PC7_AF8 +#define I2C4_SDA_PF15_AF4 +#define I2C4_SDA_PG4_AF4 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define UART5_RX_PD2_AF5 +#define UART5_TX_PC12_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_RX_PE1_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART1_TX_PE0_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_RX_PD6_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART2_TX_PD5_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PD9_AF7 +#define USART3_RX_PE15_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PD8_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MISO_PG3_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_MOSI_PG4_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI1_SCK_PG2_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF10_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI2_SCK_PF9_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 +#define SPI4_MISO_PE13_AF5 +#define SPI4_MISO_PE5_AF5 +#define SPI4_MOSI_PE14_AF5 +#define SPI4_MOSI_PE6_AF5 +#define SPI4_SCK_PE12_AF5 +#define SPI4_SCK_PE2_AF5 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) +#define SPI_MODULE_4 (4) + +#define SPI_MODULE_COUNT (4) +// EOF SPI + +// TIM +#define HRTIM1_CHA1_PA8_AF13 +#define HRTIM1_CHA2_PA9_AF13 +#define HRTIM1_CHB1_PA10_AF13 +#define HRTIM1_CHB2_PA11_AF13 +#define HRTIM1_CHC1_PB12_AF13 +#define HRTIM1_CHC2_PB13_AF13 +#define HRTIM1_CHD1_PB14_AF13 +#define HRTIM1_CHD2_PB15_AF13 +#define HRTIM1_CHE1_PC8_AF3 +#define HRTIM1_CHE2_PC9_AF3 +#define HRTIM1_CHF1_PC6_AF13 +#define HRTIM1_CHF2_PC7_AF13 +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH1_PF9_AF3 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM15_CH2_PF10_AF3 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM16_CH1_PE0_AF4 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM17_CH1_PE1_AF4 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN2_PE14_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_BKIN_PE15_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1N_PE8_AF2 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH1_PE9_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2N_PE10_AF2 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH2_PE11_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PE12_AF2 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH3_PE13_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4N_PE15_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_CH4_PE14_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM1_ETR_PE7_AF2 +#define TIM20_BKIN2_PF10_AF2 +#define TIM20_BKIN2_PF8_AF2 +#define TIM20_BKIN2_PG4_AF2 +#define TIM20_BKIN_PF7_AF2 +#define TIM20_BKIN_PF9_AF2 +#define TIM20_BKIN_PG3_AF2 +#define TIM20_CH1N_PE4_AF6 +#define TIM20_CH1N_PF4_AF3 +#define TIM20_CH1N_PG0_AF2 +#define TIM20_CH1_PB2_AF3 +#define TIM20_CH1_PE2_AF6 +#define TIM20_CH1_PF12_AF2 +#define TIM20_CH2N_PE5_AF6 +#define TIM20_CH2N_PF5_AF2 +#define TIM20_CH2N_PG1_AF2 +#define TIM20_CH2_PC2_AF6 +#define TIM20_CH2_PE3_AF6 +#define TIM20_CH2_PF13_AF2 +#define TIM20_CH3N_PE6_AF6 +#define TIM20_CH3N_PG2_AF2 +#define TIM20_CH3_PC8_AF6 +#define TIM20_CH3_PF14_AF2 +#define TIM20_CH3_PF2_AF2 +#define TIM20_CH4N_PE0_AF3 +#define TIM20_CH4N_PG3_AF6 +#define TIM20_CH4_PE1_AF6 +#define TIM20_CH4_PF15_AF2 +#define TIM20_CH4_PF3_AF2 +#define TIM20_ETR_PE0_AF6 +#define TIM20_ETR_PF11_AF2 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH1_PD3_AF2 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH2_PD4_AF2 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH3_PD7_AF2 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_CH4_PD6_AF2 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM2_ETR_PD3_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH1_PE2_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH2_PE3_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH3_PE4_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_CH4_PE5_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH1_PD12_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH2_PD13_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH3_PD14_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_CH4_PD15_AF2 +#define TIM4_CH4_PF6_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM4_ETR_PE0_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH1_PB2_AF2 +#define TIM5_CH1_PF6_AF6 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH2_PC12_AF1 +#define TIM5_CH2_PF7_AF6 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH3_PE8_AF1 +#define TIM5_CH3_PF8_AF6 +#define TIM5_CH4_PA3_AF2 +#define TIM5_CH4_PE9_AF1 +#define TIM5_CH4_PF9_AF6 +#define TIM5_ETR_PB12_AF2 +#define TIM5_ETR_PD11_AF1 +#define TIM5_ETR_PF6_AF1 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN2_PD1_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4N_PD0_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_CH4_PD1_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) +#define TIM_MODULE_20 (10) + +#define TIM_MODULE_COUNT (10) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PE0_CN +#define __PE1_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN +#define __PE6_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PF10_CN +#define __PF11_CN +#define __PF12_CN +#define __PF13_CN +#define __PF14_CN +#define __PF15_CN +#define __PF2_CN +#define __PF3_CN +#define __PF4_CN +#define __PF5_CN +#define __PF6_CN +#define __PF7_CN +#define __PF8_CN +#define __PF9_CN +#define __PG0_CN +#define __PG1_CN +#define __PG10_CN +#define __PG2_CN +#define __PG3_CN +#define __PG4_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (7) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474QB/LQFP128/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474QB/LQFP128/mcu_definitions.h new file mode 100644 index 000000000..a2bfa16f3 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474QB/LQFP128/mcu_definitions.h @@ -0,0 +1,676 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G474QB_LQFP128. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 +#define ADC3_PD10_CH7 +#define ADC3_PD11_CH8 +#define ADC3_PD12_CH9 +#define ADC3_PD13_CH10 +#define ADC3_PD14_CH11 +#define ADC3_PE10_CH14 +#define ADC3_PE11_CH15 +#define ADC3_PE12_CH16 +#define ADC3_PE13_CH3 +#define ADC3_PE7_CH4 +#define ADC3_PE8_CH6 +#define ADC3_PE9_CH2 +#define ADC4_PB12_CH3 +#define ADC4_PB14_CH4 +#define ADC4_PB15_CH5 +#define ADC4_PD10_CH7 +#define ADC4_PD11_CH8 +#define ADC4_PD12_CH9 +#define ADC4_PD13_CH10 +#define ADC4_PD14_CH11 +#define ADC4_PD8_CH12 +#define ADC4_PD9_CH13 +#define ADC4_PE10_CH14 +#define ADC4_PE11_CH15 +#define ADC4_PE12_CH16 +#define ADC4_PE14_CH1 +#define ADC4_PE15_CH2 +#define ADC4_PE8_CH6 +#define ADC5_PA8_CH1 +#define ADC5_PA9_CH2 +#define ADC5_PD10_CH7 +#define ADC5_PD11_CH8 +#define ADC5_PD12_CH9 +#define ADC5_PD13_CH10 +#define ADC5_PD14_CH11 +#define ADC5_PD8_CH12 +#define ADC5_PD9_CH13 +#define ADC5_PE10_CH14 +#define ADC5_PE11_CH15 +#define ADC5_PE12_CH16 +#define ADC5_PE8_CH6 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) +#define ADC_MODULE_4 (4) +#define ADC_MODULE_5 (5) + +#define ADC_MODULE_COUNT (5) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_RX_PD0_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN1_TX_PD1_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 +#define FDCAN3_RX_PA8_AF11 +#define FDCAN3_RX_PB3_AF11 +#define FDCAN3_TX_PA15_AF11 +#define FDCAN3_TX_PB4_AF11 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) +#define CAN_MODULE_3 (3) + +#define CAN_MODULE_COUNT (3) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +#define HAL_LL_FDCAN3_GPIO_AF11 (11) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SCL_PF6_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SCL_PF3_AF4 +#define I2C3_SCL_PG7_AF4 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 +#define I2C3_SDA_PF4_AF4 +#define I2C3_SDA_PG8_AF4 +#define I2C4_SCL_PA13_AF3 +#define I2C4_SCL_PC6_AF8 +#define I2C4_SCL_PF14_AF4 +#define I2C4_SCL_PG3_AF4 +#define I2C4_SDA_PB7_AF3 +#define I2C4_SDA_PC7_AF8 +#define I2C4_SDA_PF15_AF4 +#define I2C4_SDA_PG4_AF4 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_RX_PG8_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define LPUART1_TX_PG7_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define UART5_RX_PD2_AF5 +#define UART5_TX_PC12_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_RX_PE1_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART1_TX_PE0_AF7 +#define USART1_TX_PG9_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_RX_PD6_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART2_TX_PD5_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PD9_AF7 +#define USART3_RX_PE15_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PD8_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MISO_PG3_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_MOSI_PG4_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI1_SCK_PG2_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF10_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI2_SCK_PF9_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 +#define SPI3_SCK_PG9_AF6 +#define SPI4_MISO_PE13_AF5 +#define SPI4_MISO_PE5_AF5 +#define SPI4_MOSI_PE14_AF5 +#define SPI4_MOSI_PE6_AF5 +#define SPI4_SCK_PE12_AF5 +#define SPI4_SCK_PE2_AF5 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) +#define SPI_MODULE_4 (4) + +#define SPI_MODULE_COUNT (4) +// EOF SPI + +// TIM +#define HRTIM1_CHA1_PA8_AF13 +#define HRTIM1_CHA2_PA9_AF13 +#define HRTIM1_CHB1_PA10_AF13 +#define HRTIM1_CHB2_PA11_AF13 +#define HRTIM1_CHC1_PB12_AF13 +#define HRTIM1_CHC2_PB13_AF13 +#define HRTIM1_CHD1_PB14_AF13 +#define HRTIM1_CHD2_PB15_AF13 +#define HRTIM1_CHE1_PC8_AF3 +#define HRTIM1_CHE2_PC9_AF3 +#define HRTIM1_CHF1_PC6_AF13 +#define HRTIM1_CHF2_PC7_AF13 +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1N_PG9_AF14 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH1_PF9_AF3 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM15_CH2_PF10_AF3 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM16_CH1_PE0_AF4 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM17_CH1_PE1_AF4 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN2_PE14_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_BKIN_PE15_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1N_PE8_AF2 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH1_PE9_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2N_PE10_AF2 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH2_PE11_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PE12_AF2 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH3_PE13_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4N_PE15_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_CH4_PE14_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM1_ETR_PE7_AF2 +#define TIM20_BKIN2_PF10_AF2 +#define TIM20_BKIN2_PF8_AF2 +#define TIM20_BKIN2_PG4_AF2 +#define TIM20_BKIN_PF7_AF2 +#define TIM20_BKIN_PF9_AF2 +#define TIM20_BKIN_PG3_AF2 +#define TIM20_BKIN_PG6_AF2 +#define TIM20_CH1N_PE4_AF6 +#define TIM20_CH1N_PF4_AF3 +#define TIM20_CH1N_PG0_AF2 +#define TIM20_CH1_PB2_AF3 +#define TIM20_CH1_PE2_AF6 +#define TIM20_CH1_PF12_AF2 +#define TIM20_CH2N_PE5_AF6 +#define TIM20_CH2N_PF5_AF2 +#define TIM20_CH2N_PG1_AF2 +#define TIM20_CH2_PC2_AF6 +#define TIM20_CH2_PE3_AF6 +#define TIM20_CH2_PF13_AF2 +#define TIM20_CH3N_PE6_AF6 +#define TIM20_CH3N_PG2_AF2 +#define TIM20_CH3_PC8_AF6 +#define TIM20_CH3_PF14_AF2 +#define TIM20_CH3_PF2_AF2 +#define TIM20_CH4N_PE0_AF3 +#define TIM20_CH4N_PG3_AF6 +#define TIM20_CH4_PE1_AF6 +#define TIM20_CH4_PF15_AF2 +#define TIM20_CH4_PF3_AF2 +#define TIM20_ETR_PE0_AF6 +#define TIM20_ETR_PF11_AF2 +#define TIM20_ETR_PG5_AF2 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH1_PD3_AF2 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH2_PD4_AF2 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH3_PD7_AF2 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_CH4_PD6_AF2 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM2_ETR_PD3_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH1_PE2_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH2_PE3_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH3_PE4_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_CH4_PE5_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH1_PD12_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH2_PD13_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH3_PD14_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_CH4_PD15_AF2 +#define TIM4_CH4_PF6_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM4_ETR_PE0_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH1_PB2_AF2 +#define TIM5_CH1_PF6_AF6 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH2_PC12_AF1 +#define TIM5_CH2_PF7_AF6 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH3_PE8_AF1 +#define TIM5_CH3_PF8_AF6 +#define TIM5_CH4_PA3_AF2 +#define TIM5_CH4_PE9_AF1 +#define TIM5_CH4_PF9_AF6 +#define TIM5_ETR_PB12_AF2 +#define TIM5_ETR_PD11_AF1 +#define TIM5_ETR_PF6_AF1 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN2_PD1_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4N_PD0_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_CH4_PD1_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) +#define TIM_MODULE_20 (10) + +#define TIM_MODULE_COUNT (10) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PE0_CN +#define __PE1_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN +#define __PE6_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PF10_CN +#define __PF11_CN +#define __PF12_CN +#define __PF13_CN +#define __PF14_CN +#define __PF15_CN +#define __PF2_CN +#define __PF3_CN +#define __PF4_CN +#define __PF5_CN +#define __PF6_CN +#define __PF7_CN +#define __PF8_CN +#define __PF9_CN +#define __PG0_CN +#define __PG1_CN +#define __PG10_CN +#define __PG2_CN +#define __PG3_CN +#define __PG4_CN +#define __PG5_CN +#define __PG6_CN +#define __PG7_CN +#define __PG8_CN +#define __PG9_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (7) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474QC/LQFP128/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474QC/LQFP128/mcu_definitions.h new file mode 100644 index 000000000..ceac48189 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474QC/LQFP128/mcu_definitions.h @@ -0,0 +1,676 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G474QC_LQFP128. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 +#define ADC3_PD10_CH7 +#define ADC3_PD11_CH8 +#define ADC3_PD12_CH9 +#define ADC3_PD13_CH10 +#define ADC3_PD14_CH11 +#define ADC3_PE10_CH14 +#define ADC3_PE11_CH15 +#define ADC3_PE12_CH16 +#define ADC3_PE13_CH3 +#define ADC3_PE7_CH4 +#define ADC3_PE8_CH6 +#define ADC3_PE9_CH2 +#define ADC4_PB12_CH3 +#define ADC4_PB14_CH4 +#define ADC4_PB15_CH5 +#define ADC4_PD10_CH7 +#define ADC4_PD11_CH8 +#define ADC4_PD12_CH9 +#define ADC4_PD13_CH10 +#define ADC4_PD14_CH11 +#define ADC4_PD8_CH12 +#define ADC4_PD9_CH13 +#define ADC4_PE10_CH14 +#define ADC4_PE11_CH15 +#define ADC4_PE12_CH16 +#define ADC4_PE14_CH1 +#define ADC4_PE15_CH2 +#define ADC4_PE8_CH6 +#define ADC5_PA8_CH1 +#define ADC5_PA9_CH2 +#define ADC5_PD10_CH7 +#define ADC5_PD11_CH8 +#define ADC5_PD12_CH9 +#define ADC5_PD13_CH10 +#define ADC5_PD14_CH11 +#define ADC5_PD8_CH12 +#define ADC5_PD9_CH13 +#define ADC5_PE10_CH14 +#define ADC5_PE11_CH15 +#define ADC5_PE12_CH16 +#define ADC5_PE8_CH6 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) +#define ADC_MODULE_4 (4) +#define ADC_MODULE_5 (5) + +#define ADC_MODULE_COUNT (5) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_RX_PD0_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN1_TX_PD1_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 +#define FDCAN3_RX_PA8_AF11 +#define FDCAN3_RX_PB3_AF11 +#define FDCAN3_TX_PA15_AF11 +#define FDCAN3_TX_PB4_AF11 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) +#define CAN_MODULE_3 (3) + +#define CAN_MODULE_COUNT (3) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +#define HAL_LL_FDCAN3_GPIO_AF11 (11) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SCL_PF6_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SCL_PF3_AF4 +#define I2C3_SCL_PG7_AF4 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 +#define I2C3_SDA_PF4_AF4 +#define I2C3_SDA_PG8_AF4 +#define I2C4_SCL_PA13_AF3 +#define I2C4_SCL_PC6_AF8 +#define I2C4_SCL_PF14_AF4 +#define I2C4_SCL_PG3_AF4 +#define I2C4_SDA_PB7_AF3 +#define I2C4_SDA_PC7_AF8 +#define I2C4_SDA_PF15_AF4 +#define I2C4_SDA_PG4_AF4 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_RX_PG8_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define LPUART1_TX_PG7_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define UART5_RX_PD2_AF5 +#define UART5_TX_PC12_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_RX_PE1_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART1_TX_PE0_AF7 +#define USART1_TX_PG9_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_RX_PD6_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART2_TX_PD5_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PD9_AF7 +#define USART3_RX_PE15_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PD8_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MISO_PG3_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_MOSI_PG4_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI1_SCK_PG2_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF10_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI2_SCK_PF9_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 +#define SPI3_SCK_PG9_AF6 +#define SPI4_MISO_PE13_AF5 +#define SPI4_MISO_PE5_AF5 +#define SPI4_MOSI_PE14_AF5 +#define SPI4_MOSI_PE6_AF5 +#define SPI4_SCK_PE12_AF5 +#define SPI4_SCK_PE2_AF5 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) +#define SPI_MODULE_4 (4) + +#define SPI_MODULE_COUNT (4) +// EOF SPI + +// TIM +#define HRTIM1_CHA1_PA8_AF13 +#define HRTIM1_CHA2_PA9_AF13 +#define HRTIM1_CHB1_PA10_AF13 +#define HRTIM1_CHB2_PA11_AF13 +#define HRTIM1_CHC1_PB12_AF13 +#define HRTIM1_CHC2_PB13_AF13 +#define HRTIM1_CHD1_PB14_AF13 +#define HRTIM1_CHD2_PB15_AF13 +#define HRTIM1_CHE1_PC8_AF3 +#define HRTIM1_CHE2_PC9_AF3 +#define HRTIM1_CHF1_PC6_AF13 +#define HRTIM1_CHF2_PC7_AF13 +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1N_PG9_AF14 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH1_PF9_AF3 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM15_CH2_PF10_AF3 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM16_CH1_PE0_AF4 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM17_CH1_PE1_AF4 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN2_PE14_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_BKIN_PE15_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1N_PE8_AF2 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH1_PE9_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2N_PE10_AF2 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH2_PE11_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PE12_AF2 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH3_PE13_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4N_PE15_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_CH4_PE14_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM1_ETR_PE7_AF2 +#define TIM20_BKIN2_PF10_AF2 +#define TIM20_BKIN2_PF8_AF2 +#define TIM20_BKIN2_PG4_AF2 +#define TIM20_BKIN_PF7_AF2 +#define TIM20_BKIN_PF9_AF2 +#define TIM20_BKIN_PG3_AF2 +#define TIM20_BKIN_PG6_AF2 +#define TIM20_CH1N_PE4_AF6 +#define TIM20_CH1N_PF4_AF3 +#define TIM20_CH1N_PG0_AF2 +#define TIM20_CH1_PB2_AF3 +#define TIM20_CH1_PE2_AF6 +#define TIM20_CH1_PF12_AF2 +#define TIM20_CH2N_PE5_AF6 +#define TIM20_CH2N_PF5_AF2 +#define TIM20_CH2N_PG1_AF2 +#define TIM20_CH2_PC2_AF6 +#define TIM20_CH2_PE3_AF6 +#define TIM20_CH2_PF13_AF2 +#define TIM20_CH3N_PE6_AF6 +#define TIM20_CH3N_PG2_AF2 +#define TIM20_CH3_PC8_AF6 +#define TIM20_CH3_PF14_AF2 +#define TIM20_CH3_PF2_AF2 +#define TIM20_CH4N_PE0_AF3 +#define TIM20_CH4N_PG3_AF6 +#define TIM20_CH4_PE1_AF6 +#define TIM20_CH4_PF15_AF2 +#define TIM20_CH4_PF3_AF2 +#define TIM20_ETR_PE0_AF6 +#define TIM20_ETR_PF11_AF2 +#define TIM20_ETR_PG5_AF2 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH1_PD3_AF2 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH2_PD4_AF2 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH3_PD7_AF2 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_CH4_PD6_AF2 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM2_ETR_PD3_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH1_PE2_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH2_PE3_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH3_PE4_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_CH4_PE5_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH1_PD12_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH2_PD13_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH3_PD14_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_CH4_PD15_AF2 +#define TIM4_CH4_PF6_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM4_ETR_PE0_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH1_PB2_AF2 +#define TIM5_CH1_PF6_AF6 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH2_PC12_AF1 +#define TIM5_CH2_PF7_AF6 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH3_PE8_AF1 +#define TIM5_CH3_PF8_AF6 +#define TIM5_CH4_PA3_AF2 +#define TIM5_CH4_PE9_AF1 +#define TIM5_CH4_PF9_AF6 +#define TIM5_ETR_PB12_AF2 +#define TIM5_ETR_PD11_AF1 +#define TIM5_ETR_PF6_AF1 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN2_PD1_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4N_PD0_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_CH4_PD1_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) +#define TIM_MODULE_20 (10) + +#define TIM_MODULE_COUNT (10) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PE0_CN +#define __PE1_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN +#define __PE6_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PF10_CN +#define __PF11_CN +#define __PF12_CN +#define __PF13_CN +#define __PF14_CN +#define __PF15_CN +#define __PF2_CN +#define __PF3_CN +#define __PF4_CN +#define __PF5_CN +#define __PF6_CN +#define __PF7_CN +#define __PF8_CN +#define __PF9_CN +#define __PG0_CN +#define __PG1_CN +#define __PG10_CN +#define __PG2_CN +#define __PG3_CN +#define __PG4_CN +#define __PG5_CN +#define __PG6_CN +#define __PG7_CN +#define __PG8_CN +#define __PG9_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (7) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474QE/LQFP128/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474QE/LQFP128/mcu_definitions.h new file mode 100644 index 000000000..7892e47c2 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474QE/LQFP128/mcu_definitions.h @@ -0,0 +1,676 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G474QE_LQFP128. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 +#define ADC3_PD10_CH7 +#define ADC3_PD11_CH8 +#define ADC3_PD12_CH9 +#define ADC3_PD13_CH10 +#define ADC3_PD14_CH11 +#define ADC3_PE10_CH14 +#define ADC3_PE11_CH15 +#define ADC3_PE12_CH16 +#define ADC3_PE13_CH3 +#define ADC3_PE7_CH4 +#define ADC3_PE8_CH6 +#define ADC3_PE9_CH2 +#define ADC4_PB12_CH3 +#define ADC4_PB14_CH4 +#define ADC4_PB15_CH5 +#define ADC4_PD10_CH7 +#define ADC4_PD11_CH8 +#define ADC4_PD12_CH9 +#define ADC4_PD13_CH10 +#define ADC4_PD14_CH11 +#define ADC4_PD8_CH12 +#define ADC4_PD9_CH13 +#define ADC4_PE10_CH14 +#define ADC4_PE11_CH15 +#define ADC4_PE12_CH16 +#define ADC4_PE14_CH1 +#define ADC4_PE15_CH2 +#define ADC4_PE8_CH6 +#define ADC5_PA8_CH1 +#define ADC5_PA9_CH2 +#define ADC5_PD10_CH7 +#define ADC5_PD11_CH8 +#define ADC5_PD12_CH9 +#define ADC5_PD13_CH10 +#define ADC5_PD14_CH11 +#define ADC5_PD8_CH12 +#define ADC5_PD9_CH13 +#define ADC5_PE10_CH14 +#define ADC5_PE11_CH15 +#define ADC5_PE12_CH16 +#define ADC5_PE8_CH6 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) +#define ADC_MODULE_4 (4) +#define ADC_MODULE_5 (5) + +#define ADC_MODULE_COUNT (5) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_RX_PD0_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN1_TX_PD1_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 +#define FDCAN3_RX_PA8_AF11 +#define FDCAN3_RX_PB3_AF11 +#define FDCAN3_TX_PA15_AF11 +#define FDCAN3_TX_PB4_AF11 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) +#define CAN_MODULE_3 (3) + +#define CAN_MODULE_COUNT (3) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +#define HAL_LL_FDCAN3_GPIO_AF11 (11) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SCL_PF6_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SCL_PF3_AF4 +#define I2C3_SCL_PG7_AF4 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 +#define I2C3_SDA_PF4_AF4 +#define I2C3_SDA_PG8_AF4 +#define I2C4_SCL_PA13_AF3 +#define I2C4_SCL_PC6_AF8 +#define I2C4_SCL_PF14_AF4 +#define I2C4_SCL_PG3_AF4 +#define I2C4_SDA_PB7_AF3 +#define I2C4_SDA_PC7_AF8 +#define I2C4_SDA_PF15_AF4 +#define I2C4_SDA_PG4_AF4 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_RX_PG8_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define LPUART1_TX_PG7_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define UART5_RX_PD2_AF5 +#define UART5_TX_PC12_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_RX_PE1_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART1_TX_PE0_AF7 +#define USART1_TX_PG9_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_RX_PD6_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART2_TX_PD5_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PD9_AF7 +#define USART3_RX_PE15_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PD8_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MISO_PG3_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_MOSI_PG4_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI1_SCK_PG2_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF10_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI2_SCK_PF9_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 +#define SPI3_SCK_PG9_AF6 +#define SPI4_MISO_PE13_AF5 +#define SPI4_MISO_PE5_AF5 +#define SPI4_MOSI_PE14_AF5 +#define SPI4_MOSI_PE6_AF5 +#define SPI4_SCK_PE12_AF5 +#define SPI4_SCK_PE2_AF5 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) +#define SPI_MODULE_4 (4) + +#define SPI_MODULE_COUNT (4) +// EOF SPI + +// TIM +#define HRTIM1_CHA1_PA8_AF13 +#define HRTIM1_CHA2_PA9_AF13 +#define HRTIM1_CHB1_PA10_AF13 +#define HRTIM1_CHB2_PA11_AF13 +#define HRTIM1_CHC1_PB12_AF13 +#define HRTIM1_CHC2_PB13_AF13 +#define HRTIM1_CHD1_PB14_AF13 +#define HRTIM1_CHD2_PB15_AF13 +#define HRTIM1_CHE1_PC8_AF3 +#define HRTIM1_CHE2_PC9_AF3 +#define HRTIM1_CHF1_PC6_AF13 +#define HRTIM1_CHF2_PC7_AF13 +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1N_PG9_AF14 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH1_PF9_AF3 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM15_CH2_PF10_AF3 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM16_CH1_PE0_AF4 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM17_CH1_PE1_AF4 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN2_PE14_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_BKIN_PE15_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1N_PE8_AF2 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH1_PE9_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2N_PE10_AF2 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH2_PE11_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PE12_AF2 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH3_PE13_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4N_PE15_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_CH4_PE14_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM1_ETR_PE7_AF2 +#define TIM20_BKIN2_PF10_AF2 +#define TIM20_BKIN2_PF8_AF2 +#define TIM20_BKIN2_PG4_AF2 +#define TIM20_BKIN_PF7_AF2 +#define TIM20_BKIN_PF9_AF2 +#define TIM20_BKIN_PG3_AF2 +#define TIM20_BKIN_PG6_AF2 +#define TIM20_CH1N_PE4_AF6 +#define TIM20_CH1N_PF4_AF3 +#define TIM20_CH1N_PG0_AF2 +#define TIM20_CH1_PB2_AF3 +#define TIM20_CH1_PE2_AF6 +#define TIM20_CH1_PF12_AF2 +#define TIM20_CH2N_PE5_AF6 +#define TIM20_CH2N_PF5_AF2 +#define TIM20_CH2N_PG1_AF2 +#define TIM20_CH2_PC2_AF6 +#define TIM20_CH2_PE3_AF6 +#define TIM20_CH2_PF13_AF2 +#define TIM20_CH3N_PE6_AF6 +#define TIM20_CH3N_PG2_AF2 +#define TIM20_CH3_PC8_AF6 +#define TIM20_CH3_PF14_AF2 +#define TIM20_CH3_PF2_AF2 +#define TIM20_CH4N_PE0_AF3 +#define TIM20_CH4N_PG3_AF6 +#define TIM20_CH4_PE1_AF6 +#define TIM20_CH4_PF15_AF2 +#define TIM20_CH4_PF3_AF2 +#define TIM20_ETR_PE0_AF6 +#define TIM20_ETR_PF11_AF2 +#define TIM20_ETR_PG5_AF2 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH1_PD3_AF2 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH2_PD4_AF2 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH3_PD7_AF2 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_CH4_PD6_AF2 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM2_ETR_PD3_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH1_PE2_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH2_PE3_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH3_PE4_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_CH4_PE5_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH1_PD12_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH2_PD13_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH3_PD14_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_CH4_PD15_AF2 +#define TIM4_CH4_PF6_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM4_ETR_PE0_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH1_PB2_AF2 +#define TIM5_CH1_PF6_AF6 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH2_PC12_AF1 +#define TIM5_CH2_PF7_AF6 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH3_PE8_AF1 +#define TIM5_CH3_PF8_AF6 +#define TIM5_CH4_PA3_AF2 +#define TIM5_CH4_PE9_AF1 +#define TIM5_CH4_PF9_AF6 +#define TIM5_ETR_PB12_AF2 +#define TIM5_ETR_PD11_AF1 +#define TIM5_ETR_PF6_AF1 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN2_PD1_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4N_PD0_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_CH4_PD1_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) +#define TIM_MODULE_20 (10) + +#define TIM_MODULE_COUNT (10) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PE0_CN +#define __PE1_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN +#define __PE6_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PF10_CN +#define __PF11_CN +#define __PF12_CN +#define __PF13_CN +#define __PF14_CN +#define __PF15_CN +#define __PF2_CN +#define __PF3_CN +#define __PF4_CN +#define __PF5_CN +#define __PF6_CN +#define __PF7_CN +#define __PF8_CN +#define __PF9_CN +#define __PG0_CN +#define __PG1_CN +#define __PG10_CN +#define __PG2_CN +#define __PG3_CN +#define __PG4_CN +#define __PG5_CN +#define __PG6_CN +#define __PG7_CN +#define __PG8_CN +#define __PG9_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (7) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474RB/LQFP64/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474RB/LQFP64/mcu_definitions.h new file mode 100644 index 000000000..4cf7960f1 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474RB/LQFP64/mcu_definitions.h @@ -0,0 +1,479 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G474RB_LQFP64. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 +#define ADC4_PB12_CH3 +#define ADC4_PB14_CH4 +#define ADC4_PB15_CH5 +#define ADC5_PA8_CH1 +#define ADC5_PA9_CH2 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) +#define ADC_MODULE_4 (4) +#define ADC_MODULE_5 (5) + +#define ADC_MODULE_COUNT (5) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 +#define FDCAN3_RX_PA8_AF11 +#define FDCAN3_RX_PB3_AF11 +#define FDCAN3_TX_PA15_AF11 +#define FDCAN3_TX_PB4_AF11 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) +#define CAN_MODULE_3 (3) + +#define CAN_MODULE_COUNT (3) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +#define HAL_LL_FDCAN3_GPIO_AF11 (11) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 +#define I2C4_SCL_PA13_AF3 +#define I2C4_SCL_PC6_AF8 +#define I2C4_SDA_PB7_AF3 +#define I2C4_SDA_PC7_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define UART5_RX_PD2_AF5 +#define UART5_TX_PC12_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define HRTIM1_CHA1_PA8_AF13 +#define HRTIM1_CHA2_PA9_AF13 +#define HRTIM1_CHB1_PA10_AF13 +#define HRTIM1_CHB2_PA11_AF13 +#define HRTIM1_CHC1_PB12_AF13 +#define HRTIM1_CHC2_PB13_AF13 +#define HRTIM1_CHD1_PB14_AF13 +#define HRTIM1_CHD2_PB15_AF13 +#define HRTIM1_CHE1_PC8_AF3 +#define HRTIM1_CHE2_PC9_AF3 +#define HRTIM1_CHF1_PC6_AF13 +#define HRTIM1_CHF2_PC7_AF13 +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM20_CH1_PB2_AF3 +#define TIM20_CH2_PC2_AF6 +#define TIM20_CH3_PC8_AF6 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH1_PB2_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH2_PC12_AF1 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH4_PA3_AF2 +#define TIM5_ETR_PB12_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) +#define TIM_MODULE_20 (10) + +#define TIM_MODULE_COUNT (10) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD2_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (6) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474RC/LQFP64/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474RC/LQFP64/mcu_definitions.h new file mode 100644 index 000000000..dec0b9d3f --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474RC/LQFP64/mcu_definitions.h @@ -0,0 +1,479 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G474RC_LQFP64. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 +#define ADC4_PB12_CH3 +#define ADC4_PB14_CH4 +#define ADC4_PB15_CH5 +#define ADC5_PA8_CH1 +#define ADC5_PA9_CH2 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) +#define ADC_MODULE_4 (4) +#define ADC_MODULE_5 (5) + +#define ADC_MODULE_COUNT (5) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 +#define FDCAN3_RX_PA8_AF11 +#define FDCAN3_RX_PB3_AF11 +#define FDCAN3_TX_PA15_AF11 +#define FDCAN3_TX_PB4_AF11 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) +#define CAN_MODULE_3 (3) + +#define CAN_MODULE_COUNT (3) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +#define HAL_LL_FDCAN3_GPIO_AF11 (11) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 +#define I2C4_SCL_PA13_AF3 +#define I2C4_SCL_PC6_AF8 +#define I2C4_SDA_PB7_AF3 +#define I2C4_SDA_PC7_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define UART5_RX_PD2_AF5 +#define UART5_TX_PC12_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define HRTIM1_CHA1_PA8_AF13 +#define HRTIM1_CHA2_PA9_AF13 +#define HRTIM1_CHB1_PA10_AF13 +#define HRTIM1_CHB2_PA11_AF13 +#define HRTIM1_CHC1_PB12_AF13 +#define HRTIM1_CHC2_PB13_AF13 +#define HRTIM1_CHD1_PB14_AF13 +#define HRTIM1_CHD2_PB15_AF13 +#define HRTIM1_CHE1_PC8_AF3 +#define HRTIM1_CHE2_PC9_AF3 +#define HRTIM1_CHF1_PC6_AF13 +#define HRTIM1_CHF2_PC7_AF13 +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM20_CH1_PB2_AF3 +#define TIM20_CH2_PC2_AF6 +#define TIM20_CH3_PC8_AF6 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH1_PB2_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH2_PC12_AF1 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH4_PA3_AF2 +#define TIM5_ETR_PB12_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) +#define TIM_MODULE_20 (10) + +#define TIM_MODULE_COUNT (10) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD2_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (6) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474RE/LQFP64/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474RE/LQFP64/mcu_definitions.h new file mode 100644 index 000000000..bf6fb4d47 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474RE/LQFP64/mcu_definitions.h @@ -0,0 +1,479 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G474RE_LQFP64. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 +#define ADC4_PB12_CH3 +#define ADC4_PB14_CH4 +#define ADC4_PB15_CH5 +#define ADC5_PA8_CH1 +#define ADC5_PA9_CH2 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) +#define ADC_MODULE_4 (4) +#define ADC_MODULE_5 (5) + +#define ADC_MODULE_COUNT (5) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 +#define FDCAN3_RX_PA8_AF11 +#define FDCAN3_RX_PB3_AF11 +#define FDCAN3_TX_PA15_AF11 +#define FDCAN3_TX_PB4_AF11 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) +#define CAN_MODULE_3 (3) + +#define CAN_MODULE_COUNT (3) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +#define HAL_LL_FDCAN3_GPIO_AF11 (11) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 +#define I2C4_SCL_PA13_AF3 +#define I2C4_SCL_PC6_AF8 +#define I2C4_SDA_PB7_AF3 +#define I2C4_SDA_PC7_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define UART5_RX_PD2_AF5 +#define UART5_TX_PC12_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define HRTIM1_CHA1_PA8_AF13 +#define HRTIM1_CHA2_PA9_AF13 +#define HRTIM1_CHB1_PA10_AF13 +#define HRTIM1_CHB2_PA11_AF13 +#define HRTIM1_CHC1_PB12_AF13 +#define HRTIM1_CHC2_PB13_AF13 +#define HRTIM1_CHD1_PB14_AF13 +#define HRTIM1_CHD2_PB15_AF13 +#define HRTIM1_CHE1_PC8_AF3 +#define HRTIM1_CHE2_PC9_AF3 +#define HRTIM1_CHF1_PC6_AF13 +#define HRTIM1_CHF2_PC7_AF13 +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM20_CH1_PB2_AF3 +#define TIM20_CH2_PC2_AF6 +#define TIM20_CH3_PC8_AF6 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH1_PB2_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH2_PC12_AF1 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH4_PA3_AF2 +#define TIM5_ETR_PB12_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) +#define TIM_MODULE_20 (10) + +#define TIM_MODULE_COUNT (10) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD2_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (6) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474VB/LQFP100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474VB/LQFP100/mcu_definitions.h new file mode 100644 index 000000000..5abda71ee --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474VB/LQFP100/mcu_definitions.h @@ -0,0 +1,615 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G474VB_LQFP100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 +#define ADC3_PD10_CH7 +#define ADC3_PD11_CH8 +#define ADC3_PD12_CH9 +#define ADC3_PD13_CH10 +#define ADC3_PD14_CH11 +#define ADC3_PE10_CH14 +#define ADC3_PE11_CH15 +#define ADC3_PE12_CH16 +#define ADC3_PE13_CH3 +#define ADC3_PE7_CH4 +#define ADC3_PE8_CH6 +#define ADC3_PE9_CH2 +#define ADC4_PB12_CH3 +#define ADC4_PB14_CH4 +#define ADC4_PB15_CH5 +#define ADC4_PD10_CH7 +#define ADC4_PD11_CH8 +#define ADC4_PD12_CH9 +#define ADC4_PD13_CH10 +#define ADC4_PD14_CH11 +#define ADC4_PD8_CH12 +#define ADC4_PD9_CH13 +#define ADC4_PE10_CH14 +#define ADC4_PE11_CH15 +#define ADC4_PE12_CH16 +#define ADC4_PE14_CH1 +#define ADC4_PE15_CH2 +#define ADC4_PE8_CH6 +#define ADC5_PA8_CH1 +#define ADC5_PA9_CH2 +#define ADC5_PD10_CH7 +#define ADC5_PD11_CH8 +#define ADC5_PD12_CH9 +#define ADC5_PD13_CH10 +#define ADC5_PD14_CH11 +#define ADC5_PD8_CH12 +#define ADC5_PD9_CH13 +#define ADC5_PE10_CH14 +#define ADC5_PE11_CH15 +#define ADC5_PE12_CH16 +#define ADC5_PE8_CH6 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) +#define ADC_MODULE_4 (4) +#define ADC_MODULE_5 (5) + +#define ADC_MODULE_COUNT (5) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_RX_PD0_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN1_TX_PD1_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 +#define FDCAN3_RX_PA8_AF11 +#define FDCAN3_RX_PB3_AF11 +#define FDCAN3_TX_PA15_AF11 +#define FDCAN3_TX_PB4_AF11 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) +#define CAN_MODULE_3 (3) + +#define CAN_MODULE_COUNT (3) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +#define HAL_LL_FDCAN3_GPIO_AF11 (11) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 +#define I2C4_SCL_PA13_AF3 +#define I2C4_SCL_PC6_AF8 +#define I2C4_SDA_PB7_AF3 +#define I2C4_SDA_PC7_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define UART5_RX_PD2_AF5 +#define UART5_TX_PC12_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_RX_PE1_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART1_TX_PE0_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_RX_PD6_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART2_TX_PD5_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PD9_AF7 +#define USART3_RX_PE15_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PD8_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF10_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI2_SCK_PF9_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 +#define SPI4_MISO_PE13_AF5 +#define SPI4_MISO_PE5_AF5 +#define SPI4_MOSI_PE14_AF5 +#define SPI4_MOSI_PE6_AF5 +#define SPI4_SCK_PE12_AF5 +#define SPI4_SCK_PE2_AF5 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) +#define SPI_MODULE_4 (4) + +#define SPI_MODULE_COUNT (4) +// EOF SPI + +// TIM +#define HRTIM1_CHA1_PA8_AF13 +#define HRTIM1_CHA2_PA9_AF13 +#define HRTIM1_CHB1_PA10_AF13 +#define HRTIM1_CHB2_PA11_AF13 +#define HRTIM1_CHC1_PB12_AF13 +#define HRTIM1_CHC2_PB13_AF13 +#define HRTIM1_CHD1_PB14_AF13 +#define HRTIM1_CHD2_PB15_AF13 +#define HRTIM1_CHE1_PC8_AF3 +#define HRTIM1_CHE2_PC9_AF3 +#define HRTIM1_CHF1_PC6_AF13 +#define HRTIM1_CHF2_PC7_AF13 +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH1_PF9_AF3 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM15_CH2_PF10_AF3 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM16_CH1_PE0_AF4 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM17_CH1_PE1_AF4 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN2_PE14_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_BKIN_PE15_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1N_PE8_AF2 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH1_PE9_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2N_PE10_AF2 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH2_PE11_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PE12_AF2 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH3_PE13_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4N_PE15_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_CH4_PE14_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM1_ETR_PE7_AF2 +#define TIM20_BKIN2_PF10_AF2 +#define TIM20_BKIN_PF9_AF2 +#define TIM20_CH1N_PE4_AF6 +#define TIM20_CH1_PB2_AF3 +#define TIM20_CH1_PE2_AF6 +#define TIM20_CH2N_PE5_AF6 +#define TIM20_CH2_PC2_AF6 +#define TIM20_CH2_PE3_AF6 +#define TIM20_CH3N_PE6_AF6 +#define TIM20_CH3_PC8_AF6 +#define TIM20_CH3_PF2_AF2 +#define TIM20_CH4N_PE0_AF3 +#define TIM20_CH4_PE1_AF6 +#define TIM20_ETR_PE0_AF6 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH1_PD3_AF2 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH2_PD4_AF2 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH3_PD7_AF2 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_CH4_PD6_AF2 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM2_ETR_PD3_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH1_PE2_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH2_PE3_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH3_PE4_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_CH4_PE5_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH1_PD12_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH2_PD13_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH3_PD14_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_CH4_PD15_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM4_ETR_PE0_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH1_PB2_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH2_PC12_AF1 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH3_PE8_AF1 +#define TIM5_CH4_PA3_AF2 +#define TIM5_CH4_PE9_AF1 +#define TIM5_CH4_PF9_AF6 +#define TIM5_ETR_PB12_AF2 +#define TIM5_ETR_PD11_AF1 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN2_PD1_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4N_PD0_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_CH4_PD1_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) +#define TIM_MODULE_20 (10) + +#define TIM_MODULE_COUNT (10) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PE0_CN +#define __PE1_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN +#define __PE6_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PF10_CN +#define __PF2_CN +#define __PF9_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (7) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474VB/TFBGA100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474VB/TFBGA100/mcu_definitions.h new file mode 100644 index 000000000..9cfbf6372 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474VB/TFBGA100/mcu_definitions.h @@ -0,0 +1,615 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G474VB_TFBGA100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 +#define ADC3_PD10_CH7 +#define ADC3_PD11_CH8 +#define ADC3_PD12_CH9 +#define ADC3_PD13_CH10 +#define ADC3_PD14_CH11 +#define ADC3_PE10_CH14 +#define ADC3_PE11_CH15 +#define ADC3_PE12_CH16 +#define ADC3_PE13_CH3 +#define ADC3_PE7_CH4 +#define ADC3_PE8_CH6 +#define ADC3_PE9_CH2 +#define ADC4_PB12_CH3 +#define ADC4_PB14_CH4 +#define ADC4_PB15_CH5 +#define ADC4_PD10_CH7 +#define ADC4_PD11_CH8 +#define ADC4_PD12_CH9 +#define ADC4_PD13_CH10 +#define ADC4_PD14_CH11 +#define ADC4_PD8_CH12 +#define ADC4_PD9_CH13 +#define ADC4_PE10_CH14 +#define ADC4_PE11_CH15 +#define ADC4_PE12_CH16 +#define ADC4_PE14_CH1 +#define ADC4_PE15_CH2 +#define ADC4_PE8_CH6 +#define ADC5_PA8_CH1 +#define ADC5_PA9_CH2 +#define ADC5_PD10_CH7 +#define ADC5_PD11_CH8 +#define ADC5_PD12_CH9 +#define ADC5_PD13_CH10 +#define ADC5_PD14_CH11 +#define ADC5_PD8_CH12 +#define ADC5_PD9_CH13 +#define ADC5_PE10_CH14 +#define ADC5_PE11_CH15 +#define ADC5_PE12_CH16 +#define ADC5_PE8_CH6 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) +#define ADC_MODULE_4 (4) +#define ADC_MODULE_5 (5) + +#define ADC_MODULE_COUNT (5) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_RX_PD0_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN1_TX_PD1_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 +#define FDCAN3_RX_PA8_AF11 +#define FDCAN3_RX_PB3_AF11 +#define FDCAN3_TX_PA15_AF11 +#define FDCAN3_TX_PB4_AF11 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) +#define CAN_MODULE_3 (3) + +#define CAN_MODULE_COUNT (3) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +#define HAL_LL_FDCAN3_GPIO_AF11 (11) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 +#define I2C4_SCL_PA13_AF3 +#define I2C4_SCL_PC6_AF8 +#define I2C4_SDA_PB7_AF3 +#define I2C4_SDA_PC7_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define UART5_RX_PD2_AF5 +#define UART5_TX_PC12_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_RX_PE1_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART1_TX_PE0_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_RX_PD6_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART2_TX_PD5_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PD9_AF7 +#define USART3_RX_PE15_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PD8_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF10_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI2_SCK_PF9_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 +#define SPI4_MISO_PE13_AF5 +#define SPI4_MISO_PE5_AF5 +#define SPI4_MOSI_PE14_AF5 +#define SPI4_MOSI_PE6_AF5 +#define SPI4_SCK_PE12_AF5 +#define SPI4_SCK_PE2_AF5 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) +#define SPI_MODULE_4 (4) + +#define SPI_MODULE_COUNT (4) +// EOF SPI + +// TIM +#define HRTIM1_CHA1_PA8_AF13 +#define HRTIM1_CHA2_PA9_AF13 +#define HRTIM1_CHB1_PA10_AF13 +#define HRTIM1_CHB2_PA11_AF13 +#define HRTIM1_CHC1_PB12_AF13 +#define HRTIM1_CHC2_PB13_AF13 +#define HRTIM1_CHD1_PB14_AF13 +#define HRTIM1_CHD2_PB15_AF13 +#define HRTIM1_CHE1_PC8_AF3 +#define HRTIM1_CHE2_PC9_AF3 +#define HRTIM1_CHF1_PC6_AF13 +#define HRTIM1_CHF2_PC7_AF13 +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH1_PF9_AF3 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM15_CH2_PF10_AF3 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM16_CH1_PE0_AF4 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM17_CH1_PE1_AF4 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN2_PE14_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_BKIN_PE15_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1N_PE8_AF2 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH1_PE9_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2N_PE10_AF2 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH2_PE11_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PE12_AF2 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH3_PE13_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4N_PE15_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_CH4_PE14_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM1_ETR_PE7_AF2 +#define TIM20_BKIN2_PF10_AF2 +#define TIM20_BKIN_PF9_AF2 +#define TIM20_CH1N_PE4_AF6 +#define TIM20_CH1_PB2_AF3 +#define TIM20_CH1_PE2_AF6 +#define TIM20_CH2N_PE5_AF6 +#define TIM20_CH2_PC2_AF6 +#define TIM20_CH2_PE3_AF6 +#define TIM20_CH3N_PE6_AF6 +#define TIM20_CH3_PC8_AF6 +#define TIM20_CH3_PF2_AF2 +#define TIM20_CH4N_PE0_AF3 +#define TIM20_CH4_PE1_AF6 +#define TIM20_ETR_PE0_AF6 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH1_PD3_AF2 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH2_PD4_AF2 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH3_PD7_AF2 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_CH4_PD6_AF2 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM2_ETR_PD3_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH1_PE2_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH2_PE3_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH3_PE4_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_CH4_PE5_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH1_PD12_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH2_PD13_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH3_PD14_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_CH4_PD15_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM4_ETR_PE0_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH1_PB2_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH2_PC12_AF1 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH3_PE8_AF1 +#define TIM5_CH4_PA3_AF2 +#define TIM5_CH4_PE9_AF1 +#define TIM5_CH4_PF9_AF6 +#define TIM5_ETR_PB12_AF2 +#define TIM5_ETR_PD11_AF1 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN2_PD1_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4N_PD0_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_CH4_PD1_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) +#define TIM_MODULE_20 (10) + +#define TIM_MODULE_COUNT (10) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PE0_CN +#define __PE1_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN +#define __PE6_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PF10_CN +#define __PF2_CN +#define __PF9_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (7) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474VC/LQFP100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474VC/LQFP100/mcu_definitions.h new file mode 100644 index 000000000..811433260 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474VC/LQFP100/mcu_definitions.h @@ -0,0 +1,615 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G474VC_LQFP100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 +#define ADC3_PD10_CH7 +#define ADC3_PD11_CH8 +#define ADC3_PD12_CH9 +#define ADC3_PD13_CH10 +#define ADC3_PD14_CH11 +#define ADC3_PE10_CH14 +#define ADC3_PE11_CH15 +#define ADC3_PE12_CH16 +#define ADC3_PE13_CH3 +#define ADC3_PE7_CH4 +#define ADC3_PE8_CH6 +#define ADC3_PE9_CH2 +#define ADC4_PB12_CH3 +#define ADC4_PB14_CH4 +#define ADC4_PB15_CH5 +#define ADC4_PD10_CH7 +#define ADC4_PD11_CH8 +#define ADC4_PD12_CH9 +#define ADC4_PD13_CH10 +#define ADC4_PD14_CH11 +#define ADC4_PD8_CH12 +#define ADC4_PD9_CH13 +#define ADC4_PE10_CH14 +#define ADC4_PE11_CH15 +#define ADC4_PE12_CH16 +#define ADC4_PE14_CH1 +#define ADC4_PE15_CH2 +#define ADC4_PE8_CH6 +#define ADC5_PA8_CH1 +#define ADC5_PA9_CH2 +#define ADC5_PD10_CH7 +#define ADC5_PD11_CH8 +#define ADC5_PD12_CH9 +#define ADC5_PD13_CH10 +#define ADC5_PD14_CH11 +#define ADC5_PD8_CH12 +#define ADC5_PD9_CH13 +#define ADC5_PE10_CH14 +#define ADC5_PE11_CH15 +#define ADC5_PE12_CH16 +#define ADC5_PE8_CH6 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) +#define ADC_MODULE_4 (4) +#define ADC_MODULE_5 (5) + +#define ADC_MODULE_COUNT (5) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_RX_PD0_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN1_TX_PD1_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 +#define FDCAN3_RX_PA8_AF11 +#define FDCAN3_RX_PB3_AF11 +#define FDCAN3_TX_PA15_AF11 +#define FDCAN3_TX_PB4_AF11 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) +#define CAN_MODULE_3 (3) + +#define CAN_MODULE_COUNT (3) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +#define HAL_LL_FDCAN3_GPIO_AF11 (11) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 +#define I2C4_SCL_PA13_AF3 +#define I2C4_SCL_PC6_AF8 +#define I2C4_SDA_PB7_AF3 +#define I2C4_SDA_PC7_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define UART5_RX_PD2_AF5 +#define UART5_TX_PC12_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_RX_PE1_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART1_TX_PE0_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_RX_PD6_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART2_TX_PD5_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PD9_AF7 +#define USART3_RX_PE15_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PD8_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF10_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI2_SCK_PF9_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 +#define SPI4_MISO_PE13_AF5 +#define SPI4_MISO_PE5_AF5 +#define SPI4_MOSI_PE14_AF5 +#define SPI4_MOSI_PE6_AF5 +#define SPI4_SCK_PE12_AF5 +#define SPI4_SCK_PE2_AF5 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) +#define SPI_MODULE_4 (4) + +#define SPI_MODULE_COUNT (4) +// EOF SPI + +// TIM +#define HRTIM1_CHA1_PA8_AF13 +#define HRTIM1_CHA2_PA9_AF13 +#define HRTIM1_CHB1_PA10_AF13 +#define HRTIM1_CHB2_PA11_AF13 +#define HRTIM1_CHC1_PB12_AF13 +#define HRTIM1_CHC2_PB13_AF13 +#define HRTIM1_CHD1_PB14_AF13 +#define HRTIM1_CHD2_PB15_AF13 +#define HRTIM1_CHE1_PC8_AF3 +#define HRTIM1_CHE2_PC9_AF3 +#define HRTIM1_CHF1_PC6_AF13 +#define HRTIM1_CHF2_PC7_AF13 +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH1_PF9_AF3 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM15_CH2_PF10_AF3 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM16_CH1_PE0_AF4 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM17_CH1_PE1_AF4 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN2_PE14_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_BKIN_PE15_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1N_PE8_AF2 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH1_PE9_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2N_PE10_AF2 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH2_PE11_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PE12_AF2 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH3_PE13_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4N_PE15_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_CH4_PE14_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM1_ETR_PE7_AF2 +#define TIM20_BKIN2_PF10_AF2 +#define TIM20_BKIN_PF9_AF2 +#define TIM20_CH1N_PE4_AF6 +#define TIM20_CH1_PB2_AF3 +#define TIM20_CH1_PE2_AF6 +#define TIM20_CH2N_PE5_AF6 +#define TIM20_CH2_PC2_AF6 +#define TIM20_CH2_PE3_AF6 +#define TIM20_CH3N_PE6_AF6 +#define TIM20_CH3_PC8_AF6 +#define TIM20_CH3_PF2_AF2 +#define TIM20_CH4N_PE0_AF3 +#define TIM20_CH4_PE1_AF6 +#define TIM20_ETR_PE0_AF6 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH1_PD3_AF2 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH2_PD4_AF2 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH3_PD7_AF2 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_CH4_PD6_AF2 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM2_ETR_PD3_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH1_PE2_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH2_PE3_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH3_PE4_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_CH4_PE5_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH1_PD12_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH2_PD13_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH3_PD14_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_CH4_PD15_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM4_ETR_PE0_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH1_PB2_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH2_PC12_AF1 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH3_PE8_AF1 +#define TIM5_CH4_PA3_AF2 +#define TIM5_CH4_PE9_AF1 +#define TIM5_CH4_PF9_AF6 +#define TIM5_ETR_PB12_AF2 +#define TIM5_ETR_PD11_AF1 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN2_PD1_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4N_PD0_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_CH4_PD1_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) +#define TIM_MODULE_20 (10) + +#define TIM_MODULE_COUNT (10) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PE0_CN +#define __PE1_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN +#define __PE6_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PF10_CN +#define __PF2_CN +#define __PF9_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (7) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474VC/TFBGA100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474VC/TFBGA100/mcu_definitions.h new file mode 100644 index 000000000..3a5ad2046 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474VC/TFBGA100/mcu_definitions.h @@ -0,0 +1,615 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G474VC_TFBGA100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 +#define ADC3_PD10_CH7 +#define ADC3_PD11_CH8 +#define ADC3_PD12_CH9 +#define ADC3_PD13_CH10 +#define ADC3_PD14_CH11 +#define ADC3_PE10_CH14 +#define ADC3_PE11_CH15 +#define ADC3_PE12_CH16 +#define ADC3_PE13_CH3 +#define ADC3_PE7_CH4 +#define ADC3_PE8_CH6 +#define ADC3_PE9_CH2 +#define ADC4_PB12_CH3 +#define ADC4_PB14_CH4 +#define ADC4_PB15_CH5 +#define ADC4_PD10_CH7 +#define ADC4_PD11_CH8 +#define ADC4_PD12_CH9 +#define ADC4_PD13_CH10 +#define ADC4_PD14_CH11 +#define ADC4_PD8_CH12 +#define ADC4_PD9_CH13 +#define ADC4_PE10_CH14 +#define ADC4_PE11_CH15 +#define ADC4_PE12_CH16 +#define ADC4_PE14_CH1 +#define ADC4_PE15_CH2 +#define ADC4_PE8_CH6 +#define ADC5_PA8_CH1 +#define ADC5_PA9_CH2 +#define ADC5_PD10_CH7 +#define ADC5_PD11_CH8 +#define ADC5_PD12_CH9 +#define ADC5_PD13_CH10 +#define ADC5_PD14_CH11 +#define ADC5_PD8_CH12 +#define ADC5_PD9_CH13 +#define ADC5_PE10_CH14 +#define ADC5_PE11_CH15 +#define ADC5_PE12_CH16 +#define ADC5_PE8_CH6 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) +#define ADC_MODULE_4 (4) +#define ADC_MODULE_5 (5) + +#define ADC_MODULE_COUNT (5) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_RX_PD0_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN1_TX_PD1_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 +#define FDCAN3_RX_PA8_AF11 +#define FDCAN3_RX_PB3_AF11 +#define FDCAN3_TX_PA15_AF11 +#define FDCAN3_TX_PB4_AF11 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) +#define CAN_MODULE_3 (3) + +#define CAN_MODULE_COUNT (3) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +#define HAL_LL_FDCAN3_GPIO_AF11 (11) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 +#define I2C4_SCL_PA13_AF3 +#define I2C4_SCL_PC6_AF8 +#define I2C4_SDA_PB7_AF3 +#define I2C4_SDA_PC7_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define UART5_RX_PD2_AF5 +#define UART5_TX_PC12_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_RX_PE1_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART1_TX_PE0_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_RX_PD6_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART2_TX_PD5_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PD9_AF7 +#define USART3_RX_PE15_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PD8_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF10_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI2_SCK_PF9_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 +#define SPI4_MISO_PE13_AF5 +#define SPI4_MISO_PE5_AF5 +#define SPI4_MOSI_PE14_AF5 +#define SPI4_MOSI_PE6_AF5 +#define SPI4_SCK_PE12_AF5 +#define SPI4_SCK_PE2_AF5 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) +#define SPI_MODULE_4 (4) + +#define SPI_MODULE_COUNT (4) +// EOF SPI + +// TIM +#define HRTIM1_CHA1_PA8_AF13 +#define HRTIM1_CHA2_PA9_AF13 +#define HRTIM1_CHB1_PA10_AF13 +#define HRTIM1_CHB2_PA11_AF13 +#define HRTIM1_CHC1_PB12_AF13 +#define HRTIM1_CHC2_PB13_AF13 +#define HRTIM1_CHD1_PB14_AF13 +#define HRTIM1_CHD2_PB15_AF13 +#define HRTIM1_CHE1_PC8_AF3 +#define HRTIM1_CHE2_PC9_AF3 +#define HRTIM1_CHF1_PC6_AF13 +#define HRTIM1_CHF2_PC7_AF13 +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH1_PF9_AF3 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM15_CH2_PF10_AF3 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM16_CH1_PE0_AF4 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM17_CH1_PE1_AF4 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN2_PE14_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_BKIN_PE15_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1N_PE8_AF2 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH1_PE9_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2N_PE10_AF2 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH2_PE11_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PE12_AF2 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH3_PE13_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4N_PE15_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_CH4_PE14_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM1_ETR_PE7_AF2 +#define TIM20_BKIN2_PF10_AF2 +#define TIM20_BKIN_PF9_AF2 +#define TIM20_CH1N_PE4_AF6 +#define TIM20_CH1_PB2_AF3 +#define TIM20_CH1_PE2_AF6 +#define TIM20_CH2N_PE5_AF6 +#define TIM20_CH2_PC2_AF6 +#define TIM20_CH2_PE3_AF6 +#define TIM20_CH3N_PE6_AF6 +#define TIM20_CH3_PC8_AF6 +#define TIM20_CH3_PF2_AF2 +#define TIM20_CH4N_PE0_AF3 +#define TIM20_CH4_PE1_AF6 +#define TIM20_ETR_PE0_AF6 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH1_PD3_AF2 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH2_PD4_AF2 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH3_PD7_AF2 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_CH4_PD6_AF2 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM2_ETR_PD3_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH1_PE2_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH2_PE3_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH3_PE4_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_CH4_PE5_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH1_PD12_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH2_PD13_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH3_PD14_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_CH4_PD15_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM4_ETR_PE0_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH1_PB2_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH2_PC12_AF1 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH3_PE8_AF1 +#define TIM5_CH4_PA3_AF2 +#define TIM5_CH4_PE9_AF1 +#define TIM5_CH4_PF9_AF6 +#define TIM5_ETR_PB12_AF2 +#define TIM5_ETR_PD11_AF1 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN2_PD1_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4N_PD0_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_CH4_PD1_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) +#define TIM_MODULE_20 (10) + +#define TIM_MODULE_COUNT (10) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PE0_CN +#define __PE1_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN +#define __PE6_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PF10_CN +#define __PF2_CN +#define __PF9_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (7) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474VE/LQFP100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474VE/LQFP100/mcu_definitions.h new file mode 100644 index 000000000..86989b4b8 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474VE/LQFP100/mcu_definitions.h @@ -0,0 +1,615 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G474VE_LQFP100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 +#define ADC3_PD10_CH7 +#define ADC3_PD11_CH8 +#define ADC3_PD12_CH9 +#define ADC3_PD13_CH10 +#define ADC3_PD14_CH11 +#define ADC3_PE10_CH14 +#define ADC3_PE11_CH15 +#define ADC3_PE12_CH16 +#define ADC3_PE13_CH3 +#define ADC3_PE7_CH4 +#define ADC3_PE8_CH6 +#define ADC3_PE9_CH2 +#define ADC4_PB12_CH3 +#define ADC4_PB14_CH4 +#define ADC4_PB15_CH5 +#define ADC4_PD10_CH7 +#define ADC4_PD11_CH8 +#define ADC4_PD12_CH9 +#define ADC4_PD13_CH10 +#define ADC4_PD14_CH11 +#define ADC4_PD8_CH12 +#define ADC4_PD9_CH13 +#define ADC4_PE10_CH14 +#define ADC4_PE11_CH15 +#define ADC4_PE12_CH16 +#define ADC4_PE14_CH1 +#define ADC4_PE15_CH2 +#define ADC4_PE8_CH6 +#define ADC5_PA8_CH1 +#define ADC5_PA9_CH2 +#define ADC5_PD10_CH7 +#define ADC5_PD11_CH8 +#define ADC5_PD12_CH9 +#define ADC5_PD13_CH10 +#define ADC5_PD14_CH11 +#define ADC5_PD8_CH12 +#define ADC5_PD9_CH13 +#define ADC5_PE10_CH14 +#define ADC5_PE11_CH15 +#define ADC5_PE12_CH16 +#define ADC5_PE8_CH6 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) +#define ADC_MODULE_4 (4) +#define ADC_MODULE_5 (5) + +#define ADC_MODULE_COUNT (5) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_RX_PD0_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN1_TX_PD1_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 +#define FDCAN3_RX_PA8_AF11 +#define FDCAN3_RX_PB3_AF11 +#define FDCAN3_TX_PA15_AF11 +#define FDCAN3_TX_PB4_AF11 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) +#define CAN_MODULE_3 (3) + +#define CAN_MODULE_COUNT (3) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +#define HAL_LL_FDCAN3_GPIO_AF11 (11) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 +#define I2C4_SCL_PA13_AF3 +#define I2C4_SCL_PC6_AF8 +#define I2C4_SDA_PB7_AF3 +#define I2C4_SDA_PC7_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define UART5_RX_PD2_AF5 +#define UART5_TX_PC12_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_RX_PE1_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART1_TX_PE0_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_RX_PD6_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART2_TX_PD5_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PD9_AF7 +#define USART3_RX_PE15_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PD8_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF10_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI2_SCK_PF9_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 +#define SPI4_MISO_PE13_AF5 +#define SPI4_MISO_PE5_AF5 +#define SPI4_MOSI_PE14_AF5 +#define SPI4_MOSI_PE6_AF5 +#define SPI4_SCK_PE12_AF5 +#define SPI4_SCK_PE2_AF5 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) +#define SPI_MODULE_4 (4) + +#define SPI_MODULE_COUNT (4) +// EOF SPI + +// TIM +#define HRTIM1_CHA1_PA8_AF13 +#define HRTIM1_CHA2_PA9_AF13 +#define HRTIM1_CHB1_PA10_AF13 +#define HRTIM1_CHB2_PA11_AF13 +#define HRTIM1_CHC1_PB12_AF13 +#define HRTIM1_CHC2_PB13_AF13 +#define HRTIM1_CHD1_PB14_AF13 +#define HRTIM1_CHD2_PB15_AF13 +#define HRTIM1_CHE1_PC8_AF3 +#define HRTIM1_CHE2_PC9_AF3 +#define HRTIM1_CHF1_PC6_AF13 +#define HRTIM1_CHF2_PC7_AF13 +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH1_PF9_AF3 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM15_CH2_PF10_AF3 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM16_CH1_PE0_AF4 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM17_CH1_PE1_AF4 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN2_PE14_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_BKIN_PE15_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1N_PE8_AF2 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH1_PE9_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2N_PE10_AF2 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH2_PE11_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PE12_AF2 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH3_PE13_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4N_PE15_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_CH4_PE14_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM1_ETR_PE7_AF2 +#define TIM20_BKIN2_PF10_AF2 +#define TIM20_BKIN_PF9_AF2 +#define TIM20_CH1N_PE4_AF6 +#define TIM20_CH1_PB2_AF3 +#define TIM20_CH1_PE2_AF6 +#define TIM20_CH2N_PE5_AF6 +#define TIM20_CH2_PC2_AF6 +#define TIM20_CH2_PE3_AF6 +#define TIM20_CH3N_PE6_AF6 +#define TIM20_CH3_PC8_AF6 +#define TIM20_CH3_PF2_AF2 +#define TIM20_CH4N_PE0_AF3 +#define TIM20_CH4_PE1_AF6 +#define TIM20_ETR_PE0_AF6 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH1_PD3_AF2 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH2_PD4_AF2 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH3_PD7_AF2 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_CH4_PD6_AF2 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM2_ETR_PD3_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH1_PE2_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH2_PE3_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH3_PE4_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_CH4_PE5_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH1_PD12_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH2_PD13_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH3_PD14_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_CH4_PD15_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM4_ETR_PE0_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH1_PB2_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH2_PC12_AF1 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH3_PE8_AF1 +#define TIM5_CH4_PA3_AF2 +#define TIM5_CH4_PE9_AF1 +#define TIM5_CH4_PF9_AF6 +#define TIM5_ETR_PB12_AF2 +#define TIM5_ETR_PD11_AF1 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN2_PD1_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4N_PD0_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_CH4_PD1_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) +#define TIM_MODULE_20 (10) + +#define TIM_MODULE_COUNT (10) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PE0_CN +#define __PE1_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN +#define __PE6_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PF10_CN +#define __PF2_CN +#define __PF9_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (7) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474VE/TFBGA100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474VE/TFBGA100/mcu_definitions.h new file mode 100644 index 000000000..2556c308a --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G474VE/TFBGA100/mcu_definitions.h @@ -0,0 +1,615 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G474VE_TFBGA100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 +#define ADC3_PD10_CH7 +#define ADC3_PD11_CH8 +#define ADC3_PD12_CH9 +#define ADC3_PD13_CH10 +#define ADC3_PD14_CH11 +#define ADC3_PE10_CH14 +#define ADC3_PE11_CH15 +#define ADC3_PE12_CH16 +#define ADC3_PE13_CH3 +#define ADC3_PE7_CH4 +#define ADC3_PE8_CH6 +#define ADC3_PE9_CH2 +#define ADC4_PB12_CH3 +#define ADC4_PB14_CH4 +#define ADC4_PB15_CH5 +#define ADC4_PD10_CH7 +#define ADC4_PD11_CH8 +#define ADC4_PD12_CH9 +#define ADC4_PD13_CH10 +#define ADC4_PD14_CH11 +#define ADC4_PD8_CH12 +#define ADC4_PD9_CH13 +#define ADC4_PE10_CH14 +#define ADC4_PE11_CH15 +#define ADC4_PE12_CH16 +#define ADC4_PE14_CH1 +#define ADC4_PE15_CH2 +#define ADC4_PE8_CH6 +#define ADC5_PA8_CH1 +#define ADC5_PA9_CH2 +#define ADC5_PD10_CH7 +#define ADC5_PD11_CH8 +#define ADC5_PD12_CH9 +#define ADC5_PD13_CH10 +#define ADC5_PD14_CH11 +#define ADC5_PD8_CH12 +#define ADC5_PD9_CH13 +#define ADC5_PE10_CH14 +#define ADC5_PE11_CH15 +#define ADC5_PE12_CH16 +#define ADC5_PE8_CH6 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) +#define ADC_MODULE_4 (4) +#define ADC_MODULE_5 (5) + +#define ADC_MODULE_COUNT (5) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_RX_PD0_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN1_TX_PD1_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 +#define FDCAN3_RX_PA8_AF11 +#define FDCAN3_RX_PB3_AF11 +#define FDCAN3_TX_PA15_AF11 +#define FDCAN3_TX_PB4_AF11 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) +#define CAN_MODULE_3 (3) + +#define CAN_MODULE_COUNT (3) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +#define HAL_LL_FDCAN3_GPIO_AF11 (11) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 +#define I2C4_SCL_PA13_AF3 +#define I2C4_SCL_PC6_AF8 +#define I2C4_SDA_PB7_AF3 +#define I2C4_SDA_PC7_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define UART5_RX_PD2_AF5 +#define UART5_TX_PC12_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_RX_PE1_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART1_TX_PE0_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_RX_PD6_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART2_TX_PD5_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PD9_AF7 +#define USART3_RX_PE15_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PD8_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF10_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI2_SCK_PF9_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 +#define SPI4_MISO_PE13_AF5 +#define SPI4_MISO_PE5_AF5 +#define SPI4_MOSI_PE14_AF5 +#define SPI4_MOSI_PE6_AF5 +#define SPI4_SCK_PE12_AF5 +#define SPI4_SCK_PE2_AF5 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) +#define SPI_MODULE_4 (4) + +#define SPI_MODULE_COUNT (4) +// EOF SPI + +// TIM +#define HRTIM1_CHA1_PA8_AF13 +#define HRTIM1_CHA2_PA9_AF13 +#define HRTIM1_CHB1_PA10_AF13 +#define HRTIM1_CHB2_PA11_AF13 +#define HRTIM1_CHC1_PB12_AF13 +#define HRTIM1_CHC2_PB13_AF13 +#define HRTIM1_CHD1_PB14_AF13 +#define HRTIM1_CHD2_PB15_AF13 +#define HRTIM1_CHE1_PC8_AF3 +#define HRTIM1_CHE2_PC9_AF3 +#define HRTIM1_CHF1_PC6_AF13 +#define HRTIM1_CHF2_PC7_AF13 +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH1_PF9_AF3 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM15_CH2_PF10_AF3 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM16_CH1_PE0_AF4 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM17_CH1_PE1_AF4 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN2_PE14_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_BKIN_PE15_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1N_PE8_AF2 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH1_PE9_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2N_PE10_AF2 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH2_PE11_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PE12_AF2 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH3_PE13_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4N_PE15_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_CH4_PE14_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM1_ETR_PE7_AF2 +#define TIM20_BKIN2_PF10_AF2 +#define TIM20_BKIN_PF9_AF2 +#define TIM20_CH1N_PE4_AF6 +#define TIM20_CH1_PB2_AF3 +#define TIM20_CH1_PE2_AF6 +#define TIM20_CH2N_PE5_AF6 +#define TIM20_CH2_PC2_AF6 +#define TIM20_CH2_PE3_AF6 +#define TIM20_CH3N_PE6_AF6 +#define TIM20_CH3_PC8_AF6 +#define TIM20_CH3_PF2_AF2 +#define TIM20_CH4N_PE0_AF3 +#define TIM20_CH4_PE1_AF6 +#define TIM20_ETR_PE0_AF6 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH1_PD3_AF2 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH2_PD4_AF2 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH3_PD7_AF2 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_CH4_PD6_AF2 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM2_ETR_PD3_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH1_PE2_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH2_PE3_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH3_PE4_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_CH4_PE5_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH1_PD12_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH2_PD13_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH3_PD14_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_CH4_PD15_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM4_ETR_PE0_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH1_PB2_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH2_PC12_AF1 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH3_PE8_AF1 +#define TIM5_CH4_PA3_AF2 +#define TIM5_CH4_PE9_AF1 +#define TIM5_CH4_PF9_AF6 +#define TIM5_ETR_PB12_AF2 +#define TIM5_ETR_PD11_AF1 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN2_PD1_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4N_PD0_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_CH4_PD1_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) +#define TIM_MODULE_20 (10) + +#define TIM_MODULE_COUNT (10) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PE0_CN +#define __PE1_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN +#define __PE6_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PF10_CN +#define __PF2_CN +#define __PF9_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (7) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G483CE/LQFP48/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G483CE/LQFP48/mcu_definitions.h new file mode 100644 index 000000000..4ee1bba2e --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G483CE/LQFP48/mcu_definitions.h @@ -0,0 +1,391 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G483CE_LQFP48. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 +#define ADC4_PB12_CH3 +#define ADC4_PB14_CH4 +#define ADC4_PB15_CH5 +#define ADC5_PA8_CH1 +#define ADC5_PA9_CH2 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) +#define ADC_MODULE_4 (4) +#define ADC_MODULE_5 (5) + +#define ADC_MODULE_COUNT (5) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 +#define FDCAN3_RX_PA8_AF11 +#define FDCAN3_RX_PB3_AF11 +#define FDCAN3_TX_PA15_AF11 +#define FDCAN3_TX_PB4_AF11 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) +#define CAN_MODULE_3 (3) + +#define CAN_MODULE_COUNT (3) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +#define HAL_LL_FDCAN3_GPIO_AF11 (11) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SDA_PB5_AF8 +#define I2C4_SCL_PA13_AF3 +#define I2C4_SDA_PB7_AF3 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) + +#define UART_MODULE_COUNT (3) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_SCK_PB3_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_ETR_PA12_AF11 +#define TIM20_CH1_PB2_AF3 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_ETR_PB3_AF10 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH1_PB2_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH4_PA3_AF2 +#define TIM5_ETR_PB12_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) +#define TIM_MODULE_20 (10) + +#define TIM_MODULE_COUNT (10) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G483CE/UFQFPN48/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G483CE/UFQFPN48/mcu_definitions.h new file mode 100644 index 000000000..21644ecf3 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G483CE/UFQFPN48/mcu_definitions.h @@ -0,0 +1,414 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G483CE_UFQFPN48. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC4_CH5 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 +#define ADC4_PB12_CH3 +#define ADC4_PB14_CH4 +#define ADC4_PB15_CH5 +#define ADC5_PA8_CH1 +#define ADC5_PA9_CH2 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) +#define ADC_MODULE_4 (4) +#define ADC_MODULE_5 (5) + +#define ADC_MODULE_COUNT (5) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 +#define FDCAN3_RX_PA8_AF11 +#define FDCAN3_RX_PB3_AF11 +#define FDCAN3_TX_PA15_AF11 +#define FDCAN3_TX_PB4_AF11 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) +#define CAN_MODULE_3 (3) + +#define CAN_MODULE_COUNT (3) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +#define HAL_LL_FDCAN3_GPIO_AF11 (11) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C4_SCL_PA13_AF3 +#define I2C4_SCL_PC6_AF8 +#define I2C4_SDA_PB7_AF3 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (4) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM20_CH1_PB2_AF3 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_ETR_PB3_AF10 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH1_PB2_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH4_PA3_AF2 +#define TIM5_ETR_PB12_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) +#define TIM_MODULE_20 (10) + +#define TIM_MODULE_COUNT (10) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC10_CN +#define __PC11_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC4_CN +#define __PC6_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G483ME/LQFP80/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G483ME/LQFP80/mcu_definitions.h new file mode 100644 index 000000000..5c7cf5efe --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G483ME/LQFP80/mcu_definitions.h @@ -0,0 +1,531 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G483ME_LQFP80. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 +#define ADC3_PD10_CH7 +#define ADC3_PE10_CH14 +#define ADC3_PE11_CH15 +#define ADC3_PE12_CH16 +#define ADC3_PE13_CH3 +#define ADC3_PE7_CH4 +#define ADC3_PE8_CH6 +#define ADC3_PE9_CH2 +#define ADC4_PB12_CH3 +#define ADC4_PB14_CH4 +#define ADC4_PB15_CH5 +#define ADC4_PD10_CH7 +#define ADC4_PD8_CH12 +#define ADC4_PD9_CH13 +#define ADC4_PE10_CH14 +#define ADC4_PE11_CH15 +#define ADC4_PE12_CH16 +#define ADC4_PE14_CH1 +#define ADC4_PE15_CH2 +#define ADC4_PE8_CH6 +#define ADC5_PA8_CH1 +#define ADC5_PA9_CH2 +#define ADC5_PD10_CH7 +#define ADC5_PD8_CH12 +#define ADC5_PD9_CH13 +#define ADC5_PE10_CH14 +#define ADC5_PE11_CH15 +#define ADC5_PE12_CH16 +#define ADC5_PE8_CH6 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) +#define ADC_MODULE_4 (4) +#define ADC_MODULE_5 (5) + +#define ADC_MODULE_COUNT (5) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_RX_PD0_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN1_TX_PD1_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 +#define FDCAN3_RX_PA8_AF11 +#define FDCAN3_RX_PB3_AF11 +#define FDCAN3_TX_PA15_AF11 +#define FDCAN3_TX_PB4_AF11 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) +#define CAN_MODULE_3 (3) + +#define CAN_MODULE_COUNT (3) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +#define HAL_LL_FDCAN3_GPIO_AF11 (11) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 +#define I2C4_SCL_PA13_AF3 +#define I2C4_SCL_PC6_AF8 +#define I2C4_SDA_PB7_AF3 +#define I2C4_SDA_PC7_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define UART5_RX_PD2_AF5 +#define UART5_TX_PC12_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PD9_AF7 +#define USART3_RX_PE15_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PD8_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 +#define SPI4_MISO_PE13_AF5 +#define SPI4_MOSI_PE14_AF5 +#define SPI4_SCK_PE12_AF5 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) +#define SPI_MODULE_4 (4) + +#define SPI_MODULE_COUNT (4) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN2_PE14_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_BKIN_PE15_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1N_PE8_AF2 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH1_PE9_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2N_PE10_AF2 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH2_PE11_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PE12_AF2 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH3_PE13_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4N_PE15_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_CH4_PE14_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM1_ETR_PE7_AF2 +#define TIM20_CH1_PB2_AF3 +#define TIM20_CH2_PC2_AF6 +#define TIM20_CH3_PC8_AF6 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH1_PB2_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH2_PC12_AF1 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH3_PE8_AF1 +#define TIM5_CH4_PA3_AF2 +#define TIM5_CH4_PE9_AF1 +#define TIM5_ETR_PB12_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN2_PD1_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4N_PD0_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_CH4_PD1_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) +#define TIM_MODULE_20 (10) + +#define TIM_MODULE_COUNT (10) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD2_CN +#define __PD8_CN +#define __PD9_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (7) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G483ME/WLCSP81/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G483ME/WLCSP81/mcu_definitions.h new file mode 100644 index 000000000..44f937211 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G483ME/WLCSP81/mcu_definitions.h @@ -0,0 +1,536 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G483ME_WLCSP81. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 +#define ADC3_PD10_CH7 +#define ADC3_PD11_CH8 +#define ADC3_PE10_CH14 +#define ADC3_PE11_CH15 +#define ADC3_PE12_CH16 +#define ADC3_PE13_CH3 +#define ADC3_PE7_CH4 +#define ADC3_PE8_CH6 +#define ADC3_PE9_CH2 +#define ADC4_PB12_CH3 +#define ADC4_PB14_CH4 +#define ADC4_PB15_CH5 +#define ADC4_PD10_CH7 +#define ADC4_PD11_CH8 +#define ADC4_PD8_CH12 +#define ADC4_PD9_CH13 +#define ADC4_PE10_CH14 +#define ADC4_PE11_CH15 +#define ADC4_PE12_CH16 +#define ADC4_PE14_CH1 +#define ADC4_PE15_CH2 +#define ADC4_PE8_CH6 +#define ADC5_PA8_CH1 +#define ADC5_PA9_CH2 +#define ADC5_PD10_CH7 +#define ADC5_PD11_CH8 +#define ADC5_PD8_CH12 +#define ADC5_PD9_CH13 +#define ADC5_PE10_CH14 +#define ADC5_PE11_CH15 +#define ADC5_PE12_CH16 +#define ADC5_PE8_CH6 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) +#define ADC_MODULE_4 (4) +#define ADC_MODULE_5 (5) + +#define ADC_MODULE_COUNT (5) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_RX_PD0_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN1_TX_PD1_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 +#define FDCAN3_RX_PA8_AF11 +#define FDCAN3_RX_PB3_AF11 +#define FDCAN3_TX_PA15_AF11 +#define FDCAN3_TX_PB4_AF11 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) +#define CAN_MODULE_3 (3) + +#define CAN_MODULE_COUNT (3) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +#define HAL_LL_FDCAN3_GPIO_AF11 (11) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 +#define I2C4_SCL_PA13_AF3 +#define I2C4_SCL_PC6_AF8 +#define I2C4_SDA_PB7_AF3 +#define I2C4_SDA_PC7_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define UART5_RX_PD2_AF5 +#define UART5_TX_PC12_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PD9_AF7 +#define USART3_RX_PE15_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PD8_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 +#define SPI4_MISO_PE13_AF5 +#define SPI4_MOSI_PE14_AF5 +#define SPI4_SCK_PE12_AF5 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) +#define SPI_MODULE_4 (4) + +#define SPI_MODULE_COUNT (4) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN2_PE14_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_BKIN_PE15_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1N_PE8_AF2 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH1_PE9_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2N_PE10_AF2 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH2_PE11_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PE12_AF2 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH3_PE13_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4N_PE15_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_CH4_PE14_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM1_ETR_PE7_AF2 +#define TIM20_CH1_PB2_AF3 +#define TIM20_CH2_PC2_AF6 +#define TIM20_CH3_PC8_AF6 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH1_PB2_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH2_PC12_AF1 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH3_PE8_AF1 +#define TIM5_CH4_PA3_AF2 +#define TIM5_CH4_PE9_AF1 +#define TIM5_ETR_PB12_AF2 +#define TIM5_ETR_PD11_AF1 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN2_PD1_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4N_PD0_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_CH4_PD1_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) +#define TIM_MODULE_20 (10) + +#define TIM_MODULE_COUNT (10) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD11_CN +#define __PD2_CN +#define __PD8_CN +#define __PD9_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (7) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G483PE/UFBGA121/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G483PE/UFBGA121/mcu_definitions.h new file mode 100644 index 000000000..4f6b01875 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G483PE/UFBGA121/mcu_definitions.h @@ -0,0 +1,650 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G483PE_UFBGA121. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 +#define ADC3_PD10_CH7 +#define ADC3_PD11_CH8 +#define ADC3_PD12_CH9 +#define ADC3_PD13_CH10 +#define ADC3_PD14_CH11 +#define ADC3_PE10_CH14 +#define ADC3_PE11_CH15 +#define ADC3_PE12_CH16 +#define ADC3_PE13_CH3 +#define ADC3_PE7_CH4 +#define ADC3_PE8_CH6 +#define ADC3_PE9_CH2 +#define ADC4_PB12_CH3 +#define ADC4_PB14_CH4 +#define ADC4_PB15_CH5 +#define ADC4_PD10_CH7 +#define ADC4_PD11_CH8 +#define ADC4_PD12_CH9 +#define ADC4_PD13_CH10 +#define ADC4_PD14_CH11 +#define ADC4_PD8_CH12 +#define ADC4_PD9_CH13 +#define ADC4_PE10_CH14 +#define ADC4_PE11_CH15 +#define ADC4_PE12_CH16 +#define ADC4_PE14_CH1 +#define ADC4_PE15_CH2 +#define ADC4_PE8_CH6 +#define ADC5_PA8_CH1 +#define ADC5_PA9_CH2 +#define ADC5_PD10_CH7 +#define ADC5_PD11_CH8 +#define ADC5_PD12_CH9 +#define ADC5_PD13_CH10 +#define ADC5_PD14_CH11 +#define ADC5_PD8_CH12 +#define ADC5_PD9_CH13 +#define ADC5_PE10_CH14 +#define ADC5_PE11_CH15 +#define ADC5_PE12_CH16 +#define ADC5_PE8_CH6 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) +#define ADC_MODULE_4 (4) +#define ADC_MODULE_5 (5) + +#define ADC_MODULE_COUNT (5) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_RX_PD0_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN1_TX_PD1_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 +#define FDCAN3_RX_PA8_AF11 +#define FDCAN3_RX_PB3_AF11 +#define FDCAN3_TX_PA15_AF11 +#define FDCAN3_TX_PB4_AF11 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) +#define CAN_MODULE_3 (3) + +#define CAN_MODULE_COUNT (3) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +#define HAL_LL_FDCAN3_GPIO_AF11 (11) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SCL_PF6_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SCL_PF3_AF4 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 +#define I2C3_SDA_PF4_AF4 +#define I2C4_SCL_PA13_AF3 +#define I2C4_SCL_PC6_AF8 +#define I2C4_SCL_PF14_AF4 +#define I2C4_SCL_PG3_AF4 +#define I2C4_SDA_PB7_AF3 +#define I2C4_SDA_PC7_AF8 +#define I2C4_SDA_PF15_AF4 +#define I2C4_SDA_PG4_AF4 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define UART5_RX_PD2_AF5 +#define UART5_TX_PC12_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_RX_PE1_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART1_TX_PE0_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_RX_PD6_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART2_TX_PD5_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PD9_AF7 +#define USART3_RX_PE15_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PD8_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MISO_PG3_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_MOSI_PG4_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI1_SCK_PG2_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF10_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI2_SCK_PF9_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 +#define SPI4_MISO_PE13_AF5 +#define SPI4_MISO_PE5_AF5 +#define SPI4_MOSI_PE14_AF5 +#define SPI4_MOSI_PE6_AF5 +#define SPI4_SCK_PE12_AF5 +#define SPI4_SCK_PE2_AF5 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) +#define SPI_MODULE_4 (4) + +#define SPI_MODULE_COUNT (4) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH1_PF9_AF3 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM15_CH2_PF10_AF3 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM16_CH1_PE0_AF4 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM17_CH1_PE1_AF4 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN2_PE14_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_BKIN_PE15_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1N_PE8_AF2 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH1_PE9_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2N_PE10_AF2 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH2_PE11_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PE12_AF2 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH3_PE13_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4N_PE15_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_CH4_PE14_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM1_ETR_PE7_AF2 +#define TIM20_BKIN2_PF10_AF2 +#define TIM20_BKIN2_PF8_AF2 +#define TIM20_BKIN2_PG4_AF2 +#define TIM20_BKIN_PF7_AF2 +#define TIM20_BKIN_PF9_AF2 +#define TIM20_BKIN_PG3_AF2 +#define TIM20_CH1N_PE4_AF6 +#define TIM20_CH1N_PF4_AF3 +#define TIM20_CH1N_PG0_AF2 +#define TIM20_CH1_PB2_AF3 +#define TIM20_CH1_PE2_AF6 +#define TIM20_CH1_PF12_AF2 +#define TIM20_CH2N_PE5_AF6 +#define TIM20_CH2N_PF5_AF2 +#define TIM20_CH2N_PG1_AF2 +#define TIM20_CH2_PC2_AF6 +#define TIM20_CH2_PE3_AF6 +#define TIM20_CH2_PF13_AF2 +#define TIM20_CH3N_PE6_AF6 +#define TIM20_CH3N_PG2_AF2 +#define TIM20_CH3_PC8_AF6 +#define TIM20_CH3_PF14_AF2 +#define TIM20_CH3_PF2_AF2 +#define TIM20_CH4N_PE0_AF3 +#define TIM20_CH4N_PG3_AF6 +#define TIM20_CH4_PE1_AF6 +#define TIM20_CH4_PF15_AF2 +#define TIM20_CH4_PF3_AF2 +#define TIM20_ETR_PE0_AF6 +#define TIM20_ETR_PF11_AF2 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH1_PD3_AF2 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH2_PD4_AF2 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH3_PD7_AF2 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_CH4_PD6_AF2 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM2_ETR_PD3_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH1_PE2_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH2_PE3_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH3_PE4_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_CH4_PE5_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH1_PD12_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH2_PD13_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH3_PD14_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_CH4_PD15_AF2 +#define TIM4_CH4_PF6_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM4_ETR_PE0_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH1_PB2_AF2 +#define TIM5_CH1_PF6_AF6 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH2_PC12_AF1 +#define TIM5_CH2_PF7_AF6 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH3_PE8_AF1 +#define TIM5_CH3_PF8_AF6 +#define TIM5_CH4_PA3_AF2 +#define TIM5_CH4_PE9_AF1 +#define TIM5_CH4_PF9_AF6 +#define TIM5_ETR_PB12_AF2 +#define TIM5_ETR_PD11_AF1 +#define TIM5_ETR_PF6_AF1 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN2_PD1_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4N_PD0_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_CH4_PD1_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) +#define TIM_MODULE_20 (10) + +#define TIM_MODULE_COUNT (10) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PE0_CN +#define __PE1_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN +#define __PE6_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PF10_CN +#define __PF11_CN +#define __PF12_CN +#define __PF13_CN +#define __PF14_CN +#define __PF15_CN +#define __PF2_CN +#define __PF3_CN +#define __PF4_CN +#define __PF5_CN +#define __PF6_CN +#define __PF7_CN +#define __PF8_CN +#define __PF9_CN +#define __PG0_CN +#define __PG1_CN +#define __PG10_CN +#define __PG2_CN +#define __PG3_CN +#define __PG4_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (7) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G483QE/LQFP128/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G483QE/LQFP128/mcu_definitions.h new file mode 100644 index 000000000..fe40f8d60 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G483QE/LQFP128/mcu_definitions.h @@ -0,0 +1,664 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G483QE_LQFP128. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 +#define ADC3_PD10_CH7 +#define ADC3_PD11_CH8 +#define ADC3_PD12_CH9 +#define ADC3_PD13_CH10 +#define ADC3_PD14_CH11 +#define ADC3_PE10_CH14 +#define ADC3_PE11_CH15 +#define ADC3_PE12_CH16 +#define ADC3_PE13_CH3 +#define ADC3_PE7_CH4 +#define ADC3_PE8_CH6 +#define ADC3_PE9_CH2 +#define ADC4_PB12_CH3 +#define ADC4_PB14_CH4 +#define ADC4_PB15_CH5 +#define ADC4_PD10_CH7 +#define ADC4_PD11_CH8 +#define ADC4_PD12_CH9 +#define ADC4_PD13_CH10 +#define ADC4_PD14_CH11 +#define ADC4_PD8_CH12 +#define ADC4_PD9_CH13 +#define ADC4_PE10_CH14 +#define ADC4_PE11_CH15 +#define ADC4_PE12_CH16 +#define ADC4_PE14_CH1 +#define ADC4_PE15_CH2 +#define ADC4_PE8_CH6 +#define ADC5_PA8_CH1 +#define ADC5_PA9_CH2 +#define ADC5_PD10_CH7 +#define ADC5_PD11_CH8 +#define ADC5_PD12_CH9 +#define ADC5_PD13_CH10 +#define ADC5_PD14_CH11 +#define ADC5_PD8_CH12 +#define ADC5_PD9_CH13 +#define ADC5_PE10_CH14 +#define ADC5_PE11_CH15 +#define ADC5_PE12_CH16 +#define ADC5_PE8_CH6 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) +#define ADC_MODULE_4 (4) +#define ADC_MODULE_5 (5) + +#define ADC_MODULE_COUNT (5) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_RX_PD0_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN1_TX_PD1_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 +#define FDCAN3_RX_PA8_AF11 +#define FDCAN3_RX_PB3_AF11 +#define FDCAN3_TX_PA15_AF11 +#define FDCAN3_TX_PB4_AF11 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) +#define CAN_MODULE_3 (3) + +#define CAN_MODULE_COUNT (3) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +#define HAL_LL_FDCAN3_GPIO_AF11 (11) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SCL_PF6_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SCL_PF3_AF4 +#define I2C3_SCL_PG7_AF4 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 +#define I2C3_SDA_PF4_AF4 +#define I2C3_SDA_PG8_AF4 +#define I2C4_SCL_PA13_AF3 +#define I2C4_SCL_PC6_AF8 +#define I2C4_SCL_PF14_AF4 +#define I2C4_SCL_PG3_AF4 +#define I2C4_SDA_PB7_AF3 +#define I2C4_SDA_PC7_AF8 +#define I2C4_SDA_PF15_AF4 +#define I2C4_SDA_PG4_AF4 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_RX_PG8_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define LPUART1_TX_PG7_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define UART5_RX_PD2_AF5 +#define UART5_TX_PC12_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_RX_PE1_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART1_TX_PE0_AF7 +#define USART1_TX_PG9_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_RX_PD6_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART2_TX_PD5_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PD9_AF7 +#define USART3_RX_PE15_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PD8_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MISO_PG3_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_MOSI_PG4_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI1_SCK_PG2_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF10_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI2_SCK_PF9_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 +#define SPI3_SCK_PG9_AF6 +#define SPI4_MISO_PE13_AF5 +#define SPI4_MISO_PE5_AF5 +#define SPI4_MOSI_PE14_AF5 +#define SPI4_MOSI_PE6_AF5 +#define SPI4_SCK_PE12_AF5 +#define SPI4_SCK_PE2_AF5 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) +#define SPI_MODULE_4 (4) + +#define SPI_MODULE_COUNT (4) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1N_PG9_AF14 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH1_PF9_AF3 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM15_CH2_PF10_AF3 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM16_CH1_PE0_AF4 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM17_CH1_PE1_AF4 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN2_PE14_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_BKIN_PE15_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1N_PE8_AF2 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH1_PE9_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2N_PE10_AF2 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH2_PE11_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PE12_AF2 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH3_PE13_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4N_PE15_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_CH4_PE14_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM1_ETR_PE7_AF2 +#define TIM20_BKIN2_PF10_AF2 +#define TIM20_BKIN2_PF8_AF2 +#define TIM20_BKIN2_PG4_AF2 +#define TIM20_BKIN_PF7_AF2 +#define TIM20_BKIN_PF9_AF2 +#define TIM20_BKIN_PG3_AF2 +#define TIM20_BKIN_PG6_AF2 +#define TIM20_CH1N_PE4_AF6 +#define TIM20_CH1N_PF4_AF3 +#define TIM20_CH1N_PG0_AF2 +#define TIM20_CH1_PB2_AF3 +#define TIM20_CH1_PE2_AF6 +#define TIM20_CH1_PF12_AF2 +#define TIM20_CH2N_PE5_AF6 +#define TIM20_CH2N_PF5_AF2 +#define TIM20_CH2N_PG1_AF2 +#define TIM20_CH2_PC2_AF6 +#define TIM20_CH2_PE3_AF6 +#define TIM20_CH2_PF13_AF2 +#define TIM20_CH3N_PE6_AF6 +#define TIM20_CH3N_PG2_AF2 +#define TIM20_CH3_PC8_AF6 +#define TIM20_CH3_PF14_AF2 +#define TIM20_CH3_PF2_AF2 +#define TIM20_CH4N_PE0_AF3 +#define TIM20_CH4N_PG3_AF6 +#define TIM20_CH4_PE1_AF6 +#define TIM20_CH4_PF15_AF2 +#define TIM20_CH4_PF3_AF2 +#define TIM20_ETR_PE0_AF6 +#define TIM20_ETR_PF11_AF2 +#define TIM20_ETR_PG5_AF2 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH1_PD3_AF2 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH2_PD4_AF2 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH3_PD7_AF2 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_CH4_PD6_AF2 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM2_ETR_PD3_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH1_PE2_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH2_PE3_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH3_PE4_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_CH4_PE5_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH1_PD12_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH2_PD13_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH3_PD14_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_CH4_PD15_AF2 +#define TIM4_CH4_PF6_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM4_ETR_PE0_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH1_PB2_AF2 +#define TIM5_CH1_PF6_AF6 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH2_PC12_AF1 +#define TIM5_CH2_PF7_AF6 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH3_PE8_AF1 +#define TIM5_CH3_PF8_AF6 +#define TIM5_CH4_PA3_AF2 +#define TIM5_CH4_PE9_AF1 +#define TIM5_CH4_PF9_AF6 +#define TIM5_ETR_PB12_AF2 +#define TIM5_ETR_PD11_AF1 +#define TIM5_ETR_PF6_AF1 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN2_PD1_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4N_PD0_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_CH4_PD1_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) +#define TIM_MODULE_20 (10) + +#define TIM_MODULE_COUNT (10) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PE0_CN +#define __PE1_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN +#define __PE6_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PF10_CN +#define __PF11_CN +#define __PF12_CN +#define __PF13_CN +#define __PF14_CN +#define __PF15_CN +#define __PF2_CN +#define __PF3_CN +#define __PF4_CN +#define __PF5_CN +#define __PF6_CN +#define __PF7_CN +#define __PF8_CN +#define __PF9_CN +#define __PG0_CN +#define __PG1_CN +#define __PG10_CN +#define __PG2_CN +#define __PG3_CN +#define __PG4_CN +#define __PG5_CN +#define __PG6_CN +#define __PG7_CN +#define __PG8_CN +#define __PG9_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (7) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G483RE/LQFP64/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G483RE/LQFP64/mcu_definitions.h new file mode 100644 index 000000000..b83612325 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G483RE/LQFP64/mcu_definitions.h @@ -0,0 +1,467 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G483RE_LQFP64. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 +#define ADC4_PB12_CH3 +#define ADC4_PB14_CH4 +#define ADC4_PB15_CH5 +#define ADC5_PA8_CH1 +#define ADC5_PA9_CH2 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) +#define ADC_MODULE_4 (4) +#define ADC_MODULE_5 (5) + +#define ADC_MODULE_COUNT (5) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 +#define FDCAN3_RX_PA8_AF11 +#define FDCAN3_RX_PB3_AF11 +#define FDCAN3_TX_PA15_AF11 +#define FDCAN3_TX_PB4_AF11 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) +#define CAN_MODULE_3 (3) + +#define CAN_MODULE_COUNT (3) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +#define HAL_LL_FDCAN3_GPIO_AF11 (11) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 +#define I2C4_SCL_PA13_AF3 +#define I2C4_SCL_PC6_AF8 +#define I2C4_SDA_PB7_AF3 +#define I2C4_SDA_PC7_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define UART5_RX_PD2_AF5 +#define UART5_TX_PC12_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM20_CH1_PB2_AF3 +#define TIM20_CH2_PC2_AF6 +#define TIM20_CH3_PC8_AF6 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH1_PB2_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH2_PC12_AF1 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH4_PA3_AF2 +#define TIM5_ETR_PB12_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) +#define TIM_MODULE_20 (10) + +#define TIM_MODULE_COUNT (10) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD2_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (6) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G483VE/LQFP100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G483VE/LQFP100/mcu_definitions.h new file mode 100644 index 000000000..fa2b04d25 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G483VE/LQFP100/mcu_definitions.h @@ -0,0 +1,603 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G483VE_LQFP100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 +#define ADC3_PD10_CH7 +#define ADC3_PD11_CH8 +#define ADC3_PD12_CH9 +#define ADC3_PD13_CH10 +#define ADC3_PD14_CH11 +#define ADC3_PE10_CH14 +#define ADC3_PE11_CH15 +#define ADC3_PE12_CH16 +#define ADC3_PE13_CH3 +#define ADC3_PE7_CH4 +#define ADC3_PE8_CH6 +#define ADC3_PE9_CH2 +#define ADC4_PB12_CH3 +#define ADC4_PB14_CH4 +#define ADC4_PB15_CH5 +#define ADC4_PD10_CH7 +#define ADC4_PD11_CH8 +#define ADC4_PD12_CH9 +#define ADC4_PD13_CH10 +#define ADC4_PD14_CH11 +#define ADC4_PD8_CH12 +#define ADC4_PD9_CH13 +#define ADC4_PE10_CH14 +#define ADC4_PE11_CH15 +#define ADC4_PE12_CH16 +#define ADC4_PE14_CH1 +#define ADC4_PE15_CH2 +#define ADC4_PE8_CH6 +#define ADC5_PA8_CH1 +#define ADC5_PA9_CH2 +#define ADC5_PD10_CH7 +#define ADC5_PD11_CH8 +#define ADC5_PD12_CH9 +#define ADC5_PD13_CH10 +#define ADC5_PD14_CH11 +#define ADC5_PD8_CH12 +#define ADC5_PD9_CH13 +#define ADC5_PE10_CH14 +#define ADC5_PE11_CH15 +#define ADC5_PE12_CH16 +#define ADC5_PE8_CH6 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) +#define ADC_MODULE_4 (4) +#define ADC_MODULE_5 (5) + +#define ADC_MODULE_COUNT (5) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_RX_PD0_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN1_TX_PD1_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 +#define FDCAN3_RX_PA8_AF11 +#define FDCAN3_RX_PB3_AF11 +#define FDCAN3_TX_PA15_AF11 +#define FDCAN3_TX_PB4_AF11 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) +#define CAN_MODULE_3 (3) + +#define CAN_MODULE_COUNT (3) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +#define HAL_LL_FDCAN3_GPIO_AF11 (11) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 +#define I2C4_SCL_PA13_AF3 +#define I2C4_SCL_PC6_AF8 +#define I2C4_SDA_PB7_AF3 +#define I2C4_SDA_PC7_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define UART5_RX_PD2_AF5 +#define UART5_TX_PC12_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_RX_PE1_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART1_TX_PE0_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_RX_PD6_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART2_TX_PD5_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PD9_AF7 +#define USART3_RX_PE15_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PD8_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF10_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI2_SCK_PF9_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 +#define SPI4_MISO_PE13_AF5 +#define SPI4_MISO_PE5_AF5 +#define SPI4_MOSI_PE14_AF5 +#define SPI4_MOSI_PE6_AF5 +#define SPI4_SCK_PE12_AF5 +#define SPI4_SCK_PE2_AF5 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) +#define SPI_MODULE_4 (4) + +#define SPI_MODULE_COUNT (4) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH1_PF9_AF3 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM15_CH2_PF10_AF3 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM16_CH1_PE0_AF4 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM17_CH1_PE1_AF4 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN2_PE14_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_BKIN_PE15_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1N_PE8_AF2 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH1_PE9_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2N_PE10_AF2 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH2_PE11_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PE12_AF2 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH3_PE13_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4N_PE15_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_CH4_PE14_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM1_ETR_PE7_AF2 +#define TIM20_BKIN2_PF10_AF2 +#define TIM20_BKIN_PF9_AF2 +#define TIM20_CH1N_PE4_AF6 +#define TIM20_CH1_PB2_AF3 +#define TIM20_CH1_PE2_AF6 +#define TIM20_CH2N_PE5_AF6 +#define TIM20_CH2_PC2_AF6 +#define TIM20_CH2_PE3_AF6 +#define TIM20_CH3N_PE6_AF6 +#define TIM20_CH3_PC8_AF6 +#define TIM20_CH3_PF2_AF2 +#define TIM20_CH4N_PE0_AF3 +#define TIM20_CH4_PE1_AF6 +#define TIM20_ETR_PE0_AF6 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH1_PD3_AF2 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH2_PD4_AF2 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH3_PD7_AF2 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_CH4_PD6_AF2 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM2_ETR_PD3_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH1_PE2_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH2_PE3_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH3_PE4_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_CH4_PE5_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH1_PD12_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH2_PD13_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH3_PD14_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_CH4_PD15_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM4_ETR_PE0_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH1_PB2_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH2_PC12_AF1 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH3_PE8_AF1 +#define TIM5_CH4_PA3_AF2 +#define TIM5_CH4_PE9_AF1 +#define TIM5_CH4_PF9_AF6 +#define TIM5_ETR_PB12_AF2 +#define TIM5_ETR_PD11_AF1 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN2_PD1_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4N_PD0_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_CH4_PD1_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) +#define TIM_MODULE_20 (10) + +#define TIM_MODULE_COUNT (10) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PE0_CN +#define __PE1_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN +#define __PE6_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PF10_CN +#define __PF2_CN +#define __PF9_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (7) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G483VE/TFBGA100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G483VE/TFBGA100/mcu_definitions.h new file mode 100644 index 000000000..0ca043e02 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G483VE/TFBGA100/mcu_definitions.h @@ -0,0 +1,603 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G483VE_TFBGA100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 +#define ADC3_PD10_CH7 +#define ADC3_PD11_CH8 +#define ADC3_PD12_CH9 +#define ADC3_PD13_CH10 +#define ADC3_PD14_CH11 +#define ADC3_PE10_CH14 +#define ADC3_PE11_CH15 +#define ADC3_PE12_CH16 +#define ADC3_PE13_CH3 +#define ADC3_PE7_CH4 +#define ADC3_PE8_CH6 +#define ADC3_PE9_CH2 +#define ADC4_PB12_CH3 +#define ADC4_PB14_CH4 +#define ADC4_PB15_CH5 +#define ADC4_PD10_CH7 +#define ADC4_PD11_CH8 +#define ADC4_PD12_CH9 +#define ADC4_PD13_CH10 +#define ADC4_PD14_CH11 +#define ADC4_PD8_CH12 +#define ADC4_PD9_CH13 +#define ADC4_PE10_CH14 +#define ADC4_PE11_CH15 +#define ADC4_PE12_CH16 +#define ADC4_PE14_CH1 +#define ADC4_PE15_CH2 +#define ADC4_PE8_CH6 +#define ADC5_PA8_CH1 +#define ADC5_PA9_CH2 +#define ADC5_PD10_CH7 +#define ADC5_PD11_CH8 +#define ADC5_PD12_CH9 +#define ADC5_PD13_CH10 +#define ADC5_PD14_CH11 +#define ADC5_PD8_CH12 +#define ADC5_PD9_CH13 +#define ADC5_PE10_CH14 +#define ADC5_PE11_CH15 +#define ADC5_PE12_CH16 +#define ADC5_PE8_CH6 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) +#define ADC_MODULE_4 (4) +#define ADC_MODULE_5 (5) + +#define ADC_MODULE_COUNT (5) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_RX_PD0_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN1_TX_PD1_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 +#define FDCAN3_RX_PA8_AF11 +#define FDCAN3_RX_PB3_AF11 +#define FDCAN3_TX_PA15_AF11 +#define FDCAN3_TX_PB4_AF11 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) +#define CAN_MODULE_3 (3) + +#define CAN_MODULE_COUNT (3) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +#define HAL_LL_FDCAN3_GPIO_AF11 (11) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 +#define I2C4_SCL_PA13_AF3 +#define I2C4_SCL_PC6_AF8 +#define I2C4_SDA_PB7_AF3 +#define I2C4_SDA_PC7_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define UART5_RX_PD2_AF5 +#define UART5_TX_PC12_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_RX_PE1_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART1_TX_PE0_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_RX_PD6_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART2_TX_PD5_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PD9_AF7 +#define USART3_RX_PE15_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PD8_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF10_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI2_SCK_PF9_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 +#define SPI4_MISO_PE13_AF5 +#define SPI4_MISO_PE5_AF5 +#define SPI4_MOSI_PE14_AF5 +#define SPI4_MOSI_PE6_AF5 +#define SPI4_SCK_PE12_AF5 +#define SPI4_SCK_PE2_AF5 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) +#define SPI_MODULE_4 (4) + +#define SPI_MODULE_COUNT (4) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH1_PF9_AF3 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM15_CH2_PF10_AF3 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM16_CH1_PE0_AF4 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM17_CH1_PE1_AF4 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN2_PE14_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_BKIN_PE15_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1N_PE8_AF2 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH1_PE9_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2N_PE10_AF2 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH2_PE11_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PE12_AF2 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH3_PE13_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4N_PE15_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_CH4_PE14_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM1_ETR_PE7_AF2 +#define TIM20_BKIN2_PF10_AF2 +#define TIM20_BKIN_PF9_AF2 +#define TIM20_CH1N_PE4_AF6 +#define TIM20_CH1_PB2_AF3 +#define TIM20_CH1_PE2_AF6 +#define TIM20_CH2N_PE5_AF6 +#define TIM20_CH2_PC2_AF6 +#define TIM20_CH2_PE3_AF6 +#define TIM20_CH3N_PE6_AF6 +#define TIM20_CH3_PC8_AF6 +#define TIM20_CH3_PF2_AF2 +#define TIM20_CH4N_PE0_AF3 +#define TIM20_CH4_PE1_AF6 +#define TIM20_ETR_PE0_AF6 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH1_PD3_AF2 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH2_PD4_AF2 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH3_PD7_AF2 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_CH4_PD6_AF2 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM2_ETR_PD3_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH1_PE2_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH2_PE3_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH3_PE4_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_CH4_PE5_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH1_PD12_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH2_PD13_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH3_PD14_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_CH4_PD15_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM4_ETR_PE0_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH1_PB2_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH2_PC12_AF1 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH3_PE8_AF1 +#define TIM5_CH4_PA3_AF2 +#define TIM5_CH4_PE9_AF1 +#define TIM5_CH4_PF9_AF6 +#define TIM5_ETR_PB12_AF2 +#define TIM5_ETR_PD11_AF1 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN2_PD1_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4N_PD0_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_CH4_PD1_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) +#define TIM_MODULE_20 (10) + +#define TIM_MODULE_COUNT (10) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PE0_CN +#define __PE1_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN +#define __PE6_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PF10_CN +#define __PF2_CN +#define __PF9_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (7) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G484CE/LQFP48/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G484CE/LQFP48/mcu_definitions.h new file mode 100644 index 000000000..97ea8a7b0 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G484CE/LQFP48/mcu_definitions.h @@ -0,0 +1,399 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G484CE_LQFP48. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 +#define ADC4_PB12_CH3 +#define ADC4_PB14_CH4 +#define ADC4_PB15_CH5 +#define ADC5_PA8_CH1 +#define ADC5_PA9_CH2 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) +#define ADC_MODULE_4 (4) +#define ADC_MODULE_5 (5) + +#define ADC_MODULE_COUNT (5) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 +#define FDCAN3_RX_PA8_AF11 +#define FDCAN3_RX_PB3_AF11 +#define FDCAN3_TX_PA15_AF11 +#define FDCAN3_TX_PB4_AF11 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) +#define CAN_MODULE_3 (3) + +#define CAN_MODULE_COUNT (3) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +#define HAL_LL_FDCAN3_GPIO_AF11 (11) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SDA_PB5_AF8 +#define I2C4_SCL_PA13_AF3 +#define I2C4_SDA_PB7_AF3 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) + +#define UART_MODULE_COUNT (3) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_SCK_PB3_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define HRTIM1_CHA1_PA8_AF13 +#define HRTIM1_CHA2_PA9_AF13 +#define HRTIM1_CHB1_PA10_AF13 +#define HRTIM1_CHB2_PA11_AF13 +#define HRTIM1_CHC1_PB12_AF13 +#define HRTIM1_CHC2_PB13_AF13 +#define HRTIM1_CHD1_PB14_AF13 +#define HRTIM1_CHD2_PB15_AF13 +#define LPTIM1_ETR_PB6_AF11 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_ETR_PA12_AF11 +#define TIM20_CH1_PB2_AF3 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_ETR_PB3_AF10 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH1_PB2_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH4_PA3_AF2 +#define TIM5_ETR_PB12_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) +#define TIM_MODULE_20 (10) + +#define TIM_MODULE_COUNT (10) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G484CE/UFQFPN48/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G484CE/UFQFPN48/mcu_definitions.h new file mode 100644 index 000000000..f1e872bb9 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G484CE/UFQFPN48/mcu_definitions.h @@ -0,0 +1,423 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G484CE_UFQFPN48. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC4_CH5 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 +#define ADC4_PB12_CH3 +#define ADC4_PB14_CH4 +#define ADC4_PB15_CH5 +#define ADC5_PA8_CH1 +#define ADC5_PA9_CH2 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) +#define ADC_MODULE_4 (4) +#define ADC_MODULE_5 (5) + +#define ADC_MODULE_COUNT (5) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 +#define FDCAN3_RX_PA8_AF11 +#define FDCAN3_RX_PB3_AF11 +#define FDCAN3_TX_PA15_AF11 +#define FDCAN3_TX_PB4_AF11 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) +#define CAN_MODULE_3 (3) + +#define CAN_MODULE_COUNT (3) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +#define HAL_LL_FDCAN3_GPIO_AF11 (11) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C4_SCL_PA13_AF3 +#define I2C4_SCL_PC6_AF8 +#define I2C4_SDA_PB7_AF3 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (4) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define HRTIM1_CHA1_PA8_AF13 +#define HRTIM1_CHA2_PA9_AF13 +#define HRTIM1_CHB1_PA10_AF13 +#define HRTIM1_CHB2_PA11_AF13 +#define HRTIM1_CHC1_PB12_AF13 +#define HRTIM1_CHC2_PB13_AF13 +#define HRTIM1_CHD1_PB14_AF13 +#define HRTIM1_CHD2_PB15_AF13 +#define HRTIM1_CHF1_PC6_AF13 +#define LPTIM1_ETR_PB6_AF11 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM20_CH1_PB2_AF3 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_ETR_PB3_AF10 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH1_PB2_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH4_PA3_AF2 +#define TIM5_ETR_PB12_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) +#define TIM_MODULE_20 (10) + +#define TIM_MODULE_COUNT (10) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC10_CN +#define __PC11_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC4_CN +#define __PC6_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G484ME/LQFP80/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G484ME/LQFP80/mcu_definitions.h new file mode 100644 index 000000000..b18b0caae --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G484ME/LQFP80/mcu_definitions.h @@ -0,0 +1,543 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G484ME_LQFP80. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 +#define ADC3_PD10_CH7 +#define ADC3_PE10_CH14 +#define ADC3_PE11_CH15 +#define ADC3_PE12_CH16 +#define ADC3_PE13_CH3 +#define ADC3_PE7_CH4 +#define ADC3_PE8_CH6 +#define ADC3_PE9_CH2 +#define ADC4_PB12_CH3 +#define ADC4_PB14_CH4 +#define ADC4_PB15_CH5 +#define ADC4_PD10_CH7 +#define ADC4_PD8_CH12 +#define ADC4_PD9_CH13 +#define ADC4_PE10_CH14 +#define ADC4_PE11_CH15 +#define ADC4_PE12_CH16 +#define ADC4_PE14_CH1 +#define ADC4_PE15_CH2 +#define ADC4_PE8_CH6 +#define ADC5_PA8_CH1 +#define ADC5_PA9_CH2 +#define ADC5_PD10_CH7 +#define ADC5_PD8_CH12 +#define ADC5_PD9_CH13 +#define ADC5_PE10_CH14 +#define ADC5_PE11_CH15 +#define ADC5_PE12_CH16 +#define ADC5_PE8_CH6 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) +#define ADC_MODULE_4 (4) +#define ADC_MODULE_5 (5) + +#define ADC_MODULE_COUNT (5) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_RX_PD0_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN1_TX_PD1_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 +#define FDCAN3_RX_PA8_AF11 +#define FDCAN3_RX_PB3_AF11 +#define FDCAN3_TX_PA15_AF11 +#define FDCAN3_TX_PB4_AF11 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) +#define CAN_MODULE_3 (3) + +#define CAN_MODULE_COUNT (3) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +#define HAL_LL_FDCAN3_GPIO_AF11 (11) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 +#define I2C4_SCL_PA13_AF3 +#define I2C4_SCL_PC6_AF8 +#define I2C4_SDA_PB7_AF3 +#define I2C4_SDA_PC7_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define UART5_RX_PD2_AF5 +#define UART5_TX_PC12_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PD9_AF7 +#define USART3_RX_PE15_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PD8_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 +#define SPI4_MISO_PE13_AF5 +#define SPI4_MOSI_PE14_AF5 +#define SPI4_SCK_PE12_AF5 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) +#define SPI_MODULE_4 (4) + +#define SPI_MODULE_COUNT (4) +// EOF SPI + +// TIM +#define HRTIM1_CHA1_PA8_AF13 +#define HRTIM1_CHA2_PA9_AF13 +#define HRTIM1_CHB1_PA10_AF13 +#define HRTIM1_CHB2_PA11_AF13 +#define HRTIM1_CHC1_PB12_AF13 +#define HRTIM1_CHC2_PB13_AF13 +#define HRTIM1_CHD1_PB14_AF13 +#define HRTIM1_CHD2_PB15_AF13 +#define HRTIM1_CHE1_PC8_AF3 +#define HRTIM1_CHE2_PC9_AF3 +#define HRTIM1_CHF1_PC6_AF13 +#define HRTIM1_CHF2_PC7_AF13 +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN2_PE14_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_BKIN_PE15_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1N_PE8_AF2 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH1_PE9_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2N_PE10_AF2 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH2_PE11_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PE12_AF2 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH3_PE13_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4N_PE15_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_CH4_PE14_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM1_ETR_PE7_AF2 +#define TIM20_CH1_PB2_AF3 +#define TIM20_CH2_PC2_AF6 +#define TIM20_CH3_PC8_AF6 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH1_PB2_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH2_PC12_AF1 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH3_PE8_AF1 +#define TIM5_CH4_PA3_AF2 +#define TIM5_CH4_PE9_AF1 +#define TIM5_ETR_PB12_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN2_PD1_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4N_PD0_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_CH4_PD1_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) +#define TIM_MODULE_20 (10) + +#define TIM_MODULE_COUNT (10) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD2_CN +#define __PD8_CN +#define __PD9_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (7) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G484ME/WLCSP81/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G484ME/WLCSP81/mcu_definitions.h new file mode 100644 index 000000000..81b2c6fde --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G484ME/WLCSP81/mcu_definitions.h @@ -0,0 +1,548 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G484ME_WLCSP81. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 +#define ADC3_PD10_CH7 +#define ADC3_PD11_CH8 +#define ADC3_PE10_CH14 +#define ADC3_PE11_CH15 +#define ADC3_PE12_CH16 +#define ADC3_PE13_CH3 +#define ADC3_PE7_CH4 +#define ADC3_PE8_CH6 +#define ADC3_PE9_CH2 +#define ADC4_PB12_CH3 +#define ADC4_PB14_CH4 +#define ADC4_PB15_CH5 +#define ADC4_PD10_CH7 +#define ADC4_PD11_CH8 +#define ADC4_PD8_CH12 +#define ADC4_PD9_CH13 +#define ADC4_PE10_CH14 +#define ADC4_PE11_CH15 +#define ADC4_PE12_CH16 +#define ADC4_PE14_CH1 +#define ADC4_PE15_CH2 +#define ADC4_PE8_CH6 +#define ADC5_PA8_CH1 +#define ADC5_PA9_CH2 +#define ADC5_PD10_CH7 +#define ADC5_PD11_CH8 +#define ADC5_PD8_CH12 +#define ADC5_PD9_CH13 +#define ADC5_PE10_CH14 +#define ADC5_PE11_CH15 +#define ADC5_PE12_CH16 +#define ADC5_PE8_CH6 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) +#define ADC_MODULE_4 (4) +#define ADC_MODULE_5 (5) + +#define ADC_MODULE_COUNT (5) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_RX_PD0_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN1_TX_PD1_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 +#define FDCAN3_RX_PA8_AF11 +#define FDCAN3_RX_PB3_AF11 +#define FDCAN3_TX_PA15_AF11 +#define FDCAN3_TX_PB4_AF11 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) +#define CAN_MODULE_3 (3) + +#define CAN_MODULE_COUNT (3) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +#define HAL_LL_FDCAN3_GPIO_AF11 (11) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 +#define I2C4_SCL_PA13_AF3 +#define I2C4_SCL_PC6_AF8 +#define I2C4_SDA_PB7_AF3 +#define I2C4_SDA_PC7_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define UART5_RX_PD2_AF5 +#define UART5_TX_PC12_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PD9_AF7 +#define USART3_RX_PE15_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PD8_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 +#define SPI4_MISO_PE13_AF5 +#define SPI4_MOSI_PE14_AF5 +#define SPI4_SCK_PE12_AF5 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) +#define SPI_MODULE_4 (4) + +#define SPI_MODULE_COUNT (4) +// EOF SPI + +// TIM +#define HRTIM1_CHA1_PA8_AF13 +#define HRTIM1_CHA2_PA9_AF13 +#define HRTIM1_CHB1_PA10_AF13 +#define HRTIM1_CHB2_PA11_AF13 +#define HRTIM1_CHC1_PB12_AF13 +#define HRTIM1_CHC2_PB13_AF13 +#define HRTIM1_CHD1_PB14_AF13 +#define HRTIM1_CHD2_PB15_AF13 +#define HRTIM1_CHE1_PC8_AF3 +#define HRTIM1_CHE2_PC9_AF3 +#define HRTIM1_CHF1_PC6_AF13 +#define HRTIM1_CHF2_PC7_AF13 +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN2_PE14_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_BKIN_PE15_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1N_PE8_AF2 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH1_PE9_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2N_PE10_AF2 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH2_PE11_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PE12_AF2 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH3_PE13_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4N_PE15_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_CH4_PE14_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM1_ETR_PE7_AF2 +#define TIM20_CH1_PB2_AF3 +#define TIM20_CH2_PC2_AF6 +#define TIM20_CH3_PC8_AF6 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH1_PB2_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH2_PC12_AF1 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH3_PE8_AF1 +#define TIM5_CH4_PA3_AF2 +#define TIM5_CH4_PE9_AF1 +#define TIM5_ETR_PB12_AF2 +#define TIM5_ETR_PD11_AF1 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN2_PD1_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4N_PD0_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_CH4_PD1_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) +#define TIM_MODULE_20 (10) + +#define TIM_MODULE_COUNT (10) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD11_CN +#define __PD2_CN +#define __PD8_CN +#define __PD9_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (7) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G484PE/UFBGA121/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G484PE/UFBGA121/mcu_definitions.h new file mode 100644 index 000000000..cb7cf97f2 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G484PE/UFBGA121/mcu_definitions.h @@ -0,0 +1,662 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G484PE_UFBGA121. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 +#define ADC3_PD10_CH7 +#define ADC3_PD11_CH8 +#define ADC3_PD12_CH9 +#define ADC3_PD13_CH10 +#define ADC3_PD14_CH11 +#define ADC3_PE10_CH14 +#define ADC3_PE11_CH15 +#define ADC3_PE12_CH16 +#define ADC3_PE13_CH3 +#define ADC3_PE7_CH4 +#define ADC3_PE8_CH6 +#define ADC3_PE9_CH2 +#define ADC4_PB12_CH3 +#define ADC4_PB14_CH4 +#define ADC4_PB15_CH5 +#define ADC4_PD10_CH7 +#define ADC4_PD11_CH8 +#define ADC4_PD12_CH9 +#define ADC4_PD13_CH10 +#define ADC4_PD14_CH11 +#define ADC4_PD8_CH12 +#define ADC4_PD9_CH13 +#define ADC4_PE10_CH14 +#define ADC4_PE11_CH15 +#define ADC4_PE12_CH16 +#define ADC4_PE14_CH1 +#define ADC4_PE15_CH2 +#define ADC4_PE8_CH6 +#define ADC5_PA8_CH1 +#define ADC5_PA9_CH2 +#define ADC5_PD10_CH7 +#define ADC5_PD11_CH8 +#define ADC5_PD12_CH9 +#define ADC5_PD13_CH10 +#define ADC5_PD14_CH11 +#define ADC5_PD8_CH12 +#define ADC5_PD9_CH13 +#define ADC5_PE10_CH14 +#define ADC5_PE11_CH15 +#define ADC5_PE12_CH16 +#define ADC5_PE8_CH6 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) +#define ADC_MODULE_4 (4) +#define ADC_MODULE_5 (5) + +#define ADC_MODULE_COUNT (5) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_RX_PD0_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN1_TX_PD1_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 +#define FDCAN3_RX_PA8_AF11 +#define FDCAN3_RX_PB3_AF11 +#define FDCAN3_TX_PA15_AF11 +#define FDCAN3_TX_PB4_AF11 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) +#define CAN_MODULE_3 (3) + +#define CAN_MODULE_COUNT (3) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +#define HAL_LL_FDCAN3_GPIO_AF11 (11) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SCL_PF6_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SCL_PF3_AF4 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 +#define I2C3_SDA_PF4_AF4 +#define I2C4_SCL_PA13_AF3 +#define I2C4_SCL_PC6_AF8 +#define I2C4_SCL_PF14_AF4 +#define I2C4_SCL_PG3_AF4 +#define I2C4_SDA_PB7_AF3 +#define I2C4_SDA_PC7_AF8 +#define I2C4_SDA_PF15_AF4 +#define I2C4_SDA_PG4_AF4 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define UART5_RX_PD2_AF5 +#define UART5_TX_PC12_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_RX_PE1_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART1_TX_PE0_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_RX_PD6_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART2_TX_PD5_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PD9_AF7 +#define USART3_RX_PE15_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PD8_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MISO_PG3_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_MOSI_PG4_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI1_SCK_PG2_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF10_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI2_SCK_PF9_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 +#define SPI4_MISO_PE13_AF5 +#define SPI4_MISO_PE5_AF5 +#define SPI4_MOSI_PE14_AF5 +#define SPI4_MOSI_PE6_AF5 +#define SPI4_SCK_PE12_AF5 +#define SPI4_SCK_PE2_AF5 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) +#define SPI_MODULE_4 (4) + +#define SPI_MODULE_COUNT (4) +// EOF SPI + +// TIM +#define HRTIM1_CHA1_PA8_AF13 +#define HRTIM1_CHA2_PA9_AF13 +#define HRTIM1_CHB1_PA10_AF13 +#define HRTIM1_CHB2_PA11_AF13 +#define HRTIM1_CHC1_PB12_AF13 +#define HRTIM1_CHC2_PB13_AF13 +#define HRTIM1_CHD1_PB14_AF13 +#define HRTIM1_CHD2_PB15_AF13 +#define HRTIM1_CHE1_PC8_AF3 +#define HRTIM1_CHE2_PC9_AF3 +#define HRTIM1_CHF1_PC6_AF13 +#define HRTIM1_CHF2_PC7_AF13 +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH1_PF9_AF3 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM15_CH2_PF10_AF3 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM16_CH1_PE0_AF4 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM17_CH1_PE1_AF4 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN2_PE14_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_BKIN_PE15_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1N_PE8_AF2 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH1_PE9_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2N_PE10_AF2 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH2_PE11_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PE12_AF2 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH3_PE13_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4N_PE15_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_CH4_PE14_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM1_ETR_PE7_AF2 +#define TIM20_BKIN2_PF10_AF2 +#define TIM20_BKIN2_PF8_AF2 +#define TIM20_BKIN2_PG4_AF2 +#define TIM20_BKIN_PF7_AF2 +#define TIM20_BKIN_PF9_AF2 +#define TIM20_BKIN_PG3_AF2 +#define TIM20_CH1N_PE4_AF6 +#define TIM20_CH1N_PF4_AF3 +#define TIM20_CH1N_PG0_AF2 +#define TIM20_CH1_PB2_AF3 +#define TIM20_CH1_PE2_AF6 +#define TIM20_CH1_PF12_AF2 +#define TIM20_CH2N_PE5_AF6 +#define TIM20_CH2N_PF5_AF2 +#define TIM20_CH2N_PG1_AF2 +#define TIM20_CH2_PC2_AF6 +#define TIM20_CH2_PE3_AF6 +#define TIM20_CH2_PF13_AF2 +#define TIM20_CH3N_PE6_AF6 +#define TIM20_CH3N_PG2_AF2 +#define TIM20_CH3_PC8_AF6 +#define TIM20_CH3_PF14_AF2 +#define TIM20_CH3_PF2_AF2 +#define TIM20_CH4N_PE0_AF3 +#define TIM20_CH4N_PG3_AF6 +#define TIM20_CH4_PE1_AF6 +#define TIM20_CH4_PF15_AF2 +#define TIM20_CH4_PF3_AF2 +#define TIM20_ETR_PE0_AF6 +#define TIM20_ETR_PF11_AF2 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH1_PD3_AF2 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH2_PD4_AF2 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH3_PD7_AF2 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_CH4_PD6_AF2 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM2_ETR_PD3_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH1_PE2_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH2_PE3_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH3_PE4_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_CH4_PE5_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH1_PD12_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH2_PD13_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH3_PD14_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_CH4_PD15_AF2 +#define TIM4_CH4_PF6_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM4_ETR_PE0_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH1_PB2_AF2 +#define TIM5_CH1_PF6_AF6 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH2_PC12_AF1 +#define TIM5_CH2_PF7_AF6 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH3_PE8_AF1 +#define TIM5_CH3_PF8_AF6 +#define TIM5_CH4_PA3_AF2 +#define TIM5_CH4_PE9_AF1 +#define TIM5_CH4_PF9_AF6 +#define TIM5_ETR_PB12_AF2 +#define TIM5_ETR_PD11_AF1 +#define TIM5_ETR_PF6_AF1 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN2_PD1_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4N_PD0_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_CH4_PD1_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) +#define TIM_MODULE_20 (10) + +#define TIM_MODULE_COUNT (10) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PE0_CN +#define __PE1_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN +#define __PE6_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PF10_CN +#define __PF11_CN +#define __PF12_CN +#define __PF13_CN +#define __PF14_CN +#define __PF15_CN +#define __PF2_CN +#define __PF3_CN +#define __PF4_CN +#define __PF5_CN +#define __PF6_CN +#define __PF7_CN +#define __PF8_CN +#define __PF9_CN +#define __PG0_CN +#define __PG1_CN +#define __PG10_CN +#define __PG2_CN +#define __PG3_CN +#define __PG4_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (7) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G484QE/LQFP128/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G484QE/LQFP128/mcu_definitions.h new file mode 100644 index 000000000..1dbeabc88 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G484QE/LQFP128/mcu_definitions.h @@ -0,0 +1,676 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G484QE_LQFP128. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 +#define ADC3_PD10_CH7 +#define ADC3_PD11_CH8 +#define ADC3_PD12_CH9 +#define ADC3_PD13_CH10 +#define ADC3_PD14_CH11 +#define ADC3_PE10_CH14 +#define ADC3_PE11_CH15 +#define ADC3_PE12_CH16 +#define ADC3_PE13_CH3 +#define ADC3_PE7_CH4 +#define ADC3_PE8_CH6 +#define ADC3_PE9_CH2 +#define ADC4_PB12_CH3 +#define ADC4_PB14_CH4 +#define ADC4_PB15_CH5 +#define ADC4_PD10_CH7 +#define ADC4_PD11_CH8 +#define ADC4_PD12_CH9 +#define ADC4_PD13_CH10 +#define ADC4_PD14_CH11 +#define ADC4_PD8_CH12 +#define ADC4_PD9_CH13 +#define ADC4_PE10_CH14 +#define ADC4_PE11_CH15 +#define ADC4_PE12_CH16 +#define ADC4_PE14_CH1 +#define ADC4_PE15_CH2 +#define ADC4_PE8_CH6 +#define ADC5_PA8_CH1 +#define ADC5_PA9_CH2 +#define ADC5_PD10_CH7 +#define ADC5_PD11_CH8 +#define ADC5_PD12_CH9 +#define ADC5_PD13_CH10 +#define ADC5_PD14_CH11 +#define ADC5_PD8_CH12 +#define ADC5_PD9_CH13 +#define ADC5_PE10_CH14 +#define ADC5_PE11_CH15 +#define ADC5_PE12_CH16 +#define ADC5_PE8_CH6 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) +#define ADC_MODULE_4 (4) +#define ADC_MODULE_5 (5) + +#define ADC_MODULE_COUNT (5) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_RX_PD0_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN1_TX_PD1_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 +#define FDCAN3_RX_PA8_AF11 +#define FDCAN3_RX_PB3_AF11 +#define FDCAN3_TX_PA15_AF11 +#define FDCAN3_TX_PB4_AF11 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) +#define CAN_MODULE_3 (3) + +#define CAN_MODULE_COUNT (3) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +#define HAL_LL_FDCAN3_GPIO_AF11 (11) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SCL_PF6_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SCL_PF3_AF4 +#define I2C3_SCL_PG7_AF4 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 +#define I2C3_SDA_PF4_AF4 +#define I2C3_SDA_PG8_AF4 +#define I2C4_SCL_PA13_AF3 +#define I2C4_SCL_PC6_AF8 +#define I2C4_SCL_PF14_AF4 +#define I2C4_SCL_PG3_AF4 +#define I2C4_SDA_PB7_AF3 +#define I2C4_SDA_PC7_AF8 +#define I2C4_SDA_PF15_AF4 +#define I2C4_SDA_PG4_AF4 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_RX_PG8_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define LPUART1_TX_PG7_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define UART5_RX_PD2_AF5 +#define UART5_TX_PC12_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_RX_PE1_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART1_TX_PE0_AF7 +#define USART1_TX_PG9_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_RX_PD6_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART2_TX_PD5_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PD9_AF7 +#define USART3_RX_PE15_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PD8_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MISO_PG3_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_MOSI_PG4_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI1_SCK_PG2_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF10_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI2_SCK_PF9_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 +#define SPI3_SCK_PG9_AF6 +#define SPI4_MISO_PE13_AF5 +#define SPI4_MISO_PE5_AF5 +#define SPI4_MOSI_PE14_AF5 +#define SPI4_MOSI_PE6_AF5 +#define SPI4_SCK_PE12_AF5 +#define SPI4_SCK_PE2_AF5 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) +#define SPI_MODULE_4 (4) + +#define SPI_MODULE_COUNT (4) +// EOF SPI + +// TIM +#define HRTIM1_CHA1_PA8_AF13 +#define HRTIM1_CHA2_PA9_AF13 +#define HRTIM1_CHB1_PA10_AF13 +#define HRTIM1_CHB2_PA11_AF13 +#define HRTIM1_CHC1_PB12_AF13 +#define HRTIM1_CHC2_PB13_AF13 +#define HRTIM1_CHD1_PB14_AF13 +#define HRTIM1_CHD2_PB15_AF13 +#define HRTIM1_CHE1_PC8_AF3 +#define HRTIM1_CHE2_PC9_AF3 +#define HRTIM1_CHF1_PC6_AF13 +#define HRTIM1_CHF2_PC7_AF13 +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1N_PG9_AF14 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH1_PF9_AF3 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM15_CH2_PF10_AF3 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM16_CH1_PE0_AF4 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM17_CH1_PE1_AF4 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN2_PE14_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_BKIN_PE15_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1N_PE8_AF2 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH1_PE9_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2N_PE10_AF2 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH2_PE11_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PE12_AF2 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH3_PE13_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4N_PE15_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_CH4_PE14_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM1_ETR_PE7_AF2 +#define TIM20_BKIN2_PF10_AF2 +#define TIM20_BKIN2_PF8_AF2 +#define TIM20_BKIN2_PG4_AF2 +#define TIM20_BKIN_PF7_AF2 +#define TIM20_BKIN_PF9_AF2 +#define TIM20_BKIN_PG3_AF2 +#define TIM20_BKIN_PG6_AF2 +#define TIM20_CH1N_PE4_AF6 +#define TIM20_CH1N_PF4_AF3 +#define TIM20_CH1N_PG0_AF2 +#define TIM20_CH1_PB2_AF3 +#define TIM20_CH1_PE2_AF6 +#define TIM20_CH1_PF12_AF2 +#define TIM20_CH2N_PE5_AF6 +#define TIM20_CH2N_PF5_AF2 +#define TIM20_CH2N_PG1_AF2 +#define TIM20_CH2_PC2_AF6 +#define TIM20_CH2_PE3_AF6 +#define TIM20_CH2_PF13_AF2 +#define TIM20_CH3N_PE6_AF6 +#define TIM20_CH3N_PG2_AF2 +#define TIM20_CH3_PC8_AF6 +#define TIM20_CH3_PF14_AF2 +#define TIM20_CH3_PF2_AF2 +#define TIM20_CH4N_PE0_AF3 +#define TIM20_CH4N_PG3_AF6 +#define TIM20_CH4_PE1_AF6 +#define TIM20_CH4_PF15_AF2 +#define TIM20_CH4_PF3_AF2 +#define TIM20_ETR_PE0_AF6 +#define TIM20_ETR_PF11_AF2 +#define TIM20_ETR_PG5_AF2 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH1_PD3_AF2 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH2_PD4_AF2 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH3_PD7_AF2 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_CH4_PD6_AF2 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM2_ETR_PD3_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH1_PE2_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH2_PE3_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH3_PE4_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_CH4_PE5_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH1_PD12_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH2_PD13_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH3_PD14_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_CH4_PD15_AF2 +#define TIM4_CH4_PF6_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM4_ETR_PE0_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH1_PB2_AF2 +#define TIM5_CH1_PF6_AF6 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH2_PC12_AF1 +#define TIM5_CH2_PF7_AF6 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH3_PE8_AF1 +#define TIM5_CH3_PF8_AF6 +#define TIM5_CH4_PA3_AF2 +#define TIM5_CH4_PE9_AF1 +#define TIM5_CH4_PF9_AF6 +#define TIM5_ETR_PB12_AF2 +#define TIM5_ETR_PD11_AF1 +#define TIM5_ETR_PF6_AF1 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN2_PD1_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4N_PD0_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_CH4_PD1_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) +#define TIM_MODULE_20 (10) + +#define TIM_MODULE_COUNT (10) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PE0_CN +#define __PE1_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN +#define __PE6_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PF10_CN +#define __PF11_CN +#define __PF12_CN +#define __PF13_CN +#define __PF14_CN +#define __PF15_CN +#define __PF2_CN +#define __PF3_CN +#define __PF4_CN +#define __PF5_CN +#define __PF6_CN +#define __PF7_CN +#define __PF8_CN +#define __PF9_CN +#define __PG0_CN +#define __PG1_CN +#define __PG10_CN +#define __PG2_CN +#define __PG3_CN +#define __PG4_CN +#define __PG5_CN +#define __PG6_CN +#define __PG7_CN +#define __PG8_CN +#define __PG9_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (7) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G484RE/LQFP64/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G484RE/LQFP64/mcu_definitions.h new file mode 100644 index 000000000..555221d91 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G484RE/LQFP64/mcu_definitions.h @@ -0,0 +1,479 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G484RE_LQFP64. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 +#define ADC4_PB12_CH3 +#define ADC4_PB14_CH4 +#define ADC4_PB15_CH5 +#define ADC5_PA8_CH1 +#define ADC5_PA9_CH2 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) +#define ADC_MODULE_4 (4) +#define ADC_MODULE_5 (5) + +#define ADC_MODULE_COUNT (5) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 +#define FDCAN3_RX_PA8_AF11 +#define FDCAN3_RX_PB3_AF11 +#define FDCAN3_TX_PA15_AF11 +#define FDCAN3_TX_PB4_AF11 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) +#define CAN_MODULE_3 (3) + +#define CAN_MODULE_COUNT (3) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +#define HAL_LL_FDCAN3_GPIO_AF11 (11) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 +#define I2C4_SCL_PA13_AF3 +#define I2C4_SCL_PC6_AF8 +#define I2C4_SDA_PB7_AF3 +#define I2C4_SDA_PC7_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define UART5_RX_PD2_AF5 +#define UART5_TX_PC12_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define HRTIM1_CHA1_PA8_AF13 +#define HRTIM1_CHA2_PA9_AF13 +#define HRTIM1_CHB1_PA10_AF13 +#define HRTIM1_CHB2_PA11_AF13 +#define HRTIM1_CHC1_PB12_AF13 +#define HRTIM1_CHC2_PB13_AF13 +#define HRTIM1_CHD1_PB14_AF13 +#define HRTIM1_CHD2_PB15_AF13 +#define HRTIM1_CHE1_PC8_AF3 +#define HRTIM1_CHE2_PC9_AF3 +#define HRTIM1_CHF1_PC6_AF13 +#define HRTIM1_CHF2_PC7_AF13 +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM20_CH1_PB2_AF3 +#define TIM20_CH2_PC2_AF6 +#define TIM20_CH3_PC8_AF6 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH1_PB2_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH2_PC12_AF1 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH4_PA3_AF2 +#define TIM5_ETR_PB12_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) +#define TIM_MODULE_20 (10) + +#define TIM_MODULE_COUNT (10) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD2_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (6) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G484VE/LQFP100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G484VE/LQFP100/mcu_definitions.h new file mode 100644 index 000000000..945843a09 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G484VE/LQFP100/mcu_definitions.h @@ -0,0 +1,615 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G484VE_LQFP100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 +#define ADC3_PD10_CH7 +#define ADC3_PD11_CH8 +#define ADC3_PD12_CH9 +#define ADC3_PD13_CH10 +#define ADC3_PD14_CH11 +#define ADC3_PE10_CH14 +#define ADC3_PE11_CH15 +#define ADC3_PE12_CH16 +#define ADC3_PE13_CH3 +#define ADC3_PE7_CH4 +#define ADC3_PE8_CH6 +#define ADC3_PE9_CH2 +#define ADC4_PB12_CH3 +#define ADC4_PB14_CH4 +#define ADC4_PB15_CH5 +#define ADC4_PD10_CH7 +#define ADC4_PD11_CH8 +#define ADC4_PD12_CH9 +#define ADC4_PD13_CH10 +#define ADC4_PD14_CH11 +#define ADC4_PD8_CH12 +#define ADC4_PD9_CH13 +#define ADC4_PE10_CH14 +#define ADC4_PE11_CH15 +#define ADC4_PE12_CH16 +#define ADC4_PE14_CH1 +#define ADC4_PE15_CH2 +#define ADC4_PE8_CH6 +#define ADC5_PA8_CH1 +#define ADC5_PA9_CH2 +#define ADC5_PD10_CH7 +#define ADC5_PD11_CH8 +#define ADC5_PD12_CH9 +#define ADC5_PD13_CH10 +#define ADC5_PD14_CH11 +#define ADC5_PD8_CH12 +#define ADC5_PD9_CH13 +#define ADC5_PE10_CH14 +#define ADC5_PE11_CH15 +#define ADC5_PE12_CH16 +#define ADC5_PE8_CH6 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) +#define ADC_MODULE_4 (4) +#define ADC_MODULE_5 (5) + +#define ADC_MODULE_COUNT (5) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_RX_PD0_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN1_TX_PD1_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 +#define FDCAN3_RX_PA8_AF11 +#define FDCAN3_RX_PB3_AF11 +#define FDCAN3_TX_PA15_AF11 +#define FDCAN3_TX_PB4_AF11 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) +#define CAN_MODULE_3 (3) + +#define CAN_MODULE_COUNT (3) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +#define HAL_LL_FDCAN3_GPIO_AF11 (11) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 +#define I2C4_SCL_PA13_AF3 +#define I2C4_SCL_PC6_AF8 +#define I2C4_SDA_PB7_AF3 +#define I2C4_SDA_PC7_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define UART5_RX_PD2_AF5 +#define UART5_TX_PC12_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_RX_PE1_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART1_TX_PE0_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_RX_PD6_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART2_TX_PD5_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PD9_AF7 +#define USART3_RX_PE15_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PD8_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF10_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI2_SCK_PF9_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 +#define SPI4_MISO_PE13_AF5 +#define SPI4_MISO_PE5_AF5 +#define SPI4_MOSI_PE14_AF5 +#define SPI4_MOSI_PE6_AF5 +#define SPI4_SCK_PE12_AF5 +#define SPI4_SCK_PE2_AF5 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) +#define SPI_MODULE_4 (4) + +#define SPI_MODULE_COUNT (4) +// EOF SPI + +// TIM +#define HRTIM1_CHA1_PA8_AF13 +#define HRTIM1_CHA2_PA9_AF13 +#define HRTIM1_CHB1_PA10_AF13 +#define HRTIM1_CHB2_PA11_AF13 +#define HRTIM1_CHC1_PB12_AF13 +#define HRTIM1_CHC2_PB13_AF13 +#define HRTIM1_CHD1_PB14_AF13 +#define HRTIM1_CHD2_PB15_AF13 +#define HRTIM1_CHE1_PC8_AF3 +#define HRTIM1_CHE2_PC9_AF3 +#define HRTIM1_CHF1_PC6_AF13 +#define HRTIM1_CHF2_PC7_AF13 +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH1_PF9_AF3 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM15_CH2_PF10_AF3 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM16_CH1_PE0_AF4 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM17_CH1_PE1_AF4 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN2_PE14_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_BKIN_PE15_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1N_PE8_AF2 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH1_PE9_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2N_PE10_AF2 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH2_PE11_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PE12_AF2 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH3_PE13_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4N_PE15_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_CH4_PE14_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM1_ETR_PE7_AF2 +#define TIM20_BKIN2_PF10_AF2 +#define TIM20_BKIN_PF9_AF2 +#define TIM20_CH1N_PE4_AF6 +#define TIM20_CH1_PB2_AF3 +#define TIM20_CH1_PE2_AF6 +#define TIM20_CH2N_PE5_AF6 +#define TIM20_CH2_PC2_AF6 +#define TIM20_CH2_PE3_AF6 +#define TIM20_CH3N_PE6_AF6 +#define TIM20_CH3_PC8_AF6 +#define TIM20_CH3_PF2_AF2 +#define TIM20_CH4N_PE0_AF3 +#define TIM20_CH4_PE1_AF6 +#define TIM20_ETR_PE0_AF6 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH1_PD3_AF2 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH2_PD4_AF2 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH3_PD7_AF2 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_CH4_PD6_AF2 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM2_ETR_PD3_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH1_PE2_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH2_PE3_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH3_PE4_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_CH4_PE5_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH1_PD12_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH2_PD13_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH3_PD14_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_CH4_PD15_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM4_ETR_PE0_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH1_PB2_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH2_PC12_AF1 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH3_PE8_AF1 +#define TIM5_CH4_PA3_AF2 +#define TIM5_CH4_PE9_AF1 +#define TIM5_CH4_PF9_AF6 +#define TIM5_ETR_PB12_AF2 +#define TIM5_ETR_PD11_AF1 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN2_PD1_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4N_PD0_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_CH4_PD1_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) +#define TIM_MODULE_20 (10) + +#define TIM_MODULE_COUNT (10) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PE0_CN +#define __PE1_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN +#define __PE6_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PF10_CN +#define __PF2_CN +#define __PF9_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (7) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G484VE/TFBGA100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G484VE/TFBGA100/mcu_definitions.h new file mode 100644 index 000000000..491e0eef0 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G484VE/TFBGA100/mcu_definitions.h @@ -0,0 +1,615 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G484VE_TFBGA100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 +#define ADC3_PD10_CH7 +#define ADC3_PD11_CH8 +#define ADC3_PD12_CH9 +#define ADC3_PD13_CH10 +#define ADC3_PD14_CH11 +#define ADC3_PE10_CH14 +#define ADC3_PE11_CH15 +#define ADC3_PE12_CH16 +#define ADC3_PE13_CH3 +#define ADC3_PE7_CH4 +#define ADC3_PE8_CH6 +#define ADC3_PE9_CH2 +#define ADC4_PB12_CH3 +#define ADC4_PB14_CH4 +#define ADC4_PB15_CH5 +#define ADC4_PD10_CH7 +#define ADC4_PD11_CH8 +#define ADC4_PD12_CH9 +#define ADC4_PD13_CH10 +#define ADC4_PD14_CH11 +#define ADC4_PD8_CH12 +#define ADC4_PD9_CH13 +#define ADC4_PE10_CH14 +#define ADC4_PE11_CH15 +#define ADC4_PE12_CH16 +#define ADC4_PE14_CH1 +#define ADC4_PE15_CH2 +#define ADC4_PE8_CH6 +#define ADC5_PA8_CH1 +#define ADC5_PA9_CH2 +#define ADC5_PD10_CH7 +#define ADC5_PD11_CH8 +#define ADC5_PD12_CH9 +#define ADC5_PD13_CH10 +#define ADC5_PD14_CH11 +#define ADC5_PD8_CH12 +#define ADC5_PD9_CH13 +#define ADC5_PE10_CH14 +#define ADC5_PE11_CH15 +#define ADC5_PE12_CH16 +#define ADC5_PE8_CH6 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) +#define ADC_MODULE_4 (4) +#define ADC_MODULE_5 (5) + +#define ADC_MODULE_COUNT (5) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_RX_PD0_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN1_TX_PD1_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 +#define FDCAN3_RX_PA8_AF11 +#define FDCAN3_RX_PB3_AF11 +#define FDCAN3_TX_PA15_AF11 +#define FDCAN3_TX_PB4_AF11 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) +#define CAN_MODULE_3 (3) + +#define CAN_MODULE_COUNT (3) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +#define HAL_LL_FDCAN3_GPIO_AF11 (11) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 +#define I2C4_SCL_PA13_AF3 +#define I2C4_SCL_PC6_AF8 +#define I2C4_SDA_PB7_AF3 +#define I2C4_SDA_PC7_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define UART5_RX_PD2_AF5 +#define UART5_TX_PC12_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_RX_PE1_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART1_TX_PE0_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_RX_PD6_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART2_TX_PD5_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PD9_AF7 +#define USART3_RX_PE15_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PD8_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF10_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI2_SCK_PF9_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 +#define SPI4_MISO_PE13_AF5 +#define SPI4_MISO_PE5_AF5 +#define SPI4_MOSI_PE14_AF5 +#define SPI4_MOSI_PE6_AF5 +#define SPI4_SCK_PE12_AF5 +#define SPI4_SCK_PE2_AF5 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) +#define SPI_MODULE_4 (4) + +#define SPI_MODULE_COUNT (4) +// EOF SPI + +// TIM +#define HRTIM1_CHA1_PA8_AF13 +#define HRTIM1_CHA2_PA9_AF13 +#define HRTIM1_CHB1_PA10_AF13 +#define HRTIM1_CHB2_PA11_AF13 +#define HRTIM1_CHC1_PB12_AF13 +#define HRTIM1_CHC2_PB13_AF13 +#define HRTIM1_CHD1_PB14_AF13 +#define HRTIM1_CHD2_PB15_AF13 +#define HRTIM1_CHE1_PC8_AF3 +#define HRTIM1_CHE2_PC9_AF3 +#define HRTIM1_CHF1_PC6_AF13 +#define HRTIM1_CHF2_PC7_AF13 +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH1_PF9_AF3 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM15_CH2_PF10_AF3 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM16_CH1_PE0_AF4 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM17_CH1_PE1_AF4 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN2_PE14_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_BKIN_PE15_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1N_PE8_AF2 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH1_PE9_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2N_PE10_AF2 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH2_PE11_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PE12_AF2 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH3_PE13_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4N_PE15_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_CH4_PE14_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM1_ETR_PE7_AF2 +#define TIM20_BKIN2_PF10_AF2 +#define TIM20_BKIN_PF9_AF2 +#define TIM20_CH1N_PE4_AF6 +#define TIM20_CH1_PB2_AF3 +#define TIM20_CH1_PE2_AF6 +#define TIM20_CH2N_PE5_AF6 +#define TIM20_CH2_PC2_AF6 +#define TIM20_CH2_PE3_AF6 +#define TIM20_CH3N_PE6_AF6 +#define TIM20_CH3_PC8_AF6 +#define TIM20_CH3_PF2_AF2 +#define TIM20_CH4N_PE0_AF3 +#define TIM20_CH4_PE1_AF6 +#define TIM20_ETR_PE0_AF6 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH1_PD3_AF2 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH2_PD4_AF2 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH3_PD7_AF2 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_CH4_PD6_AF2 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM2_ETR_PD3_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH1_PE2_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH2_PE3_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH3_PE4_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_CH4_PE5_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH1_PD12_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH2_PD13_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH3_PD14_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_CH4_PD15_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM4_ETR_PE0_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH1_PB2_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH2_PC12_AF1 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH3_PE8_AF1 +#define TIM5_CH4_PA3_AF2 +#define TIM5_CH4_PE9_AF1 +#define TIM5_CH4_PF9_AF6 +#define TIM5_ETR_PB12_AF2 +#define TIM5_ETR_PD11_AF1 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN2_PD1_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4N_PD0_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_CH4_PD1_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) +#define TIM_MODULE_20 (10) + +#define TIM_MODULE_COUNT (10) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PE0_CN +#define __PE1_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN +#define __PE6_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PF10_CN +#define __PF2_CN +#define __PF9_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (7) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G491CC/LQFP48/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G491CC/LQFP48/mcu_definitions.h new file mode 100644 index 000000000..92f8f4fbf --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G491CC/LQFP48/mcu_definitions.h @@ -0,0 +1,368 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G491CC_LQFP48. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) + +#define ADC_MODULE_COUNT (3) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) + +#define CAN_MODULE_COUNT (2) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SDA_PB5_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) + +#define UART_MODULE_COUNT (3) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_SCK_PB3_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_ETR_PA12_AF11 +#define TIM20_CH1_PB2_AF3 +#define TIM20_ETR_PA15_AF3 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_ETR_PB3_AF10 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_8 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) +#define TIM_MODULE_20 (9) + +#define TIM_MODULE_COUNT (9) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G491CC/UFQFPN48/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G491CC/UFQFPN48/mcu_definitions.h new file mode 100644 index 000000000..a15c02d94 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G491CC/UFQFPN48/mcu_definitions.h @@ -0,0 +1,385 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G491CC_UFQFPN48. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC4_CH5 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) + +#define ADC_MODULE_COUNT (3) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) + +#define CAN_MODULE_COUNT (2) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) + +#define UART_MODULE_COUNT (3) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM20_CH1_PB2_AF3 +#define TIM20_ETR_PA15_AF3 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_ETR_PB3_AF10 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_8 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) +#define TIM_MODULE_20 (9) + +#define TIM_MODULE_COUNT (9) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC10_CN +#define __PC11_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC4_CN +#define __PC6_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G491CE/LQFP48/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G491CE/LQFP48/mcu_definitions.h new file mode 100644 index 000000000..ff99b8950 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G491CE/LQFP48/mcu_definitions.h @@ -0,0 +1,368 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G491CE_LQFP48. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) + +#define ADC_MODULE_COUNT (3) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) + +#define CAN_MODULE_COUNT (2) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SDA_PB5_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) + +#define UART_MODULE_COUNT (3) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_SCK_PB3_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_ETR_PA12_AF11 +#define TIM20_CH1_PB2_AF3 +#define TIM20_ETR_PA15_AF3 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_ETR_PB3_AF10 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_8 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) +#define TIM_MODULE_20 (9) + +#define TIM_MODULE_COUNT (9) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G491CE/UFQFPN48/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G491CE/UFQFPN48/mcu_definitions.h new file mode 100644 index 000000000..7d9d00244 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G491CE/UFQFPN48/mcu_definitions.h @@ -0,0 +1,385 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G491CE_UFQFPN48. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC4_CH5 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) + +#define ADC_MODULE_COUNT (3) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) + +#define CAN_MODULE_COUNT (2) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) + +#define UART_MODULE_COUNT (3) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM20_CH1_PB2_AF3 +#define TIM20_ETR_PA15_AF3 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_ETR_PB3_AF10 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_8 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) +#define TIM_MODULE_20 (9) + +#define TIM_MODULE_COUNT (9) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC10_CN +#define __PC11_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC4_CN +#define __PC6_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G491KC/UFQFPN32/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G491KC/UFQFPN32/mcu_definitions.h new file mode 100644 index 000000000..d4b9d03cf --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G491KC/UFQFPN32/mcu_definitions.h @@ -0,0 +1,309 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G491KC_UFQFPN32. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) + +#define ADC_MODULE_COUNT (3) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB6_AF9 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) + +#define CAN_MODULE_COUNT (2) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SDA_PB5_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_TX_PA2_AF12 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (2) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_SCK_PB3_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH2_PA3_AF9 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_ETR_PA12_AF11 +#define TIM20_ETR_PA15_AF3 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_ETR_PB3_AF10 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_8 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) +#define TIM_MODULE_20 (9) + +#define TIM_MODULE_COUNT (9) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (4) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G491KE/UFQFPN32/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G491KE/UFQFPN32/mcu_definitions.h new file mode 100644 index 000000000..d8c2181ed --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G491KE/UFQFPN32/mcu_definitions.h @@ -0,0 +1,309 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G491KE_UFQFPN32. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) + +#define ADC_MODULE_COUNT (3) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB6_AF9 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) + +#define CAN_MODULE_COUNT (2) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SDA_PB5_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_TX_PA2_AF12 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (2) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_SCK_PB3_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH2_PA3_AF9 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_ETR_PA12_AF11 +#define TIM20_ETR_PA15_AF3 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_ETR_PB3_AF10 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_8 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) +#define TIM_MODULE_20 (9) + +#define TIM_MODULE_COUNT (9) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (4) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G491MC/LQFP80/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G491MC/LQFP80/mcu_definitions.h new file mode 100644 index 000000000..7d2a7b4c1 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G491MC/LQFP80/mcu_definitions.h @@ -0,0 +1,483 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G491MC_LQFP80. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 +#define ADC3_PD10_CH7 +#define ADC3_PE10_CH14 +#define ADC3_PE11_CH15 +#define ADC3_PE12_CH16 +#define ADC3_PE13_CH3 +#define ADC3_PE7_CH4 +#define ADC3_PE8_CH6 +#define ADC3_PE9_CH2 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) + +#define ADC_MODULE_COUNT (3) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_RX_PD0_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN1_TX_PD1_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) + +#define CAN_MODULE_COUNT (2) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define UART5_RX_PD2_AF5 +#define UART5_TX_PC12_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PD9_AF7 +#define USART3_RX_PE15_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PD8_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN2_PE14_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_BKIN_PE15_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1N_PE8_AF2 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH1_PE9_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2N_PE10_AF2 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH2_PE11_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PE12_AF2 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH3_PE13_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4N_PE15_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_CH4_PE14_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM1_ETR_PE7_AF2 +#define TIM20_CH1_PB2_AF3 +#define TIM20_CH2_PC2_AF6 +#define TIM20_CH3_PC8_AF6 +#define TIM20_ETR_PA15_AF3 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN2_PD1_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4N_PD0_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_CH4_PD1_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_8 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) +#define TIM_MODULE_20 (9) + +#define TIM_MODULE_COUNT (9) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD2_CN +#define __PD8_CN +#define __PD9_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (7) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G491ME/LQFP80/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G491ME/LQFP80/mcu_definitions.h new file mode 100644 index 000000000..16a76756a --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G491ME/LQFP80/mcu_definitions.h @@ -0,0 +1,483 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G491ME_LQFP80. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 +#define ADC3_PD10_CH7 +#define ADC3_PE10_CH14 +#define ADC3_PE11_CH15 +#define ADC3_PE12_CH16 +#define ADC3_PE13_CH3 +#define ADC3_PE7_CH4 +#define ADC3_PE8_CH6 +#define ADC3_PE9_CH2 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) + +#define ADC_MODULE_COUNT (3) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_RX_PD0_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN1_TX_PD1_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) + +#define CAN_MODULE_COUNT (2) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define UART5_RX_PD2_AF5 +#define UART5_TX_PC12_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PD9_AF7 +#define USART3_RX_PE15_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PD8_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN2_PE14_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_BKIN_PE15_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1N_PE8_AF2 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH1_PE9_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2N_PE10_AF2 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH2_PE11_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PE12_AF2 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH3_PE13_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4N_PE15_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_CH4_PE14_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM1_ETR_PE7_AF2 +#define TIM20_CH1_PB2_AF3 +#define TIM20_CH2_PC2_AF6 +#define TIM20_CH3_PC8_AF6 +#define TIM20_ETR_PA15_AF3 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN2_PD1_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4N_PD0_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_CH4_PD1_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_8 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) +#define TIM_MODULE_20 (9) + +#define TIM_MODULE_COUNT (9) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD2_CN +#define __PD8_CN +#define __PD9_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (7) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G491RC/LQFP64/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G491RC/LQFP64/mcu_definitions.h new file mode 100644 index 000000000..ed6ad40de --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G491RC/LQFP64/mcu_definitions.h @@ -0,0 +1,441 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G491RC_LQFP64. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) + +#define ADC_MODULE_COUNT (3) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) + +#define CAN_MODULE_COUNT (2) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define UART5_RX_PD2_AF5 +#define UART5_TX_PC12_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM20_CH1_PB2_AF3 +#define TIM20_CH2_PC2_AF6 +#define TIM20_CH3_PC8_AF6 +#define TIM20_ETR_PA15_AF3 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_8 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) +#define TIM_MODULE_20 (9) + +#define TIM_MODULE_COUNT (9) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD2_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (6) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G491RC/UFBGA64/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G491RC/UFBGA64/mcu_definitions.h new file mode 100644 index 000000000..234c31649 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G491RC/UFBGA64/mcu_definitions.h @@ -0,0 +1,441 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G491RC_UFBGA64. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) + +#define ADC_MODULE_COUNT (3) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) + +#define CAN_MODULE_COUNT (2) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define UART5_RX_PD2_AF5 +#define UART5_TX_PC12_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM20_CH1_PB2_AF3 +#define TIM20_CH2_PC2_AF6 +#define TIM20_CH3_PC8_AF6 +#define TIM20_ETR_PA15_AF3 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_8 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) +#define TIM_MODULE_20 (9) + +#define TIM_MODULE_COUNT (9) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD2_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (6) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G491RE/LQFP64/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G491RE/LQFP64/mcu_definitions.h new file mode 100644 index 000000000..b355294c3 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G491RE/LQFP64/mcu_definitions.h @@ -0,0 +1,441 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G491RE_LQFP64. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) + +#define ADC_MODULE_COUNT (3) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) + +#define CAN_MODULE_COUNT (2) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define UART5_RX_PD2_AF5 +#define UART5_TX_PC12_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM20_CH1_PB2_AF3 +#define TIM20_CH2_PC2_AF6 +#define TIM20_CH3_PC8_AF6 +#define TIM20_ETR_PA15_AF3 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_8 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) +#define TIM_MODULE_20 (9) + +#define TIM_MODULE_COUNT (9) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD2_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (6) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G491RE/UFBGA64/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G491RE/UFBGA64/mcu_definitions.h new file mode 100644 index 000000000..a1266d429 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G491RE/UFBGA64/mcu_definitions.h @@ -0,0 +1,441 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G491RE_UFBGA64. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) + +#define ADC_MODULE_COUNT (3) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) + +#define CAN_MODULE_COUNT (2) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define UART5_RX_PD2_AF5 +#define UART5_TX_PC12_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM20_CH1_PB2_AF3 +#define TIM20_CH2_PC2_AF6 +#define TIM20_CH3_PC8_AF6 +#define TIM20_ETR_PA15_AF3 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_8 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) +#define TIM_MODULE_20 (9) + +#define TIM_MODULE_COUNT (9) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD2_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (6) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G491RE/WLCSP64/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G491RE/WLCSP64/mcu_definitions.h new file mode 100644 index 000000000..d1cbb642e --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G491RE/WLCSP64/mcu_definitions.h @@ -0,0 +1,441 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G491RE_WLCSP64. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) + +#define ADC_MODULE_COUNT (3) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) + +#define CAN_MODULE_COUNT (2) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define UART5_RX_PD2_AF5 +#define UART5_TX_PC12_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM20_CH1_PB2_AF3 +#define TIM20_CH2_PC2_AF6 +#define TIM20_CH3_PC8_AF6 +#define TIM20_ETR_PA15_AF3 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_8 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) +#define TIM_MODULE_20 (9) + +#define TIM_MODULE_COUNT (9) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD2_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (6) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G491VC/LQFP100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G491VC/LQFP100/mcu_definitions.h new file mode 100644 index 000000000..b10712b33 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G491VC/LQFP100/mcu_definitions.h @@ -0,0 +1,542 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G491VC_LQFP100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 +#define ADC3_PD10_CH7 +#define ADC3_PD11_CH8 +#define ADC3_PD12_CH9 +#define ADC3_PD13_CH10 +#define ADC3_PD14_CH11 +#define ADC3_PE10_CH14 +#define ADC3_PE11_CH15 +#define ADC3_PE12_CH16 +#define ADC3_PE13_CH3 +#define ADC3_PE7_CH4 +#define ADC3_PE8_CH6 +#define ADC3_PE9_CH2 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) + +#define ADC_MODULE_COUNT (3) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_RX_PD0_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN1_TX_PD1_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) + +#define CAN_MODULE_COUNT (2) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define UART5_RX_PD2_AF5 +#define UART5_TX_PC12_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_RX_PE1_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART1_TX_PE0_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_RX_PD6_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART2_TX_PD5_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PD9_AF7 +#define USART3_RX_PE15_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PD8_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF10_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI2_SCK_PF9_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH1_PF9_AF3 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM15_CH2_PF10_AF3 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM16_CH1_PE0_AF4 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM17_CH1_PE1_AF4 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN2_PE14_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_BKIN_PE15_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1N_PE8_AF2 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH1_PE9_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2N_PE10_AF2 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH2_PE11_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PE12_AF2 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH3_PE13_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4N_PE15_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_CH4_PE14_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM1_ETR_PE7_AF2 +#define TIM20_BKIN2_PF10_AF2 +#define TIM20_BKIN_PF9_AF2 +#define TIM20_CH1N_PE4_AF6 +#define TIM20_CH1_PB2_AF3 +#define TIM20_CH1_PE2_AF6 +#define TIM20_CH2N_PE5_AF6 +#define TIM20_CH2_PC2_AF6 +#define TIM20_CH2_PE3_AF6 +#define TIM20_CH3N_PE6_AF6 +#define TIM20_CH3_PC8_AF6 +#define TIM20_CH3_PF2_AF2 +#define TIM20_CH4N_PE0_AF3 +#define TIM20_CH4_PE1_AF6 +#define TIM20_ETR_PA15_AF3 +#define TIM20_ETR_PE0_AF6 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH1_PD3_AF2 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH2_PD4_AF2 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH3_PD7_AF2 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_CH4_PD6_AF2 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM2_ETR_PD3_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH1_PE2_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH2_PE3_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH3_PE4_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_CH4_PE5_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH1_PD12_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH2_PD13_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH3_PD14_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_CH4_PD15_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM4_ETR_PE0_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN2_PD1_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4N_PD0_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_CH4_PD1_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_8 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) +#define TIM_MODULE_20 (9) + +#define TIM_MODULE_COUNT (9) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PE0_CN +#define __PE1_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN +#define __PE6_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PF10_CN +#define __PF2_CN +#define __PF9_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (7) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G491VE/LQFP100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G491VE/LQFP100/mcu_definitions.h new file mode 100644 index 000000000..7175063e3 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G491VE/LQFP100/mcu_definitions.h @@ -0,0 +1,542 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G491VE_LQFP100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 +#define ADC3_PD10_CH7 +#define ADC3_PD11_CH8 +#define ADC3_PD12_CH9 +#define ADC3_PD13_CH10 +#define ADC3_PD14_CH11 +#define ADC3_PE10_CH14 +#define ADC3_PE11_CH15 +#define ADC3_PE12_CH16 +#define ADC3_PE13_CH3 +#define ADC3_PE7_CH4 +#define ADC3_PE8_CH6 +#define ADC3_PE9_CH2 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) + +#define ADC_MODULE_COUNT (3) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_RX_PD0_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN1_TX_PD1_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) + +#define CAN_MODULE_COUNT (2) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define UART5_RX_PD2_AF5 +#define UART5_TX_PC12_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_RX_PE1_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART1_TX_PE0_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_RX_PD6_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART2_TX_PD5_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PD9_AF7 +#define USART3_RX_PE15_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PD8_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF10_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI2_SCK_PF9_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH1_PF9_AF3 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM15_CH2_PF10_AF3 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM16_CH1_PE0_AF4 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM17_CH1_PE1_AF4 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN2_PE14_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_BKIN_PE15_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1N_PE8_AF2 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH1_PE9_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2N_PE10_AF2 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH2_PE11_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PE12_AF2 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH3_PE13_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4N_PE15_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_CH4_PE14_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM1_ETR_PE7_AF2 +#define TIM20_BKIN2_PF10_AF2 +#define TIM20_BKIN_PF9_AF2 +#define TIM20_CH1N_PE4_AF6 +#define TIM20_CH1_PB2_AF3 +#define TIM20_CH1_PE2_AF6 +#define TIM20_CH2N_PE5_AF6 +#define TIM20_CH2_PC2_AF6 +#define TIM20_CH2_PE3_AF6 +#define TIM20_CH3N_PE6_AF6 +#define TIM20_CH3_PC8_AF6 +#define TIM20_CH3_PF2_AF2 +#define TIM20_CH4N_PE0_AF3 +#define TIM20_CH4_PE1_AF6 +#define TIM20_ETR_PA15_AF3 +#define TIM20_ETR_PE0_AF6 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH1_PD3_AF2 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH2_PD4_AF2 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH3_PD7_AF2 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_CH4_PD6_AF2 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM2_ETR_PD3_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH1_PE2_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH2_PE3_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH3_PE4_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_CH4_PE5_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH1_PD12_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH2_PD13_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH3_PD14_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_CH4_PD15_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM4_ETR_PE0_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN2_PD1_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4N_PD0_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_CH4_PD1_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_8 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) +#define TIM_MODULE_20 (9) + +#define TIM_MODULE_COUNT (9) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PE0_CN +#define __PE1_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN +#define __PE6_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PF10_CN +#define __PF2_CN +#define __PF9_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (7) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G4A1CE/LQFP48/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G4A1CE/LQFP48/mcu_definitions.h new file mode 100644 index 000000000..bb0edd361 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G4A1CE/LQFP48/mcu_definitions.h @@ -0,0 +1,368 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G4A1CE_LQFP48. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) + +#define ADC_MODULE_COUNT (3) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) + +#define CAN_MODULE_COUNT (2) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SDA_PB5_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) + +#define UART_MODULE_COUNT (3) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_SCK_PB3_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_ETR_PA12_AF11 +#define TIM20_CH1_PB2_AF3 +#define TIM20_ETR_PA15_AF3 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_ETR_PB3_AF10 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_8 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) +#define TIM_MODULE_20 (9) + +#define TIM_MODULE_COUNT (9) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G4A1CE/UFQFPN48/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G4A1CE/UFQFPN48/mcu_definitions.h new file mode 100644 index 000000000..592c1b690 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G4A1CE/UFQFPN48/mcu_definitions.h @@ -0,0 +1,385 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G4A1CE_UFQFPN48. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC4_CH5 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) + +#define ADC_MODULE_COUNT (3) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) + +#define CAN_MODULE_COUNT (2) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) + +#define UART_MODULE_COUNT (3) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM20_CH1_PB2_AF3 +#define TIM20_ETR_PA15_AF3 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_ETR_PB3_AF10 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_8 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) +#define TIM_MODULE_20 (9) + +#define TIM_MODULE_COUNT (9) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC10_CN +#define __PC11_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC4_CN +#define __PC6_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G4A1KE/UFQFPN32/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G4A1KE/UFQFPN32/mcu_definitions.h new file mode 100644 index 000000000..4924b61af --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G4A1KE/UFQFPN32/mcu_definitions.h @@ -0,0 +1,309 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G4A1KE_UFQFPN32. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) + +#define ADC_MODULE_COUNT (3) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB6_AF9 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) + +#define CAN_MODULE_COUNT (2) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SDA_PB5_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_TX_PA2_AF12 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (2) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_SCK_PB3_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH2_PA3_AF9 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_ETR_PA12_AF11 +#define TIM20_ETR_PA15_AF3 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_ETR_PB3_AF10 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_8 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) +#define TIM_MODULE_20 (9) + +#define TIM_MODULE_COUNT (9) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (4) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G4A1ME/LQFP80/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G4A1ME/LQFP80/mcu_definitions.h new file mode 100644 index 000000000..28d50f12e --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G4A1ME/LQFP80/mcu_definitions.h @@ -0,0 +1,483 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G4A1ME_LQFP80. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 +#define ADC3_PD10_CH7 +#define ADC3_PE10_CH14 +#define ADC3_PE11_CH15 +#define ADC3_PE12_CH16 +#define ADC3_PE13_CH3 +#define ADC3_PE7_CH4 +#define ADC3_PE8_CH6 +#define ADC3_PE9_CH2 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) + +#define ADC_MODULE_COUNT (3) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_RX_PD0_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN1_TX_PD1_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) + +#define CAN_MODULE_COUNT (2) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define UART5_RX_PD2_AF5 +#define UART5_TX_PC12_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PD9_AF7 +#define USART3_RX_PE15_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PD8_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN2_PE14_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_BKIN_PE15_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1N_PE8_AF2 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH1_PE9_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2N_PE10_AF2 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH2_PE11_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PE12_AF2 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH3_PE13_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4N_PE15_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_CH4_PE14_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM1_ETR_PE7_AF2 +#define TIM20_CH1_PB2_AF3 +#define TIM20_CH2_PC2_AF6 +#define TIM20_CH3_PC8_AF6 +#define TIM20_ETR_PA15_AF3 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN2_PD1_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4N_PD0_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_CH4_PD1_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_8 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) +#define TIM_MODULE_20 (9) + +#define TIM_MODULE_COUNT (9) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD2_CN +#define __PD8_CN +#define __PD9_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (7) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G4A1RE/LQFP64/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G4A1RE/LQFP64/mcu_definitions.h new file mode 100644 index 000000000..6ffe686c4 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G4A1RE/LQFP64/mcu_definitions.h @@ -0,0 +1,441 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G4A1RE_LQFP64. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) + +#define ADC_MODULE_COUNT (3) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) + +#define CAN_MODULE_COUNT (2) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define UART5_RX_PD2_AF5 +#define UART5_TX_PC12_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM20_CH1_PB2_AF3 +#define TIM20_CH2_PC2_AF6 +#define TIM20_CH3_PC8_AF6 +#define TIM20_ETR_PA15_AF3 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_8 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) +#define TIM_MODULE_20 (9) + +#define TIM_MODULE_COUNT (9) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD2_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (6) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G4A1RE/UFBGA64/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G4A1RE/UFBGA64/mcu_definitions.h new file mode 100644 index 000000000..74abf8e7f --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G4A1RE/UFBGA64/mcu_definitions.h @@ -0,0 +1,441 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G4A1RE_UFBGA64. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) + +#define ADC_MODULE_COUNT (3) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) + +#define CAN_MODULE_COUNT (2) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define UART5_RX_PD2_AF5 +#define UART5_TX_PC12_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM20_CH1_PB2_AF3 +#define TIM20_CH2_PC2_AF6 +#define TIM20_CH3_PC8_AF6 +#define TIM20_ETR_PA15_AF3 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_8 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) +#define TIM_MODULE_20 (9) + +#define TIM_MODULE_COUNT (9) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD2_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (6) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G4A1RE/WLCSP64/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G4A1RE/WLCSP64/mcu_definitions.h new file mode 100644 index 000000000..5a68529e9 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G4A1RE/WLCSP64/mcu_definitions.h @@ -0,0 +1,441 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G4A1RE_WLCSP64. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) + +#define ADC_MODULE_COUNT (3) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) + +#define CAN_MODULE_COUNT (2) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define UART5_RX_PD2_AF5 +#define UART5_TX_PC12_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM20_CH1_PB2_AF3 +#define TIM20_CH2_PC2_AF6 +#define TIM20_CH3_PC8_AF6 +#define TIM20_ETR_PA15_AF3 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_8 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) +#define TIM_MODULE_20 (9) + +#define TIM_MODULE_COUNT (9) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD2_CN +#define __PF0_CN +#define __PF1_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (6) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G4A1VE/LQFP100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G4A1VE/LQFP100/mcu_definitions.h new file mode 100644 index 000000000..d0e9800ce --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32G4A1VE/LQFP100/mcu_definitions.h @@ -0,0 +1,542 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32G4A1VE_LQFP100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH1 +#define ADC1_PA1_CH2 +#define ADC1_PA2_CH3 +#define ADC1_PA3_CH4 +#define ADC1_PB0_CH15 +#define ADC1_PB11_CH14 +#define ADC1_PB12_CH11 +#define ADC1_PB14_CH5 +#define ADC1_PB1_CH12 +#define ADC1_PC0_CH6 +#define ADC1_PC1_CH7 +#define ADC1_PC2_CH8 +#define ADC1_PC3_CH9 +#define ADC1_PF0_CH10 +#define ADC2_PA0_CH1 +#define ADC2_PA1_CH2 +#define ADC2_PA4_CH17 +#define ADC2_PA5_CH13 +#define ADC2_PA6_CH3 +#define ADC2_PA7_CH4 +#define ADC2_PB11_CH14 +#define ADC2_PB15_CH15 +#define ADC2_PB2_CH12 +#define ADC2_PC0_CH6 +#define ADC2_PC1_CH7 +#define ADC2_PC2_CH8 +#define ADC2_PC3_CH9 +#define ADC2_PC4_CH5 +#define ADC2_PC5_CH11 +#define ADC2_PF1_CH10 +#define ADC3_PB0_CH12 +#define ADC3_PB13_CH5 +#define ADC3_PB1_CH1 +#define ADC3_PD10_CH7 +#define ADC3_PD11_CH8 +#define ADC3_PD12_CH9 +#define ADC3_PD13_CH10 +#define ADC3_PD14_CH11 +#define ADC3_PE10_CH14 +#define ADC3_PE11_CH15 +#define ADC3_PE12_CH16 +#define ADC3_PE13_CH3 +#define ADC3_PE7_CH4 +#define ADC3_PE8_CH6 +#define ADC3_PE9_CH2 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) +#define ADC_MODULE_3 (3) + +#define ADC_MODULE_COUNT (3) +// EOF ADC + +// CAN +#define FDCAN1_RX_PA11_AF9 +#define FDCAN1_RX_PB8_AF9 +#define FDCAN1_RX_PD0_AF9 +#define FDCAN1_TX_PA12_AF9 +#define FDCAN1_TX_PB9_AF9 +#define FDCAN1_TX_PD1_AF9 +#define FDCAN2_RX_PB12_AF9 +#define FDCAN2_RX_PB5_AF9 +#define FDCAN2_TX_PB13_AF9 +#define FDCAN2_TX_PB6_AF9 + +#define CAN_MODULE_1 (1) +#define CAN_MODULE_2 (2) + +#define CAN_MODULE_COUNT (2) + +#define HAL_LL_FDCAN1_GPIO_AF9 (9) +#define HAL_LL_FDCAN2_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (116) +#define DMA_NUM_OF_CHANNELS_FAMILY (116) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (8) +#define DMA_NUM_OF_STREAMS_FAMILY (8) +// EOF DMA + +// I2C +#define I2C1_SCL_PA13_AF4 +#define I2C1_SCL_PA15_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PA14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PA9_AF4 +#define I2C2_SCL_PC4_AF4 +#define I2C2_SDA_PA8_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA8_AF2 +#define I2C3_SCL_PC8_AF8 +#define I2C3_SDA_PB5_AF8 +#define I2C3_SDA_PC11_AF8 +#define I2C3_SDA_PC9_AF8 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF12 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF12 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PC11_AF5 +#define UART4_TX_PC10_AF5 +#define UART5_RX_PD2_AF5 +#define UART5_TX_PC12_AF5 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PC5_AF7 +#define USART1_RX_PE1_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PC4_AF7 +#define USART1_TX_PE0_AF7 +#define USART2_RX_PA15_AF7 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PB4_AF7 +#define USART2_RX_PD6_AF7 +#define USART2_TX_PA14_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PB3_AF7 +#define USART2_TX_PD5_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PB8_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PD9_AF7 +#define USART3_RX_PE15_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PB9_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PD8_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PA10_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PA11_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PF10_AF5 +#define SPI2_SCK_PF1_AF5 +#define SPI2_SCK_PF9_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF11 +#define LPTIM1_ETR_PC3_AF1 +#define TIM15_BKIN_PA9_AF9 +#define TIM15_BKIN_PC5_AF2 +#define TIM15_CH1N_PA1_AF9 +#define TIM15_CH1N_PB15_AF2 +#define TIM15_CH1_PA2_AF9 +#define TIM15_CH1_PB14_AF1 +#define TIM15_CH1_PF9_AF3 +#define TIM15_CH2_PA3_AF9 +#define TIM15_CH2_PB15_AF1 +#define TIM15_CH2_PF10_AF3 +#define TIM16_BKIN_PB5_AF1 +#define TIM16_CH1N_PA13_AF1 +#define TIM16_CH1N_PB6_AF1 +#define TIM16_CH1_PA12_AF1 +#define TIM16_CH1_PA6_AF1 +#define TIM16_CH1_PB4_AF1 +#define TIM16_CH1_PB8_AF1 +#define TIM16_CH1_PE0_AF4 +#define TIM17_BKIN_PA10_AF1 +#define TIM17_BKIN_PB4_AF10 +#define TIM17_CH1N_PB7_AF1 +#define TIM17_CH1_PA7_AF1 +#define TIM17_CH1_PB5_AF10 +#define TIM17_CH1_PB9_AF1 +#define TIM17_CH1_PE1_AF4 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PC3_AF6 +#define TIM1_BKIN2_PE14_AF6 +#define TIM1_BKIN_PA14_AF6 +#define TIM1_BKIN_PA15_AF9 +#define TIM1_BKIN_PA6_AF6 +#define TIM1_BKIN_PB10_AF12 +#define TIM1_BKIN_PB12_AF6 +#define TIM1_BKIN_PB8_AF12 +#define TIM1_BKIN_PC13_AF2 +#define TIM1_BKIN_PE15_AF2 +#define TIM1_CH1N_PA11_AF6 +#define TIM1_CH1N_PA7_AF6 +#define TIM1_CH1N_PB13_AF6 +#define TIM1_CH1N_PC13_AF4 +#define TIM1_CH1N_PE8_AF2 +#define TIM1_CH1_PA8_AF6 +#define TIM1_CH1_PC0_AF2 +#define TIM1_CH1_PE9_AF2 +#define TIM1_CH2N_PA12_AF6 +#define TIM1_CH2N_PB0_AF6 +#define TIM1_CH2N_PB14_AF6 +#define TIM1_CH2N_PE10_AF2 +#define TIM1_CH2_PA9_AF6 +#define TIM1_CH2_PC1_AF2 +#define TIM1_CH2_PE11_AF2 +#define TIM1_CH3N_PB15_AF4 +#define TIM1_CH3N_PB1_AF6 +#define TIM1_CH3N_PB9_AF12 +#define TIM1_CH3N_PE12_AF2 +#define TIM1_CH3N_PF0_AF6 +#define TIM1_CH3_PA10_AF6 +#define TIM1_CH3_PC2_AF2 +#define TIM1_CH3_PE13_AF2 +#define TIM1_CH4N_PC5_AF6 +#define TIM1_CH4N_PE15_AF6 +#define TIM1_CH4_PA11_AF11 +#define TIM1_CH4_PC3_AF2 +#define TIM1_CH4_PE14_AF2 +#define TIM1_ETR_PA12_AF11 +#define TIM1_ETR_PC4_AF2 +#define TIM1_ETR_PE7_AF2 +#define TIM20_BKIN2_PF10_AF2 +#define TIM20_BKIN_PF9_AF2 +#define TIM20_CH1N_PE4_AF6 +#define TIM20_CH1_PB2_AF3 +#define TIM20_CH1_PE2_AF6 +#define TIM20_CH2N_PE5_AF6 +#define TIM20_CH2_PC2_AF6 +#define TIM20_CH2_PE3_AF6 +#define TIM20_CH3N_PE6_AF6 +#define TIM20_CH3_PC8_AF6 +#define TIM20_CH3_PF2_AF2 +#define TIM20_CH4N_PE0_AF3 +#define TIM20_CH4_PE1_AF6 +#define TIM20_ETR_PA15_AF3 +#define TIM20_ETR_PE0_AF6 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH1_PD3_AF2 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH2_PD4_AF2 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PA9_AF10 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH3_PD7_AF2 +#define TIM2_CH4_PA10_AF10 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_CH4_PD6_AF2 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF14 +#define TIM2_ETR_PA5_AF2 +#define TIM2_ETR_PD3_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH1_PE2_AF2 +#define TIM3_CH2_PA4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH2_PE3_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH3_PE4_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PB7_AF10 +#define TIM3_CH4_PC9_AF2 +#define TIM3_CH4_PE5_AF2 +#define TIM3_ETR_PB3_AF10 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PA11_AF10 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH1_PD12_AF2 +#define TIM4_CH2_PA12_AF10 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH2_PD13_AF2 +#define TIM4_CH3_PA13_AF10 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH3_PD14_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_CH4_PD15_AF2 +#define TIM4_ETR_PA8_AF10 +#define TIM4_ETR_PB3_AF2 +#define TIM4_ETR_PE0_AF2 +#define TIM8_BKIN2_PB6_AF10 +#define TIM8_BKIN2_PC9_AF6 +#define TIM8_BKIN2_PD1_AF6 +#define TIM8_BKIN_PA0_AF9 +#define TIM8_BKIN_PA10_AF11 +#define TIM8_BKIN_PA6_AF4 +#define TIM8_BKIN_PB7_AF5 +#define TIM8_BKIN_PD2_AF4 +#define TIM8_CH1N_PA7_AF4 +#define TIM8_CH1N_PB3_AF4 +#define TIM8_CH1N_PC10_AF4 +#define TIM8_CH1_PA15_AF2 +#define TIM8_CH1_PB6_AF5 +#define TIM8_CH1_PC6_AF4 +#define TIM8_CH2N_PB0_AF4 +#define TIM8_CH2N_PB4_AF4 +#define TIM8_CH2N_PC11_AF4 +#define TIM8_CH2_PA14_AF5 +#define TIM8_CH2_PB8_AF10 +#define TIM8_CH2_PC7_AF4 +#define TIM8_CH3N_PB1_AF4 +#define TIM8_CH3N_PB5_AF3 +#define TIM8_CH3N_PC12_AF4 +#define TIM8_CH3_PB9_AF10 +#define TIM8_CH3_PC8_AF4 +#define TIM8_CH4N_PC13_AF6 +#define TIM8_CH4N_PD0_AF6 +#define TIM8_CH4_PC9_AF4 +#define TIM8_CH4_PD1_AF4 +#define TIM8_ETR_PA0_AF10 +#define TIM8_ETR_PB6_AF6 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_8 (5) +#define TIM_MODULE_15 (6) +#define TIM_MODULE_16 (7) +#define TIM_MODULE_17 (8) +#define TIM_MODULE_20 (9) + +#define TIM_MODULE_COUNT (9) + +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM20_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PE0_CN +#define __PE1_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN +#define __PE6_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PF10_CN +#define __PF2_CN +#define __PF9_CN +#define __PG10_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN +#define __PORT_G_CN + +#define PORT_COUNT (7) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32L4P5AE/UFBGA169/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32L4P5AE/UFBGA169/mcu_definitions.h new file mode 100644 index 000000000..22c1559f3 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32L4P5AE/UFBGA169/mcu_definitions.h @@ -0,0 +1,569 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32L4P5AE_UFBGA169. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH5 +#define ADC1_PA1_CH6 +#define ADC1_PA2_CH7 +#define ADC1_PA3_CH8 +#define ADC1_PA4_CH9 +#define ADC1_PA5_CH10 +#define ADC1_PA6_CH11 +#define ADC1_PA7_CH12 +#define ADC1_PB0_CH15 +#define ADC1_PB1_CH16 +#define ADC1_PC0_CH1 +#define ADC1_PC1_CH2 +#define ADC1_PC2_CH3 +#define ADC1_PC3_CH4 +#define ADC1_PC4_CH13 +#define ADC1_PC5_CH14 +#define ADC2_PA0_CH5 +#define ADC2_PA1_CH6 +#define ADC2_PA2_CH7 +#define ADC2_PA3_CH8 +#define ADC2_PA4_CH9 +#define ADC2_PA5_CH10 +#define ADC2_PA6_CH11 +#define ADC2_PA7_CH12 +#define ADC2_PB0_CH15 +#define ADC2_PB1_CH16 +#define ADC2_PC0_CH1 +#define ADC2_PC1_CH2 +#define ADC2_PC2_CH3 +#define ADC2_PC3_CH4 +#define ADC2_PC4_CH13 +#define ADC2_PC5_CH14 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// CAN +#define CAN1_RX_PA11_AF9 +#define CAN1_RX_PB8_AF9 +#define CAN1_RX_PD0_AF9 +#define CAN1_RX_PI9_AF9 +#define CAN1_TX_PA12_AF9 +#define CAN1_TX_PB9_AF9 +#define CAN1_TX_PD1_AF9 +#define CAN1_TX_PH13_AF9 + +#define CAN_MODULE_1 (1) + +#define CAN_MODULE_COUNT (1) + +#define HAL_LL_CAN1_BASE_ADDRESS (0x40006400UL) + +#define HAL_LL_CAN1_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (94) +#define DMA_NUM_OF_CHANNELS_FAMILY (94) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (7) +#define DMA_NUM_OF_STREAMS_FAMILY (7) +// EOF DMA + +// I2C +#define I2C1_SCL_PB6_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SCL_PG14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C1_SDA_PG13_AF4 +#define I2C2_SCL_PB10_AF4 +#define I2C2_SCL_PB13_AF4 +#define I2C2_SCL_PF1_AF4 +#define I2C2_SCL_PH4_AF4 +#define I2C2_SDA_PB11_AF4 +#define I2C2_SDA_PB14_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C2_SDA_PH5_AF4 +#define I2C3_SCL_PA7_AF4 +#define I2C3_SCL_PC0_AF4 +#define I2C3_SCL_PG7_AF4 +#define I2C3_SCL_PH7_AF4 +#define I2C3_SDA_PB4_AF4 +#define I2C3_SDA_PC1_AF4 +#define I2C3_SDA_PC9_AF6 +#define I2C3_SDA_PG8_AF4 +#define I2C3_SDA_PH8_AF4 +#define I2C4_SCL_PB10_AF3 +#define I2C4_SCL_PB6_AF5 +#define I2C4_SCL_PD12_AF4 +#define I2C4_SCL_PF14_AF4 +#define I2C4_SDA_PB11_AF3 +#define I2C4_SDA_PB7_AF5 +#define I2C4_SDA_PD13_AF4 +#define I2C4_SDA_PF15_AF4 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF8 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_RX_PG8_AF8 +#define LPUART1_TX_PA2_AF8 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define LPUART1_TX_PG7_AF8 +#define UART4_RX_PA1_AF8 +#define UART4_RX_PC11_AF8 +#define UART4_TX_PA0_AF8 +#define UART4_TX_PC10_AF8 +#define UART5_RX_PD2_AF8 +#define UART5_TX_PC12_AF8 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PG10_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PG9_AF7 +#define USART2_RX_PA15_AF3 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PD6_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PD5_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PC5_AF7 +#define USART3_RX_PD9_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PC4_AF7 +#define USART3_TX_PD8_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF5 +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MISO_PE14_AF5 +#define SPI1_MISO_PG3_AF5 +#define SPI1_MOSI_PA12_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_MOSI_PE15_AF5 +#define SPI1_MOSI_PG4_AF5 +#define SPI1_SCK_PA1_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI1_SCK_PE13_AF5 +#define SPI1_SCK_PG2_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MISO_PC2_AF5 +#define SPI2_MISO_PD3_AF5 +#define SPI2_MISO_PI2_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_MOSI_PC1_AF3 +#define SPI2_MOSI_PC3_AF5 +#define SPI2_MOSI_PD4_AF5 +#define SPI2_MOSI_PI3_AF5 +#define SPI2_SCK_PA9_AF3 +#define SPI2_SCK_PB10_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PD1_AF5 +#define SPI2_SCK_PD3_AF3 +#define SPI2_SCK_PI1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MISO_PG10_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_MOSI_PD6_AF5 +#define SPI3_MOSI_PG11_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 +#define SPI3_SCK_PG9_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF1 +#define LPTIM1_ETR_PC3_AF1 +#define LPTIM1_ETR_PG12_AF1 +#define LPTIM2_ETR_PA5_AF14 +#define LPTIM2_ETR_PC3_AF14 +#define LPTIM2_ETR_PD11_AF14 +#define TIM15_BKIN_PA9_AF14 +#define TIM15_BKIN_PB12_AF14 +#define TIM15_CH1N_PA1_AF14 +#define TIM15_CH1N_PB13_AF14 +#define TIM15_CH1N_PG9_AF14 +#define TIM15_CH1_PA2_AF14 +#define TIM15_CH1_PB14_AF14 +#define TIM15_CH1_PG10_AF14 +#define TIM15_CH2_PA3_AF14 +#define TIM15_CH2_PB15_AF14 +#define TIM15_CH2_PF10_AF14 +#define TIM15_CH2_PG11_AF14 +#define TIM16_BKIN_PB5_AF14 +#define TIM16_CH1N_PB6_AF14 +#define TIM16_CH1_PA6_AF14 +#define TIM16_CH1_PB8_AF14 +#define TIM16_CH1_PE0_AF14 +#define TIM17_BKIN_PA10_AF14 +#define TIM17_BKIN_PB4_AF14 +#define TIM17_CH1N_PB7_AF14 +#define TIM17_CH1_PA7_AF14 +#define TIM17_CH1_PB9_AF14 +#define TIM17_CH1_PE1_AF14 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PE14_AF3 +#define TIM1_BKIN_PA6_AF12 +#define TIM1_BKIN_PB12_AF3 +#define TIM1_BKIN_PE15_AF3 +#define TIM1_CH1N_PA7_AF1 +#define TIM1_CH1N_PB13_AF1 +#define TIM1_CH1N_PE8_AF1 +#define TIM1_CH1_PA8_AF1 +#define TIM1_CH1_PE9_AF1 +#define TIM1_CH2N_PB0_AF1 +#define TIM1_CH2N_PB14_AF1 +#define TIM1_CH2N_PE10_AF1 +#define TIM1_CH2_PA9_AF1 +#define TIM1_CH2_PE11_AF1 +#define TIM1_CH3N_PB15_AF1 +#define TIM1_CH3N_PB1_AF1 +#define TIM1_CH3N_PE12_AF1 +#define TIM1_CH3_PA10_AF1 +#define TIM1_CH3_PE13_AF1 +#define TIM1_CH4_PA11_AF1 +#define TIM1_CH4_PE14_AF1 +#define TIM1_ETR_PA12_AF1 +#define TIM1_ETR_PE7_AF1 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH1_PE3_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH2_PE4_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH3_PE5_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PC9_AF2 +#define TIM3_CH4_PE6_AF2 +#define TIM3_ETR_PD2_AF2 +#define TIM3_ETR_PE2_AF2 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH1_PD12_AF2 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH2_PD13_AF2 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH3_PD14_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_CH4_PD15_AF2 +#define TIM4_ETR_PE0_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH1_PH10_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH2_PH11_AF2 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH3_PH12_AF2 +#define TIM5_CH4_PA3_AF2 +#define TIM5_CH4_PI0_AF2 +#define TIM8_BKIN2_PB6_AF12 +#define TIM8_BKIN2_PC9_AF14 +#define TIM8_BKIN_PA6_AF13 +#define TIM8_BKIN_PB7_AF13 +#define TIM8_BKIN_PI4_AF3 +#define TIM8_CH1N_PA5_AF3 +#define TIM8_CH1N_PA7_AF3 +#define TIM8_CH1N_PH13_AF3 +#define TIM8_CH1_PC6_AF3 +#define TIM8_CH1_PI5_AF3 +#define TIM8_CH2N_PB0_AF3 +#define TIM8_CH2N_PB14_AF3 +#define TIM8_CH2N_PH14_AF3 +#define TIM8_CH2_PC7_AF3 +#define TIM8_CH2_PI6_AF3 +#define TIM8_CH3N_PB15_AF3 +#define TIM8_CH3N_PB1_AF3 +#define TIM8_CH3N_PH15_AF3 +#define TIM8_CH3_PC8_AF3 +#define TIM8_CH3_PI7_AF3 +#define TIM8_CH4_PC9_AF3 +#define TIM8_CH4_PI2_AF3 +#define TIM8_ETR_PA0_AF3 +#define TIM8_ETR_PI3_AF3 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) + +#define TIM_MODULE_COUNT (9) + +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PE0_CN +#define __PE1_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN +#define __PE6_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PF10_CN +#define __PF11_CN +#define __PF12_CN +#define __PF13_CN +#define __PF14_CN +#define __PF15_CN +#define __PF2_CN +#define __PF3_CN +#define __PF4_CN +#define __PF5_CN +#define __PG0_CN +#define __PG1_CN +#define __PG10_CN +#define __PG11_CN +#define __PG12_CN +#define __PG13_CN +#define __PG14_CN +#define __PG15_CN +#define __PG2_CN +#define __PG3_CN +#define __PG4_CN +#define __PG5_CN +#define __PG6_CN +#define __PG7_CN +#define __PG8_CN +#define __PG9_CN +#define __PH0_CN +#define __PH1_CN +#define __PH10_CN +#define __PH11_CN +#define __PH12_CN +#define __PH13_CN +#define __PH14_CN +#define __PH15_CN +#define __PH2_CN +#define __PH3_CN +#define __PH4_CN +#define __PH5_CN +#define __PH6_CN +#define __PH7_CN +#define __PH8_CN +#define __PH9_CN +#define __PI0_CN +#define __PI1_CN +#define __PI10_CN +#define __PI11_CN +#define __PI2_CN +#define __PI3_CN +#define __PI4_CN +#define __PI5_CN +#define __PI6_CN +#define __PI7_CN +#define __PI8_CN +#define __PI9_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN +#define __PORT_G_CN +#define __PORT_H_CN +#define __PORT_I_CN + +#define PORT_COUNT (9) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32L4P5AG/UFBGA169/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32L4P5AG/UFBGA169/mcu_definitions.h new file mode 100644 index 000000000..3ac23cdad --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32L4P5AG/UFBGA169/mcu_definitions.h @@ -0,0 +1,569 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32L4P5AG_UFBGA169. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH5 +#define ADC1_PA1_CH6 +#define ADC1_PA2_CH7 +#define ADC1_PA3_CH8 +#define ADC1_PA4_CH9 +#define ADC1_PA5_CH10 +#define ADC1_PA6_CH11 +#define ADC1_PA7_CH12 +#define ADC1_PB0_CH15 +#define ADC1_PB1_CH16 +#define ADC1_PC0_CH1 +#define ADC1_PC1_CH2 +#define ADC1_PC2_CH3 +#define ADC1_PC3_CH4 +#define ADC1_PC4_CH13 +#define ADC1_PC5_CH14 +#define ADC2_PA0_CH5 +#define ADC2_PA1_CH6 +#define ADC2_PA2_CH7 +#define ADC2_PA3_CH8 +#define ADC2_PA4_CH9 +#define ADC2_PA5_CH10 +#define ADC2_PA6_CH11 +#define ADC2_PA7_CH12 +#define ADC2_PB0_CH15 +#define ADC2_PB1_CH16 +#define ADC2_PC0_CH1 +#define ADC2_PC1_CH2 +#define ADC2_PC2_CH3 +#define ADC2_PC3_CH4 +#define ADC2_PC4_CH13 +#define ADC2_PC5_CH14 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// CAN +#define CAN1_RX_PA11_AF9 +#define CAN1_RX_PB8_AF9 +#define CAN1_RX_PD0_AF9 +#define CAN1_RX_PI9_AF9 +#define CAN1_TX_PA12_AF9 +#define CAN1_TX_PB9_AF9 +#define CAN1_TX_PD1_AF9 +#define CAN1_TX_PH13_AF9 + +#define CAN_MODULE_1 (1) + +#define CAN_MODULE_COUNT (1) + +#define HAL_LL_CAN1_BASE_ADDRESS (0x40006400UL) + +#define HAL_LL_CAN1_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (94) +#define DMA_NUM_OF_CHANNELS_FAMILY (94) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (7) +#define DMA_NUM_OF_STREAMS_FAMILY (7) +// EOF DMA + +// I2C +#define I2C1_SCL_PB6_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SCL_PG14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C1_SDA_PG13_AF4 +#define I2C2_SCL_PB10_AF4 +#define I2C2_SCL_PB13_AF4 +#define I2C2_SCL_PF1_AF4 +#define I2C2_SCL_PH4_AF4 +#define I2C2_SDA_PB11_AF4 +#define I2C2_SDA_PB14_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C2_SDA_PH5_AF4 +#define I2C3_SCL_PA7_AF4 +#define I2C3_SCL_PC0_AF4 +#define I2C3_SCL_PG7_AF4 +#define I2C3_SCL_PH7_AF4 +#define I2C3_SDA_PB4_AF4 +#define I2C3_SDA_PC1_AF4 +#define I2C3_SDA_PC9_AF6 +#define I2C3_SDA_PG8_AF4 +#define I2C3_SDA_PH8_AF4 +#define I2C4_SCL_PB10_AF3 +#define I2C4_SCL_PB6_AF5 +#define I2C4_SCL_PD12_AF4 +#define I2C4_SCL_PF14_AF4 +#define I2C4_SDA_PB11_AF3 +#define I2C4_SDA_PB7_AF5 +#define I2C4_SDA_PD13_AF4 +#define I2C4_SDA_PF15_AF4 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF8 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_RX_PG8_AF8 +#define LPUART1_TX_PA2_AF8 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define LPUART1_TX_PG7_AF8 +#define UART4_RX_PA1_AF8 +#define UART4_RX_PC11_AF8 +#define UART4_TX_PA0_AF8 +#define UART4_TX_PC10_AF8 +#define UART5_RX_PD2_AF8 +#define UART5_TX_PC12_AF8 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PG10_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PG9_AF7 +#define USART2_RX_PA15_AF3 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PD6_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PD5_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PC5_AF7 +#define USART3_RX_PD9_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PC4_AF7 +#define USART3_TX_PD8_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF5 +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MISO_PE14_AF5 +#define SPI1_MISO_PG3_AF5 +#define SPI1_MOSI_PA12_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_MOSI_PE15_AF5 +#define SPI1_MOSI_PG4_AF5 +#define SPI1_SCK_PA1_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI1_SCK_PE13_AF5 +#define SPI1_SCK_PG2_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MISO_PC2_AF5 +#define SPI2_MISO_PD3_AF5 +#define SPI2_MISO_PI2_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_MOSI_PC1_AF3 +#define SPI2_MOSI_PC3_AF5 +#define SPI2_MOSI_PD4_AF5 +#define SPI2_MOSI_PI3_AF5 +#define SPI2_SCK_PA9_AF3 +#define SPI2_SCK_PB10_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PD1_AF5 +#define SPI2_SCK_PD3_AF3 +#define SPI2_SCK_PI1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MISO_PG10_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_MOSI_PD6_AF5 +#define SPI3_MOSI_PG11_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 +#define SPI3_SCK_PG9_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF1 +#define LPTIM1_ETR_PC3_AF1 +#define LPTIM1_ETR_PG12_AF1 +#define LPTIM2_ETR_PA5_AF14 +#define LPTIM2_ETR_PC3_AF14 +#define LPTIM2_ETR_PD11_AF14 +#define TIM15_BKIN_PA9_AF14 +#define TIM15_BKIN_PB12_AF14 +#define TIM15_CH1N_PA1_AF14 +#define TIM15_CH1N_PB13_AF14 +#define TIM15_CH1N_PG9_AF14 +#define TIM15_CH1_PA2_AF14 +#define TIM15_CH1_PB14_AF14 +#define TIM15_CH1_PG10_AF14 +#define TIM15_CH2_PA3_AF14 +#define TIM15_CH2_PB15_AF14 +#define TIM15_CH2_PF10_AF14 +#define TIM15_CH2_PG11_AF14 +#define TIM16_BKIN_PB5_AF14 +#define TIM16_CH1N_PB6_AF14 +#define TIM16_CH1_PA6_AF14 +#define TIM16_CH1_PB8_AF14 +#define TIM16_CH1_PE0_AF14 +#define TIM17_BKIN_PA10_AF14 +#define TIM17_BKIN_PB4_AF14 +#define TIM17_CH1N_PB7_AF14 +#define TIM17_CH1_PA7_AF14 +#define TIM17_CH1_PB9_AF14 +#define TIM17_CH1_PE1_AF14 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PE14_AF3 +#define TIM1_BKIN_PA6_AF12 +#define TIM1_BKIN_PB12_AF3 +#define TIM1_BKIN_PE15_AF3 +#define TIM1_CH1N_PA7_AF1 +#define TIM1_CH1N_PB13_AF1 +#define TIM1_CH1N_PE8_AF1 +#define TIM1_CH1_PA8_AF1 +#define TIM1_CH1_PE9_AF1 +#define TIM1_CH2N_PB0_AF1 +#define TIM1_CH2N_PB14_AF1 +#define TIM1_CH2N_PE10_AF1 +#define TIM1_CH2_PA9_AF1 +#define TIM1_CH2_PE11_AF1 +#define TIM1_CH3N_PB15_AF1 +#define TIM1_CH3N_PB1_AF1 +#define TIM1_CH3N_PE12_AF1 +#define TIM1_CH3_PA10_AF1 +#define TIM1_CH3_PE13_AF1 +#define TIM1_CH4_PA11_AF1 +#define TIM1_CH4_PE14_AF1 +#define TIM1_ETR_PA12_AF1 +#define TIM1_ETR_PE7_AF1 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH1_PE3_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH2_PE4_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH3_PE5_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PC9_AF2 +#define TIM3_CH4_PE6_AF2 +#define TIM3_ETR_PD2_AF2 +#define TIM3_ETR_PE2_AF2 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH1_PD12_AF2 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH2_PD13_AF2 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH3_PD14_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_CH4_PD15_AF2 +#define TIM4_ETR_PE0_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH1_PH10_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH2_PH11_AF2 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH3_PH12_AF2 +#define TIM5_CH4_PA3_AF2 +#define TIM5_CH4_PI0_AF2 +#define TIM8_BKIN2_PB6_AF12 +#define TIM8_BKIN2_PC9_AF14 +#define TIM8_BKIN_PA6_AF13 +#define TIM8_BKIN_PB7_AF13 +#define TIM8_BKIN_PI4_AF3 +#define TIM8_CH1N_PA5_AF3 +#define TIM8_CH1N_PA7_AF3 +#define TIM8_CH1N_PH13_AF3 +#define TIM8_CH1_PC6_AF3 +#define TIM8_CH1_PI5_AF3 +#define TIM8_CH2N_PB0_AF3 +#define TIM8_CH2N_PB14_AF3 +#define TIM8_CH2N_PH14_AF3 +#define TIM8_CH2_PC7_AF3 +#define TIM8_CH2_PI6_AF3 +#define TIM8_CH3N_PB15_AF3 +#define TIM8_CH3N_PB1_AF3 +#define TIM8_CH3N_PH15_AF3 +#define TIM8_CH3_PC8_AF3 +#define TIM8_CH3_PI7_AF3 +#define TIM8_CH4_PC9_AF3 +#define TIM8_CH4_PI2_AF3 +#define TIM8_ETR_PA0_AF3 +#define TIM8_ETR_PI3_AF3 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) + +#define TIM_MODULE_COUNT (9) + +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PE0_CN +#define __PE1_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN +#define __PE6_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PF10_CN +#define __PF11_CN +#define __PF12_CN +#define __PF13_CN +#define __PF14_CN +#define __PF15_CN +#define __PF2_CN +#define __PF3_CN +#define __PF4_CN +#define __PF5_CN +#define __PG0_CN +#define __PG1_CN +#define __PG10_CN +#define __PG11_CN +#define __PG12_CN +#define __PG13_CN +#define __PG14_CN +#define __PG15_CN +#define __PG2_CN +#define __PG3_CN +#define __PG4_CN +#define __PG5_CN +#define __PG6_CN +#define __PG7_CN +#define __PG8_CN +#define __PG9_CN +#define __PH0_CN +#define __PH1_CN +#define __PH10_CN +#define __PH11_CN +#define __PH12_CN +#define __PH13_CN +#define __PH14_CN +#define __PH15_CN +#define __PH2_CN +#define __PH3_CN +#define __PH4_CN +#define __PH5_CN +#define __PH6_CN +#define __PH7_CN +#define __PH8_CN +#define __PH9_CN +#define __PI0_CN +#define __PI1_CN +#define __PI10_CN +#define __PI11_CN +#define __PI2_CN +#define __PI3_CN +#define __PI4_CN +#define __PI5_CN +#define __PI6_CN +#define __PI7_CN +#define __PI8_CN +#define __PI9_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN +#define __PORT_G_CN +#define __PORT_H_CN +#define __PORT_I_CN + +#define PORT_COUNT (9) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32L4P5CE/LQFP48/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32L4P5CE/LQFP48/mcu_definitions.h new file mode 100644 index 000000000..a1dbae604 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32L4P5CE/LQFP48/mcu_definitions.h @@ -0,0 +1,336 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32L4P5CE_LQFP48. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH5 +#define ADC1_PA1_CH6 +#define ADC1_PA2_CH7 +#define ADC1_PA3_CH8 +#define ADC1_PA4_CH9 +#define ADC1_PA5_CH10 +#define ADC1_PA6_CH11 +#define ADC1_PA7_CH12 +#define ADC1_PB0_CH15 +#define ADC1_PB1_CH16 +#define ADC2_PA0_CH5 +#define ADC2_PA1_CH6 +#define ADC2_PA2_CH7 +#define ADC2_PA3_CH8 +#define ADC2_PA4_CH9 +#define ADC2_PA5_CH10 +#define ADC2_PA6_CH11 +#define ADC2_PA7_CH12 +#define ADC2_PB0_CH15 +#define ADC2_PB1_CH16 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// CAN +#define CAN1_RX_PA11_AF9 +#define CAN1_RX_PB8_AF9 +#define CAN1_TX_PA12_AF9 +#define CAN1_TX_PB9_AF9 + +#define CAN_MODULE_1 (1) + +#define CAN_MODULE_COUNT (1) + +#define HAL_LL_CAN1_BASE_ADDRESS (0x40006400UL) + +#define HAL_LL_CAN1_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (94) +#define DMA_NUM_OF_CHANNELS_FAMILY (94) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (7) +#define DMA_NUM_OF_STREAMS_FAMILY (7) +// EOF DMA + +// I2C +#define I2C1_SCL_PB6_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PB10_AF4 +#define I2C2_SCL_PB13_AF4 +#define I2C2_SDA_PB11_AF4 +#define I2C2_SDA_PB14_AF4 +#define I2C3_SCL_PA7_AF4 +#define I2C3_SDA_PB4_AF4 +#define I2C4_SCL_PB10_AF3 +#define I2C4_SCL_PB6_AF5 +#define I2C4_SDA_PB11_AF3 +#define I2C4_SDA_PB7_AF5 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF8 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_TX_PA2_AF8 +#define LPUART1_TX_PB11_AF8 +#define UART4_RX_PA1_AF8 +#define UART4_TX_PA0_AF8 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART2_RX_PA15_AF3 +#define USART2_RX_PA3_AF7 +#define USART2_TX_PA2_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_TX_PB10_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (4) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF5 +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA12_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA1_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PA9_AF3 +#define SPI2_SCK_PB10_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_SCK_PB3_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF1 +#define LPTIM2_ETR_PA5_AF14 +#define TIM15_BKIN_PA9_AF14 +#define TIM15_BKIN_PB12_AF14 +#define TIM15_CH1N_PA1_AF14 +#define TIM15_CH1N_PB13_AF14 +#define TIM15_CH1_PA2_AF14 +#define TIM15_CH1_PB14_AF14 +#define TIM15_CH2_PA3_AF14 +#define TIM15_CH2_PB15_AF14 +#define TIM16_BKIN_PB5_AF14 +#define TIM16_CH1N_PB6_AF14 +#define TIM16_CH1_PA6_AF14 +#define TIM16_CH1_PB8_AF14 +#define TIM17_BKIN_PA10_AF14 +#define TIM17_BKIN_PB4_AF14 +#define TIM17_CH1N_PB7_AF14 +#define TIM17_CH1_PA7_AF14 +#define TIM17_CH1_PB9_AF14 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN_PA6_AF12 +#define TIM1_BKIN_PB12_AF3 +#define TIM1_CH1N_PA7_AF1 +#define TIM1_CH1N_PB13_AF1 +#define TIM1_CH1_PA8_AF1 +#define TIM1_CH2N_PB0_AF1 +#define TIM1_CH2N_PB14_AF1 +#define TIM1_CH2_PA9_AF1 +#define TIM1_CH3N_PB15_AF1 +#define TIM1_CH3N_PB1_AF1 +#define TIM1_CH3_PA10_AF1 +#define TIM1_CH4_PA11_AF1 +#define TIM1_ETR_PA12_AF1 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH4_PA3_AF2 +#define TIM8_BKIN2_PB6_AF12 +#define TIM8_BKIN_PA6_AF13 +#define TIM8_BKIN_PB7_AF13 +#define TIM8_CH1N_PA5_AF3 +#define TIM8_CH1N_PA7_AF3 +#define TIM8_CH2N_PB0_AF3 +#define TIM8_CH2N_PB14_AF3 +#define TIM8_CH3N_PB15_AF3 +#define TIM8_CH3N_PB1_AF3 +#define TIM8_ETR_PA0_AF3 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) + +#define TIM_MODULE_COUNT (9) + +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PH0_CN +#define __PH1_CN +#define __PH3_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_H_CN + +#define PORT_COUNT (4) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32L4P5CE/UFQFPN48/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32L4P5CE/UFQFPN48/mcu_definitions.h new file mode 100644 index 000000000..c95b4b5b0 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32L4P5CE/UFQFPN48/mcu_definitions.h @@ -0,0 +1,336 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32L4P5CE_UFQFPN48. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH5 +#define ADC1_PA1_CH6 +#define ADC1_PA2_CH7 +#define ADC1_PA3_CH8 +#define ADC1_PA4_CH9 +#define ADC1_PA5_CH10 +#define ADC1_PA6_CH11 +#define ADC1_PA7_CH12 +#define ADC1_PB0_CH15 +#define ADC1_PB1_CH16 +#define ADC2_PA0_CH5 +#define ADC2_PA1_CH6 +#define ADC2_PA2_CH7 +#define ADC2_PA3_CH8 +#define ADC2_PA4_CH9 +#define ADC2_PA5_CH10 +#define ADC2_PA6_CH11 +#define ADC2_PA7_CH12 +#define ADC2_PB0_CH15 +#define ADC2_PB1_CH16 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// CAN +#define CAN1_RX_PA11_AF9 +#define CAN1_RX_PB8_AF9 +#define CAN1_TX_PA12_AF9 +#define CAN1_TX_PB9_AF9 + +#define CAN_MODULE_1 (1) + +#define CAN_MODULE_COUNT (1) + +#define HAL_LL_CAN1_BASE_ADDRESS (0x40006400UL) + +#define HAL_LL_CAN1_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (94) +#define DMA_NUM_OF_CHANNELS_FAMILY (94) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (7) +#define DMA_NUM_OF_STREAMS_FAMILY (7) +// EOF DMA + +// I2C +#define I2C1_SCL_PB6_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PB10_AF4 +#define I2C2_SCL_PB13_AF4 +#define I2C2_SDA_PB11_AF4 +#define I2C2_SDA_PB14_AF4 +#define I2C3_SCL_PA7_AF4 +#define I2C3_SDA_PB4_AF4 +#define I2C4_SCL_PB10_AF3 +#define I2C4_SCL_PB6_AF5 +#define I2C4_SDA_PB11_AF3 +#define I2C4_SDA_PB7_AF5 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF8 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_TX_PA2_AF8 +#define LPUART1_TX_PB11_AF8 +#define UART4_RX_PA1_AF8 +#define UART4_TX_PA0_AF8 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART2_RX_PA15_AF3 +#define USART2_RX_PA3_AF7 +#define USART2_TX_PA2_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_TX_PB10_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (4) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF5 +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA12_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA1_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PA9_AF3 +#define SPI2_SCK_PB10_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_SCK_PB3_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF1 +#define LPTIM2_ETR_PA5_AF14 +#define TIM15_BKIN_PA9_AF14 +#define TIM15_BKIN_PB12_AF14 +#define TIM15_CH1N_PA1_AF14 +#define TIM15_CH1N_PB13_AF14 +#define TIM15_CH1_PA2_AF14 +#define TIM15_CH1_PB14_AF14 +#define TIM15_CH2_PA3_AF14 +#define TIM15_CH2_PB15_AF14 +#define TIM16_BKIN_PB5_AF14 +#define TIM16_CH1N_PB6_AF14 +#define TIM16_CH1_PA6_AF14 +#define TIM16_CH1_PB8_AF14 +#define TIM17_BKIN_PA10_AF14 +#define TIM17_BKIN_PB4_AF14 +#define TIM17_CH1N_PB7_AF14 +#define TIM17_CH1_PA7_AF14 +#define TIM17_CH1_PB9_AF14 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN_PA6_AF12 +#define TIM1_BKIN_PB12_AF3 +#define TIM1_CH1N_PA7_AF1 +#define TIM1_CH1N_PB13_AF1 +#define TIM1_CH1_PA8_AF1 +#define TIM1_CH2N_PB0_AF1 +#define TIM1_CH2N_PB14_AF1 +#define TIM1_CH2_PA9_AF1 +#define TIM1_CH3N_PB15_AF1 +#define TIM1_CH3N_PB1_AF1 +#define TIM1_CH3_PA10_AF1 +#define TIM1_CH4_PA11_AF1 +#define TIM1_ETR_PA12_AF1 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH4_PA3_AF2 +#define TIM8_BKIN2_PB6_AF12 +#define TIM8_BKIN_PA6_AF13 +#define TIM8_BKIN_PB7_AF13 +#define TIM8_CH1N_PA5_AF3 +#define TIM8_CH1N_PA7_AF3 +#define TIM8_CH2N_PB0_AF3 +#define TIM8_CH2N_PB14_AF3 +#define TIM8_CH3N_PB15_AF3 +#define TIM8_CH3N_PB1_AF3 +#define TIM8_ETR_PA0_AF3 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) + +#define TIM_MODULE_COUNT (9) + +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PH0_CN +#define __PH1_CN +#define __PH3_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_H_CN + +#define PORT_COUNT (4) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32L4P5CG/LQFP48/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32L4P5CG/LQFP48/mcu_definitions.h new file mode 100644 index 000000000..d59136419 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32L4P5CG/LQFP48/mcu_definitions.h @@ -0,0 +1,336 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32L4P5CG_LQFP48. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH5 +#define ADC1_PA1_CH6 +#define ADC1_PA2_CH7 +#define ADC1_PA3_CH8 +#define ADC1_PA4_CH9 +#define ADC1_PA5_CH10 +#define ADC1_PA6_CH11 +#define ADC1_PA7_CH12 +#define ADC1_PB0_CH15 +#define ADC1_PB1_CH16 +#define ADC2_PA0_CH5 +#define ADC2_PA1_CH6 +#define ADC2_PA2_CH7 +#define ADC2_PA3_CH8 +#define ADC2_PA4_CH9 +#define ADC2_PA5_CH10 +#define ADC2_PA6_CH11 +#define ADC2_PA7_CH12 +#define ADC2_PB0_CH15 +#define ADC2_PB1_CH16 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// CAN +#define CAN1_RX_PA11_AF9 +#define CAN1_RX_PB8_AF9 +#define CAN1_TX_PA12_AF9 +#define CAN1_TX_PB9_AF9 + +#define CAN_MODULE_1 (1) + +#define CAN_MODULE_COUNT (1) + +#define HAL_LL_CAN1_BASE_ADDRESS (0x40006400UL) + +#define HAL_LL_CAN1_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (94) +#define DMA_NUM_OF_CHANNELS_FAMILY (94) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (7) +#define DMA_NUM_OF_STREAMS_FAMILY (7) +// EOF DMA + +// I2C +#define I2C1_SCL_PB6_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PB10_AF4 +#define I2C2_SCL_PB13_AF4 +#define I2C2_SDA_PB11_AF4 +#define I2C2_SDA_PB14_AF4 +#define I2C3_SCL_PA7_AF4 +#define I2C3_SDA_PB4_AF4 +#define I2C4_SCL_PB10_AF3 +#define I2C4_SCL_PB6_AF5 +#define I2C4_SDA_PB11_AF3 +#define I2C4_SDA_PB7_AF5 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF8 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_TX_PA2_AF8 +#define LPUART1_TX_PB11_AF8 +#define UART4_RX_PA1_AF8 +#define UART4_TX_PA0_AF8 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART2_RX_PA15_AF3 +#define USART2_RX_PA3_AF7 +#define USART2_TX_PA2_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_TX_PB10_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (4) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF5 +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA12_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA1_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PA9_AF3 +#define SPI2_SCK_PB10_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_SCK_PB3_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF1 +#define LPTIM2_ETR_PA5_AF14 +#define TIM15_BKIN_PA9_AF14 +#define TIM15_BKIN_PB12_AF14 +#define TIM15_CH1N_PA1_AF14 +#define TIM15_CH1N_PB13_AF14 +#define TIM15_CH1_PA2_AF14 +#define TIM15_CH1_PB14_AF14 +#define TIM15_CH2_PA3_AF14 +#define TIM15_CH2_PB15_AF14 +#define TIM16_BKIN_PB5_AF14 +#define TIM16_CH1N_PB6_AF14 +#define TIM16_CH1_PA6_AF14 +#define TIM16_CH1_PB8_AF14 +#define TIM17_BKIN_PA10_AF14 +#define TIM17_BKIN_PB4_AF14 +#define TIM17_CH1N_PB7_AF14 +#define TIM17_CH1_PA7_AF14 +#define TIM17_CH1_PB9_AF14 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN_PA6_AF12 +#define TIM1_BKIN_PB12_AF3 +#define TIM1_CH1N_PA7_AF1 +#define TIM1_CH1N_PB13_AF1 +#define TIM1_CH1_PA8_AF1 +#define TIM1_CH2N_PB0_AF1 +#define TIM1_CH2N_PB14_AF1 +#define TIM1_CH2_PA9_AF1 +#define TIM1_CH3N_PB15_AF1 +#define TIM1_CH3N_PB1_AF1 +#define TIM1_CH3_PA10_AF1 +#define TIM1_CH4_PA11_AF1 +#define TIM1_ETR_PA12_AF1 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH4_PA3_AF2 +#define TIM8_BKIN2_PB6_AF12 +#define TIM8_BKIN_PA6_AF13 +#define TIM8_BKIN_PB7_AF13 +#define TIM8_CH1N_PA5_AF3 +#define TIM8_CH1N_PA7_AF3 +#define TIM8_CH2N_PB0_AF3 +#define TIM8_CH2N_PB14_AF3 +#define TIM8_CH3N_PB15_AF3 +#define TIM8_CH3N_PB1_AF3 +#define TIM8_ETR_PA0_AF3 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) + +#define TIM_MODULE_COUNT (9) + +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PH0_CN +#define __PH1_CN +#define __PH3_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_H_CN + +#define PORT_COUNT (4) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32L4P5CG/UFQFPN48/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32L4P5CG/UFQFPN48/mcu_definitions.h new file mode 100644 index 000000000..1cce569f9 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32L4P5CG/UFQFPN48/mcu_definitions.h @@ -0,0 +1,336 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32L4P5CG_UFQFPN48. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH5 +#define ADC1_PA1_CH6 +#define ADC1_PA2_CH7 +#define ADC1_PA3_CH8 +#define ADC1_PA4_CH9 +#define ADC1_PA5_CH10 +#define ADC1_PA6_CH11 +#define ADC1_PA7_CH12 +#define ADC1_PB0_CH15 +#define ADC1_PB1_CH16 +#define ADC2_PA0_CH5 +#define ADC2_PA1_CH6 +#define ADC2_PA2_CH7 +#define ADC2_PA3_CH8 +#define ADC2_PA4_CH9 +#define ADC2_PA5_CH10 +#define ADC2_PA6_CH11 +#define ADC2_PA7_CH12 +#define ADC2_PB0_CH15 +#define ADC2_PB1_CH16 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// CAN +#define CAN1_RX_PA11_AF9 +#define CAN1_RX_PB8_AF9 +#define CAN1_TX_PA12_AF9 +#define CAN1_TX_PB9_AF9 + +#define CAN_MODULE_1 (1) + +#define CAN_MODULE_COUNT (1) + +#define HAL_LL_CAN1_BASE_ADDRESS (0x40006400UL) + +#define HAL_LL_CAN1_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (94) +#define DMA_NUM_OF_CHANNELS_FAMILY (94) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (7) +#define DMA_NUM_OF_STREAMS_FAMILY (7) +// EOF DMA + +// I2C +#define I2C1_SCL_PB6_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PB10_AF4 +#define I2C2_SCL_PB13_AF4 +#define I2C2_SDA_PB11_AF4 +#define I2C2_SDA_PB14_AF4 +#define I2C3_SCL_PA7_AF4 +#define I2C3_SDA_PB4_AF4 +#define I2C4_SCL_PB10_AF3 +#define I2C4_SCL_PB6_AF5 +#define I2C4_SDA_PB11_AF3 +#define I2C4_SDA_PB7_AF5 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF8 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_TX_PA2_AF8 +#define LPUART1_TX_PB11_AF8 +#define UART4_RX_PA1_AF8 +#define UART4_TX_PA0_AF8 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART2_RX_PA15_AF3 +#define USART2_RX_PA3_AF7 +#define USART2_TX_PA2_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_TX_PB10_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (4) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF5 +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA12_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA1_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PA9_AF3 +#define SPI2_SCK_PB10_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_SCK_PB3_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF1 +#define LPTIM2_ETR_PA5_AF14 +#define TIM15_BKIN_PA9_AF14 +#define TIM15_BKIN_PB12_AF14 +#define TIM15_CH1N_PA1_AF14 +#define TIM15_CH1N_PB13_AF14 +#define TIM15_CH1_PA2_AF14 +#define TIM15_CH1_PB14_AF14 +#define TIM15_CH2_PA3_AF14 +#define TIM15_CH2_PB15_AF14 +#define TIM16_BKIN_PB5_AF14 +#define TIM16_CH1N_PB6_AF14 +#define TIM16_CH1_PA6_AF14 +#define TIM16_CH1_PB8_AF14 +#define TIM17_BKIN_PA10_AF14 +#define TIM17_BKIN_PB4_AF14 +#define TIM17_CH1N_PB7_AF14 +#define TIM17_CH1_PA7_AF14 +#define TIM17_CH1_PB9_AF14 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN_PA6_AF12 +#define TIM1_BKIN_PB12_AF3 +#define TIM1_CH1N_PA7_AF1 +#define TIM1_CH1N_PB13_AF1 +#define TIM1_CH1_PA8_AF1 +#define TIM1_CH2N_PB0_AF1 +#define TIM1_CH2N_PB14_AF1 +#define TIM1_CH2_PA9_AF1 +#define TIM1_CH3N_PB15_AF1 +#define TIM1_CH3N_PB1_AF1 +#define TIM1_CH3_PA10_AF1 +#define TIM1_CH4_PA11_AF1 +#define TIM1_ETR_PA12_AF1 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH4_PA3_AF2 +#define TIM8_BKIN2_PB6_AF12 +#define TIM8_BKIN_PA6_AF13 +#define TIM8_BKIN_PB7_AF13 +#define TIM8_CH1N_PA5_AF3 +#define TIM8_CH1N_PA7_AF3 +#define TIM8_CH2N_PB0_AF3 +#define TIM8_CH2N_PB14_AF3 +#define TIM8_CH3N_PB15_AF3 +#define TIM8_CH3N_PB1_AF3 +#define TIM8_ETR_PA0_AF3 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) + +#define TIM_MODULE_COUNT (9) + +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PH0_CN +#define __PH1_CN +#define __PH3_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_H_CN + +#define PORT_COUNT (4) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32L4P5QE/UFBGA132/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32L4P5QE/UFBGA132/mcu_definitions.h new file mode 100644 index 000000000..6cd05bfef --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32L4P5QE/UFBGA132/mcu_definitions.h @@ -0,0 +1,519 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32L4P5QE_UFBGA132. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH5 +#define ADC1_PA1_CH6 +#define ADC1_PA2_CH7 +#define ADC1_PA3_CH8 +#define ADC1_PA4_CH9 +#define ADC1_PA5_CH10 +#define ADC1_PA6_CH11 +#define ADC1_PA7_CH12 +#define ADC1_PB0_CH15 +#define ADC1_PB1_CH16 +#define ADC1_PC0_CH1 +#define ADC1_PC1_CH2 +#define ADC1_PC2_CH3 +#define ADC1_PC3_CH4 +#define ADC1_PC4_CH13 +#define ADC1_PC5_CH14 +#define ADC2_PA0_CH5 +#define ADC2_PA1_CH6 +#define ADC2_PA2_CH7 +#define ADC2_PA3_CH8 +#define ADC2_PA4_CH9 +#define ADC2_PA5_CH10 +#define ADC2_PA6_CH11 +#define ADC2_PA7_CH12 +#define ADC2_PB0_CH15 +#define ADC2_PB1_CH16 +#define ADC2_PC0_CH1 +#define ADC2_PC1_CH2 +#define ADC2_PC2_CH3 +#define ADC2_PC3_CH4 +#define ADC2_PC4_CH13 +#define ADC2_PC5_CH14 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// CAN +#define CAN1_RX_PA11_AF9 +#define CAN1_RX_PB8_AF9 +#define CAN1_RX_PD0_AF9 +#define CAN1_TX_PA12_AF9 +#define CAN1_TX_PB9_AF9 +#define CAN1_TX_PD1_AF9 + +#define CAN_MODULE_1 (1) + +#define CAN_MODULE_COUNT (1) + +#define HAL_LL_CAN1_BASE_ADDRESS (0x40006400UL) + +#define HAL_LL_CAN1_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (94) +#define DMA_NUM_OF_CHANNELS_FAMILY (94) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (7) +#define DMA_NUM_OF_STREAMS_FAMILY (7) +// EOF DMA + +// I2C +#define I2C1_SCL_PB6_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SCL_PG14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C1_SDA_PG13_AF4 +#define I2C2_SCL_PB10_AF4 +#define I2C2_SCL_PB13_AF4 +#define I2C2_SCL_PF1_AF4 +#define I2C2_SDA_PB11_AF4 +#define I2C2_SDA_PB14_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA7_AF4 +#define I2C3_SCL_PC0_AF4 +#define I2C3_SCL_PG7_AF4 +#define I2C3_SDA_PB4_AF4 +#define I2C3_SDA_PC1_AF4 +#define I2C3_SDA_PC9_AF6 +#define I2C3_SDA_PG8_AF4 +#define I2C4_SCL_PB10_AF3 +#define I2C4_SCL_PB6_AF5 +#define I2C4_SCL_PD12_AF4 +#define I2C4_SCL_PF14_AF4 +#define I2C4_SDA_PB11_AF3 +#define I2C4_SDA_PB7_AF5 +#define I2C4_SDA_PD13_AF4 +#define I2C4_SDA_PF15_AF4 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF8 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_RX_PG8_AF8 +#define LPUART1_TX_PA2_AF8 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define LPUART1_TX_PG7_AF8 +#define UART4_RX_PA1_AF8 +#define UART4_RX_PC11_AF8 +#define UART4_TX_PA0_AF8 +#define UART4_TX_PC10_AF8 +#define UART5_RX_PD2_AF8 +#define UART5_TX_PC12_AF8 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PG10_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PG9_AF7 +#define USART2_RX_PA15_AF3 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PD6_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PD5_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PC5_AF7 +#define USART3_RX_PD9_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PC4_AF7 +#define USART3_TX_PD8_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF5 +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MISO_PE14_AF5 +#define SPI1_MISO_PG3_AF5 +#define SPI1_MOSI_PA12_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_MOSI_PE15_AF5 +#define SPI1_MOSI_PG4_AF5 +#define SPI1_SCK_PA1_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI1_SCK_PE13_AF5 +#define SPI1_SCK_PG2_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MISO_PC2_AF5 +#define SPI2_MISO_PD3_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_MOSI_PC1_AF3 +#define SPI2_MOSI_PC3_AF5 +#define SPI2_MOSI_PD4_AF5 +#define SPI2_SCK_PA9_AF3 +#define SPI2_SCK_PB10_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PD1_AF5 +#define SPI2_SCK_PD3_AF3 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MISO_PG10_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_MOSI_PD6_AF5 +#define SPI3_MOSI_PG11_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 +#define SPI3_SCK_PG9_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF1 +#define LPTIM1_ETR_PC3_AF1 +#define LPTIM1_ETR_PG12_AF1 +#define LPTIM2_ETR_PA5_AF14 +#define LPTIM2_ETR_PC3_AF14 +#define LPTIM2_ETR_PD11_AF14 +#define TIM15_BKIN_PA9_AF14 +#define TIM15_BKIN_PB12_AF14 +#define TIM15_CH1N_PA1_AF14 +#define TIM15_CH1N_PB13_AF14 +#define TIM15_CH1N_PG9_AF14 +#define TIM15_CH1_PA2_AF14 +#define TIM15_CH1_PB14_AF14 +#define TIM15_CH1_PG10_AF14 +#define TIM15_CH2_PA3_AF14 +#define TIM15_CH2_PB15_AF14 +#define TIM15_CH2_PG11_AF14 +#define TIM16_BKIN_PB5_AF14 +#define TIM16_CH1N_PB6_AF14 +#define TIM16_CH1_PA6_AF14 +#define TIM16_CH1_PB8_AF14 +#define TIM16_CH1_PE0_AF14 +#define TIM17_BKIN_PA10_AF14 +#define TIM17_BKIN_PB4_AF14 +#define TIM17_CH1N_PB7_AF14 +#define TIM17_CH1_PA7_AF14 +#define TIM17_CH1_PB9_AF14 +#define TIM17_CH1_PE1_AF14 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PE14_AF3 +#define TIM1_BKIN_PA6_AF12 +#define TIM1_BKIN_PB12_AF3 +#define TIM1_BKIN_PE15_AF3 +#define TIM1_CH1N_PA7_AF1 +#define TIM1_CH1N_PB13_AF1 +#define TIM1_CH1N_PE8_AF1 +#define TIM1_CH1_PA8_AF1 +#define TIM1_CH1_PE9_AF1 +#define TIM1_CH2N_PB0_AF1 +#define TIM1_CH2N_PB14_AF1 +#define TIM1_CH2N_PE10_AF1 +#define TIM1_CH2_PA9_AF1 +#define TIM1_CH2_PE11_AF1 +#define TIM1_CH3N_PB15_AF1 +#define TIM1_CH3N_PB1_AF1 +#define TIM1_CH3N_PE12_AF1 +#define TIM1_CH3_PA10_AF1 +#define TIM1_CH3_PE13_AF1 +#define TIM1_CH4_PA11_AF1 +#define TIM1_CH4_PE14_AF1 +#define TIM1_ETR_PA12_AF1 +#define TIM1_ETR_PE7_AF1 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH1_PE3_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH2_PE4_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH3_PE5_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PC9_AF2 +#define TIM3_CH4_PE6_AF2 +#define TIM3_ETR_PD2_AF2 +#define TIM3_ETR_PE2_AF2 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH1_PD12_AF2 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH2_PD13_AF2 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH3_PD14_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_CH4_PD15_AF2 +#define TIM4_ETR_PE0_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH4_PA3_AF2 +#define TIM8_BKIN2_PB6_AF12 +#define TIM8_BKIN2_PC9_AF14 +#define TIM8_BKIN_PA6_AF13 +#define TIM8_BKIN_PB7_AF13 +#define TIM8_CH1N_PA5_AF3 +#define TIM8_CH1N_PA7_AF3 +#define TIM8_CH1_PC6_AF3 +#define TIM8_CH2N_PB0_AF3 +#define TIM8_CH2N_PB14_AF3 +#define TIM8_CH2_PC7_AF3 +#define TIM8_CH3N_PB15_AF3 +#define TIM8_CH3N_PB1_AF3 +#define TIM8_CH3_PC8_AF3 +#define TIM8_CH4_PC9_AF3 +#define TIM8_ETR_PA0_AF3 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) + +#define TIM_MODULE_COUNT (9) + +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PE0_CN +#define __PE1_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN +#define __PE6_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PF11_CN +#define __PF12_CN +#define __PF13_CN +#define __PF14_CN +#define __PF15_CN +#define __PF2_CN +#define __PF3_CN +#define __PF4_CN +#define __PF5_CN +#define __PG0_CN +#define __PG1_CN +#define __PG10_CN +#define __PG11_CN +#define __PG12_CN +#define __PG13_CN +#define __PG14_CN +#define __PG15_CN +#define __PG2_CN +#define __PG3_CN +#define __PG4_CN +#define __PG5_CN +#define __PG6_CN +#define __PG7_CN +#define __PG8_CN +#define __PG9_CN +#define __PH0_CN +#define __PH1_CN +#define __PH3_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN +#define __PORT_G_CN +#define __PORT_H_CN + +#define PORT_COUNT (8) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32L4P5QG/UFBGA132/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32L4P5QG/UFBGA132/mcu_definitions.h new file mode 100644 index 000000000..442bc4da2 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32L4P5QG/UFBGA132/mcu_definitions.h @@ -0,0 +1,519 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32L4P5QG_UFBGA132. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH5 +#define ADC1_PA1_CH6 +#define ADC1_PA2_CH7 +#define ADC1_PA3_CH8 +#define ADC1_PA4_CH9 +#define ADC1_PA5_CH10 +#define ADC1_PA6_CH11 +#define ADC1_PA7_CH12 +#define ADC1_PB0_CH15 +#define ADC1_PB1_CH16 +#define ADC1_PC0_CH1 +#define ADC1_PC1_CH2 +#define ADC1_PC2_CH3 +#define ADC1_PC3_CH4 +#define ADC1_PC4_CH13 +#define ADC1_PC5_CH14 +#define ADC2_PA0_CH5 +#define ADC2_PA1_CH6 +#define ADC2_PA2_CH7 +#define ADC2_PA3_CH8 +#define ADC2_PA4_CH9 +#define ADC2_PA5_CH10 +#define ADC2_PA6_CH11 +#define ADC2_PA7_CH12 +#define ADC2_PB0_CH15 +#define ADC2_PB1_CH16 +#define ADC2_PC0_CH1 +#define ADC2_PC1_CH2 +#define ADC2_PC2_CH3 +#define ADC2_PC3_CH4 +#define ADC2_PC4_CH13 +#define ADC2_PC5_CH14 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// CAN +#define CAN1_RX_PA11_AF9 +#define CAN1_RX_PB8_AF9 +#define CAN1_RX_PD0_AF9 +#define CAN1_TX_PA12_AF9 +#define CAN1_TX_PB9_AF9 +#define CAN1_TX_PD1_AF9 + +#define CAN_MODULE_1 (1) + +#define CAN_MODULE_COUNT (1) + +#define HAL_LL_CAN1_BASE_ADDRESS (0x40006400UL) + +#define HAL_LL_CAN1_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (94) +#define DMA_NUM_OF_CHANNELS_FAMILY (94) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (7) +#define DMA_NUM_OF_STREAMS_FAMILY (7) +// EOF DMA + +// I2C +#define I2C1_SCL_PB6_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SCL_PG14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C1_SDA_PG13_AF4 +#define I2C2_SCL_PB10_AF4 +#define I2C2_SCL_PB13_AF4 +#define I2C2_SCL_PF1_AF4 +#define I2C2_SDA_PB11_AF4 +#define I2C2_SDA_PB14_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA7_AF4 +#define I2C3_SCL_PC0_AF4 +#define I2C3_SCL_PG7_AF4 +#define I2C3_SDA_PB4_AF4 +#define I2C3_SDA_PC1_AF4 +#define I2C3_SDA_PC9_AF6 +#define I2C3_SDA_PG8_AF4 +#define I2C4_SCL_PB10_AF3 +#define I2C4_SCL_PB6_AF5 +#define I2C4_SCL_PD12_AF4 +#define I2C4_SCL_PF14_AF4 +#define I2C4_SDA_PB11_AF3 +#define I2C4_SDA_PB7_AF5 +#define I2C4_SDA_PD13_AF4 +#define I2C4_SDA_PF15_AF4 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF8 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_RX_PG8_AF8 +#define LPUART1_TX_PA2_AF8 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define LPUART1_TX_PG7_AF8 +#define UART4_RX_PA1_AF8 +#define UART4_RX_PC11_AF8 +#define UART4_TX_PA0_AF8 +#define UART4_TX_PC10_AF8 +#define UART5_RX_PD2_AF8 +#define UART5_TX_PC12_AF8 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PG10_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PG9_AF7 +#define USART2_RX_PA15_AF3 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PD6_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PD5_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PC5_AF7 +#define USART3_RX_PD9_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PC4_AF7 +#define USART3_TX_PD8_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF5 +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MISO_PE14_AF5 +#define SPI1_MISO_PG3_AF5 +#define SPI1_MOSI_PA12_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_MOSI_PE15_AF5 +#define SPI1_MOSI_PG4_AF5 +#define SPI1_SCK_PA1_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI1_SCK_PE13_AF5 +#define SPI1_SCK_PG2_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MISO_PC2_AF5 +#define SPI2_MISO_PD3_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_MOSI_PC1_AF3 +#define SPI2_MOSI_PC3_AF5 +#define SPI2_MOSI_PD4_AF5 +#define SPI2_SCK_PA9_AF3 +#define SPI2_SCK_PB10_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PD1_AF5 +#define SPI2_SCK_PD3_AF3 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MISO_PG10_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_MOSI_PD6_AF5 +#define SPI3_MOSI_PG11_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 +#define SPI3_SCK_PG9_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF1 +#define LPTIM1_ETR_PC3_AF1 +#define LPTIM1_ETR_PG12_AF1 +#define LPTIM2_ETR_PA5_AF14 +#define LPTIM2_ETR_PC3_AF14 +#define LPTIM2_ETR_PD11_AF14 +#define TIM15_BKIN_PA9_AF14 +#define TIM15_BKIN_PB12_AF14 +#define TIM15_CH1N_PA1_AF14 +#define TIM15_CH1N_PB13_AF14 +#define TIM15_CH1N_PG9_AF14 +#define TIM15_CH1_PA2_AF14 +#define TIM15_CH1_PB14_AF14 +#define TIM15_CH1_PG10_AF14 +#define TIM15_CH2_PA3_AF14 +#define TIM15_CH2_PB15_AF14 +#define TIM15_CH2_PG11_AF14 +#define TIM16_BKIN_PB5_AF14 +#define TIM16_CH1N_PB6_AF14 +#define TIM16_CH1_PA6_AF14 +#define TIM16_CH1_PB8_AF14 +#define TIM16_CH1_PE0_AF14 +#define TIM17_BKIN_PA10_AF14 +#define TIM17_BKIN_PB4_AF14 +#define TIM17_CH1N_PB7_AF14 +#define TIM17_CH1_PA7_AF14 +#define TIM17_CH1_PB9_AF14 +#define TIM17_CH1_PE1_AF14 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PE14_AF3 +#define TIM1_BKIN_PA6_AF12 +#define TIM1_BKIN_PB12_AF3 +#define TIM1_BKIN_PE15_AF3 +#define TIM1_CH1N_PA7_AF1 +#define TIM1_CH1N_PB13_AF1 +#define TIM1_CH1N_PE8_AF1 +#define TIM1_CH1_PA8_AF1 +#define TIM1_CH1_PE9_AF1 +#define TIM1_CH2N_PB0_AF1 +#define TIM1_CH2N_PB14_AF1 +#define TIM1_CH2N_PE10_AF1 +#define TIM1_CH2_PA9_AF1 +#define TIM1_CH2_PE11_AF1 +#define TIM1_CH3N_PB15_AF1 +#define TIM1_CH3N_PB1_AF1 +#define TIM1_CH3N_PE12_AF1 +#define TIM1_CH3_PA10_AF1 +#define TIM1_CH3_PE13_AF1 +#define TIM1_CH4_PA11_AF1 +#define TIM1_CH4_PE14_AF1 +#define TIM1_ETR_PA12_AF1 +#define TIM1_ETR_PE7_AF1 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH1_PE3_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH2_PE4_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH3_PE5_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PC9_AF2 +#define TIM3_CH4_PE6_AF2 +#define TIM3_ETR_PD2_AF2 +#define TIM3_ETR_PE2_AF2 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH1_PD12_AF2 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH2_PD13_AF2 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH3_PD14_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_CH4_PD15_AF2 +#define TIM4_ETR_PE0_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH4_PA3_AF2 +#define TIM8_BKIN2_PB6_AF12 +#define TIM8_BKIN2_PC9_AF14 +#define TIM8_BKIN_PA6_AF13 +#define TIM8_BKIN_PB7_AF13 +#define TIM8_CH1N_PA5_AF3 +#define TIM8_CH1N_PA7_AF3 +#define TIM8_CH1_PC6_AF3 +#define TIM8_CH2N_PB0_AF3 +#define TIM8_CH2N_PB14_AF3 +#define TIM8_CH2_PC7_AF3 +#define TIM8_CH3N_PB15_AF3 +#define TIM8_CH3N_PB1_AF3 +#define TIM8_CH3_PC8_AF3 +#define TIM8_CH4_PC9_AF3 +#define TIM8_ETR_PA0_AF3 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) + +#define TIM_MODULE_COUNT (9) + +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PE0_CN +#define __PE1_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN +#define __PE6_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PF11_CN +#define __PF12_CN +#define __PF13_CN +#define __PF14_CN +#define __PF15_CN +#define __PF2_CN +#define __PF3_CN +#define __PF4_CN +#define __PF5_CN +#define __PG0_CN +#define __PG1_CN +#define __PG10_CN +#define __PG11_CN +#define __PG12_CN +#define __PG13_CN +#define __PG14_CN +#define __PG15_CN +#define __PG2_CN +#define __PG3_CN +#define __PG4_CN +#define __PG5_CN +#define __PG6_CN +#define __PG7_CN +#define __PG8_CN +#define __PG9_CN +#define __PH0_CN +#define __PH1_CN +#define __PH3_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN +#define __PORT_G_CN +#define __PORT_H_CN + +#define PORT_COUNT (8) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32L4P5RE/LQFP64/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32L4P5RE/LQFP64/mcu_definitions.h new file mode 100644 index 000000000..2ae31cc82 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32L4P5RE/LQFP64/mcu_definitions.h @@ -0,0 +1,392 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32L4P5RE_LQFP64. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH5 +#define ADC1_PA1_CH6 +#define ADC1_PA2_CH7 +#define ADC1_PA3_CH8 +#define ADC1_PA4_CH9 +#define ADC1_PA5_CH10 +#define ADC1_PA6_CH11 +#define ADC1_PA7_CH12 +#define ADC1_PB0_CH15 +#define ADC1_PB1_CH16 +#define ADC1_PC0_CH1 +#define ADC1_PC1_CH2 +#define ADC1_PC2_CH3 +#define ADC1_PC3_CH4 +#define ADC1_PC4_CH13 +#define ADC1_PC5_CH14 +#define ADC2_PA0_CH5 +#define ADC2_PA1_CH6 +#define ADC2_PA2_CH7 +#define ADC2_PA3_CH8 +#define ADC2_PA4_CH9 +#define ADC2_PA5_CH10 +#define ADC2_PA6_CH11 +#define ADC2_PA7_CH12 +#define ADC2_PB0_CH15 +#define ADC2_PB1_CH16 +#define ADC2_PC0_CH1 +#define ADC2_PC1_CH2 +#define ADC2_PC2_CH3 +#define ADC2_PC3_CH4 +#define ADC2_PC4_CH13 +#define ADC2_PC5_CH14 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// CAN +#define CAN1_RX_PA11_AF9 +#define CAN1_RX_PB8_AF9 +#define CAN1_TX_PA12_AF9 +#define CAN1_TX_PB9_AF9 + +#define CAN_MODULE_1 (1) + +#define CAN_MODULE_COUNT (1) + +#define HAL_LL_CAN1_BASE_ADDRESS (0x40006400UL) + +#define HAL_LL_CAN1_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (94) +#define DMA_NUM_OF_CHANNELS_FAMILY (94) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (7) +#define DMA_NUM_OF_STREAMS_FAMILY (7) +// EOF DMA + +// I2C +#define I2C1_SCL_PB6_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PB10_AF4 +#define I2C2_SCL_PB13_AF4 +#define I2C2_SDA_PB11_AF4 +#define I2C2_SDA_PB14_AF4 +#define I2C3_SCL_PA7_AF4 +#define I2C3_SCL_PC0_AF4 +#define I2C3_SDA_PB4_AF4 +#define I2C3_SDA_PC1_AF4 +#define I2C3_SDA_PC9_AF6 +#define I2C4_SCL_PB10_AF3 +#define I2C4_SCL_PB6_AF5 +#define I2C4_SDA_PB11_AF3 +#define I2C4_SDA_PB7_AF5 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF8 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF8 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PA1_AF8 +#define UART4_RX_PC11_AF8 +#define UART4_TX_PA0_AF8 +#define UART4_TX_PC10_AF8 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART2_RX_PA15_AF3 +#define USART2_RX_PA3_AF7 +#define USART2_TX_PA2_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PC5_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PC4_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (4) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF5 +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA12_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA1_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MISO_PC2_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_MOSI_PC1_AF3 +#define SPI2_MOSI_PC3_AF5 +#define SPI2_SCK_PA9_AF3 +#define SPI2_SCK_PB10_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF1 +#define LPTIM1_ETR_PC3_AF1 +#define LPTIM2_ETR_PA5_AF14 +#define LPTIM2_ETR_PC3_AF14 +#define TIM15_BKIN_PA9_AF14 +#define TIM15_BKIN_PB12_AF14 +#define TIM15_CH1N_PA1_AF14 +#define TIM15_CH1N_PB13_AF14 +#define TIM15_CH1_PA2_AF14 +#define TIM15_CH1_PB14_AF14 +#define TIM15_CH2_PA3_AF14 +#define TIM15_CH2_PB15_AF14 +#define TIM16_BKIN_PB5_AF14 +#define TIM16_CH1N_PB6_AF14 +#define TIM16_CH1_PA6_AF14 +#define TIM16_CH1_PB8_AF14 +#define TIM17_BKIN_PA10_AF14 +#define TIM17_BKIN_PB4_AF14 +#define TIM17_CH1N_PB7_AF14 +#define TIM17_CH1_PA7_AF14 +#define TIM17_CH1_PB9_AF14 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN_PA6_AF12 +#define TIM1_BKIN_PB12_AF3 +#define TIM1_CH1N_PA7_AF1 +#define TIM1_CH1N_PB13_AF1 +#define TIM1_CH1_PA8_AF1 +#define TIM1_CH2N_PB0_AF1 +#define TIM1_CH2N_PB14_AF1 +#define TIM1_CH2_PA9_AF1 +#define TIM1_CH3N_PB15_AF1 +#define TIM1_CH3N_PB1_AF1 +#define TIM1_CH3_PA10_AF1 +#define TIM1_CH4_PA11_AF1 +#define TIM1_ETR_PA12_AF1 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PC9_AF2 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH4_PA3_AF2 +#define TIM8_BKIN2_PB6_AF12 +#define TIM8_BKIN2_PC9_AF14 +#define TIM8_BKIN_PA6_AF13 +#define TIM8_BKIN_PB7_AF13 +#define TIM8_CH1N_PA5_AF3 +#define TIM8_CH1N_PA7_AF3 +#define TIM8_CH1_PC6_AF3 +#define TIM8_CH2N_PB0_AF3 +#define TIM8_CH2N_PB14_AF3 +#define TIM8_CH2_PC7_AF3 +#define TIM8_CH3N_PB15_AF3 +#define TIM8_CH3N_PB1_AF3 +#define TIM8_CH3_PC8_AF3 +#define TIM8_CH4_PC9_AF3 +#define TIM8_ETR_PA0_AF3 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) + +#define TIM_MODULE_COUNT (9) + +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD2_CN +#define __PH0_CN +#define __PH1_CN +#define __PH3_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_H_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32L4P5RG/LQFP64/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32L4P5RG/LQFP64/mcu_definitions.h new file mode 100644 index 000000000..3b95bc772 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32L4P5RG/LQFP64/mcu_definitions.h @@ -0,0 +1,392 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32L4P5RG_LQFP64. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH5 +#define ADC1_PA1_CH6 +#define ADC1_PA2_CH7 +#define ADC1_PA3_CH8 +#define ADC1_PA4_CH9 +#define ADC1_PA5_CH10 +#define ADC1_PA6_CH11 +#define ADC1_PA7_CH12 +#define ADC1_PB0_CH15 +#define ADC1_PB1_CH16 +#define ADC1_PC0_CH1 +#define ADC1_PC1_CH2 +#define ADC1_PC2_CH3 +#define ADC1_PC3_CH4 +#define ADC1_PC4_CH13 +#define ADC1_PC5_CH14 +#define ADC2_PA0_CH5 +#define ADC2_PA1_CH6 +#define ADC2_PA2_CH7 +#define ADC2_PA3_CH8 +#define ADC2_PA4_CH9 +#define ADC2_PA5_CH10 +#define ADC2_PA6_CH11 +#define ADC2_PA7_CH12 +#define ADC2_PB0_CH15 +#define ADC2_PB1_CH16 +#define ADC2_PC0_CH1 +#define ADC2_PC1_CH2 +#define ADC2_PC2_CH3 +#define ADC2_PC3_CH4 +#define ADC2_PC4_CH13 +#define ADC2_PC5_CH14 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// CAN +#define CAN1_RX_PA11_AF9 +#define CAN1_RX_PB8_AF9 +#define CAN1_TX_PA12_AF9 +#define CAN1_TX_PB9_AF9 + +#define CAN_MODULE_1 (1) + +#define CAN_MODULE_COUNT (1) + +#define HAL_LL_CAN1_BASE_ADDRESS (0x40006400UL) + +#define HAL_LL_CAN1_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (94) +#define DMA_NUM_OF_CHANNELS_FAMILY (94) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (7) +#define DMA_NUM_OF_STREAMS_FAMILY (7) +// EOF DMA + +// I2C +#define I2C1_SCL_PB6_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PB10_AF4 +#define I2C2_SCL_PB13_AF4 +#define I2C2_SDA_PB11_AF4 +#define I2C2_SDA_PB14_AF4 +#define I2C3_SCL_PA7_AF4 +#define I2C3_SCL_PC0_AF4 +#define I2C3_SDA_PB4_AF4 +#define I2C3_SDA_PC1_AF4 +#define I2C3_SDA_PC9_AF6 +#define I2C4_SCL_PB10_AF3 +#define I2C4_SCL_PB6_AF5 +#define I2C4_SDA_PB11_AF3 +#define I2C4_SDA_PB7_AF5 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF8 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF8 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PA1_AF8 +#define UART4_RX_PC11_AF8 +#define UART4_TX_PA0_AF8 +#define UART4_TX_PC10_AF8 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART2_RX_PA15_AF3 +#define USART2_RX_PA3_AF7 +#define USART2_TX_PA2_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PC5_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PC4_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (4) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF5 +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA12_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA1_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MISO_PC2_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_MOSI_PC1_AF3 +#define SPI2_MOSI_PC3_AF5 +#define SPI2_SCK_PA9_AF3 +#define SPI2_SCK_PB10_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF1 +#define LPTIM1_ETR_PC3_AF1 +#define LPTIM2_ETR_PA5_AF14 +#define LPTIM2_ETR_PC3_AF14 +#define TIM15_BKIN_PA9_AF14 +#define TIM15_BKIN_PB12_AF14 +#define TIM15_CH1N_PA1_AF14 +#define TIM15_CH1N_PB13_AF14 +#define TIM15_CH1_PA2_AF14 +#define TIM15_CH1_PB14_AF14 +#define TIM15_CH2_PA3_AF14 +#define TIM15_CH2_PB15_AF14 +#define TIM16_BKIN_PB5_AF14 +#define TIM16_CH1N_PB6_AF14 +#define TIM16_CH1_PA6_AF14 +#define TIM16_CH1_PB8_AF14 +#define TIM17_BKIN_PA10_AF14 +#define TIM17_BKIN_PB4_AF14 +#define TIM17_CH1N_PB7_AF14 +#define TIM17_CH1_PA7_AF14 +#define TIM17_CH1_PB9_AF14 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN_PA6_AF12 +#define TIM1_BKIN_PB12_AF3 +#define TIM1_CH1N_PA7_AF1 +#define TIM1_CH1N_PB13_AF1 +#define TIM1_CH1_PA8_AF1 +#define TIM1_CH2N_PB0_AF1 +#define TIM1_CH2N_PB14_AF1 +#define TIM1_CH2_PA9_AF1 +#define TIM1_CH3N_PB15_AF1 +#define TIM1_CH3N_PB1_AF1 +#define TIM1_CH3_PA10_AF1 +#define TIM1_CH4_PA11_AF1 +#define TIM1_ETR_PA12_AF1 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PC9_AF2 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH4_PA3_AF2 +#define TIM8_BKIN2_PB6_AF12 +#define TIM8_BKIN2_PC9_AF14 +#define TIM8_BKIN_PA6_AF13 +#define TIM8_BKIN_PB7_AF13 +#define TIM8_CH1N_PA5_AF3 +#define TIM8_CH1N_PA7_AF3 +#define TIM8_CH1_PC6_AF3 +#define TIM8_CH2N_PB0_AF3 +#define TIM8_CH2N_PB14_AF3 +#define TIM8_CH2_PC7_AF3 +#define TIM8_CH3N_PB15_AF3 +#define TIM8_CH3N_PB1_AF3 +#define TIM8_CH3_PC8_AF3 +#define TIM8_CH4_PC9_AF3 +#define TIM8_ETR_PA0_AF3 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) + +#define TIM_MODULE_COUNT (9) + +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD2_CN +#define __PH0_CN +#define __PH1_CN +#define __PH3_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_H_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32L4P5VE/LQFP100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32L4P5VE/LQFP100/mcu_definitions.h new file mode 100644 index 000000000..a79bc7bb8 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32L4P5VE/LQFP100/mcu_definitions.h @@ -0,0 +1,468 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32L4P5VE_LQFP100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH5 +#define ADC1_PA1_CH6 +#define ADC1_PA2_CH7 +#define ADC1_PA3_CH8 +#define ADC1_PA4_CH9 +#define ADC1_PA5_CH10 +#define ADC1_PA6_CH11 +#define ADC1_PA7_CH12 +#define ADC1_PB0_CH15 +#define ADC1_PB1_CH16 +#define ADC1_PC0_CH1 +#define ADC1_PC1_CH2 +#define ADC1_PC2_CH3 +#define ADC1_PC3_CH4 +#define ADC1_PC4_CH13 +#define ADC1_PC5_CH14 +#define ADC2_PA0_CH5 +#define ADC2_PA1_CH6 +#define ADC2_PA2_CH7 +#define ADC2_PA3_CH8 +#define ADC2_PA4_CH9 +#define ADC2_PA5_CH10 +#define ADC2_PA6_CH11 +#define ADC2_PA7_CH12 +#define ADC2_PB0_CH15 +#define ADC2_PB1_CH16 +#define ADC2_PC0_CH1 +#define ADC2_PC1_CH2 +#define ADC2_PC2_CH3 +#define ADC2_PC3_CH4 +#define ADC2_PC4_CH13 +#define ADC2_PC5_CH14 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// CAN +#define CAN1_RX_PA11_AF9 +#define CAN1_RX_PB8_AF9 +#define CAN1_RX_PD0_AF9 +#define CAN1_TX_PA12_AF9 +#define CAN1_TX_PB9_AF9 +#define CAN1_TX_PD1_AF9 + +#define CAN_MODULE_1 (1) + +#define CAN_MODULE_COUNT (1) + +#define HAL_LL_CAN1_BASE_ADDRESS (0x40006400UL) + +#define HAL_LL_CAN1_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (94) +#define DMA_NUM_OF_CHANNELS_FAMILY (94) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (7) +#define DMA_NUM_OF_STREAMS_FAMILY (7) +// EOF DMA + +// I2C +#define I2C1_SCL_PB6_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PB10_AF4 +#define I2C2_SCL_PB13_AF4 +#define I2C2_SDA_PB11_AF4 +#define I2C2_SDA_PB14_AF4 +#define I2C3_SCL_PA7_AF4 +#define I2C3_SCL_PC0_AF4 +#define I2C3_SDA_PB4_AF4 +#define I2C3_SDA_PC1_AF4 +#define I2C3_SDA_PC9_AF6 +#define I2C4_SCL_PB10_AF3 +#define I2C4_SCL_PB6_AF5 +#define I2C4_SCL_PD12_AF4 +#define I2C4_SDA_PB11_AF3 +#define I2C4_SDA_PB7_AF5 +#define I2C4_SDA_PD13_AF4 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF8 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF8 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PA1_AF8 +#define UART4_RX_PC11_AF8 +#define UART4_TX_PA0_AF8 +#define UART4_TX_PC10_AF8 +#define UART5_RX_PD2_AF8 +#define UART5_TX_PC12_AF8 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART2_RX_PA15_AF3 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PD6_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PD5_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PC5_AF7 +#define USART3_RX_PD9_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PC4_AF7 +#define USART3_TX_PD8_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF5 +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MISO_PE14_AF5 +#define SPI1_MOSI_PA12_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_MOSI_PE15_AF5 +#define SPI1_SCK_PA1_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI1_SCK_PE13_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MISO_PC2_AF5 +#define SPI2_MISO_PD3_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_MOSI_PC1_AF3 +#define SPI2_MOSI_PC3_AF5 +#define SPI2_MOSI_PD4_AF5 +#define SPI2_SCK_PA9_AF3 +#define SPI2_SCK_PB10_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PD1_AF5 +#define SPI2_SCK_PD3_AF3 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_MOSI_PD6_AF5 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF1 +#define LPTIM1_ETR_PC3_AF1 +#define LPTIM2_ETR_PA5_AF14 +#define LPTIM2_ETR_PC3_AF14 +#define LPTIM2_ETR_PD11_AF14 +#define TIM15_BKIN_PA9_AF14 +#define TIM15_BKIN_PB12_AF14 +#define TIM15_CH1N_PA1_AF14 +#define TIM15_CH1N_PB13_AF14 +#define TIM15_CH1_PA2_AF14 +#define TIM15_CH1_PB14_AF14 +#define TIM15_CH2_PA3_AF14 +#define TIM15_CH2_PB15_AF14 +#define TIM16_BKIN_PB5_AF14 +#define TIM16_CH1N_PB6_AF14 +#define TIM16_CH1_PA6_AF14 +#define TIM16_CH1_PB8_AF14 +#define TIM16_CH1_PE0_AF14 +#define TIM17_BKIN_PA10_AF14 +#define TIM17_BKIN_PB4_AF14 +#define TIM17_CH1N_PB7_AF14 +#define TIM17_CH1_PA7_AF14 +#define TIM17_CH1_PB9_AF14 +#define TIM17_CH1_PE1_AF14 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PE14_AF3 +#define TIM1_BKIN_PA6_AF12 +#define TIM1_BKIN_PB12_AF3 +#define TIM1_BKIN_PE15_AF3 +#define TIM1_CH1N_PA7_AF1 +#define TIM1_CH1N_PB13_AF1 +#define TIM1_CH1N_PE8_AF1 +#define TIM1_CH1_PA8_AF1 +#define TIM1_CH1_PE9_AF1 +#define TIM1_CH2N_PB0_AF1 +#define TIM1_CH2N_PB14_AF1 +#define TIM1_CH2N_PE10_AF1 +#define TIM1_CH2_PA9_AF1 +#define TIM1_CH2_PE11_AF1 +#define TIM1_CH3N_PB15_AF1 +#define TIM1_CH3N_PB1_AF1 +#define TIM1_CH3N_PE12_AF1 +#define TIM1_CH3_PA10_AF1 +#define TIM1_CH3_PE13_AF1 +#define TIM1_CH4_PA11_AF1 +#define TIM1_CH4_PE14_AF1 +#define TIM1_ETR_PA12_AF1 +#define TIM1_ETR_PE7_AF1 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH1_PE3_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH2_PE4_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH3_PE5_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PC9_AF2 +#define TIM3_CH4_PE6_AF2 +#define TIM3_ETR_PD2_AF2 +#define TIM3_ETR_PE2_AF2 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH1_PD12_AF2 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH2_PD13_AF2 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH3_PD14_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_CH4_PD15_AF2 +#define TIM4_ETR_PE0_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH4_PA3_AF2 +#define TIM8_BKIN2_PB6_AF12 +#define TIM8_BKIN2_PC9_AF14 +#define TIM8_BKIN_PA6_AF13 +#define TIM8_BKIN_PB7_AF13 +#define TIM8_CH1N_PA5_AF3 +#define TIM8_CH1N_PA7_AF3 +#define TIM8_CH1_PC6_AF3 +#define TIM8_CH2N_PB0_AF3 +#define TIM8_CH2N_PB14_AF3 +#define TIM8_CH2_PC7_AF3 +#define TIM8_CH3N_PB15_AF3 +#define TIM8_CH3N_PB1_AF3 +#define TIM8_CH3_PC8_AF3 +#define TIM8_CH4_PC9_AF3 +#define TIM8_ETR_PA0_AF3 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) + +#define TIM_MODULE_COUNT (9) + +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PE0_CN +#define __PE1_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN +#define __PE6_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PH0_CN +#define __PH1_CN +#define __PH3_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_H_CN + +#define PORT_COUNT (6) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32L4P5VE/WLCSP100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32L4P5VE/WLCSP100/mcu_definitions.h new file mode 100644 index 000000000..422a4bd01 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32L4P5VE/WLCSP100/mcu_definitions.h @@ -0,0 +1,466 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32L4P5VE_WLCSP100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH5 +#define ADC1_PA1_CH6 +#define ADC1_PA2_CH7 +#define ADC1_PA3_CH8 +#define ADC1_PA4_CH9 +#define ADC1_PA5_CH10 +#define ADC1_PA6_CH11 +#define ADC1_PA7_CH12 +#define ADC1_PB0_CH15 +#define ADC1_PB1_CH16 +#define ADC1_PC0_CH1 +#define ADC1_PC1_CH2 +#define ADC1_PC2_CH3 +#define ADC1_PC3_CH4 +#define ADC1_PC4_CH13 +#define ADC1_PC5_CH14 +#define ADC2_PA0_CH5 +#define ADC2_PA1_CH6 +#define ADC2_PA2_CH7 +#define ADC2_PA3_CH8 +#define ADC2_PA4_CH9 +#define ADC2_PA5_CH10 +#define ADC2_PA6_CH11 +#define ADC2_PA7_CH12 +#define ADC2_PB0_CH15 +#define ADC2_PB1_CH16 +#define ADC2_PC0_CH1 +#define ADC2_PC1_CH2 +#define ADC2_PC2_CH3 +#define ADC2_PC3_CH4 +#define ADC2_PC4_CH13 +#define ADC2_PC5_CH14 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// CAN +#define CAN1_RX_PA11_AF9 +#define CAN1_RX_PB8_AF9 +#define CAN1_RX_PD0_AF9 +#define CAN1_TX_PA12_AF9 +#define CAN1_TX_PB9_AF9 +#define CAN1_TX_PD1_AF9 + +#define CAN_MODULE_1 (1) + +#define CAN_MODULE_COUNT (1) + +#define HAL_LL_CAN1_BASE_ADDRESS (0x40006400UL) + +#define HAL_LL_CAN1_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (94) +#define DMA_NUM_OF_CHANNELS_FAMILY (94) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (7) +#define DMA_NUM_OF_STREAMS_FAMILY (7) +// EOF DMA + +// I2C +#define I2C1_SCL_PB6_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PB10_AF4 +#define I2C2_SCL_PB13_AF4 +#define I2C2_SDA_PB11_AF4 +#define I2C2_SDA_PB14_AF4 +#define I2C3_SCL_PA7_AF4 +#define I2C3_SCL_PC0_AF4 +#define I2C3_SDA_PB4_AF4 +#define I2C3_SDA_PC1_AF4 +#define I2C3_SDA_PC9_AF6 +#define I2C4_SCL_PB10_AF3 +#define I2C4_SCL_PB6_AF5 +#define I2C4_SDA_PB11_AF3 +#define I2C4_SDA_PB7_AF5 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF8 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF8 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PA1_AF8 +#define UART4_RX_PC11_AF8 +#define UART4_TX_PA0_AF8 +#define UART4_TX_PC10_AF8 +#define UART5_RX_PD2_AF8 +#define UART5_TX_PC12_AF8 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PG10_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PG9_AF7 +#define USART2_RX_PA15_AF3 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PD6_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PD5_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PC5_AF7 +#define USART3_RX_PD9_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PC4_AF7 +#define USART3_TX_PD8_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF5 +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MISO_PE14_AF5 +#define SPI1_MOSI_PA12_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_MOSI_PE15_AF5 +#define SPI1_SCK_PA1_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI1_SCK_PE13_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MISO_PC2_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_MOSI_PC1_AF3 +#define SPI2_MOSI_PC3_AF5 +#define SPI2_MOSI_PD4_AF5 +#define SPI2_SCK_PA9_AF3 +#define SPI2_SCK_PB10_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PD1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MISO_PG10_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_MOSI_PD6_AF5 +#define SPI3_MOSI_PG11_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 +#define SPI3_SCK_PG9_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF1 +#define LPTIM1_ETR_PC3_AF1 +#define LPTIM1_ETR_PG12_AF1 +#define LPTIM2_ETR_PA5_AF14 +#define LPTIM2_ETR_PC3_AF14 +#define TIM15_BKIN_PA9_AF14 +#define TIM15_BKIN_PB12_AF14 +#define TIM15_CH1N_PA1_AF14 +#define TIM15_CH1N_PB13_AF14 +#define TIM15_CH1N_PG9_AF14 +#define TIM15_CH1_PA2_AF14 +#define TIM15_CH1_PB14_AF14 +#define TIM15_CH1_PG10_AF14 +#define TIM15_CH2_PA3_AF14 +#define TIM15_CH2_PB15_AF14 +#define TIM15_CH2_PG11_AF14 +#define TIM16_BKIN_PB5_AF14 +#define TIM16_CH1N_PB6_AF14 +#define TIM16_CH1_PA6_AF14 +#define TIM16_CH1_PB8_AF14 +#define TIM17_BKIN_PA10_AF14 +#define TIM17_BKIN_PB4_AF14 +#define TIM17_CH1N_PB7_AF14 +#define TIM17_CH1_PA7_AF14 +#define TIM17_CH1_PB9_AF14 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PE14_AF3 +#define TIM1_BKIN_PA6_AF12 +#define TIM1_BKIN_PB12_AF3 +#define TIM1_BKIN_PE15_AF3 +#define TIM1_CH1N_PA7_AF1 +#define TIM1_CH1N_PB13_AF1 +#define TIM1_CH1N_PE8_AF1 +#define TIM1_CH1_PA8_AF1 +#define TIM1_CH1_PE9_AF1 +#define TIM1_CH2N_PB0_AF1 +#define TIM1_CH2N_PB14_AF1 +#define TIM1_CH2N_PE10_AF1 +#define TIM1_CH2_PA9_AF1 +#define TIM1_CH2_PE11_AF1 +#define TIM1_CH3N_PB15_AF1 +#define TIM1_CH3N_PB1_AF1 +#define TIM1_CH3N_PE12_AF1 +#define TIM1_CH3_PA10_AF1 +#define TIM1_CH3_PE13_AF1 +#define TIM1_CH4_PA11_AF1 +#define TIM1_CH4_PE14_AF1 +#define TIM1_ETR_PA12_AF1 +#define TIM1_ETR_PE7_AF1 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH1_PE3_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH2_PE4_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH3_PE5_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PC9_AF2 +#define TIM3_CH4_PE6_AF2 +#define TIM3_ETR_PD2_AF2 +#define TIM3_ETR_PE2_AF2 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH3_PD14_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_CH4_PD15_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH4_PA3_AF2 +#define TIM8_BKIN2_PB6_AF12 +#define TIM8_BKIN2_PC9_AF14 +#define TIM8_BKIN_PA6_AF13 +#define TIM8_BKIN_PB7_AF13 +#define TIM8_CH1N_PA5_AF3 +#define TIM8_CH1N_PA7_AF3 +#define TIM8_CH1_PC6_AF3 +#define TIM8_CH2N_PB0_AF3 +#define TIM8_CH2N_PB14_AF3 +#define TIM8_CH2_PC7_AF3 +#define TIM8_CH3N_PB15_AF3 +#define TIM8_CH3N_PB1_AF3 +#define TIM8_CH3_PC8_AF3 +#define TIM8_CH4_PC9_AF3 +#define TIM8_ETR_PA0_AF3 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) + +#define TIM_MODULE_COUNT (9) + +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD14_CN +#define __PD15_CN +#define __PD2_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN +#define __PE6_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PG10_CN +#define __PG11_CN +#define __PG12_CN +#define __PG9_CN +#define __PH0_CN +#define __PH1_CN +#define __PH3_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_G_CN +#define __PORT_H_CN + +#define PORT_COUNT (7) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32L4P5VG/LQFP100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32L4P5VG/LQFP100/mcu_definitions.h new file mode 100644 index 000000000..06c39e606 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32L4P5VG/LQFP100/mcu_definitions.h @@ -0,0 +1,468 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32L4P5VG_LQFP100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH5 +#define ADC1_PA1_CH6 +#define ADC1_PA2_CH7 +#define ADC1_PA3_CH8 +#define ADC1_PA4_CH9 +#define ADC1_PA5_CH10 +#define ADC1_PA6_CH11 +#define ADC1_PA7_CH12 +#define ADC1_PB0_CH15 +#define ADC1_PB1_CH16 +#define ADC1_PC0_CH1 +#define ADC1_PC1_CH2 +#define ADC1_PC2_CH3 +#define ADC1_PC3_CH4 +#define ADC1_PC4_CH13 +#define ADC1_PC5_CH14 +#define ADC2_PA0_CH5 +#define ADC2_PA1_CH6 +#define ADC2_PA2_CH7 +#define ADC2_PA3_CH8 +#define ADC2_PA4_CH9 +#define ADC2_PA5_CH10 +#define ADC2_PA6_CH11 +#define ADC2_PA7_CH12 +#define ADC2_PB0_CH15 +#define ADC2_PB1_CH16 +#define ADC2_PC0_CH1 +#define ADC2_PC1_CH2 +#define ADC2_PC2_CH3 +#define ADC2_PC3_CH4 +#define ADC2_PC4_CH13 +#define ADC2_PC5_CH14 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// CAN +#define CAN1_RX_PA11_AF9 +#define CAN1_RX_PB8_AF9 +#define CAN1_RX_PD0_AF9 +#define CAN1_TX_PA12_AF9 +#define CAN1_TX_PB9_AF9 +#define CAN1_TX_PD1_AF9 + +#define CAN_MODULE_1 (1) + +#define CAN_MODULE_COUNT (1) + +#define HAL_LL_CAN1_BASE_ADDRESS (0x40006400UL) + +#define HAL_LL_CAN1_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (94) +#define DMA_NUM_OF_CHANNELS_FAMILY (94) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (7) +#define DMA_NUM_OF_STREAMS_FAMILY (7) +// EOF DMA + +// I2C +#define I2C1_SCL_PB6_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PB10_AF4 +#define I2C2_SCL_PB13_AF4 +#define I2C2_SDA_PB11_AF4 +#define I2C2_SDA_PB14_AF4 +#define I2C3_SCL_PA7_AF4 +#define I2C3_SCL_PC0_AF4 +#define I2C3_SDA_PB4_AF4 +#define I2C3_SDA_PC1_AF4 +#define I2C3_SDA_PC9_AF6 +#define I2C4_SCL_PB10_AF3 +#define I2C4_SCL_PB6_AF5 +#define I2C4_SCL_PD12_AF4 +#define I2C4_SDA_PB11_AF3 +#define I2C4_SDA_PB7_AF5 +#define I2C4_SDA_PD13_AF4 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF8 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF8 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PA1_AF8 +#define UART4_RX_PC11_AF8 +#define UART4_TX_PA0_AF8 +#define UART4_TX_PC10_AF8 +#define UART5_RX_PD2_AF8 +#define UART5_TX_PC12_AF8 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART2_RX_PA15_AF3 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PD6_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PD5_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PC5_AF7 +#define USART3_RX_PD9_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PC4_AF7 +#define USART3_TX_PD8_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF5 +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MISO_PE14_AF5 +#define SPI1_MOSI_PA12_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_MOSI_PE15_AF5 +#define SPI1_SCK_PA1_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI1_SCK_PE13_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MISO_PC2_AF5 +#define SPI2_MISO_PD3_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_MOSI_PC1_AF3 +#define SPI2_MOSI_PC3_AF5 +#define SPI2_MOSI_PD4_AF5 +#define SPI2_SCK_PA9_AF3 +#define SPI2_SCK_PB10_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PD1_AF5 +#define SPI2_SCK_PD3_AF3 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_MOSI_PD6_AF5 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF1 +#define LPTIM1_ETR_PC3_AF1 +#define LPTIM2_ETR_PA5_AF14 +#define LPTIM2_ETR_PC3_AF14 +#define LPTIM2_ETR_PD11_AF14 +#define TIM15_BKIN_PA9_AF14 +#define TIM15_BKIN_PB12_AF14 +#define TIM15_CH1N_PA1_AF14 +#define TIM15_CH1N_PB13_AF14 +#define TIM15_CH1_PA2_AF14 +#define TIM15_CH1_PB14_AF14 +#define TIM15_CH2_PA3_AF14 +#define TIM15_CH2_PB15_AF14 +#define TIM16_BKIN_PB5_AF14 +#define TIM16_CH1N_PB6_AF14 +#define TIM16_CH1_PA6_AF14 +#define TIM16_CH1_PB8_AF14 +#define TIM16_CH1_PE0_AF14 +#define TIM17_BKIN_PA10_AF14 +#define TIM17_BKIN_PB4_AF14 +#define TIM17_CH1N_PB7_AF14 +#define TIM17_CH1_PA7_AF14 +#define TIM17_CH1_PB9_AF14 +#define TIM17_CH1_PE1_AF14 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PE14_AF3 +#define TIM1_BKIN_PA6_AF12 +#define TIM1_BKIN_PB12_AF3 +#define TIM1_BKIN_PE15_AF3 +#define TIM1_CH1N_PA7_AF1 +#define TIM1_CH1N_PB13_AF1 +#define TIM1_CH1N_PE8_AF1 +#define TIM1_CH1_PA8_AF1 +#define TIM1_CH1_PE9_AF1 +#define TIM1_CH2N_PB0_AF1 +#define TIM1_CH2N_PB14_AF1 +#define TIM1_CH2N_PE10_AF1 +#define TIM1_CH2_PA9_AF1 +#define TIM1_CH2_PE11_AF1 +#define TIM1_CH3N_PB15_AF1 +#define TIM1_CH3N_PB1_AF1 +#define TIM1_CH3N_PE12_AF1 +#define TIM1_CH3_PA10_AF1 +#define TIM1_CH3_PE13_AF1 +#define TIM1_CH4_PA11_AF1 +#define TIM1_CH4_PE14_AF1 +#define TIM1_ETR_PA12_AF1 +#define TIM1_ETR_PE7_AF1 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH1_PE3_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH2_PE4_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH3_PE5_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PC9_AF2 +#define TIM3_CH4_PE6_AF2 +#define TIM3_ETR_PD2_AF2 +#define TIM3_ETR_PE2_AF2 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH1_PD12_AF2 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH2_PD13_AF2 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH3_PD14_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_CH4_PD15_AF2 +#define TIM4_ETR_PE0_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH4_PA3_AF2 +#define TIM8_BKIN2_PB6_AF12 +#define TIM8_BKIN2_PC9_AF14 +#define TIM8_BKIN_PA6_AF13 +#define TIM8_BKIN_PB7_AF13 +#define TIM8_CH1N_PA5_AF3 +#define TIM8_CH1N_PA7_AF3 +#define TIM8_CH1_PC6_AF3 +#define TIM8_CH2N_PB0_AF3 +#define TIM8_CH2N_PB14_AF3 +#define TIM8_CH2_PC7_AF3 +#define TIM8_CH3N_PB15_AF3 +#define TIM8_CH3N_PB1_AF3 +#define TIM8_CH3_PC8_AF3 +#define TIM8_CH4_PC9_AF3 +#define TIM8_ETR_PA0_AF3 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) + +#define TIM_MODULE_COUNT (9) + +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PE0_CN +#define __PE1_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN +#define __PE6_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PH0_CN +#define __PH1_CN +#define __PH3_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_H_CN + +#define PORT_COUNT (6) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32L4P5VG/WLCSP100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32L4P5VG/WLCSP100/mcu_definitions.h new file mode 100644 index 000000000..ca48effb8 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32L4P5VG/WLCSP100/mcu_definitions.h @@ -0,0 +1,466 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32L4P5VG_WLCSP100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH5 +#define ADC1_PA1_CH6 +#define ADC1_PA2_CH7 +#define ADC1_PA3_CH8 +#define ADC1_PA4_CH9 +#define ADC1_PA5_CH10 +#define ADC1_PA6_CH11 +#define ADC1_PA7_CH12 +#define ADC1_PB0_CH15 +#define ADC1_PB1_CH16 +#define ADC1_PC0_CH1 +#define ADC1_PC1_CH2 +#define ADC1_PC2_CH3 +#define ADC1_PC3_CH4 +#define ADC1_PC4_CH13 +#define ADC1_PC5_CH14 +#define ADC2_PA0_CH5 +#define ADC2_PA1_CH6 +#define ADC2_PA2_CH7 +#define ADC2_PA3_CH8 +#define ADC2_PA4_CH9 +#define ADC2_PA5_CH10 +#define ADC2_PA6_CH11 +#define ADC2_PA7_CH12 +#define ADC2_PB0_CH15 +#define ADC2_PB1_CH16 +#define ADC2_PC0_CH1 +#define ADC2_PC1_CH2 +#define ADC2_PC2_CH3 +#define ADC2_PC3_CH4 +#define ADC2_PC4_CH13 +#define ADC2_PC5_CH14 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// CAN +#define CAN1_RX_PA11_AF9 +#define CAN1_RX_PB8_AF9 +#define CAN1_RX_PD0_AF9 +#define CAN1_TX_PA12_AF9 +#define CAN1_TX_PB9_AF9 +#define CAN1_TX_PD1_AF9 + +#define CAN_MODULE_1 (1) + +#define CAN_MODULE_COUNT (1) + +#define HAL_LL_CAN1_BASE_ADDRESS (0x40006400UL) + +#define HAL_LL_CAN1_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (94) +#define DMA_NUM_OF_CHANNELS_FAMILY (94) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (7) +#define DMA_NUM_OF_STREAMS_FAMILY (7) +// EOF DMA + +// I2C +#define I2C1_SCL_PB6_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PB10_AF4 +#define I2C2_SCL_PB13_AF4 +#define I2C2_SDA_PB11_AF4 +#define I2C2_SDA_PB14_AF4 +#define I2C3_SCL_PA7_AF4 +#define I2C3_SCL_PC0_AF4 +#define I2C3_SDA_PB4_AF4 +#define I2C3_SDA_PC1_AF4 +#define I2C3_SDA_PC9_AF6 +#define I2C4_SCL_PB10_AF3 +#define I2C4_SCL_PB6_AF5 +#define I2C4_SDA_PB11_AF3 +#define I2C4_SDA_PB7_AF5 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF8 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF8 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PA1_AF8 +#define UART4_RX_PC11_AF8 +#define UART4_TX_PA0_AF8 +#define UART4_TX_PC10_AF8 +#define UART5_RX_PD2_AF8 +#define UART5_TX_PC12_AF8 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PG10_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PG9_AF7 +#define USART2_RX_PA15_AF3 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PD6_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PD5_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PC5_AF7 +#define USART3_RX_PD9_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PC4_AF7 +#define USART3_TX_PD8_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF5 +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MISO_PE14_AF5 +#define SPI1_MOSI_PA12_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_MOSI_PE15_AF5 +#define SPI1_SCK_PA1_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI1_SCK_PE13_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MISO_PC2_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_MOSI_PC1_AF3 +#define SPI2_MOSI_PC3_AF5 +#define SPI2_MOSI_PD4_AF5 +#define SPI2_SCK_PA9_AF3 +#define SPI2_SCK_PB10_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PD1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MISO_PG10_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_MOSI_PD6_AF5 +#define SPI3_MOSI_PG11_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 +#define SPI3_SCK_PG9_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF1 +#define LPTIM1_ETR_PC3_AF1 +#define LPTIM1_ETR_PG12_AF1 +#define LPTIM2_ETR_PA5_AF14 +#define LPTIM2_ETR_PC3_AF14 +#define TIM15_BKIN_PA9_AF14 +#define TIM15_BKIN_PB12_AF14 +#define TIM15_CH1N_PA1_AF14 +#define TIM15_CH1N_PB13_AF14 +#define TIM15_CH1N_PG9_AF14 +#define TIM15_CH1_PA2_AF14 +#define TIM15_CH1_PB14_AF14 +#define TIM15_CH1_PG10_AF14 +#define TIM15_CH2_PA3_AF14 +#define TIM15_CH2_PB15_AF14 +#define TIM15_CH2_PG11_AF14 +#define TIM16_BKIN_PB5_AF14 +#define TIM16_CH1N_PB6_AF14 +#define TIM16_CH1_PA6_AF14 +#define TIM16_CH1_PB8_AF14 +#define TIM17_BKIN_PA10_AF14 +#define TIM17_BKIN_PB4_AF14 +#define TIM17_CH1N_PB7_AF14 +#define TIM17_CH1_PA7_AF14 +#define TIM17_CH1_PB9_AF14 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PE14_AF3 +#define TIM1_BKIN_PA6_AF12 +#define TIM1_BKIN_PB12_AF3 +#define TIM1_BKIN_PE15_AF3 +#define TIM1_CH1N_PA7_AF1 +#define TIM1_CH1N_PB13_AF1 +#define TIM1_CH1N_PE8_AF1 +#define TIM1_CH1_PA8_AF1 +#define TIM1_CH1_PE9_AF1 +#define TIM1_CH2N_PB0_AF1 +#define TIM1_CH2N_PB14_AF1 +#define TIM1_CH2N_PE10_AF1 +#define TIM1_CH2_PA9_AF1 +#define TIM1_CH2_PE11_AF1 +#define TIM1_CH3N_PB15_AF1 +#define TIM1_CH3N_PB1_AF1 +#define TIM1_CH3N_PE12_AF1 +#define TIM1_CH3_PA10_AF1 +#define TIM1_CH3_PE13_AF1 +#define TIM1_CH4_PA11_AF1 +#define TIM1_CH4_PE14_AF1 +#define TIM1_ETR_PA12_AF1 +#define TIM1_ETR_PE7_AF1 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH1_PE3_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH2_PE4_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH3_PE5_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PC9_AF2 +#define TIM3_CH4_PE6_AF2 +#define TIM3_ETR_PD2_AF2 +#define TIM3_ETR_PE2_AF2 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH3_PD14_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_CH4_PD15_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH4_PA3_AF2 +#define TIM8_BKIN2_PB6_AF12 +#define TIM8_BKIN2_PC9_AF14 +#define TIM8_BKIN_PA6_AF13 +#define TIM8_BKIN_PB7_AF13 +#define TIM8_CH1N_PA5_AF3 +#define TIM8_CH1N_PA7_AF3 +#define TIM8_CH1_PC6_AF3 +#define TIM8_CH2N_PB0_AF3 +#define TIM8_CH2N_PB14_AF3 +#define TIM8_CH2_PC7_AF3 +#define TIM8_CH3N_PB15_AF3 +#define TIM8_CH3N_PB1_AF3 +#define TIM8_CH3_PC8_AF3 +#define TIM8_CH4_PC9_AF3 +#define TIM8_ETR_PA0_AF3 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) + +#define TIM_MODULE_COUNT (9) + +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD14_CN +#define __PD15_CN +#define __PD2_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN +#define __PE6_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PG10_CN +#define __PG11_CN +#define __PG12_CN +#define __PG9_CN +#define __PH0_CN +#define __PH1_CN +#define __PH3_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_G_CN +#define __PORT_H_CN + +#define PORT_COUNT (7) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32L4P5ZE/LQFP144/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32L4P5ZE/LQFP144/mcu_definitions.h new file mode 100644 index 000000000..cffa9c4e0 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32L4P5ZE/LQFP144/mcu_definitions.h @@ -0,0 +1,531 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32L4P5ZE_LQFP144. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH5 +#define ADC1_PA1_CH6 +#define ADC1_PA2_CH7 +#define ADC1_PA3_CH8 +#define ADC1_PA4_CH9 +#define ADC1_PA5_CH10 +#define ADC1_PA6_CH11 +#define ADC1_PA7_CH12 +#define ADC1_PB0_CH15 +#define ADC1_PB1_CH16 +#define ADC1_PC0_CH1 +#define ADC1_PC1_CH2 +#define ADC1_PC2_CH3 +#define ADC1_PC3_CH4 +#define ADC1_PC4_CH13 +#define ADC1_PC5_CH14 +#define ADC2_PA0_CH5 +#define ADC2_PA1_CH6 +#define ADC2_PA2_CH7 +#define ADC2_PA3_CH8 +#define ADC2_PA4_CH9 +#define ADC2_PA5_CH10 +#define ADC2_PA6_CH11 +#define ADC2_PA7_CH12 +#define ADC2_PB0_CH15 +#define ADC2_PB1_CH16 +#define ADC2_PC0_CH1 +#define ADC2_PC1_CH2 +#define ADC2_PC2_CH3 +#define ADC2_PC3_CH4 +#define ADC2_PC4_CH13 +#define ADC2_PC5_CH14 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// CAN +#define CAN1_RX_PA11_AF9 +#define CAN1_RX_PB8_AF9 +#define CAN1_RX_PD0_AF9 +#define CAN1_TX_PA12_AF9 +#define CAN1_TX_PB9_AF9 +#define CAN1_TX_PD1_AF9 + +#define CAN_MODULE_1 (1) + +#define CAN_MODULE_COUNT (1) + +#define HAL_LL_CAN1_BASE_ADDRESS (0x40006400UL) + +#define HAL_LL_CAN1_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (94) +#define DMA_NUM_OF_CHANNELS_FAMILY (94) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (7) +#define DMA_NUM_OF_STREAMS_FAMILY (7) +// EOF DMA + +// I2C +#define I2C1_SCL_PB6_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SCL_PG14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C1_SDA_PG13_AF4 +#define I2C2_SCL_PB10_AF4 +#define I2C2_SCL_PB13_AF4 +#define I2C2_SCL_PF1_AF4 +#define I2C2_SDA_PB11_AF4 +#define I2C2_SDA_PB14_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA7_AF4 +#define I2C3_SCL_PC0_AF4 +#define I2C3_SCL_PG7_AF4 +#define I2C3_SDA_PB4_AF4 +#define I2C3_SDA_PC1_AF4 +#define I2C3_SDA_PC9_AF6 +#define I2C3_SDA_PG8_AF4 +#define I2C4_SCL_PB10_AF3 +#define I2C4_SCL_PB6_AF5 +#define I2C4_SCL_PD12_AF4 +#define I2C4_SCL_PF14_AF4 +#define I2C4_SDA_PB11_AF3 +#define I2C4_SDA_PB7_AF5 +#define I2C4_SDA_PD13_AF4 +#define I2C4_SDA_PF15_AF4 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF8 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_RX_PG8_AF8 +#define LPUART1_TX_PA2_AF8 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define LPUART1_TX_PG7_AF8 +#define UART4_RX_PA1_AF8 +#define UART4_RX_PC11_AF8 +#define UART4_TX_PA0_AF8 +#define UART4_TX_PC10_AF8 +#define UART5_RX_PD2_AF8 +#define UART5_TX_PC12_AF8 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PG10_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PG9_AF7 +#define USART2_RX_PA15_AF3 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PD6_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PD5_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PC5_AF7 +#define USART3_RX_PD9_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PC4_AF7 +#define USART3_TX_PD8_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF5 +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MISO_PE14_AF5 +#define SPI1_MISO_PG3_AF5 +#define SPI1_MOSI_PA12_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_MOSI_PE15_AF5 +#define SPI1_MOSI_PG4_AF5 +#define SPI1_SCK_PA1_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI1_SCK_PE13_AF5 +#define SPI1_SCK_PG2_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MISO_PC2_AF5 +#define SPI2_MISO_PD3_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_MOSI_PC1_AF3 +#define SPI2_MOSI_PC3_AF5 +#define SPI2_MOSI_PD4_AF5 +#define SPI2_SCK_PA9_AF3 +#define SPI2_SCK_PB10_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PD1_AF5 +#define SPI2_SCK_PD3_AF3 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MISO_PG10_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_MOSI_PD6_AF5 +#define SPI3_MOSI_PG11_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 +#define SPI3_SCK_PG9_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF1 +#define LPTIM1_ETR_PC3_AF1 +#define LPTIM1_ETR_PG12_AF1 +#define LPTIM2_ETR_PA5_AF14 +#define LPTIM2_ETR_PC3_AF14 +#define LPTIM2_ETR_PD11_AF14 +#define TIM15_BKIN_PA9_AF14 +#define TIM15_BKIN_PB12_AF14 +#define TIM15_CH1N_PA1_AF14 +#define TIM15_CH1N_PB13_AF14 +#define TIM15_CH1N_PG9_AF14 +#define TIM15_CH1_PA2_AF14 +#define TIM15_CH1_PB14_AF14 +#define TIM15_CH1_PF9_AF14 +#define TIM15_CH1_PG10_AF14 +#define TIM15_CH2_PA3_AF14 +#define TIM15_CH2_PB15_AF14 +#define TIM15_CH2_PF10_AF14 +#define TIM15_CH2_PG11_AF14 +#define TIM16_BKIN_PB5_AF14 +#define TIM16_CH1N_PB6_AF14 +#define TIM16_CH1_PA6_AF14 +#define TIM16_CH1_PB8_AF14 +#define TIM16_CH1_PE0_AF14 +#define TIM17_BKIN_PA10_AF14 +#define TIM17_BKIN_PB4_AF14 +#define TIM17_CH1N_PB7_AF14 +#define TIM17_CH1_PA7_AF14 +#define TIM17_CH1_PB9_AF14 +#define TIM17_CH1_PE1_AF14 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PE14_AF3 +#define TIM1_BKIN_PA6_AF12 +#define TIM1_BKIN_PB12_AF3 +#define TIM1_BKIN_PE15_AF3 +#define TIM1_CH1N_PA7_AF1 +#define TIM1_CH1N_PB13_AF1 +#define TIM1_CH1N_PE8_AF1 +#define TIM1_CH1_PA8_AF1 +#define TIM1_CH1_PE9_AF1 +#define TIM1_CH2N_PB0_AF1 +#define TIM1_CH2N_PB14_AF1 +#define TIM1_CH2N_PE10_AF1 +#define TIM1_CH2_PA9_AF1 +#define TIM1_CH2_PE11_AF1 +#define TIM1_CH3N_PB15_AF1 +#define TIM1_CH3N_PB1_AF1 +#define TIM1_CH3N_PE12_AF1 +#define TIM1_CH3_PA10_AF1 +#define TIM1_CH3_PE13_AF1 +#define TIM1_CH4_PA11_AF1 +#define TIM1_CH4_PE14_AF1 +#define TIM1_ETR_PA12_AF1 +#define TIM1_ETR_PE7_AF1 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH1_PE3_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH2_PE4_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH3_PE5_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PC9_AF2 +#define TIM3_CH4_PE6_AF2 +#define TIM3_ETR_PD2_AF2 +#define TIM3_ETR_PE2_AF2 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH1_PD12_AF2 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH2_PD13_AF2 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH3_PD14_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_CH4_PD15_AF2 +#define TIM4_ETR_PE0_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH1_PF6_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH2_PF7_AF2 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH3_PF8_AF2 +#define TIM5_CH4_PA3_AF2 +#define TIM5_CH4_PF9_AF2 +#define TIM5_ETR_PF6_AF1 +#define TIM8_BKIN2_PB6_AF12 +#define TIM8_BKIN2_PC9_AF14 +#define TIM8_BKIN_PA6_AF13 +#define TIM8_BKIN_PB7_AF13 +#define TIM8_CH1N_PA5_AF3 +#define TIM8_CH1N_PA7_AF3 +#define TIM8_CH1_PC6_AF3 +#define TIM8_CH2N_PB0_AF3 +#define TIM8_CH2N_PB14_AF3 +#define TIM8_CH2_PC7_AF3 +#define TIM8_CH3N_PB15_AF3 +#define TIM8_CH3N_PB1_AF3 +#define TIM8_CH3_PC8_AF3 +#define TIM8_CH4_PC9_AF3 +#define TIM8_ETR_PA0_AF3 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) + +#define TIM_MODULE_COUNT (9) + +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PE0_CN +#define __PE1_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN +#define __PE6_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PF10_CN +#define __PF11_CN +#define __PF12_CN +#define __PF13_CN +#define __PF14_CN +#define __PF15_CN +#define __PF2_CN +#define __PF3_CN +#define __PF4_CN +#define __PF5_CN +#define __PF6_CN +#define __PF7_CN +#define __PF8_CN +#define __PF9_CN +#define __PG0_CN +#define __PG1_CN +#define __PG10_CN +#define __PG11_CN +#define __PG12_CN +#define __PG13_CN +#define __PG14_CN +#define __PG15_CN +#define __PG2_CN +#define __PG3_CN +#define __PG4_CN +#define __PG5_CN +#define __PG6_CN +#define __PG7_CN +#define __PG8_CN +#define __PG9_CN +#define __PH0_CN +#define __PH1_CN +#define __PH3_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN +#define __PORT_G_CN +#define __PORT_H_CN + +#define PORT_COUNT (8) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32L4P5ZG/LQFP144/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32L4P5ZG/LQFP144/mcu_definitions.h new file mode 100644 index 000000000..35e5eef78 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32L4P5ZG/LQFP144/mcu_definitions.h @@ -0,0 +1,531 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32L4P5ZG_LQFP144. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH5 +#define ADC1_PA1_CH6 +#define ADC1_PA2_CH7 +#define ADC1_PA3_CH8 +#define ADC1_PA4_CH9 +#define ADC1_PA5_CH10 +#define ADC1_PA6_CH11 +#define ADC1_PA7_CH12 +#define ADC1_PB0_CH15 +#define ADC1_PB1_CH16 +#define ADC1_PC0_CH1 +#define ADC1_PC1_CH2 +#define ADC1_PC2_CH3 +#define ADC1_PC3_CH4 +#define ADC1_PC4_CH13 +#define ADC1_PC5_CH14 +#define ADC2_PA0_CH5 +#define ADC2_PA1_CH6 +#define ADC2_PA2_CH7 +#define ADC2_PA3_CH8 +#define ADC2_PA4_CH9 +#define ADC2_PA5_CH10 +#define ADC2_PA6_CH11 +#define ADC2_PA7_CH12 +#define ADC2_PB0_CH15 +#define ADC2_PB1_CH16 +#define ADC2_PC0_CH1 +#define ADC2_PC1_CH2 +#define ADC2_PC2_CH3 +#define ADC2_PC3_CH4 +#define ADC2_PC4_CH13 +#define ADC2_PC5_CH14 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// CAN +#define CAN1_RX_PA11_AF9 +#define CAN1_RX_PB8_AF9 +#define CAN1_RX_PD0_AF9 +#define CAN1_TX_PA12_AF9 +#define CAN1_TX_PB9_AF9 +#define CAN1_TX_PD1_AF9 + +#define CAN_MODULE_1 (1) + +#define CAN_MODULE_COUNT (1) + +#define HAL_LL_CAN1_BASE_ADDRESS (0x40006400UL) + +#define HAL_LL_CAN1_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (94) +#define DMA_NUM_OF_CHANNELS_FAMILY (94) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (7) +#define DMA_NUM_OF_STREAMS_FAMILY (7) +// EOF DMA + +// I2C +#define I2C1_SCL_PB6_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SCL_PG14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C1_SDA_PG13_AF4 +#define I2C2_SCL_PB10_AF4 +#define I2C2_SCL_PB13_AF4 +#define I2C2_SCL_PF1_AF4 +#define I2C2_SDA_PB11_AF4 +#define I2C2_SDA_PB14_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA7_AF4 +#define I2C3_SCL_PC0_AF4 +#define I2C3_SCL_PG7_AF4 +#define I2C3_SDA_PB4_AF4 +#define I2C3_SDA_PC1_AF4 +#define I2C3_SDA_PC9_AF6 +#define I2C3_SDA_PG8_AF4 +#define I2C4_SCL_PB10_AF3 +#define I2C4_SCL_PB6_AF5 +#define I2C4_SCL_PD12_AF4 +#define I2C4_SCL_PF14_AF4 +#define I2C4_SDA_PB11_AF3 +#define I2C4_SDA_PB7_AF5 +#define I2C4_SDA_PD13_AF4 +#define I2C4_SDA_PF15_AF4 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF8 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_RX_PG8_AF8 +#define LPUART1_TX_PA2_AF8 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define LPUART1_TX_PG7_AF8 +#define UART4_RX_PA1_AF8 +#define UART4_RX_PC11_AF8 +#define UART4_TX_PA0_AF8 +#define UART4_TX_PC10_AF8 +#define UART5_RX_PD2_AF8 +#define UART5_TX_PC12_AF8 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PG10_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PG9_AF7 +#define USART2_RX_PA15_AF3 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PD6_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PD5_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PC5_AF7 +#define USART3_RX_PD9_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PC4_AF7 +#define USART3_TX_PD8_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF5 +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MISO_PE14_AF5 +#define SPI1_MISO_PG3_AF5 +#define SPI1_MOSI_PA12_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_MOSI_PE15_AF5 +#define SPI1_MOSI_PG4_AF5 +#define SPI1_SCK_PA1_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI1_SCK_PE13_AF5 +#define SPI1_SCK_PG2_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MISO_PC2_AF5 +#define SPI2_MISO_PD3_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_MOSI_PC1_AF3 +#define SPI2_MOSI_PC3_AF5 +#define SPI2_MOSI_PD4_AF5 +#define SPI2_SCK_PA9_AF3 +#define SPI2_SCK_PB10_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PD1_AF5 +#define SPI2_SCK_PD3_AF3 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MISO_PG10_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_MOSI_PD6_AF5 +#define SPI3_MOSI_PG11_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 +#define SPI3_SCK_PG9_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF1 +#define LPTIM1_ETR_PC3_AF1 +#define LPTIM1_ETR_PG12_AF1 +#define LPTIM2_ETR_PA5_AF14 +#define LPTIM2_ETR_PC3_AF14 +#define LPTIM2_ETR_PD11_AF14 +#define TIM15_BKIN_PA9_AF14 +#define TIM15_BKIN_PB12_AF14 +#define TIM15_CH1N_PA1_AF14 +#define TIM15_CH1N_PB13_AF14 +#define TIM15_CH1N_PG9_AF14 +#define TIM15_CH1_PA2_AF14 +#define TIM15_CH1_PB14_AF14 +#define TIM15_CH1_PF9_AF14 +#define TIM15_CH1_PG10_AF14 +#define TIM15_CH2_PA3_AF14 +#define TIM15_CH2_PB15_AF14 +#define TIM15_CH2_PF10_AF14 +#define TIM15_CH2_PG11_AF14 +#define TIM16_BKIN_PB5_AF14 +#define TIM16_CH1N_PB6_AF14 +#define TIM16_CH1_PA6_AF14 +#define TIM16_CH1_PB8_AF14 +#define TIM16_CH1_PE0_AF14 +#define TIM17_BKIN_PA10_AF14 +#define TIM17_BKIN_PB4_AF14 +#define TIM17_CH1N_PB7_AF14 +#define TIM17_CH1_PA7_AF14 +#define TIM17_CH1_PB9_AF14 +#define TIM17_CH1_PE1_AF14 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PE14_AF3 +#define TIM1_BKIN_PA6_AF12 +#define TIM1_BKIN_PB12_AF3 +#define TIM1_BKIN_PE15_AF3 +#define TIM1_CH1N_PA7_AF1 +#define TIM1_CH1N_PB13_AF1 +#define TIM1_CH1N_PE8_AF1 +#define TIM1_CH1_PA8_AF1 +#define TIM1_CH1_PE9_AF1 +#define TIM1_CH2N_PB0_AF1 +#define TIM1_CH2N_PB14_AF1 +#define TIM1_CH2N_PE10_AF1 +#define TIM1_CH2_PA9_AF1 +#define TIM1_CH2_PE11_AF1 +#define TIM1_CH3N_PB15_AF1 +#define TIM1_CH3N_PB1_AF1 +#define TIM1_CH3N_PE12_AF1 +#define TIM1_CH3_PA10_AF1 +#define TIM1_CH3_PE13_AF1 +#define TIM1_CH4_PA11_AF1 +#define TIM1_CH4_PE14_AF1 +#define TIM1_ETR_PA12_AF1 +#define TIM1_ETR_PE7_AF1 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH1_PE3_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH2_PE4_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH3_PE5_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PC9_AF2 +#define TIM3_CH4_PE6_AF2 +#define TIM3_ETR_PD2_AF2 +#define TIM3_ETR_PE2_AF2 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH1_PD12_AF2 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH2_PD13_AF2 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH3_PD14_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_CH4_PD15_AF2 +#define TIM4_ETR_PE0_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH1_PF6_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH2_PF7_AF2 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH3_PF8_AF2 +#define TIM5_CH4_PA3_AF2 +#define TIM5_CH4_PF9_AF2 +#define TIM5_ETR_PF6_AF1 +#define TIM8_BKIN2_PB6_AF12 +#define TIM8_BKIN2_PC9_AF14 +#define TIM8_BKIN_PA6_AF13 +#define TIM8_BKIN_PB7_AF13 +#define TIM8_CH1N_PA5_AF3 +#define TIM8_CH1N_PA7_AF3 +#define TIM8_CH1_PC6_AF3 +#define TIM8_CH2N_PB0_AF3 +#define TIM8_CH2N_PB14_AF3 +#define TIM8_CH2_PC7_AF3 +#define TIM8_CH3N_PB15_AF3 +#define TIM8_CH3N_PB1_AF3 +#define TIM8_CH3_PC8_AF3 +#define TIM8_CH4_PC9_AF3 +#define TIM8_ETR_PA0_AF3 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) + +#define TIM_MODULE_COUNT (9) + +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PE0_CN +#define __PE1_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN +#define __PE6_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PF10_CN +#define __PF11_CN +#define __PF12_CN +#define __PF13_CN +#define __PF14_CN +#define __PF15_CN +#define __PF2_CN +#define __PF3_CN +#define __PF4_CN +#define __PF5_CN +#define __PF6_CN +#define __PF7_CN +#define __PF8_CN +#define __PF9_CN +#define __PG0_CN +#define __PG1_CN +#define __PG10_CN +#define __PG11_CN +#define __PG12_CN +#define __PG13_CN +#define __PG14_CN +#define __PG15_CN +#define __PG2_CN +#define __PG3_CN +#define __PG4_CN +#define __PG5_CN +#define __PG6_CN +#define __PG7_CN +#define __PG8_CN +#define __PG9_CN +#define __PH0_CN +#define __PH1_CN +#define __PH3_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN +#define __PORT_G_CN +#define __PORT_H_CN + +#define PORT_COUNT (8) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32L4Q5AG/UFBGA169/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32L4Q5AG/UFBGA169/mcu_definitions.h new file mode 100644 index 000000000..5d3d25b6d --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32L4Q5AG/UFBGA169/mcu_definitions.h @@ -0,0 +1,569 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32L4Q5AG_UFBGA169. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH5 +#define ADC1_PA1_CH6 +#define ADC1_PA2_CH7 +#define ADC1_PA3_CH8 +#define ADC1_PA4_CH9 +#define ADC1_PA5_CH10 +#define ADC1_PA6_CH11 +#define ADC1_PA7_CH12 +#define ADC1_PB0_CH15 +#define ADC1_PB1_CH16 +#define ADC1_PC0_CH1 +#define ADC1_PC1_CH2 +#define ADC1_PC2_CH3 +#define ADC1_PC3_CH4 +#define ADC1_PC4_CH13 +#define ADC1_PC5_CH14 +#define ADC2_PA0_CH5 +#define ADC2_PA1_CH6 +#define ADC2_PA2_CH7 +#define ADC2_PA3_CH8 +#define ADC2_PA4_CH9 +#define ADC2_PA5_CH10 +#define ADC2_PA6_CH11 +#define ADC2_PA7_CH12 +#define ADC2_PB0_CH15 +#define ADC2_PB1_CH16 +#define ADC2_PC0_CH1 +#define ADC2_PC1_CH2 +#define ADC2_PC2_CH3 +#define ADC2_PC3_CH4 +#define ADC2_PC4_CH13 +#define ADC2_PC5_CH14 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// CAN +#define CAN1_RX_PA11_AF9 +#define CAN1_RX_PB8_AF9 +#define CAN1_RX_PD0_AF9 +#define CAN1_RX_PI9_AF9 +#define CAN1_TX_PA12_AF9 +#define CAN1_TX_PB9_AF9 +#define CAN1_TX_PD1_AF9 +#define CAN1_TX_PH13_AF9 + +#define CAN_MODULE_1 (1) + +#define CAN_MODULE_COUNT (1) + +#define HAL_LL_CAN1_BASE_ADDRESS (0x40006400UL) + +#define HAL_LL_CAN1_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (94) +#define DMA_NUM_OF_CHANNELS_FAMILY (94) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (7) +#define DMA_NUM_OF_STREAMS_FAMILY (7) +// EOF DMA + +// I2C +#define I2C1_SCL_PB6_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SCL_PG14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C1_SDA_PG13_AF4 +#define I2C2_SCL_PB10_AF4 +#define I2C2_SCL_PB13_AF4 +#define I2C2_SCL_PF1_AF4 +#define I2C2_SCL_PH4_AF4 +#define I2C2_SDA_PB11_AF4 +#define I2C2_SDA_PB14_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C2_SDA_PH5_AF4 +#define I2C3_SCL_PA7_AF4 +#define I2C3_SCL_PC0_AF4 +#define I2C3_SCL_PG7_AF4 +#define I2C3_SCL_PH7_AF4 +#define I2C3_SDA_PB4_AF4 +#define I2C3_SDA_PC1_AF4 +#define I2C3_SDA_PC9_AF6 +#define I2C3_SDA_PG8_AF4 +#define I2C3_SDA_PH8_AF4 +#define I2C4_SCL_PB10_AF3 +#define I2C4_SCL_PB6_AF5 +#define I2C4_SCL_PD12_AF4 +#define I2C4_SCL_PF14_AF4 +#define I2C4_SDA_PB11_AF3 +#define I2C4_SDA_PB7_AF5 +#define I2C4_SDA_PD13_AF4 +#define I2C4_SDA_PF15_AF4 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF8 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_RX_PG8_AF8 +#define LPUART1_TX_PA2_AF8 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define LPUART1_TX_PG7_AF8 +#define UART4_RX_PA1_AF8 +#define UART4_RX_PC11_AF8 +#define UART4_TX_PA0_AF8 +#define UART4_TX_PC10_AF8 +#define UART5_RX_PD2_AF8 +#define UART5_TX_PC12_AF8 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PG10_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PG9_AF7 +#define USART2_RX_PA15_AF3 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PD6_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PD5_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PC5_AF7 +#define USART3_RX_PD9_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PC4_AF7 +#define USART3_TX_PD8_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF5 +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MISO_PE14_AF5 +#define SPI1_MISO_PG3_AF5 +#define SPI1_MOSI_PA12_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_MOSI_PE15_AF5 +#define SPI1_MOSI_PG4_AF5 +#define SPI1_SCK_PA1_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI1_SCK_PE13_AF5 +#define SPI1_SCK_PG2_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MISO_PC2_AF5 +#define SPI2_MISO_PD3_AF5 +#define SPI2_MISO_PI2_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_MOSI_PC1_AF3 +#define SPI2_MOSI_PC3_AF5 +#define SPI2_MOSI_PD4_AF5 +#define SPI2_MOSI_PI3_AF5 +#define SPI2_SCK_PA9_AF3 +#define SPI2_SCK_PB10_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PD1_AF5 +#define SPI2_SCK_PD3_AF3 +#define SPI2_SCK_PI1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MISO_PG10_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_MOSI_PD6_AF5 +#define SPI3_MOSI_PG11_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 +#define SPI3_SCK_PG9_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF1 +#define LPTIM1_ETR_PC3_AF1 +#define LPTIM1_ETR_PG12_AF1 +#define LPTIM2_ETR_PA5_AF14 +#define LPTIM2_ETR_PC3_AF14 +#define LPTIM2_ETR_PD11_AF14 +#define TIM15_BKIN_PA9_AF14 +#define TIM15_BKIN_PB12_AF14 +#define TIM15_CH1N_PA1_AF14 +#define TIM15_CH1N_PB13_AF14 +#define TIM15_CH1N_PG9_AF14 +#define TIM15_CH1_PA2_AF14 +#define TIM15_CH1_PB14_AF14 +#define TIM15_CH1_PG10_AF14 +#define TIM15_CH2_PA3_AF14 +#define TIM15_CH2_PB15_AF14 +#define TIM15_CH2_PF10_AF14 +#define TIM15_CH2_PG11_AF14 +#define TIM16_BKIN_PB5_AF14 +#define TIM16_CH1N_PB6_AF14 +#define TIM16_CH1_PA6_AF14 +#define TIM16_CH1_PB8_AF14 +#define TIM16_CH1_PE0_AF14 +#define TIM17_BKIN_PA10_AF14 +#define TIM17_BKIN_PB4_AF14 +#define TIM17_CH1N_PB7_AF14 +#define TIM17_CH1_PA7_AF14 +#define TIM17_CH1_PB9_AF14 +#define TIM17_CH1_PE1_AF14 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PE14_AF3 +#define TIM1_BKIN_PA6_AF12 +#define TIM1_BKIN_PB12_AF3 +#define TIM1_BKIN_PE15_AF3 +#define TIM1_CH1N_PA7_AF1 +#define TIM1_CH1N_PB13_AF1 +#define TIM1_CH1N_PE8_AF1 +#define TIM1_CH1_PA8_AF1 +#define TIM1_CH1_PE9_AF1 +#define TIM1_CH2N_PB0_AF1 +#define TIM1_CH2N_PB14_AF1 +#define TIM1_CH2N_PE10_AF1 +#define TIM1_CH2_PA9_AF1 +#define TIM1_CH2_PE11_AF1 +#define TIM1_CH3N_PB15_AF1 +#define TIM1_CH3N_PB1_AF1 +#define TIM1_CH3N_PE12_AF1 +#define TIM1_CH3_PA10_AF1 +#define TIM1_CH3_PE13_AF1 +#define TIM1_CH4_PA11_AF1 +#define TIM1_CH4_PE14_AF1 +#define TIM1_ETR_PA12_AF1 +#define TIM1_ETR_PE7_AF1 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH1_PE3_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH2_PE4_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH3_PE5_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PC9_AF2 +#define TIM3_CH4_PE6_AF2 +#define TIM3_ETR_PD2_AF2 +#define TIM3_ETR_PE2_AF2 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH1_PD12_AF2 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH2_PD13_AF2 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH3_PD14_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_CH4_PD15_AF2 +#define TIM4_ETR_PE0_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH1_PH10_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH2_PH11_AF2 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH3_PH12_AF2 +#define TIM5_CH4_PA3_AF2 +#define TIM5_CH4_PI0_AF2 +#define TIM8_BKIN2_PB6_AF12 +#define TIM8_BKIN2_PC9_AF14 +#define TIM8_BKIN_PA6_AF13 +#define TIM8_BKIN_PB7_AF13 +#define TIM8_BKIN_PI4_AF3 +#define TIM8_CH1N_PA5_AF3 +#define TIM8_CH1N_PA7_AF3 +#define TIM8_CH1N_PH13_AF3 +#define TIM8_CH1_PC6_AF3 +#define TIM8_CH1_PI5_AF3 +#define TIM8_CH2N_PB0_AF3 +#define TIM8_CH2N_PB14_AF3 +#define TIM8_CH2N_PH14_AF3 +#define TIM8_CH2_PC7_AF3 +#define TIM8_CH2_PI6_AF3 +#define TIM8_CH3N_PB15_AF3 +#define TIM8_CH3N_PB1_AF3 +#define TIM8_CH3N_PH15_AF3 +#define TIM8_CH3_PC8_AF3 +#define TIM8_CH3_PI7_AF3 +#define TIM8_CH4_PC9_AF3 +#define TIM8_CH4_PI2_AF3 +#define TIM8_ETR_PA0_AF3 +#define TIM8_ETR_PI3_AF3 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) + +#define TIM_MODULE_COUNT (9) + +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PE0_CN +#define __PE1_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN +#define __PE6_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PF10_CN +#define __PF11_CN +#define __PF12_CN +#define __PF13_CN +#define __PF14_CN +#define __PF15_CN +#define __PF2_CN +#define __PF3_CN +#define __PF4_CN +#define __PF5_CN +#define __PG0_CN +#define __PG1_CN +#define __PG10_CN +#define __PG11_CN +#define __PG12_CN +#define __PG13_CN +#define __PG14_CN +#define __PG15_CN +#define __PG2_CN +#define __PG3_CN +#define __PG4_CN +#define __PG5_CN +#define __PG6_CN +#define __PG7_CN +#define __PG8_CN +#define __PG9_CN +#define __PH0_CN +#define __PH1_CN +#define __PH10_CN +#define __PH11_CN +#define __PH12_CN +#define __PH13_CN +#define __PH14_CN +#define __PH15_CN +#define __PH2_CN +#define __PH3_CN +#define __PH4_CN +#define __PH5_CN +#define __PH6_CN +#define __PH7_CN +#define __PH8_CN +#define __PH9_CN +#define __PI0_CN +#define __PI1_CN +#define __PI10_CN +#define __PI11_CN +#define __PI2_CN +#define __PI3_CN +#define __PI4_CN +#define __PI5_CN +#define __PI6_CN +#define __PI7_CN +#define __PI8_CN +#define __PI9_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN +#define __PORT_G_CN +#define __PORT_H_CN +#define __PORT_I_CN + +#define PORT_COUNT (9) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32L4Q5CG/LQFP48/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32L4Q5CG/LQFP48/mcu_definitions.h new file mode 100644 index 000000000..aee13825c --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32L4Q5CG/LQFP48/mcu_definitions.h @@ -0,0 +1,336 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32L4Q5CG_LQFP48. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH5 +#define ADC1_PA1_CH6 +#define ADC1_PA2_CH7 +#define ADC1_PA3_CH8 +#define ADC1_PA4_CH9 +#define ADC1_PA5_CH10 +#define ADC1_PA6_CH11 +#define ADC1_PA7_CH12 +#define ADC1_PB0_CH15 +#define ADC1_PB1_CH16 +#define ADC2_PA0_CH5 +#define ADC2_PA1_CH6 +#define ADC2_PA2_CH7 +#define ADC2_PA3_CH8 +#define ADC2_PA4_CH9 +#define ADC2_PA5_CH10 +#define ADC2_PA6_CH11 +#define ADC2_PA7_CH12 +#define ADC2_PB0_CH15 +#define ADC2_PB1_CH16 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// CAN +#define CAN1_RX_PA11_AF9 +#define CAN1_RX_PB8_AF9 +#define CAN1_TX_PA12_AF9 +#define CAN1_TX_PB9_AF9 + +#define CAN_MODULE_1 (1) + +#define CAN_MODULE_COUNT (1) + +#define HAL_LL_CAN1_BASE_ADDRESS (0x40006400UL) + +#define HAL_LL_CAN1_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (94) +#define DMA_NUM_OF_CHANNELS_FAMILY (94) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (7) +#define DMA_NUM_OF_STREAMS_FAMILY (7) +// EOF DMA + +// I2C +#define I2C1_SCL_PB6_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PB10_AF4 +#define I2C2_SCL_PB13_AF4 +#define I2C2_SDA_PB11_AF4 +#define I2C2_SDA_PB14_AF4 +#define I2C3_SCL_PA7_AF4 +#define I2C3_SDA_PB4_AF4 +#define I2C4_SCL_PB10_AF3 +#define I2C4_SCL_PB6_AF5 +#define I2C4_SDA_PB11_AF3 +#define I2C4_SDA_PB7_AF5 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF8 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_TX_PA2_AF8 +#define LPUART1_TX_PB11_AF8 +#define UART4_RX_PA1_AF8 +#define UART4_TX_PA0_AF8 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART2_RX_PA15_AF3 +#define USART2_RX_PA3_AF7 +#define USART2_TX_PA2_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_TX_PB10_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (4) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF5 +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA12_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA1_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PA9_AF3 +#define SPI2_SCK_PB10_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_SCK_PB3_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF1 +#define LPTIM2_ETR_PA5_AF14 +#define TIM15_BKIN_PA9_AF14 +#define TIM15_BKIN_PB12_AF14 +#define TIM15_CH1N_PA1_AF14 +#define TIM15_CH1N_PB13_AF14 +#define TIM15_CH1_PA2_AF14 +#define TIM15_CH1_PB14_AF14 +#define TIM15_CH2_PA3_AF14 +#define TIM15_CH2_PB15_AF14 +#define TIM16_BKIN_PB5_AF14 +#define TIM16_CH1N_PB6_AF14 +#define TIM16_CH1_PA6_AF14 +#define TIM16_CH1_PB8_AF14 +#define TIM17_BKIN_PA10_AF14 +#define TIM17_BKIN_PB4_AF14 +#define TIM17_CH1N_PB7_AF14 +#define TIM17_CH1_PA7_AF14 +#define TIM17_CH1_PB9_AF14 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN_PA6_AF12 +#define TIM1_BKIN_PB12_AF3 +#define TIM1_CH1N_PA7_AF1 +#define TIM1_CH1N_PB13_AF1 +#define TIM1_CH1_PA8_AF1 +#define TIM1_CH2N_PB0_AF1 +#define TIM1_CH2N_PB14_AF1 +#define TIM1_CH2_PA9_AF1 +#define TIM1_CH3N_PB15_AF1 +#define TIM1_CH3N_PB1_AF1 +#define TIM1_CH3_PA10_AF1 +#define TIM1_CH4_PA11_AF1 +#define TIM1_ETR_PA12_AF1 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH4_PA3_AF2 +#define TIM8_BKIN2_PB6_AF12 +#define TIM8_BKIN_PA6_AF13 +#define TIM8_BKIN_PB7_AF13 +#define TIM8_CH1N_PA5_AF3 +#define TIM8_CH1N_PA7_AF3 +#define TIM8_CH2N_PB0_AF3 +#define TIM8_CH2N_PB14_AF3 +#define TIM8_CH3N_PB15_AF3 +#define TIM8_CH3N_PB1_AF3 +#define TIM8_ETR_PA0_AF3 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) + +#define TIM_MODULE_COUNT (9) + +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PH0_CN +#define __PH1_CN +#define __PH3_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_H_CN + +#define PORT_COUNT (4) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32L4Q5CG/UFQFPN48/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32L4Q5CG/UFQFPN48/mcu_definitions.h new file mode 100644 index 000000000..51ca1a2e2 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32L4Q5CG/UFQFPN48/mcu_definitions.h @@ -0,0 +1,336 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32L4Q5CG_UFQFPN48. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH5 +#define ADC1_PA1_CH6 +#define ADC1_PA2_CH7 +#define ADC1_PA3_CH8 +#define ADC1_PA4_CH9 +#define ADC1_PA5_CH10 +#define ADC1_PA6_CH11 +#define ADC1_PA7_CH12 +#define ADC1_PB0_CH15 +#define ADC1_PB1_CH16 +#define ADC2_PA0_CH5 +#define ADC2_PA1_CH6 +#define ADC2_PA2_CH7 +#define ADC2_PA3_CH8 +#define ADC2_PA4_CH9 +#define ADC2_PA5_CH10 +#define ADC2_PA6_CH11 +#define ADC2_PA7_CH12 +#define ADC2_PB0_CH15 +#define ADC2_PB1_CH16 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// CAN +#define CAN1_RX_PA11_AF9 +#define CAN1_RX_PB8_AF9 +#define CAN1_TX_PA12_AF9 +#define CAN1_TX_PB9_AF9 + +#define CAN_MODULE_1 (1) + +#define CAN_MODULE_COUNT (1) + +#define HAL_LL_CAN1_BASE_ADDRESS (0x40006400UL) + +#define HAL_LL_CAN1_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (94) +#define DMA_NUM_OF_CHANNELS_FAMILY (94) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (7) +#define DMA_NUM_OF_STREAMS_FAMILY (7) +// EOF DMA + +// I2C +#define I2C1_SCL_PB6_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PB10_AF4 +#define I2C2_SCL_PB13_AF4 +#define I2C2_SDA_PB11_AF4 +#define I2C2_SDA_PB14_AF4 +#define I2C3_SCL_PA7_AF4 +#define I2C3_SDA_PB4_AF4 +#define I2C4_SCL_PB10_AF3 +#define I2C4_SCL_PB6_AF5 +#define I2C4_SDA_PB11_AF3 +#define I2C4_SDA_PB7_AF5 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF8 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_TX_PA2_AF8 +#define LPUART1_TX_PB11_AF8 +#define UART4_RX_PA1_AF8 +#define UART4_TX_PA0_AF8 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART2_RX_PA15_AF3 +#define USART2_RX_PA3_AF7 +#define USART2_TX_PA2_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_TX_PB10_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (4) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF5 +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA12_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA1_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_SCK_PA9_AF3 +#define SPI2_SCK_PB10_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_SCK_PB3_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF1 +#define LPTIM2_ETR_PA5_AF14 +#define TIM15_BKIN_PA9_AF14 +#define TIM15_BKIN_PB12_AF14 +#define TIM15_CH1N_PA1_AF14 +#define TIM15_CH1N_PB13_AF14 +#define TIM15_CH1_PA2_AF14 +#define TIM15_CH1_PB14_AF14 +#define TIM15_CH2_PA3_AF14 +#define TIM15_CH2_PB15_AF14 +#define TIM16_BKIN_PB5_AF14 +#define TIM16_CH1N_PB6_AF14 +#define TIM16_CH1_PA6_AF14 +#define TIM16_CH1_PB8_AF14 +#define TIM17_BKIN_PA10_AF14 +#define TIM17_BKIN_PB4_AF14 +#define TIM17_CH1N_PB7_AF14 +#define TIM17_CH1_PA7_AF14 +#define TIM17_CH1_PB9_AF14 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN_PA6_AF12 +#define TIM1_BKIN_PB12_AF3 +#define TIM1_CH1N_PA7_AF1 +#define TIM1_CH1N_PB13_AF1 +#define TIM1_CH1_PA8_AF1 +#define TIM1_CH2N_PB0_AF1 +#define TIM1_CH2N_PB14_AF1 +#define TIM1_CH2_PA9_AF1 +#define TIM1_CH3N_PB15_AF1 +#define TIM1_CH3N_PB1_AF1 +#define TIM1_CH3_PA10_AF1 +#define TIM1_CH4_PA11_AF1 +#define TIM1_ETR_PA12_AF1 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH4_PA3_AF2 +#define TIM8_BKIN2_PB6_AF12 +#define TIM8_BKIN_PA6_AF13 +#define TIM8_BKIN_PB7_AF13 +#define TIM8_CH1N_PA5_AF3 +#define TIM8_CH1N_PA7_AF3 +#define TIM8_CH2N_PB0_AF3 +#define TIM8_CH2N_PB14_AF3 +#define TIM8_CH3N_PB15_AF3 +#define TIM8_CH3N_PB1_AF3 +#define TIM8_ETR_PA0_AF3 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) + +#define TIM_MODULE_COUNT (9) + +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PH0_CN +#define __PH1_CN +#define __PH3_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_H_CN + +#define PORT_COUNT (4) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32L4Q5QG/UFBGA132/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32L4Q5QG/UFBGA132/mcu_definitions.h new file mode 100644 index 000000000..c99965a93 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32L4Q5QG/UFBGA132/mcu_definitions.h @@ -0,0 +1,519 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32L4Q5QG_UFBGA132. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH5 +#define ADC1_PA1_CH6 +#define ADC1_PA2_CH7 +#define ADC1_PA3_CH8 +#define ADC1_PA4_CH9 +#define ADC1_PA5_CH10 +#define ADC1_PA6_CH11 +#define ADC1_PA7_CH12 +#define ADC1_PB0_CH15 +#define ADC1_PB1_CH16 +#define ADC1_PC0_CH1 +#define ADC1_PC1_CH2 +#define ADC1_PC2_CH3 +#define ADC1_PC3_CH4 +#define ADC1_PC4_CH13 +#define ADC1_PC5_CH14 +#define ADC2_PA0_CH5 +#define ADC2_PA1_CH6 +#define ADC2_PA2_CH7 +#define ADC2_PA3_CH8 +#define ADC2_PA4_CH9 +#define ADC2_PA5_CH10 +#define ADC2_PA6_CH11 +#define ADC2_PA7_CH12 +#define ADC2_PB0_CH15 +#define ADC2_PB1_CH16 +#define ADC2_PC0_CH1 +#define ADC2_PC1_CH2 +#define ADC2_PC2_CH3 +#define ADC2_PC3_CH4 +#define ADC2_PC4_CH13 +#define ADC2_PC5_CH14 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// CAN +#define CAN1_RX_PA11_AF9 +#define CAN1_RX_PB8_AF9 +#define CAN1_RX_PD0_AF9 +#define CAN1_TX_PA12_AF9 +#define CAN1_TX_PB9_AF9 +#define CAN1_TX_PD1_AF9 + +#define CAN_MODULE_1 (1) + +#define CAN_MODULE_COUNT (1) + +#define HAL_LL_CAN1_BASE_ADDRESS (0x40006400UL) + +#define HAL_LL_CAN1_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (94) +#define DMA_NUM_OF_CHANNELS_FAMILY (94) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (7) +#define DMA_NUM_OF_STREAMS_FAMILY (7) +// EOF DMA + +// I2C +#define I2C1_SCL_PB6_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SCL_PG14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C1_SDA_PG13_AF4 +#define I2C2_SCL_PB10_AF4 +#define I2C2_SCL_PB13_AF4 +#define I2C2_SCL_PF1_AF4 +#define I2C2_SDA_PB11_AF4 +#define I2C2_SDA_PB14_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA7_AF4 +#define I2C3_SCL_PC0_AF4 +#define I2C3_SCL_PG7_AF4 +#define I2C3_SDA_PB4_AF4 +#define I2C3_SDA_PC1_AF4 +#define I2C3_SDA_PC9_AF6 +#define I2C3_SDA_PG8_AF4 +#define I2C4_SCL_PB10_AF3 +#define I2C4_SCL_PB6_AF5 +#define I2C4_SCL_PD12_AF4 +#define I2C4_SCL_PF14_AF4 +#define I2C4_SDA_PB11_AF3 +#define I2C4_SDA_PB7_AF5 +#define I2C4_SDA_PD13_AF4 +#define I2C4_SDA_PF15_AF4 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF8 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_RX_PG8_AF8 +#define LPUART1_TX_PA2_AF8 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define LPUART1_TX_PG7_AF8 +#define UART4_RX_PA1_AF8 +#define UART4_RX_PC11_AF8 +#define UART4_TX_PA0_AF8 +#define UART4_TX_PC10_AF8 +#define UART5_RX_PD2_AF8 +#define UART5_TX_PC12_AF8 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PG10_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PG9_AF7 +#define USART2_RX_PA15_AF3 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PD6_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PD5_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PC5_AF7 +#define USART3_RX_PD9_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PC4_AF7 +#define USART3_TX_PD8_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF5 +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MISO_PE14_AF5 +#define SPI1_MISO_PG3_AF5 +#define SPI1_MOSI_PA12_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_MOSI_PE15_AF5 +#define SPI1_MOSI_PG4_AF5 +#define SPI1_SCK_PA1_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI1_SCK_PE13_AF5 +#define SPI1_SCK_PG2_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MISO_PC2_AF5 +#define SPI2_MISO_PD3_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_MOSI_PC1_AF3 +#define SPI2_MOSI_PC3_AF5 +#define SPI2_MOSI_PD4_AF5 +#define SPI2_SCK_PA9_AF3 +#define SPI2_SCK_PB10_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PD1_AF5 +#define SPI2_SCK_PD3_AF3 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MISO_PG10_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_MOSI_PD6_AF5 +#define SPI3_MOSI_PG11_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 +#define SPI3_SCK_PG9_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF1 +#define LPTIM1_ETR_PC3_AF1 +#define LPTIM1_ETR_PG12_AF1 +#define LPTIM2_ETR_PA5_AF14 +#define LPTIM2_ETR_PC3_AF14 +#define LPTIM2_ETR_PD11_AF14 +#define TIM15_BKIN_PA9_AF14 +#define TIM15_BKIN_PB12_AF14 +#define TIM15_CH1N_PA1_AF14 +#define TIM15_CH1N_PB13_AF14 +#define TIM15_CH1N_PG9_AF14 +#define TIM15_CH1_PA2_AF14 +#define TIM15_CH1_PB14_AF14 +#define TIM15_CH1_PG10_AF14 +#define TIM15_CH2_PA3_AF14 +#define TIM15_CH2_PB15_AF14 +#define TIM15_CH2_PG11_AF14 +#define TIM16_BKIN_PB5_AF14 +#define TIM16_CH1N_PB6_AF14 +#define TIM16_CH1_PA6_AF14 +#define TIM16_CH1_PB8_AF14 +#define TIM16_CH1_PE0_AF14 +#define TIM17_BKIN_PA10_AF14 +#define TIM17_BKIN_PB4_AF14 +#define TIM17_CH1N_PB7_AF14 +#define TIM17_CH1_PA7_AF14 +#define TIM17_CH1_PB9_AF14 +#define TIM17_CH1_PE1_AF14 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PE14_AF3 +#define TIM1_BKIN_PA6_AF12 +#define TIM1_BKIN_PB12_AF3 +#define TIM1_BKIN_PE15_AF3 +#define TIM1_CH1N_PA7_AF1 +#define TIM1_CH1N_PB13_AF1 +#define TIM1_CH1N_PE8_AF1 +#define TIM1_CH1_PA8_AF1 +#define TIM1_CH1_PE9_AF1 +#define TIM1_CH2N_PB0_AF1 +#define TIM1_CH2N_PB14_AF1 +#define TIM1_CH2N_PE10_AF1 +#define TIM1_CH2_PA9_AF1 +#define TIM1_CH2_PE11_AF1 +#define TIM1_CH3N_PB15_AF1 +#define TIM1_CH3N_PB1_AF1 +#define TIM1_CH3N_PE12_AF1 +#define TIM1_CH3_PA10_AF1 +#define TIM1_CH3_PE13_AF1 +#define TIM1_CH4_PA11_AF1 +#define TIM1_CH4_PE14_AF1 +#define TIM1_ETR_PA12_AF1 +#define TIM1_ETR_PE7_AF1 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH1_PE3_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH2_PE4_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH3_PE5_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PC9_AF2 +#define TIM3_CH4_PE6_AF2 +#define TIM3_ETR_PD2_AF2 +#define TIM3_ETR_PE2_AF2 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH1_PD12_AF2 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH2_PD13_AF2 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH3_PD14_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_CH4_PD15_AF2 +#define TIM4_ETR_PE0_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH4_PA3_AF2 +#define TIM8_BKIN2_PB6_AF12 +#define TIM8_BKIN2_PC9_AF14 +#define TIM8_BKIN_PA6_AF13 +#define TIM8_BKIN_PB7_AF13 +#define TIM8_CH1N_PA5_AF3 +#define TIM8_CH1N_PA7_AF3 +#define TIM8_CH1_PC6_AF3 +#define TIM8_CH2N_PB0_AF3 +#define TIM8_CH2N_PB14_AF3 +#define TIM8_CH2_PC7_AF3 +#define TIM8_CH3N_PB15_AF3 +#define TIM8_CH3N_PB1_AF3 +#define TIM8_CH3_PC8_AF3 +#define TIM8_CH4_PC9_AF3 +#define TIM8_ETR_PA0_AF3 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) + +#define TIM_MODULE_COUNT (9) + +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PE0_CN +#define __PE1_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN +#define __PE6_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PF11_CN +#define __PF12_CN +#define __PF13_CN +#define __PF14_CN +#define __PF15_CN +#define __PF2_CN +#define __PF3_CN +#define __PF4_CN +#define __PF5_CN +#define __PG0_CN +#define __PG1_CN +#define __PG10_CN +#define __PG11_CN +#define __PG12_CN +#define __PG13_CN +#define __PG14_CN +#define __PG15_CN +#define __PG2_CN +#define __PG3_CN +#define __PG4_CN +#define __PG5_CN +#define __PG6_CN +#define __PG7_CN +#define __PG8_CN +#define __PG9_CN +#define __PH0_CN +#define __PH1_CN +#define __PH3_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN +#define __PORT_G_CN +#define __PORT_H_CN + +#define PORT_COUNT (8) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32L4Q5RG/LQFP64/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32L4Q5RG/LQFP64/mcu_definitions.h new file mode 100644 index 000000000..e692e309d --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32L4Q5RG/LQFP64/mcu_definitions.h @@ -0,0 +1,392 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32L4Q5RG_LQFP64. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH5 +#define ADC1_PA1_CH6 +#define ADC1_PA2_CH7 +#define ADC1_PA3_CH8 +#define ADC1_PA4_CH9 +#define ADC1_PA5_CH10 +#define ADC1_PA6_CH11 +#define ADC1_PA7_CH12 +#define ADC1_PB0_CH15 +#define ADC1_PB1_CH16 +#define ADC1_PC0_CH1 +#define ADC1_PC1_CH2 +#define ADC1_PC2_CH3 +#define ADC1_PC3_CH4 +#define ADC1_PC4_CH13 +#define ADC1_PC5_CH14 +#define ADC2_PA0_CH5 +#define ADC2_PA1_CH6 +#define ADC2_PA2_CH7 +#define ADC2_PA3_CH8 +#define ADC2_PA4_CH9 +#define ADC2_PA5_CH10 +#define ADC2_PA6_CH11 +#define ADC2_PA7_CH12 +#define ADC2_PB0_CH15 +#define ADC2_PB1_CH16 +#define ADC2_PC0_CH1 +#define ADC2_PC1_CH2 +#define ADC2_PC2_CH3 +#define ADC2_PC3_CH4 +#define ADC2_PC4_CH13 +#define ADC2_PC5_CH14 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// CAN +#define CAN1_RX_PA11_AF9 +#define CAN1_RX_PB8_AF9 +#define CAN1_TX_PA12_AF9 +#define CAN1_TX_PB9_AF9 + +#define CAN_MODULE_1 (1) + +#define CAN_MODULE_COUNT (1) + +#define HAL_LL_CAN1_BASE_ADDRESS (0x40006400UL) + +#define HAL_LL_CAN1_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (94) +#define DMA_NUM_OF_CHANNELS_FAMILY (94) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (7) +#define DMA_NUM_OF_STREAMS_FAMILY (7) +// EOF DMA + +// I2C +#define I2C1_SCL_PB6_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PB10_AF4 +#define I2C2_SCL_PB13_AF4 +#define I2C2_SDA_PB11_AF4 +#define I2C2_SDA_PB14_AF4 +#define I2C3_SCL_PA7_AF4 +#define I2C3_SCL_PC0_AF4 +#define I2C3_SDA_PB4_AF4 +#define I2C3_SDA_PC1_AF4 +#define I2C3_SDA_PC9_AF6 +#define I2C4_SCL_PB10_AF3 +#define I2C4_SCL_PB6_AF5 +#define I2C4_SDA_PB11_AF3 +#define I2C4_SDA_PB7_AF5 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF8 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF8 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PA1_AF8 +#define UART4_RX_PC11_AF8 +#define UART4_TX_PA0_AF8 +#define UART4_TX_PC10_AF8 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART2_RX_PA15_AF3 +#define USART2_RX_PA3_AF7 +#define USART2_TX_PA2_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PC5_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PC4_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (4) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF5 +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MOSI_PA12_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_SCK_PA1_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MISO_PC2_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_MOSI_PC1_AF3 +#define SPI2_MOSI_PC3_AF5 +#define SPI2_SCK_PA9_AF3 +#define SPI2_SCK_PB10_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF1 +#define LPTIM1_ETR_PC3_AF1 +#define LPTIM2_ETR_PA5_AF14 +#define LPTIM2_ETR_PC3_AF14 +#define TIM15_BKIN_PA9_AF14 +#define TIM15_BKIN_PB12_AF14 +#define TIM15_CH1N_PA1_AF14 +#define TIM15_CH1N_PB13_AF14 +#define TIM15_CH1_PA2_AF14 +#define TIM15_CH1_PB14_AF14 +#define TIM15_CH2_PA3_AF14 +#define TIM15_CH2_PB15_AF14 +#define TIM16_BKIN_PB5_AF14 +#define TIM16_CH1N_PB6_AF14 +#define TIM16_CH1_PA6_AF14 +#define TIM16_CH1_PB8_AF14 +#define TIM17_BKIN_PA10_AF14 +#define TIM17_BKIN_PB4_AF14 +#define TIM17_CH1N_PB7_AF14 +#define TIM17_CH1_PA7_AF14 +#define TIM17_CH1_PB9_AF14 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN_PA6_AF12 +#define TIM1_BKIN_PB12_AF3 +#define TIM1_CH1N_PA7_AF1 +#define TIM1_CH1N_PB13_AF1 +#define TIM1_CH1_PA8_AF1 +#define TIM1_CH2N_PB0_AF1 +#define TIM1_CH2N_PB14_AF1 +#define TIM1_CH2_PA9_AF1 +#define TIM1_CH3N_PB15_AF1 +#define TIM1_CH3N_PB1_AF1 +#define TIM1_CH3_PA10_AF1 +#define TIM1_CH4_PA11_AF1 +#define TIM1_ETR_PA12_AF1 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PC9_AF2 +#define TIM3_ETR_PD2_AF2 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH4_PA3_AF2 +#define TIM8_BKIN2_PB6_AF12 +#define TIM8_BKIN2_PC9_AF14 +#define TIM8_BKIN_PA6_AF13 +#define TIM8_BKIN_PB7_AF13 +#define TIM8_CH1N_PA5_AF3 +#define TIM8_CH1N_PA7_AF3 +#define TIM8_CH1_PC6_AF3 +#define TIM8_CH2N_PB0_AF3 +#define TIM8_CH2N_PB14_AF3 +#define TIM8_CH2_PC7_AF3 +#define TIM8_CH3N_PB15_AF3 +#define TIM8_CH3N_PB1_AF3 +#define TIM8_CH3_PC8_AF3 +#define TIM8_CH4_PC9_AF3 +#define TIM8_ETR_PA0_AF3 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) + +#define TIM_MODULE_COUNT (9) + +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD2_CN +#define __PH0_CN +#define __PH1_CN +#define __PH3_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_H_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32L4Q5VG/LQFP100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32L4Q5VG/LQFP100/mcu_definitions.h new file mode 100644 index 000000000..7c69576b3 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32L4Q5VG/LQFP100/mcu_definitions.h @@ -0,0 +1,468 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32L4Q5VG_LQFP100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH5 +#define ADC1_PA1_CH6 +#define ADC1_PA2_CH7 +#define ADC1_PA3_CH8 +#define ADC1_PA4_CH9 +#define ADC1_PA5_CH10 +#define ADC1_PA6_CH11 +#define ADC1_PA7_CH12 +#define ADC1_PB0_CH15 +#define ADC1_PB1_CH16 +#define ADC1_PC0_CH1 +#define ADC1_PC1_CH2 +#define ADC1_PC2_CH3 +#define ADC1_PC3_CH4 +#define ADC1_PC4_CH13 +#define ADC1_PC5_CH14 +#define ADC2_PA0_CH5 +#define ADC2_PA1_CH6 +#define ADC2_PA2_CH7 +#define ADC2_PA3_CH8 +#define ADC2_PA4_CH9 +#define ADC2_PA5_CH10 +#define ADC2_PA6_CH11 +#define ADC2_PA7_CH12 +#define ADC2_PB0_CH15 +#define ADC2_PB1_CH16 +#define ADC2_PC0_CH1 +#define ADC2_PC1_CH2 +#define ADC2_PC2_CH3 +#define ADC2_PC3_CH4 +#define ADC2_PC4_CH13 +#define ADC2_PC5_CH14 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// CAN +#define CAN1_RX_PA11_AF9 +#define CAN1_RX_PB8_AF9 +#define CAN1_RX_PD0_AF9 +#define CAN1_TX_PA12_AF9 +#define CAN1_TX_PB9_AF9 +#define CAN1_TX_PD1_AF9 + +#define CAN_MODULE_1 (1) + +#define CAN_MODULE_COUNT (1) + +#define HAL_LL_CAN1_BASE_ADDRESS (0x40006400UL) + +#define HAL_LL_CAN1_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (94) +#define DMA_NUM_OF_CHANNELS_FAMILY (94) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (7) +#define DMA_NUM_OF_STREAMS_FAMILY (7) +// EOF DMA + +// I2C +#define I2C1_SCL_PB6_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PB10_AF4 +#define I2C2_SCL_PB13_AF4 +#define I2C2_SDA_PB11_AF4 +#define I2C2_SDA_PB14_AF4 +#define I2C3_SCL_PA7_AF4 +#define I2C3_SCL_PC0_AF4 +#define I2C3_SDA_PB4_AF4 +#define I2C3_SDA_PC1_AF4 +#define I2C3_SDA_PC9_AF6 +#define I2C4_SCL_PB10_AF3 +#define I2C4_SCL_PB6_AF5 +#define I2C4_SCL_PD12_AF4 +#define I2C4_SDA_PB11_AF3 +#define I2C4_SDA_PB7_AF5 +#define I2C4_SDA_PD13_AF4 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF8 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF8 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PA1_AF8 +#define UART4_RX_PC11_AF8 +#define UART4_TX_PA0_AF8 +#define UART4_TX_PC10_AF8 +#define UART5_RX_PD2_AF8 +#define UART5_TX_PC12_AF8 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART2_RX_PA15_AF3 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PD6_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PD5_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PC5_AF7 +#define USART3_RX_PD9_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PC4_AF7 +#define USART3_TX_PD8_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF5 +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MISO_PE14_AF5 +#define SPI1_MOSI_PA12_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_MOSI_PE15_AF5 +#define SPI1_SCK_PA1_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI1_SCK_PE13_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MISO_PC2_AF5 +#define SPI2_MISO_PD3_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_MOSI_PC1_AF3 +#define SPI2_MOSI_PC3_AF5 +#define SPI2_MOSI_PD4_AF5 +#define SPI2_SCK_PA9_AF3 +#define SPI2_SCK_PB10_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PD1_AF5 +#define SPI2_SCK_PD3_AF3 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_MOSI_PD6_AF5 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF1 +#define LPTIM1_ETR_PC3_AF1 +#define LPTIM2_ETR_PA5_AF14 +#define LPTIM2_ETR_PC3_AF14 +#define LPTIM2_ETR_PD11_AF14 +#define TIM15_BKIN_PA9_AF14 +#define TIM15_BKIN_PB12_AF14 +#define TIM15_CH1N_PA1_AF14 +#define TIM15_CH1N_PB13_AF14 +#define TIM15_CH1_PA2_AF14 +#define TIM15_CH1_PB14_AF14 +#define TIM15_CH2_PA3_AF14 +#define TIM15_CH2_PB15_AF14 +#define TIM16_BKIN_PB5_AF14 +#define TIM16_CH1N_PB6_AF14 +#define TIM16_CH1_PA6_AF14 +#define TIM16_CH1_PB8_AF14 +#define TIM16_CH1_PE0_AF14 +#define TIM17_BKIN_PA10_AF14 +#define TIM17_BKIN_PB4_AF14 +#define TIM17_CH1N_PB7_AF14 +#define TIM17_CH1_PA7_AF14 +#define TIM17_CH1_PB9_AF14 +#define TIM17_CH1_PE1_AF14 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PE14_AF3 +#define TIM1_BKIN_PA6_AF12 +#define TIM1_BKIN_PB12_AF3 +#define TIM1_BKIN_PE15_AF3 +#define TIM1_CH1N_PA7_AF1 +#define TIM1_CH1N_PB13_AF1 +#define TIM1_CH1N_PE8_AF1 +#define TIM1_CH1_PA8_AF1 +#define TIM1_CH1_PE9_AF1 +#define TIM1_CH2N_PB0_AF1 +#define TIM1_CH2N_PB14_AF1 +#define TIM1_CH2N_PE10_AF1 +#define TIM1_CH2_PA9_AF1 +#define TIM1_CH2_PE11_AF1 +#define TIM1_CH3N_PB15_AF1 +#define TIM1_CH3N_PB1_AF1 +#define TIM1_CH3N_PE12_AF1 +#define TIM1_CH3_PA10_AF1 +#define TIM1_CH3_PE13_AF1 +#define TIM1_CH4_PA11_AF1 +#define TIM1_CH4_PE14_AF1 +#define TIM1_ETR_PA12_AF1 +#define TIM1_ETR_PE7_AF1 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH1_PE3_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH2_PE4_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH3_PE5_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PC9_AF2 +#define TIM3_CH4_PE6_AF2 +#define TIM3_ETR_PD2_AF2 +#define TIM3_ETR_PE2_AF2 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH1_PD12_AF2 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH2_PD13_AF2 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH3_PD14_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_CH4_PD15_AF2 +#define TIM4_ETR_PE0_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH4_PA3_AF2 +#define TIM8_BKIN2_PB6_AF12 +#define TIM8_BKIN2_PC9_AF14 +#define TIM8_BKIN_PA6_AF13 +#define TIM8_BKIN_PB7_AF13 +#define TIM8_CH1N_PA5_AF3 +#define TIM8_CH1N_PA7_AF3 +#define TIM8_CH1_PC6_AF3 +#define TIM8_CH2N_PB0_AF3 +#define TIM8_CH2N_PB14_AF3 +#define TIM8_CH2_PC7_AF3 +#define TIM8_CH3N_PB15_AF3 +#define TIM8_CH3N_PB1_AF3 +#define TIM8_CH3_PC8_AF3 +#define TIM8_CH4_PC9_AF3 +#define TIM8_ETR_PA0_AF3 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) + +#define TIM_MODULE_COUNT (9) + +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PE0_CN +#define __PE1_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN +#define __PE6_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PH0_CN +#define __PH1_CN +#define __PH3_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_H_CN + +#define PORT_COUNT (6) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32L4Q5VG/WLCSP100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32L4Q5VG/WLCSP100/mcu_definitions.h new file mode 100644 index 000000000..27956befb --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32L4Q5VG/WLCSP100/mcu_definitions.h @@ -0,0 +1,466 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32L4Q5VG_WLCSP100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH5 +#define ADC1_PA1_CH6 +#define ADC1_PA2_CH7 +#define ADC1_PA3_CH8 +#define ADC1_PA4_CH9 +#define ADC1_PA5_CH10 +#define ADC1_PA6_CH11 +#define ADC1_PA7_CH12 +#define ADC1_PB0_CH15 +#define ADC1_PB1_CH16 +#define ADC1_PC0_CH1 +#define ADC1_PC1_CH2 +#define ADC1_PC2_CH3 +#define ADC1_PC3_CH4 +#define ADC1_PC4_CH13 +#define ADC1_PC5_CH14 +#define ADC2_PA0_CH5 +#define ADC2_PA1_CH6 +#define ADC2_PA2_CH7 +#define ADC2_PA3_CH8 +#define ADC2_PA4_CH9 +#define ADC2_PA5_CH10 +#define ADC2_PA6_CH11 +#define ADC2_PA7_CH12 +#define ADC2_PB0_CH15 +#define ADC2_PB1_CH16 +#define ADC2_PC0_CH1 +#define ADC2_PC1_CH2 +#define ADC2_PC2_CH3 +#define ADC2_PC3_CH4 +#define ADC2_PC4_CH13 +#define ADC2_PC5_CH14 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// CAN +#define CAN1_RX_PA11_AF9 +#define CAN1_RX_PB8_AF9 +#define CAN1_RX_PD0_AF9 +#define CAN1_TX_PA12_AF9 +#define CAN1_TX_PB9_AF9 +#define CAN1_TX_PD1_AF9 + +#define CAN_MODULE_1 (1) + +#define CAN_MODULE_COUNT (1) + +#define HAL_LL_CAN1_BASE_ADDRESS (0x40006400UL) + +#define HAL_LL_CAN1_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (94) +#define DMA_NUM_OF_CHANNELS_FAMILY (94) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (7) +#define DMA_NUM_OF_STREAMS_FAMILY (7) +// EOF DMA + +// I2C +#define I2C1_SCL_PB6_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C2_SCL_PB10_AF4 +#define I2C2_SCL_PB13_AF4 +#define I2C2_SDA_PB11_AF4 +#define I2C2_SDA_PB14_AF4 +#define I2C3_SCL_PA7_AF4 +#define I2C3_SCL_PC0_AF4 +#define I2C3_SDA_PB4_AF4 +#define I2C3_SDA_PC1_AF4 +#define I2C3_SDA_PC9_AF6 +#define I2C4_SCL_PB10_AF3 +#define I2C4_SCL_PB6_AF5 +#define I2C4_SDA_PB11_AF3 +#define I2C4_SDA_PB7_AF5 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF8 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_TX_PA2_AF8 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define UART4_RX_PA1_AF8 +#define UART4_RX_PC11_AF8 +#define UART4_TX_PA0_AF8 +#define UART4_TX_PC10_AF8 +#define UART5_RX_PD2_AF8 +#define UART5_TX_PC12_AF8 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PG10_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PG9_AF7 +#define USART2_RX_PA15_AF3 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PD6_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PD5_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PC5_AF7 +#define USART3_RX_PD9_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PC4_AF7 +#define USART3_TX_PD8_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF5 +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MISO_PE14_AF5 +#define SPI1_MOSI_PA12_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_MOSI_PE15_AF5 +#define SPI1_SCK_PA1_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI1_SCK_PE13_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MISO_PC2_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_MOSI_PC1_AF3 +#define SPI2_MOSI_PC3_AF5 +#define SPI2_MOSI_PD4_AF5 +#define SPI2_SCK_PA9_AF3 +#define SPI2_SCK_PB10_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PD1_AF5 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MISO_PG10_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_MOSI_PD6_AF5 +#define SPI3_MOSI_PG11_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 +#define SPI3_SCK_PG9_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF1 +#define LPTIM1_ETR_PC3_AF1 +#define LPTIM1_ETR_PG12_AF1 +#define LPTIM2_ETR_PA5_AF14 +#define LPTIM2_ETR_PC3_AF14 +#define TIM15_BKIN_PA9_AF14 +#define TIM15_BKIN_PB12_AF14 +#define TIM15_CH1N_PA1_AF14 +#define TIM15_CH1N_PB13_AF14 +#define TIM15_CH1N_PG9_AF14 +#define TIM15_CH1_PA2_AF14 +#define TIM15_CH1_PB14_AF14 +#define TIM15_CH1_PG10_AF14 +#define TIM15_CH2_PA3_AF14 +#define TIM15_CH2_PB15_AF14 +#define TIM15_CH2_PG11_AF14 +#define TIM16_BKIN_PB5_AF14 +#define TIM16_CH1N_PB6_AF14 +#define TIM16_CH1_PA6_AF14 +#define TIM16_CH1_PB8_AF14 +#define TIM17_BKIN_PA10_AF14 +#define TIM17_BKIN_PB4_AF14 +#define TIM17_CH1N_PB7_AF14 +#define TIM17_CH1_PA7_AF14 +#define TIM17_CH1_PB9_AF14 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PE14_AF3 +#define TIM1_BKIN_PA6_AF12 +#define TIM1_BKIN_PB12_AF3 +#define TIM1_BKIN_PE15_AF3 +#define TIM1_CH1N_PA7_AF1 +#define TIM1_CH1N_PB13_AF1 +#define TIM1_CH1N_PE8_AF1 +#define TIM1_CH1_PA8_AF1 +#define TIM1_CH1_PE9_AF1 +#define TIM1_CH2N_PB0_AF1 +#define TIM1_CH2N_PB14_AF1 +#define TIM1_CH2N_PE10_AF1 +#define TIM1_CH2_PA9_AF1 +#define TIM1_CH2_PE11_AF1 +#define TIM1_CH3N_PB15_AF1 +#define TIM1_CH3N_PB1_AF1 +#define TIM1_CH3N_PE12_AF1 +#define TIM1_CH3_PA10_AF1 +#define TIM1_CH3_PE13_AF1 +#define TIM1_CH4_PA11_AF1 +#define TIM1_CH4_PE14_AF1 +#define TIM1_ETR_PA12_AF1 +#define TIM1_ETR_PE7_AF1 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH1_PE3_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH2_PE4_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH3_PE5_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PC9_AF2 +#define TIM3_CH4_PE6_AF2 +#define TIM3_ETR_PD2_AF2 +#define TIM3_ETR_PE2_AF2 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH3_PD14_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_CH4_PD15_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH4_PA3_AF2 +#define TIM8_BKIN2_PB6_AF12 +#define TIM8_BKIN2_PC9_AF14 +#define TIM8_BKIN_PA6_AF13 +#define TIM8_BKIN_PB7_AF13 +#define TIM8_CH1N_PA5_AF3 +#define TIM8_CH1N_PA7_AF3 +#define TIM8_CH1_PC6_AF3 +#define TIM8_CH2N_PB0_AF3 +#define TIM8_CH2N_PB14_AF3 +#define TIM8_CH2_PC7_AF3 +#define TIM8_CH3N_PB15_AF3 +#define TIM8_CH3N_PB1_AF3 +#define TIM8_CH3_PC8_AF3 +#define TIM8_CH4_PC9_AF3 +#define TIM8_ETR_PA0_AF3 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) + +#define TIM_MODULE_COUNT (9) + +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD14_CN +#define __PD15_CN +#define __PD2_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN +#define __PE6_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PG10_CN +#define __PG11_CN +#define __PG12_CN +#define __PG9_CN +#define __PH0_CN +#define __PH1_CN +#define __PH3_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_G_CN +#define __PORT_H_CN + +#define PORT_COUNT (7) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32L4Q5ZG/LQFP144/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32L4Q5ZG/LQFP144/mcu_definitions.h new file mode 100644 index 000000000..21f9a5140 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/ai_generated/STM32/STM32L4Q5ZG/LQFP144/mcu_definitions.h @@ -0,0 +1,531 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for STM32L4Q5ZG_LQFP144. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC1_PA0_CH5 +#define ADC1_PA1_CH6 +#define ADC1_PA2_CH7 +#define ADC1_PA3_CH8 +#define ADC1_PA4_CH9 +#define ADC1_PA5_CH10 +#define ADC1_PA6_CH11 +#define ADC1_PA7_CH12 +#define ADC1_PB0_CH15 +#define ADC1_PB1_CH16 +#define ADC1_PC0_CH1 +#define ADC1_PC1_CH2 +#define ADC1_PC2_CH3 +#define ADC1_PC3_CH4 +#define ADC1_PC4_CH13 +#define ADC1_PC5_CH14 +#define ADC2_PA0_CH5 +#define ADC2_PA1_CH6 +#define ADC2_PA2_CH7 +#define ADC2_PA3_CH8 +#define ADC2_PA4_CH9 +#define ADC2_PA5_CH10 +#define ADC2_PA6_CH11 +#define ADC2_PA7_CH12 +#define ADC2_PB0_CH15 +#define ADC2_PB1_CH16 +#define ADC2_PC0_CH1 +#define ADC2_PC1_CH2 +#define ADC2_PC2_CH3 +#define ADC2_PC3_CH4 +#define ADC2_PC4_CH13 +#define ADC2_PC5_CH14 + +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// CAN +#define CAN1_RX_PA11_AF9 +#define CAN1_RX_PB8_AF9 +#define CAN1_RX_PD0_AF9 +#define CAN1_TX_PA12_AF9 +#define CAN1_TX_PB9_AF9 +#define CAN1_TX_PD1_AF9 + +#define CAN_MODULE_1 (1) + +#define CAN_MODULE_COUNT (1) + +#define HAL_LL_CAN1_BASE_ADDRESS (0x40006400UL) + +#define HAL_LL_CAN1_GPIO_AF9 (9) +// EOF CAN + +// DMA +#define DMA_NUM_OF_CHANNELS (94) +#define DMA_NUM_OF_CHANNELS_FAMILY (94) +#define DMA_NUM_OF_MODULES (2) +#define DMA_NUM_OF_STREAMS (7) +#define DMA_NUM_OF_STREAMS_FAMILY (7) +// EOF DMA + +// I2C +#define I2C1_SCL_PB6_AF4 +#define I2C1_SCL_PB8_AF4 +#define I2C1_SCL_PG14_AF4 +#define I2C1_SDA_PB7_AF4 +#define I2C1_SDA_PB9_AF4 +#define I2C1_SDA_PG13_AF4 +#define I2C2_SCL_PB10_AF4 +#define I2C2_SCL_PB13_AF4 +#define I2C2_SCL_PF1_AF4 +#define I2C2_SDA_PB11_AF4 +#define I2C2_SDA_PB14_AF4 +#define I2C2_SDA_PF0_AF4 +#define I2C3_SCL_PA7_AF4 +#define I2C3_SCL_PC0_AF4 +#define I2C3_SCL_PG7_AF4 +#define I2C3_SDA_PB4_AF4 +#define I2C3_SDA_PC1_AF4 +#define I2C3_SDA_PC9_AF6 +#define I2C3_SDA_PG8_AF4 +#define I2C4_SCL_PB10_AF3 +#define I2C4_SCL_PB6_AF5 +#define I2C4_SCL_PD12_AF4 +#define I2C4_SCL_PF14_AF4 +#define I2C4_SDA_PB11_AF3 +#define I2C4_SDA_PB7_AF5 +#define I2C4_SDA_PD13_AF4 +#define I2C4_SDA_PF15_AF4 + +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) +#define I2C_MODULE_3 (3) +#define I2C_MODULE_4 (4) + +#define I2C_MODULE_COUNT (4) +// EOF I2C + +// U(S)ART +#define LPUART1_RX_PA3_AF8 +#define LPUART1_RX_PB10_AF8 +#define LPUART1_RX_PC0_AF8 +#define LPUART1_RX_PG8_AF8 +#define LPUART1_TX_PA2_AF8 +#define LPUART1_TX_PB11_AF8 +#define LPUART1_TX_PC1_AF8 +#define LPUART1_TX_PG7_AF8 +#define UART4_RX_PA1_AF8 +#define UART4_RX_PC11_AF8 +#define UART4_TX_PA0_AF8 +#define UART4_TX_PC10_AF8 +#define UART5_RX_PD2_AF8 +#define UART5_TX_PC12_AF8 +#define USART1_RX_PA10_AF7 +#define USART1_RX_PB7_AF7 +#define USART1_RX_PG10_AF7 +#define USART1_TX_PA9_AF7 +#define USART1_TX_PB6_AF7 +#define USART1_TX_PG9_AF7 +#define USART2_RX_PA15_AF3 +#define USART2_RX_PA3_AF7 +#define USART2_RX_PD6_AF7 +#define USART2_TX_PA2_AF7 +#define USART2_TX_PD5_AF7 +#define USART3_RX_PB11_AF7 +#define USART3_RX_PC11_AF7 +#define USART3_RX_PC5_AF7 +#define USART3_RX_PD9_AF7 +#define USART3_TX_PB10_AF7 +#define USART3_TX_PC10_AF7 +#define USART3_TX_PC4_AF7 +#define USART3_TX_PD8_AF7 + +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) +#define UART_MODULE_5 (5) + +#define UART_MODULE_COUNT (5) +// EOF U(S)ART + +// SPI +#define SPI1_MISO_PA11_AF5 +#define SPI1_MISO_PA6_AF5 +#define SPI1_MISO_PB4_AF5 +#define SPI1_MISO_PE14_AF5 +#define SPI1_MISO_PG3_AF5 +#define SPI1_MOSI_PA12_AF5 +#define SPI1_MOSI_PA7_AF5 +#define SPI1_MOSI_PB5_AF5 +#define SPI1_MOSI_PE15_AF5 +#define SPI1_MOSI_PG4_AF5 +#define SPI1_SCK_PA1_AF5 +#define SPI1_SCK_PA5_AF5 +#define SPI1_SCK_PB3_AF5 +#define SPI1_SCK_PE13_AF5 +#define SPI1_SCK_PG2_AF5 +#define SPI2_MISO_PB14_AF5 +#define SPI2_MISO_PC2_AF5 +#define SPI2_MISO_PD3_AF5 +#define SPI2_MOSI_PB15_AF5 +#define SPI2_MOSI_PC1_AF3 +#define SPI2_MOSI_PC3_AF5 +#define SPI2_MOSI_PD4_AF5 +#define SPI2_SCK_PA9_AF3 +#define SPI2_SCK_PB10_AF5 +#define SPI2_SCK_PB13_AF5 +#define SPI2_SCK_PD1_AF5 +#define SPI2_SCK_PD3_AF3 +#define SPI3_MISO_PB4_AF6 +#define SPI3_MISO_PC11_AF6 +#define SPI3_MISO_PG10_AF6 +#define SPI3_MOSI_PB5_AF6 +#define SPI3_MOSI_PC12_AF6 +#define SPI3_MOSI_PD6_AF5 +#define SPI3_MOSI_PG11_AF6 +#define SPI3_SCK_PB3_AF6 +#define SPI3_SCK_PC10_AF6 +#define SPI3_SCK_PG9_AF6 + +#define SPI_MODULE_1 (1) +#define SPI_MODULE_2 (2) +#define SPI_MODULE_3 (3) + +#define SPI_MODULE_COUNT (3) +// EOF SPI + +// TIM +#define LPTIM1_ETR_PB6_AF1 +#define LPTIM1_ETR_PC3_AF1 +#define LPTIM1_ETR_PG12_AF1 +#define LPTIM2_ETR_PA5_AF14 +#define LPTIM2_ETR_PC3_AF14 +#define LPTIM2_ETR_PD11_AF14 +#define TIM15_BKIN_PA9_AF14 +#define TIM15_BKIN_PB12_AF14 +#define TIM15_CH1N_PA1_AF14 +#define TIM15_CH1N_PB13_AF14 +#define TIM15_CH1N_PG9_AF14 +#define TIM15_CH1_PA2_AF14 +#define TIM15_CH1_PB14_AF14 +#define TIM15_CH1_PF9_AF14 +#define TIM15_CH1_PG10_AF14 +#define TIM15_CH2_PA3_AF14 +#define TIM15_CH2_PB15_AF14 +#define TIM15_CH2_PF10_AF14 +#define TIM15_CH2_PG11_AF14 +#define TIM16_BKIN_PB5_AF14 +#define TIM16_CH1N_PB6_AF14 +#define TIM16_CH1_PA6_AF14 +#define TIM16_CH1_PB8_AF14 +#define TIM16_CH1_PE0_AF14 +#define TIM17_BKIN_PA10_AF14 +#define TIM17_BKIN_PB4_AF14 +#define TIM17_CH1N_PB7_AF14 +#define TIM17_CH1_PA7_AF14 +#define TIM17_CH1_PB9_AF14 +#define TIM17_CH1_PE1_AF14 +#define TIM1_BKIN2_PA11_AF12 +#define TIM1_BKIN2_PE14_AF3 +#define TIM1_BKIN_PA6_AF12 +#define TIM1_BKIN_PB12_AF3 +#define TIM1_BKIN_PE15_AF3 +#define TIM1_CH1N_PA7_AF1 +#define TIM1_CH1N_PB13_AF1 +#define TIM1_CH1N_PE8_AF1 +#define TIM1_CH1_PA8_AF1 +#define TIM1_CH1_PE9_AF1 +#define TIM1_CH2N_PB0_AF1 +#define TIM1_CH2N_PB14_AF1 +#define TIM1_CH2N_PE10_AF1 +#define TIM1_CH2_PA9_AF1 +#define TIM1_CH2_PE11_AF1 +#define TIM1_CH3N_PB15_AF1 +#define TIM1_CH3N_PB1_AF1 +#define TIM1_CH3N_PE12_AF1 +#define TIM1_CH3_PA10_AF1 +#define TIM1_CH3_PE13_AF1 +#define TIM1_CH4_PA11_AF1 +#define TIM1_CH4_PE14_AF1 +#define TIM1_ETR_PA12_AF1 +#define TIM1_ETR_PE7_AF1 +#define TIM2_CH1_PA0_AF1 +#define TIM2_CH1_PA15_AF1 +#define TIM2_CH1_PA5_AF1 +#define TIM2_CH2_PA1_AF1 +#define TIM2_CH2_PB3_AF1 +#define TIM2_CH3_PA2_AF1 +#define TIM2_CH3_PB10_AF1 +#define TIM2_CH4_PA3_AF1 +#define TIM2_CH4_PB11_AF1 +#define TIM2_ETR_PA0_AF14 +#define TIM2_ETR_PA15_AF2 +#define TIM2_ETR_PA5_AF2 +#define TIM3_CH1_PA6_AF2 +#define TIM3_CH1_PB4_AF2 +#define TIM3_CH1_PC6_AF2 +#define TIM3_CH1_PE3_AF2 +#define TIM3_CH2_PA7_AF2 +#define TIM3_CH2_PB5_AF2 +#define TIM3_CH2_PC7_AF2 +#define TIM3_CH2_PE4_AF2 +#define TIM3_CH3_PB0_AF2 +#define TIM3_CH3_PC8_AF2 +#define TIM3_CH3_PE5_AF2 +#define TIM3_CH4_PB1_AF2 +#define TIM3_CH4_PC9_AF2 +#define TIM3_CH4_PE6_AF2 +#define TIM3_ETR_PD2_AF2 +#define TIM3_ETR_PE2_AF2 +#define TIM4_CH1_PB6_AF2 +#define TIM4_CH1_PD12_AF2 +#define TIM4_CH2_PB7_AF2 +#define TIM4_CH2_PD13_AF2 +#define TIM4_CH3_PB8_AF2 +#define TIM4_CH3_PD14_AF2 +#define TIM4_CH4_PB9_AF2 +#define TIM4_CH4_PD15_AF2 +#define TIM4_ETR_PE0_AF2 +#define TIM5_CH1_PA0_AF2 +#define TIM5_CH1_PF6_AF2 +#define TIM5_CH2_PA1_AF2 +#define TIM5_CH2_PF7_AF2 +#define TIM5_CH3_PA2_AF2 +#define TIM5_CH3_PF8_AF2 +#define TIM5_CH4_PA3_AF2 +#define TIM5_CH4_PF9_AF2 +#define TIM5_ETR_PF6_AF1 +#define TIM8_BKIN2_PB6_AF12 +#define TIM8_BKIN2_PC9_AF14 +#define TIM8_BKIN_PA6_AF13 +#define TIM8_BKIN_PB7_AF13 +#define TIM8_CH1N_PA5_AF3 +#define TIM8_CH1N_PA7_AF3 +#define TIM8_CH1_PC6_AF3 +#define TIM8_CH2N_PB0_AF3 +#define TIM8_CH2N_PB14_AF3 +#define TIM8_CH2_PC7_AF3 +#define TIM8_CH3N_PB15_AF3 +#define TIM8_CH3N_PB1_AF3 +#define TIM8_CH3_PC8_AF3 +#define TIM8_CH4_PC9_AF3 +#define TIM8_ETR_PA0_AF3 + +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) +#define TIM_MODULE_4 (4) +#define TIM_MODULE_5 (5) +#define TIM_MODULE_8 (6) +#define TIM_MODULE_15 (7) +#define TIM_MODULE_16 (8) +#define TIM_MODULE_17 (9) + +#define TIM_MODULE_COUNT (9) + +#define TIM1_BUS (2) +#define TIM8_BUS (2) +#define TIM15_BUS (2) +#define TIM16_BUS (2) +#define TIM17_BUS (2) +#define TIM2_BUS (1) +#define TIM3_BUS (1) +#define TIM4_BUS (1) +#define TIM5_BUS (1) +// EOF TIM + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PB0_CN +#define __PB1_CN +#define __PB10_CN +#define __PB11_CN +#define __PB12_CN +#define __PB13_CN +#define __PB14_CN +#define __PB15_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PC0_CN +#define __PC1_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PD0_CN +#define __PD1_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PE0_CN +#define __PE1_CN +#define __PE10_CN +#define __PE11_CN +#define __PE12_CN +#define __PE13_CN +#define __PE14_CN +#define __PE15_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN +#define __PE6_CN +#define __PE7_CN +#define __PE8_CN +#define __PE9_CN +#define __PF0_CN +#define __PF1_CN +#define __PF10_CN +#define __PF11_CN +#define __PF12_CN +#define __PF13_CN +#define __PF14_CN +#define __PF15_CN +#define __PF2_CN +#define __PF3_CN +#define __PF4_CN +#define __PF5_CN +#define __PF6_CN +#define __PF7_CN +#define __PF8_CN +#define __PF9_CN +#define __PG0_CN +#define __PG1_CN +#define __PG10_CN +#define __PG11_CN +#define __PG12_CN +#define __PG13_CN +#define __PG14_CN +#define __PG15_CN +#define __PG2_CN +#define __PG3_CN +#define __PG4_CN +#define __PG5_CN +#define __PG6_CN +#define __PG7_CN +#define __PG8_CN +#define __PG9_CN +#define __PH0_CN +#define __PH1_CN +#define __PH3_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN +#define __PORT_F_CN +#define __PORT_G_CN +#define __PORT_H_CN + +#define PORT_COUNT (8) +#define PORT_SIZE (16) +// EOF GPIO + +// IVT_TABLE +#define UART1_IVT (37) +#define UART1_NVIC (53) +#define UART2_IVT (38) +#define UART2_NVIC (54) +#define UART3_IVT (39) +#define UART3_NVIC (55) +#define UART4_IVT (52) +#define UART4_NVIC (68) +#define UART5_IVT (53) +#define UART5_NVIC (69) +// EOF IVT_TABLE + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/.gitkeep b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/.gitkeep new file mode 100644 index 000000000..e69de29bb diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32C011D6/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32C011D6/mcu_reg_addresses.h new file mode 100644 index 000000000..f46c6498f --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32C011D6/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32C011D6 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32C011D6 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32C011F4/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32C011F4/mcu_reg_addresses.h new file mode 100644 index 000000000..d6724ba1d --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32C011F4/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32C011F4 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32C011F4 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32C011F6/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32C011F6/mcu_reg_addresses.h new file mode 100644 index 000000000..bcb04d5ef --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32C011F6/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32C011F6 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32C011F6 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32C011J4/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32C011J4/mcu_reg_addresses.h new file mode 100644 index 000000000..4804e4af4 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32C011J4/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32C011J4 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32C011J4 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32C011J6/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32C011J6/mcu_reg_addresses.h new file mode 100644 index 000000000..17901a99d --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32C011J6/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32C011J6 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32C011J6 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32C031C4/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32C031C4/mcu_reg_addresses.h new file mode 100644 index 000000000..5f8000de0 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32C031C4/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32C031C4 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32C031C4 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32C031C6/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32C031C6/mcu_reg_addresses.h new file mode 100644 index 000000000..6814cbfca --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32C031C6/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32C031C6 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32C031C6 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32C031F4/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32C031F4/mcu_reg_addresses.h new file mode 100644 index 000000000..202aeda4d --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32C031F4/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32C031F4 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32C031F4 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32C031F6/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32C031F6/mcu_reg_addresses.h new file mode 100644 index 000000000..473bc6a5b --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32C031F6/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32C031F6 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32C031F6 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32C031G4/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32C031G4/mcu_reg_addresses.h new file mode 100644 index 000000000..6922aa81b --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32C031G4/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32C031G4 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32C031G4 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32C031G6/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32C031G6/mcu_reg_addresses.h new file mode 100644 index 000000000..a72db5671 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32C031G6/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32C031G6 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32C031G6 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32C031K4/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32C031K4/mcu_reg_addresses.h new file mode 100644 index 000000000..4f2279bf5 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32C031K4/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32C031K4 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32C031K4 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32C031K6/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32C031K6/mcu_reg_addresses.h new file mode 100644 index 000000000..c6a89576c --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32C031K6/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32C031K6 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32C031K6 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G051C6/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G051C6/mcu_reg_addresses.h new file mode 100644 index 000000000..dc1687a19 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G051C6/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G051C6 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G051C6 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G051C8/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G051C8/mcu_reg_addresses.h new file mode 100644 index 000000000..5061aa7cc --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G051C8/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G051C8 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G051C8 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G051F6/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G051F6/mcu_reg_addresses.h new file mode 100644 index 000000000..62a556dc5 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G051F6/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G051F6 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G051F6 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G051F8/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G051F8/mcu_reg_addresses.h new file mode 100644 index 000000000..9badf1374 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G051F8/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G051F8 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G051F8 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G051G6/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G051G6/mcu_reg_addresses.h new file mode 100644 index 000000000..ba65dc014 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G051G6/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G051G6 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G051G6 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G051G8/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G051G8/mcu_reg_addresses.h new file mode 100644 index 000000000..55ed3490e --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G051G8/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G051G8 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G051G8 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G051K6/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G051K6/mcu_reg_addresses.h new file mode 100644 index 000000000..0fae39208 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G051K6/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G051K6 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G051K6 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G051K8/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G051K8/mcu_reg_addresses.h new file mode 100644 index 000000000..94533b88e --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G051K8/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G051K8 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G051K8 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G061C6/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G061C6/mcu_reg_addresses.h new file mode 100644 index 000000000..1b5d42d88 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G061C6/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G061C6 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G061C6 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G061C8/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G061C8/mcu_reg_addresses.h new file mode 100644 index 000000000..d36521cd6 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G061C8/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G061C8 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G061C8 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G061F6/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G061F6/mcu_reg_addresses.h new file mode 100644 index 000000000..d43e0560d --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G061F6/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G061F6 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G061F6 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G061F8/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G061F8/mcu_reg_addresses.h new file mode 100644 index 000000000..ff7a30abc --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G061F8/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G061F8 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G061F8 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G061G6/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G061G6/mcu_reg_addresses.h new file mode 100644 index 000000000..e3928d4a9 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G061G6/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G061G6 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G061G6 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G061G8/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G061G8/mcu_reg_addresses.h new file mode 100644 index 000000000..39e408519 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G061G8/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G061G8 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G061G8 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G061K6/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G061K6/mcu_reg_addresses.h new file mode 100644 index 000000000..fb5bb3fad --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G061K6/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G061K6 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G061K6 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G061K8/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G061K8/mcu_reg_addresses.h new file mode 100644 index 000000000..1803c9b1c --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G061K8/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G061K8 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G061K8 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0B1CB/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0B1CB/mcu_reg_addresses.h new file mode 100644 index 000000000..d811af5c4 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0B1CB/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G0B1CB register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G0B1CB REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0B1CC/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0B1CC/mcu_reg_addresses.h new file mode 100644 index 000000000..ca06eb724 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0B1CC/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G0B1CC register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G0B1CC REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0B1CE/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0B1CE/mcu_reg_addresses.h new file mode 100644 index 000000000..6d4676f02 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0B1CE/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G0B1CE register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G0B1CE REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0B1KB/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0B1KB/mcu_reg_addresses.h new file mode 100644 index 000000000..1d64bb51e --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0B1KB/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G0B1KB register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G0B1KB REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0B1KC/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0B1KC/mcu_reg_addresses.h new file mode 100644 index 000000000..b63a2bcb2 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0B1KC/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G0B1KC register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G0B1KC REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0B1KE/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0B1KE/mcu_reg_addresses.h new file mode 100644 index 000000000..f1c532ec7 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0B1KE/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G0B1KE register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G0B1KE REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0B1MB/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0B1MB/mcu_reg_addresses.h new file mode 100644 index 000000000..05fae7c62 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0B1MB/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G0B1MB register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G0B1MB REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0B1MC/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0B1MC/mcu_reg_addresses.h new file mode 100644 index 000000000..516b19557 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0B1MC/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G0B1MC register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G0B1MC REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0B1ME/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0B1ME/mcu_reg_addresses.h new file mode 100644 index 000000000..4147d88bf --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0B1ME/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G0B1ME register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G0B1ME REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0B1NE/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0B1NE/mcu_reg_addresses.h new file mode 100644 index 000000000..a777fee48 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0B1NE/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G0B1NE register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G0B1NE REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0B1RB/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0B1RB/mcu_reg_addresses.h new file mode 100644 index 000000000..111f95d7a --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0B1RB/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G0B1RB register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G0B1RB REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0B1RC/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0B1RC/mcu_reg_addresses.h new file mode 100644 index 000000000..0f8ea72e8 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0B1RC/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G0B1RC register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G0B1RC REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0B1RE/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0B1RE/mcu_reg_addresses.h new file mode 100644 index 000000000..625c7b99a --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0B1RE/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G0B1RE register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G0B1RE REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0B1VB/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0B1VB/mcu_reg_addresses.h new file mode 100644 index 000000000..b2e2ca17d --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0B1VB/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G0B1VB register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G0B1VB REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0B1VC/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0B1VC/mcu_reg_addresses.h new file mode 100644 index 000000000..3f01149c2 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0B1VC/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G0B1VC register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G0B1VC REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0B1VE/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0B1VE/mcu_reg_addresses.h new file mode 100644 index 000000000..1c32b30c9 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0B1VE/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G0B1VE register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G0B1VE REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0C1CC/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0C1CC/mcu_reg_addresses.h new file mode 100644 index 000000000..d1ca690aa --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0C1CC/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G0C1CC register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G0C1CC REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0C1CE/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0C1CE/mcu_reg_addresses.h new file mode 100644 index 000000000..8736c775f --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0C1CE/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G0C1CE register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G0C1CE REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0C1KC/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0C1KC/mcu_reg_addresses.h new file mode 100644 index 000000000..45d33d30b --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0C1KC/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G0C1KC register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G0C1KC REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0C1KE/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0C1KE/mcu_reg_addresses.h new file mode 100644 index 000000000..c548f878a --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0C1KE/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G0C1KE register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G0C1KE REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0C1MC/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0C1MC/mcu_reg_addresses.h new file mode 100644 index 000000000..b68fd361e --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0C1MC/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G0C1MC register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G0C1MC REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0C1ME/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0C1ME/mcu_reg_addresses.h new file mode 100644 index 000000000..908abce3c --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0C1ME/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G0C1ME register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G0C1ME REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0C1NE/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0C1NE/mcu_reg_addresses.h new file mode 100644 index 000000000..8ebb8fbc4 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0C1NE/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G0C1NE register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G0C1NE REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0C1RC/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0C1RC/mcu_reg_addresses.h new file mode 100644 index 000000000..765db4d25 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0C1RC/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G0C1RC register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G0C1RC REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0C1RE/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0C1RE/mcu_reg_addresses.h new file mode 100644 index 000000000..65c9713f0 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0C1RE/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G0C1RE register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G0C1RE REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0C1VC/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0C1VC/mcu_reg_addresses.h new file mode 100644 index 000000000..64b0afe80 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0C1VC/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G0C1VC register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G0C1VC REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0C1VE/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0C1VE/mcu_reg_addresses.h new file mode 100644 index 000000000..d1c2c483b --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G0C1VE/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G0C1VE register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G0C1VE REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G431C6/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G431C6/mcu_reg_addresses.h new file mode 100644 index 000000000..490c6b26b --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G431C6/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G431C6 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G431C6 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G431C8/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G431C8/mcu_reg_addresses.h new file mode 100644 index 000000000..59c8b5b94 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G431C8/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G431C8 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G431C8 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G431CB/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G431CB/mcu_reg_addresses.h new file mode 100644 index 000000000..436e1a804 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G431CB/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G431CB register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G431CB REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G431K6/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G431K6/mcu_reg_addresses.h new file mode 100644 index 000000000..2359736fc --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G431K6/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G431K6 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G431K6 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G431K8/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G431K8/mcu_reg_addresses.h new file mode 100644 index 000000000..b852c6ea3 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G431K8/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G431K8 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G431K8 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G431KB/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G431KB/mcu_reg_addresses.h new file mode 100644 index 000000000..2a5286202 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G431KB/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G431KB register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G431KB REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G431M6/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G431M6/mcu_reg_addresses.h new file mode 100644 index 000000000..a6dcc671c --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G431M6/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G431M6 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G431M6 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G431M8/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G431M8/mcu_reg_addresses.h new file mode 100644 index 000000000..be9b1e6cb --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G431M8/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G431M8 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G431M8 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G431MB/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G431MB/mcu_reg_addresses.h new file mode 100644 index 000000000..62f744456 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G431MB/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G431MB register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G431MB REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G431R6/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G431R6/mcu_reg_addresses.h new file mode 100644 index 000000000..575877842 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G431R6/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G431R6 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G431R6 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G431R8/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G431R8/mcu_reg_addresses.h new file mode 100644 index 000000000..796af8527 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G431R8/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G431R8 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G431R8 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G431RB/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G431RB/mcu_reg_addresses.h new file mode 100644 index 000000000..5fc6671c9 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G431RB/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G431RB register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G431RB REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G431V6/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G431V6/mcu_reg_addresses.h new file mode 100644 index 000000000..5d44da23d --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G431V6/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G431V6 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G431V6 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G431V8/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G431V8/mcu_reg_addresses.h new file mode 100644 index 000000000..89b966f4a --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G431V8/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G431V8 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G431V8 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G431VB/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G431VB/mcu_reg_addresses.h new file mode 100644 index 000000000..02a9ab9b9 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G431VB/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G431VB register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G431VB REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G441CB/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G441CB/mcu_reg_addresses.h new file mode 100644 index 000000000..84d7d8066 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G441CB/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G441CB register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G441CB REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G441KB/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G441KB/mcu_reg_addresses.h new file mode 100644 index 000000000..f617c5ff8 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G441KB/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G441KB register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G441KB REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G441MB/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G441MB/mcu_reg_addresses.h new file mode 100644 index 000000000..74ec211d7 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G441MB/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G441MB register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G441MB REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G441RB/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G441RB/mcu_reg_addresses.h new file mode 100644 index 000000000..c7ef54da6 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G441RB/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G441RB register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G441RB REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G441VB/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G441VB/mcu_reg_addresses.h new file mode 100644 index 000000000..5bfa40155 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G441VB/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G441VB register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G441VB REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G473CB/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G473CB/mcu_reg_addresses.h new file mode 100644 index 000000000..50a45f5fa --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G473CB/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G473CB register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G473CB REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G473CC/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G473CC/mcu_reg_addresses.h new file mode 100644 index 000000000..3331ef245 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G473CC/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G473CC register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G473CC REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G473CE/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G473CE/mcu_reg_addresses.h new file mode 100644 index 000000000..81b739e8a --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G473CE/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G473CE register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G473CE REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G473MB/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G473MB/mcu_reg_addresses.h new file mode 100644 index 000000000..bda063db8 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G473MB/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G473MB register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G473MB REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G473MC/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G473MC/mcu_reg_addresses.h new file mode 100644 index 000000000..bbc8a1a26 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G473MC/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G473MC register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G473MC REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G473ME/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G473ME/mcu_reg_addresses.h new file mode 100644 index 000000000..5ec7ce8a6 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G473ME/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G473ME register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G473ME REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G473PB/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G473PB/mcu_reg_addresses.h new file mode 100644 index 000000000..fa087bddb --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G473PB/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G473PB register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G473PB REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G473PC/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G473PC/mcu_reg_addresses.h new file mode 100644 index 000000000..52f3ebfa8 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G473PC/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G473PC register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G473PC REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G473PE/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G473PE/mcu_reg_addresses.h new file mode 100644 index 000000000..60c98a267 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G473PE/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G473PE register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G473PE REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G473QB/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G473QB/mcu_reg_addresses.h new file mode 100644 index 000000000..d300a9850 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G473QB/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G473QB register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G473QB REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G473QC/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G473QC/mcu_reg_addresses.h new file mode 100644 index 000000000..7255cabed --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G473QC/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G473QC register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G473QC REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G473QE/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G473QE/mcu_reg_addresses.h new file mode 100644 index 000000000..accbaf6eb --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G473QE/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G473QE register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G473QE REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G473RB/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G473RB/mcu_reg_addresses.h new file mode 100644 index 000000000..4176efc7f --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G473RB/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G473RB register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G473RB REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G473RC/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G473RC/mcu_reg_addresses.h new file mode 100644 index 000000000..1ad483267 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G473RC/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G473RC register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G473RC REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G473RE/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G473RE/mcu_reg_addresses.h new file mode 100644 index 000000000..36c8325ac --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G473RE/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G473RE register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G473RE REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G473VB/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G473VB/mcu_reg_addresses.h new file mode 100644 index 000000000..db8005eac --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G473VB/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G473VB register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G473VB REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G473VC/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G473VC/mcu_reg_addresses.h new file mode 100644 index 000000000..ea9bc8db4 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G473VC/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G473VC register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G473VC REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G473VE/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G473VE/mcu_reg_addresses.h new file mode 100644 index 000000000..a36296ba5 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G473VE/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G473VE register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G473VE REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G474CB/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G474CB/mcu_reg_addresses.h new file mode 100644 index 000000000..39f60f856 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G474CB/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G474CB register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G474CB REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G474CC/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G474CC/mcu_reg_addresses.h new file mode 100644 index 000000000..95e28f571 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G474CC/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G474CC register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G474CC REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G474CE/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G474CE/mcu_reg_addresses.h new file mode 100644 index 000000000..2fcada6a2 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G474CE/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G474CE register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G474CE REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G474MB/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G474MB/mcu_reg_addresses.h new file mode 100644 index 000000000..bb601a7c5 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G474MB/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G474MB register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G474MB REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G474MC/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G474MC/mcu_reg_addresses.h new file mode 100644 index 000000000..754a7e929 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G474MC/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G474MC register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G474MC REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G474ME/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G474ME/mcu_reg_addresses.h new file mode 100644 index 000000000..28fdae053 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G474ME/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G474ME register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G474ME REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G474PB/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G474PB/mcu_reg_addresses.h new file mode 100644 index 000000000..40be78e35 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G474PB/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G474PB register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G474PB REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G474PC/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G474PC/mcu_reg_addresses.h new file mode 100644 index 000000000..f3f1f9fea --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G474PC/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G474PC register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G474PC REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G474PE/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G474PE/mcu_reg_addresses.h new file mode 100644 index 000000000..13a5523cc --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G474PE/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G474PE register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G474PE REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G474QB/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G474QB/mcu_reg_addresses.h new file mode 100644 index 000000000..41a2c629e --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G474QB/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G474QB register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G474QB REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G474QC/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G474QC/mcu_reg_addresses.h new file mode 100644 index 000000000..585ee8528 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G474QC/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G474QC register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G474QC REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G474QE/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G474QE/mcu_reg_addresses.h new file mode 100644 index 000000000..6b299d0a0 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G474QE/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G474QE register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G474QE REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G474RB/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G474RB/mcu_reg_addresses.h new file mode 100644 index 000000000..bd37b9131 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G474RB/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G474RB register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G474RB REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G474RC/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G474RC/mcu_reg_addresses.h new file mode 100644 index 000000000..71c32db9e --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G474RC/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G474RC register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G474RC REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G474RE/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G474RE/mcu_reg_addresses.h new file mode 100644 index 000000000..f5da03c22 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G474RE/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G474RE register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G474RE REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G474VB/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G474VB/mcu_reg_addresses.h new file mode 100644 index 000000000..45f0905e3 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G474VB/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G474VB register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G474VB REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G474VC/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G474VC/mcu_reg_addresses.h new file mode 100644 index 000000000..def0c9c90 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G474VC/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G474VC register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G474VC REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G474VE/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G474VE/mcu_reg_addresses.h new file mode 100644 index 000000000..b88c1c121 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G474VE/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G474VE register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G474VE REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G483CE/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G483CE/mcu_reg_addresses.h new file mode 100644 index 000000000..4fa378ea3 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G483CE/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G483CE register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G483CE REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G483ME/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G483ME/mcu_reg_addresses.h new file mode 100644 index 000000000..3e6d421ab --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G483ME/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G483ME register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G483ME REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G483PE/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G483PE/mcu_reg_addresses.h new file mode 100644 index 000000000..e859a7b83 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G483PE/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G483PE register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G483PE REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G483QE/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G483QE/mcu_reg_addresses.h new file mode 100644 index 000000000..db4372e15 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G483QE/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G483QE register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G483QE REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G483RE/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G483RE/mcu_reg_addresses.h new file mode 100644 index 000000000..3e536af8f --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G483RE/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G483RE register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G483RE REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G483VE/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G483VE/mcu_reg_addresses.h new file mode 100644 index 000000000..1143eed96 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G483VE/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G483VE register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G483VE REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G484CE/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G484CE/mcu_reg_addresses.h new file mode 100644 index 000000000..725dfc783 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G484CE/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G484CE register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G484CE REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G484ME/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G484ME/mcu_reg_addresses.h new file mode 100644 index 000000000..d53ccd4e3 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G484ME/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G484ME register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G484ME REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G484PE/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G484PE/mcu_reg_addresses.h new file mode 100644 index 000000000..426940f4b --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G484PE/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G484PE register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G484PE REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G484QE/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G484QE/mcu_reg_addresses.h new file mode 100644 index 000000000..362d53463 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G484QE/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G484QE register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G484QE REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G484RE/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G484RE/mcu_reg_addresses.h new file mode 100644 index 000000000..ff574d8b3 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G484RE/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G484RE register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G484RE REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G484VE/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G484VE/mcu_reg_addresses.h new file mode 100644 index 000000000..370044c02 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G484VE/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G484VE register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G484VE REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G491CC/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G491CC/mcu_reg_addresses.h new file mode 100644 index 000000000..40b7d786c --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G491CC/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G491CC register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G491CC REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G491CE/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G491CE/mcu_reg_addresses.h new file mode 100644 index 000000000..631f687f7 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G491CE/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G491CE register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G491CE REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G491KC/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G491KC/mcu_reg_addresses.h new file mode 100644 index 000000000..56367eece --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G491KC/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G491KC register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G491KC REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G491KE/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G491KE/mcu_reg_addresses.h new file mode 100644 index 000000000..e1259f042 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G491KE/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G491KE register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G491KE REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G491MC/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G491MC/mcu_reg_addresses.h new file mode 100644 index 000000000..5fcdafb6e --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G491MC/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G491MC register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G491MC REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G491ME/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G491ME/mcu_reg_addresses.h new file mode 100644 index 000000000..6e80f9a1b --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G491ME/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G491ME register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G491ME REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G491RC/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G491RC/mcu_reg_addresses.h new file mode 100644 index 000000000..857adb235 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G491RC/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G491RC register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G491RC REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G491RE/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G491RE/mcu_reg_addresses.h new file mode 100644 index 000000000..2472cfc32 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G491RE/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G491RE register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G491RE REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G491VC/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G491VC/mcu_reg_addresses.h new file mode 100644 index 000000000..67729c156 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G491VC/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G491VC register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G491VC REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G491VE/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G491VE/mcu_reg_addresses.h new file mode 100644 index 000000000..45cd7b68f --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G491VE/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G491VE register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G491VE REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G4A1CE/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G4A1CE/mcu_reg_addresses.h new file mode 100644 index 000000000..7620b1fbe --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G4A1CE/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G4A1CE register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G4A1CE REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G4A1KE/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G4A1KE/mcu_reg_addresses.h new file mode 100644 index 000000000..18f88c288 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G4A1KE/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G4A1KE register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G4A1KE REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G4A1ME/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G4A1ME/mcu_reg_addresses.h new file mode 100644 index 000000000..523c09430 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G4A1ME/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G4A1ME register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G4A1ME REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G4A1RE/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G4A1RE/mcu_reg_addresses.h new file mode 100644 index 000000000..cc0401c4b --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G4A1RE/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G4A1RE register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G4A1RE REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G4A1VE/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G4A1VE/mcu_reg_addresses.h new file mode 100644 index 000000000..10a96772d --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32G4A1VE/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32G4A1VE register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32G4A1VE REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32L4P5AE/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32L4P5AE/mcu_reg_addresses.h new file mode 100644 index 000000000..b0f689385 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32L4P5AE/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32L4P5AE register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32L4P5AE REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32L4P5AG/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32L4P5AG/mcu_reg_addresses.h new file mode 100644 index 000000000..6466a3ae1 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32L4P5AG/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32L4P5AG register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32L4P5AG REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32L4P5CE/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32L4P5CE/mcu_reg_addresses.h new file mode 100644 index 000000000..8db78433f --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32L4P5CE/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32L4P5CE register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32L4P5CE REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32L4P5CG/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32L4P5CG/mcu_reg_addresses.h new file mode 100644 index 000000000..a571675b2 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32L4P5CG/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32L4P5CG register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32L4P5CG REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32L4P5QE/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32L4P5QE/mcu_reg_addresses.h new file mode 100644 index 000000000..c0fb6ae21 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32L4P5QE/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32L4P5QE register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32L4P5QE REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32L4P5QG/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32L4P5QG/mcu_reg_addresses.h new file mode 100644 index 000000000..619638d36 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32L4P5QG/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32L4P5QG register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32L4P5QG REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32L4P5RE/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32L4P5RE/mcu_reg_addresses.h new file mode 100644 index 000000000..e112ec58f --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32L4P5RE/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32L4P5RE register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32L4P5RE REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32L4P5RG/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32L4P5RG/mcu_reg_addresses.h new file mode 100644 index 000000000..4ca983007 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32L4P5RG/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32L4P5RG register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32L4P5RG REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32L4P5VE/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32L4P5VE/mcu_reg_addresses.h new file mode 100644 index 000000000..3b7e9157f --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32L4P5VE/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32L4P5VE register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32L4P5VE REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32L4P5VG/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32L4P5VG/mcu_reg_addresses.h new file mode 100644 index 000000000..ab4529497 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32L4P5VG/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32L4P5VG register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32L4P5VG REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32L4P5ZE/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32L4P5ZE/mcu_reg_addresses.h new file mode 100644 index 000000000..5e5f8df49 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32L4P5ZE/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32L4P5ZE register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32L4P5ZE REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32L4P5ZG/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32L4P5ZG/mcu_reg_addresses.h new file mode 100644 index 000000000..e0bc6b2cc --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32L4P5ZG/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32L4P5ZG register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32L4P5ZG REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32L4Q5AG/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32L4Q5AG/mcu_reg_addresses.h new file mode 100644 index 000000000..a73b011e6 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32L4Q5AG/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32L4Q5AG register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32L4Q5AG REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32L4Q5CG/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32L4Q5CG/mcu_reg_addresses.h new file mode 100644 index 000000000..a06e5306c --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32L4Q5CG/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32L4Q5CG register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32L4Q5CG REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32L4Q5QG/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32L4Q5QG/mcu_reg_addresses.h new file mode 100644 index 000000000..466804071 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32L4Q5QG/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32L4Q5QG register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32L4Q5QG REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32L4Q5RG/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32L4Q5RG/mcu_reg_addresses.h new file mode 100644 index 000000000..82fa9bf95 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32L4Q5RG/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32L4Q5RG register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32L4Q5RG REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32L4Q5VG/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32L4Q5VG/mcu_reg_addresses.h new file mode 100644 index 000000000..9b4033be9 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32L4Q5VG/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32L4Q5VG register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32L4Q5VG REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32L4Q5ZG/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32L4Q5ZG/mcu_reg_addresses.h new file mode 100644 index 000000000..a4276d88f --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/ai_generated/STM32/STM32L4Q5ZG/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details STM32L4Q5ZG register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// STM32L4Q5ZG REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/core/CMakeLists.txt b/targets/arm/mikroe/core/CMakeLists.txt index 924af5b17..36f15fd57 100644 --- a/targets/arm/mikroe/core/CMakeLists.txt +++ b/targets/arm/mikroe/core/CMakeLists.txt @@ -1,71 +1,71 @@ -## ./targets/arm/mikroe/core/CMakeLists.txt -set(hal_ll_core_def_list "") -if(${MCU_NAME} MATCHES "^STM32.*") - set(chip_vendor "stm32") - list(APPEND hal_ll_core_def_list ${chip_vendor}) - string(SUBSTRING ${MCU_NAME} 0 7 STRIPED_MCU_NAME) - list(APPEND hal_ll_core_def_list ${STRIPED_MCU_NAME}xx) - string(SUBSTRING ${MCU_NAME} 6 1 MEMAKE_MCU_NAME_6TH_CHAR) - if (${MEMAKE_MCU_NAME_6TH_CHAR} MATCHES "0") - set(hal_ll_core_source "m0") - list(APPEND hal_ll_core_def_list __cortex_m0__) - elseif ((${MEMAKE_MCU_NAME_6TH_CHAR} MATCHES "1") OR (${MEMAKE_MCU_NAME_6TH_CHAR} MATCHES "2")) - set(hal_ll_core_source "m3") - list(APPEND hal_ll_core_def_list __cortex_m3__) - elseif((${MEMAKE_MCU_NAME_6TH_CHAR} MATCHES "3") OR (${MEMAKE_MCU_NAME_6TH_CHAR} MATCHES "4")) - set(hal_ll_core_source "m4") - list(APPEND hal_ll_core_def_list __cortex_m4__) - elseif(${MEMAKE_MCU_NAME_6TH_CHAR} MATCHES "7") - set(hal_ll_core_source "m7") - list(APPEND hal_ll_core_def_list __cortex_m7__) - else() - list(APPEND hal_ll_core_def_list __cortex_not_supported__) - endif() -elseif(${MCU_NAME} MATCHES "^MK.*") - set(chip_vendor "nxp") - list(APPEND hal_ll_core_def_list ${chip_vendor}) - if((${CORE_NAME} MATCHES "M4EF") OR (${CORE_NAME} MATCHES "M4DSP")) - set(hal_ll_core_source "m4") - list(APPEND hal_ll_core_def_list __cortex_m4__) - elseif(${CORE_NAME} MATCHES "M7") - set(hal_ll_core_source "m7") - list(APPEND hal_ll_core_def_list __cortex_m7__) - else() - list(APPEND hal_ll_core_def_list __cortex_not_supported__) - endif() -elseif(${MCU_NAME} MATCHES "^TM4C.*") - set(chip_vendor "tiva") - list(APPEND hal_ll_core_def_list ${chip_vendor}) - set(hal_ll_core_source "m4") -else() - list(hal_ll_core_def_list __vendor_not_supported__) -endif() - -mikrosdk_add_library(lib_hal_ll_core MikroSDK.HalLowLevelCore - src/hal_ll_core.c - src/${chip_vendor}/${hal_ll_core_source}/hal_ll_core_port.c - - include/hal_ll_core_defines.h - include/hal_ll_core_port.h - include/hal_ll_core.h -) - -target_compile_definitions(lib_hal_ll_core - PUBLIC - ${hal_ll_core_def_list} -) - -target_link_libraries(lib_hal_ll_core PUBLIC - MikroC.Core - MikroSDK.HalLowLevelCommon -) - -target_include_directories(lib_hal_ll_core -PRIVATE - include -INTERFACE - $ - $ -) - -mikrosdk_install(MikroSDK.HalLowLevelCore) +## ./targets/arm/mikroe/core/CMakeLists.txt +set(hal_ll_core_def_list "") +if(${MCU_NAME} MATCHES "^STM32.*") + set(chip_vendor "stm32") + list(APPEND hal_ll_core_def_list ${chip_vendor}) + string(SUBSTRING ${MCU_NAME} 0 7 STRIPED_MCU_NAME) + list(APPEND hal_ll_core_def_list ${STRIPED_MCU_NAME}xx) + string(SUBSTRING ${MCU_NAME} 6 1 MEMAKE_MCU_NAME_6TH_CHAR) + if (${MEMAKE_MCU_NAME_6TH_CHAR} MATCHES "0") + set(hal_ll_core_source "m0") + list(APPEND hal_ll_core_def_list __cortex_m0__) + elseif ((${MEMAKE_MCU_NAME_6TH_CHAR} MATCHES "1") OR (${MEMAKE_MCU_NAME_6TH_CHAR} MATCHES "2")) + set(hal_ll_core_source "m3") + list(APPEND hal_ll_core_def_list __cortex_m3__) + elseif((${MEMAKE_MCU_NAME_6TH_CHAR} MATCHES "3") OR (${MEMAKE_MCU_NAME_6TH_CHAR} MATCHES "4")) + set(hal_ll_core_source "m4") + list(APPEND hal_ll_core_def_list __cortex_m4__) + elseif(${MEMAKE_MCU_NAME_6TH_CHAR} MATCHES "7") + set(hal_ll_core_source "m7") + list(APPEND hal_ll_core_def_list __cortex_m7__) + else() + list(APPEND hal_ll_core_def_list __cortex_not_supported__) + endif() +elseif(${MCU_NAME} MATCHES "^MK.*") + set(chip_vendor "nxp") + list(APPEND hal_ll_core_def_list ${chip_vendor}) + if((${CORE_NAME} MATCHES "M4EF") OR (${CORE_NAME} MATCHES "M4DSP")) + set(hal_ll_core_source "m4") + list(APPEND hal_ll_core_def_list __cortex_m4__) + elseif(${CORE_NAME} MATCHES "M7") + set(hal_ll_core_source "m7") + list(APPEND hal_ll_core_def_list __cortex_m7__) + else() + list(APPEND hal_ll_core_def_list __cortex_not_supported__) + endif() +elseif(${MCU_NAME} MATCHES "^TM4C.*") + set(chip_vendor "tiva") + list(APPEND hal_ll_core_def_list ${chip_vendor}) + set(hal_ll_core_source "m4") +else() + list(hal_ll_core_def_list __vendor_not_supported__) +endif() + +mikrosdk_add_library(lib_hal_ll_core MikroSDK.HalLowLevelCore + src/hal_ll_core.c + src/${chip_vendor}/${hal_ll_core_source}/hal_ll_core_port.c + + include/hal_ll_core_defines.h + include/hal_ll_core_port.h + include/hal_ll_core.h +) + +target_compile_definitions(lib_hal_ll_core + PUBLIC + ${hal_ll_core_def_list} +) + +target_link_libraries(lib_hal_ll_core PUBLIC + MikroC.Core + MikroSDK.HalLowLevelCommon +) + +target_include_directories(lib_hal_ll_core +PRIVATE + include +INTERFACE + $ + $ +) + +mikrosdk_install(MikroSDK.HalLowLevelCore) diff --git a/targets/arm/mikroe/nxp/src/gpio/CMakeLists.txt b/targets/arm/mikroe/nxp/src/gpio/CMakeLists.txt index a9fb56cea..76e1c7b42 100644 --- a/targets/arm/mikroe/nxp/src/gpio/CMakeLists.txt +++ b/targets/arm/mikroe/nxp/src/gpio/CMakeLists.txt @@ -1,64 +1,64 @@ -## ./targets/arm/mikroe/nxp/src/gpio/CMakeLists.txt -set(hal_ll_def_list "") -set(mcu_header_path ${MCU_NAME}) - -find_cortex(hal_ll_def_list) - -list(APPEND hal_ll_def_list ${MCU_NAME}) -string(SUBSTRING ${MCU_NAME} 0 4 MCU_NAME_FIRST_4) -list(APPEND hal_ll_def_list ${MCU_NAME_FIRST_4}) - -if (${MCU_NAME} MATCHES "^MKV4[246]F(.+)$") - list(APPEND hal_ll_def_list "__MKV4X_RCC__") -elseif (${MCU_NAME} MATCHES "^MKV5[68]F(.+)$") - list(APPEND hal_ll_def_list "__MKV5X_RCC__") -elseif (${MCU_NAME} MATCHES "^MK[2568](.+)$") - list(APPEND hal_ll_def_list "__MKX_RCC__") -endif() - -# BEGIN GPIO -list(APPEND hal_ll_def_list "MACRO_USAGE_GPIO") -set(gpio_subimplementation "implementation_1/hal_ll_gpio_port.c") -# END GPIO - -mikrosdk_add_library(lib_hal_ll_gpio MikroSDK.HalLowLevel.GPIO - # BEGIN GPIO - hal_ll_gpio.c - ${gpio_subimplementation} - # END GPIO - ../../include/hal_ll_rcc.h - ../../include/hal_ll_target.h - # BEGIN GPIO - ../../include/gpio/hal_ll_gpio.h - ../../include/gpio/hal_ll_gpio_port.h - ../../include/gpio/hal_ll_gpio_constants.h - # END GPIO -) - -target_compile_definitions(lib_hal_ll_gpio PUBLIC - ${hal_ll_def_list} -) - -target_link_libraries(lib_hal_ll_gpio PUBLIC - MikroC.Core - MikroSDK.HalLowLevelCore - MikroSDK.HalLowLevelCommon -) - -string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) -target_include_directories(lib_hal_ll_gpio - PRIVATE - ../../include - # BEGIN GPIO - ../../include/gpio - # END GPIO - - INTERFACE - $ - $ - $ - $ -) - -mikrosdk_install(MikroSDK.HalLowLevel.GPIO) -install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.GPIO ../../include/gpio/hal_ll_gpio.h ../../include/gpio/hal_ll_gpio_constants.h ../../include/gpio/hal_ll_gpio_port.h) +## ./targets/arm/mikroe/nxp/src/gpio/CMakeLists.txt +set(hal_ll_def_list "") +set(mcu_header_path ${MCU_NAME}) + +find_cortex(hal_ll_def_list) + +list(APPEND hal_ll_def_list ${MCU_NAME}) +string(SUBSTRING ${MCU_NAME} 0 4 MCU_NAME_FIRST_4) +list(APPEND hal_ll_def_list ${MCU_NAME_FIRST_4}) + +if (${MCU_NAME} MATCHES "^MKV4[246]F(.+)$") + list(APPEND hal_ll_def_list "__MKV4X_RCC__") +elseif (${MCU_NAME} MATCHES "^MKV5[68]F(.+)$") + list(APPEND hal_ll_def_list "__MKV5X_RCC__") +elseif (${MCU_NAME} MATCHES "^MK[2568](.+)$") + list(APPEND hal_ll_def_list "__MKX_RCC__") +endif() + +# BEGIN GPIO +list(APPEND hal_ll_def_list "MACRO_USAGE_GPIO") +set(gpio_subimplementation "implementation_1/hal_ll_gpio_port.c") +# END GPIO + +mikrosdk_add_library(lib_hal_ll_gpio MikroSDK.HalLowLevel.GPIO + # BEGIN GPIO + hal_ll_gpio.c + ${gpio_subimplementation} + # END GPIO + ../../include/hal_ll_rcc.h + ../../include/hal_ll_target.h + # BEGIN GPIO + ../../include/gpio/hal_ll_gpio.h + ../../include/gpio/hal_ll_gpio_port.h + ../../include/gpio/hal_ll_gpio_constants.h + # END GPIO +) + +target_compile_definitions(lib_hal_ll_gpio PUBLIC + ${hal_ll_def_list} +) + +target_link_libraries(lib_hal_ll_gpio PUBLIC + MikroC.Core + MikroSDK.HalLowLevelCore + MikroSDK.HalLowLevelCommon +) + +string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) +target_include_directories(lib_hal_ll_gpio + PRIVATE + ../../include + # BEGIN GPIO + ../../include/gpio + # END GPIO + + INTERFACE + $ + $ + $ + $ +) + +mikrosdk_install(MikroSDK.HalLowLevel.GPIO) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.GPIO ../../include/gpio/hal_ll_gpio.h ../../include/gpio/hal_ll_gpio_constants.h ../../include/gpio/hal_ll_gpio_port.h) diff --git a/targets/arm/mikroe/nxp/src/hal_ll/CMakeLists.txt b/targets/arm/mikroe/nxp/src/hal_ll/CMakeLists.txt index 9f4bca7d5..93a06627f 100644 --- a/targets/arm/mikroe/nxp/src/hal_ll/CMakeLists.txt +++ b/targets/arm/mikroe/nxp/src/hal_ll/CMakeLists.txt @@ -1,15 +1,15 @@ -## ./targets/arm/mikroe/nxp/src/hal_ll/CMakeLists.txt -add_library(lib_hal_ll INTERFACE) - -add_library(MikroSDK.HalLowLevel ALIAS lib_hal_ll) - -set(module_list "") -set(module_list_supported "") -set_module_support(module_list module_list_supported ${MCU_NAME} "hal_ll_layer") - -target_link_libraries(lib_hal_ll INTERFACE - ${module_list} -) - -mikrosdk_install(MikroSDK.HalLowLevel) -install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel ../../include/hal_ll_rcc.h ../../include/hal_ll_target.h ../../include/hal_ll_pin_names.h ../../include/hal_ll_target_names.h) +## ./targets/arm/mikroe/nxp/src/hal_ll/CMakeLists.txt +add_library(lib_hal_ll INTERFACE) + +add_library(MikroSDK.HalLowLevel ALIAS lib_hal_ll) + +set(module_list "") +set(module_list_supported "") +set_module_support(module_list module_list_supported ${MCU_NAME} "hal_ll_layer") + +target_link_libraries(lib_hal_ll INTERFACE + ${module_list} +) + +mikrosdk_install(MikroSDK.HalLowLevel) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel ../../include/hal_ll_rcc.h ../../include/hal_ll_target.h ../../include/hal_ll_pin_names.h ../../include/hal_ll_target_names.h) diff --git a/targets/arm/mikroe/nxp/src/i2c/CMakeLists.txt b/targets/arm/mikroe/nxp/src/i2c/CMakeLists.txt index 6904277e8..abc00de44 100644 --- a/targets/arm/mikroe/nxp/src/i2c/CMakeLists.txt +++ b/targets/arm/mikroe/nxp/src/i2c/CMakeLists.txt @@ -1,87 +1,87 @@ -## ./targets/arm/mikroe/nxp/src/i2c/CMakeLists.txt -set(mcu_header_path ${MCU_NAME}) - -find_cortex(hal_ll_def_list) - -list(APPEND hal_ll_def_list ${MCU_NAME}) -string(SUBSTRING ${MCU_NAME} 0 4 MCU_NAME_FIRST_4) -list(APPEND hal_ll_def_list ${MCU_NAME_FIRST_4}) - -if (${MCU_NAME} MATCHES "^MKV4[246]F(.+)$") - list(APPEND hal_ll_def_list "__MKV4X_RCC__") -elseif (${MCU_NAME} MATCHES "^MKV5[68]F(.+)$") - list(APPEND hal_ll_def_list "__MKV5X_RCC__") -elseif (${MCU_NAME} MATCHES "^MK[2568](.+)$") - list(APPEND hal_ll_def_list "__MKX_RCC__") -endif() - -## BEGIN I2C -list(APPEND hal_ll_def_list "MACRO_USAGE_I2C") -set(i2c_subimplementation "implementation_1/hal_ll_i2c_master.c") -set(i2c_pin_map "hal_ll_i2c_pin_map") - -if (${MCU_NAME} MATCHES "^MKV(.+)$") - list(APPEND hal_ll_def_list "HAL_LL_RCC_CLOCK_OUTPUT") -endif() -if (${MCU_NAME} MATCHES "^MK([V]|6[456])(.+)$") - list(APPEND hal_ll_def_list "I2C_MASTER_CHIP_SELECT") -endif() -if (${MCU_NAME} MATCHES "^MK64(.+)$") - list(APPEND hal_ll_def_list "I2C_MASTER_CHIP_SELECT_MK64") -endif() - -## END I2C - -# TSC2003 Special case -if (NOT DEFINED _MSDK_TFT_TP_) - list(APPEND hal_ll_def_list "__TFT_NON_TSC2003__") -else() - if (${_MSDK_TFT_TP_} MATCHES "__TP_TSC2003__") - list(APPEND hal_ll_def_list "__TFT_RESISTIVE_TSC2003__") - else() - list(APPEND hal_ll_def_list "__TFT_NON_TSC2003__") - endif() -endif() - -mikrosdk_add_library(lib_hal_ll_i2c_master MikroSDK.HalLowLevel.I2C.Master - ${i2c_subimplementation} - - ../../include/hal_ll_rcc.h - ../../include/hal_ll_target.h -# BEGIN I2C - ../../include/i2c/hal_ll_i2c_master.h - ../../include/i2c/${i2c_pin_map}/hal_ll_i2c_pin_map.h -# END I2C -) - -target_compile_definitions(lib_hal_ll_i2c_master PUBLIC - ${hal_ll_def_list} -) - -target_link_libraries(lib_hal_ll_i2c_master PUBLIC - MikroC.Core - MikroSDK.HalLowLevelCore - MikroSDK.HalLowLevelCommon -) - -string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) -target_include_directories(lib_hal_ll_i2c_master - PRIVATE - ../../include - ../../include/gpio - # BEGIN I2C - ../../include/i2c - ../../include/i2c/${i2c_pin_map} - # END I2C - - INTERFACE - $ - $ - $ - $ - $ - $ - ) - -mikrosdk_install(MikroSDK.HalLowLevel.I2C.Master) -install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.I2C.Master ../../include/i2c/hal_ll_i2c_master.h) +## ./targets/arm/mikroe/nxp/src/i2c/CMakeLists.txt +set(mcu_header_path ${MCU_NAME}) + +find_cortex(hal_ll_def_list) + +list(APPEND hal_ll_def_list ${MCU_NAME}) +string(SUBSTRING ${MCU_NAME} 0 4 MCU_NAME_FIRST_4) +list(APPEND hal_ll_def_list ${MCU_NAME_FIRST_4}) + +if (${MCU_NAME} MATCHES "^MKV4[246]F(.+)$") + list(APPEND hal_ll_def_list "__MKV4X_RCC__") +elseif (${MCU_NAME} MATCHES "^MKV5[68]F(.+)$") + list(APPEND hal_ll_def_list "__MKV5X_RCC__") +elseif (${MCU_NAME} MATCHES "^MK[2568](.+)$") + list(APPEND hal_ll_def_list "__MKX_RCC__") +endif() + +## BEGIN I2C +list(APPEND hal_ll_def_list "MACRO_USAGE_I2C") +set(i2c_subimplementation "implementation_1/hal_ll_i2c_master.c") +set(i2c_pin_map "hal_ll_i2c_pin_map") + +if (${MCU_NAME} MATCHES "^MKV(.+)$") + list(APPEND hal_ll_def_list "HAL_LL_RCC_CLOCK_OUTPUT") +endif() +if (${MCU_NAME} MATCHES "^MK([V]|6[456])(.+)$") + list(APPEND hal_ll_def_list "I2C_MASTER_CHIP_SELECT") +endif() +if (${MCU_NAME} MATCHES "^MK64(.+)$") + list(APPEND hal_ll_def_list "I2C_MASTER_CHIP_SELECT_MK64") +endif() + +## END I2C + +# TSC2003 Special case +if (NOT DEFINED _MSDK_TFT_TP_) + list(APPEND hal_ll_def_list "__TFT_NON_TSC2003__") +else() + if (${_MSDK_TFT_TP_} MATCHES "__TP_TSC2003__") + list(APPEND hal_ll_def_list "__TFT_RESISTIVE_TSC2003__") + else() + list(APPEND hal_ll_def_list "__TFT_NON_TSC2003__") + endif() +endif() + +mikrosdk_add_library(lib_hal_ll_i2c_master MikroSDK.HalLowLevel.I2C.Master + ${i2c_subimplementation} + + ../../include/hal_ll_rcc.h + ../../include/hal_ll_target.h +# BEGIN I2C + ../../include/i2c/hal_ll_i2c_master.h + ../../include/i2c/${i2c_pin_map}/hal_ll_i2c_pin_map.h +# END I2C +) + +target_compile_definitions(lib_hal_ll_i2c_master PUBLIC + ${hal_ll_def_list} +) + +target_link_libraries(lib_hal_ll_i2c_master PUBLIC + MikroC.Core + MikroSDK.HalLowLevelCore + MikroSDK.HalLowLevelCommon +) + +string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) +target_include_directories(lib_hal_ll_i2c_master + PRIVATE + ../../include + ../../include/gpio + # BEGIN I2C + ../../include/i2c + ../../include/i2c/${i2c_pin_map} + # END I2C + + INTERFACE + $ + $ + $ + $ + $ + $ + ) + +mikrosdk_install(MikroSDK.HalLowLevel.I2C.Master) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.I2C.Master ../../include/i2c/hal_ll_i2c_master.h) diff --git a/targets/arm/mikroe/nxp/src/one_wire/CMakeLists.txt b/targets/arm/mikroe/nxp/src/one_wire/CMakeLists.txt index e9c11541e..3cd6cf882 100644 --- a/targets/arm/mikroe/nxp/src/one_wire/CMakeLists.txt +++ b/targets/arm/mikroe/nxp/src/one_wire/CMakeLists.txt @@ -1,31 +1,31 @@ -## ./targets/arm/mikroe/nxp/src/one_wire/CMakeLists.txt -set(hal_ll_def_list "") -list(APPEND hal_ll_def_list "MACRO_USAGE_ONE_WIRE") - -mikrosdk_add_library(lib_hal_ll_one_wire MikroSDK.HalLowLevel.OneWire - hal_ll_one_wire.c - - ../../include/one_wire/hal_ll_one_wire.h) - -target_compile_definitions(lib_hal_ll_one_wire PUBLIC - ${hal_ll_def_list} -) - -target_link_libraries(lib_hal_ll_one_wire PUBLIC - MikroC.Core - MikroSDK.HalLowLevel.GPIO - MikroSDK.HalLowLevelCommon -) - -target_include_directories(lib_hal_ll_one_wire - PRIVATE - ../../include/one_wire - INTERFACE - $ - $ - $ - $ -) - -mikrosdk_install(MikroSDK.HalLowLevel.OneWire) -install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.OneWire ../../include/one_wire/hal_ll_one_wire.h) +## ./targets/arm/mikroe/nxp/src/one_wire/CMakeLists.txt +set(hal_ll_def_list "") +list(APPEND hal_ll_def_list "MACRO_USAGE_ONE_WIRE") + +mikrosdk_add_library(lib_hal_ll_one_wire MikroSDK.HalLowLevel.OneWire + hal_ll_one_wire.c + + ../../include/one_wire/hal_ll_one_wire.h) + +target_compile_definitions(lib_hal_ll_one_wire PUBLIC + ${hal_ll_def_list} +) + +target_link_libraries(lib_hal_ll_one_wire PUBLIC + MikroC.Core + MikroSDK.HalLowLevel.GPIO + MikroSDK.HalLowLevelCommon +) + +target_include_directories(lib_hal_ll_one_wire + PRIVATE + ../../include/one_wire + INTERFACE + $ + $ + $ + $ +) + +mikrosdk_install(MikroSDK.HalLowLevel.OneWire) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.OneWire ../../include/one_wire/hal_ll_one_wire.h) diff --git a/targets/arm/mikroe/nxp/src/spi_master/CMakeLists.txt b/targets/arm/mikroe/nxp/src/spi_master/CMakeLists.txt index ad310257b..06bddd056 100644 --- a/targets/arm/mikroe/nxp/src/spi_master/CMakeLists.txt +++ b/targets/arm/mikroe/nxp/src/spi_master/CMakeLists.txt @@ -1,71 +1,71 @@ -## ./targets/arm/mikroe/nxp/src/spi_master/CMakeLists.txt -set(hal_ll_def_list "") -set(MCU_NAME_FIRST_4 "") -set(mcu_header_path ${MCU_NAME}) - -find_cortex(hal_ll_def_list) - -list(APPEND hal_ll_def_list ${MCU_NAME}) -string(SUBSTRING ${MCU_NAME} 0 4 MCU_NAME_FIRST_4) -list(APPEND hal_ll_def_list ${MCU_NAME_FIRST_4}) - -if (${MCU_NAME} MATCHES "^MKV4[246]F(.+)$") - list(APPEND hal_ll_def_list "__MKV4X_RCC__") -elseif (${MCU_NAME} MATCHES "^MKV5[68]F(.+)$") - list(APPEND hal_ll_def_list "__MKV5X_RCC__") -elseif (${MCU_NAME} MATCHES "^MK[2568](.+)$") - list(APPEND hal_ll_def_list "__MKX_RCC__") -endif() - -# BEGIN SPI -list(APPEND hal_ll_def_list "MACRO_USAGE_SPI") - -if (${MCU_NAME} MATCHES "^MKV(.+)$") - list(APPEND hal_ll_def_list "HAL_LL_RCC_CLOCK_OUTPUT") -endif() - -set( spi_subimplementation "implementation_1/hal_ll_spi_master.c" ) -set( spi_pin_map "hal_ll_spi_master_pin_map" ) -# END SPI - -mikrosdk_add_library(lib_hal_ll_spi_master MikroSDK.HalLowLevel.SPI.Master - ${spi_subimplementation} - - ../../include/hal_ll_rcc.h - ../../include/hal_ll_target.h - # BEGIN SPI - ../../include/spi_master/hal_ll_spi_master.h - ../../include/spi_master/${spi_pin_map}/hal_ll_spi_master_pin_map.h - # END SPI -) - -target_compile_definitions(lib_hal_ll_spi_master PUBLIC - ${hal_ll_def_list} -) - -target_link_libraries(lib_hal_ll_spi_master PUBLIC - MikroC.Core - MikroSDK.HalLowLevelCore - MikroSDK.HalLowLevelCommon -) - -string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) -target_include_directories(lib_hal_ll_spi_master - PRIVATE - ../../include - ../../include/gpio - # BEGIN SPI - ../../include/spi_master - ../../include/spi_master/${spi_pin_map} - # END SPI - INTERFACE - $ - $ - $ - $ - $ - $ -) - -mikrosdk_install(MikroSDK.HalLowLevel.SPI.Master) -install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.SPI.Master ../../include/spi_master/hal_ll_spi_master.h) +## ./targets/arm/mikroe/nxp/src/spi_master/CMakeLists.txt +set(hal_ll_def_list "") +set(MCU_NAME_FIRST_4 "") +set(mcu_header_path ${MCU_NAME}) + +find_cortex(hal_ll_def_list) + +list(APPEND hal_ll_def_list ${MCU_NAME}) +string(SUBSTRING ${MCU_NAME} 0 4 MCU_NAME_FIRST_4) +list(APPEND hal_ll_def_list ${MCU_NAME_FIRST_4}) + +if (${MCU_NAME} MATCHES "^MKV4[246]F(.+)$") + list(APPEND hal_ll_def_list "__MKV4X_RCC__") +elseif (${MCU_NAME} MATCHES "^MKV5[68]F(.+)$") + list(APPEND hal_ll_def_list "__MKV5X_RCC__") +elseif (${MCU_NAME} MATCHES "^MK[2568](.+)$") + list(APPEND hal_ll_def_list "__MKX_RCC__") +endif() + +# BEGIN SPI +list(APPEND hal_ll_def_list "MACRO_USAGE_SPI") + +if (${MCU_NAME} MATCHES "^MKV(.+)$") + list(APPEND hal_ll_def_list "HAL_LL_RCC_CLOCK_OUTPUT") +endif() + +set( spi_subimplementation "implementation_1/hal_ll_spi_master.c" ) +set( spi_pin_map "hal_ll_spi_master_pin_map" ) +# END SPI + +mikrosdk_add_library(lib_hal_ll_spi_master MikroSDK.HalLowLevel.SPI.Master + ${spi_subimplementation} + + ../../include/hal_ll_rcc.h + ../../include/hal_ll_target.h + # BEGIN SPI + ../../include/spi_master/hal_ll_spi_master.h + ../../include/spi_master/${spi_pin_map}/hal_ll_spi_master_pin_map.h + # END SPI +) + +target_compile_definitions(lib_hal_ll_spi_master PUBLIC + ${hal_ll_def_list} +) + +target_link_libraries(lib_hal_ll_spi_master PUBLIC + MikroC.Core + MikroSDK.HalLowLevelCore + MikroSDK.HalLowLevelCommon +) + +string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) +target_include_directories(lib_hal_ll_spi_master + PRIVATE + ../../include + ../../include/gpio + # BEGIN SPI + ../../include/spi_master + ../../include/spi_master/${spi_pin_map} + # END SPI + INTERFACE + $ + $ + $ + $ + $ + $ +) + +mikrosdk_install(MikroSDK.HalLowLevel.SPI.Master) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.SPI.Master ../../include/spi_master/hal_ll_spi_master.h) diff --git a/targets/arm/mikroe/nxp/src/tim/CMakeLists.txt b/targets/arm/mikroe/nxp/src/tim/CMakeLists.txt index cf6c3672b..f8e8a30ba 100644 --- a/targets/arm/mikroe/nxp/src/tim/CMakeLists.txt +++ b/targets/arm/mikroe/nxp/src/tim/CMakeLists.txt @@ -1,74 +1,74 @@ -## ./targets/arm/mikroe/nxp/src/tim/CMakeLists.txt -set(hal_ll_def_list "") -set(MCU_NAME_FIRST_4 "") -set(mcu_header_path ${MCU_NAME}) - -find_cortex(hal_ll_def_list) - -list(APPEND hal_ll_def_list ${MCU_NAME}) -string(SUBSTRING ${MCU_NAME} 0 4 MCU_NAME_FIRST_4) -list(APPEND hal_ll_def_list ${MCU_NAME_FIRST_4}) - -if (${MCU_NAME} MATCHES "^MKV4[246]F(.+)$") - list(APPEND hal_ll_def_list "__MKV4X_RCC__") -elseif (${MCU_NAME} MATCHES "^MKV5[68]F(.+)$") - list(APPEND hal_ll_def_list "__MKV5X_RCC__") -elseif (${MCU_NAME} MATCHES "^MK[2568](.+)$") - list(APPEND hal_ll_def_list "__MKX_RCC__") -endif() - -# BEGIN TIM -list(APPEND hal_ll_def_list "MACRO_USAGE_TIM") - -if (${MCU_NAME} MATCHES "^MKV(.+)$") - list(APPEND hal_ll_def_list "HAL_LL_RCC_CLOCK_OUTPUT") - list(APPEND hal_ll_def_list "__mkv__") -elseif (${MCU_NAME} MATCHES "^MK[2456](.+)$") - list(APPEND hal_ll_def_list "__mk__") -endif() - -set( tim_subimplementation "implementation_1/hal_ll_tim.c" ) -set( tim_pin_map "hal_ll_tim_pin_map" ) -# END TIM - -mikrosdk_add_library(lib_hal_ll_tim MikroSDK.HalLowLevel.TIM - ${tim_subimplementation} - - ../../include/hal_ll_rcc.h - ../../include/hal_ll_target.h - # BEGIN TIM - ../../include/tim/hal_ll_tim.h - ../../include/tim/${tim_pin_map}/hal_ll_tim_pin_map.h - # END TIM -) - -target_compile_definitions(lib_hal_ll_tim PUBLIC - ${hal_ll_def_list} -) - -target_link_libraries(lib_hal_ll_tim PUBLIC - MikroC.Core - MikroSDK.HalLowLevelCore - MikroSDK.HalLowLevelCommon -) - -string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) -target_include_directories(lib_hal_ll_tim - PRIVATE - ../../include - ../../include/gpio - # BEGIN TIM - ../../include/tim - ../../include/tim/${tim_pin_map} - # END TIM - INTERFACE - $ - $ - $ - $ - $ - $ -) - -mikrosdk_install(MikroSDK.HalLowLevel.TIM) -install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.TIM ../../include/tim/hal_ll_tim.h) +## ./targets/arm/mikroe/nxp/src/tim/CMakeLists.txt +set(hal_ll_def_list "") +set(MCU_NAME_FIRST_4 "") +set(mcu_header_path ${MCU_NAME}) + +find_cortex(hal_ll_def_list) + +list(APPEND hal_ll_def_list ${MCU_NAME}) +string(SUBSTRING ${MCU_NAME} 0 4 MCU_NAME_FIRST_4) +list(APPEND hal_ll_def_list ${MCU_NAME_FIRST_4}) + +if (${MCU_NAME} MATCHES "^MKV4[246]F(.+)$") + list(APPEND hal_ll_def_list "__MKV4X_RCC__") +elseif (${MCU_NAME} MATCHES "^MKV5[68]F(.+)$") + list(APPEND hal_ll_def_list "__MKV5X_RCC__") +elseif (${MCU_NAME} MATCHES "^MK[2568](.+)$") + list(APPEND hal_ll_def_list "__MKX_RCC__") +endif() + +# BEGIN TIM +list(APPEND hal_ll_def_list "MACRO_USAGE_TIM") + +if (${MCU_NAME} MATCHES "^MKV(.+)$") + list(APPEND hal_ll_def_list "HAL_LL_RCC_CLOCK_OUTPUT") + list(APPEND hal_ll_def_list "__mkv__") +elseif (${MCU_NAME} MATCHES "^MK[2456](.+)$") + list(APPEND hal_ll_def_list "__mk__") +endif() + +set( tim_subimplementation "implementation_1/hal_ll_tim.c" ) +set( tim_pin_map "hal_ll_tim_pin_map" ) +# END TIM + +mikrosdk_add_library(lib_hal_ll_tim MikroSDK.HalLowLevel.TIM + ${tim_subimplementation} + + ../../include/hal_ll_rcc.h + ../../include/hal_ll_target.h + # BEGIN TIM + ../../include/tim/hal_ll_tim.h + ../../include/tim/${tim_pin_map}/hal_ll_tim_pin_map.h + # END TIM +) + +target_compile_definitions(lib_hal_ll_tim PUBLIC + ${hal_ll_def_list} +) + +target_link_libraries(lib_hal_ll_tim PUBLIC + MikroC.Core + MikroSDK.HalLowLevelCore + MikroSDK.HalLowLevelCommon +) + +string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) +target_include_directories(lib_hal_ll_tim + PRIVATE + ../../include + ../../include/gpio + # BEGIN TIM + ../../include/tim + ../../include/tim/${tim_pin_map} + # END TIM + INTERFACE + $ + $ + $ + $ + $ + $ +) + +mikrosdk_install(MikroSDK.HalLowLevel.TIM) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.TIM ../../include/tim/hal_ll_tim.h) diff --git a/targets/arm/mikroe/stm32/src/adc/CMakeLists.txt b/targets/arm/mikroe/stm32/src/adc/CMakeLists.txt index 75fbb2c1d..cc9b1be82 100644 --- a/targets/arm/mikroe/stm32/src/adc/CMakeLists.txt +++ b/targets/arm/mikroe/stm32/src/adc/CMakeLists.txt @@ -1,85 +1,85 @@ -## ./targets/arm/mikroe/stm32/src/adc/CMakeLists.txt -set(hal_ll_def_list "") -set(MEMAKE_MCU_NAME_FIRST_7 "") -set(mcu_header_path "") - -find_cortex(hal_ll_def_list) - -list(APPEND hal_ll_def_list ${MCU_NAME}) - -find_mcu_header_path(hal_ll_def_list mcu_header_path MEMAKE_MCU_NAME_FIRST_7) - -##BEGINADC -list(APPEND hal_ll_def_list "MACRO_USAGE_ADC") -list(APPEND hal_ll_def_list "HAL_LL_ADC_RESOLUTION_CMAKE=HAL_LL_ADC_RESOLUTION_12_BIT") -string(SUBSTRING ${MCU_NAME} 0 8 MEMAKE_MCU_NAME_FIRST_8) - -if ((${MEMAKE_MCU_NAME_FIRST_7} MATCHES "STM32F2") OR (${MEMAKE_MCU_NAME_FIRST_7} MATCHES "STM32F4") OR - (${MEMAKE_MCU_NAME_FIRST_7} MATCHES "STM32F7")) - set(adc_subimplementation "implementation_1/subimplementation_1/hal_ll_adc.c") - set(adc_pin_map "hal_ll_adc_pin_map/implementation_1/subimplementation_1") -elseif (${MEMAKE_MCU_NAME_FIRST_7} MATCHES "STM32L4") - set(adc_subimplementation "implementation_1/subimplementation_2/hal_ll_adc.c") - set(adc_pin_map "hal_ll_adc_pin_map/implementation_1/subimplementation_2") -elseif ((${MEMAKE_MCU_NAME_FIRST_7} MATCHES "STM32F1") OR (${MEMAKE_MCU_NAME_FIRST_8} MATCHES "STM32F37")) - set(adc_subimplementation "implementation_4/subimplementation_1/hal_ll_adc.c") - set(adc_pin_map "hal_ll_adc_pin_map/implementation_4/subimplementation_1") -elseif (${MEMAKE_MCU_NAME_FIRST_7} MATCHES "STM32F3") - set(adc_subimplementation "implementation_1/subimplementation_3/hal_ll_adc.c") - set(adc_pin_map "hal_ll_adc_pin_map/implementation_1/subimplementation_3") -elseif (${MEMAKE_MCU_NAME_FIRST_7} MATCHES "STM32H7") - set(adc_subimplementation "implementation_2/hal_ll_adc.c") - set(adc_pin_map "hal_ll_adc_pin_map/implementation_2") -elseif ((${MEMAKE_MCU_NAME_FIRST_7} MATCHES "STM32F0") OR (${MEMAKE_MCU_NAME_FIRST_7} MATCHES "STM32L0")) - set(adc_subimplementation "implementation_3/subimplementation_1/hal_ll_adc.c") - set(adc_pin_map "hal_ll_adc_pin_map/implementation_3/subimplementation_1") -elseif (${MEMAKE_MCU_NAME_FIRST_7} MATCHES "STM32G0") - set(adc_subimplementation "implementation_3/subimplementation_2/hal_ll_adc.c") - set(adc_pin_map "hal_ll_adc_pin_map/implementation_3/subimplementation_2") -elseif (${MEMAKE_MCU_NAME_FIRST_7} MATCHES "STM32L1") - set(adc_subimplementation "implementation_4/subimplementation_2/hal_ll_adc.c") - set(adc_pin_map "hal_ll_adc_pin_map/implementation_4/subimplementation_2") -endif() -##ENDADC - -mikrosdk_add_library(lib_hal_ll_adc MikroSDK.HalLowLevel.ADC - ${adc_subimplementation} - ../../include/hal_ll_rcc.h - ../../include/hal_ll_target.h -#BEGINADC - ../../include/adc/hal_ll_adc.h - ../../include/adc/${adc_pin_map}/hal_ll_adc_pin_map.h -#ENDADC -) - -target_compile_definitions(lib_hal_ll_adc PUBLIC - ${hal_ll_def_list} -) - -target_link_libraries(lib_hal_ll_adc PUBLIC - MikroC.Core - MikroSDK.HalLowLevelCore - MikroSDK.HalLowLevelCommon -) -string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) -target_include_directories(lib_hal_ll_adc - PRIVATE - ../../include - ../../include/gpio - #BEGINADC - ../../include/adc - ../../include/adc/${adc_pin_map} - #ENDADC - INTERFACE - $ - $ - $ - $ - - $ - $ -) - -mikrosdk_install(MikroSDK.HalLowLevel.ADC) - -install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.ADC ../../include/adc/hal_ll_adc.h) +## ./targets/arm/mikroe/stm32/src/adc/CMakeLists.txt +set(hal_ll_def_list "") +set(MEMAKE_MCU_NAME_FIRST_7 "") +set(mcu_header_path "") + +find_cortex(hal_ll_def_list) + +list(APPEND hal_ll_def_list ${MCU_NAME}) + +find_mcu_header_path(hal_ll_def_list mcu_header_path MEMAKE_MCU_NAME_FIRST_7) + +##BEGINADC +list(APPEND hal_ll_def_list "MACRO_USAGE_ADC") +list(APPEND hal_ll_def_list "HAL_LL_ADC_RESOLUTION_CMAKE=HAL_LL_ADC_RESOLUTION_12_BIT") +string(SUBSTRING ${MCU_NAME} 0 8 MEMAKE_MCU_NAME_FIRST_8) + +if ((${MEMAKE_MCU_NAME_FIRST_7} MATCHES "STM32F2") OR (${MEMAKE_MCU_NAME_FIRST_7} MATCHES "STM32F4") OR + (${MEMAKE_MCU_NAME_FIRST_7} MATCHES "STM32F7")) + set(adc_subimplementation "implementation_1/subimplementation_1/hal_ll_adc.c") + set(adc_pin_map "hal_ll_adc_pin_map/implementation_1/subimplementation_1") +elseif (${MEMAKE_MCU_NAME_FIRST_7} MATCHES "STM32L4") + set(adc_subimplementation "implementation_1/subimplementation_2/hal_ll_adc.c") + set(adc_pin_map "hal_ll_adc_pin_map/implementation_1/subimplementation_2") +elseif ((${MEMAKE_MCU_NAME_FIRST_7} MATCHES "STM32F1") OR (${MEMAKE_MCU_NAME_FIRST_8} MATCHES "STM32F37")) + set(adc_subimplementation "implementation_4/subimplementation_1/hal_ll_adc.c") + set(adc_pin_map "hal_ll_adc_pin_map/implementation_4/subimplementation_1") +elseif (${MEMAKE_MCU_NAME_FIRST_7} MATCHES "STM32F3") + set(adc_subimplementation "implementation_1/subimplementation_3/hal_ll_adc.c") + set(adc_pin_map "hal_ll_adc_pin_map/implementation_1/subimplementation_3") +elseif (${MEMAKE_MCU_NAME_FIRST_7} MATCHES "STM32H7") + set(adc_subimplementation "implementation_2/hal_ll_adc.c") + set(adc_pin_map "hal_ll_adc_pin_map/implementation_2") +elseif ((${MEMAKE_MCU_NAME_FIRST_7} MATCHES "STM32F0") OR (${MEMAKE_MCU_NAME_FIRST_7} MATCHES "STM32L0")) + set(adc_subimplementation "implementation_3/subimplementation_1/hal_ll_adc.c") + set(adc_pin_map "hal_ll_adc_pin_map/implementation_3/subimplementation_1") +elseif (${MEMAKE_MCU_NAME_FIRST_7} MATCHES "STM32G0") + set(adc_subimplementation "implementation_3/subimplementation_2/hal_ll_adc.c") + set(adc_pin_map "hal_ll_adc_pin_map/implementation_3/subimplementation_2") +elseif (${MEMAKE_MCU_NAME_FIRST_7} MATCHES "STM32L1") + set(adc_subimplementation "implementation_4/subimplementation_2/hal_ll_adc.c") + set(adc_pin_map "hal_ll_adc_pin_map/implementation_4/subimplementation_2") +endif() +##ENDADC + +mikrosdk_add_library(lib_hal_ll_adc MikroSDK.HalLowLevel.ADC + ${adc_subimplementation} + ../../include/hal_ll_rcc.h + ../../include/hal_ll_target.h +#BEGINADC + ../../include/adc/hal_ll_adc.h + ../../include/adc/${adc_pin_map}/hal_ll_adc_pin_map.h +#ENDADC +) + +target_compile_definitions(lib_hal_ll_adc PUBLIC + ${hal_ll_def_list} +) + +target_link_libraries(lib_hal_ll_adc PUBLIC + MikroC.Core + MikroSDK.HalLowLevelCore + MikroSDK.HalLowLevelCommon +) +string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) +target_include_directories(lib_hal_ll_adc + PRIVATE + ../../include + ../../include/gpio + #BEGINADC + ../../include/adc + ../../include/adc/${adc_pin_map} + #ENDADC + INTERFACE + $ + $ + $ + $ + + $ + $ +) + +mikrosdk_install(MikroSDK.HalLowLevel.ADC) + +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.ADC ../../include/adc/hal_ll_adc.h) diff --git a/targets/arm/mikroe/stm32/src/gpio/CMakeLists.txt b/targets/arm/mikroe/stm32/src/gpio/CMakeLists.txt index 20a962261..a9e06dfea 100644 --- a/targets/arm/mikroe/stm32/src/gpio/CMakeLists.txt +++ b/targets/arm/mikroe/stm32/src/gpio/CMakeLists.txt @@ -1,62 +1,62 @@ -## ./targets/arm/mikroe/stm32/src/gpio/CMakeLists.txt -set(hal_ll_def_list "") -set(MEMAKE_MCU_NAME_FIRST_7 "") -set(mcu_header_path "") - -find_cortex(hal_ll_def_list) - -list(APPEND hal_ll_def_list ${MCU_NAME}) -list(APPEND hal_ll_def_list "MACRO_USAGE_GPIO") -find_mcu_header_path(hal_ll_def_list mcu_header_path MEMAKE_MCU_NAME_FIRST_7) - -## BEGIN GPIO -if(${MEMAKE_MCU_NAME_FIRST_7} MATCHES "STM32F1") - list(APPEND hal_ll_def_list __hal_ll_gpio_subset_2__) - set(gpio_subimplementation "implementation_2/hal_ll_gpio_port.c") -else() - list(APPEND hal_ll_def_list __hal_ll_gpio_subset_1__) - set(gpio_subimplementation "implementation_1/hal_ll_gpio_port.c") -endif() -## END GPIO - -mikrosdk_add_library(lib_hal_ll_gpio MikroSDK.HalLowLevel.GPIO - # BEGIN GPIO - hal_ll_gpio.c - ${gpio_subimplementation} - # END GPIO - ../../include/hal_ll_rcc.h - ../../include/hal_ll_target.h - # BEGIN GPIO - ../../include/gpio/hal_ll_gpio.h - ../../include/gpio/hal_ll_gpio_port.h - ../../include/gpio/hal_ll_gpio_constants.h - # END GPIO - -) - -target_compile_definitions(lib_hal_ll_gpio PUBLIC - ${hal_ll_def_list} -) - -target_link_libraries(lib_hal_ll_gpio PUBLIC - MikroC.Core - MikroSDK.HalLowLevelCore - MikroSDK.HalLowLevelCommon -) -string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) -target_include_directories(lib_hal_ll_gpio - PRIVATE - ../../include - # BEGIN GPIO - ../../include/gpio - # END GPIO - - INTERFACE - $ - $ - $ - $ -) - -mikrosdk_install(MikroSDK.HalLowLevel.GPIO) -install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.GPIO ../../include/gpio/hal_ll_gpio.h ../../include/gpio/hal_ll_gpio_constants.h ../../include/gpio/hal_ll_gpio_port.h) +## ./targets/arm/mikroe/stm32/src/gpio/CMakeLists.txt +set(hal_ll_def_list "") +set(MEMAKE_MCU_NAME_FIRST_7 "") +set(mcu_header_path "") + +find_cortex(hal_ll_def_list) + +list(APPEND hal_ll_def_list ${MCU_NAME}) +list(APPEND hal_ll_def_list "MACRO_USAGE_GPIO") +find_mcu_header_path(hal_ll_def_list mcu_header_path MEMAKE_MCU_NAME_FIRST_7) + +## BEGIN GPIO +if(${MEMAKE_MCU_NAME_FIRST_7} MATCHES "STM32F1") + list(APPEND hal_ll_def_list __hal_ll_gpio_subset_2__) + set(gpio_subimplementation "implementation_2/hal_ll_gpio_port.c") +else() + list(APPEND hal_ll_def_list __hal_ll_gpio_subset_1__) + set(gpio_subimplementation "implementation_1/hal_ll_gpio_port.c") +endif() +## END GPIO + +mikrosdk_add_library(lib_hal_ll_gpio MikroSDK.HalLowLevel.GPIO + # BEGIN GPIO + hal_ll_gpio.c + ${gpio_subimplementation} + # END GPIO + ../../include/hal_ll_rcc.h + ../../include/hal_ll_target.h + # BEGIN GPIO + ../../include/gpio/hal_ll_gpio.h + ../../include/gpio/hal_ll_gpio_port.h + ../../include/gpio/hal_ll_gpio_constants.h + # END GPIO + +) + +target_compile_definitions(lib_hal_ll_gpio PUBLIC + ${hal_ll_def_list} +) + +target_link_libraries(lib_hal_ll_gpio PUBLIC + MikroC.Core + MikroSDK.HalLowLevelCore + MikroSDK.HalLowLevelCommon +) +string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) +target_include_directories(lib_hal_ll_gpio + PRIVATE + ../../include + # BEGIN GPIO + ../../include/gpio + # END GPIO + + INTERFACE + $ + $ + $ + $ +) + +mikrosdk_install(MikroSDK.HalLowLevel.GPIO) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.GPIO ../../include/gpio/hal_ll_gpio.h ../../include/gpio/hal_ll_gpio_constants.h ../../include/gpio/hal_ll_gpio_port.h) diff --git a/targets/arm/mikroe/stm32/src/hal_ll/CMakeLists.txt b/targets/arm/mikroe/stm32/src/hal_ll/CMakeLists.txt index 8ce1b4a40..a8bc860e8 100644 --- a/targets/arm/mikroe/stm32/src/hal_ll/CMakeLists.txt +++ b/targets/arm/mikroe/stm32/src/hal_ll/CMakeLists.txt @@ -1,15 +1,15 @@ -## ./targets/arm/mikroe/stm32/src/hal_ll/CMakeLists.txt -add_library(lib_hal_ll INTERFACE) - -add_library(MikroSDK.HalLowLevel ALIAS lib_hal_ll) - -set(module_list "") -set(module_list_supported "") -set_module_support(module_list module_list_supported ${MCU_NAME} "hal_ll_layer") - -target_link_libraries(lib_hal_ll INTERFACE - ${module_list} -) - -mikrosdk_install(MikroSDK.HalLowLevel) -install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel ../../include/hal_ll_rcc.h ../../include/hal_ll_target.h ../../include/hal_ll_pin_names.h ../../include/hal_ll_target_names.h) +## ./targets/arm/mikroe/stm32/src/hal_ll/CMakeLists.txt +add_library(lib_hal_ll INTERFACE) + +add_library(MikroSDK.HalLowLevel ALIAS lib_hal_ll) + +set(module_list "") +set(module_list_supported "") +set_module_support(module_list module_list_supported ${MCU_NAME} "hal_ll_layer") + +target_link_libraries(lib_hal_ll INTERFACE + ${module_list} +) + +mikrosdk_install(MikroSDK.HalLowLevel) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel ../../include/hal_ll_rcc.h ../../include/hal_ll_target.h ../../include/hal_ll_pin_names.h ../../include/hal_ll_target_names.h) diff --git a/targets/arm/mikroe/stm32/src/i2c/CMakeLists.txt b/targets/arm/mikroe/stm32/src/i2c/CMakeLists.txt index 34ced2ba6..f42cfc345 100644 --- a/targets/arm/mikroe/stm32/src/i2c/CMakeLists.txt +++ b/targets/arm/mikroe/stm32/src/i2c/CMakeLists.txt @@ -1,77 +1,77 @@ -## ./targets/arm/mikroe/stm32/src/i2c/CMakeLists.txt -set(hal_ll_def_list "") -set(MEMAKE_MCU_NAME_FIRST_7 "") -set(mcu_header_path "") - -find_cortex(hal_ll_def_list) - -find_mcu_header_path(hal_ll_def_list mcu_header_path MEMAKE_MCU_NAME_FIRST_7) -## BEGIN I2C -list(APPEND hal_ll_def_list "MACRO_USAGE_I2C") - -if((${MEMAKE_MCU_NAME_FIRST_7} MATCHES "STM32F1") OR -(${MEMAKE_MCU_NAME_FIRST_7} MATCHES "STM32L1") OR -(${MEMAKE_MCU_NAME_FIRST_7} MATCHES "STM32F2") OR -(${MEMAKE_MCU_NAME_FIRST_7} MATCHES "STM32F4")) - set(i2c_subimplementation "implementation_1/hal_ll_i2c_master.c") - set(i2c_pin_map "hal_ll_i2c_pin_map/implementation_1") -else() - set(i2c_subimplementation "implementation_2/hal_ll_i2c_master.c") - set(i2c_pin_map "hal_ll_i2c_pin_map/implementation_2") -endif() - -if (${MCU_NAME} MATCHES "(^STM32F10[13](.+)$)") - list(APPEND hal_ll_def_list __STM32F101_103_ERRATA__) -endif() - -if (NOT DEFINED _MSDK_TFT_TP_) - list(APPEND hal_ll_def_list "__TFT_NON_TSC2003__") -else() - if (${_MSDK_TFT_TP_} MATCHES "__TP_TSC2003__") - list(APPEND hal_ll_def_list "__TFT_RESISTIVE_TSC2003__") - else() - list(APPEND hal_ll_def_list "__TFT_NON_TSC2003__") - endif() -endif() - -mikrosdk_add_library(lib_hal_ll_i2c_master MikroSDK.HalLowLevel.I2C.Master - ${i2c_subimplementation} - - ../../include/hal_ll_rcc.h - ../../include/hal_ll_target.h -# BEGIN I2C - ../../include/i2c/hal_ll_i2c_master.h - ../../include/i2c/${i2c_pin_map}/hal_ll_i2c_pin_map.h -# END I2C -) - -target_compile_definitions(lib_hal_ll_i2c_master PUBLIC - ${hal_ll_def_list} -) - -target_link_libraries(lib_hal_ll_i2c_master PUBLIC - MikroC.Core - MikroSDK.HalLowLevelCore - MikroSDK.HalLowLevelCommon -) -string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) -target_include_directories(lib_hal_ll_i2c_master - PRIVATE - ../../include - ../../include/gpio -# BEGIN I2C - ../../include/i2c - ../../include/i2c/${i2c_pin_map} -# END I2C - - INTERFACE - $ - $ - $ - $ - $ - $ -) - -mikrosdk_install(MikroSDK.HalLowLevel.I2C.Master) -install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.I2C.Master ../../include/i2c/hal_ll_i2c_master.h) +## ./targets/arm/mikroe/stm32/src/i2c/CMakeLists.txt +set(hal_ll_def_list "") +set(MEMAKE_MCU_NAME_FIRST_7 "") +set(mcu_header_path "") + +find_cortex(hal_ll_def_list) + +find_mcu_header_path(hal_ll_def_list mcu_header_path MEMAKE_MCU_NAME_FIRST_7) +## BEGIN I2C +list(APPEND hal_ll_def_list "MACRO_USAGE_I2C") + +if((${MEMAKE_MCU_NAME_FIRST_7} MATCHES "STM32F1") OR +(${MEMAKE_MCU_NAME_FIRST_7} MATCHES "STM32L1") OR +(${MEMAKE_MCU_NAME_FIRST_7} MATCHES "STM32F2") OR +(${MEMAKE_MCU_NAME_FIRST_7} MATCHES "STM32F4")) + set(i2c_subimplementation "implementation_1/hal_ll_i2c_master.c") + set(i2c_pin_map "hal_ll_i2c_pin_map/implementation_1") +else() + set(i2c_subimplementation "implementation_2/hal_ll_i2c_master.c") + set(i2c_pin_map "hal_ll_i2c_pin_map/implementation_2") +endif() + +if (${MCU_NAME} MATCHES "(^STM32F10[13](.+)$)") + list(APPEND hal_ll_def_list __STM32F101_103_ERRATA__) +endif() + +if (NOT DEFINED _MSDK_TFT_TP_) + list(APPEND hal_ll_def_list "__TFT_NON_TSC2003__") +else() + if (${_MSDK_TFT_TP_} MATCHES "__TP_TSC2003__") + list(APPEND hal_ll_def_list "__TFT_RESISTIVE_TSC2003__") + else() + list(APPEND hal_ll_def_list "__TFT_NON_TSC2003__") + endif() +endif() + +mikrosdk_add_library(lib_hal_ll_i2c_master MikroSDK.HalLowLevel.I2C.Master + ${i2c_subimplementation} + + ../../include/hal_ll_rcc.h + ../../include/hal_ll_target.h +# BEGIN I2C + ../../include/i2c/hal_ll_i2c_master.h + ../../include/i2c/${i2c_pin_map}/hal_ll_i2c_pin_map.h +# END I2C +) + +target_compile_definitions(lib_hal_ll_i2c_master PUBLIC + ${hal_ll_def_list} +) + +target_link_libraries(lib_hal_ll_i2c_master PUBLIC + MikroC.Core + MikroSDK.HalLowLevelCore + MikroSDK.HalLowLevelCommon +) +string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) +target_include_directories(lib_hal_ll_i2c_master + PRIVATE + ../../include + ../../include/gpio +# BEGIN I2C + ../../include/i2c + ../../include/i2c/${i2c_pin_map} +# END I2C + + INTERFACE + $ + $ + $ + $ + $ + $ +) + +mikrosdk_install(MikroSDK.HalLowLevel.I2C.Master) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.I2C.Master ../../include/i2c/hal_ll_i2c_master.h) diff --git a/targets/arm/mikroe/stm32/src/one_wire/CMakeLists.txt b/targets/arm/mikroe/stm32/src/one_wire/CMakeLists.txt index 2cbc874f1..125aa7244 100644 --- a/targets/arm/mikroe/stm32/src/one_wire/CMakeLists.txt +++ b/targets/arm/mikroe/stm32/src/one_wire/CMakeLists.txt @@ -1,31 +1,31 @@ -## ./targets/arm/mikroe/stm32/src/one_wire/CMakeLists.txt -set(hal_ll_def_list) -list(APPEND hal_ll_def_list "MACRO_USAGE_ONE_WIRE") - -mikrosdk_add_library(lib_hal_ll_one_wire MikroSDK.HalLowLevel.OneWire - hal_ll_one_wire.c - - ../../include/one_wire/hal_ll_one_wire.h -) - -target_compile_definitions(lib_hal_ll_one_wire PUBLIC - ${hal_ll_def_list} -) - -target_link_libraries(lib_hal_ll_one_wire PUBLIC - MikroC.Core - MikroSDK.HalLowLevel.GPIO - MikroSDK.HalLowLevelCommon -) -target_include_directories(lib_hal_ll_one_wire - PRIVATE - ../../include/one_wire - INTERFACE - $ - $ - $ - $ -) - -mikrosdk_install(MikroSDK.HalLowLevel.OneWire) -install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.OneWire ../../include/one_wire/hal_ll_one_wire.h) +## ./targets/arm/mikroe/stm32/src/one_wire/CMakeLists.txt +set(hal_ll_def_list) +list(APPEND hal_ll_def_list "MACRO_USAGE_ONE_WIRE") + +mikrosdk_add_library(lib_hal_ll_one_wire MikroSDK.HalLowLevel.OneWire + hal_ll_one_wire.c + + ../../include/one_wire/hal_ll_one_wire.h +) + +target_compile_definitions(lib_hal_ll_one_wire PUBLIC + ${hal_ll_def_list} +) + +target_link_libraries(lib_hal_ll_one_wire PUBLIC + MikroC.Core + MikroSDK.HalLowLevel.GPIO + MikroSDK.HalLowLevelCommon +) +target_include_directories(lib_hal_ll_one_wire + PRIVATE + ../../include/one_wire + INTERFACE + $ + $ + $ + $ +) + +mikrosdk_install(MikroSDK.HalLowLevel.OneWire) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.OneWire ../../include/one_wire/hal_ll_one_wire.h) diff --git a/targets/arm/mikroe/stm32/src/spi_master/CMakeLists.txt b/targets/arm/mikroe/stm32/src/spi_master/CMakeLists.txt index ea04a7b1a..f10d60847 100644 --- a/targets/arm/mikroe/stm32/src/spi_master/CMakeLists.txt +++ b/targets/arm/mikroe/stm32/src/spi_master/CMakeLists.txt @@ -1,59 +1,59 @@ -## ./targets/arm/mikroe/stm32/src/spi_master/CMakeLists.txt -set(hal_ll_def_list "") -set(MEMAKE_MCU_NAME_FIRST_7 "") -set(mcu_header_path "") - -find_cortex(hal_ll_def_list) - -find_mcu_header_path(hal_ll_def_list mcu_header_path MEMAKE_MCU_NAME_FIRST_7) - -if (${MEMAKE_MCU_NAME_FIRST_7} MATCHES "STM32H7") - set(spi_subimplementation "implementation_2/hal_ll_spi_master.c") - set(spi_pin_map "hal_ll_spi_master_pin_map/implementation_2") -else() - set(spi_subimplementation "implementation_1/hal_ll_spi_master.c") - set(spi_pin_map "hal_ll_spi_master_pin_map/implementation_1") -endif() -list(APPEND hal_ll_def_list "MACRO_USAGE_SPI") - -mikrosdk_add_library(lib_hal_ll_spi_master MikroSDK.HalLowLevel.SPI.Master - ${spi_subimplementation} - - ../../include/hal_ll_rcc.h - ../../include/hal_ll_target.h -# BEGIN SPI - ../../include/spi_master/hal_ll_spi_master.h - ../../include/spi_master/${spi_pin_map}/hal_ll_spi_master_pin_map.h -# END SPI -) - -target_compile_definitions(lib_hal_ll_spi_master PUBLIC - ${hal_ll_def_list} -) - -target_link_libraries(lib_hal_ll_spi_master PUBLIC - MikroC.Core - MikroSDK.HalLowLevelCore - MikroSDK.HalLowLevelCommon -) -string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) -target_include_directories(lib_hal_ll_spi_master - PRIVATE - ../../include - ../../include/gpio -# BEGIN SPI - ../../include/spi_master - ../../include/spi_master/${spi_pin_map} -# END SPI - - INTERFACE - $ - $ - $ - $ - $ - $ -) - -mikrosdk_install(MikroSDK.HalLowLevel.SPI.Master) -install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.SPI.Master ../../include/spi_master/hal_ll_spi_master.h) +## ./targets/arm/mikroe/stm32/src/spi_master/CMakeLists.txt +set(hal_ll_def_list "") +set(MEMAKE_MCU_NAME_FIRST_7 "") +set(mcu_header_path "") + +find_cortex(hal_ll_def_list) + +find_mcu_header_path(hal_ll_def_list mcu_header_path MEMAKE_MCU_NAME_FIRST_7) + +if (${MEMAKE_MCU_NAME_FIRST_7} MATCHES "STM32H7") + set(spi_subimplementation "implementation_2/hal_ll_spi_master.c") + set(spi_pin_map "hal_ll_spi_master_pin_map/implementation_2") +else() + set(spi_subimplementation "implementation_1/hal_ll_spi_master.c") + set(spi_pin_map "hal_ll_spi_master_pin_map/implementation_1") +endif() +list(APPEND hal_ll_def_list "MACRO_USAGE_SPI") + +mikrosdk_add_library(lib_hal_ll_spi_master MikroSDK.HalLowLevel.SPI.Master + ${spi_subimplementation} + + ../../include/hal_ll_rcc.h + ../../include/hal_ll_target.h +# BEGIN SPI + ../../include/spi_master/hal_ll_spi_master.h + ../../include/spi_master/${spi_pin_map}/hal_ll_spi_master_pin_map.h +# END SPI +) + +target_compile_definitions(lib_hal_ll_spi_master PUBLIC + ${hal_ll_def_list} +) + +target_link_libraries(lib_hal_ll_spi_master PUBLIC + MikroC.Core + MikroSDK.HalLowLevelCore + MikroSDK.HalLowLevelCommon +) +string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) +target_include_directories(lib_hal_ll_spi_master + PRIVATE + ../../include + ../../include/gpio +# BEGIN SPI + ../../include/spi_master + ../../include/spi_master/${spi_pin_map} +# END SPI + + INTERFACE + $ + $ + $ + $ + $ + $ +) + +mikrosdk_install(MikroSDK.HalLowLevel.SPI.Master) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.SPI.Master ../../include/spi_master/hal_ll_spi_master.h) diff --git a/targets/arm/mikroe/stm32/src/tim/CMakeLists.txt b/targets/arm/mikroe/stm32/src/tim/CMakeLists.txt index 890a0442d..a3dc16815 100644 --- a/targets/arm/mikroe/stm32/src/tim/CMakeLists.txt +++ b/targets/arm/mikroe/stm32/src/tim/CMakeLists.txt @@ -1,63 +1,63 @@ -## ./targets/arm/mikroe/stm32/src/tim/CMakeLists.txt -set(hal_ll_def_list "") -set(MEMAKE_MCU_NAME_FIRST_7 "") -set(mcu_header_path "") - -find_cortex(hal_ll_def_list) - -find_mcu_header_path(hal_ll_def_list mcu_header_path MEMAKE_MCU_NAME_FIRST_7) - -## BEGIN TIM -if ((${MEMAKE_MCU_NAME_FIRST_7} MATCHES "STM32L1") OR (${MEMAKE_MCU_NAME_FIRST_7} MATCHES "STM32F2") OR - (${MEMAKE_MCU_NAME_FIRST_7} MATCHES "STM32F4") OR (${MEMAKE_MCU_NAME_FIRST_7} MATCHES "STM32F7") OR - (${MEMAKE_MCU_NAME_FIRST_7} MATCHES "STM32H7")) - set(tim_subimplementation "implementation_1/hal_ll_tim.c") - set(tim_pin_map "hal_ll_tim_pin_map/implementation_1") -else() - set(tim_subimplementation "implementation_2/hal_ll_tim.c") - set(tim_pin_map "hal_ll_tim_pin_map/implementation_2") -endif() -## END TIM - -list(APPEND hal_ll_def_list "MACRO_USAGE_TIM") - -mikrosdk_add_library(lib_hal_ll_tim MikroSDK.HalLowLevel.TIM - ${tim_subimplementation} - - ../../include/hal_ll_rcc.h - ../../include/hal_ll_target.h -# BEGIN TIM - ../../include/tim/hal_ll_tim.h - ../../include/tim/${tim_pin_map}/hal_ll_tim_pin_map.h -# END TIM -) - -target_compile_definitions(lib_hal_ll_tim PUBLIC - ${hal_ll_def_list} -) - -target_link_libraries(lib_hal_ll_tim PUBLIC - MikroC.Core - MikroSDK.HalLowLevelCore - MikroSDK.HalLowLevelCommon -) -string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) -target_include_directories(lib_hal_ll_tim - PRIVATE - ../../include - ../../include/gpio -:: BEGIN TIM - ../../include/tim - ../../include/tim/${tim_pin_map} -:: END TIM - - INTERFACE - $ - $ - $ - $ - $ -) - -mikrosdk_install(MikroSDK.HalLowLevel.TIM) -install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.TIM ../../include/tim/hal_ll_tim.h) +## ./targets/arm/mikroe/stm32/src/tim/CMakeLists.txt +set(hal_ll_def_list "") +set(MEMAKE_MCU_NAME_FIRST_7 "") +set(mcu_header_path "") + +find_cortex(hal_ll_def_list) + +find_mcu_header_path(hal_ll_def_list mcu_header_path MEMAKE_MCU_NAME_FIRST_7) + +## BEGIN TIM +if ((${MEMAKE_MCU_NAME_FIRST_7} MATCHES "STM32L1") OR (${MEMAKE_MCU_NAME_FIRST_7} MATCHES "STM32F2") OR + (${MEMAKE_MCU_NAME_FIRST_7} MATCHES "STM32F4") OR (${MEMAKE_MCU_NAME_FIRST_7} MATCHES "STM32F7") OR + (${MEMAKE_MCU_NAME_FIRST_7} MATCHES "STM32H7")) + set(tim_subimplementation "implementation_1/hal_ll_tim.c") + set(tim_pin_map "hal_ll_tim_pin_map/implementation_1") +else() + set(tim_subimplementation "implementation_2/hal_ll_tim.c") + set(tim_pin_map "hal_ll_tim_pin_map/implementation_2") +endif() +## END TIM + +list(APPEND hal_ll_def_list "MACRO_USAGE_TIM") + +mikrosdk_add_library(lib_hal_ll_tim MikroSDK.HalLowLevel.TIM + ${tim_subimplementation} + + ../../include/hal_ll_rcc.h + ../../include/hal_ll_target.h +# BEGIN TIM + ../../include/tim/hal_ll_tim.h + ../../include/tim/${tim_pin_map}/hal_ll_tim_pin_map.h +# END TIM +) + +target_compile_definitions(lib_hal_ll_tim PUBLIC + ${hal_ll_def_list} +) + +target_link_libraries(lib_hal_ll_tim PUBLIC + MikroC.Core + MikroSDK.HalLowLevelCore + MikroSDK.HalLowLevelCommon +) +string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) +target_include_directories(lib_hal_ll_tim + PRIVATE + ../../include + ../../include/gpio +:: BEGIN TIM + ../../include/tim + ../../include/tim/${tim_pin_map} +:: END TIM + + INTERFACE + $ + $ + $ + $ + $ +) + +mikrosdk_install(MikroSDK.HalLowLevel.TIM) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.TIM ../../include/tim/hal_ll_tim.h) diff --git a/targets/arm/mikroe/stm32/src/uart/CMakeLists.txt b/targets/arm/mikroe/stm32/src/uart/CMakeLists.txt index 792a3f5fe..1b966b9d1 100644 --- a/targets/arm/mikroe/stm32/src/uart/CMakeLists.txt +++ b/targets/arm/mikroe/stm32/src/uart/CMakeLists.txt @@ -1,63 +1,63 @@ -## ./targets/arm/mikroe/stm32/src/uart/CMakeLists.txt -set(hal_ll_def_list "") -set(MEMAKE_MCU_NAME_FIRST_7 "") -set(mcu_header_path "") - -find_cortex(hal_ll_def_list) - -find_mcu_header_path(hal_ll_def_list mcu_header_path MEMAKE_MCU_NAME_FIRST_7) - -## BEGIN UART -if ((${MEMAKE_MCU_NAME_FIRST_7} MATCHES "STM32F1") OR (${MEMAKE_MCU_NAME_FIRST_7} MATCHES "STM32L1") OR - (${MEMAKE_MCU_NAME_FIRST_7} MATCHES "STM32F2") OR (${MEMAKE_MCU_NAME_FIRST_7} MATCHES "STM32F4")) - set(uart_subimplementation "implementation_1/hal_ll_uart.c") - set(uart_pin_map "hal_ll_uart_pin_map/implementation_1") -else() - set(uart_subimplementation "implementation_2/hal_ll_uart.c") - set(uart_pin_map "hal_ll_uart_pin_map/implementation_2") -endif() -## END UART - -list(APPEND hal_ll_def_list "MACRO_USAGE_UART") - -mikrosdk_add_library(lib_hal_ll_uart MikroSDK.HalLowLevel.UART - ${uart_subimplementation} - - ../../include/hal_ll_rcc.h - ../../include/hal_ll_target.h -# BEGIN UART - ../../include/uart/hal_ll_uart.h - ../../include/uart/${uart_pin_map}/hal_ll_uart_pin_map.h -# END UART -) - -target_compile_definitions(lib_hal_ll_uart PUBLIC - ${hal_ll_def_list} -) - -target_link_libraries(lib_hal_ll_uart PUBLIC - MikroC.Core - MikroSDK.HalLowLevelCore - MikroSDK.HalLowLevelCommon -) -string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) -target_include_directories(lib_hal_ll_uart - PRIVATE - ../../include - ../../include/gpio - # BEGIN UART - ../../include/uart - ../../include/uart/${uart_pin_map} - # END UART - - INTERFACE - $ - $ - $ - $ - $ - $ -) - -mikrosdk_install(MikroSDK.HalLowLevel.UART) -install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.UART ../../include/uart/hal_ll_uart.h) +## ./targets/arm/mikroe/stm32/src/uart/CMakeLists.txt +set(hal_ll_def_list "") +set(MEMAKE_MCU_NAME_FIRST_7 "") +set(mcu_header_path "") + +find_cortex(hal_ll_def_list) + +find_mcu_header_path(hal_ll_def_list mcu_header_path MEMAKE_MCU_NAME_FIRST_7) + +## BEGIN UART +if ((${MEMAKE_MCU_NAME_FIRST_7} MATCHES "STM32F1") OR (${MEMAKE_MCU_NAME_FIRST_7} MATCHES "STM32L1") OR + (${MEMAKE_MCU_NAME_FIRST_7} MATCHES "STM32F2") OR (${MEMAKE_MCU_NAME_FIRST_7} MATCHES "STM32F4")) + set(uart_subimplementation "implementation_1/hal_ll_uart.c") + set(uart_pin_map "hal_ll_uart_pin_map/implementation_1") +else() + set(uart_subimplementation "implementation_2/hal_ll_uart.c") + set(uart_pin_map "hal_ll_uart_pin_map/implementation_2") +endif() +## END UART + +list(APPEND hal_ll_def_list "MACRO_USAGE_UART") + +mikrosdk_add_library(lib_hal_ll_uart MikroSDK.HalLowLevel.UART + ${uart_subimplementation} + + ../../include/hal_ll_rcc.h + ../../include/hal_ll_target.h +# BEGIN UART + ../../include/uart/hal_ll_uart.h + ../../include/uart/${uart_pin_map}/hal_ll_uart_pin_map.h +# END UART +) + +target_compile_definitions(lib_hal_ll_uart PUBLIC + ${hal_ll_def_list} +) + +target_link_libraries(lib_hal_ll_uart PUBLIC + MikroC.Core + MikroSDK.HalLowLevelCore + MikroSDK.HalLowLevelCommon +) +string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) +target_include_directories(lib_hal_ll_uart + PRIVATE + ../../include + ../../include/gpio + # BEGIN UART + ../../include/uart + ../../include/uart/${uart_pin_map} + # END UART + + INTERFACE + $ + $ + $ + $ + $ + $ +) + +mikrosdk_install(MikroSDK.HalLowLevel.UART) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.UART ../../include/uart/hal_ll_uart.h) diff --git a/targets/arm/mikroe/tiva/src/adc/CMakeLists.txt b/targets/arm/mikroe/tiva/src/adc/CMakeLists.txt index aaaba8e2c..f146c6a31 100644 --- a/targets/arm/mikroe/tiva/src/adc/CMakeLists.txt +++ b/targets/arm/mikroe/tiva/src/adc/CMakeLists.txt @@ -1,62 +1,62 @@ -## ./targets/arm/mikroe/tiva/src/adc/CMakeLists.txt -set(hal_ll_def_list "") -set(mcu_header_path ${MCU_NAME}) - -find_cortex(hal_ll_def_list) - -list(APPEND hal_ll_def_list ${MCU_NAME}) - -if (${CORE_NAME} EQUAL "M4EF") - list(APPEND hal_ll_def_list "__cortex_m4_fpu__") -else() - list(APPEND hal_ll_def_list "__cortex_not_supported__") -endif() - -# BEGIN ADC -list(APPEND hal_ll_def_list "MACRO_USAGE_ADC") -list(APPEND hal_ll_def_list "HAL_LL_ADC_RESOLUTION_CMAKE=HAL_LL_ADC_RESOLUTION_12_BIT") -set(adc_subimplementation "implementation_1/hal_ll_adc.c") -set(adc_pin_map "hal_ll_adc_pin_map/implementation_1") -# END ADC - -mikrosdk_add_library(lib_hal_ll_adc MikroSDK.HalLowLevel.ADC - ${adc_subimplementation} - ../../include/hal_ll_rcc.h - ../../include/hal_ll_target.h -#BEGIN ADC - ../../include/adc/hal_ll_adc.h - ../../include/adc/${adc_pin_map}/hal_ll_adc_pin_map.h -#END ADC -) - -target_compile_definitions(lib_hal_ll_adc PUBLIC - ${hal_ll_def_list} -) - -target_link_libraries(lib_hal_ll_adc PUBLIC - MikroC.Core - MikroSDK.HalLowLevelCore - MikroSDK.HalLowLevelCommon -) - -string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) -target_include_directories(lib_hal_ll_adc - PRIVATE - ../../include - ../../include/gpio - #BEGINADC - ../../include/adc - ../../include/adc/${adc_pin_map} - #ENDADC - INTERFACE - $ - $ - $ - $ - - $ - $ -) - -mikrosdk_install(MikroSDK.HalLowLevel.ADC) -install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.ADC ../../include/adc/hal_ll_adc.h) +## ./targets/arm/mikroe/tiva/src/adc/CMakeLists.txt +set(hal_ll_def_list "") +set(mcu_header_path ${MCU_NAME}) + +find_cortex(hal_ll_def_list) + +list(APPEND hal_ll_def_list ${MCU_NAME}) + +if (${CORE_NAME} EQUAL "M4EF") + list(APPEND hal_ll_def_list "__cortex_m4_fpu__") +else() + list(APPEND hal_ll_def_list "__cortex_not_supported__") +endif() + +# BEGIN ADC +list(APPEND hal_ll_def_list "MACRO_USAGE_ADC") +list(APPEND hal_ll_def_list "HAL_LL_ADC_RESOLUTION_CMAKE=HAL_LL_ADC_RESOLUTION_12_BIT") +set(adc_subimplementation "implementation_1/hal_ll_adc.c") +set(adc_pin_map "hal_ll_adc_pin_map/implementation_1") +# END ADC + +mikrosdk_add_library(lib_hal_ll_adc MikroSDK.HalLowLevel.ADC + ${adc_subimplementation} + ../../include/hal_ll_rcc.h + ../../include/hal_ll_target.h +#BEGIN ADC + ../../include/adc/hal_ll_adc.h + ../../include/adc/${adc_pin_map}/hal_ll_adc_pin_map.h +#END ADC +) + +target_compile_definitions(lib_hal_ll_adc PUBLIC + ${hal_ll_def_list} +) + +target_link_libraries(lib_hal_ll_adc PUBLIC + MikroC.Core + MikroSDK.HalLowLevelCore + MikroSDK.HalLowLevelCommon +) + +string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) +target_include_directories(lib_hal_ll_adc + PRIVATE + ../../include + ../../include/gpio + #BEGINADC + ../../include/adc + ../../include/adc/${adc_pin_map} + #ENDADC + INTERFACE + $ + $ + $ + $ + + $ + $ +) + +mikrosdk_install(MikroSDK.HalLowLevel.ADC) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.ADC ../../include/adc/hal_ll_adc.h) diff --git a/targets/arm/mikroe/tiva/src/gpio/CMakeLists.txt b/targets/arm/mikroe/tiva/src/gpio/CMakeLists.txt index 4f9ca2313..101edda17 100644 --- a/targets/arm/mikroe/tiva/src/gpio/CMakeLists.txt +++ b/targets/arm/mikroe/tiva/src/gpio/CMakeLists.txt @@ -1,63 +1,63 @@ -## ./targets/arm/mikroe/tiva/src/gpio/CMakeLists.txt -set(hal_ll_def_list "") -set(MCU_NAME_FIRST_7 "") -set(mcu_header_path ${MCU_NAME}) - -find_cortex(hal_ll_def_list) - -list(APPEND hal_ll_def_list ${MCU_NAME}) -string(SUBSTRING ${MCU_NAME} 0 7 MCU_NAME_FIRST_7) -list(APPEND hal_ll_def_list ${MCU_NAME_FIRST_7}) - -if (${CORE_NAME} EQUAL "M4EF") - list(APPEND hal_ll_def_list "__cortex_m4_fpu__") -else() - list(APPEND hal_ll_def_list "__cortex_not_supported__") -endif() - -# BEGIN GPIO -list(APPEND hal_ll_def_list "MACRO_USAGE_GPIO") -set(gpio_subimplementation "implementation_1/hal_ll_gpio_port.c") -# END GPIO - -mikrosdk_add_library(lib_hal_ll_gpio MikroSDK.HalLowLevel.GPIO - # BEGIN GPIO - hal_ll_gpio.c - ${gpio_subimplementation} - # END GPIO - ../../include/hal_ll_rcc.h - ../../include/hal_ll_target.h - # BEGIN GPIO - ../../include/gpio/hal_ll_gpio.h - ../../include/gpio/hal_ll_gpio_port.h - ../../include/gpio/hal_ll_gpio_constants.h - # END GPIO -) - -target_compile_definitions(lib_hal_ll_gpio PUBLIC - ${hal_ll_def_list} -) - -target_link_libraries(lib_hal_ll_gpio PUBLIC - MikroC.Core - MikroSDK.HalLowLevelCore - MikroSDK.HalLowLevelCommon -) - -string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) -target_include_directories(lib_hal_ll_gpio - PRIVATE - ../../include - # BEGIN GPIO - ../../include/gpio - # END GPIO - - INTERFACE - $ - $ - $ - $ -) - -mikrosdk_install(MikroSDK.HalLowLevel.GPIO) -install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.GPIO ../../include/gpio/hal_ll_gpio.h ../../include/gpio/hal_ll_gpio_constants.h ../../include/gpio/hal_ll_gpio_port.h) +## ./targets/arm/mikroe/tiva/src/gpio/CMakeLists.txt +set(hal_ll_def_list "") +set(MCU_NAME_FIRST_7 "") +set(mcu_header_path ${MCU_NAME}) + +find_cortex(hal_ll_def_list) + +list(APPEND hal_ll_def_list ${MCU_NAME}) +string(SUBSTRING ${MCU_NAME} 0 7 MCU_NAME_FIRST_7) +list(APPEND hal_ll_def_list ${MCU_NAME_FIRST_7}) + +if (${CORE_NAME} EQUAL "M4EF") + list(APPEND hal_ll_def_list "__cortex_m4_fpu__") +else() + list(APPEND hal_ll_def_list "__cortex_not_supported__") +endif() + +# BEGIN GPIO +list(APPEND hal_ll_def_list "MACRO_USAGE_GPIO") +set(gpio_subimplementation "implementation_1/hal_ll_gpio_port.c") +# END GPIO + +mikrosdk_add_library(lib_hal_ll_gpio MikroSDK.HalLowLevel.GPIO + # BEGIN GPIO + hal_ll_gpio.c + ${gpio_subimplementation} + # END GPIO + ../../include/hal_ll_rcc.h + ../../include/hal_ll_target.h + # BEGIN GPIO + ../../include/gpio/hal_ll_gpio.h + ../../include/gpio/hal_ll_gpio_port.h + ../../include/gpio/hal_ll_gpio_constants.h + # END GPIO +) + +target_compile_definitions(lib_hal_ll_gpio PUBLIC + ${hal_ll_def_list} +) + +target_link_libraries(lib_hal_ll_gpio PUBLIC + MikroC.Core + MikroSDK.HalLowLevelCore + MikroSDK.HalLowLevelCommon +) + +string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) +target_include_directories(lib_hal_ll_gpio + PRIVATE + ../../include + # BEGIN GPIO + ../../include/gpio + # END GPIO + + INTERFACE + $ + $ + $ + $ +) + +mikrosdk_install(MikroSDK.HalLowLevel.GPIO) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.GPIO ../../include/gpio/hal_ll_gpio.h ../../include/gpio/hal_ll_gpio_constants.h ../../include/gpio/hal_ll_gpio_port.h) diff --git a/targets/arm/mikroe/tiva/src/hal_ll/CMakeLists.txt b/targets/arm/mikroe/tiva/src/hal_ll/CMakeLists.txt index 53c4def8e..219b13c6a 100644 --- a/targets/arm/mikroe/tiva/src/hal_ll/CMakeLists.txt +++ b/targets/arm/mikroe/tiva/src/hal_ll/CMakeLists.txt @@ -1,15 +1,15 @@ -## ./targets/arm/mikroe/tiva/src/hal_ll/CMakeLists.txt -add_library(lib_hal_ll INTERFACE) - -add_library(MikroSDK.HalLowLevel ALIAS lib_hal_ll) - -set(module_list "") -set(module_list_supported "") -set_module_support(module_list module_list_supported ${MCU_NAME} "hal_ll_layer") - -target_link_libraries(lib_hal_ll INTERFACE - ${module_list} -) - -mikrosdk_install(MikroSDK.HalLowLevel) -install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel ../../include/hal_ll_rcc.h ../../include/hal_ll_target.h ../../include/hal_ll_pin_names.h ../../include/hal_ll_target_names.h) +## ./targets/arm/mikroe/tiva/src/hal_ll/CMakeLists.txt +add_library(lib_hal_ll INTERFACE) + +add_library(MikroSDK.HalLowLevel ALIAS lib_hal_ll) + +set(module_list "") +set(module_list_supported "") +set_module_support(module_list module_list_supported ${MCU_NAME} "hal_ll_layer") + +target_link_libraries(lib_hal_ll INTERFACE + ${module_list} +) + +mikrosdk_install(MikroSDK.HalLowLevel) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel ../../include/hal_ll_rcc.h ../../include/hal_ll_target.h ../../include/hal_ll_pin_names.h ../../include/hal_ll_target_names.h) diff --git a/targets/arm/mikroe/tiva/src/i2c/CMakeLists.txt b/targets/arm/mikroe/tiva/src/i2c/CMakeLists.txt index a41574e67..28ab72984 100644 --- a/targets/arm/mikroe/tiva/src/i2c/CMakeLists.txt +++ b/targets/arm/mikroe/tiva/src/i2c/CMakeLists.txt @@ -1,72 +1,72 @@ -## ./targets/arm/mikroe/tiva/src/i2c/CMakeLists.txt -set(mcu_header_path ${MCU_NAME}) - -find_cortex(hal_ll_def_list) - -list(APPEND hal_ll_def_list ${MCU_NAME}) - -if (${CORE_NAME} EQUAL "M4EF") - list(APPEND hal_ll_def_list "__cortex_m4_fpu__") -else() - list(APPEND hal_ll_def_list "__cortex_not_supported__") -endif() - -## BEGIN I2C -list(APPEND hal_ll_def_list "MACRO_USAGE_I2C") -set(i2c_subimplementation "implementation_1/hal_ll_i2c_master.c") -set(i2c_pin_map "hal_ll_i2c_pin_map/implementation_1") -## END I2C - -# TSC2003 Special case -if (NOT DEFINED _MSDK_TFT_TP_) - list(APPEND hal_ll_def_list "__TFT_NON_TSC2003__") -else() - if (${_MSDK_TFT_TP_} MATCHES "__TP_TSC2003__") - list(APPEND hal_ll_def_list "__TFT_RESISTIVE_TSC2003__") - else() - list(APPEND hal_ll_def_list "__TFT_NON_TSC2003__") - endif() -endif() - -mikrosdk_add_library(lib_hal_ll_i2c_master MikroSDK.HalLowLevel.I2C.Master - ${i2c_subimplementation} - - ../../include/hal_ll_rcc.h - ../../include/hal_ll_target.h -# BEGIN I2C - ../../include/i2c/hal_ll_i2c_master.h - ../../include/i2c/${i2c_pin_map}/hal_ll_i2c_pin_map.h -# END I2C -) - -target_compile_definitions(lib_hal_ll_i2c_master PUBLIC - ${hal_ll_def_list} -) - -target_link_libraries(lib_hal_ll_i2c_master PUBLIC - MikroC.Core - MikroSDK.HalLowLevelCore - MikroSDK.HalLowLevelCommon -) - -string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) -target_include_directories(lib_hal_ll_i2c_master - PRIVATE - ../../include - ../../include/gpio - # BEGIN I2C - ../../include/i2c - ../../include/i2c/${i2c_pin_map} - # END I2C - - INTERFACE - $ - $ - $ - $ - $ - $ - ) - -mikrosdk_install(MikroSDK.HalLowLevel.I2C.Master) -install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.I2C.Master ../../include/i2c/hal_ll_i2c_master.h) +## ./targets/arm/mikroe/tiva/src/i2c/CMakeLists.txt +set(mcu_header_path ${MCU_NAME}) + +find_cortex(hal_ll_def_list) + +list(APPEND hal_ll_def_list ${MCU_NAME}) + +if (${CORE_NAME} EQUAL "M4EF") + list(APPEND hal_ll_def_list "__cortex_m4_fpu__") +else() + list(APPEND hal_ll_def_list "__cortex_not_supported__") +endif() + +## BEGIN I2C +list(APPEND hal_ll_def_list "MACRO_USAGE_I2C") +set(i2c_subimplementation "implementation_1/hal_ll_i2c_master.c") +set(i2c_pin_map "hal_ll_i2c_pin_map/implementation_1") +## END I2C + +# TSC2003 Special case +if (NOT DEFINED _MSDK_TFT_TP_) + list(APPEND hal_ll_def_list "__TFT_NON_TSC2003__") +else() + if (${_MSDK_TFT_TP_} MATCHES "__TP_TSC2003__") + list(APPEND hal_ll_def_list "__TFT_RESISTIVE_TSC2003__") + else() + list(APPEND hal_ll_def_list "__TFT_NON_TSC2003__") + endif() +endif() + +mikrosdk_add_library(lib_hal_ll_i2c_master MikroSDK.HalLowLevel.I2C.Master + ${i2c_subimplementation} + + ../../include/hal_ll_rcc.h + ../../include/hal_ll_target.h +# BEGIN I2C + ../../include/i2c/hal_ll_i2c_master.h + ../../include/i2c/${i2c_pin_map}/hal_ll_i2c_pin_map.h +# END I2C +) + +target_compile_definitions(lib_hal_ll_i2c_master PUBLIC + ${hal_ll_def_list} +) + +target_link_libraries(lib_hal_ll_i2c_master PUBLIC + MikroC.Core + MikroSDK.HalLowLevelCore + MikroSDK.HalLowLevelCommon +) + +string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) +target_include_directories(lib_hal_ll_i2c_master + PRIVATE + ../../include + ../../include/gpio + # BEGIN I2C + ../../include/i2c + ../../include/i2c/${i2c_pin_map} + # END I2C + + INTERFACE + $ + $ + $ + $ + $ + $ + ) + +mikrosdk_install(MikroSDK.HalLowLevel.I2C.Master) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.I2C.Master ../../include/i2c/hal_ll_i2c_master.h) diff --git a/targets/arm/mikroe/tiva/src/one_wire/CMakeLists.txt b/targets/arm/mikroe/tiva/src/one_wire/CMakeLists.txt index 98c337b59..8e2be839d 100644 --- a/targets/arm/mikroe/tiva/src/one_wire/CMakeLists.txt +++ b/targets/arm/mikroe/tiva/src/one_wire/CMakeLists.txt @@ -1,31 +1,31 @@ -## ./targets/arm/mikroe/tiva/src/one_wire/CMakeLists.txt -set(hal_ll_def_list "") -list(APPEND hal_ll_def_list "MACRO_USAGE_ONE_WIRE") - -mikrosdk_add_library(lib_hal_ll_one_wire MikroSDK.HalLowLevel.OneWire - hal_ll_one_wire.c - - ../../include/one_wire/hal_ll_one_wire.h) - -target_compile_definitions(lib_hal_ll_one_wire PUBLIC - ${hal_ll_def_list} -) - -target_link_libraries(lib_hal_ll_one_wire PUBLIC - MikroC.Core - MikroSDK.HalLowLevel.GPIO - MikroSDK.HalLowLevelCommon -) - -target_include_directories(lib_hal_ll_one_wire - PRIVATE - ../../include/one_wire - INTERFACE - $ - $ - $ - $ -) - -mikrosdk_install(MikroSDK.HalLowLevel.OneWire) -install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.OneWire ../../include/one_wire/hal_ll_one_wire.h) +## ./targets/arm/mikroe/tiva/src/one_wire/CMakeLists.txt +set(hal_ll_def_list "") +list(APPEND hal_ll_def_list "MACRO_USAGE_ONE_WIRE") + +mikrosdk_add_library(lib_hal_ll_one_wire MikroSDK.HalLowLevel.OneWire + hal_ll_one_wire.c + + ../../include/one_wire/hal_ll_one_wire.h) + +target_compile_definitions(lib_hal_ll_one_wire PUBLIC + ${hal_ll_def_list} +) + +target_link_libraries(lib_hal_ll_one_wire PUBLIC + MikroC.Core + MikroSDK.HalLowLevel.GPIO + MikroSDK.HalLowLevelCommon +) + +target_include_directories(lib_hal_ll_one_wire + PRIVATE + ../../include/one_wire + INTERFACE + $ + $ + $ + $ +) + +mikrosdk_install(MikroSDK.HalLowLevel.OneWire) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.OneWire ../../include/one_wire/hal_ll_one_wire.h) diff --git a/targets/arm/mikroe/tiva/src/spi_master/CMakeLists.txt b/targets/arm/mikroe/tiva/src/spi_master/CMakeLists.txt index d9dd09fd7..07cbb37ff 100644 --- a/targets/arm/mikroe/tiva/src/spi_master/CMakeLists.txt +++ b/targets/arm/mikroe/tiva/src/spi_master/CMakeLists.txt @@ -1,65 +1,65 @@ -## ./targets/arm/mikroe/tiva/src/spi_master/CMakeLists.txt -set(hal_ll_def_list "") -set(MCU_NAME_FIRST_7 "") -set(mcu_header_path ${MCU_NAME}) - -find_cortex(hal_ll_def_list) - -list(APPEND hal_ll_def_list ${MCU_NAME}) -string(SUBSTRING ${MCU_NAME} 0 7 MCU_NAME_FIRST_7) -list(APPEND hal_ll_def_list ${MCU_NAME_FIRST_7}) - -if (${CORE_NAME} EQUAL "M4EF") - list(APPEND hal_ll_def_list "__cortex_m4_fpu__") -else() - list(APPEND hal_ll_def_list "__cortex_not_supported__") -endif() - -# BEGIN SPI -list(APPEND hal_ll_def_list "MACRO_USAGE_SPI") - -set( spi_subimplementation "implementation_1/hal_ll_spi_master.c" ) -set( spi_pin_map "hal_ll_spi_master_pin_map/implementation_1" ) -# END SPI - -mikrosdk_add_library(lib_hal_ll_spi_master MikroSDK.HalLowLevel.SPI.Master - ${spi_subimplementation} - - ../../include/hal_ll_rcc.h - ../../include/hal_ll_target.h - # BEGIN SPI - ../../include/spi_master/hal_ll_spi_master.h - ../../include/spi_master/${spi_pin_map}/hal_ll_spi_master_pin_map.h - # END SPI -) - -target_compile_definitions(lib_hal_ll_spi_master PUBLIC - ${hal_ll_def_list} -) - -target_link_libraries(lib_hal_ll_spi_master PUBLIC - MikroC.Core - MikroSDK.HalLowLevelCore - MikroSDK.HalLowLevelCommon -) - -string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) -target_include_directories(lib_hal_ll_spi_master - PRIVATE - ../../include - ../../include/gpio - # BEGIN SPI - ../../include/spi_master - ../../include/spi_master/${spi_pin_map} - # END SPI - INTERFACE - $ - $ - $ - $ - $ - $ -) - -mikrosdk_install(MikroSDK.HalLowLevel.SPI.Master) -install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.SPI.Master ../../include/spi_master/hal_ll_spi_master.h) +## ./targets/arm/mikroe/tiva/src/spi_master/CMakeLists.txt +set(hal_ll_def_list "") +set(MCU_NAME_FIRST_7 "") +set(mcu_header_path ${MCU_NAME}) + +find_cortex(hal_ll_def_list) + +list(APPEND hal_ll_def_list ${MCU_NAME}) +string(SUBSTRING ${MCU_NAME} 0 7 MCU_NAME_FIRST_7) +list(APPEND hal_ll_def_list ${MCU_NAME_FIRST_7}) + +if (${CORE_NAME} EQUAL "M4EF") + list(APPEND hal_ll_def_list "__cortex_m4_fpu__") +else() + list(APPEND hal_ll_def_list "__cortex_not_supported__") +endif() + +# BEGIN SPI +list(APPEND hal_ll_def_list "MACRO_USAGE_SPI") + +set( spi_subimplementation "implementation_1/hal_ll_spi_master.c" ) +set( spi_pin_map "hal_ll_spi_master_pin_map/implementation_1" ) +# END SPI + +mikrosdk_add_library(lib_hal_ll_spi_master MikroSDK.HalLowLevel.SPI.Master + ${spi_subimplementation} + + ../../include/hal_ll_rcc.h + ../../include/hal_ll_target.h + # BEGIN SPI + ../../include/spi_master/hal_ll_spi_master.h + ../../include/spi_master/${spi_pin_map}/hal_ll_spi_master_pin_map.h + # END SPI +) + +target_compile_definitions(lib_hal_ll_spi_master PUBLIC + ${hal_ll_def_list} +) + +target_link_libraries(lib_hal_ll_spi_master PUBLIC + MikroC.Core + MikroSDK.HalLowLevelCore + MikroSDK.HalLowLevelCommon +) + +string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) +target_include_directories(lib_hal_ll_spi_master + PRIVATE + ../../include + ../../include/gpio + # BEGIN SPI + ../../include/spi_master + ../../include/spi_master/${spi_pin_map} + # END SPI + INTERFACE + $ + $ + $ + $ + $ + $ +) + +mikrosdk_install(MikroSDK.HalLowLevel.SPI.Master) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.SPI.Master ../../include/spi_master/hal_ll_spi_master.h) diff --git a/targets/arm/mikroe/tiva/src/tim/CMakeLists.txt b/targets/arm/mikroe/tiva/src/tim/CMakeLists.txt index 517fabb52..3cfad235a 100644 --- a/targets/arm/mikroe/tiva/src/tim/CMakeLists.txt +++ b/targets/arm/mikroe/tiva/src/tim/CMakeLists.txt @@ -1,64 +1,64 @@ -## ./targets/arm/mikroe/tiva/src/tim/CMakeLists.txt -set(hal_ll_def_list "") -set(MCU_NAME_FIRST_7 "") -set(mcu_header_path ${MCU_NAME}) - -find_cortex(hal_ll_def_list) - -list(APPEND hal_ll_def_list ${MCU_NAME}) -string(SUBSTRING ${MCU_NAME} 0 7 MCU_NAME_FIRST_7) -list(APPEND hal_ll_def_list ${MCU_NAME_FIRST_7}) - -if (${CORE_NAME} EQUAL "M4EF") - list(APPEND hal_ll_def_list "__cortex_m4_fpu__") -else() - list(APPEND hal_ll_def_list "__cortex_not_supported__") -endif() - -# BEGIN TIM -list(APPEND hal_ll_def_list "MACRO_USAGE_TIM") -set( tim_subimplementation "implementation_1/hal_ll_tim.c" ) -set( tim_pin_map "hal_ll_tim_pin_map/implementation_1" ) -# END TIM - -mikrosdk_add_library(lib_hal_ll_tim MikroSDK.HalLowLevel.TIM - ${tim_subimplementation} - - ../../include/hal_ll_rcc.h - ../../include/hal_ll_target.h - # BEGIN TIM - ../../include/tim/hal_ll_tim.h - ../../include/tim/${tim_pin_map}/hal_ll_tim_pin_map.h - # END TIM -) - -target_compile_definitions(lib_hal_ll_tim PUBLIC - ${hal_ll_def_list} -) - -target_link_libraries(lib_hal_ll_tim PUBLIC - MikroC.Core - MikroSDK.HalLowLevelCore - MikroSDK.HalLowLevelCommon -) - -string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) -target_include_directories(lib_hal_ll_tim - PRIVATE - ../../include - ../../include/gpio - # BEGIN TIM - ../../include/tim - ../../include/tim/${tim_pin_map} - # END TIM - INTERFACE - $ - $ - $ - $ - $ - $ -) - -mikrosdk_install(MikroSDK.HalLowLevel.TIM) -install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.TIM ../../include/tim/hal_ll_tim.h) +## ./targets/arm/mikroe/tiva/src/tim/CMakeLists.txt +set(hal_ll_def_list "") +set(MCU_NAME_FIRST_7 "") +set(mcu_header_path ${MCU_NAME}) + +find_cortex(hal_ll_def_list) + +list(APPEND hal_ll_def_list ${MCU_NAME}) +string(SUBSTRING ${MCU_NAME} 0 7 MCU_NAME_FIRST_7) +list(APPEND hal_ll_def_list ${MCU_NAME_FIRST_7}) + +if (${CORE_NAME} EQUAL "M4EF") + list(APPEND hal_ll_def_list "__cortex_m4_fpu__") +else() + list(APPEND hal_ll_def_list "__cortex_not_supported__") +endif() + +# BEGIN TIM +list(APPEND hal_ll_def_list "MACRO_USAGE_TIM") +set( tim_subimplementation "implementation_1/hal_ll_tim.c" ) +set( tim_pin_map "hal_ll_tim_pin_map/implementation_1" ) +# END TIM + +mikrosdk_add_library(lib_hal_ll_tim MikroSDK.HalLowLevel.TIM + ${tim_subimplementation} + + ../../include/hal_ll_rcc.h + ../../include/hal_ll_target.h + # BEGIN TIM + ../../include/tim/hal_ll_tim.h + ../../include/tim/${tim_pin_map}/hal_ll_tim_pin_map.h + # END TIM +) + +target_compile_definitions(lib_hal_ll_tim PUBLIC + ${hal_ll_def_list} +) + +target_link_libraries(lib_hal_ll_tim PUBLIC + MikroC.Core + MikroSDK.HalLowLevelCore + MikroSDK.HalLowLevelCommon +) + +string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) +target_include_directories(lib_hal_ll_tim + PRIVATE + ../../include + ../../include/gpio + # BEGIN TIM + ../../include/tim + ../../include/tim/${tim_pin_map} + # END TIM + INTERFACE + $ + $ + $ + $ + $ + $ +) + +mikrosdk_install(MikroSDK.HalLowLevel.TIM) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.TIM ../../include/tim/hal_ll_tim.h) diff --git a/targets/arm/mikroe/tiva/src/uart/CMakeLists.txt b/targets/arm/mikroe/tiva/src/uart/CMakeLists.txt index 8f7890c0f..ec6679bde 100644 --- a/targets/arm/mikroe/tiva/src/uart/CMakeLists.txt +++ b/targets/arm/mikroe/tiva/src/uart/CMakeLists.txt @@ -1,61 +1,61 @@ -## ./targets/arm/mikroe/tiva/src/uart/CMakeLists.txt -set(hal_ll_def_list "") -set(mcu_header_path ${MCU_NAME}) - -find_cortex(hal_ll_def_list) - -list(APPEND hal_ll_def_list ${MCU_NAME}) - -if (${CORE_NAME} EQUAL "M4EF") - list(APPEND hal_ll_def_list "__cortex_m4_fpu__") -else() - list(APPEND hal_ll_def_list "__cortex_not_supported__") -endif() - -# BEGIN UART -list(APPEND hal_ll_def_list "MACRO_USAGE_UART") -set(uart_subimplementation "implementation_1/hal_ll_uart.c") -set(uart_pin_map "hal_ll_uart_pin_map/implementation_1") -# END UART - -mikrosdk_add_library(lib_hal_ll_uart MikroSDK.HalLowLevel.UART - ${uart_subimplementation} - - ../../include/hal_ll_rcc.h - ../../include/hal_ll_target.h - # BEGIN UART - ../../include/uart/hal_ll_uart.h - ../../include/uart/${uart_pin_map}/hal_ll_uart_pin_map.h - # END UART -) - -target_compile_definitions(lib_hal_ll_uart PUBLIC - ${hal_ll_def_list} -) - -target_link_libraries(lib_hal_ll_uart PUBLIC - MikroC.Core - MikroSDK.HalLowLevelCore - MikroSDK.HalLowLevelCommon -) - -string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) -target_include_directories(lib_hal_ll_uart - PRIVATE - ../../include - ../../include/gpio - # BEGIN UART - ../../include/uart - ../../include/uart/${uart_pin_map} - # END UART - INTERFACE - $ - $ - $ - $ - $ - $ -) - -mikrosdk_install(MikroSDK.HalLowLevel.UART) -install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.UART ../../include/uart/hal_ll_uart.h) +## ./targets/arm/mikroe/tiva/src/uart/CMakeLists.txt +set(hal_ll_def_list "") +set(mcu_header_path ${MCU_NAME}) + +find_cortex(hal_ll_def_list) + +list(APPEND hal_ll_def_list ${MCU_NAME}) + +if (${CORE_NAME} EQUAL "M4EF") + list(APPEND hal_ll_def_list "__cortex_m4_fpu__") +else() + list(APPEND hal_ll_def_list "__cortex_not_supported__") +endif() + +# BEGIN UART +list(APPEND hal_ll_def_list "MACRO_USAGE_UART") +set(uart_subimplementation "implementation_1/hal_ll_uart.c") +set(uart_pin_map "hal_ll_uart_pin_map/implementation_1") +# END UART + +mikrosdk_add_library(lib_hal_ll_uart MikroSDK.HalLowLevel.UART + ${uart_subimplementation} + + ../../include/hal_ll_rcc.h + ../../include/hal_ll_target.h + # BEGIN UART + ../../include/uart/hal_ll_uart.h + ../../include/uart/${uart_pin_map}/hal_ll_uart_pin_map.h + # END UART +) + +target_compile_definitions(lib_hal_ll_uart PUBLIC + ${hal_ll_def_list} +) + +target_link_libraries(lib_hal_ll_uart PUBLIC + MikroC.Core + MikroSDK.HalLowLevelCore + MikroSDK.HalLowLevelCommon +) + +string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) +target_include_directories(lib_hal_ll_uart + PRIVATE + ../../include + ../../include/gpio + # BEGIN UART + ../../include/uart + ../../include/uart/${uart_pin_map} + # END UART + INTERFACE + $ + $ + $ + $ + $ + $ +) + +mikrosdk_install(MikroSDK.HalLowLevel.UART) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.UART ../../include/uart/hal_ll_uart.h) diff --git a/targets/avr_8bit/mikroe/CMakeLists.txt b/targets/avr_8bit/mikroe/CMakeLists.txt index 1ec25f1e3..951478d76 100644 --- a/targets/avr_8bit/mikroe/CMakeLists.txt +++ b/targets/avr_8bit/mikroe/CMakeLists.txt @@ -1,4 +1,4 @@ -## ./targets/avr_8bit/mikroe/CMakeLists.txt -add_subdirectory(common) -add_subdirectory(core) -add_subdirectory(avr) +## ./targets/avr_8bit/mikroe/CMakeLists.txt +add_subdirectory(common) +add_subdirectory(core) +add_subdirectory(avr) diff --git a/targets/avr_8bit/mikroe/avr/include/hal_ll/CMakeLists.txt b/targets/avr_8bit/mikroe/avr/include/hal_ll/CMakeLists.txt index 138221f97..0239e8503 100644 --- a/targets/avr_8bit/mikroe/avr/include/hal_ll/CMakeLists.txt +++ b/targets/avr_8bit/mikroe/avr/include/hal_ll/CMakeLists.txt @@ -1,17 +1,17 @@ -## ./targets/avr_8bit/mikroe/avr/include/hal_ll/CMakeLists.txt -add_library(lib_hal_ll INTERFACE) - -add_library(MikroSDK.HalLowLevel ALIAS lib_hal_ll) - -target_link_libraries(lib_hal_ll INTERFACE - MikroSDK.HalLowLevel.ADC - MikroSDK.HalLowLevel.GPIO - MikroSDK.HalLowLevel.I2C.Master - MikroSDK.HalLowLevel.SPI.Master - MikroSDK.HalLowLevel.TIM - MikroSDK.HalLowLevel.UART - # MikroSDK.HalLowLevel.OneWire TODO -) - -mikrosdk_install(MikroSDK.HalLowLevel) -install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel ../../include/hal_ll_target.h ../../include/hal_ll_pin_names.h ../../include/hal_ll_target_names.h) +## ./targets/avr_8bit/mikroe/avr/include/hal_ll/CMakeLists.txt +add_library(lib_hal_ll INTERFACE) + +add_library(MikroSDK.HalLowLevel ALIAS lib_hal_ll) + +target_link_libraries(lib_hal_ll INTERFACE + MikroSDK.HalLowLevel.ADC + MikroSDK.HalLowLevel.GPIO + MikroSDK.HalLowLevel.I2C.Master + MikroSDK.HalLowLevel.SPI.Master + MikroSDK.HalLowLevel.TIM + MikroSDK.HalLowLevel.UART + # MikroSDK.HalLowLevel.OneWire TODO +) + +mikrosdk_install(MikroSDK.HalLowLevel) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel ../../include/hal_ll_target.h ../../include/hal_ll_pin_names.h ../../include/hal_ll_target_names.h) diff --git a/targets/avr_8bit/mikroe/avr/src/gpio/CMakeLists.txt b/targets/avr_8bit/mikroe/avr/src/gpio/CMakeLists.txt index b6e3d677d..fc3717db0 100644 --- a/targets/avr_8bit/mikroe/avr/src/gpio/CMakeLists.txt +++ b/targets/avr_8bit/mikroe/avr/src/gpio/CMakeLists.txt @@ -1,65 +1,65 @@ -## ./targets/avr_8bit/mikroe/avr/src/gpio/CMakeLists.txt -set(hal_ll_def_list "") -if((${CORE_NAME} MATCHES "GT64K") OR (${CORE_NAME} MATCHES "LTE64K")) - list(APPEND hal_ll_def_list "__avr_8_bit__") -else() - list(APPEND hal_ll_def_list "__family_not_supported__") -endif() - -list(APPEND hal_ll_def_list ${MCU_NAME}) - -string(LENGTH ${MCU_NAME} MEMAKE_MCU_NAME_LENGTH) -MATH(EXPR BEGIN_INDEX "${MEMAKE_MCU_NAME_LENGTH}-3") -string(SUBSTRING ${MCU_NAME} ${BEGIN_INDEX} 3 MCU_NAME_LAST_3) -MATH(EXPR BEGIN_INDEX_4TH "${MEMAKE_MCU_NAME_LENGTH}-4") -string(SUBSTRING ${MCU_NAME} ${BEGIN_INDEX_4TH} 1 MCU_ON_4) -MATH(EXPR BEGIN_INDEX_4TH "${MEMAKE_MCU_NAME_LENGTH}-5") -string(SUBSTRING ${MCU_NAME} ${BEGIN_INDEX_4TH} 1 MCU_ON_5) -MATH(EXPR BEGIN_INDEX_5TH "${MEMAKE_MCU_NAME_LENGTH}-5") -string(SUBSTRING ${MCU_NAME} ${BEGIN_INDEX_5TH} 5 MCU_NAME_LAST_5) - -## BEGIN GPIO -if ((${MCU_NAME} MATCHES "AT")) - set(gpio_implementation "implementation_1") - set(gpio_subimplementation "subimplementation_1") -else() - list(APPEND hal_ll_def_list "__hal_ll_gpio_not_supported__") -endif() - -list(APPEND hal_ll_def_list "MACRO_USAGE_GPIO") - -mikrosdk_add_library(lib_hal_ll_gpio MikroSDK.HalLowLevel.GPIO - ${gpio_implementation}/hal_ll_gpio.c - ${gpio_implementation}/${gpio_subimplementation}/hal_ll_gpio_port.c - ../../include/hal_ll_target.h - ../../include/gpio/hal_ll_gpio.h - ../../include/gpio/hal_ll_gpio_port.h - ../../include/gpio/hal_ll_gpio_constants.h -) - -target_compile_definitions(lib_hal_ll_gpio PUBLIC - ${hal_ll_def_list} -) - -target_link_libraries(lib_hal_ll_gpio PUBLIC - MikroC.Core - MikroSDK.HalLowLevelCore - MikroSDK.HalLowLevelCommon -) - -string(TOLOWER ${MCU_NAME} MCU_NAME_LOWER) -target_include_directories(lib_hal_ll_gpio - PRIVATE - ../../include - ../../include/gpio - ../../include/adc - INTERFACE - $ - $ - $ - $ - $ -) - -mikrosdk_install(MikroSDK.HalLowLevel.GPIO) -install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.GPIO ../../include/gpio/hal_ll_gpio.h ../../include/gpio/hal_ll_gpio_constants.h ../../include/gpio/hal_ll_gpio_port.h) +## ./targets/avr_8bit/mikroe/avr/src/gpio/CMakeLists.txt +set(hal_ll_def_list "") +if((${CORE_NAME} MATCHES "GT64K") OR (${CORE_NAME} MATCHES "LTE64K")) + list(APPEND hal_ll_def_list "__avr_8_bit__") +else() + list(APPEND hal_ll_def_list "__family_not_supported__") +endif() + +list(APPEND hal_ll_def_list ${MCU_NAME}) + +string(LENGTH ${MCU_NAME} MEMAKE_MCU_NAME_LENGTH) +MATH(EXPR BEGIN_INDEX "${MEMAKE_MCU_NAME_LENGTH}-3") +string(SUBSTRING ${MCU_NAME} ${BEGIN_INDEX} 3 MCU_NAME_LAST_3) +MATH(EXPR BEGIN_INDEX_4TH "${MEMAKE_MCU_NAME_LENGTH}-4") +string(SUBSTRING ${MCU_NAME} ${BEGIN_INDEX_4TH} 1 MCU_ON_4) +MATH(EXPR BEGIN_INDEX_4TH "${MEMAKE_MCU_NAME_LENGTH}-5") +string(SUBSTRING ${MCU_NAME} ${BEGIN_INDEX_4TH} 1 MCU_ON_5) +MATH(EXPR BEGIN_INDEX_5TH "${MEMAKE_MCU_NAME_LENGTH}-5") +string(SUBSTRING ${MCU_NAME} ${BEGIN_INDEX_5TH} 5 MCU_NAME_LAST_5) + +## BEGIN GPIO +if ((${MCU_NAME} MATCHES "AT")) + set(gpio_implementation "implementation_1") + set(gpio_subimplementation "subimplementation_1") +else() + list(APPEND hal_ll_def_list "__hal_ll_gpio_not_supported__") +endif() + +list(APPEND hal_ll_def_list "MACRO_USAGE_GPIO") + +mikrosdk_add_library(lib_hal_ll_gpio MikroSDK.HalLowLevel.GPIO + ${gpio_implementation}/hal_ll_gpio.c + ${gpio_implementation}/${gpio_subimplementation}/hal_ll_gpio_port.c + ../../include/hal_ll_target.h + ../../include/gpio/hal_ll_gpio.h + ../../include/gpio/hal_ll_gpio_port.h + ../../include/gpio/hal_ll_gpio_constants.h +) + +target_compile_definitions(lib_hal_ll_gpio PUBLIC + ${hal_ll_def_list} +) + +target_link_libraries(lib_hal_ll_gpio PUBLIC + MikroC.Core + MikroSDK.HalLowLevelCore + MikroSDK.HalLowLevelCommon +) + +string(TOLOWER ${MCU_NAME} MCU_NAME_LOWER) +target_include_directories(lib_hal_ll_gpio + PRIVATE + ../../include + ../../include/gpio + ../../include/adc + INTERFACE + $ + $ + $ + $ + $ +) + +mikrosdk_install(MikroSDK.HalLowLevel.GPIO) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.GPIO ../../include/gpio/hal_ll_gpio.h ../../include/gpio/hal_ll_gpio_constants.h ../../include/gpio/hal_ll_gpio_port.h) diff --git a/targets/avr_8bit/mikroe/avr/src/hal_ll/CMakeLists.txt b/targets/avr_8bit/mikroe/avr/src/hal_ll/CMakeLists.txt index c86cc6a7a..3d8a677cb 100644 --- a/targets/avr_8bit/mikroe/avr/src/hal_ll/CMakeLists.txt +++ b/targets/avr_8bit/mikroe/avr/src/hal_ll/CMakeLists.txt @@ -1,14 +1,14 @@ -## ./targets/avr_8bit/mikroe/avr/src/hal_ll/CMakeLists.txt -add_library(lib_hal_ll INTERFACE) -add_library(MikroSDK.HalLowLevel ALIAS lib_hal_ll) - -set(module_list "") -set(module_list_supported "") -set_module_support(module_list module_list_supported ${MCU_NAME} "hal_ll_layer") - -target_link_libraries(lib_hal_ll INTERFACE - ${module_list} -) - -mikrosdk_install(MikroSDK.HalLowLevel) -install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel ../../include/hal_ll_target.h ../../include/hal_ll_pin_names.h ../../include/hal_ll_target_names.h) +## ./targets/avr_8bit/mikroe/avr/src/hal_ll/CMakeLists.txt +add_library(lib_hal_ll INTERFACE) +add_library(MikroSDK.HalLowLevel ALIAS lib_hal_ll) + +set(module_list "") +set(module_list_supported "") +set_module_support(module_list module_list_supported ${MCU_NAME} "hal_ll_layer") + +target_link_libraries(lib_hal_ll INTERFACE + ${module_list} +) + +mikrosdk_install(MikroSDK.HalLowLevel) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel ../../include/hal_ll_target.h ../../include/hal_ll_pin_names.h ../../include/hal_ll_target_names.h) diff --git a/targets/avr_8bit/mikroe/avr/src/i2c/CMakeLists.txt b/targets/avr_8bit/mikroe/avr/src/i2c/CMakeLists.txt index 568e544e9..ef6d77a99 100644 --- a/targets/avr_8bit/mikroe/avr/src/i2c/CMakeLists.txt +++ b/targets/avr_8bit/mikroe/avr/src/i2c/CMakeLists.txt @@ -1,69 +1,69 @@ -## ./targets/avr_8bit/mikroe/avr/src/i2c/CMakeLists.txt -set(hal_ll_def_list "") -if((${CORE_NAME} MATCHES "GT64K") OR (${CORE_NAME} MATCHES "LTE64K")) - list(APPEND hal_ll_def_list "__avr_8_bit__") -else() - list(APPEND hal_ll_def_list "__family_not_supported__") -endif() - -list(APPEND hal_ll_def_list ${MCU_NAME}) - -string(LENGTH ${MCU_NAME} MEMAKE_MCU_NAME_LENGTH) -MATH(EXPR BEGIN_INDEX "${MEMAKE_MCU_NAME_LENGTH}-3") -string(SUBSTRING ${MCU_NAME} ${BEGIN_INDEX} 3 MCU_NAME_LAST_3) - -if ((${MCU_NAME} MATCHES "^ATMEGA(32|64)9[AP]?0?[AP]?$") OR (${MCU_NAME} MATCHES "^ATMEGA(32|64)[MU][12]$") OR (${MCU_NAME} MATCHES "^ATMEGA(32|64)5[0]?(PA|A|P)?$")) - set(i2c_implementation "implementation_3/hal_ll_i2c_master.c") -elseif (${MCU_NAME} MATCHES "^ATXMEGA(.+)$") - set(i2c_implementation "implementation_2/hal_ll_i2c_master.c") -elseif (${MCU_NAME} MATCHES "^AT([^X])(.+)$") - set(i2c_implementation "implementation_1/hal_ll_i2c_master.c") -else() - message(FATAL_ERROR "MCU not supported") -endif() - -list(APPEND hal_ll_def_list "MACRO_USAGE_I2C") - -if (NOT DEFINED _MSDK_TFT_TP_) - list(APPEND hal_ll_def_list "__TFT_NON_TSC2003__") -else() - if (${_MSDK_TFT_TP_} MATCHES "__TP_TSC2003__") - list(APPEND hal_ll_def_list "__TFT_RESISTIVE_TSC2003__") - else() - list(APPEND hal_ll_def_list "__TFT_NON_TSC2003__") - endif() -endif() - -mikrosdk_add_library(lib_hal_ll_i2c_master MikroSDK.HalLowLevel.I2C.Master - ${i2c_implementation} - - ../../include/hal_ll_target.h - ../../include/i2c/hal_ll_i2c_master.h - ../../include/i2c/hal_ll_i2c_pin_map.h -) - -target_compile_definitions(lib_hal_ll_i2c_master PUBLIC - ${hal_ll_def_list} -) - -target_link_libraries(lib_hal_ll_i2c_master PUBLIC - MikroC.Core - MikroSDK.HalLowLevelCore - MikroSDK.HalLowLevelCommon -) -string(TOLOWER ${MCU_NAME} MCU_NAME_LOWER) -target_include_directories(lib_hal_ll_i2c_master - PRIVATE - ../../include - ../../include/gpio - ../../include/i2c - INTERFACE - $ - $ - $ - $ - $ -) - -mikrosdk_install(MikroSDK.HalLowLevel.I2C.Master) -install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.I2C.Master ../../include/i2c/hal_ll_i2c_master.h ../../include/i2c/hal_ll_i2c_pin_map.h) +## ./targets/avr_8bit/mikroe/avr/src/i2c/CMakeLists.txt +set(hal_ll_def_list "") +if((${CORE_NAME} MATCHES "GT64K") OR (${CORE_NAME} MATCHES "LTE64K")) + list(APPEND hal_ll_def_list "__avr_8_bit__") +else() + list(APPEND hal_ll_def_list "__family_not_supported__") +endif() + +list(APPEND hal_ll_def_list ${MCU_NAME}) + +string(LENGTH ${MCU_NAME} MEMAKE_MCU_NAME_LENGTH) +MATH(EXPR BEGIN_INDEX "${MEMAKE_MCU_NAME_LENGTH}-3") +string(SUBSTRING ${MCU_NAME} ${BEGIN_INDEX} 3 MCU_NAME_LAST_3) + +if ((${MCU_NAME} MATCHES "^ATMEGA(32|64)9[AP]?0?[AP]?$") OR (${MCU_NAME} MATCHES "^ATMEGA(32|64)[MU][12]$") OR (${MCU_NAME} MATCHES "^ATMEGA(32|64)5[0]?(PA|A|P)?$")) + set(i2c_implementation "implementation_3/hal_ll_i2c_master.c") +elseif (${MCU_NAME} MATCHES "^ATXMEGA(.+)$") + set(i2c_implementation "implementation_2/hal_ll_i2c_master.c") +elseif (${MCU_NAME} MATCHES "^AT([^X])(.+)$") + set(i2c_implementation "implementation_1/hal_ll_i2c_master.c") +else() + message(FATAL_ERROR "MCU not supported") +endif() + +list(APPEND hal_ll_def_list "MACRO_USAGE_I2C") + +if (NOT DEFINED _MSDK_TFT_TP_) + list(APPEND hal_ll_def_list "__TFT_NON_TSC2003__") +else() + if (${_MSDK_TFT_TP_} MATCHES "__TP_TSC2003__") + list(APPEND hal_ll_def_list "__TFT_RESISTIVE_TSC2003__") + else() + list(APPEND hal_ll_def_list "__TFT_NON_TSC2003__") + endif() +endif() + +mikrosdk_add_library(lib_hal_ll_i2c_master MikroSDK.HalLowLevel.I2C.Master + ${i2c_implementation} + + ../../include/hal_ll_target.h + ../../include/i2c/hal_ll_i2c_master.h + ../../include/i2c/hal_ll_i2c_pin_map.h +) + +target_compile_definitions(lib_hal_ll_i2c_master PUBLIC + ${hal_ll_def_list} +) + +target_link_libraries(lib_hal_ll_i2c_master PUBLIC + MikroC.Core + MikroSDK.HalLowLevelCore + MikroSDK.HalLowLevelCommon +) +string(TOLOWER ${MCU_NAME} MCU_NAME_LOWER) +target_include_directories(lib_hal_ll_i2c_master + PRIVATE + ../../include + ../../include/gpio + ../../include/i2c + INTERFACE + $ + $ + $ + $ + $ +) + +mikrosdk_install(MikroSDK.HalLowLevel.I2C.Master) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.I2C.Master ../../include/i2c/hal_ll_i2c_master.h ../../include/i2c/hal_ll_i2c_pin_map.h) diff --git a/targets/avr_8bit/mikroe/avr/src/one_wire/CMakeLists.txt b/targets/avr_8bit/mikroe/avr/src/one_wire/CMakeLists.txt index 07cdca3f9..5c54c41ff 100644 --- a/targets/avr_8bit/mikroe/avr/src/one_wire/CMakeLists.txt +++ b/targets/avr_8bit/mikroe/avr/src/one_wire/CMakeLists.txt @@ -1,32 +1,32 @@ -## ./targets/avr_8bit/mikroe/avr/src/one_wire/CMakeLists.txt -set(hal_ll_def_list) -list(APPEND hal_ll_def_list "MACRO_USAGE_ONE_WIRE") - -mikrosdk_add_library(lib_hal_ll_one_wire MikroSDK.HalLowLevel.OneWire - hal_ll_one_wire.c - - ../../include/one_wire/hal_ll_one_wire.h -) - -target_compile_definitions(lib_hal_ll_one_wire PUBLIC - ${hal_ll_def_list} -) - -target_link_libraries(lib_hal_ll_one_wire PUBLIC - MikroC.Core - MikroSDK.HalLowLevel.GPIO - MikroSDK.HalLowLevelCommon -) - -target_include_directories(lib_hal_ll_one_wire - PRIVATE - ../../include/one_wire - INTERFACE - $ - $ - $ - $ -) - -mikrosdk_install(MikroSDK.HalLowLevel.OneWire) -install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.OneWire ../../include/one_wire/hal_ll_one_wire.h) +## ./targets/avr_8bit/mikroe/avr/src/one_wire/CMakeLists.txt +set(hal_ll_def_list) +list(APPEND hal_ll_def_list "MACRO_USAGE_ONE_WIRE") + +mikrosdk_add_library(lib_hal_ll_one_wire MikroSDK.HalLowLevel.OneWire + hal_ll_one_wire.c + + ../../include/one_wire/hal_ll_one_wire.h +) + +target_compile_definitions(lib_hal_ll_one_wire PUBLIC + ${hal_ll_def_list} +) + +target_link_libraries(lib_hal_ll_one_wire PUBLIC + MikroC.Core + MikroSDK.HalLowLevel.GPIO + MikroSDK.HalLowLevelCommon +) + +target_include_directories(lib_hal_ll_one_wire + PRIVATE + ../../include/one_wire + INTERFACE + $ + $ + $ + $ +) + +mikrosdk_install(MikroSDK.HalLowLevel.OneWire) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.OneWire ../../include/one_wire/hal_ll_one_wire.h) diff --git a/targets/avr_8bit/mikroe/avr/src/tim/CMakeLists.txt b/targets/avr_8bit/mikroe/avr/src/tim/CMakeLists.txt index a5d59cbc3..7fb73eb33 100644 --- a/targets/avr_8bit/mikroe/avr/src/tim/CMakeLists.txt +++ b/targets/avr_8bit/mikroe/avr/src/tim/CMakeLists.txt @@ -1,65 +1,65 @@ -## ./targets/avr_8bit/mikroe/avr/src/tim/CMakeLists.txt -set(hal_ll_def_list "") -if((${CORE_NAME} MATCHES "GT64K") OR (${CORE_NAME} MATCHES "LTE64K")) - list(APPEND hal_ll_def_list "__avr_8_bit__") -else() - list(APPEND hal_ll_def_list "__family_not_supported__") -endif() - -list(APPEND hal_ll_def_list ${MCU_NAME}) - -string(LENGTH ${MCU_NAME} MEMAKE_MCU_NAME_LENGTH) -MATH(EXPR BEGIN_INDEX "${MEMAKE_MCU_NAME_LENGTH}-3") -string(SUBSTRING ${MCU_NAME} ${BEGIN_INDEX} 3 MCU_NAME_LAST_3) - -## BEGIN TIM -if (${MCU_NAME} MATCHES "ATX") - set(tim_implementation "implementation_3") -elseif ( ( ${MCU_NAME} MATCHES "^ATMEGA(32|64|128)4(A|P|PA)?$" ) OR ( ${MCU_NAME} MATCHES "^AT90USB(64|128)[67]$" ) OR ( ${MCU_NAME} MATCHES "^ATMEGA(64|128|256)[01]$" ) OR ( ${MCU_NAME} MATCHES "^ATMEGA(328)(A|P|PA)?$" ) OR ( ${MCU_NAME} MATCHES "^ATMEGA(324|328)PB$" ) OR ( ${MCU_NAME} MATCHES "^ATMEGA(32|64)M1$" ) OR ( ${MCU_NAME} MATCHES "^ATMEGA(32)U[24]$" ) OR ( ${MCU_NAME} MATCHES "^ATMEGA406$" ) OR ( ${MCU_NAME} MATCHES "^ATTINY16(34|7)$" ) ) - set(tim_implementation "implementation_2") -elseif (${MCU_NAME} MATCHES "AT") - set(tim_implementation "implementation_1") -else() - set(tim_implementation "__mcu_not_supported__") -endif() - -if (${MCU_NAME} MATCHES "^ATXMEGA(16|32)E5$") - list(APPEND hal_ll_def_list __hal_ll_tim_subset_atxmega_e5_series__) -endif() -## END TIM - -list(APPEND hal_ll_def_list "MACRO_USAGE_TIM") - -mikrosdk_add_library(lib_hal_ll_tim MikroSDK.HalLowLevel.TIM - ${tim_implementation}/hal_ll_tim.c - - ../../include/hal_ll_target.h - ../../include/tim/hal_ll_tim.h -) - -target_compile_definitions(lib_hal_ll_tim PUBLIC - ${hal_ll_def_list} -) - -target_link_libraries(lib_hal_ll_tim PUBLIC - MikroC.Core - MikroSDK.HalLowLevelCore - MikroSDK.HalLowLevelCommon -) - -string(TOLOWER ${MCU_NAME} MCU_NAME_LOWER) -target_include_directories(lib_hal_ll_tim - PRIVATE - ../../include - ../../include/gpio - ../../include/tim - INTERFACE - $ - $ - $ - $ - $ -) - -mikrosdk_install(MikroSDK.HalLowLevel.TIM) -install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.TIM ../../include/tim/hal_ll_tim.h ../../include/tim/hal_ll_tim_pin_map.h) +## ./targets/avr_8bit/mikroe/avr/src/tim/CMakeLists.txt +set(hal_ll_def_list "") +if((${CORE_NAME} MATCHES "GT64K") OR (${CORE_NAME} MATCHES "LTE64K")) + list(APPEND hal_ll_def_list "__avr_8_bit__") +else() + list(APPEND hal_ll_def_list "__family_not_supported__") +endif() + +list(APPEND hal_ll_def_list ${MCU_NAME}) + +string(LENGTH ${MCU_NAME} MEMAKE_MCU_NAME_LENGTH) +MATH(EXPR BEGIN_INDEX "${MEMAKE_MCU_NAME_LENGTH}-3") +string(SUBSTRING ${MCU_NAME} ${BEGIN_INDEX} 3 MCU_NAME_LAST_3) + +## BEGIN TIM +if (${MCU_NAME} MATCHES "ATX") + set(tim_implementation "implementation_3") +elseif ( ( ${MCU_NAME} MATCHES "^ATMEGA(32|64|128)4(A|P|PA)?$" ) OR ( ${MCU_NAME} MATCHES "^AT90USB(64|128)[67]$" ) OR ( ${MCU_NAME} MATCHES "^ATMEGA(64|128|256)[01]$" ) OR ( ${MCU_NAME} MATCHES "^ATMEGA(328)(A|P|PA)?$" ) OR ( ${MCU_NAME} MATCHES "^ATMEGA(324|328)PB$" ) OR ( ${MCU_NAME} MATCHES "^ATMEGA(32|64)M1$" ) OR ( ${MCU_NAME} MATCHES "^ATMEGA(32)U[24]$" ) OR ( ${MCU_NAME} MATCHES "^ATMEGA406$" ) OR ( ${MCU_NAME} MATCHES "^ATTINY16(34|7)$" ) ) + set(tim_implementation "implementation_2") +elseif (${MCU_NAME} MATCHES "AT") + set(tim_implementation "implementation_1") +else() + set(tim_implementation "__mcu_not_supported__") +endif() + +if (${MCU_NAME} MATCHES "^ATXMEGA(16|32)E5$") + list(APPEND hal_ll_def_list __hal_ll_tim_subset_atxmega_e5_series__) +endif() +## END TIM + +list(APPEND hal_ll_def_list "MACRO_USAGE_TIM") + +mikrosdk_add_library(lib_hal_ll_tim MikroSDK.HalLowLevel.TIM + ${tim_implementation}/hal_ll_tim.c + + ../../include/hal_ll_target.h + ../../include/tim/hal_ll_tim.h +) + +target_compile_definitions(lib_hal_ll_tim PUBLIC + ${hal_ll_def_list} +) + +target_link_libraries(lib_hal_ll_tim PUBLIC + MikroC.Core + MikroSDK.HalLowLevelCore + MikroSDK.HalLowLevelCommon +) + +string(TOLOWER ${MCU_NAME} MCU_NAME_LOWER) +target_include_directories(lib_hal_ll_tim + PRIVATE + ../../include + ../../include/gpio + ../../include/tim + INTERFACE + $ + $ + $ + $ + $ +) + +mikrosdk_install(MikroSDK.HalLowLevel.TIM) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.TIM ../../include/tim/hal_ll_tim.h ../../include/tim/hal_ll_tim_pin_map.h) diff --git a/targets/avr_8bit/mikroe/avr/src/uart/CMakeLists.txt b/targets/avr_8bit/mikroe/avr/src/uart/CMakeLists.txt index 71f841191..b00440f77 100644 --- a/targets/avr_8bit/mikroe/avr/src/uart/CMakeLists.txt +++ b/targets/avr_8bit/mikroe/avr/src/uart/CMakeLists.txt @@ -1,67 +1,67 @@ -## ./targets/avr_8bit/mikroe/avr/src/uart/CMakeLists.txt -set(hal_ll_def_list "") -if((${CORE_NAME} MATCHES "GT64K") OR (${CORE_NAME} MATCHES "LTE64K")) - list(APPEND hal_ll_def_list "__avr_8_bit__") -else() - list(APPEND hal_ll_def_list "__family_not_supported__") -endif() - -list(APPEND hal_ll_def_list ${MCU_NAME}) - -## Uncomment if you want to map interrupt routines using -## actual interrupt address. By default, interrupt vector -## approach is used. -# list(APPEND hal_ll_def_list "__MIKROSDK_AVR_IVT_ADDRESSES__") - -string(LENGTH ${MCU_NAME} MEMAKE_MCU_NAME_LENGTH) -MATH(EXPR BEGIN_INDEX "${MEMAKE_MCU_NAME_LENGTH}-3") -string(SUBSTRING ${MCU_NAME} ${BEGIN_INDEX} 3 MCU_NAME_LAST_3) - -## BEGIN UART -if ( (${MCU_NAME} MATCHES "^ATXMEGA(.+)$") ) - set(uart_implementation "implementation_2") - list(APPEND hal_ll_def_list "__ATXMEGA__") -elseif (${MCU_NAME} MATCHES "^AT(.+)$") - set(uart_implementation "implementation_1") - list(APPEND hal_ll_def_list "__ATMEGA__") -else() - set(uart_implementation "__mcu_not_supported__") -endif() -## END UART - -mikrosdk_add_library(lib_hal_ll_uart MikroSDK.HalLowLevel.UART - ${uart_implementation}/hal_ll_uart.c - - ../../include/hal_ll_target.h - ../../include/uart/hal_ll_uart.h - ../../include/uart/hal_ll_uart_pin_map.h -) - -target_compile_definitions(lib_hal_ll_uart PUBLIC - ${hal_ll_def_list} -) - -target_link_libraries(lib_hal_ll_uart PUBLIC - MikroC.Core - MikroSDK.HalLowLevelCore - MikroSDK.HalLowLevelCommon -) -string(TOLOWER ${MCU_NAME} MCU_NAME_LOWER) -target_include_directories(lib_hal_ll_uart - PRIVATE - ../../include - ../../include/gpio -# BEGIN UART - ../../include/uart - ../../include/uart/${uart_pin_map} -# END UART - - INTERFACE - $ - $ - $ - $ -) - -mikrosdk_install(MikroSDK.HalLowLevel.UART) -install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.UART ../../include/uart/hal_ll_uart.h ../../include/uart/hal_ll_uart_pin_map.h) +## ./targets/avr_8bit/mikroe/avr/src/uart/CMakeLists.txt +set(hal_ll_def_list "") +if((${CORE_NAME} MATCHES "GT64K") OR (${CORE_NAME} MATCHES "LTE64K")) + list(APPEND hal_ll_def_list "__avr_8_bit__") +else() + list(APPEND hal_ll_def_list "__family_not_supported__") +endif() + +list(APPEND hal_ll_def_list ${MCU_NAME}) + +## Uncomment if you want to map interrupt routines using +## actual interrupt address. By default, interrupt vector +## approach is used. +# list(APPEND hal_ll_def_list "__MIKROSDK_AVR_IVT_ADDRESSES__") + +string(LENGTH ${MCU_NAME} MEMAKE_MCU_NAME_LENGTH) +MATH(EXPR BEGIN_INDEX "${MEMAKE_MCU_NAME_LENGTH}-3") +string(SUBSTRING ${MCU_NAME} ${BEGIN_INDEX} 3 MCU_NAME_LAST_3) + +## BEGIN UART +if ( (${MCU_NAME} MATCHES "^ATXMEGA(.+)$") ) + set(uart_implementation "implementation_2") + list(APPEND hal_ll_def_list "__ATXMEGA__") +elseif (${MCU_NAME} MATCHES "^AT(.+)$") + set(uart_implementation "implementation_1") + list(APPEND hal_ll_def_list "__ATMEGA__") +else() + set(uart_implementation "__mcu_not_supported__") +endif() +## END UART + +mikrosdk_add_library(lib_hal_ll_uart MikroSDK.HalLowLevel.UART + ${uart_implementation}/hal_ll_uart.c + + ../../include/hal_ll_target.h + ../../include/uart/hal_ll_uart.h + ../../include/uart/hal_ll_uart_pin_map.h +) + +target_compile_definitions(lib_hal_ll_uart PUBLIC + ${hal_ll_def_list} +) + +target_link_libraries(lib_hal_ll_uart PUBLIC + MikroC.Core + MikroSDK.HalLowLevelCore + MikroSDK.HalLowLevelCommon +) +string(TOLOWER ${MCU_NAME} MCU_NAME_LOWER) +target_include_directories(lib_hal_ll_uart + PRIVATE + ../../include + ../../include/gpio +# BEGIN UART + ../../include/uart + ../../include/uart/${uart_pin_map} +# END UART + + INTERFACE + $ + $ + $ + $ +) + +mikrosdk_install(MikroSDK.HalLowLevel.UART) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.UART ../../include/uart/hal_ll_uart.h ../../include/uart/hal_ll_uart_pin_map.h) diff --git a/targets/avr_8bit/mikroe/core/CMakeLists.txt b/targets/avr_8bit/mikroe/core/CMakeLists.txt index bd2b7fd4f..a2a87d7be 100644 --- a/targets/avr_8bit/mikroe/core/CMakeLists.txt +++ b/targets/avr_8bit/mikroe/core/CMakeLists.txt @@ -1,43 +1,43 @@ -## ./targets/avr_8bit/mikroe/core/CMakeLists.txt -set(hal_ll_core_def_list "") -string(SUBSTRING ${MCU_NAME} 0 5 MEMAKE_MCU_NAME_FIRST_5) -string(SUBSTRING ${MCU_NAME} 0 6 MEMAKE_MCU_NAME_FIRST_6) - -if (${MCU_NAME} MATCHES "AT") - set(hal_ll_core_source "hal_ll_core.c") - list(APPEND hal_ll_core_def_list "__avr__") -else() - set(hal_ll_core_def_list "__family_not_supported__") -endif() - -string(LENGTH ${MCU_NAME} MCU_NAME_LENGTH) -MATH(EXPR BEGIN_INDEX "${MCU_NAME_LENGTH}-3") -string(SUBSTRING ${MCU_NAME} ${BEGIN_INDEX} 3 MCU_NAME_LAST_3) - -mikrosdk_add_library(lib_hal_ll_core MikroSDK.HalLowLevelCore - src/${hal_ll_core_source} - - include/hal_ll_core_defines.h - include/hal_ll_core_port.h - include/hal_ll_core.h -) - -target_compile_definitions(lib_hal_ll_core - PUBLIC - ${hal_ll_core_def_list} -) - -target_link_libraries(lib_hal_ll_core PUBLIC - MikroC.Core - MikroSDK.HalLowLevelCommon -) - -target_include_directories(lib_hal_ll_core -PRIVATE - include -INTERFACE - $ - $ -) - -mikrosdk_install(MikroSDK.HalLowLevelCore) +## ./targets/avr_8bit/mikroe/core/CMakeLists.txt +set(hal_ll_core_def_list "") +string(SUBSTRING ${MCU_NAME} 0 5 MEMAKE_MCU_NAME_FIRST_5) +string(SUBSTRING ${MCU_NAME} 0 6 MEMAKE_MCU_NAME_FIRST_6) + +if (${MCU_NAME} MATCHES "AT") + set(hal_ll_core_source "hal_ll_core.c") + list(APPEND hal_ll_core_def_list "__avr__") +else() + set(hal_ll_core_def_list "__family_not_supported__") +endif() + +string(LENGTH ${MCU_NAME} MCU_NAME_LENGTH) +MATH(EXPR BEGIN_INDEX "${MCU_NAME_LENGTH}-3") +string(SUBSTRING ${MCU_NAME} ${BEGIN_INDEX} 3 MCU_NAME_LAST_3) + +mikrosdk_add_library(lib_hal_ll_core MikroSDK.HalLowLevelCore + src/${hal_ll_core_source} + + include/hal_ll_core_defines.h + include/hal_ll_core_port.h + include/hal_ll_core.h +) + +target_compile_definitions(lib_hal_ll_core + PUBLIC + ${hal_ll_core_def_list} +) + +target_link_libraries(lib_hal_ll_core PUBLIC + MikroC.Core + MikroSDK.HalLowLevelCommon +) + +target_include_directories(lib_hal_ll_core +PRIVATE + include +INTERFACE + $ + $ +) + +mikrosdk_install(MikroSDK.HalLowLevelCore) diff --git a/targets/pic_32bit/mikroe/CMakeLists.txt b/targets/pic_32bit/mikroe/CMakeLists.txt index a7cc23424..efe473081 100644 --- a/targets/pic_32bit/mikroe/CMakeLists.txt +++ b/targets/pic_32bit/mikroe/CMakeLists.txt @@ -1,4 +1,4 @@ -## ./targets/pic_32bit/mikroe/CMakeLists.txt -add_subdirectory(pic32) -add_subdirectory(common) -add_subdirectory(core) +## ./targets/pic_32bit/mikroe/CMakeLists.txt +add_subdirectory(pic32) +add_subdirectory(common) +add_subdirectory(core) diff --git a/targets/pic_32bit/mikroe/core/CMakeLists.txt b/targets/pic_32bit/mikroe/core/CMakeLists.txt index 819de5fb5..34a86ca67 100644 --- a/targets/pic_32bit/mikroe/core/CMakeLists.txt +++ b/targets/pic_32bit/mikroe/core/CMakeLists.txt @@ -1,41 +1,41 @@ -## ./targets/pic_32bit/mikroe/core/CMakeLists.txt -set(hal_ll_core_def_list "") - -if (${MCU_NAME} MATCHES "PIC32") - list(APPEND hal_ll_core_def_list "__pic32__") -endif() - -if (${MCU_NAME} MATCHES "PIC32") - string(SUBSTRING ${MCU_NAME} 0 7 MCU_NAME_FIRST_7) - list(APPEND hal_ll_core_def_list ${MCU_NAME_FIRST_7}xx) -else() - list(APPEND hal_ll_core_def_list "__family_not_supported__") -endif() - -mikrosdk_add_library(lib_hal_ll_core MikroSDK.HalLowLevelCore - src/hal_ll_core.c - - include/hal_ll_core_defines.h - include/hal_ll_core_port.h - include/hal_ll_core.h -) - -target_compile_definitions(lib_hal_ll_core - PUBLIC - ${hal_ll_core_def_list} -) - -target_link_libraries(lib_hal_ll_core PUBLIC - MikroSDK.HalLowLevelCommon -) - -target_include_directories(lib_hal_ll_core - PRIVATE - include - INTERFACE - $ - - $ -) - -mikrosdk_install(MikroSDK.HalLowLevelCore) +## ./targets/pic_32bit/mikroe/core/CMakeLists.txt +set(hal_ll_core_def_list "") + +if (${MCU_NAME} MATCHES "PIC32") + list(APPEND hal_ll_core_def_list "__pic32__") +endif() + +if (${MCU_NAME} MATCHES "PIC32") + string(SUBSTRING ${MCU_NAME} 0 7 MCU_NAME_FIRST_7) + list(APPEND hal_ll_core_def_list ${MCU_NAME_FIRST_7}xx) +else() + list(APPEND hal_ll_core_def_list "__family_not_supported__") +endif() + +mikrosdk_add_library(lib_hal_ll_core MikroSDK.HalLowLevelCore + src/hal_ll_core.c + + include/hal_ll_core_defines.h + include/hal_ll_core_port.h + include/hal_ll_core.h +) + +target_compile_definitions(lib_hal_ll_core + PUBLIC + ${hal_ll_core_def_list} +) + +target_link_libraries(lib_hal_ll_core PUBLIC + MikroSDK.HalLowLevelCommon +) + +target_include_directories(lib_hal_ll_core + PRIVATE + include + INTERFACE + $ + + $ +) + +mikrosdk_install(MikroSDK.HalLowLevelCore) diff --git a/targets/pic_32bit/mikroe/pic32/src/adc/CMakeLists.txt b/targets/pic_32bit/mikroe/pic32/src/adc/CMakeLists.txt index ad4a86d31..a2c6e066f 100644 --- a/targets/pic_32bit/mikroe/pic32/src/adc/CMakeLists.txt +++ b/targets/pic_32bit/mikroe/pic32/src/adc/CMakeLists.txt @@ -1,82 +1,82 @@ -## ./targets/pic_32bit/mikroe/pic32/src/adc/CMakeLists.txt -set(hal_ll_def_list "") - -## BEGIN ADC -if(${MCU_NAME} MATCHES "PIC32") - string(SUBSTRING ${MCU_NAME} 0 5 MCU_NAME_FIRST_5) - string(SUBSTRING ${MCU_NAME} 0 7 MCU_NAME_FIRST_7) - string(SUBSTRING ${MCU_NAME} 0 8 MCU_NAME_FIRST_8) - string(SUBSTRING ${MCU_NAME} 0 10 MCU_NAME_FIRST_10) - - list(APPEND hal_ll_def_list ${MCU_NAME}) - list(APPEND hal_ll_def_list ${MCU_NAME_FIRST_5}xx) - list(APPEND hal_ll_def_list ${MCU_NAME_FIRST_7}xx) - list(APPEND hal_ll_def_list ${MCU_NAME_FIRST_8}xx) - list(APPEND hal_ll_def_list ${MCU_NAME_FIRST_10}xx) - list(APPEND hal_ll_def_list "__pic32__") -else() - list(APPEND hal_ll_def_list "__family_not_supported__") -endif() - -if(${MCU_NAME_FIRST_7} MATCHES "PIC32MX") - list(APPEND hal_ll_def_list "HAL_LL_ADC_RESOLUTION_CMAKE=HAL_LL_ADC_RESOLUTION_10_BIT") -elseif(${MCU_NAME_FIRST_7} MATCHES "PIC32MZ") - list(APPEND hal_ll_def_list "HAL_LL_ADC_RESOLUTION_CMAKE=HAL_LL_ADC_RESOLUTION_12_BIT") -endif() - -if(${MCU_NAME} MATCHES "(^PIC32MX[1-7][1-79][045]F(512|256|128|064|032|016)[HLBCD]B?$)") - set(adc_implementation "implementation_1/hal_ll_adc.c") -elseif (${MCU_NAME} MATCHES "(^PIC32MZ(0512|1024|2048)EF[FEHMGK](064|100|124|144)$)") - set(adc_implementation "implementation_2/hal_ll_adc.c") -endif() -## END ADC - -## BEGIN PMD -if (${MCU_NAME} MATCHES "(^PIC32MX([12][0-9]{2}|330|350|370|430|450|470|530|550|570)F(512|256|128|064|032|016)[HLBCD]B?$|^PIC32MZ(0512|1024|2048)EF[FEHMGK](064|100|124|144)$)") - list(APPEND hal_ll_def_list "HAL_LL_PERIPHERAL_MODULE_DISABLE") -endif() -## END PMD - -list(APPEND hal_ll_def_list "MACRO_USAGE_ADC") - -mikrosdk_add_library(lib_hal_ll_adc MikroSDK.HalLowLevel.ADC - ${adc_implementation} - ../../include/hal_ll_target.h - ../../include/hal_ll_slrcon_map.h - ../../include/hal_ll_odcon_map.h -## BEGIN ADC - ../../include/adc/hal_ll_adc.h - ../../include/adc/hal_ll_analog_in_map.h -## END ADC -) - -target_compile_definitions(lib_hal_ll_adc PUBLIC - ${hal_ll_def_list} -) - -target_link_libraries(lib_hal_ll_adc PUBLIC - MikroC.Core - MikroSDK.HalLowLevelCore - MikroSDK.HalLowLevelCommon -) - -string(TOLOWER ${MCU_NAME} MCU_HEADER_PATH_LOWER) -target_include_directories(lib_hal_ll_adc - PRIVATE - ../../include - ../../include/gpio - #BEGINADC - ../../include/adc - #ENDADC - INTERFACE - $ - $ - $ - $ - - $ - $ -) - -mikrosdk_install(MikroSDK.HalLowLevel.ADC) -install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.ADC ../../include/adc/hal_ll_adc.h) +## ./targets/pic_32bit/mikroe/pic32/src/adc/CMakeLists.txt +set(hal_ll_def_list "") + +## BEGIN ADC +if(${MCU_NAME} MATCHES "PIC32") + string(SUBSTRING ${MCU_NAME} 0 5 MCU_NAME_FIRST_5) + string(SUBSTRING ${MCU_NAME} 0 7 MCU_NAME_FIRST_7) + string(SUBSTRING ${MCU_NAME} 0 8 MCU_NAME_FIRST_8) + string(SUBSTRING ${MCU_NAME} 0 10 MCU_NAME_FIRST_10) + + list(APPEND hal_ll_def_list ${MCU_NAME}) + list(APPEND hal_ll_def_list ${MCU_NAME_FIRST_5}xx) + list(APPEND hal_ll_def_list ${MCU_NAME_FIRST_7}xx) + list(APPEND hal_ll_def_list ${MCU_NAME_FIRST_8}xx) + list(APPEND hal_ll_def_list ${MCU_NAME_FIRST_10}xx) + list(APPEND hal_ll_def_list "__pic32__") +else() + list(APPEND hal_ll_def_list "__family_not_supported__") +endif() + +if(${MCU_NAME_FIRST_7} MATCHES "PIC32MX") + list(APPEND hal_ll_def_list "HAL_LL_ADC_RESOLUTION_CMAKE=HAL_LL_ADC_RESOLUTION_10_BIT") +elseif(${MCU_NAME_FIRST_7} MATCHES "PIC32MZ") + list(APPEND hal_ll_def_list "HAL_LL_ADC_RESOLUTION_CMAKE=HAL_LL_ADC_RESOLUTION_12_BIT") +endif() + +if(${MCU_NAME} MATCHES "(^PIC32MX[1-7][1-79][045]F(512|256|128|064|032|016)[HLBCD]B?$)") + set(adc_implementation "implementation_1/hal_ll_adc.c") +elseif (${MCU_NAME} MATCHES "(^PIC32MZ(0512|1024|2048)EF[FEHMGK](064|100|124|144)$)") + set(adc_implementation "implementation_2/hal_ll_adc.c") +endif() +## END ADC + +## BEGIN PMD +if (${MCU_NAME} MATCHES "(^PIC32MX([12][0-9]{2}|330|350|370|430|450|470|530|550|570)F(512|256|128|064|032|016)[HLBCD]B?$|^PIC32MZ(0512|1024|2048)EF[FEHMGK](064|100|124|144)$)") + list(APPEND hal_ll_def_list "HAL_LL_PERIPHERAL_MODULE_DISABLE") +endif() +## END PMD + +list(APPEND hal_ll_def_list "MACRO_USAGE_ADC") + +mikrosdk_add_library(lib_hal_ll_adc MikroSDK.HalLowLevel.ADC + ${adc_implementation} + ../../include/hal_ll_target.h + ../../include/hal_ll_slrcon_map.h + ../../include/hal_ll_odcon_map.h +## BEGIN ADC + ../../include/adc/hal_ll_adc.h + ../../include/adc/hal_ll_analog_in_map.h +## END ADC +) + +target_compile_definitions(lib_hal_ll_adc PUBLIC + ${hal_ll_def_list} +) + +target_link_libraries(lib_hal_ll_adc PUBLIC + MikroC.Core + MikroSDK.HalLowLevelCore + MikroSDK.HalLowLevelCommon +) + +string(TOLOWER ${MCU_NAME} MCU_HEADER_PATH_LOWER) +target_include_directories(lib_hal_ll_adc + PRIVATE + ../../include + ../../include/gpio + #BEGINADC + ../../include/adc + #ENDADC + INTERFACE + $ + $ + $ + $ + + $ + $ +) + +mikrosdk_install(MikroSDK.HalLowLevel.ADC) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.ADC ../../include/adc/hal_ll_adc.h) diff --git a/targets/pic_32bit/mikroe/pic32/src/gpio/CMakeLists.txt b/targets/pic_32bit/mikroe/pic32/src/gpio/CMakeLists.txt index 80dba05b6..e444c2e73 100644 --- a/targets/pic_32bit/mikroe/pic32/src/gpio/CMakeLists.txt +++ b/targets/pic_32bit/mikroe/pic32/src/gpio/CMakeLists.txt @@ -1,88 +1,88 @@ -## ./targets/pic_32bit/mikroe/pic32/src/gpio/CMakeLists.txt -set(hal_ll_def_list "") - -## BEGIN GPIO -if(${MCU_NAME} MATCHES "PIC32") - string(SUBSTRING ${MCU_NAME} 0 5 MCU_NAME_FIRST_5) - string(SUBSTRING ${MCU_NAME} 0 7 MCU_NAME_FIRST_7) - string(SUBSTRING ${MCU_NAME} 0 8 MCU_NAME_FIRST_8) - string(SUBSTRING ${MCU_NAME} 0 10 MCU_NAME_FIRST_10) - - list(APPEND hal_ll_def_list ${MCU_NAME}) - list(APPEND hal_ll_def_list ${MCU_NAME_FIRST_5}xx) - list(APPEND hal_ll_def_list ${MCU_NAME_FIRST_7}xx) - list(APPEND hal_ll_def_list ${MCU_NAME_FIRST_8}xx) - list(APPEND hal_ll_def_list ${MCU_NAME_FIRST_10}xx) - - list(APPEND hal_ll_def_list "__pic32__") -else() - list(APPEND hal_ll_def_list "__family_not_supported__") -endif() - -if(${MCU_NAME} MATCHES "(^PIC32MX[1-7][1-79][045]F(512|256|128|064|032|016)[HLBCD]B?$|^PIC32MZ(0512|1024|2048)EF[FEHMGK](064|100|124|144)$)") - list(APPEND hal_ll_def_list "__hal_ll_gpio_subset_1__") - set(gpio_implementation "implementation_1/hal_ll_gpio.c") - set(gpio_subimplementation "implementation_1/subimplementation_1/hal_ll_gpio_port.c") - # Match PIC32MX MCUs where analog pins are set by clearing respective register bit - if (${MCU_NAME} MATCHES "(^PIC32MX[34][246][0]F(032|064|128|256|512)[HL]$)|(^PIC32MX[567][3679][45]F(064|128|256|512)[HL]$)") - list(APPEND hal_ll_def_list "MARK_AS_DIGITAL=set_reg_bit") - list(APPEND hal_ll_def_list "MARK_AS_ANALOG=clear_reg_bit") - # Match PIC32MZ and PIC32MX MCUs where analog pins are set by setting respective register bit - elseif(${MCU_NAME} MATCHES "(^PIC32MX[12][12357][0]F(016|032|064|128|256)[BCD]B?$)|(^PIC32MX[34][357][0]F(064|128|256|512)[HL]B?$)|(^PIC32MX[125][2357][0]F(064|128|256|512)[HL]$)|(^PIC32MZ(0512|1024|2048)EF[E-HKM](064|100|124|144)$)") - list(APPEND hal_ll_def_list "MARK_AS_DIGITAL=clear_reg_bit") - list(APPEND hal_ll_def_list "MARK_AS_ANALOG=set_reg_bit") - endif() -endif() -## END GPIO - -## BEGIN PMD -if (${MCU_NAME} MATCHES "(^PIC32MX([12][0-9]{2}|330|350|370|430|450|470|530|550|570)F(512|256|128|064|032|016)[HLBCD]B?$|^PIC32MZ(0512|1024|2048)EF[FEHMGK](064|100|124|144)$)") - list(APPEND hal_ll_def_list "HAL_LL_PERIPHERAL_MODULE_DISABLE") -endif() -## END PMD - -list(APPEND hal_ll_def_list "MACRO_USAGE_GPIO") - -mikrosdk_add_library(lib_hal_ll_gpio MikroSDK.HalLowLevel.GPIO - ${gpio_implementation} - ${gpio_subimplementation} - - ../../include/hal_ll_target.h - ../../include/hal_ll_slrcon_map.h - ../../include/hal_ll_odcon_map.h -## BEGIN GPIO - ../../include/gpio/hal_ll_gpio.h - ../../include/gpio/hal_ll_gpio_port.h - ../../include/gpio/hal_ll_gpio_constants.h -## END GPIO -) - -target_compile_definitions(lib_hal_ll_gpio PUBLIC - ${hal_ll_def_list} -) - -target_link_libraries(lib_hal_ll_gpio PUBLIC - MikroC.Core - MikroSDK.HalLowLevelCore - MikroSDK.HalLowLevelCommon -) - -string(TOLOWER ${MCU_NAME} MCU_HEADER_PATH_LOWER) -target_include_directories(lib_hal_ll_gpio - PRIVATE - ../../include - ../../include/gpio - #BEGINADC - ../../include/adc - #ENDADC - INTERFACE - $ - $ - $ - - $ - $ -) - -mikrosdk_install(MikroSDK.HalLowLevel.GPIO) -install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.GPIO ../../include/gpio/hal_ll_gpio.h ../../include/gpio/hal_ll_gpio_constants.h ../../include/gpio/hal_ll_gpio_port.h) +## ./targets/pic_32bit/mikroe/pic32/src/gpio/CMakeLists.txt +set(hal_ll_def_list "") + +## BEGIN GPIO +if(${MCU_NAME} MATCHES "PIC32") + string(SUBSTRING ${MCU_NAME} 0 5 MCU_NAME_FIRST_5) + string(SUBSTRING ${MCU_NAME} 0 7 MCU_NAME_FIRST_7) + string(SUBSTRING ${MCU_NAME} 0 8 MCU_NAME_FIRST_8) + string(SUBSTRING ${MCU_NAME} 0 10 MCU_NAME_FIRST_10) + + list(APPEND hal_ll_def_list ${MCU_NAME}) + list(APPEND hal_ll_def_list ${MCU_NAME_FIRST_5}xx) + list(APPEND hal_ll_def_list ${MCU_NAME_FIRST_7}xx) + list(APPEND hal_ll_def_list ${MCU_NAME_FIRST_8}xx) + list(APPEND hal_ll_def_list ${MCU_NAME_FIRST_10}xx) + + list(APPEND hal_ll_def_list "__pic32__") +else() + list(APPEND hal_ll_def_list "__family_not_supported__") +endif() + +if(${MCU_NAME} MATCHES "(^PIC32MX[1-7][1-79][045]F(512|256|128|064|032|016)[HLBCD]B?$|^PIC32MZ(0512|1024|2048)EF[FEHMGK](064|100|124|144)$)") + list(APPEND hal_ll_def_list "__hal_ll_gpio_subset_1__") + set(gpio_implementation "implementation_1/hal_ll_gpio.c") + set(gpio_subimplementation "implementation_1/subimplementation_1/hal_ll_gpio_port.c") + # Match PIC32MX MCUs where analog pins are set by clearing respective register bit + if (${MCU_NAME} MATCHES "(^PIC32MX[34][246][0]F(032|064|128|256|512)[HL]$)|(^PIC32MX[567][3679][45]F(064|128|256|512)[HL]$)") + list(APPEND hal_ll_def_list "MARK_AS_DIGITAL=set_reg_bit") + list(APPEND hal_ll_def_list "MARK_AS_ANALOG=clear_reg_bit") + # Match PIC32MZ and PIC32MX MCUs where analog pins are set by setting respective register bit + elseif(${MCU_NAME} MATCHES "(^PIC32MX[12][12357][0]F(016|032|064|128|256)[BCD]B?$)|(^PIC32MX[34][357][0]F(064|128|256|512)[HL]B?$)|(^PIC32MX[125][2357][0]F(064|128|256|512)[HL]$)|(^PIC32MZ(0512|1024|2048)EF[E-HKM](064|100|124|144)$)") + list(APPEND hal_ll_def_list "MARK_AS_DIGITAL=clear_reg_bit") + list(APPEND hal_ll_def_list "MARK_AS_ANALOG=set_reg_bit") + endif() +endif() +## END GPIO + +## BEGIN PMD +if (${MCU_NAME} MATCHES "(^PIC32MX([12][0-9]{2}|330|350|370|430|450|470|530|550|570)F(512|256|128|064|032|016)[HLBCD]B?$|^PIC32MZ(0512|1024|2048)EF[FEHMGK](064|100|124|144)$)") + list(APPEND hal_ll_def_list "HAL_LL_PERIPHERAL_MODULE_DISABLE") +endif() +## END PMD + +list(APPEND hal_ll_def_list "MACRO_USAGE_GPIO") + +mikrosdk_add_library(lib_hal_ll_gpio MikroSDK.HalLowLevel.GPIO + ${gpio_implementation} + ${gpio_subimplementation} + + ../../include/hal_ll_target.h + ../../include/hal_ll_slrcon_map.h + ../../include/hal_ll_odcon_map.h +## BEGIN GPIO + ../../include/gpio/hal_ll_gpio.h + ../../include/gpio/hal_ll_gpio_port.h + ../../include/gpio/hal_ll_gpio_constants.h +## END GPIO +) + +target_compile_definitions(lib_hal_ll_gpio PUBLIC + ${hal_ll_def_list} +) + +target_link_libraries(lib_hal_ll_gpio PUBLIC + MikroC.Core + MikroSDK.HalLowLevelCore + MikroSDK.HalLowLevelCommon +) + +string(TOLOWER ${MCU_NAME} MCU_HEADER_PATH_LOWER) +target_include_directories(lib_hal_ll_gpio + PRIVATE + ../../include + ../../include/gpio + #BEGINADC + ../../include/adc + #ENDADC + INTERFACE + $ + $ + $ + + $ + $ +) + +mikrosdk_install(MikroSDK.HalLowLevel.GPIO) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.GPIO ../../include/gpio/hal_ll_gpio.h ../../include/gpio/hal_ll_gpio_constants.h ../../include/gpio/hal_ll_gpio_port.h) diff --git a/targets/pic_32bit/mikroe/pic32/src/hal_ll/CMakeLists.txt b/targets/pic_32bit/mikroe/pic32/src/hal_ll/CMakeLists.txt index 9d3818763..f590ee265 100644 --- a/targets/pic_32bit/mikroe/pic32/src/hal_ll/CMakeLists.txt +++ b/targets/pic_32bit/mikroe/pic32/src/hal_ll/CMakeLists.txt @@ -1,15 +1,15 @@ -## ./targets/pic_32bit/mikroe/pic32/src/hal_ll/CMakeLists.txt -add_library(lib_hal_ll INTERFACE) - -add_library(MikroSDK.HalLowLevel ALIAS lib_hal_ll) - -set(module_list "") -set(module_list_supported "") -set_module_support(module_list module_list_supported ${MCU_NAME} "hal_ll_layer") - -target_link_libraries(lib_hal_ll INTERFACE - ${module_list} -) - -mikrosdk_install(MikroSDK.HalLowLevel) -install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel ../../include/hal_ll_target.h ../../include/hal_ll_pin_names.h ../../include/hal_ll_target_names.h) +## ./targets/pic_32bit/mikroe/pic32/src/hal_ll/CMakeLists.txt +add_library(lib_hal_ll INTERFACE) + +add_library(MikroSDK.HalLowLevel ALIAS lib_hal_ll) + +set(module_list "") +set(module_list_supported "") +set_module_support(module_list module_list_supported ${MCU_NAME} "hal_ll_layer") + +target_link_libraries(lib_hal_ll INTERFACE + ${module_list} +) + +mikrosdk_install(MikroSDK.HalLowLevel) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel ../../include/hal_ll_target.h ../../include/hal_ll_pin_names.h ../../include/hal_ll_target_names.h) diff --git a/targets/pic_32bit/mikroe/pic32/src/i2c/CMakeLists.txt b/targets/pic_32bit/mikroe/pic32/src/i2c/CMakeLists.txt index 487fe7005..9ce445b8a 100644 --- a/targets/pic_32bit/mikroe/pic32/src/i2c/CMakeLists.txt +++ b/targets/pic_32bit/mikroe/pic32/src/i2c/CMakeLists.txt @@ -1,85 +1,85 @@ -## ./targets/pic_32bit/mikroe/pic32/src/i2c/CMakeLists.txt -set(hal_ll_def_list "") - -## BEGIN I2C -if (${MCU_NAME} MATCHES "PIC32" ) - string(SUBSTRING ${MCU_NAME} 0 5 MCU_NAME_FIRST_5) - string(SUBSTRING ${MCU_NAME} 0 7 MCU_NAME_FIRST_7) - string(SUBSTRING ${MCU_NAME} 0 8 MCU_NAME_FIRST_8) - string(SUBSTRING ${MCU_NAME} 0 10 MCU_NAME_FIRST_10) - - list(APPEND hal_ll_def_list ${MCU_NAME}) - list(APPEND hal_ll_def_list ${MCU_NAME_FIRST_5}xx) - list(APPEND hal_ll_def_list ${MCU_NAME_FIRST_7}xx) - list(APPEND hal_ll_def_list ${MCU_NAME_FIRST_8}xx) - list(APPEND hal_ll_def_list ${MCU_NAME_FIRST_10}xx) - - list(APPEND hal_ll_def_list "__pic32__") -else() - list(APPEND hal_ll_def_list "__family_not_supported__") -endif() - -if(${MCU_NAME} MATCHES "(^PIC32MX[1-7][1-79][045]F(512|256|128|064|032|016)[HLBCD]B?$|^PIC32MZ(0512|1024|2048)EF[FEHMGK](064|100|124|144)$)") - set(i2c_implementation "implementation_1/hal_ll_i2c_master.c") -endif() -## END I2C - -## BEGIN PMD -if(${MCU_NAME} MATCHES "(^PIC32MX([12][0-9]{2}|330|350|370|430|450|470|530|550|570)F(512|256|128|064|032|016)[HLBCD]B?$|^PIC32MZ(0512|1024|2048)EF[FEHMGK](064|100|124|144)$)") - list(APPEND "HAL_LL_PERIPHERAL_MODULE_DISABLE") -endif() -## END PMD - -list(APPEND hal_ll_def_list "MACRO_USAGE_I2C") - -if (NOT DEFINED _MSDK_TFT_TP_) - list(APPEND hal_ll_def_list "__TFT_NON_TSC2003__") -else() - if(${_MSDK_TFT_TP_} MATCHES "__TP_TSC2003__") - list(APPEND hal_ll_def_list "__TFT_RESISTIVE_TSC2003__") - else() - list(APPEND hal_ll_def_list "__TFT_NON_TSC2003__") - endif() -endif() - -mikrosdk_add_library(lib_hal_ll_i2c_master MikroSDK.HalLowLevel.I2C.Master - ${i2c_implementation} - - ../../include/hal_ll_target.h - ../../include/hal_ll_slrcon_map.h - ../../include/hal_ll_odcon_map.h -## BEGIN I2C - ../../include/i2c/hal_ll_i2c_master.h - ../../include/i2c/hal_ll_i2c_pin_map.h -## END I2C -) - -target_compile_definitions(lib_hal_ll_i2c_master PUBLIC - ${hal_ll_def_list} -) - -target_link_libraries(lib_hal_ll_i2c_master PUBLIC - MikroC.Core - MikroSDK.HalLowLevelCore - MikroSDK.HalLowLevelCommon -) - -string(TOLOWER ${MCU_NAME} MCU_HEADER_PATH_LOWER) -target_include_directories(lib_hal_ll_i2c_master - PRIVATE - ../../include - ../../include/gpio - #BEGINADC - ../../include/i2c - #ENDADC - INTERFACE - $ - $ - $ - - $ - $ -) - -mikrosdk_install(MikroSDK.HalLowLevel.I2C.Master) -install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.I2C.Master ../../include/i2c/hal_ll_i2c_master.h ../../include/i2c/hal_ll_i2c_pin_map.h) +## ./targets/pic_32bit/mikroe/pic32/src/i2c/CMakeLists.txt +set(hal_ll_def_list "") + +## BEGIN I2C +if (${MCU_NAME} MATCHES "PIC32" ) + string(SUBSTRING ${MCU_NAME} 0 5 MCU_NAME_FIRST_5) + string(SUBSTRING ${MCU_NAME} 0 7 MCU_NAME_FIRST_7) + string(SUBSTRING ${MCU_NAME} 0 8 MCU_NAME_FIRST_8) + string(SUBSTRING ${MCU_NAME} 0 10 MCU_NAME_FIRST_10) + + list(APPEND hal_ll_def_list ${MCU_NAME}) + list(APPEND hal_ll_def_list ${MCU_NAME_FIRST_5}xx) + list(APPEND hal_ll_def_list ${MCU_NAME_FIRST_7}xx) + list(APPEND hal_ll_def_list ${MCU_NAME_FIRST_8}xx) + list(APPEND hal_ll_def_list ${MCU_NAME_FIRST_10}xx) + + list(APPEND hal_ll_def_list "__pic32__") +else() + list(APPEND hal_ll_def_list "__family_not_supported__") +endif() + +if(${MCU_NAME} MATCHES "(^PIC32MX[1-7][1-79][045]F(512|256|128|064|032|016)[HLBCD]B?$|^PIC32MZ(0512|1024|2048)EF[FEHMGK](064|100|124|144)$)") + set(i2c_implementation "implementation_1/hal_ll_i2c_master.c") +endif() +## END I2C + +## BEGIN PMD +if(${MCU_NAME} MATCHES "(^PIC32MX([12][0-9]{2}|330|350|370|430|450|470|530|550|570)F(512|256|128|064|032|016)[HLBCD]B?$|^PIC32MZ(0512|1024|2048)EF[FEHMGK](064|100|124|144)$)") + list(APPEND "HAL_LL_PERIPHERAL_MODULE_DISABLE") +endif() +## END PMD + +list(APPEND hal_ll_def_list "MACRO_USAGE_I2C") + +if (NOT DEFINED _MSDK_TFT_TP_) + list(APPEND hal_ll_def_list "__TFT_NON_TSC2003__") +else() + if(${_MSDK_TFT_TP_} MATCHES "__TP_TSC2003__") + list(APPEND hal_ll_def_list "__TFT_RESISTIVE_TSC2003__") + else() + list(APPEND hal_ll_def_list "__TFT_NON_TSC2003__") + endif() +endif() + +mikrosdk_add_library(lib_hal_ll_i2c_master MikroSDK.HalLowLevel.I2C.Master + ${i2c_implementation} + + ../../include/hal_ll_target.h + ../../include/hal_ll_slrcon_map.h + ../../include/hal_ll_odcon_map.h +## BEGIN I2C + ../../include/i2c/hal_ll_i2c_master.h + ../../include/i2c/hal_ll_i2c_pin_map.h +## END I2C +) + +target_compile_definitions(lib_hal_ll_i2c_master PUBLIC + ${hal_ll_def_list} +) + +target_link_libraries(lib_hal_ll_i2c_master PUBLIC + MikroC.Core + MikroSDK.HalLowLevelCore + MikroSDK.HalLowLevelCommon +) + +string(TOLOWER ${MCU_NAME} MCU_HEADER_PATH_LOWER) +target_include_directories(lib_hal_ll_i2c_master + PRIVATE + ../../include + ../../include/gpio + #BEGINADC + ../../include/i2c + #ENDADC + INTERFACE + $ + $ + $ + + $ + $ +) + +mikrosdk_install(MikroSDK.HalLowLevel.I2C.Master) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.I2C.Master ../../include/i2c/hal_ll_i2c_master.h ../../include/i2c/hal_ll_i2c_pin_map.h) diff --git a/targets/pic_32bit/mikroe/pic32/src/one_wire/CMakeLists.txt b/targets/pic_32bit/mikroe/pic32/src/one_wire/CMakeLists.txt index 52e15989d..1ce120d52 100644 --- a/targets/pic_32bit/mikroe/pic32/src/one_wire/CMakeLists.txt +++ b/targets/pic_32bit/mikroe/pic32/src/one_wire/CMakeLists.txt @@ -1,31 +1,31 @@ -## ./targets/pic_32bit/mikroe/pic32/src/one_wire/CMakeLists.txt -set(hal_ll_def_list) -list(APPEND hal_ll_def_list "MACRO_USAGE_ONE_WIRE") - -mikrosdk_add_library(lib_hal_ll_one_wire MikroSDK.HalLowLevel.OneWire - hal_ll_one_wire.c - - ../../include/one_wire/hal_ll_one_wire.h -) - -target_compile_definitions(lib_hal_ll_one_wire PUBLIC - ${hal_ll_def_list} -) - -target_link_libraries(lib_hal_ll_one_wire PUBLIC - MikroC.Core - MikroSDK.HalLowLevel.GPIO - MikroSDK.HalLowLevelCommon -) -target_include_directories(lib_hal_ll_one_wire - PRIVATE - ../../include/one_wire - INTERFACE - $ - $ - $ - $ -) - -mikrosdk_install(MikroSDK.HalLowLevel.OneWire) -install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.OneWire ../../include/one_wire/hal_ll_one_wire.h) +## ./targets/pic_32bit/mikroe/pic32/src/one_wire/CMakeLists.txt +set(hal_ll_def_list) +list(APPEND hal_ll_def_list "MACRO_USAGE_ONE_WIRE") + +mikrosdk_add_library(lib_hal_ll_one_wire MikroSDK.HalLowLevel.OneWire + hal_ll_one_wire.c + + ../../include/one_wire/hal_ll_one_wire.h +) + +target_compile_definitions(lib_hal_ll_one_wire PUBLIC + ${hal_ll_def_list} +) + +target_link_libraries(lib_hal_ll_one_wire PUBLIC + MikroC.Core + MikroSDK.HalLowLevel.GPIO + MikroSDK.HalLowLevelCommon +) +target_include_directories(lib_hal_ll_one_wire + PRIVATE + ../../include/one_wire + INTERFACE + $ + $ + $ + $ +) + +mikrosdk_install(MikroSDK.HalLowLevel.OneWire) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.OneWire ../../include/one_wire/hal_ll_one_wire.h) diff --git a/targets/pic_32bit/mikroe/pic32/src/spi_master/CMakeLists.txt b/targets/pic_32bit/mikroe/pic32/src/spi_master/CMakeLists.txt index c01d5ddbc..cd8dc3915 100644 --- a/targets/pic_32bit/mikroe/pic32/src/spi_master/CMakeLists.txt +++ b/targets/pic_32bit/mikroe/pic32/src/spi_master/CMakeLists.txt @@ -1,93 +1,93 @@ -## ./targets/pic_32bit/mikroe/pic32/src/spi_master/CMakeLists.txt -set(hal_ll_def_list "") - -## BEGIN I2C -if(${MCU_NAME} MATCHES "PIC32") - string(SUBSTRING ${MCU_NAME} 0 5 MCU_NAME_FIRST_5) - string(SUBSTRING ${MCU_NAME} 0 7 MCU_NAME_FIRST_7) - string(SUBSTRING ${MCU_NAME} 0 8 MCU_NAME_FIRST_8) - string(SUBSTRING ${MCU_NAME} 0 10 MCU_NAME_FIRST_10) - - list(APPEND hal_ll_def_list ${MCU_NAME}) - list(APPEND hal_ll_def_list ${MCU_NAME_FIRST_5}xx) - list(APPEND hal_ll_def_list ${MCU_NAME_FIRST_7}xx) - list(APPEND hal_ll_def_list ${MCU_NAME_FIRST_8}xx) - list(APPEND hal_ll_def_list ${MCU_NAME_FIRST_10}xx) - - list(APPEND hal_ll_def_list "__pic32__") -else() - list(APPEND hal_ll_def_list "__family_not_supported__") -endif() - -## BEGIN SPI -if(${MCU_NAME} MATCHES "(^PIC32MX[1-7][1-79][045]F(512|256|128|064|032|016)[HLBCD]B?$|^PIC32MZ(0512|1024|2048)EF[FEHMGK](064|100|124|144)$)") - set(spi_master_implementation "implementation_1/hal_ll_spi_master.c") -endif() - ## Match group of PIC32MX MCU's which utilize SPIxBRG<12:0> register bits. - ## 1st datasheet -> https://ww1.microchip.com/downloads/en/DeviceDoc/PIC32MX1XX2XX%20283644-PIN_Datasheet_DS60001168L.pdf -if(${MCU_NAME} MATCHES "(^PIC32MX[12][12357][0]F(016|032|064|128|256)[BCD]B?$)") - list(APPEND hal_ll_def_list "SPI_BAUD_REG_13_BIT_RESOLUTION") - ## Match group of PIC32MX MCU's which utilize SPIxBRG<8:0> register bits. - ## 2nd datasheet -> https://ww1.microchip.com/downloads/en/DeviceDoc/PIC32MX330350370430450470_Datasheet_DS60001185H.pdf - ## 3rd datasheet -> https://ww1.microchip.com/downloads/en/DeviceDoc/61143H.pdf - ## 4th datasheet -> https://ww1.microchip.com/downloads/en/DeviceDoc/PIC32MX5XX6XX7XX_Family)Datasheet_DS60001156K.pdf - ## 5th datasheet -> https://ww1.microchip.com/downloads/en/DeviceDoc/PIC32MX1XX2XX5XX%2064100-PIN_Family_60001290F.pdf -elseif(${MCU_NAME} MATCHES "(^PIC32MX[34][357][0]F(064|128|256|512)[HL]B?$)|(^PIC32MX[34][246][0]F(032|064|128|256|512)[HL]$)|(^PIC32MX[567][3679][45]F(064|128|256|512)[HL]$)|(^PIC32MX[125][2357][0]F(064|128|256|512)[HL]$)") - list(APPEND hal_ll_def_list "SPI_BAUD_REG_9_BIT_RESOLUTION") - ## Match group of PIC32MZ MCU's which utilize both SPIxBRG<8:0> and SPIxBRG<12:0> register bits. - ## 6th datasheet -> https://ww1.microchip.com/downloads/en/DeviceDoc/PIC32MZ%20EF%20Family%20Datasheet_DS60001320G.pdf -elseif(${MCU_NAME} MATCHES "(^PIC32MZ(0512|1024|2048)EF[FEHMGK](064|100|124|144)$)") - list(APPEND hal_ll_def_list "SPI_BAUD_REG_9_AND_13_BIT_RESOLUTION_MZ") -endif() -## END SPI - -## BEGIN PMD -if(${MCU_NAME} MATCHES "(^PIC32MX([12][0-9]{2}|330|350|370|430|450|470|530|550|570)F(512|256|128|064|032|016)[HLBCD]B?$|^PIC32MZ(0512|1024|2048)EF[FEHMGK](064|100|124|144)$)") - list(APPEND hal_ll_def_list "HAL_LL_PERIPHERAL_MODULE_DISABLE") -endif() -## END PMD - -list(APPEND hal_ll_def_list "MACRO_USAGE_SPI") - -mikrosdk_add_library(lib_hal_ll_spi_master MikroSDK.HalLowLevel.SPI.Master - ${spi_master_implementation} - - ../../include/hal_ll_target.h - ../../include/hal_ll_slrcon_map.h - ../../include/hal_ll_odcon_map.h -## BEGIN SPI - ../../include/spi_master/hal_ll_spi_master.h - ../../include/spi_master/hal_ll_spi_master_pin_map.h -## END SPI -) - -target_compile_definitions(lib_hal_ll_spi_master PUBLIC - ${hal_ll_def_list} -) - -target_link_libraries(lib_hal_ll_spi_master PUBLIC - MikroC.Core - MikroSDK.HalLowLevel.PPS - MikroSDK.HalLowLevelCore - MikroSDK.HalLowLevelCommon -) - -string(TOLOWER ${MCU_NAME} MCU_HEADER_PATH_LOWER) -target_include_directories(lib_hal_ll_spi_master - PRIVATE - ../../include - ../../include/gpio -## BEGIN SPI - ../../include/spi_master -## END SPI - INTERFACE - $ - $ - $ - - $ - $ -) - -mikrosdk_install(MikroSDK.HalLowLevel.SPI.Master) -install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.SPI.Master ../../include/spi_master/hal_ll_spi_master.h ../../include/spi_master/hal_ll_spi_master_pin_map.h) +## ./targets/pic_32bit/mikroe/pic32/src/spi_master/CMakeLists.txt +set(hal_ll_def_list "") + +## BEGIN I2C +if(${MCU_NAME} MATCHES "PIC32") + string(SUBSTRING ${MCU_NAME} 0 5 MCU_NAME_FIRST_5) + string(SUBSTRING ${MCU_NAME} 0 7 MCU_NAME_FIRST_7) + string(SUBSTRING ${MCU_NAME} 0 8 MCU_NAME_FIRST_8) + string(SUBSTRING ${MCU_NAME} 0 10 MCU_NAME_FIRST_10) + + list(APPEND hal_ll_def_list ${MCU_NAME}) + list(APPEND hal_ll_def_list ${MCU_NAME_FIRST_5}xx) + list(APPEND hal_ll_def_list ${MCU_NAME_FIRST_7}xx) + list(APPEND hal_ll_def_list ${MCU_NAME_FIRST_8}xx) + list(APPEND hal_ll_def_list ${MCU_NAME_FIRST_10}xx) + + list(APPEND hal_ll_def_list "__pic32__") +else() + list(APPEND hal_ll_def_list "__family_not_supported__") +endif() + +## BEGIN SPI +if(${MCU_NAME} MATCHES "(^PIC32MX[1-7][1-79][045]F(512|256|128|064|032|016)[HLBCD]B?$|^PIC32MZ(0512|1024|2048)EF[FEHMGK](064|100|124|144)$)") + set(spi_master_implementation "implementation_1/hal_ll_spi_master.c") +endif() + ## Match group of PIC32MX MCU's which utilize SPIxBRG<12:0> register bits. + ## 1st datasheet -> https://ww1.microchip.com/downloads/en/DeviceDoc/PIC32MX1XX2XX%20283644-PIN_Datasheet_DS60001168L.pdf +if(${MCU_NAME} MATCHES "(^PIC32MX[12][12357][0]F(016|032|064|128|256)[BCD]B?$)") + list(APPEND hal_ll_def_list "SPI_BAUD_REG_13_BIT_RESOLUTION") + ## Match group of PIC32MX MCU's which utilize SPIxBRG<8:0> register bits. + ## 2nd datasheet -> https://ww1.microchip.com/downloads/en/DeviceDoc/PIC32MX330350370430450470_Datasheet_DS60001185H.pdf + ## 3rd datasheet -> https://ww1.microchip.com/downloads/en/DeviceDoc/61143H.pdf + ## 4th datasheet -> https://ww1.microchip.com/downloads/en/DeviceDoc/PIC32MX5XX6XX7XX_Family)Datasheet_DS60001156K.pdf + ## 5th datasheet -> https://ww1.microchip.com/downloads/en/DeviceDoc/PIC32MX1XX2XX5XX%2064100-PIN_Family_60001290F.pdf +elseif(${MCU_NAME} MATCHES "(^PIC32MX[34][357][0]F(064|128|256|512)[HL]B?$)|(^PIC32MX[34][246][0]F(032|064|128|256|512)[HL]$)|(^PIC32MX[567][3679][45]F(064|128|256|512)[HL]$)|(^PIC32MX[125][2357][0]F(064|128|256|512)[HL]$)") + list(APPEND hal_ll_def_list "SPI_BAUD_REG_9_BIT_RESOLUTION") + ## Match group of PIC32MZ MCU's which utilize both SPIxBRG<8:0> and SPIxBRG<12:0> register bits. + ## 6th datasheet -> https://ww1.microchip.com/downloads/en/DeviceDoc/PIC32MZ%20EF%20Family%20Datasheet_DS60001320G.pdf +elseif(${MCU_NAME} MATCHES "(^PIC32MZ(0512|1024|2048)EF[FEHMGK](064|100|124|144)$)") + list(APPEND hal_ll_def_list "SPI_BAUD_REG_9_AND_13_BIT_RESOLUTION_MZ") +endif() +## END SPI + +## BEGIN PMD +if(${MCU_NAME} MATCHES "(^PIC32MX([12][0-9]{2}|330|350|370|430|450|470|530|550|570)F(512|256|128|064|032|016)[HLBCD]B?$|^PIC32MZ(0512|1024|2048)EF[FEHMGK](064|100|124|144)$)") + list(APPEND hal_ll_def_list "HAL_LL_PERIPHERAL_MODULE_DISABLE") +endif() +## END PMD + +list(APPEND hal_ll_def_list "MACRO_USAGE_SPI") + +mikrosdk_add_library(lib_hal_ll_spi_master MikroSDK.HalLowLevel.SPI.Master + ${spi_master_implementation} + + ../../include/hal_ll_target.h + ../../include/hal_ll_slrcon_map.h + ../../include/hal_ll_odcon_map.h +## BEGIN SPI + ../../include/spi_master/hal_ll_spi_master.h + ../../include/spi_master/hal_ll_spi_master_pin_map.h +## END SPI +) + +target_compile_definitions(lib_hal_ll_spi_master PUBLIC + ${hal_ll_def_list} +) + +target_link_libraries(lib_hal_ll_spi_master PUBLIC + MikroC.Core + MikroSDK.HalLowLevel.PPS + MikroSDK.HalLowLevelCore + MikroSDK.HalLowLevelCommon +) + +string(TOLOWER ${MCU_NAME} MCU_HEADER_PATH_LOWER) +target_include_directories(lib_hal_ll_spi_master + PRIVATE + ../../include + ../../include/gpio +## BEGIN SPI + ../../include/spi_master +## END SPI + INTERFACE + $ + $ + $ + + $ + $ +) + +mikrosdk_install(MikroSDK.HalLowLevel.SPI.Master) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.SPI.Master ../../include/spi_master/hal_ll_spi_master.h ../../include/spi_master/hal_ll_spi_master_pin_map.h) diff --git a/targets/pic_32bit/mikroe/pic32/src/tim/CMakeLists.txt b/targets/pic_32bit/mikroe/pic32/src/tim/CMakeLists.txt index 62aa248a0..e6e5b8ab8 100644 --- a/targets/pic_32bit/mikroe/pic32/src/tim/CMakeLists.txt +++ b/targets/pic_32bit/mikroe/pic32/src/tim/CMakeLists.txt @@ -1,75 +1,75 @@ -## ./targets/pic_32bit/mikroe/pic32/src/tim/CMakeLists.txt -set(hal_ll_def_list "") - -## BEGIN TIM -if(${MCU_NAME} MATCHES "PIC32") - string(SUBSTRING ${MCU_NAME} 0 5 MCU_NAME_FIRST_5) - string(SUBSTRING ${MCU_NAME} 0 7 MCU_NAME_FIRST_7) - string(SUBSTRING ${MCU_NAME} 0 8 MCU_NAME_FIRST_8) - string(SUBSTRING ${MCU_NAME} 0 10 MCU_NAME_FIRST_10) - - list(APPEND hal_ll_def_list ${MCU_NAME}) - list(APPEND hal_ll_def_list ${MCU_NAME_FIRST_5}xx) - list(APPEND hal_ll_def_list ${MCU_NAME_FIRST_7}xx) - list(APPEND hal_ll_def_list ${MCU_NAME_FIRST_8}xx) - list(APPEND hal_ll_def_list ${MCU_NAME_FIRST_10}xx) - - list(APPEND hal_ll_def_list "__pic32__") -else() - list(APPEND hal_ll_def_list "__family_not_supported__") -endif() - -if(${MCU_NAME} MATCHES "(^PIC32MX[1-7][1-79][045]F(512|256|128|064|032|016)[HLBCD]B?$|^PIC32MZ(0512|1024|2048)EF[FEHMGK](064|100|124|144)$)") - set(tim_implementation "implementation_1/hal_ll_tim.c") -endif() -## END TIM - -## BEGIN PMD -if(${MCU_NAME} MATCHES "(^PIC32MX([12][0-9]{2}|330|350|370|430|450|470|530|550|570)F(512|256|128|064|032|016)[HLBCD]B?$|^PIC32MZ(0512|1024|2048)EF[FEHMGK](064|100|124|144)$)") - list(APPEND hal_ll_def_list "HAL_LL_PERIPHERAL_MODULE_DISABLE") -endif() -## END PMD - -list(APPEND hal_ll_def_list "MACRO_USAGE_TIM") - -mikrosdk_add_library(lib_hal_ll_tim MikroSDK.HalLowLevel.TIM - ${tim_implementation} - - ../../include/hal_ll_target.h - ../../include/hal_ll_slrcon_map.h - ../../include/hal_ll_odcon_map.h -## BEGIN TIM - ../../include/tim/hal_ll_tim.h - ../../include/tim/hal_ll_tim_pin_map.h -## END TIM -) - -target_compile_definitions(lib_hal_ll_tim PUBLIC - ${hal_ll_def_list} -) - -target_link_libraries(lib_hal_ll_tim PUBLIC - MikroC.Core - MikroSDK.HalLowLevel.PPS - MikroSDK.HalLowLevelCore - MikroSDK.HalLowLevelCommon -) - -string(TOLOWER ${MCU_NAME} MCU_HEADER_PATH_LOWER) -target_include_directories(lib_hal_ll_tim - PRIVATE - ../../include - ../../include/gpio -## BEGIN TIM - ../../include/tim -## END TIM - INTERFACE - $ - $ - - $ - $ -) - -mikrosdk_install(MikroSDK.HalLowLevel.TIM) -install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.TIM ../../include/tim/hal_ll_tim.h ../../include/tim/hal_ll_tim_pin_map.h) +## ./targets/pic_32bit/mikroe/pic32/src/tim/CMakeLists.txt +set(hal_ll_def_list "") + +## BEGIN TIM +if(${MCU_NAME} MATCHES "PIC32") + string(SUBSTRING ${MCU_NAME} 0 5 MCU_NAME_FIRST_5) + string(SUBSTRING ${MCU_NAME} 0 7 MCU_NAME_FIRST_7) + string(SUBSTRING ${MCU_NAME} 0 8 MCU_NAME_FIRST_8) + string(SUBSTRING ${MCU_NAME} 0 10 MCU_NAME_FIRST_10) + + list(APPEND hal_ll_def_list ${MCU_NAME}) + list(APPEND hal_ll_def_list ${MCU_NAME_FIRST_5}xx) + list(APPEND hal_ll_def_list ${MCU_NAME_FIRST_7}xx) + list(APPEND hal_ll_def_list ${MCU_NAME_FIRST_8}xx) + list(APPEND hal_ll_def_list ${MCU_NAME_FIRST_10}xx) + + list(APPEND hal_ll_def_list "__pic32__") +else() + list(APPEND hal_ll_def_list "__family_not_supported__") +endif() + +if(${MCU_NAME} MATCHES "(^PIC32MX[1-7][1-79][045]F(512|256|128|064|032|016)[HLBCD]B?$|^PIC32MZ(0512|1024|2048)EF[FEHMGK](064|100|124|144)$)") + set(tim_implementation "implementation_1/hal_ll_tim.c") +endif() +## END TIM + +## BEGIN PMD +if(${MCU_NAME} MATCHES "(^PIC32MX([12][0-9]{2}|330|350|370|430|450|470|530|550|570)F(512|256|128|064|032|016)[HLBCD]B?$|^PIC32MZ(0512|1024|2048)EF[FEHMGK](064|100|124|144)$)") + list(APPEND hal_ll_def_list "HAL_LL_PERIPHERAL_MODULE_DISABLE") +endif() +## END PMD + +list(APPEND hal_ll_def_list "MACRO_USAGE_TIM") + +mikrosdk_add_library(lib_hal_ll_tim MikroSDK.HalLowLevel.TIM + ${tim_implementation} + + ../../include/hal_ll_target.h + ../../include/hal_ll_slrcon_map.h + ../../include/hal_ll_odcon_map.h +## BEGIN TIM + ../../include/tim/hal_ll_tim.h + ../../include/tim/hal_ll_tim_pin_map.h +## END TIM +) + +target_compile_definitions(lib_hal_ll_tim PUBLIC + ${hal_ll_def_list} +) + +target_link_libraries(lib_hal_ll_tim PUBLIC + MikroC.Core + MikroSDK.HalLowLevel.PPS + MikroSDK.HalLowLevelCore + MikroSDK.HalLowLevelCommon +) + +string(TOLOWER ${MCU_NAME} MCU_HEADER_PATH_LOWER) +target_include_directories(lib_hal_ll_tim + PRIVATE + ../../include + ../../include/gpio +## BEGIN TIM + ../../include/tim +## END TIM + INTERFACE + $ + $ + + $ + $ +) + +mikrosdk_install(MikroSDK.HalLowLevel.TIM) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.TIM ../../include/tim/hal_ll_tim.h ../../include/tim/hal_ll_tim_pin_map.h) diff --git a/targets/pic_32bit/mikroe/pic32/src/uart/CMakeLists.txt b/targets/pic_32bit/mikroe/pic32/src/uart/CMakeLists.txt index fb22892ab..196a1cd97 100644 --- a/targets/pic_32bit/mikroe/pic32/src/uart/CMakeLists.txt +++ b/targets/pic_32bit/mikroe/pic32/src/uart/CMakeLists.txt @@ -1,80 +1,80 @@ -## ./targets/pic_32bit/mikroe/pic32/src/uart/CMakeLists.txt -set(hal_ll_def_list "") - -## BEGIN UART -if(${MCU_NAME} MATCHES "PIC32") - string(SUBSTRING ${MCU_NAME} 0 5 MCU_NAME_FIRST_5) - string(SUBSTRING ${MCU_NAME} 0 7 MCU_NAME_FIRST_7) - string(SUBSTRING ${MCU_NAME} 0 8 MCU_NAME_FIRST_8) - string(SUBSTRING ${MCU_NAME} 0 10 MCU_NAME_FIRST_10) - - list(APPEND hal_ll_def_list ${MCU_NAME}) - list(APPEND hal_ll_def_list ${MCU_NAME_FIRST_5}xx) - list(APPEND hal_ll_def_list ${MCU_NAME_FIRST_7}xx) - list(APPEND hal_ll_def_list ${MCU_NAME_FIRST_8}xx) - list(APPEND hal_ll_def_list ${MCU_NAME_FIRST_10}xx) - - list(APPEND hal_ll_def_list "__pic32__") -else() - list(APPEND hal_ll_def_list "__family_not_supported__") -endif() - -if(${MCU_NAME} MATCHES "(^PIC32MX[1-7][1-79][045]F(512|256|128|064|032|016)[HLBCD]B?$|^PIC32MZ(0512|1024|2048)EF[FEHMGK](064|100|124|144)$)") - set(uart_implementation "implementation_1/hal_ll_uart.c") -endif() - -if(${MCU_NAME} MATCHES "(^PIC32MX[34][246][0]F(032|064|128|256|512)[HL]$)") - list(APPEND hal_ll_def_list "interrupt_case_1") -elseif(${MCU_NAME} MATCHES "(^PIC32MX(.+)$)") - list(APPEND hal_ll_def_list "interrupt_case_2") -endif() -## END UART - -## BEGIN PMD -if(${MCU_NAME} MATCHES "(^PIC32MX([12][0-9]{2}|330|350|370|430|450|470|530|550|570)F(512|256|128|064|032|016)[HLBCD]B?$|^PIC32MZ(0512|1024|2048)EF[FEHMGK](064|100|124|144)$)") - list(APPEND hal_ll_def_list "HAL_LL_PERIPHERAL_MODULE_DISABLE") -endif() -## END PMD - -list(APPEND hal_ll_def_list "MACRO_USAGE_UART") - -mikrosdk_add_library(lib_hal_ll_uart MikroSDK.HalLowLevel.UART - ${uart_implementation} - - ../../include/hal_ll_target.h - ../../include/hal_ll_slrcon_map.h - ../../include/hal_ll_odcon_map.h -## BEGIN UART - ../../include/uart/hal_ll_uart.h - ../../include/uart/hal_ll_uart_pin_map.h -## END UART -) - -target_compile_definitions(lib_hal_ll_uart PUBLIC - ${hal_ll_def_list} -) - -target_link_libraries(lib_hal_ll_uart PUBLIC - MikroC.Core - MikroSDK.HalLowLevel.PPS - MikroSDK.HalLowLevelCore - MikroSDK.HalLowLevelCommon -) - -string(TOLOWER ${MCU_NAME} MCU_HEADER_PATH_LOWER) -target_include_directories(lib_hal_ll_uart - PRIVATE - ../../include -## BEGIN UART - ../../include/uart -## END UART - INTERFACE - $ - $ - - $ - $ -) - -mikrosdk_install(MikroSDK.HalLowLevel.UART) -install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.UART ../../include/uart/hal_ll_uart.h ../../include/uart/hal_ll_uart_pin_map.h) +## ./targets/pic_32bit/mikroe/pic32/src/uart/CMakeLists.txt +set(hal_ll_def_list "") + +## BEGIN UART +if(${MCU_NAME} MATCHES "PIC32") + string(SUBSTRING ${MCU_NAME} 0 5 MCU_NAME_FIRST_5) + string(SUBSTRING ${MCU_NAME} 0 7 MCU_NAME_FIRST_7) + string(SUBSTRING ${MCU_NAME} 0 8 MCU_NAME_FIRST_8) + string(SUBSTRING ${MCU_NAME} 0 10 MCU_NAME_FIRST_10) + + list(APPEND hal_ll_def_list ${MCU_NAME}) + list(APPEND hal_ll_def_list ${MCU_NAME_FIRST_5}xx) + list(APPEND hal_ll_def_list ${MCU_NAME_FIRST_7}xx) + list(APPEND hal_ll_def_list ${MCU_NAME_FIRST_8}xx) + list(APPEND hal_ll_def_list ${MCU_NAME_FIRST_10}xx) + + list(APPEND hal_ll_def_list "__pic32__") +else() + list(APPEND hal_ll_def_list "__family_not_supported__") +endif() + +if(${MCU_NAME} MATCHES "(^PIC32MX[1-7][1-79][045]F(512|256|128|064|032|016)[HLBCD]B?$|^PIC32MZ(0512|1024|2048)EF[FEHMGK](064|100|124|144)$)") + set(uart_implementation "implementation_1/hal_ll_uart.c") +endif() + +if(${MCU_NAME} MATCHES "(^PIC32MX[34][246][0]F(032|064|128|256|512)[HL]$)") + list(APPEND hal_ll_def_list "interrupt_case_1") +elseif(${MCU_NAME} MATCHES "(^PIC32MX(.+)$)") + list(APPEND hal_ll_def_list "interrupt_case_2") +endif() +## END UART + +## BEGIN PMD +if(${MCU_NAME} MATCHES "(^PIC32MX([12][0-9]{2}|330|350|370|430|450|470|530|550|570)F(512|256|128|064|032|016)[HLBCD]B?$|^PIC32MZ(0512|1024|2048)EF[FEHMGK](064|100|124|144)$)") + list(APPEND hal_ll_def_list "HAL_LL_PERIPHERAL_MODULE_DISABLE") +endif() +## END PMD + +list(APPEND hal_ll_def_list "MACRO_USAGE_UART") + +mikrosdk_add_library(lib_hal_ll_uart MikroSDK.HalLowLevel.UART + ${uart_implementation} + + ../../include/hal_ll_target.h + ../../include/hal_ll_slrcon_map.h + ../../include/hal_ll_odcon_map.h +## BEGIN UART + ../../include/uart/hal_ll_uart.h + ../../include/uart/hal_ll_uart_pin_map.h +## END UART +) + +target_compile_definitions(lib_hal_ll_uart PUBLIC + ${hal_ll_def_list} +) + +target_link_libraries(lib_hal_ll_uart PUBLIC + MikroC.Core + MikroSDK.HalLowLevel.PPS + MikroSDK.HalLowLevelCore + MikroSDK.HalLowLevelCommon +) + +string(TOLOWER ${MCU_NAME} MCU_HEADER_PATH_LOWER) +target_include_directories(lib_hal_ll_uart + PRIVATE + ../../include +## BEGIN UART + ../../include/uart +## END UART + INTERFACE + $ + $ + + $ + $ +) + +mikrosdk_install(MikroSDK.HalLowLevel.UART) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.UART ../../include/uart/hal_ll_uart.h ../../include/uart/hal_ll_uart_pin_map.h) diff --git a/targets/pic_8bit/mikroe/CMakeLists.txt b/targets/pic_8bit/mikroe/CMakeLists.txt index fc1177de3..bd3e885cd 100644 --- a/targets/pic_8bit/mikroe/CMakeLists.txt +++ b/targets/pic_8bit/mikroe/CMakeLists.txt @@ -1,4 +1,4 @@ -## ./targets/pic_8bit/mikroe/CMakeLists.txt -add_subdirectory(common) -add_subdirectory(core) -add_subdirectory(pic18) +## ./targets/pic_8bit/mikroe/CMakeLists.txt +add_subdirectory(common) +add_subdirectory(core) +add_subdirectory(pic18) diff --git a/targets/pic_8bit/mikroe/core/CMakeLists.txt b/targets/pic_8bit/mikroe/core/CMakeLists.txt index eba9be4f1..e12c08251 100644 --- a/targets/pic_8bit/mikroe/core/CMakeLists.txt +++ b/targets/pic_8bit/mikroe/core/CMakeLists.txt @@ -1,63 +1,63 @@ -## ./targets/pic_8bit/mikroe/core/CMakeLists.txt -set(hal_ll_core_def_list "") -string(SUBSTRING ${MCU_NAME} 0 5 MEMAKE_MCU_NAME_FIRST_5) -string(SUBSTRING ${MCU_NAME} 0 6 MEMAKE_MCU_NAME_FIRST_6) - -if (${MCU_NAME} MATCHES "PIC18") - set(hal_ll_core_source "hal_ll_core.c") - list(APPEND hal_ll_core_def_list "__pic18__") - if(${MCU_NAME} MATCHES "PIC18LF") - list(APPEND hal_ll_core_def_list ${MEMAKE_MCU_NAME_FIRST_6}"xx") - else() - list(APPEND hal_ll_core_def_list ${MEMAKE_MCU_NAME_FIRST_5}"xx") - endif() -else() ## TODO Only PIC18 MCUs supported at the moment. - list(APPEND hal_ll_core_def_list ${MEMAKE_MCU_NAME_FIRST_5}"xx") - set(hal_ll_core_source "pic_not_supported.c") - set(hal_ll_core_def_list "__family_not_supported__") -endif() - -if (${MCU_NAME} MATCHES "^PIC18L?F[245][4-7]((K(42|83))|Q43)$") - list(APPEND hal_ll_core_def_list "INTCON_REG=INTCON0") -else() - list(APPEND hal_ll_core_def_list "INTCON_REG=INTCON") -endif() - -string(LENGTH ${MCU_NAME} MCU_NAME_LENGTH) -MATH(EXPR BEGIN_INDEX "${MCU_NAME_LENGTH}-3") -string(SUBSTRING ${MCU_NAME} ${BEGIN_INDEX} 3 MCU_NAME_LAST_3) - -## K42 and Q43 have different assembly instructions -if((${MCU_NAME_LAST_3} MATCHES "K42") OR (${MCU_NAME_LAST_3} MATCHES "Q43")) - list(APPEND hal_ll_core_def_list "__hal_ll_core_subimplementation_1__") -else() - list(APPEND hal_ll_core_def_list "__hal_ll_core_subimplementation_2__") -endif() - -mikrosdk_add_library(lib_hal_ll_core MikroSDK.HalLowLevelCore - src/${hal_ll_core_source} - - include/hal_ll_core_defines.h - include/hal_ll_core_port.h - include/hal_ll_core.h -) - -target_compile_definitions(lib_hal_ll_core - PUBLIC - ${hal_ll_core_def_list} -) - -target_link_libraries(lib_hal_ll_core PUBLIC - MikroC.Core - MikroSDK.HalLowLevelCommon -) - -target_include_directories(lib_hal_ll_core -PRIVATE - include -INTERFACE - $ - $ -) - -mikrosdk_install(MikroSDK.HalLowLevelCore) +## ./targets/pic_8bit/mikroe/core/CMakeLists.txt +set(hal_ll_core_def_list "") +string(SUBSTRING ${MCU_NAME} 0 5 MEMAKE_MCU_NAME_FIRST_5) +string(SUBSTRING ${MCU_NAME} 0 6 MEMAKE_MCU_NAME_FIRST_6) + +if (${MCU_NAME} MATCHES "PIC18") + set(hal_ll_core_source "hal_ll_core.c") + list(APPEND hal_ll_core_def_list "__pic18__") + if(${MCU_NAME} MATCHES "PIC18LF") + list(APPEND hal_ll_core_def_list ${MEMAKE_MCU_NAME_FIRST_6}"xx") + else() + list(APPEND hal_ll_core_def_list ${MEMAKE_MCU_NAME_FIRST_5}"xx") + endif() +else() ## TODO Only PIC18 MCUs supported at the moment. + list(APPEND hal_ll_core_def_list ${MEMAKE_MCU_NAME_FIRST_5}"xx") + set(hal_ll_core_source "pic_not_supported.c") + set(hal_ll_core_def_list "__family_not_supported__") +endif() + +if (${MCU_NAME} MATCHES "^PIC18L?F[245][4-7]((K(42|83))|Q43)$") + list(APPEND hal_ll_core_def_list "INTCON_REG=INTCON0") +else() + list(APPEND hal_ll_core_def_list "INTCON_REG=INTCON") +endif() + +string(LENGTH ${MCU_NAME} MCU_NAME_LENGTH) +MATH(EXPR BEGIN_INDEX "${MCU_NAME_LENGTH}-3") +string(SUBSTRING ${MCU_NAME} ${BEGIN_INDEX} 3 MCU_NAME_LAST_3) + +## K42 and Q43 have different assembly instructions +if((${MCU_NAME_LAST_3} MATCHES "K42") OR (${MCU_NAME_LAST_3} MATCHES "Q43")) + list(APPEND hal_ll_core_def_list "__hal_ll_core_subimplementation_1__") +else() + list(APPEND hal_ll_core_def_list "__hal_ll_core_subimplementation_2__") +endif() + +mikrosdk_add_library(lib_hal_ll_core MikroSDK.HalLowLevelCore + src/${hal_ll_core_source} + + include/hal_ll_core_defines.h + include/hal_ll_core_port.h + include/hal_ll_core.h +) + +target_compile_definitions(lib_hal_ll_core + PUBLIC + ${hal_ll_core_def_list} +) + +target_link_libraries(lib_hal_ll_core PUBLIC + MikroC.Core + MikroSDK.HalLowLevelCommon +) + +target_include_directories(lib_hal_ll_core +PRIVATE + include +INTERFACE + $ + $ +) + +mikrosdk_install(MikroSDK.HalLowLevelCore) diff --git a/targets/pic_8bit/mikroe/pic18/src/adc/CMakeLists.txt b/targets/pic_8bit/mikroe/pic18/src/adc/CMakeLists.txt index d474f9fff..17d8175a4 100644 --- a/targets/pic_8bit/mikroe/pic18/src/adc/CMakeLists.txt +++ b/targets/pic_8bit/mikroe/pic18/src/adc/CMakeLists.txt @@ -1,81 +1,81 @@ -## ./targets/pic_8bit/mikroe/pic18/src/adc/CMakeLists.txt -set(hal_ll_def_list "") - -if(${MCU_NAME} MATCHES "PIC18") - list(APPEND hal_ll_def_list "__pic18__") -else() - list(APPEND hal_ll_def_list "__family_not_supported__") -endif() - -list(APPEND hal_ll_def_list ${MCU_NAME}) - -## BEGIN ADC -list(APPEND hal_ll_def_list "HAL_LL_ADC_RESOLUTION_CMAKE=HAL_LL_ADC_RESOLUTION_12_BIT") - -string(LENGTH ${MCU_NAME} MEMAKE_MCU_NAME_LENGTH) -MATH(EXPR BEGIN_INDEX "${MEMAKE_MCU_NAME_LENGTH}-3") -MATH(EXPR BEGIN_INDEX_5TH "${MEMAKE_MCU_NAME_LENGTH}-5") -MATH(EXPR BEGIN_INDEX_4TH "${MEMAKE_MCU_NAME_LENGTH}-4") -string(SUBSTRING ${MCU_NAME} ${BEGIN_INDEX} 3 MCU_NAME_LAST_3) -string(SUBSTRING ${MCU_NAME} ${BEGIN_INDEX_5TH} 1 MCU_NAME_5TH_CHAR) -string(SUBSTRING ${MCU_NAME} ${BEGIN_INDEX_4TH} 1 MCU_NAME_4TH_CHAR) -string(SUBSTRING ${MCU_NAME} ${BEGIN_INDEX_5TH} 5 MCU_NAME_LAST5_CHARS) - -if (${MCU_NAME_LAST_3} MATCHES "J94") - set(adc_implementation "implementation_1") -elseif ((${MCU_NAME_LAST_3} MATCHES "K50") OR (${MCU_NAME} MATCHES "(^PIC18(((.+)4[56]K22$)|((.+)26K22$)))")) - set(adc_implementation "implementation_2/subimplementation_2") -elseif ((${MCU_NAME_LAST_3} MATCHES "K22") OR (${MCU_NAME_LAST_3} MATCHES "K80") OR (${MCU_NAME_LAST_3} MATCHES "K90")) - set(adc_implementation "implementation_2/subimplementation_1") -elseif ((${MCU_NAME_LAST_3} MATCHES "K40") OR (${MCU_NAME_LAST_3} MATCHES "Q10")) - set(adc_implementation "implementation_3/subimplementation_1") -elseif ((${MCU_NAME_LAST_3} MATCHES "K42") OR (${MCU_NAME_LAST_3} MATCHES "Q43")) - set(adc_implementation "implementation_3/subimplementation_2") -elseif ((${MCU_NAME_LAST_3} MATCHES "J50") OR (${MCU_NAME_LAST_3} MATCHES "J55") OR ((${MCU_NAME_LAST_3} MATCHES "J11") AND (${MCU_NAME_5TH_CHAR} MATCHES "8") AND ((${MCU_NAME_4TH_CHAR} MATCHES "6") OR (${MCU_NAME_4TH_CHAR} MATCHES "7"))) OR (${MCU_NAME_LAST5_CHARS} MATCHES "66J16") OR (${MCU_NAME_LAST5_CHARS} MATCHES "86J16")) - set(adc_implementation "implementation_4") -elseif (((${MCU_NAME_LAST_3} MATCHES "J13") OR (${MCU_NAME_LAST_3} MATCHES "J53")) AND ((${MCU_NAME_5TH_CHAR} MATCHES "2") OR (${MCU_NAME_5TH_CHAR} MATCHES "4"))) - set(adc_implementation "implementation_5/subimplementation_1") -elseif (${MCU_NAME_LAST_3} MATCHES "J11") - set(adc_implementation "implementation_5/subimplementation_2") -else() - set(adc_implementation "implementation_2/subimplementation_3") -endif() -## END ADC - -list(APPEND hal_ll_def_list "MACRO_USAGE_ADC") - -mikrosdk_add_library(lib_hal_ll_adc MikroSDK.HalLowLevel.ADC - ${adc_implementation}/hal_ll_adc.c - ../../include/hal_ll_target.h - ../../include/hal_ll_slrcon_map.h - ../../include/hal_ll_odcon_map.h - ../../include/adc/hal_ll_adc.h - ../../include/adc/hal_ll_analog_in_map.h - -) - -target_compile_definitions(lib_hal_ll_adc PUBLIC - ${hal_ll_def_list} -) - -target_link_libraries(lib_hal_ll_adc PUBLIC - MikroC.Core - MikroSDK.HalLowLevelCore - MikroSDK.HalLowLevelCommon -) -string(TOLOWER ${MCU_NAME} MCU_NAME_LOWER) -target_include_directories(lib_hal_ll_adc - PRIVATE - ../../include - ../../include/gpio - ../../include/adc - INTERFACE - $ - $ - $ - $ - $ -) - -mikrosdk_install(MikroSDK.HalLowLevel.ADC) -install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.ADC ../../include/adc/hal_ll_adc.h ../../include/adc/hal_ll_analog_in_map.h) +## ./targets/pic_8bit/mikroe/pic18/src/adc/CMakeLists.txt +set(hal_ll_def_list "") + +if(${MCU_NAME} MATCHES "PIC18") + list(APPEND hal_ll_def_list "__pic18__") +else() + list(APPEND hal_ll_def_list "__family_not_supported__") +endif() + +list(APPEND hal_ll_def_list ${MCU_NAME}) + +## BEGIN ADC +list(APPEND hal_ll_def_list "HAL_LL_ADC_RESOLUTION_CMAKE=HAL_LL_ADC_RESOLUTION_12_BIT") + +string(LENGTH ${MCU_NAME} MEMAKE_MCU_NAME_LENGTH) +MATH(EXPR BEGIN_INDEX "${MEMAKE_MCU_NAME_LENGTH}-3") +MATH(EXPR BEGIN_INDEX_5TH "${MEMAKE_MCU_NAME_LENGTH}-5") +MATH(EXPR BEGIN_INDEX_4TH "${MEMAKE_MCU_NAME_LENGTH}-4") +string(SUBSTRING ${MCU_NAME} ${BEGIN_INDEX} 3 MCU_NAME_LAST_3) +string(SUBSTRING ${MCU_NAME} ${BEGIN_INDEX_5TH} 1 MCU_NAME_5TH_CHAR) +string(SUBSTRING ${MCU_NAME} ${BEGIN_INDEX_4TH} 1 MCU_NAME_4TH_CHAR) +string(SUBSTRING ${MCU_NAME} ${BEGIN_INDEX_5TH} 5 MCU_NAME_LAST5_CHARS) + +if (${MCU_NAME_LAST_3} MATCHES "J94") + set(adc_implementation "implementation_1") +elseif ((${MCU_NAME_LAST_3} MATCHES "K50") OR (${MCU_NAME} MATCHES "(^PIC18(((.+)4[56]K22$)|((.+)26K22$)))")) + set(adc_implementation "implementation_2/subimplementation_2") +elseif ((${MCU_NAME_LAST_3} MATCHES "K22") OR (${MCU_NAME_LAST_3} MATCHES "K80") OR (${MCU_NAME_LAST_3} MATCHES "K90")) + set(adc_implementation "implementation_2/subimplementation_1") +elseif ((${MCU_NAME_LAST_3} MATCHES "K40") OR (${MCU_NAME_LAST_3} MATCHES "Q10")) + set(adc_implementation "implementation_3/subimplementation_1") +elseif ((${MCU_NAME_LAST_3} MATCHES "K42") OR (${MCU_NAME_LAST_3} MATCHES "Q43")) + set(adc_implementation "implementation_3/subimplementation_2") +elseif ((${MCU_NAME_LAST_3} MATCHES "J50") OR (${MCU_NAME_LAST_3} MATCHES "J55") OR ((${MCU_NAME_LAST_3} MATCHES "J11") AND (${MCU_NAME_5TH_CHAR} MATCHES "8") AND ((${MCU_NAME_4TH_CHAR} MATCHES "6") OR (${MCU_NAME_4TH_CHAR} MATCHES "7"))) OR (${MCU_NAME_LAST5_CHARS} MATCHES "66J16") OR (${MCU_NAME_LAST5_CHARS} MATCHES "86J16")) + set(adc_implementation "implementation_4") +elseif (((${MCU_NAME_LAST_3} MATCHES "J13") OR (${MCU_NAME_LAST_3} MATCHES "J53")) AND ((${MCU_NAME_5TH_CHAR} MATCHES "2") OR (${MCU_NAME_5TH_CHAR} MATCHES "4"))) + set(adc_implementation "implementation_5/subimplementation_1") +elseif (${MCU_NAME_LAST_3} MATCHES "J11") + set(adc_implementation "implementation_5/subimplementation_2") +else() + set(adc_implementation "implementation_2/subimplementation_3") +endif() +## END ADC + +list(APPEND hal_ll_def_list "MACRO_USAGE_ADC") + +mikrosdk_add_library(lib_hal_ll_adc MikroSDK.HalLowLevel.ADC + ${adc_implementation}/hal_ll_adc.c + ../../include/hal_ll_target.h + ../../include/hal_ll_slrcon_map.h + ../../include/hal_ll_odcon_map.h + ../../include/adc/hal_ll_adc.h + ../../include/adc/hal_ll_analog_in_map.h + +) + +target_compile_definitions(lib_hal_ll_adc PUBLIC + ${hal_ll_def_list} +) + +target_link_libraries(lib_hal_ll_adc PUBLIC + MikroC.Core + MikroSDK.HalLowLevelCore + MikroSDK.HalLowLevelCommon +) +string(TOLOWER ${MCU_NAME} MCU_NAME_LOWER) +target_include_directories(lib_hal_ll_adc + PRIVATE + ../../include + ../../include/gpio + ../../include/adc + INTERFACE + $ + $ + $ + $ + $ +) + +mikrosdk_install(MikroSDK.HalLowLevel.ADC) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.ADC ../../include/adc/hal_ll_adc.h ../../include/adc/hal_ll_analog_in_map.h) diff --git a/targets/pic_8bit/mikroe/pic18/src/gpio/CMakeLists.txt b/targets/pic_8bit/mikroe/pic18/src/gpio/CMakeLists.txt index 4f018630a..f4beaa955 100644 --- a/targets/pic_8bit/mikroe/pic18/src/gpio/CMakeLists.txt +++ b/targets/pic_8bit/mikroe/pic18/src/gpio/CMakeLists.txt @@ -1,79 +1,79 @@ -## ./targets/pic_8bit/mikroe/pic18/src/gpio/CMakeLists.txt -set(hal_ll_def_list "") -if(${MCU_NAME} MATCHES "PIC18") - list(APPEND hal_ll_def_list "__pic18__") -else() - list(APPEND hal_ll_def_list "__family_not_supported__") -endif() - -list(APPEND hal_ll_def_list ${MCU_NAME}) - -string(LENGTH ${MCU_NAME} MEMAKE_MCU_NAME_LENGTH) -MATH(EXPR BEGIN_INDEX "${MEMAKE_MCU_NAME_LENGTH}-3") -string(SUBSTRING ${MCU_NAME} ${BEGIN_INDEX} 3 MCU_NAME_LAST_3) -MATH(EXPR BEGIN_INDEX_4TH "${MEMAKE_MCU_NAME_LENGTH}-4") -string(SUBSTRING ${MCU_NAME} ${BEGIN_INDEX_4TH} 1 MCU_ON_4) -MATH(EXPR BEGIN_INDEX_4TH "${MEMAKE_MCU_NAME_LENGTH}-5") -string(SUBSTRING ${MCU_NAME} ${BEGIN_INDEX_4TH} 1 MCU_ON_5) -MATH(EXPR BEGIN_INDEX_5TH "${MEMAKE_MCU_NAME_LENGTH}-5") -string(SUBSTRING ${MCU_NAME} ${BEGIN_INDEX_5TH} 5 MCU_NAME_LAST_5) - -## BEGIN GPIO -if ((${MCU_NAME_LAST_3} MATCHES "J50") OR (${MCU_NAME_LAST_3} MATCHES "J55") OR ((${MCU_NAME_LAST_3} MATCHES "J11") AND ((${MCU_ON_5} MATCHES "8") AND ((${MCU_ON_4} MATCHES "6") OR (${MCU_ON_4} MATCHES "7")))) OR (${MCU_NAME_LAST_5} MATCHES "66J16") OR (${MCU_NAME_LAST_5} MATCHES "86J16")) - list(APPEND hal_ll_def_list "__hal_ll_gpio_subset_1__") - set(gpio_implementation "implementation_1") - set(gpio_subimplementation "subimplementation_2") -elseif (${MCU_NAME} MATCHES "PIC18") - list(APPEND hal_ll_def_list "__hal_ll_gpio_subset_1__") - set(gpio_implementation "implementation_1") - set(gpio_subimplementation "subimplementation_1") -else() - list(APPEND hal_ll_def_list "__hal_ll_gpio_not_supported__") -endif() - -## Specific PIC chips have shared SFR addresses -## Page number 82 -- http://ww1.microchip.com/downloads/en/devicedoc/39775b.pdf -if (${MCU_NAME} MATCHES "(^PIC18F[68][5-7]J5[05]$)") - list(APPEND hal_ll_def_list "__hal_ll_shared_sfrs__") -endif() -## END GPIO - -list(APPEND hal_ll_def_list "MACRO_USAGE_GPIO") - -mikrosdk_add_library(lib_hal_ll_gpio MikroSDK.HalLowLevel.GPIO - ${gpio_implementation}/hal_ll_gpio.c - ${gpio_implementation}/${gpio_subimplementation}/hal_ll_gpio_port.c - ../../include/hal_ll_target.h - ../../include/hal_ll_slrcon_map.h - ../../include/hal_ll_odcon_map.h - ../../include/gpio/hal_ll_gpio.h - ../../include/gpio/hal_ll_gpio_port.h - ../../include/gpio/hal_ll_gpio_constants.h -) - -target_compile_definitions(lib_hal_ll_gpio PUBLIC - ${hal_ll_def_list} -) - -target_link_libraries(lib_hal_ll_gpio PUBLIC - MikroC.Core - MikroSDK.HalLowLevelCore - MikroSDK.HalLowLevelCommon -) - -string(TOLOWER ${MCU_NAME} MCU_NAME_LOWER) -target_include_directories(lib_hal_ll_gpio - PRIVATE - ../../include - ../../include/gpio - ../../include/adc - INTERFACE - $ - $ - $ - $ - $ -) - -mikrosdk_install(MikroSDK.HalLowLevel.GPIO) -install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.GPIO ../../include/gpio/hal_ll_gpio.h ../../include/gpio/hal_ll_gpio_constants.h ../../include/gpio/hal_ll_gpio_port.h) +## ./targets/pic_8bit/mikroe/pic18/src/gpio/CMakeLists.txt +set(hal_ll_def_list "") +if(${MCU_NAME} MATCHES "PIC18") + list(APPEND hal_ll_def_list "__pic18__") +else() + list(APPEND hal_ll_def_list "__family_not_supported__") +endif() + +list(APPEND hal_ll_def_list ${MCU_NAME}) + +string(LENGTH ${MCU_NAME} MEMAKE_MCU_NAME_LENGTH) +MATH(EXPR BEGIN_INDEX "${MEMAKE_MCU_NAME_LENGTH}-3") +string(SUBSTRING ${MCU_NAME} ${BEGIN_INDEX} 3 MCU_NAME_LAST_3) +MATH(EXPR BEGIN_INDEX_4TH "${MEMAKE_MCU_NAME_LENGTH}-4") +string(SUBSTRING ${MCU_NAME} ${BEGIN_INDEX_4TH} 1 MCU_ON_4) +MATH(EXPR BEGIN_INDEX_4TH "${MEMAKE_MCU_NAME_LENGTH}-5") +string(SUBSTRING ${MCU_NAME} ${BEGIN_INDEX_4TH} 1 MCU_ON_5) +MATH(EXPR BEGIN_INDEX_5TH "${MEMAKE_MCU_NAME_LENGTH}-5") +string(SUBSTRING ${MCU_NAME} ${BEGIN_INDEX_5TH} 5 MCU_NAME_LAST_5) + +## BEGIN GPIO +if ((${MCU_NAME_LAST_3} MATCHES "J50") OR (${MCU_NAME_LAST_3} MATCHES "J55") OR ((${MCU_NAME_LAST_3} MATCHES "J11") AND ((${MCU_ON_5} MATCHES "8") AND ((${MCU_ON_4} MATCHES "6") OR (${MCU_ON_4} MATCHES "7")))) OR (${MCU_NAME_LAST_5} MATCHES "66J16") OR (${MCU_NAME_LAST_5} MATCHES "86J16")) + list(APPEND hal_ll_def_list "__hal_ll_gpio_subset_1__") + set(gpio_implementation "implementation_1") + set(gpio_subimplementation "subimplementation_2") +elseif (${MCU_NAME} MATCHES "PIC18") + list(APPEND hal_ll_def_list "__hal_ll_gpio_subset_1__") + set(gpio_implementation "implementation_1") + set(gpio_subimplementation "subimplementation_1") +else() + list(APPEND hal_ll_def_list "__hal_ll_gpio_not_supported__") +endif() + +## Specific PIC chips have shared SFR addresses +## Page number 82 -- http://ww1.microchip.com/downloads/en/devicedoc/39775b.pdf +if (${MCU_NAME} MATCHES "(^PIC18F[68][5-7]J5[05]$)") + list(APPEND hal_ll_def_list "__hal_ll_shared_sfrs__") +endif() +## END GPIO + +list(APPEND hal_ll_def_list "MACRO_USAGE_GPIO") + +mikrosdk_add_library(lib_hal_ll_gpio MikroSDK.HalLowLevel.GPIO + ${gpio_implementation}/hal_ll_gpio.c + ${gpio_implementation}/${gpio_subimplementation}/hal_ll_gpio_port.c + ../../include/hal_ll_target.h + ../../include/hal_ll_slrcon_map.h + ../../include/hal_ll_odcon_map.h + ../../include/gpio/hal_ll_gpio.h + ../../include/gpio/hal_ll_gpio_port.h + ../../include/gpio/hal_ll_gpio_constants.h +) + +target_compile_definitions(lib_hal_ll_gpio PUBLIC + ${hal_ll_def_list} +) + +target_link_libraries(lib_hal_ll_gpio PUBLIC + MikroC.Core + MikroSDK.HalLowLevelCore + MikroSDK.HalLowLevelCommon +) + +string(TOLOWER ${MCU_NAME} MCU_NAME_LOWER) +target_include_directories(lib_hal_ll_gpio + PRIVATE + ../../include + ../../include/gpio + ../../include/adc + INTERFACE + $ + $ + $ + $ + $ +) + +mikrosdk_install(MikroSDK.HalLowLevel.GPIO) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.GPIO ../../include/gpio/hal_ll_gpio.h ../../include/gpio/hal_ll_gpio_constants.h ../../include/gpio/hal_ll_gpio_port.h) diff --git a/targets/pic_8bit/mikroe/pic18/src/hal_ll/CMakeLists.txt b/targets/pic_8bit/mikroe/pic18/src/hal_ll/CMakeLists.txt index f6e0cf961..6cf982e61 100644 --- a/targets/pic_8bit/mikroe/pic18/src/hal_ll/CMakeLists.txt +++ b/targets/pic_8bit/mikroe/pic18/src/hal_ll/CMakeLists.txt @@ -1,15 +1,15 @@ -## ./targets/pic_8bit/mikroe/pic18/src/hal_ll/CMakeLists.txt -add_library(lib_hal_ll INTERFACE) - -add_library(MikroSDK.HalLowLevel ALIAS lib_hal_ll) - -set(module_list "") -set(module_list_supported "") -set_module_support(module_list module_list_supported ${MCU_NAME} "hal_ll_layer") - -target_link_libraries(lib_hal_ll INTERFACE - ${module_list} -) - -mikrosdk_install(MikroSDK.HalLowLevel) -install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel ../../include/hal_ll_target.h ../../include/hal_ll_pin_names.h ../../include/hal_ll_target_names.h) +## ./targets/pic_8bit/mikroe/pic18/src/hal_ll/CMakeLists.txt +add_library(lib_hal_ll INTERFACE) + +add_library(MikroSDK.HalLowLevel ALIAS lib_hal_ll) + +set(module_list "") +set(module_list_supported "") +set_module_support(module_list module_list_supported ${MCU_NAME} "hal_ll_layer") + +target_link_libraries(lib_hal_ll INTERFACE + ${module_list} +) + +mikrosdk_install(MikroSDK.HalLowLevel) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel ../../include/hal_ll_target.h ../../include/hal_ll_pin_names.h ../../include/hal_ll_target_names.h) diff --git a/targets/pic_8bit/mikroe/pic18/src/i2c/CMakeLists.txt b/targets/pic_8bit/mikroe/pic18/src/i2c/CMakeLists.txt index d25bdc345..a89ba2e7a 100644 --- a/targets/pic_8bit/mikroe/pic18/src/i2c/CMakeLists.txt +++ b/targets/pic_8bit/mikroe/pic18/src/i2c/CMakeLists.txt @@ -1,78 +1,78 @@ -## ./targets/pic_8bit/mikroe/pic18/src/i2c/CMakeLists.txt -set(hal_ll_def_list "") -if(${MCU_NAME} MATCHES "PIC18") - list(APPEND hal_ll_def_list "__pic18__") -else() - list(APPEND hal_ll_def_list "__family_not_supported__") -endif() - -list(APPEND hal_ll_def_list ${MCU_NAME}) - -string(LENGTH ${MCU_NAME} MEMAKE_MCU_NAME_LENGTH) -MATH(EXPR BEGIN_INDEX "${MEMAKE_MCU_NAME_LENGTH}-3") -string(SUBSTRING ${MCU_NAME} ${BEGIN_INDEX} 3 MCU_NAME_LAST_3) - -## BEGIN I2C -if ((${MCU_NAME_LAST_3} MATCHES "K42") OR (${MCU_NAME_LAST_3} MATCHES "Q43")) - set(i2c_implementation "implementation_2") -else() - set(i2c_implementation "implementation_1") -endif() - -if(${MCU_NAME} MATCHES "^PIC18F47Q10$") - list(APPEND hal_ll_def_list "_I2C_BRG_FORMULA_ALTERNATE_") -endif() - -## Specific PIC chips have shared SFR addresses -## Page number 82 -- http://ww1.microchip.com/downloads/en/devicedoc/39775b.pdf -if (${MCU_NAME} MATCHES "(^PIC18F[68][5-7]J5[05]$)") - list(APPEND hal_ll_def_list "__hal_ll_shared_sfrs__") -endif() -## END I2C - -list(APPEND hal_ll_def_list "MACRO_USAGE_I2C") - -if (NOT DEFINED _MSDK_TFT_TP_) - list(APPEND hal_ll_def_list "__TFT_NON_TSC2003__") -else() - if (${_MSDK_TFT_TP_} MATCHES "__TP_TSC2003__") - list(APPEND hal_ll_def_list "__TFT_RESISTIVE_TSC2003__") - else() - list(APPEND hal_ll_def_list "__TFT_NON_TSC2003__") - endif() -endif() - -mikrosdk_add_library(lib_hal_ll_i2c_master MikroSDK.HalLowLevel.I2C.Master - ${i2c_implementation}/hal_ll_i2c_master.c - - ../../include/hal_ll_target.h - ../../include/hal_ll_slrcon_map.h - ../../include/hal_ll_odcon_map.h - ../../include/i2c/hal_ll_i2c_master.h - ../../include/i2c/hal_ll_i2c_pin_map.h -) - -target_compile_definitions(lib_hal_ll_i2c_master PUBLIC - ${hal_ll_def_list} -) - -target_link_libraries(lib_hal_ll_i2c_master PUBLIC - MikroC.Core - MikroSDK.HalLowLevel.PPS - MikroSDK.HalLowLevelCore - MikroSDK.HalLowLevelCommon -) -string(TOLOWER ${MCU_NAME} MCU_NAME_LOWER) -target_include_directories(lib_hal_ll_i2c_master - PRIVATE - ../../include - ../../include/i2c - INTERFACE - $ - $ - $ - $ -) - -mikrosdk_install(MikroSDK.HalLowLevel.I2C.Master) -install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.I2C.Master ../../include/i2c/hal_ll_i2c_master.h ../../include/i2c/hal_ll_i2c_pin_map.h) +## ./targets/pic_8bit/mikroe/pic18/src/i2c/CMakeLists.txt +set(hal_ll_def_list "") +if(${MCU_NAME} MATCHES "PIC18") + list(APPEND hal_ll_def_list "__pic18__") +else() + list(APPEND hal_ll_def_list "__family_not_supported__") +endif() + +list(APPEND hal_ll_def_list ${MCU_NAME}) + +string(LENGTH ${MCU_NAME} MEMAKE_MCU_NAME_LENGTH) +MATH(EXPR BEGIN_INDEX "${MEMAKE_MCU_NAME_LENGTH}-3") +string(SUBSTRING ${MCU_NAME} ${BEGIN_INDEX} 3 MCU_NAME_LAST_3) + +## BEGIN I2C +if ((${MCU_NAME_LAST_3} MATCHES "K42") OR (${MCU_NAME_LAST_3} MATCHES "Q43")) + set(i2c_implementation "implementation_2") +else() + set(i2c_implementation "implementation_1") +endif() + +if(${MCU_NAME} MATCHES "^PIC18F47Q10$") + list(APPEND hal_ll_def_list "_I2C_BRG_FORMULA_ALTERNATE_") +endif() + +## Specific PIC chips have shared SFR addresses +## Page number 82 -- http://ww1.microchip.com/downloads/en/devicedoc/39775b.pdf +if (${MCU_NAME} MATCHES "(^PIC18F[68][5-7]J5[05]$)") + list(APPEND hal_ll_def_list "__hal_ll_shared_sfrs__") +endif() +## END I2C + +list(APPEND hal_ll_def_list "MACRO_USAGE_I2C") + +if (NOT DEFINED _MSDK_TFT_TP_) + list(APPEND hal_ll_def_list "__TFT_NON_TSC2003__") +else() + if (${_MSDK_TFT_TP_} MATCHES "__TP_TSC2003__") + list(APPEND hal_ll_def_list "__TFT_RESISTIVE_TSC2003__") + else() + list(APPEND hal_ll_def_list "__TFT_NON_TSC2003__") + endif() +endif() + +mikrosdk_add_library(lib_hal_ll_i2c_master MikroSDK.HalLowLevel.I2C.Master + ${i2c_implementation}/hal_ll_i2c_master.c + + ../../include/hal_ll_target.h + ../../include/hal_ll_slrcon_map.h + ../../include/hal_ll_odcon_map.h + ../../include/i2c/hal_ll_i2c_master.h + ../../include/i2c/hal_ll_i2c_pin_map.h +) + +target_compile_definitions(lib_hal_ll_i2c_master PUBLIC + ${hal_ll_def_list} +) + +target_link_libraries(lib_hal_ll_i2c_master PUBLIC + MikroC.Core + MikroSDK.HalLowLevel.PPS + MikroSDK.HalLowLevelCore + MikroSDK.HalLowLevelCommon +) +string(TOLOWER ${MCU_NAME} MCU_NAME_LOWER) +target_include_directories(lib_hal_ll_i2c_master + PRIVATE + ../../include + ../../include/i2c + INTERFACE + $ + $ + $ + $ +) + +mikrosdk_install(MikroSDK.HalLowLevel.I2C.Master) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.I2C.Master ../../include/i2c/hal_ll_i2c_master.h ../../include/i2c/hal_ll_i2c_pin_map.h) diff --git a/targets/pic_8bit/mikroe/pic18/src/one_wire/CMakeLists.txt b/targets/pic_8bit/mikroe/pic18/src/one_wire/CMakeLists.txt index f467a377e..35170a17c 100644 --- a/targets/pic_8bit/mikroe/pic18/src/one_wire/CMakeLists.txt +++ b/targets/pic_8bit/mikroe/pic18/src/one_wire/CMakeLists.txt @@ -1,32 +1,32 @@ -## ./targets/pic_8bit/mikroe/pic18/src/one_wire/CMakeLists.txt -set(hal_ll_def_list) -list(APPEND hal_ll_def_list "MACRO_USAGE_ONE_WIRE") - -mikrosdk_add_library(lib_hal_ll_one_wire MikroSDK.HalLowLevel.OneWire - hal_ll_one_wire.c - - ../../include/one_wire/hal_ll_one_wire.h -) - -target_compile_definitions(lib_hal_ll_one_wire PUBLIC - ${hal_ll_def_list} -) - -target_link_libraries(lib_hal_ll_one_wire PUBLIC - MikroC.Core - MikroSDK.HalLowLevel.GPIO - MikroSDK.HalLowLevelCommon -) - -target_include_directories(lib_hal_ll_one_wire - PRIVATE - ../../include/one_wire - INTERFACE - $ - $ - $ - $ -) - -mikrosdk_install(MikroSDK.HalLowLevel.OneWire) -install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.OneWire ../../include/one_wire/hal_ll_one_wire.h) +## ./targets/pic_8bit/mikroe/pic18/src/one_wire/CMakeLists.txt +set(hal_ll_def_list) +list(APPEND hal_ll_def_list "MACRO_USAGE_ONE_WIRE") + +mikrosdk_add_library(lib_hal_ll_one_wire MikroSDK.HalLowLevel.OneWire + hal_ll_one_wire.c + + ../../include/one_wire/hal_ll_one_wire.h +) + +target_compile_definitions(lib_hal_ll_one_wire PUBLIC + ${hal_ll_def_list} +) + +target_link_libraries(lib_hal_ll_one_wire PUBLIC + MikroC.Core + MikroSDK.HalLowLevel.GPIO + MikroSDK.HalLowLevelCommon +) + +target_include_directories(lib_hal_ll_one_wire + PRIVATE + ../../include/one_wire + INTERFACE + $ + $ + $ + $ +) + +mikrosdk_install(MikroSDK.HalLowLevel.OneWire) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.OneWire ../../include/one_wire/hal_ll_one_wire.h) diff --git a/targets/pic_8bit/mikroe/pic18/src/pps/CMakeLists.txt b/targets/pic_8bit/mikroe/pic18/src/pps/CMakeLists.txt index 9e4b0ed46..6cb9488fc 100644 --- a/targets/pic_8bit/mikroe/pic18/src/pps/CMakeLists.txt +++ b/targets/pic_8bit/mikroe/pic18/src/pps/CMakeLists.txt @@ -1,83 +1,83 @@ -## ./targets/pic_8bit/mikroe/pic18/src/pps/CMakeLists.txt -set(hal_ll_def_list "") -if (${MCU_NAME} MATCHES "PIC18") - list(APPEND hal_ll_def_list "__pic18__") -else() - list(APPEND hal_ll_def_list "__family_not_supported__") -endif() - -list(APPEND hal_ll_def_list ${MCU_NAME}) - -string(LENGTH ${MCU_NAME} MEMAKE_MCU_NAME_LENGTH) -MATH(EXPR BEGIN_INDEX "${MEMAKE_MCU_NAME_LENGTH}-3") -string(SUBSTRING ${MCU_NAME} ${BEGIN_INDEX} 3 MCU_NAME_LAST_3) - -if (${MCU_NAME} MATCHES "(^PIC18.+[24].+J1[13]$)|(^PIC18.+[24].+J5[03]$)|(^PIC18.+J94$)|(^PIC18.+K4[02]$)|(^PIC18.+Q43$)|(^PIC18.+Q10$)") - if (${MCU_NAME_LAST_3} MATCHES "J94") - list(APPEND hal_ll_def_list "__hal_ll_pps_lock_unlock_case_1__") - elseif ((${MCU_NAME_LAST_3} MATCHES "K40") OR (${MCU_NAME_LAST_3} MATCHES "K42") OR (${MCU_NAME_LAST_3} MATCHES "Q43") OR (${MCU_NAME_LAST_3} MATCHES "Q10")) - list(APPEND hal_ll_def_list "__hal_ll_pps_lock_unlock_case_2__") - else() - list(APPEND hal_ll_def_list "__hal_ll_pps_lock_unlock_case_3__") - endif() - set(pps_connections_path ${MCU_NAME}) -else() - list(APPEND hal_ll_def_list "__hal_ll_pps_lock_unlock_case_4__") - set(pps_connections_path "HAL_LL_PPS_DEFAULT") -endif() - -if (${MCU_NAME} MATCHES "(^PIC18(.+)K4[0]$)|(^PIC18(.+)Q10$)") - if (${MCU_NAME_LAST_3} MATCHES "Q10") - list(APPEND hal_ll_def_list "__hal_ll_pps_i2c_in_out__") - list(APPEND hal_ll_def_list "__hal_ll_pps_spi_in_out__") - elseif (${MCU_NAME_LAST_3} MATCHES "K40") - list(APPEND hal_ll_def_list "__hal_ll_pps_i2c_in_out__") - endif() -endif() - -set(pps_implementation "implementation_1") -list(APPEND hal_ll_def_list "MACRO_USAGE_PPS") - -mikrosdk_add_library(lib_hal_ll_pps MikroSDK.HalLowLevel.PPS - hal_ll_pps.c - ${pps_implementation}/hal_ll_pps_port.c - - ../../include/hal_ll_target.h - ../../include/hal_ll_slrcon_map.h - ../../include/hal_ll_odcon_map.h - ../../include/pps/hal_ll_pps.h - ../../include/pps/hal_ll_pps_port.h - ../../include/pps/hal_ll_pps_defines.h - ../../include/pps/hal_ll_pps_connection_defs/${pps_connections_path}/hal_ll_pps_connection_defs.h -) - -target_compile_definitions(lib_hal_ll_pps PUBLIC - ${hal_ll_def_list} -) - -target_link_libraries(lib_hal_ll_pps PUBLIC - MikroC.Core - MikroSDK.HalLowLevelCore - MikroSDK.HalLowLevelCommon -) -string(TOLOWER ${MCU_NAME} MCU_NAME_LOWER) -target_include_directories(lib_hal_ll_pps - PRIVATE - ../../include - ../../include/gpio - ../../include/pps - ../../include/pps/hal_ll_pps_connection_defs - ../../include/pps/hal_ll_pps_connection_defs/${pps_connections_path} - INTERFACE - $ - $ - $ - $ - $ - - $ - $ -) - -mikrosdk_install(MikroSDK.HalLowLevel.PPS) -install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.PPS ../../include/pps/hal_ll_pps.h ../../include/pps/hal_ll_pps_port.h ../../include/pps/hal_ll_pps_defines.h) +## ./targets/pic_8bit/mikroe/pic18/src/pps/CMakeLists.txt +set(hal_ll_def_list "") +if (${MCU_NAME} MATCHES "PIC18") + list(APPEND hal_ll_def_list "__pic18__") +else() + list(APPEND hal_ll_def_list "__family_not_supported__") +endif() + +list(APPEND hal_ll_def_list ${MCU_NAME}) + +string(LENGTH ${MCU_NAME} MEMAKE_MCU_NAME_LENGTH) +MATH(EXPR BEGIN_INDEX "${MEMAKE_MCU_NAME_LENGTH}-3") +string(SUBSTRING ${MCU_NAME} ${BEGIN_INDEX} 3 MCU_NAME_LAST_3) + +if (${MCU_NAME} MATCHES "(^PIC18.+[24].+J1[13]$)|(^PIC18.+[24].+J5[03]$)|(^PIC18.+J94$)|(^PIC18.+K4[02]$)|(^PIC18.+Q43$)|(^PIC18.+Q10$)") + if (${MCU_NAME_LAST_3} MATCHES "J94") + list(APPEND hal_ll_def_list "__hal_ll_pps_lock_unlock_case_1__") + elseif ((${MCU_NAME_LAST_3} MATCHES "K40") OR (${MCU_NAME_LAST_3} MATCHES "K42") OR (${MCU_NAME_LAST_3} MATCHES "Q43") OR (${MCU_NAME_LAST_3} MATCHES "Q10")) + list(APPEND hal_ll_def_list "__hal_ll_pps_lock_unlock_case_2__") + else() + list(APPEND hal_ll_def_list "__hal_ll_pps_lock_unlock_case_3__") + endif() + set(pps_connections_path ${MCU_NAME}) +else() + list(APPEND hal_ll_def_list "__hal_ll_pps_lock_unlock_case_4__") + set(pps_connections_path "HAL_LL_PPS_DEFAULT") +endif() + +if (${MCU_NAME} MATCHES "(^PIC18(.+)K4[0]$)|(^PIC18(.+)Q10$)") + if (${MCU_NAME_LAST_3} MATCHES "Q10") + list(APPEND hal_ll_def_list "__hal_ll_pps_i2c_in_out__") + list(APPEND hal_ll_def_list "__hal_ll_pps_spi_in_out__") + elseif (${MCU_NAME_LAST_3} MATCHES "K40") + list(APPEND hal_ll_def_list "__hal_ll_pps_i2c_in_out__") + endif() +endif() + +set(pps_implementation "implementation_1") +list(APPEND hal_ll_def_list "MACRO_USAGE_PPS") + +mikrosdk_add_library(lib_hal_ll_pps MikroSDK.HalLowLevel.PPS + hal_ll_pps.c + ${pps_implementation}/hal_ll_pps_port.c + + ../../include/hal_ll_target.h + ../../include/hal_ll_slrcon_map.h + ../../include/hal_ll_odcon_map.h + ../../include/pps/hal_ll_pps.h + ../../include/pps/hal_ll_pps_port.h + ../../include/pps/hal_ll_pps_defines.h + ../../include/pps/hal_ll_pps_connection_defs/${pps_connections_path}/hal_ll_pps_connection_defs.h +) + +target_compile_definitions(lib_hal_ll_pps PUBLIC + ${hal_ll_def_list} +) + +target_link_libraries(lib_hal_ll_pps PUBLIC + MikroC.Core + MikroSDK.HalLowLevelCore + MikroSDK.HalLowLevelCommon +) +string(TOLOWER ${MCU_NAME} MCU_NAME_LOWER) +target_include_directories(lib_hal_ll_pps + PRIVATE + ../../include + ../../include/gpio + ../../include/pps + ../../include/pps/hal_ll_pps_connection_defs + ../../include/pps/hal_ll_pps_connection_defs/${pps_connections_path} + INTERFACE + $ + $ + $ + $ + $ + + $ + $ +) + +mikrosdk_install(MikroSDK.HalLowLevel.PPS) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.PPS ../../include/pps/hal_ll_pps.h ../../include/pps/hal_ll_pps_port.h ../../include/pps/hal_ll_pps_defines.h) diff --git a/targets/pic_8bit/mikroe/pic18/src/tim/CMakeLists.txt b/targets/pic_8bit/mikroe/pic18/src/tim/CMakeLists.txt index 357b36b4b..9d50f5f31 100644 --- a/targets/pic_8bit/mikroe/pic18/src/tim/CMakeLists.txt +++ b/targets/pic_8bit/mikroe/pic18/src/tim/CMakeLists.txt @@ -1,58 +1,58 @@ -## ./targets/pic_8bit/mikroe/pic18/src/tim/CMakeLists.txt -set(hal_ll_def_list "") -if(${MCU_NAME} MATCHES "PIC18") - list(APPEND hal_ll_def_list "__pic18__") -else() - list(APPEND hal_ll_def_list "__family_not_supported__") -endif() - -list(APPEND hal_ll_def_list ${MCU_NAME}) - -string(LENGTH ${MCU_NAME} MEMAKE_MCU_NAME_LENGTH) -MATH(EXPR BEGIN_INDEX "${MEMAKE_MCU_NAME_LENGTH}-3") -string(SUBSTRING ${MCU_NAME} ${BEGIN_INDEX} 3 MCU_NAME_LAST_3) - -## BEGIN TIM -if ((${MCU_NAME_LAST_3} MATCHES "K42") OR (${MCU_NAME_LAST_3} MATCHES "K40") OR (${MCU_NAME_LAST_3} MATCHES "Q43") OR (${MCU_NAME_LAST_3} MATCHES "Q10")) - set(tim_implementation "implementation_2") -else() - set(tim_implementation "implementation_1") -endif() -## END TIM - -list(APPEND hal_ll_def_list "MACRO_USAGE_TIM") - -mikrosdk_add_library(lib_hal_ll_tim MikroSDK.HalLowLevel.TIM - ${tim_implementation}/hal_ll_tim.c - - ../../include/hal_ll_target.h - ../../include/hal_ll_slrcon_map.h - ../../include/hal_ll_odcon_map.h - ../../include/tim/hal_ll_tim.h -) - -target_compile_definitions(lib_hal_ll_tim PUBLIC - ${hal_ll_def_list} -) - -target_link_libraries(lib_hal_ll_tim PUBLIC - MikroC.Core - MikroSDK.HalLowLevel.PPS - MikroSDK.HalLowLevelCore - MikroSDK.HalLowLevelCommon -) - -string(TOLOWER ${MCU_NAME} MCU_NAME_LOWER) -target_include_directories(lib_hal_ll_tim - PRIVATE - ../../include - ../../include/tim - INTERFACE - $ - $ - $ - $ -) - -mikrosdk_install(MikroSDK.HalLowLevel.TIM) -install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.TIM ../../include/tim/hal_ll_tim.h ../../include/tim/hal_ll_tim_pin_map.h) +## ./targets/pic_8bit/mikroe/pic18/src/tim/CMakeLists.txt +set(hal_ll_def_list "") +if(${MCU_NAME} MATCHES "PIC18") + list(APPEND hal_ll_def_list "__pic18__") +else() + list(APPEND hal_ll_def_list "__family_not_supported__") +endif() + +list(APPEND hal_ll_def_list ${MCU_NAME}) + +string(LENGTH ${MCU_NAME} MEMAKE_MCU_NAME_LENGTH) +MATH(EXPR BEGIN_INDEX "${MEMAKE_MCU_NAME_LENGTH}-3") +string(SUBSTRING ${MCU_NAME} ${BEGIN_INDEX} 3 MCU_NAME_LAST_3) + +## BEGIN TIM +if ((${MCU_NAME_LAST_3} MATCHES "K42") OR (${MCU_NAME_LAST_3} MATCHES "K40") OR (${MCU_NAME_LAST_3} MATCHES "Q43") OR (${MCU_NAME_LAST_3} MATCHES "Q10")) + set(tim_implementation "implementation_2") +else() + set(tim_implementation "implementation_1") +endif() +## END TIM + +list(APPEND hal_ll_def_list "MACRO_USAGE_TIM") + +mikrosdk_add_library(lib_hal_ll_tim MikroSDK.HalLowLevel.TIM + ${tim_implementation}/hal_ll_tim.c + + ../../include/hal_ll_target.h + ../../include/hal_ll_slrcon_map.h + ../../include/hal_ll_odcon_map.h + ../../include/tim/hal_ll_tim.h +) + +target_compile_definitions(lib_hal_ll_tim PUBLIC + ${hal_ll_def_list} +) + +target_link_libraries(lib_hal_ll_tim PUBLIC + MikroC.Core + MikroSDK.HalLowLevel.PPS + MikroSDK.HalLowLevelCore + MikroSDK.HalLowLevelCommon +) + +string(TOLOWER ${MCU_NAME} MCU_NAME_LOWER) +target_include_directories(lib_hal_ll_tim + PRIVATE + ../../include + ../../include/tim + INTERFACE + $ + $ + $ + $ +) + +mikrosdk_install(MikroSDK.HalLowLevel.TIM) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.TIM ../../include/tim/hal_ll_tim.h ../../include/tim/hal_ll_tim_pin_map.h) diff --git a/targets/pic_8bit/mikroe/pic18/src/uart/CMakeLists.txt b/targets/pic_8bit/mikroe/pic18/src/uart/CMakeLists.txt index eb1c94680..05d1be833 100644 --- a/targets/pic_8bit/mikroe/pic18/src/uart/CMakeLists.txt +++ b/targets/pic_8bit/mikroe/pic18/src/uart/CMakeLists.txt @@ -1,69 +1,69 @@ -## ./targets/pic_8bit/mikroe/pic18/src/uart/CMakeLists.txt -set(hal_ll_def_list "") -if(${MCU_NAME} MATCHES "PIC18") - list(APPEND hal_ll_def_list "__pic18__") -else() - list(APPEND hal_ll_def_list "__family_not_supported__") -endif() - -list(APPEND hal_ll_def_list ${MCU_NAME}) - -string(LENGTH ${MCU_NAME} MEMAKE_MCU_NAME_LENGTH) -MATH(EXPR BEGIN_INDEX "${MEMAKE_MCU_NAME_LENGTH}-3") -string(SUBSTRING ${MCU_NAME} ${BEGIN_INDEX} 3 MCU_NAME_LAST_3) - -## BEGIN UART -if ((${MCU_NAME_LAST_3} MATCHES "K42") OR (${MCU_NAME_LAST_3} MATCHES "Q43")) - set(uart_implementation "implementation_2") -else() - set(uart_implementation "implementation_1") -endif() - -if (${MCU_NAME} MATCHES "(^PIC18F(([68]5J11$)|([68]5J90$)|([68]6J[79][023]$)|([68]7J[9][03]$)|(87J72$)))") - list(APPEND hal_ll_def_list "__hal_ll_uart_baud_specific__") -endif() -if (${MCU_NAME} MATCHES "(^PIC18(.+)[68][567]20$)") - list(APPEND hal_ll_def_list "__hal_ll_uart_no_16bit_timer__") -endif() -## END UART - -mikrosdk_add_library(lib_hal_ll_uart MikroSDK.HalLowLevel.UART - ${uart_implementation}/hal_ll_uart.c - - ../../include/hal_ll_target.h - ../../include/hal_ll_slrcon_map.h - ../../include/hal_ll_odcon_map.h - ../../include/uart/hal_ll_uart.h - ../../include/uart/hal_ll_uart_pin_map.h -) - -target_compile_definitions(lib_hal_ll_uart PUBLIC - ${hal_ll_def_list} -) - -target_link_libraries(lib_hal_ll_uart PUBLIC - MikroC.Core - MikroSDK.HalLowLevel.PPS - MikroSDK.HalLowLevelCore - MikroSDK.HalLowLevelCommon -) -string(TOLOWER ${MCU_NAME} MCU_NAME_LOWER) -target_include_directories(lib_hal_ll_uart - PRIVATE - ../../include - ../../include/gpio -# BEGIN UART - ../../include/uart - ../../include/uart/${uart_pin_map} -# END UART - - INTERFACE - $ - $ - $ - $ -) -list(APPEND hal_ll_def_list "MACRO_USAGE_UART") - -mikrosdk_install(MikroSDK.HalLowLevel.UART) -install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.UART ../../include/uart/hal_ll_uart.h ../../include/uart/hal_ll_uart_pin_map.h) +## ./targets/pic_8bit/mikroe/pic18/src/uart/CMakeLists.txt +set(hal_ll_def_list "") +if(${MCU_NAME} MATCHES "PIC18") + list(APPEND hal_ll_def_list "__pic18__") +else() + list(APPEND hal_ll_def_list "__family_not_supported__") +endif() + +list(APPEND hal_ll_def_list ${MCU_NAME}) + +string(LENGTH ${MCU_NAME} MEMAKE_MCU_NAME_LENGTH) +MATH(EXPR BEGIN_INDEX "${MEMAKE_MCU_NAME_LENGTH}-3") +string(SUBSTRING ${MCU_NAME} ${BEGIN_INDEX} 3 MCU_NAME_LAST_3) + +## BEGIN UART +if ((${MCU_NAME_LAST_3} MATCHES "K42") OR (${MCU_NAME_LAST_3} MATCHES "Q43")) + set(uart_implementation "implementation_2") +else() + set(uart_implementation "implementation_1") +endif() + +if (${MCU_NAME} MATCHES "(^PIC18F(([68]5J11$)|([68]5J90$)|([68]6J[79][023]$)|([68]7J[9][03]$)|(87J72$)))") + list(APPEND hal_ll_def_list "__hal_ll_uart_baud_specific__") +endif() +if (${MCU_NAME} MATCHES "(^PIC18(.+)[68][567]20$)") + list(APPEND hal_ll_def_list "__hal_ll_uart_no_16bit_timer__") +endif() +## END UART + +mikrosdk_add_library(lib_hal_ll_uart MikroSDK.HalLowLevel.UART + ${uart_implementation}/hal_ll_uart.c + + ../../include/hal_ll_target.h + ../../include/hal_ll_slrcon_map.h + ../../include/hal_ll_odcon_map.h + ../../include/uart/hal_ll_uart.h + ../../include/uart/hal_ll_uart_pin_map.h +) + +target_compile_definitions(lib_hal_ll_uart PUBLIC + ${hal_ll_def_list} +) + +target_link_libraries(lib_hal_ll_uart PUBLIC + MikroC.Core + MikroSDK.HalLowLevel.PPS + MikroSDK.HalLowLevelCore + MikroSDK.HalLowLevelCommon +) +string(TOLOWER ${MCU_NAME} MCU_NAME_LOWER) +target_include_directories(lib_hal_ll_uart + PRIVATE + ../../include + ../../include/gpio +# BEGIN UART + ../../include/uart + ../../include/uart/${uart_pin_map} +# END UART + + INTERFACE + $ + $ + $ + $ +) +list(APPEND hal_ll_def_list "MACRO_USAGE_UART") + +mikrosdk_install(MikroSDK.HalLowLevel.UART) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.UART ../../include/uart/hal_ll_uart.h ../../include/uart/hal_ll_uart_pin_map.h) diff --git a/targets/riscv/mikroe/CMakeLists.txt b/targets/riscv/mikroe/CMakeLists.txt index 1d8209bf5..b47919c10 100644 --- a/targets/riscv/mikroe/CMakeLists.txt +++ b/targets/riscv/mikroe/CMakeLists.txt @@ -1,10 +1,10 @@ -## ./targets/riscv/mikroe/CMakeLists.txt -if(${MCU_NAME} MATCHES "(^GD32VF(.+)$)") - set(vendor_id "gigadevice") -else() - set(vendor_id "__implementation_error__") -endif() - -add_subdirectory(${vendor_id}) -add_subdirectory(common) -add_subdirectory(core) +## ./targets/riscv/mikroe/CMakeLists.txt +if(${MCU_NAME} MATCHES "(^GD32VF(.+)$)") + set(vendor_id "gigadevice") +else() + set(vendor_id "__implementation_error__") +endif() + +add_subdirectory(${vendor_id}) +add_subdirectory(common) +add_subdirectory(core) diff --git a/targets/riscv/mikroe/core/CMakeLists.txt b/targets/riscv/mikroe/core/CMakeLists.txt index ae1111415..ee6462375 100644 --- a/targets/riscv/mikroe/core/CMakeLists.txt +++ b/targets/riscv/mikroe/core/CMakeLists.txt @@ -1,41 +1,41 @@ -## ./targets/riscv/mikroe/core/CMakeLists.txt -set(hal_ll_core_def_list "") -if(${MCU_NAME} MATCHES "^GD32VF.*") - set(chip_vendor "gigadevice") - list(APPEND hal_ll_core_def_list ${chip_vendor}) - string(SUBSTRING ${MCU_NAME} 0 9 STRIPED_MCU_NAME) - list(APPEND hal_ll_core_def_list ${STRIPED_MCU_NAME}) - set(hal_ll_core_source "bumblebee") - list(APPEND hal_ll_core_def_list __core_bumblebee__) -else() - list(hal_ll_core_def_list __vendor_not_supported__) -endif() - -mikrosdk_add_library(lib_hal_ll_core MikroSDK.HalLowLevelCore - src/hal_ll_core.c - src/${chip_vendor}/${hal_ll_core_source}/hal_ll_core_port.c - - include/hal_ll_core_defines.h - include/hal_ll_core_port.h - include/hal_ll_core.h -) - -target_compile_definitions(lib_hal_ll_core - PUBLIC - ${hal_ll_core_def_list} -) - -target_link_libraries(lib_hal_ll_core PUBLIC - MikroC.Core - MikroSDK.HalLowLevelCommon -) - -target_include_directories(lib_hal_ll_core - PRIVATE - include - INTERFACE - $ - $ -) - -mikrosdk_install(MikroSDK.HalLowLevelCore) +## ./targets/riscv/mikroe/core/CMakeLists.txt +set(hal_ll_core_def_list "") +if(${MCU_NAME} MATCHES "^GD32VF.*") + set(chip_vendor "gigadevice") + list(APPEND hal_ll_core_def_list ${chip_vendor}) + string(SUBSTRING ${MCU_NAME} 0 9 STRIPED_MCU_NAME) + list(APPEND hal_ll_core_def_list ${STRIPED_MCU_NAME}) + set(hal_ll_core_source "bumblebee") + list(APPEND hal_ll_core_def_list __core_bumblebee__) +else() + list(hal_ll_core_def_list __vendor_not_supported__) +endif() + +mikrosdk_add_library(lib_hal_ll_core MikroSDK.HalLowLevelCore + src/hal_ll_core.c + src/${chip_vendor}/${hal_ll_core_source}/hal_ll_core_port.c + + include/hal_ll_core_defines.h + include/hal_ll_core_port.h + include/hal_ll_core.h +) + +target_compile_definitions(lib_hal_ll_core + PUBLIC + ${hal_ll_core_def_list} +) + +target_link_libraries(lib_hal_ll_core PUBLIC + MikroC.Core + MikroSDK.HalLowLevelCommon +) + +target_include_directories(lib_hal_ll_core + PRIVATE + include + INTERFACE + $ + $ +) + +mikrosdk_install(MikroSDK.HalLowLevelCore) diff --git a/targets/riscv/mikroe/gigadevice/src/adc/CMakeLists.txt b/targets/riscv/mikroe/gigadevice/src/adc/CMakeLists.txt index c22991c22..08bfc164b 100644 --- a/targets/riscv/mikroe/gigadevice/src/adc/CMakeLists.txt +++ b/targets/riscv/mikroe/gigadevice/src/adc/CMakeLists.txt @@ -1,53 +1,53 @@ -## ./targets/riscv/mikroe/gigadevice/src/adc/CMakeLists.txt -set(hal_ll_def_list "") -set(mcu_header_path "") - -list(APPEND hal_ll_def_list ${MCU_NAME}) - -## BEGINADC -list(APPEND hal_ll_def_list "HAL_LL_ADC_RESOLUTION_CMAKE=HAL_LL_ADC_RESOLUTION_12_BIT") - -set(mcu_header_path ${MCU_NAME}) -set(adc_subimplementation "implementation_1/hal_ll_adc.c") -set(adc_pin_map "hal_ll_adc_pin_map/implementation_1") -## END ADC - -mikrosdk_add_library(lib_hal_ll_adc MikroSDK.HalLowLevel.ADC - ${adc_subimplementation} - ../../include/hal_ll_rcu.h - ../../include/hal_ll_target.h - - ../../include/adc/hal_ll_adc.h - ../../include/adc/${adc_pin_map}/hal_ll_adc_pin_map.h -) - -target_compile_definitions(lib_hal_ll_adc PUBLIC - ${hal_ll_def_list} -) - -target_link_libraries(lib_hal_ll_adc PUBLIC - MikroC.Core - MikroSDK.HalLowLevelCore - MikroSDK.HalLowLevelCommon -) - -string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) -target_include_directories(lib_hal_ll_adc - PRIVATE - ../../include - ../../include/gpio - - ../../include/adc - ../../include/adc/${adc_pin_map} - INTERFACE - $ - $ - $ - $ - - $ - $ -) - -mikrosdk_install(MikroSDK.HalLowLevel.ADC) -install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.ADC ../../include/adc/hal_ll_adc.h) +## ./targets/riscv/mikroe/gigadevice/src/adc/CMakeLists.txt +set(hal_ll_def_list "") +set(mcu_header_path "") + +list(APPEND hal_ll_def_list ${MCU_NAME}) + +## BEGINADC +list(APPEND hal_ll_def_list "HAL_LL_ADC_RESOLUTION_CMAKE=HAL_LL_ADC_RESOLUTION_12_BIT") + +set(mcu_header_path ${MCU_NAME}) +set(adc_subimplementation "implementation_1/hal_ll_adc.c") +set(adc_pin_map "hal_ll_adc_pin_map/implementation_1") +## END ADC + +mikrosdk_add_library(lib_hal_ll_adc MikroSDK.HalLowLevel.ADC + ${adc_subimplementation} + ../../include/hal_ll_rcu.h + ../../include/hal_ll_target.h + + ../../include/adc/hal_ll_adc.h + ../../include/adc/${adc_pin_map}/hal_ll_adc_pin_map.h +) + +target_compile_definitions(lib_hal_ll_adc PUBLIC + ${hal_ll_def_list} +) + +target_link_libraries(lib_hal_ll_adc PUBLIC + MikroC.Core + MikroSDK.HalLowLevelCore + MikroSDK.HalLowLevelCommon +) + +string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) +target_include_directories(lib_hal_ll_adc + PRIVATE + ../../include + ../../include/gpio + + ../../include/adc + ../../include/adc/${adc_pin_map} + INTERFACE + $ + $ + $ + $ + + $ + $ +) + +mikrosdk_install(MikroSDK.HalLowLevel.ADC) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.ADC ../../include/adc/hal_ll_adc.h) diff --git a/targets/riscv/mikroe/gigadevice/src/gpio/CMakeLists.txt b/targets/riscv/mikroe/gigadevice/src/gpio/CMakeLists.txt index 3faf2f698..5ab2d58ac 100644 --- a/targets/riscv/mikroe/gigadevice/src/gpio/CMakeLists.txt +++ b/targets/riscv/mikroe/gigadevice/src/gpio/CMakeLists.txt @@ -1,45 +1,45 @@ -## ./targets/riscv/mikroe/gigadevice/src/gpio/CMakeLists.txt -set(hal_ll_def_list "") -set(mcu_header_path "") - -list(APPEND hal_ll_def_list ${MCU_NAME}) - -## BEGIN GPIO -set(mcu_header_path ${MCU_NAME}) -set(gpio_subimplementation "implementation_1/hal_ll_gpio_port.c") -## END GPIO - -mikrosdk_add_library(lib_hal_ll_gpio MikroSDK.HalLowLevel.GPIO - hal_ll_gpio.c - ${gpio_subimplementation} - - ../../include/gpio/hal_ll_gpio.h - ../../include/gpio/hal_ll_gpio_port.h - ../../include/gpio/hal_ll_gpio_constants.h - - ../../include/hal_ll_rcu.h - ../../include/hal_ll_target.h - ../../include/hal_ll_pin_names.h - ../../include/hal_ll_target_names.h -) - -target_link_libraries(lib_hal_ll_gpio PUBLIC - MikroC.Core - MikroSDK.HalLowLevelCore - MikroSDK.HalLowLevelCommon -) - -string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) -target_include_directories(lib_hal_ll_gpio - PRIVATE - ../../include - ../../include/gpio - INTERFACE - $ - $ - $ - $ -) - -mikrosdk_install(MikroSDK.HalLowLevel.GPIO) -install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.GPIO ../../include/gpio/hal_ll_gpio.h ../../include/gpio/hal_ll_gpio_constants.h ../../include/gpio/hal_ll_gpio_port.h) +## ./targets/riscv/mikroe/gigadevice/src/gpio/CMakeLists.txt +set(hal_ll_def_list "") +set(mcu_header_path "") + +list(APPEND hal_ll_def_list ${MCU_NAME}) + +## BEGIN GPIO +set(mcu_header_path ${MCU_NAME}) +set(gpio_subimplementation "implementation_1/hal_ll_gpio_port.c") +## END GPIO + +mikrosdk_add_library(lib_hal_ll_gpio MikroSDK.HalLowLevel.GPIO + hal_ll_gpio.c + ${gpio_subimplementation} + + ../../include/gpio/hal_ll_gpio.h + ../../include/gpio/hal_ll_gpio_port.h + ../../include/gpio/hal_ll_gpio_constants.h + + ../../include/hal_ll_rcu.h + ../../include/hal_ll_target.h + ../../include/hal_ll_pin_names.h + ../../include/hal_ll_target_names.h +) + +target_link_libraries(lib_hal_ll_gpio PUBLIC + MikroC.Core + MikroSDK.HalLowLevelCore + MikroSDK.HalLowLevelCommon +) + +string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) +target_include_directories(lib_hal_ll_gpio + PRIVATE + ../../include + ../../include/gpio + INTERFACE + $ + $ + $ + $ +) + +mikrosdk_install(MikroSDK.HalLowLevel.GPIO) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.GPIO ../../include/gpio/hal_ll_gpio.h ../../include/gpio/hal_ll_gpio_constants.h ../../include/gpio/hal_ll_gpio_port.h) diff --git a/targets/riscv/mikroe/gigadevice/src/hal_ll/CMakeLists.txt b/targets/riscv/mikroe/gigadevice/src/hal_ll/CMakeLists.txt index f0da67c3c..48b7f7280 100644 --- a/targets/riscv/mikroe/gigadevice/src/hal_ll/CMakeLists.txt +++ b/targets/riscv/mikroe/gigadevice/src/hal_ll/CMakeLists.txt @@ -1,15 +1,15 @@ -## ./targets/riscv/mikroe/gigadevice/src/hal_ll/CMakeLists.txt -add_library(lib_hal_ll INTERFACE) - -add_library(MikroSDK.HalLowLevel ALIAS lib_hal_ll) - -set(module_list "") -set(module_list_supported "") -set_module_support(module_list module_list_supported ${MCU_NAME} "hal_ll_layer") - -target_link_libraries(lib_hal_ll INTERFACE - ${module_list} -) - -mikrosdk_install(MikroSDK.HalLowLevel) -install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel ../../include/hal_ll_target.h ../../include/hal_ll_pin_names.h ../../include/hal_ll_target_names.h) +## ./targets/riscv/mikroe/gigadevice/src/hal_ll/CMakeLists.txt +add_library(lib_hal_ll INTERFACE) + +add_library(MikroSDK.HalLowLevel ALIAS lib_hal_ll) + +set(module_list "") +set(module_list_supported "") +set_module_support(module_list module_list_supported ${MCU_NAME} "hal_ll_layer") + +target_link_libraries(lib_hal_ll INTERFACE + ${module_list} +) + +mikrosdk_install(MikroSDK.HalLowLevel) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel ../../include/hal_ll_target.h ../../include/hal_ll_pin_names.h ../../include/hal_ll_target_names.h) diff --git a/targets/riscv/mikroe/gigadevice/src/i2c/CMakeLists.txt b/targets/riscv/mikroe/gigadevice/src/i2c/CMakeLists.txt index 0744b3461..bf8a9daa2 100644 --- a/targets/riscv/mikroe/gigadevice/src/i2c/CMakeLists.txt +++ b/targets/riscv/mikroe/gigadevice/src/i2c/CMakeLists.txt @@ -1,50 +1,50 @@ -## ./targets/riscv/mikroe/gigadevice/src/i2c/CMakeLists.txt -set(hal_ll_def_list "") -set(mcu_header_path "") - -list(APPEND hal_ll_def_list ${MCU_NAME}) - -## BEGIN I2C -set(mcu_header_path ${MCU_NAME}) -set(i2c_subimplementation "implementation_1/hal_ll_i2c_master.c") -set(i2c_pin_map "hal_ll_i2c_pin_map/implementation_1") -# END I2C - -mikrosdk_add_library(lib_hal_ll_i2c_master MikroSDK.HalLowLevel.I2C.Master - ${i2c_subimplementation} - - ../../include/hal_ll_rcu.h - ../../include/hal_ll_target.h - - ../../include/i2c/hal_ll_i2c_master.h - ../../include/i2c/${i2c_pin_map}/hal_ll_i2c_pin_map.h -) - -target_compile_definitions(lib_hal_ll_i2c_master PUBLIC - ${hal_ll_def_list} -) - -target_link_libraries(lib_hal_ll_i2c_master PUBLIC - MikroC.Core - MikroSDK.HalLowLevelCore - MikroSDK.HalLowLevelCommon -) -string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) -target_include_directories(lib_hal_ll_i2c_master - PRIVATE - ../../include - ../../include/gpio - - ../../include/i2c - ../../include/i2c/${i2c_pin_map} - INTERFACE - $ - $ - $ - $ - $ - $ -) - -mikrosdk_install(MikroSDK.HalLowLevel.I2C.Master) -install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.I2C.Master ../../include/i2c/hal_ll_i2c_master.h) +## ./targets/riscv/mikroe/gigadevice/src/i2c/CMakeLists.txt +set(hal_ll_def_list "") +set(mcu_header_path "") + +list(APPEND hal_ll_def_list ${MCU_NAME}) + +## BEGIN I2C +set(mcu_header_path ${MCU_NAME}) +set(i2c_subimplementation "implementation_1/hal_ll_i2c_master.c") +set(i2c_pin_map "hal_ll_i2c_pin_map/implementation_1") +# END I2C + +mikrosdk_add_library(lib_hal_ll_i2c_master MikroSDK.HalLowLevel.I2C.Master + ${i2c_subimplementation} + + ../../include/hal_ll_rcu.h + ../../include/hal_ll_target.h + + ../../include/i2c/hal_ll_i2c_master.h + ../../include/i2c/${i2c_pin_map}/hal_ll_i2c_pin_map.h +) + +target_compile_definitions(lib_hal_ll_i2c_master PUBLIC + ${hal_ll_def_list} +) + +target_link_libraries(lib_hal_ll_i2c_master PUBLIC + MikroC.Core + MikroSDK.HalLowLevelCore + MikroSDK.HalLowLevelCommon +) +string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) +target_include_directories(lib_hal_ll_i2c_master + PRIVATE + ../../include + ../../include/gpio + + ../../include/i2c + ../../include/i2c/${i2c_pin_map} + INTERFACE + $ + $ + $ + $ + $ + $ +) + +mikrosdk_install(MikroSDK.HalLowLevel.I2C.Master) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.I2C.Master ../../include/i2c/hal_ll_i2c_master.h) diff --git a/targets/riscv/mikroe/gigadevice/src/one_wire/CMakeLists.txt b/targets/riscv/mikroe/gigadevice/src/one_wire/CMakeLists.txt index f29e4fc37..3f223ba3c 100644 --- a/targets/riscv/mikroe/gigadevice/src/one_wire/CMakeLists.txt +++ b/targets/riscv/mikroe/gigadevice/src/one_wire/CMakeLists.txt @@ -1,31 +1,31 @@ -## ./targets/riscv/mikroe/gigadevice/src/one_wire/CMakeLists.txt -set(hal_ll_def_list) -list(APPEND hal_ll_def_list "MACRO_USAGE_ONE_WIRE") - -mikrosdk_add_library(lib_hal_ll_one_wire MikroSDK.HalLowLevel.OneWire - hal_ll_one_wire.c - - ../../include/one_wire/hal_ll_one_wire.h -) - -target_compile_definitions(lib_hal_ll_one_wire PUBLIC - ${hal_ll_def_list} -) - -target_link_libraries(lib_hal_ll_one_wire PUBLIC - MikroC.Core - MikroSDK.HalLowLevel.GPIO - MikroSDK.HalLowLevelCommon -) -target_include_directories(lib_hal_ll_one_wire - PRIVATE - ../../include/one_wire - INTERFACE - $ - $ - $ - $ -) - -mikrosdk_install(MikroSDK.HalLowLevel.OneWire) -install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.OneWire ../../include/one_wire/hal_ll_one_wire.h) +## ./targets/riscv/mikroe/gigadevice/src/one_wire/CMakeLists.txt +set(hal_ll_def_list) +list(APPEND hal_ll_def_list "MACRO_USAGE_ONE_WIRE") + +mikrosdk_add_library(lib_hal_ll_one_wire MikroSDK.HalLowLevel.OneWire + hal_ll_one_wire.c + + ../../include/one_wire/hal_ll_one_wire.h +) + +target_compile_definitions(lib_hal_ll_one_wire PUBLIC + ${hal_ll_def_list} +) + +target_link_libraries(lib_hal_ll_one_wire PUBLIC + MikroC.Core + MikroSDK.HalLowLevel.GPIO + MikroSDK.HalLowLevelCommon +) +target_include_directories(lib_hal_ll_one_wire + PRIVATE + ../../include/one_wire + INTERFACE + $ + $ + $ + $ +) + +mikrosdk_install(MikroSDK.HalLowLevel.OneWire) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.OneWire ../../include/one_wire/hal_ll_one_wire.h) diff --git a/targets/riscv/mikroe/gigadevice/src/spi_master/CMakeLists.txt b/targets/riscv/mikroe/gigadevice/src/spi_master/CMakeLists.txt index ad31fe98f..5314f8f5d 100644 --- a/targets/riscv/mikroe/gigadevice/src/spi_master/CMakeLists.txt +++ b/targets/riscv/mikroe/gigadevice/src/spi_master/CMakeLists.txt @@ -1,51 +1,51 @@ -## ./targets/riscv/mikroe/gigadevice/src/spi_master/CMakeLists.txt -set(hal_ll_def_list "") -set(mcu_header_path "") - -list(APPEND hal_ll_def_list ${MCU_NAME}) - -## BEGIN SPI -set(mcu_header_path ${MCU_NAME}) -set(spi_subimplementation "implementation_1/hal_ll_spi_master.c") -set(spi_pin_map "hal_ll_spi_master_pin_map/implementation_1") -## END SPI - -mikrosdk_add_library(lib_hal_ll_spi_master MikroSDK.HalLowLevel.SPI.Master - ${spi_subimplementation} - - ../../include/hal_ll_rcu.h - ../../include/hal_ll_target.h - - ../../include/spi_master/hal_ll_spi_master.h - ../../include/spi_master/${spi_pin_map}/hal_ll_spi_master_pin_map.h -) - -target_compile_definitions(lib_hal_ll_spi_master PUBLIC - ${hal_ll_def_list} -) - -target_link_libraries(lib_hal_ll_spi_master PUBLIC - MikroC.Core - MikroSDK.HalLowLevelCore - MikroSDK.HalLowLevelCommon -) - -string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) -target_include_directories(lib_hal_ll_spi_master - PRIVATE - ../../include - ../../include/gpio - - ../../include/spi_master - ../../include/spi_master/${spi_pin_map} - INTERFACE - $ - $ - $ - $ - $ - $ -) - -mikrosdk_install(MikroSDK.HalLowLevel.SPI.Master) -install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.SPI.Master ../../include/spi_master/hal_ll_spi_master.h) +## ./targets/riscv/mikroe/gigadevice/src/spi_master/CMakeLists.txt +set(hal_ll_def_list "") +set(mcu_header_path "") + +list(APPEND hal_ll_def_list ${MCU_NAME}) + +## BEGIN SPI +set(mcu_header_path ${MCU_NAME}) +set(spi_subimplementation "implementation_1/hal_ll_spi_master.c") +set(spi_pin_map "hal_ll_spi_master_pin_map/implementation_1") +## END SPI + +mikrosdk_add_library(lib_hal_ll_spi_master MikroSDK.HalLowLevel.SPI.Master + ${spi_subimplementation} + + ../../include/hal_ll_rcu.h + ../../include/hal_ll_target.h + + ../../include/spi_master/hal_ll_spi_master.h + ../../include/spi_master/${spi_pin_map}/hal_ll_spi_master_pin_map.h +) + +target_compile_definitions(lib_hal_ll_spi_master PUBLIC + ${hal_ll_def_list} +) + +target_link_libraries(lib_hal_ll_spi_master PUBLIC + MikroC.Core + MikroSDK.HalLowLevelCore + MikroSDK.HalLowLevelCommon +) + +string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) +target_include_directories(lib_hal_ll_spi_master + PRIVATE + ../../include + ../../include/gpio + + ../../include/spi_master + ../../include/spi_master/${spi_pin_map} + INTERFACE + $ + $ + $ + $ + $ + $ +) + +mikrosdk_install(MikroSDK.HalLowLevel.SPI.Master) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.SPI.Master ../../include/spi_master/hal_ll_spi_master.h) diff --git a/targets/riscv/mikroe/gigadevice/src/tim/CMakeLists.txt b/targets/riscv/mikroe/gigadevice/src/tim/CMakeLists.txt index f2bd9811c..dc56ef6d7 100644 --- a/targets/riscv/mikroe/gigadevice/src/tim/CMakeLists.txt +++ b/targets/riscv/mikroe/gigadevice/src/tim/CMakeLists.txt @@ -1,50 +1,50 @@ -## ./targets/riscv/mikroe/gigadevice/src/tim/CMakeLists.txt -set(hal_ll_def_list "") -set(mcu_header_path "") - -list(APPEND hal_ll_def_list ${MCU_NAME}) - -## BEGIN TIM -set(mcu_header_path ${MCU_NAME}) -set(tim_subimplementation "implementation_1/hal_ll_tim.c") -set(tim_pin_map "hal_ll_tim_pin_map/implementation_1") -## END TIM - -mikrosdk_add_library(lib_hal_ll_tim MikroSDK.HalLowLevel.TIM - ${tim_subimplementation} - - ../../include/hal_ll_rcu.h - ../../include/hal_ll_target.h - - ../../include/tim/hal_ll_tim.h - ../../include/tim/${tim_pin_map}/hal_ll_tim_pin_map.h -) - -target_compile_definitions(lib_hal_ll_tim PUBLIC - ${hal_ll_def_list} -) - -target_link_libraries(lib_hal_ll_tim PUBLIC - MikroC.Core - MikroSDK.HalLowLevelCore - MikroSDK.HalLowLevelCommon -) - -string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) -target_include_directories(lib_hal_ll_tim - PRIVATE - ../../include - ../../include/gpio - - ../../include/tim - ../../include/tim/${tim_pin_map} - INTERFACE - $ - $ - $ - $ - $ -) - -mikrosdk_install(MikroSDK.HalLowLevel.TIM) -install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.TIM ../../include/tim/hal_ll_tim.h) +## ./targets/riscv/mikroe/gigadevice/src/tim/CMakeLists.txt +set(hal_ll_def_list "") +set(mcu_header_path "") + +list(APPEND hal_ll_def_list ${MCU_NAME}) + +## BEGIN TIM +set(mcu_header_path ${MCU_NAME}) +set(tim_subimplementation "implementation_1/hal_ll_tim.c") +set(tim_pin_map "hal_ll_tim_pin_map/implementation_1") +## END TIM + +mikrosdk_add_library(lib_hal_ll_tim MikroSDK.HalLowLevel.TIM + ${tim_subimplementation} + + ../../include/hal_ll_rcu.h + ../../include/hal_ll_target.h + + ../../include/tim/hal_ll_tim.h + ../../include/tim/${tim_pin_map}/hal_ll_tim_pin_map.h +) + +target_compile_definitions(lib_hal_ll_tim PUBLIC + ${hal_ll_def_list} +) + +target_link_libraries(lib_hal_ll_tim PUBLIC + MikroC.Core + MikroSDK.HalLowLevelCore + MikroSDK.HalLowLevelCommon +) + +string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) +target_include_directories(lib_hal_ll_tim + PRIVATE + ../../include + ../../include/gpio + + ../../include/tim + ../../include/tim/${tim_pin_map} + INTERFACE + $ + $ + $ + $ + $ +) + +mikrosdk_install(MikroSDK.HalLowLevel.TIM) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.TIM ../../include/tim/hal_ll_tim.h) diff --git a/targets/riscv/mikroe/gigadevice/src/uart/CMakeLists.txt b/targets/riscv/mikroe/gigadevice/src/uart/CMakeLists.txt index 50a07b62a..6a889f8e6 100644 --- a/targets/riscv/mikroe/gigadevice/src/uart/CMakeLists.txt +++ b/targets/riscv/mikroe/gigadevice/src/uart/CMakeLists.txt @@ -1,51 +1,51 @@ -## ./targets/riscv/mikroe/gigadevice/src/uart/CMakeLists.txt -set(hal_ll_def_list "") -set(mcu_header_path "") - -list(APPEND hal_ll_def_list ${MCU_NAME}) - -## BEGIN UART -set(mcu_header_path ${MCU_NAME}) -set(uart_subimplementation "implementation_1/hal_ll_uart.c") -set(uart_pin_map "hal_ll_uart_pin_map/implementation_1") -## END UART - -mikrosdk_add_library(lib_hal_ll_uart MikroSDK.HalLowLevel.UART - ${uart_subimplementation} - - ../../include/hal_ll_rcu.h - ../../include/hal_ll_target.h - - ../../include/uart/hal_ll_uart.h - ../../include/uart/${uart_pin_map}/hal_ll_uart_pin_map.h -) - -target_compile_definitions(lib_hal_ll_uart PUBLIC - ${hal_ll_def_list} -) - -target_link_libraries(lib_hal_ll_uart PUBLIC - MikroC.Core - MikroSDK.HalLowLevelCore - MikroSDK.HalLowLevelCommon -) - -string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) -target_include_directories(lib_hal_ll_uart - PRIVATE - ../../include - ../../include/gpio - - ../../include/uart - ../../include/uart/${uart_pin_map} - INTERFACE - $ - $ - $ - $ - $ - $ -) - -mikrosdk_install(MikroSDK.HalLowLevel.UART) -install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.UART ../../include/uart/hal_ll_uart.h) +## ./targets/riscv/mikroe/gigadevice/src/uart/CMakeLists.txt +set(hal_ll_def_list "") +set(mcu_header_path "") + +list(APPEND hal_ll_def_list ${MCU_NAME}) + +## BEGIN UART +set(mcu_header_path ${MCU_NAME}) +set(uart_subimplementation "implementation_1/hal_ll_uart.c") +set(uart_pin_map "hal_ll_uart_pin_map/implementation_1") +## END UART + +mikrosdk_add_library(lib_hal_ll_uart MikroSDK.HalLowLevel.UART + ${uart_subimplementation} + + ../../include/hal_ll_rcu.h + ../../include/hal_ll_target.h + + ../../include/uart/hal_ll_uart.h + ../../include/uart/${uart_pin_map}/hal_ll_uart_pin_map.h +) + +target_compile_definitions(lib_hal_ll_uart PUBLIC + ${hal_ll_def_list} +) + +target_link_libraries(lib_hal_ll_uart PUBLIC + MikroC.Core + MikroSDK.HalLowLevelCore + MikroSDK.HalLowLevelCommon +) + +string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) +target_include_directories(lib_hal_ll_uart + PRIVATE + ../../include + ../../include/gpio + + ../../include/uart + ../../include/uart/${uart_pin_map} + INTERFACE + $ + $ + $ + $ + $ + $ +) + +mikrosdk_install(MikroSDK.HalLowLevel.UART) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.UART ../../include/uart/hal_ll_uart.h)