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          "data": {
            "info": "Situación en el Mapa de Memoria",
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          },
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            "readonly": true
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        },
        {
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          "data": {
            "info": "**BUS Direcciones**",
            "readonly": true
          },
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            "height": 40
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        },
        {
          "id": "8afa8957-e117-4391-81e5-f2193e97fb6f",
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            "info": "**BUS Datos**  \n(Salida)",
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            "info": "Periférico  \nlisto",
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            "readonly": true
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            "y": 440
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          "data": {
            "info": "Posición de la RAM  ",
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          "data": {
            "info": "## PUERTO DE SALIDA",
            "readonly": true
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              "data": {
                "name": "",
                "value": "0",
                "local": false
              },
              "position": {
                "x": 728,
                "y": 128
              }
            },
            {
              "id": "7dbe7521-0f9f-43ee-ab0c-0439e2c20bc2",
              "type": "basic.code",
              "data": {
                "code": "assign k = VALUE;",
                "params": [
                  {
                    "name": "VALUE"
                  }
                ],
                "ports": {
                  "in": [],
                  "out": [
                    {
                      "name": "k",
                      "range": "[31:0]",
                      "size": 32
                    }
                  ]
                }
              },
              "position": {
                "x": 672,
                "y": 248
              },
              "size": {
                "width": 208,
                "height": 64
              }
            }
          ],
          "wires": [
            {
              "source": {
                "block": "c0fb4784-5e8c-4f41-9f4b-6daa2e9e03a4",
                "port": "constant-out"
              },
              "target": {
                "block": "7dbe7521-0f9f-43ee-ab0c-0439e2c20bc2",
                "port": "VALUE"
              }
            },
            {
              "source": {
                "block": "7dbe7521-0f9f-43ee-ab0c-0439e2c20bc2",
                "port": "k"
              },
              "target": {
                "block": "6c6347fd-d955-489b-acab-c4eef791127f",
                "port": "in"
              },
              "size": 32
            }
          ]
        }
      }
    },
    "dccd52713240167a29ea40dd4722a87a9375c41c": {
      "package": {
        "name": "Smiley",
        "version": "0.1",
        "description": "Stickers de Smiley",
        "author": "Juan Gonzalez-Gomez (Obijuan)",
        "image": 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+a2WMUjUZN%20W7xgOiFKJBLMCrmA30kz35/GHWuRhQyLmbk3EaWNBNCOzkAT3bnpkv6siCKFw2FTFi+YSojkihM4%20l4Om72Femd4spjZrupARET2ZeYsLr5Uw1FjUxbUiJi5ozMfDbTQxJp16yOVyFIlETFe8YJpVWxCE%20s+FwmFmcMH3fjQq5GlCPSrb8ix0sZhptIrTu+TKi+NmBuzc55nHjs7OzFI/HTRWiM40QRSKR1Vwu%20J/nYxFgbpv/WgFy+wDxNUndX9BSuyKzOMrNSQIOyDsx8f5pZvPDll1+aKl9kCiGKx+PF2dlZycd6%20gs109yaHu7IGzM3Xr0nxeWqLcvkC3gS1EQVxl+bmN+r2++GKtKdUvMDCTPkiwwtROp0ufvnll5KP%20cS4HihNq6krqGx6rpxCafxOxocsUBSW/H2hPZ6CJ7vxdunjBTPkiQwtRKS/EtKY/nEZxQo1YzmzX%20Jb+AXbU1hEBcK0KMdOKL8XY6f066ed8s+SJDr+LRaJSZF7oyeRKTE2zkhoj2ihaQa1CxoRN365bb%20gyuqDdP33cx8USwWM3y+yLBClEwmmf1CPcFmujp5CndfDVnUeZyP2V4H3BCEyEjI5YtKw1EhRArJ%20ZrNF1oVDXqj25PKFuofljOTMIETqENeKmMqtI52BJuak7qWlJYrFYoZ1RYYUIrnjvqfvo2m19guZ%20cRaPzEoBI38U8txALhKuSF+uTp5i9hfduHHDsIfpGW5Fj8fjxYWFBcnH0C9UH4y2i8Vipuy9q2e1%203PHXg9Cq3kzf45jz6Ix6fpGhhCibzRZjsZjkYwG/k64gL2T7HbURX4+xhchY1wqOVn+8Hidz8HMu%20l6NYLGa4km5DCZFsSA5z5LCjxq7aEtcKjlZ/BvpPMEu6v/nmG8OF6AyzssuF5K5MnsQcOSxkB+Rf%207GDKgondY2YFJfi1YPq+WzZEByE6QrmQHEq164dR+3bgiipzs3jv7IubaygXojOMKzKEEJULyQHs%20qLGrts6CjzxR7ZAL0d24ccMwja51F6JEIoGQnIHdkNHyQ9hVm9/NYiNRW+RCdKzz3WwlRIIgnGVd%20CITkDLCQrRh5IUOOyKxuFhuJ2uLmGpinui4sLBhiFl1dhSgaja4iJGdcjL5rRZe+zCZP3DWsmzW6%20W7MiHw+3MRtdY7FY3XuL6iZEPM8zZ8lNjLUhJGcIR2Rs17GcgSsy6yYCjrb2sBpdRVGkaDRa196i%20ugkRKyTn6WhE46pRFguD71rzL7CYsd3ilsHfux28STXG63HSxHi75GOPHj2qa29RXYQoHo8Xl5aW%20JB+7e9OFxlUDYPTQjhkcW10X+rzxF3qEVmvP1clTzOMi6lm4UPMVXxCEs6yeofPnWjBLzihuyARV%20TRnkGZjkTOA4cnm4onowfZ+T/PrS0lLdChdqLkSsAgXO5aC7jMoOUAe3YYL8i7hWRD8KAzPM40N4%20rj70BluYvUX1KlyoqRCl02l2gcJ4O3k9TtwlhlnkzbHAox9FymmYI2SJEu76cfemi1m4UI+hqDUV%20IrkCBfQMYZFQt+hiV21WpyHCzdYNucKFb775hrLZbE1DdDUTIp7nmRMUEJLDImH1RRfiLOVmUWxS%20TybG2g1TuFAzIWJNe+0JNqNAAYuEeiGCIzK1OCPHVz/cXAPzaPHZ2dmalnPXRIgSiUQxl8tJu6G/%20ww1hcahi9w9HZGpxRo6vvpSbuGApIWL9QSNDrZiggMUBjgjiDOrIVYYrWlhYqJkr0l2IYrGYpBvi%20XA6mLQSgYiHConsMMxUBoHKu/vQGW5iuqFa5Il2FSBCEs/F4XPIxlGsbF8xwM7ujxfsHlDF9j93k%20mkgkdHdFugpRPB5nNq9OjLXj3TfqjnrNXAlkjIoxsaNFaNUQeD1OGhlqlXysFrki3YSonBvCPDkA%20tMcszawHrxehVcPASpXkcjndXZFuagA3ZF4Qtzexw8DCDkzoinQRIjk3dAfTtYHGIKdlXjBdAa5I%20NyFiuSFPRyN9PNyGdxtou5itYTEzKyisgCvSU4gUqS3ALhVoA8KqQE9XlEwmdXFFmgtRIpEowg1h%20lwoAsJ4rYpkMwwkRy77BDQG9QAkwALVxRXpNW9BUiFgz5TiXA4NNgW6gBNjk718eDtzurkhrIZL8%20OvqGAABMR4uNhKlc0ezsrObnFWmmDqzzhtA3BEDtQKEJ0NIV1Woyt2ZCxHJDI8OtcEMA1IhlFJoA%20DWFN5n706BEJgnDWUEKUzWaLjx49knwMbggAAMxJb7CFAn7p4dTxeHzVUELEdENDrZiwbTIwQBQA%20UImZYK37dRMi5nBTuCEAADA1Hw+3EedyHPu6lmN/qhYiVgNrT7AZp68CAIAVXNG4vq5ICyGS/Dqr%20Bh0AAIC5YK3nCwsLmpRyVyVE2WxWsmQb43zMS8APFwsAeBe9G1yrEiLWCxgZhhsyKyi1BwAoWde1%20CM9VteogLAeAwXauHY24CEAXeoMt5JG4v0RRrLpoQbUQsYoUzp9rQck2AHXC44EQAf1gVUInk8n6%20OCLWL0ZuCACgBM6FcLBZYIXnqp0/p+oOyGazxdnZ2eO7sY5GTNkGdVjIHLgIJgZtHubBzTUwUy/V%20uCJVQsT6hQP9LXinABYyACwMy2xUUz2nSoiYxz1gkoIl8CDhDQCQESKpNSKXy1E6nVYVnlMsROl0%20uri0tHTs6wG/E0UKVhEiJLzN6w7RBwZqIkYtikyK5kIENwSAceE4c+XL4L7NychQW32FiJ0fQpEC%20qA+9jMO7ANw30Ml5B5okj4cQRZGSyaTi8JwiIUqn08VcLnfs6+fPtaAj30o3mR8hVtM6IpRCgzq7%20IjXVc4ruWpbtghuy2GKGTYWpd6pmApMgzAsrT6S7ECEsB4xIbxBtA2YFoTnz4vU4NQvPVSxECMvZ%20aWFHzsXUiztcBqgRWoXnKlYQuCGARRcuQ2tQbm5uWOE5nuchRMA+iztCO8cx08gjs5Wbg3dhheeU%20NrdWJETZbFayiRVhOeveXFh0zYuZChbgaM2PFj1FFakIy2bBDcEVYdE1ojibZ3OIaSzmR4vwXEV3%20LCssh6S2hYXIJCEv9M1IibM5FvcA+tUsgdfjlNy4Li0tVXw0REWfYqkjHzBbzuKLmUkWCbMsuhBn%20ideJsL7lXVGl1XNl7wSe54vSvxhhOUsvZiZZJJBjkBJnc4QrMcHDSkJ0gqUf2ggRs1ruHITIypgl%207ApXLo0Zwl6eDrx31lkvWiQLh6SiaWodkYT1dyBJbHHM4DR6kKM09fuHsKq1YH0eWVG1ioVIEISz%20UmXbCMtZHzM4Dcwpk1vkjb9RDKCZ1VJUE56TFaJkMrmKnSh2OIbd9aOZlS1EBl/kOZcDPYgWgxXO%20r6RgQfZOYCkZyrZt4ooM7jhwH8q5DWM72gBC+9ZbL2TKuAVBOKupEHk6GpEgts1i1oTXZ+JFwchT%20J7CJsCYyza2rqoQom81KTtvGDQSrbQQ8HY0I7ZjYdWDYqVXXDHVTFpif5HQ6Lfl15Ifsg5ET3tgQ%20mfsaYaqCNZGpnFMnRMgPASNvPBCWM6/rQHjfuri5BslNhlT1tWohwg2EXTVeFzYReO+AmvdXrp+I%20KURSCoYbCLtqI4CG6up2pxBIoCesaIVceK5BiXIhHIJdNV4THC0cEVDpiBQLEW4gcLCrNtrCz6rM%20Aca/VgjvWx9WPxGrAI4pRKxvQDgEOxwjwOpVAMZ3j9jM2gOpkLAoiszziSoWIoRD7IuRJq1jR21u%20R4s5lfaAZVpYJueYEAmCcFaqkRVnh9j7pjLKNGe4IXNvJLChtQcs51uxEKXT6VVpq4WwHG6s+jMy%201IY3w6Tiff5cC6Zh2Ga9UDZhoaHSJ2Ikh90Xs/rvqlG2rQ6vx2mIMm6E5eyF1D2nxBFJCxEWANsL%20Ub3DcyPDrXgjTOwkIUT2Qsq8sAoWjglRNps99s2I64K9haS+IR6E5cz83rUiLGczWOeFSWnMsTtD%20aqICTsIE9RYCT0cjXHkVeD1OOn+ufmIEN2Q/lDS2viNE6XS6qETZgM2sdqCpbrmGibF2vAFV8vFw%20fTYSno5GCJENYRW4SaV/GspZJjllA/ajHoLAuRzID2nkSuqR58N7Z0/cXIPk4YxlQ3OsQgUPQnPg%200K661vfDQP8J5BdMKgqcywE3a2dXJBFOl0r/VCRE6GQH9VzMrkyexEXX0NHW8ghxbCLsDWsQwtHK%20uXfuEEEQjn0DKuZAPRezkaFWbIQ0xM010MR47RwKNhH2xtPBFCK2I1pYWJC01gDUazHDQmbejcTE%20WBs2EXZ3RAHp9/9o5VzDITd0VvoHoWQWHOfq5Cndc0VYyMy7keBcDroyeQoX2/aOSHqNOBp9OxAi%201ow5FCoAFndvurCQYSPBcLKnkBsCzI3k0XqEBpZC/fGDIERAmoH+E7o1SU7fd2Mh05np+5wuPzfg%20d9IX46iUA3/cD0ockSJrBUBJMLTON5w/14IGyBrQG2yhiTFtm1w5l4Om77lxccEf94TEhvJoCXcF%20jggxesDGzTXQzA+nNd09Td/HQlYr7t7kNJ2WceemC3ll8A6sEu7DdQmyjghuCFS6s/7uXvVhntJu%20GiG52jI/e0aTz/rEWFvdxggBczmifc1ZPSZEUmDGHKiUj4fbqhIjzuWg+dkz2E3Xy9V+f7qqEOvI%20UCvdvcnhYgIJR1T+M30gROghAvUSI09HI0So3otFoIlWfvqzqjDdlcmTCKcCGUckrSOHe4kayt2c%20ACgVo9S/3qt4QRsZaqUU/x7uNYM4o/nZMxUXMOxtIP5EV1FmD2QIVOqIpE7MA6Ca3fW/+ffpu3uc%20ZHk353LsCdC/3kOZtgHF6O5Njlb+8z6NDLVK5o4Cfid9d4+j//vpz9QbbMFFA2XvKSkO1yU494VI%20ekHxY5cKqnNHpeT1cmabxLVd8nQ0ohLTBHg9f1Qv5vIFyr/YISKC8ADNOFypLbsisGJ7AKhxScC8%20ooTNA6iGnmAzPU9tMR9vOGqRAAAAAL05XCDXcNQiHSaA0BwAAIAqKVeBLZslRhIZAABAtZQLzZeq%205nClAAAA1JRSxTaECAAAQL2E6A9HJAWOCAcAAKAF5VqBkAQCAACgK+VagSBEAAAA6kKpYruBSHrg%20KQAAAKAnpR5WOCIAAAB1hSlEXhyKBwAAQAMCaosVcCgeAAAALSg3HAGhOQAAAHUFQgQAAABCBAAA%20AEIEAAAAQIgAAABAiAAAAICagvN/AQBAJ3L5AuVf7Bz7uqejEcevQ4gAAKB6BHGXMivbtJjaIlHc%20peWVAuXzO5LiwyLgdxLHNVBvsJk6/U3UE2y23aGkTjvfPLlDN8xiakvyud6OxoPm3k5/E3GcgwL+%20JpxeC4CNxefBw3V6MvNWkeCwyKwUiIjo+aE1KOB3Um+wmUaG2sqebgohMpE9npvfpMXUJmVWCopu%20nueMr3MuBwUCTQe7mIH+E/iEAmCDtaR/8DdNBKicOGVWCvTg4RvydDTSyHArTYy1W3YD7LTyDfPk%206VvNdi1HEdeK9Dy1dbCL8XQ00sz3p22xewHAroxfFHUXoaPkX+zQ7anX9GB6nQb6T9Cdmy7LCRLz%20r8nnd0z5By2mNmnok9/I/7+/0O2p1zW7afIvdqh/8CUtZ7bxaQXAgixntt8Jn9Uaca1IT56+Jf+H%20/6VbU6/sIUS5Fzumu0nODb6k/sHf6Mdnm3W7Uax2gwAA9teYFWNsMsW1It2eek1/Cf1imo3vYmpT%20nRCZBUHcpcvXRAp+9Gtddysl6iWCAACdBUAsGur1ZFYKFPzoV3o888b019bUOaLlzDYNf/p7zWO2%20AAD70Rkw5nL5+UWRRLFIX4y3m+6adnd3/+GIurq6TPcHPJ55Q8GPfoUIAQBqQm+whTiXw5Cv7au/%20rVEuXzDdNXW73X8IUek/zOSEPr8oGvK1BfzoEQbAqkwY2HU8efrWtNeVmSMyQr6FhZELAibG2vFp%20BcCiXJ08RT3BZlwIhSyW0RNTbt+NKpIBv5M+Hm7DXQeAhXk2e4ZuTb2iB9PrJK79UcBQanLvPDSy%20h4iof/A3XDQGPp/vDyHy+Xy0sLCAqyKBZ3/ETznx6wk208z3p3HBALCJM7o6eeqgLNkIQ0xHhlrN%20KESOd4RICkHcNWQHb0+wuWZl0iPDrXR18tTB9SgNOFzObJO4ViRvRyMN9J/AiB8AbEhvsEX2cUHc%20VfwzJ8baaKD/BN2ael1x9GdirM3Q07zLDUiQfeWZle2yF7oefDHerliIRoZaaWS4VbFNPhzbdHMN%201BtsMeQ1AQAYj4yKJlhuf515NttCi6lNGr8gP1ZoZKiV7t7kDH0dpAYkcNwfr9mUDa29wRb67l5l%20F35kqJVW/vM+Td93Q0AAAKZb61L8e3Rl8iR5OhrfeSzgd9LM96dp+r7blH9bqYfoQIhCoZDkE43W%20SXyYj4fbaOb708y6/oDfSal/vUfT9904gAoAYFrcXANdnTxF//fTn2nlP+/T/Oyf6MXq/6N/8++b%20JiVQVWhueWXb0H/oQP8JWvnpzzQ3v0H5FzskirsH1Sos9+PpaFTUBGvW4a8AgPqznFHeZHrU+RzG%2063GacmMtAoYiiwAAHwdJREFUteYerk1wEpmvofXobkFJybTHo1CIMLkBAKAScU15sYLX02iLa3NY%20iBqIiLq7ux3Sao4jDQAAAKin3OTtAyFiq3nRchelU8UInkouJAAAHF87lDffB/z2OFzzcG3CgRD1%209fUde6IV8yOcRY/aBQBYA6udvlpJnkz2L7ZifkQuEVjNhQQAgKMoHUemZn0yOqw8WSgUchwTosM1%203Ycx42hxOdQkAtUkHAEAQPFG2YKFCpXUGhwIEatyzmquSM2OY9HAk8gBAMZETW7Za0lHdLzW4Ggq%20qAJHZC0hUlODj14iAIBS1KydVnRElYQnbeeIiJQfXodeIgCA4g2sinWj02IVc6yhr0en+TQcesA2%20vURqKufQUwUAUIKakD7HOSx1DVhDX48an4Z3L8LxQaJW7CXqVXHC4vIKhAgAoMARqQjNWW0wMys8%20eTQV1CD3IJGxjwxXi5qChQyECABQIYK4qzg0Z8XSbdY16O7u/oApRKwD8lDCTbS8gl4iAIB+G9eA%2033qnBEiFJzmOI7fb/bNiIbJasl6N/X2OEm4AQBULcDk6A9Yb7SMVnpSKvL0jRKxziazYR6Nm94GC%20BQCAXmtFpwVnzEmZmLJCxHREFuyjUfOmo7EVAFAJz1UNO7VWaI7V0CulM0eFyCFVOZezZC+RciFC%20wQIAoBy5fEFxtbGno9FyJ0lXWjF3TIhYT7JifkRNCTccEQBAj3XCioUKrI370Yq5ioWIyHr5ETWJ%20wfyLHctVEAIAtEXNxt1q/UNE0pXGXq/3WMWcMiGyYFiqB64IAGAAR6QmQmNGQWbpS8VCZMX8iJo3%20f25+A580AID0hj2zrW7GnMVKt1kRNCVC5KjUZtlRiNBPBADQ0g2dP2fFsJy0ELFahCSnf0odG27N%20ggXlN4C4VlR1zggAwPrMPVMeMbFifkhJoQJTiOxSsKB2N4LwHADgKIK4q7JQwXr5ISln2NXVJVmo%20wBQiO01YULMbmZuHIwIAVL9B9XQ0WnK0T0YilcMyOIodkRULFgb6lQtR/sUOxv0AAKoWImu6IemN%20OsvgMIXI5/M5vF6vLRyR1+NUNX79ydM3+OQBAIhoLyz34zPlkZKB/hMWFCJpnVDsiFjfZNWGTjWu%20COE5AEA1bohIXS+jGYWI4zhmRbasENkpTzQy1Kb4exCeAwBUI0Tnz7WQm2uw3LWQKtiQC8upEiIr%20lnF3BpqIcyk/Kx7hOQAAwnKHjYry/JCsEHV3d0tO4rbqiBs1NwXCcwAAtWE5O+WHVAsR65utmica%20GW5V/D35FzvoKQLA5jx4uK74e6wallOTH1IlRFZ1Rb3BFlXVc49nEJ4DwK4sZ7Yle2bs6IaIpFM3%204XC47PfJChHrBzy3bHhOefXcj882cTQEAHBDthciVnSoXFiurBCx+omsGo5SUz1HRPTk6Vt8IgGw%20GYK4q2otHBlqtWhYTl2hQlkhYv0Qca1oydLlzkCTqpMSn8xAiACwG3PzG4qPBLeqG9q7HseFqKur%20i3w+X9mS5LJCxArPWbV6Tm1PEXJFANiL21OvFX+Pp6PRkkKUyxckz2GqxA1V6ogkx3ZbtYdGTfUc%20kfpYMQDAfCymNlUdgKd2fTGjG5IzMoqFyO12/yx1PlFmpUCCuGu5C+rmGmhkSPnNklkp4JwiAGzC%20LRVuiIhUrS1mEeajcBxHoVCookkBFWXMWKpm2aIFlbsWtTcnAMBci+5zlSexej1Oy10P1mSJSsNy%20ECIGvcEWVUULz1NbmD8HgMVRW5z0xXi7Ja8HSwcqDctVLEQ+n8/R1dUlufBalYkxdTcNckUAWJdc%20vqCqXcPT0WjJI8HldCAcDn+gqRCxbJa4VrSsK/p4uE3lINS3aHAFwKLcVhl+vzJ50rLXREoDBgcH%20mceCVyVEkUhEkS2zhCtSaaUvX1vDJxYAuKEDN/TxcJslrwmrl0pJWE6REHV3d9tqygLRXnhOjSv6%208dkmKugAsBhqN5hWLdmWW/+VhOUUCRFL5awcnnNzDaigAwDQYmpT1ZlDnMuhOt9sViFSGpZTLES2%20DM+pvImep7bgigCwCGo3lhPj7ZacK1da97UIyykWIrnwnBWbW4mIvB6n6ia08QsiPsEAWGDBVVMh%20bHU3xBprpjQsp1iIWGpn5fAckfqKF8ygA8D8qM0NWdkNsZpY1YTlVAlRNBpl7hqsSjWu6Ktra5Z1%20iwBYnVtTr1TNlLNjbohlVHQRIlZzq9UPiLtz06Wqgk5cK9LtqVf4RANgMnL5Aj2YVtegbmU3RCR9%20BhvHcarCcqqEiEiuaMG6yXk316C6r+jBwzcY/QOAybh8bU3VeUNWd0O5fIF5JLiasFw1QvSB9IJr%207fE2avuKiIjGLwr4ZANgEtSWaxPtRU/s5obkDIpuQuR2u38eHBw89vX8ix1L7/zdXANdmTyl6nsz%20KwX6dhpz6AAwOoK4q7ri1cpTFA6ESGLoq9frrfjIB82ESE79rO6KvhhvJ09Ho6rvvT31CnPoADA4%20t1UWKBARTd/nLH1t5uY3JK9NNW6oKiEKh8O26ymq9mYT14o0fhG9RQAYlcXUJj14qK7loifYbNkJ%202yVY7Sh1EyLWL7d6TxHR3nlFPcFmVd/7PLWFEB0ABqSakBwR0fQ9a7uhXL7A7B3y+XyOan625kK0%20Z22tP2dt+h6nunABIToAjEc1IbkrkyctefrqYfQoUtBEiHw+n4NVtGD1OWtej1N1Obe4VqThT3/H%20Jx8Ag1BNSM7T0Wjpcu0DIWIUKYTDYUe1P7vqGkOWGtoh/HR18pTqwoXMSoFuodEVgLojiLs0/In6%20jeH0fc7S5dpEe7khPYoUSjiKxWLVP8Tn8xVzudyxr6/8533L29XF1Cb1D/6m+vvnZ/9k+QQnAEbm%203OBLVUNNiYjOn2uhpz/8ybbX6Pfff/9AbROrpo6IiD1/zuql3ER7hQsTY+r7BoY/+R2z6ACoE99O%20r6sWIc7loOn7bstfo+XMtuQ1Gh0dJS1ESDNHJAjCWZ/PtyqK4rE3auWnP1vetgriLgVDv6pOdPYE%20m+nZ7BmsCgDUeIENfvSr6u+f+f40DfSfsPx1Gr8gSBYq/PTTT9Td3e3Q4ndoohBut/tn1vEQUgku%20q+HmGqpqZHue2kK+CIAabx77B1+q/v7z51psIUK5fEFShPr6+jQTIc2EiIgoFotJft0O4Tmi6kN0%20t6deW77/CgCj0D/4UtVAUyL7hOTk1m9WOqbuQiRXym2Xw+GuTJ6igF99ccb4BQFTugHQmfELAmVW%201Pfxzfxw2vLphpJr1LNkWxchklNJOzS4Eu2H6O6p3yntjQASULwAgE48nnnDbMyshImxNttUuT54%20uC7pGlnRr2rQpFjhMKFQqLiwsHDs69/d4yw/lbbEt9Pr9NXf1lR/f8DvpH/z72PVAEBDqm21sNPn%20UhB3yf/hf48JEcdxJAiCQ+vfp7m/tHMpd4kvxttVz6Ij2mt2Hb+A84sA0IrlzHZVTaucy1FVtMNs%20PJl5K+mGtM4N6eaIiNgNrnZq3mTtKJRwZfIkXVV5/hEAQLvPop0iOkRE//Phf4+1o3AcR9ls9gOt%20eod0dURE7BjiLZvkioj28kXzVfYG3Z56bZtCDwD0EqFqKuSIiEaGWm0lQqxxPtFolPQQId0ckZwr%20stvOotp8kR2vGQBailA1FXJ2zNfW2g3p5ojkXNFtG7kior180chQa1U/4/OLIsq6AVBItWXanMtR%20dVTDjBvnWrshXR0RXJG2O7PSh6Iz0IQVBoAKRKiaMm0iotS/3rPV502uUk5PN6SrI4Ir+oNSvkjt%20QXpEez1G/YMv4YwAqIEIfXePs92mj9U3pLcb0t0RybmiO3930Rfj7bZ6o5cz21UnTuGMANBXhCbG%202ujuTc5W162ebkh3RyTvil7ZboJAZ6CJ7tx0VfUz4IwA0E+ERoZabSdC9XZDNXFERETd3d3FpaWl%20Y1+3a5+MFpV0cEYAaCtCAb+T5mfP2GKO3GFy+QL5//eX42tMjdxQTRwREVE8HpdW4el1yuULtvvQ%20aFFJV3JGmNgN7Iwg7tLQJ79BhKqAlbOPx+M1cUM1c0RE7Bl0I0Otthmprscujgh9RsC+IlRtNard%20owuswwG9Xi9ls1lHrV5HzeSf5YqePH1Li6lNW36Qpu+7q5pJV+LziyImMACIEERIMZcZKQLWem16%20Ieru7naMjo5KX4xra7b9QM18f7qqM4wOixEGpQK77OL9H/4XIlQlc/Mb9Dy1dezrfX19mp83ZBgh%20ItqroOO44xUpmZWCbXf0pR4jLcToydO3NPTJbzjPCFh68ay2BQIitOcoWQZAj/OGDCVEPp/PwRoj%20/tW1NdsuoFqK0Y/PNql/8CXECFiOb6fXafjT36sWISKyfcXpg4fSo3xGR0cpFAo5av16alascKDE%20gnC2u7t7VarJ1Y6NZEd3KVrEvbHjA1ZDq8IezuWgOzddti7ukSvXTqfT5PP5ai5ENa9VdLvdPzPL%20uR++sW3hgtbOSFwrUvCjX1HEAEy/OftL6BfNRGh+9oztK0zHL4qSX49Go3URobo4ohKscm4ck62t%20MyLaK5G/c9Nlyx4JYF4WU5s0/Ik2oThECPaYm9+g4U+Pn1Rb63LtujuiEolEQvLrmZUC3Zp6Zeub%20RUtnRLRXxNA/+NKWzcPAnNyaekX9g79BhDTe4LIKFFjrseWFyOfzOa5fvy75mF0nLkiJ0flz2hyt%20nlkpUDD0KyYxAMMvlucGX2o2oR8i9Ae3p15JFigMDg7WpUDhMHULzRHJFy70BJvpmc0OpWKhVaK2%20BEJ1wIhoGYoj2gvzz3x/mrweJ65tapP6B387LtR1LFAwhCMiki9ceJ7aom+n1/HppL0JDBNj2iVY%20nzx9S8HQr5jgDQzjgi5fEzULxZVEaH72DERoH7meoXqLUN0dUYlwOFycnZ2VtNUp/j3cTPs8nnlD%20nzMqXtRi1wnowBgsZ7Zp/KKgWWEOHP9xbk29kgx1dnV1UTqddhjhNRpCiARBOOvz+VZF8fgiixDd%20u8zNb9D4BUGznWNp9zh9z404OjDEAlkNdu9FlBJ6qaGmREQ//fQTdXd3G0KIDLFlcLvdP7PGSiBE%209y4D/SdofvYMeToaNfuZmZUCBT/6lW7Z8LBCUHsWU5v0Px/+V3MR+u4eBxE6wvhF6fmT169fN4wI%20GcYRlWD1FiFEJ+EiNe41KuHpaKTp+xz1BltwkYHm9+ztqVf04KG2TdaojFPmOI0UkjOkEGWz2WJ3%20dzchRKdgx6NxRV2J8+da6O5NF8QfaMLjmTf01bU1TUPKRPY+0K6c65SqkiMyVkiuhKHePZ/P55AL%200dm90VWK6ftu+u4eR5xL2/vqx2ebFAwhXAeqXxDPDb6kzy+KmovQyFAr/Zt/HyIk4TzHL0gXNRkt%20JGdIR1SCFaIjIkr96z1YcAn0qD4q4elopCuTJ3EKLKiYXL5At6de6+LWMbhUHlaUxIghOUMLkVyI%20ztPRSCn+PeyCmDshgX58ps/g2J5gM12dPIn8EZC9Bx88XKcH0+uaOyAiVHiWgzVLjsiYIbkShlzN%20fT6fgzX7KP9ih76y8Ymucri5Bnr6w590CdUR7YVH+wd/o3ODL209JR1IC9CtqVfk36+G00OEJsba%20UJRQxoWyTmn++uuvDStChnVEJViNrkR7pZqw5mz0DNXBIYFaOSCivVDc9H03DfSfwAWX4S+hXyQ/%207319fcTzvMPIr93QQiQ3iw4lm5WhR9MgBAnUQoCI9qo3p++7EYovw+VromRZvFFmyZlaiIiIeJ4v%20fvTRR5KPoXSzMhZTmzR+QZScvAtBAkYUIM7loCuTp+iL8XZc9DLI5YX++c9/Ujgcdhj9bzC8EBER%20xWKx4o0bNyQfGxlqpen7btyNFSwgejQTSlGqshvoP4FNgkVYzmzTg4frulTBSW1opu9x6GGrgFx+%2073gXqU3BpUuXKB6PO8zwd5hCiIjkS7rv/N2FnZOCBUXv3NHhXe3IcCtNjLVjUTEpj2fe0JOnb+l5%20aqsm9wtyQcpg5YW6urqI5/kP3G73zxAiLXf0MoNRiYjmZ/+EkJACbk290j28cnSXOzLUigITk+yy%20Hzxcpyczb2t2f2BitnJY/UIcxxHP84aukjOtEBHJ54swj07dgnP52ppufUdyLmlkqA2FJkba6Im7%20NDe/UTP3UyLgd9Ldmy5sIlU4VdaRMP/4xz8oEok4zPT3mEqIiOTzRSheUEetihmO4ulopImxdhro%20b8EGok7MzW8cCFAtQTGCeuSOdjBTXsjUQkQk31+E4gX1fDu9TrenXtUsHHN0EzEy1Ea9wWY4pRqJ%20z9z8Rl3e64mxNroyeQobRpVRDFZxgpFH+FhSiOT6i4hw6mhV13a/PFfv3qNyTmmgv4UG+k8gZKPR%204rWY2qK5+Y2ahmGPgonu1X82WUe/cBxH2WzWNMUJlhAiIqJ0Ol0MhULEKl7A5IXqFy+9hlYqgXM5%20qCfYTL3BFrglha5nMbVJi6mtmlRIyoH+Mm0Y+uQ35kbCyHPkLC1ERESJRKL42WefMRcwTF6wjiAd%20dku9wWYK+JsgTId2ypmVbVpMbdFiaqumxQYQoNrAmpxAZM7iBEsJEZF88QIq6awrSIff40BgX5T8%20TRTwOy3/fi+mNmk5U6DMyjYtr2zX3fFAgPRFrkJudHSUEomEw+x/o+mFiIgoEokUHz16JPkYKun0%20EaR6JbqViFOn30meDid1BpwU8DeZ7h5YzmyTuLZLi6ktWs5sU/7FjuFEBwKkL3Lje8wwzNRWQiQI%20wtlQKLS6tLQEMarVNa/RzDE9FkvO5aDOQBNxrgbqDDj375HaC1UuX6D8ix0SxSItr2yTKO7S8kqB%20RHHX0IJzlJGhvekZCJNqvxHpH3zJrJAz0+QEWwhRSYzkJi+grFvf0MGDh+umWjzLidVhd1XNAlsS%20lxL5/E7N+7X0cp0T4+00MtSK0HeNRciMkxNsI0RE5SvpIEb6spjapCczbw2XRwLaEfA7aWKsHRWp%20OkcbWGXaROavkLO8EBERJZPJ4l//+lfm4xNjbXT3Joe7XecP0p4gvbGMS7IznMtBA/0nEH4zgAhZ%20oULOFkJEJF/WTYQeo1qHGJ48fVPTAZpAG86f22sqxmfFGCL09ddfUzQadVjxb7ekEBHJl3VDjOpD%20vUfLgPKURi1h/p+xRMgqZdq2EyIi+bJuiBFECUB8jALrSAc7iJDlhQhiZA4WU5v7orRpiYoyo1Ma%20mzTQfwKn6BpchKzUK2RrISKSn9YNMTIWuXyB5uY3aTG1Sc9TW3BLGrqe3n3xQcOpOUTIar1Cthei%20cg2vECPjspzZprlnG3vDOzPbECaFwtMbbKGeYDNcD0QIQgQxAloK095EaWPOWasHh+ftlQbCQngg%20QhAiiBGoIYeHgOZe7Bhm+rQeeDoaKeB3UmegyTZDXi21Bom79NW1NYiQnYUIYmQfSnPcFlNbppvh%20VnI43o5G8ngaqdPfRBznQG7HAiIkV6JtVxGypRBBjEDp/J49N7Xnno7OhNPDVQX8TuL2Q2aHZ9h5%20OhrJ62ncH8KKyQUQIfthSyGqVIxw5Dg4TOlYhspEB3kaABGCEGkkRhiUCgCoZvMy/OnvzP44iBCE%20CGIEANBVhFhHOUCE3sX2sQO32/0zz/MfjI6OMp/z5Olb+kvoFxLEXXy6AABlmZvfgAjBEamj3Dgg%20nPQKACjH45k39PlFkfk4RAiOSJZEIuGQc0aZlQL5P/wvLWe2cbEAAMe4fE2UFaHBwUGIEISoMjH6%20+uuvmY+La0XqH3xJc/MbuFgAACLaq4wb+uQ3evDwDfM5o6OjlEwmHRCh4yA0xxYk2cP1iIju/N1F%20X4y342IBYGNy+QINf/q7bLO0HY5ygBDpBM/zxXA4TKLIttqoqAPAvpSrjCOy7vHeWoLQnAyhUMjB%208zx5vV7mc1BRB4A9eTzzhoIf/coUIY7jIEJwRNpRSa8R53LQ/OwZjGgBwAbITc8uiRDP89Td3Q0R%20giPShkp6jcS1IgU/+pUez7zBBQPAouTyBfpL6BdZEerq6qJ0Og0RghDpI0aJRMJx/fp12ed9flGk%208QsCQnUAWIzF1CYFQ7/KFiWUyrN9Ph9ESAEIzakgmUwWI5GIbBFDwO+k6XtuhOoAsAC3pl7R7anX%20ss+5dOkSxeNxCBCEqHak0+liJBKhcnmjOzddOE4CAJMiiLs0/OnvsseCcBxH8XgcRQkQojrdpIJw%20NhKJrM7Ozso+b2Sole7cdGE0EAAmYm5+g8YvCLKl2V6vl5LJJPJBEKL6E4/Hi19++aXscxCqA8A8%20Luj21CvZKQlERH19fZRMJjGuB0JkHCppfiXCNAYAjMxyZpvGLwplj5S/fv06xWIxuCAIkQF3UoJw%20NhwOry4sLMg+ryfYTNP3OPJ6nLhoABiESgoSOI6jZDJJoVAIIqQhSFpoyH6/UdkS7+epLQqG0HME%20gFFc0F9Cv5QVob6+Pspmsx9AhOCITEM6nS6Gw2HK5XKyzzt/roWm77tRyABAHfh2ep1uT72SLUgg%20QigOQmRiBEE4G41GV+UO2yNCmTcA9XBBleSCvF4vJRIJhOIgROankgZYIuSOAKgFleSCiPamJCQS%20CVTFQYis5Y4qKWTgXA66MnkKlXUAaMxiapPGL4iUf7Ej/xnkOEokEhQOh+GCIETWJB6PF2OxWFl3%20FPA76e5NF/UGW3DRAKhmEyju0lfX1mQHlZZAbxCEyDZks9liJBKhcu6ICFMZAKiGSosROI6jWCxG%200WgULghCZC8SiUQxGo2WdUcI1wGgjMXUJl2+tla2GIFoLxcUj8cJE7MhRPYNG1Q4r44I4ToAypHL%20F+jytTX68dlm2eciFwQhAkfgeb4YiUTK9h0R7fUe3b3pQnUdAKUNnbhLDx6uV1QNR0Q0OjpK8Xgc%20uSAIEZByR/F4fPXGjRsVPX9irI2uTJ5C/gjYmkrzQER7p6fG43H0BUGIQDmUFDNwLgdNjLfTxFg7%20BAnYisczb+j21Ouy5dhEe2G4aDSK6QgQIqCUZDJZjEajFYXrUNAA7IKSQgSivTBcLBZDMQKECFRD%20LBYrxuPxstV1RESejka6MnkS44KAJQXo1tRr2dNSD4MwHIQIaEylc+sgSMDuAuT1eikWi+HobggR%200Asl+aOSIE2MtdPIcCtySMBUzM1v0LcP1ysWoFIeKBqNohoOQgRqAc/zxVgsVrEgoagBmAUlRQgl%20Ll26RLFYDAIEIQL1EqRoNEpLS0sVC9JA/wm6MnkSfUjAMJT6gJ7MvFUkQChEgBABA5FIJIqxWKyi%20CrsS58+10Bfj7ZjUAOpGLl+g21OvaW5+o6I+IAgQhAhYVJBKhQ0D/ScQtgM1YW5+gx7PvKloFA8E%20CEIETEoymSzG4/GKc0hEf4TtJsbaqTPQhIsINEUQd+nJzFt68HBdUfgNAgQhAiZHaVFDiYDfSRNj%207XBJQBP3Mze/UdF5QO9sjDiOwuEwBAhCBKxCOp0uxuNxqrQP6TAjQ6000H+CBvpP4EKCisjlC/Tk%206VvFxQclAUIZNoQIWJhsNltMJBJU6aSGw3g6Gmmgv4VGhtoQugPHEMRdmpvfoAcP1ysev3OYrq4u%20ikajaESFEAHbLBqCcDaZTK7G4/GKS78hSoAlPnPzG4oLD0qMjo5SJBLBKB4IEbAzPM8XE4mEqrAd%20RAniowav10uRSIQikQjyPwBCBN51SYlEYjUejysq/5YSpd5gC3JKFiKXL9Biaqsq8SHaO5Y7Eong%20VFQAIQKVu6RkMqk4l1SCczmoJ9hMA/0nqDfYjEkOJmM5s01zz/acj5qcT4murq6S+0HxAYAQAXUu%20KZlMriaTSZqdna3qZx12Sz3BZpSFG9j1PE9tKZp0cBSv10vhcJgikQh1d3fD/QAIEdCGbDZbTCaT%20lEgkVBU4HCXgd1JvsBnCVGfheZ7aosXUluIy62MOeL/vZ/9/EB8AIQLmEqWSMHX6m6gn2Eyd/iYU%20PmjMYmqTljMFWkxtUmalULXwQHwAhAgYTpSSyaTiCQ7l2BMlJwX8TRAnBSxntml5ZZsyK9u0vFKo%20+EyfSiiF3cLhMEquAYQIGI9STonn+aoKHSpxTh5PI/UGm8nT0WjbQohcfs/ZLKa2KJ/f2Refgua/%20p6+vryQ8yPkACBEwFzzPF0uipFUIT06gOK6BeoPNxLkaqDPg3P/X3C5qObNN4touLWcKJK7t0mJq%20i0RxVxfBOep6QqEQhUIhVLsBCBGwjlvieX6V53nieV53YTpKT7B5b5HtaCSPp5GIiDr9TcRxexv8%20WjorQdylzMr2wX8v7ofORHGXlvcFJpPZrqpyTanw7IsOhUIhNJkCCBGAMBkBzuWggEZuKp/f0aQ4%20QCu6urpKYTYID4AQAXAYnueL6XSaeJ6ndDqtesIDeNftdHd3H4gOCgwAhAgAha4pnU6v8jxP2WyW%200um04ZyTkejr6yOfz3cgPN3d3cjvAAgRAHqQTqeLgiBQSaBKIqVHlZ7R4DjuQGjcbncptIbwGoAQ%20AWAUeJ4v7v9bEi0SBIGy2awpQn1dXV3kdrvJ7XYfiM2hfyE2AEIEgJUc1WGhOvTYO/99mHJiVhIR%20KUpiUmLfxRz+/xAZACECAAAAag2mTAIAAIAQAQAAsC//HzL0oR/uyDq7AAAAAElFTkSuQmCC%22%20preserveAspectRatio=%22none%22%20height=%22526.25%22%20width=%22522.5%22%20image-rendering=%22optimizeQuality%22%20transform=%22translate(-130.179%20-266.38)%22/%3E%3C/svg%3E"
      },
      "design": {
        "graph": {
          "blocks": [],
          "wires": []
        }
      }
    },
    "87abc950ab83340895d1780090127b1528046813": {
      "package": {
        "name": "OR-4",
        "version": "1.0.1",
        "description": "Puerta OR de 4 entradas",
        "author": "Jesús Arroyo, Juan González",
        "image": "%3Csvg%20xmlns=%22http://www.w3.org/2000/svg%22%20height=%22192.718%22%20width=%22383.697%22%20version=%221%22%3E%3Cpath%20d=%22M175.56%20188.718H84.527s30.345-42.538%2031.086-94.03c.743-51.49-31.821-90.294-31.821-90.294L176.109%204c46.445%201.948%20103.899%2053.44%20123.047%2093.678-32.601%2067.503-92.158%2089.79-123.596%2091.04z%22%20fill=%22none%22%20stroke=%22#000%22%20stroke-width=%228%22%20stroke-linecap=%22round%22%20stroke-linejoin=%22round%22/%3E%3Cpath%20d=%22M4.057%2047.292h99.605M4.883%20145.168h100.981M298.57%2098.89h81.07%22%20fill=%22none%22%20stroke=%22#000%22%20stroke-width=%228%22%20stroke-linecap=%22round%22/%3E%3Ctext%20style=%22line-height:125%25%22%20font-weight=%22400%22%20font-size=%2266.317%22%20y=%22121.28%22%20x=%22131.572%22%20font-family=%22sans-serif%22%20letter-spacing=%220%22%20word-spacing=%220%22%20fill=%22#00f%22%3E%3Ctspan%20font-weight=%22700%22%20y=%22121.28%22%20x=%22131.572%22%3EOR%3C/tspan%3E%3C/text%3E%3C/svg%3E"
      },
      "design": {
        "graph": {
          "blocks": [
            {
              "id": "18c2ebc7-5152-439c-9b3f-851c59bac834",
              "type": "basic.input",
              "data": {
                "name": ""
              },
              "position": {
                "x": 72,
                "y": 48
              }
            },
            {
              "id": "97b51945-d716-4b6c-9db9-970d08541249",
              "type": "basic.input",
              "data": {
                "name": ""
              },
              "position": {
                "x": 72,
                "y": 120
              }
            },
            {
              "id": "664caf9e-5f40-4df4-800a-b626af702e62",
              "type": "basic.output",
              "data": {
                "name": ""
              },
              "position": {
                "x": 784,
                "y": 152
              }
            },
            {
              "id": "8c46de6c-8895-446f-bcbd-850a4a72c42d",
              "type": "basic.input",
              "data": {
                "name": ""
              },
              "position": {
                "x": 72,
                "y": 184
              }
            },
            {
              "id": "e3048d1d-5eca-42de-9b82-e4da2969a091",
              "type": "basic.input",
              "data": {
                "name": ""
              },
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                "y": 256
              }
            },
            {
              "id": "00925b04-5004-4307-a737-fa4e97c8b6ab",
              "type": "basic.code",
              "data": {
                "code": "//-- Puerta OR\n\n//-- module and (input wire a, input wire b,\n//--             output wire c);\n\nassign o = a | b | c | d;\n\n//-- endmodule",
                "params": [],
                "ports": {
                  "in": [
                    {
                      "name": "a"
                    },
                    {
                      "name": "b"
                    },
                    {
                      "name": "c"
                    },
                    {
                      "name": "d"
                    }
                  ],
                  "out": [
                    {
                      "name": "o"
                    }
                  ]
                }
              },
              "position": {
                "x": 256,
                "y": 48
              },
              "size": {
                "width": 464,
                "height": 272
              }
            }
          ],
          "wires": [
            {
              "source": {
                "block": "18c2ebc7-5152-439c-9b3f-851c59bac834",
                "port": "out"
              },
              "target": {
                "block": "00925b04-5004-4307-a737-fa4e97c8b6ab",
                "port": "a"
              }
            },
            {
              "source": {
                "block": "97b51945-d716-4b6c-9db9-970d08541249",
                "port": "out"
              },
              "target": {
                "block": "00925b04-5004-4307-a737-fa4e97c8b6ab",
                "port": "b"
              }
            },
            {
              "source": {
                "block": "00925b04-5004-4307-a737-fa4e97c8b6ab",
                "port": "o"
              },
              "target": {
                "block": "664caf9e-5f40-4df4-800a-b626af702e62",
                "port": "in"
              }
            },
            {
              "source": {
                "block": "8c46de6c-8895-446f-bcbd-850a4a72c42d",
                "port": "out"
              },
              "target": {
                "block": "00925b04-5004-4307-a737-fa4e97c8b6ab",
                "port": "c"
              }
            },
            {
              "source": {
                "block": "e3048d1d-5eca-42de-9b82-e4da2969a091",
                "port": "out"
              },
              "target": {
                "block": "00925b04-5004-4307-a737-fa4e97c8b6ab",
                "port": "d"
              }
            }
          ]
        }
      }
    },
    "6c0c4a7377571a0dec833de770a99fe2fdff71dd": {
      "package": {
        "name": "IO",
        "version": "0.1.2",
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      },
      "design": {
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            },
            {
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              "position": {
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              }
            },
            {
              "id": "3924e842-5646-4d03-bfa7-e141cf32635f",
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                "range": "[3:0]",
                "clock": false,
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              },
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              }
            },
            {
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              "position": {
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              }
            },
            {
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              }
            },
            {
              "id": "16e78204-213e-4833-9096-89d735307ec2",
              "type": "basic.code",
              "data": {
                "code": "assign o3 = i[3];\nassign o2 = i[2];\nassign o1 = i[1];\nassign o0 = i[0];",
                "params": [],
                "ports": {
                  "in": [
                    {
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                      "range": "[3:0]",
                      "size": 4
                    }
                  ],
                  "out": [
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                    {
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                    },
                    {
                      "name": "o1"
                    },
                    {
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                  ]
                }
              },
              "position": {
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                "y": 176
              },
              "size": {
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                "height": 112
              }
            }
          ],
          "wires": [
            {
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                "port": "out"
              },
              "target": {
                "block": "16e78204-213e-4833-9096-89d735307ec2",
                "port": "i"
              },
              "size": 4
            },
            {
              "source": {
                "block": "16e78204-213e-4833-9096-89d735307ec2",
                "port": "o1"
              },
              "target": {
                "block": "d912538b-1b79-4d87-9a1b-2a960500bad1",
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            {
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                "clock": false
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                  "out": [
                    {
                      "name": "k",
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                    "index": "12",
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                  },
                  {
                    "index": "11",
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                  },
                  {
                    "index": "10",
                    "name": "",
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                  {
                    "index": "9",
                    "name": "",
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                  },
                  {
                    "index": "8",
                    "name": "",
                    "value": ""
                  },
                  {
                    "index": "7",
                    "name": "",
                    "value": ""
                  },
                  {
                    "index": "6",
                    "name": "",
                    "value": ""
                  },
                  {
                    "index": "5",
                    "name": "",
                    "value": ""
                  },
                  {
                    "index": "4",
                    "name": "",
                    "value": ""
                  },
                  {
                    "index": "3",
                    "name": "",
                    "value": ""
                  },
                  {
                    "index": "2",
                    "name": "",
                    "value": ""
                  },
                  {
                    "index": "1",
                    "name": "",
                    "value": ""
                  },
                  {
                    "index": "0",
                    "name": "",
                    "value": ""
                  }
                ],
                "virtual": true
              },
              "position": {
                "x": 2296,
                "y": 880
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            },
            {
              "id": "250adedc-83de-4325-91ac-06a8b219fea6",
              "type": "basic.outputLabel",
              "data": {
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                "name": "cpuregs_wrdata",
                "range": "[31:0]",
                "size": 32
              },
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                "y": 944
              }
            },
            {
              "id": "1eb45aca-79e6-436d-8616-277b14ac264a",
              "type": "basic.info",
              "data": {
                "info": "## ENTRADAS",
                "readonly": true
              },
              "position": {
                "x": -128,
                "y": -16
              },
              "size": {
                "width": 160,
                "height": 32
              }
            },
            {
              "id": "b4834aed-ddc8-4701-b9a2-f21c32e62320",
              "type": "basic.code",
              "data": {
                "code": "reg [31:0] regs [0:31];\n\nalways @(posedge clk)\n\tif (wen) regs[waddr[4:0]] <= wdata;\n\nassign rdata1 = regs[raddr1[4:0]];\nassign rdata2 = regs[raddr2[4:0]];",
                "params": [],
                "ports": {
                  "in": [
                    {
                      "name": "clk"
                    },
                    {
                      "name": "wen"
                    },
                    {
                      "name": "waddr",
                      "range": "[5:0]",
                      "size": 6
                    },
                    {
                      "name": "raddr1",
                      "range": "[5:0]",
                      "size": 6
                    },
                    {
                      "name": "raddr2",
                      "range": "[5:0]",
                      "size": 6
                    },
                    {
                      "name": "wdata",
                      "range": "[31:0]",
                      "size": 32
                    }
                  ],
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                "code": "`define PICORV32_REGS picosoc_regs\n\n\nparameter integer MEM_WORDS = 256;\n\n`define PICORV32_V\n\nparameter [ 0:0] ENABLE_COUNTERS = 1;\nparameter [ 0:0] ENABLE_COUNTERS64 = 1;\nparameter [ 0:0] ENABLE_REGS_16_31 = 1;\nparameter [ 0:0] ENABLE_REGS_DUALPORT = 1;\nparameter [ 0:0] LATCHED_MEM_RDATA = 0;\nparameter [ 0:0] TWO_STAGE_SHIFT = 1;\nparameter [ 0:0] BARREL_SHIFTER = 1;\nparameter [ 0:0] TWO_CYCLE_COMPARE = 0;\nparameter [ 0:0] TWO_CYCLE_ALU = 0;\nparameter [ 0:0] COMPRESSED_ISA = 0;\nparameter [ 0:0] CATCH_MISALIGN = 1;\nparameter [ 0:0] CATCH_ILLINSN = 1;\nparameter [ 0:0] ENABLE_PCPI = 0;\nparameter [ 0:0] ENABLE_MUL = 0;\nparameter [ 0:0] ENABLE_FAST_MUL = 0;\nparameter [ 0:0] ENABLE_DIV = 0;\nparameter [ 0:0] ENABLE_IRQ = 1;\nparameter [ 0:0] ENABLE_IRQ_QREGS = 0;\nparameter [ 0:0] ENABLE_IRQ_TIMER = 1;\nparameter [ 0:0] ENABLE_TRACE = 0;\nparameter [ 0:0] REGS_INIT_ZERO = 0;\nparameter [31:0] MASKED_IRQ = 32'h 0000_0000;\nparameter [31:0] LATCHED_IRQ = 32'h ffff_ffff;\nparameter [31:0] PROGADDR_RESET = 32'h 0010_0000; // 1 MB into flash,\nparameter [31:0] PROGADDR_IRQ = 32'h 0000_0000;\nparameter [31:0] STACKADDR = (4*MEM_WORDS);       // end of memory\n\n\nreg mem_valid_i;\nassign mem_valid = mem_valid_i;\nreg mem_instr_i;\nassign mem_instr = mem_instr_i;\nreg [31:0] mem_addr_i;\nassign mem_addr = mem_addr_i;\nreg [31:0] mem_wdata_i;\nassign mem_wdata = mem_wdata_i;\nreg [ 3:0] mem_wstrb_i;\nassign mem_wstrb = mem_wstrb_i;\nreg [31:0] eoi;\n\nreg trap;\n\n\n// Pico Co-Processor Interface (PCPI)\nreg        pcpi_valid_i;\nassign pcpi_valid = pcpi_valid_i;\nreg [31:0] pcpi_insn_i;\nassign pcpi_insn = pcpi_insn_i;\nwire     pcpi_wr;\nwire [31:0] pcpi_rd;\nwire pcpi_wait;\nwire pcpi_ready;\n\n\n// Look-Ahead Interface\nwire            mem_la_read;\nwire            mem_la_write;\nwire     [31:0] mem_la_addr;\nreg [31:0] mem_la_wdata;\nreg [ 3:0] mem_la_wstrb;\n\n// Trace Interface\nreg        trace_valid;\nreg [35:0] trace_data;\n\n\tlocalparam integer irq_timer = 0;\n\tlocalparam integer irq_ebreak = 1;\n\tlocalparam integer irq_buserror = 2;\n\n\tlocalparam integer irqregs_offset = ENABLE_REGS_16_31 ? 32 : 16;\n\tlocalparam integer regfile_size = (ENABLE_REGS_16_31 ? 32 : 16) + 4*ENABLE_IRQ*ENABLE_IRQ_QREGS;\n\tlocalparam integer regindex_bits = (ENABLE_REGS_16_31 ? 5 : 4) + ENABLE_IRQ*ENABLE_IRQ_QREGS;\n\n\tlocalparam WITH_PCPI = ENABLE_PCPI || ENABLE_MUL || ENABLE_FAST_MUL || ENABLE_DIV;\n\n\tlocalparam [35:0] TRACE_BRANCH = {4'b 0001, 32'b 0};\n\tlocalparam [35:0] TRACE_ADDR   = {4'b 0010, 32'b 0};\n\tlocalparam [35:0] TRACE_IRQ    = {4'b 1000, 32'b 0};\n\n//-- Añadido para instanciar los registros\nassign cpuregs_wen = resetn && cpuregs_write && latched_rd;\n\n//FORMAL_KEEP:\nreg [63:0] dbg_ascii_instr;\nreg [31:0] dbg_insn_imm;\nreg [4:0] dbg_insn_rs1;\nreg [4:0] dbg_insn_rs2;\nreg [4:0] dbg_insn_rd;\nreg [31:0] dbg_rs1val;\nreg [31:0] dbg_rs2val;\nreg dbg_rs1val_valid;\nreg dbg_rs2val_valid;\nreg [127:0] dbg_ascii_state;\n\n\treg [63:0] count_cycle, count_instr;\n\treg [31:0] reg_pc, reg_next_pc, reg_op1, reg_op2, reg_out;\n\treg [4:0] reg_sh;\n\n\treg [31:0] next_insn_opcode;\n\treg [31:0] dbg_insn_opcode;\n\treg [31:0] dbg_insn_addr;\n\n\twire dbg_mem_valid = mem_valid_i;\n\twire dbg_mem_instr = mem_instr_i;\n\twire dbg_mem_ready = mem_ready;\n\twire [31:0] dbg_mem_addr  = mem_addr_i;\n\twire [31:0] dbg_mem_wdata = mem_wdata_i;\n\twire [ 3:0] dbg_mem_wstrb = mem_wstrb_i;\n\twire [31:0] dbg_mem_rdata = mem_rdata;\n\n\tassign pcpi_rs1 = reg_op1;\n\tassign pcpi_rs2 = reg_op2;\n\n\twire [31:0] next_pc;\n\n\treg irq_delay;\n\treg irq_active;\n\treg [31:0] irq_mask;\n\treg [31:0] irq_pending;\n\treg [31:0] timer;\n\n`ifndef PICORV32_REGS\n\treg [31:0] cpuregs [0:regfile_size-1];\n\n\tinteger i;\n\tinitial begin\n\t\tif (REGS_INIT_ZERO) begin\n\t\t\tfor (i = 0; i < regfile_size; i = i+1)\n\t\t\t\tcpuregs[i] = 0;\n\t\tend\n\tend\n`endif\n\n\ttask empty_statement;\n\t\t// This task is used by the `assert directive in non-formal mode to\n\t\t// avoid empty statement (which are unsupported by plain Verilog syntax).\n\t\tbegin end\n\tendtask\n\n`ifdef DEBUGREGS\n\twire [31:0] dbg_reg_x0  = 0;\n\twire [31:0] dbg_reg_x1  = cpuregs[1];\n\twire [31:0] dbg_reg_x2  = cpuregs[2];\n\twire [31:0] dbg_reg_x3  = cpuregs[3];\n\twire [31:0] dbg_reg_x4  = cpuregs[4];\n\twire [31:0] dbg_reg_x5  = cpuregs[5];\n\twire [31:0] dbg_reg_x6  = cpuregs[6];\n\twire [31:0] dbg_reg_x7  = cpuregs[7];\n\twire [31:0] dbg_reg_x8  = cpuregs[8];\n\twire [31:0] dbg_reg_x9  = cpuregs[9];\n\twire [31:0] dbg_reg_x10 = cpuregs[10];\n\twire [31:0] dbg_reg_x11 = cpuregs[11];\n\twire [31:0] dbg_reg_x12 = cpuregs[12];\n\twire [31:0] dbg_reg_x13 = cpuregs[13];\n\twire [31:0] dbg_reg_x14 = cpuregs[14];\n\twire [31:0] dbg_reg_x15 = cpuregs[15];\n\twire [31:0] dbg_reg_x16 = cpuregs[16];\n\twire [31:0] dbg_reg_x17 = cpuregs[17];\n\twire [31:0] dbg_reg_x18 = cpuregs[18];\n\twire [31:0] dbg_reg_x19 = cpuregs[19];\n\twire [31:0] dbg_reg_x20 = cpuregs[20];\n\twire [31:0] dbg_reg_x21 = cpuregs[21];\n\twire [31:0] dbg_reg_x22 = cpuregs[22];\n\twire [31:0] dbg_reg_x23 = cpuregs[23];\n\twire [31:0] dbg_reg_x24 = cpuregs[24];\n\twire [31:0] dbg_reg_x25 = cpuregs[25];\n\twire [31:0] dbg_reg_x26 = cpuregs[26];\n\twire [31:0] dbg_reg_x27 = cpuregs[27];\n\twire [31:0] dbg_reg_x28 = cpuregs[28];\n\twire [31:0] dbg_reg_x29 = cpuregs[29];\n\twire [31:0] dbg_reg_x30 = cpuregs[30];\n\twire [31:0] dbg_reg_x31 = cpuregs[31];\n`endif\n\n\t// Internal PCPI Cores\n\n\treg        pcpi_int_wr;\n\treg [31:0] pcpi_int_rd;\n\treg        pcpi_int_wait;\n\treg        pcpi_int_ready;\n\n\tgenerate if (ENABLE_FAST_MUL) begin\n\t\tpicorv32_pcpi_fast_mul pcpi_mul (\n\t\t\t.clk       (clk            ),\n\t\t\t.resetn    (resetn         ),\n\t\t\t.pcpi_valid(pcpi_valid_i     ),\n\t\t\t.pcpi_insn (pcpi_insn_i      ),\n\t\t\t.pcpi_rs1  (pcpi_rs1       ),\n\t\t\t.pcpi_rs2  (pcpi_rs2       ),\n\t\t\t.pcpi_wr   (pcpi_mul_wr    ),\n\t\t\t.pcpi_rd   (pcpi_mul_rd    ),\n\t\t\t.pcpi_wait (pcpi_mul_wait  ),\n\t\t\t.pcpi_ready(pcpi_mul_ready )\n\t\t);\n\tend else if (ENABLE_MUL) begin\n\t\t\n\tend else begin\n\t\tassign pcpi_mul_wr = 0;\n\t\tassign pcpi_mul_rd = 32'bx;\n\t\tassign pcpi_mul_wait = 0;\n\t\tassign pcpi_mul_ready = 0;\n\tend endgenerate\n\n\tgenerate if (ENABLE_DIV) begin\n\t\t\n\tend else begin\n\t\tassign pcpi_div_wr = 0;\n\t\tassign pcpi_div_rd = 32'bx;\n\t\tassign pcpi_div_wait = 0;\n\t\tassign pcpi_div_ready = 0;\n\tend endgenerate\n\n\talways @* begin\n\t\tpcpi_int_wr = 0;\n\t\tpcpi_int_rd = 32'bx;\n\t\tpcpi_int_wait  = |{ENABLE_PCPI && pcpi_wait,  (ENABLE_MUL || ENABLE_FAST_MUL) && pcpi_mul_wait,  ENABLE_DIV && pcpi_div_wait};\n\t\tpcpi_int_ready = |{ENABLE_PCPI && pcpi_ready, (ENABLE_MUL || ENABLE_FAST_MUL) && pcpi_mul_ready, ENABLE_DIV && pcpi_div_ready};\n\n\t\t(* parallel_case *)\n\t\tcase (1'b1)\n\t\t\tENABLE_PCPI && pcpi_ready: begin\n\t\t\t\tpcpi_int_wr = ENABLE_PCPI ? pcpi_wr : 0;\n\t\t\t\tpcpi_int_rd = ENABLE_PCPI ? pcpi_rd : 0;\n\t\t\tend\n\t\t\t(ENABLE_MUL || ENABLE_FAST_MUL) && pcpi_mul_ready: begin\n\t\t\t\tpcpi_int_wr = pcpi_mul_wr;\n\t\t\t\tpcpi_int_rd = pcpi_mul_rd;\n\t\t\tend\n\t\t\tENABLE_DIV && pcpi_div_ready: begin\n\t\t\t\tpcpi_int_wr = pcpi_div_wr;\n\t\t\t\tpcpi_int_rd = pcpi_div_rd;\n\t\t\tend\n\t\tendcase\n\tend\n\n\n\t// Memory Interface\n\n\treg [1:0] mem_state;\n\treg [1:0] mem_wordsize;\n\treg [31:0] mem_rdata_word;\n\treg [31:0] mem_rdata_q;\n\treg mem_do_prefetch;\n\treg mem_do_rinst;\n\treg mem_do_rdata;\n\treg mem_do_wdata;\n\n\twire mem_xfer;\n\treg mem_la_secondword, mem_la_firstword_reg, last_mem_valid;\n\twire mem_la_firstword = COMPRESSED_ISA && (mem_do_prefetch || mem_do_rinst) && next_pc[1] && !mem_la_secondword;\n\twire mem_la_firstword_xfer = COMPRESSED_ISA && mem_xfer && (!last_mem_valid ? mem_la_firstword : mem_la_firstword_reg);\n\n\treg prefetched_high_word;\n\treg clear_prefetched_high_word;\n\treg [15:0] mem_16bit_buffer;\n\n\twire [31:0] mem_rdata_latched_noshuffle;\n\twire [31:0] mem_rdata_latched;\n\n\twire mem_la_use_prefetched_high_word = COMPRESSED_ISA && mem_la_firstword && prefetched_high_word && !clear_prefetched_high_word;\n\tassign mem_xfer = (mem_valid_i && mem_ready) || (mem_la_use_prefetched_high_word && mem_do_rinst);\n\n\twire mem_busy = |{mem_do_prefetch, mem_do_rinst, mem_do_rdata, mem_do_wdata};\n\twire mem_done = resetn && ((mem_xfer && |mem_state && (mem_do_rinst || mem_do_rdata || mem_do_wdata)) || (&mem_state && mem_do_rinst)) &&\n\t\t\t(!mem_la_firstword || (~&mem_rdata_latched[1:0] && mem_xfer));\n\n\tassign mem_la_write = resetn && !mem_state && mem_do_wdata;\n\tassign mem_la_read = resetn && ((!mem_la_use_prefetched_high_word && !mem_state && (mem_do_rinst || mem_do_prefetch || mem_do_rdata)) ||\n\t\t\t(COMPRESSED_ISA && mem_xfer && (!last_mem_valid ? mem_la_firstword : mem_la_firstword_reg) && !mem_la_secondword && &mem_rdata_latched[1:0]));\n\tassign mem_la_addr = (mem_do_prefetch || mem_do_rinst) ? {next_pc[31:2] + mem_la_firstword_xfer, 2'b00} : {reg_op1[31:2], 2'b00};\n\n\tassign mem_rdata_latched_noshuffle = (mem_xfer || LATCHED_MEM_RDATA) ? mem_rdata : mem_rdata_q;\n\n\tassign mem_rdata_latched = COMPRESSED_ISA && mem_la_use_prefetched_high_word ? {16'bx, mem_16bit_buffer} :\n\t\t\tCOMPRESSED_ISA && mem_la_secondword ? {mem_rdata_latched_noshuffle[15:0], mem_16bit_buffer} :\n\t\t\tCOMPRESSED_ISA && mem_la_firstword ? {16'bx, mem_rdata_latched_noshuffle[31:16]} : mem_rdata_latched_noshuffle;\n\n\talways @(posedge clk) begin\n\t\tif (!resetn) begin\n\t\t\tmem_la_firstword_reg <= 0;\n\t\t\tlast_mem_valid <= 0;\n\t\tend else begin\n\t\t\tif (!last_mem_valid)\n\t\t\t\tmem_la_firstword_reg <= mem_la_firstword;\n\t\t\tlast_mem_valid <= mem_valid_i && !mem_ready;\n\t\tend\n\tend\n\n\talways @* begin\n\t\t(* full_case *)\n\t\tcase (mem_wordsize)\n\t\t\t0: begin\n\t\t\t\tmem_la_wdata = reg_op2;\n\t\t\t\tmem_la_wstrb = 4'b1111;\n\t\t\t\tmem_rdata_word = mem_rdata;\n\t\t\tend\n\t\t\t1: begin\n\t\t\t\tmem_la_wdata = {2{reg_op2[15:0]}};\n\t\t\t\tmem_la_wstrb = reg_op1[1] ? 4'b1100 : 4'b0011;\n\t\t\t\tcase (reg_op1[1])\n\t\t\t\t\t1'b0: mem_rdata_word = {16'b0, mem_rdata[15: 0]};\n\t\t\t\t\t1'b1: mem_rdata_word = {16'b0, mem_rdata[31:16]};\n\t\t\t\tendcase\n\t\t\tend\n\t\t\t2: begin\n\t\t\t\tmem_la_wdata = {4{reg_op2[7:0]}};\n\t\t\t\tmem_la_wstrb = 4'b0001 << reg_op1[1:0];\n\t\t\t\tcase (reg_op1[1:0])\n\t\t\t\t\t2'b00: mem_rdata_word = {24'b0, mem_rdata[ 7: 0]};\n\t\t\t\t\t2'b01: mem_rdata_word = {24'b0, mem_rdata[15: 8]};\n\t\t\t\t\t2'b10: mem_rdata_word = {24'b0, mem_rdata[23:16]};\n\t\t\t\t\t2'b11: mem_rdata_word = {24'b0, mem_rdata[31:24]};\n\t\t\t\tendcase\n\t\t\tend\n\t\tendcase\n\tend\n\n\talways @(posedge clk) begin\n\t\tif (mem_xfer) begin\n\t\t\tmem_rdata_q <= COMPRESSED_ISA ? mem_rdata_latched : mem_rdata;\n\t\t\tnext_insn_opcode <= COMPRESSED_ISA ? mem_rdata_latched : mem_rdata;\n\t\tend\n\n\t\tif (COMPRESSED_ISA && mem_done && (mem_do_prefetch || mem_do_rinst)) begin\n\t\t\tcase (mem_rdata_latched[1:0])\n\t\t\t\t2'b00: begin // Quadrant 0\n\t\t\t\t\tcase (mem_rdata_latched[15:13])\n\t\t\t\t\t\t3'b000: begin // C.ADDI4SPN\n\t\t\t\t\t\t\tmem_rdata_q[14:12] <= 3'b000;\n\t\t\t\t\t\t\tmem_rdata_q[31:20] <= {2'b0, mem_rdata_latched[10:7], mem_rdata_latched[12:11], mem_rdata_latched[5], mem_rdata_latched[6], 2'b00};\n\t\t\t\t\t\tend\n\t\t\t\t\t\t3'b010: begin // C.LW\n\t\t\t\t\t\t\tmem_rdata_q[31:20] <= {5'b0, mem_rdata_latched[5], mem_rdata_latched[12:10], mem_rdata_latched[6], 2'b00};\n\t\t\t\t\t\t\tmem_rdata_q[14:12] <= 3'b 010;\n\t\t\t\t\t\tend\n\t\t\t\t\t\t3'b 110: begin // C.SW\n\t\t\t\t\t\t\t{mem_rdata_q[31:25], mem_rdata_q[11:7]} <= {5'b0, mem_rdata_latched[5], mem_rdata_latched[12:10], mem_rdata_latched[6], 2'b00};\n\t\t\t\t\t\t\tmem_rdata_q[14:12] <= 3'b 010;\n\t\t\t\t\t\tend\n\t\t\t\t\tendcase\n\t\t\t\tend\n\t\t\t\t2'b01: begin // Quadrant 1\n\t\t\t\t\tcase (mem_rdata_latched[15:13])\n\t\t\t\t\t\t3'b 000: begin // C.ADDI\n\t\t\t\t\t\t\tmem_rdata_q[14:12] <= 3'b000;\n\t\t\t\t\t\t\tmem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]});\n\t\t\t\t\t\tend\n\t\t\t\t\t\t3'b 010: begin // C.LI\n\t\t\t\t\t\t\tmem_rdata_q[14:12] <= 3'b000;\n\t\t\t\t\t\t\tmem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]});\n\t\t\t\t\t\tend\n\t\t\t\t\t\t3'b 011: begin\n\t\t\t\t\t\t\tif (mem_rdata_latched[11:7] == 2) begin // C.ADDI16SP\n\t\t\t\t\t\t\t\tmem_rdata_q[14:12] <= 3'b000;\n\t\t\t\t\t\t\t\tmem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[4:3],\n\t\t\t\t\t\t\t\t\t\tmem_rdata_latched[5], mem_rdata_latched[2], mem_rdata_latched[6], 4'b 0000});\n\t\t\t\t\t\t\tend else begin // C.LUI\n\t\t\t\t\t\t\t\tmem_rdata_q[31:12] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]});\n\t\t\t\t\t\t\tend\n\t\t\t\t\t\tend\n\t\t\t\t\t\t3'b100: begin\n\t\t\t\t\t\t\tif (mem_rdata_latched[11:10] == 2'b00) begin // C.SRLI\n\t\t\t\t\t\t\t\tmem_rdata_q[31:25] <= 7'b0000000;\n\t\t\t\t\t\t\t\tmem_rdata_q[14:12] <= 3'b 101;\n\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\tif (mem_rdata_latched[11:10] == 2'b01) begin // C.SRAI\n\t\t\t\t\t\t\t\tmem_rdata_q[31:25] <= 7'b0100000;\n\t\t\t\t\t\t\t\tmem_rdata_q[14:12] <= 3'b 101;\n\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\tif (mem_rdata_latched[11:10] == 2'b10) begin // C.ANDI\n\t\t\t\t\t\t\t\tmem_rdata_q[14:12] <= 3'b111;\n\t\t\t\t\t\t\t\tmem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]});\n\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\tif (mem_rdata_latched[12:10] == 3'b011) begin // C.SUB, C.XOR, C.OR, C.AND\n\t\t\t\t\t\t\t\tif (mem_rdata_latched[6:5] == 2'b00) mem_rdata_q[14:12] <= 3'b000;\n\t\t\t\t\t\t\t\tif (mem_rdata_latched[6:5] == 2'b01) mem_rdata_q[14:12] <= 3'b100;\n\t\t\t\t\t\t\t\tif (mem_rdata_latched[6:5] == 2'b10) mem_rdata_q[14:12] <= 3'b110;\n\t\t\t\t\t\t\t\tif (mem_rdata_latched[6:5] == 2'b11) mem_rdata_q[14:12] <= 3'b111;\n\t\t\t\t\t\t\t\tmem_rdata_q[31:25] <= mem_rdata_latched[6:5] == 2'b00 ? 7'b0100000 : 7'b0000000;\n\t\t\t\t\t\t\tend\n\t\t\t\t\t\tend\n\t\t\t\t\t\t3'b 110: begin // C.BEQZ\n\t\t\t\t\t\t\tmem_rdata_q[14:12] <= 3'b000;\n\t\t\t\t\t\t\t{ mem_rdata_q[31], mem_rdata_q[7], mem_rdata_q[30:25], mem_rdata_q[11:8] } <=\n\t\t\t\t\t\t\t\t\t$signed({mem_rdata_latched[12], mem_rdata_latched[6:5], mem_rdata_latched[2],\n\t\t\t\t\t\t\t\t\t\t\tmem_rdata_latched[11:10], mem_rdata_latched[4:3]});\n\t\t\t\t\t\tend\n\t\t\t\t\t\t3'b 111: begin // C.BNEZ\n\t\t\t\t\t\t\tmem_rdata_q[14:12] <= 3'b001;\n\t\t\t\t\t\t\t{ mem_rdata_q[31], mem_rdata_q[7], mem_rdata_q[30:25], mem_rdata_q[11:8] } <=\n\t\t\t\t\t\t\t\t\t$signed({mem_rdata_latched[12], mem_rdata_latched[6:5], mem_rdata_latched[2],\n\t\t\t\t\t\t\t\t\t\t\tmem_rdata_latched[11:10], mem_rdata_latched[4:3]});\n\t\t\t\t\t\tend\n\t\t\t\t\tendcase\n\t\t\t\tend\n\t\t\t\t2'b10: begin // Quadrant 2\n\t\t\t\t\tcase (mem_rdata_latched[15:13])\n\t\t\t\t\t\t3'b000: begin // C.SLLI\n\t\t\t\t\t\t\tmem_rdata_q[31:25] <= 7'b0000000;\n\t\t\t\t\t\t\tmem_rdata_q[14:12] <= 3'b 001;\n\t\t\t\t\t\tend\n\t\t\t\t\t\t3'b010: begin // C.LWSP\n\t\t\t\t\t\t\tmem_rdata_q[31:20] <= {4'b0, mem_rdata_latched[3:2], mem_rdata_latched[12], mem_rdata_latched[6:4], 2'b00};\n\t\t\t\t\t\t\tmem_rdata_q[14:12] <= 3'b 010;\n\t\t\t\t\t\tend\n\t\t\t\t\t\t3'b100: begin\n\t\t\t\t\t\t\tif (mem_rdata_latched[12] == 0 && mem_rdata_latched[6:2] == 0) begin // C.JR\n\t\t\t\t\t\t\t\tmem_rdata_q[14:12] <= 3'b000;\n\t\t\t\t\t\t\t\tmem_rdata_q[31:20] <= 12'b0;\n\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\tif (mem_rdata_latched[12] == 0 && mem_rdata_latched[6:2] != 0) begin // C.MV\n\t\t\t\t\t\t\t\tmem_rdata_q[14:12] <= 3'b000;\n\t\t\t\t\t\t\t\tmem_rdata_q[31:25] <= 7'b0000000;\n\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\tif (mem_rdata_latched[12] != 0 && mem_rdata_latched[11:7] != 0 && mem_rdata_latched[6:2] == 0) begin // C.JALR\n\t\t\t\t\t\t\t\tmem_rdata_q[14:12] <= 3'b000;\n\t\t\t\t\t\t\t\tmem_rdata_q[31:20] <= 12'b0;\n\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\tif (mem_rdata_latched[12] != 0 && mem_rdata_latched[6:2] != 0) begin // C.ADD\n\t\t\t\t\t\t\t\tmem_rdata_q[14:12] <= 3'b000;\n\t\t\t\t\t\t\t\tmem_rdata_q[31:25] <= 7'b0000000;\n\t\t\t\t\t\t\tend\n\t\t\t\t\t\tend\n\t\t\t\t\t\t3'b110: begin // C.SWSP\n\t\t\t\t\t\t\t{mem_rdata_q[31:25], mem_rdata_q[11:7]} <= {4'b0, mem_rdata_latched[8:7], mem_rdata_latched[12:9], 2'b00};\n\t\t\t\t\t\t\tmem_rdata_q[14:12] <= 3'b 010;\n\t\t\t\t\t\tend\n\t\t\t\t\tendcase\n\t\t\t\tend\n\t\t\tendcase\n\t\tend\n\tend\n/*\n\talways @(posedge clk) begin\n\t\tif (resetn && !trap) begin\n\t\t\tif (mem_do_prefetch || mem_do_rinst || mem_do_rdata)\n\t\t\t\t//`assert(!mem_do_wdata);\n\n\t\t\tif (mem_do_prefetch || mem_do_rinst)\n\t\t\t\t//`assert(!mem_do_rdata);\n\n\t\t\tif (mem_do_rdata)\n\t\t\t\t//`assert(!mem_do_prefetch && !mem_do_rinst);\n\n\t\t\tif (mem_do_wdata)\n\t\t\t\t//`assert(!(mem_do_prefetch || mem_do_rinst || mem_do_rdata));\n\n\t\t\tif (mem_state == 2 || mem_state == 3)\n\t\t\t\t//`assert(mem_valid || mem_do_prefetch);\n\t\tend\n\tend*/\n\n\talways @(posedge clk) begin\n\t\tif (!resetn || trap) begin\n\t\t\tif (!resetn)\n\t\t\t\tmem_state <= 0;\n\t\t\tif (!resetn || mem_ready)\n\t\t\t\tmem_valid_i <= 0;\n\t\t\tmem_la_secondword <= 0;\n\t\t\tprefetched_high_word <= 0;\n\t\tend else begin\n\t\t\tif (mem_la_read || mem_la_write) begin\n\t\t\t\tmem_addr_i <= mem_la_addr;\n\t\t\t\tmem_wstrb_i <= mem_la_wstrb & {4{mem_la_write}};\n\t\t\tend\n\t\t\tif (mem_la_write) begin\n\t\t\t\tmem_wdata_i <= mem_la_wdata;\n\t\t\tend\n\t\t\tcase (mem_state)\n\t\t\t\t0: begin\n\t\t\t\t\tif (mem_do_prefetch || mem_do_rinst || mem_do_rdata) begin\n\t\t\t\t\t\tmem_valid_i <= !mem_la_use_prefetched_high_word;\n\t\t\t\t\t\tmem_instr_i <= mem_do_prefetch || mem_do_rinst;\n\t\t\t\t\t\tmem_wstrb_i <= 0;\n\t\t\t\t\t\tmem_state <= 1;\n\t\t\t\t\tend\n\t\t\t\t\tif (mem_do_wdata) begin\n\t\t\t\t\t\tmem_valid_i <= 1;\n\t\t\t\t\t\tmem_instr_i <= 0;\n\t\t\t\t\t\tmem_state <= 2;\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\t\t1: begin\n\t\t\t\t\t//`assert(mem_wstrb == 0);\n\t\t\t\t\t//`assert(mem_do_prefetch || mem_do_rinst || mem_do_rdata);\n\t\t\t\t\t//`assert(mem_valid == !mem_la_use_prefetched_high_word);\n\t\t\t\t\t//`assert(mem_instr == (mem_do_prefetch || mem_do_rinst));\n\t\t\t\t\tif (mem_xfer) begin\n\t\t\t\t\t\tif (COMPRESSED_ISA && mem_la_read) begin\n\t\t\t\t\t\t\tmem_valid_i <= 1;\n\t\t\t\t\t\t\tmem_la_secondword <= 1;\n\t\t\t\t\t\t\tif (!mem_la_use_prefetched_high_word)\n\t\t\t\t\t\t\t\tmem_16bit_buffer <= mem_rdata[31:16];\n\t\t\t\t\t\tend else begin\n\t\t\t\t\t\t\tmem_valid_i <= 0;\n\t\t\t\t\t\t\tmem_la_secondword <= 0;\n\t\t\t\t\t\t\tif (COMPRESSED_ISA && !mem_do_rdata) begin\n\t\t\t\t\t\t\t\tif (~&mem_rdata[1:0] || mem_la_secondword) begin\n\t\t\t\t\t\t\t\t\tmem_16bit_buffer <= mem_rdata[31:16];\n\t\t\t\t\t\t\t\t\tprefetched_high_word <= 1;\n\t\t\t\t\t\t\t\tend else begin\n\t\t\t\t\t\t\t\t\tprefetched_high_word <= 0;\n\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\tmem_state <= mem_do_rinst || mem_do_rdata ? 0 : 3;\n\t\t\t\t\t\tend\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\t\t2: begin\n\t\t\t\t\t//`assert(mem_wstrb != 0);\n\t\t\t\t\t//`assert(mem_do_wdata);\n\t\t\t\t\tif (mem_xfer) begin\n\t\t\t\t\t\tmem_valid_i <= 0;\n\t\t\t\t\t\tmem_state <= 0;\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\t\t3: begin\n\t\t\t\t\t//`assert(mem_wstrb == 0);\n\t\t\t\t\t//`assert(mem_do_prefetch);\n\t\t\t\t\tif (mem_do_rinst) begin\n\t\t\t\t\t\tmem_state <= 0;\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\tendcase\n\t\tend\n\n\t\tif (clear_prefetched_high_word)\n\t\t\tprefetched_high_word <= 0;\n\tend\n\n\n\t// Instruction Decoder\n\n\treg instr_lui, instr_auipc, instr_jal, instr_jalr;\n\treg instr_beq, instr_bne, instr_blt, instr_bge, instr_bltu, instr_bgeu;\n\treg instr_lb, instr_lh, instr_lw, instr_lbu, instr_lhu, instr_sb, instr_sh, instr_sw;\n\treg instr_addi, instr_slti, instr_sltiu, instr_xori, instr_ori, instr_andi, instr_slli, instr_srli, instr_srai;\n\treg instr_add, instr_sub, instr_sll, instr_slt, instr_sltu, instr_xor, instr_srl, instr_sra, instr_or, instr_and;\n\treg instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh, instr_ecall_ebreak;\n\treg instr_getq, instr_setq, instr_retirq, instr_maskirq, instr_waitirq, instr_timer;\n\twire instr_trap;\n\n\treg [regindex_bits-1:0] decoded_rd, decoded_rs1, decoded_rs2;\n\treg [31:0] decoded_imm, decoded_imm_uj;\n\treg decoder_trigger;\n\treg decoder_trigger_q;\n\treg decoder_pseudo_trigger;\n\treg decoder_pseudo_trigger_q;\n\treg compressed_instr;\n\n\treg is_lui_auipc_jal;\n\treg is_lb_lh_lw_lbu_lhu;\n\treg is_slli_srli_srai;\n\treg is_jalr_addi_slti_sltiu_xori_ori_andi;\n\treg is_sb_sh_sw;\n\treg is_sll_srl_sra;\n\treg is_lui_auipc_jal_jalr_addi_add_sub;\n\treg is_slti_blt_slt;\n\treg is_sltiu_bltu_sltu;\n\treg is_beq_bne_blt_bge_bltu_bgeu;\n\treg is_lbu_lhu_lw;\n\treg is_alu_reg_imm;\n\treg is_alu_reg_reg;\n\treg is_compare;\n\n\tassign instr_trap = (CATCH_ILLINSN || WITH_PCPI) && !{instr_lui, instr_auipc, instr_jal, instr_jalr,\n\t\t\tinstr_beq, instr_bne, instr_blt, instr_bge, instr_bltu, instr_bgeu,\n\t\t\tinstr_lb, instr_lh, instr_lw, instr_lbu, instr_lhu, instr_sb, instr_sh, instr_sw,\n\t\t\tinstr_addi, instr_slti, instr_sltiu, instr_xori, instr_ori, instr_andi, instr_slli, instr_srli, instr_srai,\n\t\t\tinstr_add, instr_sub, instr_sll, instr_slt, instr_sltu, instr_xor, instr_srl, instr_sra, instr_or, instr_and,\n\t\t\tinstr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh,\n\t\t\tinstr_getq, instr_setq, instr_retirq, instr_maskirq, instr_waitirq, instr_timer};\n\n\twire is_rdcycle_rdcycleh_rdinstr_rdinstrh;\n\tassign is_rdcycle_rdcycleh_rdinstr_rdinstrh = |{instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh};\n\n\treg [63:0] new_ascii_instr;\n\t/*\n\t`FORMAL_KEEP reg [63:0] dbg_ascii_instr;\n\t`FORMAL_KEEP reg [31:0] dbg_insn_imm;\n\t`FORMAL_KEEP reg [4:0] dbg_insn_rs1;\n\t`FORMAL_KEEP reg [4:0] dbg_insn_rs2;\n\t`FORMAL_KEEP reg [4:0] dbg_insn_rd;\n\t`FORMAL_KEEP reg [31:0] dbg_rs1val;\n\t`FORMAL_KEEP reg [31:0] dbg_rs2val;\n\t`FORMAL_KEEP reg dbg_rs1val_valid;\n\t`FORMAL_KEEP reg dbg_rs2val_valid;*/\n\n\talways @* begin\n\t\tnew_ascii_instr = \"\";\n\n\t\tif (instr_lui)      new_ascii_instr = \"lui\";\n\t\tif (instr_auipc)    new_ascii_instr = \"auipc\";\n\t\tif (instr_jal)      new_ascii_instr = \"jal\";\n\t\tif (instr_jalr)     new_ascii_instr = \"jalr\";\n\n\t\tif (instr_beq)      new_ascii_instr = \"beq\";\n\t\tif (instr_bne)      new_ascii_instr = \"bne\";\n\t\tif (instr_blt)      new_ascii_instr = \"blt\";\n\t\tif (instr_bge)      new_ascii_instr = \"bge\";\n\t\tif (instr_bltu)     new_ascii_instr = \"bltu\";\n\t\tif (instr_bgeu)     new_ascii_instr = \"bgeu\";\n\n\t\tif (instr_lb)       new_ascii_instr = \"lb\";\n\t\tif (instr_lh)       new_ascii_instr = \"lh\";\n\t\tif (instr_lw)       new_ascii_instr = \"lw\";\n\t\tif (instr_lbu)      new_ascii_instr = \"lbu\";\n\t\tif (instr_lhu)      new_ascii_instr = \"lhu\";\n\t\tif (instr_sb)       new_ascii_instr = \"sb\";\n\t\tif (instr_sh)       new_ascii_instr = \"sh\";\n\t\tif (instr_sw)       new_ascii_instr = \"sw\";\n\n\t\tif (instr_addi)     new_ascii_instr = \"addi\";\n\t\tif (instr_slti)     new_ascii_instr = \"slti\";\n\t\tif (instr_sltiu)    new_ascii_instr = \"sltiu\";\n\t\tif (instr_xori)     new_ascii_instr = \"xori\";\n\t\tif (instr_ori)      new_ascii_instr = \"ori\";\n\t\tif (instr_andi)     new_ascii_instr = \"andi\";\n\t\tif (instr_slli)     new_ascii_instr = \"slli\";\n\t\tif (instr_srli)     new_ascii_instr = \"srli\";\n\t\tif (instr_srai)     new_ascii_instr = \"srai\";\n\n\t\tif (instr_add)      new_ascii_instr = \"add\";\n\t\tif (instr_sub)      new_ascii_instr = \"sub\";\n\t\tif (instr_sll)      new_ascii_instr = \"sll\";\n\t\tif (instr_slt)      new_ascii_instr = \"slt\";\n\t\tif (instr_sltu)     new_ascii_instr = \"sltu\";\n\t\tif (instr_xor)      new_ascii_instr = \"xor\";\n\t\tif (instr_srl)      new_ascii_instr = \"srl\";\n\t\tif (instr_sra)      new_ascii_instr = \"sra\";\n\t\tif (instr_or)       new_ascii_instr = \"or\";\n\t\tif (instr_and)      new_ascii_instr = \"and\";\n\n\t\tif (instr_rdcycle)  new_ascii_instr = \"rdcycle\";\n\t\tif (instr_rdcycleh) new_ascii_instr = \"rdcycleh\";\n\t\tif (instr_rdinstr)  new_ascii_instr = \"rdinstr\";\n\t\tif (instr_rdinstrh) new_ascii_instr = \"rdinstrh\";\n\n\t\tif (instr_getq)     new_ascii_instr = \"getq\";\n\t\tif (instr_setq)     new_ascii_instr = \"setq\";\n\t\tif (instr_retirq)   new_ascii_instr = \"retirq\";\n\t\tif (instr_maskirq)  new_ascii_instr = \"maskirq\";\n\t\tif (instr_waitirq)  new_ascii_instr = \"waitirq\";\n\t\tif (instr_timer)    new_ascii_instr = \"timer\";\n\tend\n\n\treg [63:0] q_ascii_instr;\n\treg [31:0] q_insn_imm;\n\treg [31:0] q_insn_opcode;\n\treg [4:0] q_insn_rs1;\n\treg [4:0] q_insn_rs2;\n\treg [4:0] q_insn_rd;\n\treg dbg_next;\n\n\twire launch_next_insn;\n\treg dbg_valid_insn;\n\n\treg [63:0] cached_ascii_instr;\n\treg [31:0] cached_insn_imm;\n\treg [31:0] cached_insn_opcode;\n\treg [4:0] cached_insn_rs1;\n\treg [4:0] cached_insn_rs2;\n\treg [4:0] cached_insn_rd;\n\n\talways @(posedge clk) begin\n\t\tq_ascii_instr <= dbg_ascii_instr;\n\t\tq_insn_imm <= dbg_insn_imm;\n\t\tq_insn_opcode <= dbg_insn_opcode;\n\t\tq_insn_rs1 <= dbg_insn_rs1;\n\t\tq_insn_rs2 <= dbg_insn_rs2;\n\t\tq_insn_rd <= dbg_insn_rd;\n\t\tdbg_next <= launch_next_insn;\n\n\t\tif (!resetn || trap)\n\t\t\tdbg_valid_insn <= 0;\n\t\telse if (launch_next_insn)\n\t\t\tdbg_valid_insn <= 1;\n\n\t\tif (decoder_trigger_q) begin\n\t\t\tcached_ascii_instr <= new_ascii_instr;\n\t\t\tcached_insn_imm <= decoded_imm;\n\t\t\tif (&next_insn_opcode[1:0])\n\t\t\t\tcached_insn_opcode <= next_insn_opcode;\n\t\t\telse\n\t\t\t\tcached_insn_opcode <= {16'b0, next_insn_opcode[15:0]};\n\t\t\tcached_insn_rs1 <= decoded_rs1;\n\t\t\tcached_insn_rs2 <= decoded_rs2;\n\t\t\tcached_insn_rd <= decoded_rd;\n\t\tend\n\n\t\tif (launch_next_insn) begin\n\t\t\tdbg_insn_addr <= next_pc;\n\t\tend\n\tend\n\n\talways @* begin\n\t\tdbg_ascii_instr = q_ascii_instr;\n\t\tdbg_insn_imm = q_insn_imm;\n\t\tdbg_insn_opcode = q_insn_opcode;\n\t\tdbg_insn_rs1 = q_insn_rs1;\n\t\tdbg_insn_rs2 = q_insn_rs2;\n\t\tdbg_insn_rd = q_insn_rd;\n\n\t\tif (dbg_next) begin\n\t\t\tif (decoder_pseudo_trigger_q) begin\n\t\t\t\tdbg_ascii_instr = cached_ascii_instr;\n\t\t\t\tdbg_insn_imm = cached_insn_imm;\n\t\t\t\tdbg_insn_opcode = cached_insn_opcode;\n\t\t\t\tdbg_insn_rs1 = cached_insn_rs1;\n\t\t\t\tdbg_insn_rs2 = cached_insn_rs2;\n\t\t\t\tdbg_insn_rd = cached_insn_rd;\n\t\t\tend else begin\n\t\t\t\tdbg_ascii_instr = new_ascii_instr;\n\t\t\t\tif (&next_insn_opcode[1:0])\n\t\t\t\t\tdbg_insn_opcode = next_insn_opcode;\n\t\t\t\telse\n\t\t\t\t\tdbg_insn_opcode = {16'b0, next_insn_opcode[15:0]};\n\t\t\t\tdbg_insn_imm = decoded_imm;\n\t\t\t\tdbg_insn_rs1 = decoded_rs1;\n\t\t\t\tdbg_insn_rs2 = decoded_rs2;\n\t\t\t\tdbg_insn_rd = decoded_rd;\n\t\t\tend\n\t\tend\n\tend\n\n`ifdef DEBUGASM\n\talways @(posedge clk) begin\n\t\tif (dbg_next) begin\n\t\t\t$display(\"debugasm %x %x %s\", dbg_insn_addr, dbg_insn_opcode, dbg_ascii_instr ? dbg_ascii_instr : \"*\");\n\t\tend\n\tend\n`endif\n\n`ifdef DEBUG\n\talways @(posedge clk) begin\n\t\tif (dbg_next) begin\n\t\t\tif (&dbg_insn_opcode[1:0])\n\t\t\t\t$display(\"DECODE: 0x%08x 0x%08x %-0s\", dbg_insn_addr, dbg_insn_opcode, dbg_ascii_instr ? dbg_ascii_instr : \"UNKNOWN\");\n\t\t\telse\n\t\t\t\t$display(\"DECODE: 0x%08x     0x%04x %-0s\", dbg_insn_addr, dbg_insn_opcode[15:0], dbg_ascii_instr ? dbg_ascii_instr : \"UNKNOWN\");\n\t\tend\n\tend\n`endif\n\n\talways @(posedge clk) begin\n\t\tis_lui_auipc_jal <= |{instr_lui, instr_auipc, instr_jal};\n\t\tis_lui_auipc_jal_jalr_addi_add_sub <= |{instr_lui, instr_auipc, instr_jal, instr_jalr, instr_addi, instr_add, instr_sub};\n\t\tis_slti_blt_slt <= |{instr_slti, instr_blt, instr_slt};\n\t\tis_sltiu_bltu_sltu <= |{instr_sltiu, instr_bltu, instr_sltu};\n\t\tis_lbu_lhu_lw <= |{instr_lbu, instr_lhu, instr_lw};\n\t\tis_compare <= |{is_beq_bne_blt_bge_bltu_bgeu, instr_slti, instr_slt, instr_sltiu, instr_sltu};\n\n\t\tif (mem_do_rinst && mem_done) begin\n\t\t\tinstr_lui     <= mem_rdata_latched[6:0] == 7'b0110111;\n\t\t\tinstr_auipc   <= mem_rdata_latched[6:0] == 7'b0010111;\n\t\t\tinstr_jal     <= mem_rdata_latched[6:0] == 7'b1101111;\n\t\t\tinstr_jalr    <= mem_rdata_latched[6:0] == 7'b1100111 && mem_rdata_latched[14:12] == 3'b000;\n\t\t\tinstr_retirq  <= mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000010 && ENABLE_IRQ;\n\t\t\tinstr_waitirq <= mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000100 && ENABLE_IRQ;\n\n\t\t\tis_beq_bne_blt_bge_bltu_bgeu <= mem_rdata_latched[6:0] == 7'b1100011;\n\t\t\tis_lb_lh_lw_lbu_lhu          <= mem_rdata_latched[6:0] == 7'b0000011;\n\t\t\tis_sb_sh_sw                  <= mem_rdata_latched[6:0] == 7'b0100011;\n\t\t\tis_alu_reg_imm               <= mem_rdata_latched[6:0] == 7'b0010011;\n\t\t\tis_alu_reg_reg               <= mem_rdata_latched[6:0] == 7'b0110011;\n\n\t\t\t{ decoded_imm_uj[31:20], decoded_imm_uj[10:1], decoded_imm_uj[11], decoded_imm_uj[19:12], decoded_imm_uj[0] } <= $signed({mem_rdata_latched[31:12], 1'b0});\n\n\t\t\tdecoded_rd <= mem_rdata_latched[11:7];\n\t\t\tdecoded_rs1 <= mem_rdata_latched[19:15];\n\t\t\tdecoded_rs2 <= mem_rdata_latched[24:20];\n\n\t\t\tif (mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000000 && ENABLE_IRQ && ENABLE_IRQ_QREGS)\n\t\t\t\tdecoded_rs1[regindex_bits-1] <= 1; // instr_getq\n\n\t\t\tif (mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000010 && ENABLE_IRQ)\n\t\t\t\tdecoded_rs1 <= ENABLE_IRQ_QREGS ? irqregs_offset : 3; // instr_retirq\n\n\t\t\tcompressed_instr <= 0;\n\t\t\tif (COMPRESSED_ISA && mem_rdata_latched[1:0] != 2'b11) begin\n\t\t\t\tcompressed_instr <= 1;\n\t\t\t\tdecoded_rd <= 0;\n\t\t\t\tdecoded_rs1 <= 0;\n\t\t\t\tdecoded_rs2 <= 0;\n\n\t\t\t\t{ decoded_imm_uj[31:11], decoded_imm_uj[4], decoded_imm_uj[9:8], decoded_imm_uj[10], decoded_imm_uj[6],\n\t\t\t\t  decoded_imm_uj[7], decoded_imm_uj[3:1], decoded_imm_uj[5], decoded_imm_uj[0] } <= $signed({mem_rdata_latched[12:2], 1'b0});\n\n\t\t\t\tcase (mem_rdata_latched[1:0])\n\t\t\t\t\t2'b00: begin // Quadrant 0\n\t\t\t\t\t\tcase (mem_rdata_latched[15:13])\n\t\t\t\t\t\t\t3'b000: begin // C.ADDI4SPN\n\t\t\t\t\t\t\t\tis_alu_reg_imm <= |mem_rdata_latched[12:5];\n\t\t\t\t\t\t\t\tdecoded_rs1 <= 2;\n\t\t\t\t\t\t\t\tdecoded_rd <= 8 + mem_rdata_latched[4:2];\n\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\t3'b010: begin // C.LW\n\t\t\t\t\t\t\t\tis_lb_lh_lw_lbu_lhu <= 1;\n\t\t\t\t\t\t\t\tdecoded_rs1 <= 8 + mem_rdata_latched[9:7];\n\t\t\t\t\t\t\t\tdecoded_rd <= 8 + mem_rdata_latched[4:2];\n\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\t3'b110: begin // C.SW\n\t\t\t\t\t\t\t\tis_sb_sh_sw <= 1;\n\t\t\t\t\t\t\t\tdecoded_rs1 <= 8 + mem_rdata_latched[9:7];\n\t\t\t\t\t\t\t\tdecoded_rs2 <= 8 + mem_rdata_latched[4:2];\n\t\t\t\t\t\t\tend\n\t\t\t\t\t\tendcase\n\t\t\t\t\tend\n\t\t\t\t\t2'b01: begin // Quadrant 1\n\t\t\t\t\t\tcase (mem_rdata_latched[15:13])\n\t\t\t\t\t\t\t3'b000: begin // C.NOP / C.ADDI\n\t\t\t\t\t\t\t\tis_alu_reg_imm <= 1;\n\t\t\t\t\t\t\t\tdecoded_rd <= mem_rdata_latched[11:7];\n\t\t\t\t\t\t\t\tdecoded_rs1 <= mem_rdata_latched[11:7];\n\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\t3'b001: begin // C.JAL\n\t\t\t\t\t\t\t\tinstr_jal <= 1;\n\t\t\t\t\t\t\t\tdecoded_rd <= 1;\n\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\t3'b 010: begin // C.LI\n\t\t\t\t\t\t\t\tis_alu_reg_imm <= 1;\n\t\t\t\t\t\t\t\tdecoded_rd <= mem_rdata_latched[11:7];\n\t\t\t\t\t\t\t\tdecoded_rs1 <= 0;\n\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\t3'b 011: begin\n\t\t\t\t\t\t\t\tif (mem_rdata_latched[12] || mem_rdata_latched[6:2]) begin\n\t\t\t\t\t\t\t\t\tif (mem_rdata_latched[11:7] == 2) begin // C.ADDI16SP\n\t\t\t\t\t\t\t\t\t\tis_alu_reg_imm <= 1;\n\t\t\t\t\t\t\t\t\t\tdecoded_rd <= mem_rdata_latched[11:7];\n\t\t\t\t\t\t\t\t\t\tdecoded_rs1 <= mem_rdata_latched[11:7];\n\t\t\t\t\t\t\t\t\tend else begin // C.LUI\n\t\t\t\t\t\t\t\t\t\tinstr_lui <= 1;\n\t\t\t\t\t\t\t\t\t\tdecoded_rd <= mem_rdata_latched[11:7];\n\t\t\t\t\t\t\t\t\t\tdecoded_rs1 <= 0;\n\t\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\t3'b100: begin\n\t\t\t\t\t\t\t\tif (!mem_rdata_latched[11] && !mem_rdata_latched[12]) begin // C.SRLI, C.SRAI\n\t\t\t\t\t\t\t\t\tis_alu_reg_imm <= 1;\n\t\t\t\t\t\t\t\t\tdecoded_rd <= 8 + mem_rdata_latched[9:7];\n\t\t\t\t\t\t\t\t\tdecoded_rs1 <= 8 + mem_rdata_latched[9:7];\n\t\t\t\t\t\t\t\t\tdecoded_rs2 <= {mem_rdata_latched[12], mem_rdata_latched[6:2]};\n\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\t\tif (mem_rdata_latched[11:10] == 2'b10) begin // C.ANDI\n\t\t\t\t\t\t\t\t\tis_alu_reg_imm <= 1;\n\t\t\t\t\t\t\t\t\tdecoded_rd <= 8 + mem_rdata_latched[9:7];\n\t\t\t\t\t\t\t\t\tdecoded_rs1 <= 8 + mem_rdata_latched[9:7];\n\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\t\tif (mem_rdata_latched[12:10] == 3'b011) begin // C.SUB, C.XOR, C.OR, C.AND\n\t\t\t\t\t\t\t\t\tis_alu_reg_reg <= 1;\n\t\t\t\t\t\t\t\t\tdecoded_rd <= 8 + mem_rdata_latched[9:7];\n\t\t\t\t\t\t\t\t\tdecoded_rs1 <= 8 + mem_rdata_latched[9:7];\n\t\t\t\t\t\t\t\t\tdecoded_rs2 <= 8 + mem_rdata_latched[4:2];\n\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\t3'b101: begin // C.J\n\t\t\t\t\t\t\t\tinstr_jal <= 1;\n\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\t3'b110: begin // C.BEQZ\n\t\t\t\t\t\t\t\tis_beq_bne_blt_bge_bltu_bgeu <= 1;\n\t\t\t\t\t\t\t\tdecoded_rs1 <= 8 + mem_rdata_latched[9:7];\n\t\t\t\t\t\t\t\tdecoded_rs2 <= 0;\n\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\t3'b111: begin // C.BNEZ\n\t\t\t\t\t\t\t\tis_beq_bne_blt_bge_bltu_bgeu <= 1;\n\t\t\t\t\t\t\t\tdecoded_rs1 <= 8 + mem_rdata_latched[9:7];\n\t\t\t\t\t\t\t\tdecoded_rs2 <= 0;\n\t\t\t\t\t\t\tend\n\t\t\t\t\t\tendcase\n\t\t\t\t\tend\n\t\t\t\t\t2'b10: begin // Quadrant 2\n\t\t\t\t\t\tcase (mem_rdata_latched[15:13])\n\t\t\t\t\t\t\t3'b000: begin // C.SLLI\n\t\t\t\t\t\t\t\tif (!mem_rdata_latched[12]) begin\n\t\t\t\t\t\t\t\t\tis_alu_reg_imm <= 1;\n\t\t\t\t\t\t\t\t\tdecoded_rd <= mem_rdata_latched[11:7];\n\t\t\t\t\t\t\t\t\tdecoded_rs1 <= mem_rdata_latched[11:7];\n\t\t\t\t\t\t\t\t\tdecoded_rs2 <= {mem_rdata_latched[12], mem_rdata_latched[6:2]};\n\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\t3'b010: begin // C.LWSP\n\t\t\t\t\t\t\t\tif (mem_rdata_latched[11:7]) begin\n\t\t\t\t\t\t\t\t\tis_lb_lh_lw_lbu_lhu <= 1;\n\t\t\t\t\t\t\t\t\tdecoded_rd <= mem_rdata_latched[11:7];\n\t\t\t\t\t\t\t\t\tdecoded_rs1 <= 2;\n\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\t3'b100: begin\n\t\t\t\t\t\t\t\tif (mem_rdata_latched[12] == 0 && mem_rdata_latched[11:7] != 0 && mem_rdata_latched[6:2] == 0) begin // C.JR\n\t\t\t\t\t\t\t\t\tinstr_jalr <= 1;\n\t\t\t\t\t\t\t\t\tdecoded_rd <= 0;\n\t\t\t\t\t\t\t\t\tdecoded_rs1 <= mem_rdata_latched[11:7];\n\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\t\tif (mem_rdata_latched[12] == 0 && mem_rdata_latched[6:2] != 0) begin // C.MV\n\t\t\t\t\t\t\t\t\tis_alu_reg_reg <= 1;\n\t\t\t\t\t\t\t\t\tdecoded_rd <= mem_rdata_latched[11:7];\n\t\t\t\t\t\t\t\t\tdecoded_rs1 <= 0;\n\t\t\t\t\t\t\t\t\tdecoded_rs2 <= mem_rdata_latched[6:2];\n\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\t\tif (mem_rdata_latched[12] != 0 && mem_rdata_latched[11:7] != 0 && mem_rdata_latched[6:2] == 0) begin // C.JALR\n\t\t\t\t\t\t\t\t\tinstr_jalr <= 1;\n\t\t\t\t\t\t\t\t\tdecoded_rd <= 1;\n\t\t\t\t\t\t\t\t\tdecoded_rs1 <= mem_rdata_latched[11:7];\n\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\t\tif (mem_rdata_latched[12] != 0 && mem_rdata_latched[6:2] != 0) begin // C.ADD\n\t\t\t\t\t\t\t\t\tis_alu_reg_reg <= 1;\n\t\t\t\t\t\t\t\t\tdecoded_rd <= mem_rdata_latched[11:7];\n\t\t\t\t\t\t\t\t\tdecoded_rs1 <= mem_rdata_latched[11:7];\n\t\t\t\t\t\t\t\t\tdecoded_rs2 <= mem_rdata_latched[6:2];\n\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\t3'b110: begin // C.SWSP\n\t\t\t\t\t\t\t\tis_sb_sh_sw <= 1;\n\t\t\t\t\t\t\t\tdecoded_rs1 <= 2;\n\t\t\t\t\t\t\t\tdecoded_rs2 <= mem_rdata_latched[6:2];\n\t\t\t\t\t\t\tend\n\t\t\t\t\t\tendcase\n\t\t\t\t\tend\n\t\t\t\tendcase\n\t\t\tend\n\t\tend\n\n\t\tif (decoder_trigger && !decoder_pseudo_trigger) begin\n\t\t\tpcpi_insn_i <= WITH_PCPI ? mem_rdata_q : 'bx;\n\n\t\t\tinstr_beq   <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b000;\n\t\t\tinstr_bne   <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b001;\n\t\t\tinstr_blt   <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b100;\n\t\t\tinstr_bge   <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b101;\n\t\t\tinstr_bltu  <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b110;\n\t\t\tinstr_bgeu  <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b111;\n\n\t\t\tinstr_lb    <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b000;\n\t\t\tinstr_lh    <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b001;\n\t\t\tinstr_lw    <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b010;\n\t\t\tinstr_lbu   <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b100;\n\t\t\tinstr_lhu   <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b101;\n\n\t\t\tinstr_sb    <= is_sb_sh_sw && mem_rdata_q[14:12] == 3'b000;\n\t\t\tinstr_sh    <= is_sb_sh_sw && mem_rdata_q[14:12] == 3'b001;\n\t\t\tinstr_sw    <= is_sb_sh_sw && mem_rdata_q[14:12] == 3'b010;\n\n\t\t\tinstr_addi  <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b000;\n\t\t\tinstr_slti  <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b010;\n\t\t\tinstr_sltiu <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b011;\n\t\t\tinstr_xori  <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b100;\n\t\t\tinstr_ori   <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b110;\n\t\t\tinstr_andi  <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b111;\n\n\t\t\tinstr_slli  <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000;\n\t\t\tinstr_srli  <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000;\n\t\t\tinstr_srai  <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000;\n\n\t\t\tinstr_add   <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b000 && mem_rdata_q[31:25] == 7'b0000000;\n\t\t\tinstr_sub   <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b000 && mem_rdata_q[31:25] == 7'b0100000;\n\t\t\tinstr_sll   <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000;\n\t\t\tinstr_slt   <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b010 && mem_rdata_q[31:25] == 7'b0000000;\n\t\t\tinstr_sltu  <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b011 && mem_rdata_q[31:25] == 7'b0000000;\n\t\t\tinstr_xor   <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b100 && mem_rdata_q[31:25] == 7'b0000000;\n\t\t\tinstr_srl   <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000;\n\t\t\tinstr_sra   <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000;\n\t\t\tinstr_or    <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b110 && mem_rdata_q[31:25] == 7'b0000000;\n\t\t\tinstr_and   <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b111 && mem_rdata_q[31:25] == 7'b0000000;\n\n\t\t\tinstr_rdcycle  <= ((mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11000000000000000010) ||\n\t\t\t                   (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11000000000100000010)) && ENABLE_COUNTERS;\n\t\t\tinstr_rdcycleh <= ((mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11001000000000000010) ||\n\t\t\t                   (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11001000000100000010)) && ENABLE_COUNTERS && ENABLE_COUNTERS64;\n\t\t\tinstr_rdinstr  <=  (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11000000001000000010) && ENABLE_COUNTERS;\n\t\t\tinstr_rdinstrh <=  (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11001000001000000010) && ENABLE_COUNTERS && ENABLE_COUNTERS64;\n\n\t\t\tinstr_ecall_ebreak <= ((mem_rdata_q[6:0] == 7'b1110011 && !mem_rdata_q[31:21] && !mem_rdata_q[19:7]) ||\n\t\t\t\t\t(COMPRESSED_ISA && mem_rdata_q[15:0] == 16'h9002));\n\n\t\t\tinstr_getq    <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000000 && ENABLE_IRQ && ENABLE_IRQ_QREGS;\n\t\t\tinstr_setq    <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000001 && ENABLE_IRQ && ENABLE_IRQ_QREGS;\n\t\t\tinstr_maskirq <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000011 && ENABLE_IRQ;\n\t\t\tinstr_timer   <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000101 && ENABLE_IRQ && ENABLE_IRQ_TIMER;\n\n\t\t\tis_slli_srli_srai <= is_alu_reg_imm && |{\n\t\t\t\tmem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000,\n\t\t\t\tmem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000,\n\t\t\t\tmem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000\n\t\t\t};\n\n\t\t\tis_jalr_addi_slti_sltiu_xori_ori_andi <= instr_jalr || is_alu_reg_imm && |{\n\t\t\t\tmem_rdata_q[14:12] == 3'b000,\n\t\t\t\tmem_rdata_q[14:12] == 3'b010,\n\t\t\t\tmem_rdata_q[14:12] == 3'b011,\n\t\t\t\tmem_rdata_q[14:12] == 3'b100,\n\t\t\t\tmem_rdata_q[14:12] == 3'b110,\n\t\t\t\tmem_rdata_q[14:12] == 3'b111\n\t\t\t};\n\n\t\t\tis_sll_srl_sra <= is_alu_reg_reg && |{\n\t\t\t\tmem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000,\n\t\t\t\tmem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000,\n\t\t\t\tmem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000\n\t\t\t};\n\n\t\t\tis_lui_auipc_jal_jalr_addi_add_sub <= 0;\n\t\t\tis_compare <= 0;\n\n\t\t\t(* parallel_case *)\n\t\t\tcase (1'b1)\n\t\t\t\tinstr_jal:\n\t\t\t\t\tdecoded_imm <= decoded_imm_uj;\n\t\t\t\t|{instr_lui, instr_auipc}:\n\t\t\t\t\tdecoded_imm <= mem_rdata_q[31:12] << 12;\n\t\t\t\t|{instr_jalr, is_lb_lh_lw_lbu_lhu, is_alu_reg_imm}:\n\t\t\t\t\tdecoded_imm <= $signed(mem_rdata_q[31:20]);\n\t\t\t\tis_beq_bne_blt_bge_bltu_bgeu:\n\t\t\t\t\tdecoded_imm <= $signed({mem_rdata_q[31], mem_rdata_q[7], mem_rdata_q[30:25], mem_rdata_q[11:8], 1'b0});\n\t\t\t\tis_sb_sh_sw:\n\t\t\t\t\tdecoded_imm <= $signed({mem_rdata_q[31:25], mem_rdata_q[11:7]});\n\t\t\t\tdefault:\n\t\t\t\t\tdecoded_imm <= 1'bx;\n\t\t\tendcase\n\t\tend\n\n\t\tif (!resetn) begin\n\t\t\tis_beq_bne_blt_bge_bltu_bgeu <= 0;\n\t\t\tis_compare <= 0;\n\n\t\t\tinstr_beq   <= 0;\n\t\t\tinstr_bne   <= 0;\n\t\t\tinstr_blt   <= 0;\n\t\t\tinstr_bge   <= 0;\n\t\t\tinstr_bltu  <= 0;\n\t\t\tinstr_bgeu  <= 0;\n\n\t\t\tinstr_addi  <= 0;\n\t\t\tinstr_slti  <= 0;\n\t\t\tinstr_sltiu <= 0;\n\t\t\tinstr_xori  <= 0;\n\t\t\tinstr_ori   <= 0;\n\t\t\tinstr_andi  <= 0;\n\n\t\t\tinstr_add   <= 0;\n\t\t\tinstr_sub   <= 0;\n\t\t\tinstr_sll   <= 0;\n\t\t\tinstr_slt   <= 0;\n\t\t\tinstr_sltu  <= 0;\n\t\t\tinstr_xor   <= 0;\n\t\t\tinstr_srl   <= 0;\n\t\t\tinstr_sra   <= 0;\n\t\t\tinstr_or    <= 0;\n\t\t\tinstr_and   <= 0;\n\t\tend\n\tend\n\n\n\t// Main State Machine\n\n\tlocalparam cpu_state_trap   = 8'b10000000;\n\tlocalparam cpu_state_fetch  = 8'b01000000;\n\tlocalparam cpu_state_ld_rs1 = 8'b00100000;\n\tlocalparam cpu_state_ld_rs2 = 8'b00010000;\n\tlocalparam cpu_state_exec   = 8'b00001000;\n\tlocalparam cpu_state_shift  = 8'b00000100;\n\tlocalparam cpu_state_stmem  = 8'b00000010;\n\tlocalparam cpu_state_ldmem  = 8'b00000001;\n\n\treg [7:0] cpu_state;\n\treg [1:0] irq_state;\n\n\t//`FORMAL_KEEP reg [127:0] dbg_ascii_state;\n\n\talways @* begin\n\t\tdbg_ascii_state = \"\";\n\t\tif (cpu_state == cpu_state_trap)   dbg_ascii_state = \"trap\";\n\t\tif (cpu_state == cpu_state_fetch)  dbg_ascii_state = \"fetch\";\n\t\tif (cpu_state == cpu_state_ld_rs1) dbg_ascii_state = \"ld_rs1\";\n\t\tif (cpu_state == cpu_state_ld_rs2) dbg_ascii_state = \"ld_rs2\";\n\t\tif (cpu_state == cpu_state_exec)   dbg_ascii_state = \"exec\";\n\t\tif (cpu_state == cpu_state_shift)  dbg_ascii_state = \"shift\";\n\t\tif (cpu_state == cpu_state_stmem)  dbg_ascii_state = \"stmem\";\n\t\tif (cpu_state == cpu_state_ldmem)  dbg_ascii_state = \"ldmem\";\n\tend\n\n\treg set_mem_do_rinst;\n\treg set_mem_do_rdata;\n\treg set_mem_do_wdata;\n\n\treg latched_store;\n\treg latched_stalu;\n\treg latched_branch;\n\treg latched_compr;\n\treg latched_trace;\n\treg latched_is_lu;\n\treg latched_is_lh;\n\treg latched_is_lb;\n\treg [regindex_bits-1:0] latched_rd;\n\n\treg [31:0] current_pc;\n\tassign next_pc = latched_store && latched_branch ? reg_out & ~1 : reg_next_pc;\n\n\treg [3:0] pcpi_timeout_counter;\n\treg pcpi_timeout;\n\n\treg [31:0] next_irq_pending;\n\treg do_waitirq;\n\n\treg [31:0] alu_out, alu_out_q;\n\treg alu_out_0, alu_out_0_q;\n\treg alu_wait, alu_wait_2;\n\n\treg [31:0] alu_add_sub;\n\treg [31:0] alu_shl, alu_shr;\n\treg alu_eq, alu_ltu, alu_lts;\n\n\tgenerate if (TWO_CYCLE_ALU) begin\n\t\talways @(posedge clk) begin\n\t\t\talu_add_sub <= instr_sub ? reg_op1 - reg_op2 : reg_op1 + reg_op2;\n\t\t\talu_eq <= reg_op1 == reg_op2;\n\t\t\talu_lts <= $signed(reg_op1) < $signed(reg_op2);\n\t\t\talu_ltu <= reg_op1 < reg_op2;\n\t\t\talu_shl <= reg_op1 << reg_op2[4:0];\n\t\t\talu_shr <= $signed({instr_sra || instr_srai ? reg_op1[31] : 1'b0, reg_op1}) >>> reg_op2[4:0];\n\t\tend\n\tend else begin\n\t\talways @* begin\n\t\t\talu_add_sub = instr_sub ? reg_op1 - reg_op2 : reg_op1 + reg_op2;\n\t\t\talu_eq = reg_op1 == reg_op2;\n\t\t\talu_lts = $signed(reg_op1) < $signed(reg_op2);\n\t\t\talu_ltu = reg_op1 < reg_op2;\n\t\t\talu_shl = reg_op1 << reg_op2[4:0];\n\t\t\talu_shr = $signed({instr_sra || instr_srai ? reg_op1[31] : 1'b0, reg_op1}) >>> reg_op2[4:0];\n\t\tend\n\tend endgenerate\n\n\talways @* begin\n\t\talu_out_0 = 'bx;\n\t\t(* parallel_case, full_case *)\n\t\tcase (1'b1)\n\t\t\tinstr_beq:\n\t\t\t\talu_out_0 = alu_eq;\n\t\t\tinstr_bne:\n\t\t\t\talu_out_0 = !alu_eq;\n\t\t\tinstr_bge:\n\t\t\t\talu_out_0 = !alu_lts;\n\t\t\tinstr_bgeu:\n\t\t\t\talu_out_0 = !alu_ltu;\n\t\t\tis_slti_blt_slt && (!TWO_CYCLE_COMPARE || !{instr_beq,instr_bne,instr_bge,instr_bgeu}):\n\t\t\t\talu_out_0 = alu_lts;\n\t\t\tis_sltiu_bltu_sltu && (!TWO_CYCLE_COMPARE || !{instr_beq,instr_bne,instr_bge,instr_bgeu}):\n\t\t\t\talu_out_0 = alu_ltu;\n\t\tendcase\n\n\t\talu_out = 'bx;\n\t\t(* parallel_case, full_case *)\n\t\tcase (1'b1)\n\t\t\tis_lui_auipc_jal_jalr_addi_add_sub:\n\t\t\t\talu_out = alu_add_sub;\n\t\t\tis_compare:\n\t\t\t\talu_out = alu_out_0;\n\t\t\tinstr_xori || instr_xor:\n\t\t\t\talu_out = reg_op1 ^ reg_op2;\n\t\t\tinstr_ori || instr_or:\n\t\t\t\talu_out = reg_op1 | reg_op2;\n\t\t\tinstr_andi || instr_and:\n\t\t\t\talu_out = reg_op1 & reg_op2;\n\t\t\tBARREL_SHIFTER && (instr_sll || instr_slli):\n\t\t\t\talu_out = alu_shl;\n\t\t\tBARREL_SHIFTER && (instr_srl || instr_srli || instr_sra || instr_srai):\n\t\t\t\talu_out = alu_shr;\n\t\tendcase\n\n`ifdef RISCV_FORMAL_BLACKBOX_ALU\n\t\talu_out_0 = $anyseq;\n\t\talu_out = $anyseq;\n`endif\n\tend\n\n\treg clear_prefetched_high_word_q;\n\talways @(posedge clk) clear_prefetched_high_word_q <= clear_prefetched_high_word;\n\n\talways @* begin\n\t\tclear_prefetched_high_word = clear_prefetched_high_word_q;\n\t\tif (!prefetched_high_word)\n\t\t\tclear_prefetched_high_word = 0;\n\t\tif (latched_branch || irq_state || !resetn)\n\t\t\tclear_prefetched_high_word = COMPRESSED_ISA;\n\tend\n\n\treg cpuregs_write;\n\treg [31:0] cpuregs_wrdata_i;\n    assign cpuregs_wrdata = cpuregs_wrdata_i;\n\treg [31:0] cpuregs_rs1;\n\treg [31:0] cpuregs_rs2;\n\treg [regindex_bits-1:0] decoded_rs;\n\n\talways @* begin\n\t\tcpuregs_write = 0;\n\t\tcpuregs_wrdata_i = 'bx;\n\n\t\tif (cpu_state == cpu_state_fetch) begin\n\t\t\t(* parallel_case *)\n\t\t\tcase (1'b1)\n\t\t\t\tlatched_branch: begin\n\t\t\t\t\tcpuregs_wrdata_i = reg_pc + (latched_compr ? 2 : 4);\n\t\t\t\t\tcpuregs_write = 1;\n\t\t\t\tend\n\t\t\t\tlatched_store && !latched_branch: begin\n\t\t\t\t\tcpuregs_wrdata_i = latched_stalu ? alu_out_q : reg_out;\n\t\t\t\t\tcpuregs_write = 1;\n\t\t\t\tend\n\t\t\t\tENABLE_IRQ && irq_state[0]: begin\n\t\t\t\t\tcpuregs_wrdata_i = reg_next_pc | latched_compr;\n\t\t\t\t\tcpuregs_write = 1;\n\t\t\t\tend\n\t\t\t\tENABLE_IRQ && irq_state[1]: begin\n\t\t\t\t\tcpuregs_wrdata_i = irq_pending & ~irq_mask;\n\t\t\t\t\tcpuregs_write = 1;\n\t\t\t\tend\n\t\t\tendcase\n\t\tend\n\tend\n\n`ifndef PICORV32_REGS\n\talways @(posedge clk) begin\n\t\tif (resetn && cpuregs_write && latched_rd)\n\t\t\tcpuregs[latched_rd] <= cpuregs_wrdata_i;\n\tend\n\n\talways @* begin\n\t\tdecoded_rs = 'bx;\n\t\tif (ENABLE_REGS_DUALPORT) begin\n`ifndef RISCV_FORMAL_BLACKBOX_REGS\n\t\t\tcpuregs_rs1 = decoded_rs1 ? cpuregs[decoded_rs1] : 0;\n\t\t\tcpuregs_rs2 = decoded_rs2 ? cpuregs[decoded_rs2] : 0;\n`else\n\t\t\tcpuregs_rs1 = decoded_rs1 ? $anyseq : 0;\n\t\t\tcpuregs_rs2 = decoded_rs2 ? $anyseq : 0;\n`endif\n\t\tend else begin\n\t\t\tdecoded_rs = (cpu_state == cpu_state_ld_rs2) ? decoded_rs2 : decoded_rs1;\n`ifndef RISCV_FORMAL_BLACKBOX_REGS\n\t\t\tcpuregs_rs1 = decoded_rs ? cpuregs[decoded_rs] : 0;\n`else\n\t\t\tcpuregs_rs1 = decoded_rs ? $anyseq : 0;\n`endif\n\t\t\tcpuregs_rs2 = cpuregs_rs1;\n\t\tend\n\tend\n`else\n\n\tassign cpuregs_waddr = latched_rd;\n\tassign cpuregs_raddr1 = ENABLE_REGS_DUALPORT ? decoded_rs1 : decoded_rs;\n\tassign cpuregs_raddr2 = ENABLE_REGS_DUALPORT ? decoded_rs2 : 0;\n\n\talways @* begin\n\t\tdecoded_rs = 'bx;\n\t\tif (ENABLE_REGS_DUALPORT) begin\n\t\t\tcpuregs_rs1 = decoded_rs1 ? cpuregs_rdata1 : 0;\n\t\t\tcpuregs_rs2 = decoded_rs2 ? cpuregs_rdata2 : 0;\n\t\tend else begin\n\t\t\tdecoded_rs = (cpu_state == cpu_state_ld_rs2) ? decoded_rs2 : decoded_rs1;\n\t\t\tcpuregs_rs1 = decoded_rs ? cpuregs_rdata1 : 0;\n\t\t\tcpuregs_rs2 = cpuregs_rs1;\n\t\tend\n\tend\n`endif\n\n\tassign launch_next_insn = cpu_state == cpu_state_fetch && decoder_trigger && (!ENABLE_IRQ || irq_delay || irq_active || !(irq_pending & ~irq_mask));\n\n\talways @(posedge clk) begin\n\t\ttrap <= 0;\n\t\treg_sh <= 'bx;\n\t\treg_out <= 'bx;\n\t\tset_mem_do_rinst = 0;\n\t\tset_mem_do_rdata = 0;\n\t\tset_mem_do_wdata = 0;\n\n\t\talu_out_0_q <= alu_out_0;\n\t\talu_out_q <= alu_out;\n\n\t\talu_wait <= 0;\n\t\talu_wait_2 <= 0;\n\n\t\tif (launch_next_insn) begin\n\t\t\tdbg_rs1val <= 'bx;\n\t\t\tdbg_rs2val <= 'bx;\n\t\t\tdbg_rs1val_valid <= 0;\n\t\t\tdbg_rs2val_valid <= 0;\n\t\tend\n\n\t\tif (WITH_PCPI && CATCH_ILLINSN) begin\n\t\t\tif (resetn && pcpi_valid_i && !pcpi_int_wait) begin\n\t\t\t\tif (pcpi_timeout_counter)\n\t\t\t\t\tpcpi_timeout_counter <= pcpi_timeout_counter - 1;\n\t\t\tend else\n\t\t\t\tpcpi_timeout_counter <= ~0;\n\t\t\tpcpi_timeout <= !pcpi_timeout_counter;\n\t\tend\n\n\t\tif (ENABLE_COUNTERS) begin\n\t\t\tcount_cycle <= resetn ? count_cycle + 1 : 0;\n\t\t\tif (!ENABLE_COUNTERS64) count_cycle[63:32] <= 0;\n\t\tend else begin\n\t\t\tcount_cycle <= 'bx;\n\t\t\tcount_instr <= 'bx;\n\t\tend\n\n\t\tnext_irq_pending = ENABLE_IRQ ? irq_pending & LATCHED_IRQ : 'bx;\n\n\t\tif (ENABLE_IRQ && ENABLE_IRQ_TIMER && timer) begin\n\t\t\tif (timer - 1 == 0)\n\t\t\t\tnext_irq_pending[irq_timer] = 1;\n\t\t\ttimer <= timer - 1;\n\t\tend\n\n\t\tif (ENABLE_IRQ) begin\n\t\t\tnext_irq_pending = next_irq_pending | irq;\n\t\tend\n\n\t\tdecoder_trigger <= mem_do_rinst && mem_done;\n\t\tdecoder_trigger_q <= decoder_trigger;\n\t\tdecoder_pseudo_trigger <= 0;\n\t\tdecoder_pseudo_trigger_q <= decoder_pseudo_trigger;\n\t\tdo_waitirq <= 0;\n\n\t\ttrace_valid <= 0;\n\n\t\tif (!ENABLE_TRACE)\n\t\t\ttrace_data <= 'bx;\n\n\t\tif (!resetn) begin\n\t\t\treg_pc <= PROGADDR_RESET;\n\t\t\treg_next_pc <= PROGADDR_RESET;\n\t\t\tif (ENABLE_COUNTERS)\n\t\t\t\tcount_instr <= 0;\n\t\t\tlatched_store <= 0;\n\t\t\tlatched_stalu <= 0;\n\t\t\tlatched_branch <= 0;\n\t\t\tlatched_trace <= 0;\n\t\t\tlatched_is_lu <= 0;\n\t\t\tlatched_is_lh <= 0;\n\t\t\tlatched_is_lb <= 0;\n\t\t\tpcpi_valid_i <= 0;\n\t\t\tpcpi_timeout <= 0;\n\t\t\tirq_active <= 0;\n\t\t\tirq_delay <= 0;\n\t\t\tirq_mask <= ~0;\n\t\t\tnext_irq_pending = 0;\n\t\t\tirq_state <= 0;\n\t\t\teoi <= 0;\n\t\t\ttimer <= 0;\n\t\t\tif (~STACKADDR) begin\n\t\t\t\tlatched_store <= 1;\n\t\t\t\tlatched_rd <= 2;\n\t\t\t\treg_out <= STACKADDR;\n\t\t\tend\n\t\t\tcpu_state <= cpu_state_fetch;\n\t\tend else\n\t\t(* parallel_case, full_case *)\n\t\tcase (cpu_state)\n\t\t\tcpu_state_trap: begin\n\t\t\t\ttrap <= 1;\n\t\t\tend\n\n\t\t\tcpu_state_fetch: begin\n\t\t\t\tmem_do_rinst <= !decoder_trigger && !do_waitirq;\n\t\t\t\tmem_wordsize <= 0;\n\n\t\t\t\tcurrent_pc = reg_next_pc;\n\n\t\t\t\t(* parallel_case *)\n\t\t\t\tcase (1'b1)\n\t\t\t\t\tlatched_branch: begin\n\t\t\t\t\t\tcurrent_pc = latched_store ? (latched_stalu ? alu_out_q : reg_out) & ~1 : reg_next_pc;\n\t\t\t\t\t\t//`debug($display(\"ST_RD:  %2d 0x%08x, BRANCH 0x%08x\", latched_rd, reg_pc + (latched_compr ? 2 : 4), current_pc);)\n\t\t\t\t\tend\n\t\t\t\t\tlatched_store && !latched_branch: begin\n\t\t\t\t\t\t//`debug($display(\"ST_RD:  %2d 0x%08x\", latched_rd, latched_stalu ? alu_out_q : reg_out);)\n\t\t\t\t\tend\n\t\t\t\t\tENABLE_IRQ && irq_state[0]: begin\n\t\t\t\t\t\tcurrent_pc = PROGADDR_IRQ;\n\t\t\t\t\t\tirq_active <= 1;\n\t\t\t\t\t\tmem_do_rinst <= 1;\n\t\t\t\t\tend\n\t\t\t\t\tENABLE_IRQ && irq_state[1]: begin\n\t\t\t\t\t\teoi <= irq_pending & ~irq_mask;\n\t\t\t\t\t\tnext_irq_pending = next_irq_pending & irq_mask;\n\t\t\t\t\tend\n\t\t\t\tendcase\n\n\t\t\t\tif (ENABLE_TRACE && latched_trace) begin\n\t\t\t\t\tlatched_trace <= 0;\n\t\t\t\t\ttrace_valid <= 1;\n\t\t\t\t\tif (latched_branch)\n\t\t\t\t\t\ttrace_data <= (irq_active ? TRACE_IRQ : 0) | TRACE_BRANCH | (current_pc & 32'hfffffffe);\n\t\t\t\t\telse\n\t\t\t\t\t\ttrace_data <= (irq_active ? TRACE_IRQ : 0) | (latched_stalu ? alu_out_q : reg_out);\n\t\t\t\tend\n\n\t\t\t\treg_pc <= current_pc;\n\t\t\t\treg_next_pc <= current_pc;\n\n\t\t\t\tlatched_store <= 0;\n\t\t\t\tlatched_stalu <= 0;\n\t\t\t\tlatched_branch <= 0;\n\t\t\t\tlatched_is_lu <= 0;\n\t\t\t\tlatched_is_lh <= 0;\n\t\t\t\tlatched_is_lb <= 0;\n\t\t\t\tlatched_rd <= decoded_rd;\n\t\t\t\tlatched_compr <= compressed_instr;\n\n\t\t\t\tif (ENABLE_IRQ && ((decoder_trigger && !irq_active && !irq_delay && |(irq_pending & ~irq_mask)) || irq_state)) begin\n\t\t\t\t\tirq_state <=\n\t\t\t\t\t\tirq_state == 2'b00 ? 2'b01 :\n\t\t\t\t\t\tirq_state == 2'b01 ? 2'b10 : 2'b00;\n\t\t\t\t\tlatched_compr <= latched_compr;\n\t\t\t\t\tif (ENABLE_IRQ_QREGS)\n\t\t\t\t\t\tlatched_rd <= irqregs_offset | irq_state[0];\n\t\t\t\t\telse\n\t\t\t\t\t\tlatched_rd <= irq_state[0] ? 4 : 3;\n\t\t\t\tend else\n\t\t\t\tif (ENABLE_IRQ && (decoder_trigger || do_waitirq) && instr_waitirq) begin\n\t\t\t\t\tif (irq_pending) begin\n\t\t\t\t\t\tlatched_store <= 1;\n\t\t\t\t\t\treg_out <= irq_pending;\n\t\t\t\t\t\treg_next_pc <= current_pc + (compressed_instr ? 2 : 4);\n\t\t\t\t\t\tmem_do_rinst <= 1;\n\t\t\t\t\tend else\n\t\t\t\t\t\tdo_waitirq <= 1;\n\t\t\t\tend else\n\t\t\t\tif (decoder_trigger) begin\n\t\t\t\t\t//`debug($display(\"-- %-0t\", $time);)\n\t\t\t\t\tirq_delay <= irq_active;\n\t\t\t\t\treg_next_pc <= current_pc + (compressed_instr ? 2 : 4);\n\t\t\t\t\tif (ENABLE_TRACE)\n\t\t\t\t\t\tlatched_trace <= 1;\n\t\t\t\t\tif (ENABLE_COUNTERS) begin\n\t\t\t\t\t\tcount_instr <= count_instr + 1;\n\t\t\t\t\t\tif (!ENABLE_COUNTERS64) count_instr[63:32] <= 0;\n\t\t\t\t\tend\n\t\t\t\t\tif (instr_jal) begin\n\t\t\t\t\t\tmem_do_rinst <= 1;\n\t\t\t\t\t\treg_next_pc <= current_pc + decoded_imm_uj;\n\t\t\t\t\t\tlatched_branch <= 1;\n\t\t\t\t\tend else begin\n\t\t\t\t\t\tmem_do_rinst <= 0;\n\t\t\t\t\t\tmem_do_prefetch <= !instr_jalr && !instr_retirq;\n\t\t\t\t\t\tcpu_state <= cpu_state_ld_rs1;\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\tend\n\n\t\t\tcpu_state_ld_rs1: begin\n\t\t\t\treg_op1 <= 'bx;\n\t\t\t\treg_op2 <= 'bx;\n\n\t\t\t\t(* parallel_case *)\n\t\t\t\tcase (1'b1)\n\t\t\t\t\t(CATCH_ILLINSN || WITH_PCPI) && instr_trap: begin\n\t\t\t\t\t\tif (WITH_PCPI) begin\n\t\t\t\t\t\t\t//`debug($display(\"LD_RS1: %2d 0x%08x\", decoded_rs1, cpuregs_rs1);)\n\t\t\t\t\t\t\treg_op1 <= cpuregs_rs1;\n\t\t\t\t\t\t\tdbg_rs1val <= cpuregs_rs1;\n\t\t\t\t\t\t\tdbg_rs1val_valid <= 1;\n\t\t\t\t\t\t\tif (ENABLE_REGS_DUALPORT) begin\n\t\t\t\t\t\t\t\tpcpi_valid_i <= 1;\n\t\t\t\t\t\t\t\t//`debug($display(\"LD_RS2: %2d 0x%08x\", decoded_rs2, cpuregs_rs2);)\n\t\t\t\t\t\t\t\treg_sh <= cpuregs_rs2;\n\t\t\t\t\t\t\t\treg_op2 <= cpuregs_rs2;\n\t\t\t\t\t\t\t\tdbg_rs2val <= cpuregs_rs2;\n\t\t\t\t\t\t\t\tdbg_rs2val_valid <= 1;\n\t\t\t\t\t\t\t\tif (pcpi_int_ready) begin\n\t\t\t\t\t\t\t\t\tmem_do_rinst <= 1;\n\t\t\t\t\t\t\t\t\tpcpi_valid_i <= 0;\n\t\t\t\t\t\t\t\t\treg_out <= pcpi_int_rd;\n\t\t\t\t\t\t\t\t\tlatched_store <= pcpi_int_wr;\n\t\t\t\t\t\t\t\t\tcpu_state <= cpu_state_fetch;\n\t\t\t\t\t\t\t\tend else\n\t\t\t\t\t\t\t\tif (CATCH_ILLINSN && (pcpi_timeout || instr_ecall_ebreak)) begin\n\t\t\t\t\t\t\t\t\tpcpi_valid_i <= 0;\n\t\t\t\t\t\t\t\t\t//`debug($display(\"EBREAK OR UNSUPPORTED INSN AT 0x%08x\", reg_pc);)\n\t\t\t\t\t\t\t\t\tif (ENABLE_IRQ && !irq_mask[irq_ebreak] && !irq_active) begin\n\t\t\t\t\t\t\t\t\t\tnext_irq_pending[irq_ebreak] = 1;\n\t\t\t\t\t\t\t\t\t\tcpu_state <= cpu_state_fetch;\n\t\t\t\t\t\t\t\t\tend else\n\t\t\t\t\t\t\t\t\t\tcpu_state <= cpu_state_trap;\n\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\tend else begin\n\t\t\t\t\t\t\t\tcpu_state <= cpu_state_ld_rs2;\n\t\t\t\t\t\t\tend\n\t\t\t\t\t\tend else begin\n\t\t\t\t\t\t\t//`debug($display(\"EBREAK OR UNSUPPORTED INSN AT 0x%08x\", reg_pc);)\n\t\t\t\t\t\t\tif (ENABLE_IRQ && !irq_mask[irq_ebreak] && !irq_active) begin\n\t\t\t\t\t\t\t\tnext_irq_pending[irq_ebreak] = 1;\n\t\t\t\t\t\t\t\tcpu_state <= cpu_state_fetch;\n\t\t\t\t\t\t\tend else\n\t\t\t\t\t\t\t\tcpu_state <= cpu_state_trap;\n\t\t\t\t\t\tend\n\t\t\t\t\tend\n\t\t\t\t\tENABLE_COUNTERS && is_rdcycle_rdcycleh_rdinstr_rdinstrh: begin\n\t\t\t\t\t\t(* parallel_case, full_case *)\n\t\t\t\t\t\tcase (1'b1)\n\t\t\t\t\t\t\tinstr_rdcycle:\n\t\t\t\t\t\t\t\treg_out <= count_cycle[31:0];\n\t\t\t\t\t\t\tinstr_rdcycleh && ENABLE_COUNTERS64:\n\t\t\t\t\t\t\t\treg_out <= count_cycle[63:32];\n\t\t\t\t\t\t\tinstr_rdinstr:\n\t\t\t\t\t\t\t\treg_out <= count_instr[31:0];\n\t\t\t\t\t\t\tinstr_rdinstrh && ENABLE_COUNTERS64:\n\t\t\t\t\t\t\t\treg_out <= count_instr[63:32];\n\t\t\t\t\t\tendcase\n\t\t\t\t\t\tlatched_store <= 1;\n\t\t\t\t\t\tcpu_state <= cpu_state_fetch;\n\t\t\t\t\tend\n\t\t\t\t\tis_lui_auipc_jal: begin\n\t\t\t\t\t\treg_op1 <= instr_lui ? 0 : reg_pc;\n\t\t\t\t\t\treg_op2 <= decoded_imm;\n\t\t\t\t\t\tif (TWO_CYCLE_ALU)\n\t\t\t\t\t\t\talu_wait <= 1;\n\t\t\t\t\t\telse\n\t\t\t\t\t\t\tmem_do_rinst <= mem_do_prefetch;\n\t\t\t\t\t\tcpu_state <= cpu_state_exec;\n\t\t\t\t\tend\n\t\t\t\t\tENABLE_IRQ && ENABLE_IRQ_QREGS && instr_getq: begin\n\t\t\t\t\t\t//`debug($display(\"LD_RS1: %2d 0x%08x\", decoded_rs1, cpuregs_rs1);)\n\t\t\t\t\t\treg_out <= cpuregs_rs1;\n\t\t\t\t\t\t//dbg_rs1val <= cpuregs_rs1;\n\t\t\t\t\t\t//dbg_rs1val_valid <= 1;\n\t\t\t\t\t\tlatched_store <= 1;\n\t\t\t\t\t\tcpu_state <= cpu_state_fetch;\n\t\t\t\t\tend\n\t\t\t\t\tENABLE_IRQ && ENABLE_IRQ_QREGS && instr_setq: begin\n\t\t\t\t\t\t//`debug($display(\"LD_RS1: %2d 0x%08x\", decoded_rs1, cpuregs_rs1);)\n\t\t\t\t\t\treg_out <= cpuregs_rs1;\n\t\t\t\t\t\t//dbg_rs1val <= cpuregs_rs1;\n\t\t\t\t\t\t//dbg_rs1val_valid <= 1;\n\t\t\t\t\t\tlatched_rd <= latched_rd | irqregs_offset;\n\t\t\t\t\t\tlatched_store <= 1;\n\t\t\t\t\t\tcpu_state <= cpu_state_fetch;\n\t\t\t\t\tend\n\t\t\t\t\tENABLE_IRQ && instr_retirq: begin\n\t\t\t\t\t\t//eoi <= 0;\n\t\t\t\t\t\tirq_active <= 0;\n\t\t\t\t\t\tlatched_branch <= 1;\n\t\t\t\t\t\tlatched_store <= 1;\n\t\t\t\t\t\t//`debug($display(\"LD_RS1: %2d 0x%08x\", decoded_rs1, cpuregs_rs1);)\n\t\t\t\t\t\treg_out <= CATCH_MISALIGN ? (cpuregs_rs1 & 32'h fffffffe) : cpuregs_rs1;\n\t\t\t\t\t\t//dbg_rs1val <= cpuregs_rs1;\n\t\t\t\t\t\t//dbg_rs1val_valid <= 1;\n\t\t\t\t\t\tcpu_state <= cpu_state_fetch;\n\t\t\t\t\tend\n\t\t\t\t\tENABLE_IRQ && instr_maskirq: begin\n\t\t\t\t\t\tlatched_store <= 1;\n\t\t\t\t\t\treg_out <= irq_mask;\n\t\t\t\t\t\t//`debug($display(\"LD_RS1: %2d 0x%08x\", decoded_rs1, cpuregs_rs1);)\n\t\t\t\t\t\tirq_mask <= cpuregs_rs1 | MASKED_IRQ;\n\t\t\t\t\t\t//dbg_rs1val <= cpuregs_rs1;\n\t\t\t\t\t\t//dbg_rs1val_valid <= 1;\n\t\t\t\t\t\tcpu_state <= cpu_state_fetch;\n\t\t\t\t\tend\n\t\t\t\t\tENABLE_IRQ && ENABLE_IRQ_TIMER && instr_timer: begin\n\t\t\t\t\t\tlatched_store <= 1;\n\t\t\t\t\t\treg_out <= timer;\n\t\t\t\t\t\t//`debug($display(\"LD_RS1: %2d 0x%08x\", decoded_rs1, cpuregs_rs1);)\n\t\t\t\t\t\ttimer <= cpuregs_rs1;\n\t\t\t\t\t\t//dbg_rs1val <= cpuregs_rs1;\n\t\t\t\t\t\t//dbg_rs1val_valid <= 1;\n\t\t\t\t\t\tcpu_state <= cpu_state_fetch;\n\t\t\t\t\tend\n\t\t\t\t\tis_lb_lh_lw_lbu_lhu && !instr_trap: begin\n\t\t\t\t\t\t//`debug($display(\"LD_RS1: %2d 0x%08x\", decoded_rs1, cpuregs_rs1);)\n\t\t\t\t\t\treg_op1 <= cpuregs_rs1;\n\t\t\t\t\t\t//dbg_rs1val <= cpuregs_rs1;\n\t\t\t\t\t\t//dbg_rs1val_valid <= 1;\n\t\t\t\t\t\tcpu_state <= cpu_state_ldmem;\n\t\t\t\t\t\tmem_do_rinst <= 1;\n\t\t\t\t\tend\n\t\t\t\t\tis_slli_srli_srai && !BARREL_SHIFTER: begin\n\t\t\t\t\t\t//`debug($display(\"LD_RS1: %2d 0x%08x\", decoded_rs1, cpuregs_rs1);)\n\t\t\t\t\t\treg_op1 <= cpuregs_rs1;\n\t\t\t\t\t\t//dbg_rs1val <= cpuregs_rs1;\n\t\t\t\t\t\t//dbg_rs1val_valid <= 1;\n\t\t\t\t\t\treg_sh <= decoded_rs2;\n\t\t\t\t\t\tcpu_state <= cpu_state_shift;\n\t\t\t\t\tend\n\t\t\t\t\tis_jalr_addi_slti_sltiu_xori_ori_andi, is_slli_srli_srai && BARREL_SHIFTER: begin\n\t\t\t\t\t\t//`debug($display(\"LD_RS1: %2d 0x%08x\", decoded_rs1, cpuregs_rs1);)\n\t\t\t\t\t\treg_op1 <= cpuregs_rs1;\n\t\t\t\t\t\t//dbg_rs1val <= cpuregs_rs1;\n\t\t\t\t\t\t//dbg_rs1val_valid <= 1;\n\t\t\t\t\t\treg_op2 <= is_slli_srli_srai && BARREL_SHIFTER ? decoded_rs2 : decoded_imm;\n\t\t\t\t\t\tif (TWO_CYCLE_ALU)\n\t\t\t\t\t\t\talu_wait <= 1;\n\t\t\t\t\t\telse\n\t\t\t\t\t\t\tmem_do_rinst <= mem_do_prefetch;\n\t\t\t\t\t\tcpu_state <= cpu_state_exec;\n\t\t\t\t\tend\n\t\t\t\t\tdefault: begin\n\t\t\t\t\t\t//`debug($display(\"LD_RS1: %2d 0x%08x\", decoded_rs1, cpuregs_rs1);)\n\t\t\t\t\t\treg_op1 <= cpuregs_rs1;\n\t\t\t\t\t\t//dbg_rs1val <= cpuregs_rs1;\n\t\t\t\t\t\t//dbg_rs1val_valid <= 1;\n\t\t\t\t\t\tif (ENABLE_REGS_DUALPORT) begin\n\t\t\t\t\t\t\t//`debug($display(\"LD_RS2: %2d 0x%08x\", decoded_rs2, cpuregs_rs2);)\n\t\t\t\t\t\t\treg_sh <= cpuregs_rs2;\n\t\t\t\t\t\t\treg_op2 <= cpuregs_rs2;\n\t\t\t\t\t\t\tdbg_rs2val <= cpuregs_rs2;\n\t\t\t\t\t\t\tdbg_rs2val_valid <= 1;\n\t\t\t\t\t\t\t(* parallel_case *)\n\t\t\t\t\t\t\tcase (1'b1)\n\t\t\t\t\t\t\t\tis_sb_sh_sw: begin\n\t\t\t\t\t\t\t\t\tcpu_state <= cpu_state_stmem;\n\t\t\t\t\t\t\t\t\tmem_do_rinst <= 1;\n\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\t\tis_sll_srl_sra && !BARREL_SHIFTER: begin\n\t\t\t\t\t\t\t\t\tcpu_state <= cpu_state_shift;\n\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\t\tdefault: begin\n\t\t\t\t\t\t\t\t\tif (TWO_CYCLE_ALU || (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu)) begin\n\t\t\t\t\t\t\t\t\t\talu_wait_2 <= TWO_CYCLE_ALU && (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu);\n\t\t\t\t\t\t\t\t\t\talu_wait <= 1;\n\t\t\t\t\t\t\t\t\tend else\n\t\t\t\t\t\t\t\t\t\tmem_do_rinst <= mem_do_prefetch;\n\t\t\t\t\t\t\t\t\tcpu_state <= cpu_state_exec;\n\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\tendcase\n\t\t\t\t\t\tend else\n\t\t\t\t\t\t\tcpu_state <= cpu_state_ld_rs2;\n\t\t\t\t\tend\n\t\t\t\tendcase\n\t\t\tend\n\n\t\t\tcpu_state_ld_rs2: begin\n\t\t\t\t//`debug($display(\"LD_RS2: %2d 0x%08x\", decoded_rs2, cpuregs_rs2);)\n\t\t\t\treg_sh <= cpuregs_rs2;\n\t\t\t\treg_op2 <= cpuregs_rs2;\n\t\t\t\tdbg_rs2val <= cpuregs_rs2;\n\t\t\t\tdbg_rs2val_valid <= 1;\n\n\t\t\t\t(* parallel_case *)\n\t\t\t\tcase (1'b1)\n\t\t\t\t\tWITH_PCPI && instr_trap: begin\n\t\t\t\t\t\tpcpi_valid_i <= 1;\n\t\t\t\t\t\tif (pcpi_int_ready) begin\n\t\t\t\t\t\t\tmem_do_rinst <= 1;\n\t\t\t\t\t\t\tpcpi_valid_i <= 0;\n\t\t\t\t\t\t\treg_out <= pcpi_int_rd;\n\t\t\t\t\t\t\tlatched_store <= pcpi_int_wr;\n\t\t\t\t\t\t\tcpu_state <= cpu_state_fetch;\n\t\t\t\t\t\tend else\n\t\t\t\t\t\tif (CATCH_ILLINSN && (pcpi_timeout || instr_ecall_ebreak)) begin\n\t\t\t\t\t\t\tpcpi_valid_i <= 0;\n\t\t\t\t\t\t\t//`debug($display(\"EBREAK OR UNSUPPORTED INSN AT 0x%08x\", reg_pc);)\n\t\t\t\t\t\t\tif (ENABLE_IRQ && !irq_mask[irq_ebreak] && !irq_active) begin\n\t\t\t\t\t\t\t\tnext_irq_pending[irq_ebreak] = 1;\n\t\t\t\t\t\t\t\tcpu_state <= cpu_state_fetch;\n\t\t\t\t\t\t\tend else\n\t\t\t\t\t\t\t\tcpu_state <= cpu_state_trap;\n\t\t\t\t\t\tend\n\t\t\t\t\tend\n\t\t\t\t\tis_sb_sh_sw: begin\n\t\t\t\t\t\tcpu_state <= cpu_state_stmem;\n\t\t\t\t\t\tmem_do_rinst <= 1;\n\t\t\t\t\tend\n\t\t\t\t\tis_sll_srl_sra && !BARREL_SHIFTER: begin\n\t\t\t\t\t\tcpu_state <= cpu_state_shift;\n\t\t\t\t\tend\n\t\t\t\t\tdefault: begin\n\t\t\t\t\t\tif (TWO_CYCLE_ALU || (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu)) begin\n\t\t\t\t\t\t\talu_wait_2 <= TWO_CYCLE_ALU && (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu);\n\t\t\t\t\t\t\talu_wait <= 1;\n\t\t\t\t\t\tend else\n\t\t\t\t\t\t\tmem_do_rinst <= mem_do_prefetch;\n\t\t\t\t\t\tcpu_state <= cpu_state_exec;\n\t\t\t\t\tend\n\t\t\t\tendcase\n\t\t\tend\n\n\t\t\tcpu_state_exec: begin\n\t\t\t\treg_out <= reg_pc + decoded_imm;\n\t\t\t\tif ((TWO_CYCLE_ALU || TWO_CYCLE_COMPARE) && (alu_wait || alu_wait_2)) begin\n\t\t\t\t\tmem_do_rinst <= mem_do_prefetch && !alu_wait_2;\n\t\t\t\t\talu_wait <= alu_wait_2;\n\t\t\t\tend else\n\t\t\t\tif (is_beq_bne_blt_bge_bltu_bgeu) begin\n\t\t\t\t\tlatched_rd <= 0;\n\t\t\t\t\tlatched_store <= TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0;\n\t\t\t\t\tlatched_branch <= TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0;\n\t\t\t\t\tif (mem_done)\n\t\t\t\t\t\tcpu_state <= cpu_state_fetch;\n\t\t\t\t\tif (TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0) begin\n\t\t\t\t\t\tdecoder_trigger <= 0;\n\t\t\t\t\t\tset_mem_do_rinst = 1;\n\t\t\t\t\tend\n\t\t\t\tend else begin\n\t\t\t\t\tlatched_branch <= instr_jalr;\n\t\t\t\t\tlatched_store <= 1;\n\t\t\t\t\tlatched_stalu <= 1;\n\t\t\t\t\tcpu_state <= cpu_state_fetch;\n\t\t\t\tend\n\t\t\tend\n\n\t\t\tcpu_state_shift: begin\n\t\t\t\tlatched_store <= 1;\n\t\t\t\tif (reg_sh == 0) begin\n\t\t\t\t\treg_out <= reg_op1;\n\t\t\t\t\tmem_do_rinst <= mem_do_prefetch;\n\t\t\t\t\tcpu_state <= cpu_state_fetch;\n\t\t\t\tend else if (TWO_STAGE_SHIFT && reg_sh >= 4) begin\n\t\t\t\t\t(* parallel_case, full_case *)\n\t\t\t\t\tcase (1'b1)\n\t\t\t\t\t\tinstr_slli || instr_sll: reg_op1 <= reg_op1 << 4;\n\t\t\t\t\t\tinstr_srli || instr_srl: reg_op1 <= reg_op1 >> 4;\n\t\t\t\t\t\tinstr_srai || instr_sra: reg_op1 <= $signed(reg_op1) >>> 4;\n\t\t\t\t\tendcase\n\t\t\t\t\treg_sh <= reg_sh - 4;\n\t\t\t\tend else begin\n\t\t\t\t\t(* parallel_case, full_case *)\n\t\t\t\t\tcase (1'b1)\n\t\t\t\t\t\tinstr_slli || instr_sll: reg_op1 <= reg_op1 << 1;\n\t\t\t\t\t\tinstr_srli || instr_srl: reg_op1 <= reg_op1 >> 1;\n\t\t\t\t\t\tinstr_srai || instr_sra: reg_op1 <= $signed(reg_op1) >>> 1;\n\t\t\t\t\tendcase\n\t\t\t\t\treg_sh <= reg_sh - 1;\n\t\t\t\tend\n\t\t\tend\n\n\t\t\tcpu_state_stmem: begin\n\t\t\t\tif (ENABLE_TRACE)\n\t\t\t\t\treg_out <= reg_op2;\n\t\t\t\tif (!mem_do_prefetch || mem_done) begin\n\t\t\t\t\tif (!mem_do_wdata) begin\n\t\t\t\t\t\t(* parallel_case, full_case *)\n\t\t\t\t\t\tcase (1'b1)\n\t\t\t\t\t\t\tinstr_sb: mem_wordsize <= 2;\n\t\t\t\t\t\t\tinstr_sh: mem_wordsize <= 1;\n\t\t\t\t\t\t\tinstr_sw: mem_wordsize <= 0;\n\t\t\t\t\t\tendcase\n\t\t\t\t\t\tif (ENABLE_TRACE) begin\n\t\t\t\t\t\t\ttrace_valid <= 1;\n\t\t\t\t\t\t\ttrace_data <= (irq_active ? TRACE_IRQ : 0) | TRACE_ADDR | ((reg_op1 + decoded_imm) & 32'hffffffff);\n\t\t\t\t\t\tend\n\t\t\t\t\t\treg_op1 <= reg_op1 + decoded_imm;\n\t\t\t\t\t\tset_mem_do_wdata = 1;\n\t\t\t\t\tend\n\t\t\t\t\tif (!mem_do_prefetch && mem_done) begin\n\t\t\t\t\t\tcpu_state <= cpu_state_fetch;\n\t\t\t\t\t\tdecoder_trigger <= 1;\n\t\t\t\t\t\tdecoder_pseudo_trigger <= 1;\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\tend\n\n\t\t\tcpu_state_ldmem: begin\n\t\t\t\tlatched_store <= 1;\n\t\t\t\tif (!mem_do_prefetch || mem_done) begin\n\t\t\t\t\tif (!mem_do_rdata) begin\n\t\t\t\t\t\t(* parallel_case, full_case *)\n\t\t\t\t\t\tcase (1'b1)\n\t\t\t\t\t\t\tinstr_lb || instr_lbu: mem_wordsize <= 2;\n\t\t\t\t\t\t\tinstr_lh || instr_lhu: mem_wordsize <= 1;\n\t\t\t\t\t\t\tinstr_lw: mem_wordsize <= 0;\n\t\t\t\t\t\tendcase\n\t\t\t\t\t\tlatched_is_lu <= is_lbu_lhu_lw;\n\t\t\t\t\t\tlatched_is_lh <= instr_lh;\n\t\t\t\t\t\tlatched_is_lb <= instr_lb;\n\t\t\t\t\t\tif (ENABLE_TRACE) begin\n\t\t\t\t\t\t\ttrace_valid <= 1;\n\t\t\t\t\t\t\ttrace_data <= (irq_active ? TRACE_IRQ : 0) | TRACE_ADDR | ((reg_op1 + decoded_imm) & 32'hffffffff);\n\t\t\t\t\t\tend\n\t\t\t\t\t\treg_op1 <= reg_op1 + decoded_imm;\n\t\t\t\t\t\tset_mem_do_rdata = 1;\n\t\t\t\t\tend\n\t\t\t\t\tif (!mem_do_prefetch && mem_done) begin\n\t\t\t\t\t\t(* parallel_case, full_case *)\n\t\t\t\t\t\tcase (1'b1)\n\t\t\t\t\t\t\tlatched_is_lu: reg_out <= mem_rdata_word;\n\t\t\t\t\t\t\tlatched_is_lh: reg_out <= $signed(mem_rdata_word[15:0]);\n\t\t\t\t\t\t\tlatched_is_lb: reg_out <= $signed(mem_rdata_word[7:0]);\n\t\t\t\t\t\tendcase\n\t\t\t\t\t\tdecoder_trigger <= 1;\n\t\t\t\t\t\tdecoder_pseudo_trigger <= 1;\n\t\t\t\t\t\tcpu_state <= cpu_state_fetch;\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\tend\n\t\tendcase\n\n\t\tif (CATCH_MISALIGN && resetn && (mem_do_rdata || mem_do_wdata)) begin\n\t\t\tif (mem_wordsize == 0 && reg_op1[1:0] != 0) begin\n\t\t\t\t//`debug($display(\"MISALIGNED WORD: 0x%08x\", reg_op1);)\n\t\t\t\tif (ENABLE_IRQ && !irq_mask[irq_buserror] && !irq_active) begin\n\t\t\t\t\tnext_irq_pending[irq_buserror] = 1;\n\t\t\t\tend else\n\t\t\t\t\tcpu_state <= cpu_state_trap;\n\t\t\tend\n\t\t\tif (mem_wordsize == 1 && reg_op1[0] != 0) begin\n\t\t\t\t//`debug($display(\"MISALIGNED HALFWORD: 0x%08x\", reg_op1);)\n\t\t\t\tif (ENABLE_IRQ && !irq_mask[irq_buserror] && !irq_active) begin\n\t\t\t\t\tnext_irq_pending[irq_buserror] = 1;\n\t\t\t\tend else\n\t\t\t\t\tcpu_state <= cpu_state_trap;\n\t\t\tend\n\t\tend\n\t\tif (CATCH_MISALIGN && resetn && mem_do_rinst && (COMPRESSED_ISA ? reg_pc[0] : |reg_pc[1:0])) begin\n\t\t\t//`debug($display(\"MISALIGNED INSTRUCTION: 0x%08x\", reg_pc);)\n\t\t\tif (ENABLE_IRQ && !irq_mask[irq_buserror] && !irq_active) begin\n\t\t\t\tnext_irq_pending[irq_buserror] = 1;\n\t\t\tend else\n\t\t\t\tcpu_state <= cpu_state_trap;\n\t\tend\n\t\tif (!CATCH_ILLINSN && decoder_trigger_q && !decoder_pseudo_trigger_q && instr_ecall_ebreak) begin\n\t\t\tcpu_state <= cpu_state_trap;\n\t\tend\n\n\t\tif (!resetn || mem_done) begin\n\t\t\tmem_do_prefetch <= 0;\n\t\t\tmem_do_rinst <= 0;\n\t\t\tmem_do_rdata <= 0;\n\t\t\tmem_do_wdata <= 0;\n\t\tend\n\n\t\tif (set_mem_do_rinst)\n\t\t\tmem_do_rinst <= 1;\n\t\tif (set_mem_do_rdata)\n\t\t\tmem_do_rdata <= 1;\n\t\tif (set_mem_do_wdata)\n\t\t\tmem_do_wdata <= 1;\n\n\t\tirq_pending <= next_irq_pending & ~MASKED_IRQ;\n\n\t\tif (!CATCH_MISALIGN) begin\n\t\t\tif (COMPRESSED_ISA) begin\n\t\t\t\treg_pc[0] <= 0;\n\t\t\t\treg_next_pc[0] <= 0;\n\t\t\tend else begin\n\t\t\t\treg_pc[1:0] <= 0;\n\t\t\t\treg_next_pc[1:0] <= 0;\n\t\t\tend\n\t\tend\n\t\tcurrent_pc = 'bx;\n\tend\n\n`ifdef RISCV_FORMAL\n\treg dbg_irq_call;\n\treg dbg_irq_enter;\n\treg [31:0] dbg_irq_ret;\n\talways @(posedge clk) begin\n\t\trvfi_valid <= resetn && (launch_next_insn || trap) && dbg_valid_insn;\n\t\trvfi_order <= resetn ? rvfi_order + rvfi_valid : 0;\n\n\t\trvfi_insn <= dbg_insn_opcode;\n\t\trvfi_rs1_addr <= dbg_rs1val_valid ? dbg_insn_rs1 : 0;\n\t\trvfi_rs2_addr <= dbg_rs2val_valid ? dbg_insn_rs2 : 0;\n\t\trvfi_pc_rdata <= dbg_insn_addr;\n\t\trvfi_rs1_rdata <= dbg_rs1val_valid ? dbg_rs1val : 0;\n\t\trvfi_rs2_rdata <= dbg_rs2val_valid ? dbg_rs2val : 0;\n\t\trvfi_trap <= trap;\n\t\trvfi_halt <= trap;\n\t\trvfi_intr <= dbg_irq_enter;\n\t\trvfi_mode <= 3;\n\n\t\tif (!resetn) begin\n\t\t\tdbg_irq_call <= 0;\n\t\t\tdbg_irq_enter <= 0;\n\t\tend else\n\t\tif (rvfi_valid) begin\n\t\t\tdbg_irq_call <= 0;\n\t\t\tdbg_irq_enter <= dbg_irq_call;\n\t\tend else\n\t\tif (irq_state == 1) begin\n\t\t\tdbg_irq_call <= 1;\n\t\t\tdbg_irq_ret <= next_pc;\n\t\tend\n\n\t\tif (!resetn) begin\n\t\t\trvfi_rd_addr <= 0;\n\t\t\trvfi_rd_wdata <= 0;\n\t\tend else\n\t\tif (cpuregs_write && !irq_state) begin\n\t\t\trvfi_rd_addr <= latched_rd;\n\t\t\trvfi_rd_wdata <= latched_rd ? cpuregs_wrdata_i : 0;\n\t\tend else\n\t\tif (rvfi_valid) begin\n\t\t\trvfi_rd_addr <= 0;\n\t\t\trvfi_rd_wdata <= 0;\n\t\tend\n\n\t\tcasez (dbg_insn_opcode)\n\t\t\t32'b 0000000_?????_000??_???_?????_0001011: begin // getq\n\t\t\t\trvfi_rs1_addr <= 0;\n\t\t\t\trvfi_rs1_rdata <= 0;\n\t\t\tend\n\t\t\t32'b 0000001_?????_?????_???_000??_0001011: begin // setq\n\t\t\t\trvfi_rd_addr <= 0;\n\t\t\t\trvfi_rd_wdata <= 0;\n\t\t\tend\n\t\t\t32'b 0000010_?????_00000_???_00000_0001011: begin // retirq\n\t\t\t\trvfi_rs1_addr <= 0;\n\t\t\t\trvfi_rs1_rdata <= 0;\n\t\t\tend\n\t\tendcase\n\n\t\tif (!dbg_irq_call) begin\n\t\t\tif (dbg_mem_instr) begin\n\t\t\t\trvfi_mem_addr <= 0;\n\t\t\t\trvfi_mem_rmask <= 0;\n\t\t\t\trvfi_mem_wmask <= 0;\n\t\t\t\trvfi_mem_rdata <= 0;\n\t\t\t\trvfi_mem_wdata <= 0;\n\t\t\tend else\n\t\t\tif (dbg_mem_valid && dbg_mem_ready) begin\n\t\t\t\trvfi_mem_addr <= dbg_mem_addr;\n\t\t\t\trvfi_mem_rmask <= dbg_mem_wstrb ? 0 : ~0;\n\t\t\t\trvfi_mem_wmask <= dbg_mem_wstrb;\n\t\t\t\trvfi_mem_rdata <= dbg_mem_rdata;\n\t\t\t\trvfi_mem_wdata <= dbg_mem_wdata;\n\t\t\tend\n\t\tend\n\tend\n\n\talways @* begin\n\t\trvfi_pc_wdata = dbg_irq_call ? dbg_irq_ret : dbg_insn_addr;\n\tend\n`endif\n\n\t// Formal Verification\n`ifdef FORMAL\n\treg [3:0] last_mem_nowait;\n\talways @(posedge clk)\n\t\tlast_mem_nowait <= {last_mem_nowait, mem_ready || !mem_valid_i};\n\n\t// stall the memory interface for max 4 cycles\n\trestrict property (|last_mem_nowait || mem_ready || !mem_valid_i);\n\n\t// resetn low in first cycle, after that resetn high\n\trestrict property (resetn != $initstate);\n\n\t// this just makes it much easier to read traces. uncomment as needed.\n\t// assume property (mem_valid || !mem_ready);\n\n\treg ok;\n\talways @* begin\n\t\tif (resetn) begin\n\t\t\t// instruction fetches are read-only\n\t\t\tif (mem_valid_i && mem_instr_i)\n\t\t\t\tassert (mem_wstrb_i == 0);\n\n\t\t\t// cpu_state must be valid\n\t\t\tok = 0;\n\t\t\tif (cpu_state == cpu_state_trap)   ok = 1;\n\t\t\tif (cpu_state == cpu_state_fetch)  ok = 1;\n\t\t\tif (cpu_state == cpu_state_ld_rs1) ok = 1;\n\t\t\tif (cpu_state == cpu_state_ld_rs2) ok = !ENABLE_REGS_DUALPORT;\n\t\t\tif (cpu_state == cpu_state_exec)   ok = 1;\n\t\t\tif (cpu_state == cpu_state_shift)  ok = 1;\n\t\t\tif (cpu_state == cpu_state_stmem)  ok = 1;\n\t\t\tif (cpu_state == cpu_state_ldmem)  ok = 1;\n\t\t\tassert (ok);\n\t\tend\n\tend\n\n\treg last_mem_la_read = 0;\n\treg last_mem_la_write = 0;\n\treg [31:0] last_mem_la_addr;\n\treg [31:0] last_mem_la_wdata;\n\treg [3:0] last_mem_la_wstrb = 0;\n\n\talways @(posedge clk) begin\n\t\tlast_mem_la_read <= mem_la_read;\n\t\tlast_mem_la_write <= mem_la_write;\n\t\tlast_mem_la_addr <= mem_la_addr;\n\t\tlast_mem_la_wdata <= mem_la_wdata;\n\t\tlast_mem_la_wstrb <= mem_la_wstrb;\n\n\t\tif (last_mem_la_read) begin\n\t\t\tassert(mem_valid_i);\n\t\t\tassert(mem_addr_i == last_mem_la_addr);\n\t\t\tassert(mem_wstrb_i == 0);\n\t\tend\n\t\tif (last_mem_la_write) begin\n\t\t\tassert(mem_valid_i);\n\t\t\tassert(mem_addr_i == last_mem_la_addr);\n\t\t\tassert(mem_wdata_i == last_mem_la_wdata);\n\t\t\tassert(mem_wstrb_i == last_mem_la_wstrb);\n\t\tend\n\t\tif (mem_la_read || mem_la_write) begin\n\t\t\tassert(!mem_valid_i || mem_ready);\n\t\tend\n\tend\n`endif\n",
                "params": [],
                "ports": {
                  "in": [
                    {
                      "name": "clk"
                    },
                    {
                      "name": "resetn"
                    },
                    {
                      "name": "mem_ready"
                    },
                    {
                      "name": "mem_rdata",
                      "range": "[31:0]",
                      "size": 32
                    },
                    {
                      "name": "irq",
                      "range": "[31:0]",
                      "size": 32
                    },
                    {
                      "name": "cpuregs_rdata1",
                      "range": "[31:0]",
                      "size": 32
                    },
                    {
                      "name": "cpuregs_rdata2",
                      "range": "[31:0]",
                      "size": 32
                    },
                    {
                      "name": "pcpi_mul_wr"
                    },
                    {
                      "name": "pcpi_mul_rd",
                      "range": "[31:0]",
                      "size": 32
                    },
                    {
                      "name": "pcpi_mul_wait"
                    },
                    {
                      "name": "pcpi_mul_ready"
                    },
                    {
                      "name": "pcpi_div_wr"
                    },
                    {
                      "name": "pcpi_div_rd",
                      "range": "[31:0]",
                      "size": 32
                    },
                    {
                      "name": "pcpi_div_wait"
                    },
                    {
                      "name": "pcpi_div_ready"
                    }
                  ],
                  "out": [
                    {
                      "name": "mem_valid"
                    },
                    {
                      "name": "mem_instr"
                    },
                    {
                      "name": "mem_addr",
                      "range": "[31:0]",
                      "size": 32
                    },
                    {
                      "name": "mem_wdata",
                      "range": "[31:0]",
                      "size": 32
                    },
                    {
                      "name": "mem_wstrb",
                      "range": "[3:0]",
                      "size": 4
                    },
                    {
                      "name": "cpuregs_wen"
                    },
                    {
                      "name": "cpuregs_waddr",
                      "range": "[5:0]",
                      "size": 6
                    },
                    {
                      "name": "cpuregs_raddr1",
                      "range": "[5:0]",
                      "size": 6
                    },
                    {
                      "name": "cpuregs_raddr2",
                      "range": "[5:0]",
                      "size": 6
                    },
                    {
                      "name": "cpuregs_wrdata",
                      "range": "[31:0]",
                      "size": 32
                    },
                    {
                      "name": "pcpi_valid"
                    },
                    {
                      "name": "pcpi_insn",
                      "range": "[31:0]",
                      "size": 32
                    },
                    {
                      "name": "pcpi_rs1",
                      "range": "[31:0]",
                      "size": 32
                    },
                    {
                      "name": "pcpi_rs2",
                      "range": "[31:0]",
                      "size": 32
                    }
                  ]
                }
              },
              "position": {
                "x": 432,
                "y": 64
              },
              "size": {
                "width": 632,
                "height": 976
              }
            }
          ],
          "wires": [
            {
              "source": {
                "block": "672f3db4-2c47-414c-86f7-aa09c1e78d3e",
                "port": "mem_valid"
              },
              "target": {
                "block": "185eb5c9-699b-4d16-aea4-750005ea6c2a",
                "port": "inlabel"
              },
              "vertices": []
            },
            {
              "source": {
                "block": "672f3db4-2c47-414c-86f7-aa09c1e78d3e",
                "port": "mem_instr"
              },
              "target": {
                "block": "b3d70b47-fb3a-4f8b-a82e-ddc9ab4ba29e",
                "port": "inlabel"
              },
              "vertices": []
            },
            {
              "source": {
                "block": "672f3db4-2c47-414c-86f7-aa09c1e78d3e",
                "port": "mem_addr",
                "size": 32
              },
              "target": {
                "block": "e4be38e3-3408-4ec9-a593-23b12d220a67",
                "port": "inlabel"
              },
              "vertices": [],
              "size": 32
            },
            {
              "source": {
                "block": "672f3db4-2c47-414c-86f7-aa09c1e78d3e",
                "port": "mem_wdata",
                "size": 32
              },
              "target": {
                "block": "f80e9ba7-0cf3-4672-9262-c2ca8e891b19",
                "port": "inlabel"
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              "vertices": [],
              "size": 32
            },
            {
              "source": {
                "block": "672f3db4-2c47-414c-86f7-aa09c1e78d3e",
                "port": "mem_wstrb",
                "size": 4
              },
              "target": {
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                "port": "inlabel"
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              "vertices": [],
              "size": 4
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              "source": {
                "block": "672f3db4-2c47-414c-86f7-aa09c1e78d3e",
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                "size": 6
              },
              "target": {
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                "port": "inlabel"
              },
              "vertices": [],
              "size": 6
            },
            {
              "source": {
                "block": "672f3db4-2c47-414c-86f7-aa09c1e78d3e",
                "port": "cpuregs_raddr1",
                "size": 6
              },
              "target": {
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                "port": "inlabel"
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              "vertices": [],
              "size": 6
            },
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              "source": {
                "block": "672f3db4-2c47-414c-86f7-aa09c1e78d3e",
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                "size": 6
              },
              "target": {
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                "port": "inlabel"
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              "vertices": [],
              "size": 6
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                "block": "672f3db4-2c47-414c-86f7-aa09c1e78d3e",
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                "size": 32
              },
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                "port": "cpuregs_wen"
              },
              "target": {
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                "port": "inlabel"
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              "vertices": []
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                "block": "fec03309-ca41-4ff1-83b2-b5e6b9ee8003",
                "port": "outlabel"
              },
              "target": {
                "block": "672f3db4-2c47-414c-86f7-aa09c1e78d3e",
                "port": "mem_ready"
              },
              "vertices": []
            },
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                "port": "outlabel"
              },
              "target": {
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                "port": "mem_rdata",
                "size": 32
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              "vertices": [],
              "size": 32
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              "target": {
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                "port": "irq",
                "size": 32
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              "size": 32
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              "target": {
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                "size": 32
              },
              "vertices": [],
              "size": 32
            },
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              "target": {
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              },
              "vertices": [],
              "size": 32
            },
            {
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                "port": "out"
              },
              "target": {
                "block": "ccfac857-0e6a-40b7-a96c-fc2c2e0161ad",
                "port": "inlabel"
              }
            },
            {
              "source": {
                "block": "2a9d46d9-e252-4b8c-bc32-7e4ab786fe8a",
                "port": "outlabel"
              },
              "target": {
                "block": "672f3db4-2c47-414c-86f7-aa09c1e78d3e",
                "port": "clk"
              }
            },
            {
              "source": {
                "block": "cc797022-1c90-4469-a646-c1c31ed014fe",
                "port": "out"
              },
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                "port": "outlabel"
              },
              "target": {
                "block": "672f3db4-2c47-414c-86f7-aa09c1e78d3e",
                "port": "resetn"
              }
            },
            {
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                "port": "out"
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              }
            },
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                "port": "out",
                "size": 32
              },
              "target": {
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                "port": "inlabel"
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              "size": 32
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            {
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                "port": "out",
                "size": 32
              },
              "target": {
                "block": "94d9d28f-d68f-44ee-8329-d30493df2829",
                "port": "inlabel"
              },
              "size": 32
            },
            {
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                "port": "outlabel"
              },
              "target": {
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                "port": "in"
              }
            },
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                "port": "outlabel"
              },
              "target": {
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              }
            },
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              },
              "target": {
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                "port": "in",
                "size": 32
              },
              "size": 32
            },
            {
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                "port": "outlabel"
              },
              "target": {
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                "port": "in",
                "size": 32
              },
              "size": 32
            },
            {
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                "block": "7b62b745-c8fa-4c1e-b7dd-efeff07d7654",
                "port": "outlabel"
              },
              "target": {
                "block": "956b95fb-48bc-4273-bc3f-d9b6cffeaa9e",
                "port": "in",
                "size": 4
              },
              "size": 4
            },
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                "info": "## Rising edge detector\n\nIt generates a 1-period pulse (tic) when a rising edge is detected on the  \ninput signal",
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                "code": "reg [31:0] rdata_i;\nassign rdata = rdata_i;\nreg        xfer_resetn_i;\nassign xfer_resetn = xfer_resetn_i;\n\treg        din_valid_i;\n    assign din_valid = din_valid_i;\n\treg  [7:0] din_data_i;\n    assign din_data = din_data_i;\n\treg  [3:0] din_tag_i;\n    assign din_tag = din_tag_i;\n\treg        din_cont_i;\n    assign din_tag = din_tag_i;\n\treg        din_qspi_i;\n    assign din_qspi = din_qspi_i;\n\treg        din_ddr;\n\treg        din_rd_i;\n    assign din_rd = din_rd_i;\n\nwire       dout_valid_i;\nassign dout_valid = dout_valid_i;\n\twire [7:0] dout_data_i;\n    assign dout_data = dout_data_i;\n\twire [3:0] dout_tag_i;\n    assign dout_tag = dout_tag_i;\n\n\treg [23:0] buffer;\n\n\treg [23:0] rd_addr;\n\treg rd_valid;\n\treg rd_wait;\n\treg rd_inc;\n\n\tassign ready = valid && (addr == rd_addr) && rd_valid;\n\twire jump = valid && !ready && (addr != rd_addr+4) && rd_valid;\n\n\treg softreset;\n\n\treg       config_en;      // cfgreg[31]\n\treg       config_ddr;     // cfgreg[22]\n\treg       config_qspi;    // cfgreg[21]\n\treg       config_cont;    // cfgreg[20]\n\treg [3:0] config_dummy;   // cfgreg[19:16]\n\treg [3:0] config_oe;      // cfgreg[11:8]\n\treg       config_csb;     // cfgreg[5]\n\treg       config_clk;     // cfgref[4]\n\treg [3:0] config_do;      // cfgreg[3:0]\n\n\tassign cfgreg_do[31] = config_en;\n\tassign cfgreg_do[30:23] = 0;\n\tassign cfgreg_do[22] = config_ddr;\n\tassign cfgreg_do[21] = config_qspi;\n\tassign cfgreg_do[20] = config_cont;\n\tassign cfgreg_do[19:16] = config_dummy;\n\tassign cfgreg_do[15:12] = 0;\n\tassign cfgreg_do[11:8] = {1'b0, 1'b0, flash_io1_oe, flash_io0_oe};\n\tassign cfgreg_do[7:6] = 0;\n\tassign cfgreg_do[5] = flash_csb;\n\tassign cfgreg_do[4] = flash_clk;\n\tassign cfgreg_do[3:0] = {1'b0, 1'b0, flash_io1_di, flash_io0_di};\n\n\talways @(posedge clk) begin\n\t\tsoftreset <= !config_en || cfgreg_we;\n\t\tif (!resetn) begin\n\t\t\tsoftreset <= 1;\n\t\t\tconfig_en <= 1;\n\t\t\tconfig_csb <= 0;\n\t\t\tconfig_clk <= 0;\n\t\t\tconfig_oe <= 0;\n\t\t\tconfig_do <= 0;\n\t\t\tconfig_ddr <= 0;\n\t\t\tconfig_qspi <= 0;\n\t\t\tconfig_cont <= 0;\n\t\t\tconfig_dummy <= 8;\n\t\tend else begin\n\t\t\tif (cfgreg_we[0]) begin\n\t\t\t\tconfig_csb <= cfgreg_di[5];\n\t\t\t\tconfig_clk <= cfgreg_di[4];\n\t\t\t\tconfig_do <= cfgreg_di[3:0];\n\t\t\tend\n\t\t\tif (cfgreg_we[1]) begin\n\t\t\t\tconfig_oe <= cfgreg_di[11:8];\n\t\t\tend\n\t\t\tif (cfgreg_we[2]) begin\n\t\t\t\tconfig_ddr <= cfgreg_di[22];\n\t\t\t\tconfig_qspi <= cfgreg_di[21];\n\t\t\t\tconfig_cont <= cfgreg_di[20];\n\t\t\t\tconfig_dummy <= cfgreg_di[19:16];\n\t\t\tend\n\t\t\tif (cfgreg_we[3]) begin\n\t\t\t\tconfig_en <= cfgreg_di[31];\n\t\t\tend\n\t\tend\n\tend\n\n\t\n\twire xfer_io2_oe;\n\twire xfer_io3_oe;\n\n\t\n\twire xfer_io2_do;\n\twire xfer_io3_do;\n\n\treg xfer_io0_90;\n\treg xfer_io1_90;\n\treg xfer_io2_90;\n\treg xfer_io3_90;\n\n\talways @(negedge clk) begin\n\t\txfer_io0_90 <= xfer_io0_do;\n\t\txfer_io1_90 <= xfer_io1_do;\n\t\txfer_io2_90 <= xfer_io2_do;\n\t\txfer_io3_90 <= xfer_io3_do;\n\tend\n\n\tassign flash_csb = config_en ? xfer_csb : config_csb;\n\tassign flash_clk = config_en ? xfer_clk : config_clk;\n\n\tassign flash_io0_oe = config_en ? xfer_io0_oe : config_oe[0];\n\tassign flash_io1_oe = config_en ? xfer_io1_oe : config_oe[1];\n\t//assign flash_io2_oe = config_en ? xfer_io2_oe : config_oe[2];\n\t//assign flash_io3_oe = config_en ? xfer_io3_oe : config_oe[3];\n\n\tassign flash_io0_do = config_en ? (config_ddr ? xfer_io0_90 : xfer_io0_do) : config_do[0];\n\tassign flash_io1_do = config_en ? (config_ddr ? xfer_io1_90 : xfer_io1_do) : config_do[1];\n\t//assign flash_io2_do = config_en ? (config_ddr ? xfer_io2_90 : xfer_io2_do) : config_do[2];\n\t//assign flash_io3_do = config_en ? (config_ddr ? xfer_io3_90 : xfer_io3_do) : config_do[3];\n\n\twire xfer_dspi_i = din_ddr && !din_qspi_i;\n    assign xfer_dspi = xfer_dspi_i;\n\twire xfer_ddr_i = din_ddr && din_qspi_i;\n    assign xfer_ddr = xfer_ddr_i;\n\n\treg [3:0] state;\n\n\talways @(posedge clk) begin\n\t\txfer_resetn_i <= 1;\n\t\tdin_valid_i <= 0;\n\n\t\tif (!resetn || softreset) begin\n\t\t\tstate <= 0;\n\t\t\txfer_resetn_i <= 0;\n\t\t\trd_valid <= 0;\n\t\t\tdin_tag_i <= 0;\n\t\t\tdin_cont_i <= 0;\n\t\t\tdin_qspi_i <= 0;\n\t\t\tdin_ddr <= 0;\n\t\t\tdin_rd_i <= 0;\n\t\tend else begin\n\t\t\tif (dout_valid_i && dout_tag_i == 1) buffer[ 7: 0] <= dout_data_i;\n\t\t\tif (dout_valid_i && dout_tag_i == 2) buffer[15: 8] <= dout_data_i;\n\t\t\tif (dout_valid_i && dout_tag_i == 3) buffer[23:16] <= dout_data_i;\n\t\t\tif (dout_valid_i && dout_tag_i == 4) begin\n\t\t\t\trdata_i <= {dout_data_i, buffer};\n\t\t\t\trd_addr <= rd_inc ? rd_addr + 4 : addr;\n\t\t\t\trd_valid <= 1;\n\t\t\t\trd_wait <= rd_inc;\n\t\t\t\trd_inc <= 1;\n\t\t\tend\n\n\t\t\tif (valid)\n\t\t\t\trd_wait <= 0;\n\n\t\t\tcase (state)\n\t\t\t\t0: begin\n\t\t\t\t\tdin_valid_i <= 1;\n\t\t\t\t\tdin_data_i <= 8'h ff;\n\t\t\t\t\tdin_tag_i <= 0;\n\t\t\t\t\tif (din_ready) begin\n\t\t\t\t\t\tdin_valid_i <= 0;\n\t\t\t\t\t\tstate <= 1;\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\t\t1: begin\n\t\t\t\t\tif (dout_valid_i) begin\n\t\t\t\t\t\txfer_resetn_i <= 0;\n\t\t\t\t\t\tstate <= 2;\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\t\t2: begin\n\t\t\t\t\tdin_valid_i <= 1;\n\t\t\t\t\tdin_data_i <= 8'h ab;\n\t\t\t\t\tdin_tag_i <= 0;\n\t\t\t\t\tif (din_ready) begin\n\t\t\t\t\t\tdin_valid_i <= 0;\n\t\t\t\t\t\tstate <= 3;\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\t\t3: begin\n\t\t\t\t\tif (dout_valid_i) begin\n\t\t\t\t\t\txfer_resetn_i <= 0;\n\t\t\t\t\t\tstate <= 4;\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\t\t4: begin\n\t\t\t\t\trd_inc <= 0;\n\t\t\t\t\tdin_valid_i <= 1;\n\t\t\t\t\tdin_tag_i <= 0;\n\t\t\t\t\tcase ({config_ddr, config_qspi})\n\t\t\t\t\t\t2'b11: din_data_i <= 8'h ED;\n\t\t\t\t\t\t2'b01: din_data_i <= 8'h EB;\n\t\t\t\t\t\t2'b10: din_data_i <= 8'h BB;\n\t\t\t\t\t\t2'b00: din_data_i <= 8'h 03;\n\t\t\t\t\tendcase\n\t\t\t\t\tif (din_ready) begin\n\t\t\t\t\t\tdin_valid_i <= 0;\n\t\t\t\t\t\tstate <= 5;\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\t\t5: begin\n\t\t\t\t\tif (valid && !ready) begin\n\t\t\t\t\t\tdin_valid_i <= 1;\n\t\t\t\t\t\tdin_tag_i <= 0;\n\t\t\t\t\t\tdin_data_i <= addr[23:16];\n\t\t\t\t\t\tdin_qspi_i <= config_qspi;\n\t\t\t\t\t\tdin_ddr <= config_ddr;\n\t\t\t\t\t\tif (din_ready) begin\n\t\t\t\t\t\t\tdin_valid_i <= 0;\n\t\t\t\t\t\t\tstate <= 6;\n\t\t\t\t\t\tend\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\t\t6: begin\n\t\t\t\t\tdin_valid_i <= 1;\n\t\t\t\t\tdin_tag_i <= 0;\n\t\t\t\t\tdin_data_i <= addr[15:8];\n\t\t\t\t\tif (din_ready) begin\n\t\t\t\t\t\tdin_valid_i <= 0;\n\t\t\t\t\t\tstate <= 7;\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\t\t7: begin\n\t\t\t\t\tdin_valid_i <= 1;\n\t\t\t\t\tdin_tag_i <= 0;\n\t\t\t\t\tdin_data_i <= addr[7:0];\n\t\t\t\t\tif (din_ready) begin\n\t\t\t\t\t\tdin_valid_i <= 0;\n\t\t\t\t\t\tdin_data_i <= 0;\n\t\t\t\t\t\tstate <= config_qspi || config_ddr ? 8 : 9;\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\t\t8: begin\n\t\t\t\t\tdin_valid_i <= 1;\n\t\t\t\t\tdin_tag_i <= 0;\n\t\t\t\t\tdin_data_i <= config_cont ? 8'h A5 : 8'h FF;\n\t\t\t\t\tif (din_ready) begin\n\t\t\t\t\t\tdin_rd_i <= 1;\n\t\t\t\t\t\tdin_data_i <= config_dummy;\n\t\t\t\t\t\tdin_valid_i <= 0;\n\t\t\t\t\t\tstate <= 9;\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\t\t9: begin\n\t\t\t\t\tdin_valid_i <= 1;\n\t\t\t\t\tdin_tag_i <= 1;\n\t\t\t\t\tif (din_ready) begin\n\t\t\t\t\t\tdin_valid_i <= 0;\n\t\t\t\t\t\tstate <= 10;\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\t\t10: begin\n\t\t\t\t\tdin_valid_i <= 1;\n\t\t\t\t\tdin_data_i <= 8'h 00;\n\t\t\t\t\tdin_tag_i <= 2;\n\t\t\t\t\tif (din_ready) begin\n\t\t\t\t\t\tdin_valid_i <= 0;\n\t\t\t\t\t\tstate <= 11;\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\t\t11: begin\n\t\t\t\t\tdin_valid_i <= 1;\n\t\t\t\t\tdin_tag_i <= 3;\n\t\t\t\t\tif (din_ready) begin\n\t\t\t\t\t\tdin_valid_i <= 0;\n\t\t\t\t\t\tstate <= 12;\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\t\t12: begin\n\t\t\t\t\tif (!rd_wait || valid) begin\n\t\t\t\t\t\tdin_valid_i <= 1;\n\t\t\t\t\t\tdin_tag_i <= 4;\n\t\t\t\t\t\tif (din_ready) begin\n\t\t\t\t\t\t\tdin_valid_i <= 0;\n\t\t\t\t\t\t\tstate <= 9;\n\t\t\t\t\t\tend\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\tendcase\n\n\t\t\tif (jump) begin\n\t\t\t\trd_inc <= 0;\n\t\t\t\trd_valid <= 0;\n\t\t\t\txfer_resetn_i <= 0;\n\t\t\t\tif (config_cont) begin\n\t\t\t\t\tstate <= 5;\n\t\t\t\tend else begin\n\t\t\t\t\tstate <= 4;\n\t\t\t\t\tdin_qspi_i <= 0;\n\t\t\t\t\tdin_ddr <= 0;\n\t\t\t\tend\n\t\t\t\tdin_rd_i <= 0;\n\t\t\tend\n\t\tend\n\tend",
                "params": [],
                "ports": {
                  "in": [
                    {
                      "name": "clk"
                    },
                    {
                      "name": "resetn"
                    },
                    {
                      "name": "valid"
                    },
                    {
                      "name": "addr",
                      "range": "[23:0]",
                      "size": 24
                    },
                    {
                      "name": "flash_io0_di"
                    },
                    {
                      "name": "flash_io1_di"
                    },
                    {
                      "name": "cfgreg_we",
                      "range": "[3:0]",
                      "size": 4
                    },
                    {
                      "name": "cfgreg_di",
                      "range": "[31:0]",
                      "size": 32
                    },
                    {
                      "name": "din_ready"
                    },
                    {
                      "name": "dout_valid"
                    },
                    {
                      "name": "dout_data",
                      "range": "[7:0]",
                      "size": 8
                    },
                    {
                      "name": "dout_tag",
                      "range": "[3:0]",
                      "size": 4
                    },
                    {
                      "name": "xfer_csb"
                    },
                    {
                      "name": "xfer_clk"
                    },
                    {
                      "name": "xfer_io0_oe"
                    },
                    {
                      "name": "xfer_io1_oe"
                    },
                    {
                      "name": "xfer_io0_do"
                    },
                    {
                      "name": "xfer_io1_do"
                    }
                  ],
                  "out": [
                    {
                      "name": "ready"
                    },
                    {
                      "name": "rdata",
                      "range": "[31:0]",
                      "size": 32
                    },
                    {
                      "name": "flash_csb"
                    },
                    {
                      "name": "flash_clk"
                    },
                    {
                      "name": "flash_io0_oe"
                    },
                    {
                      "name": "flash_io1_oe"
                    },
                    {
                      "name": "flash_io0_do"
                    },
                    {
                      "name": "flash_io1_do"
                    },
                    {
                      "name": "cfgreg_do",
                      "range": "[31:0]",
                      "size": 32
                    },
                    {
                      "name": "xfer_resetn"
                    },
                    {
                      "name": "din_valid"
                    },
                    {
                      "name": "din_data",
                      "range": "[7:0]",
                      "size": 8
                    },
                    {
                      "name": "din_tag",
                      "range": "[3:0]",
                      "size": 4
                    },
                    {
                      "name": "din_cont"
                    },
                    {
                      "name": "xfer_dspi"
                    },
                    {
                      "name": "din_qspi"
                    },
                    {
                      "name": "xfer_ddr"
                    },
                    {
                      "name": "din_rd"
                    }
                  ]
                }
              },
              "position": {
                "x": 464,
                "y": 96
              },
              "size": {
                "width": 728,
                "height": 952
              }
            },
            {
              "id": "d349af7a-799b-4317-9be6-890549041ff1",
              "type": "basic.code",
              "data": {
                "code": "reg [7:0] obuffer;\n\treg [7:0] ibuffer;\n\n\treg [3:0] count;\n\treg [3:0] dummy_count;\n\n\treg xfer_cont;\n\treg xfer_dspi;\n\treg xfer_qspi;\n\treg xfer_ddr;\n\treg xfer_ddr_q;\n\treg xfer_rd;\n\treg [3:0] xfer_tag;\n\treg [3:0] xfer_tag_q;\n\n\treg [7:0] next_obuffer;\n\treg [7:0] next_ibuffer;\n\treg [3:0] next_count;\n\n\treg fetch;\n\treg next_fetch;\n\treg last_fetch;\n\t\n\t\n\treg flash_csb_i;\n    assign flash_csb = flash_csb_i;\n\treg flash_clk_i;\n    assign flash_clk = flash_clk_i;\n\n\treg flash_io0_oe_i;\n    assign flash_io0_oe = flash_io0_oe_i;\n\treg flash_io1_oe_i;\n    assign flash_io1_oe = flash_io1_oe_i;\n\t\n\n\treg flash_io0_do_i;\n    assign flash_io0_do = flash_io0_do_i;\n\treg flash_io1_do_i;\n    assign flash_io1_do = flash_io1_do_i;\n\t\n\n\talways @(posedge clk) begin\n\t\txfer_ddr_q <= xfer_ddr;\n\t\txfer_tag_q <= xfer_tag;\n\tend\n\n\tassign din_ready = din_valid && resetn && next_fetch;\n\n\tassign dout_valid = (xfer_ddr_q ? fetch && !last_fetch : next_fetch && !fetch) && resetn;\n\tassign dout_data = ibuffer;\n\tassign dout_tag = xfer_tag_q;\n\n\talways @* begin\n\t\tflash_io0_oe_i = 0;\n\t\tflash_io1_oe_i = 0;\n\t\t//flash_io2_oe = 0;\n\t\t//flash_io3_oe = 0;\n\n\t\tflash_io0_do_i = 0;\n\t\tflash_io1_do_i = 0;\n\t\t//flash_io2_do = 0;\n\t\t//flash_io3_do = 0;\n\n\t\tnext_obuffer = obuffer;\n\t\tnext_ibuffer = ibuffer;\n\t\tnext_count = count;\n\t\tnext_fetch = 0;\n\n\t\tif (dummy_count == 0) begin\n\t\t\tcasez ({xfer_ddr, xfer_qspi, xfer_dspi})\n\t\t\t\t3'b 000: begin\n\t\t\t\t\tflash_io0_oe_i = 1;\n\t\t\t\t\tflash_io0_do_i = obuffer[7];\n\n\t\t\t\t\tif (flash_clk_i) begin\n\t\t\t\t\t\tnext_obuffer = {obuffer[6:0], 1'b 0};\n\t\t\t\t\t\tnext_count = count - |count;\n\t\t\t\t\tend else begin\n\t\t\t\t\t\tnext_ibuffer = {ibuffer[6:0], flash_io1_di};\n\t\t\t\t\tend\n\n\t\t\t\t\tnext_fetch = (next_count == 0);\n\t\t\t\tend\n\t\t\t\t3'b 01?: begin\n\t\t\t\t\tflash_io0_oe_i = !xfer_rd;\n\t\t\t\t\tflash_io1_oe_i = !xfer_rd;\n\t\t\t\t\t//flash_io2_oe = !xfer_rd;\n\t\t\t\t\t//flash_io3_oe = !xfer_rd;\n\n\t\t\t\t\tflash_io0_do_i = obuffer[4];\n\t\t\t\t\tflash_io1_do_i = obuffer[5];\n\t\t\t\t\t//flash_io2_do = obuffer[6];\n\t\t\t\t\t//flash_io3_do = obuffer[7];\n\n\t\t\t\t\tif (flash_clk_i) begin\n\t\t\t\t\t\tnext_obuffer = {obuffer[3:0], 4'b 0000};\n\t\t\t\t\t\tnext_count = count - {|count, 2'b00};\n\t\t\t\t\tend else begin\n\t\t\t\t\t\tnext_ibuffer = {ibuffer[3:0], 1'b0, 1'b0, flash_io1_di, flash_io0_di};\n\t\t\t\t\tend\n\n\t\t\t\t\tnext_fetch = (next_count == 0);\n\t\t\t\tend\n\t\t\t\t3'b 11?: begin\n\t\t\t\t\tflash_io0_oe_i = !xfer_rd;\n\t\t\t\t\tflash_io1_oe_i = !xfer_rd;\n\t\t\t\t\t//flash_io2_oe = !xfer_rd;\n\t\t\t\t\t//flash_io3_oe = !xfer_rd;\n\n\t\t\t\t\tflash_io0_do_i = obuffer[4];\n\t\t\t\t\tflash_io1_do_i = obuffer[5];\n\t\t\t\t\t//flash_io2_do = obuffer[6];\n\t\t\t\t\t//flash_io3_do = obuffer[7];\n\n\t\t\t\t\tnext_obuffer = {obuffer[3:0], 4'b 0000};\n\t\t\t\t\tnext_ibuffer = {ibuffer[3:0], 1'b0, 1'b0, flash_io1_di, flash_io0_di};\n\t\t\t\t\tnext_count = count - {|count, 2'b00};\n\n\t\t\t\t\tnext_fetch = (next_count == 0);\n\t\t\t\tend\n\t\t\t\t3'b ??1: begin\n\t\t\t\t\tflash_io0_oe_i = !xfer_rd;\n\t\t\t\t\tflash_io1_oe_i = !xfer_rd;\n\n\t\t\t\t\tflash_io0_do_i = obuffer[6];\n\t\t\t\t\tflash_io1_do_i = obuffer[7];\n\n\t\t\t\t\tif (flash_clk_i) begin\n\t\t\t\t\t\tnext_obuffer = {obuffer[5:0], 2'b 00};\n\t\t\t\t\t\tnext_count = count - {|count, 1'b0};\n\t\t\t\t\tend else begin\n\t\t\t\t\t\tnext_ibuffer = {ibuffer[5:0], flash_io1_di, flash_io0_di};\n\t\t\t\t\tend\n\n\t\t\t\t\tnext_fetch = (next_count == 0);\n\t\t\t\tend\n\t\t\tendcase\n\t\tend\n\tend\n\n\talways @(posedge clk) begin\n\t\tif (!resetn) begin\n\t\t\tfetch <= 1;\n\t\t\tlast_fetch <= 1;\n\t\t\tflash_csb_i <= 1;\n\t\t\tflash_clk_i <= 0;\n\t\t\tcount <= 0;\n\t\t\tdummy_count <= 0;\n\t\t\txfer_tag <= 0;\n\t\t\txfer_cont <= 0;\n\t\t\txfer_dspi <= 0;\n\t\t\txfer_qspi <= 0;\n\t\t\txfer_ddr <= 0;\n\t\t\txfer_rd <= 0;\n\t\tend else begin\n\t\t\tfetch <= next_fetch;\n\t\t\tlast_fetch <= xfer_ddr ? fetch : 1;\n\t\t\tif (dummy_count) begin\n\t\t\t\tflash_clk_i <= !flash_clk_i && !flash_csb_i;\n\t\t\t\tdummy_count <= dummy_count - flash_clk_i;\n\t\t\tend else\n\t\t\tif (count) begin\n\t\t\t\tflash_clk_i <= !flash_clk_i && !flash_csb_i;\n\t\t\t\tobuffer <= next_obuffer;\n\t\t\t\tibuffer <= next_ibuffer;\n\t\t\t\tcount <= next_count;\n\t\t\tend\n\t\t\tif (din_valid && din_ready) begin\n\t\t\t\tflash_csb_i <= 0;\n\t\t\t\tflash_clk_i <= 0;\n\n\t\t\t\tcount <= 8;\n\t\t\t\tdummy_count <= din_rd ? din_data : 0;\n\t\t\t\tobuffer <= din_data;\n\n\t\t\t\txfer_tag <= din_tag;\n\t\t\t\txfer_cont <= din_cont;\n\t\t\t\txfer_dspi <= din_dspi;\n\t\t\t\txfer_qspi <= din_qspi;\n\t\t\t\txfer_ddr <= din_ddr;\n\t\t\t\txfer_rd <= din_rd;\n\t\t\tend\n\t\tend\n\tend",
                "params": [],
                "ports": {
                  "in": [
                    {
                      "name": "clk"
                    },
                    {
                      "name": "resetn"
                    },
                    {
                      "name": "din_valid"
                    },
                    {
                      "name": "din_data",
                      "range": "[7:0]",
                      "size": 8
                    },
                    {
                      "name": "din_tag",
                      "range": "[3:0]",
                      "size": 4
                    },
                    {
                      "name": "din_cont"
                    },
                    {
                      "name": "din_dspi"
                    },
                    {
                      "name": "din_qspi"
                    },
                    {
                      "name": "din_ddr"
                    },
                    {
                      "name": "din_rd"
                    },
                    {
                      "name": "flash_io0_di"
                    },
                    {
                      "name": "flash_io1_di"
                    }
                  ],
                  "out": [
                    {
                      "name": "din_ready"
                    },
                    {
                      "name": "dout_valid"
                    },
                    {
                      "name": "dout_data",
                      "range": "[7:0]",
                      "size": 8
                    },
                    {
                      "name": "dout_tag",
                      "range": "[3:0]",
                      "size": 4
                    },
                    {
                      "name": "flash_csb"
                    },
                    {
                      "name": "flash_clk"
                    },
                    {
                      "name": "flash_io0_oe"
                    },
                    {
                      "name": "flash_io1_oe"
                    },
                    {
                      "name": "flash_io0_do"
                    },
                    {
                      "name": "flash_io1_do"
                    }
                  ]
                }
              },
              "position": {
                "x": 1696,
                "y": 216
              },
              "size": {
                "width": 664,
                "height": 744
              }
            },
            {
              "id": "c850a3dc-12d0-42c7-ace8-15e613e4508f",
              "type": "basic.info",
              "data": {
                "info": "spimemio_xfer.v",
                "readonly": true
              },
              "position": {
                "x": 1976,
                "y": 168
              },
              "size": {
                "width": 136,
                "height": 40
              }
            },
            {
              "id": "95cb3fab-f18b-494b-ac8c-10fe14669e02",
              "type": "bb787cd998ce2b0e553a16e3e989479e24c00485",
              "position": {
                "x": 1704,
                "y": 1104
              },
              "size": {
                "width": 96,
                "height": 96
              }
            },
            {
              "id": "41c42313-d432-4f89-83ee-ff71f6758e67",
              "type": "d7e6ff61e136e0120db6aaabf8b34ea6fd14c159",
              "position": {
                "x": 2168,
                "y": 1104
              },
              "size": {
                "width": 96,
                "height": 64
              }
            },
            {
              "id": "32ca89b4-2eac-4d9e-949c-afb8114feba9",
              "type": "a0b8df28f3452068e469a9c210e4e62ae8c78900",
              "position": {
                "x": 120,
                "y": 408
              },
              "size": {
                "width": 96,
                "height": 64
              }
            }
          ],
          "wires": [
            {
              "source": {
                "block": "3c3311da-d805-405a-9f73-c78c1accccad",
                "port": "ready"
              },
              "target": {
                "block": "4589ee10-de7a-4ce9-8b49-c47e42f9e0bb",
                "port": "inlabel"
              },
              "vertices": []
            },
            {
              "source": {
                "block": "3c3311da-d805-405a-9f73-c78c1accccad",
                "port": "rdata",
                "size": 32
              },
              "target": {
                "block": "ccff9622-4a6e-450a-87b8-849bdf551289",
                "port": "inlabel"
              },
              "vertices": [],
              "size": 32
            },
            {
              "source": {
                "block": "3c3311da-d805-405a-9f73-c78c1accccad",
                "port": "flash_io0_oe"
              },
              "target": {
                "block": "095bacdc-bc80-450b-8d8b-a1f011c1b3ce",
                "port": "inlabel"
              },
              "vertices": []
            },
            {
              "source": {
                "block": "3c3311da-d805-405a-9f73-c78c1accccad",
                "port": "flash_io1_oe"
              },
              "target": {
                "block": "6d52a5cd-2c52-4109-88a8-432e1c8844f2",
                "port": "inlabel"
              },
              "vertices": []
            },
            {
              "source": {
                "block": "3c3311da-d805-405a-9f73-c78c1accccad",
                "port": "flash_io0_do"
              },
              "target": {
                "block": "d1a79736-1939-438f-86d0-29caacc6967e",
                "port": "inlabel"
              },
              "vertices": []
            },
            {
              "source": {
                "block": "3c3311da-d805-405a-9f73-c78c1accccad",
                "port": "flash_io1_do"
              },
              "target": {
                "block": "24501276-1c2d-479f-9095-4b19498f0a48",
                "port": "inlabel"
              },
              "vertices": []
            },
            {
              "source": {
                "block": "3c3311da-d805-405a-9f73-c78c1accccad",
                "port": "cfgreg_do",
                "size": 32
              },
              "target": {
                "block": "ed758264-a3e7-4353-a14d-0168cb47b676",
                "port": "inlabel"
              },
              "vertices": [],
              "size": 32
            },
            {
              "source": {
                "block": "3c3311da-d805-405a-9f73-c78c1accccad",
                "port": "xfer_resetn"
              },
              "target": {
                "block": "ae5082de-9fb8-4e23-8b37-78ab71b4ef4f",
                "port": "inlabel"
              },
              "vertices": []
            },
            {
              "source": {
                "block": "3c3311da-d805-405a-9f73-c78c1accccad",
                "port": "din_valid"
              },
              "target": {
                "block": "6a988c4f-5100-4bbb-a975-fd3dda22af4f",
                "port": "inlabel"
              },
              "vertices": []
            },
            {
              "source": {
                "block": "3c3311da-d805-405a-9f73-c78c1accccad",
                "port": "din_data",
                "size": 8
              },
              "target": {
                "block": "69504315-3648-4286-a539-0ccd783e10e1",
                "port": "inlabel"
              },
              "vertices": [],
              "size": 8
            },
            {
              "source": {
                "block": "3c3311da-d805-405a-9f73-c78c1accccad",
                "port": "din_tag",
                "size": 4
              },
              "target": {
                "block": "6cd5a52d-069d-4215-94c2-36dda065c6c8",
                "port": "inlabel"
              },
              "vertices": [],
              "size": 4
            },
            {
              "source": {
                "block": "3c3311da-d805-405a-9f73-c78c1accccad",
                "port": "din_cont"
              },
              "target": {
                "block": "f8b147cd-1ba4-4fcf-9c37-98606a02ff1c",
                "port": "inlabel"
              },
              "vertices": []
            },
            {
              "source": {
                "block": "3c3311da-d805-405a-9f73-c78c1accccad",
                "port": "xfer_dspi"
              },
              "target": {
                "block": "05bcaf14-a62c-4f5f-b22a-8bbc03435c24",
                "port": "inlabel"
              },
              "vertices": []
            },
            {
              "source": {
                "block": "3c3311da-d805-405a-9f73-c78c1accccad",
                "port": "din_qspi"
              },
              "target": {
                "block": "140205b6-1922-40e5-b166-e250fcbaab4d",
                "port": "inlabel"
              },
              "vertices": []
            },
            {
              "source": {
                "block": "3c3311da-d805-405a-9f73-c78c1accccad",
                "port": "xfer_ddr"
              },
              "target": {
                "block": "d7b52c50-bd13-4187-ae58-7df4fd1a85f1",
                "port": "inlabel"
              },
              "vertices": []
            },
            {
              "source": {
                "block": "3c3311da-d805-405a-9f73-c78c1accccad",
                "port": "din_rd"
              },
              "target": {
                "block": "cfce9cfb-cb5b-4be9-a260-10e2a70e417a",
                "port": "inlabel"
              },
              "vertices": []
            },
            {
              "source": {
                "block": "d536cc3b-759a-4662-b5b9-ed2cb9522473",
                "port": "outlabel"
              },
              "target": {
                "block": "3c3311da-d805-405a-9f73-c78c1accccad",
                "port": "resetn"
              },
              "vertices": []
            },
            {
              "source": {
                "block": "d3dc84e5-6b19-44a5-989c-49c5f65816d0",
                "port": "outlabel"
              },
              "target": {
                "block": "3c3311da-d805-405a-9f73-c78c1accccad",
                "port": "valid"
              },
              "vertices": []
            },
            {
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                "port": "outlabel"
              },
              "target": {
                "block": "3c3311da-d805-405a-9f73-c78c1accccad",
                "port": "addr",
                "size": 24
              },
              "vertices": [],
              "size": 24
            },
            {
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                "block": "ca942bee-a683-4ba2-8fc0-352fa0ee5285",
                "port": "outlabel"
              },
              "target": {
                "block": "3c3311da-d805-405a-9f73-c78c1accccad",
                "port": "flash_io0_di"
              },
              "vertices": []
            },
            {
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                "port": "outlabel"
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              "target": {
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                "port": "flash_io1_di"
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                "port": "outlabel"
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              "target": {
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                "port": "din_ready"
              },
              "vertices": []
            },
            {
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                "port": "outlabel"
              },
              "target": {
                "block": "3c3311da-d805-405a-9f73-c78c1accccad",
                "port": "dout_data",
                "size": 8
              },
              "vertices": [],
              "size": 8
            },
            {
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                "port": "outlabel"
              },
              "target": {
                "block": "3c3311da-d805-405a-9f73-c78c1accccad",
                "port": "dout_valid"
              },
              "vertices": []
            },
            {
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                "block": "9dd0d106-c3d8-42d2-8d5b-59823b9adfe3",
                "port": "outlabel"
              },
              "target": {
                "block": "3c3311da-d805-405a-9f73-c78c1accccad",
                "port": "dout_tag",
                "size": 4
              },
              "vertices": [],
              "size": 4
            },
            {
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                "port": "outlabel"
              },
              "target": {
                "block": "3c3311da-d805-405a-9f73-c78c1accccad",
                "port": "xfer_csb"
              },
              "vertices": []
            },
            {
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              },
              "target": {
                "block": "3c3311da-d805-405a-9f73-c78c1accccad",
                "port": "xfer_clk"
              },
              "vertices": []
            },
            {
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                "port": "outlabel"
              },
              "target": {
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                "port": "xfer_io0_oe"
              },
              "vertices": []
            },
            {
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                "port": "outlabel"
              },
              "target": {
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                "port": "xfer_io1_oe"
              },
              "vertices": []
            },
            {
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                "port": "outlabel"
              },
              "target": {
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                "port": "xfer_io0_do"
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            },
            {
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              "target": {
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                "port": "xfer_io1_do"
              },
              "vertices": []
            },
            {
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                "port": "din_ready"
              },
              "target": {
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                "port": "inlabel"
              },
              "vertices": []
            },
            {
              "source": {
                "block": "d349af7a-799b-4317-9be6-890549041ff1",
                "port": "dout_valid"
              },
              "target": {
                "block": "255fb454-8d70-4971-947e-9d673b4d9f3f",
                "port": "inlabel"
              },
              "vertices": []
            },
            {
              "source": {
                "block": "d349af7a-799b-4317-9be6-890549041ff1",
                "port": "dout_data",
                "size": 8
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