0032-Xtensa-Implement-Mac16-feature-and-operations.patch

From 34427ee39d2fc6b742f0efe7777d95bdc7ffa1ad Mon Sep 17 00:00:00 2001
From: Andrei Safronov <safronov@espressif.com>
Date: Wed, 5 Apr 2023 00:58:51 +0300
Subject: [PATCH 032/158] [Xtensa] Implement Mac16 feature and operations.

---
 .../Disassembler/XtensaDisassembler.cpp       |  47 ++-
 llvm/lib/Target/Xtensa/Xtensa.td              |   5 +
 llvm/lib/Target/Xtensa/XtensaDSPInstrInfo.td  | 353 ++++++++++++++++++
 llvm/lib/Target/Xtensa/XtensaInstrInfo.td     |   5 +
 llvm/lib/Target/Xtensa/XtensaRegisterInfo.td  |  12 +-
 llvm/lib/Target/Xtensa/XtensaSubtarget.cpp    |   1 +
 llvm/lib/Target/Xtensa/XtensaSubtarget.h      |   5 +
 llvm/test/MC/Xtensa/xtensa-valid-mac16.s      | 234 ++++++++++++
 8 files changed, 658 insertions(+), 4 deletions(-)
 create mode 100644 llvm/lib/Target/Xtensa/XtensaDSPInstrInfo.td
 create mode 100644 llvm/test/MC/Xtensa/xtensa-valid-mac16.s

diff --git a/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp b/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp
index ebcab090d420..e470ed8d2766 100644
--- a/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp
+++ b/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp
@@ -107,10 +107,51 @@ static DecodeStatus DecodeBRRegisterClass(MCInst &Inst, uint64_t RegNo,
   return MCDisassembler::Success;
 }
 
+static const unsigned MRDecoderTable[] = {Xtensa::M0, Xtensa::M1, Xtensa::M2,
+                                          Xtensa::M3};
+
+static DecodeStatus DecodeMRRegisterClass(MCInst &Inst, uint64_t RegNo,
+                                          uint64_t Address,
+                                          const void *Decoder) {
+  if (RegNo >= std::size(MRDecoderTable))
+    return MCDisassembler::Fail;
+
+  unsigned Reg = MRDecoderTable[RegNo];
+  Inst.addOperand(MCOperand::createReg(Reg));
+  return MCDisassembler::Success;
+}
+
+static const unsigned MR01DecoderTable[] = {Xtensa::M0, Xtensa::M1};
+
+static DecodeStatus DecodeMR01RegisterClass(MCInst &Inst, uint64_t RegNo,
+                                            uint64_t Address,
+                                            const void *Decoder) {
+  if (RegNo > 2)
+    return MCDisassembler::Fail;
+
+  unsigned Reg = MR01DecoderTable[RegNo];
+  Inst.addOperand(MCOperand::createReg(Reg));
+  return MCDisassembler::Success;
+}
+
+static const unsigned MR23DecoderTable[] = {Xtensa::M2, Xtensa::M3};
+
+static DecodeStatus DecodeMR23RegisterClass(MCInst &Inst, uint64_t RegNo,
+                                            uint64_t Address,
+                                            const void *Decoder) {
+  if ((RegNo < 2) || (RegNo > 3))
+    return MCDisassembler::Fail;
+
+  unsigned Reg = MR23DecoderTable[RegNo - 2];
+  Inst.addOperand(MCOperand::createReg(Reg));
+  return MCDisassembler::Success;
+}
+
 static const unsigned SRDecoderTable[] = {
-    Xtensa::LBEG,        0, Xtensa::LEND, 1, Xtensa::LCOUNT,      2,
-    Xtensa::SAR,         3, Xtensa::BREG, 4, Xtensa ::WINDOWBASE, 72,
-    Xtensa::WINDOWSTART, 73};
+    Xtensa::LEND, 1,  Xtensa::LCOUNT,      2,  Xtensa::SAR,         3,
+    Xtensa::BREG, 4,  Xtensa::ACCLO,       16, Xtensa::ACCHI,       17,
+    Xtensa::M0,   32, Xtensa::M1,          33, Xtensa::M2,          34,
+    Xtensa::M3,   35, Xtensa ::WINDOWBASE, 72, Xtensa::WINDOWSTART, 73};
 
 static DecodeStatus DecodeSRRegisterClass(MCInst &Inst, uint64_t RegNo,
                                           uint64_t Address,
diff --git a/llvm/lib/Target/Xtensa/Xtensa.td b/llvm/lib/Target/Xtensa/Xtensa.td
index 5555d73ca4be..5468b91e2494 100644
--- a/llvm/lib/Target/Xtensa/Xtensa.td
+++ b/llvm/lib/Target/Xtensa/Xtensa.td
@@ -67,6 +67,11 @@ def FeatureDiv32            : SubtargetFeature<"div32", "HasDiv32", "true",
 def HasDiv32                : Predicate<"Subtarget->hasDiv32()">,
                                          AssemblerPredicate<(all_of FeatureDiv32)>;
 
+def FeatureMAC16            : SubtargetFeature<"mac16", "HasMAC16", "true",
+                                               "Enable Xtensa MAC16 instructions">;
+def HasMAC16                : Predicate<"Subtarget->hasMAC16()">,
+                                         AssemblerPredicate<(all_of FeatureMAC16)>;
+
 //===----------------------------------------------------------------------===//
 // Xtensa supported processors.
 //===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/Xtensa/XtensaDSPInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaDSPInstrInfo.td
new file mode 100644
index 000000000000..d80df4632064
--- /dev/null
+++ b/llvm/lib/Target/Xtensa/XtensaDSPInstrInfo.td
@@ -0,0 +1,353 @@
+//===- XtensaDSPInstrInfo.td - Xtensa Target Description ---*- tablegen -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the Xtensa DSP instructions in TableGen format.
+//
+//===----------------------------------------------------------------------===//
+
+// Multiply
+class UMUL_AA<bits<4> oper1, string instrAsm>
+  : RRR_Inst<0x04, oper1, 0x07, (outs), (ins AR:$s, AR:$t),
+             instrAsm#"\t$s, $t", []>, Requires<[HasMAC16]> {
+  let r = 0;
+  let Defs = [M1, M2, ACCLO, ACCHI];
+}
+
+def UMUL_AA_LL : UMUL_AA<0x00, "umul.aa.ll">;
+def UMUL_AA_HL : UMUL_AA<0x01, "umul.aa.hl">;
+def UMUL_AA_LH : UMUL_AA<0x02, "umul.aa.lh">;
+def UMUL_AA_HH : UMUL_AA<0x03, "umul.aa.hh">;
+
+class MUL_AA<bits<4> oper1, string instrAsm>
+  : RRR_Inst<0x04, oper1, 0x07, (outs), (ins AR:$s, AR:$t),
+             instrAsm#"\t$s, $t", []>, Requires<[HasMAC16]> {
+  let r = 0;
+  let Defs = [M1, M2, ACCLO, ACCHI];
+}
+
+def MUL_AA_LL : MUL_AA<0x04, "mul.aa.ll">;
+def MUL_AA_HL : MUL_AA<0x05, "mul.aa.hl">;
+def MUL_AA_LH : MUL_AA<0x06, "mul.aa.lh">;
+def MUL_AA_HH : MUL_AA<0x07, "mul.aa.hh">;
+
+class MUL_AD<bits<4> oper1, string instrAsm>
+  : RRR_Inst<0x04, oper1, 0x03, (outs), (ins AR:$s, MR23:$y),
+             instrAsm#"\t$s, $y", []>, Requires<[HasMAC16]> {
+  bits<2> y;
+
+  let r = 0;
+  let t{3} = 0;
+  let t{2} = y{0};
+  let t{1-0} = 0;
+  let Defs = [M1, M2, ACCLO, ACCHI];
+}
+
+def MUL_AD_LL : MUL_AD<0x04, "mul.ad.ll">;
+def MUL_AD_HL : MUL_AD<0x05, "mul.ad.hl">;
+def MUL_AD_LH : MUL_AD<0x06, "mul.ad.lh">;
+def MUL_AD_HH : MUL_AD<0x07, "mul.ad.hh">;
+
+class MUL_DA<bits<4> oper1, string instrAsm>
+  : RRR_Inst<0x04, oper1, 0x06, (outs), (ins MR01:$x, AR:$t),
+             instrAsm#"\t$x, $t", []>, Requires<[HasMAC16]> {
+  bits<2> x;
+
+  let r{3} = 0;
+  let r{2} = x{0};
+  let r{1-0} = 0;
+  let s = 0;
+  let Defs = [M1, M2, ACCLO, ACCHI];
+}
+
+def MUL_DA_LL : MUL_DA<0x04, "mul.da.ll">;
+def MUL_DA_HL : MUL_DA<0x05, "mul.da.hl">;
+def MUL_DA_LH : MUL_DA<0x06, "mul.da.lh">;
+def MUL_DA_HH : MUL_DA<0x07, "mul.da.hh">;
+
+class MUL_DD<bits<4> oper1, string instrAsm>
+  : RRR_Inst<0x04, oper1, 0x02, (outs), (ins MR01:$x, MR23:$y),
+             instrAsm#"\t$x, $y", []>, Requires<[HasMAC16]> {
+  bits<2> x;
+  bits<2> y;
+
+  let r{3} = 0;
+  let r{2} = x{0};
+  let r{1-0} = 0;
+  let s = 0;
+  let t{3} = 0;
+  let t{2} = y{0};
+  let t{1-0} = 0;
+  let Defs = [M1, M2, ACCLO, ACCHI];
+}
+
+def MUL_DD_LL : MUL_DD<0x04, "mul.dd.ll">;
+def MUL_DD_HL : MUL_DD<0x05, "mul.dd.hl">;
+def MUL_DD_LH : MUL_DD<0x06, "mul.dd.lh">;
+def MUL_DD_HH : MUL_DD<0x07, "mul.dd.hh">;
+
+class MULA_AA<bits<4> oper1, string instrAsm>
+  : RRR_Inst<0x04, oper1, 0x07, (outs), (ins AR:$s, AR:$t),
+             instrAsm#"\t$s, $t", []>, Requires<[HasMAC16]> {
+  let r = 0;
+  let Defs = [M1, M2, ACCLO, ACCHI];
+}
+
+def MULA_AA_LL : MULA_AA<0x08, "mula.aa.ll">;
+def MULA_AA_HL : MULA_AA<0x09, "mula.aa.hl">;
+def MULA_AA_LH : MULA_AA<0x0A, "mula.aa.lh">;
+def MULA_AA_HH : MULA_AA<0x0B, "mula.aa.hh">;
+
+class MULA_AD<bits<4> oper1, string instrAsm>
+  : RRR_Inst<0x04, oper1, 0x03, (outs), (ins AR:$s, MR23:$y),
+             instrAsm#"\t$s, $y", []>, Requires<[HasMAC16]> {
+  bits<2> y;
+
+  let r = 0;
+  let t{3} = 0;
+  let t{2} = y{0};
+  let t{1-0} = 0;
+
+  let Uses = [ACCLO, ACCHI];
+  let Defs = [M1, M2, ACCLO, ACCHI];
+}
+
+def MULA_AD_LL : MULA_AD<0x08, "mula.ad.ll">;
+def MULA_AD_HL : MULA_AD<0x09, "mula.ad.hl">;
+def MULA_AD_LH : MULA_AD<0x0A, "mula.ad.lh">;
+def MULA_AD_HH : MULA_AD<0x0B, "mula.ad.hh">;
+
+class MULA_DA<bits<4> oper1, string instrAsm>
+  : RRR_Inst<0x04, oper1, 0x06, (outs), (ins MR01:$x, AR:$t),
+             instrAsm#"\t$x, $t", []>, Requires<[HasMAC16]> {
+  bits<2> x;
+
+  let r{3} = 0;
+  let r{2} = x{0};
+  let r{1-0} = 0;
+  let s = 0;
+
+  let Uses = [ACCLO, ACCHI];
+  let Defs = [M1, M2, ACCLO, ACCHI];
+}
+
+def MULA_DA_LL : MULA_DA<0x08, "mula.da.ll">;
+def MULA_DA_HL : MULA_DA<0x09, "mula.da.hl">;
+def MULA_DA_LH : MULA_DA<0x0A, "mula.da.lh">;
+def MULA_DA_HH : MULA_DA<0x0B, "mula.da.hh">;
+
+class MULA_DD<bits<4> oper1, string instrAsm>
+  : RRR_Inst<0x04, oper1, 0x02, (outs), (ins MR01:$x, MR23:$y),
+             instrAsm#"\t$x, $y", []>, Requires<[HasMAC16]> {
+  bits<2> x;
+  bits<2> y;
+
+  let r{3} = 0;
+  let r{2} = x{0};
+  let r{1-0} = 0;
+  let s = 0;
+  let t{3} = 0;
+  let t{2} = y{0};
+  let t{1-0} = 0;
+
+  let Uses = [ACCLO, ACCHI];
+  let Defs = [M1, M2, ACCLO, ACCHI];
+}
+
+def MULA_DD_LL : MULA_DD<0x08, "mula.dd.ll">;
+def MULA_DD_HL : MULA_DD<0x09, "mula.dd.hl">;
+def MULA_DD_LH : MULA_DD<0x0A, "mula.dd.lh">;
+def MULA_DD_HH : MULA_DD<0x0B, "mula.dd.hh">;
+
+class MULS_AA<bits<4> oper1, string instrAsm>
+  : RRR_Inst<0x04, oper1, 0x07, (outs), (ins AR:$s, AR:$t),
+             instrAsm#"\t$s, $t", []>, Requires<[HasMAC16]> {
+  let r = 0;
+  let Uses = [ACCLO, ACCHI];
+  let Defs = [M1, M2, ACCLO, ACCHI];
+}
+
+def MULS_AA_LL : MULS_AA<0x0C, "muls.aa.ll">;
+def MULS_AA_HL : MULS_AA<0x0D, "muls.aa.hl">;
+def MULS_AA_LH : MULS_AA<0x0E, "muls.aa.lh">;
+def MULS_AA_HH : MULS_AA<0x0F, "muls.aa.hh">;
+
+class MULS_AD<bits<4> oper1, string instrAsm>
+  : RRR_Inst<0x04, oper1, 0x03, (outs), (ins AR:$s, MR23:$y),
+             instrAsm#"\t$s, $y", []>, Requires<[HasMAC16]> {
+  bits<2> y;
+
+  let r = 0;
+  let t{3} = 0;
+  let t{2} = y{0};
+  let t{1-0} = 0;
+
+  let Uses = [ACCLO, ACCHI];
+  let Defs = [M1, M2, ACCLO, ACCHI];
+}
+
+def MULS_AD_LL : MULS_AD<0x0C, "muls.ad.ll">;
+def MULS_AD_HL : MULS_AD<0x0D, "muls.ad.hl">;
+def MULS_AD_LH : MULS_AD<0x0E, "muls.ad.lh">;
+def MULS_AD_HH : MULS_AD<0x0F, "muls.ad.hh">;
+
+class MULS_DA<bits<4> oper1, string instrAsm>
+  : RRR_Inst<0x04, oper1, 0x06, (outs), (ins MR01:$x, AR:$t),
+             instrAsm#"\t$x, $t", []>, Requires<[HasMAC16]> {
+  bits<2> x;
+
+  let r{3} = 0;
+  let r{2} = x{0};
+  let r{1-0} = 0;
+  let s = 0;
+
+  let Uses = [ACCLO, ACCHI];
+  let Defs = [M1, M2, ACCLO, ACCHI];
+}
+
+def MULS_DA_LL : MULS_DA<0x0C, "muls.da.ll">;
+def MULS_DA_HL : MULS_DA<0x0D, "muls.da.hl">;
+def MULS_DA_LH : MULS_DA<0x0E, "muls.da.lh">;
+def MULS_DA_HH : MULS_DA<0x0F, "muls.da.hh">;
+
+class MULS_DD<bits<4> oper1, string instrAsm>
+  : RRR_Inst<0x04, oper1, 0x02, (outs), (ins MR01:$x, MR23:$y),
+             instrAsm#"\t$x, $y", []>, Requires<[HasMAC16]> {
+  bits<2> x;
+  bits<2> y;
+
+  let r{3} = 0;
+  let r{2} = x{0};
+  let r{1-0} = 0;
+  let s = 0;
+  let t{3} = 0;
+  let t{2} = y{0};
+  let t{1-0} = 0;
+
+  let Uses = [ACCLO, ACCHI];
+  let Defs = [M1, M2, ACCLO, ACCHI];
+}
+
+def MULS_DD_LL : MULS_DD<0x0C, "muls.dd.ll">;
+def MULS_DD_HL : MULS_DD<0x0D, "muls.dd.hl">;
+def MULS_DD_LH : MULS_DD<0x0E, "muls.dd.lh">;
+def MULS_DD_HH : MULS_DD<0x0F, "muls.dd.hh">;
+
+//===----------------------------------------------------------------------===//
+// Multiply-accumulate with load
+
+class MULA_DA_LDDEC<bits<4> oper1, string instrAsm>
+  : RRR_Inst<0x04, oper1, 0x05, (outs MR:$w, AR:$d), (ins AR:$s, MR01:$x, AR:$t),
+             instrAsm#"\t $w, $s, $x, $t", []>, Requires<[HasMAC16]> {
+  bits<2> x;
+  bits<2> w;
+
+  let Constraints = "$s = $d";
+  let mayLoad = 1;
+  let r{3} = 0;
+  let r{2} = x{0};
+  let r{1-0} = w{1-0};
+  let Uses = [ACCLO, ACCHI];
+  let Defs = [M1, M2, ACCLO, ACCHI];
+}
+
+def MULA_DA_LL_LDDEC : MULA_DA_LDDEC<0x08, "mula.da.ll.lddec">;
+def MULA_DA_HL_LDDEC : MULA_DA_LDDEC<0x09, "mula.da.hl.lddec">;
+def MULA_DA_LH_LDDEC : MULA_DA_LDDEC<0x0A, "mula.da.lh.lddec">;
+def MULA_DA_HH_LDDEC : MULA_DA_LDDEC<0x0B, "mula.da.hh.lddec">;
+
+class MULA_DA_LDINC<bits<4> oper1, string instrAsm>
+  : RRR_Inst<0x04, oper1, 0x04, (outs MR:$w, AR:$d), (ins AR:$s, MR:$x, AR:$t),
+             instrAsm#"\t $w, $s, $x, $t", []>, Requires<[HasMAC16]> {
+  bits<1> x;
+  bits<2> w;
+
+  let Constraints = "$s = $d";
+  let mayLoad = 1;
+  let r{3} = 0;
+  let r{2} = x{0};
+  let r{1-0} = w{1-0};
+  let Uses = [ACCLO, ACCHI];
+  let Defs = [M1, M2, ACCLO, ACCHI];
+}
+
+def MULA_DA_LL_LDINC: MULA_DA_LDINC<0x08, "mula.da.ll.ldinc">;
+def MULA_DA_HL_LDINC: MULA_DA_LDINC<0x09, "mula.da.hl.ldinc">;
+def MULA_DA_LH_LDINC: MULA_DA_LDINC<0x0A, "mula.da.lh.ldinc">;
+def MULA_DA_HH_LDINC: MULA_DA_LDINC<0x0B, "mula.da.hh.ldinc">;
+
+class MULA_DD_LDDEC<bits<4> oper1, string instrAsm>
+  : RRR_Inst<0x04, oper1, 0x01, (outs MR:$w, AR:$d), (ins AR:$s, MR01:$x, MR23:$y),
+             instrAsm#"\t $w, $s, $x, $y", []>, Requires<[HasMAC16]> {
+  bits<2> x;
+  bits<2> y;
+  bits<2> w;
+
+  let Constraints = "$s = $d";
+  let mayLoad = 1;
+  let r{3} = 0;
+  let r{2} = x{0};
+  let r{1-0} = w{1-0};
+  let t{3} = 0;
+  let t{2} = y{0};
+  let t{1-0} = 0;
+  let Uses = [ACCLO, ACCHI];
+  let Defs = [M1, M2, ACCLO, ACCHI];
+}
+
+def MULA_DD_LL_LDDEC : MULA_DD_LDDEC<0x08, "mula.dd.ll.lddec">;
+def MULA_DD_HL_LDDEC : MULA_DD_LDDEC<0x09, "mula.dd.hl.lddec">;
+def MULA_DD_LH_LDDEC : MULA_DD_LDDEC<0x0A, "mula.dd.lh.lddec">;
+def MULA_DD_HH_LDDEC : MULA_DD_LDDEC<0x0B, "mula.dd.hh.lddec">;
+
+class MULA_DD_LDINC<bits<4> oper1, string instrAsm>
+  : RRR_Inst<0x04, oper1, 0x00, (outs MR:$w, AR:$d), (ins AR:$s, MR01:$x, MR23:$y),
+             instrAsm#"\t $w, $s, $x, $y", []>, Requires<[HasMAC16]> {
+  bits<2> x;
+  bits<2> y;
+  bits<2> w;
+
+  let Constraints = "$s = $d";
+  let mayLoad = 1;
+  let r{3} = 0;
+  let r{2} = x{0};
+  let r{1-0} = w{1-0};
+  let t{3} = 0;
+  let t{2} = y{0};
+  let t{1-0} = 0;
+  let Uses = [ACCLO, ACCHI];
+  let Defs = [M1, M2, ACCLO, ACCHI];
+}
+
+def MULA_DD_LL_LDINC : MULA_DD_LDINC<0x08, "mula.dd.ll.ldinc">;
+def MULA_DD_HL_LDINC : MULA_DD_LDINC<0x09, "mula.dd.hl.ldinc">;
+def MULA_DD_LH_LDINC : MULA_DD_LDINC<0x0A, "mula.dd.lh.ldinc">;
+def MULA_DD_HH_LDINC : MULA_DD_LDINC<0x0B, "mula.dd.hh.ldinc">;
+
+def LDDEC : RRR_Inst<0x04, 0x00, 0x09, (outs MR:$w, AR:$d), (ins AR:$s),
+                    "lddec\t $w, $s", []>, Requires<[HasMAC16]> {
+  bits<2> w;
+
+  let Constraints = "$s = $d";
+  let mayLoad = 1;
+  let r{3-2} = 0;
+  let r{1-0} = w{1-0};
+  let t = 0x00;
+}
+
+def LDINC : RRR_Inst<0x04, 0x00, 0x08, (outs MR:$w, AR:$d), (ins AR:$s),
+                    "ldinc\t $w, $s", []>, Requires<[HasMAC16]> {
+  bits<2> w;
+
+  let Constraints = "$s = $d";
+  let mayLoad = 1;
+  let r{3-2} = 0;
+  let r{1-0} = w{1-0};
+  let t = 0;
+}
diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td
index e12f4a632d10..fa15b7833575 100644
--- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td
+++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td
@@ -1190,3 +1190,8 @@ def QUOS : ArithLogic_RRR<0x0D, 0x02, "quos", sdiv>, Requires<[HasDiv32]>;
 def QUOU : ArithLogic_RRR<0x0C, 0x02, "quou", udiv>, Requires<[HasDiv32]>;
 def REMS : ArithLogic_RRR<0x0F, 0x02, "rems", srem>, Requires<[HasDiv32]>;
 def REMU : ArithLogic_RRR<0x0E, 0x02, "remu", urem>, Requires<[HasDiv32]>;
+
+//===----------------------------------------------------------------------===//
+// DSP Instructions
+//===----------------------------------------------------------------------===//
+include "XtensaDSPInstrInfo.td"
diff --git a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.td b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.td
index d7fbdcff09b9..4e953f7bfe15 100644
--- a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.td
+++ b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.td
@@ -81,11 +81,21 @@ def SAR : SRReg<3, "sar", ["SAR","3"]>;
 
 def BREG : SRReg<4, "br", ["BR", "4"]>;
 
+def ACCLO : SRReg<16, "acclo", ["ACCLO", "16"]>;
+def ACCHI : SRReg<17, "acchi", ["ACCHI", "17"]>;
+def M0 : SRReg<32, "m0", ["M0", "32"]>;
+def M1 : SRReg<33, "m1", ["M1", "33"]>;
+def M2 : SRReg<34, "m2", ["M2", "34"]>;
+def M3 : SRReg<35, "m3", ["M3", "35"]>;
 def WINDOWBASE : SRReg<72, "windowbase", ["WINDOWBASE", "72"]>;
 def WINDOWSTART : SRReg<73, "windowstart", ["WINDOWSTART", "73"]>;
 
+def MR01 :  RegisterClass<"Xtensa", [i32], 32, (add M0, M1)>;
+def MR23 :  RegisterClass<"Xtensa", [i32], 32, (add M2, M3)>;
+def MR :  RegisterClass<"Xtensa", [i32], 32, (add MR01, MR23)>;
+
 def SR :  RegisterClass<"Xtensa", [i32], 32, (add LBEG, LEND, LCOUNT,
-  SAR, BREG, WINDOWBASE, WINDOWSTART)>;
+  SAR, BREG, MR, WINDOWBASE, WINDOWSTART)>;
 
 //===----------------------------------------------------------------------===//
 // USER registers
diff --git a/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp b/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp
index 03fd8cb99cb9..b23346ea4335 100644
--- a/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp
+++ b/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp
@@ -42,6 +42,7 @@ XtensaSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) {
   HasMul32 = false;
   HasMul32High = false;
   HasDiv32 = false;
+  HasMAC16 = false;
 
   // Parse features string.
   ParseSubtargetFeatures(CPUName, CPUName, FS);
diff --git a/llvm/lib/Target/Xtensa/XtensaSubtarget.h b/llvm/lib/Target/Xtensa/XtensaSubtarget.h
index f129ddbdb893..a4bfd2ae3956 100644
--- a/llvm/lib/Target/Xtensa/XtensaSubtarget.h
+++ b/llvm/lib/Target/Xtensa/XtensaSubtarget.h
@@ -68,6 +68,9 @@ private:
   // Enable Xtensa Div32 option
   bool HasDiv32;
 
+  // Enabled Xtensa MAC16 instructions
+  bool HasMAC16;
+
   XtensaSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
 
 public:
@@ -105,6 +108,8 @@ public:
 
   bool hasDiv32() const { return HasDiv32; }
 
+  bool hasMAC16() const { return HasMAC16; }
+
   // Automatically generated by tblgen.
   void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
 };
diff --git a/llvm/test/MC/Xtensa/xtensa-valid-mac16.s b/llvm/test/MC/Xtensa/xtensa-valid-mac16.s
new file mode 100644
index 000000000000..dee79da7755d
--- /dev/null
+++ b/llvm/test/MC/Xtensa/xtensa-valid-mac16.s
@@ -0,0 +1,234 @@
+# RUN: llvm-mc %s -triple=xtensa -mattr=+mac16 -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK,CHECK-INST %s
+
+.align	4
+LBL0:
+
+# CHECK-INST: umul.aa.ll	a2, a3
+# CHECK: encoding: [0x34,0x02,0x70]
+	umul.aa.ll	a2, a3
+# CHECK-INST: umul.aa.lh	a2, a3
+# CHECK: encoding: [0x34,0x02,0x72]
+	umul.aa.lh	a2, a3
+# CHECK-INST: umul.aa.hl	a2, a3
+# CHECK: encoding: [0x34,0x02,0x71]
+	umul.aa.hl	a2, a3
+# CHECK-INST: umul.aa.hh	a2, a3
+# CHECK: encoding: [0x34,0x02,0x73]
+	umul.aa.hh	a2, a3
+
+# CHECK-INST: mul.aa.ll	a2, a3
+# CHECK: encoding: [0x34,0x02,0x74]
+	mul.aa.ll	a2, a3
+# CHECK-INST: mul.aa.lh	a2, a3
+# CHECK: encoding: [0x34,0x02,0x76]
+	mul.aa.lh	a2, a3
+# CHECK-INST: mul.aa.hl	a2, a3
+# CHECK: encoding: [0x34,0x02,0x75]
+	mul.aa.hl	a2, a3
+# CHECK-INST: mul.aa.hh	a2, a3
+# CHECK: encoding: [0x34,0x02,0x77]
+	mul.aa.hh	a2, a3
+	
+# CHECK-INST: mul.ad.ll	a2, m2
+# CHECK: encoding: [0x04,0x02,0x34]
+	mul.ad.ll	a2, m2
+# CHECK-INST: mul.ad.lh	a2, m2
+# CHECK: encoding: [0x04,0x02,0x36]
+	mul.ad.lh	a2, m2
+# CHECK-INST: mul.ad.hl	a2, m2
+# CHECK: encoding: [0x04,0x02,0x35]
+	mul.ad.hl	a2, m2
+# CHECK-INST: mul.ad.hh	a2, m2
+# CHECK: encoding: [0x04,0x02,0x37]
+	mul.ad.hh	a2, m2
+	
+# CHECK-INST: mul.da.ll	m1, a3
+# CHECK: encoding: [0x34,0x40,0x64]
+	mul.da.ll	m1, a3
+# CHECK-INST: mul.da.lh	m1, a3
+# CHECK: encoding: [0x34,0x40,0x66]
+	mul.da.lh	m1, a3
+# CHECK-INST: mul.da.hl	m1, a3
+# CHECK: encoding: [0x34,0x40,0x65]
+	mul.da.hl	m1, a3
+# CHECK-INST: mul.da.hh	m1, a3
+# CHECK: encoding: [0x34,0x40,0x67]
+	mul.da.hh	m1, a3
+	
+# CHECK-INST: mul.dd.ll	m1, m2
+# CHECK: encoding: [0x04,0x40,0x24]
+	mul.dd.ll	m1, m2
+# CHECK-INST: mul.dd.lh	m1, m2
+# CHECK: encoding: [0x04,0x40,0x26]
+	mul.dd.lh	m1, m2
+# CHECK-INST: mul.dd.hl	m1, m2
+# CHECK: encoding: [0x04,0x40,0x25]
+	mul.dd.hl	m1, m2
+# CHECK-INST: mul.dd.hh	m1, m2
+# CHECK: encoding: [0x04,0x40,0x27]
+	mul.dd.hh	m1, m2
+
+# CHECK-INST: mula.aa.ll	a2, a3
+# CHECK: encoding: [0x34,0x02,0x78]
+	mula.aa.ll	a2, a3
+# CHECK-INST: mula.aa.lh	a2, a3
+# CHECK: encoding: [0x34,0x02,0x7a]
+	mula.aa.lh	a2, a3
+# CHECK-INST: mula.aa.hl	a2, a3
+# CHECK: encoding: [0x34,0x02,0x79]
+	mula.aa.hl	a2, a3
+# CHECK-INST: mula.aa.hh	a2, a3
+# CHECK: encoding: [0x34,0x02,0x7b]
+	mula.aa.hh	a2, a3
+
+# CHECK-INST: mula.ad.ll	a2, m2
+# CHECK: encoding: [0x04,0x02,0x38]
+	mula.ad.ll	a2, m2
+# CHECK-INST: mula.ad.lh	a2, m2
+# CHECK: encoding: [0x04,0x02,0x3a]
+	mula.ad.lh	a2, m2
+# CHECK-INST: mula.ad.hl	a2, m2
+# CHECK: encoding: [0x04,0x02,0x39]
+	mula.ad.hl	a2, m2
+# CHECK-INST: mula.ad.hh	a2, m2
+# CHECK: encoding: [0x04,0x02,0x3b]
+	mula.ad.hh	a2, m2
+
+# CHECK-INST: mula.da.ll	m1, a3
+# CHECK: encoding: [0x34,0x40,0x68]
+	mula.da.ll	m1, a3
+# CHECK-INST: mula.da.lh	m1, a3
+# CHECK: encoding: [0x34,0x40,0x6a]
+	mula.da.lh	m1, a3
+# CHECK-INST: mula.da.hl	m1, a3
+# CHECK: encoding: [0x34,0x40,0x69]
+	mula.da.hl	m1, a3
+# CHECK-INST: mula.da.hh	m1, a3
+# CHECK: encoding: [0x34,0x40,0x6b]
+	mula.da.hh	m1, a3
+
+# CHECK-INST: mula.dd.ll	m1, m2
+# CHECK: encoding: [0x04,0x40,0x28]
+	mula.dd.ll	m1, m2
+# CHECK-INST: mula.dd.lh	m1, m2
+# CHECK: encoding: [0x04,0x40,0x2a]
+	mula.dd.lh	m1, m2
+# CHECK-INST: mula.dd.hl	m1, m2
+# CHECK: encoding: [0x04,0x40,0x29]
+	mula.dd.hl	m1, m2
+# CHECK-INST: mula.dd.hh	m1, m2
+# CHECK: encoding: [0x04,0x40,0x2b]
+	mula.dd.hh	m1, m2
+
+# CHECK-INST: muls.aa.ll	a2, a3
+# CHECK: encoding: [0x34,0x02,0x7c]
+	muls.aa.ll	a2, a3
+# CHECK-INST: muls.aa.lh	a2, a3
+# CHECK: encoding: [0x34,0x02,0x7e]
+	muls.aa.lh	a2, a3
+# CHECK-INST: muls.aa.hl	a2, a3
+# CHECK: encoding: [0x34,0x02,0x7d]
+	muls.aa.hl	a2, a3
+# CHECK-INST: muls.aa.hh	a2, a3
+# CHECK: encoding: [0x34,0x02,0x7f]
+	muls.aa.hh	a2, a3
+
+# CHECK-INST: muls.ad.ll	a2, m2
+# CHECK: encoding: [0x04,0x02,0x3c]
+	muls.ad.ll	a2, m2
+# CHECK-INST: muls.ad.lh	a2, m2
+# CHECK: encoding: [0x04,0x02,0x3e]
+	muls.ad.lh	a2, m2
+# CHECK-INST: muls.ad.hl	a2, m2
+# CHECK: encoding: [0x04,0x02,0x3d]
+	muls.ad.hl	a2, m2
+# CHECK-INST: muls.ad.hh	a2, m2
+# CHECK: encoding: [0x04,0x02,0x3f]
+	muls.ad.hh	a2, m2
+
+# CHECK-INST: muls.da.ll	m1, a3
+# CHECK: encoding: [0x34,0x40,0x6c]
+	muls.da.ll	m1, a3
+# CHECK-INST: muls.da.lh	m1, a3
+# CHECK: encoding: [0x34,0x40,0x6e]
+	muls.da.lh	m1, a3
+# CHECK-INST: muls.da.hl	m1, a3
+# CHECK: encoding: [0x34,0x40,0x6d]
+	muls.da.hl	m1, a3
+# CHECK-INST: muls.da.hh	m1, a3
+# CHECK: encoding: [0x34,0x40,0x6f]
+	muls.da.hh	m1, a3
+
+# CHECK-INST: muls.dd.ll	m1, m2
+# CHECK: encoding: [0x04,0x40,0x2c]
+	muls.dd.ll	m1, m2
+# CHECK-INST: muls.dd.lh	m1, m2
+# CHECK: encoding: [0x04,0x40,0x2e]
+	muls.dd.lh	m1, m2
+# CHECK-INST: muls.dd.hl	m1, m2
+# CHECK: encoding: [0x04,0x40,0x2d]
+	muls.dd.hl	m1, m2
+# CHECK-INST: muls.dd.hh	m1, m2
+# CHECK: encoding: [0x04,0x40,0x2f]
+	muls.dd.hh	m1, m2
+
+# CHECK-INST: mula.da.ll.lddec	 m1, a8, m0, a3
+# CHECK: encoding: [0x34,0x18,0x58]
+	mula.da.ll.lddec	 m1, a8, m0, a3
+# CHECK-INST: mula.da.hl.lddec	 m1, a8, m0, a3
+# CHECK: encoding: [0x34,0x18,0x59]
+	mula.da.hl.lddec	 m1, a8, m0, a3
+# CHECK-INST: mula.da.lh.lddec	 m1, a8, m0, a3
+# CHECK: encoding: [0x34,0x18,0x5a]
+	mula.da.lh.lddec	 m1, a8, m0, a3
+# CHECK-INST: mula.da.hh.lddec	 m1, a8, m0, a3
+# CHECK: encoding: [0x34,0x18,0x5b]
+	mula.da.hh.lddec	 m1, a8, m0, a3
+
+# CHECK-INST: mula.dd.ll.lddec	 m1, a8, m0, m2
+# CHECK: encoding: [0x04,0x18,0x18]
+	mula.dd.ll.lddec	 m1, a8, m0, m2
+# CHECK-INST: mula.dd.hl.lddec	 m1, a8, m0, m2
+# CHECK: encoding: [0x04,0x18,0x19]
+	mula.dd.hl.lddec	 m1, a8, m0, m2
+# CHECK-INST: mula.dd.lh.lddec	 m1, a8, m0, m2
+# CHECK: encoding: [0x04,0x18,0x1a]
+	mula.dd.lh.lddec	 m1, a8, m0, m2
+# CHECK-INST: mula.dd.hh.lddec	 m1, a8, m0, m2
+# CHECK: encoding: [0x04,0x18,0x1b]
+	mula.dd.hh.lddec	 m1, a8, m0, m2
+
+# CHECK-INST: mula.da.ll.ldinc	 m1, a8, m0, a3
+# CHECK: encoding: [0x34,0x18,0x48]
+	mula.da.ll.ldinc	 m1, a8, m0, a3
+# CHECK-INST: mula.da.hl.ldinc	 m1, a8, m0, a3
+# CHECK: encoding: [0x34,0x18,0x49]
+	mula.da.hl.ldinc	 m1, a8, m0, a3
+# CHECK-INST: mula.da.lh.ldinc	 m1, a8, m0, a3
+# CHECK: encoding: [0x34,0x18,0x4a]
+	mula.da.lh.ldinc	 m1, a8, m0, a3
+# CHECK-INST: mula.da.hh.ldinc	 m1, a8, m0, a3
+# CHECK: encoding: [0x34,0x18,0x4b]
+	mula.da.hh.ldinc	 m1, a8, m0, a3
+
+# CHECK-INST: mula.dd.ll.ldinc	 m1, a8, m0, m2
+# CHECK: encoding: [0x04,0x18,0x08]
+	mula.dd.ll.ldinc	 m1, a8, m0, m2
+# CHECK-INST: mula.dd.hl.ldinc	 m1, a8, m0, m2
+# CHECK: encoding: [0x04,0x18,0x09]
+	mula.dd.hl.ldinc	 m1, a8, m0, m2
+# CHECK-INST: mula.dd.lh.ldinc	 m1, a8, m0, m2
+# CHECK: encoding: [0x04,0x18,0x0a]
+	mula.dd.lh.ldinc	 m1, a8, m0, m2
+# CHECK-INST: mula.dd.hh.ldinc	 m1, a8, m0, m2
+# CHECK: encoding: [0x04,0x18,0x0b]
+	mula.dd.hh.ldinc	 m1, a8, m0, m2
+
+# CHECK-INST: lddec	 m0, a8
+# CHECK: encoding: [0x04,0x08,0x90]
+	lddec	 m0, a8
+# CHECK-INST: ldinc	 m0, a8
+# CHECK: encoding: [0x04,0x08,0x80]
+	ldinc	 m0, a8
+
-- 
2.40.1