Hardware info from David Moon

Peter Lothberg wrote:

How wide is the adress bus output from the paging box?

I think it varied on each KA10. In the original design, it was 19 bits (i.e. just one extra bit was added). Later a second extra bit was added to some copies. And I think that some sections(!) of the memory bus on some machines were later diddled to have 22-bit addressing compatible with the KI10 and KL10, but bits 14 and 15 were hard-wired to zero rather than coming out of the paging box associative memories. For further complexity, on one machine there was a pdp6 involved, which had its own idea of the meanings of some of the memory bus lines that DEC later recycled to be the extra address bits.

I'd have to check the prints to be sure of the details, but the overall story is that there is no simple answer. If you build something, you can make it do whatever you want, rather than be exactly compatible with any one of the three copies of the KA10 paging box. The software really doesn't care; even the format of page-table entries is parameterized, since it has been different on every machine ITS has run on.

Is the data chanel (DF10) a 18 or 22 adress bit device?

Again, there isn't a simple answer. MIT-AI (the old one: the KA) didn't have any DF10's. It had a one-of-a-kind combined disk and serial-line controller, which was the only DMA device. If I remember correctly it was originally an 18-bit address device but was later expanded to 20 bits of address. The other devices that you would expect to be DMA (mag tape, dec tape, ARPA network, 340 display, maybe analog I/O) all worked by using the KA10's single-instruction interrupt handler feature. All our KA10's were modified to have an extra I/O bus cable which added seven additional interrupt levels, each with its own pair of interrupt instructions in locations 62-77. These were all at the same priority level as channel 1 in the standard interrupt levels (highest priority), hence this was called the "channel 1 multiplex feature." If I remember correctly the hardware for this was a single flip chip module (a custom module designed at MIT, not a standard DEC module) containing only a few parts. You might want to do this too, if you have a lot of I/O devices.

MIT-AI also had a device, which was heavily used for many years although it never worked reliably, that mapped portions of the pdp10's address space into eight pdp-11 Unibuses. The pdp-11's in question (they weren't all real pdp-11's; one was a Lisp machine and one was a Chess machine) were scattered around the lab; some were I/O controllers for the pdp-10, while others were independent machines that just used this device as a high-speed link to the timesharing system. The effect of this hardware was to make pdp-11 memory look like extremely slow pdp-10 memory with the right-hand 4 bits of each word missing. A user program in the timesharing system could issue a system call to map an arbitrary portion of an arbitrary pdp-11's memory into its virtual address space and could then do whatever it wanted to it. These references were mapped through the usual virtual-to-physical page map and then again through a pdp-10-physical to pdp-11-physical page map located inside the 10/11 interface device.

MIT-ML and MIT-DM (also KA's) had 18-bit DF10's with a special kludge modification (disabled with a toggle switch for running DEC diagnostics) to take extra address bits from the complement of some high-order bits of the count. The complementation is so that with a small count (which is negative) you address the low-order memory, for compatibility. I fear that idiots may have thrown away the documentation of this modification.

MIT-MC (a KL) has 22-bit DF10's. MIT-AI (a KS) uses RH-11's in place of DF-10's!

The software really doesn't care what kind of data channel you use as long as it can address all of memory somehow. If it isn't the same as any of the channels it already knows about a few instructions in several places would have to be changed.

The existing page relocating and protection logic circuit is it used for any purpose, or is it just "shorted out" ?

It's not used. If I remember correctly, it is actually removed and the space in the machine is used for something else. It's valuable space because it already has power wiring for TTL logic (I suppose you've discovered that here and there in the KA10 there is early TTL logic, with its power and ground offset from the DEC power and ground to make the logic levels compatible, since they are both voltage logics with the levels separated by approximately 3 volts). I'd have to check the prints to see what was put there. Incidentally, the way the interface between the processor and the paging box works is approximately as follows. The data portion of the memory bus simply connects to both of them. Data transfers between the two always go through memory (there is an instruction that reads eight words from memory and loads them into all the registers in the paging box, and another instruction that stores eight words into memory). The address portion of the memory bus leaves the processor with a virtual address on it and is received by the paging box. It maps the address and drives a second set of cables with the physical address; the processor doesn't know that it isn't talking directly to the memories. I forget who drives the control portion of the memory bus; I think the processor does, but the paging box controls what it drives? In addition to the memory bus, a large number of control and timing signals pass between the two boxes on several cables. A lot of the memory-subroutine pulses go back and forth, also instruction timing signals for the paging-box-manipulating instructions, and signals associated with page-fault reporting. The paging box does not connect to the I/O bus.

Is the paging box use the existing "memory protection violation" interupt/status logic ?

Sort of. If I remember correctly, there is a big mess of hand changes on the prints here. What it amounts to is that it uses the existing logic, but it has to fix a lot of bugs in it because DEC never intended for it to be possible to restart an instruction after a memory protection violation. Things I remember: the store-cycle timing pulses are rearranged to check for write access to the memory operand before modifying the accumulator; if a page fault is pending the check for interrupts is done earlier so there won't be a 1-instruction delay before the page-fault interrupt goes off; if a page fault is about to go off the store-cycle is inhibited from changing anything; the PC and PC flags are captured at the beginning of each instruction by a register in the paging box, so changes to them are allowed to go through; some bugs with MPV in BLT are fixed.

I hope we can find an accurate KA10 print set with all the ITS modifications. There really was accurate documentation for each KA10 when we had the KA10s, but they're all gone now. I'm not in the right place to look, and I'm also not in the same place as my personal copy (which is not at all accurate).

By the way, I wasn't present when all these modifications were designed and implemented. I know a good deal about them though, since I had to maintain them for several years.

One more point. This 1970 paging box was a separate bay, standing next to bay 1 of the KA (except on the AI machine where it stood next to bay 3 for some reason), containing about half a dozen wire wrap boards of TTL plus two DEC flip-chip racks full of Systems Concepts DEC<->TTL level converters and cable connectors. From the 1985 standpoint, that seems like a real waste. If I were doing it today, I would try to design something using today's TTL parts, packaged on double-height flip-chip modules, that would fit in the space where the relocate/protect logic goes that would do the whole job and wouldn't require level convertors. I'd probably try to use that TI 512-entry cache-directory chip, since with 256 system pages plus 256 user pages it would fit nicely.

That would be easier and more elegant since you wouldn't need to change the cabling at all. Of course there are still the various internal changes to the processor logic, which would be done by re-wire-wrapping the backplane and adding standard B-series flip-chip modules where necessary (there is probably enough spare space since that is how it was done at MIT).

If your 1985-technology paging box didn't turn out 100% software compatible with the 1970-technology one, there is no harm done since ITS is already software compatible with three paging boxes and a fourth can be added as long as it only differs in detail and not in function (the bit layout of page table words, the exact way page faults are reported, the instructions to control the paging box, the size and organization of the associative memory could all be changed).