From caebb928c593f893305d7f12c4cccbc813798306 Mon Sep 17 00:00:00 2001 From: Peter-Herrmann Date: Sat, 4 Nov 2023 14:48:43 -0700 Subject: [PATCH] verilog only syntax --- wishbone/wb_to_obi.v | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/wishbone/wb_to_obi.v b/wishbone/wb_to_obi.v index c27091d..9c611cd 100644 --- a/wishbone/wb_to_obi.v +++ b/wishbone/wb_to_obi.v @@ -43,7 +43,8 @@ module wb_to_obi ( input [31:0] rdata_i ); - logic read_outstanding, write_completed, read_accepted_a, write_accepted_a; + reg read_outstanding, write_completed; + wire read_accepted_a, write_accepted_a; assign read_accepted_a = (req_o && gnt_i) && !wbs_we_i; assign write_accepted_a = (req_o && gnt_i) && wbs_we_i;