From 4659e0bfa57694890476b499dc0e6204c2890f4c Mon Sep 17 00:00:00 2001 From: Vin Huang Date: Wed, 31 Jul 2024 10:01:37 +0800 Subject: [PATCH] Enable UseScaleAlphaVec in YAML files --- .../Tensile/Logic/aquavanjaram/- Euclidean | 0 ...ijk_Ailk_Bjlk_BBS_BH_Bias_FDMN_SPA_AS.yaml | 76 ++-- ...ijk_Ailk_Bjlk_BBS_BH_Bias_FDMN_SPB_AS.yaml | 42 +-- ...vanjaram_Cijk_Ailk_Bjlk_BBS_BH_SPB_AS.yaml | 38 +- ...ijk_Ailk_Bjlk_HHS_BH_Bias_FDMN_SPA_AS.yaml | 78 ++-- ...ijk_Ailk_Bjlk_HHS_BH_Bias_FDMN_SPB_AS.yaml | 44 +-- ...vanjaram_Cijk_Ailk_Bjlk_HHS_BH_SPB_AS.yaml | 24 +- ...k_Ailk_Bjlk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml | 22 +- ...k_Ailk_Bjlk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml | 22 +- ...k_Ailk_Bjlk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml | 22 +- ...k_Ailk_Bjlk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml | 20 +- ...k_Ailk_Bjlk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml | 64 ++-- ...k_Ailk_Bjlk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml | 32 +- ...ijk_Ailk_Bljk_BBS_BH_Bias_FDMN_SPA_AS.yaml | 80 ++--- ...ijk_Ailk_Bljk_BBS_BH_Bias_FDMN_SPB_AS.yaml | 50 +-- ...vanjaram_Cijk_Ailk_Bljk_BBS_BH_SPB_AS.yaml | 44 +-- ...ijk_Ailk_Bljk_HHS_BH_Bias_FDMN_SPA_AS.yaml | 82 ++--- ...ijk_Ailk_Bljk_HHS_BH_Bias_FDMN_SPB_AS.yaml | 44 +-- ...vanjaram_Cijk_Ailk_Bljk_HHS_BH_SPB_AS.yaml | 46 +-- ...k_Ailk_Bljk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml | 22 +- ...k_Ailk_Bljk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml | 24 +- ...k_Ailk_Bljk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml | 20 +- ...k_Ailk_Bljk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml | 22 +- ...k_Ailk_Bljk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml | 82 ++--- ...k_Ailk_Bljk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml | 44 +-- ...ijk_Alik_Bjlk_BBS_BH_Bias_FDMN_SPA_AS.yaml | 76 ++-- ...ijk_Alik_Bjlk_BBS_BH_Bias_FDMN_SPB_AS.yaml | 26 +- ...vanjaram_Cijk_Alik_Bjlk_BBS_BH_SPB_AS.yaml | 24 +- ...ijk_Alik_Bjlk_HHS_BH_Bias_FDMN_SPA_AS.yaml | 76 ++-- ...ijk_Alik_Bjlk_HHS_BH_Bias_FDMN_SPB_AS.yaml | 32 +- ...vanjaram_Cijk_Alik_Bjlk_HHS_BH_SPB_AS.yaml | 34 +- ...k_Alik_Bjlk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml | 24 +- ...k_Alik_Bjlk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml | 22 +- ...k_Alik_Bjlk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml | 22 +- ...k_Alik_Bjlk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml | 20 +- ...k_Alik_Bjlk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml | 335 ++---------------- ...k_Alik_Bjlk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml | 44 +-- ...ijk_Alik_Bljk_BBS_BH_Bias_FDMN_SPA_AS.yaml | 88 ++--- ...ijk_Alik_Bljk_BBS_BH_Bias_FDMN_SPB_AS.yaml | 40 +-- ...vanjaram_Cijk_Alik_Bljk_BBS_BH_SPB_AS.yaml | 44 +-- ...ijk_Alik_Bljk_HHS_BH_Bias_FDMN_SPA_AS.yaml | 88 ++--- ...ijk_Alik_Bljk_HHS_BH_Bias_FDMN_SPB_AS.yaml | 40 +-- ...vanjaram_Cijk_Alik_Bljk_HHS_BH_SPB_AS.yaml | 24 +- ...k_Alik_Bljk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml | 26 +- ...k_Alik_Bljk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml | 24 +- ...k_Alik_Bljk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml | 24 +- ...k_Alik_Bljk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml | 22 +- ...k_Alik_Bljk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml | 66 ++-- ...k_Alik_Bljk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml | 44 +-- ...ijk_Ailk_Bjlk_BBS_BH_Bias_FDMN_SPA_AS.yaml | 76 ++-- ...ijk_Ailk_Bjlk_BBS_BH_Bias_FDMN_SPB_AS.yaml | 42 +-- ...vanjaram_Cijk_Ailk_Bjlk_BBS_BH_SPB_AS.yaml | 38 +- ...ijk_Ailk_Bjlk_HHS_BH_Bias_FDMN_SPA_AS.yaml | 78 ++-- ...ijk_Ailk_Bjlk_HHS_BH_Bias_FDMN_SPB_AS.yaml | 44 +-- ...vanjaram_Cijk_Ailk_Bjlk_HHS_BH_SPB_AS.yaml | 24 +- ...k_Ailk_Bjlk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml | 22 +- ...k_Ailk_Bjlk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml | 20 +- ...k_Ailk_Bjlk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml | 22 +- ...k_Ailk_Bjlk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml | 20 +- ...k_Ailk_Bjlk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml | 64 ++-- ...k_Ailk_Bjlk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml | 32 +- ...ijk_Ailk_Bljk_BBS_BH_Bias_FDMN_SPA_AS.yaml | 80 ++--- ...ijk_Ailk_Bljk_BBS_BH_Bias_FDMN_SPB_AS.yaml | 50 +-- ...vanjaram_Cijk_Ailk_Bljk_BBS_BH_SPB_AS.yaml | 44 +-- ...ijk_Ailk_Bljk_HHS_BH_Bias_FDMN_SPA_AS.yaml | 82 ++--- ...ijk_Ailk_Bljk_HHS_BH_Bias_FDMN_SPB_AS.yaml | 44 +-- ...vanjaram_Cijk_Ailk_Bljk_HHS_BH_SPB_AS.yaml | 46 +-- ...k_Ailk_Bljk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml | 20 +- ...k_Ailk_Bljk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml | 22 +- ...k_Ailk_Bljk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml | 20 +- ...k_Ailk_Bljk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml | 22 +- ...k_Ailk_Bljk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml | 82 ++--- ...k_Ailk_Bljk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml | 44 +-- ...ijk_Alik_Bjlk_BBS_BH_Bias_FDMN_SPA_AS.yaml | 76 ++-- ...ijk_Alik_Bjlk_BBS_BH_Bias_FDMN_SPB_AS.yaml | 26 +- ...vanjaram_Cijk_Alik_Bjlk_BBS_BH_SPB_AS.yaml | 24 +- ...ijk_Alik_Bjlk_HHS_BH_Bias_FDMN_SPA_AS.yaml | 76 ++-- ...ijk_Alik_Bjlk_HHS_BH_Bias_FDMN_SPB_AS.yaml | 32 +- ...vanjaram_Cijk_Alik_Bjlk_HHS_BH_SPB_AS.yaml | 34 +- ...k_Alik_Bjlk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml | 22 +- ...k_Alik_Bjlk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml | 20 +- ...k_Alik_Bjlk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml | 22 +- ...k_Alik_Bjlk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml | 20 +- ...k_Alik_Bjlk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml | 335 ++---------------- ...k_Alik_Bjlk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml | 44 +-- ...ijk_Alik_Bljk_BBS_BH_Bias_FDMN_SPA_AS.yaml | 88 ++--- ...ijk_Alik_Bljk_BBS_BH_Bias_FDMN_SPB_AS.yaml | 40 +-- ...vanjaram_Cijk_Alik_Bljk_BBS_BH_SPB_AS.yaml | 44 +-- ...ijk_Alik_Bljk_HHS_BH_Bias_FDMN_SPA_AS.yaml | 88 ++--- ...ijk_Alik_Bljk_HHS_BH_Bias_FDMN_SPB_AS.yaml | 40 +-- ...vanjaram_Cijk_Alik_Bljk_HHS_BH_SPB_AS.yaml | 24 +- ...k_Alik_Bljk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml | 24 +- ...k_Alik_Bljk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml | 22 +- ...k_Alik_Bljk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml | 24 +- ...k_Alik_Bljk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml | 22 +- ...k_Alik_Bljk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml | 66 ++-- ...k_Alik_Bljk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml | 44 +-- ...ijk_Ailk_Bjlk_BBS_BH_Bias_FDMN_SPA_AS.yaml | 76 ++-- ...ijk_Ailk_Bjlk_BBS_BH_Bias_FDMN_SPB_AS.yaml | 42 +-- ...vanjaram_Cijk_Ailk_Bjlk_BBS_BH_SPB_AS.yaml | 38 +- ...ijk_Ailk_Bjlk_HHS_BH_Bias_FDMN_SPA_AS.yaml | 78 ++-- ...ijk_Ailk_Bjlk_HHS_BH_Bias_FDMN_SPB_AS.yaml | 44 +-- ...vanjaram_Cijk_Ailk_Bjlk_HHS_BH_SPB_AS.yaml | 24 +- ...k_Ailk_Bjlk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml | 22 +- ...k_Ailk_Bjlk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml | 20 +- ...k_Ailk_Bjlk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml | 22 +- ...k_Ailk_Bjlk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml | 20 +- ...k_Ailk_Bjlk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml | 64 ++-- ...k_Ailk_Bjlk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml | 32 +- ...ijk_Ailk_Bljk_BBS_BH_Bias_FDMN_SPA_AS.yaml | 80 ++--- ...ijk_Ailk_Bljk_BBS_BH_Bias_FDMN_SPB_AS.yaml | 50 +-- ...vanjaram_Cijk_Ailk_Bljk_BBS_BH_SPB_AS.yaml | 44 +-- ...ijk_Ailk_Bljk_HHS_BH_Bias_FDMN_SPA_AS.yaml | 82 ++--- ...ijk_Ailk_Bljk_HHS_BH_Bias_FDMN_SPB_AS.yaml | 44 +-- ...vanjaram_Cijk_Ailk_Bljk_HHS_BH_SPB_AS.yaml | 46 +-- ...k_Ailk_Bljk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml | 20 +- ...k_Ailk_Bljk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml | 22 +- ...k_Ailk_Bljk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml | 20 +- ...k_Ailk_Bljk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml | 22 +- ...k_Ailk_Bljk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml | 82 ++--- ...k_Ailk_Bljk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml | 44 +-- ...ijk_Alik_Bjlk_BBS_BH_Bias_FDMN_SPA_AS.yaml | 76 ++-- ...ijk_Alik_Bjlk_BBS_BH_Bias_FDMN_SPB_AS.yaml | 26 +- ...vanjaram_Cijk_Alik_Bjlk_BBS_BH_SPB_AS.yaml | 24 +- ...ijk_Alik_Bjlk_HHS_BH_Bias_FDMN_SPA_AS.yaml | 76 ++-- ...ijk_Alik_Bjlk_HHS_BH_Bias_FDMN_SPB_AS.yaml | 32 +- ...vanjaram_Cijk_Alik_Bjlk_HHS_BH_SPB_AS.yaml | 34 +- ...k_Alik_Bjlk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml | 22 +- ...k_Alik_Bjlk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml | 20 +- ...k_Alik_Bjlk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml | 22 +- ...k_Alik_Bjlk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml | 20 +- ...k_Alik_Bjlk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml | 335 ++---------------- ...k_Alik_Bjlk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml | 44 +-- ...ijk_Alik_Bljk_BBS_BH_Bias_FDMN_SPA_AS.yaml | 88 ++--- ...ijk_Alik_Bljk_BBS_BH_Bias_FDMN_SPB_AS.yaml | 40 +-- ...vanjaram_Cijk_Alik_Bljk_BBS_BH_SPB_AS.yaml | 44 +-- ...ijk_Alik_Bljk_HHS_BH_Bias_FDMN_SPA_AS.yaml | 88 ++--- ...ijk_Alik_Bljk_HHS_BH_Bias_FDMN_SPB_AS.yaml | 40 +-- ...vanjaram_Cijk_Alik_Bljk_HHS_BH_SPB_AS.yaml | 24 +- ...k_Alik_Bljk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml | 24 +- ...k_Alik_Bljk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml | 22 +- ...k_Alik_Bljk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml | 24 +- ...k_Alik_Bljk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml | 22 +- ...k_Alik_Bljk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml | 66 ++-- ...k_Alik_Bljk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml | 44 +-- 145 files changed, 3052 insertions(+), 3847 deletions(-) delete mode 100644 library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/- Euclidean rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx940 => asm_full/aquavanjaram/gfx940/Equality}/aquavanjaram_Cijk_Ailk_Bjlk_BBS_BH_Bias_FDMN_SPA_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx940 => asm_full/aquavanjaram/gfx940/Equality}/aquavanjaram_Cijk_Ailk_Bjlk_BBS_BH_Bias_FDMN_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx940 => asm_full/aquavanjaram/gfx940/Equality}/aquavanjaram_Cijk_Ailk_Bjlk_BBS_BH_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx940 => asm_full/aquavanjaram/gfx940/Equality}/aquavanjaram_Cijk_Ailk_Bjlk_HHS_BH_Bias_FDMN_SPA_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx940 => asm_full/aquavanjaram/gfx940/Equality}/aquavanjaram_Cijk_Ailk_Bjlk_HHS_BH_Bias_FDMN_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx940 => asm_full/aquavanjaram/gfx940/Equality}/aquavanjaram_Cijk_Ailk_Bjlk_HHS_BH_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx940 => asm_full/aquavanjaram/gfx940/Equality}/aquavanjaram_Cijk_Ailk_Bjlk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx940 => asm_full/aquavanjaram/gfx940/Equality}/aquavanjaram_Cijk_Ailk_Bjlk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx940 => asm_full/aquavanjaram/gfx940/Equality}/aquavanjaram_Cijk_Ailk_Bjlk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx940 => asm_full/aquavanjaram/gfx940/Equality}/aquavanjaram_Cijk_Ailk_Bjlk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx940 => asm_full/aquavanjaram/gfx940/Equality}/aquavanjaram_Cijk_Ailk_Bjlk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx940 => asm_full/aquavanjaram/gfx940/Equality}/aquavanjaram_Cijk_Ailk_Bjlk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx940 => asm_full/aquavanjaram/gfx940/Equality}/aquavanjaram_Cijk_Ailk_Bljk_BBS_BH_Bias_FDMN_SPA_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx940 => asm_full/aquavanjaram/gfx940/Equality}/aquavanjaram_Cijk_Ailk_Bljk_BBS_BH_Bias_FDMN_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx940 => asm_full/aquavanjaram/gfx940/Equality}/aquavanjaram_Cijk_Ailk_Bljk_BBS_BH_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx940 => asm_full/aquavanjaram/gfx940/Equality}/aquavanjaram_Cijk_Ailk_Bljk_HHS_BH_Bias_FDMN_SPA_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx940 => asm_full/aquavanjaram/gfx940/Equality}/aquavanjaram_Cijk_Ailk_Bljk_HHS_BH_Bias_FDMN_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx940 => asm_full/aquavanjaram/gfx940/Equality}/aquavanjaram_Cijk_Ailk_Bljk_HHS_BH_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx940 => asm_full/aquavanjaram/gfx940/Equality}/aquavanjaram_Cijk_Ailk_Bljk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx940 => asm_full/aquavanjaram/gfx940/Equality}/aquavanjaram_Cijk_Ailk_Bljk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx940 => asm_full/aquavanjaram/gfx940/Equality}/aquavanjaram_Cijk_Ailk_Bljk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx940 => asm_full/aquavanjaram/gfx940/Equality}/aquavanjaram_Cijk_Ailk_Bljk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx940 => asm_full/aquavanjaram/gfx940/Equality}/aquavanjaram_Cijk_Ailk_Bljk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx940 => asm_full/aquavanjaram/gfx940/Equality}/aquavanjaram_Cijk_Ailk_Bljk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx940 => asm_full/aquavanjaram/gfx940/Equality}/aquavanjaram_Cijk_Alik_Bjlk_BBS_BH_Bias_FDMN_SPA_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx940 => asm_full/aquavanjaram/gfx940/Equality}/aquavanjaram_Cijk_Alik_Bjlk_BBS_BH_Bias_FDMN_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx940 => asm_full/aquavanjaram/gfx940/Equality}/aquavanjaram_Cijk_Alik_Bjlk_BBS_BH_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx940 => asm_full/aquavanjaram/gfx940/Equality}/aquavanjaram_Cijk_Alik_Bjlk_HHS_BH_Bias_FDMN_SPA_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx940 => asm_full/aquavanjaram/gfx940/Equality}/aquavanjaram_Cijk_Alik_Bjlk_HHS_BH_Bias_FDMN_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx940 => asm_full/aquavanjaram/gfx940/Equality}/aquavanjaram_Cijk_Alik_Bjlk_HHS_BH_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx940 => asm_full/aquavanjaram/gfx940/Equality}/aquavanjaram_Cijk_Alik_Bjlk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx940 => asm_full/aquavanjaram/gfx940/Equality}/aquavanjaram_Cijk_Alik_Bjlk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx940 => asm_full/aquavanjaram/gfx940/Equality}/aquavanjaram_Cijk_Alik_Bjlk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx940 => asm_full/aquavanjaram/gfx940/Equality}/aquavanjaram_Cijk_Alik_Bjlk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx940 => asm_full/aquavanjaram/gfx940/Equality}/aquavanjaram_Cijk_Alik_Bjlk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml (96%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx940 => asm_full/aquavanjaram/gfx940/Equality}/aquavanjaram_Cijk_Alik_Bjlk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx940 => asm_full/aquavanjaram/gfx940/Equality}/aquavanjaram_Cijk_Alik_Bljk_BBS_BH_Bias_FDMN_SPA_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx940 => asm_full/aquavanjaram/gfx940/Equality}/aquavanjaram_Cijk_Alik_Bljk_BBS_BH_Bias_FDMN_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx940 => asm_full/aquavanjaram/gfx940/Equality}/aquavanjaram_Cijk_Alik_Bljk_BBS_BH_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx940 => asm_full/aquavanjaram/gfx940/Equality}/aquavanjaram_Cijk_Alik_Bljk_HHS_BH_Bias_FDMN_SPA_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx940 => asm_full/aquavanjaram/gfx940/Equality}/aquavanjaram_Cijk_Alik_Bljk_HHS_BH_Bias_FDMN_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx940 => asm_full/aquavanjaram/gfx940/Equality}/aquavanjaram_Cijk_Alik_Bljk_HHS_BH_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx940 => asm_full/aquavanjaram/gfx940/Equality}/aquavanjaram_Cijk_Alik_Bljk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx940 => asm_full/aquavanjaram/gfx940/Equality}/aquavanjaram_Cijk_Alik_Bljk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx940 => asm_full/aquavanjaram/gfx940/Equality}/aquavanjaram_Cijk_Alik_Bljk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx940 => asm_full/aquavanjaram/gfx940/Equality}/aquavanjaram_Cijk_Alik_Bljk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx940 => asm_full/aquavanjaram/gfx940/Equality}/aquavanjaram_Cijk_Alik_Bljk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx940 => asm_full/aquavanjaram/gfx940/Equality}/aquavanjaram_Cijk_Alik_Bljk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx941 => asm_full/aquavanjaram/gfx941/Equality}/aquavanjaram_Cijk_Ailk_Bjlk_BBS_BH_Bias_FDMN_SPA_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx941 => asm_full/aquavanjaram/gfx941/Equality}/aquavanjaram_Cijk_Ailk_Bjlk_BBS_BH_Bias_FDMN_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx941 => asm_full/aquavanjaram/gfx941/Equality}/aquavanjaram_Cijk_Ailk_Bjlk_BBS_BH_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx941 => asm_full/aquavanjaram/gfx941/Equality}/aquavanjaram_Cijk_Ailk_Bjlk_HHS_BH_Bias_FDMN_SPA_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx941 => asm_full/aquavanjaram/gfx941/Equality}/aquavanjaram_Cijk_Ailk_Bjlk_HHS_BH_Bias_FDMN_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx941 => asm_full/aquavanjaram/gfx941/Equality}/aquavanjaram_Cijk_Ailk_Bjlk_HHS_BH_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx941 => asm_full/aquavanjaram/gfx941/Equality}/aquavanjaram_Cijk_Ailk_Bjlk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx941 => asm_full/aquavanjaram/gfx941/Equality}/aquavanjaram_Cijk_Ailk_Bjlk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx941 => asm_full/aquavanjaram/gfx941/Equality}/aquavanjaram_Cijk_Ailk_Bjlk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx941 => asm_full/aquavanjaram/gfx941/Equality}/aquavanjaram_Cijk_Ailk_Bjlk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx941 => asm_full/aquavanjaram/gfx941/Equality}/aquavanjaram_Cijk_Ailk_Bjlk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx941 => asm_full/aquavanjaram/gfx941/Equality}/aquavanjaram_Cijk_Ailk_Bjlk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx941 => asm_full/aquavanjaram/gfx941/Equality}/aquavanjaram_Cijk_Ailk_Bljk_BBS_BH_Bias_FDMN_SPA_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx941 => asm_full/aquavanjaram/gfx941/Equality}/aquavanjaram_Cijk_Ailk_Bljk_BBS_BH_Bias_FDMN_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx941 => asm_full/aquavanjaram/gfx941/Equality}/aquavanjaram_Cijk_Ailk_Bljk_BBS_BH_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx941 => asm_full/aquavanjaram/gfx941/Equality}/aquavanjaram_Cijk_Ailk_Bljk_HHS_BH_Bias_FDMN_SPA_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx941 => asm_full/aquavanjaram/gfx941/Equality}/aquavanjaram_Cijk_Ailk_Bljk_HHS_BH_Bias_FDMN_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx941 => asm_full/aquavanjaram/gfx941/Equality}/aquavanjaram_Cijk_Ailk_Bljk_HHS_BH_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx941 => asm_full/aquavanjaram/gfx941/Equality}/aquavanjaram_Cijk_Ailk_Bljk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx941 => asm_full/aquavanjaram/gfx941/Equality}/aquavanjaram_Cijk_Ailk_Bljk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx941 => asm_full/aquavanjaram/gfx941/Equality}/aquavanjaram_Cijk_Ailk_Bljk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx941 => asm_full/aquavanjaram/gfx941/Equality}/aquavanjaram_Cijk_Ailk_Bljk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx941 => asm_full/aquavanjaram/gfx941/Equality}/aquavanjaram_Cijk_Ailk_Bljk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx941 => asm_full/aquavanjaram/gfx941/Equality}/aquavanjaram_Cijk_Ailk_Bljk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx941 => asm_full/aquavanjaram/gfx941/Equality}/aquavanjaram_Cijk_Alik_Bjlk_BBS_BH_Bias_FDMN_SPA_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx941 => asm_full/aquavanjaram/gfx941/Equality}/aquavanjaram_Cijk_Alik_Bjlk_BBS_BH_Bias_FDMN_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx941 => asm_full/aquavanjaram/gfx941/Equality}/aquavanjaram_Cijk_Alik_Bjlk_BBS_BH_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx941 => asm_full/aquavanjaram/gfx941/Equality}/aquavanjaram_Cijk_Alik_Bjlk_HHS_BH_Bias_FDMN_SPA_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx941 => asm_full/aquavanjaram/gfx941/Equality}/aquavanjaram_Cijk_Alik_Bjlk_HHS_BH_Bias_FDMN_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx941 => asm_full/aquavanjaram/gfx941/Equality}/aquavanjaram_Cijk_Alik_Bjlk_HHS_BH_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx941 => asm_full/aquavanjaram/gfx941/Equality}/aquavanjaram_Cijk_Alik_Bjlk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx941 => asm_full/aquavanjaram/gfx941/Equality}/aquavanjaram_Cijk_Alik_Bjlk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx941 => asm_full/aquavanjaram/gfx941/Equality}/aquavanjaram_Cijk_Alik_Bjlk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx941 => asm_full/aquavanjaram/gfx941/Equality}/aquavanjaram_Cijk_Alik_Bjlk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx941 => asm_full/aquavanjaram/gfx941/Equality}/aquavanjaram_Cijk_Alik_Bjlk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml (96%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx941 => asm_full/aquavanjaram/gfx941/Equality}/aquavanjaram_Cijk_Alik_Bjlk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx941 => asm_full/aquavanjaram/gfx941/Equality}/aquavanjaram_Cijk_Alik_Bljk_BBS_BH_Bias_FDMN_SPA_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx941 => asm_full/aquavanjaram/gfx941/Equality}/aquavanjaram_Cijk_Alik_Bljk_BBS_BH_Bias_FDMN_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx941 => asm_full/aquavanjaram/gfx941/Equality}/aquavanjaram_Cijk_Alik_Bljk_BBS_BH_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx941 => asm_full/aquavanjaram/gfx941/Equality}/aquavanjaram_Cijk_Alik_Bljk_HHS_BH_Bias_FDMN_SPA_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx941 => asm_full/aquavanjaram/gfx941/Equality}/aquavanjaram_Cijk_Alik_Bljk_HHS_BH_Bias_FDMN_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx941 => asm_full/aquavanjaram/gfx941/Equality}/aquavanjaram_Cijk_Alik_Bljk_HHS_BH_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx941 => asm_full/aquavanjaram/gfx941/Equality}/aquavanjaram_Cijk_Alik_Bljk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx941 => asm_full/aquavanjaram/gfx941/Equality}/aquavanjaram_Cijk_Alik_Bljk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx941 => asm_full/aquavanjaram/gfx941/Equality}/aquavanjaram_Cijk_Alik_Bljk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx941 => asm_full/aquavanjaram/gfx941/Equality}/aquavanjaram_Cijk_Alik_Bljk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx941 => asm_full/aquavanjaram/gfx941/Equality}/aquavanjaram_Cijk_Alik_Bljk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx941 => asm_full/aquavanjaram/gfx941/Equality}/aquavanjaram_Cijk_Alik_Bljk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx942 => asm_full/aquavanjaram/gfx942/Equality}/aquavanjaram_Cijk_Ailk_Bjlk_BBS_BH_Bias_FDMN_SPA_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx942 => asm_full/aquavanjaram/gfx942/Equality}/aquavanjaram_Cijk_Ailk_Bjlk_BBS_BH_Bias_FDMN_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx942 => asm_full/aquavanjaram/gfx942/Equality}/aquavanjaram_Cijk_Ailk_Bjlk_BBS_BH_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx942 => asm_full/aquavanjaram/gfx942/Equality}/aquavanjaram_Cijk_Ailk_Bjlk_HHS_BH_Bias_FDMN_SPA_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx942 => asm_full/aquavanjaram/gfx942/Equality}/aquavanjaram_Cijk_Ailk_Bjlk_HHS_BH_Bias_FDMN_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx942 => asm_full/aquavanjaram/gfx942/Equality}/aquavanjaram_Cijk_Ailk_Bjlk_HHS_BH_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx942 => asm_full/aquavanjaram/gfx942/Equality}/aquavanjaram_Cijk_Ailk_Bjlk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx942 => asm_full/aquavanjaram/gfx942/Equality}/aquavanjaram_Cijk_Ailk_Bjlk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx942 => asm_full/aquavanjaram/gfx942/Equality}/aquavanjaram_Cijk_Ailk_Bjlk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx942 => asm_full/aquavanjaram/gfx942/Equality}/aquavanjaram_Cijk_Ailk_Bjlk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx942 => asm_full/aquavanjaram/gfx942/Equality}/aquavanjaram_Cijk_Ailk_Bjlk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx942 => asm_full/aquavanjaram/gfx942/Equality}/aquavanjaram_Cijk_Ailk_Bjlk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx942 => asm_full/aquavanjaram/gfx942/Equality}/aquavanjaram_Cijk_Ailk_Bljk_BBS_BH_Bias_FDMN_SPA_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx942 => asm_full/aquavanjaram/gfx942/Equality}/aquavanjaram_Cijk_Ailk_Bljk_BBS_BH_Bias_FDMN_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx942 => asm_full/aquavanjaram/gfx942/Equality}/aquavanjaram_Cijk_Ailk_Bljk_BBS_BH_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx942 => asm_full/aquavanjaram/gfx942/Equality}/aquavanjaram_Cijk_Ailk_Bljk_HHS_BH_Bias_FDMN_SPA_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx942 => asm_full/aquavanjaram/gfx942/Equality}/aquavanjaram_Cijk_Ailk_Bljk_HHS_BH_Bias_FDMN_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx942 => asm_full/aquavanjaram/gfx942/Equality}/aquavanjaram_Cijk_Ailk_Bljk_HHS_BH_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx942 => asm_full/aquavanjaram/gfx942/Equality}/aquavanjaram_Cijk_Ailk_Bljk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx942 => asm_full/aquavanjaram/gfx942/Equality}/aquavanjaram_Cijk_Ailk_Bljk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx942 => asm_full/aquavanjaram/gfx942/Equality}/aquavanjaram_Cijk_Ailk_Bljk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx942 => asm_full/aquavanjaram/gfx942/Equality}/aquavanjaram_Cijk_Ailk_Bljk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx942 => asm_full/aquavanjaram/gfx942/Equality}/aquavanjaram_Cijk_Ailk_Bljk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx942 => asm_full/aquavanjaram/gfx942/Equality}/aquavanjaram_Cijk_Ailk_Bljk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx942 => asm_full/aquavanjaram/gfx942/Equality}/aquavanjaram_Cijk_Alik_Bjlk_BBS_BH_Bias_FDMN_SPA_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx942 => asm_full/aquavanjaram/gfx942/Equality}/aquavanjaram_Cijk_Alik_Bjlk_BBS_BH_Bias_FDMN_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx942 => asm_full/aquavanjaram/gfx942/Equality}/aquavanjaram_Cijk_Alik_Bjlk_BBS_BH_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx942 => asm_full/aquavanjaram/gfx942/Equality}/aquavanjaram_Cijk_Alik_Bjlk_HHS_BH_Bias_FDMN_SPA_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx942 => asm_full/aquavanjaram/gfx942/Equality}/aquavanjaram_Cijk_Alik_Bjlk_HHS_BH_Bias_FDMN_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx942 => asm_full/aquavanjaram/gfx942/Equality}/aquavanjaram_Cijk_Alik_Bjlk_HHS_BH_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx942 => asm_full/aquavanjaram/gfx942/Equality}/aquavanjaram_Cijk_Alik_Bjlk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx942 => asm_full/aquavanjaram/gfx942/Equality}/aquavanjaram_Cijk_Alik_Bjlk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx942 => asm_full/aquavanjaram/gfx942/Equality}/aquavanjaram_Cijk_Alik_Bjlk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx942 => asm_full/aquavanjaram/gfx942/Equality}/aquavanjaram_Cijk_Alik_Bjlk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx942 => asm_full/aquavanjaram/gfx942/Equality}/aquavanjaram_Cijk_Alik_Bjlk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml (96%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx942 => asm_full/aquavanjaram/gfx942/Equality}/aquavanjaram_Cijk_Alik_Bjlk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx942 => asm_full/aquavanjaram/gfx942/Equality}/aquavanjaram_Cijk_Alik_Bljk_BBS_BH_Bias_FDMN_SPA_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx942 => asm_full/aquavanjaram/gfx942/Equality}/aquavanjaram_Cijk_Alik_Bljk_BBS_BH_Bias_FDMN_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx942 => asm_full/aquavanjaram/gfx942/Equality}/aquavanjaram_Cijk_Alik_Bljk_BBS_BH_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx942 => asm_full/aquavanjaram/gfx942/Equality}/aquavanjaram_Cijk_Alik_Bljk_HHS_BH_Bias_FDMN_SPA_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx942 => asm_full/aquavanjaram/gfx942/Equality}/aquavanjaram_Cijk_Alik_Bljk_HHS_BH_Bias_FDMN_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx942 => asm_full/aquavanjaram/gfx942/Equality}/aquavanjaram_Cijk_Alik_Bljk_HHS_BH_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx942 => asm_full/aquavanjaram/gfx942/Equality}/aquavanjaram_Cijk_Alik_Bljk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx942 => asm_full/aquavanjaram/gfx942/Equality}/aquavanjaram_Cijk_Alik_Bljk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx942 => asm_full/aquavanjaram/gfx942/Equality}/aquavanjaram_Cijk_Alik_Bljk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx942 => asm_full/aquavanjaram/gfx942/Equality}/aquavanjaram_Cijk_Alik_Bljk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx942 => asm_full/aquavanjaram/gfx942/Equality}/aquavanjaram_Cijk_Alik_Bljk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml (99%) rename library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/{aquavanjaram/gfx942 => asm_full/aquavanjaram/gfx942/Equality}/aquavanjaram_Cijk_Alik_Bljk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml (99%) diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/- Euclidean b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/- Euclidean deleted file mode 100644 index e69de29b..00000000 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Ailk_Bjlk_BBS_BH_Bias_FDMN_SPA_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Ailk_Bjlk_BBS_BH_Bias_FDMN_SPA_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Ailk_Bjlk_BBS_BH_Bias_FDMN_SPA_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Ailk_Bjlk_BBS_BH_Bias_FDMN_SPA_AS.yaml index 10776558..6c2d5fbd 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Ailk_Bjlk_BBS_BH_Bias_FDMN_SPA_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Ailk_Bjlk_BBS_BH_Bias_FDMN_SPA_AS.yaml @@ -74,7 +74,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false - - 1LDSBuffer: 0 @@ -289,7 +289,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -560,7 +560,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -820,7 +820,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1077,7 +1077,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1345,7 +1345,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1605,7 +1605,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1862,7 +1862,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2130,7 +2130,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2390,7 +2390,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2647,7 +2647,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2904,7 +2904,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3172,7 +3172,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3443,7 +3443,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3703,7 +3703,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3960,7 +3960,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4228,7 +4228,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4488,7 +4488,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4745,7 +4745,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -5011,7 +5011,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5280,7 +5280,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5548,7 +5548,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5816,7 +5816,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6084,7 +6084,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6352,7 +6352,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6620,7 +6620,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6888,7 +6888,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7156,7 +7156,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7424,7 +7424,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7692,7 +7692,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7960,7 +7960,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8228,7 +8228,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8496,7 +8496,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8764,7 +8764,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9032,7 +9032,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9300,7 +9300,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9568,7 +9568,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9836,7 +9836,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Ailk_Bjlk_BBS_BH_Bias_FDMN_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Ailk_Bjlk_BBS_BH_Bias_FDMN_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Ailk_Bjlk_BBS_BH_Bias_FDMN_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Ailk_Bjlk_BBS_BH_Bias_FDMN_SPB_AS.yaml index 83260235..7f0ea6c0 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Ailk_Bjlk_BBS_BH_Bias_FDMN_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Ailk_Bjlk_BBS_BH_Bias_FDMN_SPB_AS.yaml @@ -74,7 +74,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -289,7 +289,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -560,7 +560,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -831,7 +831,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1102,7 +1102,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1373,7 +1373,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1644,7 +1644,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1915,7 +1915,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2186,7 +2186,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2457,7 +2457,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2728,7 +2728,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2999,7 +2999,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3270,7 +3270,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3541,7 +3541,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3812,7 +3812,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4083,7 +4083,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4354,7 +4354,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4625,7 +4625,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4896,7 +4896,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5167,7 +5167,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5438,7 +5438,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Ailk_Bjlk_BBS_BH_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Ailk_Bjlk_BBS_BH_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Ailk_Bjlk_BBS_BH_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Ailk_Bjlk_BBS_BH_SPB_AS.yaml index 4f9edbf6..ed9bcfae 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Ailk_Bjlk_BBS_BH_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Ailk_Bjlk_BBS_BH_SPB_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -286,7 +286,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -555,7 +555,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -824,7 +824,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1093,7 +1093,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1362,7 +1362,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1631,7 +1631,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1900,7 +1900,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2169,7 +2169,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2438,7 +2438,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2707,7 +2707,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2976,7 +2976,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3245,7 +3245,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3514,7 +3514,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3783,7 +3783,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4052,7 +4052,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4321,7 +4321,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4590,7 +4590,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4859,7 +4859,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Ailk_Bjlk_HHS_BH_Bias_FDMN_SPA_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Ailk_Bjlk_HHS_BH_Bias_FDMN_SPA_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Ailk_Bjlk_HHS_BH_Bias_FDMN_SPA_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Ailk_Bjlk_HHS_BH_Bias_FDMN_SPA_AS.yaml index 7e179d5e..993bbadb 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Ailk_Bjlk_HHS_BH_Bias_FDMN_SPA_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Ailk_Bjlk_HHS_BH_Bias_FDMN_SPA_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false - - 1LDSBuffer: 0 @@ -277,7 +277,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -534,7 +534,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -791,7 +791,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1059,7 +1059,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1330,7 +1330,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1590,7 +1590,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1858,7 +1858,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2129,7 +2129,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2400,7 +2400,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2671,7 +2671,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2931,7 +2931,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3188,7 +3188,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3456,7 +3456,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3727,7 +3727,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3987,7 +3987,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4244,7 +4244,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4501,7 +4501,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4769,7 +4769,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -5040,7 +5040,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -5309,7 +5309,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5578,7 +5578,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5846,7 +5846,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6114,7 +6114,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6382,7 +6382,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6650,7 +6650,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6918,7 +6918,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7186,7 +7186,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7454,7 +7454,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7722,7 +7722,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7990,7 +7990,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8258,7 +8258,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8526,7 +8526,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8794,7 +8794,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9062,7 +9062,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9330,7 +9330,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9598,7 +9598,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9866,7 +9866,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -10134,7 +10134,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Ailk_Bjlk_HHS_BH_Bias_FDMN_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Ailk_Bjlk_HHS_BH_Bias_FDMN_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Ailk_Bjlk_HHS_BH_Bias_FDMN_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Ailk_Bjlk_HHS_BH_Bias_FDMN_SPB_AS.yaml index c992582c..be3aeb20 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Ailk_Bjlk_HHS_BH_Bias_FDMN_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Ailk_Bjlk_HHS_BH_Bias_FDMN_SPB_AS.yaml @@ -74,7 +74,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -289,7 +289,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -560,7 +560,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -831,7 +831,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1102,7 +1102,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1373,7 +1373,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1644,7 +1644,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1915,7 +1915,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2186,7 +2186,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2457,7 +2457,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2728,7 +2728,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2999,7 +2999,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3270,7 +3270,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3541,7 +3541,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3812,7 +3812,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4083,7 +4083,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4354,7 +4354,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4625,7 +4625,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4896,7 +4896,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5167,7 +5167,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5438,7 +5438,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5709,7 +5709,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Ailk_Bjlk_HHS_BH_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Ailk_Bjlk_HHS_BH_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Ailk_Bjlk_HHS_BH_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Ailk_Bjlk_HHS_BH_SPB_AS.yaml index c89b162a..f6f8e836 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Ailk_Bjlk_HHS_BH_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Ailk_Bjlk_HHS_BH_SPB_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -286,7 +286,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -555,7 +555,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -824,7 +824,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1093,7 +1093,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1362,7 +1362,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1631,7 +1631,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1900,7 +1900,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2169,7 +2169,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2438,7 +2438,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2707,7 +2707,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2976,7 +2976,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Ailk_Bjlk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Ailk_Bjlk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Ailk_Bjlk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Ailk_Bjlk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml index 04ecbe1c..caeb701f 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Ailk_Bjlk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Ailk_Bjlk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -287,7 +287,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -546,7 +546,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -813,7 +813,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1072,7 +1072,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1339,7 +1339,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1609,7 +1609,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1879,7 +1879,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2149,7 +2149,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2419,7 +2419,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2678,7 +2678,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Ailk_Bjlk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Ailk_Bjlk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Ailk_Bjlk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Ailk_Bjlk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml index 393776df..f7681b5f 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Ailk_Bjlk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Ailk_Bjlk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml @@ -1,6 +1,6 @@ - {MinimumRequiredVersion: 4.33.0} - aquavanjaram -- gfx942 +- gfx940 - [Device 0049, Device 0050] - Activation: true ActivationComputeDataType: 0 @@ -74,7 +74,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -289,7 +289,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -560,7 +560,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -831,7 +831,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1102,7 +1102,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1373,7 +1373,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1644,7 +1644,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1915,7 +1915,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2186,7 +2186,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2457,7 +2457,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Ailk_Bjlk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Ailk_Bjlk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Ailk_Bjlk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Ailk_Bjlk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml index 7495518a..0269c6c4 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Ailk_Bjlk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Ailk_Bjlk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -287,7 +287,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -546,7 +546,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -813,7 +813,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1072,7 +1072,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1339,7 +1339,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1609,7 +1609,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1879,7 +1879,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2149,7 +2149,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2419,7 +2419,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2678,7 +2678,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Ailk_Bjlk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Ailk_Bjlk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Ailk_Bjlk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Ailk_Bjlk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml index 0e529f7b..ffc5fb01 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Ailk_Bjlk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Ailk_Bjlk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml @@ -74,7 +74,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -289,7 +289,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -560,7 +560,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -831,7 +831,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1102,7 +1102,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1373,7 +1373,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1644,7 +1644,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1915,7 +1915,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2186,7 +2186,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2457,7 +2457,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Ailk_Bjlk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Ailk_Bjlk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Ailk_Bjlk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Ailk_Bjlk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml index 2c2871f7..c55a85f9 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Ailk_Bjlk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Ailk_Bjlk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false - - 1LDSBuffer: 0 @@ -288,7 +288,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -548,7 +548,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -805,7 +805,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1073,7 +1073,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1344,7 +1344,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1615,7 +1615,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1886,7 +1886,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2146,7 +2146,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2403,7 +2403,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2660,7 +2660,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2928,7 +2928,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3199,7 +3199,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3459,7 +3459,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3716,7 +3716,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3984,7 +3984,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4244,7 +4244,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4507,7 +4507,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4772,7 +4772,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5037,7 +5037,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5302,7 +5302,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5567,7 +5567,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5832,7 +5832,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6097,7 +6097,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6362,7 +6362,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6627,7 +6627,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6892,7 +6892,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7157,7 +7157,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7422,7 +7422,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7687,7 +7687,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7952,7 +7952,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8217,7 +8217,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Ailk_Bjlk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Ailk_Bjlk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Ailk_Bjlk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Ailk_Bjlk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml index c24104ad..54188e1d 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Ailk_Bjlk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Ailk_Bjlk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml @@ -74,7 +74,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -289,7 +289,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -560,7 +560,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -831,7 +831,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1102,7 +1102,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1373,7 +1373,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1644,7 +1644,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1915,7 +1915,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2186,7 +2186,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2457,7 +2457,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2728,7 +2728,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2999,7 +2999,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3270,7 +3270,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3541,7 +3541,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3812,7 +3812,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4083,7 +4083,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Ailk_Bljk_BBS_BH_Bias_FDMN_SPA_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Ailk_Bljk_BBS_BH_Bias_FDMN_SPA_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Ailk_Bljk_BBS_BH_Bias_FDMN_SPA_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Ailk_Bljk_BBS_BH_Bias_FDMN_SPA_AS.yaml index 96834db1..6e2620dd 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Ailk_Bljk_BBS_BH_Bias_FDMN_SPA_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Ailk_Bljk_BBS_BH_Bias_FDMN_SPA_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false - - 1LDSBuffer: 0 @@ -277,7 +277,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -545,7 +545,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -805,7 +805,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1062,7 +1062,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1330,7 +1330,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1590,7 +1590,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1858,7 +1858,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2118,7 +2118,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2386,7 +2386,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2646,7 +2646,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2903,7 +2903,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3160,7 +3160,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3417,7 +3417,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3674,7 +3674,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3931,7 +3931,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4188,7 +4188,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4445,7 +4445,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4711,7 +4711,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4979,7 +4979,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5247,7 +5247,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5515,7 +5515,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5783,7 +5783,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6051,7 +6051,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6319,7 +6319,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6587,7 +6587,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6855,7 +6855,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7123,7 +7123,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7391,7 +7391,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7659,7 +7659,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7927,7 +7927,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8195,7 +8195,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8463,7 +8463,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8731,7 +8731,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8999,7 +8999,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9267,7 +9267,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9535,7 +9535,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9803,7 +9803,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -10071,7 +10071,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -10339,7 +10339,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Ailk_Bljk_BBS_BH_Bias_FDMN_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Ailk_Bljk_BBS_BH_Bias_FDMN_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Ailk_Bljk_BBS_BH_Bias_FDMN_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Ailk_Bljk_BBS_BH_Bias_FDMN_SPB_AS.yaml index f921dbab..44bbcd4c 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Ailk_Bljk_BBS_BH_Bias_FDMN_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Ailk_Bljk_BBS_BH_Bias_FDMN_SPB_AS.yaml @@ -74,7 +74,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -289,7 +289,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -560,7 +560,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -831,7 +831,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1102,7 +1102,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1373,7 +1373,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1644,7 +1644,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1915,7 +1915,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2186,7 +2186,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2457,7 +2457,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2728,7 +2728,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2999,7 +2999,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3270,7 +3270,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3541,7 +3541,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3812,7 +3812,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4083,7 +4083,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4354,7 +4354,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4625,7 +4625,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4896,7 +4896,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5167,7 +5167,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5438,7 +5438,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5709,7 +5709,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5980,7 +5980,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6251,7 +6251,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6522,7 +6522,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Ailk_Bljk_BBS_BH_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Ailk_Bljk_BBS_BH_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Ailk_Bljk_BBS_BH_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Ailk_Bljk_BBS_BH_SPB_AS.yaml index 771ca428..26d15f68 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Ailk_Bljk_BBS_BH_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Ailk_Bljk_BBS_BH_SPB_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -286,7 +286,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -555,7 +555,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -824,7 +824,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1093,7 +1093,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1362,7 +1362,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1631,7 +1631,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1900,7 +1900,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2169,7 +2169,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2438,7 +2438,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2707,7 +2707,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2976,7 +2976,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3245,7 +3245,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3514,7 +3514,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3783,7 +3783,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4052,7 +4052,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4321,7 +4321,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4590,7 +4590,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4859,7 +4859,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5128,7 +5128,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5397,7 +5397,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5666,7 +5666,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Ailk_Bljk_HHS_BH_Bias_FDMN_SPA_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Ailk_Bljk_HHS_BH_Bias_FDMN_SPA_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Ailk_Bljk_HHS_BH_Bias_FDMN_SPA_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Ailk_Bljk_HHS_BH_Bias_FDMN_SPA_AS.yaml index 915d68fb..d5eb642e 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Ailk_Bljk_HHS_BH_Bias_FDMN_SPA_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Ailk_Bljk_HHS_BH_Bias_FDMN_SPA_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false - - 1LDSBuffer: 0 @@ -288,7 +288,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -559,7 +559,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -819,7 +819,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1076,7 +1076,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1333,7 +1333,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1590,7 +1590,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1858,7 +1858,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2129,7 +2129,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2400,7 +2400,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2660,7 +2660,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2928,7 +2928,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3199,7 +3199,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3459,7 +3459,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3716,7 +3716,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3973,7 +3973,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4230,7 +4230,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4487,7 +4487,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4744,7 +4744,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -5010,7 +5010,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5278,7 +5278,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5546,7 +5546,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5814,7 +5814,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6082,7 +6082,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6350,7 +6350,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6618,7 +6618,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6886,7 +6886,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7154,7 +7154,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7422,7 +7422,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7690,7 +7690,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7958,7 +7958,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8226,7 +8226,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8494,7 +8494,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8762,7 +8762,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9030,7 +9030,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9298,7 +9298,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9566,7 +9566,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9834,7 +9834,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -10102,7 +10102,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -10370,7 +10370,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -10638,7 +10638,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Ailk_Bljk_HHS_BH_Bias_FDMN_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Ailk_Bljk_HHS_BH_Bias_FDMN_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Ailk_Bljk_HHS_BH_Bias_FDMN_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Ailk_Bljk_HHS_BH_Bias_FDMN_SPB_AS.yaml index edabb548..e93568ea 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Ailk_Bljk_HHS_BH_Bias_FDMN_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Ailk_Bljk_HHS_BH_Bias_FDMN_SPB_AS.yaml @@ -74,7 +74,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -289,7 +289,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -560,7 +560,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -831,7 +831,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1102,7 +1102,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1373,7 +1373,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1644,7 +1644,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1915,7 +1915,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2186,7 +2186,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2457,7 +2457,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2728,7 +2728,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2999,7 +2999,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3270,7 +3270,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3541,7 +3541,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3812,7 +3812,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4083,7 +4083,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4354,7 +4354,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4625,7 +4625,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4896,7 +4896,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5167,7 +5167,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5438,7 +5438,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5709,7 +5709,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Ailk_Bljk_HHS_BH_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Ailk_Bljk_HHS_BH_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Ailk_Bljk_HHS_BH_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Ailk_Bljk_HHS_BH_SPB_AS.yaml index 18b75307..6ef4fe59 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Ailk_Bljk_HHS_BH_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Ailk_Bljk_HHS_BH_SPB_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -286,7 +286,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -555,7 +555,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -824,7 +824,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1093,7 +1093,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1362,7 +1362,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1631,7 +1631,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1900,7 +1900,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2169,7 +2169,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2438,7 +2438,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2707,7 +2707,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2976,7 +2976,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3245,7 +3245,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3514,7 +3514,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3783,7 +3783,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4052,7 +4052,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4321,7 +4321,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4590,7 +4590,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4859,7 +4859,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5128,7 +5128,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5397,7 +5397,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5666,7 +5666,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5935,7 +5935,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Ailk_Bljk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Ailk_Bljk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Ailk_Bljk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Ailk_Bljk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml index 0ea6b9e0..db469a71 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Ailk_Bljk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Ailk_Bljk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml @@ -1,6 +1,6 @@ - {MinimumRequiredVersion: 4.33.0} - aquavanjaram -- gfx942 +- gfx940 - [Device 0049, Device 0050] - Activation: true ActivationComputeDataType: 0 @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -287,7 +287,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -557,7 +557,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -816,7 +816,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1083,7 +1083,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1342,7 +1342,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1609,7 +1609,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1868,7 +1868,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2124,7 +2124,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2391,7 +2391,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Ailk_Bljk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Ailk_Bljk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Ailk_Bljk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Ailk_Bljk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml index d517f3b5..66188beb 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Ailk_Bljk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Ailk_Bljk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml @@ -1,6 +1,6 @@ - {MinimumRequiredVersion: 4.33.0} - aquavanjaram -- gfx942 +- gfx940 - [Device 0049, Device 0050] - Activation: true ActivationComputeDataType: 0 @@ -74,7 +74,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -289,7 +289,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -560,7 +560,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -831,7 +831,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1102,7 +1102,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1373,7 +1373,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1644,7 +1644,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1915,7 +1915,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2186,7 +2186,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2457,7 +2457,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2728,7 +2728,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Ailk_Bljk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Ailk_Bljk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Ailk_Bljk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Ailk_Bljk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml index ac63feb0..e7520636 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Ailk_Bljk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Ailk_Bljk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -287,7 +287,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -557,7 +557,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -816,7 +816,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1083,7 +1083,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1342,7 +1342,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1609,7 +1609,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1868,7 +1868,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2124,7 +2124,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2391,7 +2391,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Ailk_Bljk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Ailk_Bljk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Ailk_Bljk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Ailk_Bljk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml index f25b6e7d..6ee6bae6 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Ailk_Bljk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Ailk_Bljk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml @@ -74,7 +74,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -289,7 +289,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -560,7 +560,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -831,7 +831,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1102,7 +1102,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1373,7 +1373,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1644,7 +1644,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1915,7 +1915,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2186,7 +2186,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2457,7 +2457,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2728,7 +2728,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Ailk_Bljk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Ailk_Bljk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Ailk_Bljk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Ailk_Bljk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml index 4efafa96..c5213a5e 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Ailk_Bljk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Ailk_Bljk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false - - 1LDSBuffer: 0 @@ -288,7 +288,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -559,7 +559,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -819,7 +819,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1076,7 +1076,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1344,7 +1344,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1604,7 +1604,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1872,7 +1872,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2143,7 +2143,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2403,7 +2403,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2671,7 +2671,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2931,7 +2931,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3199,7 +3199,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3470,7 +3470,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3741,7 +3741,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4001,7 +4001,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4258,7 +4258,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4526,7 +4526,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4786,7 +4786,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -5043,7 +5043,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -5311,7 +5311,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -5577,7 +5577,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5842,7 +5842,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6107,7 +6107,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6372,7 +6372,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6637,7 +6637,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6902,7 +6902,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7167,7 +7167,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7432,7 +7432,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7697,7 +7697,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7962,7 +7962,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8227,7 +8227,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8492,7 +8492,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8757,7 +8757,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9022,7 +9022,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9287,7 +9287,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9552,7 +9552,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9817,7 +9817,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -10082,7 +10082,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -10347,7 +10347,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -10612,7 +10612,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Ailk_Bljk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Ailk_Bljk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Ailk_Bljk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Ailk_Bljk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml index ef911174..3a7f3f31 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Ailk_Bljk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Ailk_Bljk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml @@ -74,7 +74,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -289,7 +289,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -560,7 +560,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -831,7 +831,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1102,7 +1102,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1373,7 +1373,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1644,7 +1644,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1915,7 +1915,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2186,7 +2186,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2457,7 +2457,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2728,7 +2728,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2999,7 +2999,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3270,7 +3270,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3541,7 +3541,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3812,7 +3812,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4083,7 +4083,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4354,7 +4354,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4625,7 +4625,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4896,7 +4896,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5167,7 +5167,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5438,7 +5438,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5709,7 +5709,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Alik_Bjlk_BBS_BH_Bias_FDMN_SPA_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Alik_Bjlk_BBS_BH_Bias_FDMN_SPA_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Alik_Bjlk_BBS_BH_Bias_FDMN_SPA_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Alik_Bjlk_BBS_BH_Bias_FDMN_SPA_AS.yaml index 8e1cfdc0..cb7b223c 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Alik_Bjlk_BBS_BH_Bias_FDMN_SPA_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Alik_Bjlk_BBS_BH_Bias_FDMN_SPA_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false - - 1LDSBuffer: 0 @@ -288,7 +288,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -559,7 +559,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -830,7 +830,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1090,7 +1090,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1347,7 +1347,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1615,7 +1615,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1875,7 +1875,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2143,7 +2143,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2414,7 +2414,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2685,7 +2685,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2945,7 +2945,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3213,7 +3213,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3484,7 +3484,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3744,7 +3744,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4001,7 +4001,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4258,7 +4258,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4515,7 +4515,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4772,7 +4772,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -5040,7 +5040,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5310,7 +5310,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5578,7 +5578,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5848,7 +5848,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6118,7 +6118,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6388,7 +6388,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6658,7 +6658,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6928,7 +6928,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7198,7 +7198,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7468,7 +7468,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7738,7 +7738,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8008,7 +8008,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8278,7 +8278,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8548,7 +8548,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8818,7 +8818,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9088,7 +9088,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9358,7 +9358,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9628,7 +9628,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9898,7 +9898,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Alik_Bjlk_BBS_BH_Bias_FDMN_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Alik_Bjlk_BBS_BH_Bias_FDMN_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Alik_Bjlk_BBS_BH_Bias_FDMN_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Alik_Bjlk_BBS_BH_Bias_FDMN_SPB_AS.yaml index 31b9b93a..7c828895 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Alik_Bjlk_BBS_BH_Bias_FDMN_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Alik_Bjlk_BBS_BH_Bias_FDMN_SPB_AS.yaml @@ -74,7 +74,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -289,7 +289,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -560,7 +560,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -831,7 +831,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1102,7 +1102,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1373,7 +1373,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1644,7 +1644,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1915,7 +1915,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2186,7 +2186,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2457,7 +2457,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2728,7 +2728,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2999,7 +2999,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3270,7 +3270,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Alik_Bjlk_BBS_BH_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Alik_Bjlk_BBS_BH_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Alik_Bjlk_BBS_BH_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Alik_Bjlk_BBS_BH_SPB_AS.yaml index d027eb85..1c6c10f2 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Alik_Bjlk_BBS_BH_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Alik_Bjlk_BBS_BH_SPB_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -286,7 +286,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -555,7 +555,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -824,7 +824,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1093,7 +1093,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1362,7 +1362,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1631,7 +1631,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1900,7 +1900,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2169,7 +2169,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2438,7 +2438,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2707,7 +2707,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2976,7 +2976,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Alik_Bjlk_HHS_BH_Bias_FDMN_SPA_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Alik_Bjlk_HHS_BH_Bias_FDMN_SPA_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Alik_Bjlk_HHS_BH_Bias_FDMN_SPA_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Alik_Bjlk_HHS_BH_Bias_FDMN_SPA_AS.yaml index 800a9feb..f7eff84d 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Alik_Bjlk_HHS_BH_Bias_FDMN_SPA_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Alik_Bjlk_HHS_BH_Bias_FDMN_SPA_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false - - 1LDSBuffer: 0 @@ -288,7 +288,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -559,7 +559,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -819,7 +819,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1076,7 +1076,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1333,7 +1333,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1590,7 +1590,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1847,7 +1847,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2115,7 +2115,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2386,7 +2386,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2657,7 +2657,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2928,7 +2928,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3188,7 +3188,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3445,7 +3445,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3702,7 +3702,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3970,7 +3970,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4230,7 +4230,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4487,7 +4487,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4755,7 +4755,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -5026,7 +5026,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5296,7 +5296,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5564,7 +5564,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5834,7 +5834,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6104,7 +6104,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6374,7 +6374,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6644,7 +6644,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6914,7 +6914,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7184,7 +7184,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7454,7 +7454,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7724,7 +7724,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7994,7 +7994,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8264,7 +8264,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8534,7 +8534,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8804,7 +8804,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9074,7 +9074,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9344,7 +9344,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9614,7 +9614,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9884,7 +9884,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Alik_Bjlk_HHS_BH_Bias_FDMN_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Alik_Bjlk_HHS_BH_Bias_FDMN_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Alik_Bjlk_HHS_BH_Bias_FDMN_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Alik_Bjlk_HHS_BH_Bias_FDMN_SPB_AS.yaml index b595faf8..e1c5a446 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Alik_Bjlk_HHS_BH_Bias_FDMN_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Alik_Bjlk_HHS_BH_Bias_FDMN_SPB_AS.yaml @@ -74,7 +74,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -289,7 +289,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -560,7 +560,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -831,7 +831,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1102,7 +1102,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1373,7 +1373,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1644,7 +1644,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1915,7 +1915,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2186,7 +2186,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2457,7 +2457,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2728,7 +2728,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2999,7 +2999,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3270,7 +3270,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3541,7 +3541,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3812,7 +3812,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4083,7 +4083,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Alik_Bjlk_HHS_BH_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Alik_Bjlk_HHS_BH_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Alik_Bjlk_HHS_BH_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Alik_Bjlk_HHS_BH_SPB_AS.yaml index c1acf142..e81cdecc 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Alik_Bjlk_HHS_BH_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Alik_Bjlk_HHS_BH_SPB_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -286,7 +286,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -555,7 +555,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -824,7 +824,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1093,7 +1093,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1362,7 +1362,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1631,7 +1631,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1900,7 +1900,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2169,7 +2169,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2438,7 +2438,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2707,7 +2707,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2976,7 +2976,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3245,7 +3245,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3514,7 +3514,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3783,7 +3783,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4052,7 +4052,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4321,7 +4321,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Alik_Bjlk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Alik_Bjlk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Alik_Bjlk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Alik_Bjlk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml index 1d4d748d..35b27736 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Alik_Bjlk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Alik_Bjlk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml @@ -1,6 +1,6 @@ - {MinimumRequiredVersion: 4.33.0} - aquavanjaram -- gfx942 +- gfx940 - [Device 0049, Device 0050] - Activation: true ActivationComputeDataType: 0 @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -287,7 +287,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -546,7 +546,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -802,7 +802,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1058,7 +1058,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1325,7 +1325,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1584,7 +1584,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1851,7 +1851,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2110,7 +2110,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2366,7 +2366,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2633,7 +2633,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Alik_Bjlk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Alik_Bjlk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Alik_Bjlk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Alik_Bjlk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml index 50b55d7c..8fcc4163 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Alik_Bjlk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Alik_Bjlk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml @@ -1,6 +1,6 @@ - {MinimumRequiredVersion: 4.33.0} - aquavanjaram -- gfx942 +- gfx940 - [Device 0049, Device 0050] - Activation: true ActivationComputeDataType: 0 @@ -74,7 +74,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -289,7 +289,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -560,7 +560,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -831,7 +831,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1102,7 +1102,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1373,7 +1373,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1644,7 +1644,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1915,7 +1915,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2186,7 +2186,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2457,7 +2457,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Alik_Bjlk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Alik_Bjlk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Alik_Bjlk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Alik_Bjlk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml index f29bb5bd..90224cb3 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Alik_Bjlk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Alik_Bjlk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -287,7 +287,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -546,7 +546,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -802,7 +802,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1058,7 +1058,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1325,7 +1325,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1584,7 +1584,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1851,7 +1851,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2110,7 +2110,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2366,7 +2366,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2633,7 +2633,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Alik_Bjlk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Alik_Bjlk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Alik_Bjlk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Alik_Bjlk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml index 1382176e..7f69fc11 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Alik_Bjlk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Alik_Bjlk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml @@ -74,7 +74,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -289,7 +289,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -560,7 +560,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -831,7 +831,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1102,7 +1102,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1373,7 +1373,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1644,7 +1644,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1915,7 +1915,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2186,7 +2186,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2457,7 +2457,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Alik_Bjlk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Alik_Bjlk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml similarity index 96% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Alik_Bjlk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Alik_Bjlk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml index e62bb137..287d10e5 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Alik_Bjlk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Alik_Bjlk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false - - 1LDSBuffer: 0 @@ -277,7 +277,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -545,7 +545,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -816,7 +816,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1076,7 +1076,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1333,7 +1333,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1590,7 +1590,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1847,7 +1847,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2115,7 +2115,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2375,7 +2375,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2643,7 +2643,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2914,7 +2914,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3185,7 +3185,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3456,7 +3456,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3716,7 +3716,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3973,7 +3973,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4241,7 +4241,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4501,7 +4501,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4758,7 +4758,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -5015,7 +5015,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -5272,7 +5272,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -5535,7 +5535,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5800,7 +5800,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6065,7 +6065,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6330,7 +6330,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6595,7 +6595,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6860,7 +6860,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7125,7 +7125,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7390,7 +7390,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7655,7 +7655,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7920,7 +7920,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8185,7 +8185,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8450,7 +8450,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8715,7 +8715,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8773,271 +8773,6 @@ _WorkspaceSizePerElemBias: 0 _WorkspaceSizePerElemC: 0 _staggerStrideShift: 1 - - 1LDSBuffer: 0 - ActivationAlt: false - ActivationFuncCall: true - ActivationFused: true - AssertFree0ElementMultiple: 1 - AssertFree1ElementMultiple: 1 - AssertSummationElementMultiple: 8 - AssignedDerivedParameters: true - AssignedProblemIndependentDerivedParameters: true - BufferLoad: true - BufferStore: true - CUCount: null - ClusterLocalRead: 0 - CodeObjectVersion: default - CustomKernelName: '' - DepthU: 64 - DirectToLds: false - DirectToLdsA: false - DirectToLdsB: false - DirectToLdsMetadata: false - DirectToVgprSparseMetadata: 0 - EdgeType: ShiftPtr - EnableF32XdlMathOp: false - EnableMatrixInstruction: true - ExpandPointerSwap: 1 - GlobalReadPerMfma: 1 - GlobalReadVectorWidthA: 16 - GlobalReadVectorWidthB: 16 - GlobalReadVectorWidthMetadata: 8 - GlobalSplitU: 1 - GlobalSplitUAlgorithm: MultipleBuffer - GlobalWriteVectorWidth: 1 - GroupLoadStore: false - GuaranteeNoPartialA: true - GuaranteeNoPartialB: false - ISA: [9, 4, 0] - InnerUnroll: 1 - InterleaveAlpha: 0 - KernelLanguage: Assembly - LSCA: 32 - LSCB: 256 - LSCMetadata: 8 - LSPA: 128 - LSPB: 16 - LSPMetadata: 256 - LVCA: 2 - LVCB: 16 - LVCMetadata: 1 - LVPA: 8 - LVPB: 1 - LVPMetadata: 32 - LdsBlockSizePerPadA: 128 - LdsBlockSizePerPadB: 0 - LdsBlockSizePerPadMetadata: 128 - LdsInitCVgprs: false - LdsNumElements: 60672 - LdsNumElementsAlignedA: 9216 - LdsNumElementsAlignedB: 16384 - LdsNumElementsAlignedMetadata: 2304 - LdsOffsetA: 0 - LdsOffsetA_Blk: 32768 - LdsOffsetB: 11520 - LdsOffsetB_Blk: 44288 - LdsOffsetBias: 0 - LdsOffsetMetadata: 9216 - LdsOffsetMetadata_Blk: 41984 - LdsPadA: 16 - LdsPadB: 0 - LdsPadMetadata: 4 - LocalReadVectorWidth: 16 - LocalSplitU: 1 - LocalWritePerMfma: -1 - LocalWriteUseSgprA: false - LocalWriteUseSgprB: false - LocalWriteUseSgprMetadat: false - LoopIters: 2 - LoopUnroll: 64 - MFMA_BF16_1K: false - MIArchVgpr: false - MIBlock: [32, 32, 32, 1, 1, 1] - MIInputPerThread: 16 - MIInputPerThreadA: 8 - MIInputPerThreadB: 16 - MIInputPerThreadMetadata: 2 - MIOutputVectorWidth: 4 - MIRegPerOut: 1 - MIWaveGroup: [2, 2] - MIWaveTile: [4, 4] - MIWaveTileA: 4 - MIWaveTileB: 4 - MIWaveTileMetadata: 4 - MacroTile0: 256 - MacroTile1: 256 - MacroTileA: 256 - MacroTileB: 256 - MacroTileMetadata: 256 - MagicDivAlg: 2 - MatrixInstB: 1 - MatrixInstBM: 1 - MatrixInstBN: 1 - MatrixInstK: 32 - MatrixInstM: 32 - MatrixInstN: 32 - MatrixInstruction: [32, 32, 32, 1] - MaxOccupancy: 40 - MaxVgprNumber: 256 - MinVgprNumber: 0 - NoLdsWriteCode: false - NoReject: false - NoTailLoop: false - NonTemporal: -1 - NonTemporalA: 0 - NonTemporalB: 0 - NonTemporalC: 0 - NonTemporalD: 0 - NonTemporalE: 0 - NonTemporalMetadata: 0 - NumElementsPerBatchStore: 0 - NumElementsPerThread: 256 - NumGlobalWriteVectorsPerThread: 256 - NumLoadsA: 2 - NumLoadsB: 4 - NumLoadsCoalescedA: 1 - NumLoadsCoalescedB: 1 - NumLoadsCoalescedMetadata: 1 - NumLoadsMetadata: 1 - NumLoadsPerpendicularA: 2 - NumLoadsPerpendicularB: 4 - NumLoadsPerpendicularMetadata: 1 - NumThreads: 256 - OptNoLoadLoop: 1 - PackedC0IdxChars: [I] - PackedC0IndicesX: [0] - PackedC1IdxChars: [J] - PackedC1IndicesX: [1] - PrefetchGlobalRead: 2 - PrefetchLocalRead: 1 - ProblemType: - Activation: true - ActivationComputeDataType: 0 - ActivationNoGuard: false - ActivationType: all - AllowNoFreeDims: false - AssignedDerivedParameters: true - Batched: true - BetaOnlyUseBias: false - BiasDataTypeList: [0] - BiasSrc: D - ComplexConjugateA: false - ComplexConjugateB: false - ComputeDataType: 0 - DataType: 8 - DestDataType: 8 - F32XdlMathOp: 0 - Fp16AltImpl: false - Gradient: false - GroupedGemm: false - HighPrecisionAccumulate: true - Index0: 0 - Index01A: 0 - Index01B: 1 - Index01Metadata: 0 - Index1: 1 - IndexAssignmentsA: [3, 0, 2] - IndexAssignmentsB: [1, 3, 2] - IndexAssignmentsLD: [4, 5, 6, 7] - IndexAssignmentsMetadata: [3, 0, 2] - IndexUnroll: 3 - IndexUnrollA: 0 - IndexUnrollB: 1 - IndexUnrollM: 0 - IndicesBatch: [2] - IndicesFree: [0, 1] - IndicesSummation: [3] - MirrorDimsA: &id023 [] - MirrorDimsB: [] - MirrorDimsMetadata: *id023 - NumIndicesBatch: 1 - NumIndicesC: 3 - NumIndicesFree: 2 - NumIndicesLD: 4 - NumIndicesSummation: 1 - OperationType: GEMM - SetConstStrideA: [] - SetConstStrideB: [] - SetConstStrideBias: [] - SilentHighPrecisionAccumulate: false - Sparse: 1 - StridedBatched: true - SupportUserArgs: false - TLUA: false - TLUB: true - TLUMetadata: false - Tensor0: 0 - Tensor1: 1 - TileA: 0 - TileAwareSelection: false - TileB: 1 - TotalIndices: 4 - TransposeA: true - TransposeB: true - UseBeta: true - UseBias: 3 - UseE: false - UseInitialStridesAB: false - UseInitialStridesCD: false - UseScaleAB: "" - UseScaleAlphaVec: 0 - UseScaleDVec: false - ScheduleGlobalRead: 1 - ScheduleIterAlg: 3 - ScheduleLocalWrite: 1 - SolutionIndex: 33 - SolutionNameMin: Cijk_Alik_Bjlk_I8I8S_BH_Bias_FDMN_SPA_AS_MT256x256x64_MI32x32x32x1_SN_1LDSB0_AFC1_AF0EM1_GRVWB16_GSU1_LBSPPB0_LPB0_MIWT4_4_NLCB1_PLR1_SUS128_WG64_4_1 - SourceSwap: 0 - StaggerU: 4 - StaggerUMapping: 0 - StaggerUStride: 128 - StorePriorityOpt: false - StoreRemapVectorWidth: 0 - StoreSyncOpt: 0 - StoreVectorWidth: 4 - SubGroup0: 4 - SubGroup1: 64 - SubGroupA: 4 - SubGroupB: 64 - SubGroupMetadata: 4 - SuppressNoLoadLoop: false - ThreadTile: [1, 1] - ThreadTile0: 64 - ThreadTile1: 4 - ThreadTileA: 64 - ThreadTileB: 4 - ThreadTileMetadata: 64 - TransposeLDS: 1 - TransposeLDSMetadata: true - UnrollMajorLDSA: true - UnrollMajorLDSB: false - UnrollMajorLDSMetadata: true - Use64bShadowLimit: 1 - UseInstOffsetForGRO: 0 - UseSgprForGRO: -1 - Valid: true - VectorStore: -1 - VectorWidthA: 1 - VectorWidthB: 1 - VectorWidthMetadata: 1 - WaveSeparateGlobalReadA: 0 - WaveSeparateGlobalReadB: 0 - WaveSeparateGlobalReadMetadata: 0 - WavefrontSize: 64 - WorkGroup: [64, 4, 1] - WorkGroupMapping: 18 - WorkGroupReduction: false - WorkspaceCheck: [0, 0] - _DepthU: 64 - _DepthUA: 32 - _DepthUB: 64 - _DepthUMetadata: 8 - _GlobalAccumulation: null - _UseSgprForGRO: false - _VectorStore: 1 - _WorkspaceSizePerElemBias: 0 - _WorkspaceSizePerElemC: 0 - _staggerStrideShift: 1 - [2, 3, 0, 1] - - - [16, 16, 1, 16] - [1, 0.0] @@ -9160,7 +8895,7 @@ - - [10240, 10240, 1, 19200] - [32, 28.647] - - [10240, 10240, 1, 20480] - - [33, 26.172] + - [32, 26.172] - null - null - DeviceEfficiency diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Alik_Bjlk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Alik_Bjlk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Alik_Bjlk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Alik_Bjlk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml index e65ce908..12fee66c 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Alik_Bjlk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Alik_Bjlk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml @@ -74,7 +74,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -289,7 +289,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -560,7 +560,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -831,7 +831,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1102,7 +1102,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1373,7 +1373,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1644,7 +1644,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1915,7 +1915,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2186,7 +2186,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2457,7 +2457,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2728,7 +2728,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2999,7 +2999,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3270,7 +3270,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3541,7 +3541,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3812,7 +3812,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4083,7 +4083,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4354,7 +4354,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4625,7 +4625,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4896,7 +4896,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5167,7 +5167,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5438,7 +5438,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5709,7 +5709,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Alik_Bljk_BBS_BH_Bias_FDMN_SPA_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Alik_Bljk_BBS_BH_Bias_FDMN_SPA_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Alik_Bljk_BBS_BH_Bias_FDMN_SPA_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Alik_Bljk_BBS_BH_Bias_FDMN_SPA_AS.yaml index 83170f71..d4b3f473 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Alik_Bljk_BBS_BH_Bias_FDMN_SPA_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Alik_Bljk_BBS_BH_Bias_FDMN_SPA_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false - - 1LDSBuffer: 0 @@ -288,7 +288,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -548,7 +548,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -805,7 +805,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1062,7 +1062,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1330,7 +1330,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1590,7 +1590,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1858,7 +1858,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2129,7 +2129,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2400,7 +2400,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2671,7 +2671,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2942,7 +2942,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3202,7 +3202,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3470,7 +3470,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3741,7 +3741,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4001,7 +4001,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4258,7 +4258,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4515,7 +4515,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4772,7 +4772,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -5040,7 +5040,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5310,7 +5310,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5580,7 +5580,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5850,7 +5850,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6120,7 +6120,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6390,7 +6390,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6660,7 +6660,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6930,7 +6930,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7200,7 +7200,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7470,7 +7470,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7740,7 +7740,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8010,7 +8010,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8280,7 +8280,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8550,7 +8550,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8820,7 +8820,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9090,7 +9090,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9360,7 +9360,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9630,7 +9630,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9900,7 +9900,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -10170,7 +10170,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -10440,7 +10440,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -10710,7 +10710,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -10978,7 +10978,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -11246,7 +11246,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -11514,7 +11514,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Alik_Bljk_BBS_BH_Bias_FDMN_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Alik_Bljk_BBS_BH_Bias_FDMN_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Alik_Bljk_BBS_BH_Bias_FDMN_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Alik_Bljk_BBS_BH_Bias_FDMN_SPB_AS.yaml index d90ba668..13e3b757 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Alik_Bljk_BBS_BH_Bias_FDMN_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Alik_Bljk_BBS_BH_Bias_FDMN_SPB_AS.yaml @@ -74,7 +74,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -289,7 +289,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -560,7 +560,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -831,7 +831,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1102,7 +1102,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1373,7 +1373,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1644,7 +1644,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1915,7 +1915,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2186,7 +2186,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2457,7 +2457,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2728,7 +2728,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2999,7 +2999,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3270,7 +3270,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3541,7 +3541,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3812,7 +3812,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4083,7 +4083,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4354,7 +4354,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4625,7 +4625,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4896,7 +4896,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5167,7 +5167,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Alik_Bljk_BBS_BH_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Alik_Bljk_BBS_BH_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Alik_Bljk_BBS_BH_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Alik_Bljk_BBS_BH_SPB_AS.yaml index a4e85add..cbc68e26 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Alik_Bljk_BBS_BH_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Alik_Bljk_BBS_BH_SPB_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -286,7 +286,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -555,7 +555,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -824,7 +824,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1093,7 +1093,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1362,7 +1362,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1631,7 +1631,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1900,7 +1900,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2169,7 +2169,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2438,7 +2438,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2707,7 +2707,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2976,7 +2976,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3245,7 +3245,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3514,7 +3514,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3783,7 +3783,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4052,7 +4052,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4321,7 +4321,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4590,7 +4590,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4859,7 +4859,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5128,7 +5128,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5397,7 +5397,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5666,7 +5666,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Alik_Bljk_HHS_BH_Bias_FDMN_SPA_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Alik_Bljk_HHS_BH_Bias_FDMN_SPA_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Alik_Bljk_HHS_BH_Bias_FDMN_SPA_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Alik_Bljk_HHS_BH_Bias_FDMN_SPA_AS.yaml index 546153a1..bdf4e9ec 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Alik_Bljk_HHS_BH_Bias_FDMN_SPA_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Alik_Bljk_HHS_BH_Bias_FDMN_SPA_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false - - 1LDSBuffer: 0 @@ -288,7 +288,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -548,7 +548,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -805,7 +805,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1062,7 +1062,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1319,7 +1319,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1587,7 +1587,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1858,7 +1858,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2129,7 +2129,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2400,7 +2400,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2660,7 +2660,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2928,7 +2928,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3199,7 +3199,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3459,7 +3459,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3716,7 +3716,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3973,7 +3973,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4230,7 +4230,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4487,7 +4487,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4744,7 +4744,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -5012,7 +5012,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5282,7 +5282,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5552,7 +5552,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5822,7 +5822,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6092,7 +6092,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6362,7 +6362,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6632,7 +6632,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6902,7 +6902,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7172,7 +7172,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7442,7 +7442,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7712,7 +7712,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7982,7 +7982,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8252,7 +8252,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8522,7 +8522,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8792,7 +8792,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9062,7 +9062,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9332,7 +9332,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9602,7 +9602,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9872,7 +9872,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -10142,7 +10142,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -10412,7 +10412,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -10682,7 +10682,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -10950,7 +10950,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -11218,7 +11218,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -11486,7 +11486,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Alik_Bljk_HHS_BH_Bias_FDMN_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Alik_Bljk_HHS_BH_Bias_FDMN_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Alik_Bljk_HHS_BH_Bias_FDMN_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Alik_Bljk_HHS_BH_Bias_FDMN_SPB_AS.yaml index c64870a8..1c2078ed 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Alik_Bljk_HHS_BH_Bias_FDMN_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Alik_Bljk_HHS_BH_Bias_FDMN_SPB_AS.yaml @@ -74,7 +74,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -289,7 +289,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -560,7 +560,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -831,7 +831,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1102,7 +1102,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1373,7 +1373,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1644,7 +1644,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1915,7 +1915,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2186,7 +2186,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2457,7 +2457,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2728,7 +2728,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2999,7 +2999,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3270,7 +3270,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3541,7 +3541,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3812,7 +3812,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4083,7 +4083,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4354,7 +4354,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4625,7 +4625,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4896,7 +4896,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5167,7 +5167,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Alik_Bljk_HHS_BH_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Alik_Bljk_HHS_BH_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Alik_Bljk_HHS_BH_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Alik_Bljk_HHS_BH_SPB_AS.yaml index 5c7b29cb..04fbab2d 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Alik_Bljk_HHS_BH_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Alik_Bljk_HHS_BH_SPB_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -286,7 +286,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -555,7 +555,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -824,7 +824,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1093,7 +1093,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1362,7 +1362,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1631,7 +1631,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1900,7 +1900,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2169,7 +2169,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2438,7 +2438,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2707,7 +2707,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2976,7 +2976,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Alik_Bljk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Alik_Bljk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Alik_Bljk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Alik_Bljk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml index 6df08e0c..7dbf3aa1 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Alik_Bljk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Alik_Bljk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml @@ -1,6 +1,6 @@ - {MinimumRequiredVersion: 4.33.0} - aquavanjaram -- gfx942 +- gfx940 - [Device 0049, Device 0050] - Activation: true ActivationComputeDataType: 0 @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -287,7 +287,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -557,7 +557,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -816,7 +816,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1072,7 +1072,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1339,7 +1339,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1598,7 +1598,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1854,7 +1854,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2110,7 +2110,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2377,7 +2377,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2636,7 +2636,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2892,7 +2892,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Alik_Bljk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Alik_Bljk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Alik_Bljk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Alik_Bljk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml index e436d08e..0c5389e1 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Alik_Bljk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Alik_Bljk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml @@ -1,6 +1,6 @@ - {MinimumRequiredVersion: 4.33.0} - aquavanjaram -- gfx942 +- gfx940 - [Device 0049, Device 0050] - Activation: true ActivationComputeDataType: 0 @@ -74,7 +74,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -289,7 +289,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -560,7 +560,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -831,7 +831,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1102,7 +1102,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1373,7 +1373,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1644,7 +1644,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1915,7 +1915,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2186,7 +2186,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2457,7 +2457,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2728,7 +2728,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Alik_Bljk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Alik_Bljk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Alik_Bljk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Alik_Bljk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml index bc5d15de..764ca92f 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Alik_Bljk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Alik_Bljk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -287,7 +287,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -557,7 +557,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -816,7 +816,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1072,7 +1072,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1339,7 +1339,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1598,7 +1598,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1854,7 +1854,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2110,7 +2110,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2377,7 +2377,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2636,7 +2636,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2892,7 +2892,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Alik_Bljk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Alik_Bljk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Alik_Bljk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Alik_Bljk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml index da5c7c12..44f0b32c 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Alik_Bljk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Alik_Bljk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml @@ -74,7 +74,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -289,7 +289,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -560,7 +560,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -831,7 +831,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1102,7 +1102,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1373,7 +1373,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1644,7 +1644,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1915,7 +1915,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2186,7 +2186,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2457,7 +2457,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2728,7 +2728,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Alik_Bljk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Alik_Bljk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Alik_Bljk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Alik_Bljk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml index 2436feb0..5c125b47 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Alik_Bljk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Alik_Bljk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false - - 1LDSBuffer: 0 @@ -288,7 +288,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -548,7 +548,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -805,7 +805,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1073,7 +1073,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1333,7 +1333,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1590,7 +1590,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1847,7 +1847,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2115,7 +2115,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2375,7 +2375,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2632,7 +2632,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2889,7 +2889,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3146,7 +3146,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3403,7 +3403,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3660,7 +3660,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3928,7 +3928,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4188,7 +4188,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4451,7 +4451,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4716,7 +4716,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4981,7 +4981,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5246,7 +5246,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5511,7 +5511,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5776,7 +5776,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6041,7 +6041,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6306,7 +6306,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6571,7 +6571,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6836,7 +6836,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7101,7 +7101,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7366,7 +7366,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7631,7 +7631,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7896,7 +7896,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8161,7 +8161,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8426,7 +8426,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Alik_Bljk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Alik_Bljk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Alik_Bljk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Alik_Bljk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml index fb28288f..b311239d 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx940/aquavanjaram_Cijk_Alik_Bljk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx940/Equality/aquavanjaram_Cijk_Alik_Bljk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml @@ -74,7 +74,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -289,7 +289,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -560,7 +560,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -831,7 +831,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1102,7 +1102,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1373,7 +1373,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1644,7 +1644,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1915,7 +1915,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2186,7 +2186,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2457,7 +2457,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2728,7 +2728,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2999,7 +2999,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3270,7 +3270,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3541,7 +3541,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3812,7 +3812,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4083,7 +4083,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4354,7 +4354,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4625,7 +4625,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4896,7 +4896,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5167,7 +5167,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5438,7 +5438,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5709,7 +5709,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Ailk_Bjlk_BBS_BH_Bias_FDMN_SPA_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Ailk_Bjlk_BBS_BH_Bias_FDMN_SPA_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Ailk_Bjlk_BBS_BH_Bias_FDMN_SPA_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Ailk_Bjlk_BBS_BH_Bias_FDMN_SPA_AS.yaml index bbcdca9c..7350f24d 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Ailk_Bjlk_BBS_BH_Bias_FDMN_SPA_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Ailk_Bjlk_BBS_BH_Bias_FDMN_SPA_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false - - 1LDSBuffer: 0 @@ -288,7 +288,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -559,7 +559,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -819,7 +819,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1076,7 +1076,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1344,7 +1344,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1604,7 +1604,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1861,7 +1861,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2129,7 +2129,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2389,7 +2389,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2646,7 +2646,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2903,7 +2903,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3171,7 +3171,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3442,7 +3442,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3702,7 +3702,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3959,7 +3959,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4227,7 +4227,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4487,7 +4487,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4744,7 +4744,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -5010,7 +5010,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5279,7 +5279,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5547,7 +5547,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5815,7 +5815,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6083,7 +6083,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6351,7 +6351,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6619,7 +6619,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6887,7 +6887,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7155,7 +7155,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7423,7 +7423,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7691,7 +7691,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7959,7 +7959,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8227,7 +8227,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8495,7 +8495,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8763,7 +8763,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9031,7 +9031,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9299,7 +9299,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9567,7 +9567,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9835,7 +9835,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Ailk_Bjlk_BBS_BH_Bias_FDMN_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Ailk_Bjlk_BBS_BH_Bias_FDMN_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Ailk_Bjlk_BBS_BH_Bias_FDMN_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Ailk_Bjlk_BBS_BH_Bias_FDMN_SPB_AS.yaml index 0472a421..671fed55 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Ailk_Bjlk_BBS_BH_Bias_FDMN_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Ailk_Bjlk_BBS_BH_Bias_FDMN_SPB_AS.yaml @@ -74,7 +74,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -289,7 +289,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -560,7 +560,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -831,7 +831,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1102,7 +1102,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1373,7 +1373,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1644,7 +1644,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1915,7 +1915,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2186,7 +2186,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2457,7 +2457,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2728,7 +2728,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2999,7 +2999,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3270,7 +3270,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3541,7 +3541,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3812,7 +3812,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4083,7 +4083,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4354,7 +4354,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4625,7 +4625,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4896,7 +4896,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5167,7 +5167,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5438,7 +5438,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Ailk_Bjlk_BBS_BH_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Ailk_Bjlk_BBS_BH_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Ailk_Bjlk_BBS_BH_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Ailk_Bjlk_BBS_BH_SPB_AS.yaml index 04fe4e49..6c9a1a93 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Ailk_Bjlk_BBS_BH_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Ailk_Bjlk_BBS_BH_SPB_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -286,7 +286,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -555,7 +555,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -824,7 +824,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1093,7 +1093,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1362,7 +1362,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1631,7 +1631,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1900,7 +1900,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2169,7 +2169,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2438,7 +2438,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2707,7 +2707,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2976,7 +2976,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3245,7 +3245,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3514,7 +3514,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3783,7 +3783,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4052,7 +4052,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4321,7 +4321,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4590,7 +4590,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4859,7 +4859,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Ailk_Bjlk_HHS_BH_Bias_FDMN_SPA_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Ailk_Bjlk_HHS_BH_Bias_FDMN_SPA_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Ailk_Bjlk_HHS_BH_Bias_FDMN_SPA_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Ailk_Bjlk_HHS_BH_Bias_FDMN_SPA_AS.yaml index bd280925..3724a5ba 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Ailk_Bjlk_HHS_BH_Bias_FDMN_SPA_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Ailk_Bjlk_HHS_BH_Bias_FDMN_SPA_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false - - 1LDSBuffer: 0 @@ -277,7 +277,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -534,7 +534,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -791,7 +791,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1059,7 +1059,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1330,7 +1330,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1590,7 +1590,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1858,7 +1858,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2129,7 +2129,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2400,7 +2400,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2671,7 +2671,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2931,7 +2931,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3188,7 +3188,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3456,7 +3456,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3727,7 +3727,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3987,7 +3987,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4244,7 +4244,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4501,7 +4501,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4769,7 +4769,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -5040,7 +5040,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -5309,7 +5309,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5578,7 +5578,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5846,7 +5846,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6114,7 +6114,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6382,7 +6382,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6650,7 +6650,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6918,7 +6918,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7186,7 +7186,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7454,7 +7454,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7722,7 +7722,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7990,7 +7990,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8258,7 +8258,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8526,7 +8526,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8794,7 +8794,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9062,7 +9062,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9330,7 +9330,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9598,7 +9598,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9866,7 +9866,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -10134,7 +10134,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Ailk_Bjlk_HHS_BH_Bias_FDMN_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Ailk_Bjlk_HHS_BH_Bias_FDMN_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Ailk_Bjlk_HHS_BH_Bias_FDMN_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Ailk_Bjlk_HHS_BH_Bias_FDMN_SPB_AS.yaml index da09abca..91ad93fc 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Ailk_Bjlk_HHS_BH_Bias_FDMN_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Ailk_Bjlk_HHS_BH_Bias_FDMN_SPB_AS.yaml @@ -74,7 +74,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -289,7 +289,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -560,7 +560,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -831,7 +831,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1102,7 +1102,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1373,7 +1373,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1644,7 +1644,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1915,7 +1915,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2186,7 +2186,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2457,7 +2457,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2728,7 +2728,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2999,7 +2999,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3270,7 +3270,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3541,7 +3541,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3812,7 +3812,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4083,7 +4083,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4354,7 +4354,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4625,7 +4625,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4896,7 +4896,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5167,7 +5167,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5438,7 +5438,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5709,7 +5709,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Ailk_Bjlk_HHS_BH_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Ailk_Bjlk_HHS_BH_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Ailk_Bjlk_HHS_BH_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Ailk_Bjlk_HHS_BH_SPB_AS.yaml index 5919bcf8..35808211 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Ailk_Bjlk_HHS_BH_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Ailk_Bjlk_HHS_BH_SPB_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -286,7 +286,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -555,7 +555,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -824,7 +824,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1093,7 +1093,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1362,7 +1362,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1631,7 +1631,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1900,7 +1900,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2169,7 +2169,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2438,7 +2438,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2707,7 +2707,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2976,7 +2976,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Ailk_Bjlk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Ailk_Bjlk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Ailk_Bjlk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Ailk_Bjlk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml index 5a3c2fe4..599dff5f 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Ailk_Bjlk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Ailk_Bjlk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -287,7 +287,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -546,7 +546,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -813,7 +813,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1072,7 +1072,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1339,7 +1339,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1609,7 +1609,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1879,7 +1879,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2149,7 +2149,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2419,7 +2419,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2678,7 +2678,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Ailk_Bjlk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Ailk_Bjlk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Ailk_Bjlk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Ailk_Bjlk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml index 193b5ef8..cf23bfe1 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Ailk_Bjlk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Ailk_Bjlk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml @@ -74,7 +74,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -289,7 +289,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -560,7 +560,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -831,7 +831,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1102,7 +1102,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1373,7 +1373,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1644,7 +1644,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1915,7 +1915,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2186,7 +2186,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2457,7 +2457,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Ailk_Bjlk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Ailk_Bjlk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Ailk_Bjlk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Ailk_Bjlk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml index cd873438..5fcf3eaa 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Ailk_Bjlk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Ailk_Bjlk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -287,7 +287,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -546,7 +546,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -813,7 +813,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1072,7 +1072,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1339,7 +1339,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1609,7 +1609,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1879,7 +1879,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2149,7 +2149,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2419,7 +2419,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2678,7 +2678,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Ailk_Bjlk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Ailk_Bjlk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Ailk_Bjlk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Ailk_Bjlk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml index 2ca8d6cf..0efb10fd 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Ailk_Bjlk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Ailk_Bjlk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml @@ -74,7 +74,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -289,7 +289,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -560,7 +560,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -831,7 +831,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1102,7 +1102,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1373,7 +1373,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1644,7 +1644,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1915,7 +1915,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2186,7 +2186,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2457,7 +2457,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Ailk_Bjlk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Ailk_Bjlk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Ailk_Bjlk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Ailk_Bjlk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml index dc8cefb8..04c49c20 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Ailk_Bjlk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Ailk_Bjlk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false - - 1LDSBuffer: 0 @@ -288,7 +288,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -548,7 +548,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -805,7 +805,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1073,7 +1073,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1344,7 +1344,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1615,7 +1615,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1886,7 +1886,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2146,7 +2146,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2403,7 +2403,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2660,7 +2660,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2928,7 +2928,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3199,7 +3199,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3459,7 +3459,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3716,7 +3716,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3984,7 +3984,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4244,7 +4244,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4507,7 +4507,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4772,7 +4772,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5037,7 +5037,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5302,7 +5302,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5567,7 +5567,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5832,7 +5832,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6097,7 +6097,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6362,7 +6362,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6627,7 +6627,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6892,7 +6892,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7157,7 +7157,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7422,7 +7422,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7687,7 +7687,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7952,7 +7952,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8217,7 +8217,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Ailk_Bjlk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Ailk_Bjlk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Ailk_Bjlk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Ailk_Bjlk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml index 429013ba..666088c9 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Ailk_Bjlk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Ailk_Bjlk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml @@ -74,7 +74,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -289,7 +289,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -560,7 +560,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -831,7 +831,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1102,7 +1102,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1373,7 +1373,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1644,7 +1644,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1915,7 +1915,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2186,7 +2186,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2457,7 +2457,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2728,7 +2728,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2999,7 +2999,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3270,7 +3270,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3541,7 +3541,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3812,7 +3812,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4083,7 +4083,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Ailk_Bljk_BBS_BH_Bias_FDMN_SPA_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Ailk_Bljk_BBS_BH_Bias_FDMN_SPA_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Ailk_Bljk_BBS_BH_Bias_FDMN_SPA_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Ailk_Bljk_BBS_BH_Bias_FDMN_SPA_AS.yaml index 23092d2b..acf50aa1 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Ailk_Bljk_BBS_BH_Bias_FDMN_SPA_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Ailk_Bljk_BBS_BH_Bias_FDMN_SPA_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false - - 1LDSBuffer: 0 @@ -277,7 +277,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -545,7 +545,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -805,7 +805,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1062,7 +1062,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1330,7 +1330,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1590,7 +1590,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1858,7 +1858,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2118,7 +2118,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2386,7 +2386,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2646,7 +2646,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2903,7 +2903,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3160,7 +3160,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3417,7 +3417,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3674,7 +3674,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3931,7 +3931,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4188,7 +4188,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4445,7 +4445,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4711,7 +4711,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4979,7 +4979,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5247,7 +5247,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5515,7 +5515,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5783,7 +5783,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6051,7 +6051,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6319,7 +6319,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6587,7 +6587,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6855,7 +6855,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7123,7 +7123,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7391,7 +7391,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7659,7 +7659,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7927,7 +7927,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8195,7 +8195,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8463,7 +8463,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8731,7 +8731,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8999,7 +8999,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9267,7 +9267,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9535,7 +9535,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9803,7 +9803,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -10071,7 +10071,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -10339,7 +10339,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Ailk_Bljk_BBS_BH_Bias_FDMN_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Ailk_Bljk_BBS_BH_Bias_FDMN_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Ailk_Bljk_BBS_BH_Bias_FDMN_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Ailk_Bljk_BBS_BH_Bias_FDMN_SPB_AS.yaml index f6e2d3ba..31bb28da 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Ailk_Bljk_BBS_BH_Bias_FDMN_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Ailk_Bljk_BBS_BH_Bias_FDMN_SPB_AS.yaml @@ -74,7 +74,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -289,7 +289,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -560,7 +560,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -831,7 +831,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1102,7 +1102,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1373,7 +1373,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1644,7 +1644,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1915,7 +1915,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2186,7 +2186,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2457,7 +2457,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2728,7 +2728,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2999,7 +2999,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3270,7 +3270,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3541,7 +3541,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3812,7 +3812,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4083,7 +4083,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4354,7 +4354,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4625,7 +4625,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4896,7 +4896,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5167,7 +5167,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5438,7 +5438,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5709,7 +5709,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5980,7 +5980,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6251,7 +6251,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6522,7 +6522,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Ailk_Bljk_BBS_BH_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Ailk_Bljk_BBS_BH_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Ailk_Bljk_BBS_BH_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Ailk_Bljk_BBS_BH_SPB_AS.yaml index ca53243a..f15c3516 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Ailk_Bljk_BBS_BH_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Ailk_Bljk_BBS_BH_SPB_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -286,7 +286,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -555,7 +555,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -824,7 +824,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1093,7 +1093,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1362,7 +1362,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1631,7 +1631,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1900,7 +1900,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2169,7 +2169,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2438,7 +2438,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2707,7 +2707,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2976,7 +2976,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3245,7 +3245,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3514,7 +3514,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3783,7 +3783,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4052,7 +4052,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4321,7 +4321,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4590,7 +4590,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4859,7 +4859,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5128,7 +5128,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5397,7 +5397,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5666,7 +5666,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Ailk_Bljk_HHS_BH_Bias_FDMN_SPA_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Ailk_Bljk_HHS_BH_Bias_FDMN_SPA_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Ailk_Bljk_HHS_BH_Bias_FDMN_SPA_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Ailk_Bljk_HHS_BH_Bias_FDMN_SPA_AS.yaml index 8901797b..3fa58bef 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Ailk_Bljk_HHS_BH_Bias_FDMN_SPA_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Ailk_Bljk_HHS_BH_Bias_FDMN_SPA_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false - - 1LDSBuffer: 0 @@ -288,7 +288,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -559,7 +559,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -819,7 +819,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1076,7 +1076,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1333,7 +1333,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1590,7 +1590,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1858,7 +1858,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2129,7 +2129,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2400,7 +2400,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2660,7 +2660,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2928,7 +2928,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3199,7 +3199,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3459,7 +3459,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3716,7 +3716,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3973,7 +3973,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4230,7 +4230,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4487,7 +4487,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4744,7 +4744,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -5010,7 +5010,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5278,7 +5278,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5546,7 +5546,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5814,7 +5814,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6082,7 +6082,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6350,7 +6350,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6618,7 +6618,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6886,7 +6886,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7154,7 +7154,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7422,7 +7422,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7690,7 +7690,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7958,7 +7958,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8226,7 +8226,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8494,7 +8494,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8762,7 +8762,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9030,7 +9030,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9298,7 +9298,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9566,7 +9566,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9834,7 +9834,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -10102,7 +10102,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -10370,7 +10370,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -10638,7 +10638,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Ailk_Bljk_HHS_BH_Bias_FDMN_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Ailk_Bljk_HHS_BH_Bias_FDMN_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Ailk_Bljk_HHS_BH_Bias_FDMN_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Ailk_Bljk_HHS_BH_Bias_FDMN_SPB_AS.yaml index 002edce3..b1cec0c8 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Ailk_Bljk_HHS_BH_Bias_FDMN_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Ailk_Bljk_HHS_BH_Bias_FDMN_SPB_AS.yaml @@ -74,7 +74,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -289,7 +289,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -560,7 +560,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -831,7 +831,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1102,7 +1102,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1373,7 +1373,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1644,7 +1644,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1915,7 +1915,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2186,7 +2186,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2457,7 +2457,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2728,7 +2728,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2999,7 +2999,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3270,7 +3270,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3541,7 +3541,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3812,7 +3812,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4083,7 +4083,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4354,7 +4354,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4625,7 +4625,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4896,7 +4896,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5167,7 +5167,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5438,7 +5438,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5709,7 +5709,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Ailk_Bljk_HHS_BH_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Ailk_Bljk_HHS_BH_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Ailk_Bljk_HHS_BH_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Ailk_Bljk_HHS_BH_SPB_AS.yaml index 6972aa63..9f50bfd2 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Ailk_Bljk_HHS_BH_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Ailk_Bljk_HHS_BH_SPB_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -286,7 +286,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -555,7 +555,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -824,7 +824,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1093,7 +1093,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1362,7 +1362,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1631,7 +1631,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1900,7 +1900,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2169,7 +2169,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2438,7 +2438,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2707,7 +2707,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2976,7 +2976,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3245,7 +3245,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3514,7 +3514,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3783,7 +3783,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4052,7 +4052,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4321,7 +4321,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4590,7 +4590,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4859,7 +4859,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5128,7 +5128,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5397,7 +5397,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5666,7 +5666,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5935,7 +5935,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Ailk_Bljk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Ailk_Bljk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Ailk_Bljk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Ailk_Bljk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml index 9def8c6c..47317efc 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Ailk_Bljk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Ailk_Bljk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -287,7 +287,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -557,7 +557,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -816,7 +816,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1083,7 +1083,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1342,7 +1342,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1609,7 +1609,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1868,7 +1868,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2124,7 +2124,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2391,7 +2391,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Ailk_Bljk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Ailk_Bljk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Ailk_Bljk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Ailk_Bljk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml index f8276026..acfd1fb4 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Ailk_Bljk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Ailk_Bljk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml @@ -74,7 +74,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -289,7 +289,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -560,7 +560,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -831,7 +831,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1102,7 +1102,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1373,7 +1373,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1644,7 +1644,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1915,7 +1915,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2186,7 +2186,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2457,7 +2457,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2728,7 +2728,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Ailk_Bljk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Ailk_Bljk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Ailk_Bljk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Ailk_Bljk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml index fb49c563..e540695e 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Ailk_Bljk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Ailk_Bljk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -287,7 +287,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -557,7 +557,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -816,7 +816,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1083,7 +1083,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1342,7 +1342,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1609,7 +1609,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1868,7 +1868,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2124,7 +2124,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2391,7 +2391,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Ailk_Bljk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Ailk_Bljk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Ailk_Bljk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Ailk_Bljk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml index 79b08886..6368fd71 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Ailk_Bljk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Ailk_Bljk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml @@ -74,7 +74,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -289,7 +289,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -560,7 +560,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -831,7 +831,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1102,7 +1102,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1373,7 +1373,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1644,7 +1644,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1915,7 +1915,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2186,7 +2186,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2457,7 +2457,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2728,7 +2728,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Ailk_Bljk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Ailk_Bljk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Ailk_Bljk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Ailk_Bljk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml index 87a8745e..1d60f05c 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Ailk_Bljk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Ailk_Bljk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false - - 1LDSBuffer: 0 @@ -288,7 +288,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -559,7 +559,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -819,7 +819,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1076,7 +1076,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1344,7 +1344,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1604,7 +1604,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1872,7 +1872,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2143,7 +2143,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2403,7 +2403,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2671,7 +2671,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2931,7 +2931,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3199,7 +3199,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3470,7 +3470,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3741,7 +3741,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4001,7 +4001,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4258,7 +4258,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4526,7 +4526,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4786,7 +4786,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -5043,7 +5043,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -5311,7 +5311,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -5577,7 +5577,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5842,7 +5842,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6107,7 +6107,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6372,7 +6372,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6637,7 +6637,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6902,7 +6902,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7167,7 +7167,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7432,7 +7432,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7697,7 +7697,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7962,7 +7962,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8227,7 +8227,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8492,7 +8492,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8757,7 +8757,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9022,7 +9022,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9287,7 +9287,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9552,7 +9552,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9817,7 +9817,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -10082,7 +10082,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -10347,7 +10347,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -10612,7 +10612,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Ailk_Bljk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Ailk_Bljk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Ailk_Bljk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Ailk_Bljk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml index 1f95e7a0..4413fb2e 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Ailk_Bljk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Ailk_Bljk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml @@ -74,7 +74,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -289,7 +289,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -560,7 +560,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -831,7 +831,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1102,7 +1102,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1373,7 +1373,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1644,7 +1644,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1915,7 +1915,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2186,7 +2186,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2457,7 +2457,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2728,7 +2728,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2999,7 +2999,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3270,7 +3270,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3541,7 +3541,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3812,7 +3812,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4083,7 +4083,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4354,7 +4354,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4625,7 +4625,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4896,7 +4896,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5167,7 +5167,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5438,7 +5438,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5709,7 +5709,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Alik_Bjlk_BBS_BH_Bias_FDMN_SPA_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Alik_Bjlk_BBS_BH_Bias_FDMN_SPA_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Alik_Bjlk_BBS_BH_Bias_FDMN_SPA_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Alik_Bjlk_BBS_BH_Bias_FDMN_SPA_AS.yaml index edc1494f..cd25a9fd 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Alik_Bjlk_BBS_BH_Bias_FDMN_SPA_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Alik_Bjlk_BBS_BH_Bias_FDMN_SPA_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false - - 1LDSBuffer: 0 @@ -288,7 +288,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -559,7 +559,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -830,7 +830,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1090,7 +1090,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1347,7 +1347,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1615,7 +1615,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1875,7 +1875,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2143,7 +2143,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2414,7 +2414,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2685,7 +2685,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2945,7 +2945,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3213,7 +3213,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3484,7 +3484,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3744,7 +3744,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4001,7 +4001,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4258,7 +4258,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4515,7 +4515,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4772,7 +4772,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -5040,7 +5040,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5310,7 +5310,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5578,7 +5578,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5848,7 +5848,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6118,7 +6118,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6388,7 +6388,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6658,7 +6658,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6928,7 +6928,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7198,7 +7198,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7468,7 +7468,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7738,7 +7738,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8008,7 +8008,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8278,7 +8278,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8548,7 +8548,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8818,7 +8818,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9088,7 +9088,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9358,7 +9358,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9628,7 +9628,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9898,7 +9898,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Alik_Bjlk_BBS_BH_Bias_FDMN_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Alik_Bjlk_BBS_BH_Bias_FDMN_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Alik_Bjlk_BBS_BH_Bias_FDMN_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Alik_Bjlk_BBS_BH_Bias_FDMN_SPB_AS.yaml index 5550913a..7d5d8e81 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Alik_Bjlk_BBS_BH_Bias_FDMN_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Alik_Bjlk_BBS_BH_Bias_FDMN_SPB_AS.yaml @@ -74,7 +74,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -289,7 +289,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -560,7 +560,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -831,7 +831,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1102,7 +1102,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1373,7 +1373,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1644,7 +1644,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1915,7 +1915,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2186,7 +2186,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2457,7 +2457,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2728,7 +2728,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2999,7 +2999,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3270,7 +3270,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Alik_Bjlk_BBS_BH_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Alik_Bjlk_BBS_BH_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Alik_Bjlk_BBS_BH_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Alik_Bjlk_BBS_BH_SPB_AS.yaml index 5cb08b05..db90e5b3 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Alik_Bjlk_BBS_BH_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Alik_Bjlk_BBS_BH_SPB_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -286,7 +286,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -555,7 +555,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -824,7 +824,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1093,7 +1093,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1362,7 +1362,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1631,7 +1631,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1900,7 +1900,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2169,7 +2169,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2438,7 +2438,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2707,7 +2707,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2976,7 +2976,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Alik_Bjlk_HHS_BH_Bias_FDMN_SPA_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Alik_Bjlk_HHS_BH_Bias_FDMN_SPA_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Alik_Bjlk_HHS_BH_Bias_FDMN_SPA_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Alik_Bjlk_HHS_BH_Bias_FDMN_SPA_AS.yaml index f5fdd1b2..5e0318f6 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Alik_Bjlk_HHS_BH_Bias_FDMN_SPA_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Alik_Bjlk_HHS_BH_Bias_FDMN_SPA_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false - - 1LDSBuffer: 0 @@ -288,7 +288,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -559,7 +559,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -819,7 +819,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1076,7 +1076,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1333,7 +1333,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1590,7 +1590,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1847,7 +1847,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2115,7 +2115,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2386,7 +2386,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2657,7 +2657,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2928,7 +2928,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3188,7 +3188,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3445,7 +3445,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3702,7 +3702,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3970,7 +3970,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4230,7 +4230,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4487,7 +4487,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4755,7 +4755,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -5026,7 +5026,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5296,7 +5296,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5564,7 +5564,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5834,7 +5834,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6104,7 +6104,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6374,7 +6374,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6644,7 +6644,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6914,7 +6914,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7184,7 +7184,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7454,7 +7454,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7724,7 +7724,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7994,7 +7994,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8264,7 +8264,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8534,7 +8534,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8804,7 +8804,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9074,7 +9074,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9344,7 +9344,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9614,7 +9614,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9884,7 +9884,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Alik_Bjlk_HHS_BH_Bias_FDMN_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Alik_Bjlk_HHS_BH_Bias_FDMN_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Alik_Bjlk_HHS_BH_Bias_FDMN_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Alik_Bjlk_HHS_BH_Bias_FDMN_SPB_AS.yaml index 09197e63..03c48ffb 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Alik_Bjlk_HHS_BH_Bias_FDMN_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Alik_Bjlk_HHS_BH_Bias_FDMN_SPB_AS.yaml @@ -74,7 +74,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -289,7 +289,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -560,7 +560,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -831,7 +831,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1102,7 +1102,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1373,7 +1373,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1644,7 +1644,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1915,7 +1915,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2186,7 +2186,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2457,7 +2457,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2728,7 +2728,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2999,7 +2999,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3270,7 +3270,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3541,7 +3541,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3812,7 +3812,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4083,7 +4083,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Alik_Bjlk_HHS_BH_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Alik_Bjlk_HHS_BH_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Alik_Bjlk_HHS_BH_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Alik_Bjlk_HHS_BH_SPB_AS.yaml index 40f24bad..105852d2 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Alik_Bjlk_HHS_BH_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Alik_Bjlk_HHS_BH_SPB_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -286,7 +286,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -555,7 +555,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -824,7 +824,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1093,7 +1093,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1362,7 +1362,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1631,7 +1631,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1900,7 +1900,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2169,7 +2169,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2438,7 +2438,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2707,7 +2707,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2976,7 +2976,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3245,7 +3245,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3514,7 +3514,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3783,7 +3783,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4052,7 +4052,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4321,7 +4321,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Alik_Bjlk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Alik_Bjlk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Alik_Bjlk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Alik_Bjlk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml index 9f6578b7..df0f9fa0 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Alik_Bjlk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Alik_Bjlk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -287,7 +287,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -546,7 +546,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -802,7 +802,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1058,7 +1058,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1325,7 +1325,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1584,7 +1584,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1851,7 +1851,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2110,7 +2110,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2366,7 +2366,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2633,7 +2633,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Alik_Bjlk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Alik_Bjlk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Alik_Bjlk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Alik_Bjlk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml index acf35df6..5d8d0f7b 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Alik_Bjlk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Alik_Bjlk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml @@ -74,7 +74,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -289,7 +289,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -560,7 +560,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -831,7 +831,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1102,7 +1102,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1373,7 +1373,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1644,7 +1644,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1915,7 +1915,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2186,7 +2186,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2457,7 +2457,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Alik_Bjlk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Alik_Bjlk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Alik_Bjlk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Alik_Bjlk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml index 42ea6b97..eab32bd3 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Alik_Bjlk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Alik_Bjlk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -287,7 +287,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -546,7 +546,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -802,7 +802,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1058,7 +1058,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1325,7 +1325,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1584,7 +1584,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1851,7 +1851,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2110,7 +2110,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2366,7 +2366,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2633,7 +2633,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Alik_Bjlk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Alik_Bjlk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Alik_Bjlk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Alik_Bjlk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml index d0b903df..e9945062 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Alik_Bjlk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Alik_Bjlk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml @@ -74,7 +74,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -289,7 +289,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -560,7 +560,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -831,7 +831,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1102,7 +1102,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1373,7 +1373,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1644,7 +1644,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1915,7 +1915,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2186,7 +2186,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2457,7 +2457,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Alik_Bjlk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Alik_Bjlk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml similarity index 96% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Alik_Bjlk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Alik_Bjlk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml index 3feeadd0..991a9941 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Alik_Bjlk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Alik_Bjlk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false - - 1LDSBuffer: 0 @@ -277,7 +277,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -545,7 +545,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -816,7 +816,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1076,7 +1076,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1333,7 +1333,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1590,7 +1590,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1847,7 +1847,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2115,7 +2115,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2375,7 +2375,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2643,7 +2643,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2914,7 +2914,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3185,7 +3185,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3456,7 +3456,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3716,7 +3716,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3973,7 +3973,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4241,7 +4241,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4501,7 +4501,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4758,7 +4758,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -5015,7 +5015,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -5272,7 +5272,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -5535,7 +5535,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5800,7 +5800,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6065,7 +6065,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6330,7 +6330,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6595,7 +6595,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6860,7 +6860,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7125,7 +7125,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7390,7 +7390,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7655,7 +7655,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7920,7 +7920,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8185,7 +8185,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8450,7 +8450,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8715,7 +8715,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8773,271 +8773,6 @@ _WorkspaceSizePerElemBias: 0 _WorkspaceSizePerElemC: 0 _staggerStrideShift: 1 - - 1LDSBuffer: 0 - ActivationAlt: false - ActivationFuncCall: true - ActivationFused: true - AssertFree0ElementMultiple: 1 - AssertFree1ElementMultiple: 1 - AssertSummationElementMultiple: 8 - AssignedDerivedParameters: true - AssignedProblemIndependentDerivedParameters: true - BufferLoad: true - BufferStore: true - CUCount: null - ClusterLocalRead: 0 - CodeObjectVersion: default - CustomKernelName: '' - DepthU: 64 - DirectToLds: false - DirectToLdsA: false - DirectToLdsB: false - DirectToLdsMetadata: false - DirectToVgprSparseMetadata: 0 - EdgeType: ShiftPtr - EnableF32XdlMathOp: false - EnableMatrixInstruction: true - ExpandPointerSwap: 1 - GlobalReadPerMfma: 1 - GlobalReadVectorWidthA: 16 - GlobalReadVectorWidthB: 16 - GlobalReadVectorWidthMetadata: 8 - GlobalSplitU: 1 - GlobalSplitUAlgorithm: MultipleBuffer - GlobalWriteVectorWidth: 1 - GroupLoadStore: false - GuaranteeNoPartialA: true - GuaranteeNoPartialB: false - ISA: [9, 4, 1] - InnerUnroll: 1 - InterleaveAlpha: 0 - KernelLanguage: Assembly - LSCA: 32 - LSCB: 256 - LSCMetadata: 8 - LSPA: 128 - LSPB: 16 - LSPMetadata: 256 - LVCA: 2 - LVCB: 16 - LVCMetadata: 1 - LVPA: 8 - LVPB: 1 - LVPMetadata: 32 - LdsBlockSizePerPadA: 128 - LdsBlockSizePerPadB: 0 - LdsBlockSizePerPadMetadata: 128 - LdsInitCVgprs: false - LdsNumElements: 60672 - LdsNumElementsAlignedA: 9216 - LdsNumElementsAlignedB: 16384 - LdsNumElementsAlignedMetadata: 2304 - LdsOffsetA: 0 - LdsOffsetA_Blk: 32768 - LdsOffsetB: 11520 - LdsOffsetB_Blk: 44288 - LdsOffsetBias: 0 - LdsOffsetMetadata: 9216 - LdsOffsetMetadata_Blk: 41984 - LdsPadA: 16 - LdsPadB: 0 - LdsPadMetadata: 4 - LocalReadVectorWidth: 16 - LocalSplitU: 1 - LocalWritePerMfma: -1 - LocalWriteUseSgprA: false - LocalWriteUseSgprB: false - LocalWriteUseSgprMetadat: false - LoopIters: 2 - LoopUnroll: 64 - MFMA_BF16_1K: false - MIArchVgpr: false - MIBlock: [32, 32, 32, 1, 1, 1] - MIInputPerThread: 16 - MIInputPerThreadA: 8 - MIInputPerThreadB: 16 - MIInputPerThreadMetadata: 2 - MIOutputVectorWidth: 4 - MIRegPerOut: 1 - MIWaveGroup: [2, 2] - MIWaveTile: [4, 4] - MIWaveTileA: 4 - MIWaveTileB: 4 - MIWaveTileMetadata: 4 - MacroTile0: 256 - MacroTile1: 256 - MacroTileA: 256 - MacroTileB: 256 - MacroTileMetadata: 256 - MagicDivAlg: 2 - MatrixInstB: 1 - MatrixInstBM: 1 - MatrixInstBN: 1 - MatrixInstK: 32 - MatrixInstM: 32 - MatrixInstN: 32 - MatrixInstruction: [32, 32, 32, 1] - MaxOccupancy: 40 - MaxVgprNumber: 256 - MinVgprNumber: 0 - NoLdsWriteCode: false - NoReject: false - NoTailLoop: false - NonTemporal: -1 - NonTemporalA: 0 - NonTemporalB: 0 - NonTemporalC: 0 - NonTemporalD: 0 - NonTemporalE: 0 - NonTemporalMetadata: 0 - NumElementsPerBatchStore: 0 - NumElementsPerThread: 256 - NumGlobalWriteVectorsPerThread: 256 - NumLoadsA: 2 - NumLoadsB: 4 - NumLoadsCoalescedA: 1 - NumLoadsCoalescedB: 1 - NumLoadsCoalescedMetadata: 1 - NumLoadsMetadata: 1 - NumLoadsPerpendicularA: 2 - NumLoadsPerpendicularB: 4 - NumLoadsPerpendicularMetadata: 1 - NumThreads: 256 - OptNoLoadLoop: 1 - PackedC0IdxChars: [I] - PackedC0IndicesX: [0] - PackedC1IdxChars: [J] - PackedC1IndicesX: [1] - PrefetchGlobalRead: 2 - PrefetchLocalRead: 1 - ProblemType: - Activation: true - ActivationComputeDataType: 0 - ActivationNoGuard: false - ActivationType: all - AllowNoFreeDims: false - AssignedDerivedParameters: true - Batched: true - BetaOnlyUseBias: false - BiasDataTypeList: [0] - BiasSrc: D - ComplexConjugateA: false - ComplexConjugateB: false - ComputeDataType: 0 - DataType: 8 - DestDataType: 8 - F32XdlMathOp: 0 - Fp16AltImpl: false - Gradient: false - GroupedGemm: false - HighPrecisionAccumulate: true - Index0: 0 - Index01A: 0 - Index01B: 1 - Index01Metadata: 0 - Index1: 1 - IndexAssignmentsA: [3, 0, 2] - IndexAssignmentsB: [1, 3, 2] - IndexAssignmentsLD: [4, 5, 6, 7] - IndexAssignmentsMetadata: [3, 0, 2] - IndexUnroll: 3 - IndexUnrollA: 0 - IndexUnrollB: 1 - IndexUnrollM: 0 - IndicesBatch: [2] - IndicesFree: [0, 1] - IndicesSummation: [3] - MirrorDimsA: &id023 [] - MirrorDimsB: [] - MirrorDimsMetadata: *id023 - NumIndicesBatch: 1 - NumIndicesC: 3 - NumIndicesFree: 2 - NumIndicesLD: 4 - NumIndicesSummation: 1 - OperationType: GEMM - SetConstStrideA: [] - SetConstStrideB: [] - SetConstStrideBias: [] - SilentHighPrecisionAccumulate: false - Sparse: 1 - StridedBatched: true - SupportUserArgs: false - TLUA: false - TLUB: true - TLUMetadata: false - Tensor0: 0 - Tensor1: 1 - TileA: 0 - TileAwareSelection: false - TileB: 1 - TotalIndices: 4 - TransposeA: true - TransposeB: true - UseBeta: true - UseBias: 3 - UseE: false - UseInitialStridesAB: false - UseInitialStridesCD: false - UseScaleAB: "" - UseScaleAlphaVec: 0 - UseScaleDVec: false - ScheduleGlobalRead: 1 - ScheduleIterAlg: 3 - ScheduleLocalWrite: 1 - SolutionIndex: 33 - SolutionNameMin: Cijk_Alik_Bjlk_I8I8S_BH_Bias_FDMN_SPA_AS_MT256x256x64_MI32x32x32x1_SN_1LDSB0_AFC1_AF0EM1_GRVWB16_GSU1_LBSPPB0_LPB0_MIWT4_4_NLCB1_PLR1_SUS128_WG64_4_1 - SourceSwap: 0 - StaggerU: 4 - StaggerUMapping: 0 - StaggerUStride: 128 - StorePriorityOpt: false - StoreRemapVectorWidth: 0 - StoreSyncOpt: 0 - StoreVectorWidth: 4 - SubGroup0: 4 - SubGroup1: 64 - SubGroupA: 4 - SubGroupB: 64 - SubGroupMetadata: 4 - SuppressNoLoadLoop: false - ThreadTile: [1, 1] - ThreadTile0: 64 - ThreadTile1: 4 - ThreadTileA: 64 - ThreadTileB: 4 - ThreadTileMetadata: 64 - TransposeLDS: 1 - TransposeLDSMetadata: true - UnrollMajorLDSA: true - UnrollMajorLDSB: false - UnrollMajorLDSMetadata: true - Use64bShadowLimit: 1 - UseInstOffsetForGRO: 0 - UseSgprForGRO: -1 - Valid: true - VectorStore: -1 - VectorWidthA: 1 - VectorWidthB: 1 - VectorWidthMetadata: 1 - WaveSeparateGlobalReadA: 0 - WaveSeparateGlobalReadB: 0 - WaveSeparateGlobalReadMetadata: 0 - WavefrontSize: 64 - WorkGroup: [64, 4, 1] - WorkGroupMapping: 18 - WorkGroupReduction: false - WorkspaceCheck: [0, 0] - _DepthU: 64 - _DepthUA: 32 - _DepthUB: 64 - _DepthUMetadata: 8 - _GlobalAccumulation: null - _UseSgprForGRO: false - _VectorStore: 1 - _WorkspaceSizePerElemBias: 0 - _WorkspaceSizePerElemC: 0 - _staggerStrideShift: 1 - [2, 3, 0, 1] - - - [16, 16, 1, 16] - [1, 0.0] @@ -9160,7 +8895,7 @@ - - [10240, 10240, 1, 19200] - [32, 28.647] - - [10240, 10240, 1, 20480] - - [33, 26.172] + - [32, 26.172] - null - null - DeviceEfficiency diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Alik_Bjlk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Alik_Bjlk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Alik_Bjlk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Alik_Bjlk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml index ee1295cb..ea9d0405 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Alik_Bjlk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Alik_Bjlk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml @@ -74,7 +74,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -289,7 +289,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -560,7 +560,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -831,7 +831,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1102,7 +1102,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1373,7 +1373,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1644,7 +1644,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1915,7 +1915,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2186,7 +2186,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2457,7 +2457,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2728,7 +2728,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2999,7 +2999,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3270,7 +3270,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3541,7 +3541,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3812,7 +3812,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4083,7 +4083,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4354,7 +4354,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4625,7 +4625,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4896,7 +4896,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5167,7 +5167,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5438,7 +5438,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5709,7 +5709,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Alik_Bljk_BBS_BH_Bias_FDMN_SPA_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Alik_Bljk_BBS_BH_Bias_FDMN_SPA_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Alik_Bljk_BBS_BH_Bias_FDMN_SPA_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Alik_Bljk_BBS_BH_Bias_FDMN_SPA_AS.yaml index 50870b0e..cab0f186 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Alik_Bljk_BBS_BH_Bias_FDMN_SPA_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Alik_Bljk_BBS_BH_Bias_FDMN_SPA_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false - - 1LDSBuffer: 0 @@ -288,7 +288,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -548,7 +548,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -805,7 +805,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1062,7 +1062,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1330,7 +1330,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1590,7 +1590,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1858,7 +1858,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2129,7 +2129,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2400,7 +2400,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2671,7 +2671,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2942,7 +2942,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3202,7 +3202,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3470,7 +3470,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3741,7 +3741,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4001,7 +4001,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4258,7 +4258,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4515,7 +4515,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4772,7 +4772,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -5040,7 +5040,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5310,7 +5310,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5580,7 +5580,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5850,7 +5850,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6120,7 +6120,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6390,7 +6390,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6660,7 +6660,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6930,7 +6930,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7200,7 +7200,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7470,7 +7470,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7740,7 +7740,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8010,7 +8010,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8280,7 +8280,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8550,7 +8550,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8820,7 +8820,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9090,7 +9090,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9360,7 +9360,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9630,7 +9630,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9900,7 +9900,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -10170,7 +10170,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -10440,7 +10440,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -10710,7 +10710,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -10978,7 +10978,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -11246,7 +11246,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -11514,7 +11514,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Alik_Bljk_BBS_BH_Bias_FDMN_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Alik_Bljk_BBS_BH_Bias_FDMN_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Alik_Bljk_BBS_BH_Bias_FDMN_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Alik_Bljk_BBS_BH_Bias_FDMN_SPB_AS.yaml index 0744d0af..9e26cddb 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Alik_Bljk_BBS_BH_Bias_FDMN_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Alik_Bljk_BBS_BH_Bias_FDMN_SPB_AS.yaml @@ -74,7 +74,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -289,7 +289,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -560,7 +560,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -831,7 +831,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1102,7 +1102,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1373,7 +1373,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1644,7 +1644,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1915,7 +1915,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2186,7 +2186,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2457,7 +2457,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2728,7 +2728,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2999,7 +2999,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3270,7 +3270,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3541,7 +3541,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3812,7 +3812,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4083,7 +4083,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4354,7 +4354,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4625,7 +4625,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4896,7 +4896,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5167,7 +5167,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Alik_Bljk_BBS_BH_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Alik_Bljk_BBS_BH_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Alik_Bljk_BBS_BH_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Alik_Bljk_BBS_BH_SPB_AS.yaml index 3bd341d4..74469cc6 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Alik_Bljk_BBS_BH_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Alik_Bljk_BBS_BH_SPB_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -286,7 +286,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -555,7 +555,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -824,7 +824,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1093,7 +1093,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1362,7 +1362,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1631,7 +1631,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1900,7 +1900,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2169,7 +2169,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2438,7 +2438,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2707,7 +2707,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2976,7 +2976,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3245,7 +3245,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3514,7 +3514,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3783,7 +3783,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4052,7 +4052,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4321,7 +4321,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4590,7 +4590,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4859,7 +4859,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5128,7 +5128,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5397,7 +5397,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5666,7 +5666,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Alik_Bljk_HHS_BH_Bias_FDMN_SPA_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Alik_Bljk_HHS_BH_Bias_FDMN_SPA_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Alik_Bljk_HHS_BH_Bias_FDMN_SPA_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Alik_Bljk_HHS_BH_Bias_FDMN_SPA_AS.yaml index 2e886ba5..7e11b14e 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Alik_Bljk_HHS_BH_Bias_FDMN_SPA_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Alik_Bljk_HHS_BH_Bias_FDMN_SPA_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false - - 1LDSBuffer: 0 @@ -288,7 +288,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -548,7 +548,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -805,7 +805,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1062,7 +1062,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1319,7 +1319,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1587,7 +1587,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1858,7 +1858,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2129,7 +2129,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2400,7 +2400,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2660,7 +2660,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2928,7 +2928,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3199,7 +3199,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3459,7 +3459,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3716,7 +3716,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3973,7 +3973,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4230,7 +4230,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4487,7 +4487,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4744,7 +4744,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -5012,7 +5012,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5282,7 +5282,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5552,7 +5552,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5822,7 +5822,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6092,7 +6092,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6362,7 +6362,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6632,7 +6632,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6902,7 +6902,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7172,7 +7172,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7442,7 +7442,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7712,7 +7712,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7982,7 +7982,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8252,7 +8252,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8522,7 +8522,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8792,7 +8792,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9062,7 +9062,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9332,7 +9332,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9602,7 +9602,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9872,7 +9872,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -10142,7 +10142,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -10412,7 +10412,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -10682,7 +10682,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -10950,7 +10950,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -11218,7 +11218,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -11486,7 +11486,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Alik_Bljk_HHS_BH_Bias_FDMN_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Alik_Bljk_HHS_BH_Bias_FDMN_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Alik_Bljk_HHS_BH_Bias_FDMN_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Alik_Bljk_HHS_BH_Bias_FDMN_SPB_AS.yaml index e2222392..60520efd 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Alik_Bljk_HHS_BH_Bias_FDMN_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Alik_Bljk_HHS_BH_Bias_FDMN_SPB_AS.yaml @@ -74,7 +74,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -289,7 +289,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -560,7 +560,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -831,7 +831,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1102,7 +1102,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1373,7 +1373,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1644,7 +1644,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1915,7 +1915,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2186,7 +2186,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2457,7 +2457,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2728,7 +2728,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2999,7 +2999,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3270,7 +3270,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3541,7 +3541,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3812,7 +3812,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4083,7 +4083,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4354,7 +4354,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4625,7 +4625,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4896,7 +4896,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5167,7 +5167,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Alik_Bljk_HHS_BH_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Alik_Bljk_HHS_BH_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Alik_Bljk_HHS_BH_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Alik_Bljk_HHS_BH_SPB_AS.yaml index d102e2e9..1aa93aee 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Alik_Bljk_HHS_BH_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Alik_Bljk_HHS_BH_SPB_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -286,7 +286,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -555,7 +555,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -824,7 +824,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1093,7 +1093,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1362,7 +1362,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1631,7 +1631,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1900,7 +1900,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2169,7 +2169,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2438,7 +2438,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2707,7 +2707,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2976,7 +2976,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Alik_Bljk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Alik_Bljk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Alik_Bljk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Alik_Bljk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml index 978411b3..a6899647 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Alik_Bljk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Alik_Bljk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -287,7 +287,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -557,7 +557,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -816,7 +816,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1072,7 +1072,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1339,7 +1339,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1598,7 +1598,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1854,7 +1854,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2110,7 +2110,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2377,7 +2377,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2636,7 +2636,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2892,7 +2892,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Alik_Bljk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Alik_Bljk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Alik_Bljk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Alik_Bljk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml index e0a6d1ee..b2681de4 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Alik_Bljk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Alik_Bljk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml @@ -74,7 +74,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -289,7 +289,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -560,7 +560,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -831,7 +831,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1102,7 +1102,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1373,7 +1373,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1644,7 +1644,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1915,7 +1915,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2186,7 +2186,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2457,7 +2457,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2728,7 +2728,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Alik_Bljk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Alik_Bljk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Alik_Bljk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Alik_Bljk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml index 8fa8df24..a08b74c4 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Alik_Bljk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Alik_Bljk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -287,7 +287,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -557,7 +557,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -816,7 +816,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1072,7 +1072,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1339,7 +1339,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1598,7 +1598,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1854,7 +1854,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2110,7 +2110,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2377,7 +2377,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2636,7 +2636,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2892,7 +2892,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Alik_Bljk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Alik_Bljk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Alik_Bljk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Alik_Bljk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml index 72314a73..f9717b55 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Alik_Bljk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Alik_Bljk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml @@ -74,7 +74,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -289,7 +289,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -560,7 +560,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -831,7 +831,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1102,7 +1102,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1373,7 +1373,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1644,7 +1644,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1915,7 +1915,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2186,7 +2186,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2457,7 +2457,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2728,7 +2728,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Alik_Bljk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Alik_Bljk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Alik_Bljk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Alik_Bljk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml index 9440c715..84a41251 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Alik_Bljk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Alik_Bljk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false - - 1LDSBuffer: 0 @@ -288,7 +288,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -548,7 +548,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -805,7 +805,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1073,7 +1073,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1333,7 +1333,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1590,7 +1590,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1847,7 +1847,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2115,7 +2115,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2375,7 +2375,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2632,7 +2632,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2889,7 +2889,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3146,7 +3146,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3403,7 +3403,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3660,7 +3660,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3928,7 +3928,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4188,7 +4188,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4451,7 +4451,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4716,7 +4716,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4981,7 +4981,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5246,7 +5246,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5511,7 +5511,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5776,7 +5776,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6041,7 +6041,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6306,7 +6306,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6571,7 +6571,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6836,7 +6836,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7101,7 +7101,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7366,7 +7366,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7631,7 +7631,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7896,7 +7896,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8161,7 +8161,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8426,7 +8426,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Alik_Bljk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Alik_Bljk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Alik_Bljk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Alik_Bljk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml index 0578bae4..40f6383e 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx941/aquavanjaram_Cijk_Alik_Bljk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx941/Equality/aquavanjaram_Cijk_Alik_Bljk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml @@ -74,7 +74,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -289,7 +289,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -560,7 +560,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -831,7 +831,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1102,7 +1102,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1373,7 +1373,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1644,7 +1644,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1915,7 +1915,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2186,7 +2186,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2457,7 +2457,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2728,7 +2728,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2999,7 +2999,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3270,7 +3270,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3541,7 +3541,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3812,7 +3812,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4083,7 +4083,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4354,7 +4354,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4625,7 +4625,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4896,7 +4896,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5167,7 +5167,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5438,7 +5438,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5709,7 +5709,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Ailk_Bjlk_BBS_BH_Bias_FDMN_SPA_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Ailk_Bjlk_BBS_BH_Bias_FDMN_SPA_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Ailk_Bjlk_BBS_BH_Bias_FDMN_SPA_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Ailk_Bjlk_BBS_BH_Bias_FDMN_SPA_AS.yaml index 35630c6b..48db7985 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Ailk_Bjlk_BBS_BH_Bias_FDMN_SPA_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Ailk_Bjlk_BBS_BH_Bias_FDMN_SPA_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false - - 1LDSBuffer: 0 @@ -288,7 +288,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -559,7 +559,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -819,7 +819,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1076,7 +1076,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1344,7 +1344,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1604,7 +1604,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1861,7 +1861,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2129,7 +2129,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2389,7 +2389,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2646,7 +2646,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2903,7 +2903,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3171,7 +3171,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3442,7 +3442,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3702,7 +3702,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3959,7 +3959,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4227,7 +4227,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4487,7 +4487,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4744,7 +4744,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -5010,7 +5010,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5279,7 +5279,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5547,7 +5547,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5815,7 +5815,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6083,7 +6083,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6351,7 +6351,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6619,7 +6619,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6887,7 +6887,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7155,7 +7155,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7423,7 +7423,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7691,7 +7691,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7959,7 +7959,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8227,7 +8227,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8495,7 +8495,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8763,7 +8763,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9031,7 +9031,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9299,7 +9299,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9567,7 +9567,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9835,7 +9835,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Ailk_Bjlk_BBS_BH_Bias_FDMN_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Ailk_Bjlk_BBS_BH_Bias_FDMN_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Ailk_Bjlk_BBS_BH_Bias_FDMN_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Ailk_Bjlk_BBS_BH_Bias_FDMN_SPB_AS.yaml index f24491ef..83e7b089 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Ailk_Bjlk_BBS_BH_Bias_FDMN_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Ailk_Bjlk_BBS_BH_Bias_FDMN_SPB_AS.yaml @@ -74,7 +74,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -289,7 +289,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -560,7 +560,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -831,7 +831,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1102,7 +1102,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1373,7 +1373,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1644,7 +1644,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1915,7 +1915,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2186,7 +2186,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2457,7 +2457,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2728,7 +2728,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2999,7 +2999,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3270,7 +3270,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3541,7 +3541,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3812,7 +3812,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4083,7 +4083,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4354,7 +4354,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4625,7 +4625,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4896,7 +4896,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5167,7 +5167,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5438,7 +5438,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Ailk_Bjlk_BBS_BH_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Ailk_Bjlk_BBS_BH_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Ailk_Bjlk_BBS_BH_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Ailk_Bjlk_BBS_BH_SPB_AS.yaml index d33cfa5c..699e22a0 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Ailk_Bjlk_BBS_BH_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Ailk_Bjlk_BBS_BH_SPB_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -286,7 +286,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -555,7 +555,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -824,7 +824,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1093,7 +1093,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1362,7 +1362,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1631,7 +1631,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1900,7 +1900,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2169,7 +2169,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2438,7 +2438,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2707,7 +2707,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2976,7 +2976,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3245,7 +3245,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3514,7 +3514,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3783,7 +3783,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4052,7 +4052,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4321,7 +4321,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4590,7 +4590,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4859,7 +4859,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Ailk_Bjlk_HHS_BH_Bias_FDMN_SPA_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Ailk_Bjlk_HHS_BH_Bias_FDMN_SPA_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Ailk_Bjlk_HHS_BH_Bias_FDMN_SPA_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Ailk_Bjlk_HHS_BH_Bias_FDMN_SPA_AS.yaml index 1649edbd..c57a57cb 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Ailk_Bjlk_HHS_BH_Bias_FDMN_SPA_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Ailk_Bjlk_HHS_BH_Bias_FDMN_SPA_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false - - 1LDSBuffer: 0 @@ -277,7 +277,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -534,7 +534,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -791,7 +791,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1059,7 +1059,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1330,7 +1330,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1590,7 +1590,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1858,7 +1858,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2129,7 +2129,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2400,7 +2400,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2671,7 +2671,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2931,7 +2931,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3188,7 +3188,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3456,7 +3456,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3727,7 +3727,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3987,7 +3987,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4244,7 +4244,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4501,7 +4501,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4769,7 +4769,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -5040,7 +5040,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -5309,7 +5309,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5578,7 +5578,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5846,7 +5846,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6114,7 +6114,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6382,7 +6382,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6650,7 +6650,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6918,7 +6918,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7186,7 +7186,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7454,7 +7454,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7722,7 +7722,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7990,7 +7990,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8258,7 +8258,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8526,7 +8526,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8794,7 +8794,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9062,7 +9062,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9330,7 +9330,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9598,7 +9598,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9866,7 +9866,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -10134,7 +10134,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Ailk_Bjlk_HHS_BH_Bias_FDMN_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Ailk_Bjlk_HHS_BH_Bias_FDMN_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Ailk_Bjlk_HHS_BH_Bias_FDMN_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Ailk_Bjlk_HHS_BH_Bias_FDMN_SPB_AS.yaml index dd857668..a5a85840 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Ailk_Bjlk_HHS_BH_Bias_FDMN_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Ailk_Bjlk_HHS_BH_Bias_FDMN_SPB_AS.yaml @@ -74,7 +74,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -289,7 +289,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -560,7 +560,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -831,7 +831,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1102,7 +1102,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1373,7 +1373,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1644,7 +1644,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1915,7 +1915,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2186,7 +2186,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2457,7 +2457,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2728,7 +2728,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2999,7 +2999,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3270,7 +3270,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3541,7 +3541,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3812,7 +3812,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4083,7 +4083,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4354,7 +4354,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4625,7 +4625,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4896,7 +4896,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5167,7 +5167,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5438,7 +5438,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5709,7 +5709,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Ailk_Bjlk_HHS_BH_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Ailk_Bjlk_HHS_BH_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Ailk_Bjlk_HHS_BH_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Ailk_Bjlk_HHS_BH_SPB_AS.yaml index e6cb2060..55bc0679 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Ailk_Bjlk_HHS_BH_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Ailk_Bjlk_HHS_BH_SPB_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -286,7 +286,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -555,7 +555,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -824,7 +824,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1093,7 +1093,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1362,7 +1362,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1631,7 +1631,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1900,7 +1900,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2169,7 +2169,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2438,7 +2438,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2707,7 +2707,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2976,7 +2976,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Ailk_Bjlk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Ailk_Bjlk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Ailk_Bjlk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Ailk_Bjlk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml index d9a8fd06..943460d0 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Ailk_Bjlk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Ailk_Bjlk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -287,7 +287,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -546,7 +546,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -813,7 +813,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1072,7 +1072,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1339,7 +1339,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1609,7 +1609,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1879,7 +1879,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2149,7 +2149,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2419,7 +2419,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2678,7 +2678,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Ailk_Bjlk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Ailk_Bjlk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Ailk_Bjlk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Ailk_Bjlk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml index 280f5821..928caaff 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Ailk_Bjlk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Ailk_Bjlk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml @@ -74,7 +74,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -289,7 +289,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -560,7 +560,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -831,7 +831,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1102,7 +1102,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1373,7 +1373,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1644,7 +1644,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1915,7 +1915,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2186,7 +2186,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2457,7 +2457,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Ailk_Bjlk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Ailk_Bjlk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Ailk_Bjlk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Ailk_Bjlk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml index a9db50c7..d63419d9 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Ailk_Bjlk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Ailk_Bjlk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -287,7 +287,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -546,7 +546,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -813,7 +813,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1072,7 +1072,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1339,7 +1339,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1609,7 +1609,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1879,7 +1879,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2149,7 +2149,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2419,7 +2419,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2678,7 +2678,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Ailk_Bjlk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Ailk_Bjlk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Ailk_Bjlk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Ailk_Bjlk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml index 1cf641ff..e8cae413 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Ailk_Bjlk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Ailk_Bjlk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml @@ -74,7 +74,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -289,7 +289,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -560,7 +560,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -831,7 +831,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1102,7 +1102,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1373,7 +1373,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1644,7 +1644,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1915,7 +1915,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2186,7 +2186,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2457,7 +2457,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Ailk_Bjlk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Ailk_Bjlk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Ailk_Bjlk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Ailk_Bjlk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml index e546f5a4..03f02f20 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Ailk_Bjlk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Ailk_Bjlk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false - - 1LDSBuffer: 0 @@ -288,7 +288,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -548,7 +548,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -805,7 +805,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1073,7 +1073,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1344,7 +1344,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1615,7 +1615,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1886,7 +1886,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2146,7 +2146,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2403,7 +2403,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2660,7 +2660,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2928,7 +2928,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3199,7 +3199,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3459,7 +3459,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3716,7 +3716,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3984,7 +3984,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4244,7 +4244,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4507,7 +4507,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4772,7 +4772,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5037,7 +5037,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5302,7 +5302,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5567,7 +5567,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5832,7 +5832,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6097,7 +6097,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6362,7 +6362,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6627,7 +6627,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6892,7 +6892,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7157,7 +7157,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7422,7 +7422,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7687,7 +7687,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7952,7 +7952,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8217,7 +8217,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Ailk_Bjlk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Ailk_Bjlk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Ailk_Bjlk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Ailk_Bjlk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml index 405cee29..f92a7117 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Ailk_Bjlk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Ailk_Bjlk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml @@ -74,7 +74,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -289,7 +289,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -560,7 +560,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -831,7 +831,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1102,7 +1102,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1373,7 +1373,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1644,7 +1644,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1915,7 +1915,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2186,7 +2186,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2457,7 +2457,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2728,7 +2728,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2999,7 +2999,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3270,7 +3270,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3541,7 +3541,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3812,7 +3812,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4083,7 +4083,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Ailk_Bljk_BBS_BH_Bias_FDMN_SPA_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Ailk_Bljk_BBS_BH_Bias_FDMN_SPA_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Ailk_Bljk_BBS_BH_Bias_FDMN_SPA_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Ailk_Bljk_BBS_BH_Bias_FDMN_SPA_AS.yaml index 7d3fcd8d..b46d3275 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Ailk_Bljk_BBS_BH_Bias_FDMN_SPA_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Ailk_Bljk_BBS_BH_Bias_FDMN_SPA_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false - - 1LDSBuffer: 0 @@ -277,7 +277,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -545,7 +545,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -805,7 +805,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1062,7 +1062,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1330,7 +1330,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1590,7 +1590,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1858,7 +1858,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2118,7 +2118,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2386,7 +2386,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2646,7 +2646,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2903,7 +2903,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3160,7 +3160,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3417,7 +3417,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3674,7 +3674,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3931,7 +3931,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4188,7 +4188,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4445,7 +4445,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4711,7 +4711,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4979,7 +4979,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5247,7 +5247,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5515,7 +5515,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5783,7 +5783,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6051,7 +6051,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6319,7 +6319,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6587,7 +6587,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6855,7 +6855,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7123,7 +7123,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7391,7 +7391,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7659,7 +7659,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7927,7 +7927,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8195,7 +8195,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8463,7 +8463,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8731,7 +8731,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8999,7 +8999,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9267,7 +9267,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9535,7 +9535,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9803,7 +9803,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -10071,7 +10071,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -10339,7 +10339,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Ailk_Bljk_BBS_BH_Bias_FDMN_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Ailk_Bljk_BBS_BH_Bias_FDMN_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Ailk_Bljk_BBS_BH_Bias_FDMN_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Ailk_Bljk_BBS_BH_Bias_FDMN_SPB_AS.yaml index 0e9a79e9..90f40968 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Ailk_Bljk_BBS_BH_Bias_FDMN_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Ailk_Bljk_BBS_BH_Bias_FDMN_SPB_AS.yaml @@ -74,7 +74,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -289,7 +289,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -560,7 +560,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -831,7 +831,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1102,7 +1102,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1373,7 +1373,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1644,7 +1644,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1915,7 +1915,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2186,7 +2186,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2457,7 +2457,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2728,7 +2728,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2999,7 +2999,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3270,7 +3270,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3541,7 +3541,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3812,7 +3812,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4083,7 +4083,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4354,7 +4354,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4625,7 +4625,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4896,7 +4896,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5167,7 +5167,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5438,7 +5438,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5709,7 +5709,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5980,7 +5980,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6251,7 +6251,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6522,7 +6522,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Ailk_Bljk_BBS_BH_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Ailk_Bljk_BBS_BH_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Ailk_Bljk_BBS_BH_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Ailk_Bljk_BBS_BH_SPB_AS.yaml index 616d3f74..a8890ef2 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Ailk_Bljk_BBS_BH_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Ailk_Bljk_BBS_BH_SPB_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -286,7 +286,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -555,7 +555,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -824,7 +824,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1093,7 +1093,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1362,7 +1362,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1631,7 +1631,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1900,7 +1900,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2169,7 +2169,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2438,7 +2438,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2707,7 +2707,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2976,7 +2976,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3245,7 +3245,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3514,7 +3514,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3783,7 +3783,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4052,7 +4052,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4321,7 +4321,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4590,7 +4590,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4859,7 +4859,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5128,7 +5128,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5397,7 +5397,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5666,7 +5666,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Ailk_Bljk_HHS_BH_Bias_FDMN_SPA_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Ailk_Bljk_HHS_BH_Bias_FDMN_SPA_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Ailk_Bljk_HHS_BH_Bias_FDMN_SPA_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Ailk_Bljk_HHS_BH_Bias_FDMN_SPA_AS.yaml index f6fe8b84..d8cbe36e 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Ailk_Bljk_HHS_BH_Bias_FDMN_SPA_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Ailk_Bljk_HHS_BH_Bias_FDMN_SPA_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false - - 1LDSBuffer: 0 @@ -288,7 +288,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -559,7 +559,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -819,7 +819,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1076,7 +1076,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1333,7 +1333,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1590,7 +1590,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1858,7 +1858,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2129,7 +2129,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2400,7 +2400,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2660,7 +2660,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2928,7 +2928,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3199,7 +3199,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3459,7 +3459,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3716,7 +3716,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3973,7 +3973,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4230,7 +4230,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4487,7 +4487,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4744,7 +4744,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -5010,7 +5010,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5278,7 +5278,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5546,7 +5546,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5814,7 +5814,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6082,7 +6082,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6350,7 +6350,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6618,7 +6618,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6886,7 +6886,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7154,7 +7154,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7422,7 +7422,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7690,7 +7690,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7958,7 +7958,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8226,7 +8226,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8494,7 +8494,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8762,7 +8762,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9030,7 +9030,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9298,7 +9298,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9566,7 +9566,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9834,7 +9834,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -10102,7 +10102,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -10370,7 +10370,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -10638,7 +10638,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Ailk_Bljk_HHS_BH_Bias_FDMN_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Ailk_Bljk_HHS_BH_Bias_FDMN_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Ailk_Bljk_HHS_BH_Bias_FDMN_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Ailk_Bljk_HHS_BH_Bias_FDMN_SPB_AS.yaml index 40a82a28..be5af8a7 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Ailk_Bljk_HHS_BH_Bias_FDMN_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Ailk_Bljk_HHS_BH_Bias_FDMN_SPB_AS.yaml @@ -74,7 +74,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -289,7 +289,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -560,7 +560,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -831,7 +831,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1102,7 +1102,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1373,7 +1373,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1644,7 +1644,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1915,7 +1915,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2186,7 +2186,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2457,7 +2457,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2728,7 +2728,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2999,7 +2999,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3270,7 +3270,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3541,7 +3541,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3812,7 +3812,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4083,7 +4083,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4354,7 +4354,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4625,7 +4625,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4896,7 +4896,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5167,7 +5167,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5438,7 +5438,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5709,7 +5709,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Ailk_Bljk_HHS_BH_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Ailk_Bljk_HHS_BH_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Ailk_Bljk_HHS_BH_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Ailk_Bljk_HHS_BH_SPB_AS.yaml index d7dab6f9..09c34f9a 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Ailk_Bljk_HHS_BH_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Ailk_Bljk_HHS_BH_SPB_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -286,7 +286,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -555,7 +555,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -824,7 +824,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1093,7 +1093,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1362,7 +1362,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1631,7 +1631,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1900,7 +1900,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2169,7 +2169,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2438,7 +2438,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2707,7 +2707,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2976,7 +2976,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3245,7 +3245,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3514,7 +3514,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3783,7 +3783,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4052,7 +4052,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4321,7 +4321,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4590,7 +4590,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4859,7 +4859,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5128,7 +5128,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5397,7 +5397,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5666,7 +5666,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5935,7 +5935,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Ailk_Bljk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Ailk_Bljk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Ailk_Bljk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Ailk_Bljk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml index c401addb..a28733ea 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Ailk_Bljk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Ailk_Bljk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -287,7 +287,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -557,7 +557,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -816,7 +816,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1083,7 +1083,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1342,7 +1342,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1609,7 +1609,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1868,7 +1868,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2124,7 +2124,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2391,7 +2391,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Ailk_Bljk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Ailk_Bljk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Ailk_Bljk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Ailk_Bljk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml index 8f370155..52923b35 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Ailk_Bljk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Ailk_Bljk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml @@ -74,7 +74,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -289,7 +289,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -560,7 +560,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -831,7 +831,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1102,7 +1102,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1373,7 +1373,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1644,7 +1644,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1915,7 +1915,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2186,7 +2186,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2457,7 +2457,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2728,7 +2728,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Ailk_Bljk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Ailk_Bljk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Ailk_Bljk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Ailk_Bljk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml index 86b829ab..4a07eabe 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Ailk_Bljk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Ailk_Bljk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -287,7 +287,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -557,7 +557,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -816,7 +816,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1083,7 +1083,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1342,7 +1342,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1609,7 +1609,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1868,7 +1868,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2124,7 +2124,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2391,7 +2391,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Ailk_Bljk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Ailk_Bljk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Ailk_Bljk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Ailk_Bljk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml index ac01b9d2..dcec7f0c 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Ailk_Bljk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Ailk_Bljk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml @@ -74,7 +74,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -289,7 +289,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -560,7 +560,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -831,7 +831,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1102,7 +1102,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1373,7 +1373,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1644,7 +1644,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1915,7 +1915,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2186,7 +2186,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2457,7 +2457,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2728,7 +2728,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Ailk_Bljk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Ailk_Bljk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Ailk_Bljk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Ailk_Bljk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml index fe40dd51..baf09557 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Ailk_Bljk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Ailk_Bljk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false - - 1LDSBuffer: 0 @@ -288,7 +288,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -559,7 +559,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -819,7 +819,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1076,7 +1076,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1344,7 +1344,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1604,7 +1604,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1872,7 +1872,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2143,7 +2143,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2403,7 +2403,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2671,7 +2671,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2931,7 +2931,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3199,7 +3199,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3470,7 +3470,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3741,7 +3741,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4001,7 +4001,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4258,7 +4258,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4526,7 +4526,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4786,7 +4786,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -5043,7 +5043,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -5311,7 +5311,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -5577,7 +5577,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5842,7 +5842,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6107,7 +6107,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6372,7 +6372,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6637,7 +6637,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6902,7 +6902,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7167,7 +7167,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7432,7 +7432,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7697,7 +7697,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7962,7 +7962,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8227,7 +8227,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8492,7 +8492,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8757,7 +8757,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9022,7 +9022,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9287,7 +9287,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9552,7 +9552,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9817,7 +9817,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -10082,7 +10082,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -10347,7 +10347,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -10612,7 +10612,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Ailk_Bljk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Ailk_Bljk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Ailk_Bljk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Ailk_Bljk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml index b4aa118f..9a3e4c92 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Ailk_Bljk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Ailk_Bljk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml @@ -74,7 +74,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -289,7 +289,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -560,7 +560,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -831,7 +831,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1102,7 +1102,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1373,7 +1373,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1644,7 +1644,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1915,7 +1915,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2186,7 +2186,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2457,7 +2457,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2728,7 +2728,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2999,7 +2999,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3270,7 +3270,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3541,7 +3541,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3812,7 +3812,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4083,7 +4083,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4354,7 +4354,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4625,7 +4625,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4896,7 +4896,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5167,7 +5167,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5438,7 +5438,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5709,7 +5709,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Alik_Bjlk_BBS_BH_Bias_FDMN_SPA_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Alik_Bjlk_BBS_BH_Bias_FDMN_SPA_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Alik_Bjlk_BBS_BH_Bias_FDMN_SPA_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Alik_Bjlk_BBS_BH_Bias_FDMN_SPA_AS.yaml index 62867ad7..dc465fc2 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Alik_Bjlk_BBS_BH_Bias_FDMN_SPA_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Alik_Bjlk_BBS_BH_Bias_FDMN_SPA_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false - - 1LDSBuffer: 0 @@ -288,7 +288,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -559,7 +559,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -830,7 +830,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1090,7 +1090,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1347,7 +1347,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1615,7 +1615,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1875,7 +1875,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2143,7 +2143,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2414,7 +2414,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2685,7 +2685,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2945,7 +2945,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3213,7 +3213,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3484,7 +3484,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3744,7 +3744,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4001,7 +4001,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4258,7 +4258,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4515,7 +4515,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4772,7 +4772,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -5040,7 +5040,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5310,7 +5310,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5578,7 +5578,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5848,7 +5848,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6118,7 +6118,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6388,7 +6388,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6658,7 +6658,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6928,7 +6928,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7198,7 +7198,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7468,7 +7468,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7738,7 +7738,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8008,7 +8008,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8278,7 +8278,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8548,7 +8548,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8818,7 +8818,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9088,7 +9088,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9358,7 +9358,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9628,7 +9628,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9898,7 +9898,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Alik_Bjlk_BBS_BH_Bias_FDMN_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Alik_Bjlk_BBS_BH_Bias_FDMN_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Alik_Bjlk_BBS_BH_Bias_FDMN_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Alik_Bjlk_BBS_BH_Bias_FDMN_SPB_AS.yaml index 6318b5b8..bbc60f35 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Alik_Bjlk_BBS_BH_Bias_FDMN_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Alik_Bjlk_BBS_BH_Bias_FDMN_SPB_AS.yaml @@ -74,7 +74,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -289,7 +289,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -560,7 +560,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -831,7 +831,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1102,7 +1102,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1373,7 +1373,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1644,7 +1644,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1915,7 +1915,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2186,7 +2186,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2457,7 +2457,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2728,7 +2728,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2999,7 +2999,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3270,7 +3270,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Alik_Bjlk_BBS_BH_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Alik_Bjlk_BBS_BH_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Alik_Bjlk_BBS_BH_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Alik_Bjlk_BBS_BH_SPB_AS.yaml index 6cd40621..c8f7c40a 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Alik_Bjlk_BBS_BH_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Alik_Bjlk_BBS_BH_SPB_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -286,7 +286,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -555,7 +555,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -824,7 +824,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1093,7 +1093,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1362,7 +1362,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1631,7 +1631,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1900,7 +1900,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2169,7 +2169,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2438,7 +2438,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2707,7 +2707,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2976,7 +2976,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Alik_Bjlk_HHS_BH_Bias_FDMN_SPA_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Alik_Bjlk_HHS_BH_Bias_FDMN_SPA_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Alik_Bjlk_HHS_BH_Bias_FDMN_SPA_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Alik_Bjlk_HHS_BH_Bias_FDMN_SPA_AS.yaml index bba56876..6bca5f04 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Alik_Bjlk_HHS_BH_Bias_FDMN_SPA_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Alik_Bjlk_HHS_BH_Bias_FDMN_SPA_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false - - 1LDSBuffer: 0 @@ -288,7 +288,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -559,7 +559,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -819,7 +819,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1076,7 +1076,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1333,7 +1333,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1590,7 +1590,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1847,7 +1847,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2115,7 +2115,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2386,7 +2386,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2657,7 +2657,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2928,7 +2928,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3188,7 +3188,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3445,7 +3445,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3702,7 +3702,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3970,7 +3970,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4230,7 +4230,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4487,7 +4487,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4755,7 +4755,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -5026,7 +5026,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5296,7 +5296,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5564,7 +5564,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5834,7 +5834,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6104,7 +6104,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6374,7 +6374,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6644,7 +6644,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6914,7 +6914,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7184,7 +7184,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7454,7 +7454,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7724,7 +7724,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7994,7 +7994,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8264,7 +8264,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8534,7 +8534,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8804,7 +8804,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9074,7 +9074,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9344,7 +9344,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9614,7 +9614,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9884,7 +9884,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Alik_Bjlk_HHS_BH_Bias_FDMN_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Alik_Bjlk_HHS_BH_Bias_FDMN_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Alik_Bjlk_HHS_BH_Bias_FDMN_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Alik_Bjlk_HHS_BH_Bias_FDMN_SPB_AS.yaml index 75d92bae..d79e9baf 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Alik_Bjlk_HHS_BH_Bias_FDMN_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Alik_Bjlk_HHS_BH_Bias_FDMN_SPB_AS.yaml @@ -74,7 +74,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -289,7 +289,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -560,7 +560,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -831,7 +831,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1102,7 +1102,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1373,7 +1373,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1644,7 +1644,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1915,7 +1915,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2186,7 +2186,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2457,7 +2457,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2728,7 +2728,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2999,7 +2999,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3270,7 +3270,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3541,7 +3541,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3812,7 +3812,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4083,7 +4083,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Alik_Bjlk_HHS_BH_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Alik_Bjlk_HHS_BH_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Alik_Bjlk_HHS_BH_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Alik_Bjlk_HHS_BH_SPB_AS.yaml index 5bf55360..e59f8eef 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Alik_Bjlk_HHS_BH_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Alik_Bjlk_HHS_BH_SPB_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -286,7 +286,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -555,7 +555,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -824,7 +824,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1093,7 +1093,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1362,7 +1362,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1631,7 +1631,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1900,7 +1900,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2169,7 +2169,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2438,7 +2438,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2707,7 +2707,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2976,7 +2976,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3245,7 +3245,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3514,7 +3514,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3783,7 +3783,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4052,7 +4052,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4321,7 +4321,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Alik_Bjlk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Alik_Bjlk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Alik_Bjlk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Alik_Bjlk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml index 47a12b3e..9cf79151 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Alik_Bjlk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Alik_Bjlk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -287,7 +287,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -546,7 +546,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -802,7 +802,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1058,7 +1058,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1325,7 +1325,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1584,7 +1584,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1851,7 +1851,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2110,7 +2110,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2366,7 +2366,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2633,7 +2633,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Alik_Bjlk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Alik_Bjlk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Alik_Bjlk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Alik_Bjlk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml index bc65ee3a..a5d576c2 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Alik_Bjlk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Alik_Bjlk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml @@ -74,7 +74,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -289,7 +289,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -560,7 +560,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -831,7 +831,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1102,7 +1102,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1373,7 +1373,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1644,7 +1644,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1915,7 +1915,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2186,7 +2186,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2457,7 +2457,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Alik_Bjlk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Alik_Bjlk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Alik_Bjlk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Alik_Bjlk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml index bb90dfc7..a81a1223 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Alik_Bjlk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Alik_Bjlk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -287,7 +287,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -546,7 +546,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -802,7 +802,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1058,7 +1058,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1325,7 +1325,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1584,7 +1584,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1851,7 +1851,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2110,7 +2110,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2366,7 +2366,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2633,7 +2633,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Alik_Bjlk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Alik_Bjlk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Alik_Bjlk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Alik_Bjlk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml index 94241ef1..c9c60b5e 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Alik_Bjlk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Alik_Bjlk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml @@ -74,7 +74,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -289,7 +289,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -560,7 +560,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -831,7 +831,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1102,7 +1102,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1373,7 +1373,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1644,7 +1644,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1915,7 +1915,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2186,7 +2186,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2457,7 +2457,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Alik_Bjlk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Alik_Bjlk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml similarity index 96% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Alik_Bjlk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Alik_Bjlk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml index 25fe94b3..40fd8720 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Alik_Bjlk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Alik_Bjlk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false - - 1LDSBuffer: 0 @@ -277,7 +277,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -545,7 +545,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -816,7 +816,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1076,7 +1076,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1333,7 +1333,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1590,7 +1590,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1847,7 +1847,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2115,7 +2115,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2375,7 +2375,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2643,7 +2643,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2914,7 +2914,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3185,7 +3185,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3456,7 +3456,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3716,7 +3716,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3973,7 +3973,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4241,7 +4241,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4501,7 +4501,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4758,7 +4758,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -5015,7 +5015,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -5272,7 +5272,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -5535,7 +5535,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5800,7 +5800,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6065,7 +6065,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6330,7 +6330,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6595,7 +6595,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6860,7 +6860,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7125,7 +7125,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7390,7 +7390,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7655,7 +7655,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7920,7 +7920,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8185,7 +8185,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8450,7 +8450,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8715,7 +8715,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8773,271 +8773,6 @@ _WorkspaceSizePerElemBias: 0 _WorkspaceSizePerElemC: 0 _staggerStrideShift: 1 - - 1LDSBuffer: 0 - ActivationAlt: false - ActivationFuncCall: true - ActivationFused: true - AssertFree0ElementMultiple: 1 - AssertFree1ElementMultiple: 1 - AssertSummationElementMultiple: 8 - AssignedDerivedParameters: true - AssignedProblemIndependentDerivedParameters: true - BufferLoad: true - BufferStore: true - CUCount: null - ClusterLocalRead: 0 - CodeObjectVersion: default - CustomKernelName: '' - DepthU: 64 - DirectToLds: false - DirectToLdsA: false - DirectToLdsB: false - DirectToLdsMetadata: false - DirectToVgprSparseMetadata: 0 - EdgeType: ShiftPtr - EnableF32XdlMathOp: false - EnableMatrixInstruction: true - ExpandPointerSwap: 1 - GlobalReadPerMfma: 1 - GlobalReadVectorWidthA: 16 - GlobalReadVectorWidthB: 16 - GlobalReadVectorWidthMetadata: 8 - GlobalSplitU: 1 - GlobalSplitUAlgorithm: MultipleBuffer - GlobalWriteVectorWidth: 1 - GroupLoadStore: false - GuaranteeNoPartialA: true - GuaranteeNoPartialB: false - ISA: [9, 4, 2] - InnerUnroll: 1 - InterleaveAlpha: 0 - KernelLanguage: Assembly - LSCA: 32 - LSCB: 256 - LSCMetadata: 8 - LSPA: 128 - LSPB: 16 - LSPMetadata: 256 - LVCA: 2 - LVCB: 16 - LVCMetadata: 1 - LVPA: 8 - LVPB: 1 - LVPMetadata: 32 - LdsBlockSizePerPadA: 128 - LdsBlockSizePerPadB: 0 - LdsBlockSizePerPadMetadata: 128 - LdsInitCVgprs: false - LdsNumElements: 60672 - LdsNumElementsAlignedA: 9216 - LdsNumElementsAlignedB: 16384 - LdsNumElementsAlignedMetadata: 2304 - LdsOffsetA: 0 - LdsOffsetA_Blk: 32768 - LdsOffsetB: 11520 - LdsOffsetB_Blk: 44288 - LdsOffsetBias: 0 - LdsOffsetMetadata: 9216 - LdsOffsetMetadata_Blk: 41984 - LdsPadA: 16 - LdsPadB: 0 - LdsPadMetadata: 4 - LocalReadVectorWidth: 16 - LocalSplitU: 1 - LocalWritePerMfma: -1 - LocalWriteUseSgprA: false - LocalWriteUseSgprB: false - LocalWriteUseSgprMetadat: false - LoopIters: 2 - LoopUnroll: 64 - MFMA_BF16_1K: false - MIArchVgpr: false - MIBlock: [32, 32, 32, 1, 1, 1] - MIInputPerThread: 16 - MIInputPerThreadA: 8 - MIInputPerThreadB: 16 - MIInputPerThreadMetadata: 2 - MIOutputVectorWidth: 4 - MIRegPerOut: 1 - MIWaveGroup: [2, 2] - MIWaveTile: [4, 4] - MIWaveTileA: 4 - MIWaveTileB: 4 - MIWaveTileMetadata: 4 - MacroTile0: 256 - MacroTile1: 256 - MacroTileA: 256 - MacroTileB: 256 - MacroTileMetadata: 256 - MagicDivAlg: 2 - MatrixInstB: 1 - MatrixInstBM: 1 - MatrixInstBN: 1 - MatrixInstK: 32 - MatrixInstM: 32 - MatrixInstN: 32 - MatrixInstruction: [32, 32, 32, 1] - MaxOccupancy: 40 - MaxVgprNumber: 256 - MinVgprNumber: 0 - NoLdsWriteCode: false - NoReject: false - NoTailLoop: false - NonTemporal: -1 - NonTemporalA: 0 - NonTemporalB: 0 - NonTemporalC: 0 - NonTemporalD: 0 - NonTemporalE: 0 - NonTemporalMetadata: 0 - NumElementsPerBatchStore: 0 - NumElementsPerThread: 256 - NumGlobalWriteVectorsPerThread: 256 - NumLoadsA: 2 - NumLoadsB: 4 - NumLoadsCoalescedA: 1 - NumLoadsCoalescedB: 1 - NumLoadsCoalescedMetadata: 1 - NumLoadsMetadata: 1 - NumLoadsPerpendicularA: 2 - NumLoadsPerpendicularB: 4 - NumLoadsPerpendicularMetadata: 1 - NumThreads: 256 - OptNoLoadLoop: 1 - PackedC0IdxChars: [I] - PackedC0IndicesX: [0] - PackedC1IdxChars: [J] - PackedC1IndicesX: [1] - PrefetchGlobalRead: 2 - PrefetchLocalRead: 1 - ProblemType: - Activation: true - ActivationComputeDataType: 0 - ActivationNoGuard: false - ActivationType: all - AllowNoFreeDims: false - AssignedDerivedParameters: true - Batched: true - BetaOnlyUseBias: false - BiasDataTypeList: [0] - BiasSrc: D - ComplexConjugateA: false - ComplexConjugateB: false - ComputeDataType: 0 - DataType: 8 - DestDataType: 8 - F32XdlMathOp: 0 - Fp16AltImpl: false - Gradient: false - GroupedGemm: false - HighPrecisionAccumulate: true - Index0: 0 - Index01A: 0 - Index01B: 1 - Index01Metadata: 0 - Index1: 1 - IndexAssignmentsA: [3, 0, 2] - IndexAssignmentsB: [1, 3, 2] - IndexAssignmentsLD: [4, 5, 6, 7] - IndexAssignmentsMetadata: [3, 0, 2] - IndexUnroll: 3 - IndexUnrollA: 0 - IndexUnrollB: 1 - IndexUnrollM: 0 - IndicesBatch: [2] - IndicesFree: [0, 1] - IndicesSummation: [3] - MirrorDimsA: &id023 [] - MirrorDimsB: [] - MirrorDimsMetadata: *id023 - NumIndicesBatch: 1 - NumIndicesC: 3 - NumIndicesFree: 2 - NumIndicesLD: 4 - NumIndicesSummation: 1 - OperationType: GEMM - SetConstStrideA: [] - SetConstStrideB: [] - SetConstStrideBias: [] - SilentHighPrecisionAccumulate: false - Sparse: 1 - StridedBatched: true - SupportUserArgs: false - TLUA: false - TLUB: true - TLUMetadata: false - Tensor0: 0 - Tensor1: 1 - TileA: 0 - TileAwareSelection: false - TileB: 1 - TotalIndices: 4 - TransposeA: true - TransposeB: true - UseBeta: true - UseBias: 3 - UseE: false - UseInitialStridesAB: false - UseInitialStridesCD: false - UseScaleAB: "" - UseScaleAlphaVec: 0 - UseScaleDVec: false - ScheduleGlobalRead: 1 - ScheduleIterAlg: 3 - ScheduleLocalWrite: 1 - SolutionIndex: 33 - SolutionNameMin: Cijk_Alik_Bjlk_I8I8S_BH_Bias_FDMN_SPA_AS_MT256x256x64_MI32x32x32x1_SN_1LDSB0_AFC1_AF0EM1_GRVWB16_GSU1_LBSPPB0_LPB0_MIWT4_4_NLCB1_PLR1_SUS128_WG64_4_1 - SourceSwap: 0 - StaggerU: 4 - StaggerUMapping: 0 - StaggerUStride: 128 - StorePriorityOpt: false - StoreRemapVectorWidth: 0 - StoreSyncOpt: 0 - StoreVectorWidth: 4 - SubGroup0: 4 - SubGroup1: 64 - SubGroupA: 4 - SubGroupB: 64 - SubGroupMetadata: 4 - SuppressNoLoadLoop: false - ThreadTile: [1, 1] - ThreadTile0: 64 - ThreadTile1: 4 - ThreadTileA: 64 - ThreadTileB: 4 - ThreadTileMetadata: 64 - TransposeLDS: 1 - TransposeLDSMetadata: true - UnrollMajorLDSA: true - UnrollMajorLDSB: false - UnrollMajorLDSMetadata: true - Use64bShadowLimit: 1 - UseInstOffsetForGRO: 0 - UseSgprForGRO: -1 - Valid: true - VectorStore: -1 - VectorWidthA: 1 - VectorWidthB: 1 - VectorWidthMetadata: 1 - WaveSeparateGlobalReadA: 0 - WaveSeparateGlobalReadB: 0 - WaveSeparateGlobalReadMetadata: 0 - WavefrontSize: 64 - WorkGroup: [64, 4, 1] - WorkGroupMapping: 18 - WorkGroupReduction: false - WorkspaceCheck: [0, 0] - _DepthU: 64 - _DepthUA: 32 - _DepthUB: 64 - _DepthUMetadata: 8 - _GlobalAccumulation: null - _UseSgprForGRO: false - _VectorStore: 1 - _WorkspaceSizePerElemBias: 0 - _WorkspaceSizePerElemC: 0 - _staggerStrideShift: 1 - [2, 3, 0, 1] - - - [16, 16, 1, 16] - [1, 0.0] @@ -9160,7 +8895,7 @@ - - [10240, 10240, 1, 19200] - [32, 28.647] - - [10240, 10240, 1, 20480] - - [33, 26.172] + - [32, 26.172] - null - null - DeviceEfficiency diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Alik_Bjlk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Alik_Bjlk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Alik_Bjlk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Alik_Bjlk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml index 525bea29..571e439c 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Alik_Bjlk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Alik_Bjlk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml @@ -74,7 +74,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -289,7 +289,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -560,7 +560,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -831,7 +831,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1102,7 +1102,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1373,7 +1373,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1644,7 +1644,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1915,7 +1915,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2186,7 +2186,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2457,7 +2457,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2728,7 +2728,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2999,7 +2999,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3270,7 +3270,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3541,7 +3541,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3812,7 +3812,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4083,7 +4083,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4354,7 +4354,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4625,7 +4625,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4896,7 +4896,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5167,7 +5167,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5438,7 +5438,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5709,7 +5709,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Alik_Bljk_BBS_BH_Bias_FDMN_SPA_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Alik_Bljk_BBS_BH_Bias_FDMN_SPA_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Alik_Bljk_BBS_BH_Bias_FDMN_SPA_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Alik_Bljk_BBS_BH_Bias_FDMN_SPA_AS.yaml index ecdac406..c6ddbc79 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Alik_Bljk_BBS_BH_Bias_FDMN_SPA_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Alik_Bljk_BBS_BH_Bias_FDMN_SPA_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false - - 1LDSBuffer: 0 @@ -288,7 +288,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -548,7 +548,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -805,7 +805,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1062,7 +1062,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1330,7 +1330,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1590,7 +1590,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1858,7 +1858,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2129,7 +2129,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2400,7 +2400,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2671,7 +2671,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2942,7 +2942,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3202,7 +3202,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3470,7 +3470,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3741,7 +3741,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4001,7 +4001,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4258,7 +4258,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4515,7 +4515,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4772,7 +4772,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -5040,7 +5040,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5310,7 +5310,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5580,7 +5580,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5850,7 +5850,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6120,7 +6120,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6390,7 +6390,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6660,7 +6660,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6930,7 +6930,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7200,7 +7200,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7470,7 +7470,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7740,7 +7740,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8010,7 +8010,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8280,7 +8280,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8550,7 +8550,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8820,7 +8820,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9090,7 +9090,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9360,7 +9360,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9630,7 +9630,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9900,7 +9900,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -10170,7 +10170,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -10440,7 +10440,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -10710,7 +10710,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -10978,7 +10978,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -11246,7 +11246,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -11514,7 +11514,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Alik_Bljk_BBS_BH_Bias_FDMN_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Alik_Bljk_BBS_BH_Bias_FDMN_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Alik_Bljk_BBS_BH_Bias_FDMN_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Alik_Bljk_BBS_BH_Bias_FDMN_SPB_AS.yaml index e9ada0f5..c3382644 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Alik_Bljk_BBS_BH_Bias_FDMN_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Alik_Bljk_BBS_BH_Bias_FDMN_SPB_AS.yaml @@ -74,7 +74,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -289,7 +289,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -560,7 +560,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -831,7 +831,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1102,7 +1102,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1373,7 +1373,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1644,7 +1644,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1915,7 +1915,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2186,7 +2186,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2457,7 +2457,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2728,7 +2728,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2999,7 +2999,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3270,7 +3270,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3541,7 +3541,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3812,7 +3812,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4083,7 +4083,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4354,7 +4354,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4625,7 +4625,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4896,7 +4896,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5167,7 +5167,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Alik_Bljk_BBS_BH_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Alik_Bljk_BBS_BH_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Alik_Bljk_BBS_BH_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Alik_Bljk_BBS_BH_SPB_AS.yaml index 89262500..ad5f9ad5 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Alik_Bljk_BBS_BH_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Alik_Bljk_BBS_BH_SPB_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -286,7 +286,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -555,7 +555,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -824,7 +824,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1093,7 +1093,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1362,7 +1362,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1631,7 +1631,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1900,7 +1900,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2169,7 +2169,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2438,7 +2438,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2707,7 +2707,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2976,7 +2976,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3245,7 +3245,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3514,7 +3514,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3783,7 +3783,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4052,7 +4052,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4321,7 +4321,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4590,7 +4590,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4859,7 +4859,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5128,7 +5128,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5397,7 +5397,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5666,7 +5666,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Alik_Bljk_HHS_BH_Bias_FDMN_SPA_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Alik_Bljk_HHS_BH_Bias_FDMN_SPA_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Alik_Bljk_HHS_BH_Bias_FDMN_SPA_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Alik_Bljk_HHS_BH_Bias_FDMN_SPA_AS.yaml index cfcc2a0f..c227c5ca 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Alik_Bljk_HHS_BH_Bias_FDMN_SPA_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Alik_Bljk_HHS_BH_Bias_FDMN_SPA_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false - - 1LDSBuffer: 0 @@ -288,7 +288,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -548,7 +548,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -805,7 +805,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1062,7 +1062,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1319,7 +1319,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1587,7 +1587,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1858,7 +1858,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2129,7 +2129,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2400,7 +2400,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2660,7 +2660,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2928,7 +2928,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3199,7 +3199,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3459,7 +3459,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3716,7 +3716,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3973,7 +3973,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4230,7 +4230,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4487,7 +4487,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4744,7 +4744,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -5012,7 +5012,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5282,7 +5282,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5552,7 +5552,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5822,7 +5822,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6092,7 +6092,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6362,7 +6362,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6632,7 +6632,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6902,7 +6902,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7172,7 +7172,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7442,7 +7442,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7712,7 +7712,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7982,7 +7982,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8252,7 +8252,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8522,7 +8522,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8792,7 +8792,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9062,7 +9062,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9332,7 +9332,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9602,7 +9602,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -9872,7 +9872,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -10142,7 +10142,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -10412,7 +10412,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -10682,7 +10682,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -10950,7 +10950,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -11218,7 +11218,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -11486,7 +11486,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Alik_Bljk_HHS_BH_Bias_FDMN_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Alik_Bljk_HHS_BH_Bias_FDMN_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Alik_Bljk_HHS_BH_Bias_FDMN_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Alik_Bljk_HHS_BH_Bias_FDMN_SPB_AS.yaml index 33e811d7..80750a20 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Alik_Bljk_HHS_BH_Bias_FDMN_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Alik_Bljk_HHS_BH_Bias_FDMN_SPB_AS.yaml @@ -74,7 +74,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -289,7 +289,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -560,7 +560,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -831,7 +831,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1102,7 +1102,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1373,7 +1373,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1644,7 +1644,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1915,7 +1915,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2186,7 +2186,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2457,7 +2457,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2728,7 +2728,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2999,7 +2999,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3270,7 +3270,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3541,7 +3541,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3812,7 +3812,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4083,7 +4083,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4354,7 +4354,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4625,7 +4625,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4896,7 +4896,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5167,7 +5167,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Alik_Bljk_HHS_BH_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Alik_Bljk_HHS_BH_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Alik_Bljk_HHS_BH_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Alik_Bljk_HHS_BH_SPB_AS.yaml index aae3c5ec..b33da545 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Alik_Bljk_HHS_BH_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Alik_Bljk_HHS_BH_SPB_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -286,7 +286,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -555,7 +555,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -824,7 +824,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1093,7 +1093,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1362,7 +1362,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1631,7 +1631,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1900,7 +1900,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2169,7 +2169,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2438,7 +2438,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2707,7 +2707,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2976,7 +2976,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Alik_Bljk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Alik_Bljk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Alik_Bljk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Alik_Bljk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml index f2f990b2..30428f96 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Alik_Bljk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Alik_Bljk_I8BS_BH_BiasS_FDMN_SPA_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -287,7 +287,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -557,7 +557,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -816,7 +816,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1072,7 +1072,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1339,7 +1339,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1598,7 +1598,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1854,7 +1854,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2110,7 +2110,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2377,7 +2377,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2636,7 +2636,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2892,7 +2892,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Alik_Bljk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Alik_Bljk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Alik_Bljk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Alik_Bljk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml index 63558027..3095dd9e 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Alik_Bljk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Alik_Bljk_I8BS_BH_BiasS_FDMN_SPB_AS.yaml @@ -74,7 +74,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -289,7 +289,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -560,7 +560,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -831,7 +831,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1102,7 +1102,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1373,7 +1373,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1644,7 +1644,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1915,7 +1915,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2186,7 +2186,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2457,7 +2457,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2728,7 +2728,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Alik_Bljk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Alik_Bljk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Alik_Bljk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Alik_Bljk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml index 81b05e06..427cb8d8 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Alik_Bljk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Alik_Bljk_I8HS_BH_BiasS_FDMN_SPA_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -287,7 +287,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -557,7 +557,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -816,7 +816,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1072,7 +1072,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1339,7 +1339,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1598,7 +1598,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1854,7 +1854,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2110,7 +2110,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2377,7 +2377,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2636,7 +2636,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2892,7 +2892,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Alik_Bljk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Alik_Bljk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Alik_Bljk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Alik_Bljk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml index 2b59b6b4..9be479de 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Alik_Bljk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Alik_Bljk_I8HS_BH_BiasS_FDMN_SPB_AS.yaml @@ -74,7 +74,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -289,7 +289,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -560,7 +560,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -831,7 +831,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1102,7 +1102,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1373,7 +1373,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1644,7 +1644,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1915,7 +1915,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2186,7 +2186,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2457,7 +2457,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2728,7 +2728,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Alik_Bljk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Alik_Bljk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Alik_Bljk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Alik_Bljk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml index 43bdd988..7006cd1b 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Alik_Bljk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Alik_Bljk_I8I8S_BH_Bias_FDMN_SPA_AS.yaml @@ -73,7 +73,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false - - 1LDSBuffer: 0 @@ -288,7 +288,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -548,7 +548,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -805,7 +805,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1073,7 +1073,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1333,7 +1333,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1590,7 +1590,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -1847,7 +1847,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2115,7 +2115,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2375,7 +2375,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2632,7 +2632,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -2889,7 +2889,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3146,7 +3146,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3403,7 +3403,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3660,7 +3660,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -3928,7 +3928,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4188,7 +4188,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false UseScaleDVec: false ScheduleGlobalRead: 1 @@ -4451,7 +4451,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4716,7 +4716,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4981,7 +4981,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5246,7 +5246,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5511,7 +5511,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5776,7 +5776,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6041,7 +6041,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6306,7 +6306,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6571,7 +6571,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -6836,7 +6836,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7101,7 +7101,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7366,7 +7366,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7631,7 +7631,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -7896,7 +7896,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8161,7 +8161,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -8426,7 +8426,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleDVec: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 diff --git a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Alik_Bljk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Alik_Bljk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml similarity index 99% rename from library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Alik_Bljk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml rename to library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Alik_Bljk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml index 9b326405..c6962d96 100644 --- a/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/aquavanjaram/gfx942/aquavanjaram_Cijk_Alik_Bljk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml +++ b/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/Equality/aquavanjaram_Cijk_Alik_Bljk_I8I8S_BH_Bias_FDMN_SPB_AS.yaml @@ -74,7 +74,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false - - 1LDSBuffer: 0 ActivationAlt: false @@ -289,7 +289,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -560,7 +560,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -831,7 +831,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1102,7 +1102,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1373,7 +1373,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1644,7 +1644,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -1915,7 +1915,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2186,7 +2186,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2457,7 +2457,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2728,7 +2728,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -2999,7 +2999,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3270,7 +3270,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3541,7 +3541,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -3812,7 +3812,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4083,7 +4083,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4354,7 +4354,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4625,7 +4625,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -4896,7 +4896,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5167,7 +5167,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5438,7 +5438,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3 @@ -5709,7 +5709,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false UseScaleAB: "" - UseScaleAlphaVec: 0 + UseScaleAlphaVec: 3 UseScaleCD: false ScheduleGlobalRead: 1 ScheduleIterAlg: 3