[AMDGPU] Use replaceOpcodeWith instead of applyCombine_s_mul_u64. NFC.

ROCm · May 3, 2024 · 1cde124 · 1cde124
1 parent 5fc5769
commit 1cde124
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Showing 2 changed files with 2 additions and 8 deletions.
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCombine.td b/llvm/lib/Target/AMDGPU/AMDGPUCombine.td
@@ -115,7 +115,7 @@ def smulu64 : GICombineRule<
  (defs root:$smul, unsigned_matchinfo:$matchinfo),
  (match (wip_match_opcode G_MUL):$smul,
  [{ return matchCombine_s_mul_u64(*${smul}, ${matchinfo}); }]),
- (apply [{ applyCombine_s_mul_u64(*${smul}, ${matchinfo}); }])>;
+ (apply [{ Helper.replaceOpcodeWith(*${smul}, ${matchinfo}); }])>;
 
 def sign_exension_in_reg_matchdata : GIDefMatchData<"std::pair<MachineInstr *, unsigned>">;
 

diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp b/llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp
@@ -107,11 +107,10 @@ class AMDGPUPostLegalizerCombinerImpl : public Combiner {
 
  // Find the s_mul_u64 instructions where the higher bits are either
  // zero-extended or sign-extended.
- bool matchCombine_s_mul_u64(MachineInstr &MI, unsigned &NewOpcode) const;
  // Replace the s_mul_u64 instructions with S_MUL_I64_I32_PSEUDO if the higher
  // 33 bits are sign extended and with S_MUL_U64_U32_PSEUDO if the higher 32
  // bits are zero extended.
- void applyCombine_s_mul_u64(MachineInstr &MI, unsigned &NewOpcode) const;
+ bool matchCombine_s_mul_u64(MachineInstr &MI, unsigned &NewOpcode) const;
 
 private:
 #define GET_GICOMBINER_CLASS_MEMBERS
@@ -438,11 +437,6 @@ bool AMDGPUPostLegalizerCombinerImpl::matchCombine_s_mul_u64(
  return false;
 }
 
-void AMDGPUPostLegalizerCombinerImpl::applyCombine_s_mul_u64(
- MachineInstr &MI, unsigned &NewOpcode) const {
- Helper.replaceOpcodeWith(MI, NewOpcode);
-}
-
 // Pass boilerplate
 // ================