[ARM] Add VECTOR_REG_CAST identity fold.

v16i8 VECTOR_REG_CAST (v16i8 Op) can use v16i8 Op directly, as the VECTOR_REG_CAST is a noop.
ROCm · Aug 24, 2024 · b9a0276 · b9a0276
1 parent 77fccb3
commit b9a0276
Show file tree

Hide file tree

Showing 2 changed files with 6 additions and 4 deletions.
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -15444,6 +15444,9 @@ static SDValue PerformVECTOR_REG_CASTCombine(SDNode *N, SelectionDAG &DAG,
  if (ST->isLittle())
  return DAG.getNode(ISD::BITCAST, dl, VT, Op);
 
+ // VT VECTOR_REG_CAST (VT Op) -> Op
+ if (Op.getValueType() == VT)
+ return Op;
  // VECTOR_REG_CAST undef -> undef
  if (Op.isUndef())
  return DAG.getUNDEF(VT);

diff --git a/llvm/test/CodeGen/Thumb2/mve-be.ll b/llvm/test/CodeGen/Thumb2/mve-be.ll
@@ -278,10 +278,9 @@ define arm_aapcs_vfpcc <4 x i32> @test(ptr %data) {
 ;
 ; CHECK-BE-LABEL: test:
 ; CHECK-BE: @ %bb.0: @ %entry
-; CHECK-BE-NEXT: movs r1, #1
-; CHECK-BE-NEXT: vldrw.u32 q1, [r0, #32]
-; CHECK-BE-NEXT: vdup.32 q0, r1
-; CHECK-BE-NEXT: vadd.i32 q0, q1, q0
+; CHECK-BE-NEXT: vldrw.u32 q0, [r0, #32]
+; CHECK-BE-NEXT: movs r0, #1
+; CHECK-BE-NEXT: vadd.i32 q0, q0, r0
 ; CHECK-BE-NEXT: vrev32.8 q0, q0
 ; CHECK-BE-NEXT: @APP
 ; CHECK-BE-NEXT: vmullb.s32 q1, q0, q0