merge main into amd-staging

Change-Id: I4012e929fe31d8afff1bd360a7a0033449ce787a
ROCm · Mar 28, 2024 · efc7219 · efc7219
2 parents f21251c + 5dfc446
commit efc7219
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diff --git a/llvm/include/llvm/Transforms/Utils/SampleProfileLoaderBaseImpl.h b/llvm/include/llvm/Transforms/Utils/SampleProfileLoaderBaseImpl.h
@@ -134,6 +134,7 @@ class PseudoProbeManager {
  F.hasFnAttribute("profile-checksum-mismatch")) &&
  "In post-link, profile checksum matching state doesn't match "
  "function 'profile-checksum-mismatch' attribute.");
+ (void)LTOPhase;
  // The desc for import function is unavailable. Check the function attribute
  // for mismatch.
  return (!Desc && !F.hasFnAttribute("profile-checksum-mismatch")) ||

diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -1000,7 +1000,7 @@ class RISCVTargetLowering : public TargetLowering {
  /// RISC-V doesn't have flags so it's better to perform the and/or in a GPR.
  bool shouldNormalizeToSelectSequence(LLVMContext &, EVT) const override {
  return false;
- };
+ }
 
  /// For available scheduling models FDIV + two independent FMULs are much
  /// faster than two FDIVs.