RISCV-Processor-ASIC

Author: Soham Kapur
Description: ASIC Implementation of a 4-Stage Pipelined 32-bit RISC-V Processor

Abstract:
RISC-V is an open instruction set architecture (ISA) developed at University of California, Berkeley. It is meant to support various extensions for customization. Building a processor from scratch is a tedious and time-taking task which makes it difficult for beginners in the field of digital hardware development to start out with learning the intricacies of processor design. The following project aims to develop a basic bare-bones processor which is useful for educationists and researchers to start out with a ready template. It follows a synchronous pipelined structure to implement 32-bit RISC-V ISA with simple arithmetic operations, created using Verilog HDL. This design can be tested, optimized, modified or customized to suit the needs of the user. It is also useful as a learning material to visualize and understand the broad steps that make a processor function. It is intended to be open source so as to reach a wider audience.

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