ArcheV

RISC-V RV-32i RTL Benchmark for evaluating Large Language Models developed by merledu

Name		Name	Last commit message	Last commit date
Latest commit History 22 Commits
.github/workflows		.github/workflows
.vscode		.vscode
backend/functional verification/verilog_2		backend/functional verification/verilog_2
frontend/web		frontend/web
functional_verification		functional_verification
project		project
rtl		rtl
src		src
syntactical_analysis		syntactical_analysis
.gitignore		.gitignore
FetchUnit10.sv		FetchUnit10.sv
README.md		README.md
__init__.py		__init__.py
build.sbt		build.sbt
build.sc		build.sc
checklist.md		checklist.md
emit_verilog.py		emit_verilog.py
integration.py		integration.py
main.py		main.py

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