From 49b3f9c20584913bba17fb276de9469f1d154e0b Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Wed, 17 Jul 2024 16:11:56 +0200 Subject: [PATCH] Add EmbeddedRiscvJtag noTap with tunnel support --- .../scala/vexriscv/plugin/EmbeddedRiscvJtag.scala | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/src/main/scala/vexriscv/plugin/EmbeddedRiscvJtag.scala b/src/main/scala/vexriscv/plugin/EmbeddedRiscvJtag.scala index 8a1c668e..2b17708d 100644 --- a/src/main/scala/vexriscv/plugin/EmbeddedRiscvJtag.scala +++ b/src/main/scala/vexriscv/plugin/EmbeddedRiscvJtag.scala @@ -15,7 +15,8 @@ import vexriscv._ class EmbeddedRiscvJtag(var p : DebugTransportModuleParameter, var debugCd : ClockDomain = null, var withTap : Boolean = true, - var withTunneling : Boolean = false + var withTunneling : Boolean = false, + var jtagCd : ClockDomain = null ) extends Plugin[VexRiscv] with VexRiscvRegressionArg{ @@ -69,6 +70,15 @@ class EmbeddedRiscvJtag(var p : DebugTransportModuleParameter, dm.io.ctrl <> logic.io.bus logic.io.jtag <> jtag } + val dmiDirectInstr = if (!withTap && withTunneling) new Area { + val logic = DebugTransportModuleTunneled( + p.copy(addressWidth = 7), + debugCd = ClockDomain.current, + jtagCd = jtagCd + ) + dm.io.ctrl <> logic.io.bus + logic.io.instruction <> jtagInstruction + } val privBus = pipeline.service(classOf[CsrPlugin]).debugBus.setAsDirectionLess() privBus <> dm.io.harts(0)