diff --git a/ext/NaxSoftware b/ext/NaxSoftware
index 469854d..054ca8a 160000
--- a/ext/NaxSoftware
+++ b/ext/NaxSoftware
@@ -1 +1 @@
-Subproject commit 469854dae119072f4377b89798c2fe9d7076bb50
+Subproject commit 054ca8a9d21fbb3b76f33ee13f20bdd022675b52
diff --git a/src/main/scala/vexiiriscv/fetch/PcPlugin.scala b/src/main/scala/vexiiriscv/fetch/PcPlugin.scala
index 0d08e2c..814f697 100644
--- a/src/main/scala/vexiiriscv/fetch/PcPlugin.scala
+++ b/src/main/scala/vexiiriscv/fetch/PcPlugin.scala
@@ -50,7 +50,8 @@ class PcPlugin(var resetVector : BigInt = 0x80000000l) extends FiberPlugin with
       val self = new Area {
         val id = Reg(Fetch.ID) init(0)
         val flow = newJumpInterface(-1, laneAgeWidth = 0, aggregationPriority = 0)
-        val increment, fault = RegInit(False)
+        val increment = RegInit(False)
+        val fault = RegInit(False) simPublic()
         val state = Reg(PC) init (resetVector) simPublic()
         val pc = state + U(WORD_BYTES).andMask(increment)
         flow.valid := True
diff --git a/src/main/scala/vexiiriscv/memory/MmuPlugin.scala b/src/main/scala/vexiiriscv/memory/MmuPlugin.scala
index fa1f794..27550dd 100644
--- a/src/main/scala/vexiiriscv/memory/MmuPlugin.scala
+++ b/src/main/scala/vexiiriscv/memory/MmuPlugin.scala
@@ -162,7 +162,7 @@ class MmuPlugin(var spec : MmuSpec,
 
     PHYSICAL_WIDTH.set(physicalWidth)
     VIRTUAL_WIDTH.set(spec.virtualWidth)
-    MIXED_WIDTH.set(VIRTUAL_WIDTH.get + (VIRTUAL_WIDTH < XLEN).toInt)
+    MIXED_WIDTH.set(VIRTUAL_WIDTH.get)
     PC_WIDTH.set(MIXED_WIDTH)
     TVAL_WIDTH.set(MIXED_WIDTH)
     assert(VIRTUAL_WIDTH.get == XLEN.get || XLEN.get > VIRTUAL_WIDTH.get && VIRTUAL_WIDTH.get > physicalWidth)