diff --git a/src/main/scala/vexiiriscv/execute/BranchPlugin.scala b/src/main/scala/vexiiriscv/execute/BranchPlugin.scala
index 12aeec36..8557995e 100644
--- a/src/main/scala/vexiiriscv/execute/BranchPlugin.scala
+++ b/src/main/scala/vexiiriscv/execute/BranchPlugin.scala
@@ -33,7 +33,7 @@ object BranchPlugin extends AreaObject {
 class PcCalc(bp: BranchPlugin, at: Int) extends Area {
   import bp._
   import BranchPlugin._
-  val ctrl = bp.layer.el.execute(at)
+  val ctrl = bp.layer.lane.execute(at)
   import ctrl._
 
   val srcp = host.find[SrcPlugin](_.layer == layer)
@@ -74,7 +74,7 @@ class BranchPlugin(val layer : LaneLayer,
   def catchMissaligned = !Riscv.RVC
   override def getLearnPort(): Option[Stream[LearnCmd]] = logic.jumpLogic.learn
 
-  def pluginsOnLane = host.list[BranchPlugin].filter(_.layer.el == layer.el)
+  def pluginsOnLane = host.list[BranchPlugin].filter(_.layer.lane == layer.lane)
   val pcCalc : Handle[PcCalc] = during build {
     // So, here we look for other branchplugins on the same lane to try reusing their calculation (better for fmax / LUT, cost some FF)
     val firstOfLane = pluginsOnLane.sortBy(_.jumpAt).head
@@ -86,7 +86,7 @@ class BranchPlugin(val layer : LaneLayer,
   }
 
   val logic = during setup new Logic{
-    val wbp = host.find[WriteBackPlugin](p => p.lane == layer.el && p.rf == IntRegFile)
+    val wbp = host.find[WriteBackPlugin](p => p.lane == layer.lane && p.rf == IntRegFile)
     val sp = host[ReschedulePlugin]
     val pcp = host[PcPlugin]
     val hp = host.get[HistoryPlugin]
diff --git a/src/main/scala/vexiiriscv/execute/CsrAccessPlugin.scala b/src/main/scala/vexiiriscv/execute/CsrAccessPlugin.scala
index 4154300b..cef2a245 100644
--- a/src/main/scala/vexiiriscv/execute/CsrAccessPlugin.scala
+++ b/src/main/scala/vexiiriscv/execute/CsrAccessPlugin.scala
@@ -42,7 +42,7 @@ class CsrAccessPlugin(val layer : LaneLayer,
   val logic = during setup new Area {
     val elp = host.find[ExecuteLanePlugin](_.laneName == layer.laneName)
     val irf = host.find[RegfileService](_.rfSpec == IntRegFile)
-    val iwb = host.find[IntFormatPlugin](_.lane == layer.el)
+    val iwb = host.find[IntFormatPlugin](_.lane == layer.lane)
     val dp = host[DispatchPlugin]
     val ram = host.get[CsrRamService]
     val sp = host[ReschedulePlugin]
@@ -77,7 +77,7 @@ class CsrAccessPlugin(val layer : LaneLayer,
       op.addRsSpec(RS1, injectAt)
     }
 
-    val age = layer.el.getExecuteAge(injectAt)
+    val age = layer.lane.getExecuteAge(injectAt)
     val flushPort = sp.newFlushPort(age, laneAgeWidth = Execute.LANE_AGE_WIDTH, withUopId = true)
     val trapPort = ts.newTrap(age, Execute.LANE_AGE_WIDTH)
 
diff --git a/src/main/scala/vexiiriscv/execute/ExecutionUnitElementSimple.scala b/src/main/scala/vexiiriscv/execute/ExecutionUnitElementSimple.scala
index 33438d4f..8ad59288 100644
--- a/src/main/scala/vexiiriscv/execute/ExecutionUnitElementSimple.scala
+++ b/src/main/scala/vexiiriscv/execute/ExecutionUnitElementSimple.scala
@@ -71,9 +71,9 @@ abstract class ExecutionUnitElementSimple(layer : LaneLayer) extends FiberPlugin
   val SEL = Payload(Bool())
 
   class Logic extends ExecuteUnitElementSimple.Api(layer,  host.find[SrcPlugin](_.layer == layer), SEL, rsUnsignedPlugin = host.get[RsUnsignedPlugin].getOrElse(null)) with Area with PostInitCallback {
-    val el = layer.el
+    val el = layer.lane
     val srcp = srcPlugin
-    val ifp = host.find[IntFormatPlugin](_.lane == layer.el)
+    val ifp = host.find[IntFormatPlugin](_.lane == layer.lane)
     val uopRetainer = retains(el.uopLock, srcp.elaborationLock, ifp.elaborationLock)
     val euPipelineRetainer = retains(el.pipelineLock)
 
diff --git a/src/main/scala/vexiiriscv/execute/Service.scala b/src/main/scala/vexiiriscv/execute/Service.scala
index f4b0aa3d..82ccf656 100644
--- a/src/main/scala/vexiiriscv/execute/Service.scala
+++ b/src/main/scala/vexiiriscv/execute/Service.scala
@@ -23,13 +23,13 @@ case class RsSpec(rs : RfRead){
   var from = 0
 }
 
-class LaneLayer(val name : String, val el : ExecuteLaneService, var priority : Int){
+class LaneLayer(val name : String, val lane : ExecuteLaneService, var priority : Int){
   val uops = mutable.LinkedHashMap[MicroOp, UopLayerSpec]()
-  el.add(this)
+  lane.add(this)
 
   def apply(uop: MicroOp) = uops(uop)
-  def add(uop: MicroOp) = uops.getOrElseUpdate(uop, new UopLayerSpec(uop, this, el))
-  def laneName = el.laneName
+  def add(uop: MicroOp) = uops.getOrElseUpdate(uop, new UopLayerSpec(uop, this, lane))
+  def laneName = lane.laneName
   def getRsUseAtMin(): Int = {
     uops.flatMap(_._2.rs.map(_._2.from)).fold(100)(_ min _)
   }
@@ -37,7 +37,7 @@ class LaneLayer(val name : String, val el : ExecuteLaneService, var priority : I
   def doChecks(): Unit = {
     for(uop <- uops.values) uop.doCheck()
   }
-  class Execute(id: Int) extends CtrlLaneMirror(el.execute(id))
+  class Execute(id: Int) extends CtrlLaneMirror(lane.execute(id))
 }
 
 class UopLayerSpec(val uop: MicroOp, val elImpl : LaneLayer, val el : ExecuteLaneService) {
diff --git a/src/main/scala/vexiiriscv/execute/SimdAddRawPlugin.scala b/src/main/scala/vexiiriscv/execute/SimdAddRawPlugin.scala
index fd46f9a7..15357859 100644
--- a/src/main/scala/vexiiriscv/execute/SimdAddRawPlugin.scala
+++ b/src/main/scala/vexiiriscv/execute/SimdAddRawPlugin.scala
@@ -21,9 +21,9 @@ object SimdAddRaw{
 class SimdAddRawPlugin(val layer : LaneLayer) extends FiberPlugin  {
   import SimdAddRaw._
   val logic = during setup new Area {
-    val wbp = host.find[WriteBackPlugin](p => p.rf == IntRegFile && p.lane == layer.el)
-    val earlyLock = retains(layer.el.uopLock, wbp.elaborationLock)
-    val lateLock = retains(layer.el.pipelineLock)
+    val wbp = host.find[WriteBackPlugin](p => p.rf == IntRegFile && p.lane == layer.lane)
+    val earlyLock = retains(layer.lane.uopLock, wbp.elaborationLock)
+    val lateLock = retains(layer.lane.pipelineLock)
     awaitBuild()
 
     val add4 = layer.add(ADD4)
@@ -39,7 +39,7 @@ class SimdAddRawPlugin(val layer : LaneLayer) extends FiberPlugin  {
     wbp.addMicroOp(wb, add4)
 
     val SEL = Payload(Bool())
-    layer.el.setDecodingDefault(SEL, False)
+    layer.lane.setDecodingDefault(SEL, False)
     add4.addDecoding(SEL -> True)
 
     earlyLock.release()
@@ -47,8 +47,8 @@ class SimdAddRawPlugin(val layer : LaneLayer) extends FiberPlugin  {
     //Let's define some logic in the execute lane [0]
     val process = new layer.Execute(id = 0) {
       //Get the RISC-V RS1/RS2 values from the register file
-      val rs1 = layer.el(IntRegFile, RS1).asUInt
-      val rs2 = layer.el(IntRegFile, RS2).asUInt
+      val rs1 = layer.lane(IntRegFile, RS1).asUInt
+      val rs2 = layer.lane(IntRegFile, RS2).asUInt
 
       //Do some computation
       val rd = UInt(32 bits)
diff --git a/src/main/scala/vexiiriscv/execute/fpu/FpuAddPlugin.scala b/src/main/scala/vexiiriscv/execute/fpu/FpuAddPlugin.scala
index c0857912..9e07fd8a 100644
--- a/src/main/scala/vexiiriscv/execute/fpu/FpuAddPlugin.scala
+++ b/src/main/scala/vexiiriscv/execute/fpu/FpuAddPlugin.scala
@@ -21,13 +21,13 @@ class FpuAddPlugin(val layer : LaneLayer,
   val logic = during setup new Area{
     val fup = host[FpuUnpackerPlugin]
     val fasp = host[FpuAddSharedPlugin]
-    val buildBefore = retains(layer.el.pipelineLock)
-    val uopLock = retains(layer.el.uopLock, fasp.elaborationLock, fup.elaborationLock)
+    val buildBefore = retains(layer.lane.pipelineLock)
+    val uopLock = retains(layer.lane.uopLock, fasp.elaborationLock, fup.elaborationLock)
     awaitBuild()
 
     val addPort = fasp.createPort(List(addAt), FpuUtils.unpackedConfig, FpuUtils.unpackedConfig)
 
-    layer.el.setDecodingDefault(SEL, False)
+    layer.lane.setDecodingDefault(SEL, False)
     def add(uop: MicroOp, decodings: (Payload[_ <: BaseType], Any)*) = {
       val spec = layer.add(uop)
       spec.addDecoding(SEL -> True)
diff --git a/src/main/scala/vexiiriscv/execute/fpu/FpuClassPlugin.scala b/src/main/scala/vexiiriscv/execute/fpu/FpuClassPlugin.scala
index 96d9a396..dee3e478 100644
--- a/src/main/scala/vexiiriscv/execute/fpu/FpuClassPlugin.scala
+++ b/src/main/scala/vexiiriscv/execute/fpu/FpuClassPlugin.scala
@@ -17,14 +17,14 @@ class FpuClassPlugin(val layer : LaneLayer, var wbAt : Int = 0) extends FiberPlu
 
   val logic = during setup new Area{
     val fup = host[FpuUnpackerPlugin]
-    val iwbp = host.find[IntFormatPlugin](p => p.lane == layer.el)
-    val buildBefore = retains(layer.el.pipelineLock)
-    val uopLock = retains(layer.el.uopLock, fup.elaborationLock, iwbp.elaborationLock)
+    val iwbp = host.find[IntFormatPlugin](p => p.lane == layer.lane)
+    val buildBefore = retains(layer.lane.pipelineLock)
+    val uopLock = retains(layer.lane.uopLock, fup.elaborationLock, iwbp.elaborationLock)
     awaitBuild()
 
     val iwb = iwbp.access(wbAt)
 
-    layer.el.setDecodingDefault(SEL, False)
+    layer.lane.setDecodingDefault(SEL, False)
     def add(uop: MicroOp, decodings: (Payload[_ <: BaseType], Any)*) = {
       val spec = layer.add(uop)
       spec.addDecoding(decodings)
diff --git a/src/main/scala/vexiiriscv/execute/fpu/FpuCmpPlugin.scala b/src/main/scala/vexiiriscv/execute/fpu/FpuCmpPlugin.scala
index d1ab8727..71e82ede 100644
--- a/src/main/scala/vexiiriscv/execute/fpu/FpuCmpPlugin.scala
+++ b/src/main/scala/vexiiriscv/execute/fpu/FpuCmpPlugin.scala
@@ -31,19 +31,19 @@ class FpuCmpPlugin(val layer : LaneLayer,
 
   val logic = during setup new Area{
     val fup = host[FpuUnpackerPlugin]
-    val fwbp = host.find[WriteBackPlugin](p => p.lane == layer.el && p.rf == FloatRegFile)
-    val iwbp = host.find[IntFormatPlugin](p => p.lane == layer.el)
-    val ffwbp = host.find[FpuFlagsWritebackPlugin](p => p.lane == layer.el)
-    val buildBefore = retains(layer.el.pipelineLock)
-    val uopLock = retains(layer.el.uopLock, fup.elaborationLock, fwbp.elaborationLock, iwbp.elaborationLock, ffwbp.elaborationLock)
+    val fwbp = host.find[WriteBackPlugin](p => p.lane == layer.lane && p.rf == FloatRegFile)
+    val iwbp = host.find[IntFormatPlugin](p => p.lane == layer.lane)
+    val ffwbp = host.find[FpuFlagsWritebackPlugin](p => p.lane == layer.lane)
+    val buildBefore = retains(layer.lane.pipelineLock)
+    val uopLock = retains(layer.lane.uopLock, fup.elaborationLock, fwbp.elaborationLock, iwbp.elaborationLock, ffwbp.elaborationLock)
     awaitBuild()
 
     val ffwb = ffwbp.createPort(List(cmpAt))
     val fwb = fwbp.createPort(floatWbAt)
     val iwb = iwbp.access(intWbAt)
 
-    layer.el.setDecodingDefault(SEL_FLOAT, False)
-    layer.el.setDecodingDefault(SEL_CMP, False)
+    layer.lane.setDecodingDefault(SEL_FLOAT, False)
+    layer.lane.setDecodingDefault(SEL_CMP, False)
     def add(uop: MicroOp, decodings: (Payload[_ <: BaseType], Any)*) = {
       val spec = layer.add(uop)
       spec.addDecoding(decodings)
@@ -132,7 +132,7 @@ class FpuCmpPlugin(val layer : LaneLayer,
 
     val onFloatWb = new layer.Execute(floatWbAt) {
       fwb.valid := SEL_FLOAT
-      fwb.payload := (FLOAT_OP === FpuCmpFloatOp.MIN_MAX && onCmp.MIN_MAX_RS2).mux(up(layer.el(FloatRegFile, RS2)), up(layer.el(FloatRegFile, RS1)))
+      fwb.payload := (FLOAT_OP === FpuCmpFloatOp.MIN_MAX && onCmp.MIN_MAX_RS2).mux(up(layer.lane(FloatRegFile, RS2)), up(layer.lane(FloatRegFile, RS1)))
       val doNan = RS1_FP.isNan && RS2_FP.isNan && FLOAT_OP === FpuCmpFloatOp.MIN_MAX
       val wb = fwb.payload
       when(doNan) {
diff --git a/src/main/scala/vexiiriscv/execute/fpu/FpuDivPlugin.scala b/src/main/scala/vexiiriscv/execute/fpu/FpuDivPlugin.scala
index a2124330..f35c5e1a 100644
--- a/src/main/scala/vexiiriscv/execute/fpu/FpuDivPlugin.scala
+++ b/src/main/scala/vexiiriscv/execute/fpu/FpuDivPlugin.scala
@@ -20,8 +20,8 @@ class FpuDivPlugin(val layer : LaneLayer,
     val fup = host[FpuUnpackerPlugin]
     val fpp = host[FpuPackerPlugin]
     val dr  = host[DivReuse]
-    val buildBefore = retains(layer.el.pipelineLock)
-    val uopLock = retains(layer.el.uopLock, fup.elaborationLock, fpp.elaborationLock)
+    val buildBefore = retains(layer.lane.pipelineLock)
+    val uopLock = retains(layer.lane.uopLock, fup.elaborationLock, fpp.elaborationLock)
     awaitBuild()
 
     val packParam = FloatUnpackedParam(
@@ -31,7 +31,7 @@ class FpuDivPlugin(val layer : LaneLayer,
     )
     val packPort = fpp.createPort(List(exeAt), packParam)
 
-    layer.el.setDecodingDefault(SEL, False)
+    layer.lane.setDecodingDefault(SEL, False)
     def add(uop: MicroOp, decodings: (Payload[_ <: BaseType], Any)*) = {
       val spec = layer.add(uop)
       spec.addDecoding(SEL -> True)
diff --git a/src/main/scala/vexiiriscv/execute/fpu/FpuF2iPlugin.scala b/src/main/scala/vexiiriscv/execute/fpu/FpuF2iPlugin.scala
index 5a56a1b0..535461b6 100644
--- a/src/main/scala/vexiiriscv/execute/fpu/FpuF2iPlugin.scala
+++ b/src/main/scala/vexiiriscv/execute/fpu/FpuF2iPlugin.scala
@@ -26,16 +26,16 @@ class FpuF2iPlugin(val layer : LaneLayer,
 
   val logic = during setup new Area{
     val fup = host[FpuUnpackerPlugin]
-    val iwbp = host.find[IntFormatPlugin](p => p.lane == layer.el)
-    val ffwbp = host.find[FpuFlagsWritebackPlugin](p => p.lane == layer.el)
-    val buildBefore = retains(layer.el.pipelineLock)
-    val uopLock = retains(layer.el.uopLock, fup.elaborationLock, iwbp.elaborationLock, ffwbp.elaborationLock)
+    val iwbp = host.find[IntFormatPlugin](p => p.lane == layer.lane)
+    val ffwbp = host.find[FpuFlagsWritebackPlugin](p => p.lane == layer.lane)
+    val buildBefore = retains(layer.lane.pipelineLock)
+    val uopLock = retains(layer.lane.uopLock, fup.elaborationLock, iwbp.elaborationLock, ffwbp.elaborationLock)
     awaitBuild()
 
     val ffwb = ffwbp.createPort(List(intWbAt))
     val iwb = iwbp.access(intWbAt)
 
-    layer.el.setDecodingDefault(SEL, False)
+    layer.lane.setDecodingDefault(SEL, False)
     def f2i(uop: MicroOp, size : Int, decodings: (Payload[_ <: BaseType], Any)*) = {
       val spec = layer.add(uop)
       spec.addDecoding(decodings)
@@ -105,9 +105,9 @@ class FpuF2iPlugin(val layer : LaneLayer,
       val round = low.msb ## low.dropHigh(1).orR
 
       val halfRater = halfRate generate new Area {
-        val firstCycle = RegNext(!layer.el.isFreezed()) init (True)
+        val firstCycle = RegNext(!layer.lane.isFreezed()) init (True)
         val freezeIt = isValid && SEL && firstCycle
-        layer.el.freezeWhen(freezeIt)
+        layer.lane.freezeWhen(freezeIt)
       }
 
       val inverter = Delay(Mux(onShift.resign, ~unsigned, unsigned) + onShift.incrementPatched, halfRate.toInt)
diff --git a/src/main/scala/vexiiriscv/execute/fpu/FpuMulPlugin.scala b/src/main/scala/vexiiriscv/execute/fpu/FpuMulPlugin.scala
index 3ec233be..2bcac205 100644
--- a/src/main/scala/vexiiriscv/execute/fpu/FpuMulPlugin.scala
+++ b/src/main/scala/vexiiriscv/execute/fpu/FpuMulPlugin.scala
@@ -29,8 +29,8 @@ class FpuMulPlugin(val layer : LaneLayer,
     val fpp = host[FpuPackerPlugin]
     val fasp = host[FpuAddSharedPlugin]
     val mp  = host[MulReuse]
-    val buildBefore = retains(layer.el.pipelineLock)
-    val uopLock = retains(layer.el.uopLock, fup.elaborationLock, fpp.elaborationLock)
+    val buildBefore = retains(layer.lane.pipelineLock)
+    val uopLock = retains(layer.lane.uopLock, fup.elaborationLock, fpp.elaborationLock)
     awaitBuild()
 
     val packParam = FloatUnpackedParam(
@@ -49,7 +49,7 @@ class FpuMulPlugin(val layer : LaneLayer,
     val addPort = withFma generate fasp.createPort(List(packAt), addParam, FpuUtils.unpackedConfig)
 
 
-    layer.el.setDecodingDefault(SEL, False)
+    layer.lane.setDecodingDefault(SEL, False)
     def add(uop: MicroOp, decodings: (Payload[_ <: BaseType], Any)*) = {
       val spec = layer.add(uop)
       spec.addDecoding(SEL -> True)
@@ -134,7 +134,7 @@ class FpuMulPlugin(val layer : LaneLayer,
     }
     import norm._
 
-    val onPack = new layer.el.Execute(packAt) {
+    val onPack = new layer.lane.Execute(packAt) {
       val nv = False
 
       val mode = FloatMode.NORMAL()
diff --git a/src/main/scala/vexiiriscv/execute/fpu/FpuMvPlugin.scala b/src/main/scala/vexiiriscv/execute/fpu/FpuMvPlugin.scala
index fc571899..c94a0feb 100644
--- a/src/main/scala/vexiiriscv/execute/fpu/FpuMvPlugin.scala
+++ b/src/main/scala/vexiiriscv/execute/fpu/FpuMvPlugin.scala
@@ -20,17 +20,17 @@ class FpuMvPlugin(val layer : LaneLayer,
   val SEL_INT = Payload(Bool())
 
   val logic = during setup new Area{
-    val fwbp = host.find[WriteBackPlugin](p => p.lane == layer.el && p.rf == FloatRegFile)
-    val iwbp = host.find[IntFormatPlugin](p => p.lane == layer.el)
-    val buildBefore = retains(layer.el.pipelineLock)
-    val uopLock = retains(layer.el.uopLock, fwbp.elaborationLock, iwbp.elaborationLock)
+    val fwbp = host.find[WriteBackPlugin](p => p.lane == layer.lane && p.rf == FloatRegFile)
+    val iwbp = host.find[IntFormatPlugin](p => p.lane == layer.lane)
+    val buildBefore = retains(layer.lane.pipelineLock)
+    val uopLock = retains(layer.lane.uopLock, fwbp.elaborationLock, iwbp.elaborationLock)
     awaitBuild()
 
     val fwb = fwbp.createPort(floatWbAt)
     val iwb = iwbp.access(intWbAt)
 
-    layer.el.setDecodingDefault(SEL_FLOAT, False)
-    layer.el.setDecodingDefault(SEL_INT, False)
+    layer.lane.setDecodingDefault(SEL_FLOAT, False)
+    layer.lane.setDecodingDefault(SEL_INT, False)
     def add(uop: MicroOp, decodings: (Payload[_ <: BaseType], Any)*) = {
       val spec = layer.add(uop)
       spec.addDecoding(decodings)
@@ -63,14 +63,14 @@ class FpuMvPlugin(val layer : LaneLayer,
 
     val onIntWb = new layer.Execute(intWbAt) {
       iwb.valid   := SEL_INT
-      iwb.payload := up(layer.el(FloatRegFile, RS1)).resized
+      iwb.payload := up(layer.lane(FloatRegFile, RS1)).resized
     }
 
     val onFloatWb = new layer.Execute(floatWbAt) {
       fwb.valid := SEL_FLOAT
-      fwb.payload(31 downto 0) := up(layer.el(IntRegFile, RS1))(31 downto 0)
+      fwb.payload(31 downto 0) := up(layer.lane(IntRegFile, RS1))(31 downto 0)
       if(Riscv.RVD.get) {
-        fwb.payload(63 downto 32) := muxDouble(FORMAT)(up(layer.el(IntRegFile, RS1))(63 downto 32))(B"xFFFFFFFF")
+        fwb.payload(63 downto 32) := muxDouble(FORMAT)(up(layer.lane(IntRegFile, RS1))(63 downto 32))(B"xFFFFFFFF")
       }
     }
 
diff --git a/src/main/scala/vexiiriscv/execute/fpu/FpuSqrtPlugin.scala b/src/main/scala/vexiiriscv/execute/fpu/FpuSqrtPlugin.scala
index 6266ef21..1cb4ff89 100644
--- a/src/main/scala/vexiiriscv/execute/fpu/FpuSqrtPlugin.scala
+++ b/src/main/scala/vexiiriscv/execute/fpu/FpuSqrtPlugin.scala
@@ -21,8 +21,8 @@ class FpuSqrtPlugin(val layer : LaneLayer,
     val fup = host[FpuUnpackerPlugin]
     val fpp = host[FpuPackerPlugin]
     val mp  = host[MulReuse]
-    val buildBefore = retains(layer.el.pipelineLock)
-    val uopLock = retains(layer.el.uopLock, fup.elaborationLock, fpp.elaborationLock)
+    val buildBefore = retains(layer.lane.pipelineLock)
+    val uopLock = retains(layer.lane.uopLock, fup.elaborationLock, fpp.elaborationLock)
     awaitBuild()
 
     val packParam = FloatUnpackedParam(
@@ -32,7 +32,7 @@ class FpuSqrtPlugin(val layer : LaneLayer,
     )
     val packPort = fpp.createPort(List(exeAt), packParam)
 
-    layer.el.setDecodingDefault(SEL, False)
+    layer.lane.setDecodingDefault(SEL, False)
     def add(uop: MicroOp, decodings: (Payload[_ <: BaseType], Any)*) = {
       val spec = layer.add(uop)
       spec.addDecoding(SEL -> True)
@@ -68,7 +68,7 @@ class FpuSqrtPlugin(val layer : LaneLayer,
 
       val unscheduleRequest = RegNext(isCancel) clearWhen (isReady) init (False)
       val freeze = isValid && SEL && !sqrt.io.output.valid & !unscheduleRequest
-      layer.el.freezeWhen(freeze)
+      layer.lane.freezeWhen(freeze)
 
       val exp = (RS1_FP.exponent >>| 1)
       val scrap = sqrt.io.output.remain =/= 0
diff --git a/src/main/scala/vexiiriscv/execute/fpu/FpuUnpackerPlugin.scala b/src/main/scala/vexiiriscv/execute/fpu/FpuUnpackerPlugin.scala
index a8baf920..57aab4a8 100644
--- a/src/main/scala/vexiiriscv/execute/fpu/FpuUnpackerPlugin.scala
+++ b/src/main/scala/vexiiriscv/execute/fpu/FpuUnpackerPlugin.scala
@@ -46,8 +46,8 @@ class FpuUnpackerPlugin(val layer : LaneLayer, unpackAt : Int = 0, packAt : Int
   val logic = during setup new Area{
     val fpp = host[FpuPackerPlugin]
     val rsUnsignedPlugin = host[RsUnsignedPlugin]
-    val buildBefore = retains(layer.el.pipelineLock)
-    val uopLock = retains(layer.el.uopLock, fpp.elaborationLock, rsUnsignedPlugin.elaborationLock)
+    val buildBefore = retains(layer.lane.pipelineLock)
+    val uopLock = retains(layer.lane.uopLock, fpp.elaborationLock, rsUnsignedPlugin.elaborationLock)
     awaitBuild()
 
     val packParam = FloatUnpackedParam(
@@ -59,7 +59,7 @@ class FpuUnpackerPlugin(val layer : LaneLayer, unpackAt : Int = 0, packAt : Int
 
     elaborationLock.await()
 
-    layer.el.setDecodingDefault(SEL_I2F, False)
+    layer.lane.setDecodingDefault(SEL_I2F, False)
     def i2f(uop: MicroOp, size: Int, signed : Boolean, decodings: (Payload[_ <: BaseType], Any)*) = {
       val spec = layer.add(uop)
       spec.addDecoding(decodings)
@@ -142,15 +142,15 @@ class FpuUnpackerPlugin(val layer : LaneLayer, unpackAt : Int = 0, packAt : Int
     }
 
 
-    val onUnpack = new layer.el.Execute(unpackAt){
+    val onUnpack = new layer.lane.Execute(unpackAt){
       val fsmPortId = 0
       val fsmCmd = unpacker.arbiter.io.inputs(fsmPortId)
       val fsmRsp = unpacker.results(fsmPortId)
       fsmCmd.setIdle()
 
-      val firstCycle = RegNext(False) setWhen(!layer.el.isFreezed())
+      val firstCycle = RegNext(False) setWhen(!layer.lane.isFreezed())
 
-      val rsValues = rsList.map(rs => this.up(layer.el(FloatRegFile, rs)))
+      val rsValues = rsList.map(rs => this.up(layer.lane(FloatRegFile, rs)))
 
       val fsmRequesters = Bits(rsList.size bits)
       val fsmServed = Bits(rsList.size bits)
@@ -222,7 +222,7 @@ class FpuUnpackerPlugin(val layer : LaneLayer, unpackAt : Int = 0, packAt : Int
         apply(RS) := RS_PRE_NORM
         val normalizer = new Area {
           val valid = unpackerSel && IS_SUBNORMAL
-          val validReg = RegNext(unpackerSel && IS_SUBNORMAL ) clearWhen(!layer.el.isFreezed()) init(False)
+          val validReg = RegNext(unpackerSel && IS_SUBNORMAL ) clearWhen(!layer.lane.isFreezed()) init(False)
           val asked = RegInit(False) setWhen (fsmRequesters(inputId) && !fsmRequesters.dropLow(inputId + 1).orR || isCancel) clearWhen (clear)
           val served = RegInit(False) setWhen (fsmRsp.valid && fsmServed.dropLow(inputId + 1).andR || isCancel) clearWhen (clear)
           fsmRequesters(inputId) := valid && !asked
@@ -244,7 +244,7 @@ class FpuUnpackerPlugin(val layer : LaneLayer, unpackAt : Int = 0, packAt : Int
             mantissa.raw := fsmRsp.data >> widthOf(fsmCmd.data) - widthOf(RS_PRE_NORM.mantissa.raw)
           }
           val freezeIt = validReg && !served || firstCycle && unpackerSel && expZero  //Maybe a bit hard on timings
-          layer.el.freezeWhen(freezeIt)
+          layer.lane.freezeWhen(freezeIt)
         }
 
         val badBoxing = p.rvd generate new Area {
@@ -260,8 +260,8 @@ class FpuUnpackerPlugin(val layer : LaneLayer, unpackAt : Int = 0, packAt : Int
     val unpackDone = !onUnpack.rs.map(_.normalizer.freezeIt).toList.orR
 
 
-    val onCvt = new layer.el.Execute(unpackAt){ //TODO fmax
-      val rs1 = up(layer.el(IntRegFile, RS1))
+    val onCvt = new layer.lane.Execute(unpackAt){ //TODO fmax
+      val rs1 = up(layer.lane(IntRegFile, RS1))
       val rs1Zero = Riscv.XLEN.get match {
         case 32 => rs1(31 downto 0) === 0
         case 64 => rs1(31 downto 0) === 0 && (RsUnsignedPlugin.IS_W || rs1(63 downto 32) === 0)
@@ -279,7 +279,7 @@ class FpuUnpackerPlugin(val layer : LaneLayer, unpackAt : Int = 0, packAt : Int
       fsmCmd.data := RsUnsignedPlugin.RS1_UNSIGNED.asBits.resized
 
       val freezeIt = isValid && SEL_I2F && !served
-      layer.el.freezeWhen(freezeIt)
+      layer.lane.freezeWhen(freezeIt)
 
       packPort.cmd.at(0) := isValid && SEL_I2F
       packPort.cmd.flags.clearAll()
diff --git a/src/main/scala/vexiiriscv/execute/fpu/FpuXxPlugin.scala b/src/main/scala/vexiiriscv/execute/fpu/FpuXxPlugin.scala
index e27d23f3..b362f4b7 100644
--- a/src/main/scala/vexiiriscv/execute/fpu/FpuXxPlugin.scala
+++ b/src/main/scala/vexiiriscv/execute/fpu/FpuXxPlugin.scala
@@ -20,8 +20,8 @@ class FpuXxPlugin(val layer : LaneLayer,
   val logic = during setup new Area{
     val fup = host[FpuUnpackerPlugin]
     val fpp = host[FpuPackerPlugin]
-    val buildBefore = retains(layer.el.pipelineLock)
-    val uopLock = retains(layer.el.uopLock, fup.elaborationLock, fpp.elaborationLock)
+    val buildBefore = retains(layer.lane.pipelineLock)
+    val uopLock = retains(layer.lane.uopLock, fup.elaborationLock, fpp.elaborationLock)
     awaitBuild()
 
     val packParam = FloatUnpackedParam(
@@ -31,7 +31,7 @@ class FpuXxPlugin(val layer : LaneLayer,
     )
     val packPort = fpp.createPort(List(packAt), packParam)
 
-    layer.el.setDecodingDefault(SEL, False)
+    layer.lane.setDecodingDefault(SEL, False)
     def add(uop: MicroOp, decodings: (Payload[_ <: BaseType], Any)*) = {
       val spec = layer.add(uop)
       spec.addDecoding(SEL -> True)
diff --git a/src/main/scala/vexiiriscv/execute/lsu/Agu.scala b/src/main/scala/vexiiriscv/execute/lsu/Agu.scala
index 09606ec0..0a94fb15 100644
--- a/src/main/scala/vexiiriscv/execute/lsu/Agu.scala
+++ b/src/main/scala/vexiiriscv/execute/lsu/Agu.scala
@@ -34,7 +34,7 @@ class AguFrontend(
   import AguPlugin._
   val sk = SrcKeys
 
-  layer.el.setDecodingDefault(SEL, False)
+  layer.lane.setDecodingDefault(SEL, False)
 
   val writingRf = ArrayBuffer[MicroOp](Rvi.LB, Rvi.LH, Rvi.LW, Rvi.LBU, Rvi.LHU)
   if (XLEN.get == 64) writingRf ++= List(Rvi.LD, Rvi.LWU)
diff --git a/src/main/scala/vexiiriscv/execute/lsu/LsuCachelessPlugin.scala b/src/main/scala/vexiiriscv/execute/lsu/LsuCachelessPlugin.scala
index 15c1c186..7bcd122a 100644
--- a/src/main/scala/vexiiriscv/execute/lsu/LsuCachelessPlugin.scala
+++ b/src/main/scala/vexiiriscv/execute/lsu/LsuCachelessPlugin.scala
@@ -50,8 +50,8 @@ class LsuCachelessPlugin(var layer : LaneLayer,
   )
 
   val logic = during setup new Area{
-    val elp = host.find[ExecuteLanePlugin](_ == layer.el)
-    val ifp = host.find[IntFormatPlugin](_.lane == layer.el)
+    val elp = host.find[ExecuteLanePlugin](_ == layer.lane)
+    val ifp = host.find[IntFormatPlugin](_.lane == layer.lane)
     val srcp = host.find[SrcPlugin](_.layer == layer)
     val ats = host[AddressTranslationService]
     val ts = host[TrapService]
@@ -65,8 +65,8 @@ class LsuCachelessPlugin(var layer : LaneLayer,
     val translationStorage = ats.newStorage(translationStorageParameter)
     atsStorageLock.release()
 
-    val trapPort = ts.newTrap(layer.el.getExecuteAge(forkAt), Execute.LANE_AGE_WIDTH)
-    val flushPort = ss.newFlushPort(layer.el.getExecuteAge(forkAt), laneAgeWidth = Execute.LANE_AGE_WIDTH, withUopId = true)
+    val trapPort = ts.newTrap(layer.lane.getExecuteAge(forkAt), Execute.LANE_AGE_WIDTH)
+    val flushPort = ss.newFlushPort(layer.lane.getExecuteAge(forkAt), laneAgeWidth = Execute.LANE_AGE_WIDTH, withUopId = true)
     val frontend = new AguFrontend(layer, host)
 
     // IntFormatPlugin specification
diff --git a/src/main/scala/vexiiriscv/execute/lsu/LsuPlugin.scala b/src/main/scala/vexiiriscv/execute/lsu/LsuPlugin.scala
index a74befdb..2d3e04b1 100644
--- a/src/main/scala/vexiiriscv/execute/lsu/LsuPlugin.scala
+++ b/src/main/scala/vexiiriscv/execute/lsu/LsuPlugin.scala
@@ -83,14 +83,14 @@ class LsuPlugin(var layer : LaneLayer,
   val logic = during setup new Area{
     assert(!(storeBufferSlots != 0 ^ storeBufferOps != 0))
     val withStoreBuffer = storeBufferSlots != 0
-    val elp = host.find[ExecuteLanePlugin](_ == layer.el)
-    val ifp = host.find[IntFormatPlugin](_.lane == layer.el)
+    val elp = host.find[ExecuteLanePlugin](_ == layer.lane)
+    val ifp = host.find[IntFormatPlugin](_.lane == layer.lane)
     val srcp = host.find[SrcPlugin](_.layer == layer)
     val ats = host[AddressTranslationService]
     val ts = host[TrapService]
     val ss = host[ScheduleService]
     val pcs = host.get[PerformanceCounterService]
-    val fpwbp = host.findOption[WriteBackPlugin](p => p.lane == layer.el && p.rf == FloatRegFile)
+    val fpwbp = host.findOption[WriteBackPlugin](p => p.lane == layer.lane && p.rf == FloatRegFile)
     val buildBefore = retains(elp.pipelineLock, ats.portsLock)
     val earlyLock = retains(List(ats.storageLock) ++ pcs.map(_.elaborationLock).toList)
     val retainer = retains(List(elp.uopLock, srcp.elaborationLock, ifp.elaborationLock, ts.trapLock, ss.elaborationLock) ++ fpwbp.map(_.elaborationLock))
@@ -107,8 +107,8 @@ class LsuPlugin(var layer : LaneLayer,
 
     earlyLock.release()
 
-    val trapPort = ts.newTrap(layer.el.getExecuteAge(ctrlAt), Execute.LANE_AGE_WIDTH)
-    val flushPort = ss.newFlushPort(layer.el.getExecuteAge(ctrlAt), laneAgeWidth = Execute.LANE_AGE_WIDTH, withUopId = true)
+    val trapPort = ts.newTrap(layer.lane.getExecuteAge(ctrlAt), Execute.LANE_AGE_WIDTH)
+    val flushPort = ss.newFlushPort(layer.lane.getExecuteAge(ctrlAt), laneAgeWidth = Execute.LANE_AGE_WIDTH, withUopId = true)
     val frontend = new AguFrontend(layer, host)
 
     // IntFormatPlugin specification
diff --git a/src/main/scala/vexiiriscv/schedule/DispatchPlugin.scala b/src/main/scala/vexiiriscv/schedule/DispatchPlugin.scala
index 8c2308a0..ff6711ba 100644
--- a/src/main/scala/vexiiriscv/schedule/DispatchPlugin.scala
+++ b/src/main/scala/vexiiriscv/schedule/DispatchPlugin.scala
@@ -233,7 +233,7 @@ class DispatchPlugin(var dispatchAt : Int,
             }
           }
           for(writeEu <- eus) {
-            val hazardFrom = ll.el.rfReadHazardFrom(ll.getRsUseAtMin()) // This is a pessimistic aproach
+            val hazardFrom = ll.lane.rfReadHazardFrom(ll.getRsUseAtMin()) // This is a pessimistic aproach
             val hazardUntil = writeEu.getRdBroadcastedFromMax()
             val hazardRange = hazardFrom until hazardUntil
             for(id <- hazardRange) {
@@ -254,7 +254,7 @@ class DispatchPlugin(var dispatchAt : Int,
           val checks = for ((otherLl, otherAts) <- resSpec.sels;
                             (otherAt, otherSel) <- otherAts;
                             delta = otherAt - selfAt; if delta > 0) yield new Area { //So currently we aren't trying to catch multi issue reservation being dispacthed at the same cycle (limitation)
-            val otherCtrl = otherLl.el.ctrl(delta)
+            val otherCtrl = otherLl.lane.ctrl(delta)
             val hit = c.ctx.hm(selfSel) && otherCtrl.isValid && otherCtrl(otherSel)
           }
         }
@@ -366,8 +366,8 @@ class DispatchPlugin(var dispatchAt : Int,
       eusFree(0).setAll()
       hartFree(0).setAll()
 
-      def eusToLayers(mask: Bits) = B(lanesLayers.map(ll => mask(eus.indexOf(ll.el))))
-      def layersToEus(mask: Bits) = B(eus.map(eu => lanesLayers.zipWithIndex.filter(_._1.el == eu).map(e => mask(e._2)).orR))
+      def eusToLayers(mask: Bits) = B(lanesLayers.map(ll => mask(eus.indexOf(ll.lane))))
+      def layersToEus(mask: Bits) = B(eus.map(eu => lanesLayers.zipWithIndex.filter(_._1.lane == eu).map(e => mask(e._2)).orR))
 
       val arbiters = for ((c, id) <- candidates.zipWithIndex) yield new Area {
         val olders = candidates.take(id)
@@ -405,7 +405,7 @@ class DispatchPlugin(var dispatchAt : Int,
       Global.COMPLETED := trap
 
       val layerOhUnfiltred = scheduler.arbiters.reader(oh)(_.layerOh) // include the bits of the other eu
-      val layersOfInterest = lanesLayers.zipWithIndex.filter(_._1.el == eu) // Only the bits for our eu  (LaneLayer -> Int
+      val layersOfInterest = lanesLayers.zipWithIndex.filter(_._1.lane == eu) // Only the bits for our eu  (LaneLayer -> Int
       val layer = layersOfInterest.map(e => B(eu.getLayerId(e._1), log2Up(eu.getLayers().size) bits) -> layerOhUnfiltred(e._2))
       eu.LAYER_SEL := OHMux.or(layer.map(_._2).asBits(), layer.map(_._1), true)
     }
diff --git a/src/main/scala/vexiiriscv/test/WhiteboxerPlugin.scala b/src/main/scala/vexiiriscv/test/WhiteboxerPlugin.scala
index 13ed5367..ce2bc1ab 100644
--- a/src/main/scala/vexiiriscv/test/WhiteboxerPlugin.scala
+++ b/src/main/scala/vexiiriscv/test/WhiteboxerPlugin.scala
@@ -139,7 +139,7 @@ class WhiteboxerPlugin extends FiberPlugin{
         uopId := c(Decode.UOP_ID)
         size := c(AguPlugin.SIZE).resized
         address := c(p.logic.tpk.TRANSLATED)
-        data := host.find[IntFormatPlugin](_.lane == p.layer.el).logic.stages.find(_.ctrlLink == c.ctrlLink).get.wb.payload
+        data := host.find[IntFormatPlugin](_.lane == p.layer.lane).logic.stages.find(_.ctrlLink == c.ctrlLink).get.wb.payload
       })
 
 
@@ -150,7 +150,7 @@ class WhiteboxerPlugin extends FiberPlugin{
         uopId := c(Decode.UOP_ID)
         size := c(AguPlugin.SIZE).resized
         address := c(LsuL1.PHYSICAL_ADDRESS)
-        data := host.find[IntFormatPlugin](_.lane == p.layer.el).logic.stages.find(_.ctrlLink == c.ctrlLink).get.wb.payload
+        data := host.find[IntFormatPlugin](_.lane == p.layer.lane).logic.stages.find(_.ctrlLink == c.ctrlLink).get.wb.payload
       })
     }