From c9bbb555ceea7428e50f8e643e5afdbff8dde233 Mon Sep 17 00:00:00 2001 From: ajayswar-s <139959004+ajayswar-s@users.noreply.github.com> Date: Fri, 25 Oct 2024 19:25:14 +0530 Subject: [PATCH] Sorting Registers in PE test-01 for print alignment (#374) Change-Id: If5bc9e734c66a9520a1e260e3bd344c5898384ce Signed-off-by: Ajayswar S --- test_pool/pe/operating_system/test_os_c001.c | 64 ++++++++++---------- 1 file changed, 32 insertions(+), 32 deletions(-) diff --git a/test_pool/pe/operating_system/test_os_c001.c b/test_pool/pe/operating_system/test_os_c001.c index 46e1be71..68186f7d 100644 --- a/test_pool/pe/operating_system/test_os_c001.c +++ b/test_pool/pe/operating_system/test_os_c001.c @@ -59,43 +59,43 @@ typedef struct{ pe_reg_info *g_pe_reg_info; reg_details reg_list[] = { - {CCSIDR_EL1, MASK_CCSIDR_LS, "CCSIDR_EL1", 0x0 }, - {MIDR_EL1, MASK_MIDR, "MIDR_EL1", 0x0 }, - {ID_AA64PFR0_EL1, 0x0, "ID_AA64PFR0_EL1" , 0x0 }, - {ID_AA64PFR1_EL1, 0x0, "ID_AA64PFR1_EL1" , 0x0 }, - {ID_AA64DFR0_EL1, 0x0, "ID_AA64DFR0_EL1" , 0x0 }, - {ID_AA64DFR1_EL1, 0x0, "ID_AA64DFR1_EL1" , 0x0 }, + {CCSIDR_EL1, MASK_CCSIDR_LS, "CCSIDR_EL1 ", 0x0 }, + {MIDR_EL1, MASK_MIDR, "MIDR_EL1 ", 0x0 }, + {MPIDR_EL1, MASK_MPIDR, "MPIDR_EL1 ", 0x0 }, + {CTR_EL0, MASK_CTR, "CTR_EL0 ", 0x0 }, + {ID_AA64PFR0_EL1, 0x0, "ID_AA64PFR0_EL1 ", 0x0 }, + {ID_AA64PFR1_EL1, 0x0, "ID_AA64PFR1_EL1 ", 0x0 }, + {ID_AA64DFR0_EL1, 0x0, "ID_AA64DFR0_EL1 ", 0x0 }, + {ID_AA64DFR1_EL1, 0x0, "ID_AA64DFR1_EL1 ", 0x0 }, {ID_AA64MMFR0_EL1, MASK_AA64MMFR0, "ID_AA64MMFR0_EL1", 0x0 }, {ID_AA64MMFR1_EL1, 0x0, "ID_AA64MMFR1_EL1", 0x0 }, {ID_AA64MMFR2_EL1, 0x0, "ID_AA64MMFR2_EL1", 0x0 }, - {CTR_EL0, MASK_CTR, "CTR_EL0" , 0x0 }, {ID_AA64ISAR0_EL1, 0x0, "ID_AA64ISAR0_EL1", 0x0 }, {ID_AA64ISAR1_EL1, 0x0, "ID_AA64ISAR1_EL1", 0x0 }, - {MPIDR_EL1, MASK_MPIDR, "MPIDR_EL1" , 0x0 }, - {ID_DFR0_EL1, 0x0, "ID_DFR0_EL1" , AA32}, - {ID_ISAR0_EL1, 0x0, "ID_ISAR0_EL1" , AA32}, - {ID_ISAR1_EL1, 0x0, "ID_ISAR1_EL1" , AA32}, - {ID_ISAR2_EL1, 0x0, "ID_ISAR2_EL1" , AA32}, - {ID_ISAR3_EL1, 0x0, "ID_ISAR3_EL1" , AA32}, - {ID_ISAR4_EL1, 0x0, "ID_ISAR4_EL1" , AA32}, - {ID_ISAR5_EL1, 0x0, "ID_ISAR5_EL1" , AA32}, - {ID_MMFR0_EL1, 0x0, "ID_MMFR0_EL1" , AA32}, - {ID_MMFR1_EL1, 0x0, "ID_MMFR1_EL1" , AA32}, - {ID_MMFR2_EL1, 0x0, "ID_MMFR2_EL1" , AA32}, - {ID_MMFR3_EL1, 0x0, "ID_MMFR3_EL1" , AA32}, - {ID_MMFR4_EL1, 0x0, "ID_MMFR4_EL1" , AA32}, - {ID_PFR0_EL1, 0x0, "ID_PFR0_EL1" , AA32}, - {ID_PFR1_EL1, 0x0, "ID_PFR1_EL1" , AA32}, - {MVFR0_EL1, 0x0, "MVFR0_EL1" , AA32}, - {MVFR1_EL1, 0x0, "MVFR1_EL1" , AA32}, - {MVFR2_EL1, 0x0, "MVFR2_EL1" , AA32}, - {PMCEID0_EL0, 0x0, "PMCEID0_EL0", PMUV3}, - {PMCEID1_EL0, 0x0, "PMCEID1_EL0", PMUV3}, - {PMCR_EL0, 0x0, "PMCR_EL0", PMUV3}, - {PMBIDR_EL1, 0x0, "PMBIDR_EL1" , SPE }, - {PMSIDR_EL1, 0x0, "PMSIDR_EL1" , SPE }, - {ERRIDR_EL1, 0x0, "ERRIDR_EL1" , RAS }, - {LORID_EL1, 0x0, "LORID_EL1" , LOR } + {PMCEID0_EL0, 0x0, "PMCEID0_EL0 ", PMUV3}, + {PMCEID1_EL0, 0x0, "PMCEID1_EL0 ", PMUV3}, + {PMCR_EL0, 0x0, "PMCR_EL0 ", PMUV3}, + {PMBIDR_EL1, 0x0, "PMBIDR_EL1 ", SPE }, + {PMSIDR_EL1, 0x0, "PMSIDR_EL1 ", SPE }, + {ERRIDR_EL1, 0x0, "ERRIDR_EL1 ", RAS }, + {LORID_EL1, 0x0, "LORID_EL1 ", LOR }, + {ID_DFR0_EL1, 0x0, "ID_DFR0_EL1 ", AA32}, + {ID_ISAR0_EL1, 0x0, "ID_ISAR0_EL1 ", AA32}, + {ID_ISAR1_EL1, 0x0, "ID_ISAR1_EL1 ", AA32}, + {ID_ISAR2_EL1, 0x0, "ID_ISAR2_EL1 ", AA32}, + {ID_ISAR3_EL1, 0x0, "ID_ISAR3_EL1 ", AA32}, + {ID_ISAR4_EL1, 0x0, "ID_ISAR4_EL1 ", AA32}, + {ID_ISAR5_EL1, 0x0, "ID_ISAR5_EL1 ", AA32}, + {ID_MMFR0_EL1, 0x0, "ID_MMFR0_EL1 ", AA32}, + {ID_MMFR1_EL1, 0x0, "ID_MMFR1_EL1 ", AA32}, + {ID_MMFR2_EL1, 0x0, "ID_MMFR2_EL1 ", AA32}, + {ID_MMFR3_EL1, 0x0, "ID_MMFR3_EL1 ", AA32}, + {ID_MMFR4_EL1, 0x0, "ID_MMFR4_EL1 ", AA32}, + {ID_PFR0_EL1, 0x0, "ID_PFR0_EL1 ", AA32}, + {ID_PFR1_EL1, 0x0, "ID_PFR1_EL1 ", AA32}, + {MVFR0_EL1, 0x0, "MVFR0_EL1 ", AA32}, + {MVFR1_EL1, 0x0, "MVFR1_EL1 ", AA32}, + {MVFR2_EL1, 0x0, "MVFR2_EL1 ", AA32} }; uint64_t