FPGA interchange development road map

[litghost]

Project page: https://github.com/orgs/SymbiFlow/projects/22

The implementation of the FPGA interchange as of YosysHQ@692d7dc and chipsalliance/python-fpga-interchange@b4331ef can place and route 7-series designs using single ended IO, FF's, LUT's and BRAM's for the most part. This issue covers the remaining work in different directions that the FPGA interchange development can take from here. I've broadly broken future work into 3 area's of work.

Improvement testing, robustness and speed

There is a lack of testing around some key portions of the FPGA interchange implementation. There is also some key performance issues that prevent the implementation from being particularly usable.

• Need to add Read the Docs build and initial documentation structure (Need to add Read the Docs build and initial documentation structure chipsalliance/fpga-interchange-schema#16)
• Investigate lookahead improvements (FPGA interchange lookahead improvements #260)
• Investigate BEL validity checking improvements (Investigate FPGA interchange BEL validity checking improvements #261)
• Need site routing test framework (Need site routing test framework #234)
• Improve YAML anchor names (Improve YAML anchor names chipsalliance/python-fpga-interchange#30)

Get FPGA interchange 7-series nextpnr implementation to feature parity with symbiflow-arch-defs

Many important features present in the symbiflow-arch-defs are missing from the currently FPGA interchange flow. Significant work remains to reach feature parity.

• Improve clock/PLL/MMCM placement (Fabric placement constraints #263)
• Need a FPGA interchange to FASM generator (Need a FPGA interchange to FASM generator chipsalliance/python-fpga-interchange#27)
  • Add kokoro runner for nextpnr to run diff FASM tests
• CARRY4/XORCY/MUXCY support (Test and implement CARRY4/XORCY/MUXCY support #262)
• LUT-RAM / Differential IO support (Implement primitive macro's  #264)
• Test SRL's and SRL chains (Test SRL's and SRL chains #265)
• Timing driven place and route (Need to define timing model data schema chipsalliance/fpga-interchange-schema#15)
• Start testing more circuits (some may be blocked by CARRY4/LUT-RAM implementations)

Get FPGA interchange nextpnr implementation to bigger fabrics and circuits

The current 7-series and other initial target architectures are limited to the 50k - 200k LUT range. To test with larger design, UltraScale+ (or other) fabrics will need to be supported. This category of work covers what is required to being to explore working with larger and larger fabrics, with the end goal of operating on the largest fabrics from Xilinx (VU19P) and other vendors.

• UltraScale+ bring-up (Ultra96 / UltraScale+ MPSoC ZU3EG) (Put link to issue here!)
• Improve node storage (Put link to issue here!)