1CX M.2 + NXP imx8mm: Can't get PCIe to initialize

[erikly01]

Hi,

I'm using the NXP imx8mm and getting pcie error messages during init. My goal is to get the Embedded Artist 1CX M.2 module up and running.

1. How do I begin to troubleshoot the issue?

2. Do we need an epdev_on regulator for pcie to work?

3. How does the ext_osc = <1> in the device tree relate to the message "pcie phy ppl can't be locked" dmesg

[    1.983047] imx6q-pcie 33800000.pcie: 33800000.pcie supply epdev_on not found, using dummy regulator
[    1.992612] OF: PCI: host bridge /pcie@0x33800000 ranges:
[    1.998031] OF: PCI:   No bus range found for /pcie@0x33800000, using [bus 00-ff]
[    2.005529] OF: PCI:    IO 0x1ff80000..0x1ff8ffff -> 0x00000000
[    2.011461] OF: PCI:   MEM 0x18000000..0x1fefffff -> 0x18000000
[    2.017844] imx6q-pcie 33800000.pcie: Initialize PHY with EXT REfCLK!.
[    2.024682] imx6q-pcie 33800000.pcie: PHY Initialization End!.
[    2.051619] imx6q-pcie 33800000.pcie: pcie phy pll can't be locked.
[    2.097900] imx6q-pcie 33800000.pcie: failed to initialize host
[    2.103825] imx6q-pcie 33800000.pcie: unable to add pcie port.

[richard-hu]

@erikly01

Thanks for your feedback.
Could you share the information about what is the SOM and baseboard you have?
(Because not all kinds of TechNexion i.mx8mm baseboard have PCIE signal on M.2 slot.)

BTW this repository qcacld-2.0 is only for TechNexion QCA9377-3/QCA6174 WLAN module.
Apparently, the WLAN module you use is not TechNexion QCA WLAN module.

Thanks~

BR,

Richard

[erikly01]

Hi Richard, We built our own board. I attached the device tree modifications that we are using. I noticed that we are missing a 32k external clock (I can also provide the PCIe schematic if necessary). I also have a few questions in regards to the error message below. 1. What does the "pcie supply epdev_on not found" mean, and will cause a pcie init failure? 2. Does "WL_REG_ON: disabling" occur because of the "failed to initialize host"? 3. Is there a way to get more verbose error messages or a pcie root complex dump? [ 1.985569] *imx6q-pcie 33800000.pcie: 33800000.pcie supply epdev_on not found, using dummy regulator* [ 1.994952] OF: PCI: host bridge /pcie@0x33800000 ranges: [ 2.000366] OF: PCI: No bus range found for /pcie@0x33800000, using [bus 00-ff] [ 2.007862] OF: PCI: IO 0x1ff80000..0x1ff8ffff -> 0x00000000 [ 2.013795] OF: PCI: MEM 0x18000000..0x1fefffff -> 0x18000000 [ 2.020164] imx6q-pcie 33800000.pcie: Initialize PHY with PLL REfCLK!. [ 2.027004] imx6q-pcie 33800000.pcie: PHY Initialization End!. [ 2.033166] imx6q-pcie 33800000.pcie: pcie phy pll is locked. [ 2.284060] *imx6q-pcie 33800000.pcie: phy link never came up* [ 2.289735] imx6q-pcie 33800000.pcie: failed to initialize host [ 2.295660] imx6q-pcie 33800000.pcie: unable to add pcie port. [ 2.302137] *imx6q-pcie: probe of 33800000.pcie failed with error -110* [ 2.328360] *WL_REG_ON: disabling* [ 2.331613] usb_otg_vbus: disabling [ 2.335126] backlight_pwr: disabling Thanks! *Erik Young, (m) 404-268-0945, erik.young@audink.com <erik.young@audink.com>* CEO, Co-Founder of Audink Inc. dba Audios This message and its contents are confidential. If you received this message in error, do not use or rely upon it. Instead, please inform the sender and then delete it. Thank you.

On Fri, Jun 19, 2020 at 4:41 AM Richard Hu ***@***.***> wrote: @erikly01 <https://github.com/erikly01> Thanks for your feedback. Could you share the information about what is the SOM and baseboard you have? (Because not all kinds of TechNexion i.mx8mm baseboard have PCIE signal on M.2 slot.) Thanks~ BR, Richard — You are receiving this because you were mentioned. Reply to this email directly, view it on GitHub <#1 (comment)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AF4X5PTOS5UKATLCFIS32TTRXMXFNANCNFSM4OBKPUFQ> .

/* * Copyright 2019 Audink Inc. * Copyright 2019 Audios * * Author: Erik Young <erik.young@audios.com> * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * as published by the Free Software Foundation; either version 2 * of the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ #include <dt-bindings/input/input.h> #include "imx8mm-pico-pi.dts" / { /*CODEC DAI driver*/ wm8524: wm8524 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_wm8524_mute>; compatible = "wlf,wm8524"; clocks = <&clk IMX8MM_CLK_SAI2_ROOT>; clock-names = "mclk"; wlf,mute-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; }; /*DAI Link driver*/ sound-wm8524 { compatible = "fsl,imx-audio-wm8524"; model = "wm8524-audio"; audio-cpu = <&sai2>; audio-codec = <&wm8524>; audio-routing = "Line Out Jack", "LINEVOUTL", "Line Out Jack", "LINEVOUTR"; }; }; /*CPU DAI driver*/ &sai2 { status = "okay"; }; &pcie0 { reset-gpio = <&gpio5 20 GPIO_ACTIVE_LOW>; ext_osc = <0>; status = "okay"; }; &bt_reg_on { reset-gpios = <&gpio3 7 GPIO_ACTIVE_LOW>; }; &wl_reg_on { gpio = <&gpio3 8 GPIO_ACTIVE_HIGH>; }; &iomuxc { imx8mm-pico { pinctrl_wm8524_mute: wm8524mutegrp { fsl,pins = < MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0xd6 ; }; pinctrl_pcie0: pcie0grp { fsl,pins = < MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x41 /* PCIE_nReset, PICO-NYMPH */ ; }; pinctrl_bt_ctrl: bt_ctrlgrp { fsl,pins = < MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x41 /* BT_REG_ON */ ; }; pinctrl_wifi_ctrl: wifi_ctrlgrp { fsl,pins = < MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x41 /* WL_REG_ON */ ; }; }; }; &pwm4 { status = "disabled"; }; &pwm1 { status = "disabled"; };