Making a small sample from scratch for learning

[vic4key]

Hi everybody,

I'm making a very small sample that called AND gate from scatch for leaning but I did sth wrong (failed at STEP 3).
Please help me, let me know what I did wrong.
I'm a newbie in this domain, so I'm sorry for my stupid questions.

My Expection:

• Write a verilog & constraint file
• Run several commands to create an .odb file for the Floorplan stage
• Load the .odb into OpenROAD GUI
• Find out the parameters, configurations, etc that required/using in the Floorplan stage

---

STEP 1. The verilog & constraint file which I wrote as the following:

The verilog file and_gate.v

module and_gate(input a, input b, output y);
  assign y = a & b;
endmodule

The constraint file and_gate.sdc

create_clock -period 10.0 [get_ports clk]

---

STEP 2. To create net-list, I used the yosys command yosys -p "read_verilog and_gate.v; synth -top and_gate; write_json and_gate.json"

A net-list file that named and_gate.json is created under the json file format.

Click here to see details

{
  "creator": "Yosys 0.13+15 (git sha1 bc027b2ca, gcc 11.3.0-1ubuntu1~22.04 -fPIC -Os)",
  "modules": {
    "and_gate": {
      "attributes": {
        "top": "00000000000000000000000000000001",
        "src": "and_gate.v:1.1-3.10"
      },
      "ports": {
        "a": {
          "direction": "input",
          "bits": [ 2 ]
        },
        "b": {
          "direction": "input",
          "bits": [ 3 ]
        },
        "c": {
          "direction": "output",
          "bits": [ 4 ]
        }
      },
      "cells": {
        "$abc$76$auto$blifparse.cc:381:parse_blif$77": {
          "hide_name": 1,
          "type": "$_AND_",
          "parameters": {
          },
          "attributes": {
          },
          "port_directions": {
            "A": "input",
            "B": "input",
            "Y": "output"
          },
          "connections": {
            "A": [ 3 ],
            "B": [ 2 ],
            "Y": [ 4 ]
          }
        }
      },
      "netnames": {
        "a": {
          "hide_name": 0,
          "bits": [ 2 ],
          "attributes": {
            "src": "and_gate.v:1.23-1.24"
          }
        },
        "b": {
          "hide_name": 0,
          "bits": [ 3 ],
          "attributes": {
            "src": "and_gate.v:1.32-1.33"
          }
        },
        "c": {
          "hide_name": 0,
          "bits": [ 4 ],
          "attributes": {
            "src": "and_gate.v:1.42-1.43"
          }
        }
      }
    }
  }
}

---

STEP 3. Trying to use openroad to do Floorplan (FAILED)

Make a results folder then set its path to the RESULTS_DIR variable for openroad use to store output files

$ mkdir results
$ set RESULTS_DIR results

After I ran read_design -json and_gate.json failed (missing read_design command), I tried read_verilog and_gate.v but it's still failed.

ubuntu@ubuntu-linux:~/Desktop/ic_test$ openroad -no_init
OpenROAD v2.0-6895-g5c85b36f8 
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
openroad> 
openroad> read_design -json and_gate.json
invalid command name "read_design"
while evaluating read_design -json and_gate.json
openroad> 
openroad> read_verilog and_gate.v
[ERROR STA-0164] and_gate.v line 2, syntax error
STA-0164
while evaluating read_verilog and_gate.v
openroad> 
openroad>

This is openroad help in my machine

Click here to see details

openroad> help
add_global_connection -net
add_pad [-name name] [-type type] [-cell library_cell] [-signal signal_name]
   [-edge edge] [-location location] [-bump rowcol]
   [-padcell_to_rdl list_of_vias] [-rdl_to_bump list_of_vias] [-bondpad bondpad]
   [-inst_name inst_name]
add_pdn_connect [-grid grid_name] -layers list_of_2_layers
   [-cut_pitch pitch_value] [-fixed_vias list_of_vias]
   [-dont_use_vias list_of_vias] [-max_rows rows] [-max_columns columns]
   [-ongrid ongrid_layers] [-split_cuts split_cuts_mapping]
add_pdn_ring [-grid grid_name] -layers list_of_2_layer_names -widths
add_pdn_stripe [-grid grid_name] -layer layer_name [-width width_value]
   [-followpins] [-extend_to_core_ring] [-pitch pitch_value]
   [-spacing spacing_value] [-offset offset_value]
   [-starts_width (POWER|GROUND)] [-extend_to_boundary] [-snap_to_grid]
   [-number_of_straps count] [-nets list_of_nets]
add_to_physical_cluster
   [-modinst path | -inst inst_name | -physical_cluster cluster_name]
   cluster_name
add_worker_address [-host host] [-port port]
adjust_rc [-res_factor res] [-cc_factor cc] [-gndc_factor gndc]
all_clocks
all_inputs
all_outputs
all_registers [-clock clocks] [-rise_clock clocks] [-fall_clock clocks] [-cells]
   [-data_pins] [-clock_pins] [-async_pins] [-output_pins] [-level_sensitive]
   [-edge_triggered]
analyze_power_grid [-vsrc vsrc_file ] [-outfile out_file] [-enable_em]
   [-em_outfile em_out_file] [-net net_name] [-dx bump_pitch_x]
   [-dy bump_pitch_y] [-node_density val_node_density]
   [-node_density_factor val_node_density_factor]
assign_ground_net -domain domain_name -net snet_name
assign_ndr -ndr name
assign_power_net -domain domain_name -net snet_name
bench_read_spef filename
bench_verilog filename
bench_wires [-met_cnt mcnt] [-cnt count] [-len wire_len] [-over] [-diag] [-all]
   [-db_only] [-under_met layer] [-w_list width] [-s_list space]
   [-over_dist dist] [-under_dist dist]
buffer_ports [-inputs] [-outputs] [-max_utilization util]
check_antennas [-verbose] [-report_file report_file] [-net net]
check_drc [-box box] [-output_file filename]
check_placement [-verbose]
check_power_grid [-net power_net]
check_setup [-verbose] [-no_input_delay] [-no_output_delay] [-multiple_clock]
   [-no_clock] [-unconstrained_endpoints] [-loops] [-generated_clocks]
   [> filename] [>> filename]
clear_global_connect
clock_tree_synthesis [-wire_unit unit] [-buf_list buflist] [-root_buf buf]
   [-clk_nets nets] [-tree_buf buf] [-distance_between_buffers]
   [-branching_point_buffers_distance] [-clustering_exponent]
   [-clustering_unbalance_ratio] [-sink_clustering_size]
   [-sink_clustering_max_diameter] [-sink_clustering_enable] [-balance_levels]
   [-sink_clustering_levels levels] [-num_static_layers]
   [-sink_clustering_buffer]
configure_cts_characterization [-max_cap cap] [-max_slew slew]
   [-slew_steps slew_steps] [-cap_steps cap_steps]
connect_pin net pin
connect_pins net pins
create_child_physical_clusters [-top_module | -modinst path]
create_clock [-name name] [-period period] [-waveform waveform] [-add]
   [-comment comment] [pins]
create_generated_clock [-name clock_name] -source master_pin
   [-master_clock clock] [-divide_by divisor | -multiply_by multiplier]
   [-duty_cycle duty_cycle] [-invert] [-edges edge_list]
   [-edge_shift edge_shift_list] [-combinational] [-add] [-comment comment]
   port_pin_list
create_logic_port [-direction direction] port_name
create_menu_item [-name name] -text item_text -script tcl_script
   [-path menu_path] [-shortcut key_shortcut] [-echo]
create_ndr -name name [-spacing val] [-width val] [-via val]
create_physical_cluster cluster_name
create_power_domain [-elements elements] name
create_power_switch [-domain domain] [-output_supply_port output_supply_port]
   [-input_supply_port input_supply_port] [-control_port control_port]
   [-on_state on_state] name
create_toolbar_button [-name name] -text button_text -script tcl_script [-echo]
create_voltage_area [-name name] [-coordinate coordinates]
   [-guard_band_x guard_x] [-guard_band_y guard_y] cells
create_voltage_domain domain_name -area
current_design [design]
current_instance [instance]
cut_rows [-endcap_master endcap_master] [-halo_width_x halo_x]
   [-halo_width_y halo_y]
define_corners corner1 [corner2]
define_pad_cell [-name name] [-type cell_type|-fill|-corner|-bondpad|-bump]
   [-cell_name cell_names_per_side] [-orient orientation_per_side]
   [-pad_pin_name pad_pin_name] [-break_signals signal_list]
   [-offset cell_offset] [-physical_only]
define_pdn_grid [-name <name>] [-macro] [-existing]
   [-grid_over_pg_pins|-grid_over_boundary]
   [-voltage_domains <list_of_voltage_domains>]
   [-orient <list_of_valid_orientations>] [-instances <list_of_instances>]
   [-cells <list_of_cell_names> ] [-default] [-halo <list_of_halo_values>]
   [-pins <list_of_pin_layers>] [-starts_with (POWER|GROUND)]
   [-obstructions <list_of_layers>] [-power_switch_cell <name>]
   [-power_control <signal_name>] [-power_control_network (STAR|DAISY)]
define_pin_shape_pattern [-layer layer] [-x_step x_step] [-y_step y_step]
   [-region region] [-size size] [-pin_keepout dist]
define_power_switch_cell -name
define_process_corner [-ext_model_index index] filename
delete_clock [-all] clocks
delete_from_list list objs
delete_generated_clock [-all] clocks
delete_instance inst
delete_net net
delete_physical_cluster cluster_name
delete_voltage_domain domain_name
density_fill [-rules rules_file] [-area {lx ly ux uy}]
detailed_placement [-max_displacement disp|{disp_x disp_y}]
detailed_route [-output_maze filename] [-output_drc filename]
   [-output_cmap filename] [-output_guide_coverage filename]
   [-db_process_node name] [-disable_via_gen] [-droute_end_iter iter]
   [-via_in_pin_bottom_layer layer] [-via_in_pin_top_layer layer]
   [-or_seed seed] [-or_k_ k] [-bottom_routing_layer layer]
   [-top_routing_layer layer] [-verbose level] [-param filename] [-distributed]
   [-remote_host rhost] [-remote_port rport] [-shared_volume vol]
   [-cloud_size sz] [-clean_patches] [-no_pin_access] [-min_access_points count]
   [-save_guide_updates] [-repair_pdn_vias layer]
detailed_route_debug [-pa] [-ta] [-dr] [-maze] [-net name] [-pin name]
   [-worker x y] [-iter iter] [-pa_markers] [-dump_dr] [-dump_dir dir]
   [-pa_edge] [-pa_commit]
detailed_route_run_worker [-dump_dir dir] [-worker_dir dir] [-drc_rpt drc]
detailed_route_worker_debug [-maze_end_iter iter] [-drc_cost d_cost]
   [-marker_cost m_cost] [-fixed_shape_cost f_cost] [-marker_decay m_decay]
   [-ripup_mode mode] [-follow_guide f_guide]
diff_spef [-file filename] [-r_res] [-r_cap] [-r_cc_cap] [-r_conn]
disconnect_pin net -all|pin
disconnect_pins net -all|pins
display_timing_cone pin [-fanin] [-fanout] [-off]
draw_route_guides net_names [-show_pin_locations]
elapsed_run_time
estimate_parasitics -placement|-global_routing
extract_parasitics [-ext_model_file filename] [-corner_cnt count]
   [-max_res ohms] [-coupling_threshold fF] [-debug_net_id id] [-lef_res]
   [-cc_model track] [-context_depth depth] [-no_merge_via_res]
filler_placement [-prefix prefix] filler_masters
find_timing_paths [-from from_list|-rise_from from_list|-fall_from from_list]
   [-through through_list|-rise_through through_list|-fall_through through_list]
   [-to to_list|-rise_to to_list|-fall_to to_list]
   [-path_delay min|min_rise|min_fall|max|max_rise|max_fall|min_max]
   [-unconstrained] [-corner corner] [-group_count path_count]
   [-endpoint_count path_count] [-unique_paths_to_endpoint]
   [-slack_max slack_max] [-slack_min slack_min] [-sort_by_slack]
   [-path_group group_name]
focus_net net [-remove] [-clear]
get_cells [-hierarchical] [-hsc separator] [-filter expr] [-regexp] [-nocase]
   [-quiet] [-of_objects objects] [patterns]
get_clocks [-regexp] [-nocase] [-quiet] patterns
get_fanin -to sink_list [-flat] [-only_cells] [-startpoints_only]
   [-levels level_count] [-pin_levels pin_count]
   [-trace_arcs timing|enabled|all]
get_fanout -from source_list [-flat] [-only_cells] [-endpoints_only]
   [-levels level_count] [-pin_levels pin_count]
   [-trace_arcs timing|enabled|all]
get_full_name objects
get_lib_cells [-hsc separator] [-regexp] [-nocase] [-quiet]
   [-of_objects objects] [patterns]
get_lib_pins [-hsc separator] [-regexp] [-nocase] [-quiet] patterns
get_libs [-regexp] [-nocase] [-quiet] patterns
get_name objects
get_nets [-hierarchical] [-hsc separator] [-regexp] [-nocase] [-quiet]
   [-of_objects objects] [patterns]
get_pins [-hierarchical] [-hsc separator] [-quiet] [-filter expr] [-regexp]
   [-nocase] [-of_objects objects] patterns
get_ports [-quiet] [-filter expr] [-regexp] [-nocase] [-of_objects objects]
   [patterns]
get_property [-object_type cell|pin|net|port|clock|timing_arc] object property
get_timing_edges [-from from_pin] [-to to_pin] [-of_objects objects]
   [-filter expr]
global_connect
global_placement [-skip_initial_place] [-skip_nesterov_place] [-timing_driven]
   [-routability_driven] [-disable_timing_driven] [-disable_routability_driven]
   [-incremental] [-force_cpu] [-skip_io] [-bin_grid_count grid_count]
   [-density target_density] [-init_density_penalty init_density_penalty]
   [-init_wirelength_coef init_wirelength_coef] [-min_phi_coef min_phi_coef]
   [-max_phi_coef max_phi_coef] [-reference_hpwl reference_hpwl]
   [-overflow overflow] [-initial_place_max_iter initial_place_max_iter]
   [-initial_place_max_fanout initial_place_max_fanout]
   [-routability_check_overflow routability_check_overflow]
   [-routability_max_density routability_max_density]
   [-routability_max_bloat_iter routability_max_bloat_iter]
   [-routability_max_inflation_iter routability_max_inflation_iter]
   [-routability_target_rc_metric routability_target_rc_metric]
   [-routability_inflation_ratio_coef routability_inflation_ratio_coef]
   [-routability_max_inflation_ratio routability_max_inflation_ratio]
   [-routability_rc_coefficients routability_rc_coefficients]
   [-timing_driven_net_reweight_overflow timing_driven_net_reweight_overflow]
   [-timing_driven_net_weight_max timing_driven_net_weight_max]
   [-timing_driven_nets_percentage timing_driven_nets_percentage]
   [-pad_left pad_left] [-pad_right pad_right]
global_route [-guide_file out_file] [-congestion_iterations iterations]
   [-congestion_report_file file_name] [-grid_origin origin]
   [-overflow_iterations iterations] [-critical_nets_percentage percent]
   [-allow_congestion] [-allow_overflow] [-verbose]
global_route_debug [-st]
group_path -name group_name [-weight weight] [-critical_range range] [-default]
   [-comment comment] [-from from_list] [-rise_from from_list]
   [-fall_from from_list] [-through through_list] [-rise_through through_list]
   [-fall_through through_list] [-to to_list] [-rise_to to_list]
   [-fall_to to_list]
help [pattern]
highlight_path [-min|-max] pin
improve_placement [-random_seed seed] [-max_displacement disp|{disp_x disp_y}]
initialize_floorplan [-utilization util] [-aspect_ratio ratio]
   [-core_space space | {bottom top left right}] [-die_area {lx ly ux uy}]
   [-core_area {lx ly ux uy}] [-site site_name]
initialize_padring [-signal_assignment_file signal_assigment_file]
insert_buffer buffer_name buffer_cell net load_pins buffer_out_net_name
insert_tiecells tie_pin [-prefix prefix]
link_design [top_cell_name]
log_begin filename
log_end
macro_placement [-halo {vertical_width horizontal_width}]
   [-channel {vertical_width horizontal_width}] [-fence_region {lx ly ux uy}]
   [-snap_layer snap_layer_number] [-style corner_max_wl|corner_min_wl]
macro_placement_debug [-partitions]
make_instance inst_path lib_cell
make_net
make_tracks [layer] [-x_pitch x_pitch] [-y_pitch y_pitch] [-x_offset x_offset]
   [-y_offset y_offset]
optimize_mirroring
pdngen [-skip_trim] [-dont_add_pins] [-reset] [-ripup] [-report_only]
   [-failed_via_report file]
pin_access [-db_process_node name] [-bottom_routing_layer layer]
   [-top_routing_layer layer] [-min_access_points count] [-verbose level]
place_cell -inst_name inst_name [-cell library_cell] -origin xy_origin -orient
place_pin [-pin_name pin_name] [-layer layer] [-location location]
   [-pin_size pin_size] [-force_to_die_boundary]
place_pins [-hor_layers h_layers] [-ver_layers v_layers] [-random_seed seed]
   [-random] [-corner_avoidance distance] [-min_distance min_dist]
   [-min_distance_in_tracks] [-exclude region] [-group_pins pin_list]
read_db filename
read_def [-floorplan_initialize|-incremental] [-continue_on_errors] filename
read_guides file_name
read_lef [-tech] [-library] filename
read_liberty [-corner corner] [-min] [-max] [-no_latch_infer] filename
read_parasitics [-min] [-max] [-elmore] [-path path] [-increment]
   [-pin_cap_included] [-keep_capacitive_coupling]
   [-coupling_reduction_factor factor] [-reduce_to pi_elmore|pi_pole_residue2]
   [-delete_after_reduce] [-quiet] [-save] filename
read_power_activities [-scope scope] -vcd filename
read_sdc [-echo] filename
read_sdf [-path path] [-corner corner] [-cond_use min|max|min_max]
   [-unescaped_dividers] filename
read_spef [-corner corner] [-min] [-max] [-path path] [-pin_cap_included]
   [-keep_capacitive_coupling] [-coupling_reduction_factor factor]
   [-reduce_to pi_elmore|pi_pole_residue2] [-delete_after_reduce] [-quiet]
   [-save] filename
read_upf [-file file]
read_verilog filename
remove_buffers
remove_fillers
remove_from_physical_cluster
   [-parent_module module_name -modinst modinst_name | -inst inst_name | -physical_cluster cluster_name]
   cluster_name
repair_antennas [diode_cell/diode_port] [-iterations iterations]
   [-ratio_margin ratio_margin]
repair_clock_inverters
repair_clock_nets [-max_wire_length max_wire_length]
repair_design [-max_wire_length max_wire_length] [-max_utilization util]
   [-slew_margin slack_margin] [-cap_margin cap_margin]
repair_pdn_vias [-net net_name] -all
repair_tie_fanout lib_port [-separation dist] [-verbose]
repair_timing [-setup] [-hold] [-setup_margin setup_margin]
   [-hold_margin hold_margin] [-allow_setup_violations]
   [-repair_tns tns_end_percent] [-max_buffer_percent buffer_percent]
   [-max_utilization util]
replace_cell instance lib_cell
report_annotated_check [-setup] [-hold] [-recovery] [-removal] [-nochange]
   [-width] [-period] [-max_skew] [-max_line lines] [-list_annotated]
   [-list_not_annotated] [-constant_arcs]
report_annotated_delay [-cell] [-net] [-from_in_ports] [-to_out_ports]
   [-max_line lines] [-list_annotated] [-list_not_annotated] [-constant_arcs]
report_arrival pin
report_cell [-connections] [-verbose] instance_path [> filename] [>> filename]
report_check_types [-violators] [-verbose] [-corner corner]
   [-format slack_only|end] [-max_delay] [-min_delay] [-recovery] [-removal]
   [-clock_gating_setup] [-clock_gating_hold] [-max_slew] [-min_slew]
   [-max_fanout] [-min_fanout] [-max_capacitance] [-min_capacitance]
   [-min_pulse_width] [-min_period] [-max_skew] [-net net] [-digits digits]
   [-no_line_splits] [> filename] [>> filename]
report_checks [-from from_list|-rise_from from_list|-fall_from from_list]
   [-through through_list|-rise_through through_list|-fall_through through_list]
   [-to to_list|-rise_to to_list|-fall_to to_list] [-unconstrained]
   [-path_delay min|min_rise|min_fall|max|max_rise|max_fall|min_max]
   [-corner corner] [-group_count path_count] [-endpoint_count path_count]
   [-unique_paths_to_endpoint] [-slack_max slack_max] [-slack_min slack_min]
   [-sort_by_slack] [-path_group group_name]
   [-format full|full_clock|full_clock_expanded|short|end|summary]
report_clock_min_period [-clocks clocks] [-include_port_paths]
report_clock_properties [clocks]
report_clock_skew [-setup|-hold] [-clock clocks] [-corner corner]]
   [-digits digits]
report_clock_skew_metric [-setup] | [-hold]
report_constant pin|instance|net
report_cts [-out_file file]
report_dcalc [-from from_pin] [-to to_pin] [-corner corner] [-min] [-max]
   [-digits digits]
report_design_area
report_design_area_metrics
report_disabled_edges
report_edges [-from from_pin] [-to to_pin]
report_erc_metrics
report_floating_nets [-verbose]
report_global_connect
report_instance [-connections] [-verbose] instance_path [> filename]
   [>> filename]
report_lib_cell cell_name [> filename] [>> filename]
report_long_wires count
report_net [-connections] [-verbose] [-corner corner] [-digits digits]
   [-hier_pins] net_path [> filename] [>> filename]
report_object_full_names objects
report_object_names objects
report_parasitic_annotation -report_unannotated
report_path [-min|-max]
   [-format full|full_clock|full_clock_expanded|short|end|summary]
report_physical_clusters
report_pin [-corner corner] [-digits digits] pin [> filename] [>> filename]
report_power [-instances instances] [-corner corner] [-digits digits]
   [> filename] [>> filename]
report_power_metric [-corner corner_name]
report_pulse_width_checks [-verbose] [-corner corner] [-digits digits]
   [-no_line_splits] [pins] [> filename] [>> filename]
report_required pin
report_slack pin
report_slews [-corner corner] pin
report_tns [-digits digits]
report_tns_metric [-setup] | [-hold]
report_units
report_units_metric
report_voltage_domains
report_wire_length [-net net_list] [-file file] [-global_route]
   [-detailed_route] [-verbose]
report_wns [-digits digits]
report_worst_negative_slack_metric [-setup] | [-hold]
report_worst_slack [-min] [-max] [-digits digits]
report_worst_slack_metric [-setup] | [-hold]
restructure [-slack_threshold slack] [-depth_threshold depth]
   [-target area|timing] [-liberty_file liberty_file] [-tielo_port tielow_port]
   [-tiehi_port tiehigh_port] [-work_dir workdir_name]
rtl_macro_placer -max_num_macro max_num_macro -min_num_macro min_num_macro
   -max_num_inst max_num_inst -min_num_inst min_num_inst -tolerance tolerance
   -max_num_level max_num_level -coarsening_ratio coarsening_ratio
   -num_bundled_ios num_bundled_ios -large_net_threshold large_net_threshold
   -signature_net_threshold signature_net_threshold -halo_width halo_width
   -fence_lx fence_lx -fence_ly fence_ly -fence_ux fence_ux -fence_uy fence_uy
   -area_weight area_weight -outline_weight outline_weight -wirelength_weight
   wirelength_weight -guidance_weight guidance_weight -fence_weight fence_weight
   -boundary_weight boundary_weight -notch_weight notch_weight
   -macro_blockage_weight macro_blockage_weight -pin_access_th pin_access_th
   -target_util target_util -target_dead_space target_dead_space -min_ar min_ar
   -snap_layer snap_layer -report_directory report_directory
run_load_balancer [-host host] [-port port] [-workers_domain workers_domain]
run_worker [-host host] [-port port] [-i]
save_image [-area {x0 y0 x1 y1}] [-resolution microns_per_pixel]
   [-display_option option] path
select -type object_type [-name name_regex] [-case_insensitive]
   [-highlight group]
set_assigned_check -setup|-hold|-recovery|-removal [-rise] [-fall]
   [-corner corner] [-min] [-max] [-from from_pins] [-to to_pins]
   [-clock rise|fall] [-cond sdf_cond] check_value
set_assigned_delay -cell|-net [-rise] [-fall] [-corner corner] [-min] [-max]
   [-from from_pins] [-to to_pins] delay
set_assigned_transition [-rise] [-fall] [-corner corner] [-min] [-max] slew pins
set_bump -row row -col col [(-power|-ground|-net) net_name] [-remove]
set_bump_options [-pitch pitch] [-bump_pin_name pin_name]
   [-spacing_to_edge spacing] [-offset {x_offset y_offset}]
   [-array_size {rows columns}] [-cell_name bump_cell_table]
   [-num_pads_per_tile value] [-rdl_layer name] [-rdl_width value]
   [-rdl_spacing value] [-rdl_route_style (45|90|under)]
   [-padcell_to_rdl list_of_vias] [-rdl_to_bump list_of_vias]
   [-rdl_cover_file_name rdl_file_name]
set_case_analysis 0|1|zero|one|rise|rising|fall|falling pins
set_clock_gating_check [-setup setup_time] [-hold hold_time] [-rise] [-fall]
   [-low] [-high] [objects]
set_clock_groups [-name name] [-logically_exclusive] [-physically_exclusive]
   [-asynchronous] [-allow_paths] [-comment comment] -group clocks
set_clock_latency [-source] [-clock clock] [-rise] [-fall] [-min] [-max]
   [-early] [-late] delay objects
set_clock_sense [-positive] [-negative] [-pulse pulse_type] [-stop_propagation]
   [-clock clocks] pins
set_clock_transition [-rise] [-fall] [-min] [-max] transition clocks
set_clock_uncertainty [-from|-rise_from|-fall_from from_clock]
   [-to|-rise_to|-fall_to to_clock] [-rise] [-fall] [-setup] [-hold] uncertainty
   [objects]
set_cmd_units [-capacitance cap_unit] [-resistance res_unit] [-time time_unit]
   [-voltage voltage_unit] [-current current_unit] [-power power_unit]
   [-distance distance_unit]
set_data_check [-from from_pin] [-rise_from from_pin] [-fall_from from_pin]
   [-to to_pin] [-rise_to to_pin] [-fall_to to_pin] [-setup | -hold]
   [-clock clock] margin
set_debug_level tool group level
set_disable_inferred_clock_gating objects
set_disable_timing [-from from_port] [-to to_port] objects
set_domain_area domain_name -area
set_dont_touch nets_instances
set_dont_use lib_cells
set_drive [-rise] [-fall] [-min] [-max] resistance ports
set_driving_cell [-lib_cell cell] [-library library] [-rise] [-fall] [-min]
   [-max] [-pin pin] [-from_pin from_pin] [-input_transition_rise trans_rise]
   [-input_transition_fall trans_fall] [-multiply_by factor] [-dont_scale]
   [-no_design_rule] ports
set_false_path [-setup] [-hold] [-rise] [-fall] [-reset_path] [-comment comment]
   [-from from_list] [-rise_from from_list] [-fall_from from_list]
   [-through through_list] [-rise_through through_list]
   [-fall_through through_list] [-to to_list] [-rise_to to_list]
   [-fall_to to_list]
set_fanout_load fanout ports
set_global_routing_layer_adjustment layer adj
set_global_routing_random [-seed seed]
   [-capacities_perturbation_percentage percent] [-perturbation_amount value]
set_global_routing_region_adjustment region [-layer layer]
   [-adjustment adjustment]
set_hierarchy_separator seperator
set_ideal_latency [-rise] [-fall] [-min] [-max] delay objects
set_ideal_net nets
set_ideal_network [-no_propagation] objects
set_ideal_transition [-rise] [-fall] [-min] [-max] transition_time objects
set_input_delay [-rise] [-fall] [-max] [-min] [-clock clock] [-clock_fall]
   [-reference_pin ref_pin] [-source_latency_included]
   [-network_latency_included] [-add_delay] delay port_pin_list
set_input_transition [-rise] [-fall] [-min] [-max] transition ports
set_io_pin_constraint [-direction direction] [-pin_names names] [-region region]
   [-mirrored_pins pins]
set_isolation [-domain domain] [-applies_to applies_to]
   [-clamp_value clamp_value] [-isolation_signal isolation_signal]
   [-isolation_sense isolation_sense] [-location location] [-update] name
set_layer_rc [-layer layer] [-via via_layer] [-capacitance cap]
   [-resistance res] [-corner corner]
set_level_shifter_strategy [-rule rule_type]
set_level_shifter_threshold [-voltage volt]
set_load [-rise] [-fall] [-max] [-min] [-subtract_pin_load] [-pin_load]
   [-wire_load] capacitance objects
set_logic_dc port_list
set_logic_one port_list
set_logic_zero port_list
set_macro_extension extension
set_max_area area
set_max_capacitance cap objects
set_max_delay [-rise] [-fall] [-ignore_clock_latency] [-reset_path]
   [-comment comment] [-from from_list] [-rise_from from_list]
   [-fall_from from_list] [-through through_list] [-rise_through through_list]
   [-fall_through through_list] [-to to_list] [-rise_to to_list]
   [-fall_to to_list] delay
set_max_dynamic_power power [unit]
set_max_fanout fanout objects
set_max_leakage_power power [unit]
set_max_time_borrow limit objects
set_max_transition [-clock_path] [-data_path] [-rise] [-fall] slew objects
set_min_capacitance cap objects
set_min_delay [-rise] [-fall] [-ignore_clock_latency] [-reset_path]
   [-comment comment] [-from from_list] [-rise_from from_list]
   [-fall_from from_list] [-through through_list] [-rise_through through_list]
   [-fall_through through_list] [-to to_list] [-rise_to to_list]
   [-fall_to to_list] delay
set_min_pulse_width [-low] [-high] value [objects]
set_multicycle_path [-setup] [-hold] [-rise] [-fall] [-start] [-end]
   [-reset_path] [-comment comment] [-from from_list] [-rise_from from_list]
   [-fall_from from_list] [-through through_list] [-rise_through through_list]
   [-fall_through through_list] [-to to_list] [-rise_to to_list]
   [-fall_to to_list] path_multiplier
set_operating_conditions [-analysis_type single|bc_wc|on_chip_variation]
   [-library lib] [condition] [-min min_condition] [-max max_condition]
   [-min_library min_lib] [-max_library max_lib]
set_output_delay [-rise] [-fall] [-max] [-min] [-clock clock] [-clock_fall]
   [-reference_pin ref_pin] [-source_latency_included]
   [-network_latency_included] [-add_delay] delay port_pin_list
set_padring_options [-type (flipchip|wirebond)] [-power power_nets]
   [-ground ground_nets] [-core_area core_area] [-die_area die_area]
   [-offsets offsets] [-pad_inst_pattern pad_inst_pattern]
   [-pad_pin_pattern pad_pin_pattern] [-pad_pin_layer pin_layer_name]
   [-pin_layer layer_name] [-connect_by_abutment signal_list]
   [-allow_filler_overlap]
set_pdnsim_net_voltage [-net net_name] [-voltage volt]
set_pin_length [-hor_length h_length] [-ver_length v_length]
set_pin_length_extension [-hor_extension h_ext] [-ver_extension v_ext]
set_pin_offset offset
set_pin_thick_multiplier [-hor_multiplier h_mult] [-ver_multiplier v_mult]
set_placement_padding -global|-masters masters|-instances insts
   [-right site_count] [-left site_count] [instances]
set_pocv_sigma_factor factor
set_port_fanout_number [-max] [-min] fanout ports
set_power_activity [-global] [-input] [-input_ports ports] [-pins pins]
   [-activity activity] [-duty duty]
set_propagated_clock objects
set_pvt insts [-min] [-max] [-process process] [-voltage voltage]
   [-temperature temperature]
set_resistance [-min] [-max] resistance nets
set_routing_alpha alpha [-net net_name] [-min_fanout fanout] [-min_hpwl hpwl]
   [-clock_nets]
set_routing_layers [-signal layers] [-clock layers]
set_sense [-type clock|data] [-positive] [-negative] [-pulse pulse_type]
   [-stop_propagation] [-clocks clocks] pins
set_timing_derate -early|-late [-rise] [-fall] [-clock] [-data] [-net_delay]
   [-cell_delay] [-cell_check] derate [objects]
set_units [-time time_unit] [-capacitance cap_unit] [-resistance res_unit]
   [-voltage voltage_unit] [-current current_unit] [-power power_unit]
   [-distance distance_unit]
set_voltage_domain -name domain_name -power power_net_name -ground
   ground_net_name [-region region_name]
   [-secondary_power secondary_power_net_name]
   [-switched_power switched_power_net_name]
set_wire_load_min_block_size block_size
set_wire_load_mode top|enclosed|segmented
set_wire_load_model -name model_name [-library lib_name] [-min] [-max] [objects]
set_wire_load_selection_group [-library lib] [-min] [-max] group_name [objects]
set_wire_rc [-clock] [-signal] [-layer layer_name] [-resistance res]
   [-capacitance cap] [-corner corner]
show_copying
show_splash
show_warranty
source [-echo] [-verbose] filename [> filename] [>> filename]
suppress_message tool id
tapcell [-tapcell_master tapcell_master] [-tap_prefix tap_prefix]
   [-endcap_master endcap_master] [-endcap_cpp endcap_cpp]
   [-endcap_prefix endcap_prefix] [-distance dist] [-halo_width_x halo_x]
   [-halo_width_y halo_y] [-tap_nwin2_master tap_nwin2_master]
   [-tap_nwin3_master tap_nwin3_master] [-tap_nwout2_master tap_nwout2_master]
   [-tap_nwout3_master tap_nwout3_master]
   [-tap_nwintie_master tap_nwintie_master]
   [-tap_nwouttie_master tap_nwouttie_master]
   [-cnrcap_nwin_master cnrcap_nwin_master]
   [-cnrcap_nwout_master cnrcap_nwout_master]
   [-incnrcap_nwin_master incnrcap_nwin_master]
   [-incnrcap_nwout_master incnrcap_nwout_master] [-tbtie_cpp tbtie_cpp]
   [-no_cell_at_top_bottom]
tapcell_ripup [-tap_prefix tap_prefix] [-endcap_prefix endcap_prefix]
triton_part_design [-num_parts num_parts]
   [-balance_constraint balance_constraint] [-seed seed]
   [-solution_file file_name] [-paths_file file_name]
   [-hypergraph_file file_name]
triton_part_hypergraph -hypergraph_file hypergraph_file [-fixed_file fixed_file]
   [-num_parts num_parts] [-balance_constraint balance_constraint]
   [-vertex_dimension vertex_dimension]
   [-hyperedge_dimension hyperedge_dimension] [-seed seed]
unset_case_analysis pins
unset_clock_groups [-logically_exclusive] [-physically_exclusive]
   [-asynchronous] [-name names] [-all]
unset_clock_latency [-source] [-clock clock] objects
unset_clock_transition clocks
unset_clock_uncertainty [-from|-rise_from|-fall_from from_clock]
   [-to|-rise_to|-fall_to to_clock] [-rise] [-fall] [-setup] [-hold] [objects]
unset_data_check [-from from_pin] [-rise_from from_pin] [-fall_from from_pin]
   [-to to_pin] [-rise_to to_pin] [-fall_to to_pin] [-setup | -hold]
   [-clock clock]
unset_disable_inferred_clock_gating objects
unset_disable_timing [-from from_port] [-to to_port] objects
unset_dont_touch nets_instances
unset_dont_use lib_cells
unset_generated_clock [-all] clocks
unset_input_delay [-rise] [-fall] [-max] [-min] [-clock clock] [-clock_fall]
   port_pin_list
unset_output_delay [-rise] [-fall] [-max] [-min] [-clock clock] [-clock_fall]
   port_pin_list
unset_path_exceptions [-setup] [-hold] [-rise] [-fall] [-from from_list]
   [-rise_from from_list] [-fall_from from_list] [-through through_list]
   [-rise_through through_list] [-fall_through through_list] [-to to_list]
   [-rise_to to_list] [-fall_to to_list]
unset_propagated_clock objects
unset_timing_derate
use_interface_cell [-domain domain] [-strategy strategy] [-lib_cells lib_cells]
user_run_time
with_output_to_variable var
write_abstract_lef [-bloat_factor amount|-bloat_occupied_layers] filename
write_cdl [-include_fillers] -masters masters_filenames out_filename
write_db filename
write_def [-version version] filename
write_guides filename
write_lef filename
write_path_spice -path_args path_args -spice_directory spice_directory
   -lib_subckt_file lib_subckts_file -model_file model_file -power power -ground
   ground
write_pg_spice [-vsrc vsrc_file ] [-outfile out_file] [-net net_name]
   [-dx bump_pitch_x] [-dy bump_pitch_y]
write_rules [-file filename] [-dir dir] [-name name] [-pattern pattern]
write_sdc [-map_hpins] [-digits digits] [-gzip] [-no_timestamp] filename
write_sdf [-corner corner] [-divider /|.] [-include_typ] [-digits digits]
   [-gzip] [-no_timestamp] [-no_version] filename
write_spef [-net_id net_id] [-nets nets] filename
write_timing_model [-corner corner] [-library_name lib_name]
   [-cell_name cell_name] filename
write_verilog [-sort] [-include_pwr_gnd] [-remove_cells cells] filename
openroad>

---

Thank you so much,
Vic P.

[rovinski]

1. OpenROAD only supports verilog netlists.
2. Your SDC file mentions a clock that does not exist. You have [get_ports clk] but there is no clk input in your design.

You should probably be using OpenROAD Flow Scripts to run a flow instead of manually running yosys.

[vic4key]

I got it. Do you know where can I read/download paper/documentation that presentation of parameters/configurations of each stage (floorplan stage, placement stage, CTS stage, routing stage)? I'd like to understand the parameters/configurations of these stages.
Thank you.

[vijayank88]

Explore this tutorial