How can I find the net for a wire?

[oharboe]

I am currently dealing with an issue related to unexpected congestion in a design that has me stumped. It appears that there might be incorrect constraints on some I/O pins of a macro.

When I try to probe deeper into the congested area by clicking on the wires, the details provided are fairly vague – something along the lines of "wire4940/A". I'm led to believe that this wire is simply a segment of a larger net.

Ideally, I would be able to trace this wire segment back to its origin and endpoint within the RTL design, which would help me identify the exact register/pin it connects from and to. However, I'm unsure of how to proceed with this.

[rovinski]

wire4940/A is an iTerm (instance terminal) meaning that wire4940 is the name of a cell, not a wire segment. I believe wire#### is the generated name for buffers which are inserted due to max wirelength targets.

The net that you have selected is connecting two iTerms, most likely buffers.

There should be a GUI display item called "Buffer Tree" which should show you what you want. See #2781 and #2824 for discussion.

[oharboe]

Manually tracing these wires is difficult. Unless you know exactly what is going on, and I don't, it is hard to figure out where the highlighted wire goes after this mess :-)

[rovinski]

It should show up in the inspector window. I suppose if it doesn't, then it isn't a buffered net after all?

[oharboe]

No "Buffer tree" here:

[vijayank88]

@oharboe
Did you tried to trace with Find option from gui?

[oharboe]

No. I don't know what to search for. This is my problem. I don't know the name of the net that wireXXXX is part of.

[maliberty]

wireXXX will be part of multiple nets and they will be show next to the iterm name.

Buffer tree only shows up if one is detected. To detect buffers we need the liberty to be loaded. If you used GUI_NO_TIMING=1 then it will not appear.

[oharboe]

So if I run make gui_final, I should see it, but if I just load 6_final.odb, I wont?

[maliberty]

Yes as .lib is not stored in the db.

[oharboe]

Works very well!

When I click on the buffer tree, I get the terminals (endpoints), which I can relate to my Verilog easily.