Route err when place_pad a pad

[xuyang-stack]

make route
failed:
[ERROR GRT-0119] Routing congestion too high. Check the congestion heatmap in the GUI and load ./reports/nangate45/gcd/base/congestion.rpt in the DRC viewer.

During the routing phase, congestion occurs. Upon checking the Design Rule Check (DRC) report, I noticed that the congestion is occurring within the module itself. This is expected because there are several obstruction (obs) regions in that area, and congestion is normal when attempting to route in such congested areas. However, ABC_GPIO should be treated as an independent module where internal routing is not necessary. It should only require connections from its pins to other modules. Why is this issue occurring?

In my own design, I made the following additions:

tcl file:
place_pad -master ABC_GPIO -row IO_SOUTH -location 420 {U_GPIOA_2}

v file:
ABC_GPIO U_GPIOA_2 (
.C(reset_io ),
.I(1'b0 ),
.IE(1'b1 ),
.OEN(1'b1 ),
.PAD(reset_pad )
);

lef file:
MACRO ABC_GPIO
CLASS PAD ;
FOREIGN ABC_GPIO 0.000 0.000 ;
ORIGIN 0.000 0.000 ;
SIZE 30.000 BY 177.000 ;
SYMMETRY R90 ;
SITE IOSite ;
PIN IE
DIRECTION INPUT ;
PORT
LAYER M5 ;
RECT 19.095 176.460 21.055 177.000 ;
LAYER M4 ;
RECT 19.095 176.460 21.055 177.000 ;
LAYER M3 ;
RECT 19.095 176.460 21.055 177.000 ;
LAYER M2 ;
RECT 19.095 176.460 21.055 177.000 ;
RECT 19.780 170.220 19.900 177.000 ;
RECT 18.905 170.220 19.900 170.340 ;
LAYER M1 ;
RECT 19.095 176.460 21.055 177.000 ;
END
AntennaGateArea 1 ;
AntennaDiffArea 0.590 ;
END IE
PIN C
DIRECTION OUTPUT ;
PORT
LAYER M5 ;
RECT 26.860 176.460 28.820 177.000 ;
LAYER M4 ;
RECT 26.860 176.460 28.820 177.000 ;
LAYER M3 ;
RECT 26.860 176.460 28.820 177.000 ;
LAYER M2 ;
RECT 26.860 176.460 28.820 177.000 ;
***************
RECT 21.790 170.505 21.910 172.690 ;
LAYER M1 ;
RECT 26.860 176.460 28.820 177.000 ;
END
AntennaGateArea 0 ;
AntennaDiffArea 0.590 ;
END C
PIN I
DIRECTION INPUT ;
PORT
LAYER M5 ;
RECT 1.180 176.460 3.140 177.000 ;
LAYER M4 ;
RECT 1.180 176.460 3.140 177.000 ;
LAYER M3 ;
RECT 1.180 176.460 3.140 177.000 ;
LAYER M2 ;
RECT 5.440 170.210 5.720 170.330 ;
********************
RECT 2.080 170.210 2.200 177.000 ;
LAYER M1 ;
RECT 1.180 176.460 3.140 177.000 ;
END
AntennaGateArea 0.5 ;
AntennaDiffArea 0.590 ;
END I
PIN PAD
DIRECTION INOUT ;
PORT
LAYER TM2 ;
RECT 2.000 0.000 28.000 3.000 ;
LAYER TM1 ;
RECT 2.000 0.000 28.000 3.000 ;
LAYER M7 ;
RECT 2.000 0.000 28.000 3.000 ;
LAYER M6 ;
RECT 2.000 0.000 28.000 3.000 ;
LAYER M5 ;
RECT 2.000 0.000 28.000 3.000 ;
LAYER M4 ;
RECT 2.000 0.000 28.000 3.000 ;
LAYER M3 ;
RECT 25.125 106.150 27.475 136.480 ;
*************
RECT 2.525 106.130 4.845 136.490 ;
LAYER M2 ;
RECT 25.125 106.150 27.475 136.480 ;
************
RECT 2.525 106.130 4.845 136.490 ;
END
END PAD
PIN OEN
DIRECTION INPUT ;
PORT
LAYER M5 ;
RECT 4.500 176.460 6.460 177.000 ;
LAYER M4 ;
RECT 4.500 176.460 6.460 177.000 ;
LAYER M3 ;
RECT 4.500 176.460 6.460 177.000 ;
LAYER M2 ;
RECT 4.500 176.460 6.460 177.000 ;
RECT 3.910 170.210 5.300 170.330 ;
RECT 4.680 170.210 4.800 177.000 ;
LAYER M1 ;
RECT 4.500 176.460 6.460 177.000 ;
END
AntennaGateArea 0.4 ;
AntennaDiffArea 0.590 ;
END OEN
OBS
LAYER TM2 ;
RECT 0.000 0.000 1.290 177.000 ;
RECT 28.710 0.000 30.000 177.000 ;
RECT 0.000 3.710 30.000 177.000 ;
LAYER TV2 ;
RECT 0.000 0.000 30.000 177.000 ;
LAYER M7 ;
RECT 0.000 0.000 1.415 177.000 ;
RECT 28.585 0.000 30.000 177.000 ;
RECT 0.000 3.585 30.000 177.000 ;
LAYER M6 ;
RECT 0.000 0.000 1.415 177.000 ;
RECT 28.585 0.000 30.000 177.000 ;
RECT 0.000 3.585 30.000 177.000 ;
LAYER TM1 ;
RECT 0.000 0.000 1.270 177.000 ;
RECT 28.730 0.000 30.000 177.000 ;
RECT 0.000 3.730 30.000 177.000 ;
LAYER M5 ;
RECT 0.000 0.000 1.415 175.875 ;
*************
RECT 29.405 0.000 30.000 177.000 ;
LAYER M4 ;
RECT 0.000 0.000 1.415 175.875 ;
***************
RECT 29.405 0.000 30.000 177.000 ;
LAYER M3 ;
RECT 1.150 108.100 1.955 136.480 ;
*****************
RECT 26.815 0.000 30.000 95.235 ;
LAYER V6 ;
RECT 0.000 0.000 30.000 177.000 ;
LAYER V5 ;
RECT 0.000 0.000 30.000 177.000 ;
LAYER V4 ;
RECT 0.000 0.000 30.000 177.000 ;
LAYER TV1 ;
RECT 0.000 0.000 30.000 177.000 ;
LAYER V3 ;
RECT 0.000 0.000 30.000 177.000 ;
LAYER V2 ;
RECT 0.000 0.000 30.000 177.000 ;
LAYER M2 ;
RECT 1.350 170.210 1.630 170.330 ;
****************
RECT 29.405 173.275 30.000 177.000 ;
LAYER M1 ;
RECT 0.000 0.000 30.000 175.875 ;
RECT 0.000 0.000 0.595 177.000 ;
RECT 3.725 0.000 3.915 177.000 ;
RECT 7.045 0.000 18.510 177.000 ;
RECT 21.640 0.000 26.275 177.000 ;
RECT 29.405 0.000 30.000 177.000 ;
LAYER V1 ;
RECT 0.000 0.000 30.000 177.000 ;
END
END ABC_GPIO

[maliberty]

This is an issue, not a discussion, and needs to have a test case attached.