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After 64 iterations DRT stopped on my design a generated a DRC report. It turns out that most of the DRC are related to METAL1 spacing (with net VSS) and Metal SpacingTableTw. The design is not very congested so I wonder why the tool could not fix these rules. Could it be that I am missing something here (maybe something in my platform definition)? Is there a way to fix these violations?
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Replies: 2 comments 5 replies
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Can you provide a test case? |
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@maliberty an attempt to upload a testcase failed because the file is too big (34 MB). Only 25 MB are allowed. Is there another way I could share it? |
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You can upload to a service like Google drive and provide a link |
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@maliberty Here is the link |
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@maliberty I was wondering if you had the chance to have a look at this and if I should keep the link active. |
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Sorry this got overlooked. I've downloaded it and will take a look. |
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You have very wide METAL1 power stripes:
The pin is less than the min space (0.19 < 0.23) from the stripe so there is always going to be a DRC error here. You need to adjust your PDN definition to be resolve this. |
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You have very wide METAL1 power stripes:
The pin is less than the min space (0.19 < 0.23) from the stripe so there is always going to be a DRC error here. You need to adjust your PDN definition to be resolve this.