What is the optimization target for CTS?

[oharboe]

There must a great number of papers written about CTS, but I found this an interesting series of slides about CTS and easy to read for someone who has only recently learned about CTS: https://www.eng.biu.ac.il/temanad/files/2017/02/Lecture-8-CTS.pdf

This made me think about what is it exactly that the CTS should target and how should it target it?

First time I heard about CTS, I thought that zero skew and zero latency was a good optimization target. Of course that can never be realized, it is just an optimization target.

I just recently tested out some visualization of the clock tree #3788, but this visualization only shows the clock network delay(not accounting for macros, only flip flops). That doesn't tell me anything about how far the clock tree is from the optimization target.

If I have very little network latency near the input/output pins and I have timing closure, is there any reason to care about skew and clock network latency in the rest of the design?

If that condition is satisfied, isn't the next things to optimize for other things like power, area and signal integrity?

[oharboe]

No takers :-)