diff --git a/.github/workflows/Pipeline.yml b/.github/workflows/Pipeline.yml
index 5d2c17d..dcbea3f 100644
--- a/.github/workflows/Pipeline.yml
+++ b/.github/workflows/Pipeline.yml
@@ -13,44 +13,44 @@ jobs:
     with:
       name: VHDLDomain
 
-  UnitTesting:
-    uses: pyTooling/Actions/.github/workflows/UnitTesting.yml@dev
-    needs:
-      - Params
-    with:
-      jobs: ${{ needs.Params.outputs.python_jobs }}
-      artifact: ${{ fromJson(needs.Params.outputs.artifact_names).unittesting_xml }}
-
-  Coverage:
-    uses: pyTooling/Actions/.github/workflows/CoverageCollection.yml@dev
-    needs:
-      - Params
-    with:
-      python_version: ${{ needs.Params.outputs.python_version }}
-      artifact: ${{ fromJson(needs.Params.outputs.artifact_names).codecoverage_html }}
-    secrets:
-      codacy_token: ${{ secrets.CODACY_PROJECT_TOKEN }}
-
-  StaticTypeCheck:
-    uses: pyTooling/Actions/.github/workflows/StaticTypeCheck.yml@dev
-    needs:
-      - Params
-    with:
-      python_version: ${{ needs.Params.outputs.python_version }}
-      requirements: '-r tests/requirements.txt'
-      commands: mypy --html-report htmlmypy -p VHDLDomain
-      html_artifact: ${{ fromJson(needs.Params.outputs.artifact_names).statictyping_html }}
-
-  PublishTestResults:
-    uses: pyTooling/Actions/.github/workflows/PublishTestResults.yml@dev
-    needs:
-      - UnitTesting
+#  UnitTesting:
+#    uses: pyTooling/Actions/.github/workflows/UnitTesting.yml@dev
+#    needs:
+#      - Params
+#    with:
+#      jobs: ${{ needs.Params.outputs.python_jobs }}
+#      artifact: ${{ fromJson(needs.Params.outputs.artifact_names).unittesting_xml }}
+#
+#  Coverage:
+#    uses: pyTooling/Actions/.github/workflows/CoverageCollection.yml@dev
+#    needs:
+#      - Params
+#    with:
+#      python_version: ${{ needs.Params.outputs.python_version }}
+#      artifact: ${{ fromJson(needs.Params.outputs.artifact_names).codecoverage_html }}
+#    secrets:
+#      codacy_token: ${{ secrets.CODACY_PROJECT_TOKEN }}
+#
+#  StaticTypeCheck:
+#    uses: pyTooling/Actions/.github/workflows/StaticTypeCheck.yml@dev
+#    needs:
+#      - Params
+#    with:
+#      python_version: ${{ needs.Params.outputs.python_version }}
+#      requirements: '-r tests/requirements.txt'
+#      commands: mypy --html-report htmlmypy -p VHDLDomain
+#      html_artifact: ${{ fromJson(needs.Params.outputs.artifact_names).statictyping_html }}
+#
+#  PublishTestResults:
+#    uses: pyTooling/Actions/.github/workflows/PublishTestResults.yml@dev
+#    needs:
+#      - UnitTesting
 
   Package:
     uses: pyTooling/Actions/.github/workflows/Package.yml@dev
     needs:
       - Params
-      - Coverage
+#      - Coverage
     with:
       python_version: ${{ needs.Params.outputs.python_version }}
       artifact: ${{ fromJson(needs.Params.outputs.artifact_names).package_all }}
@@ -59,9 +59,9 @@ jobs:
     uses: pyTooling/Actions/.github/workflows/Release.yml@dev
     if: startsWith(github.ref, 'refs/tags')
     needs:
-      - UnitTesting
-      - Coverage
-      - StaticTypeCheck
+#      - UnitTesting
+#      - Coverage
+#      - StaticTypeCheck
       - Package
 
   PublishOnPyPI:
@@ -78,61 +78,61 @@ jobs:
     secrets:
       PYPI_TOKEN: ${{ secrets.PYPI_TOKEN }}
 
-  VerifyDocs:
-    needs:
-      - Params
-    name: 👍 Verify example snippets using Python ${{ needs.Params.outputs.python_version }}
-    runs-on: ubuntu-latest
-
-    steps:
-      - name: ⏬ Checkout repository
-        uses: actions/checkout@v3
-
-      - name: ⚙ Setup GHDL
-        uses: ghdl/setup-ghdl-ci@master
-
-      - name: 🐍 Setup Python
-        uses: actions/setup-python@v4
-        with:
-          python-version: "3.10"
-#          python-version: ${{ needs.Params.outputs.python_version }}
-
-      - name: 🐍 Install dependencies
-        run: |
-          pip3 install --disable-pip-version-check git+https://github.com/ghdl/ghdl.git@$(ghdl version hash)
-
-      - name: ✂ Extract code snippet from README
-        shell: python
-        run: |
-          from pathlib import Path
-          import re
-
-          ROOT = Path('.')
-
-          with (ROOT / 'README.md').open('r') as rptr:
-              content = rptr.read()
-
-          m = re.search(r"```py(thon)?(?P<code>.*?)```", content, re.MULTILINE|re.DOTALL)
-
-          if m is None:
-              raise Exception("Regular expression did not find the example in the README!")
-
-          with (ROOT / 'tests/docs/example.py').open('w') as wptr:
-              wptr.write(m["code"])
-
-#      - name: Print example.py
-#        run: cat tests/docs/example.py
-
-      - name: ☑ Run example snippet
-        working-directory: tests/docs
-        run: |
-          python3 example.py
+#  VerifyDocs:
+#    needs:
+#      - Params
+#    name: 👍 Verify example snippets using Python ${{ needs.Params.outputs.python_version }}
+#    runs-on: ubuntu-latest
+#
+#    steps:
+#      - name: ⏬ Checkout repository
+#        uses: actions/checkout@v3
+#
+#      - name: ⚙ Setup GHDL
+#        uses: ghdl/setup-ghdl-ci@master
+#
+#      - name: 🐍 Setup Python
+#        uses: actions/setup-python@v4
+#        with:
+#          python-version: "3.10"
+##          python-version: ${{ needs.Params.outputs.python_version }}
+#
+#      - name: 🐍 Install dependencies
+#        run: |
+#          pip3 install --disable-pip-version-check git+https://github.com/ghdl/ghdl.git@$(ghdl version hash)
+#
+#      - name: ✂ Extract code snippet from README
+#        shell: python
+#        run: |
+#          from pathlib import Path
+#          import re
+#
+#          ROOT = Path('.')
+#
+#          with (ROOT / 'README.md').open('r') as rptr:
+#              content = rptr.read()
+#
+#          m = re.search(r"```py(thon)?(?P<code>.*?)```", content, re.MULTILINE|re.DOTALL)
+#
+#          if m is None:
+#              raise Exception("Regular expression did not find the example in the README!")
+#
+#          with (ROOT / 'tests/docs/example.py').open('w') as wptr:
+#              wptr.write(m["code"])
+#
+##      - name: Print example.py
+##        run: cat tests/docs/example.py
+#
+#      - name: ☑ Run example snippet
+#        working-directory: tests/docs
+#        run: |
+#          python3 example.py
 
   BuildTheDocs:
     uses: pyTooling/Actions/.github/workflows/BuildTheDocs.yml@dev
     needs:
       - Params
-      - VerifyDocs
+#      - VerifyDocs
     with:
       artifact: ${{ fromJson(needs.Params.outputs.artifact_names).documentation_html }}
 
@@ -141,23 +141,23 @@ jobs:
     needs:
       - Params
       - BuildTheDocs
-      - Coverage
-      - StaticTypeCheck
+#      - Coverage
+#      - StaticTypeCheck
     with:
       doc: ${{ fromJson(needs.Params.outputs.artifact_names).documentation_html }}
-      coverage: ${{ fromJson(needs.Params.outputs.artifact_names).codecoverage_html }}
-      typing: ${{ fromJson(needs.Params.outputs.artifact_names).statictyping_html }}
+#      coverage: ${{ fromJson(needs.Params.outputs.artifact_names).codecoverage_html }}
+#      typing: ${{ fromJson(needs.Params.outputs.artifact_names).statictyping_html }}
 
   ArtifactCleanUp:
     uses: pyTooling/Actions/.github/workflows/ArtifactCleanUp.yml@dev
     needs:
       - Params
-      - UnitTesting
-      - Coverage
-      - StaticTypeCheck
+#      - UnitTesting
+#      - Coverage
+#      - StaticTypeCheck
       - BuildTheDocs
       - PublishToGitHubPages
-      - PublishTestResults
+#      - PublishTestResults
     with:
       package: ${{ fromJson(needs.Params.outputs.artifact_names).package_all }}
       remaining: |
diff --git a/.idea/VHDLDomain.iml b/.idea/VHDLDomain.iml
index d13f6da..72f95c6 100644
--- a/.idea/VHDLDomain.iml
+++ b/.idea/VHDLDomain.iml
@@ -9,6 +9,7 @@
     </content>
     <orderEntry type="jdk" jdkName="Python 3.11" jdkType="Python SDK" />
     <orderEntry type="sourceFolder" forTests="false" />
+    <orderEntry type="module" module-name="pyVHDLModel" />
   </component>
   <component name="TestRunnerService">
     <option name="PROJECT_TEST_RUNNER" value="Unittests" />
diff --git a/VHDLDomain/Directive.py b/VHDLDomain/Directive.py
new file mode 100644
index 0000000..232a735
--- /dev/null
+++ b/VHDLDomain/Directive.py
@@ -0,0 +1,611 @@
+# ==================================================================================================================== #
+# __     ___   _ ____  _     ____                        _                                                             #
+# \ \   / / | | |  _ \| |   |  _ \  ___  _ __ ___   __ _(_)_ __                                                        #
+#  \ \ / /| |_| | | | | |   | | | |/ _ \| '_ ` _ \ / _` | | '_ \                                                       #
+#   \ V / |  _  | |_| | |___| |_| | (_) | | | | | | (_| | | | | |                                                      #
+#    \_/  |_| |_|____/|_____|____/ \___/|_| |_| |_|\__,_|_|_| |_|                                                      #
+#                                                                                                                      #
+# ==================================================================================================================== #
+# Authors:                                                                                                             #
+#   Patrick Lehmann                                                                                                    #
+#                                                                                                                      #
+# License:                                                                                                             #
+# ==================================================================================================================== #
+# Copyright 2017-2023 Patrick Lehmann - Boetzingen, Germany                                                            #
+# Copyright 2016-2017 Patrick Lehmann - Dresden, Germany                                                               #
+#                                                                                                                      #
+# Licensed under the Apache License, Version 2.0 (the "License");                                                      #
+# you may not use this file except in compliance with the License.                                                     #
+# You may obtain a copy of the License at                                                                              #
+#                                                                                                                      #
+#   http://www.apache.org/licenses/LICENSE-2.0                                                                         #
+#                                                                                                                      #
+# Unless required by applicable law or agreed to in writing, software                                                  #
+# distributed under the License is distributed on an "AS IS" BASIS,                                                    #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.                                             #
+# See the License for the specific language governing permissions and                                                  #
+# limitations under the License.                                                                                       #
+#                                                                                                                      #
+# SPDX-License-Identifier: Apache-2.0                                                                                  #
+# ==================================================================================================================== #
+#
+"""
+**A Sphinx domain providing VHDL language support.**
+
+This module contains all the directives of the VHDL domain.
+"""
+from enum import Flag, auto
+from textwrap import dedent
+from typing import List, Dict, Tuple
+
+from docutils import nodes
+from docutils.nodes import Node, section, table, tgroup
+from sphinx.directives import ObjectDescription
+from sphinx.domains import Domain
+from pyTooling.Decorators import export
+from pyGHDL.dom.DesignUnit import Entity
+from pyGHDL.dom.InterfaceItem import GenericConstantInterfaceItem, PortSignalInterfaceItem
+
+
+@export
+class ParameterStyle(Flag):
+	Never = auto()
+	Table = auto()
+	Sections = auto()
+
+
+@export
+class ArchitecturesStyle(Flag):
+	Never = auto()
+	Multiple = auto()
+	Always = auto()
+
+
+@export
+def strip(option: str):
+	return option.strip().lower()
+
+
+@export
+class BaseDirective(ObjectDescription):
+	has_content: bool = False
+	"""
+	A boolean; ``True`` if content is allowed.
+
+	Client code must handle the case where content is required but not supplied (an empty content list will be supplied).
+	"""
+
+	required_arguments = 0
+	"""Number of required directive arguments."""
+
+	optional_arguments = 0
+	"""Number of optional arguments after the required arguments."""
+
+	final_argument_whitespace = False
+	"""A boolean, indicating if the final argument may contain whitespace."""
+
+	option_spec = None
+	"""
+	Mapping of option names to validator functions.
+
+	A dictionary, mapping known option names to conversion functions such as :py:class:`int` or :py:class:`float`
+	(default: {}, no options). Several conversion functions are defined in the ``directives/__init__.py`` module.
+
+	Option conversion functions take a single parameter, the option argument (a string or :py:class:`None`), validate it
+	and/or convert it to the appropriate form. Conversion functions may raise :py:exc:`ValueError` and
+	:py:exc:`TypeError` exceptions.
+	"""
+
+	# def __init__(self, *args, **kwargs):
+	# 	super().__init__(*args, **kwargs)
+
+
+@export
+class DescribeDesign(BaseDirective):
+	"""
+	This directive will be replaced by the description of a VHDL design.
+	"""
+
+	has_content = False
+	required_arguments = 0
+	optional_arguments = 0
+
+	def run(self) -> List[Node]:
+		from VHDLDomain import Design
+
+		vhdlDomain: Domain = self.env.domains["vhdl"]
+		designs: Dict[str, Design] = vhdlDomain.data["designs"]
+		design = designs["StopWatch"]
+
+		paragraph = nodes.paragraph(text="Describe design")
+
+		items = []
+		for document in design.Documents:
+			term = nodes.term(text=f"{document.ShortPath}")
+			description = nodes.paragraph(text=f"{document.Documentation}")
+			description = nodes.literal_block(text=f"{document.Documentation}")
+			definition = nodes.definition("", description)
+
+			items.append(nodes.definition_list_item("", term, definition))
+
+		definitionList = nodes.definition_list("", *items)
+
+		return [paragraph, definitionList]
+
+
+@export
+class DescribeLibrary(BaseDirective):
+	"""
+	This directive will be replaced by the description of a VHDL library.
+	"""
+
+	has_content = False
+	required_arguments = 0
+	optional_arguments = 0
+
+	def run(self) -> List[Node]:
+		from VHDLDomain import Design
+
+		vhdlDomain: Domain = self.env.domains["vhdl"]
+		designs: Dict[str, Design] = vhdlDomain.data["designs"]
+		design = designs["StopWatch"]
+
+		paragraph = nodes.paragraph(text="Describe library")
+
+		return [paragraph]
+
+
+@export
+class DescribeDocument(BaseDirective):
+	"""
+	This directive will be replaced by the description of a VHDL document.
+	"""
+
+	has_content = False
+	required_arguments = 0
+	optional_arguments = 0
+
+	def run(self) -> List[Node]:
+		from VHDLDomain import Design
+
+		vhdlDomain: Domain = self.env.domains["vhdl"]
+		designs: Dict[str, Design] = vhdlDomain.data["designs"]
+		design = designs["StopWatch"]
+
+
+		paragraph = nodes.paragraph(text="Describe document")
+
+		return [paragraph]
+
+
+@export
+class DescribeContext(BaseDirective):
+	"""
+	This directive will be replaced by the description of a VHDL context.
+	"""
+
+	has_content = False
+	required_arguments = 0
+	optional_arguments = 1
+
+	option_spec = {
+		"referencedby":  strip,
+	}
+
+	def run(self) -> List[Node]:
+		from VHDLDomain import Design
+
+		vhdlDomain: Domain = self.env.domains["vhdl"]
+		designs: Dict[str, Design] = vhdlDomain.data["designs"]
+		design = designs["StopWatch"]
+
+		paragraph = nodes.paragraph(text="Describe context")
+
+		return [paragraph]
+
+
+@export
+class DescribeEntity(BaseDirective):
+	"""
+	This directive will be replaced by the description of a VHDL entity.
+	"""
+
+	has_content = True
+	required_arguments = 0
+	optional_arguments = 4
+
+	option_spec = {
+		"genericlist":   strip,
+		"portlist":      strip,
+		"architectures": strip,
+		"referencedby":  strip,
+	}
+
+	def _PrepareTable(self, columns: Dict[str, int], classes: List[str]) -> Tuple[table, tgroup]:
+		tableGroup = nodes.tgroup(cols=(len(columns)))
+		table = nodes.table("", tableGroup, classes=classes)
+
+		tableRow = nodes.row()
+		for columnTitle, width in columns.items():
+			tableGroup += nodes.colspec(colwidth=width)
+			tableRow += nodes.entry("", nodes.paragraph(text=columnTitle))
+
+		tableGroup += nodes.thead("", tableRow)
+
+		return table, tableGroup
+
+	def CreateDefinitionSection(self, entity: Entity) -> section:
+		title = nodes.title(text="Definition")
+		paragraph = nodes.literal_block(text=dedent(f"""\
+		entity {entity.Identifier} is
+		  generics (
+		    MODULO : positive;
+		    BITS   : positive := log2(MODULO)
+		  );
+		  ports (
+		    Clock : std_logic;
+		    Reset : std_logic
+		  );
+		end entity;
+		"""))
+		section = nodes.section(
+			"",
+			title,
+			paragraph,
+			ids=[f"{entity.NormalizedIdentifier}-definition"],
+			classes=["vhdl", "vhdl-entity-definition-section"]
+		)
+
+		return section
+
+	def CreateGenericSection(self, entity: Entity, style: ParameterStyle) -> section:
+		content = [
+			nodes.title(text="Generics")
+		]
+
+		if True:
+			content.append(nodes.paragraph(text="list of all generics"))
+
+		if style is ParameterStyle.Table:
+			table, tableGroup = self._PrepareTable(
+				columns={
+					"Generic Name": 2,
+					"Type": 1,
+					"Default Value": 4,
+				},
+				classes=["vhdl", "vhdl-generic-table"]
+			)
+
+			tableBody = nodes.tbody()
+			tableGroup += tableBody
+
+			for generic in entity.GenericItems:
+				cellGenericName = nodes.entry()
+				cellGenericType = nodes.entry()
+				cellDefaultValue = nodes.entry()
+				tableBody += nodes.row("", cellGenericName, cellGenericType, cellDefaultValue)
+
+				if isinstance(generic, GenericConstantInterfaceItem):
+					cellGenericName += nodes.paragraph(text=", ".join(generic.Identifiers))
+					cellGenericType += nodes.paragraph(text=generic.Documentation)
+					if generic.DefaultExpression is not None:
+						cellDefaultValue += nodes.paragraph(text="??")  # str(generic.DefaultExpression))
+
+			content.append(table)
+		elif style is ParameterStyle.Sections:
+			for generic in entity.GenericItems:
+				if isinstance(generic, GenericConstantInterfaceItem):
+					genericSection = nodes.section(ids=[f"{entity.NormalizedIdentifier}-generic-{nID}" for nID in generic.NormalizedIdentifiers])
+					genericSection.append(nodes.title(text=", ".join(generic.Identifiers)))
+					genericSection.append(nodes.paragraph(text=generic.Documentation))
+
+					content.append(genericSection)
+
+		section = nodes.section(
+			ids=[f"{entity.NormalizedIdentifier}-generics"],
+			classes=["vhdl", "vhdl-entity-generic-section"]
+		)
+		section.extend(content)
+
+		return section
+
+	def CreatePortSection(self, entity: Entity, style: ParameterStyle) -> section:
+		content = [
+			nodes.title(text="Ports")
+		]
+
+		if True:
+			content.append(nodes.paragraph(text="list of all ports"))
+
+		if style is ParameterStyle.Table:
+			table, tableGroup = self._PrepareTable(
+				columns={
+					"Port Name": 2,
+					"Direction": 1,
+					"Type": 1,
+					"Default Value": 3
+				},
+				classes=["vhdl", "vhdl-port-table"]
+			)
+
+			tableBody = nodes.tbody()
+			tableGroup += tableBody
+
+			for port in entity.PortItems:
+				cellPortName = nodes.entry()
+				cellPortDirection = nodes.entry()
+				cellPortType = nodes.entry()
+				cellDefaultValue = nodes.entry()
+				tableBody += nodes.row("", cellPortName, cellPortDirection, cellPortType, cellDefaultValue)
+
+				if isinstance(port, PortSignalInterfaceItem):
+					cellPortName += nodes.paragraph(text=", ".join(port.Identifiers))
+					cellPortDirection += nodes.paragraph(text=str(port.Mode))
+					cellPortType += nodes.paragraph(text=port.Documentation)
+					if port.DefaultExpression is not None:
+						cellDefaultValue += nodes.paragraph(text=str(port.DefaultExpression))
+
+			content.append(table)
+		elif style is ParameterStyle.Sections:
+			for port in entity.PortItems:
+				if isinstance(port, PortSignalInterfaceItem):
+					portSection = nodes.section(ids=[f"{entity.NormalizedIdentifier}-port-{nID}" for nID in port.NormalizedIdentifiers])
+					portSection.append(nodes.title(text=", ".join(port.Identifiers)))
+					portSection.append(nodes.paragraph(text=port.Documentation))
+
+					content.append(portSection)
+
+		section = nodes.section(
+			ids=[f"{entity.NormalizedIdentifier}-ports"],
+			classes=["vhdl", "vhdl-entity-port-section"]
+		)
+		section.extend(content)
+
+		return section
+
+	def CreateArchitectureSection(self, entity: Entity) -> section:
+		title = nodes.title(text="Architectures")
+		paragraph = nodes.paragraph(text=", ".join(entity.Architectures))
+		section = nodes.section(
+			"",
+			title,
+			paragraph,
+			ids=[f"{entity.NormalizedIdentifier}-architectures"],
+			classes=["vhdl", "vhdl-entity-architectures-section"]
+		)
+
+		return section
+
+	def CreateReferencedBySection(self, entity: Entity) -> section:
+		title = nodes.title(text="Referenced By")
+		paragraph = nodes.paragraph(text="list of usages and back links")
+		section = nodes.section(
+			"",
+			title,
+			paragraph,
+			ids=[f"{entity.NormalizedIdentifier}-referenced-by"],
+			classes=["vhdl", "vhdl-entity-referencedby-section"]
+		)
+
+		return section
+
+	def CreateInnerHierarchySection(self, entity: Entity) -> section:
+		title = nodes.title(text="Inner Hierarchy")
+		paragraph = nodes.paragraph(text="diagram of inner instances")
+		section = nodes.section(
+			"",
+			title,
+			paragraph,
+			ids=[f"{entity.NormalizedIdentifier}-hierarchy"],
+			classes=["vhdl", "vhdl-entity-innerhierarchy-section"]
+		)
+
+		return section
+
+	def ParseParameterStyleOption(self, optionName: str) -> ParameterStyle:
+		try:
+			option = self.options[optionName]
+		except KeyError:
+			try:
+				option = self.defaultValues[optionName]
+			except KeyError:
+				return ParameterStyle.Table
+
+		if option == "never":
+			return ParameterStyle.Never
+		elif option == "table":
+			return ParameterStyle.Table
+		elif option == "sections":
+			return ParameterStyle.Sections
+		else:
+			raise ValueError(f"value '{option}' is not in list of choices: never, table, sections.")
+
+	def ParseArchitecturesStyleOption(self, optionName: str) -> ArchitecturesStyle:
+		try:
+			option = self.options[optionName]
+		except KeyError:
+			try:
+				option = self.defaultValues[optionName]
+			except KeyError:
+				return ArchitecturesStyle.Multiple
+
+		if option == "never":
+			return ArchitecturesStyle.Never
+		elif option == "multiple":
+			return ArchitecturesStyle.Multiple
+		elif option == "always":
+			return ArchitecturesStyle.Always
+		else:
+			raise ValueError(f"value '{option}' is not in list of choices: never, multiple, always.")
+
+	def ParseBooleanOption(self, optionName: str, default: bool) -> bool:
+		try:
+			option = self.options[optionName]
+		except KeyError:
+			try:
+				option = self.defaultValues[optionName]
+			except KeyError:
+				return default
+
+		if option in ("yes", "true"):
+			return True
+		elif option in ("no", "false"):
+			return False
+		else:
+			raise ValueError(f"Value '{option}' not supported for a boolean value (yes/true, no/false).")
+
+	def run(self) -> List[Node]:
+		from VHDLDomain import Design
+
+		if len(self.arguments) == 1:
+			try:
+				libraryName, entityName = self.arguments[0].split(".")
+			except ValueError:
+				raise ValueError(f"Parameter to 'vhdl:describeentity' has incorrect format.")
+		else:
+			raise ValueError(f"Parameter to 'vhdl:describeentity' directive has too many content lines ({len(self.arguments)}).")
+
+		# TODO: Can this be done in an __init__ or so?
+		self.directiveName = self.name.split(":")[1]
+		self.defaultValues = self.env.config.vhdl_defaults[self.directiveName]
+
+		optionDefinition = self.ParseBooleanOption("definition", True)
+		optionGenerics = self.ParseParameterStyleOption("genericlist")
+		optionPorts = self.ParseParameterStyleOption("portlist")
+		optionArchitectures = self.ParseArchitecturesStyleOption("architectures")
+		optionReferencedBy = self.ParseBooleanOption("referencedby", True)
+		optionHierarchy = self.ParseBooleanOption("hierarchy", True)
+
+		vhdlDomain: Domain = self.env.domains["vhdl"]
+		designs: Dict[str, Design] = vhdlDomain.data["designs"]
+		design = designs["StopWatch"]
+		library = design.GetLibrary(libraryName.lower())
+		entity = library.Entities[entityName.lower()]
+
+		content = [
+			nodes.title(text=entity.Identifier),
+			nodes.paragraph(text=entity.Documentation)
+		]
+
+		if optionDefinition:
+			content.append(self.CreateDefinitionSection(entity))
+
+		if optionGenerics is not ParameterStyle.Never:
+			content.append(self.CreateGenericSection(entity, optionGenerics))
+		if optionPorts is not ParameterStyle.Never:
+			content.append(self.CreatePortSection(entity, optionPorts))
+
+		if (optionArchitectures is ArchitecturesStyle.Always or
+			(optionArchitectures is ArchitecturesStyle.Multiple and len(entity.Architectures) > 1)):
+			content.append(self.CreateArchitectureSection(entity))
+
+		if optionReferencedBy:
+			content.append(self.CreateReferencedBySection(entity))
+
+		if optionHierarchy:
+			content.append(self.CreateInnerHierarchySection(entity))
+
+		entitySection = nodes.section(
+			ids=[entity.NormalizedIdentifier],
+			classes=["vhdl", "vhdl-entity-section"]
+		)
+		entitySection.extend(content)
+
+		return [entitySection]
+
+
+@export
+class DescribeArchitecture(BaseDirective):
+	"""
+	This directive will be replaced by the description of a VHDL architecture.
+	"""
+
+	has_content = False
+	required_arguments = 0
+	optional_arguments = 0
+
+	def run(self) -> List[Node]:
+		from VHDLDomain import Design
+
+		vhdlDomain: Domain = self.env.domains["vhdl"]
+		designs: Dict[str, Design] = vhdlDomain.data["designs"]
+		design = designs["StopWatch"]
+
+		paragraph = nodes.paragraph(text="Describe architecture")
+
+		return [paragraph]
+
+
+@export
+class DescribePackage(BaseDirective):
+	"""
+	This directive will be replaced by the description of a VHDL package.
+	"""
+
+	has_content = False
+	required_arguments = 0
+	optional_arguments = 2
+
+	option_spec = {
+		"genericlist":   strip,
+		"referencedby":  strip,
+	}
+
+	def run(self) -> List[Node]:
+		from VHDLDomain import Design
+
+		vhdlDomain: Domain = self.env.domains["vhdl"]
+		designs: Dict[str, Design] = vhdlDomain.data["designs"]
+		design = designs["StopWatch"]
+
+		paragraph = nodes.paragraph(text="Describe package")
+
+		return [paragraph]
+
+
+@export
+class DescribePackageBody(BaseDirective):
+	"""
+	This directive will be replaced by the description of a VHDL package body.
+	"""
+
+	has_content = False
+	required_arguments = 0
+	optional_arguments = 0
+
+	def run(self) -> List[Node]:
+		from VHDLDomain import Design
+
+		vhdlDomain: Domain = self.env.domains["vhdl"]
+		designs: Dict[str, Design] = vhdlDomain.data["designs"]
+		design = designs["StopWatch"]
+
+		paragraph = nodes.paragraph(text="Describe package body")
+
+		return [paragraph]
+
+
+@export
+class DescribeConfiguration(BaseDirective):
+	"""
+	This directive will be replaced by the description of a VHDL configuration.
+	"""
+
+	has_content = False
+	required_arguments = 0
+	optional_arguments = 1
+
+	option_spec = {
+		"referencedby":  strip,
+	}
+
+	def run(self) -> List[Node]:
+		from VHDLDomain import Design
+
+		vhdlDomain: Domain = self.env.domains["vhdl"]
+		designs: Dict[str, Design] = vhdlDomain.data["designs"]
+		design = designs["StopWatch"]
+
+		paragraph = nodes.paragraph(text="Describe configuration")
+
+		return [paragraph]
diff --git a/VHDLDomain/Index.py b/VHDLDomain/Index.py
index 4f2f160..56d3506 100644
--- a/VHDLDomain/Index.py
+++ b/VHDLDomain/Index.py
@@ -1,41 +1,220 @@
-from typing import Iterable, Optional as Nullable, List, Tuple
-
+# ==================================================================================================================== #
+# __     ___   _ ____  _     ____                        _                                                             #
+# \ \   / / | | |  _ \| |   |  _ \  ___  _ __ ___   __ _(_)_ __                                                        #
+#  \ \ / /| |_| | | | | |   | | | |/ _ \| '_ ` _ \ / _` | | '_ \                                                       #
+#   \ V / |  _  | |_| | |___| |_| | (_) | | | | | | (_| | | | | |                                                      #
+#    \_/  |_| |_|____/|_____|____/ \___/|_| |_| |_|\__,_|_|_| |_|                                                      #
+#                                                                                                                      #
+# ==================================================================================================================== #
+# Authors:                                                                                                             #
+#   Patrick Lehmann                                                                                                    #
+#                                                                                                                      #
+# License:                                                                                                             #
+# ==================================================================================================================== #
+# Copyright 2017-2023 Patrick Lehmann - Boetzingen, Germany                                                            #
+# Copyright 2016-2017 Patrick Lehmann - Dresden, Germany                                                               #
+#                                                                                                                      #
+# Licensed under the Apache License, Version 2.0 (the "License");                                                      #
+# you may not use this file except in compliance with the License.                                                     #
+# You may obtain a copy of the License at                                                                              #
+#                                                                                                                      #
+#   http://www.apache.org/licenses/LICENSE-2.0                                                                         #
+#                                                                                                                      #
+# Unless required by applicable law or agreed to in writing, software                                                  #
+# distributed under the License is distributed on an "AS IS" BASIS,                                                    #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.                                             #
+# See the License for the specific language governing permissions and                                                  #
+# limitations under the License.                                                                                       #
+#                                                                                                                      #
+# SPDX-License-Identifier: Apache-2.0                                                                                  #
+# ==================================================================================================================== #
+#
+"""
+**A Sphinx domain providing VHDL language support.**
+
+This module contains all the indices of the VHDL domain.
+"""
+from typing import Iterable, Optional as Nullable, List, Tuple, Dict
+
+from pyGHDL.dom.NonStandard import Design
+from pyTooling.Decorators import export
+from pyVHDLModel import DesignUnitKind
 from sphinx.domains import Index, IndexEntry
 
 
-class ComponentIndex(Index):
-	name =      "componentindex"
+@export
+class BaseIndex(Index):
+	pass
+
+
+@export
+class LibraryIndex(BaseIndex):
+	"""
+	An index for VHDL libraries.
+	"""
+
+	name =      "libindex"
+	localname = "Library Index"
+	shortname = "Libraries"
+
+	def generate(self, docnames: Iterable[str] = None) -> Tuple[List[Tuple[str, List[IndexEntry]]], bool]:
+		result: List[Tuple[str, List[IndexEntry]]] = []
+
+		designs: Dict[str, Design] = self.domain.data["designs"]
+		design = designs["StopWatch"]
+		for library in design.Libraries.values():
+			entries = []
+			for entity in library.Entities.values():
+				entryName = entity.Identifier
+				entryKind = 0 if len(entity.Architectures) == 1 else 1
+				document = f"{entity.Library.Identifier}/{entity.Identifier}"
+				link = f"{entity.Library.Identifier}-{entity.Identifier}"
+				entries.append((entryName, entryKind, document, link, document, "", entity.Documentation))
+				if entryKind == 1:
+					for architecture in entity.Architectures.values():
+						architectureName = architecture.Identifier
+						architectureKind = 2
+						doc = f"{entity.Library.Identifier}/{entity.Identifier}-{architecture.Identifier}"
+						lnk = f"{entity.Library.Identifier}-{entity.Identifier}-{architecture.Identifier}"
+						entries.append((architectureName, architectureKind, doc, lnk, doc, "", architecture.Documentation))
+
+			group = (library.Identifier, entries)
+			result.append(group)
+
+		return result, True
+
+
+@export
+class DocumentIndex(BaseIndex):
+	"""
+	An index for VHDL documents.
+	"""
+
+	name =      "fileindex"
+	localname = "Document Index"
+	shortname = "Documents"
+
+	def generate(self, docnames: Iterable[str] = None) -> Tuple[List[Tuple[str, List[IndexEntry]]], bool]:
+		result: List[Tuple[str, List[IndexEntry]]] = []
+
+		designs: Dict[str, Design] = self.domain.data["designs"]
+		design = designs["StopWatch"]
+		for library in design.Libraries.values():
+			entries = []
+			for entity in library.Entities.values():
+				entryName = entity.Identifier
+				entryKind = 0 if len(entity.Architectures) == 1 else 1
+				document = f"{entity.Library.Identifier}/{entity.Identifier}"
+				link = f"{entity.Library.Identifier}-{entity.Identifier}"
+				entries.append((entryName, entryKind, document, link, document, "", entity.Documentation))
+				if entryKind == 1:
+					for architecture in entity.Architectures.values():
+						architectureName = architecture.Identifier
+						architectureKind = 2
+						doc = f"{entity.Library.Identifier}/{entity.Identifier}-{architecture.Identifier}"
+						lnk = f"{entity.Library.Identifier}-{entity.Identifier}-{architecture.Identifier}"
+						entries.append((architectureName, architectureKind, doc, lnk, doc, "", architecture.Documentation))
+
+			group = (library.Identifier, entries)
+			result.append(group)
+
+		return result, True
+
+
+@export
+class ComponentIndex(BaseIndex):
+	"""
+	An index for VHDL components.
+	"""
+
+	name =      "compindex"
 	localname = "Component Index"
 	shortname = "Components"
 
 	def generate(self, docnames: Iterable[str] = None) -> Tuple[List[Tuple[str, List[IndexEntry]]], bool]:
 		result: List[Tuple[str, List[IndexEntry]]] = []
 
+		designs: Dict[str, Design] = self.domain.data["designs"]
+		design = designs["StopWatch"]
+		for library in design.Libraries.values():
+			entries = []
+			for entity in library.Entities.values():
+				entryName = entity.Identifier
+				entryKind = 0 if len(entity.Architectures) == 1 else 1
+				document = f"{entity.Library.Identifier}/{entity.Identifier}"
+				link = f"{entity.Library.Identifier}-{entity.Identifier}"
+				entries.append((entryName, entryKind, document, link, document, "", entity.Documentation))
+				if entryKind == 1:
+					for architecture in entity.Architectures.values():
+						architectureName = architecture.Identifier
+						architectureKind = 2
+						doc = f"{entity.Library.Identifier}/{entity.Identifier}-{architecture.Identifier}"
+						lnk = f"{entity.Library.Identifier}-{entity.Identifier}-{architecture.Identifier}"
+						entries.append((architectureName, architectureKind, doc, lnk, doc, "", architecture.Documentation))
+
+			group = (library.Identifier, entries)
+			result.append(group)
+
 		return result, True
 
-class PackageIndex(Index):
-	name =      "packageindex"
+
+@export
+class PackageIndex(BaseIndex):
+	"""
+	An index for VHDL packages.
+	"""
+
+	name =      "packindex"
 	localname = "Package Index"
 	shortname = "Packages"
 
 	def generate(self, docnames: Iterable[str] = None) -> Tuple[List[Tuple[str, List[IndexEntry]]], bool]:
 		result: List[Tuple[str, List[IndexEntry]]] = []
 
+		designs: Dict[str, Design] = self.domain.data["designs"]
+		design = designs["StopWatch"]
+		for library in design.Libraries.values():
+			entries = []
+			for package in library.Packages.values():
+				entryName = package.Identifier
+				entryKind = 0
+				document = f"{package.Library.Identifier}/{package.Identifier}"
+				link = f"{package.Library.Identifier}-{package.Identifier}"
+				entries.append((entryName, entryKind, document, link, document, "", package.Documentation))
+
+			group = (library.Identifier, entries)
+			result.append(group)
+
 		return result, True
 
 
-class SubprogramIndex(Index):
-	name =      "subprogramindex"
+@export
+class SubprogramIndex(BaseIndex):
+	"""
+	An index for VHDL functions or procedures.
+	"""
+
+	name =      "subindex"
 	localname = "Subprogram Index"
 	shortname = "Subprograms"
 
 	def generate(self, docnames: Iterable[str] = None) -> Tuple[List[Tuple[str, List[IndexEntry]]], bool]:
 		result: List[Tuple[str, List[IndexEntry]]] = []
 
+		entry = ("binary2onehot", 0, "lib_Utilities/binary2onehot", "lib_Utilities-binary2onehot", "lib_Utilities/binary2onehot", "", "Conversion from binary to onehot code.")
+		group = ("B", [entry])
+
+		result.append(group)
+
 		return result, True
 
 
-class TypeIndex(Index):
+@export
+class TypeIndex(BaseIndex):
+	"""
+	An index for types and subtypes in VHDL.
+	"""
+
 	name =      "typeindex"
 	localname = "Type Index"
 	shortname = "Types"
@@ -43,4 +222,9 @@ class TypeIndex(Index):
 	def generate(self, docnames: Iterable[str] = None) -> Tuple[List[Tuple[str, List[IndexEntry]]], bool]:
 		result: List[Tuple[str, List[IndexEntry]]] = []
 
+		entry = ("BCD", 0, "lib_Utilities/BCD", "lib_Utilities-BCD", "lib_Utilities/BCD", "", "Binary coded decimal.")
+		group = ("B", [entry])
+
+		result.append(group)
+
 		return result, True
diff --git a/VHDLDomain/vhdldomain.py b/VHDLDomain/Role.py
similarity index 67%
rename from VHDLDomain/vhdldomain.py
rename to VHDLDomain/Role.py
index a2d773c..fe4eef0 100644
--- a/VHDLDomain/vhdldomain.py
+++ b/VHDLDomain/Role.py
@@ -29,3 +29,134 @@
 # SPDX-License-Identifier: Apache-2.0                                                                                  #
 # ==================================================================================================================== #
 #
+"""
+**A Sphinx domain providing VHDL language support.**
+
+This module contains all the roles of the VHDL domain.
+"""
+from pyTooling.Decorators import export
+from sphinx.roles import XRefRole
+
+
+@export
+class BaseRole(XRefRole):
+	pass
+
+
+@export
+class DesignRole(BaseRole):
+	"""
+	This role will reference a VHDL design.
+	"""
+
+
+@export
+class LibraryRole(BaseRole):
+	"""
+	This role will reference a VHDL library.
+	"""
+
+
+@export
+class DocumentRole(BaseRole):
+	"""
+	This role will reference a VHDL document.
+	"""
+
+
+@export
+class ContextRole(BaseRole):
+	"""
+	This role will reference a context.
+	"""
+
+
+@export
+class EntityRole(BaseRole):
+	"""
+	This role will reference a entity.
+	"""
+
+
+@export
+class ArchitectureRole(BaseRole):
+	"""
+	This role will reference an architecture.
+	"""
+
+
+@export
+class ComponentRole(BaseRole):
+	"""
+	This role will reference a component.
+	"""
+
+
+@export
+class PackageRole(BaseRole):
+	"""
+	This role will reference a package.
+	"""
+
+
+@export
+class PackageBodyRole(BaseRole):
+	"""
+	This role will reference a package body.
+	"""
+
+
+@export
+class ConfigurationRole(BaseRole):
+	"""
+	This role will reference a configuration.
+	"""
+
+
+@export
+class TypeRole(BaseRole):
+	"""
+	This role will reference a type.
+	"""
+
+
+@export
+class FunctionRole(BaseRole):
+	"""
+	This role will reference a function.
+	"""
+
+
+@export
+class ProcedureRole(BaseRole):
+	"""
+	This role will reference a procedure.
+	"""
+
+
+@export
+class ConstantRole(BaseRole):
+	"""
+	This role will reference a constant.
+	"""
+
+
+@export
+class GenericRole(BaseRole):
+	"""
+	This role will reference a generic.
+	"""
+
+
+@export
+class PortRole(BaseRole):
+	"""
+	This role will reference a port.
+	"""
+
+
+@export
+class ParameterRole(BaseRole):
+	"""
+	This role will reference a parameter.
+	"""
diff --git a/VHDLDomain/__init__.py b/VHDLDomain/__init__.py
index 176174b..3691c71 100644
--- a/VHDLDomain/__init__.py
+++ b/VHDLDomain/__init__.py
@@ -44,30 +44,228 @@
 __license__ =   "Apache License, Version 2.0"
 __version__ =   "0.1.0"
 
+from pathlib import Path
+from typing import Dict, Tuple, Any, Optional as Nullable, cast
+
+from docutils import nodes
+from pyGHDL.dom.NonStandard import Design as DOMDesign, Document as DOMDocument
+from pyTooling.Decorators import export
+from sphinx.addnodes import pending_xref
 from sphinx.application import Sphinx
+from sphinx.builders import Builder
 from sphinx.domains import Domain
+from sphinx.environment import BuildEnvironment
+from sphinx.extension import Extension
+
+from VHDLDomain.Directive import DescribeDesign, DescribeLibrary, DescribeDocument, DescribeEntity, DescribeArchitecture
+from VHDLDomain.Directive import DescribePackage, DescribePackageBody, DescribeConfiguration, DescribeContext
+from VHDLDomain.Index import LibraryIndex, DocumentIndex, ComponentIndex, PackageIndex, SubprogramIndex, TypeIndex
+from VHDLDomain.Role import DesignRole, LibraryRole, DocumentRole, ContextRole, EntityRole, ArchitectureRole, PackageRole, PackageBodyRole, ConfigurationRole
+
+
+@export
+class Design(DOMDesign):
+	_baseDirectory: Nullable[Path]
+
+	def __init__(self, name: str = None, baseDirectory: Path = None):
+		"""
+		Initializes a VHDL design.
 
-from VHDLDomain.Index import ComponentIndex, PackageIndex, SubprogramIndex, TypeIndex
+		:param name:          Name of the design.
+		:param baseDirectory: Base directory of the design.
+		"""
+		super().__init__(name)
+		self._baseDirectory = baseDirectory
 
+	@property
+	def BaseDirectory(self) -> Path:
+		return self._baseDirectory
 
+
+@export
+class Document(DOMDocument):
+	@property
+	def ShortPath(self) -> Path:
+		design = cast(Design, self.Parent)
+		if design._baseDirectory is None:
+			return self._path
+		else:
+			return self._path.relative_to(design._baseDirectory)
+
+
+@export
 class VHDLDomain(Domain):
-	name =  "vhdl"
-	label = "VHDL"
-	initial_data = {}
-	directives = {}
-	roles = {}
+	name =  "vhdl"  #: The name of this domain
+	label = "VHDL"  #: The label of this domain
+
+	dependencies = [
+	]  #: A list of other extensions this domain depends on.
+
+	directives = {
+		"describedesign":        DescribeDesign,
+		# "describelibrary":       DescribeLibrary,
+		# "describedocument":      DescribeDocument,
+		# "describecontext":       DescribeContext,
+		"describeentity":        DescribeEntity,
+		# "describearchitecture":  DescribeArchitecture,
+		# "describepackage":       DescribePackage,
+		# "describepackagebody":   DescribePackageBody,
+		# "describeconfiguration": DescribeConfiguration,
+	}  #: A dictionary of all directives in this domain.
+
+	roles = {
+		# "design":   DesignRole,
+		# "lib":      LibraryRole,
+		# "doc":      DocumentRole,
+		# "ctx":      ContextRole,
+		"ent":      EntityRole(),
+		# "arch":     ArchitectureRole,
+		# "pack":     PackageRole,
+		# "packbody": PackageBodyRole,
+		# "config":   ConfigurationRole,
+	}  #: A dictionary of all roles in this domain.
+
 	indices = {
+		LibraryIndex,
+		DocumentIndex,
 		ComponentIndex,
 		PackageIndex,
 		SubprogramIndex,
 		TypeIndex
-	}
+	}  #: A dictionary of all indices in this domain.
+
+	configValues: Dict[str, Tuple[Any, str, Any]] = {
+		"designs": ({}, "env", Dict),
+		"defaults": ({}, "env", Dict),
+	}  #: A dictionary of all configuration values used by this domain.
+
+	initial_data = {
+		"designs": {}
+	}  #: A dictionary of all global data fields used by this domain.
+
+	@property
+	def Designs(self) -> Dict[str, Design]:
+		return self.data["designs"]
+
+	@staticmethod
+	def ReadDesigns(sphinxApplication: Sphinx) -> None:
+		"""
+		Call back for Sphinx ``builder-inited`` event.
 
+		This callback will read the configuration variable ``vhdl_designs`` and parse the found VHDL source files.
 
+		.. seealso::
+
+		   Sphinx *builder-inited* event
+		     See http://sphinx-doc.org/extdev/appapi.html#event-builder-inited
+
+		:param sphinxApplication: The Sphinx application.
+		:return:
+		"""
+		print(f"Callback: builder-inited -> ReadDesigns")
+		print(f"[VHDL] Reading designs ...")
+
+		# Get modules to build documentation for
+		designConfigurations: Dict[str, Path] = sphinxApplication.config.vhdl_designs
+		print(designConfigurations)
+		if not designConfigurations:
+			return
+
+		_packageFiles = (
+			("lib_Utilities", Path("Utilities.pkg.vhdl")),
+			("lib_Utilities", Path("Utilities.ctx.vhdl")),
+			("lib_StopWatch", Path("StopWatch.pkg.vhdl")),
+			("lib_StopWatch", Path("StopWatch.ctx.vhdl")),
+		)
+		_encoderFiles = _packageFiles + (
+			("lib_StopWatch", Path("seg7_Encoder.vhdl")),
+			("lib_StopWatch", Path("toplevel.Encoder.vhdl")),
+		)
+		_displayFiles = _packageFiles + (
+			("lib_StopWatch", Path("Counter.vhdl")),
+			("lib_StopWatch", Path("seg7_Encoder.vhdl")),
+			("lib_StopWatch", Path("seg7_Display.vhdl")),
+			("lib_StopWatch", Path("seg7_Display.cfg.vhdl")),
+			("lib_StopWatch", Path("toplevel.Display.vhdl")),
+		)
+		_stopwatchFiles = _packageFiles + (
+			("lib_Utilities", Path("Counter.vhdl")),
+			("lib_StopWatch", Path("seg7_Encoder.vhdl")),
+			("lib_StopWatch", Path("seg7_Display.vhdl")),
+			("lib_StopWatch", Path("seg7_Display.cfg.vhdl")),
+			("lib_StopWatch", Path("StopWatch.vhdl")),
+			("lib_Utilities", Path("sync_Bits.vhdl")),
+			("lib_Utilities", Path("Debouncer.vhdl")),
+			("lib_StopWatch", Path("toplevel.vhdl")),
+		)
+
+		vhdlDomain: Domain = sphinxApplication.env.domains[VHDLDomain.name]
+		designs: Dict[str, Design] = vhdlDomain.data["designs"]
+
+		for designName, designRoot in designConfigurations.items():
+			if not isinstance(designName, str):
+				print(f"[VHDL][ERROR] '{designName}' is not a string.")
+			if not isinstance(designRoot, Path):
+				print(f"[VHDL][ERROR] '{designRoot}' is not a Path.")
+			print(f"[VHDL]   Loading design '{designName}' ...")
+			if not designRoot.exists():
+				print(f"[VHDL][ERROR] Path '{designRoot}' does not exist.")
+			design = Design(designName, designRoot)
+			design.LoadDefaultLibraries()
+			for libraryName, file in _stopwatchFiles:
+				sourceFile = designRoot / file
+
+				print(f"[VHDL]     Parsing '{sourceFile}'")
+				document = Document(sourceFile)
+				design.AddDocument(document, design.GetLibrary(libraryName))
+
+			print(f"[VHDL]     Analyzing design '{designName}' ...")
+			design.Analyze()
+
+			designs[designName] = design
+
+
+# 	@staticmethod
+# 	def ReadDesigns(app: Sphinx, docname: str, source: str) -> None:
+# 		print(f"Callback: source-read -> ReadDesigns")
+# 		print(docname)
+# #		print(source)
+
+	callbacks = {
+		"builder-inited": ReadDesigns,
+		# "source-read": ReadDesigns
+	}  #: A dictionary of all callbacks used by this domain.
+
+	def resolve_xref(
+		self,
+		env: BuildEnvironment,
+		fromdocname: str,
+		builder: Builder,
+		typ: str,
+		target: str,
+		node: pending_xref,
+		contnode: nodes.Element
+	) -> Nullable[nodes.Element]:
+		raise NotImplementedError()
+
+
+@export
 def setup(sphinxApplication: Sphinx):
+	"""
+	Extension setup function registering the VHDL domain in Sphinx.
+
+	:param sphinxApplication: The Sphinx application.
+	:return:                  Dictionary containing the extension version and some properties.
+	"""
 	sphinxApplication.add_domain(VHDLDomain)
-	# sphinxApplication.add_config_value('vhdl_autodoc_source_path', '.', 'env', [str])
+	for eventName, callback in VHDLDomain.callbacks.items():
+		sphinxApplication.connect(eventName, callback)
+	for configName, (configDefault, configRebuilt, configTypes) in VHDLDomain.configValues.items():
+		sphinxApplication.add_config_value(f"{VHDLDomain.name}_{configName}", configDefault, configRebuilt, configTypes)
 
 	return {
-		"version": "0.1"
+		"version": __version__,                          # version of the extension
+		"env_version": int(__version__.split(".")[0]),   # version of the data structure stored in the environment
+		'parallel_read_safe': False,                     # Not yet evaluated, thus false
+		'parallel_write_safe': True,                     # Internal data structure is used read-only, thus no problems will occur by parallel writing.
 	}
diff --git a/doc/Configuration/index.rst b/doc/Configuration/index.rst
new file mode 100644
index 0000000..34f6726
--- /dev/null
+++ b/doc/Configuration/index.rst
@@ -0,0 +1,18 @@
+
+
+Configuration
+#############
+
+The following configuration options can be set in :file:`conf.py`.
+
+designs
+*******
+
+``designs`` is a dictionary of VHDL designs. The key defines the design name and the value is a
+:py:class:`~pathlib.Path` object for the root directory of the design.
+
+.. code-block:: Python
+
+   vhdl_designs = {
+     "StopWatch": Path("StopWatch/src"),
+   }
diff --git a/doc/Dependency.rst b/doc/Dependency.rst
index 0e0f24e..bbc60e4 100644
--- a/doc/Dependency.rst
+++ b/doc/Dependency.rst
@@ -23,7 +23,7 @@ VHDLDomain Package
 +--------------------------------------------------------+-------------+------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------+
 | **Package**                                            | **Version** | **License**                                                                              | **Dependencies**                                                                                                                |
 +========================================================+=============+==========================================================================================+=================================================================================================================================+
-| `pyTooling <https://GitHub.com/pyTooling/pyTooling>`__ | ≥2.11.0     | `Apache License, 2.0 <https://GitHub.com/pyTooling/pyTooling/blob/master/LICENSE.txt>`__ | *None*                                                                                                                          |
+| `pyTooling <https://GitHub.com/pyTooling/pyTooling>`__ | ≥2.12.0     | `Apache License, 2.0 <https://GitHub.com/pyTooling/pyTooling/blob/master/LICENSE.txt>`__ | *None*                                                                                                                          |
 +--------------------------------------------------------+-------------+------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------+
 | `Sphinx <https://GitHub.com/sphinx-doc/sphinx>`__      | ≥5.3.0      | `BSD-2-Clause <https://GitHub.com/sphinx-doc/sphinx/blob/master/LICENSE>`__ |br|         | * ❓`sphinxcontrib-applehelp <>`__                                                                                              |
 |                                                        |             |                                                                                          | * ❓`sphinxcontrib-devhelp <>`__                                                                                                |
@@ -146,7 +146,7 @@ install the mandatory dependencies too.
 +----------------------------------------------------------------------------+--------------+----------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------+
 | **Package**                                                                | **Version**  | **License**                                                                                              | **Dependencies**                                                                                                                                     |
 +============================================================================+==============+==========================================================================================================+======================================================================================================================================================+
-| `pyTooling <https://GitHub.com/pyTooling/pyTooling>`__                     | ≥2.11.0      | `Apache License, 2.0 <https://GitHub.com/pyTooling/pyTooling/blob/main/LICENSE.md>`__                    | *None*                                                                                                                                               |
+| `pyTooling <https://GitHub.com/pyTooling/pyTooling>`__                     | ≥2.12.0      | `Apache License, 2.0 <https://GitHub.com/pyTooling/pyTooling/blob/main/LICENSE.md>`__                    | *None*                                                                                                                                               |
 +----------------------------------------------------------------------------+--------------+----------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------+
 | `wheel <https://GitHub.com/pypa/wheel>`__                                  | ≥0.38.1      | `MIT <https://github.com/pypa/wheel/blob/main/LICENSE.txt>`__                                            | *Not yet evaluated.*                                                                                                                                 |
 +----------------------------------------------------------------------------+--------------+----------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------+
diff --git a/doc/Directives/index.rst b/doc/Directives/index.rst
new file mode 100644
index 0000000..a3f23fb
--- /dev/null
+++ b/doc/Directives/index.rst
@@ -0,0 +1,63 @@
+.. _Directives:
+
+Directives
+##########
+
+.. contents:: Table of Contents
+   :local:
+
+
+vhdl:describedesign
+*******************
+
+.. rst:directive:: describedesign
+
+   .. rst:directive:option:: option1: caption of ToC
+
+
+vhdl:describelibrary
+********************
+
+.. rst:directive:: describelibrary
+
+
+vhdl:describedocument
+*********************
+
+.. rst:directive:: describedocument
+
+
+vhdl:describecontext
+********************
+
+.. rst:directive:: describecontext
+
+
+vhdl:describeentity
+*******************
+
+.. rst:directive:: describeentity
+
+
+vhdl:describearchitecture
+*************************
+
+.. rst:directive:: describearchitecture
+
+
+vhdl:describepackage
+********************
+
+.. rst:directive:: describepackage
+
+
+vhdl:describepackagebody
+************************
+
+.. rst:directive:: describepackagebody
+
+
+vhdl:describeconfiguration
+**************************
+
+.. rst:directive:: describeconfiguration
diff --git a/doc/Indices/index.rst b/doc/Indices/index.rst
new file mode 100644
index 0000000..2235992
--- /dev/null
+++ b/doc/Indices/index.rst
@@ -0,0 +1,27 @@
+.. _Indices:
+
+Indices
+#######
+
+.. contents:: Table of Contents
+   :local:
+
+Component Index
+***************
+
+This index can be referenced via ``:ref:`vhdl-compindex```
+
+Package Index
+*************
+
+This index can be referenced via ``:ref:`vhdl-packindex```
+
+Subprogram Index
+****************
+
+This index can be referenced via ``:ref:`vhdl-subindex```
+
+Type Index
+**********
+
+This index can be referenced via ``:ref:`vhdl-typeindex```
diff --git a/doc/Roles/index.rst b/doc/Roles/index.rst
new file mode 100644
index 0000000..4d5e417
--- /dev/null
+++ b/doc/Roles/index.rst
@@ -0,0 +1,78 @@
+.. _Roles:
+
+Roles
+#####
+
+.. contents:: Table of Contents
+   :local:
+
+vhdl:design
+***********
+
+.. rst:role:: design
+
+   Reference a VHDL design by name.
+
+
+vhdl:lib
+********
+
+.. rst:role:: lib
+
+   Reference a VHDL library by name.
+
+
+vhdl:doc
+********
+
+.. rst:role:: doc
+
+   Reference a VHDL source file by path.
+
+
+vhdl:ctx
+********
+
+.. rst:role:: ctx
+
+   Reference a context by library name and context name.
+
+
+vhdl:ent
+********
+
+.. rst:role:: ent
+
+   Reference a context by library name and entity name.
+
+
+vhdl:arch
+*********
+
+.. rst:role:: arch
+
+   Reference a context by library name, entity name and architecture name.
+
+
+vhdl:pack
+*********
+
+.. rst:role:: pack
+
+   Reference a context by library name and package name.
+
+
+vhdl:packbody
+*************
+
+.. rst:role:: packbody
+
+   Reference a context by library name and package name.
+
+
+vhdl:config
+***********
+
+.. rst:role:: config
+
+   Reference a context by library name and configuration name.
diff --git a/doc/StopWatch/index.rst b/doc/StopWatch/index.rst
new file mode 100644
index 0000000..a853f81
--- /dev/null
+++ b/doc/StopWatch/index.rst
@@ -0,0 +1,32 @@
+.. _EX/StopWatch:
+
+StopWatch
+#########
+
+.. #
+   :ref:`vhdl-compindex`
+   :ref:`vhdl-packindex`
+   :ref:`vhdl-subindex`
+   :ref:`vhdl-typeindex`
+
+.. #vhdl:describedesign::
+
+lib_Utilities
+*************
+
+.. vhdl:describeentity:: 	lib_Utilities.Counter
+
+.. vhdl:describeentity:: 	lib_Utilities.Debouncer
+
+.. vhdl:describeentity:: 	lib_Utilities.sync_Bits
+
+lib_StopWatch
+*************
+
+.. vhdl:describeentity:: 	lib_StopWatch.seg7_Encoder
+
+.. vhdl:describeentity:: 	lib_StopWatch.seg7_Display
+
+.. vhdl:describeentity:: 	lib_StopWatch.StopWatch
+
+.. vhdl:describeentity:: 	lib_StopWatch.toplevel
diff --git a/doc/conf.py b/doc/conf.py
index d736116..7e1f0ba 100644
--- a/doc/conf.py
+++ b/doc/conf.py
@@ -283,6 +283,40 @@
 	},
 }
 
+
+# ==============================================================================
+# AutoAPI.Sphinx
+# ==============================================================================
+vhdl_designs = {
+	"StopWatch": (Path.cwd() / "../examples/StopWatch").resolve(),
+}
+vhdl_defaults = {
+	"describedesign": {},
+	"describelibrary": {},
+	"describedocument": {},
+	"describecontext": {
+		"referencedby":  "yes",          # no, yes
+	},
+	"describeentity": {
+		"generics":      "table",        # never, table, sections
+		"ports":         "table",        # never, table, sections
+		"architectures": "multiple",     # never, multiple, always
+		"referencedby":  "yes",          # no, yes
+	},
+	"describearchitecture": {},
+	"describepackage": {
+		"generics":      "table",        # never, table, sections
+		"referencedby":  "yes",          # no, yes
+	},
+	"describepackagebody": {},
+	"describeconfiguration": {
+		"referencedby":  "yes",          # no, yes
+	},
+	"describesubprogram": {
+		"parameters":    "table",        # never, table, sections
+	},
+}
+
 # for directory in [mod for mod in Path("../VHDLDomain").iterdir() if mod.is_dir() and mod.name != "__pycache__"]:
 # 	print(f"Adding module rule for '{project}.{directory.name}'")
 # 	autoapi_modules[f"{project}.{directory.name}"] = {
diff --git a/doc/index.rst b/doc/index.rst
index 6018d4f..8a11e91 100644
--- a/doc/index.rst
+++ b/doc/index.rst
@@ -48,7 +48,7 @@ This sphinx extension adds a new language domain to Sphinx. It allows the docume
 Use Cases
 *********
 
-TBD
+* Partial or fully automated documentation of VHDL designs.
 
 
 .. _news:
@@ -58,12 +58,12 @@ News
 
 .. only:: html
 
-   Jan. 2023 - Dependency, Hierarchy, Compile Order Analysis
-   =========================================================
+   Jan. 2023 - Initial Implementation of a VHDL Domain
+   ===================================================
 
 .. only:: latex
 
-   .. rubric:: Dependency, Hierarchy, Compile Order Analysis
+   .. rubric:: Initial Implementation of a VHDL Domain
 
 * Connecting pyGHDL.dom, pyVHDLModel and Sphinx with this extension.
 
@@ -122,10 +122,26 @@ License
    :caption: Main Documentation
    :hidden:
 
-   LanguageModel/index
-   Analyze/index
-   DataStructure/index
+   Directives/index
+   Roles/index
+   Indices/index
+   Configuration/index
 
+.. raw:: latex
+
+   \part{Examples}
+
+.. toctree::
+   :caption: Examples
+   :hidden:
+
+   StopWatch/index
+   Libraries <vhdl-libindex>
+   Documents <vhdl-fileindex>
+   Components <vhdl-compindex>
+   Packages <vhdl-packindex>
+   Subprograms <vhdl-subindex>
+   Types <vhdl-typeindex>
 
 .. raw:: latex
 
@@ -143,6 +159,7 @@ License
 
 .. raw:: latex
 
+
    \part{Appendix}
 
 .. toctree::
diff --git a/doc/requirements.txt b/doc/requirements.txt
index 38f2850..25917fd 100644
--- a/doc/requirements.txt
+++ b/doc/requirements.txt
@@ -1,6 +1,6 @@
 -r ../requirements.txt
 
-pyTooling>=2.11.0
+pyTooling>=2.12.0
 
 # Enforce latest version on ReadTheDocs
 sphinx>=5.3.0, <6.0
diff --git a/doc/vhdl-compindex.rst b/doc/vhdl-compindex.rst
new file mode 100644
index 0000000..19b047b
--- /dev/null
+++ b/doc/vhdl-compindex.rst
@@ -0,0 +1,2 @@
+Component Index
+###############
diff --git a/doc/vhdl-fileindex.rst b/doc/vhdl-fileindex.rst
new file mode 100644
index 0000000..c8c4f76
--- /dev/null
+++ b/doc/vhdl-fileindex.rst
@@ -0,0 +1,2 @@
+Document Index
+##############
diff --git a/doc/vhdl-libindex.rst b/doc/vhdl-libindex.rst
new file mode 100644
index 0000000..9261486
--- /dev/null
+++ b/doc/vhdl-libindex.rst
@@ -0,0 +1,2 @@
+Library Index
+#############
diff --git a/doc/vhdl-packindex.rst b/doc/vhdl-packindex.rst
new file mode 100644
index 0000000..26a6a0e
--- /dev/null
+++ b/doc/vhdl-packindex.rst
@@ -0,0 +1,2 @@
+Package Index
+#############
diff --git a/doc/vhdl-subindex.rst b/doc/vhdl-subindex.rst
new file mode 100644
index 0000000..a8dbe25
--- /dev/null
+++ b/doc/vhdl-subindex.rst
@@ -0,0 +1,2 @@
+Subprogram Index
+################
diff --git a/doc/vhdl-typeindex.rst b/doc/vhdl-typeindex.rst
new file mode 100644
index 0000000..c976bb9
--- /dev/null
+++ b/doc/vhdl-typeindex.rst
@@ -0,0 +1,2 @@
+Type Index
+##########
diff --git a/examples/StopWatch/Counter.vhdl b/examples/StopWatch/Counter.vhdl
new file mode 100644
index 0000000..50c7c20
--- /dev/null
+++ b/examples/StopWatch/Counter.vhdl
@@ -0,0 +1,64 @@
+-- :author:  Patrick Lehmann
+-- :license: MIT
+--
+-- A generic counter module used in the StopWatch example.
+--
+library IEEE;
+use     IEEE.std_logic_1164.all;
+use     IEEE.numeric_std.all;
+
+use     work.Utilities_pkg.all;
+
+-- A generic implementation of an up-counting counter.
+entity Counter is
+	generic (
+		MODULO : positive;                -- Modulo value of the modulo N counter.
+		BITS   : natural := log2(MODULO)  -- Number of bits used by the counter output vector. This number is derived from MODULO are can be overwritten with a greater value to achieve a wider output vector.
+	);
+	port (
+		Clock      : in  std_logic;       -- System clock to operate the whole entity.
+		Reset      : in  std_logic;       -- System reset to reset the entire entity.
+		Enable     : in  std_logic;       -- Enable signal to activate the counter.
+
+		Value      : out unsigned(BITS - 1 downto 0);  -- Current state of the counter as unsigned number.
+		WrapAround : out std_logic                     -- Triggered for a single cycle, when counter wraps around.
+	);
+end entity;
+
+
+architecture rtl of Counter is
+	signal CounterValue : unsigned(log2(MODULO) - 1 downto 0) := (others => '0');
+begin
+	process (Clock)
+	begin
+		if rising_edge(Clock) then
+			if ((Reset or WrapAround) = '1') then
+				CounterValue <= (others => '0');
+			elsif (Enable = '1') then
+				CounterValue <= CounterValue + 1;
+			end if;
+		end if;
+	end process;
+
+	Value      <= resize(CounterValue, BITS);
+	WrapAround <= Enable when (CounterValue = MODULO - 1) else '0';
+end architecture;
+
+
+architecture sim of Counter is
+	signal CounterValue : unsigned(log2(MODULO) - 1 downto 0) := (others => '0');
+begin
+	process (Clock)
+	begin
+		if rising_edge(Clock) then
+			if ((Reset or WrapAround) = '1') then
+				CounterValue <= (others => '0');
+			elsif (Enable = '1') then
+				CounterValue <= CounterValue + 1;
+			end if;
+		end if;
+	end process;
+
+	Value      <= resize(CounterValue, BITS);
+	WrapAround <= Enable when (CounterValue = MODULO - 1) else '0';
+end architecture;
diff --git a/examples/StopWatch/Debouncer.vhdl b/examples/StopWatch/Debouncer.vhdl
new file mode 100644
index 0000000..27f8407
--- /dev/null
+++ b/examples/StopWatch/Debouncer.vhdl
@@ -0,0 +1,74 @@
+-- Author:  Patrick Lehmann
+-- License: MIT
+--
+-- A debouncer module to filter input signals for bouncing behavior.
+--
+library IEEE;
+use     IEEE.std_logic_1164.all;
+use     IEEE.numeric_std.all;
+
+context work.Utilities_ctx;
+
+
+entity Debouncer is
+	generic (
+		CLOCK_PERIOD   : time := 10 ns;
+		DEBOUNCE_TIME  : time := 3 ms;
+
+		BITS           : positive;
+		INPUT_SYNC     : boolean := true
+	);
+	port (
+		Clock  : in  std_logic;
+
+		Input  : in  std_logic_vector(BITS - 1 downto 0);
+		Output : out std_logic_vector(BITS - 1 downto 0) := (others => '0')
+	);
+end entity;
+
+architecture rtl of Debouncer is
+	constant DEBOUNCE_COUNTER_MAX  : positive := DEBOUNCE_TIME / (CLOCK_PERIOD* ite(IS_SIMULATION, 20, 1));
+	constant DEBOUNCE_COUNTER_BITS : positive := log2(DEBOUNCE_COUNTER_MAX);
+
+	signal Input_sync : Input'subtype;
+begin
+	assert false report "CLOCK_PERIOD:         " & time'image(CLOCK_PERIOD);
+	assert false report "DEBOUNCE_TIME:        " & time'image(DEBOUNCE_TIME);
+	--assert false report "DEBOUNCE_COUNTER_MAX: " & to_string(10 ns);
+	--assert false report "INTEGER'high:         " & integer'image(integer'high);
+
+	genSync: if INPUT_SYNC generate
+		sync: entity work.sync_Bits
+			generic map (
+				BITS => BITS
+			)
+			port map (
+				Clock  => Clock,
+				Input  => Input,
+				Output => Input_sync
+			);
+	else generate
+		Input_sync <= Input;
+	end generate;
+
+	genBits: for i in Input'range generate
+		signal DebounceCounter         : signed(DEBOUNCE_COUNTER_BITS downto 0) := to_signed(DEBOUNCE_COUNTER_MAX - 3, DEBOUNCE_COUNTER_BITS + 1);
+	begin
+		process (Clock)
+		begin
+			if rising_edge(Clock) then
+				-- restart counter, whenever Input(i) was unstable within DEBOUNCE_TIME_MS
+				if (Input(i) /= Output(i)) then
+					DebounceCounter <= DebounceCounter - 1;
+				else
+					DebounceCounter <= to_signed(DEBOUNCE_COUNTER_MAX - 3, DebounceCounter'length);
+				end if;
+
+				-- latch input bit, if input was stable for DEBOUNCE_TIME_MS
+				if (DebounceCounter(DebounceCounter'high) = '1') then
+					Output(i) <= Input(i);
+				end if;
+			end if;
+		end process;
+	end generate;
+end architecture;
diff --git a/examples/StopWatch/README.md b/examples/StopWatch/README.md
new file mode 100644
index 0000000..97fa026
--- /dev/null
+++ b/examples/StopWatch/README.md
@@ -0,0 +1,15 @@
+# StopWatch
+
+This is the project solution used in PLC2's 5-days class [**Professional VHDL**](https://www.plc2.com/en/training/detail/professional-vhdl).
+It develops step by step a stop watch running on a **Digilent Nexys4 DDR** board
+(new name *Nexys A7*).
+
+See https://github.com/PLC2/Solution-StopWatch for more details.
+
+
+# License
+
+Licensed under [MIT License](LICENSE.md).
+
+---------------
+SPDX-License-Identifier: MIT
diff --git a/examples/StopWatch/StopWatch.ctx.vhdl b/examples/StopWatch/StopWatch.ctx.vhdl
new file mode 100644
index 0000000..af89cfe
--- /dev/null
+++ b/examples/StopWatch/StopWatch.ctx.vhdl
@@ -0,0 +1,11 @@
+-- Author:  Patrick Lehmann
+-- License: MIT
+--
+-- A context summarizing other contexts and a stopwatch package.
+--
+context StopWatch_ctx is
+	library lib_Utilities;
+	context lib_Utilities.Utilities_ctx;
+
+	use work.StopWatch_pkg.all;
+end context;
diff --git a/examples/StopWatch/StopWatch.pkg.vhdl b/examples/StopWatch/StopWatch.pkg.vhdl
new file mode 100644
index 0000000..aaaa1fe
--- /dev/null
+++ b/examples/StopWatch/StopWatch.pkg.vhdl
@@ -0,0 +1,50 @@
+-- Author:  Patrick Lehmann
+-- License: MIT
+--
+-- A package for stopwatch specific types and helper functions.
+--
+library IEEE;
+use     IEEE.std_logic_1164.all;
+use     IEEE.numeric_std.all;
+
+-- Package with stop watch specific types.
+package StopWatch_pkg is
+	subtype T_BCD is unsigned(3 downto 0);
+	type T_BCD_Vector is array(natural range <>) of T_BCD;
+
+	type T_DIGIT_CONFIGURATION is record
+		Modulo : positive;
+		Dot    : std_logic;
+	end record;
+
+	type T_STOPWATCH_CONFIGURATION is array(natural range <>) of T_DIGIT_CONFIGURATION;
+
+	-- Encoder that translates from 4-bit binary (BCD) to 7-segment code.
+	--
+	-- In addition, an optional dot input is supported.
+	component seg7_Encoder is
+		port (
+			BCDValue  : in  T_BCD;
+			Dot       : in  std_logic  := '0';
+
+			Seg7Code  : out std_logic_vector(7 downto 0)
+		);
+	end component;
+
+	component seg7_Display is
+		generic (
+			CLOCK_PERIOD  : time := 10 ns;
+			REFRESH_RATE  : time := 200 us;
+			DIGITS        : positive
+		);
+		port (
+			Clock         : in  std_logic;
+
+			DigitValues   : in  T_BCD_Vector(DIGITS - 1 downto 0);
+			DotValues     : in  std_logic_vector(DIGITS - 1 downto 0) := (others => '0');
+
+			Seg7_Segments : out std_logic_vector(7 downto 0);
+			Seg7_Selects  : out std_logic_vector(DIGITS - 1 downto 0)
+		);
+	end component;
+end package;
diff --git a/examples/StopWatch/StopWatch.vhdl b/examples/StopWatch/StopWatch.vhdl
new file mode 100644
index 0000000..14ad9e8
--- /dev/null
+++ b/examples/StopWatch/StopWatch.vhdl
@@ -0,0 +1,129 @@
+-- Author:  Patrick Lehmann
+-- License: MIT
+--
+-- The stopwatch implementation for seconds and minutes.
+--
+library IEEE;
+use     IEEE.std_logic_1164.all;
+use     IEEE.numeric_std.all;
+
+library lib_Utilities;
+use     lib_Utilities.Utilities_pkg.all;
+
+use     work.StopWatch_pkg.all;
+
+
+entity Stopwatch is
+	generic (
+		CLOCK_PERIOD  : time := 10 ns;
+
+		TIMEBASE      : time;
+		CONFIG        : T_STOPWATCH_CONFIGURATION
+	);
+	port (
+		Clock  : in  std_logic;
+		Reset  : in  std_logic;
+
+		Start  : in  std_logic;
+
+		Digits : out T_BCD_Vector(CONFIG'length - 1 downto 0);
+		Dots   : out std_logic_vector(CONFIG'length - 1 downto 0)
+	);
+end entity;
+
+
+architecture rtl of Stopwatch is
+	type T_STATE is (ST_RESET, ST_IDLE, ST_COUNTING, ST_PAUSE);
+
+	signal State      : T_STATE := ST_IDLE;
+	signal NextState  : T_STATE;
+
+	signal FSM_Reset  : std_logic;
+	signal FSM_Enable : std_logic;
+
+	signal Tick       : std_logic;
+	signal Overflows  : std_logic_vector(CONFIG'length downto 0);
+
+
+begin
+	process(Clock)
+	begin
+		if rising_edge(Clock) then
+			if (Reset = '1') then
+				State <= ST_RESET;
+			else
+				State <= NextState;
+			end if;
+		end if;
+	end process;
+
+	process(State, Start)
+	begin
+		NextState  <= State;
+
+		FSM_Reset  <= '0';
+		FSM_Enable <= '0';
+
+		case State is
+			when ST_RESET =>
+				FSM_Reset <= '1';
+				NextState <= ST_IDLE;
+
+			when ST_IDLE =>
+				if (Start = '1') then
+					NextState <= ST_COUNTING;
+				end if;
+
+			when ST_COUNTING =>
+				FSM_Enable <= '1';
+
+				if (Start = '1') then
+					NextState <= ST_PAUSE;
+				end if;
+
+			when ST_PAUSE =>
+				if (Start = '1') then
+					NextState <= ST_COUNTING;
+				end if;
+
+			when others =>
+				NextState <= ST_RESET;
+
+		end case;
+	end process;
+
+	TimeBaseCnt: entity lib_Utilities.Counter
+		generic map (
+			MODULO     => TIMEBASE / (CLOCK_PERIOD * ite(IS_SIMULATION, 100, 1)),
+			BITS       => 0
+		)
+		port map (
+			Clock      => Clock,
+			Reset      => FSM_Reset,
+			Enable     => FSM_Enable,
+
+			Value      => open,
+			WrapAround => Tick
+		);
+
+	Overflows(0) <= Tick;
+
+	genDigits: for i in CONFIG'range generate
+		cnt: entity lib_Utilities.Counter
+			generic map (
+				MODULO     => CONFIG(i).Modulo,
+				BITS       => Digits(i)'length
+			)
+			port map (
+				Clock      => Clock,
+				Reset      => FSM_Reset,
+				Enable     => Overflows(i),
+
+				Value      => Digits(i),
+				WrapAround => Overflows(i + 1)
+			);
+
+		Dots(i) <= CONFIG(i).Dot;
+	end generate;
+
+end architecture;
diff --git a/examples/StopWatch/Utilities.ctx.vhdl b/examples/StopWatch/Utilities.ctx.vhdl
new file mode 100644
index 0000000..8e8ac87
--- /dev/null
+++ b/examples/StopWatch/Utilities.ctx.vhdl
@@ -0,0 +1,12 @@
+-- Author:  Patrick Lehmann
+-- License: MIT
+--
+-- A context to simplify the usage of packages.
+--
+context Utilities_ctx is
+	library IEEE;
+	use     IEEE.std_logic_1164.all,
+	        IEEE.numeric_std.all;
+
+	use work.Utilities_pkg.all;
+end context;
diff --git a/examples/StopWatch/Utilities.pkg.vhdl b/examples/StopWatch/Utilities.pkg.vhdl
new file mode 100644
index 0000000..b0dcafd
--- /dev/null
+++ b/examples/StopWatch/Utilities.pkg.vhdl
@@ -0,0 +1,115 @@
+-- Author:  Patrick Lehmann
+-- License: MIT
+--
+-- A helper package.
+--
+library IEEE;
+use     IEEE.std_logic_1164.all;
+use     IEEE.numeric_std.all;
+
+
+-- Useful utility functions and types.
+package Utilities_pkg is
+	type freq is range integer'low to integer'high units
+		Hz;
+		kHz = 1000 Hz;
+		MHz = 1000 kHz;
+		GHz = 1000 MHz;
+		THz = 1000 GHz;
+	end units;
+
+	-- deferred constant
+	constant IS_SIMULATION : boolean;
+
+	function ite(condition : boolean; ThenValue : integer; ElseValue : integer) return integer;
+
+	function log2(Value : positive) return positive;
+
+	function bin2onehot(binary : std_logic_vector; bits : natural := 0) return std_logic_vector;
+	function bin2onehot(binary : unsigned;         bits : natural := 0) return std_logic_vector;
+
+	function to_index(value : unsigned; max : positive) return natural;
+	function to_index(value : natural;  max : positive) return natural;
+
+	component Debouncer is
+		generic (
+			CLOCK_PERIOD   : time := 10 ns;
+			DEBOUNCE_TIME  : time := 3 ms;
+
+			BITS           : positive
+		);
+		port (
+			Clock  : in  std_logic;
+
+			Input  : in  std_logic_vector(BITS - 1 downto 0);
+			Output : out std_logic_vector(BITS - 1 downto 0) := (others => '0')
+		);
+	end component;
+end package;
+
+
+package body Utilities_pkg is
+	function simulation return boolean is
+		variable result : boolean := FALSE;
+	begin
+		-- synthesis translate_off
+		result := TRUE;
+		-- synthesis translate_on
+		return result;
+	end function;
+
+	-- deferred constant initialization
+	constant IS_SIMULATION : boolean := simulation;
+
+	function ite(condition : boolean; ThenValue : integer; ElseValue : integer) return integer is
+	begin
+		if condition then
+			return ThenValue;
+		else
+			return ElseValue;
+		end if;
+	end function;
+
+	function log2(Value : positive) return positive is
+		variable twosPower : natural := 1;
+		variable result    : natural := 0;
+	begin
+		while (twosPower < Value) loop
+			twosPower := twosPower * 2;
+			result    := result + 1;
+		end loop;
+		return result;
+	end function;
+
+	function bin2onehot(binary : std_logic_vector; bits : natural := 0) return std_logic_vector is
+	begin
+		return bin2onehot(unsigned(binary), bits);
+	end function;
+
+	function bin2onehot(binary : unsigned; bits : natural := 0) return std_logic_vector is
+		variable result : std_logic_vector(2**binary'length - 1 downto 0) := (others => '0');
+	begin
+		result(to_integer(binary)) := '1';
+
+		if (bits = 0) then
+			return result;
+		else
+			return result(bits - 1 downto 0);
+		end if;
+	end function;
+
+	function to_index(value : unsigned; max : positive) return natural is
+	begin
+		return to_index(to_integer(value), max);
+	end function;
+
+	function to_index(value : natural; max : positive) return natural is
+	begin
+		if (value <= max) then
+			return value;
+		else
+			return max;
+		end if;
+		-- return minimum(value, max);
+	end function;
+end package body;
diff --git a/examples/StopWatch/seg7_Display.cfg.vhdl b/examples/StopWatch/seg7_Display.cfg.vhdl
new file mode 100644
index 0000000..63d0c5e
--- /dev/null
+++ b/examples/StopWatch/seg7_Display.cfg.vhdl
@@ -0,0 +1,16 @@
+-- Author:  Patrick Lehmann
+-- License: MIT
+--
+-- A generic counter module used in the StopWatch example.
+--
+context work.StopWatch_ctx;
+
+
+-- Encoder that translates from 4-bit binary (BCD) to 7-segment code.
+configuration seg7_Display_cfg of seg7_Display is
+	for rtl
+		for enc : seg7_Encoder
+			use entity work.seg7_Encoder(rtl);
+		end for;
+	end for;
+end configuration;
diff --git a/examples/StopWatch/seg7_Display.vhdl b/examples/StopWatch/seg7_Display.vhdl
new file mode 100644
index 0000000..c8fccf0
--- /dev/null
+++ b/examples/StopWatch/seg7_Display.vhdl
@@ -0,0 +1,92 @@
+-- Author:  Patrick Lehmann
+-- License: MIT
+--
+-- A 7-segment display module.
+--
+library IEEE;
+use     IEEE.std_logic_1164.all;
+use     IEEE.numeric_std.all;
+
+library lib_Utilities;
+use     lib_Utilities.Utilities_pkg.all;
+
+use     work.StopWatch_pkg.all;
+
+
+entity seg7_Display is
+	generic (
+		CLOCK_PERIOD  : time := 10 ns;
+		REFRESH_RATE  : time := 200 us;
+		DIGITS        : positive
+	);
+	port (
+		Clock         : in  std_logic;
+
+		DigitValues   : in  T_BCD_Vector(DIGITS - 1 downto 0);
+		DotValues     : in  std_logic_vector(DIGITS - 1 downto 0) := (others => '0');
+
+		Seg7_Segments : out std_logic_vector(7 downto 0);
+		Seg7_Selects  : out std_logic_vector(DIGITS - 1 downto 0)
+	);
+end entity;
+
+
+architecture rtl of seg7_Display is
+	constant TIMEBASE_COUNTER_MAX : positive := REFRESH_RATE / (CLOCK_PERIOD * ite(IS_SIMULATION, 1_000, 1));
+
+	signal Timebase_Counter : unsigned(log2(TIMEBASE_COUNTER_MAX) - 1 downto 0) := (others => '0');
+	signal Timebase_Tick    : std_logic;
+
+	signal Digit_Select     : unsigned(log2(DIGITS) - 1 downto 0) := (others => '0');
+	signal Digit_Select_ov  : std_logic;
+
+	signal Digit            : T_BCD;
+	signal Dot              : std_logic;
+begin
+	-- refresh rate
+	process(Clock)
+	begin
+		if rising_edge(Clock) then
+			if (Timebase_Tick = '1') then
+				Timebase_Counter <= (others => '0');
+			else
+				Timebase_Counter <= Timebase_Counter + 1;
+			end if;
+		end if;
+	end process;
+
+	Timebase_Tick <= '1' when (Timebase_Counter = TIMEBASE_COUNTER_MAX - 1) else '0';
+
+
+	-- counter to select digits (time multiplexing)
+	process(Clock)
+	begin
+		if rising_edge(Clock) then
+			if (Timebase_Tick = '1') then
+				if (Digit_Select_ov = '1') then
+					Digit_Select <= (others => '0'); -- to_unsigned(5, Digit_Select'length);
+				else
+					Digit_Select <= Digit_Select + 1;
+				end if;
+			end if;
+		end if;
+	end process;
+
+	Digit_Select_ov <= '1' when (Digit_Select = DIGITS - 1) else '0';
+
+	-- multiplexer
+	Digit <= DigitValues(to_index(Digit_Select, DigitValues'high));
+	Dot   <= DotValues(to_index(Digit_Select, DotValues'high));
+
+	-- 7-segment encoder
+	enc: component seg7_Encoder
+		port map (
+			BCDValue  => Digit,
+			Dot       => Dot,
+
+			Seg7Code  => Seg7_Segments
+		);
+
+
+	Seg7_Selects <= bin2onehot(Digit_Select, DIGITS);
+end architecture;
diff --git a/examples/StopWatch/seg7_Encoder.vhdl b/examples/StopWatch/seg7_Encoder.vhdl
new file mode 100644
index 0000000..0dc22d0
--- /dev/null
+++ b/examples/StopWatch/seg7_Encoder.vhdl
@@ -0,0 +1,42 @@
+-- Author:  Patrick Lehmann
+-- License: MIT
+--
+-- A 7-segment encoder translating 4-bit binary input to 7-segment code.
+-- In addition, a dot input port is provided to control the 8th port.
+--
+context work.StopWatch_ctx;
+
+
+-- Encoder that translates from 4-bit binary (BCD) to 7-segment code.
+entity seg7_Encoder is
+	port (
+		BCDValue  : in  T_BCD;
+		Dot       : in  std_logic  := '0';
+
+		Seg7Code  : out std_logic_vector(7 downto 0)
+	);
+end entity;
+
+
+architecture rtl of seg7_Encoder is
+begin
+	process(BCDValue, Dot)
+		variable temp : std_logic_vector(6 downto 0);
+	begin
+		case BCDValue is -- segments:  GFEDCBA     -- Segment Pos.   Index Pos.
+			when x"0" =>        temp := "0111111";   --
+			when x"1" =>        temp := "0000110";   --
+			when x"2" =>        temp := "1011011";   -- 	 AAA           000
+			when x"3" =>        temp := "1001111";   -- 	F   B         5   1
+			when x"4" =>        temp := "1100110";   -- 	F   B         5   1
+			when x"5" =>        temp := "1101101";   -- 	 GGG           666
+			when x"6" =>        temp := "1111101";   -- 	E   C         4   2
+			when x"7" =>        temp := "0000111";   -- 	E   C         4   2
+			when x"8" =>        temp := "1111111";   -- 	 DDD  DOT      333  7
+			when x"9" =>        temp := "1101111";   --
+			when others =>      temp := "XXXXXXX";   --
+		end case;
+
+		Seg7Code <= Dot & temp;
+	end process;
+end architecture;
diff --git a/examples/StopWatch/sync_Bits.vhdl b/examples/StopWatch/sync_Bits.vhdl
new file mode 100644
index 0000000..499305e
--- /dev/null
+++ b/examples/StopWatch/sync_Bits.vhdl
@@ -0,0 +1,37 @@
+-- Author:  Patrick Lehmann
+-- License: MIT
+--
+-- A generic multi-FF synchronizer.
+--
+library ieee;
+use     ieee.std_logic_1164.all;
+
+
+-- Multi-stage FF synchronizer
+entity sync_Bits is
+	generic (
+		BITS      : positive              := 1;
+		STAGES    : positive range 2 to 5 := 3
+	);
+	port (
+		Clock     : in  std_logic;
+
+		Input     : in  std_logic_vector(BITS - 1 downto 0);
+		output    : in  std_logic_vector(BITS - 1 downto 0)
+	);
+end entity;
+
+
+architecture rtl of sync_Bits is
+
+begin
+	gen : for i in Input'range generate
+		signal meta   : std_logic := '0';
+		signal ffs    : std_logic_vector(STAGES - 1 downto 1) := (others => '0');
+	begin
+		meta      <= Input(i) when rising_edge(Clock);
+		ffs       <= (ffs(ffs'left downto 1) & meta) when rising_edge(Clock);
+
+		Output(i) <= ffs(ffs'left);
+	end generate;
+end architecture;
diff --git a/examples/StopWatch/toplevel.StopWatch.tb.vhdl b/examples/StopWatch/toplevel.StopWatch.tb.vhdl
new file mode 100644
index 0000000..87cd758
--- /dev/null
+++ b/examples/StopWatch/toplevel.StopWatch.tb.vhdl
@@ -0,0 +1,59 @@
+-- Author:  Patrick Lehmann
+-- License: MIT
+--
+-- A generic counter module used in the StopWatch example.
+--
+library IEEE;
+use     IEEE.std_logic_1164.all;
+use     IEEE.numeric_std.all;
+
+library lib_Utilities;
+use     lib_Utilities.Utilities_pkg.all;
+
+use     work.StopWatch_pkg.all;
+
+
+entity toplevel_tb is
+end entity;
+
+
+architecture tb of toplevel_tb is
+	constant CLOCK_PERIOD : time      := 10 ns;
+
+	signal StopSimulation : std_logic := '0';
+	signal Clock          : std_logic := '1';
+	signal Reset          : std_logic := '1';
+
+	signal StartButton    : std_logic := '0';
+
+begin
+	StopSimulation <= '1' after 30 ms;
+
+	Clock <= (Clock xnor StopSimulation) after CLOCK_PERIOD / 2;
+	Reset <= '0' after 2 us,
+	         '1' after 3 us,
+	         '0' after 20 ms,
+	         '1' after 20 ms + 2 us;
+	StartButton <= '1' after 10 us,
+	               '0' after 15 us,
+	               '1' after 10 ms,
+	               '0' after 10 ms + 1 us,
+	               '1' after 12 ms,
+	               '0' after 12 ms + 2 us,
+	               '1' after 22 ms,
+	               '0' after 22 ms + 2 us;
+
+	DUT: entity lib_StopWatch.toplevel
+		generic map (
+			CLOCK_PERIOD_NS => CLOCK_PERIOD / 1 ns
+		)
+		port map (
+			Clock          => Clock,
+			Reset_n        => Reset,
+
+			Button(0)      => StartButton,
+			Seg7_Cathode_n => open,
+			Seg7_Anode_n   => open
+		);
+
+end architecture;
diff --git a/examples/StopWatch/toplevel.vhdl b/examples/StopWatch/toplevel.vhdl
new file mode 100644
index 0000000..886025e
--- /dev/null
+++ b/examples/StopWatch/toplevel.vhdl
@@ -0,0 +1,120 @@
+-- Author:  Patrick Lehmann
+-- License: MIT
+--
+-- The toplevel entity of the design.
+--
+library IEEE;
+use     IEEE.std_logic_1164.all;
+use     IEEE.numeric_std.all;
+
+library lib_Utilities;
+use     lib_Utilities.Utilities_pkg.all;
+
+use     work.StopWatch_pkg.all;
+
+
+entity toplevel is
+	generic (
+		constant CLOCK_PERIOD       : time := 10 ns
+	);
+	port (
+		NexysA7_SystemClock         : in  std_logic;
+		NexysA7_GPIO_Button_Reset_n : in  std_logic;
+
+		NexysA7_GPIO_Button         : in  std_logic_vector(0 downto 0);
+		NexysA7_GPIO_Seg7_Cathode_n : out std_logic_vector(7 downto 0);
+		NexysA7_GPIO_Seg7_Anode_n   : out std_logic_vector(7 downto 0)
+	);
+end entity;
+
+
+architecture rtl of toplevel is
+	constant STOPWATCH_CONFIGURATION : T_STOPWATCH_CONFIGURATION := (
+		0 => (Modulo => 10, Dot => '0'),
+		1 => (Modulo => 10, Dot => '0'),
+		2 => (Modulo => 10, Dot => '0'),
+		3 => (Modulo =>  6, Dot => '0'),
+		4 => (Modulo => 10, Dot => '0'),
+		5 => (Modulo =>  6, Dot => '0')
+	);
+
+	signal Board_Reset  : std_logic;
+
+	signal Deb_Reset    : std_logic;
+	signal Deb_Start    : std_logic;
+	signal Deb_Start_d  : std_logic := '0';
+	signal Deb_Start_re : std_logic;
+
+	signal Reset        : std_logic;
+	signal Start        : std_logic;
+
+
+	signal Digits  : T_BCD_Vector(STOPWATCH_CONFIGURATION'length - 1 downto 0);
+
+	signal Cathode : std_logic_vector(7 downto 0);
+	signal Anode   : std_logic_vector(Digits'range);
+
+begin
+	-- convert from low-active inputs
+	Board_Reset <= not NexysA7_GPIO_Button_Reset_n;
+
+	-- Debounce input signals
+	deb: component Debouncer
+		generic map (
+			CLOCK_PERIOD  => CLOCK_PERIOD,
+			BITS          => 2
+		)
+		port map (
+			Clock     => NexysA7_SystemClock,
+
+			Input(0)  => Board_Reset,
+			Input(1)  => NexysA7_GPIO_Button(0),
+			Output(0) => Deb_Reset,
+			Output(1) => Deb_Start
+		);
+
+	Reset <= Deb_Reset;
+
+	-- Rising edge detection
+	Deb_Start_d  <= Deb_Start when rising_edge(NexysA7_SystemClock);
+	Deb_Start_re <= not Deb_Start_d and Deb_Start;
+
+	-- renaming
+	Start <= Deb_Start_re;
+
+	-- Stopwatch
+	sw: entity work.Stopwatch
+		generic map (
+			CLOCK_PERIOD  => CLOCK_PERIOD,
+
+			TIMEBASE      => 10 ms,
+			CONFIG        => STOPWATCH_CONFIGURATION
+		)
+		port map (
+			Clock  => NexysA7_SystemClock,
+			Reset  => Reset,
+
+			Start  => Start,
+
+			Digits => Digits
+		);
+
+	-- 7-segment display
+	display: /* configuration */ seg7_Display--_cfg
+		generic map (
+			CLOCK_PERIOD  => CLOCK_PERIOD,
+			DIGITS        => Digits'length
+		)
+		port map (
+			Clock         => NexysA7_SystemClock,
+
+			DigitValues   => Digits,
+
+			Seg7_Segments => Cathode,
+			Seg7_Selects  => Anode
+		);
+
+	-- convert to low-active outputs
+	NexysA7_GPIO_Seg7_Cathode_n <= not Cathode;
+	NexysA7_GPIO_Seg7_Anode_n   <= not ((NexysA7_GPIO_Seg7_Anode_n'high downto Anode'length => '0') & Anode);
+end architecture;
diff --git a/pyproject.toml b/pyproject.toml
index 0075b0c..df1e990 100644
--- a/pyproject.toml
+++ b/pyproject.toml
@@ -1,6 +1,6 @@
 [build-system]
 requires = [
-    "pyTooling >= 2.11.0",
+    "pyTooling >= 2.12.0",
     "setuptools >= 62.3.3",
     "wheel >= 0.38.1"
 ]
diff --git a/requirements.txt b/requirements.txt
index 9b79bd3..792e4e7 100644
--- a/requirements.txt
+++ b/requirements.txt
@@ -1 +1,2 @@
-pyTooling>=2.11.0
+pyTooling>=2.12.0
+pyGHDL