Split pbitcell tests to fix factory.reset() bug.

compiler/tests/04_dummy_pbitcell_test.py → compiler/tests/04_dummy_pbitcell_1rw1r1w_test.py

@@ -24,14 +24,6 @@ def runTest(self):
         from openram.modules import dummy_pbitcell
 
         OPTS.bitcell = "pbitcell"
-        OPTS.num_rw_ports = 1
-        OPTS.num_r_ports = 0
-        OPTS.num_w_ports = 0
-
-        debug.info(2, "Checking dummy bitcell using pbitcell (small cell)")
-        tx = dummy_pbitcell(name="rpbc")
-        self.local_check(tx)
-
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 1

compiler/tests/04_dummy_pbitcell_1rw_test.py

@@ -0,0 +1,43 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2023 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import sys, os
+import unittest
+from testutils import *
+
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
+
+class dummy_pbitcell_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram.modules import dummy_pbitcell
+
+        OPTS.bitcell = "pbitcell"
+        OPTS.num_rw_ports = 1
+        OPTS.num_r_ports = 0
+        OPTS.num_w_ports = 0
+
+        debug.info(2, "Checking dummy bitcell using pbitcell (small cell)")
+        tx = dummy_pbitcell(name="rpbc")
+        self.local_check(tx)
+
+        openram.end_openram()
+
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = openram.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/04_replica_pbitcell_test.py → compiler/tests/04_replica_pbitcell_1rw1r1w_test.py

@@ -24,14 +24,6 @@ def runTest(self):
         from openram.modules import replica_pbitcell
 
         OPTS.bitcell = "pbitcell"
-        OPTS.num_rw_ports = 1
-        OPTS.num_r_ports = 0
-        OPTS.num_w_ports = 0
-
-        debug.info(2, "Checking replica bitcell using pbitcell (small cell)")
-        tx = replica_pbitcell(name="rpbc")
-        self.local_check(tx)
-
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 1

compiler/tests/04_replica_pbitcell_1rw_test.py

@@ -0,0 +1,43 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2023 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import sys, os
+import unittest
+from testutils import *
+
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
+
+class replica_pbitcell_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram.modules import replica_pbitcell
+
+        OPTS.bitcell = "pbitcell"
+        OPTS.num_rw_ports = 1
+        OPTS.num_r_ports = 0
+        OPTS.num_w_ports = 0
+
+        debug.info(2, "Checking replica bitcell using pbitcell (small cell)")
+        tx = replica_pbitcell(name="rpbc")
+        self.local_check(tx)
+
+        openram.end_openram()
+
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = openram.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/14_replica_pbitcell_array_test.py → compiler/tests/14_replica_pbitcell_1rw1r_array_test.py

@@ -31,17 +31,6 @@ def runTest(self):
         a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, rbl=[1, 1], left_rbl=[0], right_rbl=[1])
         self.local_check(a)
 
-        OPTS.bitcell = "pbitcell"
-        OPTS.replica_bitcell = "replica_pbitcell"
-        OPTS.dummy_bitcell = "dummy_pbitcell"
-        OPTS.num_rw_ports = 1
-        OPTS.num_r_ports = 0
-        OPTS.num_w_ports = 0
-
-        debug.info(2, "Testing 4x4 array for pbitcell")
-        a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, rbl=[1, 0], left_rbl=[0])
-        self.local_check(a)
-
         openram.end_openram()
 
 

compiler/tests/14_replica_pbitcell_1rw_array_test.py

@@ -0,0 +1,42 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
+# All rights reserved.
+#
+import sys, os
+import unittest
+from testutils import *
+
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
+
+class replica_pbitcell_array_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        openram.init_openram(config_file, is_unit_test=True)
+
+        OPTS.bitcell = "pbitcell"
+        OPTS.replica_bitcell = "replica_pbitcell"
+        OPTS.dummy_bitcell = "dummy_pbitcell"
+        OPTS.num_rw_ports = 1
+        OPTS.num_r_ports = 0
+        OPTS.num_w_ports = 0
+
+        debug.info(2, "Testing 4x4 array for pbitcell")
+        a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, rbl=[1, 0], left_rbl=[0])
+        self.local_check(a)
+
+        openram.end_openram()
+
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = openram.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())