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Alinhamento com furos KiCad - novo.kicad_pcb
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Alinhamento com furos KiCad - novo.kicad_pcb
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(kicad_pcb (version 20171130) (host pcbnew "(5.1.5)-3")
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(drawings 24)
(tracks 55)
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(nets 7)
)
(page A4 portrait)
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(32 B.Adhes user)
(33 F.Adhes user)
(34 B.Paste user)
(35 F.Paste user)
(36 B.SilkS user)
(37 F.SilkS user)
(38 B.Mask user)
(39 F.Mask user)
(40 Dwgs.User user)
(41 Cmts.User user)
(42 Eco1.User user)
(43 Eco2.User user)
(44 Edge.Cuts user)
(45 Margin user)
(46 B.CrtYd user)
(47 F.CrtYd user)
(48 B.Fab user)
(49 F.Fab user)
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(net_class Default "Esta é a classe de rede padrão."
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(module tunnelAmp:C_6032-28W (layer Top) (tedit 0) (tstamp 5E91E2C3)
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(descr "<b>Chip Capacitor Type KEMET C / EIA 6032-28 Wafe solder</b><p>\nKEMET U / EIA 6032-15")
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(pad + smd rect (at 2.625 0 180) (size 2.75 1.8) (layers Top F.Paste F.Mask)
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(module tunnelAmp:C0603 (layer Top) (tedit 0) (tstamp 5E91E0F4)
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(descr "<b>CAPACITOR</b><p>\nchip")
(path /88676885)
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(fp_line (start 1.473 -0.983) (end 1.473 0.983) (layer Dwgs.User) (width 0.0508))
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(pad 1 smd rect (at -0.85 0) (size 1.1 1) (layers Top F.Paste F.Mask)
(net 1 +9V) (solder_mask_margin 0.1016))
)
(module tunnelAmp:C0603 (layer Top) (tedit 0) (tstamp 5E91E25F)
(at 146.05498 37.46638)
(descr "<b>CAPACITOR</b><p>\nchip")
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(module tunnelAmp:R0603 (layer Top) (tedit 0) (tstamp 5E91E073)
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(descr "<b>RESISTOR</b><p>\nchip")
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(module tunnelAmp:SO08 (layer Top) (tedit 0) (tstamp 5E91E0B6)
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(net 3 GND) (solder_mask_margin 0.1016))
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(net 3 GND) (solder_mask_margin 0.1016))
(pad 1 smd rect (at -1.905 2.6162 270) (size 0.6096 2.2098) (layers Top F.Paste F.Mask)
(solder_mask_margin 0.1016))
)
(module tunnelAmp:1X05 (layer Top) (tedit 0) (tstamp 5E91E159)
(at 158.11998 34.60888 270)
(descr "<b>PIN HEADER</b>")
(path /0B60073D)
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(effects (font (size 0.9652 0.9652) (thickness 0.09652)) (justify left bottom))
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(fp_line (start 3.81 -0.635) (end 3.81 0.635) (layer F.SilkS) (width 0.1524))
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(fp_line (start 1.905 -1.27) (end 3.175 -1.27) (layer F.SilkS) (width 0.1524))
(pad 5 thru_hole oval (at 5.08 0) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask)
(net 2 -9V) (solder_mask_margin 0.1016))
(pad 4 thru_hole oval (at 2.54 0) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask)
(net 3 GND) (solder_mask_margin 0.1016))
(pad 3 thru_hole oval (at 0 0) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask)
(net 4 "Net-(JP1-Pad3)") (solder_mask_margin 0.1016))
(pad 2 thru_hole oval (at -2.54 0) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask)
(net 1 +9V) (solder_mask_margin 0.1016))
(pad 1 thru_hole oval (at -5.08 0) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask)
(net 3 GND) (solder_mask_margin 0.1016))
)
(module tunnelAmp:1,6_0,9 (layer Top) (tedit 0) (tstamp 5E91E1E3)
(at 153.03998 36.51388)
(descr "<b>THROUGH-HOLE PAD</b>")
(path /BDB91568)
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(fp_line (start 0.762 0.762) (end 0.762 0.508) (layer F.SilkS) (width 0.1524))
(fp_line (start 0.508 0.762) (end 0.762 0.762) (layer F.SilkS) (width 0.1524))
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(fp_line (start -0.762 0.508) (end -0.762 0.762) (layer F.SilkS) (width 0.1524))
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(net 5 "Net-(IC1-Pad6)") (solder_mask_margin 0.1016))
)
(gr_text "EXTRA: Better Alignment\n-Add two extra vias 15mm on the upper edge\n" (at 180.7718 30.988) (layer F.SilkS) (tstamp 5EE7BADA)
(effects (font (size 1 1) (thickness 0.15)))
)
(gr_text "3.For double layer: Edit->Invert Board View\n4.Align again\n5.Repeat number 3\n6.Plot mirrored PDF of Back Copper\n" (at 180.4416 18.0594) (layer F.SilkS) (tstamp 5EA1EA64)
(effects (font (size 1 1) (thickness 0.15)))
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(gr_text "0.Board must have straight and thin edge lines and:\n->1 via in each corner + vias in 9.5mm and 14.5mm from top corners\n1.Center to the mid of the 3-4 markings (both x and y)\n2.Ctrl+M: Move 15 mm in Y" (at 162.39998 7.3279) (layer F.SilkS)
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