From c9ec130aefb3380e8faacb683fa957f5b3372971 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 18 Nov 2024 12:05:39 -0800 Subject: [PATCH] Add two testcases that needed fixing (requires Vivado) Signed-off-by: Eddie Hung --- .../rwroute/TestGlobalSignalRouting.java | 94 ++++++++++++++++++- 1 file changed, 93 insertions(+), 1 deletion(-) diff --git a/test/src/com/xilinx/rapidwright/rwroute/TestGlobalSignalRouting.java b/test/src/com/xilinx/rapidwright/rwroute/TestGlobalSignalRouting.java index efd1ae6a4..ac418bd5c 100644 --- a/test/src/com/xilinx/rapidwright/rwroute/TestGlobalSignalRouting.java +++ b/test/src/com/xilinx/rapidwright/rwroute/TestGlobalSignalRouting.java @@ -30,6 +30,7 @@ import com.xilinx.rapidwright.design.SiteInst; import com.xilinx.rapidwright.design.SitePinInst; import com.xilinx.rapidwright.design.Unisim; +import com.xilinx.rapidwright.device.Device; import com.xilinx.rapidwright.device.Node; import com.xilinx.rapidwright.device.SitePin; import com.xilinx.rapidwright.router.RouteThruHelper; @@ -38,6 +39,7 @@ import com.xilinx.rapidwright.util.ReportRouteStatusResult; import com.xilinx.rapidwright.util.VivadoTools; import org.junit.jupiter.api.Assertions; +import org.junit.jupiter.api.Assumptions; import org.junit.jupiter.api.Test; import org.junit.jupiter.api.function.Executable; import org.junit.jupiter.api.io.TempDir; @@ -47,8 +49,8 @@ import java.nio.file.Path; import java.util.ArrayList; +import java.util.Arrays; import java.util.List; -import java.util.function.BiFunction; public class TestGlobalSignalRouting { @ParameterizedTest @@ -225,4 +227,94 @@ public void testRouteStaticNetOnVersalDevice(boolean createStaticPins, @TempDir Assertions.assertEquals(0, rrs.netsWithRoutingErrors); } } + + // This is a minimized testcase from the result of GlobalSignalRouter + @ParameterizedTest + @CsvSource({ + "false,false", + "true,false", + "false,true" + }) + public void testMuxOutPinAsStaticSourceEvenWithLut6(boolean setCmuxCtag, boolean fullIntraSiteRouting) { + Assumptions.assumeTrue(FileTools.isVivadoOnPath()); + + Design design = RapidWrightDCP.loadDCP("optical-flow.dcp"); + Device device = design.getDevice(); + Net gndNet = design.getGndNet(); + boolean srcToSinkOrder = true; + gndNet.setPIPs(RouterHelper.getPIPsFromNodes(Arrays.asList( + device.getNode("CLEM_X52Y123/CLE_CLE_M_SITE_0_CMUX"), + device.getNode("INT_X52Y123/INT_NODE_SDQ_90_INT_OUT1"), + device.getNode("INT_X52Y123/WW1_W_BEG7"), + device.getNode("INT_X51Y124/INODE_E_1_FT1"), + device.getNode("INT_X51Y123/IMUX_E15") + ), srcToSinkOrder)); + SiteInst si = design.getSiteInstFromSiteName("SLICE_X81Y123"); + Cell lut6 = si.getCell("C6LUT"); + Assertions.assertEquals("LUT6", lut6.getType()); + String const0 = ""; + if (setCmuxCtag) { + if (!fullIntraSiteRouting) { + // Setting just the CMUX cTag + si.routeIntraSiteNet(gndNet, si.getBELPin("CMUX", "CMUX"), si.getBELPin("CMUX", "CMUX")); + } else { + // Full O5 -> OUTMUXC -> CMUX intra-site routing + si.routeIntraSiteNet(gndNet, si.getBELPin("C5LUT", "O5"), si.getBELPin("CMUX", "CMUX")); + } + } + + String status = VivadoTools.reportRouteStatus(design, const0); + if (!setCmuxCtag) { + // Not setting the CMUX cTag correctly causes SLICE_X81Y123 to have invalid site programming + Assertions.assertEquals("CONFLICTS", status); + } else { + // In both cases, SLICE_X81Y123 does not exhibit invalid site programming and thus net appears partially routed + Assertions.assertEquals("PARTIAL", status); + } + } + + // This is a minimized testcase from the result of GlobalSignalRouter + @ParameterizedTest + @CsvSource({ + "false,false", + "true,false", + "false,true" + }) + public void testMuxOutPinAsStaticSourceEvenWithLutRam(boolean setFmuxCtag, boolean fullIntraSiteRouting) { + Assumptions.assumeTrue(FileTools.isVivadoOnPath()); + + Design design = RapidWrightDCP.loadDCP("bnn.dcp"); + Device device = design.getDevice(); + Net gndNet = design.getGndNet(); + boolean srcToSinkOrder = true; + gndNet.setPIPs(RouterHelper.getPIPsFromNodes(Arrays.asList( + device.getNode("CLEM_X52Y218/CLE_CLE_M_SITE_0_FMUX"), + device.getNode("INT_X52Y218/SDQNODE_W_2_FT1"), + device.getNode("INT_X52Y218/EE2_W_BEG0"), + device.getNode("INT_X53Y218/INODE_W_1_FT1"), + device.getNode("INT_X53Y217/IMUX_W46"), + device.getNode("BRAM_X53Y215/BRAM_BRAM_CORE_3_ADDRENAU_PIN") + ), srcToSinkOrder)); + SiteInst si = design.getSiteInstFromSiteName("SLICE_X81Y218"); + Cell lutRam = si.getCell("F6LUT"); + Assertions.assertEquals("RAMS64E", lutRam.getType()); + String const0 = "bd_0_i/hls_inst/inst/"; + if (setFmuxCtag) { + if (!fullIntraSiteRouting) { + // Setting just the FMUX cTag + si.routeIntraSiteNet(gndNet, si.getBELPin("FMUX", "FMUX"), si.getBELPin("FMUX", "FMUX")); + } else { + // Full O5 -> OUTMUXF -> FMUX intra-site routing + si.routeIntraSiteNet(gndNet, si.getBELPin("F5LUT", "O5"), si.getBELPin("FMUX", "FMUX")); + } + } + String status = VivadoTools.reportRouteStatus(design, const0); + if (!setFmuxCtag) { + // Not setting the FMUX cTag correctly causes SLICE_X81Y218 to have invalid site programming + Assertions.assertEquals("CONFLICTS", status); + } else { + // In both cases, SLICE_X81Y218 does not exhibit invalid site programming and thus net appears partially routed + Assertions.assertEquals("PARTIAL", status); + } + } }