diff --git a/.classpath b/.classpath index ca1386291..0cc69b6ec 100644 --- a/.classpath +++ b/.classpath @@ -2,9 +2,9 @@ - + - + diff --git a/RELEASE_NOTES.TXT b/RELEASE_NOTES.TXT index ea4b5beb1..3928be1d2 100644 --- a/RELEASE_NOTES.TXT +++ b/RELEASE_NOTES.TXT @@ -1,3 +1,18 @@ +============= RapidWright 2018.2.5-beta released on 2018-11-28 ================= +Notes: + - Fixes an issue in + com.xilinx.rapidwright.device.Tile.getWireConnections() that was + causing an issue when routing clocking routes. This was manifesting + in the SLRCrosserGenerator demo. +Known Issues: + - Netlists that have two ports by same name where one is a single bit + bus and another is multi-bit are not currently supported (for + example, a module has an input 'my_signal' and 'my_signal[2:0]' is + currently not allowed in the EDIF parser. + - Clock router in Router class is disabled (under development). + - PolynomialGenerator is a toy demonstration and does not produce a + functionally valid circuit. + ============= RapidWright 2018.2.4-beta released on 2018-11-15 ================= Notes: - API Additions: