From 1115ddf23e88e1ba13276a08e6449c0a1fba76b6 Mon Sep 17 00:00:00 2001 From: Yaman Umuroglu Date: Thu, 7 Nov 2024 19:14:19 +0100 Subject: [PATCH] [RTLMVU] prototyping support for pyxsi rtlsim --- .../rtl/matrixvectoractivation_rtl.py | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/rtl/matrixvectoractivation_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/matrixvectoractivation_rtl.py index 88249f367..eb6399648 100644 --- a/src/finn/custom_op/fpgadataflow/rtl/matrixvectoractivation_rtl.py +++ b/src/finn/custom_op/fpgadataflow/rtl/matrixvectoractivation_rtl.py @@ -285,8 +285,21 @@ def prepare_codegen_default(self, fpgapart, clk): return template_path, code_gen_dict - def get_rtl_file_list(self): - verilog_files = [self.get_nodeattr("gen_top_module") + "_wrapper_sim.v"] + def get_rtl_file_list(self, abspath=False): + if abspath: + code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") + "/" + rtllib_dir = os.path.join(os.environ["FINN_ROOT"], "finn-rtllib/mvu/") + else: + code_gen_dir = "" + rtllib_dir = "" + verilog_files = [ + code_gen_dir + self.get_nodeattr("gen_top_module") + "_wrapper.v", + rtllib_dir + "mvu_vvu_axi.sv", + rtllib_dir + "replay_buffer.sv", + rtllib_dir + "mvu_4sx4u.sv", + rtllib_dir + "mvu_vvu_8sx9_dsp58.sv", + rtllib_dir + "mvu_8sx8u_dsp48.sv", + ] return verilog_files def get_verilog_paths(self):