From 25443da30260f07bebcd5d0025affb2f1a9f7a85 Mon Sep 17 00:00:00 2001 From: auphelia Date: Tue, 22 Oct 2024 10:37:01 +0100 Subject: [PATCH] [prepare rtlsim] Clean-up functions in rtl mvu and vvu --- .../rtl/matrixvectoractivation_rtl.py | 29 ++++--------------- .../rtl/vectorvectoractivation_rtl.py | 29 ++++--------------- src/finn/custom_op/fpgadataflow/rtlbackend.py | 14 +++++---- 3 files changed, 20 insertions(+), 52 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/rtl/matrixvectoractivation_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/matrixvectoractivation_rtl.py index d9ab501117..b950d5a836 100644 --- a/src/finn/custom_op/fpgadataflow/rtl/matrixvectoractivation_rtl.py +++ b/src/finn/custom_op/fpgadataflow/rtl/matrixvectoractivation_rtl.py @@ -32,7 +32,7 @@ from finn.custom_op.fpgadataflow.matrixvectoractivation import MVAU from finn.custom_op.fpgadataflow.rtlbackend import RTLBackend -from finn.util.basic import get_dsp_block, get_rtlsim_trace_depth, make_build_dir +from finn.util.basic import get_dsp_block from finn.util.data_packing import npy_to_rtlsim_input, rtlsim_output_to_npy try: @@ -282,28 +282,11 @@ def prepare_codegen_default(self, fpgapart, clk): return template_path, code_gen_dict - def prepare_rtlsim(self): - """Creates a Verilator emulation library for the RTL code generated - for this node, sets the rtlsim_so attribute to its path and returns - a PyVerilator wrapper around it.""" - - if PyVerilator is None: - raise ImportError("Installation of PyVerilator is required.") + def get_rtl_file_list(self): + verilog_files = [self.get_nodeattr("gen_top_module") + "_wrapper_sim.v"] + return verilog_files + def get_verilog_paths(self): code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") - # Path to (System-)Verilog files used by top-module & path to top-module verilog_paths = [code_gen_dir, os.environ["FINN_ROOT"] + "/finn-rtllib/mvu"] - verilog_files = [self.get_nodeattr("gen_top_module") + "_wrapper_sim.v"] - - # build the Verilator emu library - sim = PyVerilator.build( - verilog_files, - build_dir=make_build_dir("pyverilator_" + self.onnx_node.name + "_"), - verilog_path=verilog_paths, - trace_depth=get_rtlsim_trace_depth(), - top_module_name=self.get_verilog_top_module_name(), - ) - # save generated lib filename in attribute - self.set_nodeattr("rtlsim_so", sim.lib._name) - - return sim + return verilog_paths diff --git a/src/finn/custom_op/fpgadataflow/rtl/vectorvectoractivation_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/vectorvectoractivation_rtl.py index 32943d86cf..8273978c68 100644 --- a/src/finn/custom_op/fpgadataflow/rtl/vectorvectoractivation_rtl.py +++ b/src/finn/custom_op/fpgadataflow/rtl/vectorvectoractivation_rtl.py @@ -33,7 +33,7 @@ from finn.custom_op.fpgadataflow.rtlbackend import RTLBackend from finn.custom_op.fpgadataflow.vectorvectoractivation import VVAU -from finn.util.basic import get_rtlsim_trace_depth, is_versal, make_build_dir +from finn.util.basic import is_versal from finn.util.data_packing import npy_to_rtlsim_input, rtlsim_output_to_npy try: @@ -274,28 +274,11 @@ def prepare_codegen_default(self, fpgapart, clk): return template_path, code_gen_dict - def prepare_rtlsim(self): - """Creates a Verilator emulation library for the RTL code generated - for this node, sets the rtlsim_so attribute to its path and returns - a PyVerilator wrapper around it.""" - - if PyVerilator is None: - raise ImportError("Installation of PyVerilator is required.") + def get_rtl_file_list(self): + verilog_files = [self.get_nodeattr("gen_top_module") + "_wrapper_sim.v"] + return verilog_files + def get_verilog_paths(self): code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") - # Path to (System-)Verilog files used by top-module & path to top-module verilog_paths = [code_gen_dir, os.environ["FINN_ROOT"] + "/finn-rtllib/mvu"] - verilog_files = [self.get_nodeattr("gen_top_module") + "_wrapper_sim.v"] - - # build the Verilator emu library - sim = PyVerilator.build( - verilog_files, - build_dir=make_build_dir("pyverilator_" + self.onnx_node.name + "_"), - verilog_path=verilog_paths, - trace_depth=get_rtlsim_trace_depth(), - top_module_name=self.get_verilog_top_module_name(), - ) - # save generated lib filename in attribute - self.set_nodeattr("rtlsim_so", sim.lib._name) - - return sim + return verilog_paths diff --git a/src/finn/custom_op/fpgadataflow/rtlbackend.py b/src/finn/custom_op/fpgadataflow/rtlbackend.py index 62b0de46ab..2d4dc7498f 100644 --- a/src/finn/custom_op/fpgadataflow/rtlbackend.py +++ b/src/finn/custom_op/fpgadataflow/rtlbackend.py @@ -60,8 +60,7 @@ def prepare_rtlsim(self): if PyVerilator is None: raise ImportError("Installation of PyVerilator is required.") - code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") - verilog_paths = [code_gen_dir] + verilog_paths = self.get_verilog_paths() verilog_files = self.get_rtl_file_list() # build the Verilator emu library @@ -76,10 +75,13 @@ def prepare_rtlsim(self): self.set_nodeattr("rtlsim_so", sim.lib._name) return sim - # TODO: enable all rtl nodes to use parent function - # @abstractmethod - # def get_rtl_file_list(self): - # pass + def get_verilog_paths(self): + code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") + return [code_gen_dir] + + @abstractmethod + def get_rtl_file_list(self): + pass @abstractmethod def code_generation_ipi(self):