Alveo U50 stat_rx_status always 192

[victornvq2]

Hi All,
Completed build project on Alveo U50, however when on run ./ping_fpga it always returns 192 of cmac stat_rx_status, no matter how many time I try to test, thus the link never become ready, thus the local ping failed !
Please advise

Whishing you guys having a good day !
Victor

[victornvq2]

The test tool is ping_fpga that was compiled from xrt_host_api directory. It seems that cmac uplus uplus IP is not ready yet. Any hint would be appreciated !

[mariodruiz]

Hi @victornvq2,

You may need to provide more information.
What is your setup? Where did you connected the QSFP28 port to?

Mario

[victornvq2]

Hi Mario,

We have 2 development PC that have Alveo U50 on each of them. 2 PCs are connected via a Cisco QSFP+ DAC cable

1. We've build open-nic-shell and open-nic-driver on each PC, testing network card on Alveo U50. Everything works fine, we are able to ping, send + receive TCP and UDP packets at rate 15 Gbps
2. Now on one PC, we rebuild xup_vitis_networking by using Vitis 2022.1 with modifying scripts for Alveo U50. the Basic design built went fine with xclbin were generated successfully
3. We have built the xrt_host_api client then run ./ping_fpga <basic.xclbin file> but it was unsuccessful to ping the localhost
   While trying to find the problem, we found that start_rx_status always 192, it never goes down to 3
   When I try to modify to ping another PC, it also was unsuccessfully

During the testing we always kept the connection between 2 PCs with Cisco QSFP+ DAC cable that 's working with Open NIC build.

4. For device validation:
   [osp@fpga-msi build_ip]$ xbutil validate --device 0000:01:00.1
   Starting validation for 1 devices

Validate Device : [0000:01:00.1]
Platform : xilinx_u50_gen3x16_xdma_base_5
SC Version : 5.2.18
Platform ID : 44654095-25B4-C06A-EC6D-0B479D3FEBE8

Test 1 [0000:01:00.1] : pcie-link
Test Status : [PASSED]

Test 2 [0000:01:00.1] : sc-version
Test Status : [PASSED]

Test 3 [0000:01:00.1] : verify
Test Status : [PASSED]

Test 4 [0000:01:00.1] : dma
Details : Buffer size - '16 MB'
Host -> PCIe -> FPGA write bandwidth = 10095.0 MB/s
Host <- PCIe <- FPGA read bandwidth = 12008.6 MB/s
Test Status : [PASSED]

Test 5 [0000:01:00.1] : iops
Details : IOPS: 381623 (verify)
Test Status : [PASSED]

Test 6 [0000:01:00.1] : mem-bw
Details : Throughput (Type: HBM) (Bank count: 1) : 12383.8MB/s
Test Status : [PASSED]

Test 7 [0000:01:00.1] : vcu
Validation completed. Please run the command '--verbose' option for more details

I guest there's could be some different settings between Vivado flow and Vitis kernel flow, but don't know how extractly to fix it.

Please advise !

Victor

[mariodruiz]

Hi Victor,

As you are using the switch, you need to read this part of the FAQ https://github.com/Xilinx/xup_vitis_network_example#alveo-card-connected-to-a-100g-capable-switchnic-is-not-getting-link

FEC and Auto negotiation aren't enable in VNx, so the switch has to have these capabilities disabled as well. If you connect the two Alveo directly, you will get link. This happens all the time, hence it is included in the FAQ. Previous case here #32 (comment)

Mario

[victornvq2]

Mario, thank you. I will try that
Best,

[mariodruiz]

Hi @victornvq2, as part of a community contribution the RS-FEC is enabled by default in the kernel, but not by software. This should make it easier to connect to other network equipment.

Please, check the latest commit and associated documentation

[victornvq2]

hi Mario, thank I will be trying the lastest commit
Thanks,