Synthesis example for Himbaechel Example arch

[KelvinChung2000]

I am currently developing my architecture under Himbaechel. Is it possible to provide a synthesis example similar to generic?

I am currently stuck on an ERROR: No wire found for port dst[4] on source cell $flatten\top_i.$add$./Test/test_design/adding.v:5$2 error, which I believe is caused by incorrect synthesis. It will be helpful to look at the example and deduce what is missing in my synthesis script.

[yrabbit]

Not an expert here, but I believe that nextpnr is weakly dependent on synthesis: gowin for example uses exactly the same synthesis script for subsequent P&R with both nextpnr-gowin and nextpnr-himbaechel.

I think you can just use this script from generic (well, with your cells_map.v and prims.v of course).

And looking at your error message, I have a couple of questions: are you sure that the port named dst[4] can be a source on the network? If so, is there a port in the Bel in which you intend to place this cell and, most importantly, is there a wire in this Bel associated with the dst[4] port?

[KelvinChung2000]

most importantly, is there a wire in this Bel associated with the dst[4] port

I am missing this. The port name on my prims.v does not match the port name of my Bel. So, this is indeed an error due to synthesis.

I now mange to let nextpnr finish normally, I will still need to check is that right. Thanks for your help.