convert verilog to aiger with Yosys

[yagamizxy]

HI, I have several verilog files which I want to convert to aiger format using Yosys, I use the following commmad in yosys:

read_verilog gclk_reg.v nld_and.v my_ff_W_8_.v gated_netlist.v

synth_xilinx -flatten -top gclk_reg

aigmap

write_aiger -ascii my.aag

When I use the aigmap command, it show that cells like VCC LUT2 GND LDCE .etc cannt be replaced. Unsurprisingly, the write_aiger command fails, showing that "ERROR: Unsupported cell type: VCC (VCC)". So how can I map those cells to allowed cells of write_aiger?(I also used the abc -g AND command but it still failed)

Many Thanks!!

[Ravenslofty]

Well, synth_xilinx outputs LUTs, because it's meant to be a full flow. If you're dumping to AIGER you almost certainly do not want to run a full flow, so I'd suggest the generic synth -flatten; aigmap; write_aiger example.aig