Yosys optimization of combinational logic with don't care

[etnapoli]

I'm simulating and synthesizing simple circuits described in VHDL and synthesized with Yosys and web downloaded stdcell libraries.
The minimal working example of the circuit that I'm synthesizing is below.

entity test is port(
A : in std_logic_vector (3 downto 0);
Y : out std_logic);
end;
architecture beh of test is
begin
with A select
Y <= '0' when "0001",
'1' when "0010",
'0' when "0100",
'1' when "1000",
'-' when others;
end beh;

In my opinion, and by using other synthesis software as Quartus, the description simplifies to the logic
Y <= A(1) or A(3);

Bu Yosys produces a more complex circuit that seems to be ignoring the don't care condition and sees the condition as '1'. Indeed it seems that Yosys is synthesizing the following VHDL description:

with A select
Y <= '0' when "0001",
'1' when "0010",
'0' when "0100",
'1' when "1000",
'1' when others;

The Yosis script I'm using is the following:

ghdl test
hierarchy -check -top test
flatten
proc; opt -full; memory; opt -full; fsm; opt -full
techmap; opt -full
read_liberty -lib synth_gates.lib
dfflibmap -liberty synth_gates.lib
abc -liberty synth_gates.lib
splitnets -ports; opt -full
clean -purge

The std_cell library does not really matter since the same happens with three different std_cell libraries.

I can also tell that if the order of the of the lines is changed as:
with A select Y <= '0' when "0001",
'1' when "0010",
'1' when "1000",
'0' when "0100",
'-' when others;

then Yosys treats the dont'care cases as '0'.

[smunaut]

Yosys has never been really good at this. See for instance #765

FWIW, In the end I've had better results by generating truth tables externally, feed those through a logic optimizer and then feed the resulting and/or tree to yosys for lut mapping than leaving yosys do it itself.