VHDL to RTLIL or AST

[moohtuh]

Hello!

Is there any way to get RTLIL or AST from VHDL sources?

I looked at this: https://www.reddit.com/r/yosys/comments/c46qjc/vhdl_ast_representation_and_rtil_conversion/

Does anyone know if this is functional?

Lastly, how do I join chat here : https://webchat.freenode.net/
what should be the channel ?

[eddiehung]

CC @pepijndevos

[pepijndevos]

https://github.com/tgingold/ghdlsynth-beta would be your best bet for reading VHDL into yosys. On a related note, I'd really like to see this merged into yosys at some point. The proper irc channels would be #yosys and ##openfpga , ghdl discussion happens on gitter.

…

On November 22, 2019 9:20:00 PM GMT+01:00, Eddie Hung ***@***.***> wrote: CC @pepijndevos -- You are receiving this because you were mentioned. Reply to this email directly or view it on GitHub: #1458 (comment)

-- Sent from my Android device with K-9 Mail. Please excuse my brevity.

[umarcor]

FTR, see recent discussions in GHDL's repo about libghdl, the Python interface to libghdl, pyVHDLParser and pyVHDLModel: https://github.com/ghdl/ghdl/labels/Interface%3A%20Python.

/cc @Paebbels