How to transfer the bahivour model to gate-level model in Verilog? #3563
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ZhiyuanYan
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The representation is only about cells, not about wires. Even in gate-level representation the wires will continue to be grouped into buses, as they have to be connected to ports etc. You can use the |
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I tried to use the standard cell library to represent behaviour model as gate-level model. However, for some multiple-bit wire variable. It cannot be represented sucessfully. It will be represented like in the figure. How can I represent this into cell library.
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