Synthesize verilog files for xilinx zc706 fpga using yosys

[tsp6]

Hello Everyone,

I actually know that we can synthesize verilog files using yosys for gatemate fpga's using the command below:
$ yosys -l yosys.log -p 'read_verilog ; synth_gatemate -top -vlog net/_synth.v'

Now I wanted to run a synthesis for Xilinx Zynq-7000 SoC ZC706 fpga using yosys to generate netlist. May I know the command for it or how to run synthesis.

Any kind of answers or suggestions are well appreciated and will be very helpful for me.

Thank You

[nakengelhardt]

https://yosyshq.readthedocs.io/projects/yosys/en/latest/cmd/synth_xilinx.html

This is a 7-series FPGA so you would run

read_verilog <source file name>
synth_xilinx -family xc7 -top <top_module_name>
write_verilog <synthesized netlist file name>