How to trace failing issue

[vijayank88]

Facing child killed signal while running synthesis with sky130 pdk with OpenLane flow.
Log:

Model from SAT solver: { $auto$rtlil.cc:2374:ReduceAnd$136425 $auto$rtlil.cc:2374:ReduceAnd$136349 $auto$rtlil.cc:2371:Not$136355 $auto$rtlil.cc:2374:ReduceAnd$136387 $auto$rtlil.cc:2371:Not$136393 \tile_prci_domain.tile_reset_domain.boom_tile.dcache.s2_req_0_is_hella \tile_prci_domain.tile_reset_domain.boom_tile.dcache.s2_req_0_uop_uses_ldq $auto$rtlil.cc:2374:ReduceAnd$136597 $flatten\tile_prci_domain.\tile_reset_domain.\boom_tile.\lsu.$eq$/openlane/designs/DigitalTop/src/top.v:291743$63473_Y $flatten\tile_prci_domain.\tile_reset_domain.\boom_tile.\lsu.$eq$/openlane/designs/DigitalTop/src/top.v:291742$63471_Y $flatten\tile_prci_domain.\tile_reset_domain.\boom_tile.\lsu.$eq$/openlane/designs/DigitalTop/src/top.v:291741$63469_Y $flatten\tile_prci_domain.\tile_reset_domain.\boom_tile.\lsu.$eq$/openlane/designs/DigitalTop/src/top.v:291740$63467_Y $flatten\tile_prci_domain.\tile_reset_domain.\boom_tile.\lsu.$eq$/openlane/designs/DigitalTop/src/top.v:291739$63465_Y $flatten\tile_prci_domain.\tile_reset_domain.\boom_tile.\lsu.$eq$/openlane/designs/DigitalTop/src/top.v:291738$63463_Y $flatten\tile_prci_domain.\tile_reset_do[ERROR]: during executing yosys script /openlane/scripts/yosys/synth.tcl
[ERROR]: Log: designs/DigitalTop/runs/runA3/logs/synthesis/1-synthesis.log
[ERROR]: Last 10 lines:
child killed: kill signal

Any suggestion or help to trace the issue to resolve synthsis failure.
Thanks

[gatecat]

Seems to be running out of memory. Try running synthesis without flattening, and make sure the caches are being mapped to SRAM.

[vijayank88]

Used without flattening. 126GB RAM used. still got killed:

 Activation pattern for cell $shl$/openlane/designs/DigitalTop/src/top.v:289895$61326: { \searcher_is_older_7 \_l_mask_mask_T_75 $auto$rtlil.cc:2371:Not$135899 \_T_463 \_T_444 \_T_360 \_T_432 \_T_454 \_T_396 } = 9'011000011
      Size of SAT problem: 0 cells, 889688 variables, 28202155 clauses
      According to the SAT solver this pair of cel[ERROR]: during executing yosys script /openlane/scripts/yosys/synth.tcl
[ERROR]: Log: designs/DigitalTop/runs/runA2/logs/synthesis/1-synthesis.log
[ERROR]: Last 10 lines:
child killed: kill signal

[gatecat]

You could try also avoiding the share pass