Using both set and reset pins of a FF.

[tms4517]

Hi all, I was wondering why Yosys cant seem to synthesize the RTL below to make use of the set and synchronous reset pins of a FF.

`default_nettype none

module setReset
  ( input  var logic i_clk

  , input  var logic i_dat1
  , input  var logic i_dat2
  , input  var logic i_dat3

  , output var logic o_dat
  );

logic dat_q;

assign o_dat = dat_q;

always_ff @(posedge i_clk)
  if (i_dat3)
    dat_q <= '0;
  else if (i_dat1)
    dat_q <=  1'b1;
  else
    dat_q <=  i_dat2;

endmodule

Using the show command this seems to be synthesized:

I would have expected this to be synthesized:

They are both logically the same. Thank you.

[jix]

There is no builtin cell type for a FF with both a synchronous set and reset so the generic synth and optimization passes cannot output such a cell. If you are targeting an architecture that has support for such FFs a target specific pass could still recognize and replace equivalent patterns like this.

[tms4517]

ok, thank you. I appreciate your prompt response.