yosys synthesis is too slow #4717
shengqilong
started this conversation in
General
Replies: 1 comment 1 reply
-
Depending on where the slowdown happens you may get an improvement by applying |
Beta Was this translation helpful? Give feedback.
1 reply
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
-
The synthesis of Verilog always case statements with more than 1000 entries can become very slow. Is there any other way to improve the synthesis speed?
Beta Was this translation helpful? Give feedback.
All reactions