Day 4 - Design and verify a 8-bit ALU

module day4 (
  input     logic [7:0]   a_i,
  input     logic [7:0]   b_i,
  input     logic [2:0]   op_i,

  output    logic [7:0]   alu_o
);
  
  //enumerators definition for ALU opcodes
  localparam 		OP_Code_ADD = 3'b000;
  localparam 		OP_Code_SUB = 3'b001;
  localparam 		OP_Code_SLL = 3'b010;
  localparam 		OP_Code_LSR = 3'b011;
  localparam 		OP_Code_AND = 3'b100;
  localparam 		OP_Code_OR  = 3'b101;
  localparam 		OP_Code_XOR = 3'b110;
  localparam 		OP_Code_EQL = 3'b111;
  
  logic C_out;
  
  always_comb begin
    case (op_i)
      OP_Code_ADD	:	{C_out,alu_o} = {1'b0, a_i} + {1'b0, b_i};
      OP_Code_SUB : alu_o					= a_i - b_i;
      OP_Code_SLL : alu_o         = a_i[7:0] << b_i[2:0];
      OP_Code_LSR : alu_o         = a_i[7:0] >> b_i[2:0];
      OP_Code_AND : alu_o         = a_i[7:0]  & b_i[7:0];
      OP_Code_OR  : alu_o         = a_i[7:0]  | b_i[7:0];
      OP_Code_XOR : alu_o         = a_i[7:0]  ^ b_i[7:0];
      OP_Code_EQL : alu_o         = (a_i == b_i);
    endcase
  end
endmodule

//testbench
module day4_tb ();

  logic			[7:0]			a_i_tb;
  logic			[7:0]			b_i_tb;
  
  logic			[2:0]			op_i_tb;
  
  logic			[7:0]			alu_o_tb;
  
  
  day4 D4(
    
    .a_i(a_i_tb),
    .b_i(b_i_tb),
    .op_i(op_i_tb),
    .alu_o(alu_o_tb)
  );
  
  initial begin
    for (int j = 0; j < 3; j++)begin
      for (int i = 0; i <= 7; i++) begin
        a_i_tb  = $urandom_range (0, 8'hff);
        b_i_tb  = $urandom_range (0, 8'hff);
        op_i_tb = 3'(i);
        #5;
      end
    end
  end
endmodule