README.md

• eSpiMasterBfm
  • Features
  • Releases
  • Example
  • File Listing
  • BFM procedures
  • FAQ
    • INIT ends with WAIT_ALERT
  • Contributors wanted
  • eSPI Slaves
  • References

eSpiMasterBfm

Enhanced SPI Master Bus Functional Model

Features

The eSpiMasterBfm provides VHDL procedures to interact with an eSPI endpoint. Currently are procedures available for:

• IO Read/Write
• Memory Read/Write
• Endpoint Configuration

Releases

Version	Date	Source	Change log
latest		latest.zip
v0.1.3	2021-10-01	v0.1.3.zip	Bugfixes: IOWR/MEMWR checks for free queue before write; Features: GHDL continuous unit test
v0.1.2	2021-04-12	v0.1.2.zip	Bugfixes: Reset, alert mode, strlen, testbench; Features: Server Specific Platform wire decoding
v0.1.1	2021-03-12	v0.1.1.zip	Bugfixes: Supported to used IO mode; wait on virtual wire
v0.1.0	2020-12-30	v0.1.0.zip	Configuration; IO read/write; Memory read/write

Example

The full provided function set demonstrates the eSpiMasterBfm_tb.vhd. A tiny testbench example shows the snippet below:

library ieee;
  use ieee.std_logic_1164.all;
library work;
  use work.eSpiMasterBfm.all;

entity espi_tb is
end entity espi_tb;

architecture sim of espi_tb is

  -----------------------------
  -- ESPI ITF
  signal CSn    : std_logic;
  signal SCK    : std_logic;
  signal DIO    : std_logic_vector(3 downto 0);
  signal ALERTn : std_logic;
  signal RESETn : std_logic;
  -----------------------------

begin

  -----------------------------
  -- DUT
  --   add ESPI Slave here
  -----------------------------


  -----------------------------
  -- stimuli process
  p_stimuli : process
    variable eSpiBfm : tESpiBfm;                        -- eSPI Master bfm Handle
    variable good    : boolean := true;                 -- test state
    variable slv08   : std_logic_vector(7 downto 0);    -- help variable
  begin
    -- Initializes Endpoint according 'Exit G3' sequence
    --   init( this, RESETn, CSn, SCK, DIO, ALERTn, good, log );
    init( eSpiBfm, RESETn, CSn, SCK, DIO, ALERTn, good, INFO );

    -- write to io-mapped address
    --   IOWR( this, CSn, SCK, DIO, adr, data, good )
    IOWR( eSpiBfm, CSn, SCK, DIO, x"0080", x"47", good );   -- P80

    -- read from io-mapped address
    --   IORD( this, CSn, SCK, DIO, adr, data, good )
    IORD( eSpiBfm, CSn, SCK, DIO, x"0081", slv08, good );   -- P81

    -- write to memory-mapped address
    --   MEMWR32( this, CSn, SCK, DIO, adr, data, good );
    MEMWR32( eSpiBfm, CSn, SCK, DIO, x"00000080", x"47", good );    -- byte write

    -- read from memory-mapped address
    --   MEMRD32( this, CSn, SCK, DIO, adr, data, good );
    MEMRD32( eSpiBfm, CSn, SCK, DIO, x"00000080", slv08, good );    -- byte read

    -- done
    Report "That's it :-)";
    wait;   -- stop continuous run
  end process p_stimuli;
  -----------------------------


  -----------------------------
  -- External Pull Resistors
  SCK    <= 'L';
  DIO    <= (others => 'H');
  ALERTn <= 'H';
  -----------------------------

end architecture sim;

File Listing

The table below lists the major files in this project:

File	Group	Remark
eSpiMasterBfm.vhd	BFM	BFM itself, provides procedures to interact with an eSPI Slave
eSpiMasterBfm_tb.vhd	TB	eSpiMasterBfm testbench, example BFM procedure calls
eSpiMasterBfm_compile.tcl	SIM	compile script for Modelsim
eSpiMasterBfm_runsim.tcl	SIM	starts simulation

BFM procedures

Category	Procedures	Example
initialization	INIT RESET	INIT(bfm, RESETn, CSn, SCK, DIO, ALERTn, good)
slave configuration	GET_CONFIGURATION SET_CONFIGURATION GET_STATUS	GET_CONFIGURATION(bfm, CSn, SCK, DIO, adr, cfg, sts, rsp)
virtual wire	VWIREWR VWIRERD WAIT_VW_IS_EQ	VWIREWR(bfm, CSn, SCK, DIO, "PLTRST#", '1', good)
IO write	IOWR_BYTE IOWR_WORD IOWR_DWORD	IOWR(bfm, CSn, SCK, DIO, adr16, dat08, good)
IO read	IORD_BYTE IORD_WORD IORD_DWORD	IORD(bfm, CSn, SCK, DIO, adr16, dat08, good)
memory write	MEMWR32	MEMWR32(bfm, CSn, SCK, DIO, adr32, dat08, good)
memory read	MEMRD32	MEMRD32(bfm, CSn, SCK, DIO, adr32, dat08, good)
misc	tespi	tespi(bfm)

FAQ

INIT ends with WAIT_ALERT

ESPI slave initialization INIT(bfm, RESETn, CSn, SCK, DIO, ALERTn, good) stops with the log message ** Note: eSpiMasterBfm:WAIT_ALERT. This is caused by non asserting the two virtual wire inputs SLAVE_BOOT_LOAD_DONE=1 and SLAVE_BOOT_LOAD_STATUS=1. According the eSPI Specification chapter Exit from G3 point 8 needs both virtual wires set to logical one for exit G3.

Contributors wanted

If you think useful project and also helpful, feel free to fork and contribute. The license does not require this, but the project will love it :-). Contributors welcome.

eSPI Slaves

• Intel/Altera eSPI to LPC Bridge Core

References

• Intel eSPI Specification