Lightweight UART core written in VHDL.
- independent RX and TX path
- buffer register on RX and TX
- parameterizable data size
- one or two stop bits
- settable baud rate
- optional parity (odd/even)
Name |
Default |
Values |
Description |
WLS |
8 |
5..8 |
word length select; data bits |
CLK |
50_000_000 |
positive |
master clock frequency in Hz |
BPS |
115200 |
positive |
baud rate per second |
SBS |
1 |
1..2 |
Stop bit select |
PI |
true |
boolean |
Parity inhibit |
EPE |
true |
boolean |
Even parity enable, otherwise odd |
DEBU |
3 |
0..11 |
debouncer stages |
TXIMPL |
true |
boolean |
TX path implemented |
RXIMPL |
true |
boolean |
RX path implemented |
Settable at compile time.
Port |
Dir |
Width |
Description |
R |
in |
1b |
asynchronous reset |
C |
in |
1b |
clock, rising-edge only |
TXD |
out |
1b |
serial UART output |
RXD |
in |
1b |
serial UART input |
RR |
out |
5b..8b |
Receiver Holding Register Data Output |
PE |
out |
1b |
Parity error |
FE |
out |
1b |
Framing error |
DR |
out |
1b |
Data Received, one clock cycle high |
TR |
in |
5b..8b |
Transmitter Holding Register Data Input |
THRE |
out |
1b |
Transmitter Holding Register Empty |
THRL |
in |
1b |
Transmitter Holding Register Load |
TRE |
out |
1b |
Transmitter Register Empty |
The block diagram visualizes the simplified tinyUART architecture. Blocks with solid lines are own sub entities. All blocks with dashed lines are implemented
in the top level.
Technology |
EDA |
HDL generics |
Logic |
Registers |
BRAM |
Fmax |
Cyclone 10 |
Q18.1 |
defaults |
89LEs |
79FF |
0 |
89.61MHz |
Cyclone 10 |
Q18.1 |
defaults, TXIMPL=false |
43LEs |
41FF |
0 |
89.61MHz |
Cyclone 10 |
Q18.1 |
defaults, RXIMPL=false |
50LEs |
38FF |
0 |
89.67MHz |