From 8734040234ad9a1deb1c44480419ac8b207aee86 Mon Sep 17 00:00:00 2001 From: Almir Okato Date: Fri, 9 Feb 2024 16:15:33 -0300 Subject: [PATCH] esp32s3: add simple boot support The Simple Boot feature for Espressif chips is a method of booting that doesn't depend on a 2nd stage bootloader. Its not the intention to replace a 2nd stage bootloader such as MCUboot and ESP-IDF bootloader, but to have a minimal and straight-forward way of booting, and also simplify the building. This commit also removes deprecated code and makes this bootloader configuration as default for esp32s3 targets and removes the need for running 'make bootloader' command for it. Other related fix, but not directly to Simple Boot: - Instrumentation is required to run from IRAM to support it during initialization. `is_eco0` function also needs to run from IRAM. - `rtc.data` section placement was fixed. - Provide arch-defined interfaces for efuses, in order to decouple board config level from arch-defined values. Signed-off-by: Almir Okato --- arch/xtensa/Kconfig | 2 +- arch/xtensa/include/esp32s3/.gitignore | 6 + arch/xtensa/src/esp32s3/Bootloader.mk | 24 +- arch/xtensa/src/esp32s3/Kconfig | 42 +- arch/xtensa/src/esp32s3/Make.defs | 7 +- arch/xtensa/src/esp32s3/esp32s3_ble_adapter.c | 2 +- arch/xtensa/src/esp32s3/esp32s3_clockconfig.c | 2 +- arch/xtensa/src/esp32s3/esp32s3_efuse.c | 142 +- arch/xtensa/src/esp32s3/esp32s3_efuse.h | 35 + arch/xtensa/src/esp32s3/esp32s3_himem.c | 3 +- arch/xtensa/src/esp32s3/esp32s3_otg.h | 3 - arch/xtensa/src/esp32s3/esp32s3_psram_octal.c | 5 +- arch/xtensa/src/esp32s3/esp32s3_psram_quad.c | 15 +- arch/xtensa/src/esp32s3/esp32s3_rng.c | 2 +- arch/xtensa/src/esp32s3/esp32s3_rt_timer.c | 2 +- arch/xtensa/src/esp32s3/esp32s3_rtc.c | 6 +- arch/xtensa/src/esp32s3/esp32s3_spi_timing.c | 7 +- arch/xtensa/src/esp32s3/esp32s3_spiflash.c | 15 +- .../xtensa/src/esp32s3/esp32s3_spiflash_mtd.c | 10 +- arch/xtensa/src/esp32s3/esp32s3_spiram.c | 7 +- arch/xtensa/src/esp32s3/esp32s3_start.c | 351 +- arch/xtensa/src/esp32s3/esp32s3_twai.c | 1 + arch/xtensa/src/esp32s3/esp32s3_twai.h | 1 - arch/xtensa/src/esp32s3/esp32s3_userspace.c | 8 +- .../xtensa/src/esp32s3/esp32s3_wifi_adapter.c | 2 +- arch/xtensa/src/esp32s3/esp32s3_wireless.h | 2 +- arch/xtensa/src/esp32s3/hal.mk | 57 +- .../esp32s3/hardware/esp32s3_cache_memory.h | 74 +- .../src/esp32s3/hardware/esp32s3_extmem.h | 2761 ------------- .../xtensa/src/esp32s3/hardware/esp32s3_soc.h | 402 +- .../esp32s3/hardware/esp32s3_spi_mem_reg.h | 3586 ----------------- .../hardware/esp32s3_usb_serial_jtag.h | 40 +- .../src/esp32s3/rom/esp32s3_opi_flash.h | 355 -- .../xtensa/src/esp32s3/rom/esp32s3_spiflash.h | 127 +- .../esp32s3/common/scripts/flat_memory.ld | 41 +- .../esp32s3/common/scripts/kernel-space.ld | 9 + .../esp32s3/common/scripts/legacy_sections.ld | 3 + .../common/scripts/mcuboot_sections.ld | 23 +- .../common/scripts/simple_boot_sections.ld | 572 +++ .../esp32s3/common/src/esp32s3_lan9250.c | 7 +- .../esp32s3/esp32s3-box/scripts/Make.defs | 2 + .../configs/eth_lan9250/defconfig | 1 + .../esp32s3/esp32s3-devkit/scripts/Make.defs | 2 + .../esp32s3/esp32s3-devkit/src/esp32s3_ledc.c | 1 - .../esp32s3/esp32s3-devkit/src/esp32s3_twai.c | 2 - .../esp32s3/esp32s3-eye/scripts/Make.defs | 8 +- .../esp32s3/esp32s3-lcd-ev/scripts/Make.defs | 2 + .../esp32s3/esp32s3-meadow/scripts/Make.defs | 8 +- tools/esp32s3/Config.mk | 26 + 49 files changed, 1211 insertions(+), 7600 deletions(-) create mode 100644 arch/xtensa/include/esp32s3/.gitignore delete mode 100644 arch/xtensa/src/esp32s3/hardware/esp32s3_extmem.h delete mode 100644 arch/xtensa/src/esp32s3/hardware/esp32s3_spi_mem_reg.h delete mode 100644 arch/xtensa/src/esp32s3/rom/esp32s3_opi_flash.h create mode 100644 boards/xtensa/esp32s3/common/scripts/simple_boot_sections.ld diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig index 0c7f1f60ab92d..c49349b6ec401 100644 --- a/arch/xtensa/Kconfig +++ b/arch/xtensa/Kconfig @@ -78,7 +78,7 @@ config ARCH_CHIP_ESP32S3 bool "Espressif ESP32-S3" select ARCH_FAMILY_LX7 select XTENSA_HAVE_INTERRUPTS - select ARCH_HAVE_BOOTLOADER + select ARCH_HAVE_BOOTLOADER if !ESPRESSIF_SIMPLE_BOOT select ARCH_HAVE_FPU select ARCH_HAVE_MPU select ARCH_HAVE_MULTICPU diff --git a/arch/xtensa/include/esp32s3/.gitignore b/arch/xtensa/include/esp32s3/.gitignore new file mode 100644 index 0000000000000..9dd4b4aea86e7 --- /dev/null +++ b/arch/xtensa/include/esp32s3/.gitignore @@ -0,0 +1,6 @@ +/soc.h +/reg_base.h +/esp_attr.h +/esp_assert.h +/esp_bit_defs.h +/sdkconfig.h diff --git a/arch/xtensa/src/esp32s3/Bootloader.mk b/arch/xtensa/src/esp32s3/Bootloader.mk index b30db3f508ce8..9d6c704c86659 100644 --- a/arch/xtensa/src/esp32s3/Bootloader.mk +++ b/arch/xtensa/src/esp32s3/Bootloader.mk @@ -20,7 +20,7 @@ .PHONY: bootloader clean_bootloader -ifeq ($(CONFIG_ESP32S3_BOOTLOADER_BUILD_FROM_SOURCE),y) +ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),) TOOLSDIR = $(TOPDIR)/tools/espressif CHIPDIR = $(TOPDIR)/arch/xtensa/src/chip @@ -83,8 +83,13 @@ else ifeq ($(CONFIG_ESP32S3_APP_FORMAT_LEGACY),y) $(call cfg_val,CONFIG_PARTITION_TABLE_OFFSET,$(CONFIG_ESP32S3_PARTITION_TABLE_OFFSET)) \ } >> $(BOOTLOADER_CONFIG) endif +endif -ifeq ($(CONFIG_ESP32S3_APP_FORMAT_MCUBOOT),y) +ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y) +bootloader: + $(Q) echo "Using direct bootloader to boot NuttX." + +else ifeq ($(CONFIG_ESP32S3_APP_FORMAT_MCUBOOT),y) BOOTLOADER_BIN = $(TOPDIR)/mcuboot-esp32s3.bin @@ -126,18 +131,3 @@ clean_bootloader: $(call DELFILE,$(TOPDIR)/partition-table-esp32s3.bin) endif - -else ifeq ($(CONFIG_ESP32S3_BOOTLOADER_DOWNLOAD_PREBUILT),y) - -BOOTLOADER_VERSION = latest -BOOTLOADER_URL = https://github.com/espressif/esp-nuttx-bootloader/releases/download/$(BOOTLOADER_VERSION) - -bootloader: - $(call DOWNLOAD,$(BOOTLOADER_URL),bootloader-esp32s3.bin,$(TOPDIR)/bootloader-esp32s3.bin) - $(call DOWNLOAD,$(BOOTLOADER_URL),partition-table-esp32s3.bin,$(TOPDIR)/partition-table-esp32s3.bin) - -clean_bootloader: - $(call DELFILE,$(TOPDIR)/bootloader-esp32s3.bin) - $(call DELFILE,$(TOPDIR)/partition-table-esp32s3.bin) - -endif diff --git a/arch/xtensa/src/esp32s3/Kconfig b/arch/xtensa/src/esp32s3/Kconfig index 6ed15a33bb6f0..9e70c106e3935 100644 --- a/arch/xtensa/src/esp32s3/Kconfig +++ b/arch/xtensa/src/esp32s3/Kconfig @@ -39,6 +39,10 @@ config ESPRESSIF_CHIP_SERIES string default "esp32s3" +config ESPRESSIF_NUM_CPUS + int + default 2 + choice ESP32S3_DEFAULT_CPU_FREQ prompt "CPU frequency" default ESP32S3_DEFAULT_CPU_FREQ_240 @@ -530,6 +534,7 @@ config ESP32S3_WDT config ESP32S3_EFUSE bool "EFUSE support" + select EFUSE default n ---help--- Enable ESP32-S3 efuse support. @@ -1887,15 +1892,13 @@ config ESP32S3_SPI_FLASH_SUPPORT_PSRAM_STACK 3. Once operation in step 2 triggers, CPU will trigger exception. So related SPI flash functions should be sent and run in tasks which use SRAM as task stack. -if ESP32S3_APP_FORMAT_LEGACY - comment "Partition Table configuration" config ESP32S3_PARTITION_TABLE bool "Create MTD partitions from Partition Table" default n - depends on ESP32S3_MTD && ESP32S3_APP_FORMAT_LEGACY - select ESP32S3_BOOTLOADER_BUILD_FROM_SOURCE + depends on ESP32S3_MTD + select ESP32S3_APP_FORMAT_LEGACY ---help--- Decode partition table and initialize partitions as MTD. @@ -1904,8 +1907,6 @@ config ESP32S3_PARTITION_MOUNTPT default "/dev/esp/partition/" depends on ESP32S3_PARTITION_TABLE -endif # ESP32S3_APP_FORMAT_LEGACY - endif # ESP32S3_SPIFLASH endmenu # SPI Flash configuration @@ -2173,38 +2174,26 @@ endmenu menu "Bootloader and Image Configuration" -config ESP32S3_APP_FORMAT_LEGACY +config ESPRESSIF_SIMPLE_BOOT bool - default y if !ESP32S3_APP_FORMAT_MCUBOOT depends on !ESP32S3_APP_FORMAT_MCUBOOT - ---help--- - This is the legacy application image format, as supported by the ESP-IDF - 2nd stage bootloader. + depends on !ESP32S3_APP_FORMAT_LEGACY + default y config ESP32S3_APP_FORMAT_MCUBOOT bool "Enable MCUboot-bootable format" depends on !MCUBOOT_BOOTLOADER + default n select ESP32S3_HAVE_OTA_PARTITION - select ESP32S3_BOOTLOADER_BUILD_FROM_SOURCE ---help--- Enables the Espressif port of MCUboot to be used as 2nd stage bootloader. -config ESP32S3_BOOTLOADER_DOWNLOAD_PREBUILT +config ESP32S3_APP_FORMAT_LEGACY bool - default y if !ESP32S3_BOOTLOADER_BUILD_FROM_SOURCE - depends on !ESP32S3_BOOTLOADER_BUILD_FROM_SOURCE + default y if BUILD_PROTECTED ---help--- - The build system will download the prebuilt binaries from - https://github.com/espressif/esp-nuttx-bootloader according to the chosen - Application Image Format (ESP32S3_APP_FORMAT_LEGACY or ESP32S3_APP_FORMAT_MCUBOOT) - -config ESP32S3_BOOTLOADER_BUILD_FROM_SOURCE - bool "Build binaries from source" - ---help--- - The build system will build all the required binaries from source. It will clone - the https://github.com/espressif/esp-nuttx-bootloader repository and build a - custom bootloader according to the chosen Application Image Format - (ESP32S3_APP_FORMAT_LEGACY or ESP32S3_APP_FORMAT_MCUBOOT) and partition information. + This is the legacy application image format, as supported by the ESP-IDF + 2nd stage bootloader. choice prompt "Target slot for image flashing" @@ -2250,7 +2239,6 @@ config ESP32S3_CUSTOM_PARTITION_TABLE_OFFSET bool "Customize partition table offset" default n depends on ESP32S3_APP_FORMAT_LEGACY - select ESP32S3_BOOTLOADER_BUILD_FROM_SOURCE ---help--- Enable to select the offset of the partition table in the flash. diff --git a/arch/xtensa/src/esp32s3/Make.defs b/arch/xtensa/src/esp32s3/Make.defs index ec712cbd7ae02..a0f33b41abee0 100644 --- a/arch/xtensa/src/esp32s3/Make.defs +++ b/arch/xtensa/src/esp32s3/Make.defs @@ -194,7 +194,7 @@ endif ESP_HAL_3RDPARTY_REPO = esp-hal-3rdparty ifndef ESP_HAL_3RDPARTY_VERSION - ESP_HAL_3RDPARTY_VERSION = c6a4edccfce95e32ef5e34d9f1119d9c581c5c1c + ESP_HAL_3RDPARTY_VERSION = 7c4fae7ebc5342b19cab03511bfa277176bba377 endif ifndef ESP_HAL_3RDPARTY_URL @@ -212,6 +212,8 @@ chip/$(ESP_HAL_3RDPARTY_REPO): CFLAGS += -Wno-undef -Wno-unused-variable CFLAGS += ${DEFINE_PREFIX}_RETARGETABLE_LOCKING +AFLAGS += $(CFLAGS) + # Files that require the HAL recipe include chip/Bootloader.mk @@ -231,9 +233,6 @@ ifeq ($(CONFIG_ESP32S3_WIRELESS),y) $(Q) cd chip/$(ESP_HAL_3RDPARTY_REPO)/components/mbedtls/mbedtls && git apply ../../../nuttx/patches/components/mbedtls/mbedtls/*.patch endif -distclean:: - $(call DELDIR, chip/$(ESP_HAL_3RDPARTY_REPO)) - ifeq ($(CONFIG_ESP32S3_WIRELESS),y) include chip/Wireless.mk endif diff --git a/arch/xtensa/src/esp32s3/esp32s3_ble_adapter.c b/arch/xtensa/src/esp32s3/esp32s3_ble_adapter.c index f3ae9c4b4a110..5f5b537d16e7c 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_ble_adapter.c +++ b/arch/xtensa/src/esp32s3/esp32s3_ble_adapter.c @@ -53,7 +53,7 @@ #include "hardware/wdev_reg.h" #include "rom/esp32s3_spiflash.h" #include "xtensa.h" -#include "xtensa_attr.h" +#include "esp_attr.h" #include "esp32s3_irq.h" #include "esp32s3_rt_timer.h" #include "esp32s3_rtc.h" diff --git a/arch/xtensa/src/esp32s3/esp32s3_clockconfig.c b/arch/xtensa/src/esp32s3/esp32s3_clockconfig.c index 787a4064854b8..0ff404b25a93f 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_clockconfig.c +++ b/arch/xtensa/src/esp32s3/esp32s3_clockconfig.c @@ -28,7 +28,7 @@ #include #include "xtensa.h" -#include "xtensa_attr.h" +#include "esp_attr.h" #include "hardware/esp32s3_soc.h" #include "hardware/esp32s3_uart.h" #include "hardware/esp32s3_system.h" diff --git a/arch/xtensa/src/esp32s3/esp32s3_efuse.c b/arch/xtensa/src/esp32s3/esp32s3_efuse.c index fe138056cdec8..b843e8ca01763 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_efuse.c +++ b/arch/xtensa/src/esp32s3/esp32s3_efuse.c @@ -440,51 +440,6 @@ static int esp32s3_efuse_process(const efuse_desc_t *field[], void *ptr, return err; } -/**************************************************************************** - * Name: esp32s3_efuse_write_reg - * - * Description: - * Write value to efuse register. - * - * Input Parameters: - * blk - Block number of eFuse - * num_reg - The register number in the block - * value - Value to write - * - * Returned Value: - * None. - * - ****************************************************************************/ - -static void esp32s3_efuse_write_reg(uint32_t blk, uint32_t num_reg, - uint32_t value) -{ - uint32_t addr_wr_reg; - uint32_t reg_to_write; - uint32_t blk_start = g_start_efuse_wrreg[blk]; - - DEBUGASSERT(blk >= 0 && blk < EFUSE_BLK_MAX); - - DEBUGASSERT(num_reg <= 7); - - /* The block 0 and register 7 doesn't exist */ - - if (blk == 0 && num_reg == 7) - { - merr("Block 0 Register 7 doesn't exist!\n"); - return; - } - - addr_wr_reg = blk_start + num_reg * 4; - reg_to_write = getreg32(addr_wr_reg) | value; - - /* The register can be written in parts so we combine the new value - * with the one already available. - */ - - putreg32(reg_to_write, addr_wr_reg); -} - /**************************************************************************** * Name: esp32s3_efuse_write_blob * @@ -518,33 +473,6 @@ static int esp32s3_efuse_write_blob(uint32_t num_reg, int bit_offset, return OK; } -/**************************************************************************** - * Name: esp32s3_efuse_read_reg - * - * Description: - * Read efuse register. - * - * Input Parameters: - * blk - Block number of eFuse - * num_reg - The register number in the block - * - * Returned Value: - * Return the value in the efuse register. - * - ****************************************************************************/ - -static uint32_t esp32s3_efuse_read_reg(uint32_t blk, uint32_t num_reg) -{ - DEBUGASSERT(blk >= 0 && blk < EFUSE_BLK_MAX); - uint32_t value; - uint32_t blk_start = g_start_efuse_rdreg[blk]; - - DEBUGASSERT(num_reg <= 7); - - value = getreg32(blk_start + num_reg * 4); - return value; -} - /**************************************************************************** * Name: esp32s3_efuse_fill_buff * @@ -709,3 +637,73 @@ void esp32s3_efuse_burn_efuses(void) }; } +/**************************************************************************** + * Name: esp32s3_efuse_read_reg + * + * Description: + * Read efuse register. + * + * Input Parameters: + * blk - Block number of eFuse + * num_reg - The register number in the block + * + * Returned Value: + * Return the value in the efuse register. + * + ****************************************************************************/ + +uint32_t esp32s3_efuse_read_reg(uint32_t blk, uint32_t num_reg) +{ + DEBUGASSERT(blk >= 0 && blk < EFUSE_BLK_MAX); + uint32_t value; + uint32_t blk_start = g_start_efuse_rdreg[blk]; + + DEBUGASSERT(num_reg <= 7); + + value = getreg32(blk_start + num_reg * 4); + return value; +} + +/**************************************************************************** + * Name: esp32s3_efuse_write_reg + * + * Description: + * Write value to efuse register. + * + * Input Parameters: + * blk - Block number of eFuse + * num_reg - The register number in the block + * value - Value to write + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp32s3_efuse_write_reg(uint32_t blk, uint32_t num_reg, uint32_t value) +{ + uint32_t addr_wr_reg; + uint32_t reg_to_write; + uint32_t blk_start = g_start_efuse_wrreg[blk]; + + DEBUGASSERT(blk >= 0 && blk < EFUSE_BLK_MAX); + + DEBUGASSERT(num_reg <= 7); + + /* The block 0 and register 7 doesn't exist */ + + if (blk == 0 && num_reg == 7) + { + merr("Block 0 Register 7 doesn't exist!\n"); + return; + } + + addr_wr_reg = blk_start + num_reg * 4; + reg_to_write = getreg32(addr_wr_reg) | value; + + /* The register can be written in parts so we combine the new value + * with the one already available. + */ + + putreg32(reg_to_write, addr_wr_reg); +} diff --git a/arch/xtensa/src/esp32s3/esp32s3_efuse.h b/arch/xtensa/src/esp32s3/esp32s3_efuse.h index ae3d0a81a007c..b9ee0a2b0cbf0 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_efuse.h +++ b/arch/xtensa/src/esp32s3/esp32s3_efuse.h @@ -162,6 +162,41 @@ int esp32s3_efuse_write_field(const efuse_desc_t *field[], void esp32s3_efuse_burn_efuses(void); +/**************************************************************************** + * Name: esp32s3_efuse_read_reg + * + * Description: + * Read efuse register. + * + * Input Parameters: + * blk - Block number of eFuse + * num_reg - The register number in the block + * + * Returned Value: + * Return the value in the efuse register. + * + ****************************************************************************/ + +uint32_t esp32s3_efuse_read_reg(uint32_t blk, uint32_t num_reg); + +/**************************************************************************** + * Name: esp32s3_efuse_write_reg + * + * Description: + * Write value to efuse register. + * + * Input Parameters: + * blk - Block number of eFuse + * num_reg - The register number in the block + * value - Value to write + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp32s3_efuse_write_reg(uint32_t blk, uint32_t num_reg, uint32_t value); + /**************************************************************************** * Name: esp32s3_efuse_initialize * diff --git a/arch/xtensa/src/esp32s3/esp32s3_himem.c b/arch/xtensa/src/esp32s3/esp32s3_himem.c index 25d832c02977d..dbaf9751f81d9 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_himem.c +++ b/arch/xtensa/src/esp32s3/esp32s3_himem.c @@ -35,7 +35,8 @@ #include "esp32s3_spiflash_mtd.h" #include "hardware/esp32s3_soc.h" #include "hardware/esp32s3_cache_memory.h" -#include "hardware/esp32s3_extmem.h" + +#include "soc/extmem_reg.h" /**************************************************************************** * Pre-processor Definitions diff --git a/arch/xtensa/src/esp32s3/esp32s3_otg.h b/arch/xtensa/src/esp32s3/esp32s3_otg.h index 82a885cb26fcc..728b072196932 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_otg.h +++ b/arch/xtensa/src/esp32s3/esp32s3_otg.h @@ -29,9 +29,6 @@ #include -#include "chip.h" -#include "hardware/esp32s3_otg.h" - #if defined(CONFIG_ESP32S3_OTG) /**************************************************************************** diff --git a/arch/xtensa/src/esp32s3/esp32s3_psram_octal.c b/arch/xtensa/src/esp32s3/esp32s3_psram_octal.c index 675fa14e448f7..75d10b2c9e9ec 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_psram_octal.c +++ b/arch/xtensa/src/esp32s3/esp32s3_psram_octal.c @@ -33,13 +33,12 @@ #include "esp32s3_psram.h" #include "esp32s3_spi_timing.h" -#include "hardware/esp32s3_spi_mem_reg.h" #include "hardware/esp32s3_iomux.h" #include "hardware/esp32s3_gpio.h" #include "hardware/esp32s3_gpio_sigmap.h" #include "hardware/esp32s3_syscon.h" #include "rom/esp32s3_spiflash.h" -#include "rom/esp32s3_opi_flash.h" +#include "rom/opi_flash.h" /**************************************************************************** * Pre-processor Definitions @@ -600,7 +599,7 @@ static void IRAM_ATTR config_psram_spi_phases(void) * ****************************************************************************/ -static inline void spi_flash_set_rom_required_regs(void) +void IRAM_ATTR spi_flash_set_rom_required_regs(void) { #ifdef CONFIG_ESP32S3_FLASH_MODE_OCT diff --git a/arch/xtensa/src/esp32s3/esp32s3_psram_quad.c b/arch/xtensa/src/esp32s3/esp32s3_psram_quad.c index 98e2a2e16aafc..a022fcf7afc42 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_psram_quad.c +++ b/arch/xtensa/src/esp32s3/esp32s3_psram_quad.c @@ -31,11 +31,10 @@ #include "esp32s3_psram.h" #include "esp32s3_spi_timing.h" -#include "rom/esp32s3_spiflash.h" -#include "rom/esp32s3_opi_flash.h" -#include "hardware/esp32s3_spi_mem_reg.h" #include "hardware/esp32s3_iomux.h" #include "hardware/esp32s3_gpio_sigmap.h" +#include "rom/esp32s3_spiflash.h" +#include "rom/opi_flash.h" /* EFUSE */ @@ -148,6 +147,16 @@ static void psram_set_op_mode(int spi_num, int mode) } } +/* Redefine external struct members name */ + +#define addr_bit_len addrBitLen +#define cmd_bit_len cmdBitLen +#define dummy_bit_len dummyBitLen +#define tx_data txData +#define tx_data_bit_len txDataBitLen +#define rx_data rxData +#define rx_data_bit_len rxDataBitLen + static void _psram_exec_cmd(int spi_num, uint32_t cmd, int cmd_bit_len, uint32_t addr, int addr_bit_len, diff --git a/arch/xtensa/src/esp32s3/esp32s3_rng.c b/arch/xtensa/src/esp32s3/esp32s3_rng.c index 57a1bce2b47c5..63f1e891f9ebe 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_rng.c +++ b/arch/xtensa/src/esp32s3/esp32s3_rng.c @@ -41,7 +41,7 @@ #include #include "xtensa.h" -#include "xtensa_attr.h" +#include "esp_attr.h" #include "hardware/wdev_reg.h" #include "esp32s3_clockconfig.h" diff --git a/arch/xtensa/src/esp32s3/esp32s3_rt_timer.c b/arch/xtensa/src/esp32s3/esp32s3_rt_timer.c index 61c4a0aaff9f3..ca28eb1737122 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_rt_timer.c +++ b/arch/xtensa/src/esp32s3/esp32s3_rt_timer.c @@ -41,7 +41,7 @@ #include #include "xtensa.h" -#include "xtensa_attr.h" +#include "esp_attr.h" #include "esp32s3_irq.h" #include "esp32s3_rt_timer.h" #include "hardware/esp32s3_soc.h" diff --git a/arch/xtensa/src/esp32s3/esp32s3_rtc.c b/arch/xtensa/src/esp32s3/esp32s3_rtc.c index fad06a91e3ac5..0c688d84fe15d 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_rtc.c +++ b/arch/xtensa/src/esp32s3/esp32s3_rtc.c @@ -44,14 +44,14 @@ #include "hardware/esp32s3_apb_ctrl.h" #include "hardware/regi2c_dig_reg.h" #include "hardware/regi2c_ctrl.h" -#include "hardware/esp32s3_spi_mem_reg.h" -#include "hardware/esp32s3_extmem.h" #include "hardware/esp32s3_syscon.h" #include "hardware/regi2c_bbpll.h" #include "hardware/regi2c_lp_bias.h" #include "xtensa.h" -#include "xtensa_attr.h" +#include "esp_attr.h" +#include "soc/extmem_reg.h" +#include "soc/spi_mem_reg.h" #include "esp32s3_rtc.h" diff --git a/arch/xtensa/src/esp32s3/esp32s3_spi_timing.c b/arch/xtensa/src/esp32s3/esp32s3_spi_timing.c index 68c63c4f09a6f..280d19357a3fe 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_spi_timing.c +++ b/arch/xtensa/src/esp32s3/esp32s3_spi_timing.c @@ -30,12 +30,13 @@ #include "esp32s3_gpio.h" #include "esp32s3_psram.h" #include "esp32s3_spi_timing.h" -#include "hardware/esp32s3_spi_mem_reg.h" #include "hardware/esp32s3_iomux.h" #include "hardware/esp32s3_gpio.h" #include "hardware/esp32s3_gpio_sigmap.h" #include "rom/esp32s3_spiflash.h" -#include "rom/esp32s3_opi_flash.h" +#include "rom/opi_flash.h" + +#include "soc/spi_mem_reg.h" /**************************************************************************** * Pre-processor Definitions @@ -54,7 +55,7 @@ #endif #if defined(CONFIG_ESP32S3_FLASH_SAMPLE_MODE_DTR) -# if defined(CONFIG_ESP32S3_FLASH_FREQ_80M) +# if defined(CONFIG_ESP32S3_FLASH_FREQ_80M) # define ESP32S3_SPI_TIMING_FLASH_CORE_CLK 160 # elif defined(CONFIG_ESP32S3_FLASH_FREQ_120M) # define ESP32S3_SPI_TIMING_FLASH_CORE_CLK 240 diff --git a/arch/xtensa/src/esp32s3/esp32s3_spiflash.c b/arch/xtensa/src/esp32s3/esp32s3_spiflash.c index fc943f265a24b..231fab51c4d04 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_spiflash.c +++ b/arch/xtensa/src/esp32s3/esp32s3_spiflash.c @@ -41,16 +41,17 @@ #include "sched/sched.h" #include "xtensa.h" -#include "xtensa_attr.h" +#include "esp_attr.h" #include "hardware/esp32s3_efuse.h" -#include "hardware/esp32s3_extmem.h" -#include "hardware/esp32s3_spi_mem_reg.h" #include "hardware/esp32s3_cache_memory.h" #include "rom/esp32s3_spiflash.h" -#include "rom/esp32s3_opi_flash.h" #include "esp32s3_irq.h" #include "esp32s3_spiflash.h" +#include "soc/extmem_reg.h" +#include "soc/spi_mem_reg.h" +#include "rom/opi_flash.h" + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -208,14 +209,10 @@ extern void cache_invalidate_icache_all(void); * Private Data ****************************************************************************/ -static struct spiflash_guard_funcs g_spi_flash_guard_funcs = +static spi_flash_guard_funcs_t g_spi_flash_guard_funcs = { .start = spiflash_start, .end = spiflash_end, - .op_lock = NULL, - .op_unlock = NULL, - .address_is_safe = NULL, - .yield = NULL, }; static uint32_t s_flash_op_cache_state[CONFIG_SMP_NCPUS]; diff --git a/arch/xtensa/src/esp32s3/esp32s3_spiflash_mtd.c b/arch/xtensa/src/esp32s3/esp32s3_spiflash_mtd.c index 29293edd62590..ded890a90c339 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_spiflash_mtd.c +++ b/arch/xtensa/src/esp32s3/esp32s3_spiflash_mtd.c @@ -41,7 +41,7 @@ #include "hardware/esp32s3_soc.h" #include "hardware/esp32s3_cache_memory.h" -#include "xtensa_attr.h" +#include "esp_attr.h" #include "esp32s3_spiflash.h" #include "esp32s3_spiram.h" @@ -90,7 +90,7 @@ struct esp32s3_mtd_dev_s /* SPI Flash data */ - const struct spiflash_legacy_data_s **data; + esp_rom_spiflash_legacy_data_t **data; }; #ifdef CONFIG_ESP32S3_SPI_FLASH_SUPPORT_PSRAM_STACK @@ -177,7 +177,7 @@ static const struct esp32s3_mtd_dev_s g_esp32s3_spiflash = #endif .name = "esp32s3_spiflash" }, - .data = (const struct spiflash_legacy_data_s **) + .data = (esp_rom_spiflash_legacy_data_t **) (&rom_spiflash_legacy_data), }; @@ -195,7 +195,7 @@ static const struct esp32s3_mtd_dev_s g_esp32s3_spiflash_encrypt = #endif .name = "esp32s3_spiflash_encrypt" }, - .data = (const struct spiflash_legacy_data_s **) + .data = (esp_rom_spiflash_legacy_data_t **) (&rom_spiflash_legacy_data), }; @@ -1087,7 +1087,7 @@ struct mtd_dev_s *esp32s3_spiflash_alloc_mtdpart(uint32_t mtd_offset, bool encrypted) { const struct esp32s3_mtd_dev_s *priv; - const esp32s3_spiflash_chip_t *chip; + const esp_rom_spiflash_chip_t *chip; struct mtd_dev_s *mtd_part; uint32_t blocks; uint32_t startblock; diff --git a/arch/xtensa/src/esp32s3/esp32s3_spiram.c b/arch/xtensa/src/esp32s3/esp32s3_spiram.c index 39e24347d172a..c4722167f8926 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_spiram.c +++ b/arch/xtensa/src/esp32s3/esp32s3_spiram.c @@ -37,14 +37,15 @@ #include #include "xtensa.h" -#include "xtensa_attr.h" +#include "esp_attr.h" #include "esp32s3_psram.h" #include "esp32s3_spiram.h" #include "hardware/esp32s3_soc.h" #include "hardware/esp32s3_cache_memory.h" -#include "hardware/esp32s3_extmem.h" #include "hardware/esp32s3_iomux.h" +#include "soc/extmem_reg.h" + #define PSRAM_MODE PSRAM_VADDR_MODE_NORMAL #if defined(CONFIG_ESP32S3_SPIRAM) @@ -551,7 +552,7 @@ int IRAM_ATTR instruction_flash2spiram_offset(void) } #endif -#if defined(CONFIG_ESP32_SPIRAM_RODATA) +#if defined(CONFIG_ESP32S3_SPIRAM_RODATA) void rodata_flash_page_info_init(void) { uint32_t rodata_page_cnt = ((uint32_t)_rodata_reserved_end - diff --git a/arch/xtensa/src/esp32s3/esp32s3_start.c b/arch/xtensa/src/esp32s3/esp32s3_start.c index cc4afb4334d18..922dec107f8f4 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_start.c +++ b/arch/xtensa/src/esp32s3/esp32s3_start.c @@ -31,7 +31,7 @@ #include #include "xtensa.h" -#include "xtensa_attr.h" +#include "esp_attr.h" #include "esp32s3_start.h" #include "esp32s3_lowputc.h" @@ -46,10 +46,26 @@ #include "esp32s3_spi_timing.h" #include "hardware/esp32s3_cache_memory.h" #include "hardware/esp32s3_system.h" -#include "hardware/esp32s3_extmem.h" #include "rom/esp32s3_libc_stubs.h" +#include "rom/opi_flash.h" #include "rom/esp32s3_spiflash.h" -#include "rom/esp32s3_opi_flash.h" + +#include "hal/mmu_hal.h" +#include "hal/mmu_types.h" +#include "hal/cache_types.h" +#include "hal/cache_ll.h" +#include "hal/cache_hal.h" +#include "soc/extmem_reg.h" +#include "rom/cache.h" +#include "spi_flash_mmap.h" + +#ifdef CONFIG_ESPRESSIF_SIMPLE_BOOT +# include "bootloader_init.h" +# include "bootloader_flash_priv.h" +# include "esp_rom_uart.h" +# include "esp_rom_sys.h" +# include "esp_app_format.h" +#endif #include "esp_clk_internal.h" #include "periph_ctrl.h" @@ -64,15 +80,55 @@ # define showprogress(c) #endif -#ifdef CONFIG_ESP32S3_APP_FORMAT_MCUBOOT +#if defined(CONFIG_ESP32S3_APP_FORMAT_MCUBOOT) || \ + defined (CONFIG_ESPRESSIF_SIMPLE_BOOT) +# ifdef CONFIG_ESP32S3_APP_FORMAT_MCUBOOT +# define PRIMARY_SLOT_OFFSET CONFIG_ESP32S3_OTA_PRIMARY_SLOT_OFFSET + /* Cache MMU address mask (MMU tables ignore bits which are zero) */ -#define PRIMARY_SLOT_OFFSET CONFIG_ESP32S3_OTA_PRIMARY_SLOT_OFFSET +# define MMU_FLASH_MASK (~(MMU_PAGE_SIZE - 1)) +# else + /* Force offset to the beginning of the whole image */ -#define HDR_ATTR locate_code(".entry_addr") used_code +# define PRIMARY_SLOT_OFFSET 0 +# endif +# define HDR_ATTR __attribute__((section(".entry_addr"))) \ + __attribute__((used)) +# define MMU_BLOCK_SIZE 0x00010000 /* 64 KB */ +# define CACHE_REG EXTMEM_ICACHE_CTRL1_REG +# define CACHE_MASK (EXTMEM_ICACHE_SHUT_IBUS_M | \ + EXTMEM_ICACHE_SHUT_DBUS_M) + +# define CHECKSUM_ALIGN 16 +# define IS_PADD(addr) (addr == 0) +# define IS_DRAM(addr) (addr >= SOC_DRAM_LOW && addr < SOC_DRAM_HIGH) +# define IS_IRAM(addr) (addr >= SOC_IRAM_LOW && addr < SOC_IRAM_HIGH) +# define IS_IROM(addr) (addr >= SOC_IROM_LOW && addr < SOC_IROM_HIGH) +# define IS_DROM(addr) (addr >= SOC_DROM_LOW && addr < SOC_DROM_HIGH) +# define IS_SRAM(addr) (IS_IRAM(addr) || IS_DRAM(addr)) +# define IS_MMAP(addr) (IS_IROM(addr) || IS_DROM(addr)) +# ifdef SOC_RTC_FAST_MEM_SUPPORTED +# define IS_RTC_FAST_IRAM(addr) \ + (addr >= SOC_RTC_IRAM_LOW && addr < SOC_RTC_IRAM_HIGH) +# define IS_RTC_FAST_DRAM(addr) \ + (addr >= SOC_RTC_DRAM_LOW && addr < SOC_RTC_DRAM_HIGH) +# else +# define IS_RTC_FAST_IRAM(addr) 0 +# define IS_RTC_FAST_DRAM(addr) 0 +# endif +# ifdef SOC_RTC_SLOW_MEM_SUPPORTED +# define IS_RTC_SLOW_DRAM(addr) \ + (addr >= SOC_RTC_DATA_LOW && addr < SOC_RTC_DATA_HIGH) +# else +# define IS_RTC_SLOW_DRAM(addr) 0 +# endif -/* Cache MMU address mask (MMU tables ignore bits which are zero) */ +# define IS_NONE(addr) (!IS_IROM(addr) && !IS_DROM(addr) \ + && !IS_IRAM(addr) && !IS_DRAM(addr) \ + && !IS_RTC_FAST_IRAM(addr) && !IS_RTC_FAST_DRAM(addr) \ + && !IS_RTC_SLOW_DRAM(addr) && !IS_PADD(addr)) -#define MMU_FLASH_MASK (~(MMU_PAGE_SIZE - 1)) +# define IS_MAPPING(addr) IS_IROM(addr) || IS_DROM(addr) #endif @@ -80,7 +136,8 @@ * Private Types ****************************************************************************/ -#ifdef CONFIG_ESP32S3_APP_FORMAT_MCUBOOT +#if defined(CONFIG_ESP32S3_APP_FORMAT_MCUBOOT) || \ + defined (CONFIG_ESPRESSIF_SIMPLE_BOOT) extern uint8_t _image_irom_vma[]; extern uint8_t _image_irom_lma[]; extern uint8_t _image_irom_size[]; @@ -94,14 +151,9 @@ extern uint8_t _image_drom_size[]; * ROM Function Prototypes ****************************************************************************/ -#ifdef CONFIG_ESP32S3_APP_FORMAT_MCUBOOT +#if defined(CONFIG_ESP32S3_APP_FORMAT_MCUBOOT) || \ + defined (CONFIG_ESPRESSIF_SIMPLE_BOOT) extern int ets_printf(const char *fmt, ...) printf_like(1, 2); -extern int cache_dbus_mmu_set(uint32_t ext_ram, uint32_t vaddr, - uint32_t paddr, uint32_t psize, uint32_t num, - uint32_t fixed); -extern int cache_ibus_mmu_set(uint32_t ext_ram, uint32_t vaddr, - uint32_t paddr, uint32_t psize, uint32_t num, - uint32_t fixed); #endif extern void rom_config_instruction_cache_mode(uint32_t cfg_cache_size, @@ -122,7 +174,6 @@ extern void cache_set_idrom_mmu_info(uint32_t instr_page_num, int i_off, int ro_off); #ifdef CONFIG_ESP32S3_DATA_CACHE_16KB -extern void cache_invalidate_dcache_all(void); extern int cache_occupy_addr(uint32_t addr, uint32_t size); #endif @@ -130,15 +181,17 @@ extern int cache_occupy_addr(uint32_t addr, uint32_t size); * Private Function Prototypes ****************************************************************************/ -#ifdef CONFIG_ESP32S3_APP_FORMAT_MCUBOOT -noreturn_function void __start(void); +#if defined(CONFIG_ESP32S3_APP_FORMAT_MCUBOOT) || \ + defined (CONFIG_ESPRESSIF_SIMPLE_BOOT) +IRAM_ATTR noreturn_function void __start(void); #endif /**************************************************************************** * Private Data ****************************************************************************/ -#ifdef CONFIG_ESP32S3_APP_FORMAT_MCUBOOT +#if defined(CONFIG_ESP32S3_APP_FORMAT_MCUBOOT) || \ + defined (CONFIG_ESPRESSIF_SIMPLE_BOOT) HDR_ATTR static void (*_entry_point)(void) = __start; #endif @@ -146,6 +199,8 @@ HDR_ATTR static void (*_entry_point)(void) = __start; * Public Data ****************************************************************************/ +extern uint8_t _instruction_reserved_start[]; +extern uint8_t _instruction_reserved_end[]; extern uint8_t _rodata_reserved_start[]; extern uint8_t _rodata_reserved_end[]; @@ -176,6 +231,17 @@ noinstrument_function static void IRAM_ATTR configure_cpu_caches(void) { int s_instr_flash2spiram_off = 0; int s_rodata_flash2spiram_off = 0; + uint32_t _instruction_size = (uint32_t)&_instruction_reserved_end - + (uint32_t)&_instruction_reserved_start; + uint32_t cache_mmu_irom_size = + ((_instruction_size + SPI_FLASH_MMU_PAGE_SIZE - 1) / + SPI_FLASH_MMU_PAGE_SIZE) * sizeof(uint32_t); + + uint32_t _rodata_size = (uint32_t)&_rodata_reserved_end - + (uint32_t)&_rodata_reserved_start; + uint32_t cache_mmu_drom_size = + ((_rodata_size + SPI_FLASH_MMU_PAGE_SIZE - 1) / + SPI_FLASH_MMU_PAGE_SIZE) * sizeof(uint32_t); /* Configure the mode of instruction cache: cache size, cache line size. */ @@ -195,20 +261,16 @@ noinstrument_function static void IRAM_ATTR configure_cpu_caches(void) /* Configure the Cache MMU size for instruction and rodata in flash. */ - uint32_t rodata_reserved_start_align = - (uint32_t)_rodata_reserved_start & ~(MMU_PAGE_SIZE - 1); - uint32_t cache_mmu_irom_size = - ((rodata_reserved_start_align - SOC_DROM_LOW) / MMU_PAGE_SIZE) * - sizeof(uint32_t); - - uint32_t cache_mmu_drom_size = - (((uint32_t)_rodata_reserved_end - rodata_reserved_start_align + - MMU_PAGE_SIZE - 1) / - MMU_PAGE_SIZE) * sizeof(uint32_t); - cache_set_idrom_mmu_size(cache_mmu_irom_size, CACHE_DROM_MMU_MAX_END - cache_mmu_irom_size); +#if CONFIG_SPIRAM_FETCH_INSTRUCTIONS + s_instr_flash2spiram_off = instruction_flash2spiram_offset(); +#endif +#if CONFIG_SPIRAM_RODATA + s_rodata_flash2spiram_off = rodata_flash2spiram_offset(); +#endif + cache_set_idrom_mmu_info(cache_mmu_irom_size / sizeof(uint32_t), cache_mmu_drom_size / sizeof(uint32_t), (uint32_t)_rodata_reserved_start, @@ -299,6 +361,7 @@ noinstrument_function void noreturn_function IRAM_ATTR __esp32s3_start(void) esp32s3_region_protection(); +#ifndef CONFIG_ESPRESSIF_SIMPLE_BOOT /* Move CPU0 exception vectors to IRAM */ __asm__ __volatile__ ("wsr %0, vecbase\n"::"r" (_init_start)); @@ -311,6 +374,7 @@ noinstrument_function void noreturn_function IRAM_ATTR __esp32s3_start(void) { *dest++ = 0; } +#endif #ifndef CONFIG_SMP /* Make sure that the APP_CPU is disabled for now */ @@ -410,29 +474,6 @@ noinstrument_function void noreturn_function IRAM_ATTR __esp32s3_start(void) for (; ; ); /* Should not return */ } -/**************************************************************************** - * Name: calc_mmu_pages - * - * Description: - * Calculate the number of cache pages to map. - * - * Input Parameters: - * size - Size of data to map - * vaddr - Virtual address where data will be mapped - * - * Returned Value: - * Number of cache MMU pages required to do the mapping. - * - ****************************************************************************/ - -#ifdef CONFIG_ESP32S3_APP_FORMAT_MCUBOOT -static inline uint32_t calc_mmu_pages(uint32_t size, uint32_t vaddr) -{ - return (size + (vaddr - (vaddr & MMU_FLASH_MASK)) + MMU_PAGE_SIZE - 1) / - MMU_PAGE_SIZE; -} -#endif - /**************************************************************************** * Name: map_rom_segments * @@ -447,55 +488,155 @@ static inline uint32_t calc_mmu_pages(uint32_t size, uint32_t vaddr) * ****************************************************************************/ -#ifdef CONFIG_ESP32S3_APP_FORMAT_MCUBOOT -static int map_rom_segments(void) +#if defined(CONFIG_ESP32S3_APP_FORMAT_MCUBOOT) || \ + defined(CONFIG_ESPRESSIF_SIMPLE_BOOT) +static int map_rom_segments(uint32_t app_drom_start, uint32_t app_drom_vaddr, + uint32_t app_drom_size, uint32_t app_irom_start, + uint32_t app_irom_vaddr, uint32_t app_irom_size) { uint32_t rc = 0; - uint32_t regval; - uint32_t drom_lma_aligned; - uint32_t drom_vma_aligned; - uint32_t drom_page_count; - uint32_t irom_lma_aligned; - uint32_t irom_vma_aligned; - uint32_t irom_page_count; + uint32_t actual_mapped_len = 0; + uint32_t app_irom_start_aligned = app_irom_start & MMU_FLASH_MASK; + uint32_t app_irom_vaddr_aligned = app_irom_vaddr & MMU_FLASH_MASK; + uint32_t app_drom_start_aligned = app_drom_start & MMU_FLASH_MASK; + uint32_t app_drom_vaddr_aligned = app_drom_vaddr & MMU_FLASH_MASK; + +#ifdef CONFIG_ESPRESSIF_SIMPLE_BOOT + esp_image_header_t image_header; /* Header for entire image */ + esp_image_segment_header_t WORD_ALIGNED_ATTR segment_hdr; + bool padding_checksum = false; + unsigned int segments = 0; + unsigned int ram_segments = 0; + unsigned int rom_segments = 0; + size_t offset = CONFIG_BOOTLOADER_OFFSET_IN_FLASH; + + /* Read image header */ + + if (bootloader_flash_read(offset, &image_header, + sizeof(esp_image_header_t), + true) != ESP_OK) + { + ets_printf("Failed to load image header!\n"); + abort(); + } - size_t partition_offset = PRIMARY_SLOT_OFFSET; - uint32_t app_irom_lma = partition_offset + (uint32_t)_image_irom_lma; - uint32_t app_irom_size = (uint32_t)_image_irom_size; - uint32_t app_irom_vma = (uint32_t)_image_irom_vma; - uint32_t app_drom_lma = partition_offset + (uint32_t)_image_drom_lma; - uint32_t app_drom_size = (uint32_t)_image_drom_size; - uint32_t app_drom_vma = (uint32_t)_image_drom_vma; - - uint32_t autoload = cache_suspend_dcache(); - cache_invalidate_dcache_all(); + offset += sizeof(esp_image_header_t); - /* Clear the MMU entries that are already set up, so the new app only has - * the mappings it creates. - */ + /* Iterate for segment information parsing */ + + while (segments++ < 16 && rom_segments < 2) + { + /* Read segment header */ + + if (bootloader_flash_read(offset, &segment_hdr, + sizeof(esp_image_segment_header_t), + true) != ESP_OK) + { + ets_printf("failed to read segment header at %x\n", offset); + abort(); + } + + if (IS_NONE(segment_hdr.load_addr)) + { + break; + } + + if (IS_RTC_FAST_IRAM(segment_hdr.load_addr) || + IS_RTC_FAST_DRAM(segment_hdr.load_addr) || + IS_RTC_SLOW_DRAM(segment_hdr.load_addr)) + { + /* RTC segment is loaded by ROM bootloader */ + + ram_segments++; + } + + ets_printf("%s: lma 0x%08x vma 0x%08x len 0x%-6x (%u)\n", + IS_NONE(segment_hdr.load_addr) ? "???" : + IS_RTC_FAST_IRAM(segment_hdr.load_addr) || + IS_RTC_FAST_DRAM(segment_hdr.load_addr) || + IS_RTC_SLOW_DRAM(segment_hdr.load_addr) ? "rtc" : + IS_MMAP(segment_hdr.load_addr) ? + IS_IROM(segment_hdr.load_addr) ? "imap" : "dmap" : + IS_PADD(segment_hdr.load_addr) ? "padd" : + IS_DRAM(segment_hdr.load_addr) ? "dram" : "iram", + offset + sizeof(esp_image_segment_header_t), + segment_hdr.load_addr, segment_hdr.data_len, + segment_hdr.data_len); + + /* Fix drom and irom produced be the linker, as this + * is later invalidated by the elf2image command. + */ + + if (IS_DROM(segment_hdr.load_addr) && + segment_hdr.load_addr == (uint32_t)_image_drom_vma) + { + app_drom_start = offset + sizeof(esp_image_segment_header_t); + app_drom_start_aligned = app_drom_start & MMU_FLASH_MASK; + rom_segments++; + } + + if (IS_IROM(segment_hdr.load_addr) && + segment_hdr.load_addr == (uint32_t)_image_irom_vma) + { + app_irom_start = offset + sizeof(esp_image_segment_header_t); + app_irom_start_aligned = app_irom_start & MMU_FLASH_MASK; + rom_segments++; + } + + if (IS_SRAM(segment_hdr.load_addr)) + { + ram_segments++; + } + + offset += sizeof(esp_image_segment_header_t) + segment_hdr.data_len; + if (ram_segments == image_header.segment_count && !padding_checksum) + { + offset += (CHECKSUM_ALIGN - 1) - (offset % CHECKSUM_ALIGN) + 1; + padding_checksum = true; + } + } - for (size_t i = 0; i < FLASH_MMU_TABLE_SIZE; i++) + if (segments == 0 || segments == 16) { - FLASH_MMU_TABLE[i] = MMU_TABLE_INVALID_VAL; + ets_printf("Error parsing segments\n"); } - drom_lma_aligned = app_drom_lma & MMU_FLASH_MASK; - drom_vma_aligned = app_drom_vma & MMU_FLASH_MASK; - drom_page_count = calc_mmu_pages(app_drom_size, app_drom_vma); - rc = cache_dbus_mmu_set(MMU_ACCESS_FLASH, drom_vma_aligned, - drom_lma_aligned, 64, drom_page_count, 0); + ets_printf("total segments stored %d\n", segments - 1); +#endif + + cache_hal_disable(CACHE_TYPE_ALL); + + /* Clear the MMU entries that are already set up, + * so the new app only has the mappings it creates. + */ - irom_lma_aligned = app_irom_lma & MMU_FLASH_MASK; - irom_vma_aligned = app_irom_vma & MMU_FLASH_MASK; - irom_page_count = calc_mmu_pages(app_irom_size, app_irom_vma); - rc = cache_ibus_mmu_set(MMU_ACCESS_FLASH, irom_vma_aligned, - irom_lma_aligned, 64, irom_page_count, 0); + mmu_hal_unmap_all(); - regval = getreg32(EXTMEM_DCACHE_CTRL1_REG); - regval &= EXTMEM_DCACHE_SHUT_CORE0_BUS; - putreg32(regval, EXTMEM_DCACHE_CTRL1_REG); + mmu_hal_map_region(0, MMU_TARGET_FLASH0, + app_drom_vaddr_aligned, app_drom_start_aligned, + app_drom_size, &actual_mapped_len); - cache_resume_dcache(autoload); + mmu_hal_map_region(0, MMU_TARGET_FLASH0, + app_irom_vaddr_aligned, app_irom_start_aligned, + app_irom_size, &actual_mapped_len); + + /* ------------------Enable corresponding buses--------------------- */ + + cache_bus_mask_t bus_mask = cache_ll_l1_get_bus(0, app_drom_vaddr_aligned, + app_drom_size); + cache_ll_l1_enable_bus(0, bus_mask); + bus_mask = cache_ll_l1_get_bus(0, app_irom_vaddr_aligned, app_irom_size); + cache_ll_l1_enable_bus(0, bus_mask); +#if CONFIG_ESPRESSIF_NUM_CPUS > 1 + bus_mask = cache_ll_l1_get_bus(1, app_drom_vaddr_aligned, app_drom_size); + cache_ll_l1_enable_bus(1, bus_mask); + bus_mask = cache_ll_l1_get_bus(1, app_irom_vaddr_aligned, app_irom_size); + cache_ll_l1_enable_bus(1, bus_mask); +#endif + + /* ------------------Enable Cache----------------------------------- */ + + cache_hal_enable(CACHE_TYPE_ALL); return (int)rc; } @@ -520,14 +661,34 @@ static int map_rom_segments(void) noinstrument_function void IRAM_ATTR __start(void) { -#ifdef CONFIG_ESP32S3_APP_FORMAT_MCUBOOT - if (map_rom_segments() != 0) +#if defined(CONFIG_ESP32S3_APP_FORMAT_MCUBOOT) || \ + defined(CONFIG_ESPRESSIF_SIMPLE_BOOT) + size_t partition_offset = PRIMARY_SLOT_OFFSET; + uint32_t app_irom_start = partition_offset + (uint32_t)_image_irom_lma; + uint32_t app_irom_size = (uint32_t)_image_irom_size; + uint32_t app_irom_vaddr = (uint32_t)_image_irom_vma; + uint32_t app_drom_start = partition_offset + (uint32_t)_image_drom_lma; + uint32_t app_drom_size = (uint32_t)_image_drom_size; + uint32_t app_drom_vaddr = (uint32_t)_image_drom_vma; + +# ifdef CONFIG_ESPRESSIF_SIMPLE_BOOT + __asm__ __volatile__ ("wsr %0, vecbase\n"::"r" (_init_start)); + + if (bootloader_init() != 0) { - ets_printf("Failed to setup XIP, aborting\n"); + ets_printf("Hardware init failed, aborting\n"); while (true); } +# endif + if (map_rom_segments(app_drom_start, app_drom_vaddr, app_drom_size, + app_irom_start, app_irom_vaddr, app_irom_size) != 0) + { + ets_printf("Failed to setup XIP, aborting\n"); + while (true); + } #endif + configure_cpu_caches(); __esp32s3_start(); diff --git a/arch/xtensa/src/esp32s3/esp32s3_twai.c b/arch/xtensa/src/esp32s3/esp32s3_twai.c index ff7ab8e8a431d..c1e54d5b549cf 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_twai.c +++ b/arch/xtensa/src/esp32s3/esp32s3_twai.c @@ -48,6 +48,7 @@ #include "periph_ctrl.h" #include "hardware/esp32s3_system.h" +#include "hardware/esp32s3_twai.h" #include "hardware/esp32s3_gpio_sigmap.h" #if defined(CONFIG_ESP32S3_TWAI) diff --git a/arch/xtensa/src/esp32s3/esp32s3_twai.h b/arch/xtensa/src/esp32s3/esp32s3_twai.h index 7d1cb0ec03431..3bc91016f789a 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_twai.h +++ b/arch/xtensa/src/esp32s3/esp32s3_twai.h @@ -27,7 +27,6 @@ #include #include -#include "hardware/esp32s3_twai.h" /**************************************************************************** * Pre-processor Definitions diff --git a/arch/xtensa/src/esp32s3/esp32s3_userspace.c b/arch/xtensa/src/esp32s3/esp32s3_userspace.c index ca94a1eef5ee6..29edf861f0cfb 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_userspace.c +++ b/arch/xtensa/src/esp32s3/esp32s3_userspace.c @@ -35,17 +35,18 @@ #include "chip.h" #include "xtensa.h" -#include "xtensa_attr.h" +#include "esp_attr.h" #include "esp32s3_irq.h" #include "esp32s3_userspace.h" #include "hardware/esp32s3_apb_ctrl.h" #include "hardware/esp32s3_cache_memory.h" -#include "hardware/esp32s3_extmem.h" #include "hardware/esp32s3_rom_layout.h" #include "hardware/esp32s3_sensitive.h" #include "hardware/esp32s3_soc.h" #include "hardware/esp32s3_wcl_core.h" +#include "soc/extmem_reg.h" + #ifdef CONFIG_BUILD_PROTECTED /**************************************************************************** @@ -80,9 +81,6 @@ #define WCL_SEQ_LAST_VAL 6 -#define I_D_SRAM_OFFSET (SOC_DIRAM_IRAM_LOW - SOC_DIRAM_DRAM_LOW) -#define MAP_IRAM_TO_DRAM(addr) ((addr) - I_D_SRAM_OFFSET) - /* Categories bits for split line configuration */ #define PMS_SRAM_CATEGORY_BELOW 0x0 diff --git a/arch/xtensa/src/esp32s3/esp32s3_wifi_adapter.c b/arch/xtensa/src/esp32s3/esp32s3_wifi_adapter.c index 019e47eeabdcf..0dd7b0dc2a36d 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_wifi_adapter.c +++ b/arch/xtensa/src/esp32s3/esp32s3_wifi_adapter.c @@ -54,7 +54,7 @@ #include #include "xtensa.h" -#include "xtensa_attr.h" +#include "esp_attr.h" #include "hardware/esp32s3_system.h" #include "hardware/esp32s3_rtccntl.h" #include "hardware/esp32s3_syscon.h" diff --git a/arch/xtensa/src/esp32s3/esp32s3_wireless.h b/arch/xtensa/src/esp32s3/esp32s3_wireless.h index 61a6d7aeea474..d4dddbcf8538c 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_wireless.h +++ b/arch/xtensa/src/esp32s3/esp32s3_wireless.h @@ -31,7 +31,7 @@ #include #include -#include "xtensa_attr.h" +#include "esp_attr.h" #include "esp32s3_rt_timer.h" #include "esp_log.h" diff --git a/arch/xtensa/src/esp32s3/hal.mk b/arch/xtensa/src/esp32s3/hal.mk index ce193b5ac4f2f..e4765e39be319 100644 --- a/arch/xtensa/src/esp32s3/hal.mk +++ b/arch/xtensa/src/esp32s3/hal.mk @@ -20,7 +20,9 @@ # Include header paths -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)private_include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)$(CHIP_SERIES)$(DELIM)include @@ -53,8 +55,11 @@ INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)xtensa$(DELIM)$(CHIP_SERIES)$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)xtensa$(DELIM)include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)$(CHIP_SERIES)$(DELIM)include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)private_include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)bootloader_flash$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)include$(DELIM)spi_flash +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_app_format$(DELIM)include # Linker scripts @@ -78,10 +83,15 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)cpu_region_protect.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)esp_clk_tree.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_clk.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_init.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_clk_init.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_sleep.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_time.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)mspi_timing_config.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)esp_clk_tree_common.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)regi2c_ctrl.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)src$(DELIM)phy_init.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mspi_timing_tuning.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_wdt.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)clk.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)system_internal.c @@ -95,6 +105,9 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)rmt_hal.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)timer_hal_iram.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)timer_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)cache_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)mpu_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)mmu_hal.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)uart_hal_iram.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)uart_hal.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)log_noos.c @@ -103,4 +116,42 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)ledc_periph.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)rmt_periph.c +ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y) + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)bootloader_banner_wrap.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_console.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_console_loader.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)${CHIP_SERIES}$(DELIM)bootloader_${CHIP_SERIES}.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_init.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_common.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_common_loader.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)bootloader_flash$(DELIM)src$(DELIM)bootloader_flash.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)bootloader_flash$(DELIM)src$(DELIM)bootloader_flash_config_${CHIP_SERIES}.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_clock_init.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_clock_loader.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_efuse.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_mem.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_random.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_random_${CHIP_SERIES}.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)esp_image_format.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)${CHIP_SERIES}$(DELIM)bootloader_soc.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)${CHIP_SERIES}$(DELIM)bootloader_sha.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)flash_encrypt.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)${CHIP_SERIES}$(DELIM)uart_periph.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_uart.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_sys.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_systimer.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_spiflash.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_cache_esp32s2_esp32s3.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)${CHIP_SERIES}$(DELIM)esp_efuse_fields.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)${CHIP_SERIES}$(DELIM)esp_efuse_utility.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)src$(DELIM)esp_efuse_fields.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)src$(DELIM)esp_efuse_utility.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)src$(DELIM)esp_efuse_api.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)src$(DELIM)efuse_controller$(DELIM)keys$(DELIM)with_key_purposes$(DELIM)esp_efuse_api_key.c + + CHIP_ASRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_cache_writeback_esp32s3.S + + LDFLAGS += --wrap=bootloader_print_banner +endif + CFLAGS += ${DEFINE_PREFIX}ESP_PLATFORM=1 diff --git a/arch/xtensa/src/esp32s3/hardware/esp32s3_cache_memory.h b/arch/xtensa/src/esp32s3/hardware/esp32s3_cache_memory.h index 7e41044b5f4e1..2d3cc64cfee3e 100644 --- a/arch/xtensa/src/esp32s3/hardware/esp32s3_cache_memory.h +++ b/arch/xtensa/src/esp32s3/hardware/esp32s3_cache_memory.h @@ -25,73 +25,12 @@ #include #include "esp32s3_soc.h" +#include "soc/ext_mem_defs.h" /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -/* IRAM0 is connected with Cache IBUS0 */ - -#define IRAM0_ADDRESS_LOW 0x40000000 -#define IRAM0_ADDRESS_HIGH 0x44000000 -#define IRAM0_CACHE_ADDRESS_LOW 0x42000000 -#define IRAM0_CACHE_ADDRESS_HIGH 0x44000000 - -/* DRAM0 is connected with Cache DBUS0 */ - -#define DRAM0_ADDRESS_LOW 0x3c000000 -#define DRAM0_ADDRESS_HIGH 0x40000000 -#define DRAM0_CACHE_ADDRESS_LOW 0x3c000000 -#define DRAM0_CACHE_ADDRESS_HIGH 0x3e000000 -#define DRAM0_CACHE_OPERATION_HIGH DRAM0_CACHE_ADDRESS_HIGH -#define ESP_CACHE_TEMP_ADDR 0x3c800000 - -#define BUS_SIZE(bus_name) (bus_name##_ADDRESS_HIGH - \ - bus_name##_ADDRESS_LOW) -#define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW \ - && (vaddr) < \ - bus_name##_ADDRESS_HIGH) - -#define ADDRESS_IN_IRAM0(vaddr) ADDRESS_IN_BUS(IRAM0, vaddr) -#define ADDRESS_IN_IRAM0_CACHE(vaddr) ADDRESS_IN_BUS(IRAM0_CACHE, vaddr) -#define ADDRESS_IN_DRAM0(vaddr) ADDRESS_IN_BUS(DRAM0, vaddr) -#define ADDRESS_IN_DRAM0_CACHE(vaddr) ADDRESS_IN_BUS(DRAM0_CACHE, vaddr) - -#define BUS_IRAM0_CACHE_SIZE BUS_SIZE(IRAM0_CACHE) -#define BUS_DRAM0_CACHE_SIZE BUS_SIZE(DRAM0_CACHE) - -#define CACHE_IBUS 0 -#define CACHE_IBUS_MMU_START 0 -#define CACHE_IBUS_MMU_END 0x800 - -#define CACHE_DBUS 1 -#define CACHE_DBUS_MMU_START 0 -#define CACHE_DBUS_MMU_END 0x800 - -#define CACHE_IROM_MMU_START 0 -#define CACHE_IROM_MMU_END Cache_Get_IROM_MMU_End() -#define CACHE_IROM_MMU_SIZE (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START) - -#define CACHE_DROM_MMU_START CACHE_IROM_MMU_END -#define CACHE_DROM_MMU_END Cache_Get_DROM_MMU_End() -#define CACHE_DROM_MMU_SIZE (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START) - -#define CACHE_DROM_MMU_MAX_END 0x400 - -#define ICACHE_MMU_SIZE 0x800 -#define DCACHE_MMU_SIZE 0x800 - -#define MMU_BUS_START(i) 0 -#define MMU_BUS_SIZE(i) 0x800 - -#define MMU_INVALID BIT(14) -#define MMU_TYPE BIT(15) -#define MMU_ACCESS_FLASH 0 -#define MMU_ACCESS_SPIRAM BIT(15) - -#define CACHE_MAX_SYNC_NUM 0x400000 -#define CACHE_MAX_LOCK_NUM 0x8000 - #define FLASH_MMU_TABLE ((volatile uint32_t *)DR_REG_MMU_TABLE) #define FLASH_MMU_TABLE_SIZE (ICACHE_MMU_SIZE / sizeof(uint32_t)) @@ -104,15 +43,4 @@ #define BUS_ADDR_SIZE 0x200000 #define BUS_ADDR_MASK (BUS_ADDR_SIZE - 1) -#define CACHE_ICACHE_LOW_SHIFT 0 -#define CACHE_ICACHE_HIGH_SHIFT 2 -#define CACHE_DCACHE_LOW_SHIFT 4 -#define CACHE_DCACHE_HIGH_SHIFT 6 - -#define CACHE_MEMORY_IBANK0_ADDR 0x40370000 -#define CACHE_MEMORY_IBANK1_ADDR 0x40374000 - -#define CACHE_MEMORY_DBANK0_ADDR 0x3fcf0000 -#define CACHE_MEMORY_DBANK1_ADDR 0x3fcf8000 - #endif /* __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_CACHE_MEMORY_H */ diff --git a/arch/xtensa/src/esp32s3/hardware/esp32s3_extmem.h b/arch/xtensa/src/esp32s3/hardware/esp32s3_extmem.h deleted file mode 100644 index 8d19cfb61ce0f..0000000000000 --- a/arch/xtensa/src/esp32s3/hardware/esp32s3_extmem.h +++ /dev/null @@ -1,2761 +0,0 @@ -/**************************************************************************** - * arch/xtensa/src/esp32s3/hardware/esp32s3_extmem.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_EXTMEM_H -#define __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_EXTMEM_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include "esp32s3_soc.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* EXTMEM_DCACHE_CTRL_REG register - * ******* Description *********** - */ - -#define EXTMEM_DCACHE_CTRL_REG (DR_REG_EXTMEM_BASE + 0x0) - -/* EXTMEM_DCACHE_BLOCKSIZE_MODE : R/W; bitpos: [4:3]; default: 0; - * The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes,2: - * 64 bytes - */ - -#define EXTMEM_DCACHE_BLOCKSIZE_MODE 0x00000003 -#define EXTMEM_DCACHE_BLOCKSIZE_MODE_M (EXTMEM_DCACHE_BLOCKSIZE_MODE_V << EXTMEM_DCACHE_BLOCKSIZE_MODE_S) -#define EXTMEM_DCACHE_BLOCKSIZE_MODE_V 0x00000003 -#define EXTMEM_DCACHE_BLOCKSIZE_MODE_S 3 - -/* EXTMEM_DCACHE_SIZE_MODE : R/W; bitpos: [2]; default: 0; - * The bit is used to configure cache memory size.0: 32KB, 1: 64KB - */ - -#define EXTMEM_DCACHE_SIZE_MODE (BIT(2)) -#define EXTMEM_DCACHE_SIZE_MODE_M (EXTMEM_DCACHE_SIZE_MODE_V << EXTMEM_DCACHE_SIZE_MODE_S) -#define EXTMEM_DCACHE_SIZE_MODE_V 0x00000001 -#define EXTMEM_DCACHE_SIZE_MODE_S 2 - -/* EXTMEM_DCACHE_ENABLE : R/W; bitpos: [0]; default: 0; - * The bit is used to activate the data cache. 0: disable, 1: enable - */ - -#define EXTMEM_DCACHE_ENABLE (BIT(0)) -#define EXTMEM_DCACHE_ENABLE_M (EXTMEM_DCACHE_ENABLE_V << EXTMEM_DCACHE_ENABLE_S) -#define EXTMEM_DCACHE_ENABLE_V 0x00000001 -#define EXTMEM_DCACHE_ENABLE_S 0 - -/* EXTMEM_DCACHE_CTRL1_REG register - * ******* Description *********** - */ - -#define EXTMEM_DCACHE_CTRL1_REG (DR_REG_EXTMEM_BASE + 0x4) - -/* EXTMEM_DCACHE_SHUT_CORE1_BUS : R/W; bitpos: [1]; default: 1; - * The bit is used to disable core1 dbus, 0: enable, 1: disable - */ - -#define EXTMEM_DCACHE_SHUT_CORE1_BUS (BIT(1)) -#define EXTMEM_DCACHE_SHUT_CORE1_BUS_M (EXTMEM_DCACHE_SHUT_CORE1_BUS_V << EXTMEM_DCACHE_SHUT_CORE1_BUS_S) -#define EXTMEM_DCACHE_SHUT_CORE1_BUS_V 0x00000001 -#define EXTMEM_DCACHE_SHUT_CORE1_BUS_S 1 - -/* EXTMEM_DCACHE_SHUT_CORE0_BUS : R/W; bitpos: [0]; default: 1; - * The bit is used to disable core0 dbus, 0: enable, 1: disable - */ - -#define EXTMEM_DCACHE_SHUT_CORE0_BUS (BIT(0)) -#define EXTMEM_DCACHE_SHUT_CORE0_BUS_M (EXTMEM_DCACHE_SHUT_CORE0_BUS_V << EXTMEM_DCACHE_SHUT_CORE0_BUS_S) -#define EXTMEM_DCACHE_SHUT_CORE0_BUS_V 0x00000001 -#define EXTMEM_DCACHE_SHUT_CORE0_BUS_S 0 - -/* EXTMEM_DCACHE_TAG_POWER_CTRL_REG register - * ******* Description *********** - */ - -#define EXTMEM_DCACHE_TAG_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x8) - -/* EXTMEM_DCACHE_TAG_MEM_FORCE_PU : R/W; bitpos: [2]; default: 1; - * The bit is used to power dcache tag memory up, 0: follow rtc_lslp_pd, 1: - * power up - */ - -#define EXTMEM_DCACHE_TAG_MEM_FORCE_PU (BIT(2)) -#define EXTMEM_DCACHE_TAG_MEM_FORCE_PU_M (EXTMEM_DCACHE_TAG_MEM_FORCE_PU_V << EXTMEM_DCACHE_TAG_MEM_FORCE_PU_S) -#define EXTMEM_DCACHE_TAG_MEM_FORCE_PU_V 0x00000001 -#define EXTMEM_DCACHE_TAG_MEM_FORCE_PU_S 2 - -/* EXTMEM_DCACHE_TAG_MEM_FORCE_PD : R/W; bitpos: [1]; default: 0; - * The bit is used to power dcache tag memory down, 0: follow rtc_lslp_pd, - * 1: power down - */ - -#define EXTMEM_DCACHE_TAG_MEM_FORCE_PD (BIT(1)) -#define EXTMEM_DCACHE_TAG_MEM_FORCE_PD_M (EXTMEM_DCACHE_TAG_MEM_FORCE_PD_V << EXTMEM_DCACHE_TAG_MEM_FORCE_PD_S) -#define EXTMEM_DCACHE_TAG_MEM_FORCE_PD_V 0x00000001 -#define EXTMEM_DCACHE_TAG_MEM_FORCE_PD_S 1 - -/* EXTMEM_DCACHE_TAG_MEM_FORCE_ON : R/W; bitpos: [0]; default: 1; - * The bit is used to close clock gating of dcache tag memory. 1: close - * gating, 0: open clock gating. - */ - -#define EXTMEM_DCACHE_TAG_MEM_FORCE_ON (BIT(0)) -#define EXTMEM_DCACHE_TAG_MEM_FORCE_ON_M (EXTMEM_DCACHE_TAG_MEM_FORCE_ON_V << EXTMEM_DCACHE_TAG_MEM_FORCE_ON_S) -#define EXTMEM_DCACHE_TAG_MEM_FORCE_ON_V 0x00000001 -#define EXTMEM_DCACHE_TAG_MEM_FORCE_ON_S 0 - -/* EXTMEM_DCACHE_PRELOCK_CTRL_REG register - * ******* Description *********** - */ - -#define EXTMEM_DCACHE_PRELOCK_CTRL_REG (DR_REG_EXTMEM_BASE + 0xc) - -/* EXTMEM_DCACHE_PRELOCK_SCT1_EN : R/W; bitpos: [1]; default: 0; - * The bit is used to enable the second section of prelock function. - */ - -#define EXTMEM_DCACHE_PRELOCK_SCT1_EN (BIT(1)) -#define EXTMEM_DCACHE_PRELOCK_SCT1_EN_M (EXTMEM_DCACHE_PRELOCK_SCT1_EN_V << EXTMEM_DCACHE_PRELOCK_SCT1_EN_S) -#define EXTMEM_DCACHE_PRELOCK_SCT1_EN_V 0x00000001 -#define EXTMEM_DCACHE_PRELOCK_SCT1_EN_S 1 - -/* EXTMEM_DCACHE_PRELOCK_SCT0_EN : R/W; bitpos: [0]; default: 0; - * The bit is used to enable the first section of prelock function. - */ - -#define EXTMEM_DCACHE_PRELOCK_SCT0_EN (BIT(0)) -#define EXTMEM_DCACHE_PRELOCK_SCT0_EN_M (EXTMEM_DCACHE_PRELOCK_SCT0_EN_V << EXTMEM_DCACHE_PRELOCK_SCT0_EN_S) -#define EXTMEM_DCACHE_PRELOCK_SCT0_EN_V 0x00000001 -#define EXTMEM_DCACHE_PRELOCK_SCT0_EN_S 0 - -/* EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_REG register - * ******* Description *********** - */ - -#define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_REG (DR_REG_EXTMEM_BASE + 0x10) - -/* EXTMEM_DCACHE_PRELOCK_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0; - * The bits are used to configure the first start virtual address of data - * prelock, which is combined with DCACHE_PRELOCK_SCT0_SIZE_REG - */ - -#define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR 0xffffffff -#define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_M (EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_V << EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_S) -#define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_V 0xffffffff -#define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_S 0 - -/* EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_REG register - * ******* Description *********** - */ - -#define EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_REG (DR_REG_EXTMEM_BASE + 0x14) - -/* EXTMEM_DCACHE_PRELOCK_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0; - * The bits are used to configure the second start virtual address of data - * prelock, which is combined with DCACHE_PRELOCK_SCT1_SIZE_REG - */ - -#define EXTMEM_DCACHE_PRELOCK_SCT1_ADDR 0xffffffff -#define EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_M (EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_V << EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_S) -#define EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_V 0xffffffff -#define EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_S 0 - -/* EXTMEM_DCACHE_PRELOCK_SCT_SIZE_REG register - * ******* Description *********** - */ - -#define EXTMEM_DCACHE_PRELOCK_SCT_SIZE_REG (DR_REG_EXTMEM_BASE + 0x18) - -/* EXTMEM_DCACHE_PRELOCK_SCT0_SIZE : R/W; bitpos: [31:16]; default: 0; - * The bits are used to configure the first length of data locking, which is - * combined with DCACHE_PRELOCK_SCT0_ADDR_REG - */ - -#define EXTMEM_DCACHE_PRELOCK_SCT0_SIZE 0x0000ffff -#define EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_M (EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_V << EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_S) -#define EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_V 0x0000ffff -#define EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_S 16 - -/* EXTMEM_DCACHE_PRELOCK_SCT1_SIZE : R/W; bitpos: [15:0]; default: 0; - * The bits are used to configure the second length of data locking, which - * is combined with DCACHE_PRELOCK_SCT1_ADDR_REG - */ - -#define EXTMEM_DCACHE_PRELOCK_SCT1_SIZE 0x0000ffff -#define EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_M (EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_V << EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_S) -#define EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_V 0x0000ffff -#define EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_S 0 - -/* EXTMEM_DCACHE_LOCK_CTRL_REG register - * ******* Description *********** - */ - -#define EXTMEM_DCACHE_LOCK_CTRL_REG (DR_REG_EXTMEM_BASE + 0x1c) - -/* EXTMEM_DCACHE_LOCK_DONE : RO; bitpos: [2]; default: 1; - * The bit is used to indicate unlock/lock operation is finished. - */ - -#define EXTMEM_DCACHE_LOCK_DONE (BIT(2)) -#define EXTMEM_DCACHE_LOCK_DONE_M (EXTMEM_DCACHE_LOCK_DONE_V << EXTMEM_DCACHE_LOCK_DONE_S) -#define EXTMEM_DCACHE_LOCK_DONE_V 0x00000001 -#define EXTMEM_DCACHE_LOCK_DONE_S 2 - -/* EXTMEM_DCACHE_UNLOCK_ENA : R/W; bitpos: [1]; default: 0; - * The bit is used to enable unlock operation. It will be cleared by - * hardware after unlock operation done. - */ - -#define EXTMEM_DCACHE_UNLOCK_ENA (BIT(1)) -#define EXTMEM_DCACHE_UNLOCK_ENA_M (EXTMEM_DCACHE_UNLOCK_ENA_V << EXTMEM_DCACHE_UNLOCK_ENA_S) -#define EXTMEM_DCACHE_UNLOCK_ENA_V 0x00000001 -#define EXTMEM_DCACHE_UNLOCK_ENA_S 1 - -/* EXTMEM_DCACHE_LOCK_ENA : R/W; bitpos: [0]; default: 0; - * The bit is used to enable lock operation. It will be cleared by hardware - * after lock operation done. - */ - -#define EXTMEM_DCACHE_LOCK_ENA (BIT(0)) -#define EXTMEM_DCACHE_LOCK_ENA_M (EXTMEM_DCACHE_LOCK_ENA_V << EXTMEM_DCACHE_LOCK_ENA_S) -#define EXTMEM_DCACHE_LOCK_ENA_V 0x00000001 -#define EXTMEM_DCACHE_LOCK_ENA_S 0 - -/* EXTMEM_DCACHE_LOCK_ADDR_REG register - * ******* Description *********** - */ - -#define EXTMEM_DCACHE_LOCK_ADDR_REG (DR_REG_EXTMEM_BASE + 0x20) - -/* EXTMEM_DCACHE_LOCK_ADDR : R/W; bitpos: [31:0]; default: 0; - * The bits are used to configure the start virtual address for lock - * operations. It should be combined with DCACHE_LOCK_SIZE_REG. - */ - -#define EXTMEM_DCACHE_LOCK_ADDR 0xffffffff -#define EXTMEM_DCACHE_LOCK_ADDR_M (EXTMEM_DCACHE_LOCK_ADDR_V << EXTMEM_DCACHE_LOCK_ADDR_S) -#define EXTMEM_DCACHE_LOCK_ADDR_V 0xffffffff -#define EXTMEM_DCACHE_LOCK_ADDR_S 0 - -/* EXTMEM_DCACHE_LOCK_SIZE_REG register - * ******* Description *********** - */ - -#define EXTMEM_DCACHE_LOCK_SIZE_REG (DR_REG_EXTMEM_BASE + 0x24) - -/* EXTMEM_DCACHE_LOCK_SIZE : R/W; bitpos: [15:0]; default: 0; - * The bits are used to configure the length for lock operations. The bits - * are the counts of cache block. It should be combined with - * DCACHE_LOCK_ADDR_REG. - */ - -#define EXTMEM_DCACHE_LOCK_SIZE 0x0000ffff -#define EXTMEM_DCACHE_LOCK_SIZE_M (EXTMEM_DCACHE_LOCK_SIZE_V << EXTMEM_DCACHE_LOCK_SIZE_S) -#define EXTMEM_DCACHE_LOCK_SIZE_V 0x0000ffff -#define EXTMEM_DCACHE_LOCK_SIZE_S 0 - -/* EXTMEM_DCACHE_SYNC_CTRL_REG register - * ******* Description *********** - */ - -#define EXTMEM_DCACHE_SYNC_CTRL_REG (DR_REG_EXTMEM_BASE + 0x28) - -/* EXTMEM_DCACHE_SYNC_DONE : RO; bitpos: [3]; default: 0; - * The bit is used to indicate clean/writeback/invalidate operation is - * finished. - */ - -#define EXTMEM_DCACHE_SYNC_DONE (BIT(3)) -#define EXTMEM_DCACHE_SYNC_DONE_M (EXTMEM_DCACHE_SYNC_DONE_V << EXTMEM_DCACHE_SYNC_DONE_S) -#define EXTMEM_DCACHE_SYNC_DONE_V 0x00000001 -#define EXTMEM_DCACHE_SYNC_DONE_S 3 - -/* EXTMEM_DCACHE_CLEAN_ENA : R/W; bitpos: [2]; default: 0; - * The bit is used to enable clean operation. It will be cleared by hardware - * after clean operation done. - */ - -#define EXTMEM_DCACHE_CLEAN_ENA (BIT(2)) -#define EXTMEM_DCACHE_CLEAN_ENA_M (EXTMEM_DCACHE_CLEAN_ENA_V << EXTMEM_DCACHE_CLEAN_ENA_S) -#define EXTMEM_DCACHE_CLEAN_ENA_V 0x00000001 -#define EXTMEM_DCACHE_CLEAN_ENA_S 2 - -/* EXTMEM_DCACHE_WRITEBACK_ENA : R/W; bitpos: [1]; default: 0; - * The bit is used to enable writeback operation. It will be cleared by - * hardware after writeback operation done. - */ - -#define EXTMEM_DCACHE_WRITEBACK_ENA (BIT(1)) -#define EXTMEM_DCACHE_WRITEBACK_ENA_M (EXTMEM_DCACHE_WRITEBACK_ENA_V << EXTMEM_DCACHE_WRITEBACK_ENA_S) -#define EXTMEM_DCACHE_WRITEBACK_ENA_V 0x00000001 -#define EXTMEM_DCACHE_WRITEBACK_ENA_S 1 - -/* EXTMEM_DCACHE_INVALIDATE_ENA : R/W; bitpos: [0]; default: 1; - * The bit is used to enable invalidate operation. It will be cleared by - * hardware after invalidate operation done. - */ - -#define EXTMEM_DCACHE_INVALIDATE_ENA (BIT(0)) -#define EXTMEM_DCACHE_INVALIDATE_ENA_M (EXTMEM_DCACHE_INVALIDATE_ENA_V << EXTMEM_DCACHE_INVALIDATE_ENA_S) -#define EXTMEM_DCACHE_INVALIDATE_ENA_V 0x00000001 -#define EXTMEM_DCACHE_INVALIDATE_ENA_S 0 - -/* EXTMEM_DCACHE_SYNC_ADDR_REG register - * ******* Description *********** - */ - -#define EXTMEM_DCACHE_SYNC_ADDR_REG (DR_REG_EXTMEM_BASE + 0x2c) - -/* EXTMEM_DCACHE_SYNC_ADDR : R/W; bitpos: [31:0]; default: 0; - * The bits are used to configure the start virtual address for clean - * operations. It should be combined with DCACHE_SYNC_SIZE_REG. - */ - -#define EXTMEM_DCACHE_SYNC_ADDR 0xffffffff -#define EXTMEM_DCACHE_SYNC_ADDR_M (EXTMEM_DCACHE_SYNC_ADDR_V << EXTMEM_DCACHE_SYNC_ADDR_S) -#define EXTMEM_DCACHE_SYNC_ADDR_V 0xffffffff -#define EXTMEM_DCACHE_SYNC_ADDR_S 0 - -/* EXTMEM_DCACHE_SYNC_SIZE_REG register - * ******* Description *********** - */ - -#define EXTMEM_DCACHE_SYNC_SIZE_REG (DR_REG_EXTMEM_BASE + 0x30) - -/* EXTMEM_DCACHE_SYNC_SIZE : R/W; bitpos: [22:0]; default: 0; - * The bits are used to configure the length for sync operations. The bits - * are the counts of cache block. It should be combined with - * DCACHE_SYNC_ADDR_REG. - */ - -#define EXTMEM_DCACHE_SYNC_SIZE 0x007fffff -#define EXTMEM_DCACHE_SYNC_SIZE_M (EXTMEM_DCACHE_SYNC_SIZE_V << EXTMEM_DCACHE_SYNC_SIZE_S) -#define EXTMEM_DCACHE_SYNC_SIZE_V 0x007fffff -#define EXTMEM_DCACHE_SYNC_SIZE_S 0 - -/* EXTMEM_DCACHE_OCCUPY_CTRL_REG register - * ******* Description *********** - */ - -#define EXTMEM_DCACHE_OCCUPY_CTRL_REG (DR_REG_EXTMEM_BASE + 0x34) - -/* EXTMEM_DCACHE_OCCUPY_DONE : RO; bitpos: [1]; default: 1; - * The bit is used to indicate occupy operation is finished. - */ - -#define EXTMEM_DCACHE_OCCUPY_DONE (BIT(1)) -#define EXTMEM_DCACHE_OCCUPY_DONE_M (EXTMEM_DCACHE_OCCUPY_DONE_V << EXTMEM_DCACHE_OCCUPY_DONE_S) -#define EXTMEM_DCACHE_OCCUPY_DONE_V 0x00000001 -#define EXTMEM_DCACHE_OCCUPY_DONE_S 1 - -/* EXTMEM_DCACHE_OCCUPY_ENA : R/W; bitpos: [0]; default: 0; - * The bit is used to enable occupy operation. It will be cleared by - * hardware after issuing Auot-Invalidate Operation. - */ - -#define EXTMEM_DCACHE_OCCUPY_ENA (BIT(0)) -#define EXTMEM_DCACHE_OCCUPY_ENA_M (EXTMEM_DCACHE_OCCUPY_ENA_V << EXTMEM_DCACHE_OCCUPY_ENA_S) -#define EXTMEM_DCACHE_OCCUPY_ENA_V 0x00000001 -#define EXTMEM_DCACHE_OCCUPY_ENA_S 0 - -/* EXTMEM_DCACHE_OCCUPY_ADDR_REG register - * ******* Description *********** - */ - -#define EXTMEM_DCACHE_OCCUPY_ADDR_REG (DR_REG_EXTMEM_BASE + 0x38) - -/* EXTMEM_DCACHE_OCCUPY_ADDR : R/W; bitpos: [31:0]; default: 0; - * The bits are used to configure the start virtual address for occupy - * operation. It should be combined with DCACHE_OCCUPY_SIZE_REG. - */ - -#define EXTMEM_DCACHE_OCCUPY_ADDR 0xffffffff -#define EXTMEM_DCACHE_OCCUPY_ADDR_M (EXTMEM_DCACHE_OCCUPY_ADDR_V << EXTMEM_DCACHE_OCCUPY_ADDR_S) -#define EXTMEM_DCACHE_OCCUPY_ADDR_V 0xffffffff -#define EXTMEM_DCACHE_OCCUPY_ADDR_S 0 - -/* EXTMEM_DCACHE_OCCUPY_SIZE_REG register - * ******* Description *********** - */ - -#define EXTMEM_DCACHE_OCCUPY_SIZE_REG (DR_REG_EXTMEM_BASE + 0x3c) - -/* EXTMEM_DCACHE_OCCUPY_SIZE : R/W; bitpos: [15:0]; default: 0; - * The bits are used to configure the length for occupy operation. The bits - * are the counts of cache block. It should be combined with - * DCACHE_OCCUPY_ADDR_REG. - */ - -#define EXTMEM_DCACHE_OCCUPY_SIZE 0x0000ffff -#define EXTMEM_DCACHE_OCCUPY_SIZE_M (EXTMEM_DCACHE_OCCUPY_SIZE_V << EXTMEM_DCACHE_OCCUPY_SIZE_S) -#define EXTMEM_DCACHE_OCCUPY_SIZE_V 0x0000ffff -#define EXTMEM_DCACHE_OCCUPY_SIZE_S 0 - -/* EXTMEM_DCACHE_PRELOAD_CTRL_REG register - * ******* Description *********** - */ - -#define EXTMEM_DCACHE_PRELOAD_CTRL_REG (DR_REG_EXTMEM_BASE + 0x40) - -/* EXTMEM_DCACHE_PRELOAD_ORDER : R/W; bitpos: [2]; default: 0; - * The bit is used to configure the direction of preload operation. 1: - * descending, 0: ascending. - */ - -#define EXTMEM_DCACHE_PRELOAD_ORDER (BIT(2)) -#define EXTMEM_DCACHE_PRELOAD_ORDER_M (EXTMEM_DCACHE_PRELOAD_ORDER_V << EXTMEM_DCACHE_PRELOAD_ORDER_S) -#define EXTMEM_DCACHE_PRELOAD_ORDER_V 0x00000001 -#define EXTMEM_DCACHE_PRELOAD_ORDER_S 2 - -/* EXTMEM_DCACHE_PRELOAD_DONE : RO; bitpos: [1]; default: 1; - * The bit is used to indicate preload operation is finished. - */ - -#define EXTMEM_DCACHE_PRELOAD_DONE (BIT(1)) -#define EXTMEM_DCACHE_PRELOAD_DONE_M (EXTMEM_DCACHE_PRELOAD_DONE_V << EXTMEM_DCACHE_PRELOAD_DONE_S) -#define EXTMEM_DCACHE_PRELOAD_DONE_V 0x00000001 -#define EXTMEM_DCACHE_PRELOAD_DONE_S 1 - -/* EXTMEM_DCACHE_PRELOAD_ENA : R/W; bitpos: [0]; default: 0; - * The bit is used to enable preload operation. It will be cleared by - * hardware after preload operation done. - */ - -#define EXTMEM_DCACHE_PRELOAD_ENA (BIT(0)) -#define EXTMEM_DCACHE_PRELOAD_ENA_M (EXTMEM_DCACHE_PRELOAD_ENA_V << EXTMEM_DCACHE_PRELOAD_ENA_S) -#define EXTMEM_DCACHE_PRELOAD_ENA_V 0x00000001 -#define EXTMEM_DCACHE_PRELOAD_ENA_S 0 - -/* EXTMEM_DCACHE_PRELOAD_ADDR_REG register - * ******* Description *********** - */ - -#define EXTMEM_DCACHE_PRELOAD_ADDR_REG (DR_REG_EXTMEM_BASE + 0x44) - -/* EXTMEM_DCACHE_PRELOAD_ADDR : R/W; bitpos: [31:0]; default: 0; - * The bits are used to configure the start virtual address for preload - * operation. It should be combined with DCACHE_PRELOAD_SIZE_REG. - */ - -#define EXTMEM_DCACHE_PRELOAD_ADDR 0xffffffff -#define EXTMEM_DCACHE_PRELOAD_ADDR_M (EXTMEM_DCACHE_PRELOAD_ADDR_V << EXTMEM_DCACHE_PRELOAD_ADDR_S) -#define EXTMEM_DCACHE_PRELOAD_ADDR_V 0xffffffff -#define EXTMEM_DCACHE_PRELOAD_ADDR_S 0 - -/* EXTMEM_DCACHE_PRELOAD_SIZE_REG register - * ******* Description *********** - */ - -#define EXTMEM_DCACHE_PRELOAD_SIZE_REG (DR_REG_EXTMEM_BASE + 0x48) - -/* EXTMEM_DCACHE_PRELOAD_SIZE : R/W; bitpos: [15:0]; default: 0; - * The bits are used to configure the length for preload operation. The bits - * are the counts of cache block. It should be combined with - * DCACHE_PRELOAD_ADDR_REG.. - */ - -#define EXTMEM_DCACHE_PRELOAD_SIZE 0x0000ffff -#define EXTMEM_DCACHE_PRELOAD_SIZE_M (EXTMEM_DCACHE_PRELOAD_SIZE_V << EXTMEM_DCACHE_PRELOAD_SIZE_S) -#define EXTMEM_DCACHE_PRELOAD_SIZE_V 0x0000ffff -#define EXTMEM_DCACHE_PRELOAD_SIZE_S 0 - -/* EXTMEM_DCACHE_AUTOLOAD_CTRL_REG register - * ******* Description *********** - */ - -#define EXTMEM_DCACHE_AUTOLOAD_CTRL_REG (DR_REG_EXTMEM_BASE + 0x4c) - -/* EXTMEM_DCACHE_AUTOLOAD_BUFFER_CLEAR : R/W; bitpos: [9]; default: 0; - * The bit is used to clear autoload buffer in dcache. - */ - -#define EXTMEM_DCACHE_AUTOLOAD_BUFFER_CLEAR (BIT(9)) -#define EXTMEM_DCACHE_AUTOLOAD_BUFFER_CLEAR_M (EXTMEM_DCACHE_AUTOLOAD_BUFFER_CLEAR_V << EXTMEM_DCACHE_AUTOLOAD_BUFFER_CLEAR_S) -#define EXTMEM_DCACHE_AUTOLOAD_BUFFER_CLEAR_V 0x00000001 -#define EXTMEM_DCACHE_AUTOLOAD_BUFFER_CLEAR_S 9 - -/* EXTMEM_DCACHE_AUTOLOAD_SIZE : R/W; bitpos: [8:7]; default: 0; - * The bits are used to configure the numbers of the cache block for the - * issuing autoload operation. - */ - -#define EXTMEM_DCACHE_AUTOLOAD_SIZE 0x00000003 -#define EXTMEM_DCACHE_AUTOLOAD_SIZE_M (EXTMEM_DCACHE_AUTOLOAD_SIZE_V << EXTMEM_DCACHE_AUTOLOAD_SIZE_S) -#define EXTMEM_DCACHE_AUTOLOAD_SIZE_V 0x00000003 -#define EXTMEM_DCACHE_AUTOLOAD_SIZE_S 7 - -/* EXTMEM_DCACHE_AUTOLOAD_RQST : R/W; bitpos: [6:5]; default: 0; - * The bits are used to configure trigger conditions for autoload. 0/3: - * cache miss, 1: cache hit, 2: both cache miss and hit. - */ - -#define EXTMEM_DCACHE_AUTOLOAD_RQST 0x00000003 -#define EXTMEM_DCACHE_AUTOLOAD_RQST_M (EXTMEM_DCACHE_AUTOLOAD_RQST_V << EXTMEM_DCACHE_AUTOLOAD_RQST_S) -#define EXTMEM_DCACHE_AUTOLOAD_RQST_V 0x00000003 -#define EXTMEM_DCACHE_AUTOLOAD_RQST_S 5 - -/* EXTMEM_DCACHE_AUTOLOAD_ORDER : R/W; bitpos: [4]; default: 0; - * The bits are used to configure the direction of autoload. 1: descending, - * 0: ascending. - */ - -#define EXTMEM_DCACHE_AUTOLOAD_ORDER (BIT(4)) -#define EXTMEM_DCACHE_AUTOLOAD_ORDER_M (EXTMEM_DCACHE_AUTOLOAD_ORDER_V << EXTMEM_DCACHE_AUTOLOAD_ORDER_S) -#define EXTMEM_DCACHE_AUTOLOAD_ORDER_V 0x00000001 -#define EXTMEM_DCACHE_AUTOLOAD_ORDER_S 4 - -/* EXTMEM_DCACHE_AUTOLOAD_DONE : RO; bitpos: [3]; default: 1; - * The bit is used to indicate autoload operation is finished. - */ - -#define EXTMEM_DCACHE_AUTOLOAD_DONE (BIT(3)) -#define EXTMEM_DCACHE_AUTOLOAD_DONE_M (EXTMEM_DCACHE_AUTOLOAD_DONE_V << EXTMEM_DCACHE_AUTOLOAD_DONE_S) -#define EXTMEM_DCACHE_AUTOLOAD_DONE_V 0x00000001 -#define EXTMEM_DCACHE_AUTOLOAD_DONE_S 3 - -/* EXTMEM_DCACHE_AUTOLOAD_ENA : R/W; bitpos: [2]; default: 0; - * The bit is used to enable and disable autoload operation. It is combined - * with dcache_autoload_done. 1: enable, 0: disable. - */ - -#define EXTMEM_DCACHE_AUTOLOAD_ENA (BIT(2)) -#define EXTMEM_DCACHE_AUTOLOAD_ENA_M (EXTMEM_DCACHE_AUTOLOAD_ENA_V << EXTMEM_DCACHE_AUTOLOAD_ENA_S) -#define EXTMEM_DCACHE_AUTOLOAD_ENA_V 0x00000001 -#define EXTMEM_DCACHE_AUTOLOAD_ENA_S 2 - -/* EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA : R/W; bitpos: [1]; default: 0; - * The bits are used to enable the second section for autoload operation. - */ - -#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA (BIT(1)) -#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA_M (EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA_V << EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA_S) -#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA_V 0x00000001 -#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA_S 1 - -/* EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA : R/W; bitpos: [0]; default: 0; - * The bits are used to enable the first section for autoload operation. - */ - -#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA (BIT(0)) -#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA_M (EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA_V << EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA_S) -#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA_V 0x00000001 -#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA_S 0 - -/* EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_REG register - * ******* Description *********** - */ - -#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_REG (DR_REG_EXTMEM_BASE + 0x50) - -/* EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0; - * The bits are used to configure the start virtual address of the first - * section for autoload operation. It should be combined with - * dcache_autoload_sct0_ena. - */ - -#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR 0xffffffff -#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_M (EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_V << EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_S) -#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_V 0xffffffff -#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_S 0 - -/* EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_REG register - * ******* Description *********** - */ - -#define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_REG (DR_REG_EXTMEM_BASE + 0x54) - -/* EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE : R/W; bitpos: [26:0]; default: 0; - * The bits are used to configure the length of the first section for - * autoload operation. It should be combined with dcache_autoload_sct0_ena. - */ - -#define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE 0x07ffffff -#define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_M (EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_V << EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_S) -#define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_V 0x07ffffff -#define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_S 0 - -/* EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_REG register - * ******* Description *********** - */ - -#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_REG (DR_REG_EXTMEM_BASE + 0x58) - -/* EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0; - * The bits are used to configure the start virtual address of the second - * section for autoload operation. It should be combined with - * dcache_autoload_sct1_ena. - */ - -#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR 0xffffffff -#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_M (EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_V << EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_S) -#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_V 0xffffffff -#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_S 0 - -/* EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_REG register - * ******* Description *********** - */ - -#define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_REG (DR_REG_EXTMEM_BASE + 0x5c) - -/* EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE : R/W; bitpos: [26:0]; default: 0; - * The bits are used to configure the length of the second section for - * autoload operation. It should be combined with dcache_autoload_sct1_ena. - */ - -#define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE 0x07ffffff -#define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_M (EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_V << EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_S) -#define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_V 0x07ffffff -#define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_S 0 - -/* EXTMEM_ICACHE_CTRL_REG register - * ******* Description *********** - */ - -#define EXTMEM_ICACHE_CTRL_REG (DR_REG_EXTMEM_BASE + 0x60) - -/* EXTMEM_ICACHE_BLOCKSIZE_MODE : R/W; bitpos: [3]; default: 0; - * The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes - */ - -#define EXTMEM_ICACHE_BLOCKSIZE_MODE (BIT(3)) -#define EXTMEM_ICACHE_BLOCKSIZE_MODE_M (EXTMEM_ICACHE_BLOCKSIZE_MODE_V << EXTMEM_ICACHE_BLOCKSIZE_MODE_S) -#define EXTMEM_ICACHE_BLOCKSIZE_MODE_V 0x00000001 -#define EXTMEM_ICACHE_BLOCKSIZE_MODE_S 3 - -/* EXTMEM_ICACHE_SIZE_MODE : R/W; bitpos: [2]; default: 0; - * The bit is used to configure cache memory size.0: 16KB, 1: 32KB - */ - -#define EXTMEM_ICACHE_SIZE_MODE (BIT(2)) -#define EXTMEM_ICACHE_SIZE_MODE_M (EXTMEM_ICACHE_SIZE_MODE_V << EXTMEM_ICACHE_SIZE_MODE_S) -#define EXTMEM_ICACHE_SIZE_MODE_V 0x00000001 -#define EXTMEM_ICACHE_SIZE_MODE_S 2 - -/* EXTMEM_ICACHE_WAY_MODE : R/W; bitpos: [1]; default: 0; - * The bit is used to configure cache way mode.0: 4-way, 1: 8-way - */ - -#define EXTMEM_ICACHE_WAY_MODE (BIT(1)) -#define EXTMEM_ICACHE_WAY_MODE_M (EXTMEM_ICACHE_WAY_MODE_V << EXTMEM_ICACHE_WAY_MODE_S) -#define EXTMEM_ICACHE_WAY_MODE_V 0x00000001 -#define EXTMEM_ICACHE_WAY_MODE_S 1 - -/* EXTMEM_ICACHE_ENABLE : R/W; bitpos: [0]; default: 0; - * The bit is used to activate the data cache. 0: disable, 1: enable - */ - -#define EXTMEM_ICACHE_ENABLE (BIT(0)) -#define EXTMEM_ICACHE_ENABLE_M (EXTMEM_ICACHE_ENABLE_V << EXTMEM_ICACHE_ENABLE_S) -#define EXTMEM_ICACHE_ENABLE_V 0x00000001 -#define EXTMEM_ICACHE_ENABLE_S 0 - -/* EXTMEM_ICACHE_CTRL1_REG register - * ******* Description *********** - */ - -#define EXTMEM_ICACHE_CTRL1_REG (DR_REG_EXTMEM_BASE + 0x64) - -/* EXTMEM_ICACHE_SHUT_CORE1_BUS : R/W; bitpos: [1]; default: 1; - * The bit is used to disable core1 ibus, 0: enable, 1: disable - */ - -#define EXTMEM_ICACHE_SHUT_CORE1_BUS (BIT(1)) -#define EXTMEM_ICACHE_SHUT_CORE1_BUS_M (EXTMEM_ICACHE_SHUT_CORE1_BUS_V << EXTMEM_ICACHE_SHUT_CORE1_BUS_S) -#define EXTMEM_ICACHE_SHUT_CORE1_BUS_V 0x00000001 -#define EXTMEM_ICACHE_SHUT_CORE1_BUS_S 1 - -/* EXTMEM_ICACHE_SHUT_CORE0_BUS : R/W; bitpos: [0]; default: 1; - * The bit is used to disable core0 ibus, 0: enable, 1: disable - */ - -#define EXTMEM_ICACHE_SHUT_CORE0_BUS (BIT(0)) -#define EXTMEM_ICACHE_SHUT_CORE0_BUS_M (EXTMEM_ICACHE_SHUT_CORE0_BUS_V << EXTMEM_ICACHE_SHUT_CORE0_BUS_S) -#define EXTMEM_ICACHE_SHUT_CORE0_BUS_V 0x00000001 -#define EXTMEM_ICACHE_SHUT_CORE0_BUS_S 0 - -/* EXTMEM_ICACHE_TAG_POWER_CTRL_REG register - * ******* Description *********** - */ - -#define EXTMEM_ICACHE_TAG_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x68) - -/* EXTMEM_ICACHE_TAG_MEM_FORCE_PU : R/W; bitpos: [2]; default: 1; - * The bit is used to power icache tag memory up, 0: follow rtc_lslp, 1: - * power up - */ - -#define EXTMEM_ICACHE_TAG_MEM_FORCE_PU (BIT(2)) -#define EXTMEM_ICACHE_TAG_MEM_FORCE_PU_M (EXTMEM_ICACHE_TAG_MEM_FORCE_PU_V << EXTMEM_ICACHE_TAG_MEM_FORCE_PU_S) -#define EXTMEM_ICACHE_TAG_MEM_FORCE_PU_V 0x00000001 -#define EXTMEM_ICACHE_TAG_MEM_FORCE_PU_S 2 - -/* EXTMEM_ICACHE_TAG_MEM_FORCE_PD : R/W; bitpos: [1]; default: 0; - * The bit is used to power icache tag memory down, 0: follow rtc_lslp, 1: - * power down - */ - -#define EXTMEM_ICACHE_TAG_MEM_FORCE_PD (BIT(1)) -#define EXTMEM_ICACHE_TAG_MEM_FORCE_PD_M (EXTMEM_ICACHE_TAG_MEM_FORCE_PD_V << EXTMEM_ICACHE_TAG_MEM_FORCE_PD_S) -#define EXTMEM_ICACHE_TAG_MEM_FORCE_PD_V 0x00000001 -#define EXTMEM_ICACHE_TAG_MEM_FORCE_PD_S 1 - -/* EXTMEM_ICACHE_TAG_MEM_FORCE_ON : R/W; bitpos: [0]; default: 1; - * The bit is used to close clock gating of icache tag memory. 1: close - * gating, 0: open clock gating. - */ - -#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON (BIT(0)) -#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_M (EXTMEM_ICACHE_TAG_MEM_FORCE_ON_V << EXTMEM_ICACHE_TAG_MEM_FORCE_ON_S) -#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_V 0x00000001 -#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_S 0 - -/* EXTMEM_ICACHE_PRELOCK_CTRL_REG register - * ******* Description *********** - */ - -#define EXTMEM_ICACHE_PRELOCK_CTRL_REG (DR_REG_EXTMEM_BASE + 0x6c) - -/* EXTMEM_ICACHE_PRELOCK_SCT1_EN : R/W; bitpos: [1]; default: 0; - * The bit is used to enable the second section of prelock function. - */ - -#define EXTMEM_ICACHE_PRELOCK_SCT1_EN (BIT(1)) -#define EXTMEM_ICACHE_PRELOCK_SCT1_EN_M (EXTMEM_ICACHE_PRELOCK_SCT1_EN_V << EXTMEM_ICACHE_PRELOCK_SCT1_EN_S) -#define EXTMEM_ICACHE_PRELOCK_SCT1_EN_V 0x00000001 -#define EXTMEM_ICACHE_PRELOCK_SCT1_EN_S 1 - -/* EXTMEM_ICACHE_PRELOCK_SCT0_EN : R/W; bitpos: [0]; default: 0; - * The bit is used to enable the first section of prelock function. - */ - -#define EXTMEM_ICACHE_PRELOCK_SCT0_EN (BIT(0)) -#define EXTMEM_ICACHE_PRELOCK_SCT0_EN_M (EXTMEM_ICACHE_PRELOCK_SCT0_EN_V << EXTMEM_ICACHE_PRELOCK_SCT0_EN_S) -#define EXTMEM_ICACHE_PRELOCK_SCT0_EN_V 0x00000001 -#define EXTMEM_ICACHE_PRELOCK_SCT0_EN_S 0 - -/* EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_REG register - * ******* Description *********** - */ - -#define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_REG (DR_REG_EXTMEM_BASE + 0x70) - -/* EXTMEM_ICACHE_PRELOCK_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0; - * The bits are used to configure the first start virtual address of data - * prelock, which is combined with ICACHE_PRELOCK_SCT0_SIZE_REG - */ - -#define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR 0xffffffff -#define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_M (EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_V << EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_S) -#define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_V 0xffffffff -#define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_S 0 - -/* EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_REG register - * ******* Description *********** - */ - -#define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_REG (DR_REG_EXTMEM_BASE + 0x74) - -/* EXTMEM_ICACHE_PRELOCK_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0; - * The bits are used to configure the second start virtual address of data - * prelock, which is combined with ICACHE_PRELOCK_SCT1_SIZE_REG - */ - -#define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR 0xffffffff -#define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_M (EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_V << EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_S) -#define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_V 0xffffffff -#define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_S 0 - -/* EXTMEM_ICACHE_PRELOCK_SCT_SIZE_REG register - * ******* Description *********** - */ - -#define EXTMEM_ICACHE_PRELOCK_SCT_SIZE_REG (DR_REG_EXTMEM_BASE + 0x78) - -/* EXTMEM_ICACHE_PRELOCK_SCT0_SIZE : R/W; bitpos: [31:16]; default: 0; - * The bits are used to configure the first length of data locking, which is - * combined with ICACHE_PRELOCK_SCT0_ADDR_REG - */ - -#define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE 0x0000ffff -#define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_M (EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_V << EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_S) -#define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_V 0x0000ffff -#define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_S 16 - -/* EXTMEM_ICACHE_PRELOCK_SCT1_SIZE : R/W; bitpos: [15:0]; default: 0; - * The bits are used to configure the second length of data locking, which - * is combined with ICACHE_PRELOCK_SCT1_ADDR_REG - */ - -#define EXTMEM_ICACHE_PRELOCK_SCT1_SIZE 0x0000ffff -#define EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_M (EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_V << EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_S) -#define EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_V 0x0000ffff -#define EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_S 0 - -/* EXTMEM_ICACHE_LOCK_CTRL_REG register - * ******* Description *********** - */ - -#define EXTMEM_ICACHE_LOCK_CTRL_REG (DR_REG_EXTMEM_BASE + 0x7c) - -/* EXTMEM_ICACHE_LOCK_DONE : RO; bitpos: [2]; default: 1; - * The bit is used to indicate unlock/lock operation is finished. - */ - -#define EXTMEM_ICACHE_LOCK_DONE (BIT(2)) -#define EXTMEM_ICACHE_LOCK_DONE_M (EXTMEM_ICACHE_LOCK_DONE_V << EXTMEM_ICACHE_LOCK_DONE_S) -#define EXTMEM_ICACHE_LOCK_DONE_V 0x00000001 -#define EXTMEM_ICACHE_LOCK_DONE_S 2 - -/* EXTMEM_ICACHE_UNLOCK_ENA : R/W; bitpos: [1]; default: 0; - * The bit is used to enable unlock operation. It will be cleared by - * hardware after unlock operation done. - */ - -#define EXTMEM_ICACHE_UNLOCK_ENA (BIT(1)) -#define EXTMEM_ICACHE_UNLOCK_ENA_M (EXTMEM_ICACHE_UNLOCK_ENA_V << EXTMEM_ICACHE_UNLOCK_ENA_S) -#define EXTMEM_ICACHE_UNLOCK_ENA_V 0x00000001 -#define EXTMEM_ICACHE_UNLOCK_ENA_S 1 - -/* EXTMEM_ICACHE_LOCK_ENA : R/W; bitpos: [0]; default: 0; - * The bit is used to enable lock operation. It will be cleared by hardware - * after lock operation done. - */ - -#define EXTMEM_ICACHE_LOCK_ENA (BIT(0)) -#define EXTMEM_ICACHE_LOCK_ENA_M (EXTMEM_ICACHE_LOCK_ENA_V << EXTMEM_ICACHE_LOCK_ENA_S) -#define EXTMEM_ICACHE_LOCK_ENA_V 0x00000001 -#define EXTMEM_ICACHE_LOCK_ENA_S 0 - -/* EXTMEM_ICACHE_LOCK_ADDR_REG register - * ******* Description *********** - */ - -#define EXTMEM_ICACHE_LOCK_ADDR_REG (DR_REG_EXTMEM_BASE + 0x80) - -/* EXTMEM_ICACHE_LOCK_ADDR : R/W; bitpos: [31:0]; default: 0; - * The bits are used to configure the start virtual address for lock - * operations. It should be combined with ICACHE_LOCK_SIZE_REG. - */ - -#define EXTMEM_ICACHE_LOCK_ADDR 0xffffffff -#define EXTMEM_ICACHE_LOCK_ADDR_M (EXTMEM_ICACHE_LOCK_ADDR_V << EXTMEM_ICACHE_LOCK_ADDR_S) -#define EXTMEM_ICACHE_LOCK_ADDR_V 0xffffffff -#define EXTMEM_ICACHE_LOCK_ADDR_S 0 - -/* EXTMEM_ICACHE_LOCK_SIZE_REG register - * ******* Description *********** - */ - -#define EXTMEM_ICACHE_LOCK_SIZE_REG (DR_REG_EXTMEM_BASE + 0x84) - -/* EXTMEM_ICACHE_LOCK_SIZE : R/W; bitpos: [15:0]; default: 0; - * The bits are used to configure the length for lock operations. The bits - * are the counts of cache block. It should be combined with - * ICACHE_LOCK_ADDR_REG. - */ - -#define EXTMEM_ICACHE_LOCK_SIZE 0x0000ffff -#define EXTMEM_ICACHE_LOCK_SIZE_M (EXTMEM_ICACHE_LOCK_SIZE_V << EXTMEM_ICACHE_LOCK_SIZE_S) -#define EXTMEM_ICACHE_LOCK_SIZE_V 0x0000ffff -#define EXTMEM_ICACHE_LOCK_SIZE_S 0 - -/* EXTMEM_ICACHE_SYNC_CTRL_REG register - * ******* Description *********** - */ - -#define EXTMEM_ICACHE_SYNC_CTRL_REG (DR_REG_EXTMEM_BASE + 0x88) - -/* EXTMEM_ICACHE_SYNC_DONE : RO; bitpos: [1]; default: 0; - * The bit is used to indicate invalidate operation is finished. - */ - -#define EXTMEM_ICACHE_SYNC_DONE (BIT(1)) -#define EXTMEM_ICACHE_SYNC_DONE_M (EXTMEM_ICACHE_SYNC_DONE_V << EXTMEM_ICACHE_SYNC_DONE_S) -#define EXTMEM_ICACHE_SYNC_DONE_V 0x00000001 -#define EXTMEM_ICACHE_SYNC_DONE_S 1 - -/* EXTMEM_ICACHE_INVALIDATE_ENA : R/W; bitpos: [0]; default: 1; - * The bit is used to enable invalidate operation. It will be cleared by - * hardware after invalidate operation done. - */ - -#define EXTMEM_ICACHE_INVALIDATE_ENA (BIT(0)) -#define EXTMEM_ICACHE_INVALIDATE_ENA_M (EXTMEM_ICACHE_INVALIDATE_ENA_V << EXTMEM_ICACHE_INVALIDATE_ENA_S) -#define EXTMEM_ICACHE_INVALIDATE_ENA_V 0x00000001 -#define EXTMEM_ICACHE_INVALIDATE_ENA_S 0 - -/* EXTMEM_ICACHE_SYNC_ADDR_REG register - * ******* Description *********** - */ - -#define EXTMEM_ICACHE_SYNC_ADDR_REG (DR_REG_EXTMEM_BASE + 0x8c) - -/* EXTMEM_ICACHE_SYNC_ADDR : R/W; bitpos: [31:0]; default: 0; - * The bits are used to configure the start virtual address for clean - * operations. It should be combined with ICACHE_SYNC_SIZE_REG. - */ - -#define EXTMEM_ICACHE_SYNC_ADDR 0xffffffff -#define EXTMEM_ICACHE_SYNC_ADDR_M (EXTMEM_ICACHE_SYNC_ADDR_V << EXTMEM_ICACHE_SYNC_ADDR_S) -#define EXTMEM_ICACHE_SYNC_ADDR_V 0xffffffff -#define EXTMEM_ICACHE_SYNC_ADDR_S 0 - -/* EXTMEM_ICACHE_SYNC_SIZE_REG register - * ******* Description *********** - */ - -#define EXTMEM_ICACHE_SYNC_SIZE_REG (DR_REG_EXTMEM_BASE + 0x90) - -/* EXTMEM_ICACHE_SYNC_SIZE : R/W; bitpos: [22:0]; default: 0; - * The bits are used to configure the length for sync operations. The bits - * are the counts of cache block. It should be combined with - * ICACHE_SYNC_ADDR_REG. - */ - -#define EXTMEM_ICACHE_SYNC_SIZE 0x007fffff -#define EXTMEM_ICACHE_SYNC_SIZE_M (EXTMEM_ICACHE_SYNC_SIZE_V << EXTMEM_ICACHE_SYNC_SIZE_S) -#define EXTMEM_ICACHE_SYNC_SIZE_V 0x007fffff -#define EXTMEM_ICACHE_SYNC_SIZE_S 0 - -/* EXTMEM_ICACHE_PRELOAD_CTRL_REG register - * ******* Description *********** - */ - -#define EXTMEM_ICACHE_PRELOAD_CTRL_REG (DR_REG_EXTMEM_BASE + 0x94) - -/* EXTMEM_ICACHE_PRELOAD_ORDER : R/W; bitpos: [2]; default: 0; - * The bit is used to configure the direction of preload operation. 1: - * descending, 0: ascending. - */ - -#define EXTMEM_ICACHE_PRELOAD_ORDER (BIT(2)) -#define EXTMEM_ICACHE_PRELOAD_ORDER_M (EXTMEM_ICACHE_PRELOAD_ORDER_V << EXTMEM_ICACHE_PRELOAD_ORDER_S) -#define EXTMEM_ICACHE_PRELOAD_ORDER_V 0x00000001 -#define EXTMEM_ICACHE_PRELOAD_ORDER_S 2 - -/* EXTMEM_ICACHE_PRELOAD_DONE : RO; bitpos: [1]; default: 1; - * The bit is used to indicate preload operation is finished. - */ - -#define EXTMEM_ICACHE_PRELOAD_DONE (BIT(1)) -#define EXTMEM_ICACHE_PRELOAD_DONE_M (EXTMEM_ICACHE_PRELOAD_DONE_V << EXTMEM_ICACHE_PRELOAD_DONE_S) -#define EXTMEM_ICACHE_PRELOAD_DONE_V 0x00000001 -#define EXTMEM_ICACHE_PRELOAD_DONE_S 1 - -/* EXTMEM_ICACHE_PRELOAD_ENA : R/W; bitpos: [0]; default: 0; - * The bit is used to enable preload operation. It will be cleared by - * hardware after preload operation done. - */ - -#define EXTMEM_ICACHE_PRELOAD_ENA (BIT(0)) -#define EXTMEM_ICACHE_PRELOAD_ENA_M (EXTMEM_ICACHE_PRELOAD_ENA_V << EXTMEM_ICACHE_PRELOAD_ENA_S) -#define EXTMEM_ICACHE_PRELOAD_ENA_V 0x00000001 -#define EXTMEM_ICACHE_PRELOAD_ENA_S 0 - -/* EXTMEM_ICACHE_PRELOAD_ADDR_REG register - * ******* Description *********** - */ - -#define EXTMEM_ICACHE_PRELOAD_ADDR_REG (DR_REG_EXTMEM_BASE + 0x98) - -/* EXTMEM_ICACHE_PRELOAD_ADDR : R/W; bitpos: [31:0]; default: 0; - * The bits are used to configure the start virtual address for preload - * operation. It should be combined with ICACHE_PRELOAD_SIZE_REG. - */ - -#define EXTMEM_ICACHE_PRELOAD_ADDR 0xffffffff -#define EXTMEM_ICACHE_PRELOAD_ADDR_M (EXTMEM_ICACHE_PRELOAD_ADDR_V << EXTMEM_ICACHE_PRELOAD_ADDR_S) -#define EXTMEM_ICACHE_PRELOAD_ADDR_V 0xffffffff -#define EXTMEM_ICACHE_PRELOAD_ADDR_S 0 - -/* EXTMEM_ICACHE_PRELOAD_SIZE_REG register - * ******* Description *********** - */ - -#define EXTMEM_ICACHE_PRELOAD_SIZE_REG (DR_REG_EXTMEM_BASE + 0x9c) - -/* EXTMEM_ICACHE_PRELOAD_SIZE : R/W; bitpos: [15:0]; default: 0; - * The bits are used to configure the length for preload operation. The bits - * are the counts of cache block. It should be combined with - * ICACHE_PRELOAD_ADDR_REG.. - */ - -#define EXTMEM_ICACHE_PRELOAD_SIZE 0x0000ffff -#define EXTMEM_ICACHE_PRELOAD_SIZE_M (EXTMEM_ICACHE_PRELOAD_SIZE_V << EXTMEM_ICACHE_PRELOAD_SIZE_S) -#define EXTMEM_ICACHE_PRELOAD_SIZE_V 0x0000ffff -#define EXTMEM_ICACHE_PRELOAD_SIZE_S 0 - -/* EXTMEM_ICACHE_AUTOLOAD_CTRL_REG register - * ******* Description *********** - */ - -#define EXTMEM_ICACHE_AUTOLOAD_CTRL_REG (DR_REG_EXTMEM_BASE + 0xa0) - -/* EXTMEM_ICACHE_AUTOLOAD_BUFFER_CLEAR : R/W; bitpos: [9]; default: 0; - * The bit is used to clear autoload buffer in icache. - */ - -#define EXTMEM_ICACHE_AUTOLOAD_BUFFER_CLEAR (BIT(9)) -#define EXTMEM_ICACHE_AUTOLOAD_BUFFER_CLEAR_M (EXTMEM_ICACHE_AUTOLOAD_BUFFER_CLEAR_V << EXTMEM_ICACHE_AUTOLOAD_BUFFER_CLEAR_S) -#define EXTMEM_ICACHE_AUTOLOAD_BUFFER_CLEAR_V 0x00000001 -#define EXTMEM_ICACHE_AUTOLOAD_BUFFER_CLEAR_S 9 - -/* EXTMEM_ICACHE_AUTOLOAD_SIZE : R/W; bitpos: [8:7]; default: 0; - * The bits are used to configure the numbers of the cache block for the - * issuing autoload operation. - */ - -#define EXTMEM_ICACHE_AUTOLOAD_SIZE 0x00000003 -#define EXTMEM_ICACHE_AUTOLOAD_SIZE_M (EXTMEM_ICACHE_AUTOLOAD_SIZE_V << EXTMEM_ICACHE_AUTOLOAD_SIZE_S) -#define EXTMEM_ICACHE_AUTOLOAD_SIZE_V 0x00000003 -#define EXTMEM_ICACHE_AUTOLOAD_SIZE_S 7 - -/* EXTMEM_ICACHE_AUTOLOAD_RQST : R/W; bitpos: [6:5]; default: 0; - * The bits are used to configure trigger conditions for autoload. 0/3: - * cache miss, 1: cache hit, 2: both cache miss and hit. - */ - -#define EXTMEM_ICACHE_AUTOLOAD_RQST 0x00000003 -#define EXTMEM_ICACHE_AUTOLOAD_RQST_M (EXTMEM_ICACHE_AUTOLOAD_RQST_V << EXTMEM_ICACHE_AUTOLOAD_RQST_S) -#define EXTMEM_ICACHE_AUTOLOAD_RQST_V 0x00000003 -#define EXTMEM_ICACHE_AUTOLOAD_RQST_S 5 - -/* EXTMEM_ICACHE_AUTOLOAD_ORDER : R/W; bitpos: [4]; default: 0; - * The bits are used to configure the direction of autoload. 1: descending, - * 0: ascending. - */ - -#define EXTMEM_ICACHE_AUTOLOAD_ORDER (BIT(4)) -#define EXTMEM_ICACHE_AUTOLOAD_ORDER_M (EXTMEM_ICACHE_AUTOLOAD_ORDER_V << EXTMEM_ICACHE_AUTOLOAD_ORDER_S) -#define EXTMEM_ICACHE_AUTOLOAD_ORDER_V 0x00000001 -#define EXTMEM_ICACHE_AUTOLOAD_ORDER_S 4 - -/* EXTMEM_ICACHE_AUTOLOAD_DONE : RO; bitpos: [3]; default: 1; - * The bit is used to indicate autoload operation is finished. - */ - -#define EXTMEM_ICACHE_AUTOLOAD_DONE (BIT(3)) -#define EXTMEM_ICACHE_AUTOLOAD_DONE_M (EXTMEM_ICACHE_AUTOLOAD_DONE_V << EXTMEM_ICACHE_AUTOLOAD_DONE_S) -#define EXTMEM_ICACHE_AUTOLOAD_DONE_V 0x00000001 -#define EXTMEM_ICACHE_AUTOLOAD_DONE_S 3 - -/* EXTMEM_ICACHE_AUTOLOAD_ENA : R/W; bitpos: [2]; default: 0; - * The bit is used to enable and disable autoload operation. It is combined - * with icache_autoload_done. 1: enable, 0: disable. - */ - -#define EXTMEM_ICACHE_AUTOLOAD_ENA (BIT(2)) -#define EXTMEM_ICACHE_AUTOLOAD_ENA_M (EXTMEM_ICACHE_AUTOLOAD_ENA_V << EXTMEM_ICACHE_AUTOLOAD_ENA_S) -#define EXTMEM_ICACHE_AUTOLOAD_ENA_V 0x00000001 -#define EXTMEM_ICACHE_AUTOLOAD_ENA_S 2 - -/* EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA : R/W; bitpos: [1]; default: 0; - * The bits are used to enable the second section for autoload operation. - */ - -#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA (BIT(1)) -#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA_M (EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA_V << EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA_S) -#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA_V 0x00000001 -#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA_S 1 - -/* EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA : R/W; bitpos: [0]; default: 0; - * The bits are used to enable the first section for autoload operation. - */ - -#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA (BIT(0)) -#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA_M (EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA_V << EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA_S) -#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA_V 0x00000001 -#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA_S 0 - -/* EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_REG register - * ******* Description *********** - */ - -#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_REG (DR_REG_EXTMEM_BASE + 0xa4) - -/* EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0; - * The bits are used to configure the start virtual address of the first - * section for autoload operation. It should be combined with - * icache_autoload_sct0_ena. - */ - -#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR 0xffffffff -#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_M (EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_V << EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_S) -#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_V 0xffffffff -#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_S 0 - -/* EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_REG register - * ******* Description *********** - */ - -#define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_REG (DR_REG_EXTMEM_BASE + 0xa8) - -/* EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE : R/W; bitpos: [26:0]; default: 0; - * The bits are used to configure the length of the first section for - * autoload operation. It should be combined with icache_autoload_sct0_ena. - */ - -#define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE 0x07ffffff -#define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_M (EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_V << EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_S) -#define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_V 0x07ffffff -#define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_S 0 - -/* EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_REG register - * ******* Description *********** - */ - -#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_REG (DR_REG_EXTMEM_BASE + 0xac) - -/* EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0; - * The bits are used to configure the start virtual address of the second - * section for autoload operation. It should be combined with - * icache_autoload_sct1_ena. - */ - -#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR 0xffffffff -#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_M (EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_V << EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_S) -#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_V 0xffffffff -#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_S 0 - -/* EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_REG register - * ******* Description *********** - */ - -#define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_REG (DR_REG_EXTMEM_BASE + 0xb0) - -/* EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE : R/W; bitpos: [26:0]; default: 0; - * The bits are used to configure the length of the second section for - * autoload operation. It should be combined with icache_autoload_sct1_ena. - */ - -#define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE 0x07ffffff -#define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_M (EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_V << EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_S) -#define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_V 0x07ffffff -#define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_S 0 - -/* EXTMEM_IBUS_TO_FLASH_START_VADDR_REG register - * ******* Description *********** - */ - -#define EXTMEM_IBUS_TO_FLASH_START_VADDR_REG (DR_REG_EXTMEM_BASE + 0xb4) - -/* EXTMEM_IBUS_TO_FLASH_START_VADDR : R/W; bitpos: [31:0]; default: - * 1140850688; - * The bits are used to configure the start virtual address of ibus to - * access flash. The register is used to give constraints to ibus access - * counter. - */ - -#define EXTMEM_IBUS_TO_FLASH_START_VADDR 0xffffffff -#define EXTMEM_IBUS_TO_FLASH_START_VADDR_M (EXTMEM_IBUS_TO_FLASH_START_VADDR_V << EXTMEM_IBUS_TO_FLASH_START_VADDR_S) -#define EXTMEM_IBUS_TO_FLASH_START_VADDR_V 0xffffffff -#define EXTMEM_IBUS_TO_FLASH_START_VADDR_S 0 - -/* EXTMEM_IBUS_TO_FLASH_END_VADDR_REG register - * ******* Description *********** - */ - -#define EXTMEM_IBUS_TO_FLASH_END_VADDR_REG (DR_REG_EXTMEM_BASE + 0xb8) - -/* EXTMEM_IBUS_TO_FLASH_END_VADDR : R/W; bitpos: [31:0]; default: 1207959551; - * The bits are used to configure the end virtual address of ibus to access - * flash. The register is used to give constraints to ibus access counter. - */ - -#define EXTMEM_IBUS_TO_FLASH_END_VADDR 0xffffffff -#define EXTMEM_IBUS_TO_FLASH_END_VADDR_M (EXTMEM_IBUS_TO_FLASH_END_VADDR_V << EXTMEM_IBUS_TO_FLASH_END_VADDR_S) -#define EXTMEM_IBUS_TO_FLASH_END_VADDR_V 0xffffffff -#define EXTMEM_IBUS_TO_FLASH_END_VADDR_S 0 - -/* EXTMEM_DBUS_TO_FLASH_START_VADDR_REG register - * ******* Description *********** - */ - -#define EXTMEM_DBUS_TO_FLASH_START_VADDR_REG (DR_REG_EXTMEM_BASE + 0xbc) - -/* EXTMEM_DBUS_TO_FLASH_START_VADDR : R/W; bitpos: [31:0]; default: 0; - * The bits are used to configure the start virtual address of dbus to - * access flash. The register is used to give constraints to dbus access - * counter. - */ - -#define EXTMEM_DBUS_TO_FLASH_START_VADDR 0xffffffff -#define EXTMEM_DBUS_TO_FLASH_START_VADDR_M (EXTMEM_DBUS_TO_FLASH_START_VADDR_V << EXTMEM_DBUS_TO_FLASH_START_VADDR_S) -#define EXTMEM_DBUS_TO_FLASH_START_VADDR_V 0xffffffff -#define EXTMEM_DBUS_TO_FLASH_START_VADDR_S 0 - -/* EXTMEM_DBUS_TO_FLASH_END_VADDR_REG register - * ******* Description *********** - */ - -#define EXTMEM_DBUS_TO_FLASH_END_VADDR_REG (DR_REG_EXTMEM_BASE + 0xc0) - -/* EXTMEM_DBUS_TO_FLASH_END_VADDR : R/W; bitpos: [31:0]; default: 0; - * The bits are used to configure the end virtual address of dbus to access - * flash. The register is used to give constraints to dbus access counter. - */ - -#define EXTMEM_DBUS_TO_FLASH_END_VADDR 0xffffffff -#define EXTMEM_DBUS_TO_FLASH_END_VADDR_M (EXTMEM_DBUS_TO_FLASH_END_VADDR_V << EXTMEM_DBUS_TO_FLASH_END_VADDR_S) -#define EXTMEM_DBUS_TO_FLASH_END_VADDR_V 0xffffffff -#define EXTMEM_DBUS_TO_FLASH_END_VADDR_S 0 - -/* EXTMEM_CACHE_ACS_CNT_CLR_REG register - * ******* Description *********** - */ - -#define EXTMEM_CACHE_ACS_CNT_CLR_REG (DR_REG_EXTMEM_BASE + 0xc4) - -/* EXTMEM_ICACHE_ACS_CNT_CLR : WOD; bitpos: [1]; default: 0; - * The bit is used to clear icache counter. - */ - -#define EXTMEM_ICACHE_ACS_CNT_CLR (BIT(1)) -#define EXTMEM_ICACHE_ACS_CNT_CLR_M (EXTMEM_ICACHE_ACS_CNT_CLR_V << EXTMEM_ICACHE_ACS_CNT_CLR_S) -#define EXTMEM_ICACHE_ACS_CNT_CLR_V 0x00000001 -#define EXTMEM_ICACHE_ACS_CNT_CLR_S 1 - -/* EXTMEM_DCACHE_ACS_CNT_CLR : WOD; bitpos: [0]; default: 0; - * The bit is used to clear dcache counter. - */ - -#define EXTMEM_DCACHE_ACS_CNT_CLR (BIT(0)) -#define EXTMEM_DCACHE_ACS_CNT_CLR_M (EXTMEM_DCACHE_ACS_CNT_CLR_V << EXTMEM_DCACHE_ACS_CNT_CLR_S) -#define EXTMEM_DCACHE_ACS_CNT_CLR_V 0x00000001 -#define EXTMEM_DCACHE_ACS_CNT_CLR_S 0 - -/* EXTMEM_IBUS_ACS_MISS_CNT_REG register - * ******* Description *********** - */ - -#define EXTMEM_IBUS_ACS_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0xc8) - -/* EXTMEM_IBUS_ACS_MISS_CNT : RO; bitpos: [31:0]; default: 0; - * The bits are used to count the number of the cache miss caused by ibus - * access flash/spiram. - */ - -#define EXTMEM_IBUS_ACS_MISS_CNT 0xffffffff -#define EXTMEM_IBUS_ACS_MISS_CNT_M (EXTMEM_IBUS_ACS_MISS_CNT_V << EXTMEM_IBUS_ACS_MISS_CNT_S) -#define EXTMEM_IBUS_ACS_MISS_CNT_V 0xffffffff -#define EXTMEM_IBUS_ACS_MISS_CNT_S 0 - -/* EXTMEM_IBUS_ACS_CNT_REG register - * ******* Description *********** - */ - -#define EXTMEM_IBUS_ACS_CNT_REG (DR_REG_EXTMEM_BASE + 0xcc) - -/* EXTMEM_IBUS_ACS_CNT : RO; bitpos: [31:0]; default: 0; - * The bits are used to count the number of ibus access flash/spiram through - * icache. - */ - -#define EXTMEM_IBUS_ACS_CNT 0xffffffff -#define EXTMEM_IBUS_ACS_CNT_M (EXTMEM_IBUS_ACS_CNT_V << EXTMEM_IBUS_ACS_CNT_S) -#define EXTMEM_IBUS_ACS_CNT_V 0xffffffff -#define EXTMEM_IBUS_ACS_CNT_S 0 - -/* EXTMEM_DBUS_ACS_FLASH_MISS_CNT_REG register - * ******* Description *********** - */ - -#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0xd0) - -/* EXTMEM_DBUS_ACS_FLASH_MISS_CNT : RO; bitpos: [31:0]; default: 0; - * The bits are used to count the number of the cache miss caused by dbus - * access flash. - */ - -#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT 0xffffffff -#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_M (EXTMEM_DBUS_ACS_FLASH_MISS_CNT_V << EXTMEM_DBUS_ACS_FLASH_MISS_CNT_S) -#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_V 0xffffffff -#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_S 0 - -/* EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_REG register - * ******* Description *********** - */ - -#define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0xd4) - -/* EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT : RO; bitpos: [31:0]; default: 0; - * The bits are used to count the number of the cache miss caused by dbus - * access spiram. - */ - -#define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT 0xffffffff -#define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_M (EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_V << EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_S) -#define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_V 0xffffffff -#define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_S 0 - -/* EXTMEM_DBUS_ACS_CNT_REG register - * ******* Description *********** - */ - -#define EXTMEM_DBUS_ACS_CNT_REG (DR_REG_EXTMEM_BASE + 0xd8) - -/* EXTMEM_DBUS_ACS_CNT : RO; bitpos: [31:0]; default: 0; - * The bits are used to count the number of dbus access flash/spiram through - * dcache. - */ - -#define EXTMEM_DBUS_ACS_CNT 0xffffffff -#define EXTMEM_DBUS_ACS_CNT_M (EXTMEM_DBUS_ACS_CNT_V << EXTMEM_DBUS_ACS_CNT_S) -#define EXTMEM_DBUS_ACS_CNT_V 0xffffffff -#define EXTMEM_DBUS_ACS_CNT_S 0 - -/* EXTMEM_CACHE_ILG_INT_ENA_REG register - * ******* Description *********** - */ - -#define EXTMEM_CACHE_ILG_INT_ENA_REG (DR_REG_EXTMEM_BASE + 0xdc) - -/* EXTMEM_DBUS_CNT_OVF_INT_ENA : R/W; bitpos: [8]; default: 0; - * The bit is used to enable interrupt by dbus counter overflow. - */ - -#define EXTMEM_DBUS_CNT_OVF_INT_ENA (BIT(8)) -#define EXTMEM_DBUS_CNT_OVF_INT_ENA_M (EXTMEM_DBUS_CNT_OVF_INT_ENA_V << EXTMEM_DBUS_CNT_OVF_INT_ENA_S) -#define EXTMEM_DBUS_CNT_OVF_INT_ENA_V 0x00000001 -#define EXTMEM_DBUS_CNT_OVF_INT_ENA_S 8 - -/* EXTMEM_IBUS_CNT_OVF_INT_ENA : R/W; bitpos: [7]; default: 0; - * The bit is used to enable interrupt by ibus counter overflow. - */ - -#define EXTMEM_IBUS_CNT_OVF_INT_ENA (BIT(7)) -#define EXTMEM_IBUS_CNT_OVF_INT_ENA_M (EXTMEM_IBUS_CNT_OVF_INT_ENA_V << EXTMEM_IBUS_CNT_OVF_INT_ENA_S) -#define EXTMEM_IBUS_CNT_OVF_INT_ENA_V 0x00000001 -#define EXTMEM_IBUS_CNT_OVF_INT_ENA_S 7 - -/* EXTMEM_DCACHE_OCCUPY_EXC_INT_ENA : R/W; bitpos: [6]; default: 0; - * The bit is used to enable interrupt by dcache trying to replace a line - * whose blocks all have been occupied by occupy-mode. - */ - -#define EXTMEM_DCACHE_OCCUPY_EXC_INT_ENA (BIT(6)) -#define EXTMEM_DCACHE_OCCUPY_EXC_INT_ENA_M (EXTMEM_DCACHE_OCCUPY_EXC_INT_ENA_V << EXTMEM_DCACHE_OCCUPY_EXC_INT_ENA_S) -#define EXTMEM_DCACHE_OCCUPY_EXC_INT_ENA_V 0x00000001 -#define EXTMEM_DCACHE_OCCUPY_EXC_INT_ENA_S 6 - -/* EXTMEM_MMU_ENTRY_FAULT_INT_ENA : R/W; bitpos: [5]; default: 0; - * The bit is used to enable interrupt by mmu entry fault. - */ - -#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA (BIT(5)) -#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_M (EXTMEM_MMU_ENTRY_FAULT_INT_ENA_V << EXTMEM_MMU_ENTRY_FAULT_INT_ENA_S) -#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_V 0x00000001 -#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_S 5 - -/* EXTMEM_DCACHE_WRITE_FLASH_INT_ENA : R/W; bitpos: [4]; default: 0; - * The bit is used to enable interrupt by dcache trying to write flash. - */ - -#define EXTMEM_DCACHE_WRITE_FLASH_INT_ENA (BIT(4)) -#define EXTMEM_DCACHE_WRITE_FLASH_INT_ENA_M (EXTMEM_DCACHE_WRITE_FLASH_INT_ENA_V << EXTMEM_DCACHE_WRITE_FLASH_INT_ENA_S) -#define EXTMEM_DCACHE_WRITE_FLASH_INT_ENA_V 0x00000001 -#define EXTMEM_DCACHE_WRITE_FLASH_INT_ENA_S 4 - -/* EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_ENA : R/W; bitpos: [3]; default: 0; - * The bit is used to enable interrupt by preload configurations fault. - */ - -#define EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_ENA (BIT(3)) -#define EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_ENA_M (EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_ENA_V << EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_ENA_S) -#define EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_ENA_V 0x00000001 -#define EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_ENA_S 3 - -/* EXTMEM_DCACHE_SYNC_OP_FAULT_INT_ENA : R/W; bitpos: [2]; default: 0; - * The bit is used to enable interrupt by sync configurations fault. - */ - -#define EXTMEM_DCACHE_SYNC_OP_FAULT_INT_ENA (BIT(2)) -#define EXTMEM_DCACHE_SYNC_OP_FAULT_INT_ENA_M (EXTMEM_DCACHE_SYNC_OP_FAULT_INT_ENA_V << EXTMEM_DCACHE_SYNC_OP_FAULT_INT_ENA_S) -#define EXTMEM_DCACHE_SYNC_OP_FAULT_INT_ENA_V 0x00000001 -#define EXTMEM_DCACHE_SYNC_OP_FAULT_INT_ENA_S 2 - -/* EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA : R/W; bitpos: [1]; default: 0; - * The bit is used to enable interrupt by preload configurations fault. - */ - -#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA (BIT(1)) -#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_M (EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_V << EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_S) -#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_V 0x00000001 -#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_S 1 - -/* EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA : R/W; bitpos: [0]; default: 0; - * The bit is used to enable interrupt by sync configurations fault. - */ - -#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA (BIT(0)) -#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA_M (EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA_V << EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA_S) -#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA_V 0x00000001 -#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA_S 0 - -/* EXTMEM_CACHE_ILG_INT_CLR_REG register - * ******* Description *********** - */ - -#define EXTMEM_CACHE_ILG_INT_CLR_REG (DR_REG_EXTMEM_BASE + 0xe0) - -/* EXTMEM_DBUS_CNT_OVF_INT_CLR : WOD; bitpos: [8]; default: 0; - * The bit is used to clear interrupt by dbus counter overflow. - */ - -#define EXTMEM_DBUS_CNT_OVF_INT_CLR (BIT(8)) -#define EXTMEM_DBUS_CNT_OVF_INT_CLR_M (EXTMEM_DBUS_CNT_OVF_INT_CLR_V << EXTMEM_DBUS_CNT_OVF_INT_CLR_S) -#define EXTMEM_DBUS_CNT_OVF_INT_CLR_V 0x00000001 -#define EXTMEM_DBUS_CNT_OVF_INT_CLR_S 8 - -/* EXTMEM_IBUS_CNT_OVF_INT_CLR : WOD; bitpos: [7]; default: 0; - * The bit is used to clear interrupt by ibus counter overflow. - */ - -#define EXTMEM_IBUS_CNT_OVF_INT_CLR (BIT(7)) -#define EXTMEM_IBUS_CNT_OVF_INT_CLR_M (EXTMEM_IBUS_CNT_OVF_INT_CLR_V << EXTMEM_IBUS_CNT_OVF_INT_CLR_S) -#define EXTMEM_IBUS_CNT_OVF_INT_CLR_V 0x00000001 -#define EXTMEM_IBUS_CNT_OVF_INT_CLR_S 7 - -/* EXTMEM_DCACHE_OCCUPY_EXC_INT_CLR : WOD; bitpos: [6]; default: 0; - * The bit is used to clear interrupt by dcache trying to replace a line - * whose blocks all have been occupied by occupy-mode. - */ - -#define EXTMEM_DCACHE_OCCUPY_EXC_INT_CLR (BIT(6)) -#define EXTMEM_DCACHE_OCCUPY_EXC_INT_CLR_M (EXTMEM_DCACHE_OCCUPY_EXC_INT_CLR_V << EXTMEM_DCACHE_OCCUPY_EXC_INT_CLR_S) -#define EXTMEM_DCACHE_OCCUPY_EXC_INT_CLR_V 0x00000001 -#define EXTMEM_DCACHE_OCCUPY_EXC_INT_CLR_S 6 - -/* EXTMEM_MMU_ENTRY_FAULT_INT_CLR : WOD; bitpos: [5]; default: 0; - * The bit is used to clear interrupt by mmu entry fault. - */ - -#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR (BIT(5)) -#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_M (EXTMEM_MMU_ENTRY_FAULT_INT_CLR_V << EXTMEM_MMU_ENTRY_FAULT_INT_CLR_S) -#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_V 0x00000001 -#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_S 5 - -/* EXTMEM_DCACHE_WRITE_FLASH_INT_CLR : WOD; bitpos: [4]; default: 0; - * The bit is used to clear interrupt by dcache trying to write flash. - */ - -#define EXTMEM_DCACHE_WRITE_FLASH_INT_CLR (BIT(4)) -#define EXTMEM_DCACHE_WRITE_FLASH_INT_CLR_M (EXTMEM_DCACHE_WRITE_FLASH_INT_CLR_V << EXTMEM_DCACHE_WRITE_FLASH_INT_CLR_S) -#define EXTMEM_DCACHE_WRITE_FLASH_INT_CLR_V 0x00000001 -#define EXTMEM_DCACHE_WRITE_FLASH_INT_CLR_S 4 - -/* EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_CLR : WOD; bitpos: [3]; default: 0; - * The bit is used to clear interrupt by preload configurations fault. - */ - -#define EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_CLR (BIT(3)) -#define EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_CLR_M (EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_CLR_V << EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_CLR_S) -#define EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_CLR_V 0x00000001 -#define EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_CLR_S 3 - -/* EXTMEM_DCACHE_SYNC_OP_FAULT_INT_CLR : WOD; bitpos: [2]; default: 0; - * The bit is used to clear interrupt by sync configurations fault. - */ - -#define EXTMEM_DCACHE_SYNC_OP_FAULT_INT_CLR (BIT(2)) -#define EXTMEM_DCACHE_SYNC_OP_FAULT_INT_CLR_M (EXTMEM_DCACHE_SYNC_OP_FAULT_INT_CLR_V << EXTMEM_DCACHE_SYNC_OP_FAULT_INT_CLR_S) -#define EXTMEM_DCACHE_SYNC_OP_FAULT_INT_CLR_V 0x00000001 -#define EXTMEM_DCACHE_SYNC_OP_FAULT_INT_CLR_S 2 - -/* EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR : WOD; bitpos: [1]; default: 0; - * The bit is used to clear interrupt by preload configurations fault. - */ - -#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR (BIT(1)) -#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_M (EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_V << EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_S) -#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_V 0x00000001 -#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_S 1 - -/* EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR : WOD; bitpos: [0]; default: 0; - * The bit is used to clear interrupt by sync configurations fault. - */ - -#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR (BIT(0)) -#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR_M (EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR_V << EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR_S) -#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR_V 0x00000001 -#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR_S 0 - -/* EXTMEM_CACHE_ILG_INT_ST_REG register - * ******* Description *********** - */ - -#define EXTMEM_CACHE_ILG_INT_ST_REG (DR_REG_EXTMEM_BASE + 0xe4) - -/* EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_OVF_ST : RO; bitpos: [11]; default: 0; - * The bit is used to indicate interrupt by dbus access spiram miss counter - * overflow. - */ - -#define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_OVF_ST (BIT(11)) -#define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_OVF_ST_M (EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_OVF_ST_V << EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_OVF_ST_S) -#define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_OVF_ST_V 0x00000001 -#define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_OVF_ST_S 11 - -/* EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST : RO; bitpos: [10]; default: 0; - * The bit is used to indicate interrupt by dbus access flash miss counter - * overflow. - */ - -#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST (BIT(10)) -#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_M (EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_V << EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_S) -#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_V 0x00000001 -#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_S 10 - -/* EXTMEM_DBUS_ACS_CNT_OVF_ST : RO; bitpos: [9]; default: 0; - * The bit is used to indicate interrupt by dbus access flash/spiram counter - * overflow. - */ - -#define EXTMEM_DBUS_ACS_CNT_OVF_ST (BIT(9)) -#define EXTMEM_DBUS_ACS_CNT_OVF_ST_M (EXTMEM_DBUS_ACS_CNT_OVF_ST_V << EXTMEM_DBUS_ACS_CNT_OVF_ST_S) -#define EXTMEM_DBUS_ACS_CNT_OVF_ST_V 0x00000001 -#define EXTMEM_DBUS_ACS_CNT_OVF_ST_S 9 - -/* EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST : RO; bitpos: [8]; default: 0; - * The bit is used to indicate interrupt by ibus access flash/spiram miss - * counter overflow. - */ - -#define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST (BIT(8)) -#define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST_M (EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST_V << EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST_S) -#define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST_V 0x00000001 -#define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST_S 8 - -/* EXTMEM_IBUS_ACS_CNT_OVF_ST : RO; bitpos: [7]; default: 0; - * The bit is used to indicate interrupt by ibus access flash/spiram counter - * overflow. - */ - -#define EXTMEM_IBUS_ACS_CNT_OVF_ST (BIT(7)) -#define EXTMEM_IBUS_ACS_CNT_OVF_ST_M (EXTMEM_IBUS_ACS_CNT_OVF_ST_V << EXTMEM_IBUS_ACS_CNT_OVF_ST_S) -#define EXTMEM_IBUS_ACS_CNT_OVF_ST_V 0x00000001 -#define EXTMEM_IBUS_ACS_CNT_OVF_ST_S 7 - -/* EXTMEM_DCACHE_OCCUPY_EXC_ST : RO; bitpos: [6]; default: 0; - * The bit is used to indicate interrupt by dcache trying to replace a line - * whose blocks all have been occupied by occupy-mode. - */ - -#define EXTMEM_DCACHE_OCCUPY_EXC_ST (BIT(6)) -#define EXTMEM_DCACHE_OCCUPY_EXC_ST_M (EXTMEM_DCACHE_OCCUPY_EXC_ST_V << EXTMEM_DCACHE_OCCUPY_EXC_ST_S) -#define EXTMEM_DCACHE_OCCUPY_EXC_ST_V 0x00000001 -#define EXTMEM_DCACHE_OCCUPY_EXC_ST_S 6 - -/* EXTMEM_MMU_ENTRY_FAULT_ST : RO; bitpos: [5]; default: 0; - * The bit is used to indicate interrupt by mmu entry fault. - */ - -#define EXTMEM_MMU_ENTRY_FAULT_ST (BIT(5)) -#define EXTMEM_MMU_ENTRY_FAULT_ST_M (EXTMEM_MMU_ENTRY_FAULT_ST_V << EXTMEM_MMU_ENTRY_FAULT_ST_S) -#define EXTMEM_MMU_ENTRY_FAULT_ST_V 0x00000001 -#define EXTMEM_MMU_ENTRY_FAULT_ST_S 5 - -/* EXTMEM_DCACHE_WRITE_FLASH_ST : RO; bitpos: [4]; default: 0; - * The bit is used to indicate interrupt by dcache trying to write flash. - */ - -#define EXTMEM_DCACHE_WRITE_FLASH_ST (BIT(4)) -#define EXTMEM_DCACHE_WRITE_FLASH_ST_M (EXTMEM_DCACHE_WRITE_FLASH_ST_V << EXTMEM_DCACHE_WRITE_FLASH_ST_S) -#define EXTMEM_DCACHE_WRITE_FLASH_ST_V 0x00000001 -#define EXTMEM_DCACHE_WRITE_FLASH_ST_S 4 - -/* EXTMEM_DCACHE_PRELOAD_OP_FAULT_ST : RO; bitpos: [3]; default: 0; - * The bit is used to indicate interrupt by preload configurations fault. - */ - -#define EXTMEM_DCACHE_PRELOAD_OP_FAULT_ST (BIT(3)) -#define EXTMEM_DCACHE_PRELOAD_OP_FAULT_ST_M (EXTMEM_DCACHE_PRELOAD_OP_FAULT_ST_V << EXTMEM_DCACHE_PRELOAD_OP_FAULT_ST_S) -#define EXTMEM_DCACHE_PRELOAD_OP_FAULT_ST_V 0x00000001 -#define EXTMEM_DCACHE_PRELOAD_OP_FAULT_ST_S 3 - -/* EXTMEM_DCACHE_SYNC_OP_FAULT_ST : RO; bitpos: [2]; default: 0; - * The bit is used to indicate interrupt by sync configurations fault. - */ - -#define EXTMEM_DCACHE_SYNC_OP_FAULT_ST (BIT(2)) -#define EXTMEM_DCACHE_SYNC_OP_FAULT_ST_M (EXTMEM_DCACHE_SYNC_OP_FAULT_ST_V << EXTMEM_DCACHE_SYNC_OP_FAULT_ST_S) -#define EXTMEM_DCACHE_SYNC_OP_FAULT_ST_V 0x00000001 -#define EXTMEM_DCACHE_SYNC_OP_FAULT_ST_S 2 - -/* EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST : RO; bitpos: [1]; default: 0; - * The bit is used to indicate interrupt by preload configurations fault. - */ - -#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST (BIT(1)) -#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST_M (EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST_V << EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST_S) -#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST_V 0x00000001 -#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST_S 1 - -/* EXTMEM_ICACHE_SYNC_OP_FAULT_ST : RO; bitpos: [0]; default: 0; - * The bit is used to indicate interrupt by sync configurations fault. - */ - -#define EXTMEM_ICACHE_SYNC_OP_FAULT_ST (BIT(0)) -#define EXTMEM_ICACHE_SYNC_OP_FAULT_ST_M (EXTMEM_ICACHE_SYNC_OP_FAULT_ST_V << EXTMEM_ICACHE_SYNC_OP_FAULT_ST_S) -#define EXTMEM_ICACHE_SYNC_OP_FAULT_ST_V 0x00000001 -#define EXTMEM_ICACHE_SYNC_OP_FAULT_ST_S 0 - -/* EXTMEM_CORE0_ACS_CACHE_INT_ENA_REG register - * ******* Description *********** - */ - -#define EXTMEM_CORE0_ACS_CACHE_INT_ENA_REG (DR_REG_EXTMEM_BASE + 0xe8) - -/* EXTMEM_CORE0_DBUS_REJECT_INT_ENA : R/W; bitpos: [4]; default: 0; - * The bit is used to enable interrupt by authentication fail. - */ - -#define EXTMEM_CORE0_DBUS_REJECT_INT_ENA (BIT(4)) -#define EXTMEM_CORE0_DBUS_REJECT_INT_ENA_M (EXTMEM_CORE0_DBUS_REJECT_INT_ENA_V << EXTMEM_CORE0_DBUS_REJECT_INT_ENA_S) -#define EXTMEM_CORE0_DBUS_REJECT_INT_ENA_V 0x00000001 -#define EXTMEM_CORE0_DBUS_REJECT_INT_ENA_S 4 - -/* EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_ENA : R/W; bitpos: [3]; default: 0; - * The bit is used to enable interrupt by cpu access dcache while the - * corresponding dbus is disabled which include speculative access. - */ - -#define EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_ENA (BIT(3)) -#define EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_ENA_M (EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_ENA_V << EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_ENA_S) -#define EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_ENA_V 0x00000001 -#define EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_ENA_S 3 - -/* EXTMEM_CORE0_IBUS_REJECT_INT_ENA : R/W; bitpos: [2]; default: 0; - * The bit is used to enable interrupt by authentication fail. - */ - -#define EXTMEM_CORE0_IBUS_REJECT_INT_ENA (BIT(2)) -#define EXTMEM_CORE0_IBUS_REJECT_INT_ENA_M (EXTMEM_CORE0_IBUS_REJECT_INT_ENA_V << EXTMEM_CORE0_IBUS_REJECT_INT_ENA_S) -#define EXTMEM_CORE0_IBUS_REJECT_INT_ENA_V 0x00000001 -#define EXTMEM_CORE0_IBUS_REJECT_INT_ENA_S 2 - -/* EXTMEM_CORE0_IBUS_WR_IC_INT_ENA : R/W; bitpos: [1]; default: 0; - * The bit is used to enable interrupt by ibus trying to write icache - */ - -#define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA (BIT(1)) -#define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA_M (EXTMEM_CORE0_IBUS_WR_IC_INT_ENA_V << EXTMEM_CORE0_IBUS_WR_IC_INT_ENA_S) -#define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA_V 0x00000001 -#define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA_S 1 - -/* EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA : R/W; bitpos: [0]; default: 0; - * The bit is used to enable interrupt by cpu access icache while the - * corresponding ibus is disabled which include speculative access. - */ - -#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA (BIT(0)) -#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_M (EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_V << EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_S) -#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_V 0x00000001 -#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_S 0 - -/* EXTMEM_CORE0_ACS_CACHE_INT_CLR_REG register - * ******* Description *********** - */ - -#define EXTMEM_CORE0_ACS_CACHE_INT_CLR_REG (DR_REG_EXTMEM_BASE + 0xec) - -/* EXTMEM_CORE0_DBUS_REJECT_INT_CLR : WOD; bitpos: [4]; default: 0; - * The bit is used to clear interrupt by authentication fail. - */ - -#define EXTMEM_CORE0_DBUS_REJECT_INT_CLR (BIT(4)) -#define EXTMEM_CORE0_DBUS_REJECT_INT_CLR_M (EXTMEM_CORE0_DBUS_REJECT_INT_CLR_V << EXTMEM_CORE0_DBUS_REJECT_INT_CLR_S) -#define EXTMEM_CORE0_DBUS_REJECT_INT_CLR_V 0x00000001 -#define EXTMEM_CORE0_DBUS_REJECT_INT_CLR_S 4 - -/* EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_CLR : WOD; bitpos: [3]; default: 0; - * The bit is used to clear interrupt by cpu access dcache while the - * corresponding dbus is disabled or dcache is disabled which include - * speculative access. - */ - -#define EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_CLR (BIT(3)) -#define EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_CLR_M (EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_CLR_V << EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_CLR_S) -#define EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_CLR_V 0x00000001 -#define EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_CLR_S 3 - -/* EXTMEM_CORE0_IBUS_REJECT_INT_CLR : WOD; bitpos: [2]; default: 0; - * The bit is used to clear interrupt by authentication fail. - */ - -#define EXTMEM_CORE0_IBUS_REJECT_INT_CLR (BIT(2)) -#define EXTMEM_CORE0_IBUS_REJECT_INT_CLR_M (EXTMEM_CORE0_IBUS_REJECT_INT_CLR_V << EXTMEM_CORE0_IBUS_REJECT_INT_CLR_S) -#define EXTMEM_CORE0_IBUS_REJECT_INT_CLR_V 0x00000001 -#define EXTMEM_CORE0_IBUS_REJECT_INT_CLR_S 2 - -/* EXTMEM_CORE0_IBUS_WR_IC_INT_CLR : WOD; bitpos: [1]; default: 0; - * The bit is used to clear interrupt by ibus trying to write icache - */ - -#define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR (BIT(1)) -#define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR_M (EXTMEM_CORE0_IBUS_WR_IC_INT_CLR_V << EXTMEM_CORE0_IBUS_WR_IC_INT_CLR_S) -#define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR_V 0x00000001 -#define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR_S 1 - -/* EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR : WOD; bitpos: [0]; default: 0; - * The bit is used to clear interrupt by cpu access icache while the - * corresponding ibus is disabled or icache is disabled which include - * speculative access. - */ - -#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR (BIT(0)) -#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR_M (EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR_V << EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR_S) -#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR_V 0x00000001 -#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR_S 0 - -/* EXTMEM_CORE0_ACS_CACHE_INT_ST_REG register - * ******* Description *********** - */ - -#define EXTMEM_CORE0_ACS_CACHE_INT_ST_REG (DR_REG_EXTMEM_BASE + 0xf0) - -/* EXTMEM_CORE0_DBUS_REJECT_ST : RO; bitpos: [4]; default: 0; - * The bit is used to indicate interrupt by authentication fail. - */ - -#define EXTMEM_CORE0_DBUS_REJECT_ST (BIT(4)) -#define EXTMEM_CORE0_DBUS_REJECT_ST_M (EXTMEM_CORE0_DBUS_REJECT_ST_V << EXTMEM_CORE0_DBUS_REJECT_ST_S) -#define EXTMEM_CORE0_DBUS_REJECT_ST_V 0x00000001 -#define EXTMEM_CORE0_DBUS_REJECT_ST_S 4 - -/* EXTMEM_CORE0_DBUS_ACS_MSK_DCACHE_ST : RO; bitpos: [3]; default: 0; - * The bit is used to indicate interrupt by cpu access dcache while the - * core0_dbus is disabled or dcache is disabled which include speculative - * access. - */ - -#define EXTMEM_CORE0_DBUS_ACS_MSK_DCACHE_ST (BIT(3)) -#define EXTMEM_CORE0_DBUS_ACS_MSK_DCACHE_ST_M (EXTMEM_CORE0_DBUS_ACS_MSK_DCACHE_ST_V << EXTMEM_CORE0_DBUS_ACS_MSK_DCACHE_ST_S) -#define EXTMEM_CORE0_DBUS_ACS_MSK_DCACHE_ST_V 0x00000001 -#define EXTMEM_CORE0_DBUS_ACS_MSK_DCACHE_ST_S 3 - -/* EXTMEM_CORE0_IBUS_REJECT_ST : RO; bitpos: [2]; default: 0; - * The bit is used to indicate interrupt by authentication fail. - */ - -#define EXTMEM_CORE0_IBUS_REJECT_ST (BIT(2)) -#define EXTMEM_CORE0_IBUS_REJECT_ST_M (EXTMEM_CORE0_IBUS_REJECT_ST_V << EXTMEM_CORE0_IBUS_REJECT_ST_S) -#define EXTMEM_CORE0_IBUS_REJECT_ST_V 0x00000001 -#define EXTMEM_CORE0_IBUS_REJECT_ST_S 2 - -/* EXTMEM_CORE0_IBUS_WR_ICACHE_ST : RO; bitpos: [1]; default: 0; - * The bit is used to indicate interrupt by ibus trying to write icache - */ - -#define EXTMEM_CORE0_IBUS_WR_ICACHE_ST (BIT(1)) -#define EXTMEM_CORE0_IBUS_WR_ICACHE_ST_M (EXTMEM_CORE0_IBUS_WR_ICACHE_ST_V << EXTMEM_CORE0_IBUS_WR_ICACHE_ST_S) -#define EXTMEM_CORE0_IBUS_WR_ICACHE_ST_V 0x00000001 -#define EXTMEM_CORE0_IBUS_WR_ICACHE_ST_S 1 - -/* EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST : RO; bitpos: [0]; default: 0; - * The bit is used to indicate interrupt by cpu access icache while the - * core0_ibus is disabled or icache is disabled which include speculative - * access. - */ - -#define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST (BIT(0)) -#define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST_M (EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST_V << EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST_S) -#define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST_V 0x00000001 -#define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST_S 0 - -/* EXTMEM_CORE1_ACS_CACHE_INT_ENA_REG register - * ******* Description *********** - */ - -#define EXTMEM_CORE1_ACS_CACHE_INT_ENA_REG (DR_REG_EXTMEM_BASE + 0xf4) - -/* EXTMEM_CORE1_DBUS_REJECT_INT_ENA : R/W; bitpos: [4]; default: 0; - * The bit is used to enable interrupt by authentication fail. - */ - -#define EXTMEM_CORE1_DBUS_REJECT_INT_ENA (BIT(4)) -#define EXTMEM_CORE1_DBUS_REJECT_INT_ENA_M (EXTMEM_CORE1_DBUS_REJECT_INT_ENA_V << EXTMEM_CORE1_DBUS_REJECT_INT_ENA_S) -#define EXTMEM_CORE1_DBUS_REJECT_INT_ENA_V 0x00000001 -#define EXTMEM_CORE1_DBUS_REJECT_INT_ENA_S 4 - -/* EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_ENA : R/W; bitpos: [3]; default: 0; - * The bit is used to enable interrupt by cpu access dcache while the - * corresponding dbus is disabled which include speculative access. - */ - -#define EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_ENA (BIT(3)) -#define EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_ENA_M (EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_ENA_V << EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_ENA_S) -#define EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_ENA_V 0x00000001 -#define EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_ENA_S 3 - -/* EXTMEM_CORE1_IBUS_REJECT_INT_ENA : R/W; bitpos: [2]; default: 0; - * The bit is used to enable interrupt by authentication fail. - */ - -#define EXTMEM_CORE1_IBUS_REJECT_INT_ENA (BIT(2)) -#define EXTMEM_CORE1_IBUS_REJECT_INT_ENA_M (EXTMEM_CORE1_IBUS_REJECT_INT_ENA_V << EXTMEM_CORE1_IBUS_REJECT_INT_ENA_S) -#define EXTMEM_CORE1_IBUS_REJECT_INT_ENA_V 0x00000001 -#define EXTMEM_CORE1_IBUS_REJECT_INT_ENA_S 2 - -/* EXTMEM_CORE1_IBUS_WR_IC_INT_ENA : R/W; bitpos: [1]; default: 0; - * The bit is used to enable interrupt by ibus trying to write icache - */ - -#define EXTMEM_CORE1_IBUS_WR_IC_INT_ENA (BIT(1)) -#define EXTMEM_CORE1_IBUS_WR_IC_INT_ENA_M (EXTMEM_CORE1_IBUS_WR_IC_INT_ENA_V << EXTMEM_CORE1_IBUS_WR_IC_INT_ENA_S) -#define EXTMEM_CORE1_IBUS_WR_IC_INT_ENA_V 0x00000001 -#define EXTMEM_CORE1_IBUS_WR_IC_INT_ENA_S 1 - -/* EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_ENA : R/W; bitpos: [0]; default: 0; - * The bit is used to enable interrupt by cpu access icache while the - * corresponding ibus is disabled which include speculative access. - */ - -#define EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_ENA (BIT(0)) -#define EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_ENA_M (EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_ENA_V << EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_ENA_S) -#define EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_ENA_V 0x00000001 -#define EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_ENA_S 0 - -/* EXTMEM_CORE1_ACS_CACHE_INT_CLR_REG register - * ******* Description *********** - */ - -#define EXTMEM_CORE1_ACS_CACHE_INT_CLR_REG (DR_REG_EXTMEM_BASE + 0xf8) - -/* EXTMEM_CORE1_DBUS_REJECT_INT_CLR : WOD; bitpos: [4]; default: 0; - * The bit is used to clear interrupt by authentication fail. - */ - -#define EXTMEM_CORE1_DBUS_REJECT_INT_CLR (BIT(4)) -#define EXTMEM_CORE1_DBUS_REJECT_INT_CLR_M (EXTMEM_CORE1_DBUS_REJECT_INT_CLR_V << EXTMEM_CORE1_DBUS_REJECT_INT_CLR_S) -#define EXTMEM_CORE1_DBUS_REJECT_INT_CLR_V 0x00000001 -#define EXTMEM_CORE1_DBUS_REJECT_INT_CLR_S 4 - -/* EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_CLR : WOD; bitpos: [3]; default: 0; - * The bit is used to clear interrupt by cpu access dcache while the - * corresponding dbus is disabled or dcache is disabled which include - * speculative access. - */ - -#define EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_CLR (BIT(3)) -#define EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_CLR_M (EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_CLR_V << EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_CLR_S) -#define EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_CLR_V 0x00000001 -#define EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_CLR_S 3 - -/* EXTMEM_CORE1_IBUS_REJECT_INT_CLR : WOD; bitpos: [2]; default: 0; - * The bit is used to clear interrupt by authentication fail. - */ - -#define EXTMEM_CORE1_IBUS_REJECT_INT_CLR (BIT(2)) -#define EXTMEM_CORE1_IBUS_REJECT_INT_CLR_M (EXTMEM_CORE1_IBUS_REJECT_INT_CLR_V << EXTMEM_CORE1_IBUS_REJECT_INT_CLR_S) -#define EXTMEM_CORE1_IBUS_REJECT_INT_CLR_V 0x00000001 -#define EXTMEM_CORE1_IBUS_REJECT_INT_CLR_S 2 - -/* EXTMEM_CORE1_IBUS_WR_IC_INT_CLR : WOD; bitpos: [1]; default: 0; - * The bit is used to clear interrupt by ibus trying to write icache - */ - -#define EXTMEM_CORE1_IBUS_WR_IC_INT_CLR (BIT(1)) -#define EXTMEM_CORE1_IBUS_WR_IC_INT_CLR_M (EXTMEM_CORE1_IBUS_WR_IC_INT_CLR_V << EXTMEM_CORE1_IBUS_WR_IC_INT_CLR_S) -#define EXTMEM_CORE1_IBUS_WR_IC_INT_CLR_V 0x00000001 -#define EXTMEM_CORE1_IBUS_WR_IC_INT_CLR_S 1 - -/* EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_CLR : WOD; bitpos: [0]; default: 0; - * The bit is used to clear interrupt by cpu access icache while the - * corresponding ibus is disabled or icache is disabled which include - * speculative access. - */ - -#define EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_CLR (BIT(0)) -#define EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_CLR_M (EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_CLR_V << EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_CLR_S) -#define EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_CLR_V 0x00000001 -#define EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_CLR_S 0 - -/* EXTMEM_CORE1_ACS_CACHE_INT_ST_REG register - * ******* Description *********** - */ - -#define EXTMEM_CORE1_ACS_CACHE_INT_ST_REG (DR_REG_EXTMEM_BASE + 0xfc) - -/* EXTMEM_CORE1_DBUS_REJECT_ST : RO; bitpos: [4]; default: 0; - * The bit is used to indicate interrupt by authentication fail. - */ - -#define EXTMEM_CORE1_DBUS_REJECT_ST (BIT(4)) -#define EXTMEM_CORE1_DBUS_REJECT_ST_M (EXTMEM_CORE1_DBUS_REJECT_ST_V << EXTMEM_CORE1_DBUS_REJECT_ST_S) -#define EXTMEM_CORE1_DBUS_REJECT_ST_V 0x00000001 -#define EXTMEM_CORE1_DBUS_REJECT_ST_S 4 - -/* EXTMEM_CORE1_DBUS_ACS_MSK_DCACHE_ST : RO; bitpos: [3]; default: 0; - * The bit is used to indicate interrupt by cpu access dcache while the - * core1_dbus is disabled or dcache is disabled which include speculative - * access. - */ - -#define EXTMEM_CORE1_DBUS_ACS_MSK_DCACHE_ST (BIT(3)) -#define EXTMEM_CORE1_DBUS_ACS_MSK_DCACHE_ST_M (EXTMEM_CORE1_DBUS_ACS_MSK_DCACHE_ST_V << EXTMEM_CORE1_DBUS_ACS_MSK_DCACHE_ST_S) -#define EXTMEM_CORE1_DBUS_ACS_MSK_DCACHE_ST_V 0x00000001 -#define EXTMEM_CORE1_DBUS_ACS_MSK_DCACHE_ST_S 3 - -/* EXTMEM_CORE1_IBUS_REJECT_ST : RO; bitpos: [2]; default: 0; - * The bit is used to indicate interrupt by authentication fail. - */ - -#define EXTMEM_CORE1_IBUS_REJECT_ST (BIT(2)) -#define EXTMEM_CORE1_IBUS_REJECT_ST_M (EXTMEM_CORE1_IBUS_REJECT_ST_V << EXTMEM_CORE1_IBUS_REJECT_ST_S) -#define EXTMEM_CORE1_IBUS_REJECT_ST_V 0x00000001 -#define EXTMEM_CORE1_IBUS_REJECT_ST_S 2 - -/* EXTMEM_CORE1_IBUS_WR_ICACHE_ST : RO; bitpos: [1]; default: 0; - * The bit is used to indicate interrupt by ibus trying to write icache - */ - -#define EXTMEM_CORE1_IBUS_WR_ICACHE_ST (BIT(1)) -#define EXTMEM_CORE1_IBUS_WR_ICACHE_ST_M (EXTMEM_CORE1_IBUS_WR_ICACHE_ST_V << EXTMEM_CORE1_IBUS_WR_ICACHE_ST_S) -#define EXTMEM_CORE1_IBUS_WR_ICACHE_ST_V 0x00000001 -#define EXTMEM_CORE1_IBUS_WR_ICACHE_ST_S 1 - -/* EXTMEM_CORE1_IBUS_ACS_MSK_ICACHE_ST : RO; bitpos: [0]; default: 0; - * The bit is used to indicate interrupt by cpu access icache while the - * core1_ibus is disabled or icache is disabled which include speculative - * access. - */ - -#define EXTMEM_CORE1_IBUS_ACS_MSK_ICACHE_ST (BIT(0)) -#define EXTMEM_CORE1_IBUS_ACS_MSK_ICACHE_ST_M (EXTMEM_CORE1_IBUS_ACS_MSK_ICACHE_ST_V << EXTMEM_CORE1_IBUS_ACS_MSK_ICACHE_ST_S) -#define EXTMEM_CORE1_IBUS_ACS_MSK_ICACHE_ST_V 0x00000001 -#define EXTMEM_CORE1_IBUS_ACS_MSK_ICACHE_ST_S 0 - -/* EXTMEM_CORE0_DBUS_REJECT_ST_REG register - * ******* Description *********** - */ - -#define EXTMEM_CORE0_DBUS_REJECT_ST_REG (DR_REG_EXTMEM_BASE + 0x100) - -/* EXTMEM_CORE0_DBUS_WORLD : RO; bitpos: [6]; default: 0; - * The bit is used to indicate the world of CPU access dbus when - * authentication fail. 0: WORLD0, 1: WORLD1 - */ - -#define EXTMEM_CORE0_DBUS_WORLD (BIT(6)) -#define EXTMEM_CORE0_DBUS_WORLD_M (EXTMEM_CORE0_DBUS_WORLD_V << EXTMEM_CORE0_DBUS_WORLD_S) -#define EXTMEM_CORE0_DBUS_WORLD_V 0x00000001 -#define EXTMEM_CORE0_DBUS_WORLD_S 6 - -/* EXTMEM_CORE0_DBUS_ATTR : RO; bitpos: [5:3]; default: 0; - * The bits are used to indicate the attribute of CPU access dbus when - * authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: - * write-able. - */ - -#define EXTMEM_CORE0_DBUS_ATTR 0x00000007 -#define EXTMEM_CORE0_DBUS_ATTR_M (EXTMEM_CORE0_DBUS_ATTR_V << EXTMEM_CORE0_DBUS_ATTR_S) -#define EXTMEM_CORE0_DBUS_ATTR_V 0x00000007 -#define EXTMEM_CORE0_DBUS_ATTR_S 3 - -/* EXTMEM_CORE0_DBUS_TAG_ATTR : RO; bitpos: [2:0]; default: 0; - * The bits are used to indicate the attribute of data from external memory - * when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, - * 4: write-able. - */ - -#define EXTMEM_CORE0_DBUS_TAG_ATTR 0x00000007 -#define EXTMEM_CORE0_DBUS_TAG_ATTR_M (EXTMEM_CORE0_DBUS_TAG_ATTR_V << EXTMEM_CORE0_DBUS_TAG_ATTR_S) -#define EXTMEM_CORE0_DBUS_TAG_ATTR_V 0x00000007 -#define EXTMEM_CORE0_DBUS_TAG_ATTR_S 0 - -/* EXTMEM_CORE0_DBUS_REJECT_VADDR_REG register - * ******* Description *********** - */ - -#define EXTMEM_CORE0_DBUS_REJECT_VADDR_REG (DR_REG_EXTMEM_BASE + 0x104) - -/* EXTMEM_CORE0_DBUS_VADDR : RO; bitpos: [31:0]; default: 4294967295; - * The bits are used to indicate the virtual address of CPU access dbus when - * authentication fail. - */ - -#define EXTMEM_CORE0_DBUS_VADDR 0xffffffff -#define EXTMEM_CORE0_DBUS_VADDR_M (EXTMEM_CORE0_DBUS_VADDR_V << EXTMEM_CORE0_DBUS_VADDR_S) -#define EXTMEM_CORE0_DBUS_VADDR_V 0xffffffff -#define EXTMEM_CORE0_DBUS_VADDR_S 0 - -/* EXTMEM_CORE0_IBUS_REJECT_ST_REG register - * ******* Description *********** - */ - -#define EXTMEM_CORE0_IBUS_REJECT_ST_REG (DR_REG_EXTMEM_BASE + 0x108) - -/* EXTMEM_CORE0_IBUS_WORLD : RO; bitpos: [6]; default: 0; - * The bit is used to indicate the world of CPU access ibus when - * authentication fail. 0: WORLD0, 1: WORLD1 - */ - -#define EXTMEM_CORE0_IBUS_WORLD (BIT(6)) -#define EXTMEM_CORE0_IBUS_WORLD_M (EXTMEM_CORE0_IBUS_WORLD_V << EXTMEM_CORE0_IBUS_WORLD_S) -#define EXTMEM_CORE0_IBUS_WORLD_V 0x00000001 -#define EXTMEM_CORE0_IBUS_WORLD_S 6 - -/* EXTMEM_CORE0_IBUS_ATTR : RO; bitpos: [5:3]; default: 0; - * The bits are used to indicate the attribute of CPU access ibus when - * authentication fail. 0: invalidate, 1: execute-able, 2: read-able - */ - -#define EXTMEM_CORE0_IBUS_ATTR 0x00000007 -#define EXTMEM_CORE0_IBUS_ATTR_M (EXTMEM_CORE0_IBUS_ATTR_V << EXTMEM_CORE0_IBUS_ATTR_S) -#define EXTMEM_CORE0_IBUS_ATTR_V 0x00000007 -#define EXTMEM_CORE0_IBUS_ATTR_S 3 - -/* EXTMEM_CORE0_IBUS_TAG_ATTR : RO; bitpos: [2:0]; default: 0; - * The bits are used to indicate the attribute of data from external memory - * when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, - * 4: write-able. - */ - -#define EXTMEM_CORE0_IBUS_TAG_ATTR 0x00000007 -#define EXTMEM_CORE0_IBUS_TAG_ATTR_M (EXTMEM_CORE0_IBUS_TAG_ATTR_V << EXTMEM_CORE0_IBUS_TAG_ATTR_S) -#define EXTMEM_CORE0_IBUS_TAG_ATTR_V 0x00000007 -#define EXTMEM_CORE0_IBUS_TAG_ATTR_S 0 - -/* EXTMEM_CORE0_IBUS_REJECT_VADDR_REG register - * ******* Description *********** - */ - -#define EXTMEM_CORE0_IBUS_REJECT_VADDR_REG (DR_REG_EXTMEM_BASE + 0x10c) - -/* EXTMEM_CORE0_IBUS_VADDR : RO; bitpos: [31:0]; default: 4294967295; - * The bits are used to indicate the virtual address of CPU access ibus - * when authentication fail. - */ - -#define EXTMEM_CORE0_IBUS_VADDR 0xffffffff -#define EXTMEM_CORE0_IBUS_VADDR_M (EXTMEM_CORE0_IBUS_VADDR_V << EXTMEM_CORE0_IBUS_VADDR_S) -#define EXTMEM_CORE0_IBUS_VADDR_V 0xffffffff -#define EXTMEM_CORE0_IBUS_VADDR_S 0 - -/* EXTMEM_CORE1_DBUS_REJECT_ST_REG register - * ******* Description *********** - */ - -#define EXTMEM_CORE1_DBUS_REJECT_ST_REG (DR_REG_EXTMEM_BASE + 0x110) - -/* EXTMEM_CORE1_DBUS_WORLD : RO; bitpos: [6]; default: 0; - * The bit is used to indicate the world of CPU access dbus when - * authentication fail. 0: WORLD0, 1: WORLD1 - */ - -#define EXTMEM_CORE1_DBUS_WORLD (BIT(6)) -#define EXTMEM_CORE1_DBUS_WORLD_M (EXTMEM_CORE1_DBUS_WORLD_V << EXTMEM_CORE1_DBUS_WORLD_S) -#define EXTMEM_CORE1_DBUS_WORLD_V 0x00000001 -#define EXTMEM_CORE1_DBUS_WORLD_S 6 - -/* EXTMEM_CORE1_DBUS_ATTR : RO; bitpos: [5:3]; default: 0; - * The bits are used to indicate the attribute of CPU access dbus when - * authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: - * write-able. - */ - -#define EXTMEM_CORE1_DBUS_ATTR 0x00000007 -#define EXTMEM_CORE1_DBUS_ATTR_M (EXTMEM_CORE1_DBUS_ATTR_V << EXTMEM_CORE1_DBUS_ATTR_S) -#define EXTMEM_CORE1_DBUS_ATTR_V 0x00000007 -#define EXTMEM_CORE1_DBUS_ATTR_S 3 - -/* EXTMEM_CORE1_DBUS_TAG_ATTR : RO; bitpos: [2:0]; default: 0; - * The bits are used to indicate the attribute of data from external memory - * when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, - * 4: write-able. - */ - -#define EXTMEM_CORE1_DBUS_TAG_ATTR 0x00000007 -#define EXTMEM_CORE1_DBUS_TAG_ATTR_M (EXTMEM_CORE1_DBUS_TAG_ATTR_V << EXTMEM_CORE1_DBUS_TAG_ATTR_S) -#define EXTMEM_CORE1_DBUS_TAG_ATTR_V 0x00000007 -#define EXTMEM_CORE1_DBUS_TAG_ATTR_S 0 - -/* EXTMEM_CORE1_DBUS_REJECT_VADDR_REG register - * ******* Description *********** - */ - -#define EXTMEM_CORE1_DBUS_REJECT_VADDR_REG (DR_REG_EXTMEM_BASE + 0x114) - -/* EXTMEM_CORE1_DBUS_VADDR : RO; bitpos: [31:0]; default: 4294967295; - * The bits are used to indicate the virtual address of CPU access dbus when - * authentication fail. - */ - -#define EXTMEM_CORE1_DBUS_VADDR 0xffffffff -#define EXTMEM_CORE1_DBUS_VADDR_M (EXTMEM_CORE1_DBUS_VADDR_V << EXTMEM_CORE1_DBUS_VADDR_S) -#define EXTMEM_CORE1_DBUS_VADDR_V 0xffffffff -#define EXTMEM_CORE1_DBUS_VADDR_S 0 - -/* EXTMEM_CORE1_IBUS_REJECT_ST_REG register - * ******* Description *********** - */ - -#define EXTMEM_CORE1_IBUS_REJECT_ST_REG (DR_REG_EXTMEM_BASE + 0x118) - -/* EXTMEM_CORE1_IBUS_WORLD : RO; bitpos: [6]; default: 0; - * The bit is used to indicate the world of CPU access ibus when - * authentication fail. 0: WORLD0, 1: WORLD1 - */ - -#define EXTMEM_CORE1_IBUS_WORLD (BIT(6)) -#define EXTMEM_CORE1_IBUS_WORLD_M (EXTMEM_CORE1_IBUS_WORLD_V << EXTMEM_CORE1_IBUS_WORLD_S) -#define EXTMEM_CORE1_IBUS_WORLD_V 0x00000001 -#define EXTMEM_CORE1_IBUS_WORLD_S 6 - -/* EXTMEM_CORE1_IBUS_ATTR : RO; bitpos: [5:3]; default: 0; - * The bits are used to indicate the attribute of CPU access ibus when - * authentication fail. 0: invalidate, 1: execute-able, 2: read-able - */ - -#define EXTMEM_CORE1_IBUS_ATTR 0x00000007 -#define EXTMEM_CORE1_IBUS_ATTR_M (EXTMEM_CORE1_IBUS_ATTR_V << EXTMEM_CORE1_IBUS_ATTR_S) -#define EXTMEM_CORE1_IBUS_ATTR_V 0x00000007 -#define EXTMEM_CORE1_IBUS_ATTR_S 3 - -/* EXTMEM_CORE1_IBUS_TAG_ATTR : RO; bitpos: [2:0]; default: 0; - * The bits are used to indicate the attribute of data from external memory - * when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, - * 4: write-able. - */ - -#define EXTMEM_CORE1_IBUS_TAG_ATTR 0x00000007 -#define EXTMEM_CORE1_IBUS_TAG_ATTR_M (EXTMEM_CORE1_IBUS_TAG_ATTR_V << EXTMEM_CORE1_IBUS_TAG_ATTR_S) -#define EXTMEM_CORE1_IBUS_TAG_ATTR_V 0x00000007 -#define EXTMEM_CORE1_IBUS_TAG_ATTR_S 0 - -/* EXTMEM_CORE1_IBUS_REJECT_VADDR_REG register - * ******* Description *********** - */ - -#define EXTMEM_CORE1_IBUS_REJECT_VADDR_REG (DR_REG_EXTMEM_BASE + 0x11c) - -/* EXTMEM_CORE1_IBUS_VADDR : RO; bitpos: [31:0]; default: 4294967295; - * The bits are used to indicate the virtual address of CPU access ibus - * when authentication fail. - */ - -#define EXTMEM_CORE1_IBUS_VADDR 0xffffffff -#define EXTMEM_CORE1_IBUS_VADDR_M (EXTMEM_CORE1_IBUS_VADDR_V << EXTMEM_CORE1_IBUS_VADDR_S) -#define EXTMEM_CORE1_IBUS_VADDR_V 0xffffffff -#define EXTMEM_CORE1_IBUS_VADDR_S 0 - -/* EXTMEM_CACHE_MMU_FAULT_CONTENT_REG register - * ******* Description *********** - */ - -#define EXTMEM_CACHE_MMU_FAULT_CONTENT_REG (DR_REG_EXTMEM_BASE + 0x120) - -/* EXTMEM_CACHE_MMU_FAULT_CODE : RO; bitpos: [19:16]; default: 0; - * The right-most 3 bits are used to indicate the operations which cause mmu - * fault occurrence. 0: default, 1: cpu miss, 2: preload miss, 3: writeback, - * 4: cpu miss evict recovery address, 5: load miss evict recovery address, - * 6: external dma tx, 7: external dma rx. The most significant bit is used - * to indicate this operation occurs in which one icache. - */ - -#define EXTMEM_CACHE_MMU_FAULT_CODE 0x0000000f -#define EXTMEM_CACHE_MMU_FAULT_CODE_M (EXTMEM_CACHE_MMU_FAULT_CODE_V << EXTMEM_CACHE_MMU_FAULT_CODE_S) -#define EXTMEM_CACHE_MMU_FAULT_CODE_V 0x0000000f -#define EXTMEM_CACHE_MMU_FAULT_CODE_S 16 - -/* EXTMEM_CACHE_MMU_FAULT_CONTENT : RO; bitpos: [15:0]; default: 0; - * The bits are used to indicate the content of mmu entry which cause mmu - * fault.. - */ - -#define EXTMEM_CACHE_MMU_FAULT_CONTENT 0x0000ffff -#define EXTMEM_CACHE_MMU_FAULT_CONTENT_M (EXTMEM_CACHE_MMU_FAULT_CONTENT_V << EXTMEM_CACHE_MMU_FAULT_CONTENT_S) -#define EXTMEM_CACHE_MMU_FAULT_CONTENT_V 0x0000ffff -#define EXTMEM_CACHE_MMU_FAULT_CONTENT_S 0 - -/* EXTMEM_CACHE_MMU_FAULT_VADDR_REG register - * ******* Description *********** - */ - -#define EXTMEM_CACHE_MMU_FAULT_VADDR_REG (DR_REG_EXTMEM_BASE + 0x124) - -/* EXTMEM_CACHE_MMU_FAULT_VADDR : RO; bitpos: [31:0]; default: 0; - * The bits are used to indicate the virtual address which cause mmu fault.. - */ - -#define EXTMEM_CACHE_MMU_FAULT_VADDR 0xffffffff -#define EXTMEM_CACHE_MMU_FAULT_VADDR_M (EXTMEM_CACHE_MMU_FAULT_VADDR_V << EXTMEM_CACHE_MMU_FAULT_VADDR_S) -#define EXTMEM_CACHE_MMU_FAULT_VADDR_V 0xffffffff -#define EXTMEM_CACHE_MMU_FAULT_VADDR_S 0 - -/* EXTMEM_CACHE_WRAP_AROUND_CTRL_REG register - * ******* Description *********** - */ - -#define EXTMEM_CACHE_WRAP_AROUND_CTRL_REG (DR_REG_EXTMEM_BASE + 0x128) - -/* EXTMEM_CACHE_SRAM_RD_WRAP_AROUND : R/W; bitpos: [1]; default: 0; - * The bit is used to enable wrap around mode when read data from spiram. - */ - -#define EXTMEM_CACHE_SRAM_RD_WRAP_AROUND (BIT(1)) -#define EXTMEM_CACHE_SRAM_RD_WRAP_AROUND_M (EXTMEM_CACHE_SRAM_RD_WRAP_AROUND_V << EXTMEM_CACHE_SRAM_RD_WRAP_AROUND_S) -#define EXTMEM_CACHE_SRAM_RD_WRAP_AROUND_V 0x00000001 -#define EXTMEM_CACHE_SRAM_RD_WRAP_AROUND_S 1 - -/* EXTMEM_CACHE_FLASH_WRAP_AROUND : R/W; bitpos: [0]; default: 0; - * The bit is used to enable wrap around mode when read data from flash. - */ - -#define EXTMEM_CACHE_FLASH_WRAP_AROUND (BIT(0)) -#define EXTMEM_CACHE_FLASH_WRAP_AROUND_M (EXTMEM_CACHE_FLASH_WRAP_AROUND_V << EXTMEM_CACHE_FLASH_WRAP_AROUND_S) -#define EXTMEM_CACHE_FLASH_WRAP_AROUND_V 0x00000001 -#define EXTMEM_CACHE_FLASH_WRAP_AROUND_S 0 - -/* EXTMEM_CACHE_MMU_POWER_CTRL_REG register - * ******* Description *********** - */ - -#define EXTMEM_CACHE_MMU_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x12c) - -/* EXTMEM_CACHE_MMU_MEM_FORCE_PU : R/W; bitpos: [2]; default: 1; - * The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power - * up - */ - -#define EXTMEM_CACHE_MMU_MEM_FORCE_PU (BIT(2)) -#define EXTMEM_CACHE_MMU_MEM_FORCE_PU_M (EXTMEM_CACHE_MMU_MEM_FORCE_PU_V << EXTMEM_CACHE_MMU_MEM_FORCE_PU_S) -#define EXTMEM_CACHE_MMU_MEM_FORCE_PU_V 0x00000001 -#define EXTMEM_CACHE_MMU_MEM_FORCE_PU_S 2 - -/* EXTMEM_CACHE_MMU_MEM_FORCE_PD : R/W; bitpos: [1]; default: 0; - * The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power - * down - */ - -#define EXTMEM_CACHE_MMU_MEM_FORCE_PD (BIT(1)) -#define EXTMEM_CACHE_MMU_MEM_FORCE_PD_M (EXTMEM_CACHE_MMU_MEM_FORCE_PD_V << EXTMEM_CACHE_MMU_MEM_FORCE_PD_S) -#define EXTMEM_CACHE_MMU_MEM_FORCE_PD_V 0x00000001 -#define EXTMEM_CACHE_MMU_MEM_FORCE_PD_S 1 - -/* EXTMEM_CACHE_MMU_MEM_FORCE_ON : R/W; bitpos: [0]; default: 1; - * The bit is used to enable clock gating to save power when access mmu - * memory, 0: enable, 1: disable - */ - -#define EXTMEM_CACHE_MMU_MEM_FORCE_ON (BIT(0)) -#define EXTMEM_CACHE_MMU_MEM_FORCE_ON_M (EXTMEM_CACHE_MMU_MEM_FORCE_ON_V << EXTMEM_CACHE_MMU_MEM_FORCE_ON_S) -#define EXTMEM_CACHE_MMU_MEM_FORCE_ON_V 0x00000001 -#define EXTMEM_CACHE_MMU_MEM_FORCE_ON_S 0 - -/* EXTMEM_CACHE_STATE_REG register - * ******* Description *********** - */ - -#define EXTMEM_CACHE_STATE_REG (DR_REG_EXTMEM_BASE + 0x130) - -/* EXTMEM_DCACHE_STATE : RO; bitpos: [23:12]; default: 0; - * The bit is used to indicate whether dcache main fsm is in idle state or - * not. 1: in idle state, 0: not in idle state - */ - -#define EXTMEM_DCACHE_STATE 0x00000fff -#define EXTMEM_DCACHE_STATE_M (EXTMEM_DCACHE_STATE_V << EXTMEM_DCACHE_STATE_S) -#define EXTMEM_DCACHE_STATE_V 0x00000fff -#define EXTMEM_DCACHE_STATE_S 12 - -/* EXTMEM_ICACHE_STATE : RO; bitpos: [11:0]; default: 0; - * The bit is used to indicate whether icache main fsm is in idle state or - * not. 1: in idle state, 0: not in idle state - */ - -#define EXTMEM_ICACHE_STATE 0x00000fff -#define EXTMEM_ICACHE_STATE_M (EXTMEM_ICACHE_STATE_V << EXTMEM_ICACHE_STATE_S) -#define EXTMEM_ICACHE_STATE_V 0x00000fff -#define EXTMEM_ICACHE_STATE_S 0 - -/* EXTMEM_CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_REG register - * ******* Description *********** - */ - -#define EXTMEM_CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_REG (DR_REG_EXTMEM_BASE + 0x134) - -/* EXTMEM_RECORD_DISABLE_G0CB_DECRYPT : R/W; bitpos: [1]; default: 0; - * Reserved - */ - -#define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT (BIT(1)) -#define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_M (EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_V << EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_S) -#define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_V 0x00000001 -#define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_S 1 - -/* EXTMEM_RECORD_DISABLE_DB_ENCRYPT : R/W; bitpos: [0]; default: 0; - * Reserved - */ - -#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT (BIT(0)) -#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_M (EXTMEM_RECORD_DISABLE_DB_ENCRYPT_V << EXTMEM_RECORD_DISABLE_DB_ENCRYPT_S) -#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_V 0x00000001 -#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_S 0 - -/* EXTMEM_CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_REG register - * ******* Description *********** - */ - -#define EXTMEM_CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_REG (DR_REG_EXTMEM_BASE + 0x138) - -/* EXTMEM_CLK_FORCE_ON_CRYPT : R/W; bitpos: [2]; default: 1; - * The bit is used to close clock gating of external memory encrypt and - * decrypt clock. 1: close gating, 0: open clock gating. - */ - -#define EXTMEM_CLK_FORCE_ON_CRYPT (BIT(2)) -#define EXTMEM_CLK_FORCE_ON_CRYPT_M (EXTMEM_CLK_FORCE_ON_CRYPT_V << EXTMEM_CLK_FORCE_ON_CRYPT_S) -#define EXTMEM_CLK_FORCE_ON_CRYPT_V 0x00000001 -#define EXTMEM_CLK_FORCE_ON_CRYPT_S 2 - -/* EXTMEM_CLK_FORCE_ON_AUTO_CRYPT : R/W; bitpos: [1]; default: 1; - * The bit is used to close clock gating of automatic crypt clock. 1: close - * gating, 0: open clock gating. - */ - -#define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT (BIT(1)) -#define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT_M (EXTMEM_CLK_FORCE_ON_AUTO_CRYPT_V << EXTMEM_CLK_FORCE_ON_AUTO_CRYPT_S) -#define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT_V 0x00000001 -#define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT_S 1 - -/* EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT : R/W; bitpos: [0]; default: 1; - * The bit is used to close clock gating of manual crypt clock. 1: close - * gating, 0: open clock gating. - */ - -#define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT (BIT(0)) -#define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT_M (EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT_V << EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT_S) -#define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT_V 0x00000001 -#define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT_S 0 - -/* EXTMEM_CACHE_BRIDGE_ARBITER_CTRL_REG register - * ******* Description *********** - */ - -#define EXTMEM_CACHE_BRIDGE_ARBITER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x13c) - -/* EXTMEM_ALLOC_WB_HOLD_ARBITER : R/W; bitpos: [0]; default: 0; - * Reserved - */ - -#define EXTMEM_ALLOC_WB_HOLD_ARBITER (BIT(0)) -#define EXTMEM_ALLOC_WB_HOLD_ARBITER_M (EXTMEM_ALLOC_WB_HOLD_ARBITER_V << EXTMEM_ALLOC_WB_HOLD_ARBITER_S) -#define EXTMEM_ALLOC_WB_HOLD_ARBITER_V 0x00000001 -#define EXTMEM_ALLOC_WB_HOLD_ARBITER_S 0 - -/* EXTMEM_CACHE_PRELOAD_INT_CTRL_REG register - * ******* Description *********** - */ - -#define EXTMEM_CACHE_PRELOAD_INT_CTRL_REG (DR_REG_EXTMEM_BASE + 0x140) - -/* EXTMEM_DCACHE_PRELOAD_INT_CLR : WOD; bitpos: [5]; default: 0; - * The bit is used to clear the interrupt by dcache pre-load done. - */ - -#define EXTMEM_DCACHE_PRELOAD_INT_CLR (BIT(5)) -#define EXTMEM_DCACHE_PRELOAD_INT_CLR_M (EXTMEM_DCACHE_PRELOAD_INT_CLR_V << EXTMEM_DCACHE_PRELOAD_INT_CLR_S) -#define EXTMEM_DCACHE_PRELOAD_INT_CLR_V 0x00000001 -#define EXTMEM_DCACHE_PRELOAD_INT_CLR_S 5 - -/* EXTMEM_DCACHE_PRELOAD_INT_ENA : R/W; bitpos: [4]; default: 0; - * The bit is used to enable the interrupt by dcache pre-load done. - */ - -#define EXTMEM_DCACHE_PRELOAD_INT_ENA (BIT(4)) -#define EXTMEM_DCACHE_PRELOAD_INT_ENA_M (EXTMEM_DCACHE_PRELOAD_INT_ENA_V << EXTMEM_DCACHE_PRELOAD_INT_ENA_S) -#define EXTMEM_DCACHE_PRELOAD_INT_ENA_V 0x00000001 -#define EXTMEM_DCACHE_PRELOAD_INT_ENA_S 4 - -/* EXTMEM_DCACHE_PRELOAD_INT_ST : RO; bitpos: [3]; default: 0; - * The bit is used to indicate the interrupt by dcache pre-load done. - */ - -#define EXTMEM_DCACHE_PRELOAD_INT_ST (BIT(3)) -#define EXTMEM_DCACHE_PRELOAD_INT_ST_M (EXTMEM_DCACHE_PRELOAD_INT_ST_V << EXTMEM_DCACHE_PRELOAD_INT_ST_S) -#define EXTMEM_DCACHE_PRELOAD_INT_ST_V 0x00000001 -#define EXTMEM_DCACHE_PRELOAD_INT_ST_S 3 - -/* EXTMEM_ICACHE_PRELOAD_INT_CLR : WOD; bitpos: [2]; default: 0; - * The bit is used to clear the interrupt by icache pre-load done. - */ - -#define EXTMEM_ICACHE_PRELOAD_INT_CLR (BIT(2)) -#define EXTMEM_ICACHE_PRELOAD_INT_CLR_M (EXTMEM_ICACHE_PRELOAD_INT_CLR_V << EXTMEM_ICACHE_PRELOAD_INT_CLR_S) -#define EXTMEM_ICACHE_PRELOAD_INT_CLR_V 0x00000001 -#define EXTMEM_ICACHE_PRELOAD_INT_CLR_S 2 - -/* EXTMEM_ICACHE_PRELOAD_INT_ENA : R/W; bitpos: [1]; default: 0; - * The bit is used to enable the interrupt by icache pre-load done. - */ - -#define EXTMEM_ICACHE_PRELOAD_INT_ENA (BIT(1)) -#define EXTMEM_ICACHE_PRELOAD_INT_ENA_M (EXTMEM_ICACHE_PRELOAD_INT_ENA_V << EXTMEM_ICACHE_PRELOAD_INT_ENA_S) -#define EXTMEM_ICACHE_PRELOAD_INT_ENA_V 0x00000001 -#define EXTMEM_ICACHE_PRELOAD_INT_ENA_S 1 - -/* EXTMEM_ICACHE_PRELOAD_INT_ST : RO; bitpos: [0]; default: 0; - * The bit is used to indicate the interrupt by icache pre-load done. - */ - -#define EXTMEM_ICACHE_PRELOAD_INT_ST (BIT(0)) -#define EXTMEM_ICACHE_PRELOAD_INT_ST_M (EXTMEM_ICACHE_PRELOAD_INT_ST_V << EXTMEM_ICACHE_PRELOAD_INT_ST_S) -#define EXTMEM_ICACHE_PRELOAD_INT_ST_V 0x00000001 -#define EXTMEM_ICACHE_PRELOAD_INT_ST_S 0 - -/* EXTMEM_CACHE_SYNC_INT_CTRL_REG register - * ******* Description *********** - */ - -#define EXTMEM_CACHE_SYNC_INT_CTRL_REG (DR_REG_EXTMEM_BASE + 0x144) - -/* EXTMEM_DCACHE_SYNC_INT_CLR : WOD; bitpos: [5]; default: 0; - * The bit is used to clear the interrupt by dcache sync done. - */ - -#define EXTMEM_DCACHE_SYNC_INT_CLR (BIT(5)) -#define EXTMEM_DCACHE_SYNC_INT_CLR_M (EXTMEM_DCACHE_SYNC_INT_CLR_V << EXTMEM_DCACHE_SYNC_INT_CLR_S) -#define EXTMEM_DCACHE_SYNC_INT_CLR_V 0x00000001 -#define EXTMEM_DCACHE_SYNC_INT_CLR_S 5 - -/* EXTMEM_DCACHE_SYNC_INT_ENA : R/W; bitpos: [4]; default: 0; - * The bit is used to enable the interrupt by dcache sync done. - */ - -#define EXTMEM_DCACHE_SYNC_INT_ENA (BIT(4)) -#define EXTMEM_DCACHE_SYNC_INT_ENA_M (EXTMEM_DCACHE_SYNC_INT_ENA_V << EXTMEM_DCACHE_SYNC_INT_ENA_S) -#define EXTMEM_DCACHE_SYNC_INT_ENA_V 0x00000001 -#define EXTMEM_DCACHE_SYNC_INT_ENA_S 4 - -/* EXTMEM_DCACHE_SYNC_INT_ST : RO; bitpos: [3]; default: 0; - * The bit is used to indicate the interrupt by dcache sync done. - */ - -#define EXTMEM_DCACHE_SYNC_INT_ST (BIT(3)) -#define EXTMEM_DCACHE_SYNC_INT_ST_M (EXTMEM_DCACHE_SYNC_INT_ST_V << EXTMEM_DCACHE_SYNC_INT_ST_S) -#define EXTMEM_DCACHE_SYNC_INT_ST_V 0x00000001 -#define EXTMEM_DCACHE_SYNC_INT_ST_S 3 - -/* EXTMEM_ICACHE_SYNC_INT_CLR : WOD; bitpos: [2]; default: 0; - * The bit is used to clear the interrupt by icache sync done. - */ - -#define EXTMEM_ICACHE_SYNC_INT_CLR (BIT(2)) -#define EXTMEM_ICACHE_SYNC_INT_CLR_M (EXTMEM_ICACHE_SYNC_INT_CLR_V << EXTMEM_ICACHE_SYNC_INT_CLR_S) -#define EXTMEM_ICACHE_SYNC_INT_CLR_V 0x00000001 -#define EXTMEM_ICACHE_SYNC_INT_CLR_S 2 - -/* EXTMEM_ICACHE_SYNC_INT_ENA : R/W; bitpos: [1]; default: 0; - * The bit is used to enable the interrupt by icache sync done. - */ - -#define EXTMEM_ICACHE_SYNC_INT_ENA (BIT(1)) -#define EXTMEM_ICACHE_SYNC_INT_ENA_M (EXTMEM_ICACHE_SYNC_INT_ENA_V << EXTMEM_ICACHE_SYNC_INT_ENA_S) -#define EXTMEM_ICACHE_SYNC_INT_ENA_V 0x00000001 -#define EXTMEM_ICACHE_SYNC_INT_ENA_S 1 - -/* EXTMEM_ICACHE_SYNC_INT_ST : RO; bitpos: [0]; default: 0; - * The bit is used to indicate the interrupt by icache sync done. - */ - -#define EXTMEM_ICACHE_SYNC_INT_ST (BIT(0)) -#define EXTMEM_ICACHE_SYNC_INT_ST_M (EXTMEM_ICACHE_SYNC_INT_ST_V << EXTMEM_ICACHE_SYNC_INT_ST_S) -#define EXTMEM_ICACHE_SYNC_INT_ST_V 0x00000001 -#define EXTMEM_ICACHE_SYNC_INT_ST_S 0 - -/* EXTMEM_CACHE_MMU_OWNER_REG register - * ******* Description *********** - */ - -#define EXTMEM_CACHE_MMU_OWNER_REG (DR_REG_EXTMEM_BASE + 0x148) - -/* EXTMEM_CACHE_MMU_OWNER : R/W; bitpos: [23:0]; default: 0; - * The bits are used to specify the owner of MMU.bit0: icache, bit1: dcache, - * bit2: dma, bit3: reserved. - */ - -#define EXTMEM_CACHE_MMU_OWNER 0x00ffffff -#define EXTMEM_CACHE_MMU_OWNER_M (EXTMEM_CACHE_MMU_OWNER_V << EXTMEM_CACHE_MMU_OWNER_S) -#define EXTMEM_CACHE_MMU_OWNER_V 0x00ffffff -#define EXTMEM_CACHE_MMU_OWNER_S 0 - -/* EXTMEM_CACHE_CONF_MISC_REG register - * ******* Description *********** - */ - -#define EXTMEM_CACHE_CONF_MISC_REG (DR_REG_EXTMEM_BASE + 0x14c) - -/* EXTMEM_CACHE_TRACE_ENA : R/W; bitpos: [2]; default: 1; - * The bit is used to enable cache trace function. - */ - -#define EXTMEM_CACHE_TRACE_ENA (BIT(2)) -#define EXTMEM_CACHE_TRACE_ENA_M (EXTMEM_CACHE_TRACE_ENA_V << EXTMEM_CACHE_TRACE_ENA_S) -#define EXTMEM_CACHE_TRACE_ENA_V 0x00000001 -#define EXTMEM_CACHE_TRACE_ENA_S 2 - -/* EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT : R/W; bitpos: [1]; default: 1; - * The bit is used to disable checking mmu entry fault by sync operation. - */ - -#define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT (BIT(1)) -#define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_M (EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_V << EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_S) -#define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_V 0x00000001 -#define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_S 1 - -/* EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT : R/W; bitpos: [0]; default: - * 1; - * The bit is used to disable checking mmu entry fault by preload operation. - */ - -#define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT (BIT(0)) -#define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_M (EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_V << EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_S) -#define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_V 0x00000001 -#define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_S 0 - -/* EXTMEM_DCACHE_FREEZE_REG register - * ******* Description *********** - */ - -#define EXTMEM_DCACHE_FREEZE_REG (DR_REG_EXTMEM_BASE + 0x150) - -/* EXTMEM_DCACHE_FREEZE_DONE : RO; bitpos: [2]; default: 1; - * The bit is used to indicate dcache freeze success - */ - -#define EXTMEM_DCACHE_FREEZE_DONE (BIT(2)) -#define EXTMEM_DCACHE_FREEZE_DONE_M (EXTMEM_DCACHE_FREEZE_DONE_V << EXTMEM_DCACHE_FREEZE_DONE_S) -#define EXTMEM_DCACHE_FREEZE_DONE_V 0x00000001 -#define EXTMEM_DCACHE_FREEZE_DONE_S 2 - -/* EXTMEM_DCACHE_FREEZE_MODE : R/W; bitpos: [1]; default: 0; - * The bit is used to configure freeze mode, 0: assert busy if CPU miss 1: - * assert hit if CPU miss - */ - -#define EXTMEM_DCACHE_FREEZE_MODE (BIT(1)) -#define EXTMEM_DCACHE_FREEZE_MODE_M (EXTMEM_DCACHE_FREEZE_MODE_V << EXTMEM_DCACHE_FREEZE_MODE_S) -#define EXTMEM_DCACHE_FREEZE_MODE_V 0x00000001 -#define EXTMEM_DCACHE_FREEZE_MODE_S 1 - -/* EXTMEM_DCACHE_FREEZE_ENA : R/W; bitpos: [0]; default: 0; - * The bit is used to enable dcache freeze mode - */ - -#define EXTMEM_DCACHE_FREEZE_ENA (BIT(0)) -#define EXTMEM_DCACHE_FREEZE_ENA_M (EXTMEM_DCACHE_FREEZE_ENA_V << EXTMEM_DCACHE_FREEZE_ENA_S) -#define EXTMEM_DCACHE_FREEZE_ENA_V 0x00000001 -#define EXTMEM_DCACHE_FREEZE_ENA_S 0 - -/* EXTMEM_ICACHE_FREEZE_REG register - * ******* Description *********** - */ - -#define EXTMEM_ICACHE_FREEZE_REG (DR_REG_EXTMEM_BASE + 0x154) - -/* EXTMEM_ICACHE_FREEZE_DONE : RO; bitpos: [2]; default: 1; - * The bit is used to indicate icache freeze success - */ - -#define EXTMEM_ICACHE_FREEZE_DONE (BIT(2)) -#define EXTMEM_ICACHE_FREEZE_DONE_M (EXTMEM_ICACHE_FREEZE_DONE_V << EXTMEM_ICACHE_FREEZE_DONE_S) -#define EXTMEM_ICACHE_FREEZE_DONE_V 0x00000001 -#define EXTMEM_ICACHE_FREEZE_DONE_S 2 - -/* EXTMEM_ICACHE_FREEZE_MODE : R/W; bitpos: [1]; default: 0; - * The bit is used to configure freeze mode, 0: assert busy if CPU miss 1: - * assert hit if CPU miss - */ - -#define EXTMEM_ICACHE_FREEZE_MODE (BIT(1)) -#define EXTMEM_ICACHE_FREEZE_MODE_M (EXTMEM_ICACHE_FREEZE_MODE_V << EXTMEM_ICACHE_FREEZE_MODE_S) -#define EXTMEM_ICACHE_FREEZE_MODE_V 0x00000001 -#define EXTMEM_ICACHE_FREEZE_MODE_S 1 - -/* EXTMEM_ICACHE_FREEZE_ENA : R/W; bitpos: [0]; default: 0; - * The bit is used to enable icache freeze mode - */ - -#define EXTMEM_ICACHE_FREEZE_ENA (BIT(0)) -#define EXTMEM_ICACHE_FREEZE_ENA_M (EXTMEM_ICACHE_FREEZE_ENA_V << EXTMEM_ICACHE_FREEZE_ENA_S) -#define EXTMEM_ICACHE_FREEZE_ENA_V 0x00000001 -#define EXTMEM_ICACHE_FREEZE_ENA_S 0 - -/* EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_REG register - * ******* Description *********** - */ - -#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_REG (DR_REG_EXTMEM_BASE + 0x158) - -/* EXTMEM_ICACHE_ATOMIC_OPERATE_ENA : R/W; bitpos: [0]; default: 1; - * The bit is used to activate icache atomic operation protection. In this - * case, sync/lock operation can not interrupt miss-work. This feature does - * not work during invalidateAll operation. - */ - -#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA (BIT(0)) -#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_M (EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_V << EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_S) -#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_V 0x00000001 -#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_S 0 - -/* EXTMEM_DCACHE_ATOMIC_OPERATE_ENA_REG register - * ******* Description *********** - */ - -#define EXTMEM_DCACHE_ATOMIC_OPERATE_ENA_REG (DR_REG_EXTMEM_BASE + 0x15c) - -/* EXTMEM_DCACHE_ATOMIC_OPERATE_ENA : R/W; bitpos: [0]; default: 1; - * The bit is used to activate dcache atomic operation protection. In this - * case, sync/lock/occupy operation can not interrupt miss-work. This - * feature does not work during invalidateAll operation. - */ - -#define EXTMEM_DCACHE_ATOMIC_OPERATE_ENA (BIT(0)) -#define EXTMEM_DCACHE_ATOMIC_OPERATE_ENA_M (EXTMEM_DCACHE_ATOMIC_OPERATE_ENA_V << EXTMEM_DCACHE_ATOMIC_OPERATE_ENA_S) -#define EXTMEM_DCACHE_ATOMIC_OPERATE_ENA_V 0x00000001 -#define EXTMEM_DCACHE_ATOMIC_OPERATE_ENA_S 0 - -/* EXTMEM_CACHE_REQUEST_REG register - * ******* Description *********** - */ - -#define EXTMEM_CACHE_REQUEST_REG (DR_REG_EXTMEM_BASE + 0x160) - -/* EXTMEM_CACHE_REQUEST_BYPASS : R/W; bitpos: [0]; default: 0; - * The bit is used to disable request recording which could cause - * performance issue - */ - -#define EXTMEM_CACHE_REQUEST_BYPASS (BIT(0)) -#define EXTMEM_CACHE_REQUEST_BYPASS_M (EXTMEM_CACHE_REQUEST_BYPASS_V << EXTMEM_CACHE_REQUEST_BYPASS_S) -#define EXTMEM_CACHE_REQUEST_BYPASS_V 0x00000001 -#define EXTMEM_CACHE_REQUEST_BYPASS_S 0 - -/* EXTMEM_CLOCK_GATE_REG register - * ******* Description *********** - */ - -#define EXTMEM_CLOCK_GATE_REG (DR_REG_EXTMEM_BASE + 0x164) - -/* EXTMEM_CLK_EN : R/W; bitpos: [0]; default: 1; - * Reserved - */ - -#define EXTMEM_CLK_EN (BIT(0)) -#define EXTMEM_CLK_EN_M (EXTMEM_CLK_EN_V << EXTMEM_CLK_EN_S) -#define EXTMEM_CLK_EN_V 0x00000001 -#define EXTMEM_CLK_EN_S 0 - -/* EXTMEM_CACHE_TAG_OBJECT_CTRL_REG register - * ******* Description *********** - */ - -#define EXTMEM_CACHE_TAG_OBJECT_CTRL_REG (DR_REG_EXTMEM_BASE + 0x180) - -/* EXTMEM_DCACHE_TAG_OBJECT : R/W; bitpos: [1]; default: 0; - * Set this bit to set dcache tag memory as object. This bit should be - * onehot with the others fields inside this register. - */ - -#define EXTMEM_DCACHE_TAG_OBJECT (BIT(1)) -#define EXTMEM_DCACHE_TAG_OBJECT_M (EXTMEM_DCACHE_TAG_OBJECT_V << EXTMEM_DCACHE_TAG_OBJECT_S) -#define EXTMEM_DCACHE_TAG_OBJECT_V 0x00000001 -#define EXTMEM_DCACHE_TAG_OBJECT_S 1 - -/* EXTMEM_ICACHE_TAG_OBJECT : R/W; bitpos: [0]; default: 0; - * Set this bit to set icache tag memory as object. This bit should be - * onehot with the others fields inside this register. - */ - -#define EXTMEM_ICACHE_TAG_OBJECT (BIT(0)) -#define EXTMEM_ICACHE_TAG_OBJECT_M (EXTMEM_ICACHE_TAG_OBJECT_V << EXTMEM_ICACHE_TAG_OBJECT_S) -#define EXTMEM_ICACHE_TAG_OBJECT_V 0x00000001 -#define EXTMEM_ICACHE_TAG_OBJECT_S 0 - -/* EXTMEM_CACHE_TAG_WAY_OBJECT_REG register - * ******* Description *********** - */ - -#define EXTMEM_CACHE_TAG_WAY_OBJECT_REG (DR_REG_EXTMEM_BASE + 0x184) - -/* EXTMEM_CACHE_TAG_WAY_OBJECT : R/W; bitpos: [2:0]; default: 0; - * Set this bits to select which way of the tag-object will be accessed. 0: - * way0, 1: way1, 2: way2, 3: way3, .., 7: way7. - */ - -#define EXTMEM_CACHE_TAG_WAY_OBJECT 0x00000007 -#define EXTMEM_CACHE_TAG_WAY_OBJECT_M (EXTMEM_CACHE_TAG_WAY_OBJECT_V << EXTMEM_CACHE_TAG_WAY_OBJECT_S) -#define EXTMEM_CACHE_TAG_WAY_OBJECT_V 0x00000007 -#define EXTMEM_CACHE_TAG_WAY_OBJECT_S 0 - -/* EXTMEM_CACHE_VADDR_REG register - * ******* Description *********** - */ - -#define EXTMEM_CACHE_VADDR_REG (DR_REG_EXTMEM_BASE + 0x188) - -/* EXTMEM_CACHE_VADDR : R/W; bitpos: [31:0]; default: 0; - * Those bits stores the virtual address which will decide where inside the - * specified tag memory object will be accessed. - */ - -#define EXTMEM_CACHE_VADDR 0xffffffff -#define EXTMEM_CACHE_VADDR_M (EXTMEM_CACHE_VADDR_V << EXTMEM_CACHE_VADDR_S) -#define EXTMEM_CACHE_VADDR_V 0xffffffff -#define EXTMEM_CACHE_VADDR_S 0 - -/* EXTMEM_CACHE_TAG_CONTENT_REG register - * ******* Description *********** - */ - -#define EXTMEM_CACHE_TAG_CONTENT_REG (DR_REG_EXTMEM_BASE + 0x18c) - -/* EXTMEM_CACHE_TAG_CONTENT : R/W; bitpos: [31:0]; default: 0; - * This is a constant place where we can write data to or read data from the - * tag memory on the specified cache. - */ - -#define EXTMEM_CACHE_TAG_CONTENT 0xffffffff -#define EXTMEM_CACHE_TAG_CONTENT_M (EXTMEM_CACHE_TAG_CONTENT_V << EXTMEM_CACHE_TAG_CONTENT_S) -#define EXTMEM_CACHE_TAG_CONTENT_V 0xffffffff -#define EXTMEM_CACHE_TAG_CONTENT_S 0 - -/* EXTMEM_DATE_REG register - * ******* Description *********** - */ - -#define EXTMEM_DATE_REG (DR_REG_EXTMEM_BASE + 0x3fc) - -/* EXTMEM_DATE : R/W; bitpos: [27:0]; default: 33628944; - * version information. - */ - -#define EXTMEM_DATE 0x0fffffff -#define EXTMEM_DATE_M (EXTMEM_DATE_V << EXTMEM_DATE_S) -#define EXTMEM_DATE_V 0x0fffffff -#define EXTMEM_DATE_S 0 - -#endif /* __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_EXTMEM_H */ diff --git a/arch/xtensa/src/esp32s3/hardware/esp32s3_soc.h b/arch/xtensa/src/esp32s3/hardware/esp32s3_soc.h index f6337da0eca8c..9448a752c5022 100644 --- a/arch/xtensa/src/esp32s3/hardware/esp32s3_soc.h +++ b/arch/xtensa/src/esp32s3/hardware/esp32s3_soc.h @@ -30,268 +30,25 @@ #include #endif -#include "xtensa_attr.h" #include +#include "soc/soc.h" +#include "esp_attr.h" + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -/* Register Bits */ - -#define BIT31 0x80000000 -#define BIT30 0x40000000 -#define BIT29 0x20000000 -#define BIT28 0x10000000 -#define BIT27 0x08000000 -#define BIT26 0x04000000 -#define BIT25 0x02000000 -#define BIT24 0x01000000 -#define BIT23 0x00800000 -#define BIT22 0x00400000 -#define BIT21 0x00200000 -#define BIT20 0x00100000 -#define BIT19 0x00080000 -#define BIT18 0x00040000 -#define BIT17 0x00020000 -#define BIT16 0x00010000 -#define BIT15 0x00008000 -#define BIT14 0x00004000 -#define BIT13 0x00002000 -#define BIT12 0x00001000 -#define BIT11 0x00000800 -#define BIT10 0x00000400 -#define BIT9 0x00000200 -#define BIT8 0x00000100 -#define BIT7 0x00000080 -#define BIT6 0x00000040 -#define BIT5 0x00000020 -#define BIT4 0x00000010 -#define BIT3 0x00000008 -#define BIT2 0x00000004 -#define BIT1 0x00000002 -#define BIT0 0x00000001 - -#define PRO_CPU_NUM (0) -#define APP_CPU_NUM (1) - -#define PRO_CPUID (0xcdcd) -#define APP_CPUID (0xabab) - -/* Largest span of contiguous memory (DRAM or IRAM) in the address space */ - -#define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW) - -#define DR_REG_UART_BASE 0x60000000 -#define DR_REG_SPI1_BASE 0x60002000 -#define DR_REG_SPI0_BASE 0x60003000 -#define DR_REG_GPIO_BASE 0x60004000 -#define DR_REG_GPIO_SD_BASE 0x60004f00 - -#define DR_REG_FE2_BASE 0x60005000 -#define DR_REG_FE_BASE 0x60006000 - -#define DR_REG_EFUSE_BASE 0x60007000 -#define DR_REG_RTCCNTL_BASE 0x60008000 -#define DR_REG_RTCIO_BASE 0x60008400 -#define DR_REG_SENS_BASE 0x60008800 -#define DR_REG_RTC_I2C_BASE 0x60008C00 -#define DR_REG_IO_MUX_BASE 0x60009000 - -#define DR_REG_HINF_BASE 0x6000B000 -#define DR_REG_UHCI1_BASE 0x6000C000 - -#define DR_REG_I2S_BASE 0x6000F000 -#define DR_REG_UART1_BASE 0x60010000 - -#define DR_REG_BT_BASE 0x60011000 - -#define DR_REG_I2C_EXT_BASE 0x60013000 -#define DR_REG_UHCI0_BASE 0x60014000 - -#define DR_REG_SLCHOST_BASE 0x60015000 - -#define DR_REG_RMT_BASE 0x60016000 -#define DR_REG_PCNT_BASE 0x60017000 - -#define DR_REG_SLC_BASE 0x60018000 - -#define DR_REG_LEDC_BASE 0x60019000 - -#define DR_REG_NRX_BASE 0x6001CC00 -#define DR_REG_BB_BASE 0x6001D000 - -#define DR_REG_PWM0_BASE 0x6001E000 -#define DR_REG_TIMERGROUP0_BASE 0x6001F000 -#define DR_REG_TIMERGROUP1_BASE 0x60020000 -#define DR_REG_RTC_SLOWMEM_BASE 0x60021000 -#define DR_REG_SYSTIMER_BASE 0x60023000 -#define DR_REG_SPI2_BASE 0x60024000 -#define DR_REG_SPI3_BASE 0x60025000 -#define DR_REG_SYSCON_BASE 0x60026000 -#define DR_REG_APB_CTRL_BASE 0x60026000 /* Old name for SYSCON, to be removed */ -#define DR_REG_I2C1_EXT_BASE 0x60027000 -#define DR_REG_SDMMC_BASE 0x60028000 - #define REG_SPI_BASE(i) (DR_REG_SPI2_BASE + (((i) > 3) ? ((((i) - 2) * 0x1000) + 0x10000) : (((i) - 2) * 0x1000))) -#define DR_REG_PERI_BACKUP_BASE 0x6002A000 - -#define DR_REG_TWAI_BASE 0x6002B000 -#define DR_REG_PWM1_BASE 0x6002C000 -#define DR_REG_I2S1_BASE 0x6002D000 -#define DR_REG_UART2_BASE 0x6002E000 - -#define DR_REG_USB_DEVICE_BASE 0x60038000 -#define DR_REG_USB_WRAP_BASE 0x60039000 -#define DR_REG_AES_BASE 0x6003A000 -#define DR_REG_SHA_BASE 0x6003B000 -#define DR_REG_RSA_BASE 0x6003C000 -#define DR_REG_HMAC_BASE 0x6003E000 -#define DR_REG_DIGITAL_SIGNATURE_BASE 0x6003D000 -#define DR_REG_GDMA_BASE 0x6003F000 -#define DR_REG_APB_SARADC_BASE 0x60040000 -#define DR_REG_LCD_CAM_BASE 0x60041000 - #define DR_REG_USB_BASE 0x60080000 -#define DR_REG_SYSTEM_BASE 0x600C0000 -#define DR_REG_SENSITIVE_BASE 0x600C1000 -#define DR_REG_INTERRUPT_BASE 0x600C2000 - -/* Cache configuration */ - -#define DR_REG_EXTMEM_BASE 0x600C4000 -#define DR_REG_MMU_TABLE 0x600C5000 -#define DR_REG_ITAG_TABLE 0x600C6000 -#define DR_REG_DTAG_TABLE 0x600C8000 - -#define DR_REG_EXT_MEM_ENC 0x600CC000 - #define DR_REG_ASSIST_DEBUG_BASE 0x600CE000 #define DR_REG_WORLD_CNTL_BASE 0x600D0000 #define DR_REG_DPORT_END 0x600D3FFC -#define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE - (i) * 0x8000) -#define REG_UART_BASE( i ) (DR_REG_UART_BASE + (i) * 0x10000 + ((i) > 1 ? 0xe000 : 0)) -#define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000 + ((i) > 1 ? 0xe000 : 0 )) -#define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0) -#define REG_I2S_BASE( i ) (DR_REG_I2S_BASE + (i) * 0x1E000) -#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000) -#define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000) -#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000) - -/* Registers Operation */ - -#define ETS_UNCACHED_ADDR(addr) (addr) -#define ETS_CACHED_ADDR(addr) (addr) - #ifndef __ASSEMBLY__ -/* Write value to register */ - -#define REG_WRITE(_r, _v) (*(volatile uint32_t *)(_r)) = (_v) - -/* Read value from register */ - -#define REG_READ(_r) (*(volatile uint32_t *)(_r)) - -/* Get bit or get bits from register */ - -#define REG_GET_BIT(_r, _b) (*(volatile uint32_t *)(_r) & (_b)) - -/* Set bit or set bits to register */ - -#define REG_SET_BIT(_r, _b) (*(volatile uint32_t *)(_r) |= (_b)) - -/* Clear bit or clear bits of register */ - -#define REG_CLR_BIT(_r, _b) (*(volatile uint32_t *)(_r) &= ~(_b)) - -/* Set bits of register controlled by mask */ - -#define REG_SET_BITS(_r, _b, _m) (*(volatile uint32_t *)(_r) = (*(volatile uint32_t *)(_r) & ~(_m)) | ((_b) & (_m))) - -/* Get field from register, - * used when _f is not left shifted by _f##_S - */ - -#define REG_GET_FIELD(addr, field) ((getreg32(addr) >> (field##_S)) & (field##_V)) - -/* Set field to register, - * used when _f is not left shifted by _f##_S - */ - -#define REG_SET_FIELD(addr, field, val) (modifyreg32((addr), (field##_M), (((uint32_t) val) & (field##_V)) << (field##_S))) - -/* Get field value from a variable, - * used when _f is not left shifted by _f##_S - */ - -#define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f)) - -/* Get field value from a variable, - * used when _f is left shifted by _f##_S - */ - -#define VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S)) - -/* Set field value to a variable, - * used when _f is not left shifted by _f##_S - */ - -#define VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S)))) - -/* Set field value to a variable, - * used when _f is left shifted by _f##_S - */ - -#define VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S)))) - -/* Generate a value from a field value, - * used when _f is not left shifted by _f##_S - */ - -#define FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S) - -/* Generate a value from a field value, - * used when _f is left shifted by _f##_S - */ - -#define FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f)) - -/* Read value from register */ - -#define READ_PERI_REG(addr) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) - -/* Write value to register */ - -#define WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val) - -/* Clear bits of register controlled by mask */ - -#define CLEAR_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))) - -/* Set bits of register controlled by mask */ - -#define SET_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))) - -/* Get bits of register controlled by mask */ - -#define GET_PERI_REG_MASK(reg, mask) (READ_PERI_REG(reg) & (mask)) - -/* Get bits of register controlled by highest bit and lowest bit */ - -#define GET_PERI_REG_BITS(reg, hipos,lowpos) ((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)) - -/* Set bits of register controlled by mask and shift */ - -#define SET_PERI_REG_BITS(reg,bit_map,value,shift) (WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)) )) - -/* Get field of register */ - -#define GET_PERI_REG_BITS2(reg, mask,shift) ((READ_PERI_REG(reg)>>(shift))&(mask)) - /* Extract the field from the register and shift it to avoid wrong reading */ #define REG_MASK(_reg, _field) ((_reg & (_field##_M)) >> (_field##_S)) @@ -304,129 +61,7 @@ /* Peripheral Clock */ -#define APB_CLK_FREQ_ROM (40*1000000) -#define CPU_CLK_FREQ_ROM (40*1000000) -#define UART_CLK_FREQ_ROM (40*1000000) -#define EFUSE_CLK_FREQ_ROM (20*1000000) -#define CPU_CLK_FREQ APB_CLK_FREQ -#define APB_CLK_FREQ (80*1000000) -#define REF_CLK_FREQ (1000000) #define RTC_CLK_FREQ (20*1000000) -#define XTAL_CLK_FREQ (40*1000000) -#define UART_CLK_FREQ APB_CLK_FREQ -#define WDT_CLK_FREQ APB_CLK_FREQ -#define TIMER_CLK_FREQ (80000000>>4) -#define SPI_CLK_DIV 4 -#define TICKS_PER_US_ROM 40 -#define GPIO_MATRIX_DELAY_NS 0 - -/* Overall memory map */ - -#define SOC_DROM_LOW 0x3C000000 -#define SOC_DROM_HIGH 0x3D000000 -#define SOC_IROM_LOW 0x42000000 -#define SOC_IROM_HIGH 0x44000000 -#define SOC_IRAM_LOW 0x40370000 -#define SOC_IRAM_HIGH 0x403E0000 -#define SOC_DRAM_LOW 0x3FC88000 -#define SOC_DRAM_HIGH 0x3FD00000 - -#define SOC_RTC_IRAM_LOW 0x600FE000 -#define SOC_RTC_IRAM_HIGH 0x60100000 -#define SOC_RTC_DRAM_LOW 0x600FE000 -#define SOC_RTC_DRAM_HIGH 0x60100000 - -#define SOC_RTC_DATA_LOW 0x50000000 -#define SOC_RTC_DATA_HIGH 0x50002000 - -#define SOC_EXTRAM_DATA_LOW 0x3C000000 -#define SOC_EXTRAM_DATA_HIGH 0x3E000000 -#define SOC_IROM_MASK_LOW 0x40000000 -#define SOC_IROM_MASK_HIGH 0x4001A100 - -#define SOC_EXTRAM_DATA_SIZE (SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW) - -/* First and last words of the D/IRAM region, for both the DRAM address - * as well as the IRAM alias. - */ - -#define SOC_DIRAM_IRAM_LOW 0x40378000 -#define SOC_DIRAM_IRAM_HIGH 0x403E0000 -#define SOC_DIRAM_DRAM_LOW 0x3FC88000 -#define SOC_DIRAM_DRAM_HIGH 0x3FCF0000 - -/* Region of memory accessible via DMA in internal memory. - * See esp_ptr_dma_capable(). - */ - -#define SOC_DMA_LOW 0x3FC88000 -#define SOC_DMA_HIGH 0x3FD00000 - -/* Region of memory accessible via DMA in external memory. - * See esp_ptr_dma_ext_capable(). - */ - -#define SOC_DMA_EXT_LOW SOC_EXTRAM_DATA_LOW -#define SOC_DMA_EXT_HIGH SOC_EXTRAM_DATA_HIGH - -/* Region of memory that is byte-accessible. - * See esp_ptr_byte_accessible(). - */ - -#define SOC_BYTE_ACCESSIBLE_LOW 0x3FC88000 -#define SOC_BYTE_ACCESSIBLE_HIGH 0x3FD00000 - -/* Region of memory that is internal, as in on the same silicon die as the - * ESP32 CPUs (excluding RTC data region, that's checked separately.) - * See esp_ptr_internal(). - */ - -#define SOC_MEM_INTERNAL_LOW 0x3FC88000 -#define SOC_MEM_INTERNAL_HIGH 0x403E2000 - -/* Start (highest address) of ROM boot stack, only relevant during - * early boot - */ - -#define SOC_ROM_STACK_START 0x3fcebf10 - -/* Interrupt cpu using table, Please see the core-isa.h */ - -/**************************************************************************** - * Intr num Level Type PRO CPU usage APP CPU usage - * 0 1 extern level WMAC Reserved - * 1 1 extern level BT/BLE Host HCI DMA BT/BLE Host HCI DMA - * 2 1 extern level - * 3 1 extern level - * 4 1 extern level WBB - * 5 1 extern level BT/BLE Controller BT/BLE Controller - * 6 1 timer FreeRTOS Tick(L1) FreeRTOS Tick(L1) - * 7 1 software BT/BLE VHCI BT/BLE VHCI - * 8 1 extern level BT/BLE BB(RX/TX) BT/BLE BB(RX/TX) - * 9 1 extern level - * 10 1 extern edge - * 11 3 profiling - * 12 1 extern level - * 13 1 extern level - * 14 7 nmi Reserved Reserved - * 15 3 timer FreeRTOS Tick(L3) FreeRTOS Tick(L3) - * 16 5 timer - * 17 1 extern level - * 18 1 extern level - * 19 2 extern level - * 20 2 extern level - * 21 2 extern level - * 22 3 extern edge - * 23 3 extern level - * 24 4 extern level TG1_WDT - * 25 4 extern level CACHEERR - * 26 5 extern level - * 27 3 extern level Reserved Reserved - * 28 4 extern edge DPORT ACCESS DPORT ACCESS - * 29 3 software Reserved Reserved - * 30 4 extern edge Reserved Reserved - * 31 5 extern level - ****************************************************************************/ /* Core voltage needs to be increased in two cases: * 1. running at 240 MHz @@ -442,37 +77,6 @@ #define DIG_DBIAS_XTAL RTC_CNTL_DBIAS_1V10 #define DIG_DBIAS_2M RTC_CNTL_DBIAS_1V00 -/* CPU0 Interrupt number reserved, not touch this. */ - -#define ETS_WMAC_INUM 0 -#define ETS_BT_HOST_INUM 1 -#define ETS_WBB_INUM 4 -#define ETS_TG0_T1_INUM 10 /* use edge interrupt*/ -#define ETS_FRC1_INUM 22 -#define ETS_T1_WDT_INUM 24 -#define ETS_CACHEERR_INUM 25 -#define ETS_DPORT_INUM 28 - -/* CPU0 Interrupt number used in ROM, should be cancelled in SDK */ - -#define ETS_SLC_INUM 1 -#define ETS_UART0_INUM 5 -#define ETS_UART1_INUM 5 -#define ETS_SPI2_INUM 1 - -/* CPU0 Interrupt number used in ROM code only when module init function - * called, should pay attention here. - */ - -#define ETS_FRC_TIMER2_INUM 10 /* use edge*/ -#define ETS_GPIO_INUM 4 - -/* Other interrupt number should be managed by the user */ - -/* Invalid interrupt for number interrupt matrix */ - -#define ETS_INVALID_INUM 6 - #define MHZ (1000000) #define RTC_PLL_FREQ_320M 320 #define RTC_PLL_FREQ_480M 480 diff --git a/arch/xtensa/src/esp32s3/hardware/esp32s3_spi_mem_reg.h b/arch/xtensa/src/esp32s3/hardware/esp32s3_spi_mem_reg.h deleted file mode 100644 index bb80bde437015..0000000000000 --- a/arch/xtensa/src/esp32s3/hardware/esp32s3_spi_mem_reg.h +++ /dev/null @@ -1,3586 +0,0 @@ -/**************************************************************************** - * arch/xtensa/src/esp32s3/hardware/esp32s3_spi_mem_reg.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_SPI_MEM_REG_H -#define __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_SPI_MEM_REG_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include "esp32s3_soc.h" - -#ifdef __cplusplus -extern "C" -{ -#endif - -#define SPI_MEM_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x0) - -/* SPI_MEM_FLASH_READ : R/W/SC ;bitpos:[31] ;default: 1'b0 ; */ - -/* Description: Read flash enable. Read flash operation will be triggered - * when the bit is set. The bit will be cleared once the operation done. - * 1: enable 0: disable. - */ - -#define SPI_MEM_FLASH_READ (BIT(31)) -#define SPI_MEM_FLASH_READ_M (BIT(31)) -#define SPI_MEM_FLASH_READ_V 0x1 -#define SPI_MEM_FLASH_READ_S 31 - -/* SPI_MEM_FLASH_WREN : R/W/SC ;bitpos:[30] ;default: 1'b0 ; */ - -/* Description: Write flash enable. Write enable command will be sent when - * the bit is set. The bit will be cleared once the operation done. - * 1: enable - * 0: disable. - */ - -#define SPI_MEM_FLASH_WREN (BIT(30)) -#define SPI_MEM_FLASH_WREN_M (BIT(30)) -#define SPI_MEM_FLASH_WREN_V 0x1 -#define SPI_MEM_FLASH_WREN_S 30 - -/* SPI_MEM_FLASH_WRDI : R/W/SC ;bitpos:[29] ;default: 1'b0 ; */ - -/* Description: Write flash disable. Write disable command will be sent when - * the bit is set. The bit will be cleared once the operation done. 1: enable - * 0: disable. - */ - -#define SPI_MEM_FLASH_WRDI (BIT(29)) -#define SPI_MEM_FLASH_WRDI_M (BIT(29)) -#define SPI_MEM_FLASH_WRDI_V 0x1 -#define SPI_MEM_FLASH_WRDI_S 29 - -/* SPI_MEM_FLASH_RDID : R/W/SC ;bitpos:[28] ;default: 1'b0 ; */ - -/* Description: Read JEDEC ID . Read ID command will be sent when the bit is - * set. The bit will be cleared once the operation done. - * 1: enable - * 0: disable. - */ - -#define SPI_MEM_FLASH_RDID (BIT(28)) -#define SPI_MEM_FLASH_RDID_M (BIT(28)) -#define SPI_MEM_FLASH_RDID_V 0x1 -#define SPI_MEM_FLASH_RDID_S 28 - -/* SPI_MEM_FLASH_RDSR : R/W/SC ;bitpos:[27] ;default: 1'b0 ; */ - -/* Description: Read status register-1. Read status operation will be - * triggered when the bit is set. The bit will be cleared once the operation - * done.1: enable 0: disable. - */ - -#define SPI_MEM_FLASH_RDSR (BIT(27)) -#define SPI_MEM_FLASH_RDSR_M (BIT(27)) -#define SPI_MEM_FLASH_RDSR_V 0x1 -#define SPI_MEM_FLASH_RDSR_S 27 - -/* SPI_MEM_FLASH_WRSR : R/W/SC ;bitpos:[26] ;default: 1'b0 ; */ - -/* Description: Write status register enable. Write status operation will - * be triggered when the bit is set. The bit will be cleared once the - * operation done. - * 1: enable - * 0:disable. - */ - -#define SPI_MEM_FLASH_WRSR (BIT(26)) -#define SPI_MEM_FLASH_WRSR_M (BIT(26)) -#define SPI_MEM_FLASH_WRSR_V 0x1 -#define SPI_MEM_FLASH_WRSR_S 26 - -/* SPI_MEM_FLASH_PP : R/W/SC ;bitpos:[25] ;default: 1'b0 ; */ - -/* Description: Page program enable(1 byte ~64 bytes data to be programmed). - * Page program operation will be triggered when the bit is set. The bit - * will be cleared once the operation done. - * 1: enable - * 0: disable. - */ - -#define SPI_MEM_FLASH_PP (BIT(25)) -#define SPI_MEM_FLASH_PP_M (BIT(25)) -#define SPI_MEM_FLASH_PP_V 0x1 -#define SPI_MEM_FLASH_PP_S 25 - -/* SPI_MEM_FLASH_SE : R/W/SC ;bitpos:[24] ;default: 1'b0 ; */ - -/* Description: Sector erase enable(4KB). Sector erase operation will be - * triggered when the bit is set. The bit will be cleared once the operation - * done.1: enable 0: disable. - */ - -#define SPI_MEM_FLASH_SE (BIT(24)) -#define SPI_MEM_FLASH_SE_M (BIT(24)) -#define SPI_MEM_FLASH_SE_V 0x1 -#define SPI_MEM_FLASH_SE_S 24 - -/* SPI_MEM_FLASH_BE : R/W/SC ;bitpos:[23] ;default: 1'b0 ; */ - -/* Description: Block erase enable(32KB) . Block erase operation will be - * triggered when the bit is set. The bit will be cleared once the operation - * done. - * 1: enable - * 0: disable. - */ - -#define SPI_MEM_FLASH_BE (BIT(23)) -#define SPI_MEM_FLASH_BE_M (BIT(23)) -#define SPI_MEM_FLASH_BE_V 0x1 -#define SPI_MEM_FLASH_BE_S 23 - -/* SPI_MEM_FLASH_CE : R/W/SC ;bitpos:[22] ;default: 1'b0 ; */ - -/* Description: Chip erase enable. Chip erase operation will be triggered - * when the bit is set. The bit will be cleared once the operation done. - * 1: enable - * 0: disable. - */ - -#define SPI_MEM_FLASH_CE (BIT(22)) -#define SPI_MEM_FLASH_CE_M (BIT(22)) -#define SPI_MEM_FLASH_CE_V 0x1 -#define SPI_MEM_FLASH_CE_S 22 - -/* SPI_MEM_FLASH_DP : R/W/SC ;bitpos:[21] ;default: 1'b0 ; */ - -/* Description: Drive Flash into power down. An operation will be triggered - * when the bit is set. The bit will be cleared once the operation done.1: - * enable 0: disable. - */ - -#define SPI_MEM_FLASH_DP (BIT(21)) -#define SPI_MEM_FLASH_DP_M (BIT(21)) -#define SPI_MEM_FLASH_DP_V 0x1 -#define SPI_MEM_FLASH_DP_S 21 - -/* SPI_MEM_FLASH_RES : R/W/SC ;bitpos:[20] ;default: 1'b0 ; */ - -/* Description: This bit combined with SPI_MEM_RESANDRES bit releases Flash - * from the power-down state or high performance mode and obtains the devices - * ID. The bit will be cleared once the operation done.1: enable 0: disable. - */ - -#define SPI_MEM_FLASH_RES (BIT(20)) -#define SPI_MEM_FLASH_RES_M (BIT(20)) -#define SPI_MEM_FLASH_RES_V 0x1 -#define SPI_MEM_FLASH_RES_S 20 - -/* SPI_MEM_FLASH_HPM : R/W/SC ;bitpos:[19] ;default: 1'b0 ; */ - -/* Description: Drive Flash into high performance mode. The bit will be - * cleared once the operation done.1: enable 0: disable. - */ - -#define SPI_MEM_FLASH_HPM (BIT(19)) -#define SPI_MEM_FLASH_HPM_M (BIT(19)) -#define SPI_MEM_FLASH_HPM_V 0x1 -#define SPI_MEM_FLASH_HPM_S 19 - -/* SPI_MEM_USR : R/W/SC ;bitpos:[18] ;default: 1'b0 ; */ - -/* Description: User define command enable. An operation will be triggered - * when the bit is set. The bit will be cleared once the operation done.1: - * enable 0: disable. - */ - -#define SPI_MEM_USR (BIT(18)) -#define SPI_MEM_USR_M (BIT(18)) -#define SPI_MEM_USR_V 0x1 -#define SPI_MEM_USR_S 18 - -/* SPI_MEM_FLASH_PE : R/W/SC ;bitpos:[17] ;default: 1'b0 ; */ - -/* Description: In user mode, it is set to indicate that program/erase - * operation will be triggered. The bit is combined with SPI_MEM_USR bit. The - * bit will be cleared once the operation done.1: enable 0: disable. - */ - -#define SPI_MEM_FLASH_PE (BIT(17)) -#define SPI_MEM_FLASH_PE_M (BIT(17)) -#define SPI_MEM_FLASH_PE_V 0x1 -#define SPI_MEM_FLASH_PE_S 17 - -#define SPI_MEM_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x4) - -/* SPI_MEM_USR_ADDR_VALUE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ - -/* Description: In user mode, it is the memory address. other then the - * bit0-bit23 is the memory address, the bit24-bit31 are the byte length of a - * transfer. - */ - -#define SPI_MEM_USR_ADDR_VALUE 0xFFFFFFFF -#define SPI_MEM_USR_ADDR_VALUE_M ((SPI_MEM_USR_ADDR_VALUE_V)<<(SPI_MEM_USR_ADDR_VALUE_S)) -#define SPI_MEM_USR_ADDR_VALUE_V 0xFFFFFFFF -#define SPI_MEM_USR_ADDR_VALUE_S 0 - -#define SPI_MEM_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x8) - -/* SPI_MEM_FREAD_QIO : R/W ;bitpos:[24] ;default: 1'b0 ; */ - -/* Description: In hardware 0xEB read operation, ADDR phase and DIN phase - * apply 4 signals(4-bit-mode). - * 1: enable - * 0: disable. - */ - -#define SPI_MEM_FREAD_QIO (BIT(24)) -#define SPI_MEM_FREAD_QIO_M (BIT(24)) -#define SPI_MEM_FREAD_QIO_V 0x1 -#define SPI_MEM_FREAD_QIO_S 24 - -/* SPI_MEM_FREAD_DIO : R/W ;bitpos:[23] ;default: 1'b0 ; */ - -/* Description: In hardware 0xBB read operation, ADDR phase and DIN phase - * apply 2 signals(2-bit-mode). - * 1: enable - * 0: disable. - */ - -#define SPI_MEM_FREAD_DIO (BIT(23)) -#define SPI_MEM_FREAD_DIO_M (BIT(23)) -#define SPI_MEM_FREAD_DIO_V 0x1 -#define SPI_MEM_FREAD_DIO_S 23 - -/* SPI_MEM_WRSR_2B : R/W ;bitpos:[22] ;default: 1'b0 ; */ - -/* Description: Two bytes data will be written to status register when it is - * set. - * 1: enable - * 0: disable. - */ - -#define SPI_MEM_WRSR_2B (BIT(22)) -#define SPI_MEM_WRSR_2B_M (BIT(22)) -#define SPI_MEM_WRSR_2B_V 0x1 -#define SPI_MEM_WRSR_2B_S 22 - -/* SPI_MEM_WP_REG : R/W ;bitpos:[21] ;default: 1'b1 ; */ - -/* Description: Write protect signal output when SPI is idle. - * 1: output high, - * 0: output low. - */ - -#define SPI_MEM_WP_REG (BIT(21)) -#define SPI_MEM_WP_REG_M (BIT(21)) -#define SPI_MEM_WP_REG_V 0x1 -#define SPI_MEM_WP_REG_S 21 - -/* SPI_MEM_FREAD_QUAD : R/W ;bitpos:[20] ;default: 1'b0 ; */ - -/* Description: In hardware 0x6B read operation, DIN phase apply 4 - * signals(4-bit-mode). - * 1: enable - * 0: disable. - */ - -#define SPI_MEM_FREAD_QUAD (BIT(20)) -#define SPI_MEM_FREAD_QUAD_M (BIT(20)) -#define SPI_MEM_FREAD_QUAD_V 0x1 -#define SPI_MEM_FREAD_QUAD_S 20 - -/* SPI_MEM_D_POL : R/W ;bitpos:[19] ;default: 1'b1 ; */ - -/* Description: The bit is used to set MOSI line polarity, - * 1: high - * 0: low - */ - -#define SPI_MEM_D_POL (BIT(19)) -#define SPI_MEM_D_POL_M (BIT(19)) -#define SPI_MEM_D_POL_V 0x1 -#define SPI_MEM_D_POL_S 19 - -/* SPI_MEM_Q_POL : R/W ;bitpos:[18] ;default: 1'b1 ; */ - -/* Description: The bit is used to set MISO line polarity - * 1: high - * 0: low - */ - -#define SPI_MEM_Q_POL (BIT(18)) -#define SPI_MEM_Q_POL_M (BIT(18)) -#define SPI_MEM_Q_POL_V 0x1 -#define SPI_MEM_Q_POL_S 18 - -/* SPI_MEM_RESANDRES : R/W ;bitpos:[15] ;default: 1'b1 ; */ - -/* Description: The Device ID is read out to SPI_MEM_RD_STATUS register, this - * bit combine with spi_mem_flash_res bit. - * 1: enable - * 0: disable. - */ - -#define SPI_MEM_RESANDRES (BIT(15)) -#define SPI_MEM_RESANDRES_M (BIT(15)) -#define SPI_MEM_RESANDRES_V 0x1 -#define SPI_MEM_RESANDRES_S 15 - -/* SPI_MEM_FREAD_DUAL : R/W ;bitpos:[14] ;default: 1'b0 ; */ - -/* Description: In hardware 0x3B read operation, DIN phase apply 2 signals. - * 1: enable - * 0: disable - */ - -#define SPI_MEM_FREAD_DUAL (BIT(14)) -#define SPI_MEM_FREAD_DUAL_M (BIT(14)) -#define SPI_MEM_FREAD_DUAL_V 0x1 -#define SPI_MEM_FREAD_DUAL_S 14 - -/* SPI_MEM_FASTRD_MODE : R/W ;bitpos:[13] ;default: 1'b1 ; */ - -/* Description: This bit should be set when SPI_MEM_FREAD_QIO, - * SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QUAD or SPI_MEM_FREAD_DUAL is set. - */ - -#define SPI_MEM_FASTRD_MODE (BIT(13)) -#define SPI_MEM_FASTRD_MODE_M (BIT(13)) -#define SPI_MEM_FASTRD_MODE_V 0x1 -#define SPI_MEM_FASTRD_MODE_S 13 - -/* SPI_MEM_TX_CRC_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ - -/* Description: For SPI1, enable crc32 when writing encrypted data to flash. - * 1: enable - * 0:disable - */ - -#define SPI_MEM_TX_CRC_EN (BIT(11)) -#define SPI_MEM_TX_CRC_EN_M (BIT(11)) -#define SPI_MEM_TX_CRC_EN_V 0x1 -#define SPI_MEM_TX_CRC_EN_S 11 - -/* SPI_MEM_FCS_CRC_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ - -/* Description: For SPI1, initialize crc32 module before writing encrypted - * data to flash. Active low. - */ - -#define SPI_MEM_FCS_CRC_EN (BIT(10)) -#define SPI_MEM_FCS_CRC_EN_M (BIT(10)) -#define SPI_MEM_FCS_CRC_EN_V 0x1 -#define SPI_MEM_FCS_CRC_EN_S 10 - -/* SPI_MEM_FCMD_OCT : R/W ;bitpos:[9] ;default: 1'b0 ; */ - -/* Description: Set this bit to enable 8-bit-mode(8-bm) in CMD phase. */ - -#define SPI_MEM_FCMD_OCT (BIT(9)) -#define SPI_MEM_FCMD_OCT_M (BIT(9)) -#define SPI_MEM_FCMD_OCT_V 0x1 -#define SPI_MEM_FCMD_OCT_S 9 - -/* SPI_MEM_FCMD_QUAD : R/W ;bitpos:[8] ;default: 1'b0 ; */ - -/* Description: Set this bit to enable 4-bit-mode(4-bm) in CMD phase. */ - -#define SPI_MEM_FCMD_QUAD (BIT(8)) -#define SPI_MEM_FCMD_QUAD_M (BIT(8)) -#define SPI_MEM_FCMD_QUAD_V 0x1 -#define SPI_MEM_FCMD_QUAD_S 8 - -/* SPI_MEM_FCMD_DUAL : R/W ;bitpos:[7] ;default: 1'b0 ; */ - -/* Description: Set this bit to enable 2-bit-mode(2-bm) in CMD phase. */ - -#define SPI_MEM_FCMD_DUAL (BIT(7)) -#define SPI_MEM_FCMD_DUAL_M (BIT(7)) -#define SPI_MEM_FCMD_DUAL_V 0x1 -#define SPI_MEM_FCMD_DUAL_S 7 - -/* SPI_MEM_FADDR_OCT : R/W ;bitpos:[6] ;default: 1'b0 ; */ - -/* Description: Set this bit to enable 8-bit-mode(8-bm) in ADDR phase. */ - -#define SPI_MEM_FADDR_OCT (BIT(6)) -#define SPI_MEM_FADDR_OCT_M (BIT(6)) -#define SPI_MEM_FADDR_OCT_V 0x1 -#define SPI_MEM_FADDR_OCT_S 6 - -/* SPI_MEM_FDIN_OCT : R/W ;bitpos:[5] ;default: 1'b0 ; */ - -/* Description: Set this bit to enable 8-bit-mode(8-bm) in DIN phase. */ - -#define SPI_MEM_FDIN_OCT (BIT(5)) -#define SPI_MEM_FDIN_OCT_M (BIT(5)) -#define SPI_MEM_FDIN_OCT_V 0x1 -#define SPI_MEM_FDIN_OCT_S 5 - -/* SPI_MEM_FDOUT_OCT : R/W ;bitpos:[4] ;default: 1'b0 ; */ - -/* Description: Set this bit to enable 8-bit-mode(8-bm) in DOUT phase. */ - -#define SPI_MEM_FDOUT_OCT (BIT(4)) -#define SPI_MEM_FDOUT_OCT_M (BIT(4)) -#define SPI_MEM_FDOUT_OCT_V 0x1 -#define SPI_MEM_FDOUT_OCT_S 4 - -/* SPI_MEM_FDUMMY_OUT : R/W ;bitpos:[3] ;default: 1'b0 ; */ - -/* Description: In the DUMMY phase the signal level of SPI bus is output by - * the SPI0 controller. - */ - -#define SPI_MEM_FDUMMY_OUT (BIT(3)) -#define SPI_MEM_FDUMMY_OUT_M (BIT(3)) -#define SPI_MEM_FDUMMY_OUT_V 0x1 -#define SPI_MEM_FDUMMY_OUT_S 3 - -#define SPI_MEM_CTRL1_REG(i) (REG_SPI_MEM_BASE(i) + 0xC) - -/* SPI_MEM_RXFIFO_RST : R/W ;bitpos:[30] ;default: 1'b0 ; */ - -/* Description: SPI0 RX FIFO reset signal. Set this bit and clear it before - * SPI0 transfer starts. - */ - -#define SPI_MEM_RXFIFO_RST (BIT(30)) -#define SPI_MEM_RXFIFO_RST_M (BIT(30)) -#define SPI_MEM_RXFIFO_RST_V 0x1 -#define SPI_MEM_RXFIFO_RST_S 30 - -/* SPI_MEM_CS_HOLD_DLY_RES : R/W ;bitpos:[11:2] ;default: 10'h3ff ; */ - -/* Description: After RES/DP/HPM/PES/PER command is sent, SPI1 may waits - * (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or * 256) SPI_CLK cycles. - */ - -#define SPI_MEM_CS_HOLD_DLY_RES 0x000003FF -#define SPI_MEM_CS_HOLD_DLY_RES_M ((SPI_MEM_CS_HOLD_DLY_RES_V)<<(SPI_MEM_CS_HOLD_DLY_RES_S)) -#define SPI_MEM_CS_HOLD_DLY_RES_V 0x3FF -#define SPI_MEM_CS_HOLD_DLY_RES_S 2 - -/* SPI_MEM_CLK_MODE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ - -/* Description: SPI Bus clock (SPI_CLK) mode bits. 0: SPI Bus clock (SPI_CLK) - * is off when CS inactive - * 1: SPI_CLK is delayed one cycle after SPI_CS inactive - * 2: SPI_CLK isdelayed two cycles after SPI_CS inactive - * 3: SPI_CLK is always on. - */ - -#define SPI_MEM_CLK_MODE 0x00000003 -#define SPI_MEM_CLK_MODE_M ((SPI_MEM_CLK_MODE_V)<<(SPI_MEM_CLK_MODE_S)) -#define SPI_MEM_CLK_MODE_V 0x3 -#define SPI_MEM_CLK_MODE_S 0 - -#define SPI_MEM_CTRL2_REG(i) (REG_SPI_MEM_BASE(i) + 0x10) - -/* SPI_MEM_SYNC_RESET : R/W/SC ;bitpos:[31] ;default: 1'b0 ; */ - -/* Description: The FSM will be reset. */ - -#define SPI_MEM_SYNC_RESET (BIT(31)) -#define SPI_MEM_SYNC_RESET_M (BIT(31)) -#define SPI_MEM_SYNC_RESET_V 0x1 -#define SPI_MEM_SYNC_RESET_S 31 - -/* SPI_MEM_CS_HOLD_DELAY : R/W ;bitpos:[30:25] ;default: 6'd0 ; */ - -/* Description: These bits are used to set the minimum CS high time tSHSL - * between SPI burst transfer when accesses to flash. tSHSL is - * (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles. - */ - -#define SPI_MEM_CS_HOLD_DELAY 0x0000003F -#define SPI_MEM_CS_HOLD_DELAY_M ((SPI_MEM_CS_HOLD_DELAY_V)<<(SPI_MEM_CS_HOLD_DELAY_S)) -#define SPI_MEM_CS_HOLD_DELAY_V 0x3F -#define SPI_MEM_CS_HOLD_DELAY_S 25 - -/* SPI_MEM_ECC_16TO18_BYTE_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */ - -/* Description: Set this bit to enable MSPI ECC 16 bytes data with 2 ECC - * bytes mode when accesses flash. - */ - -#define SPI_MEM_ECC_16TO18_BYTE_EN (BIT(14)) -#define SPI_MEM_ECC_16TO18_BYTE_EN_M (BIT(14)) -#define SPI_MEM_ECC_16TO18_BYTE_EN_V 0x1 -#define SPI_MEM_ECC_16TO18_BYTE_EN_S 14 - -/* SPI_MEM_ECC_SKIP_PAGE_CORNER : R/W ;bitpos:[13] ;default: 1'b1 ; */ - -/* Description: 1: MSPI skips page corner when accesses flash. 0: Not skip - * page corner when accesses flash. - */ - -#define SPI_MEM_ECC_SKIP_PAGE_CORNER (BIT(13)) -#define SPI_MEM_ECC_SKIP_PAGE_CORNER_M (BIT(13)) -#define SPI_MEM_ECC_SKIP_PAGE_CORNER_V 0x1 -#define SPI_MEM_ECC_SKIP_PAGE_CORNER_S 13 - -/* SPI_MEM_ECC_CS_HOLD_TIME : R/W ;bitpos:[12:10] ;default: 3'd3 ; */ - -/* Description: SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI_CS - * hold cycle in ECC mode when accessed flash. - */ - -#define SPI_MEM_ECC_CS_HOLD_TIME 0x00000007 -#define SPI_MEM_ECC_CS_HOLD_TIME_M ((SPI_MEM_ECC_CS_HOLD_TIME_V)<<(SPI_MEM_ECC_CS_HOLD_TIME_S)) -#define SPI_MEM_ECC_CS_HOLD_TIME_V 0x7 -#define SPI_MEM_ECC_CS_HOLD_TIME_S 10 - -/* SPI_MEM_CS_HOLD_TIME : R/W ;bitpos:[9:5] ;default: 5'h1 ; */ - -/* Description: SPI Bus CS (SPI_CS) signal is delayed to inactive by SPI Bus - * clock (SPI_CLK), which is the SPI_CS hold time in non-ECC mode. These bits - * are combined with SPI_MEM_CS_HOLD bit. - */ - -#define SPI_MEM_CS_HOLD_TIME 0x0000001F -#define SPI_MEM_CS_HOLD_TIME_M ((SPI_MEM_CS_HOLD_TIME_V)<<(SPI_MEM_CS_HOLD_TIME_S)) -#define SPI_MEM_CS_HOLD_TIME_V 0x1F -#define SPI_MEM_CS_HOLD_TIME_S 5 - -/* SPI_MEM_CS_SETUP_TIME : R/W ;bitpos:[4:0] ;default: 5'h1 ; */ - -/* Description: (cycles-1) of PREP phase by SPI_CLK, which is the SPI_CS - * setup time. These bits are combined with SPI_MEM_CS_SETUP bit. - */ - -#define SPI_MEM_CS_SETUP_TIME 0x0000001F -#define SPI_MEM_CS_SETUP_TIME_M ((SPI_MEM_CS_SETUP_TIME_V)<<(SPI_MEM_CS_SETUP_TIME_S)) -#define SPI_MEM_CS_SETUP_TIME_V 0x1F -#define SPI_MEM_CS_SETUP_TIME_S 0 - -#define SPI_MEM_CLOCK_REG(i) (REG_SPI_MEM_BASE(i) + 0x14) - -/* SPI_MEM_CLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b0 ; */ - -/* Description: When SPI1 access to flash or Ext_RAM, set this bit in - * 1-division mode, f_SPI_CLK = f_MSPI_CORE_CLK. - */ - -#define SPI_MEM_CLK_EQU_SYSCLK (BIT(31)) -#define SPI_MEM_CLK_EQU_SYSCLK_M (BIT(31)) -#define SPI_MEM_CLK_EQU_SYSCLK_V 0x1 -#define SPI_MEM_CLK_EQU_SYSCLK_S 31 - -/* SPI_MEM_CLKCNT_N : R/W ;bitpos:[23:16] ;default: 8'h3 ; */ - -/* Description: When SPI1 accesses to flash or Ext_RAM, f_SPI_CLK = - * f_MSPI_CORE_CLK/(SPI_MEM_CLK_CNT_N + 1) - */ - -#define SPI_MEM_CLKCNT_N 0x000000FF -#define SPI_MEM_CLKCNT_N_M ((SPI_MEM_CLKCNT_N_V)<<(SPI_MEM_CLKCNT_N_S)) -#define SPI_MEM_CLKCNT_N_V 0xFF -#define SPI_MEM_CLKCNT_N_S 16 - -/* SPI_MEM_CLKCNT_H : R/W ;bitpos:[15:8] ;default: 8'h1 ; */ - -/* Description: It must be a floor value of ((SPI_MEM_CLKCNT_N+1)/2-1). */ - -#define SPI_MEM_CLKCNT_H 0x000000FF -#define SPI_MEM_CLKCNT_H_M ((SPI_MEM_CLKCNT_H_V)<<(SPI_MEM_CLKCNT_H_S)) -#define SPI_MEM_CLKCNT_H_V 0xFF -#define SPI_MEM_CLKCNT_H_S 8 - -/* SPI_MEM_CLKCNT_L : R/W ;bitpos:[7:0] ;default: 8'h3 ; */ - -/* Description: It must equal to the value of SPI_MEM_CLKCNT_N. */ - -#define SPI_MEM_CLKCNT_L 0x000000FF -#define SPI_MEM_CLKCNT_L_M ((SPI_MEM_CLKCNT_L_V)<<(SPI_MEM_CLKCNT_L_S)) -#define SPI_MEM_CLKCNT_L_V 0xFF -#define SPI_MEM_CLKCNT_L_S 0 - -#define SPI_MEM_USER_REG(i) (REG_SPI_MEM_BASE(i) + 0x18) - -/* SPI_MEM_USR_COMMAND : R/W ;bitpos:[31] ;default: 1'b1 ; */ - -/* Description: Set this bit to enable enable the CMD phase of an - * operation. - */ - -#define SPI_MEM_USR_COMMAND (BIT(31)) -#define SPI_MEM_USR_COMMAND_M (BIT(31)) -#define SPI_MEM_USR_COMMAND_V 0x1 -#define SPI_MEM_USR_COMMAND_S 31 - -/* SPI_MEM_USR_ADDR : R/W ;bitpos:[30] ;default: 1'b0 ; */ - -/* Description: Set this bit to enable enable the ADDR phase of an operation. - */ - -#define SPI_MEM_USR_ADDR (BIT(30)) -#define SPI_MEM_USR_ADDR_M (BIT(30)) -#define SPI_MEM_USR_ADDR_V 0x1 -#define SPI_MEM_USR_ADDR_S 30 - -/* SPI_MEM_USR_DUMMY : R/W ;bitpos:[29] ;default: 1'b0 ; */ - -/* Description: Set this bit to enable enable the DUMMY phase of an - * operation. - */ - -#define SPI_MEM_USR_DUMMY (BIT(29)) -#define SPI_MEM_USR_DUMMY_M (BIT(29)) -#define SPI_MEM_USR_DUMMY_V 0x1 -#define SPI_MEM_USR_DUMMY_S 29 - -/* SPI_MEM_USR_MISO : R/W ;bitpos:[28] ;default: 1'b0 ; */ - -/* Description: Set this bit to enable enable the DIN phase of a read-data - * operation. - */ - -#define SPI_MEM_USR_MISO (BIT(28)) -#define SPI_MEM_USR_MISO_M (BIT(28)) -#define SPI_MEM_USR_MISO_V 0x1 -#define SPI_MEM_USR_MISO_S 28 - -/* SPI_MEM_USR_MOSI : R/W ;bitpos:[27] ;default: 1'b0 ; */ - -/* Description: Set this bit to enable the DOUT phase of an write-data - * operation. - */ - -#define SPI_MEM_USR_MOSI (BIT(27)) -#define SPI_MEM_USR_MOSI_M (BIT(27)) -#define SPI_MEM_USR_MOSI_V 0x1 -#define SPI_MEM_USR_MOSI_S 27 - -/* SPI_MEM_USR_DUMMY_IDLE : R/W ;bitpos:[26] ;default: 1'b0 ; */ - -/* Description: SPI_CLK is disabled(No clock edges) in DUMMY phase when the - * bit is enable. - */ - -#define SPI_MEM_USR_DUMMY_IDLE (BIT(26)) -#define SPI_MEM_USR_DUMMY_IDLE_M (BIT(26)) -#define SPI_MEM_USR_DUMMY_IDLE_V 0x1 -#define SPI_MEM_USR_DUMMY_IDLE_S 26 - -/* SPI_MEM_USR_MOSI_HIGHPART : R/W ;bitpos:[25] ;default: 1'b0 ; */ - -/* Description: DOUT phase only access to high-part of the buffer - * SPI_MEM_W8_REG~SPI_MEM_W15_REG. - * 1: enable - * 0: disable. - */ - -#define SPI_MEM_USR_MOSI_HIGHPART (BIT(25)) -#define SPI_MEM_USR_MOSI_HIGHPART_M (BIT(25)) -#define SPI_MEM_USR_MOSI_HIGHPART_V 0x1 -#define SPI_MEM_USR_MOSI_HIGHPART_S 25 - -/* SPI_MEM_USR_MISO_HIGHPART : R/W ;bitpos:[24] ;default: 1'b0 ; */ - -/* Description: DIN phase only access to high-part of the buffer - * SPI_MEM_W8_REG~SPI_MEM_W15_REG. - * 1: enable - * 0: disable. - */ - -#define SPI_MEM_USR_MISO_HIGHPART (BIT(24)) -#define SPI_MEM_USR_MISO_HIGHPART_M (BIT(24)) -#define SPI_MEM_USR_MISO_HIGHPART_V 0x1 -#define SPI_MEM_USR_MISO_HIGHPART_S 24 - -/* SPI_MEM_FWRITE_QIO : R/W ;bitpos:[15] ;default: 1'b0 ; */ - -/* Description: Set this bit to enable 4-bit-mode(4-bm) in ADDR and DOUT - * phase in SPI1 write operation. - */ - -#define SPI_MEM_FWRITE_QIO (BIT(15)) -#define SPI_MEM_FWRITE_QIO_M (BIT(15)) -#define SPI_MEM_FWRITE_QIO_V 0x1 -#define SPI_MEM_FWRITE_QIO_S 15 - -/* SPI_MEM_FWRITE_DIO : R/W ;bitpos:[14] ;default: 1'b0 ; */ - -/* Description: Set this bit to enable 2-bm in ADDR and DOUT phase in SPI1 - * write operation. - */ - -#define SPI_MEM_FWRITE_DIO (BIT(14)) -#define SPI_MEM_FWRITE_DIO_M (BIT(14)) -#define SPI_MEM_FWRITE_DIO_V 0x1 -#define SPI_MEM_FWRITE_DIO_S 14 - -/* SPI_MEM_FWRITE_QUAD : R/W ;bitpos:[13] ;default: 1'b0 ; */ - -/* Description: Set this bit to enable 4-bm in DOUT phase in SPI1 write - * operation. - */ - -#define SPI_MEM_FWRITE_QUAD (BIT(13)) -#define SPI_MEM_FWRITE_QUAD_M (BIT(13)) -#define SPI_MEM_FWRITE_QUAD_V 0x1 -#define SPI_MEM_FWRITE_QUAD_S 13 - -/* SPI_MEM_FWRITE_DUAL : R/W ;bitpos:[12] ;default: 1'b0 ; */ - -/* Description: Set this bit to enable 2-bm in DOUT phase in SPI1 write - * operation. - */ - -#define SPI_MEM_FWRITE_DUAL (BIT(12)) -#define SPI_MEM_FWRITE_DUAL_M (BIT(12)) -#define SPI_MEM_FWRITE_DUAL_V 0x1 -#define SPI_MEM_FWRITE_DUAL_S 12 - -/* SPI_MEM_CK_OUT_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */ - -/* Description: This bit, combined with SPI_MEM_CK_IDLE_EDGE bit, is used to - * change the clock mode 0~3 of SPI_CLK. - */ - -#define SPI_MEM_CK_OUT_EDGE (BIT(9)) -#define SPI_MEM_CK_OUT_EDGE_M (BIT(9)) -#define SPI_MEM_CK_OUT_EDGE_V 0x1 -#define SPI_MEM_CK_OUT_EDGE_S 9 - -/* SPI_MEM_CS_SETUP : R/W ;bitpos:[7] ;default: 1'b0 ; */ - -/* Description: Set this bit to keep SPI_CS low when MSPI is in PREP state. */ - -#define SPI_MEM_CS_SETUP (BIT(7)) -#define SPI_MEM_CS_SETUP_M (BIT(7)) -#define SPI_MEM_CS_SETUP_V 0x1 -#define SPI_MEM_CS_SETUP_S 7 - -/* SPI_MEM_CS_HOLD : R/W ;bitpos:[6] ;default: 1'b0 ; */ - -/* Description: Set this bit to keep SPI_CS low when MSPI is in DONE state. */ - -#define SPI_MEM_CS_HOLD (BIT(6)) -#define SPI_MEM_CS_HOLD_M (BIT(6)) -#define SPI_MEM_CS_HOLD_V 0x1 -#define SPI_MEM_CS_HOLD_S 6 - -#define SPI_MEM_USER1_REG(i) (REG_SPI_MEM_BASE(i) + 0x1C) - -/* SPI_MEM_USR_ADDR_BITLEN : R/W ;bitpos:[31:26] ;default: 6'd23 ; */ - -/* Description: The length in bits of ADDR phase. The register value shall be - * (bit_num-1). - */ - -#define SPI_MEM_USR_ADDR_BITLEN 0x0000003F -#define SPI_MEM_USR_ADDR_BITLEN_M ((SPI_MEM_USR_ADDR_BITLEN_V)<<(SPI_MEM_USR_ADDR_BITLEN_S)) -#define SPI_MEM_USR_ADDR_BITLEN_V 0x3F -#define SPI_MEM_USR_ADDR_BITLEN_S 26 - -/* SPI_MEM_USR_DUMMY_CYCLELEN : R/W ;bitpos:[5:0] ;default: 6'd7 ; */ - -/* Description: The SPI_CLK cycle length minus 1 of DUMMY phase. */ - -#define SPI_MEM_USR_DUMMY_CYCLELEN 0x0000003F -#define SPI_MEM_USR_DUMMY_CYCLELEN_M ((SPI_MEM_USR_DUMMY_CYCLELEN_V)<<(SPI_MEM_USR_DUMMY_CYCLELEN_S)) -#define SPI_MEM_USR_DUMMY_CYCLELEN_V 0x3F -#define SPI_MEM_USR_DUMMY_CYCLELEN_S 0 - -#define SPI_MEM_USER2_REG(i) (REG_SPI_MEM_BASE(i) + 0x20) - -/* SPI_MEM_USR_COMMAND_BITLEN : R/W ;bitpos:[31:28] ;default: 4'd7 ; */ - -/* Description: The length in bits of CMD phase. The register value shall be - * (bit_num-1) - */ - -#define SPI_MEM_USR_COMMAND_BITLEN 0x0000000F -#define SPI_MEM_USR_COMMAND_BITLEN_M ((SPI_MEM_USR_COMMAND_BITLEN_V)<<(SPI_MEM_USR_COMMAND_BITLEN_S)) -#define SPI_MEM_USR_COMMAND_BITLEN_V 0xF -#define SPI_MEM_USR_COMMAND_BITLEN_S 28 - -/* SPI_MEM_USR_COMMAND_VALUE : R/W ;bitpos:[15:0] ;default: 16'b0 ; */ - -/* Description: The value of user defined(USR) command. */ - -#define SPI_MEM_USR_COMMAND_VALUE 0x0000FFFF -#define SPI_MEM_USR_COMMAND_VALUE_M ((SPI_MEM_USR_COMMAND_VALUE_V)<<(SPI_MEM_USR_COMMAND_VALUE_S)) -#define SPI_MEM_USR_COMMAND_VALUE_V 0xFFFF -#define SPI_MEM_USR_COMMAND_VALUE_S 0 - -#define SPI_MEM_MOSI_DLEN_REG(i) (REG_SPI_MEM_BASE(i) + 0x24) - -/* SPI_MEM_USR_MOSI_DBITLEN : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ - -/* Description: The length in bits of DOUT phase. The register value shall be - * (bit_num-1). - */ - -#define SPI_MEM_USR_MOSI_DBITLEN 0x000003FF -#define SPI_MEM_USR_MOSI_DBITLEN_M ((SPI_MEM_USR_MOSI_DBITLEN_V)<<(SPI_MEM_USR_MOSI_DBITLEN_S)) -#define SPI_MEM_USR_MOSI_DBITLEN_V 0x3FF -#define SPI_MEM_USR_MOSI_DBITLEN_S 0 - -#define SPI_MEM_MISO_DLEN_REG(i) (REG_SPI_MEM_BASE(i) + 0x28) - -/* SPI_MEM_USR_MISO_DBITLEN : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ - -/* Description: The length in bits of DIN phase. The register value shall be - * (bit_num-1). - */ - -#define SPI_MEM_USR_MISO_DBITLEN 0x000003FF -#define SPI_MEM_USR_MISO_DBITLEN_M ((SPI_MEM_USR_MISO_DBITLEN_V)<<(SPI_MEM_USR_MISO_DBITLEN_S)) -#define SPI_MEM_USR_MISO_DBITLEN_V 0x3FF -#define SPI_MEM_USR_MISO_DBITLEN_S 0 - -#define SPI_MEM_RD_STATUS_REG(i) (REG_SPI_MEM_BASE(i) + 0x2C) - -/* SPI_MEM_WB_MODE : R/W ;bitpos:[23:16] ;default: 8'h00 ; */ - -/* Description: Mode bits in the flash fast read mode it is combined with - * SPI_MEM_FASTRD_MODE bit. - */ - -#define SPI_MEM_WB_MODE 0x000000FF -#define SPI_MEM_WB_MODE_M ((SPI_MEM_WB_MODE_V)<<(SPI_MEM_WB_MODE_S)) -#define SPI_MEM_WB_MODE_V 0xFF -#define SPI_MEM_WB_MODE_S 16 - -/* SPI_MEM_STATUS : R/W/SS ;bitpos:[15:0] ;default: 16'b0 ; */ - -/* Description: The value is stored when set SPI_MEM_FLASH_RDSR bit and - * SPI_MEM_FLASH_RES bit. - */ - -#define SPI_MEM_STATUS 0x0000FFFF -#define SPI_MEM_STATUS_M ((SPI_MEM_STATUS_V)<<(SPI_MEM_STATUS_S)) -#define SPI_MEM_STATUS_V 0xFFFF -#define SPI_MEM_STATUS_S 0 - -#define SPI_MEM_EXT_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x30) - -/* SPI_MEM_EXT_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ - -/* Description: The register are the higher 32bits in the 64 bits address - * mode. - */ - -#define SPI_MEM_EXT_ADDR 0xFFFFFFFF -#define SPI_MEM_EXT_ADDR_M ((SPI_MEM_EXT_ADDR_V)<<(SPI_MEM_EXT_ADDR_S)) -#define SPI_MEM_EXT_ADDR_V 0xFFFFFFFF -#define SPI_MEM_EXT_ADDR_S 0 - -#define SPI_MEM_MISC_REG(i) (REG_SPI_MEM_BASE(i) + 0x34) - -/* SPI_MEM_AUTO_PER : R/W ;bitpos:[11] ;default: 1'b0 ; */ - -/* Description: Set this bit to enable auto PER function. Hardware will sent - * out PER command if PES command is sent. - */ - -#define SPI_MEM_AUTO_PER (BIT(11)) -#define SPI_MEM_AUTO_PER_M (BIT(11)) -#define SPI_MEM_AUTO_PER_V 0x1 -#define SPI_MEM_AUTO_PER_S 11 - -/* SPI_MEM_CS_KEEP_ACTIVE : R/W ;bitpos:[10] ;default: 1'b0 ; */ - -/* Description: SPI_CS line keep low when the bit is set. */ - -#define SPI_MEM_CS_KEEP_ACTIVE (BIT(10)) -#define SPI_MEM_CS_KEEP_ACTIVE_M (BIT(10)) -#define SPI_MEM_CS_KEEP_ACTIVE_V 0x1 -#define SPI_MEM_CS_KEEP_ACTIVE_S 10 - -/* SPI_MEM_CK_IDLE_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */ - -/* Description: - * 1: SPI_CLK line is high when MSPI is idle. - * 0: SPI_CLK line is low when MSPI is idle. - */ - -#define SPI_MEM_CK_IDLE_EDGE (BIT(9)) -#define SPI_MEM_CK_IDLE_EDGE_M (BIT(9)) -#define SPI_MEM_CK_IDLE_EDGE_V 0x1 -#define SPI_MEM_CK_IDLE_EDGE_S 9 - -/* SPI_MEM_SSUB_PIN : R/W ;bitpos:[8] ;default: 1'b0 ; */ - -/* Description: Ext_RAM is connected to SPI SUBPIN bus. */ - -#define SPI_MEM_SSUB_PIN (BIT(8)) -#define SPI_MEM_SSUB_PIN_M (BIT(8)) -#define SPI_MEM_SSUB_PIN_V 0x1 -#define SPI_MEM_SSUB_PIN_S 8 - -/* SPI_MEM_FSUB_PIN : R/W ;bitpos:[7] ;default: 1'b0 ; */ - -/* Description: Flash is connected to SPI SUBPIN bus. */ - -#define SPI_MEM_FSUB_PIN (BIT(7)) -#define SPI_MEM_FSUB_PIN_M (BIT(7)) -#define SPI_MEM_FSUB_PIN_V 0x1 -#define SPI_MEM_FSUB_PIN_S 7 - -/* SPI_MEM_CS1_DIS : R/W ;bitpos:[1] ;default: 1'b1 ; */ - -/* Description: Set this bit to raise high SPI_CS1 pin, which means that the - * SPI device(Ext_RAM) connected to SPI_CS1 is in low level when SPI1 - * transfer starts. - */ - -#define SPI_MEM_CS1_DIS (BIT(1)) -#define SPI_MEM_CS1_DIS_M (BIT(1)) -#define SPI_MEM_CS1_DIS_V 0x1 -#define SPI_MEM_CS1_DIS_S 1 - -/* SPI_MEM_CS0_DIS : R/W ;bitpos:[0] ;default: 1'b0 ; */ - -/* Description: Set this bit to raise high SPI_CS pin, which means that the - * SPI device(flash) connected to SPI_CS is in low level when SPI1 transfer - * starts. - */ - -#define SPI_MEM_CS0_DIS (BIT(0)) -#define SPI_MEM_CS0_DIS_M (BIT(0)) -#define SPI_MEM_CS0_DIS_V 0x1 -#define SPI_MEM_CS0_DIS_S 0 - -#define SPI_MEM_TX_CRC_REG(i) (REG_SPI_MEM_BASE(i) + 0x38) - -/* SPI_MEM_TX_CRC_DATA : RO ;bitpos:[31:0] ;default: 32'hffffffff ; */ - -/* Description: For SPI1, the value of crc32. */ - -#define SPI_MEM_TX_CRC_DATA 0xFFFFFFFF -#define SPI_MEM_TX_CRC_DATA_M ((SPI_MEM_TX_CRC_DATA_V)<<(SPI_MEM_TX_CRC_DATA_S)) -#define SPI_MEM_TX_CRC_DATA_V 0xFFFFFFFF -#define SPI_MEM_TX_CRC_DATA_S 0 - -#define SPI_MEM_CACHE_FCTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x3C) - -/* SPI_MEM_FADDR_QUAD : R/W ;bitpos:[8] ;default: 1'b0 ; */ - -/* Description: When SPI1 accesses to flash or Ext_RAM, set this bit to - * enable 4-bm in ADDR phase. - */ - -#define SPI_MEM_FADDR_QUAD (BIT(8)) -#define SPI_MEM_FADDR_QUAD_M (BIT(8)) -#define SPI_MEM_FADDR_QUAD_V 0x1 -#define SPI_MEM_FADDR_QUAD_S 8 - -/* SPI_MEM_FDOUT_QUAD : R/W ;bitpos:[7] ;default: 1'b0 ; */ - -/* Description: When SPI1 accesses to flash or Ext_RAM, set this bit to - * enable 4-bm in DOUT phase. - */ - -#define SPI_MEM_FDOUT_QUAD (BIT(7)) -#define SPI_MEM_FDOUT_QUAD_M (BIT(7)) -#define SPI_MEM_FDOUT_QUAD_V 0x1 -#define SPI_MEM_FDOUT_QUAD_S 7 - -/* SPI_MEM_FDIN_QUAD : R/W ;bitpos:[6] ;default: 1'b0 ; */ - -/* Description: When SPI1 accesses to flash or Ext_RAM, set this bit to - * enable 4-bm in DIN phase. - */ - -#define SPI_MEM_FDIN_QUAD (BIT(6)) -#define SPI_MEM_FDIN_QUAD_M (BIT(6)) -#define SPI_MEM_FDIN_QUAD_V 0x1 -#define SPI_MEM_FDIN_QUAD_S 6 - -/* SPI_MEM_FADDR_DUAL : R/W ;bitpos:[5] ;default: 1'b0 ; */ - -/* Description: When SPI1 accesses to flash or Ext_RAM, set this bit to - * enable 2-bm in ADDR phase. - */ - -#define SPI_MEM_FADDR_DUAL (BIT(5)) -#define SPI_MEM_FADDR_DUAL_M (BIT(5)) -#define SPI_MEM_FADDR_DUAL_V 0x1 -#define SPI_MEM_FADDR_DUAL_S 5 - -/* SPI_MEM_FDOUT_DUAL : R/W ;bitpos:[4] ;default: 1'b0 ; */ - -/* Description: When SPI1 accesses to flash or Ext_RAM, set this bit to - * enable 2-bm in DOUT phase. - */ - -#define SPI_MEM_FDOUT_DUAL (BIT(4)) -#define SPI_MEM_FDOUT_DUAL_M (BIT(4)) -#define SPI_MEM_FDOUT_DUAL_V 0x1 -#define SPI_MEM_FDOUT_DUAL_S 4 - -/* SPI_MEM_FDIN_DUAL : R/W ;bitpos:[3] ;default: 1'b0 ; */ - -/* Description: When SPI1 accesses to flash or Ext_RAM, set this bit to - * enable 2-bm in DIN phase. - */ - -#define SPI_MEM_FDIN_DUAL (BIT(3)) -#define SPI_MEM_FDIN_DUAL_M (BIT(3)) -#define SPI_MEM_FDIN_DUAL_V 0x1 -#define SPI_MEM_FDIN_DUAL_S 3 - -/* SPI_MEM_CACHE_FLASH_USR_CMD : R/W ;bitpos:[2] ;default: 1'b0 ; */ - -/* Description: - * 1: The command value of SPI0 reads flash is SPI_MEM_USR_COMMAND_VALUE. - * 0: Hardware read command value, controlled by SPI_MEM_FREAD_QIO, - * SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QUAD, SPI_MEM_FREAD_DUAL and - * SPI_MEM_FASTRD_MODE bits. - */ - -#define SPI_MEM_CACHE_FLASH_USR_CMD (BIT(2)) -#define SPI_MEM_CACHE_FLASH_USR_CMD_M (BIT(2)) -#define SPI_MEM_CACHE_FLASH_USR_CMD_V 0x1 -#define SPI_MEM_CACHE_FLASH_USR_CMD_S 2 - -/* SPI_MEM_CACHE_USR_CMD_4BYTE : R/W ;bitpos:[1] ;default: 1'b0 ; */ - -/* Description: - * Set this bit to enable SPI1 transfer with 32 bits address. The value of - * SPI_MEM_USR_ADDR_BITLEN should be 31. - */ - -#define SPI_MEM_CACHE_USR_CMD_4BYTE (BIT(1)) -#define SPI_MEM_CACHE_USR_CMD_4BYTE_M (BIT(1)) -#define SPI_MEM_CACHE_USR_CMD_4BYTE_V 0x1 -#define SPI_MEM_CACHE_USR_CMD_4BYTE_S 1 - -/* SPI_MEM_CACHE_REQ_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ - -/* Description: Set this bit to enable Cache's access and SPI0's transfer. */ - -#define SPI_MEM_CACHE_REQ_EN (BIT(0)) -#define SPI_MEM_CACHE_REQ_EN_M (BIT(0)) -#define SPI_MEM_CACHE_REQ_EN_V 0x1 -#define SPI_MEM_CACHE_REQ_EN_S 0 - -#define SPI_MEM_CACHE_SCTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x40) - -/* SPI_MEM_SRAM_WDUMMY_CYCLELEN : R/W ;bitpos:[27:22] ;default: 6'b1 ; */ - -/* Description: When SPI0 accesses to Ext_RAM, it is the SPI_CLK cycles minus - * 1 of DUMMY phase in write data transfer. - */ - -#define SPI_MEM_SRAM_WDUMMY_CYCLELEN 0x0000003F -#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_M ((SPI_MEM_SRAM_WDUMMY_CYCLELEN_V)<<(SPI_MEM_SRAM_WDUMMY_CYCLELEN_S)) -#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_V 0x3F -#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_S 22 - -/* SPI_MEM_SRAM_OCT : R/W ;bitpos:[21] ;default: 1'b0 ; */ - -/* Description: Set the bit to enable OPI mode in all SPI0 Ext_RAM - * transfer. - */ - -#define SPI_MEM_SRAM_OCT (BIT(21)) -#define SPI_MEM_SRAM_OCT_M (BIT(21)) -#define SPI_MEM_SRAM_OCT_V 0x1 -#define SPI_MEM_SRAM_OCT_S 21 - -/* SPI_MEM_CACHE_SRAM_USR_WCMD : R/W ;bitpos:[20] ;default: 1'b1 ; */ - -/* Description: - * 1: The command value of SPI0 write Ext_RAM is - * SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE. - * 0: The value is 0x3. - */ - -#define SPI_MEM_CACHE_SRAM_USR_WCMD (BIT(20)) -#define SPI_MEM_CACHE_SRAM_USR_WCMD_M (BIT(20)) -#define SPI_MEM_CACHE_SRAM_USR_WCMD_V 0x1 -#define SPI_MEM_CACHE_SRAM_USR_WCMD_S 20 - -/* SPI_MEM_SRAM_ADDR_BITLEN : R/W ;bitpos:[19:14] ;default: 6'd23 ; */ - -/* Description: When SPI0 accesses to Ext_RAM, it is the length in bits of - * ADDR phase. The register value shall be (bit_num-1). - */ - -#define SPI_MEM_SRAM_ADDR_BITLEN 0x0000003F -#define SPI_MEM_SRAM_ADDR_BITLEN_M ((SPI_MEM_SRAM_ADDR_BITLEN_V)<<(SPI_MEM_SRAM_ADDR_BITLEN_S)) -#define SPI_MEM_SRAM_ADDR_BITLEN_V 0x3F -#define SPI_MEM_SRAM_ADDR_BITLEN_S 14 - -/* SPI_MEM_SRAM_RDUMMY_CYCLELEN : R/W ;bitpos:[11:6] ;default: 6'b1 ; */ - -/* Description: When SPI0 accesses to Ext_RAM, it is the SPI_CLK cycles minus - * 1 of DUMMY phase in read data transfer. - */ - -#define SPI_MEM_SRAM_RDUMMY_CYCLELEN 0x0000003F -#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_M ((SPI_MEM_SRAM_RDUMMY_CYCLELEN_V)<<(SPI_MEM_SRAM_RDUMMY_CYCLELEN_S)) -#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_V 0x3F -#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_S 6 - -/* SPI_MEM_CACHE_SRAM_USR_RCMD : R/W ;bitpos:[5] ;default: 1'b1 ; */ - -/* Description: - * 1: The command value of SPI0 read Ext_RAM is - * SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE. - * 0: The value is 0x2. - */ - -#define SPI_MEM_CACHE_SRAM_USR_RCMD (BIT(5)) -#define SPI_MEM_CACHE_SRAM_USR_RCMD_M (BIT(5)) -#define SPI_MEM_CACHE_SRAM_USR_RCMD_V 0x1 -#define SPI_MEM_CACHE_SRAM_USR_RCMD_S 5 - -/* SPI_MEM_USR_RD_SRAM_DUMMY : R/W ;bitpos:[4] ;default: 1'b1 ; */ - -/* Description: When SPI0 accesses to Ext_RAM, set this bit to enable DUMMY - * phase in read operations. - */ - -#define SPI_MEM_USR_RD_SRAM_DUMMY (BIT(4)) -#define SPI_MEM_USR_RD_SRAM_DUMMY_M (BIT(4)) -#define SPI_MEM_USR_RD_SRAM_DUMMY_V 0x1 -#define SPI_MEM_USR_RD_SRAM_DUMMY_S 4 - -/* SPI_MEM_USR_WR_SRAM_DUMMY : R/W ;bitpos:[3] ;default: 1'b0 ; */ - -/* Description: When SPI0 accesses to Ext_RAM, set this bit to enable DUMMY - * phase in write operations. - */ - -#define SPI_MEM_USR_WR_SRAM_DUMMY (BIT(3)) -#define SPI_MEM_USR_WR_SRAM_DUMMY_M (BIT(3)) -#define SPI_MEM_USR_WR_SRAM_DUMMY_V 0x1 -#define SPI_MEM_USR_WR_SRAM_DUMMY_S 3 - -/* SPI_MEM_USR_SRAM_QIO : R/W ;bitpos:[2] ;default: 1'b0 ; */ - -/* Description: Set the bit to enable QPI mode in all SPI0 Ext_RAM transfer. - */ - -#define SPI_MEM_USR_SRAM_QIO (BIT(2)) -#define SPI_MEM_USR_SRAM_QIO_M (BIT(2)) -#define SPI_MEM_USR_SRAM_QIO_V 0x1 -#define SPI_MEM_USR_SRAM_QIO_S 2 - -/* SPI_MEM_USR_SRAM_DIO : R/W ;bitpos:[1] ;default: 1'b0 ; */ - -/* Description: Set the bit to enable 2-bm in all the phases of SPI0 Ext_RAM - * transfer. - */ - -#define SPI_MEM_USR_SRAM_DIO (BIT(1)) -#define SPI_MEM_USR_SRAM_DIO_M (BIT(1)) -#define SPI_MEM_USR_SRAM_DIO_V 0x1 -#define SPI_MEM_USR_SRAM_DIO_S 1 - -/* SPI_MEM_CACHE_USR_SCMD_4BYTE : R/W ;bitpos:[0] ;default: 1'b0 ; */ - -/* Description: Set this bit to enable SPI0 read Ext_RAM with 32 bits - * address. The value of SPI_MEM_SRAM_ADDR_BITLEN should be 31. - */ - -#define SPI_MEM_CACHE_USR_SCMD_4BYTE (BIT(0)) -#define SPI_MEM_CACHE_USR_SCMD_4BYTE_M (BIT(0)) -#define SPI_MEM_CACHE_USR_SCMD_4BYTE_V 0x1 -#define SPI_MEM_CACHE_USR_SCMD_4BYTE_S 0 - -#define SPI_MEM_SRAM_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x44) - -/* SPI_MEM_SDUMMY_OUT : R/W ;bitpos:[22] ;default: 1'b0 ; */ - -/* Description: When SPI0 accesses to Ext_RAM, in the DUMMY phase the signal - * level of SPI bus is output by the SPI0 controller. - */ - -#define SPI_MEM_SDUMMY_OUT (BIT(22)) -#define SPI_MEM_SDUMMY_OUT_M (BIT(22)) -#define SPI_MEM_SDUMMY_OUT_V 0x1 -#define SPI_MEM_SDUMMY_OUT_S 22 - -/* SPI_MEM_SCMD_OCT : R/W ;bitpos:[21] ;default: 1'b0 ; */ - -/* Description: When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in - * CMD phase. - */ - -#define SPI_MEM_SCMD_OCT (BIT(21)) -#define SPI_MEM_SCMD_OCT_M (BIT(21)) -#define SPI_MEM_SCMD_OCT_V 0x1 -#define SPI_MEM_SCMD_OCT_S 21 - -/* SPI_MEM_SADDR_OCT : R/W ;bitpos:[20] ;default: 1'b0 ; */ - -/* Description: When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in - * ADDR phase. - */ - -#define SPI_MEM_SADDR_OCT (BIT(20)) -#define SPI_MEM_SADDR_OCT_M (BIT(20)) -#define SPI_MEM_SADDR_OCT_V 0x1 -#define SPI_MEM_SADDR_OCT_S 20 - -/* SPI_MEM_SDOUT_OCT : R/W ;bitpos:[19] ;default: 1'b0 ; */ - -/* Description: When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in - * DOUT phase. - */ - -#define SPI_MEM_SDOUT_OCT (BIT(19)) -#define SPI_MEM_SDOUT_OCT_M (BIT(19)) -#define SPI_MEM_SDOUT_OCT_V 0x1 -#define SPI_MEM_SDOUT_OCT_S 19 - -/* SPI_MEM_SDIN_OCT : R/W ;bitpos:[18] ;default: 1'b0 ; */ - -/* Description: When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in - * DIN phase. - */ - -#define SPI_MEM_SDIN_OCT (BIT(18)) -#define SPI_MEM_SDIN_OCT_M (BIT(18)) -#define SPI_MEM_SDIN_OCT_V 0x1 -#define SPI_MEM_SDIN_OCT_S 18 - -/* SPI_MEM_SCMD_QUAD : R/W ;bitpos:[17] ;default: 1'b0 ; */ - -/* Description: When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in - * CMD phase. - */ - -#define SPI_MEM_SCMD_QUAD (BIT(17)) -#define SPI_MEM_SCMD_QUAD_M (BIT(17)) -#define SPI_MEM_SCMD_QUAD_V 0x1 -#define SPI_MEM_SCMD_QUAD_S 17 - -/* SPI_MEM_SADDR_QUAD : R/W ;bitpos:[16] ;default: 1'b0 ; */ - -/* Description: When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in - * ADDR phase. - */ - -#define SPI_MEM_SADDR_QUAD (BIT(16)) -#define SPI_MEM_SADDR_QUAD_M (BIT(16)) -#define SPI_MEM_SADDR_QUAD_V 0x1 -#define SPI_MEM_SADDR_QUAD_S 16 - -/* SPI_MEM_SDOUT_QUAD : R/W ;bitpos:[15] ;default: 1'b0 ; */ - -/* Description: When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in - * DOUT phase. - */ - -#define SPI_MEM_SDOUT_QUAD (BIT(15)) -#define SPI_MEM_SDOUT_QUAD_M (BIT(15)) -#define SPI_MEM_SDOUT_QUAD_V 0x1 -#define SPI_MEM_SDOUT_QUAD_S 15 - -/* SPI_MEM_SDIN_QUAD : R/W ;bitpos:[14] ;default: 1'b0 ; */ - -/* Description: When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in - * DIN phase. - */ - -#define SPI_MEM_SDIN_QUAD (BIT(14)) -#define SPI_MEM_SDIN_QUAD_M (BIT(14)) -#define SPI_MEM_SDIN_QUAD_V 0x1 -#define SPI_MEM_SDIN_QUAD_S 14 - -/* SPI_MEM_SCMD_DUAL : R/W ;bitpos:[13] ;default: 1'b0 ; */ - -/* Description: When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in - * CMD phase. - */ - -#define SPI_MEM_SCMD_DUAL (BIT(13)) -#define SPI_MEM_SCMD_DUAL_M (BIT(13)) -#define SPI_MEM_SCMD_DUAL_V 0x1 -#define SPI_MEM_SCMD_DUAL_S 13 - -/* SPI_MEM_SADDR_DUAL : R/W ;bitpos:[12] ;default: 1'b0 ; */ - -/* Description: When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in - * ADDR phase. - */ - -#define SPI_MEM_SADDR_DUAL (BIT(12)) -#define SPI_MEM_SADDR_DUAL_M (BIT(12)) -#define SPI_MEM_SADDR_DUAL_V 0x1 -#define SPI_MEM_SADDR_DUAL_S 12 - -/* SPI_MEM_SDOUT_DUAL : R/W ;bitpos:[11] ;default: 1'b0 ; */ - -/* Description: When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in - * DOUT phase. - */ - -#define SPI_MEM_SDOUT_DUAL (BIT(11)) -#define SPI_MEM_SDOUT_DUAL_M (BIT(11)) -#define SPI_MEM_SDOUT_DUAL_V 0x1 -#define SPI_MEM_SDOUT_DUAL_S 11 - -/* SPI_MEM_SDIN_DUAL : R/W ;bitpos:[10] ;default: 1'b0 ; */ - -/* Description: When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in - * DIN phase. - */ - -#define SPI_MEM_SDIN_DUAL (BIT(10)) -#define SPI_MEM_SDIN_DUAL_M (BIT(10)) -#define SPI_MEM_SDIN_DUAL_V 0x1 -#define SPI_MEM_SDIN_DUAL_S 10 - -/* SPI_MEM_SWB_MODE : R/W ;bitpos:[9:2] ;default: 8'b0 ; */ - -/* Description: Mode bits when SPI0 accesses to Ext_RAM. */ - -#define SPI_MEM_SWB_MODE 0x000000FF -#define SPI_MEM_SWB_MODE_M ((SPI_MEM_SWB_MODE_V)<<(SPI_MEM_SWB_MODE_S)) -#define SPI_MEM_SWB_MODE_V 0xFF -#define SPI_MEM_SWB_MODE_S 2 - -/* SPI_MEM_SCLK_MODE : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ - -/* Description: SPI_CLK mode bits when SPI0 accesses to Ext_RAM. - * 0: SPI_CLK is off when CS inactive - * 1: SPI_CLK is delayed one cycle after CS inactive - * 2: SPI_CLK is delayed two cycles after CS inactive - * 3: SPI_CLK is always on. - */ - -#define SPI_MEM_SCLK_MODE 0x00000003 -#define SPI_MEM_SCLK_MODE_M ((SPI_MEM_SCLK_MODE_V)<<(SPI_MEM_SCLK_MODE_S)) -#define SPI_MEM_SCLK_MODE_V 0x3 -#define SPI_MEM_SCLK_MODE_S 0 - -#define SPI_MEM_SRAM_DRD_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x48) - -/* SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN: R/W;bitpos:[31:28];default:4'h0; */ - -/* Description: When SPI0 reads Ext_RAM, it is the length in bits of CMD - * phase. The register value shall be (bit_num-1). - */ - -#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN 0x0000000F -#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_M ((SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V)<<(SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S)) -#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V 0xF -#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S 28 - -/* SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE: R/W;bitpos:[15:0];default:16'h0; */ - -/* Description: When SPI0 reads Ext_RAM, it is the command value of - * CMD phase. - */ - -#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE 0x0000FFFF -#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_M ((SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V)<<(SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S)) -#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V 0xFFFF -#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S 0 - -#define SPI_MEM_SRAM_DWR_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x4C) - -/* SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN: R/W;bitpos:[31:28];default:4'h0; */ - -/* Description: When SPI0 writes Ext_RAM, it is the length in bits of CMD - * phase. The register value shall be (bit_num-1). - */ - -#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN 0x0000000F -#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_M ((SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_V)<<(SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S)) -#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_V 0xF -#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S 28 - -/* SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE: R/W;bitpos:[15:0];default: 16'h0; */ - -/* Description: When SPI0 writes Ext_RAM, it is the command value of - * CMD phase. - */ - -#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE 0x0000FFFF -#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_M ((SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_V)<<(SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S)) -#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_V 0xFFFF -#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S 0 - -#define SPI_MEM_SRAM_CLK_REG(i) (REG_SPI_MEM_BASE(i) + 0x50) - -/* SPI_MEM_SCLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b0 ; */ - -/* Description: When SPI0 accesses to Ext_RAM, set this bit in 1-division - * mode, f_SPI_CLK = f_MSPI_CORE_CLK. - */ - -#define SPI_MEM_SCLK_EQU_SYSCLK (BIT(31)) -#define SPI_MEM_SCLK_EQU_SYSCLK_M (BIT(31)) -#define SPI_MEM_SCLK_EQU_SYSCLK_V 0x1 -#define SPI_MEM_SCLK_EQU_SYSCLK_S 31 - -/* SPI_MEM_SCLKCNT_N : R/W ;bitpos:[23:16] ;default: 8'h3 ; */ - -/* Description: When SPI0 accesses to Ext_RAM, f_SPI_CLK = - * f_MSPI_CORE_CLK/(SPI_MEM_SCLKCNT_N+1) - */ - -#define SPI_MEM_SCLKCNT_N 0x000000FF -#define SPI_MEM_SCLKCNT_N_M ((SPI_MEM_SCLKCNT_N_V)<<(SPI_MEM_SCLKCNT_N_S)) -#define SPI_MEM_SCLKCNT_N_V 0xFF -#define SPI_MEM_SCLKCNT_N_S 16 - -/* SPI_MEM_SCLKCNT_H : R/W ;bitpos:[15:8] ;default: 8'h1 ; */ - -/* Description: It must be a floor value of ((SPI_MEM_SCLKCNT_N+1)/2-1). */ - -#define SPI_MEM_SCLKCNT_H 0x000000FF -#define SPI_MEM_SCLKCNT_H_M ((SPI_MEM_SCLKCNT_H_V)<<(SPI_MEM_SCLKCNT_H_S)) -#define SPI_MEM_SCLKCNT_H_V 0xFF -#define SPI_MEM_SCLKCNT_H_S 8 - -/* SPI_MEM_SCLKCNT_L : R/W ;bitpos:[7:0] ;default: 8'h3 ; */ - -/* Description: It must equal to the value of SPI_MEM_SCLKCNT_N. */ - -#define SPI_MEM_SCLKCNT_L 0x000000FF -#define SPI_MEM_SCLKCNT_L_M ((SPI_MEM_SCLKCNT_L_V)<<(SPI_MEM_SCLKCNT_L_S)) -#define SPI_MEM_SCLKCNT_L_V 0xFF -#define SPI_MEM_SCLKCNT_L_S 0 - -#define SPI_MEM_FSM_REG(i) (REG_SPI_MEM_BASE(i) + 0x54) - -/* SPI_MEM_ST : RO ;bitpos:[2:0] ;default: 3'b0 ; */ - -/* Description: The status of SPI1 state machine. - * 0: idle state(IDLE), - * 1: preparation state(PREP), - * 2: send command state(CMD), - * 3: send address state(ADDR), - * 4: red data state(DIN), - * 5:write data state(DOUT), - * 6: wait state(DUMMY), - * 7: done state(DONE). - */ - -#define SPI_MEM_ST 0x00000007 -#define SPI_MEM_ST_M ((SPI_MEM_ST_V)<<(SPI_MEM_ST_S)) -#define SPI_MEM_ST_V 0x7 -#define SPI_MEM_ST_S 0 - -#define SPI_MEM_W0_REG(i) (REG_SPI_MEM_BASE(i) + 0x58) - -/* SPI_MEM_BUF0 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ - -/* Description: data buffer */ - -#define SPI_MEM_BUF0 0xFFFFFFFF -#define SPI_MEM_BUF0_M ((SPI_MEM_BUF0_V)<<(SPI_MEM_BUF0_S)) -#define SPI_MEM_BUF0_V 0xFFFFFFFF -#define SPI_MEM_BUF0_S 0 - -#define SPI_MEM_W1_REG(i) (REG_SPI_MEM_BASE(i) + 0x5C) - -/* SPI_MEM_BUF1 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ - -/* Description: data buffer */ - -#define SPI_MEM_BUF1 0xFFFFFFFF -#define SPI_MEM_BUF1_M ((SPI_MEM_BUF1_V)<<(SPI_MEM_BUF1_S)) -#define SPI_MEM_BUF1_V 0xFFFFFFFF -#define SPI_MEM_BUF1_S 0 - -#define SPI_MEM_W2_REG(i) (REG_SPI_MEM_BASE(i) + 0x60) - -/* SPI_MEM_BUF2 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ - -/* Description: data buffer */ - -#define SPI_MEM_BUF2 0xFFFFFFFF -#define SPI_MEM_BUF2_M ((SPI_MEM_BUF2_V)<<(SPI_MEM_BUF2_S)) -#define SPI_MEM_BUF2_V 0xFFFFFFFF -#define SPI_MEM_BUF2_S 0 - -#define SPI_MEM_W3_REG(i) (REG_SPI_MEM_BASE(i) + 0x64) - -/* SPI_MEM_BUF3 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ - -/* Description: data buffer */ - -#define SPI_MEM_BUF3 0xFFFFFFFF -#define SPI_MEM_BUF3_M ((SPI_MEM_BUF3_V)<<(SPI_MEM_BUF3_S)) -#define SPI_MEM_BUF3_V 0xFFFFFFFF -#define SPI_MEM_BUF3_S 0 - -#define SPI_MEM_W4_REG(i) (REG_SPI_MEM_BASE(i) + 0x68) - -/* SPI_MEM_BUF4 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ - -/* Description: data buffer */ - -#define SPI_MEM_BUF4 0xFFFFFFFF -#define SPI_MEM_BUF4_M ((SPI_MEM_BUF4_V)<<(SPI_MEM_BUF4_S)) -#define SPI_MEM_BUF4_V 0xFFFFFFFF -#define SPI_MEM_BUF4_S 0 - -#define SPI_MEM_W5_REG(i) (REG_SPI_MEM_BASE(i) + 0x6C) - -/* SPI_MEM_BUF5 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ - -/* Description: data buffer */ - -#define SPI_MEM_BUF5 0xFFFFFFFF -#define SPI_MEM_BUF5_M ((SPI_MEM_BUF5_V)<<(SPI_MEM_BUF5_S)) -#define SPI_MEM_BUF5_V 0xFFFFFFFF -#define SPI_MEM_BUF5_S 0 - -#define SPI_MEM_W6_REG(i) (REG_SPI_MEM_BASE(i) + 0x70) - -/* SPI_MEM_BUF6 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ - -/* Description: data buffer */ - -#define SPI_MEM_BUF6 0xFFFFFFFF -#define SPI_MEM_BUF6_M ((SPI_MEM_BUF6_V)<<(SPI_MEM_BUF6_S)) -#define SPI_MEM_BUF6_V 0xFFFFFFFF -#define SPI_MEM_BUF6_S 0 - -#define SPI_MEM_W7_REG(i) (REG_SPI_MEM_BASE(i) + 0x74) - -/* SPI_MEM_BUF7 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ - -/* Description: data buffer */ - -#define SPI_MEM_BUF7 0xFFFFFFFF -#define SPI_MEM_BUF7_M ((SPI_MEM_BUF7_V)<<(SPI_MEM_BUF7_S)) -#define SPI_MEM_BUF7_V 0xFFFFFFFF -#define SPI_MEM_BUF7_S 0 - -#define SPI_MEM_W8_REG(i) (REG_SPI_MEM_BASE(i) + 0x78) - -/* SPI_MEM_BUF8 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ - -/* Description: data buffer */ - -#define SPI_MEM_BUF8 0xFFFFFFFF -#define SPI_MEM_BUF8_M ((SPI_MEM_BUF8_V)<<(SPI_MEM_BUF8_S)) -#define SPI_MEM_BUF8_V 0xFFFFFFFF -#define SPI_MEM_BUF8_S 0 - -#define SPI_MEM_W9_REG(i) (REG_SPI_MEM_BASE(i) + 0x7C) - -/* SPI_MEM_BUF9 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ - -/* Description: data buffer */ - -#define SPI_MEM_BUF9 0xFFFFFFFF -#define SPI_MEM_BUF9_M ((SPI_MEM_BUF9_V)<<(SPI_MEM_BUF9_S)) -#define SPI_MEM_BUF9_V 0xFFFFFFFF -#define SPI_MEM_BUF9_S 0 - -#define SPI_MEM_W10_REG(i) (REG_SPI_MEM_BASE(i) + 0x80) - -/* SPI_MEM_BUF10 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ - -/* Description: data buffer */ - -#define SPI_MEM_BUF10 0xFFFFFFFF -#define SPI_MEM_BUF10_M ((SPI_MEM_BUF10_V)<<(SPI_MEM_BUF10_S)) -#define SPI_MEM_BUF10_V 0xFFFFFFFF -#define SPI_MEM_BUF10_S 0 - -#define SPI_MEM_W11_REG(i) (REG_SPI_MEM_BASE(i) + 0x84) - -/* SPI_MEM_BUF11 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ - -/* Description: data buffer */ - -#define SPI_MEM_BUF11 0xFFFFFFFF -#define SPI_MEM_BUF11_M ((SPI_MEM_BUF11_V)<<(SPI_MEM_BUF11_S)) -#define SPI_MEM_BUF11_V 0xFFFFFFFF -#define SPI_MEM_BUF11_S 0 - -#define SPI_MEM_W12_REG(i) (REG_SPI_MEM_BASE(i) + 0x88) - -/* SPI_MEM_BUF12 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ - -/* Description: data buffer */ - -#define SPI_MEM_BUF12 0xFFFFFFFF -#define SPI_MEM_BUF12_M ((SPI_MEM_BUF12_V)<<(SPI_MEM_BUF12_S)) -#define SPI_MEM_BUF12_V 0xFFFFFFFF -#define SPI_MEM_BUF12_S 0 - -#define SPI_MEM_W13_REG(i) (REG_SPI_MEM_BASE(i) + 0x8C) - -/* SPI_MEM_BUF13 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ - -/* Description: data buffer */ - -#define SPI_MEM_BUF13 0xFFFFFFFF -#define SPI_MEM_BUF13_M ((SPI_MEM_BUF13_V)<<(SPI_MEM_BUF13_S)) -#define SPI_MEM_BUF13_V 0xFFFFFFFF -#define SPI_MEM_BUF13_S 0 - -#define SPI_MEM_W14_REG(i) (REG_SPI_MEM_BASE(i) + 0x90) - -/* SPI_MEM_BUF14 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ - -/* Description: data buffer */ - -#define SPI_MEM_BUF14 0xFFFFFFFF -#define SPI_MEM_BUF14_M ((SPI_MEM_BUF14_V)<<(SPI_MEM_BUF14_S)) -#define SPI_MEM_BUF14_V 0xFFFFFFFF -#define SPI_MEM_BUF14_S 0 - -#define SPI_MEM_W15_REG(i) (REG_SPI_MEM_BASE(i) + 0x94) - -/* SPI_MEM_BUF15 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ - -/* Description: data buffer */ - -#define SPI_MEM_BUF15 0xFFFFFFFF -#define SPI_MEM_BUF15_M ((SPI_MEM_BUF15_V)<<(SPI_MEM_BUF15_S)) -#define SPI_MEM_BUF15_V 0xFFFFFFFF -#define SPI_MEM_BUF15_S 0 - -#define SPI_MEM_FLASH_WAITI_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x98) - -/* SPI_MEM_WAITI_DUMMY_CYCLELEN : R/W ;bitpos:[15:10] ;default: 6'h0 ; */ - -/* Description: The dummy cycle length when wait flash idle(RDSR). */ - -#define SPI_MEM_WAITI_DUMMY_CYCLELEN 0x0000003F -#define SPI_MEM_WAITI_DUMMY_CYCLELEN_M ((SPI_MEM_WAITI_DUMMY_CYCLELEN_V)<<(SPI_MEM_WAITI_DUMMY_CYCLELEN_S)) -#define SPI_MEM_WAITI_DUMMY_CYCLELEN_V 0x3F -#define SPI_MEM_WAITI_DUMMY_CYCLELEN_S 10 - -/* SPI_MEM_WAITI_CMD : R/W ;bitpos:[9:2] ;default: 8'h05 ; */ - -/* Description: The command value of auto wait flash idle transfer(RDSR). */ - -#define SPI_MEM_WAITI_CMD 0x000000FF -#define SPI_MEM_WAITI_CMD_M ((SPI_MEM_WAITI_CMD_V)<<(SPI_MEM_WAITI_CMD_S)) -#define SPI_MEM_WAITI_CMD_V 0xFF -#define SPI_MEM_WAITI_CMD_S 2 - -/* SPI_MEM_WAITI_DUMMY : R/W ;bitpos:[1] ;default: 1'b0 ; */ - -/* Description: Set this bit to enable DUMMY phase in auto wait flash idle - * transfer(RDSR). - */ - -#define SPI_MEM_WAITI_DUMMY (BIT(1)) -#define SPI_MEM_WAITI_DUMMY_M (BIT(1)) -#define SPI_MEM_WAITI_DUMMY_V 0x1 -#define SPI_MEM_WAITI_DUMMY_S 1 - -/* SPI_MEM_WAITI_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ - -/* Description: Set this bit to enable auto-waiting flash idle operation when - * PP/SE/BE/CE/WRSR/PES command is sent. - */ - -#define SPI_MEM_WAITI_EN (BIT(0)) -#define SPI_MEM_WAITI_EN_M (BIT(0)) -#define SPI_MEM_WAITI_EN_V 0x1 -#define SPI_MEM_WAITI_EN_S 0 - -#define SPI_MEM_FLASH_SUS_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x9C) - -/* SPI_MEM_PESR_IDLE_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */ - -/* Description: - * 1: Separate PER flash wait idle and PES flash wait idle. - * 0: Not separate. - */ - -#define SPI_MEM_PESR_IDLE_EN (BIT(5)) -#define SPI_MEM_PESR_IDLE_EN_M (BIT(5)) -#define SPI_MEM_PESR_IDLE_EN_V 0x1 -#define SPI_MEM_PESR_IDLE_EN_S 5 - -/* SPI_MEM_PES_PER_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ - -/* Description: Set this bit to enable PES transfer trigger PES transfer - * option. - */ - -#define SPI_MEM_PES_PER_EN (BIT(4)) -#define SPI_MEM_PES_PER_EN_M (BIT(4)) -#define SPI_MEM_PES_PER_EN_V 0x1 -#define SPI_MEM_PES_PER_EN_S 4 - -/* SPI_MEM_FLASH_PES_WAIT_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ - -/* Description: Set this bit to add delay time after program erase - * suspend(PES) command is sent. - */ - -#define SPI_MEM_FLASH_PES_WAIT_EN (BIT(3)) -#define SPI_MEM_FLASH_PES_WAIT_EN_M (BIT(3)) -#define SPI_MEM_FLASH_PES_WAIT_EN_V 0x1 -#define SPI_MEM_FLASH_PES_WAIT_EN_S 3 - -/* SPI_MEM_FLASH_PER_WAIT_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ - -/* Description: Set this bit to add delay time after program erase resume - * (PER) is sent. - */ - -#define SPI_MEM_FLASH_PER_WAIT_EN (BIT(2)) -#define SPI_MEM_FLASH_PER_WAIT_EN_M (BIT(2)) -#define SPI_MEM_FLASH_PER_WAIT_EN_V 0x1 -#define SPI_MEM_FLASH_PER_WAIT_EN_S 2 - -/* SPI_MEM_FLASH_PES : R/W/SS/SC ;bitpos:[1] ;default: 1'b0 ; */ - -/* Description: program erase suspend bit, program erase suspend operation - * will be triggered when the bit is set. The bit will be cleared once the - * operation done. - * 1: enable - * 0:disable. - */ - -#define SPI_MEM_FLASH_PES (BIT(1)) -#define SPI_MEM_FLASH_PES_M (BIT(1)) -#define SPI_MEM_FLASH_PES_V 0x1 -#define SPI_MEM_FLASH_PES_S 1 - -/* SPI_MEM_FLASH_PER : R/W/SS/SC ;bitpos:[0] ;default: 1'b0 ; */ - -/* Description: program erase resume bit, program erase suspend operation - * will be triggered when the bit is set. The bit will be cleared once the - * operation done. - * 1: enable - * 0: disable. - */ - -#define SPI_MEM_FLASH_PER (BIT(0)) -#define SPI_MEM_FLASH_PER_M (BIT(0)) -#define SPI_MEM_FLASH_PER_V 0x1 -#define SPI_MEM_FLASH_PER_S 0 - -#define SPI_MEM_FLASH_SUS_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0xA0) - -/* SPI_MEM_FLASH_PES_COMMAND : R/W ;bitpos:[16:9] ;default: 8'h75 ; */ - -/* Description: Program/Erase suspend command value. */ - -#define SPI_MEM_FLASH_PES_COMMAND 0x000000FF -#define SPI_MEM_FLASH_PES_COMMAND_M ((SPI_MEM_FLASH_PES_COMMAND_V)<<(SPI_MEM_FLASH_PES_COMMAND_S)) -#define SPI_MEM_FLASH_PES_COMMAND_V 0xFF -#define SPI_MEM_FLASH_PES_COMMAND_S 9 - -/* SPI_MEM_FLASH_PER_COMMAND : R/W ;bitpos:[8:1] ;default: 8'h7a ; */ - -/* Description: Program/Erase resume command value. */ - -#define SPI_MEM_FLASH_PER_COMMAND 0x000000FF -#define SPI_MEM_FLASH_PER_COMMAND_M ((SPI_MEM_FLASH_PER_COMMAND_V)<<(SPI_MEM_FLASH_PER_COMMAND_S)) -#define SPI_MEM_FLASH_PER_COMMAND_V 0xFF -#define SPI_MEM_FLASH_PER_COMMAND_S 1 - -/* SPI_MEM_FLASH_PES_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ - -/* Description: Set this bit to enable auto-suspend function. */ - -#define SPI_MEM_FLASH_PES_EN (BIT(0)) -#define SPI_MEM_FLASH_PES_EN_M (BIT(0)) -#define SPI_MEM_FLASH_PES_EN_V 0x1 -#define SPI_MEM_FLASH_PES_EN_S 0 - -#define SPI_MEM_SUS_STATUS_REG(i) (REG_SPI_MEM_BASE(i) + 0xA4) - -/* SPI_MEM_FLASH_PES_DLY_256 : R/W ;bitpos:[6] ;default: 1'b0 ; */ - -/* Description: Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. - * 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) - * SPI_CLK cycles after PES command is sent. - * 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after - * PES command is sent. - */ - -#define SPI_MEM_FLASH_PES_DLY_256 (BIT(6)) -#define SPI_MEM_FLASH_PES_DLY_256_M (BIT(6)) -#define SPI_MEM_FLASH_PES_DLY_256_V 0x1 -#define SPI_MEM_FLASH_PES_DLY_256_S 6 - -/* SPI_MEM_FLASH_PER_DLY_256 : R/W ;bitpos:[5] ;default: 1'b0 ; */ - -/* Description: Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. - * 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after - * PER command is sent. - * 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after - * PER command is sent. - */ - -#define SPI_MEM_FLASH_PER_DLY_256 (BIT(5)) -#define SPI_MEM_FLASH_PER_DLY_256_M (BIT(5)) -#define SPI_MEM_FLASH_PER_DLY_256_V 0x1 -#define SPI_MEM_FLASH_PER_DLY_256_S 5 - -/* SPI_MEM_FLASH_DP_DLY_256 : R/W ;bitpos:[4] ;default: 1'b0 ; */ - -/* Description: - * 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK - * cycles after DP command is sent. - * 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP - * command is sent. - */ - -#define SPI_MEM_FLASH_DP_DLY_256 (BIT(4)) -#define SPI_MEM_FLASH_DP_DLY_256_M (BIT(4)) -#define SPI_MEM_FLASH_DP_DLY_256_V 0x1 -#define SPI_MEM_FLASH_DP_DLY_256_S 4 - -/* SPI_MEM_FLASH_RES_DLY_256 : R/W ;bitpos:[3] ;default: 1'b0 ; */ - -/* Description: - * 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK - * cycles after RES command is sent. - * 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after - * RES command is sent. - */ - -#define SPI_MEM_FLASH_RES_DLY_256 (BIT(3)) -#define SPI_MEM_FLASH_RES_DLY_256_M (BIT(3)) -#define SPI_MEM_FLASH_RES_DLY_256_V 0x1 -#define SPI_MEM_FLASH_RES_DLY_256_S 3 - -/* SPI_MEM_FLASH_HPM_DLY_256 : R/W ;bitpos:[2] ;default: 1'b0 ; */ - -/* Description: - * 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK - * cycles after HPM command is sent. - * 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after - * HPM command is sent. - */ - -#define SPI_MEM_FLASH_HPM_DLY_256 (BIT(2)) -#define SPI_MEM_FLASH_HPM_DLY_256_M (BIT(2)) -#define SPI_MEM_FLASH_HPM_DLY_256_V 0x1 -#define SPI_MEM_FLASH_HPM_DLY_256_S 2 - -/* SPI_MEM_FLASH_SUS : R/W/SS/SC ;bitpos:[0] ;default: 1'h0 ; */ - -/* Description: The status of flash suspend. This bit is set when PES command - * is sent, and cleared when PER is sent. Only used in SPI1. - */ - -#define SPI_MEM_FLASH_SUS (BIT(0)) -#define SPI_MEM_FLASH_SUS_M (BIT(0)) -#define SPI_MEM_FLASH_SUS_V 0x1 -#define SPI_MEM_FLASH_SUS_S 0 - -#define SPI_MEM_TIMING_CALI_REG(i) (REG_SPI_MEM_BASE(i) + 0xA8) - -/* SPI_MEM_EXTRA_DUMMY_CYCLELEN : R/W ;bitpos:[4:2] ;default: 3'd0 ; */ - -/* Description: Extra SPI_CLK cycles added in DUMMY phase for timing - * compensation. Active when SPI_MEM_TIMING_CALI bit is set. - */ - -#define SPI_MEM_EXTRA_DUMMY_CYCLELEN 0x00000007 -#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_M ((SPI_MEM_EXTRA_DUMMY_CYCLELEN_V)<<(SPI_MEM_EXTRA_DUMMY_CYCLELEN_S)) -#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_V 0x7 -#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_S 2 - -/* SPI_MEM_TIMING_CALI : R/W ;bitpos:[1] ;default: 1'b0 ; */ - -/* Description: Set this bit to add extra SPI_CLK cycles in DUMMY phase for - * all reading operations. - */ - -#define SPI_MEM_TIMING_CALI (BIT(1)) -#define SPI_MEM_TIMING_CALI_M (BIT(1)) -#define SPI_MEM_TIMING_CALI_V 0x1 -#define SPI_MEM_TIMING_CALI_S 1 - -/* SPI_MEM_TIMING_CLK_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ - -/* Description: Set this bit to power on HCLK. When PLL is powered on, the - * frequency of HCLK equals to that of PLL. Otherwise, the frequency equals - * to that of XTAL. - */ - -#define SPI_MEM_TIMING_CLK_ENA (BIT(0)) -#define SPI_MEM_TIMING_CLK_ENA_M (BIT(0)) -#define SPI_MEM_TIMING_CLK_ENA_V 0x1 -#define SPI_MEM_TIMING_CLK_ENA_S 0 - -#define SPI_MEM_DIN_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0xAC) - -/* SPI_MEM_DINS_MODE : R/W ;bitpos:[26:24] ;default: 3'h0 ; */ - -/* Description: SPI_DQS input delay mode. - * 0: No delay. - * 1: Delay for (SPI_MEM_DINS_NUM+1) cycles at MSPI_CORE_CLK negative edge. - * 2: Delay for (SPI_MEM_DINS_NUM+1) cycles at HCLK positive edge and one - * cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DINS_NUM+1) - * cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. - * 4: Delay for (SPI_MEM_DINS_NUM+1) cycles at HCLK negative edge and one - * cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DINS_NUM+1) - * cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. - */ - -#define SPI_MEM_DINS_MODE 0x00000007 -#define SPI_MEM_DINS_MODE_M ((SPI_MEM_DINS_MODE_V)<<(SPI_MEM_DINS_MODE_S)) -#define SPI_MEM_DINS_MODE_V 0x7 -#define SPI_MEM_DINS_MODE_S 24 - -/* SPI_MEM_DIN7_MODE : R/W ;bitpos:[23:21] ;default: 3'h0 ; */ - -/* Description: SPI_IO7 input delay mode. - * 0: No delay. - * 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. - * 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one - * cycle at MSPI_CORE_CLK positive edge. - * 3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one - * cycle at MSPI_CORE_CLK negative edge. - * 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one - * cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) - * cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. - */ - -#define SPI_MEM_DIN7_MODE 0x00000007 -#define SPI_MEM_DIN7_MODE_M ((SPI_MEM_DIN7_MODE_V)<<(SPI_MEM_DIN7_MODE_S)) -#define SPI_MEM_DIN7_MODE_V 0x7 -#define SPI_MEM_DIN7_MODE_S 21 - -/* SPI_MEM_DIN6_MODE : R/W ;bitpos:[20:18] ;default: 3'h0 ; */ - -/* Description: SPI_IO6 input delay mode. - * 0: No delay. - * 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. - * 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one - * cycle at MSPI_CORE_CLK positive edge. - * 3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one - * cycle at MSPI_CORE_CLK negative edge. - * 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one - * cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) - * cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. - */ - -#define SPI_MEM_DIN6_MODE 0x00000007 -#define SPI_MEM_DIN6_MODE_M ((SPI_MEM_DIN6_MODE_V)<<(SPI_MEM_DIN6_MODE_S)) -#define SPI_MEM_DIN6_MODE_V 0x7 -#define SPI_MEM_DIN6_MODE_S 18 - -/* SPI_MEM_DIN5_MODE : R/W ;bitpos:[17:15] ;default: 3'h0 ; */ - -/* Description: SPI_IO5 input delay mode. - * 0: No delay. - * 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. - * 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one - * cycle at MSPI_CORE_CLK positive edge. 3: Delay for - * (SPI_MEM_DIN$n_NUM+1) - * cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative - * edge. - * 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one - * cycle at MSPI_CORE_CLK positive edge. - * 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one - * cycle at MSPI_CORE_CLK negative edge. - */ - -#define SPI_MEM_DIN5_MODE 0x00000007 -#define SPI_MEM_DIN5_MODE_M ((SPI_MEM_DIN5_MODE_V)<<(SPI_MEM_DIN5_MODE_S)) -#define SPI_MEM_DIN5_MODE_V 0x7 -#define SPI_MEM_DIN5_MODE_S 15 - -/* SPI_MEM_DIN4_MODE : R/W ;bitpos:[14:12] ;default: 3'h0 ; */ - -/* Description: SPI_IO4 input delay mode. - * 0: No delay. - * 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. - * 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one - * cycle at MSPI_CORE_CLK positive edge. - * 3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one - * cycle at MSPI_CORE_CLK negative edge. - * 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one - * cycle at MSPI_CORE_CLK positive edge. - * 5: Delay for (SPI_MEM_DIN$n_NUM+1) - * cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. - */ - -#define SPI_MEM_DIN4_MODE 0x00000007 -#define SPI_MEM_DIN4_MODE_M ((SPI_MEM_DIN4_MODE_V)<<(SPI_MEM_DIN4_MODE_S)) -#define SPI_MEM_DIN4_MODE_V 0x7 -#define SPI_MEM_DIN4_MODE_S 12 - -/* SPI_MEM_DIN3_MODE : R/W ;bitpos:[11:9] ;default: 3'h0 ; */ - -/* Description: SPI_HD input delay mode. - * 0: No delay. - * 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. - * 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one - * cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN$n_NUM+1) - * cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. - * 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one - * cycle at MSPI_CORE_CLK positive edge. - * 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one - * cycle at MSPI_CORE_CLK negative edge. - */ - -#define SPI_MEM_DIN3_MODE 0x00000007 -#define SPI_MEM_DIN3_MODE_M ((SPI_MEM_DIN3_MODE_V)<<(SPI_MEM_DIN3_MODE_S)) -#define SPI_MEM_DIN3_MODE_V 0x7 -#define SPI_MEM_DIN3_MODE_S 9 - -/* SPI_MEM_DIN2_MODE : R/W ;bitpos:[8:6] ;default: 3'h0 ; */ - -/* Description: SPI_WP input delay mode. - * 0: No delay. - * 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. - * 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one - * cycle at MSPI_CORE_CLK positive edge. - * 3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one - * cycle at MSPI_CORE_CLK negative edge. - * 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one - * cycle at MSPI_CORE_CLK positive edge. - * 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one - * cycle at MSPI_CORE_CLK negative edge. - */ - -#define SPI_MEM_DIN2_MODE 0x00000007 -#define SPI_MEM_DIN2_MODE_M ((SPI_MEM_DIN2_MODE_V)<<(SPI_MEM_DIN2_MODE_S)) -#define SPI_MEM_DIN2_MODE_V 0x7 -#define SPI_MEM_DIN2_MODE_S 6 - -/* SPI_MEM_DIN1_MODE : R/W ;bitpos:[5:3] ;default: 3'h0 ; */ - -/* Description: SPI_Q input delay mode. - * 0: No delay. - * 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. - * 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one - * cycle at MSPI_CORE_CLK positive edge. - * 3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one - * cycle at MSPI_CORE_CLK negative edge. - * 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one - * cycle at MSPI_CORE_CLK positive edge. - * 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one - * cycle at MSPI_CORE_CLK negative edge. - */ - -#define SPI_MEM_DIN1_MODE 0x00000007 -#define SPI_MEM_DIN1_MODE_M ((SPI_MEM_DIN1_MODE_V)<<(SPI_MEM_DIN1_MODE_S)) -#define SPI_MEM_DIN1_MODE_V 0x7 -#define SPI_MEM_DIN1_MODE_S 3 - -/* SPI_MEM_DIN0_MODE : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ - -/* Description: SPI_D input delay mode. - * 0: No delay. - * 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. - * 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one - * cycle at MSPI_CORE_CLK positive edge. - * 3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one - * cycle at MSPI_CORE_CLK nega tive edge. - * 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and o ne - * cycle at MSPI_CORE_CLK positive edge. - * 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one - * cycle at MSPI_CORE_CLK negative edge. - */ - -#define SPI_MEM_DIN0_MODE 0x00000007 -#define SPI_MEM_DIN0_MODE_M ((SPI_MEM_DIN0_MODE_V)<<(SPI_MEM_DIN0_MODE_S)) -#define SPI_MEM_DIN0_MODE_V 0x7 -#define SPI_MEM_DIN0_MODE_S 0 - -#define SPI_MEM_DIN_NUM_REG(i) (REG_SPI_MEM_BASE(i) + 0xB0) - -/* SPI_MEM_DINS_NUM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */ - -/* Description: SPI_DQS input delay number. */ - -#define SPI_MEM_DINS_NUM 0x00000003 -#define SPI_MEM_DINS_NUM_M ((SPI_MEM_DINS_NUM_V)<<(SPI_MEM_DINS_NUM_S)) -#define SPI_MEM_DINS_NUM_V 0x3 -#define SPI_MEM_DINS_NUM_S 16 - -/* SPI_MEM_DIN7_NUM : R/W ;bitpos:[15:14] ;default: 2'h0 ; */ - -/* Description: SPI_IO7 input delay number. */ - -#define SPI_MEM_DIN7_NUM 0x00000003 -#define SPI_MEM_DIN7_NUM_M ((SPI_MEM_DIN7_NUM_V)<<(SPI_MEM_DIN7_NUM_S)) -#define SPI_MEM_DIN7_NUM_V 0x3 -#define SPI_MEM_DIN7_NUM_S 14 - -/* SPI_MEM_DIN6_NUM : R/W ;bitpos:[13:12] ;default: 2'h0 ; */ - -/* Description: SPI_IO6 input delay number. */ - -#define SPI_MEM_DIN6_NUM 0x00000003 -#define SPI_MEM_DIN6_NUM_M ((SPI_MEM_DIN6_NUM_V)<<(SPI_MEM_DIN6_NUM_S)) -#define SPI_MEM_DIN6_NUM_V 0x3 -#define SPI_MEM_DIN6_NUM_S 12 - -/* SPI_MEM_DIN5_NUM : R/W ;bitpos:[11:10] ;default: 2'h0 ; */ - -/* Description: SPI_IO5 input delay number. */ - -#define SPI_MEM_DIN5_NUM 0x00000003 -#define SPI_MEM_DIN5_NUM_M ((SPI_MEM_DIN5_NUM_V)<<(SPI_MEM_DIN5_NUM_S)) -#define SPI_MEM_DIN5_NUM_V 0x3 -#define SPI_MEM_DIN5_NUM_S 10 - -/* SPI_MEM_DIN4_NUM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */ - -/* Description: SPI_IO4 input delay number. */ - -#define SPI_MEM_DIN4_NUM 0x00000003 -#define SPI_MEM_DIN4_NUM_M ((SPI_MEM_DIN4_NUM_V)<<(SPI_MEM_DIN4_NUM_S)) -#define SPI_MEM_DIN4_NUM_V 0x3 -#define SPI_MEM_DIN4_NUM_S 8 - -/* SPI_MEM_DIN3_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */ - -/* Description: SPI_HD input delay number. */ - -#define SPI_MEM_DIN3_NUM 0x00000003 -#define SPI_MEM_DIN3_NUM_M ((SPI_MEM_DIN3_NUM_V)<<(SPI_MEM_DIN3_NUM_S)) -#define SPI_MEM_DIN3_NUM_V 0x3 -#define SPI_MEM_DIN3_NUM_S 6 - -/* SPI_MEM_DIN2_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */ - -/* Description: SPI_WP input delay number. */ - -#define SPI_MEM_DIN2_NUM 0x00000003 -#define SPI_MEM_DIN2_NUM_M ((SPI_MEM_DIN2_NUM_V)<<(SPI_MEM_DIN2_NUM_S)) -#define SPI_MEM_DIN2_NUM_V 0x3 -#define SPI_MEM_DIN2_NUM_S 4 - -/* SPI_MEM_DIN1_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */ - -/* Description: SPI_Q input delay number. */ - -#define SPI_MEM_DIN1_NUM 0x00000003 -#define SPI_MEM_DIN1_NUM_M ((SPI_MEM_DIN1_NUM_V)<<(SPI_MEM_DIN1_NUM_S)) -#define SPI_MEM_DIN1_NUM_V 0x3 -#define SPI_MEM_DIN1_NUM_S 2 - -/* SPI_MEM_DIN0_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ - -/* Description: SPI_D input delay number. */ - -#define SPI_MEM_DIN0_NUM 0x00000003 -#define SPI_MEM_DIN0_NUM_M ((SPI_MEM_DIN0_NUM_V)<<(SPI_MEM_DIN0_NUM_S)) -#define SPI_MEM_DIN0_NUM_V 0x3 -#define SPI_MEM_DIN0_NUM_S 0 - -#define SPI_MEM_DOUT_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0xB4) - -/* SPI_MEM_DOUTS_MODE : R/W ;bitpos:[8] ;default: 1'h0 ; */ - -/* Description: SPI_DQS output delay mode. - * 0: No delay. - * 1: Delay one cycle at MSPI_CORE_CLK negative edge. - */ - -#define SPI_MEM_DOUTS_MODE (BIT(8)) -#define SPI_MEM_DOUTS_MODE_M (BIT(8)) -#define SPI_MEM_DOUTS_MODE_V 0x1 -#define SPI_MEM_DOUTS_MODE_S 8 - -/* SPI_MEM_DOUT7_MODE : R/W ;bitpos:[7] ;default: 1'h0 ; */ - -/* Description: SPI_IO7 output delay mode. - * 0: No delay. - * 1: Delay one cycle at MSPI_CORE_CLK negative edge. - */ - -#define SPI_MEM_DOUT7_MODE (BIT(7)) -#define SPI_MEM_DOUT7_MODE_M (BIT(7)) -#define SPI_MEM_DOUT7_MODE_V 0x1 -#define SPI_MEM_DOUT7_MODE_S 7 - -/* SPI_MEM_DOUT6_MODE : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -/* Description: SPI_IO6 output delay mode. - * 0: No delay. - * 1: Delay one cycle at MSPI_CORE_CLK negative edge. - */ - -#define SPI_MEM_DOUT6_MODE (BIT(6)) -#define SPI_MEM_DOUT6_MODE_M (BIT(6)) -#define SPI_MEM_DOUT6_MODE_V 0x1 -#define SPI_MEM_DOUT6_MODE_S 6 - -/* SPI_MEM_DOUT5_MODE : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -/* Description: SPI_IO5 output delay mode. - * 0: No delay. - * 1: Delay one cycle at MSPI_CORE_CLK negative edge. - */ - -#define SPI_MEM_DOUT5_MODE (BIT(5)) -#define SPI_MEM_DOUT5_MODE_M (BIT(5)) -#define SPI_MEM_DOUT5_MODE_V 0x1 -#define SPI_MEM_DOUT5_MODE_S 5 - -/* SPI_MEM_DOUT4_MODE : R/W ;bitpos:[4] ;default: 1'h0 ; */ - -/* Description: SPI_IO4 output delay mode. - * 0: No delay. - * 1: Delay one cycle at MSPI_CORE_CLK negative edge. - */ - -#define SPI_MEM_DOUT4_MODE (BIT(4)) -#define SPI_MEM_DOUT4_MODE_M (BIT(4)) -#define SPI_MEM_DOUT4_MODE_V 0x1 -#define SPI_MEM_DOUT4_MODE_S 4 - -/* SPI_MEM_DOUT3_MODE : R/W ;bitpos:[3] ;default: 1'h0 ; */ - -/* Description: SPI_HD output delay mode. - * 0: No delay. - * 1: Delay one cycle at MSPI_CORE_CLK negative edge. - */ - -#define SPI_MEM_DOUT3_MODE (BIT(3)) -#define SPI_MEM_DOUT3_MODE_M (BIT(3)) -#define SPI_MEM_DOUT3_MODE_V 0x1 -#define SPI_MEM_DOUT3_MODE_S 3 - -/* SPI_MEM_DOUT2_MODE : R/W ;bitpos:[2] ;default: 1'h0 ; */ - -/* Description: SPI_WP output delay mode. - * 0: No delay. - * 1: Delay one cycle at MSPI_CORE_CLK negative edge. - */ - -#define SPI_MEM_DOUT2_MODE (BIT(2)) -#define SPI_MEM_DOUT2_MODE_M (BIT(2)) -#define SPI_MEM_DOUT2_MODE_V 0x1 -#define SPI_MEM_DOUT2_MODE_S 2 - -/* SPI_MEM_DOUT1_MODE : R/W ;bitpos:[1] ;default: 1'h0 ; */ - -/* Description: SPI_Q output delay mode. - * 0: No delay. - * 1: Delay one cycle at MSPI_CORE_CLK negative edge. - */ - -#define SPI_MEM_DOUT1_MODE (BIT(1)) -#define SPI_MEM_DOUT1_MODE_M (BIT(1)) -#define SPI_MEM_DOUT1_MODE_V 0x1 -#define SPI_MEM_DOUT1_MODE_S 1 - -/* SPI_MEM_DOUT0_MODE : R/W ;bitpos:[0] ;default: 1'h0 ; */ - -/* Description: SPI_D output delay mode. - * 0: No delay. - * 1: Delay one cycle at MSPI_CORE_CLK negative edge. - */ - -#define SPI_MEM_DOUT0_MODE (BIT(0)) -#define SPI_MEM_DOUT0_MODE_M (BIT(0)) -#define SPI_MEM_DOUT0_MODE_V 0x1 -#define SPI_MEM_DOUT0_MODE_S 0 - -#define SPI_MEM_SPI_SMEM_TIMING_CALI_REG(i) (REG_SPI_MEM_BASE(i) + 0xBC) - -/* SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN: R/W ;bitpos:[4:2]; default: 3'd0; */ - -/* Description: Extra SPI_CLK cycles added in DUMMY phase for timing - * compensation, when SPI0 accesses to Ext_RAM. Active when - * SPI_SMEM_TIMING_CALI bit is set. - */ - -#define SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN 0x00000007 -#define SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_M ((SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V)<<(SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S)) -#define SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V 0x7 -#define SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S 2 - -/* SPI_MEM_SPI_SMEM_TIMING_CALI : R/W ;bitpos:[1] ;default: 1'b0 ; */ - -/* Description: Set this bit to add extra SPI_CLK cycles in DUMMY phase for - * all reading operations. - */ - -#define SPI_MEM_SPI_SMEM_TIMING_CALI (BIT(1)) -#define SPI_MEM_SPI_SMEM_TIMING_CALI_M (BIT(1)) -#define SPI_MEM_SPI_SMEM_TIMING_CALI_V 0x1 -#define SPI_MEM_SPI_SMEM_TIMING_CALI_S 1 - -/* SPI_MEM_SPI_SMEM_TIMING_CLK_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ - -/* Description: Set this bit to power on HCLK. When PLL is powered on, the - * frequency of HCLK equals to that of PLL. Otherwise, the frequency equals - * to that of XTAL. - */ - -#define SPI_MEM_SPI_SMEM_TIMING_CLK_ENA (BIT(0)) -#define SPI_MEM_SPI_SMEM_TIMING_CLK_ENA_M (BIT(0)) -#define SPI_MEM_SPI_SMEM_TIMING_CLK_ENA_V 0x1 -#define SPI_MEM_SPI_SMEM_TIMING_CLK_ENA_S 0 - -#define SPI_MEM_SPI_SMEM_DIN_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0xC0) - -/* SPI_MEM_SPI_SMEM_DINS_MODE : R/W ;bitpos:[26:24] ;default: 3'h0 ; */ - -/* Description: SPI_DQS input delay mode. - * 0: No delay. - * 1: Delay for (SPI_SMEM_DINS_NUM+1) cycles at MSPI_CORE_CLK negative edge. - * 2: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK positive edge and one - * cycle at MSPI_CORE_CLK positive edge. - * 3: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK positive edge and one - * cycle at MSPI_CORE_CLK negative edge. - * 4: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK negative edge and one - * cycle at MSPI_CORE_CLK positive edge. - * 5: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK negative edge and one - * cycle at MSPI_CORE_CLK negative edge. - */ - -#define SPI_MEM_SPI_SMEM_DINS_MODE 0x00000007 -#define SPI_MEM_SPI_SMEM_DINS_MODE_M ((SPI_MEM_SPI_SMEM_DINS_MODE_V)<<(SPI_MEM_SPI_SMEM_DINS_MODE_S)) -#define SPI_MEM_SPI_SMEM_DINS_MODE_V 0x7 -#define SPI_MEM_SPI_SMEM_DINS_MODE_S 24 - -/* SPI_MEM_SPI_SMEM_DIN7_MODE : R/W ;bitpos:[23:21] ;default: 3'h0 ; */ - -/* Description: SPI_IO7 input delay mode. - * 0: No delay. - * 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. - * 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one - * cycle at MSPI_CORE_CLK positive edge. - * 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one - * cycle at MSPI_CORE_CLK negative edge. - * 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one - * cycle at MSPI_CORE_CLK positive edge. - * 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one - * cycle at MSPI_CORE_CLK negative edge. - */ - -#define SPI_MEM_SPI_SMEM_DIN7_MODE 0x00000007 -#define SPI_MEM_SPI_SMEM_DIN7_MODE_M ((SPI_MEM_SPI_SMEM_DIN7_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN7_MODE_S)) -#define SPI_MEM_SPI_SMEM_DIN7_MODE_V 0x7 -#define SPI_MEM_SPI_SMEM_DIN7_MODE_S 21 - -/* SPI_MEM_SPI_SMEM_DIN6_MODE : R/W ;bitpos:[20:18] ;default: 3'h0 ; */ - -/* Description: SPI_IO6 input delay mode. - * 0: No delay. - * 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. - * 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one - * cycle at MSPI_CORE_CLK positive edge. - * 3: Delay for (S PI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one - * cycle at MSPI_CORE_CLK negative edge. - * 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one - * cycle at MSPI_CORE_CLK positive edge. - * 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one - * cycle at MSPI_CORE_CLK negative edge. - */ - -#define SPI_MEM_SPI_SMEM_DIN6_MODE 0x00000007 -#define SPI_MEM_SPI_SMEM_DIN6_MODE_M ((SPI_MEM_SPI_SMEM_DIN6_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN6_MODE_S)) -#define SPI_MEM_SPI_SMEM_DIN6_MODE_V 0x7 -#define SPI_MEM_SPI_SMEM_DIN6_MODE_S 18 - -/* SPI_MEM_SPI_SMEM_DIN5_MODE : R/W ;bitpos:[17:15] ;default: 3'h0 ; */ - -/* Description: SPI_IO5 input delay mode. - * 0: No delay. - * 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. - * 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one - * cycle at MSPI_CORE_CLK positive edge. - * 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one - * cycle at MSPI_CORE_CLK negative edge. - * 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one - * cycle at MSPI_CORE_CLK positive edge. - * 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one - * cycle at MSPI_CORE_CLK negative edge. - */ - -#define SPI_MEM_SPI_SMEM_DIN5_MODE 0x00000007 -#define SPI_MEM_SPI_SMEM_DIN5_MODE_M ((SPI_MEM_SPI_SMEM_DIN5_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN5_MODE_S)) -#define SPI_MEM_SPI_SMEM_DIN5_MODE_V 0x7 -#define SPI_MEM_SPI_SMEM_DIN5_MODE_S 15 - -/* SPI_MEM_SPI_SMEM_DIN4_MODE : R/W ;bitpos:[14:12] ;default: 3'h0 ; */ - -/* Description: SPI_IO4 input delay mode. - * 0: No delay. - * 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. - * 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one - * cycle at MSPI_CORE_CLK positive edge. - * 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one - * cycle at MSPI_CORE_CLK negative edge. - * 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one - * cycle at MSPI_CORE_CLK positive edge. - * 5: Delay for (SPI_SMEM_DIN$n_NUM+ 1) cycles at HCLK negative edge and one - * cycle at MSPI_CORE_CLK negative edge. - */ - -#define SPI_MEM_SPI_SMEM_DIN4_MODE 0x00000007 -#define SPI_MEM_SPI_SMEM_DIN4_MODE_M ((SPI_MEM_SPI_SMEM_DIN4_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN4_MODE_S)) -#define SPI_MEM_SPI_SMEM_DIN4_MODE_V 0x7 -#define SPI_MEM_SPI_SMEM_DIN4_MODE_S 12 - -/* SPI_MEM_SPI_SMEM_DIN3_MODE : R/W ;bitpos:[11:9] ;default: 3'h0 ; */ - -/* Description: SPI_HD input delay mode. - * 0: No delay. - * 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. - * 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one - * cycle at MSPI_CORE_CLK positive edge. - * 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one - * cycle at MSPI_CORE_CLK negative edge. - * 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one - * cycle at MSPI_CORE_CLK positive edge. - * 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one - * cycle at MSPI_CORE_CLK negative edge. - */ - -#define SPI_MEM_SPI_SMEM_DIN3_MODE 0x00000007 -#define SPI_MEM_SPI_SMEM_DIN3_MODE_M ((SPI_MEM_SPI_SMEM_DIN3_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN3_MODE_S)) -#define SPI_MEM_SPI_SMEM_DIN3_MODE_V 0x7 -#define SPI_MEM_SPI_SMEM_DIN3_MODE_S 9 - -/* SPI_MEM_SPI_SMEM_DIN2_MODE : R/W ;bitpos:[8:6] ;default: 3'h0 ; */ - -/* Description: SPI_WP input delay mode. - * 0: No delay. - * 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. - * 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one - * cycle at MSPI_CORE_CLK positive edge. - * 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one - * cycle at MSPI_CORE_CLK negative edge. - * 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one - * cycle at MSPI_CORE_CLK positive edge. - * 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one - * cycle at MSPI_CORE_CLK negative edge. - */ - -#define SPI_MEM_SPI_SMEM_DIN2_MODE 0x00000007 -#define SPI_MEM_SPI_SMEM_DIN2_MODE_M ((SPI_MEM_SPI_SMEM_DIN2_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN2_MODE_S)) -#define SPI_MEM_SPI_SMEM_DIN2_MODE_V 0x7 -#define SPI_MEM_SPI_SMEM_DIN2_MODE_S 6 - -/* SPI_MEM_SPI_SMEM_DIN1_MODE : R/W ;bitpos:[5:3] ;default: 3'h0 ; */ - -/* Description: SPI_Q input delay mode. - * 0: No delay. - * 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. - * 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one - * cycle at MSPI_CORE_CLK positive edge. - * 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one - * cycle at MSPI_CORE_CLK negative edge. - * 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one - * cycle at MSPI_CORE_CLK positive edge. - * 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one - * cycle at MSPI_CORE_CLK negative edge. - */ - -#define SPI_MEM_SPI_SMEM_DIN1_MODE 0x00000007 -#define SPI_MEM_SPI_SMEM_DIN1_MODE_M ((SPI_MEM_SPI_SMEM_DIN1_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN1_MODE_S)) -#define SPI_MEM_SPI_SMEM_DIN1_MODE_V 0x7 -#define SPI_MEM_SPI_SMEM_DIN1_MODE_S 3 - -/* SPI_MEM_SPI_SMEM_DIN0_MODE : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ - -/* Description: SPI_D input delay mode. - * 0: No delay. - * 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. - * 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one - * cycle at MSPI_CORE_CLK positive edge. - * 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one - * cycle at MSPI_CORE_CLK negative edge. - * 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one - * cycle at MSPI_CORE_CLK positive edge. - * 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one - * cycle at MSPI_CORE_CLK negative edge. - */ - -#define SPI_MEM_SPI_SMEM_DIN0_MODE 0x00000007 -#define SPI_MEM_SPI_SMEM_DIN0_MODE_M ((SPI_MEM_SPI_SMEM_DIN0_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN0_MODE_S)) -#define SPI_MEM_SPI_SMEM_DIN0_MODE_V 0x7 -#define SPI_MEM_SPI_SMEM_DIN0_MODE_S 0 - -#define SPI_MEM_SPI_SMEM_DIN_NUM_REG(i) (REG_SPI_MEM_BASE(i) + 0xC4) - -/* SPI_MEM_SPI_SMEM_DINS_NUM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */ - -/* Description: SPI_DQS input delay number. */ - -#define SPI_MEM_SPI_SMEM_DINS_NUM 0x00000003 -#define SPI_MEM_SPI_SMEM_DINS_NUM_M ((SPI_MEM_SPI_SMEM_DINS_NUM_V)<<(SPI_MEM_SPI_SMEM_DINS_NUM_S)) -#define SPI_MEM_SPI_SMEM_DINS_NUM_V 0x3 -#define SPI_MEM_SPI_SMEM_DINS_NUM_S 16 - -/* SPI_MEM_SPI_SMEM_DIN7_NUM : R/W ;bitpos:[15:14] ;default: 2'h0 ; */ - -/* Description: SPI_IO7 input delay number. */ - -#define SPI_MEM_SPI_SMEM_DIN7_NUM 0x00000003 -#define SPI_MEM_SPI_SMEM_DIN7_NUM_M ((SPI_MEM_SPI_SMEM_DIN7_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN7_NUM_S)) -#define SPI_MEM_SPI_SMEM_DIN7_NUM_V 0x3 -#define SPI_MEM_SPI_SMEM_DIN7_NUM_S 14 - -/* SPI_MEM_SPI_SMEM_DIN6_NUM : R/W ;bitpos:[13:12] ;default: 2'h0 ; */ - -/* Description: SPI_IO6 input delay number. */ - -#define SPI_MEM_SPI_SMEM_DIN6_NUM 0x00000003 -#define SPI_MEM_SPI_SMEM_DIN6_NUM_M ((SPI_MEM_SPI_SMEM_DIN6_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN6_NUM_S)) -#define SPI_MEM_SPI_SMEM_DIN6_NUM_V 0x3 -#define SPI_MEM_SPI_SMEM_DIN6_NUM_S 12 - -/* SPI_MEM_SPI_SMEM_DIN5_NUM : R/W ;bitpos:[11:10] ;default: 2'h0 ; */ - -/* Description: SPI_IO5 input delay number. */ - -#define SPI_MEM_SPI_SMEM_DIN5_NUM 0x00000003 -#define SPI_MEM_SPI_SMEM_DIN5_NUM_M ((SPI_MEM_SPI_SMEM_DIN5_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN5_NUM_S)) -#define SPI_MEM_SPI_SMEM_DIN5_NUM_V 0x3 -#define SPI_MEM_SPI_SMEM_DIN5_NUM_S 10 - -/* SPI_MEM_SPI_SMEM_DIN4_NUM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */ - -/* Description: SPI_IO4 input delay number. */ - -#define SPI_MEM_SPI_SMEM_DIN4_NUM 0x00000003 -#define SPI_MEM_SPI_SMEM_DIN4_NUM_M ((SPI_MEM_SPI_SMEM_DIN4_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN4_NUM_S)) -#define SPI_MEM_SPI_SMEM_DIN4_NUM_V 0x3 -#define SPI_MEM_SPI_SMEM_DIN4_NUM_S 8 - -/* SPI_MEM_SPI_SMEM_DIN3_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */ - -/* Description: SPI_HD input delay number. */ - -#define SPI_MEM_SPI_SMEM_DIN3_NUM 0x00000003 -#define SPI_MEM_SPI_SMEM_DIN3_NUM_M ((SPI_MEM_SPI_SMEM_DIN3_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN3_NUM_S)) -#define SPI_MEM_SPI_SMEM_DIN3_NUM_V 0x3 -#define SPI_MEM_SPI_SMEM_DIN3_NUM_S 6 - -/* SPI_MEM_SPI_SMEM_DIN2_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */ - -/* Description: SPI_WP input delay number. */ - -#define SPI_MEM_SPI_SMEM_DIN2_NUM 0x00000003 -#define SPI_MEM_SPI_SMEM_DIN2_NUM_M ((SPI_MEM_SPI_SMEM_DIN2_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN2_NUM_S)) -#define SPI_MEM_SPI_SMEM_DIN2_NUM_V 0x3 -#define SPI_MEM_SPI_SMEM_DIN2_NUM_S 4 - -/* SPI_MEM_SPI_SMEM_DIN1_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */ - -/* Description: SPI_Q input delay number. */ - -#define SPI_MEM_SPI_SMEM_DIN1_NUM 0x00000003 -#define SPI_MEM_SPI_SMEM_DIN1_NUM_M ((SPI_MEM_SPI_SMEM_DIN1_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN1_NUM_S)) -#define SPI_MEM_SPI_SMEM_DIN1_NUM_V 0x3 -#define SPI_MEM_SPI_SMEM_DIN1_NUM_S 2 - -/* SPI_MEM_SPI_SMEM_DIN0_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ - -/* Description: SPI_D input delay number. */ - -#define SPI_MEM_SPI_SMEM_DIN0_NUM 0x00000003 -#define SPI_MEM_SPI_SMEM_DIN0_NUM_M ((SPI_MEM_SPI_SMEM_DIN0_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN0_NUM_S)) -#define SPI_MEM_SPI_SMEM_DIN0_NUM_V 0x3 -#define SPI_MEM_SPI_SMEM_DIN0_NUM_S 0 - -#define SPI_MEM_SPI_SMEM_DOUT_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0xC8) - -/* SPI_MEM_SPI_SMEM_DOUTS_MODE : R/W ;bitpos:[8] ;default: 1'h0 ; */ - -/* Description: SPI_DQS output delay mode. - * 0: No delay. - * 1: Delay one cycle at MSPI_CORE_CLK negative edge. - */ - -#define SPI_MEM_SPI_SMEM_DOUTS_MODE (BIT(8)) -#define SPI_MEM_SPI_SMEM_DOUTS_MODE_M (BIT(8)) -#define SPI_MEM_SPI_SMEM_DOUTS_MODE_V 0x1 -#define SPI_MEM_SPI_SMEM_DOUTS_MODE_S 8 - -/* SPI_MEM_SPI_SMEM_DOUT7_MODE : R/W ;bitpos:[7] ;default: 1'h0 ; */ - -/* Description: SPI_IO7 output delay mode. - * 0: No delay. - * 1: Delay one cycle at MSPI_CORE_CLK negative edge. - */ - -#define SPI_MEM_SPI_SMEM_DOUT7_MODE (BIT(7)) -#define SPI_MEM_SPI_SMEM_DOUT7_MODE_M (BIT(7)) -#define SPI_MEM_SPI_SMEM_DOUT7_MODE_V 0x1 -#define SPI_MEM_SPI_SMEM_DOUT7_MODE_S 7 - -/* SPI_MEM_SPI_SMEM_DOUT6_MODE : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -/* Description: SPI_IO6 output delay mode. - * 0: No delay. - * 1: Delay one cycle at MSPI_CORE_CLK negative edge. - */ - -#define SPI_MEM_SPI_SMEM_DOUT6_MODE (BIT(6)) -#define SPI_MEM_SPI_SMEM_DOUT6_MODE_M (BIT(6)) -#define SPI_MEM_SPI_SMEM_DOUT6_MODE_V 0x1 -#define SPI_MEM_SPI_SMEM_DOUT6_MODE_S 6 - -/* SPI_MEM_SPI_SMEM_DOUT5_MODE : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -/* Description: SPI_IO5 output delay mode. - * 0: No delay. - * 1: Delay one cycle at MSPI_CORE_CLK negative edge. - */ - -#define SPI_MEM_SPI_SMEM_DOUT5_MODE (BIT(5)) -#define SPI_MEM_SPI_SMEM_DOUT5_MODE_M (BIT(5)) -#define SPI_MEM_SPI_SMEM_DOUT5_MODE_V 0x1 -#define SPI_MEM_SPI_SMEM_DOUT5_MODE_S 5 - -/* SPI_MEM_SPI_SMEM_DOUT4_MODE : R/W ;bitpos:[4] ;default: 1'h0 ; */ - -/* Description: SPI_IO4 output delay mode. - * 0: No delay. - * 1: Delay one cycle at MSPI_CORE_CLK negative edge. - */ - -#define SPI_MEM_SPI_SMEM_DOUT4_MODE (BIT(4)) -#define SPI_MEM_SPI_SMEM_DOUT4_MODE_M (BIT(4)) -#define SPI_MEM_SPI_SMEM_DOUT4_MODE_V 0x1 -#define SPI_MEM_SPI_SMEM_DOUT4_MODE_S 4 - -/* SPI_MEM_SPI_SMEM_DOUT3_MODE : R/W ;bitpos:[3] ;default: 1'h0 ; */ - -/* Description: SPI_HD output delay mode. - * 0: No delay. - * 1: Delay one cycle at MSPI_CORE_CLK negative edge. - */ - -#define SPI_MEM_SPI_SMEM_DOUT3_MODE (BIT(3)) -#define SPI_MEM_SPI_SMEM_DOUT3_MODE_M (BIT(3)) -#define SPI_MEM_SPI_SMEM_DOUT3_MODE_V 0x1 -#define SPI_MEM_SPI_SMEM_DOUT3_MODE_S 3 - -/* SPI_MEM_SPI_SMEM_DOUT2_MODE : R/W ;bitpos:[2] ;default: 1'h0 ; */ - -/* Description: SPI_WP output delay mode. - * 0: No delay. - * 1: Delay one cycle at MSPI_CORE_CLK negative edge. - */ - -#define SPI_MEM_SPI_SMEM_DOUT2_MODE (BIT(2)) -#define SPI_MEM_SPI_SMEM_DOUT2_MODE_M (BIT(2)) -#define SPI_MEM_SPI_SMEM_DOUT2_MODE_V 0x1 -#define SPI_MEM_SPI_SMEM_DOUT2_MODE_S 2 - -/* SPI_MEM_SPI_SMEM_DOUT1_MODE : R/W ;bitpos:[1] ;default: 1'h0 ; */ - -/* Description: SPI_Q output delay mode. - * 0: No delay. - * 1: Delay one cycle at MSPI_CORE_CLK negative edge. - */ - -#define SPI_MEM_SPI_SMEM_DOUT1_MODE (BIT(1)) -#define SPI_MEM_SPI_SMEM_DOUT1_MODE_M (BIT(1)) -#define SPI_MEM_SPI_SMEM_DOUT1_MODE_V 0x1 -#define SPI_MEM_SPI_SMEM_DOUT1_MODE_S 1 - -/* SPI_MEM_SPI_SMEM_DOUT0_MODE : R/W ;bitpos:[0] ;default: 1'h0 ; */ - -/* Description: SPI_D output delay mode. - * 0: No delay. - * 1: Delay one cycle at MSPI_CORE_CLK negative edge. - */ - -#define SPI_MEM_SPI_SMEM_DOUT0_MODE (BIT(0)) -#define SPI_MEM_SPI_SMEM_DOUT0_MODE_M (BIT(0)) -#define SPI_MEM_SPI_SMEM_DOUT0_MODE_V 0x1 -#define SPI_MEM_SPI_SMEM_DOUT0_MODE_S 0 - -#define SPI_MEM_ECC_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0xCC) - -/* SPI_MEM_SPI_FMEM_ECC_ERR_INT_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ - -/* Description: Set this bit to calculate the error times of MSPI ECC read - * when accesses to flash. - */ - -#define SPI_MEM_SPI_FMEM_ECC_ERR_INT_EN (BIT(8)) -#define SPI_MEM_SPI_FMEM_ECC_ERR_INT_EN_M (BIT(8)) -#define SPI_MEM_SPI_FMEM_ECC_ERR_INT_EN_V 0x1 -#define SPI_MEM_SPI_FMEM_ECC_ERR_INT_EN_S 8 - -/* SPI_MEM_ECC_ERR_INT_NUM : R/W ;bitpos:[7:0] ;default: 8'd10 ; */ - -/* Description: Set the error times of MSPI ECC read to generate MSPI - * SPI_MEM_ECC_ERR_INT interrupt. - */ - -#define SPI_MEM_ECC_ERR_INT_NUM 0x000000FF -#define SPI_MEM_ECC_ERR_INT_NUM_M ((SPI_MEM_ECC_ERR_INT_NUM_V)<<(SPI_MEM_ECC_ERR_INT_NUM_S)) -#define SPI_MEM_ECC_ERR_INT_NUM_V 0xFF -#define SPI_MEM_ECC_ERR_INT_NUM_S 0 - -#define SPI_MEM_ECC_ERR_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0xD0) - -/* SPI_MEM_ECC_ERR_ADDR : R/SS/WTC ;bitpos:[31:0] ;default: 32'h0 ; */ - -/* Description: These bits show the first MSPI ECC error address when - * SPI_FMEM_ECC_ERR_INT_EN/SPI_SMEM_ECC_ERR_INT_EN is set and accessed to - * flash/Ext_RAM, including ECC byte error and data error. It is cleared by - * when SPI_MEM_ECC_ERR_INT_CLR bit is set. - */ - -#define SPI_MEM_ECC_ERR_ADDR 0xFFFFFFFF -#define SPI_MEM_ECC_ERR_ADDR_M ((SPI_MEM_ECC_ERR_ADDR_V)<<(SPI_MEM_ECC_ERR_ADDR_S)) -#define SPI_MEM_ECC_ERR_ADDR_V 0xFFFFFFFF -#define SPI_MEM_ECC_ERR_ADDR_S 0 - -#define SPI_MEM_ECC_ERR_BIT_REG(i) (REG_SPI_MEM_BASE(i) + 0xD4) - -/* SPI_MEM_ECC_ERR_CNT : RO ;bitpos:[24:17] ;default: 8'd0 ; */ - -/* Description: This bits show the error times of MSPI ECC read, including - * ECC byte error and data byte error. It is cleared by when - * SPI_MEM_ECC_ERR_INT_CLR bit is set. - */ - -#define SPI_MEM_ECC_ERR_CNT 0x000000FF -#define SPI_MEM_ECC_ERR_CNT_M ((SPI_MEM_ECC_ERR_CNT_V)<<(SPI_MEM_ECC_ERR_CNT_S)) -#define SPI_MEM_ECC_ERR_CNT_V 0xFF -#define SPI_MEM_ECC_ERR_CNT_S 17 - -/* SPI_MEM_ECC_BYTE_ERR : R/SS/WTC ;bitpos:[16] ;default: 1'd0 ; */ - -/* Description: It records the first ECC byte error when - * SPI_FMEM_ECC_ERR_INT_EN/SPI_SMEM_ECC_ERR_INT_EN is set and accessed to - * flash/Ext_RAM. It is cleared by SPI_MEM_ECC_ERR_INT_CLR bit. - */ - -#define SPI_MEM_ECC_BYTE_ERR (BIT(16)) -#define SPI_MEM_ECC_BYTE_ERR_M (BIT(16)) -#define SPI_MEM_ECC_BYTE_ERR_V 0x1 -#define SPI_MEM_ECC_BYTE_ERR_S 16 - -/* SPI_MEM_ECC_CHK_ERR_BIT : R/SS/WTC ;bitpos:[15:13] ;default: 3'd0 ; */ - -/* Description: When SPI_MEM_ECC_BYTE_ERR is set, these bits show the error - * bit number of ECC byte. - */ - -#define SPI_MEM_ECC_CHK_ERR_BIT 0x00000007 -#define SPI_MEM_ECC_CHK_ERR_BIT_M ((SPI_MEM_ECC_CHK_ERR_BIT_V)<<(SPI_MEM_ECC_CHK_ERR_BIT_S)) -#define SPI_MEM_ECC_CHK_ERR_BIT_V 0x7 -#define SPI_MEM_ECC_CHK_ERR_BIT_S 13 - -/* SPI_MEM_ECC_DATA_ERR_BIT : R/SS/WTC ;bitpos:[12:6] ;default: 7'd0 ; */ - -/* Description: It records the first ECC data error bit number when - * SPI_FMEM_ECC_ERR_INT_EN/SPI_SMEM_ECC_ERR_INT_EN is set and accessed to - * flash/Ext_RAM. The value ranges from 0~127, corresponding to the bit - * number in 16 data bytes. It is cleared by SPI_MEM_ECC_ERR_INT_CLR bit. - */ - -#define SPI_MEM_ECC_DATA_ERR_BIT 0x0000007F -#define SPI_MEM_ECC_DATA_ERR_BIT_M ((SPI_MEM_ECC_DATA_ERR_BIT_V)<<(SPI_MEM_ECC_DATA_ERR_BIT_S)) -#define SPI_MEM_ECC_DATA_ERR_BIT_V 0x7F -#define SPI_MEM_ECC_DATA_ERR_BIT_S 6 - -#define SPI_MEM_SPI_SMEM_AC_REG(i) (REG_SPI_MEM_BASE(i) + 0xDC) - -/* SPI_MEM_SPI_SMEM_CS_HOLD_DELAY : R/W ;bitpos:[30:25] ;default: 6'd0 ; */ - -/* Description: These bits are used to set the minimum CS high time tSHSL - * between SPI burst transfer when accesses to external RAM. tSHSL is - * (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles. - */ - -#define SPI_MEM_SPI_SMEM_CS_HOLD_DELAY 0x0000003F -#define SPI_MEM_SPI_SMEM_CS_HOLD_DELAY_M ((SPI_MEM_SPI_SMEM_CS_HOLD_DELAY_V)<<(SPI_MEM_SPI_SMEM_CS_HOLD_DELAY_S)) -#define SPI_MEM_SPI_SMEM_CS_HOLD_DELAY_V 0x3F -#define SPI_MEM_SPI_SMEM_CS_HOLD_DELAY_S 25 - -/* SPI_MEM_SPI_SMEM_ECC_ERR_INT_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */ - -/* Description: Set this bit to calculate the error times of MSPI ECC read - * when accesses to external RAM. - */ - -#define SPI_MEM_SPI_SMEM_ECC_ERR_INT_EN (BIT(24)) -#define SPI_MEM_SPI_SMEM_ECC_ERR_INT_EN_M (BIT(24)) -#define SPI_MEM_SPI_SMEM_ECC_ERR_INT_EN_V 0x1 -#define SPI_MEM_SPI_SMEM_ECC_ERR_INT_EN_S 24 - -/* SPI_MEM_SPI_SMEM_ECC_16TO18_BYTE_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */ - -/* Description: Set this bit to enable MSPI ECC 16 bytes data with 2 ECC - * bytes mode when accesses to external RAM. - */ - -#define SPI_MEM_SPI_SMEM_ECC_16TO18_BYTE_EN (BIT(16)) -#define SPI_MEM_SPI_SMEM_ECC_16TO18_BYTE_EN_M (BIT(16)) -#define SPI_MEM_SPI_SMEM_ECC_16TO18_BYTE_EN_V 0x1 -#define SPI_MEM_SPI_SMEM_ECC_16TO18_BYTE_EN_S 16 - -/* SPI_MEM_SPI_SMEM_ECC_SKIP_PAGE_CORNER: R/W;bitpos:[15];default:1'b1 ; */ - -/* Description: - * 1: MSPI skips page corner when accesses to external RAM. - * 0: Not skip page corner when accesses to external RAM. - */ - -#define SPI_MEM_SPI_SMEM_ECC_SKIP_PAGE_CORNER (BIT(15)) -#define SPI_MEM_SPI_SMEM_ECC_SKIP_PAGE_CORNER_M (BIT(15)) -#define SPI_MEM_SPI_SMEM_ECC_SKIP_PAGE_CORNER_V 0x1 -#define SPI_MEM_SPI_SMEM_ECC_SKIP_PAGE_CORNER_S 15 - -/* SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME : R/W ;bitpos:[14:12] ;default: 3'd3 ; */ - -/* Description: SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the MSPI - * CS hold cycles in ECC mode when accesses to external RAM. - */ - -#define SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME 0x00000007 -#define SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME_M ((SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME_V)<<(SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME_S)) -#define SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME_V 0x7 -#define SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME_S 12 - -/* SPI_MEM_SPI_SMEM_CS_HOLD_TIME : R/W ;bitpos:[11:7] ;default: 5'h1 ; */ - -/* Description: SPI Bus CS (SPI_CS) signal is delayed to inactive by SPI Bus - * clock (SPI_CLK), which is the SPI_CS hold time in non-ECC mode. These bits - * are combined with SPI_MEM_CS_HOLD bit. - */ - -#define SPI_MEM_SPI_SMEM_CS_HOLD_TIME 0x0000001F -#define SPI_MEM_SPI_SMEM_CS_HOLD_TIME_M ((SPI_MEM_SPI_SMEM_CS_HOLD_TIME_V)<<(SPI_MEM_SPI_SMEM_CS_HOLD_TIME_S)) -#define SPI_MEM_SPI_SMEM_CS_HOLD_TIME_V 0x1F -#define SPI_MEM_SPI_SMEM_CS_HOLD_TIME_S 7 - -/* SPI_MEM_SPI_SMEM_CS_SETUP_TIME : R/W ;bitpos:[6:2] ;default: 5'h1 ; */ - -/* Description: (cycles-1) of PREP phase by SPI_CLK, which is the SPI_CS - * setup time. These bits are combined with SPI_MEM_CS_SETUP bit. - */ - -#define SPI_MEM_SPI_SMEM_CS_SETUP_TIME 0x0000001F -#define SPI_MEM_SPI_SMEM_CS_SETUP_TIME_M ((SPI_MEM_SPI_SMEM_CS_SETUP_TIME_V)<<(SPI_MEM_SPI_SMEM_CS_SETUP_TIME_S)) -#define SPI_MEM_SPI_SMEM_CS_SETUP_TIME_V 0x1F -#define SPI_MEM_SPI_SMEM_CS_SETUP_TIME_S 2 - -/* SPI_MEM_SPI_SMEM_CS_HOLD : R/W ;bitpos:[1] ;default: 1'b0 ; */ - -/* Description: Set this bit to keep SPI_CS low when MSPI is in DONE state. */ - -#define SPI_MEM_SPI_SMEM_CS_HOLD (BIT(1)) -#define SPI_MEM_SPI_SMEM_CS_HOLD_M (BIT(1)) -#define SPI_MEM_SPI_SMEM_CS_HOLD_V 0x1 -#define SPI_MEM_SPI_SMEM_CS_HOLD_S 1 - -/* SPI_MEM_SPI_SMEM_CS_SETUP : R/W ;bitpos:[0] ;default: 1'b0 ; */ - -/* Description: Set this bit to keep SPI_CS low when MSPI is in PREP state. */ - -#define SPI_MEM_SPI_SMEM_CS_SETUP (BIT(0)) -#define SPI_MEM_SPI_SMEM_CS_SETUP_M (BIT(0)) -#define SPI_MEM_SPI_SMEM_CS_SETUP_V 0x1 -#define SPI_MEM_SPI_SMEM_CS_SETUP_S 0 - -#define SPI_MEM_DDR_REG(i) (REG_SPI_MEM_BASE(i) + 0xE0) - -/* SPI_MEM_SPI_FMEM_HYPERBUS_CA : R/W ;bitpos:[30] ;default: 1'b0 ; */ - -/* Description: Set this bit to enable HyperRAM address out when accesses to - * flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, - * spi_usr_addr_value[3:1]}. - */ - -#define SPI_MEM_SPI_FMEM_HYPERBUS_CA (BIT(30)) -#define SPI_MEM_SPI_FMEM_HYPERBUS_CA_M (BIT(30)) -#define SPI_MEM_SPI_FMEM_HYPERBUS_CA_V 0x1 -#define SPI_MEM_SPI_FMEM_HYPERBUS_CA_S 30 - -/* SPI_MEM_SPI_FMEM_OCTA_RAM_ADDR : R/W ;bitpos:[29] ;default: 1'b0 ; */ - -/* Description: Set this bit to enable octa_ram address out when accesses to - * flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, - * spi_usr_addr_value[3:1],1'b0}. - */ - -#define SPI_MEM_SPI_FMEM_OCTA_RAM_ADDR (BIT(29)) -#define SPI_MEM_SPI_FMEM_OCTA_RAM_ADDR_M (BIT(29)) -#define SPI_MEM_SPI_FMEM_OCTA_RAM_ADDR_V 0x1 -#define SPI_MEM_SPI_FMEM_OCTA_RAM_ADDR_S 29 - -/* SPI_MEM_SPI_FMEM_CLK_DIFF_INV : R/W ;bitpos:[28] ;default: 1'b0 ; */ - -/* Description: Set this bit to invert SPI_DIFF when accesses to flash. */ - -#define SPI_MEM_SPI_FMEM_CLK_DIFF_INV (BIT(28)) -#define SPI_MEM_SPI_FMEM_CLK_DIFF_INV_M (BIT(28)) -#define SPI_MEM_SPI_FMEM_CLK_DIFF_INV_V 0x1 -#define SPI_MEM_SPI_FMEM_CLK_DIFF_INV_S 28 - -/* SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X : R/W ;bitpos:[27] ;default: 1'b0 ; */ - -/* Description: Set this bit to enable the vary dummy function in SPI - * HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram. - */ - -#define SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X (BIT(27)) -#define SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X_M (BIT(27)) -#define SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X_V 0x1 -#define SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X_S 27 - -/* SPI_MEM_SPI_FMEM_DQS_CA_IN : R/W ;bitpos:[26] ;default: 1'b0 ; */ - -/* Description: Set this bit to enable the input of SPI_DQS signal in SPI - * phases of CMD and ADDR. - */ - -#define SPI_MEM_SPI_FMEM_DQS_CA_IN (BIT(26)) -#define SPI_MEM_SPI_FMEM_DQS_CA_IN_M (BIT(26)) -#define SPI_MEM_SPI_FMEM_DQS_CA_IN_V 0x1 -#define SPI_MEM_SPI_FMEM_DQS_CA_IN_S 26 - -/* SPI_MEM_SPI_FMEM_HYPERBUS_MODE : R/W ;bitpos:[25] ;default: 1'b0 ; */ - -/* Description: Set this bit to enable the SPI HyperBus mode. */ - -#define SPI_MEM_SPI_FMEM_HYPERBUS_MODE (BIT(25)) -#define SPI_MEM_SPI_FMEM_HYPERBUS_MODE_M (BIT(25)) -#define SPI_MEM_SPI_FMEM_HYPERBUS_MODE_V 0x1 -#define SPI_MEM_SPI_FMEM_HYPERBUS_MODE_S 25 - -/* SPI_MEM_SPI_FMEM_CLK_DIFF_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */ - -/* Description: Set this bit to enable the differential SPI_CLK#. */ - -#define SPI_MEM_SPI_FMEM_CLK_DIFF_EN (BIT(24)) -#define SPI_MEM_SPI_FMEM_CLK_DIFF_EN_M (BIT(24)) -#define SPI_MEM_SPI_FMEM_CLK_DIFF_EN_V 0x1 -#define SPI_MEM_SPI_FMEM_CLK_DIFF_EN_S 24 - -/* SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_MODE : R/W ;bitpos:[22] ;default: 1'b0 ; */ - -/* Description: When SPI_FMEM_DDR_DQS_LOOP and SPI_FMEM_DDR_EN are set, - * 1: Use internal SPI_CLK as data strobe. - * 0: Use internal ~SPI_CLK as data strobe. Otherwise this bit is not - * active. - */ - -#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_MODE (BIT(22)) -#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_MODE_M (BIT(22)) -#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_MODE_V 0x1 -#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_MODE_S 22 - -/* SPI_MEM_SPI_FMEM_DDR_DQS_LOOP : R/W ;bitpos:[21] ;default: 1'b0 ; */ - -/* Description: - * 1: Use internal signal as data strobe, the strobe can not be delayed by - * input timing module. - * 0: Use input SPI_DQS signal from PAD as data strobe, the strobe can be - * delayed by input timing module - */ - -#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP (BIT(21)) -#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_M (BIT(21)) -#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_V 0x1 -#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_S 21 - -/* SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD : R/W ;bitpos:[20:14] ;default: 7'b0 ; */ - -/* Description: The delay number of data strobe which from memory based on - * SPI_CLK. - */ - -#define SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD 0x0000007F -#define SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_M ((SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_V)<<(SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_S)) -#define SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_V 0x7F -#define SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_S 14 - -/* SPI_MEM_SPI_FMEM_RX_DDR_MSK_EN : R/W ;bitpos:[13] ;default: 1'h1 ; */ - -/* Description: Set this bit to mask the first or the last byte in MSPI ECC - * DDR read mode, when accesses to flash. - */ - -#define SPI_MEM_SPI_FMEM_RX_DDR_MSK_EN (BIT(13)) -#define SPI_MEM_SPI_FMEM_RX_DDR_MSK_EN_M (BIT(13)) -#define SPI_MEM_SPI_FMEM_RX_DDR_MSK_EN_V 0x1 -#define SPI_MEM_SPI_FMEM_RX_DDR_MSK_EN_S 13 - -/* SPI_MEM_SPI_FMEM_TX_DDR_MSK_EN : R/W ;bitpos:[12] ;default: 1'h1 ; */ - -/* Description: Set this bit to mask the first or the last byte in MSPI ECC - * DDR write mode, when accesses to flash. - */ - -#define SPI_MEM_SPI_FMEM_TX_DDR_MSK_EN (BIT(12)) -#define SPI_MEM_SPI_FMEM_TX_DDR_MSK_EN_M (BIT(12)) -#define SPI_MEM_SPI_FMEM_TX_DDR_MSK_EN_V 0x1 -#define SPI_MEM_SPI_FMEM_TX_DDR_MSK_EN_S 12 - -/* SPI_MEM_SPI_FMEM_OUTMINBYTELEN : R/W ;bitpos:[11:5] ;default: 7'b1 ; */ - -/* Description: It is the minimum output data length in the panda device. */ - -#define SPI_MEM_SPI_FMEM_OUTMINBYTELEN 0x0000007F -#define SPI_MEM_SPI_FMEM_OUTMINBYTELEN_M ((SPI_MEM_SPI_FMEM_OUTMINBYTELEN_V)<<(SPI_MEM_SPI_FMEM_OUTMINBYTELEN_S)) -#define SPI_MEM_SPI_FMEM_OUTMINBYTELEN_V 0x7F -#define SPI_MEM_SPI_FMEM_OUTMINBYTELEN_S 5 - -/* SPI_MEM_SPI_FMEM_DDR_CMD_DIS : R/W ;bitpos:[4] ;default: 1'b0 ; */ - -/* Description: the bit is used to disable dual edge in command phase when - * DDR mode. - */ - -#define SPI_MEM_SPI_FMEM_DDR_CMD_DIS (BIT(4)) -#define SPI_MEM_SPI_FMEM_DDR_CMD_DIS_M (BIT(4)) -#define SPI_MEM_SPI_FMEM_DDR_CMD_DIS_V 0x1 -#define SPI_MEM_SPI_FMEM_DDR_CMD_DIS_S 4 - -/* SPI_MEM_SPI_FMEM_DDR_WDAT_SWP : R/W ;bitpos:[3] ;default: 1'b0 ; */ - -/* Description: Set the bit to reorder TX data of the word in DDR mode. */ - -#define SPI_MEM_SPI_FMEM_DDR_WDAT_SWP (BIT(3)) -#define SPI_MEM_SPI_FMEM_DDR_WDAT_SWP_M (BIT(3)) -#define SPI_MEM_SPI_FMEM_DDR_WDAT_SWP_V 0x1 -#define SPI_MEM_SPI_FMEM_DDR_WDAT_SWP_S 3 - -/* SPI_MEM_SPI_FMEM_DDR_RDAT_SWP : R/W ;bitpos:[2] ;default: 1'b0 ; */ - -/* Description: Set the bit to reorder RX data of the word in DDR mode. */ - -#define SPI_MEM_SPI_FMEM_DDR_RDAT_SWP (BIT(2)) -#define SPI_MEM_SPI_FMEM_DDR_RDAT_SWP_M (BIT(2)) -#define SPI_MEM_SPI_FMEM_DDR_RDAT_SWP_V 0x1 -#define SPI_MEM_SPI_FMEM_DDR_RDAT_SWP_S 2 - -/* SPI_MEM_SPI_FMEM_VAR_DUMMY : R/W ;bitpos:[1] ;default: 1'b0 ; */ - -/* Description: Set the bit to enable variable dummy cycle in DDRmode. */ - -#define SPI_MEM_SPI_FMEM_VAR_DUMMY (BIT(1)) -#define SPI_MEM_SPI_FMEM_VAR_DUMMY_M (BIT(1)) -#define SPI_MEM_SPI_FMEM_VAR_DUMMY_V 0x1 -#define SPI_MEM_SPI_FMEM_VAR_DUMMY_S 1 - -/* SPI_MEM_SPI_FMEM_DDR_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ - -/* Description: 1: in DDR mode, 0: in SDR mode. */ - -#define SPI_MEM_SPI_FMEM_DDR_EN (BIT(0)) -#define SPI_MEM_SPI_FMEM_DDR_EN_M (BIT(0)) -#define SPI_MEM_SPI_FMEM_DDR_EN_V 0x1 -#define SPI_MEM_SPI_FMEM_DDR_EN_S 0 - -#define SPI_MEM_SPI_SMEM_DDR_REG(i) (REG_SPI_MEM_BASE(i) + 0xE4) - -/* SPI_MEM_SPI_SMEM_HYPERBUS_CA : R/W ;bitpos:[30] ;default: 1'b0 ; */ - -/* Description: Set this bit to enable HyperRAM address out when accesses to - * external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], - * 13'd0, spi_usr_addr_value[3:1]}. - */ - -#define SPI_MEM_SPI_SMEM_HYPERBUS_CA (BIT(30)) -#define SPI_MEM_SPI_SMEM_HYPERBUS_CA_M (BIT(30)) -#define SPI_MEM_SPI_SMEM_HYPERBUS_CA_V 0x1 -#define SPI_MEM_SPI_SMEM_HYPERBUS_CA_S 30 - -/* SPI_MEM_SPI_SMEM_OCTA_RAM_ADDR : R/W ;bitpos:[29] ;default: 1'b0 ; */ - -/* Description: Set this bit to enable octa_ram address out when accesses to - * external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], - * 6'd0, spi_usr_addr_value[3:1], 1'b0}. - */ - -#define SPI_MEM_SPI_SMEM_OCTA_RAM_ADDR (BIT(29)) -#define SPI_MEM_SPI_SMEM_OCTA_RAM_ADDR_M (BIT(29)) -#define SPI_MEM_SPI_SMEM_OCTA_RAM_ADDR_V 0x1 -#define SPI_MEM_SPI_SMEM_OCTA_RAM_ADDR_S 29 - -/* SPI_MEM_SPI_SMEM_CLK_DIFF_INV : R/W ;bitpos:[28] ;default: 1'b0 ; */ - -/* Description: Set this bit to invert SPI_DIFF when accesses to external RAM - */ - -#define SPI_MEM_SPI_SMEM_CLK_DIFF_INV (BIT(28)) -#define SPI_MEM_SPI_SMEM_CLK_DIFF_INV_M (BIT(28)) -#define SPI_MEM_SPI_SMEM_CLK_DIFF_INV_V 0x1 -#define SPI_MEM_SPI_SMEM_CLK_DIFF_INV_S 28 - -/* SPI_MEM_SPI_SMEM_HYPERBUS_DUMMY_2X : R/W ;bitpos:[27] ;default: 1'b0 ; */ - -/* Description: Set this bit to enable the vary dummy function in SPI - * HyperBus mode, when SPI0 accesses to flash or SPI1 accesses flash or - * sram. - */ - -#define SPI_MEM_SPI_SMEM_HYPERBUS_DUMMY_2X (BIT(27)) -#define SPI_MEM_SPI_SMEM_HYPERBUS_DUMMY_2X_M (BIT(27)) -#define SPI_MEM_SPI_SMEM_HYPERBUS_DUMMY_2X_V 0x1 -#define SPI_MEM_SPI_SMEM_HYPERBUS_DUMMY_2X_S 27 - -/* SPI_MEM_SPI_SMEM_DQS_CA_IN : R/W ;bitpos:[26] ;default: 1'b0 ; */ - -/* Description: Set this bit to enable the input of SPI_DQS signal in SPI - * phases of CMD and ADDR. - */ - -#define SPI_MEM_SPI_SMEM_DQS_CA_IN (BIT(26)) -#define SPI_MEM_SPI_SMEM_DQS_CA_IN_M (BIT(26)) -#define SPI_MEM_SPI_SMEM_DQS_CA_IN_V 0x1 -#define SPI_MEM_SPI_SMEM_DQS_CA_IN_S 26 - -/* SPI_MEM_SPI_SMEM_HYPERBUS_MODE : R/W ;bitpos:[25] ;default: 1'b0 ; */ - -/* Description: Set this bit to enable the SPI HyperBus mode. */ - -#define SPI_MEM_SPI_SMEM_HYPERBUS_MODE (BIT(25)) -#define SPI_MEM_SPI_SMEM_HYPERBUS_MODE_M (BIT(25)) -#define SPI_MEM_SPI_SMEM_HYPERBUS_MODE_V 0x1 -#define SPI_MEM_SPI_SMEM_HYPERBUS_MODE_S 25 - -/* SPI_MEM_SPI_SMEM_CLK_DIFF_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */ - -/* Description: Set this bit to enable the differential SPI_CLK#. */ - -#define SPI_MEM_SPI_SMEM_CLK_DIFF_EN (BIT(24)) -#define SPI_MEM_SPI_SMEM_CLK_DIFF_EN_M (BIT(24)) -#define SPI_MEM_SPI_SMEM_CLK_DIFF_EN_V 0x1 -#define SPI_MEM_SPI_SMEM_CLK_DIFF_EN_S 24 - -/* SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_MODE : R/W ;bitpos:[22] ;default: 1'b0 ; */ - -/* Description: When SPI_SMEM_DDR_DQS_LOOP and SPI_SMEM_DDR_EN are set, - * 1: Use internal SPI_CLK as data strobe. - * 0: Use internal ~SPI_CLK as data strobe. Otherwise this bit is not - * active. - */ - -#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_MODE (BIT(22)) -#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_MODE_M (BIT(22)) -#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_MODE_V 0x1 -#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_MODE_S 22 - -/* SPI_MEM_SPI_SMEM_DDR_DQS_LOOP : R/W ;bitpos:[21] ;default: 1'b0 ; */ - -/* Description: - * 1: Use internal signal as data strobe, the strobe can not be delayed by - * input timing module. - * 0: Use input SPI_DQS signal from PAD as data strobe, the strobe can be - * delayed by input timing module - */ - -#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP (BIT(21)) -#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_M (BIT(21)) -#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_V 0x1 -#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_S 21 - -/* SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD : R/W ;bitpos:[20:14] ;default: 7'b0 ; */ - -/* Description: The delay number of data strobe which from memory based on - * SPI_CLK. - */ - -#define SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD 0x0000007F -#define SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_M ((SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_V)<<(SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_S)) -#define SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_V 0x7F -#define SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_S 14 - -/* SPI_MEM_SPI_SMEM_RX_DDR_MSK_EN : R/W ;bitpos:[13] ;default: 1'h1 ; */ - -/* Description: Set this bit to mask the first or the last byte in MSPI ECC - * DDR read mode, when accesses to external RAM. - */ - -#define SPI_MEM_SPI_SMEM_RX_DDR_MSK_EN (BIT(13)) -#define SPI_MEM_SPI_SMEM_RX_DDR_MSK_EN_M (BIT(13)) -#define SPI_MEM_SPI_SMEM_RX_DDR_MSK_EN_V 0x1 -#define SPI_MEM_SPI_SMEM_RX_DDR_MSK_EN_S 13 - -/* SPI_MEM_SPI_SMEM_TX_DDR_MSK_EN : R/W ;bitpos:[12] ;default: 1'h1 ; */ - -/* Description: Set this bit to mask the first or the last byte in MSPI ECC - * DDR write mode, when accesses to external RAM. - */ - -#define SPI_MEM_SPI_SMEM_TX_DDR_MSK_EN (BIT(12)) -#define SPI_MEM_SPI_SMEM_TX_DDR_MSK_EN_M (BIT(12)) -#define SPI_MEM_SPI_SMEM_TX_DDR_MSK_EN_V 0x1 -#define SPI_MEM_SPI_SMEM_TX_DDR_MSK_EN_S 12 - -/* SPI_MEM_SPI_SMEM_OUTMINBYTELEN : R/W ;bitpos:[11:5] ;default: 7'b1 ; */ - -/* Description: It is the minimum output data length in the ddr psram. */ - -#define SPI_MEM_SPI_SMEM_OUTMINBYTELEN 0x0000007F -#define SPI_MEM_SPI_SMEM_OUTMINBYTELEN_M ((SPI_MEM_SPI_SMEM_OUTMINBYTELEN_V)<<(SPI_MEM_SPI_SMEM_OUTMINBYTELEN_S)) -#define SPI_MEM_SPI_SMEM_OUTMINBYTELEN_V 0x7F -#define SPI_MEM_SPI_SMEM_OUTMINBYTELEN_S 5 - -/* SPI_MEM_SPI_SMEM_DDR_CMD_DIS : R/W ;bitpos:[4] ;default: 1'b0 ; */ - -/* Description: the bit is used to disable dual edge in CMD phase when ddr - * mode. - */ - -#define SPI_MEM_SPI_SMEM_DDR_CMD_DIS (BIT(4)) -#define SPI_MEM_SPI_SMEM_DDR_CMD_DIS_M (BIT(4)) -#define SPI_MEM_SPI_SMEM_DDR_CMD_DIS_V 0x1 -#define SPI_MEM_SPI_SMEM_DDR_CMD_DIS_S 4 - -/* SPI_MEM_SPI_SMEM_DDR_WDAT_SWP : R/W ;bitpos:[3] ;default: 1'b0 ; */ - -/* Description: Set the bit to reorder tx data of the word in spi ddr mode. */ - -#define SPI_MEM_SPI_SMEM_DDR_WDAT_SWP (BIT(3)) -#define SPI_MEM_SPI_SMEM_DDR_WDAT_SWP_M (BIT(3)) -#define SPI_MEM_SPI_SMEM_DDR_WDAT_SWP_V 0x1 -#define SPI_MEM_SPI_SMEM_DDR_WDAT_SWP_S 3 - -/* SPI_MEM_SPI_SMEM_DDR_RDAT_SWP : R/W ;bitpos:[2] ;default: 1'b0 ; */ - -/* Description: Set the bit to reorder rx data of the word in spi ddr mode. */ - -#define SPI_MEM_SPI_SMEM_DDR_RDAT_SWP (BIT(2)) -#define SPI_MEM_SPI_SMEM_DDR_RDAT_SWP_M (BIT(2)) -#define SPI_MEM_SPI_SMEM_DDR_RDAT_SWP_V 0x1 -#define SPI_MEM_SPI_SMEM_DDR_RDAT_SWP_S 2 - -/* SPI_MEM_SPI_SMEM_VAR_DUMMY : R/W ;bitpos:[1] ;default: 1'b0 ; */ - -/* Description: Set the bit to enable variable dummy cycle in spi ddr mode. */ - -#define SPI_MEM_SPI_SMEM_VAR_DUMMY (BIT(1)) -#define SPI_MEM_SPI_SMEM_VAR_DUMMY_M (BIT(1)) -#define SPI_MEM_SPI_SMEM_VAR_DUMMY_V 0x1 -#define SPI_MEM_SPI_SMEM_VAR_DUMMY_S 1 - -/* SPI_MEM_SPI_SMEM_DDR_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ - -/* Description: 1: in ddr mode, 0 in sdr mode */ - -#define SPI_MEM_SPI_SMEM_DDR_EN (BIT(0)) -#define SPI_MEM_SPI_SMEM_DDR_EN_M (BIT(0)) -#define SPI_MEM_SPI_SMEM_DDR_EN_V 0x1 -#define SPI_MEM_SPI_SMEM_DDR_EN_S 0 - -#define SPI_MEM_CLOCK_GATE_REG(i) (REG_SPI_MEM_BASE(i) + 0xE8) - -/* SPI_MEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ - -/* Description: Register clock gate enable signal. 1: Enable. 0: Disable. */ - -#define SPI_MEM_CLK_EN (BIT(0)) -#define SPI_MEM_CLK_EN_M (BIT(0)) -#define SPI_MEM_CLK_EN_V 0x1 -#define SPI_MEM_CLK_EN_S 0 - -#define SPI_MEM_CORE_CLK_SEL_REG(i) (REG_SPI_MEM_BASE(i) + 0xEC) - -/* SPI_MEM_CORE_CLK_SEL : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ - -/* Description: When the digital system clock selects PLL clock and the - * frequency of PLL clock is 480MHz, the value of SPI_MEM_CORE_CLK_SEL: - * 0: SPI0/1 module clock (MSPI_CORE_CLK) is 80MHz. - * 1: MSPI_CORE_CLK is 120MHz. - * 2: MSPI_CORE_CLK is 160MHz. - * 3: MSPI_CORE_CLK is 240MHz. When the digital system clock selects PLL - * clock and the frequency of PLL clock is 320MHz, the value of - * SPI_MEM_CORE_CLK_SEL: - * 0: MSPI_CORE_CLK is 80MHz. - * 1: MSPI_CORE_CLK is 80MHz. - * 2: MSPI_CORE_CLK 160MHz. - * 3: Not used. - */ - -#define SPI_MEM_CORE_CLK_SEL 0x00000003 -#define SPI_MEM_CORE_CLK_SEL_M ((SPI_MEM_CORE_CLK_SEL_V)<<(SPI_MEM_CORE_CLK_SEL_S)) -#define SPI_MEM_CORE_CLK_SEL_V 0x3 -#define SPI_MEM_CORE_CLK_SEL_S 0 - -#define SPI_MEM_INT_ENA_REG(i) (REG_SPI_MEM_BASE(i) + 0xF0) - -/* SPI_MEM_ECC_ERR_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ - -/* Description: The enable bit for SPI_MEM_ECC_ERR_INT interrupt. */ - -#define SPI_MEM_ECC_ERR_INT_ENA (BIT(4)) -#define SPI_MEM_ECC_ERR_INT_ENA_M (BIT(4)) -#define SPI_MEM_ECC_ERR_INT_ENA_V 0x1 -#define SPI_MEM_ECC_ERR_INT_ENA_S 4 - -/* SPI_MEM_BROWN_OUT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ - -/* Description: The enable bit for SPI_MEM_BROWN_OUT_INT interrupt. */ - -#define SPI_MEM_BROWN_OUT_INT_ENA (BIT(3)) -#define SPI_MEM_BROWN_OUT_INT_ENA_M (BIT(3)) -#define SPI_MEM_BROWN_OUT_INT_ENA_V 0x1 -#define SPI_MEM_BROWN_OUT_INT_ENA_S 3 - -/* SPI_MEM_TOTAL_TRANS_END_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ - -/* Description: The enable bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. */ - -#define SPI_MEM_TOTAL_TRANS_END_INT_ENA (BIT(2)) -#define SPI_MEM_TOTAL_TRANS_END_INT_ENA_M (BIT(2)) -#define SPI_MEM_TOTAL_TRANS_END_INT_ENA_V 0x1 -#define SPI_MEM_TOTAL_TRANS_END_INT_ENA_S 2 - -/* SPI_MEM_PES_END_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ - -/* Description: The enable bit for SPI_MEM_PES_END_INT interrupt. */ - -#define SPI_MEM_PES_END_INT_ENA (BIT(1)) -#define SPI_MEM_PES_END_INT_ENA_M (BIT(1)) -#define SPI_MEM_PES_END_INT_ENA_V 0x1 -#define SPI_MEM_PES_END_INT_ENA_S 1 - -/* SPI_MEM_PER_END_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ - -/* Description: The enable bit for SPI_MEM_PER_END_INT interrupt. */ - -#define SPI_MEM_PER_END_INT_ENA (BIT(0)) -#define SPI_MEM_PER_END_INT_ENA_M (BIT(0)) -#define SPI_MEM_PER_END_INT_ENA_V 0x1 -#define SPI_MEM_PER_END_INT_ENA_S 0 - -#define SPI_MEM_INT_CLR_REG(i) (REG_SPI_MEM_BASE(i) + 0xF4) - -/* SPI_MEM_ECC_ERR_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */ - -/* Description: The clear bit for SPI_MEM_ECC_ERR_INT interrupt. - * SPI_MEM_ECC_ERR_ADDR and SPI_MEM_ECC_ERR_CNT will be cleared by the pulse - * of this bit. - */ - -#define SPI_MEM_ECC_ERR_INT_CLR (BIT(4)) -#define SPI_MEM_ECC_ERR_INT_CLR_M (BIT(4)) -#define SPI_MEM_ECC_ERR_INT_CLR_V 0x1 -#define SPI_MEM_ECC_ERR_INT_CLR_S 4 - -/* SPI_MEM_BROWN_OUT_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */ - -/* Description: The status bit for SPI_MEM_BROWN_OUT_INT interrupt. */ - -#define SPI_MEM_BROWN_OUT_INT_CLR (BIT(3)) -#define SPI_MEM_BROWN_OUT_INT_CLR_M (BIT(3)) -#define SPI_MEM_BROWN_OUT_INT_CLR_V 0x1 -#define SPI_MEM_BROWN_OUT_INT_CLR_S 3 - -/* SPI_MEM_TOTAL_TRANS_END_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */ - -/* Description: The clear bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. */ - -#define SPI_MEM_TOTAL_TRANS_END_INT_CLR (BIT(2)) -#define SPI_MEM_TOTAL_TRANS_END_INT_CLR_M (BIT(2)) -#define SPI_MEM_TOTAL_TRANS_END_INT_CLR_V 0x1 -#define SPI_MEM_TOTAL_TRANS_END_INT_CLR_S 2 - -/* SPI_MEM_PES_END_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */ - -/* Description: The clear bit for SPI_MEM_PES_END_INT interrupt. */ - -#define SPI_MEM_PES_END_INT_CLR (BIT(1)) -#define SPI_MEM_PES_END_INT_CLR_M (BIT(1)) -#define SPI_MEM_PES_END_INT_CLR_V 0x1 -#define SPI_MEM_PES_END_INT_CLR_S 1 - -/* SPI_MEM_PER_END_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */ - -/* Description: The clear bit for SPI_MEM_PER_END_INT interrupt. */ - -#define SPI_MEM_PER_END_INT_CLR (BIT(0)) -#define SPI_MEM_PER_END_INT_CLR_M (BIT(0)) -#define SPI_MEM_PER_END_INT_CLR_V 0x1 -#define SPI_MEM_PER_END_INT_CLR_S 0 - -#define SPI_MEM_INT_RAW_REG(i) (REG_SPI_MEM_BASE(i) + 0xF8) - -/* SPI_MEM_ECC_ERR_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */ - -/* Description: The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When - * APB_CTRL_FECC_ERR_INT_EN is set and APB_CTRL_SECC_ERR_INT_EN is cleared, - * this bit is triggered when the error times of SPI0/1 ECC read flash are - * equal or bigger than APB_CTRL_ECC_ERR_INT_NUM. - * When APB_CTRL_FECC_ERR_INT_EN is cleared and APB_CTRL_SECC_ERR_INT_EN - * is set, this bit is triggered when the error times of SPI0/1 ECC read - * external RAM are equal or bigger than - * APB_CTRL_ECC_ERR_INT_NUM. When APB_CTRL_FECC_ERR_INT_EN and - * APB_CTRL_SECC_ERR_INT_EN are set, this bit is triggered when the total - * error times of SPI0/1 ECC read external RAM and flash are equal or bigger - * than APB_CTRL_ECC_ERR_INT_NUM. When APB_CTRL_FECC_ERR_INT_EN and - * APB_CTRL_SECC_ERR_INT_EN are cleared, this bit will not be triggered. - */ - -#define SPI_MEM_ECC_ERR_INT_RAW (BIT(4)) -#define SPI_MEM_ECC_ERR_INT_RAW_M (BIT(4)) -#define SPI_MEM_ECC_ERR_INT_RAW_V 0x1 -#define SPI_MEM_ECC_ERR_INT_RAW_S 4 - -/* SPI_MEM_BROWN_OUT_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */ - -/* Description: The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. - * 1: Triggered condition is that chip is loosing power and RTC module sends - * out brown out close flash request to SPI1. After SPI1 sends out suspend - * command to flash, this interrupt is triggered and MSPI returns to idle - * state. - * 0: Others. - */ - -#define SPI_MEM_BROWN_OUT_INT_RAW (BIT(3)) -#define SPI_MEM_BROWN_OUT_INT_RAW_M (BIT(3)) -#define SPI_MEM_BROWN_OUT_INT_RAW_V 0x1 -#define SPI_MEM_BROWN_OUT_INT_RAW_S 3 - -/* SPI_MEM_TOTAL_TRANS_END_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */ - -/* Description: The raw bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. - * 1: Triggered when SPI1 transfer is done and flash is already idle. When - * WRSR/PP/SE/BE/CE is sent and PES/PER command is sent, this bit is set when - * WRSR/PP/SE/BE/CE is success. - * 0: Others. - */ - -#define SPI_MEM_TOTAL_TRANS_END_INT_RAW (BIT(2)) -#define SPI_MEM_TOTAL_TRANS_END_INT_RAW_M (BIT(2)) -#define SPI_MEM_TOTAL_TRANS_END_INT_RAW_V 0x1 -#define SPI_MEM_TOTAL_TRANS_END_INT_RAW_S 2 - -/* SPI_MEM_PES_END_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */ - -/* Description: The raw bit for SPI_MEM_PES_END_INT interrupt. - * 1: Triggered when Auto Suspend command (0x75) is sent and flash is - * suspended successfully. - * 0: Others. - */ - -#define SPI_MEM_PES_END_INT_RAW (BIT(1)) -#define SPI_MEM_PES_END_INT_RAW_M (BIT(1)) -#define SPI_MEM_PES_END_INT_RAW_V 0x1 -#define SPI_MEM_PES_END_INT_RAW_S 1 - -/* SPI_MEM_PER_END_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ - -/* Description: The raw bit for SPI_MEM_PER_END_INT interrupt. - * 1: Triggered when Auto Resume command (0x7A) is sent and flash is - * resumed successfully. - * 0: Others. - */ - -#define SPI_MEM_PER_END_INT_RAW (BIT(0)) -#define SPI_MEM_PER_END_INT_RAW_M (BIT(0)) -#define SPI_MEM_PER_END_INT_RAW_V 0x1 -#define SPI_MEM_PER_END_INT_RAW_S 0 - -#define SPI_MEM_INT_ST_REG(i) (REG_SPI_MEM_BASE(i) + 0xFC) - -/* SPI_MEM_ECC_ERR_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ - -/* Description: The status bit for SPI_MEM_ECC_ERR_INT interrupt. */ - -#define SPI_MEM_ECC_ERR_INT_ST (BIT(4)) -#define SPI_MEM_ECC_ERR_INT_ST_M (BIT(4)) -#define SPI_MEM_ECC_ERR_INT_ST_V 0x1 -#define SPI_MEM_ECC_ERR_INT_ST_S 4 - -/* SPI_MEM_BROWN_OUT_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ - -/* Description: The status bit for SPI_MEM_BROWN_OUT_INT interrupt. */ - -#define SPI_MEM_BROWN_OUT_INT_ST (BIT(3)) -#define SPI_MEM_BROWN_OUT_INT_ST_M (BIT(3)) -#define SPI_MEM_BROWN_OUT_INT_ST_V 0x1 -#define SPI_MEM_BROWN_OUT_INT_ST_S 3 - -/* SPI_MEM_TOTAL_TRANS_END_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ - -/* Description: The status bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. */ - -#define SPI_MEM_TOTAL_TRANS_END_INT_ST (BIT(2)) -#define SPI_MEM_TOTAL_TRANS_END_INT_ST_M (BIT(2)) -#define SPI_MEM_TOTAL_TRANS_END_INT_ST_V 0x1 -#define SPI_MEM_TOTAL_TRANS_END_INT_ST_S 2 - -/* SPI_MEM_PES_END_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ - -/* Description: The status bit for SPI_MEM_PES_END_INT interrupt. */ - -#define SPI_MEM_PES_END_INT_ST (BIT(1)) -#define SPI_MEM_PES_END_INT_ST_M (BIT(1)) -#define SPI_MEM_PES_END_INT_ST_V 0x1 -#define SPI_MEM_PES_END_INT_ST_S 1 - -/* SPI_MEM_PER_END_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ - -/* Description: The status bit for SPI_MEM_PER_END_INT interrupt. */ - -#define SPI_MEM_PER_END_INT_ST (BIT(0)) -#define SPI_MEM_PER_END_INT_ST_M (BIT(0)) -#define SPI_MEM_PER_END_INT_ST_V 0x1 -#define SPI_MEM_PER_END_INT_ST_S 0 - -#define SPI_MEM_DATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x3FC) - -/* SPI_MEM_DATE : R/W ;bitpos:[27:5] ;default: 23'h108082 ; */ - -/* Description: SPI register version. */ - -#define SPI_MEM_DATE 0x007FFFFF -#define SPI_MEM_DATE_M ((SPI_MEM_DATE_V)<<(SPI_MEM_DATE_S)) -#define SPI_MEM_DATE_V 0x7FFFFF -#define SPI_MEM_DATE_S 5 - -/* SPI_MEM_SPICLK_PAD_DRV_CTL_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ - -/* Description: SPI_CLK PAD driver control signal. - * 1: The driver of SPI_CLK PAD is controlled by the bits - * SPI_FMEM_SPICLK_FUN_DRV[1:0] and SPI_SMEM_SPICLK_FUN_DRV[1:0]. - * 0: The driver of SPI_CLK PAD is controlled by the bits - * IO_MUX_FUNC_DRV[1:0] of SPICLK PAD. - */ - -#define SPI_MEM_SPICLK_PAD_DRV_CTL_EN (BIT(4)) -#define SPI_MEM_SPICLK_PAD_DRV_CTL_EN_M (BIT(4)) -#define SPI_MEM_SPICLK_PAD_DRV_CTL_EN_V 0x1 -#define SPI_MEM_SPICLK_PAD_DRV_CTL_EN_S 4 - -/* SPI_MEM_SPI_FMEM_SPICLK_FUN_DRV : R/W ;bitpos:[3:2] ;default: 2'b0 ; */ - -/* Description: The driver of SPI_CLK PAD is controlled by the bits - * SPI_FMEM_SPICLK_FUN_DRV[1:0] when the bit SPI_SPICLK_PAD_DRV_CTL_EN - * is set and MSPI accesses to flash. - */ - -#define SPI_MEM_SPI_FMEM_SPICLK_FUN_DRV 0x00000003 -#define SPI_MEM_SPI_FMEM_SPICLK_FUN_DRV_M ((SPI_MEM_SPI_FMEM_SPICLK_FUN_DRV_V) << \ - (SPI_MEM_SPI_FMEM_SPICLK_FUN_DRV_S)) -#define SPI_MEM_SPI_FMEM_SPICLK_FUN_DRV_V 0x3 -#define SPI_MEM_SPI_FMEM_SPICLK_FUN_DRV_S 2 - -/* SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ - -/* Description: The driver of SPI_CLK PAD is controlled by the bits - * SPI_SMEM_SPICLK_FUN_DRV[1:0] when the bit SPI_SPICLK_PAD_DRV_CTL_EN - * is set and MSPI accesses to external RAM. - */ - -#define SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV 0x00000003 -#define SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV_M ((SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV_V)<<(SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV_S)) -#define SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV_V 0x3 -#define SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV_S 0 - -#ifdef __cplusplus -} -#endif - -#endif /* __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_SPI_MEM_REG_H */ diff --git a/arch/xtensa/src/esp32s3/hardware/esp32s3_usb_serial_jtag.h b/arch/xtensa/src/esp32s3/hardware/esp32s3_usb_serial_jtag.h index 1286d57af16ff..b370e654eeb72 100644 --- a/arch/xtensa/src/esp32s3/hardware/esp32s3_usb_serial_jtag.h +++ b/arch/xtensa/src/esp32s3/hardware/esp32s3_usb_serial_jtag.h @@ -37,7 +37,7 @@ * USB_SERIAL_JTAG_EP1_REG. */ -#define USB_SERIAL_JTAG_EP1_REG (DR_REG_USB_DEVICE_BASE + 0x0) +#define USB_SERIAL_JTAG_EP1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x0) /* USB_SERIAL_JTAG_RDWR_BYTE : R/W; bitpos: [8:0]; default: 0; * Write and read byte data to/from UART Tx/Rx FIFO through this field. @@ -59,7 +59,7 @@ * USB_SERIAL_JTAG_CONF0_REG. */ -#define USB_SERIAL_JTAG_CONF0_REG (DR_REG_USB_DEVICE_BASE + 0x18) +#define USB_SERIAL_JTAG_CONF0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x18) /* USB_SERIAL_JTAG_PHY_SEL : R/W; bitpos: [0]; default: 0; * Select internal/external PHY. 1’b0: internal PHY, 1’b1: external @@ -195,7 +195,7 @@ * USB_SERIAL_JTAG_TEST_REG. */ -#define USB_SERIAL_JTAG_TEST_REG (DR_REG_USB_DEVICE_BASE + 0x1c) +#define USB_SERIAL_JTAG_TEST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x1c) /* USB_SERIAL_JTAG_TEST_ENABLE : R/W; bitpos: [0]; default: 0; * Enable test of the USB @@ -241,7 +241,7 @@ * USB_SERIAL_JTAG_MISC_CONF_REG. */ -#define USB_SERIAL_JTAG_MISC_CONF_REG (DR_REG_USB_DEVICE_BASE + 0x44) +#define USB_SERIAL_JTAG_MISC_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x44) /* USB_SERIAL_JTAG_CLK_EN : R/W; bitpos: [0]; default: 0; * 1'h1: Force clock on for register. 1'h0: Support clock only when @@ -258,7 +258,7 @@ * USB_SERIAL_JTAG_MEM_CONF_REG. */ -#define USB_SERIAL_JTAG_MEM_CONF_REG (DR_REG_USB_DEVICE_BASE + 0x48) +#define USB_SERIAL_JTAG_MEM_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x48) /* USB_SERIAL_JTAG_USB_MEM_PD : R/W; bitpos: [0]; default: 0; * 1: power down usb @@ -286,7 +286,7 @@ * USB_SERIAL_JTAG_EP1_CONF_REG. */ -#define USB_SERIAL_JTAG_EP1_CONF_REG (DR_REG_USB_DEVICE_BASE + 0x4) +#define USB_SERIAL_JTAG_EP1_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x4) /* USB_SERIAL_JTAG_WR_DONE : WT; bitpos: [0]; default: 0; * Set this bit to indicate writing byte data to UART Tx FIFO is done. @@ -325,7 +325,7 @@ * USB_SERIAL_JTAG_JFIFO_ST_REG. */ -#define USB_SERIAL_JTAG_JFIFO_ST_REG (DR_REG_USB_DEVICE_BASE + 0x20) +#define USB_SERIAL_JTAG_JFIFO_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x20) /* USB_SERIAL_JTAG_IN_FIFO_CNT : RO; bitpos: [2:0]; default: 0; * JTAG in fifo * counter. @@ -410,7 +410,7 @@ * USB_SERIAL_JTAG_FRAM_NUM_REG. */ -#define USB_SERIAL_JTAG_FRAM_NUM_REG (DR_REG_USB_DEVICE_BASE + 0x24) +#define USB_SERIAL_JTAG_FRAM_NUM_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x24) /* USB_SERIAL_JTAG_SOF_FRAME_INDEX : RO; bitpos: [11:0]; default: 0; * Frame index of received SOF @@ -426,7 +426,7 @@ * USB_SERIAL_JTAG_IN_EP0_ST_REG. */ -#define USB_SERIAL_JTAG_IN_EP0_ST_REG (DR_REG_USB_DEVICE_BASE + 0x28) +#define USB_SERIAL_JTAG_IN_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x28) /* USB_SERIAL_JTAG_IN_EP0_STATE : RO; bitpos: [2:0]; default: 1; * State of IN Endpoint 0. @@ -459,7 +459,7 @@ * USB_SERIAL_JTAG_IN_EP1_ST_REG. */ -#define USB_SERIAL_JTAG_IN_EP1_ST_REG (DR_REG_USB_DEVICE_BASE + 0x2c) +#define USB_SERIAL_JTAG_IN_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x2c) /* USB_SERIAL_JTAG_IN_EP1_STATE : RO; bitpos: [2:0]; default: 1; * State of IN Endpoint 1. @@ -493,7 +493,7 @@ * USB_SERIAL_JTAG_IN_EP2_ST_REG. */ -#define USB_SERIAL_JTAG_IN_EP2_ST_REG (DR_REG_USB_DEVICE_BASE + 0x30) +#define USB_SERIAL_JTAG_IN_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x30) /* USB_SERIAL_JTAG_IN_EP2_STATE : RO; bitpos: [2:0]; default: 1; * State of IN Endpoint @@ -529,7 +529,7 @@ * USB_SERIAL_JTAG_IN_EP3_ST_REG. */ -#define USB_SERIAL_JTAG_IN_EP3_ST_REG (DR_REG_USB_DEVICE_BASE + 0x34) +#define USB_SERIAL_JTAG_IN_EP3_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x34) /* USB_SERIAL_JTAG_IN_EP3_STATE : RO; bitpos: [2:0]; default: 1; * State of IN Endpoint @@ -565,7 +565,7 @@ * USB_SERIAL_JTAG_OUT_EP0_ST_REG. */ -#define USB_SERIAL_JTAG_OUT_EP0_ST_REG (DR_REG_USB_DEVICE_BASE + 0x38) +#define USB_SERIAL_JTAG_OUT_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x38) /* USB_SERIAL_JTAG_OUT_EP0_STATE : RO; bitpos: [2:0]; default: 0; * State of OUT Endpoint @@ -603,7 +603,7 @@ * USB_SERIAL_JTAG_OUT_EP1_ST_REG. */ -#define USB_SERIAL_JTAG_OUT_EP1_ST_REG (DR_REG_USB_DEVICE_BASE + 0x3c) +#define USB_SERIAL_JTAG_OUT_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x3c) /* USB_SERIAL_JTAG_OUT_EP1_STATE : RO; bitpos: [2:0]; default: 0; * State of OUT Endpoint @@ -651,7 +651,7 @@ * USB_SERIAL_JTAG_OUT_EP2_ST_REG. */ -#define USB_SERIAL_JTAG_OUT_EP2_ST_REG (DR_REG_USB_DEVICE_BASE + 0x40) +#define USB_SERIAL_JTAG_OUT_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x40) /* USB_SERIAL_JTAG_OUT_EP2_STATE : RO; bitpos: [2:0]; default: 0; * State of OUT Endpoint @@ -691,7 +691,7 @@ * USB_SERIAL_JTAG_INT_RAW_REG. */ -#define USB_SERIAL_JTAG_INT_RAW_REG (DR_REG_USB_DEVICE_BASE + 0x8) +#define USB_SERIAL_JTAG_INT_RAW_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x8) /* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; * The raw interrupt bit turns to high level when a flush command is @@ -828,7 +828,7 @@ * USB_SERIAL_JTAG_INT_ST_REG. */ -#define USB_SERIAL_JTAG_INT_ST_REG (DR_REG_USB_DEVICE_BASE + 0xc) +#define USB_SERIAL_JTAG_INT_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0xc) /* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST : RO; bitpos: [0]; default: 0; * The raw interrupt status bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT @@ -959,7 +959,7 @@ * USB_SERIAL_JTAG_INT_ENA_REG. */ -#define USB_SERIAL_JTAG_INT_ENA_REG (DR_REG_USB_DEVICE_BASE + 0x10) +#define USB_SERIAL_JTAG_INT_ENA_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x10) /* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA : R/W; bitpos: [0]; default: 0; * The interrupt enable bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT * interrupt. @@ -1090,7 +1090,7 @@ * USB_SERIAL_JTAG_INT_CLR_REG. */ -#define USB_SERIAL_JTAG_INT_CLR_REG (DR_REG_USB_DEVICE_BASE + 0x14) +#define USB_SERIAL_JTAG_INT_CLR_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x14) /* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR : WT; bitpos: [0]; default: 0; * Set this bit to clear the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT @@ -1219,7 +1219,7 @@ * USB_SERIAL_JTAG_DATE_REG. */ -#define USB_SERIAL_JTAG_DATE_REG (DR_REG_USB_DEVICE_BASE + 0x80) +#define USB_SERIAL_JTAG_DATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x80) /* USB_SERIAL_JTAG_DATE : R/W; bitpos: [32:0]; default: 33583872; * register version. diff --git a/arch/xtensa/src/esp32s3/rom/esp32s3_opi_flash.h b/arch/xtensa/src/esp32s3/rom/esp32s3_opi_flash.h deleted file mode 100644 index 7ac9219c2c952..0000000000000 --- a/arch/xtensa/src/esp32s3/rom/esp32s3_opi_flash.h +++ /dev/null @@ -1,355 +0,0 @@ -/***************************************************************************** - * arch/xtensa/src/esp32s3/rom/esp32s3_opi_flash.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - *****************************************************************************/ - -#ifndef __ARCH_XTENSA_SRC_ESP32S3_ROM_ESP32S3_OPI_FLASH_H -#define __ARCH_XTENSA_SRC_ESP32S3_ROM_ESP32S3_OPI_FLASH_H - -/***************************************************************************** - * Included Files - *****************************************************************************/ - -#include -#include -#include -#include - -#ifdef __cplusplus -extern "C" -{ -#endif - -typedef struct -{ - uint8_t mode; - uint8_t cmd_bit_len; - uint16_t cmd; - uint32_t addr; - uint8_t addr_bit_len; - uint8_t dummy_bit_len; - uint8_t data_bit_len; - uint8_t cs_sel: 4; - uint8_t is_pe: 4; -} esp_rom_opiflash_cmd_t; - -typedef struct -{ - uint8_t addr_bit_len; - uint8_t dummy_bit_len; - uint16_t cmd; - uint8_t cmd_bit_len; - uint8_t var_dummy_en; -} esp_rom_opiflash_spi0rd_t; - -typedef struct -{ - esp_rom_opiflash_cmd_t rdid; - esp_rom_opiflash_cmd_t rdsr; - esp_rom_opiflash_cmd_t wren; - esp_rom_opiflash_cmd_t se; - esp_rom_opiflash_cmd_t be64k; - esp_rom_opiflash_cmd_t read; - esp_rom_opiflash_cmd_t pp; - esp_rom_opiflash_spi0rd_t cache_rd_cmd; -} esp_rom_opiflash_def_t; - -typedef struct -{ - uint16_t cmd; /* !< Command value */ - uint16_t cmd_bit_len; /* !< Command byte length */ - uint32_t *addr; /* !< Point to address value */ - uint32_t addr_bit_len; /* !< Address byte length */ - uint32_t *tx_data; /* !< Point to send data buffer */ - uint32_t tx_data_bit_len; /* !< Send data byte length. */ - uint32_t *rx_data; /* !< Point to recevie data buffer */ - uint32_t rx_data_bit_len; /* !< Recevie Data byte length. */ - uint32_t dummy_bit_len; -} esp_rom_spi_cmd_t; - -#define ESP_ROM_OPIFLASH_MUX_TAKE() -#define ESP_ROM_OPIFLASH_MUX_GIVE() -#define ESP_ROM_OPIFLASH_SEL_CS0 (BIT(0)) -#define ESP_ROM_OPIFLASH_SEL_CS1 (BIT(1)) - -/* Definition of MX25UM25645G Octa Flash - * SPI status register - */ - -#define ESP_ROM_SPIFLASH_BUSY_FLAG BIT0 -#define ESP_ROM_SPIFLASH_WRENABLE_FLAG BIT1 -#define ESP_ROM_SPIFLASH_BP0 BIT2 -#define ESP_ROM_SPIFLASH_BP1 BIT3 -#define ESP_ROM_SPIFLASH_BP2 BIT4 -#define ESP_ROM_SPIFLASH_QE BIT9 - -#define FLASH_OP_MODE_RDCMD_DOUT 0x3B -#define ESP_ROM_FLASH_SECTOR_SIZE 0x1000 -#define ESP_ROM_FLASH_BLOCK_SIZE_64K 0x10000 -#define ESP_ROM_FLASH_PAGE_SIZE 256 - -/* FLASH commands */ - -#define ROM_FLASH_CMD_RDID 0x9F -#define ROM_FLASH_CMD_WRSR 0x01 -#define ROM_FLASH_CMD_WRSR2 0x31 /* Not all SPI flash uses this command */ -#define ROM_FLASH_CMD_WREN 0x06 -#define ROM_FLASH_CMD_WRDI 0x04 -#define ROM_FLASH_CMD_RDSR 0x05 -#define ROM_FLASH_CMD_RDSR2 0x35 /* Not all SPI flash uses this command */ -#define ROM_FLASH_CMD_ERASE_SEC 0x20 -#define ROM_FLASH_CMD_ERASE_BLK_32K 0x52 -#define ROM_FLASH_CMD_ERASE_BLK_64K 0xD8 -#define ROM_FLASH_CMD_OTPEN 0x3A /* Enable OTP mode, not all SPI flash uses this command */ -#define ROM_FLASH_CMD_RSTEN 0x66 -#define ROM_FLASH_CMD_RST 0x99 - -#define ROM_FLASH_CMD_SE4B 0x21 -#define ROM_FLASH_CMD_SE4B_OCT 0xDE21 -#define ROM_FLASH_CMD_BE4B 0xDC -#define ROM_FLASH_CMD_BE4B_OCT 0x23DC -#define ROM_FLASH_CMD_RSTEN_OCT 0x9966 -#define ROM_FLASH_CMD_RST_OCT 0x6699 - -#define ROM_FLASH_CMD_FSTRD4B_STR 0x13EC -#define ROM_FLASH_CMD_FSTRD4B_DTR 0x11EE -#define ROM_FLASH_CMD_FSTRD4B 0x0C -#define ROM_FLASH_CMD_PP4B 0x12 -#define ROM_FLASH_CMD_PP4B_OCT 0xED12 - -#define ROM_FLASH_CMD_RDID_OCT 0x609F -#define ROM_FLASH_CMD_WREN_OCT 0xF906 -#define ROM_FLASH_CMD_RDSR_OCT 0xFA05 -#define ROM_FLASH_CMD_RDCR2 0x71 -#define ROM_FLASH_CMD_RDCR2_OCT 0x8E71 -#define ROM_FLASH_CMD_WRCR2 0x72 -#define ROM_FLASH_CMD_WRCR2_OCT 0x8D72 - -/* Definitions for GigaDevice GD25LX256E Flash */ - -#define ROM_FLASH_CMD_RDFSR_GD 0x70 -#define ROM_FLASH_CMD_RD_GD 0x03 -#define ROM_FLASH_CMD_RD4B_GD 0x13 -#define ROM_FLASH_CMD_FSTRD_GD 0x0B -#define ROM_FLASH_CMD_FSTRD4B_GD 0x0C -#define ROM_FLASH_CMD_FSTRD_OOUT_GD 0x8B -#define ROM_FLASH_CMD_FSTRD4B_OOUT_GD 0x7C -#define ROM_FLASH_CMD_FSTRD_OIOSTR_GD 0xCB -#define ROM_FLASH_CMD_FSTRD4B_OIOSTR_GD 0xCC -#define ROM_FLASH_CMD_FSTRD4B_OIODTR_GD 0xFD - -#define ROM_FLASH_CMD_PP_GD 0x02 -#define ROM_FLASH_CMD_PP4B_GD 0x12 -#define ROM_FLASH_CMD_PP_OOUT_GD 0x82 -#define ROM_FLASH_CMD_PP4B_OOUT_GD 0x84 -#define ROM_FLASH_CMD_PP_OIO_GD 0xC2 -#define ROM_FLASH_CMD_PP4B_OIOSTR_GD 0x8E - -#define ROM_FLASH_CMD_SE_GD 0x20 -#define ROM_FLASH_CMD_SE4B_GD 0x21 -#define ROM_FLASH_CMD_BE32K_GD 0x52 -#define ROM_FLASH_CMD_BE32K4B_GD 0x5C -#define ROM_FLASH_CMD_BE64K_GD 0xD8 -#define ROM_FLASH_CMD_BE64K4B_GD 0xDC - -#define ROM_FLASH_CMD_EN4B_GD 0xB7 -#define ROM_FLASH_CMD_DIS4B_GD 0xE9 - -extern const esp_rom_opiflash_def_t *rom_opiflash_cmd_def; - -/* Init legacy driver for Octal Flash */ - -void esp_rom_opiflash_legacy_driver_init(const esp_rom_opiflash_def_t - *flash_cmd_def); - -/* Config the spi user command - * spi_num spi port - * pcmd pointer to accept the spi command struct - */ - -void esp_rom_spi_cmd_config(int spi_num, esp_rom_spi_cmd_t *pcmd); - -/* Start a spi user command sequence - * spi_num spi port - * rx_buf buffer pointer to receive data - * rx_len receive data length in byte - * cs_en_mask decide which cs to use, 0 for cs0, 1 for cs1 - * is_write_erase to indicate whether this is a write or erase - * operation, since the CPU would check permission - */ - -void esp_rom_spi_cmd_start(int spi_num, uint8_t *rx_buf, uint16_t rx_len, - uint8_t cs_en_mask, bool is_write_erase); - -/* Config opi flash pads according to efuse settings. */ - -void esp_rom_opiflash_pin_config(void); - -/* Set SPI read/write operation mode - * spi_num spi port - * mode Flash Read Mode - */ - -void esp_rom_spi_set_op_mode(int spi_num, esp_rom_spiflash_read_mode_t mode); - -/* Set data swap mode in DTR(DDR) mode - * spi_num spi port - * wr_swap to decide whether to swap fifo data in dtr write operation - * rd_swap to decide whether to swap fifo data in dtr read operation - */ - -void esp_rom_spi_set_dtr_swap_mode(int spi, bool wr_swap, bool rd_swap); - -/* To send reset command in spi/opi-str/opi-dtr mode(for MX25UM25645G) - * spi_num spi port - */ - -void esp_rom_opiflash_mode_reset(int spi_num); - -/* To execute a flash operation command - * spi_num spi port - * mode Flash Read Mode - * cmd data to send in command field - * cmd_bit_len bit length of command field - * addr data to send in address field - * addr_bit_len bit length of address field - * dummy_bits bit length of dummy field - * mosi_data data buffer to be sent in mosi field - * mosi_bit_len bit length of data buffer to be sent in mosi field - * miso_data data buffer to accept data in miso field - * miso_bit_len bit length of data buffer to accept data in miso field - * cs_mark decide which cs pin to use. 0: cs0, 1: cs1 - * is_write_erase_operation to indicate whether this a write or erase - * flash operation - */ - -void esp_rom_opiflash_exec_cmd(int spi_num, esp_rom_spiflash_read_mode_t mode, - uint32_t cmd, int cmd_bit_len, - uint32_t addr, int addr_bit_len, - int dummy_bits, - uint8_t *mosi_data, int mosi_bit_len, - uint8_t *miso_data, int miso_bit_len, - uint32_t cs_mask, - bool is_write_erase_operation); - -/* Send reset command to opi flash - * spi_num spi port - * mode Flash Operation Mode - */ - -void esp_rom_opiflash_soft_reset(int spi_num, - esp_rom_spiflash_read_mode_t mode); - -/* To read opi flash ID - * command format would be defined in initialization - * out_id buffer to accept id - * Return flash operation result - */ - -esp_rom_spiflash_result_t esp_rom_opiflash_read_id(uint8_t *out_id); - -/* To read opi flash status register - * command format would be defined in initialization - * Return opi flash status value - */ - -uint8_t esp_rom_opiflash_rdsr(void); - -/* Wait opi flash status register to be idle - * command format would be defined in initialization - * Return flash operation result - */ - -esp_rom_spiflash_result_t esp_rom_opiflash_wait_idle(void); - -/* To erase flash sector - * command format would be defined in initialization - * sector_num the sector to be erased - * Return flash operation result - */ - -esp_rom_spiflash_result_t -esp_rom_opiflash_erase_sector(uint32_t sector_num); - -/* Erase flash block - * command format would be defined in initialization - * block_num the block to be erased - * Return flash operation result - */ - -esp_rom_spiflash_result_t -esp_rom_opiflash_erase_block_64k(uint32_t block_num); - -/* To erase a flash area define by start address and length - * command format would be defined in initialization - * start_addr the start address to be erased - * area_len the erea length to be erased - * Return flash operation result - */ - -esp_rom_spiflash_result_t esp_rom_opiflash_erase_area(uint32_t start_addr, - uint32_t area_len); - -/* To read data from opi flash - * command format would be defined in initialization - * flash_addr flash address to read data from - * data_addr data buffer to accept the data - * len data length to be read - * Return flash operation result - */ - -esp_rom_spiflash_result_t esp_rom_opiflash_read(uint32_t flash_addr, - void *data_addr, - int len); - -/* To write data to opi flash - * command format would be defined in initialization - * flash_addr flash address to write data to - * data_addr data buffer to write to flash - * len data length to write - * Return flash operation result - */ - -esp_rom_spiflash_result_t esp_rom_opiflash_write(uint32_t flash_addr, - const uint32_t *data_addr, - int len); - -/* Send WREN command - * command format would be defined in initialization - * arg not used, set to NULL - * Return flash operation result - */ - -esp_rom_spiflash_result_t esp_rom_opiflash_wren(void *arg); - -/* To configure SPI0 read flash command format for cache - * command format would be defined in initialization - */ - -void -esp_rom_opiflash_cache_mode_config(esp_rom_spiflash_read_mode_t mode, - const esp_rom_opiflash_spi0rd_t *cache); - -esp_rom_spiflash_result_t esp_rom_opiflash_read_raw(uint32_t flash_addr, - uint8_t *buf, int len); - -#ifdef __cplusplus -} -#endif - -#endif /* __ARCH_XTENSA_SRC_ESP32S3_ROM_ESP32S3_OPI_FLASH_H */ diff --git a/arch/xtensa/src/esp32s3/rom/esp32s3_spiflash.h b/arch/xtensa/src/esp32s3/rom/esp32s3_spiflash.h index 183f8150e15be..57bba4ebbec89 100644 --- a/arch/xtensa/src/esp32s3/rom/esp32s3_spiflash.h +++ b/arch/xtensa/src/esp32s3/rom/esp32s3_spiflash.h @@ -28,6 +28,11 @@ #include #include +#include "esp_rom_spiflash.h" +#include "rom/spi_flash.h" +#include "rom/opi_flash.h" +#include "esp_private/spi_flash_os.h" + #ifdef __cplusplus extern "C" { @@ -37,118 +42,16 @@ extern "C" * Pre-processor Definitions *****************************************************************************/ -#define PERIPHS_SPI_FLASH_CMD SPI_CMD_REG(1) -#define PERIPHS_SPI_FLASH_ADDR SPI_ADDR_REG(1) -#define PERIPHS_SPI_FLASH_CTRL SPI_CTRL_REG(1) -#define PERIPHS_SPI_FLASH_CTRL1 SPI_CTRL1_REG(1) -#define PERIPHS_SPI_FLASH_STATUS SPI_RD_STATUS_REG(1) -#define PERIPHS_SPI_FLASH_USRREG SPI_USER_REG(1) -#define PERIPHS_SPI_FLASH_USRREG1 SPI_USER1_REG(1) -#define PERIPHS_SPI_FLASH_USRREG2 SPI_USER2_REG(1) -#define PERIPHS_SPI_FLASH_C0 SPI_W0_REG(1) -#define PERIPHS_SPI_FLASH_C1 SPI_W1_REG(1) -#define PERIPHS_SPI_FLASH_C2 SPI_W2_REG(1) -#define PERIPHS_SPI_FLASH_C3 SPI_W3_REG(1) -#define PERIPHS_SPI_FLASH_C4 SPI_W4_REG(1) -#define PERIPHS_SPI_FLASH_C5 SPI_W5_REG(1) -#define PERIPHS_SPI_FLASH_C6 SPI_W6_REG(1) -#define PERIPHS_SPI_FLASH_C7 SPI_W7_REG(1) -#define PERIPHS_SPI_FLASH_TX_CRC SPI_TX_CRC_REG(1) - -#define SPI1_R_QIO_DUMMY_CYCLELEN 5 -#define SPI1_R_QIO_ADDR_BITSLEN 23 -#define SPI1_R_FAST_DUMMY_CYCLELEN 7 -#define SPI1_R_DIO_DUMMY_CYCLELEN 3 -#define SPI1_R_DIO_ADDR_BITSLEN 23 -#define SPI1_R_FAST_ADDR_BITSLEN 23 -#define SPI1_R_SIO_ADDR_BITSLEN 23 - -#define ESP_ROM_SPIFLASH_W_SIO_ADDR_BITSLEN 23 - -#define ESP_ROM_SPIFLASH_TWO_BYTE_STATUS_EN SPI_WRSR_2B - -/* SPI address register */ - -#define ESP_ROM_SPIFLASH_BYTES_LEN 24 -#define ESP_ROM_SPIFLASH_BUFF_BYTE_WRITE_NUM 32 -#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM 64 -#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_BITS 0x3f - -/* SPI status register */ - -#define ESP_ROM_SPIFLASH_BUSY_FLAG BIT0 -#define ESP_ROM_SPIFLASH_WRENABLE_FLAG BIT1 -#define ESP_ROM_SPIFLASH_BP0 BIT2 -#define ESP_ROM_SPIFLASH_BP1 BIT3 -#define ESP_ROM_SPIFLASH_BP2 BIT4 -#define ESP_ROM_SPIFLASH_WR_PROTECT (ESP_ROM_SPIFLASH_BP0 | \ - ESP_ROM_SPIFLASH_BP1 | \ - ESP_ROM_SPIFLASH_BP2) -#define ESP_ROM_SPIFLASH_QE BIT9 - /* Extra dummy for flash read */ #define ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_20M 0 #define ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_40M 1 #define ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_80M 2 -#define FLASH_ID_GD25LQ32C 0xC86016 - /***************************************************************************** * Public Types *****************************************************************************/ -typedef enum -{ - ESP_ROM_SPIFLASH_QIO_MODE = 0, - ESP_ROM_SPIFLASH_QOUT_MODE, - ESP_ROM_SPIFLASH_DIO_MODE, - ESP_ROM_SPIFLASH_DOUT_MODE, - ESP_ROM_SPIFLASH_FASTRD_MODE, - ESP_ROM_SPIFLASH_SLOWRD_MODE, - ESP_ROM_SPIFLASH_OPI_STR_MODE, - ESP_ROM_SPIFLASH_OPI_DTR_MODE, - ESP_ROM_SPIFLASH_OOUT_MODE, - ESP_ROM_SPIFLASH_OIO_STR_MODE, - ESP_ROM_SPIFLASH_OIO_DTR_MODE, -} esp_rom_spiflash_read_mode_t; - -typedef enum -{ - ESP_ROM_SPIFLASH_RESULT_OK, - ESP_ROM_SPIFLASH_RESULT_ERR, - ESP_ROM_SPIFLASH_RESULT_TIMEOUT -} esp_rom_spiflash_result_t; - -typedef struct -{ - uint32_t device_id; - uint32_t chip_size; /* chip size in bytes */ - uint32_t block_size; - uint32_t sector_size; - uint32_t page_size; - uint32_t status_mask; -} esp32s3_spiflash_chip_t; - -typedef struct -{ - uint8_t data_length; - uint8_t read_cmd0; - uint8_t read_cmd1; - uint8_t write_cmd; - uint16_t data_mask; - uint16_t data; -} esp_rom_spiflash_common_cmd_t; - -/* Global ROM spiflash data, as used by legacy SPI flash functions */ - -struct spiflash_legacy_data_s -{ - esp32s3_spiflash_chip_t chip; - uint8_t dummy_len_plus[3]; - uint8_t sig_matrix; -}; - /* Structure holding SPI flash access critical sections management functions. * * Flash API uses two types of functions for flash access management: @@ -330,7 +233,7 @@ void esp_rom_spiflash_attach(uint32_t ishspi, bool legacy); * Please do not call this function in SDK. * * Input Parameters: - * esp32s3_spiflash_chip_t *spi : The information for Flash, which is + * esp_rom_spiflash_chip_t *spi : The information for Flash, which is * exported from ld file. * * uint32_t *status : The pointer to which to return the Flash status value. @@ -343,7 +246,7 @@ void esp_rom_spiflash_attach(uint32_t ishspi, bool legacy); *****************************************************************************/ esp_rom_spiflash_result_t -esp_rom_spiflash_read_status(esp32s3_spiflash_chip_t *spi, +esp_rom_spiflash_read_status(esp_rom_spiflash_chip_t *spi, uint32_t *status); /***************************************************************************** @@ -355,7 +258,7 @@ esp_rom_spiflash_read_status(esp32s3_spiflash_chip_t *spi, * Please do not call this function in SDK. * * Input Parameters: - * esp32s3_spiflash_chip_t *spi : The information for Flash, which is + * esp_rom_spiflash_chip_t *spi : The information for Flash, which is * exported from ld file. * * uint32_t *status : The pointer to which to return the Flash status value. @@ -368,7 +271,7 @@ esp_rom_spiflash_read_status(esp32s3_spiflash_chip_t *spi, *****************************************************************************/ esp_rom_spiflash_result_t -esp32s3_spiflash_read_statushigh(esp32s3_spiflash_chip_t *spi, +esp32s3_spiflash_read_statushigh(esp_rom_spiflash_chip_t *spi, uint32_t *status); /***************************************************************************** @@ -380,7 +283,7 @@ esp32s3_spiflash_read_statushigh(esp32s3_spiflash_chip_t *spi, * Please do not call this function in SDK. * * Input Parameters: - * esp32s3_spiflash_chip_t *spi : The information for Flash, which is + * esp_rom_spiflash_chip_t *spi : The information for Flash, which is * exported from ld file. * * uint32_t status_value : Value to . @@ -393,7 +296,7 @@ esp32s3_spiflash_read_statushigh(esp32s3_spiflash_chip_t *spi, *****************************************************************************/ esp_rom_spiflash_result_t -esp32s3_spiflash_write_status(esp32s3_spiflash_chip_t *spi, +esp32s3_spiflash_write_status(esp_rom_spiflash_chip_t *spi, uint32_t status_value); /***************************************************************************** @@ -405,7 +308,7 @@ esp32s3_spiflash_write_status(esp32s3_spiflash_chip_t *spi, * Please do not call this function in SDK. * * Input Parameters: - * esp32s3_spiflash_chip_t *spi : The information for Flash, which is + * esp_rom_spiflash_chip_t *spi : The information for Flash, which is * exported from ld file. * * uint32_t*status : The pointer to which to return the Flash status value. @@ -803,7 +706,7 @@ esp_rom_spiflash_write_encrypted(uint32_t flash_addr, * *****************************************************************************/ -esp_rom_spiflash_result_t esp_rom_spiflash_wait_idle(esp32s3_spiflash_chip_t +esp_rom_spiflash_result_t esp_rom_spiflash_wait_idle(esp_rom_spiflash_chip_t *spi); /***************************************************************************** @@ -851,7 +754,7 @@ void esp_rom_spiflash_select_qio_pins(uint8_t wp_gpio_num, * *****************************************************************************/ -void spi_flash_guard_set(const struct spiflash_guard_funcs *funcs); +void spi_flash_guard_set(const spi_flash_guard_funcs_t *funcs); /***************************************************************************** * Name: spi_flash_write_encrypted @@ -1005,8 +908,6 @@ void spi_flash_enable_cache(uint32_t cpuid); * Public Data *****************************************************************************/ -extern struct spiflash_legacy_data_s *rom_spiflash_legacy_data; - #ifdef __cplusplus } #endif diff --git a/boards/xtensa/esp32s3/common/scripts/flat_memory.ld b/boards/xtensa/esp32s3/common/scripts/flat_memory.ld index 0df435f6507d9..84a84d0e9c146 100644 --- a/boards/xtensa/esp32s3/common/scripts/flat_memory.ld +++ b/boards/xtensa/esp32s3/common/scripts/flat_memory.ld @@ -48,6 +48,8 @@ #ifdef CONFIG_ESP32S3_APP_FORMAT_MCUBOOT #define SRAM_IRAM_END 0x403ba000 +#elif defined (CONFIG_ESPRESSIF_SIMPLE_BOOT) +#define SRAM_IRAM_END 0x403c0000 #else #define SRAM_IRAM_END 0x403cc700 #endif @@ -77,6 +79,8 @@ # define FLASH_SIZE 0x2000000 #endif +#define RESERVE_RTC_MEM 24 + MEMORY { #ifdef CONFIG_ESP32S3_APP_FORMAT_MCUBOOT @@ -92,6 +96,16 @@ MEMORY metadata (RX) : org = CONFIG_ESP32S3_APP_MCUBOOT_HEADER_SIZE, len = 0x20 ROM (RX) : org = ORIGIN(metadata) + LENGTH(metadata), len = FLASH_SIZE - ORIGIN(ROM) +#elif defined (CONFIG_ESPRESSIF_SIMPLE_BOOT) + /* The 0x20 offset is a convenience for the app binary image generation. + * Flash cache has 64KB pages. The .bin file which is flashed to the chip + * has a 0x18 byte file header, and each segment has a 0x08 byte segment + * header. Setting this offset makes it simple to meet the flash cache MMU's + * constraint that (paddr % 64KB == vaddr % 64KB). + */ + + ROM (RX) : org = 0x20, + len = FLASH_SIZE - ORIGIN(ROM) #endif /* Below values assume the flash cache is on, and have the blocks this @@ -109,12 +123,7 @@ MEMORY #ifdef CONFIG_ESP32S3_APP_FORMAT_MCUBOOT irom0_0_seg (RX) : org = 0x42000000, len = FLASH_SIZE #else - /* The 0x20 offset is a convenience for the app binary image generation. - * Flash cache has 64KB pages. The .bin file which is flashed to the chip - * has a 0x18 byte file header, and each segment has a 0x08 byte segment - * header. Setting this offset makes it simple to meet the flash cache MMU's - * constraint that (paddr % 64KB == vaddr % 64KB). - */ + /* (See ROM segment above for meaning of 0x20 offset.) */ irom0_0_seg (RX) : org = 0x42000020, len = FLASH_SIZE - 0x20 #endif @@ -144,23 +153,27 @@ MEMORY drom0_0_seg (R) : org = 0x3c000000 + ORIGIN(ROM), len = FLASH_SIZE - ORIGIN(ROM) #else - /* The 0x20 offset is a convenience for the app binary image generation. - * Flash cache has 64KB pages. The .bin file which is flashed to the chip - * has a 0x18 byte file header, and each segment has a 0x08 byte segment - * header. Setting this offset makes it simple to meet the flash cache MMU's - * constraint that (paddr % 64KB == vaddr % 64KB). - */ + /* (See ROM segment above for meaning of 0x20 offset.) */ drom0_0_seg (R) : org = 0x3c000020, len = FLASH_SIZE - 0x20 #endif /* RTC fast memory (executable). Persists over deep sleep. */ - rtc_iram_seg(RWX) : org = 0x600fe000, len = 0x2000 + rtc_iram_seg(RWX) : org = 0x600fe000, len = 0x2000 - RESERVE_RTC_MEM /* RTC fast memory (same block as above), viewed from data bus */ - rtc_data_seg(RW) : org = 0x600fe000, len = 0x2000 + rtc_data_seg(RW) : org = 0x600fe000, len = 0x2000 - RESERVE_RTC_MEM + + /* We reduced the size of rtc_iram_seg by RESERVE_RTC_MEM value. + It reserves the amount of RTC fast memory that we use for this memory segment. + This segment is intended for keeping: + - (lower addr) rtc timer data (s_rtc_timer_retain_mem, see esp_clk.c files). + - (higher addr) bootloader rtc data (s_bootloader_retain_mem, when a Kconfig option is on). + The aim of this is to keep data that will not be moved around and have a fixed address. + */ + rtc_reserved_seg(RW) : org = 0x600fe000 + 0x2000 - RESERVE_RTC_MEM, len = RESERVE_RTC_MEM /* RTC slow memory (data accessible). Persists over deep sleep. * Start of RTC slow memory is reserved for ULP co-processor code + data, diff --git a/boards/xtensa/esp32s3/common/scripts/kernel-space.ld b/boards/xtensa/esp32s3/common/scripts/kernel-space.ld index 12aaaf667b531..e08c2bca08d18 100644 --- a/boards/xtensa/esp32s3/common/scripts/kernel-space.ld +++ b/boards/xtensa/esp32s3/common/scripts/kernel-space.ld @@ -118,6 +118,8 @@ SECTIONS *libsched.a:irq_csection.*(.literal .text .literal.* .text.*) *libsched.a:irq_dispatch.*(.literal .text .literal.* .text.*) + *libc.a:*lib_instrument.*(.text .text.* .literal .literal.*) + *(.wifirxiram .wifirxiram.*) *(.wifi0iram .wifi0iram.*) *(.wifiorslpiram .wifiorslpiram.*) @@ -168,6 +170,8 @@ SECTIONS *libsched.a:irq_csection.*(.bss .bss.* COMMON) *libsched.a:irq_dispatch.*(.bss .bss.* COMMON) + *libc.a:*lib_instrument.*(.bss .bss.* COMMON) + . = ALIGN(8); _ebss = ABSOLUTE(.); } >KDRAM @@ -214,6 +218,8 @@ SECTIONS *libsched.a:irq_csection.*(.rodata .rodata.*) *libsched.a:irq_dispatch.*(.rodata .rodata.*) + *libc.a:*lib_instrument.*(.rodata .rodata.*) + . = ALIGN(4); _edata = ABSOLUTE(.); @@ -225,6 +231,8 @@ SECTIONS .flash.text : { _stext = .; + _instruction_reserved_start = ABSOLUTE(.); + *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */ *(.fini.literal) @@ -239,6 +247,7 @@ SECTIONS . += 16; + _instruction_reserved_end = ABSOLUTE(.); _etext = .; } >KIROM diff --git a/boards/xtensa/esp32s3/common/scripts/legacy_sections.ld b/boards/xtensa/esp32s3/common/scripts/legacy_sections.ld index ed4a6cbb34852..739117c5c7414 100644 --- a/boards/xtensa/esp32s3/common/scripts/legacy_sections.ld +++ b/boards/xtensa/esp32s3/common/scripts/legacy_sections.ld @@ -237,6 +237,8 @@ SECTIONS .flash.text : { _stext = .; + _instruction_reserved_start = ABSOLUTE(.); + *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */ *(.fini.literal) @@ -251,6 +253,7 @@ SECTIONS . += 16; + _instruction_reserved_end = ABSOLUTE(.); _etext = .; } >default_code_seg diff --git a/boards/xtensa/esp32s3/common/scripts/mcuboot_sections.ld b/boards/xtensa/esp32s3/common/scripts/mcuboot_sections.ld index fd1f8e92b5ca3..189ae150afb37 100644 --- a/boards/xtensa/esp32s3/common/scripts/mcuboot_sections.ld +++ b/boards/xtensa/esp32s3/common/scripts/mcuboot_sections.ld @@ -61,7 +61,7 @@ SECTIONS _image_drom_lma = LOADADDR(.flash.rodata); _image_drom_size = LOADADDR(.flash.rodata) + SIZEOF(.flash.rodata) - _image_drom_lma; - .flash.rodata : + .flash.rodata : ALIGN(4) { _rodata_reserved_start = .; @@ -69,8 +69,6 @@ SECTIONS *(EXCLUDE_FILE (esp32s3_start.*) .rodata) *(EXCLUDE_FILE (esp32s3_start.*) .rodata.*) - *(.rodata) - *(.rodata.*) #ifdef CONFIG_ESP32S3_WIRELESS *(.rodata_wlog_verbose.*) *(.rodata_wlog_debug.*) @@ -128,7 +126,7 @@ SECTIONS /* Send .iram0 code to iram */ - .iram0.vectors : + .iram0.vectors : ALIGN(4) { _iram_start = ABSOLUTE(.); @@ -168,7 +166,7 @@ SECTIONS *(.init) } >iram0_0_seg AT>ROM - .iram0.text : + .iram0.text : ALIGN(4) { /* Code marked as running out of IRAM */ @@ -185,6 +183,10 @@ SECTIONS *libarch.a:xtensa_irqdispatch.*(.literal .text .literal.* .text.*) *libarch.a:xtensa_modifyreg32.*(.literal .text .literal.* .text.*) *libarch.a:xtensa_testset.*(.literal .text .literal.* .text.*) + *libarch.a:*cache_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*uart_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*mpu_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*mmu_hal.*(.text .text.* .literal .literal.*) #ifdef CONFIG_ESP32S3_BLE *libc.a:sq_remlast.*(.literal .text .literal.* .text.*) @@ -299,7 +301,7 @@ SECTIONS . = ALIGN(4); } >dram0_0_seg - .dram0.data : + .dram0.data : ALIGN(4) { /* .data initialized on power-up in ROMed configurations. */ @@ -320,6 +322,12 @@ SECTIONS *libphy.a:(.rodata .rodata.*) *libarch.a:xtensa_context.*(.rodata .rodata.*) + *libarch.a:esp32s3_spiflash.*(.rodata .rodata.*) + *libarch.a:*cache_hal.*(.rodata .rodata.*) + *libarch.a:*uart_hal.*(.rodata .rodata.*) + *libarch.a:*mpu_hal.*(.rodata .rodata.*) + *libarch.a:*mmu_hal.*(.rodata .rodata.*) + #if defined(CONFIG_STACK_CANARIES) && \ (defined(CONFIG_ESP32S3_SPIFLASH) || \ defined(CONFIG_ESP32S3_SPIRAM)) @@ -393,6 +401,8 @@ SECTIONS .flash.text : ALIGN(0x00010000) { _stext = .; + _instruction_reserved_start = ABSOLUTE(.); + *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */ *(.fini.literal) @@ -407,6 +417,7 @@ SECTIONS . += 16; + _instruction_reserved_end = ABSOLUTE(.); _etext = .; } >irom0_0_seg AT>ROM diff --git a/boards/xtensa/esp32s3/common/scripts/simple_boot_sections.ld b/boards/xtensa/esp32s3/common/scripts/simple_boot_sections.ld new file mode 100644 index 0000000000000..a7c15d17ba340 --- /dev/null +++ b/boards/xtensa/esp32s3/common/scripts/simple_boot_sections.ld @@ -0,0 +1,572 @@ +/**************************************************************************** + * boards/xtensa/esp32s3/common/scripts/mcuboot_sections.ld + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#include + +/* Default entry point: */ + +ENTRY(__start); + +_diram_i_start = 0x40378000; + +SECTIONS +{ + /* Send .iram0 code to iram */ + + .iram0.vectors : + { + _iram_start = ABSOLUTE(.); + + /* Vectors go to IRAM. */ + + _init_start = ABSOLUTE(.); + + /* Vectors according to builds/RF-2015.2-win32/esp108_v1_2_s5_512int_2/config.html */ + + . = 0x0; + KEEP (*(.window_vectors.text)); + . = 0x180; + KEEP (*(.xtensa_level2_vector.text)); + . = 0x1c0; + KEEP (*(.xtensa_level3_vector.text)); + . = 0x200; + KEEP (*(.xtensa_level4_vector.text)); + . = 0x240; + KEEP (*(.xtensa_level5_vector.text)); + . = 0x280; + KEEP (*(.debug_exception_vector.text)); + . = 0x2c0; + KEEP (*(.nmi_vector.text)); + . = 0x300; + KEEP (*(.kernel_exception_vector.text)); + . = 0x340; + KEEP (*(.user_exception_vector.text)); + . = 0x3c0; + KEEP (*(.double_exception_vector.text)); + . = 0x400; + *(.*_vector.literal) + + . = ALIGN(16); + + *(.entry.text) + *(.init.literal) + *(.init) + _init_end = ABSOLUTE(.); + } >iram0_0_seg AT>ROM + + .iram0.text : + { + /* Code marked as running out of IRAM */ + + *(.iram1 .iram1.*) + esp32s3_start.*(.literal .text .literal.* .text.*) + + *libarch.a:esp32s3_cpuindex.*(.literal .text .literal.* .text.*) + *libarch.a:esp32s3_irq.*(.literal .text .literal.* .text.*) + *libarch.a:esp32s3_user.*(.literal .text .literal.* .text.*) + *libarch.a:esp32s3_spiflash.*(.literal .text .literal.* .text.*) + *libarch.a:xtensa_assert.*(.literal .text .literal.* .text.*) + *libarch.a:xtensa_cpuint.*(.literal .text .literal.* .text.*) + *libarch.a:xtensa_cpupause.*(.literal .text .literal.* .text.*) + *libarch.a:xtensa_irqdispatch.*(.literal .text .literal.* .text.*) + *libarch.a:xtensa_modifyreg32.*(.literal .text .literal.* .text.*) + *libarch.a:xtensa_testset.*(.literal .text .literal.* .text.*) + +#ifdef CONFIG_ESP32S3_BLE + *libc.a:sq_remlast.*(.literal .text .literal.* .text.*) +#endif + + *libdrivers.a:syslog_flush.*(.literal .text .literal.* .text.*) + + *libsched.a:assert.*(.literal .text .literal.* .text.*) + *libsched.a:irq_csection.*(.literal .text .literal.* .text.*) + *libsched.a:irq_dispatch.*(.literal .text .literal.* .text.*) + *libsched.a:irq_spinlock.*(.literal .text .literal.* .text.*) + *libsched.a:sched_note.*(.literal .text .literal.* .text.*) + *libsched.a:sched_suspendscheduler.*(.literal .text .literal.* .text.*) + *libsched.a:sched_thistask.*(.literal .text .literal.* .text.*) + *libsched.a:spinlock.*(.literal .text .literal.* .text.*) + *libsched.a:*sched_get_stackinfo.*(.literal .text .literal.* .text.*) + +#ifdef CONFIG_ESP32S3_SPEED_UP_ISR + *libarch.a:xtensa_switchcontext.*(.literal.up_switch_context .text.up_switch_context) + + *libarch.a:esp32s3_timerisr.*(.literal.systimer_isr .text.systimer_isr) + *libarch.a:esp32s3_idle.*(.literal.up_idle .text.up_idle) + *libarch.a:esp32s3_dma.*(.literal.esp32s3_dma_load .text.esp32s3_dma_load \ + .literal.esp32s3_dma_enable .text.esp32s3_dma_enable) + + *libsched.a:sched_processtimer.*(.literal.nxsched_process_timer .text.nxsched_process_timer) + *libsched.a:clock_initialize.*(.literal.clock_timer .text.clock_timer) + *libsched.a:wd_start.*(.literal.wd_timer .text.wd_timer) + *libsched.a:sched_roundrobin.*(.literal.nxsched_process_roundrobin .text.nxsched_process_roundrobin) + *libsched.a:sched_reprioritizertr.*(.literal.nxsched_reprioritize_rtr .text.nxsched_reprioritize_rtr) + *libsched.a:sched_removereadytorun.*(.literal.nxsched_remove_readytorun .text.nxsched_remove_readytorun) + *libsched.a:sched_addreadytorun.*(.literal.nxsched_add_readytorun .text.nxsched_add_readytorun) + *libsched.a:sched_addprioritized.*(.literal.nxsched_add_prioritized .text.nxsched_add_prioritized) + *libsched.a:sched_mergepending.*(.literal.nxsched_merge_pending .text.nxsched_merge_pending) + *libsched.a:sched_resumescheduler.*(.literal.nxsched_resume_scheduler .text.nxsched_resume_scheduler) + + *libc.a:sq_remfirst.*(.literal.sq_remfirst .text.sq_remfirst) +#endif + + *libarch.a:esp32s3_spi_timing.*(.literal .text .literal.* .text.*) +#ifdef CONFIG_ESP32S3_SPIRAM_MODE_QUAD + *libarch.a:esp32s3_psram_quad.*(.literal .text .literal.* .text.*) +#endif +#ifdef CONFIG_ESP32S3_SPIRAM_MODE_OCT + *libarch.a:esp32s3_psram_octal.*(.literal .text .literal.* .text.*) +#endif +#if defined(CONFIG_STACK_CANARIES) && \ + (defined(CONFIG_ESP32S3_SPIFLASH) || \ + defined(CONFIG_ESP32S3_SPIRAM)) + *libc.a:lib_stackchk.*(.literal .text .literal.* .text.*) +#endif + + *libarch.a:*brownout_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*cpu.*(.text .text.* .literal .literal.*) + *libarch.a:*gpio_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*periph_ctrl.*(.text .text.* .literal .literal.*) + *libarch.a:*clk.*(.text .text.* .literal .literal.*) + *libarch.a:*efuse_hal.*(.literal.is_eco0 .text.is_eco0) + *libarch.a:*esp_clk.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_clk_tree.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_clk_tree_common.*(.text .text.* .literal .literal.*) + *libarch.a:*clk_tree_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*rtc_init.*(.text .text.* .literal .literal.*) + *libarch.a:*rtc_clk.*(.text .text.* .literal .literal.*) + *libarch.a:*rtc_clk_init.*(.text .text.* .literal .literal.*) + *libarch.a:*rtc_sleep.*(.text .text.* .literal .literal.*) + *libarch.a:*rtc_time.*(.text .text.* .literal .literal.*) + *libarch.a:*regi2c_ctrl.*(.text .text.* .literal .literal.*) + *libarch.a:*uart_hal_iram.*(.text .text.* .literal .literal.*) + *libarch.a:*wdt_hal_iram.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_banner_wrap.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_init.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_common.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_common_loader.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_console.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_console_loader.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_esp32s3.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_flash.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_flash_config_esp32s3.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_clock_init.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_clock_loader.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_efuse.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_panic.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_mem.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_random.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable) + *libarch.a:*bootloader_random*.*(.literal.bootloader_random_enable .text.bootloader_random_enable) + *libarch.a:*bootloader_random_esp32s3.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_image_format.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_soc.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_sha.*(.text .text.* .literal .literal.*) + *libarch.a:*flash_encrypt.*(.text .text.* .literal .literal.*) + *libarch.a:*cache_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*uart_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*mpu_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*mmu_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*efuse_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*uart_periph.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_rom_uart.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_rom_sys.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_rom_spiflash.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_rom_cache_esp32s2_esp32s3.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_rom_wdt.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_efuse_fields.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_efuse_api_key.*(.text .text.* .literal .literal.*) + *libarch.a:*log.*(.text .text.* .literal .literal.*) + *libarch.a:*log_noos.*(.text .text.* .literal .literal.*) + *libarch.a:*cpu_region_protect.*(.text .text.* .literal .literal.*) + *libarch.a:*mspi_timing_tuning.*(.text .text.* .literal .literal.*) + + *libc.a:*lib_instrument.*(.text .text.* .literal .literal.*) + + *(.wifirxiram .wifirxiram.*) + *(.wifi0iram .wifi0iram.*) + *(.wifiorslpiram .wifiorslpiram.*) + *(.wifislpiram .wifislpiram.*) + *(.wifislprxiram .wifislprxiram.*) + *(.phyiram .phyiram.*) + + /* align + add 16B for CPU dummy speculative instr. fetch */ + + . = ALIGN(4) + 16; + + _iram_text = ABSOLUTE(.); + } >iram0_0_seg AT > ROM + + .dram0.dummy (NOLOAD) : + { + /* This section is required to skip .iram0.text area because iram0_0_seg + * and dram0_0_seg reflect the same address space on different buses. + */ + + . = ORIGIN(dram0_0_seg) + MAX(_iram_end, _diram_i_start) - _diram_i_start; + } >dram0_0_seg + + /* Shared RAM */ + + .dram0.bss (NOLOAD) : + { + /* .bss initialized on power-up */ + + . = ALIGN(8); + _bss_start = ABSOLUTE(.); + _sbss = ABSOLUTE(.); + + *(.bss .bss.*) + *(COMMON) + *(.dynsbss) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + *(.dynbss) + *(.share.mem) + *(.gnu.linkonce.b.*) + + . = ALIGN(8); + _ebss = ABSOLUTE(.); + _bss_end = ABSOLUTE(.); + } >dram0_0_seg + + .noinit (NOLOAD) : + { + /* This section contains data that is not initialized during load, + * or during the application's initialization sequence. + */ + + . = ALIGN(4); + + *(.noinit .noinit.*) + + . = ALIGN(4); + } >dram0_0_seg + + .dram0.data : + { + /* .data initialized on power-up in ROMed configurations. */ + . = ALIGN (16); + _data_start = ABSOLUTE(.); + _sdata = ABSOLUTE(.); + KEEP (*(.data)) + KEEP (*(.data.*)) + KEEP (*(.gnu.linkonce.d.*)) + KEEP (*(.data1)) + KEEP (*(.sdata)) + KEEP (*(.sdata.*)) + KEEP (*(.gnu.linkonce.s.*)) + KEEP (*(.sdata2)) + KEEP (*(.sdata2.*)) + KEEP (*(.gnu.linkonce.s2.*)) + KEEP (*(.jcr)) + *(.dram1 .dram1.*) + esp32s3_start.*(.rodata .rodata.*) + + *libphy.a:(.rodata .rodata.*) + *libarch.a:xtensa_context.*(.rodata .rodata.*) +#if defined(CONFIG_STACK_CANARIES) && \ + (defined(CONFIG_ESP32S3_SPIFLASH) || \ + defined(CONFIG_ESP32S3_SPIRAM)) + *libc.a:lib_stackchk.*(.rodata .rodata.*) +#endif + + *libsched.a:*sched_get_stackinfo.*(.rodata .rodata.*) + *libarch.a:esp32s3_spiflash.*(.rodata .rodata.*) + *libarch.a:*brownout.*(.rodata .rodata.*) + *libarch.a:*cpu.*(.rodata .rodata.*) + *libarch.a:*gpio_hal.*(.rodata .rodata.*) + *libarch.a:*periph_ctrl.*(.rodata .rodata.*) + *libarch.a:*clk.*(.rodata .rodata.*) + *libarch.a:*esp_clk.*(.rodata .rodata.*) + *libarch.a:*esp_clk_tree.*(.rodata .rodata.*) + *libarch.a:*esp_clk_tree_common.*(.rodata .rodata.*) + *libarch.a:*clk_tree_hal.*(.rodata .rodata.*) + *libarch.a:*rtc_init.*(.rodata .rodata.*) + *libarch.a:*rtc_clk.*(.rodata .rodata.*) + *libarch.a:*rtc_clk_init.*(.rodata .rodata.*) + *libarch.a:*rtc_sleep.*(.rodata .rodata.*) + *libarch.a:*rtc_time.*(.rodata .rodata.*) + *libarch.a:*regi2c_ctrl.*(.rodata .rodata.*) + *libarch.a:*uart_hal_iram.*(.rodata .rodata.*) + *libarch.a:*wdt_hal_iram.*(.rodata .rodata.*) + *libarch.a:*bootloader_banner_wrap.*(.rodata .rodata.*) + *libarch.a:*bootloader_init.*(.rodata .rodata.*) + *libarch.a:*bootloader_common.*(.rodata .rodata.*) + *libarch.a:*bootloader_common_loader.*(.rodata .rodata.*) + *libarch.a:*bootloader_console.*(.rodata .rodata.*) + *libarch.a:*bootloader_console_loader.*(.rodata .rodata.*) + *libarch.a:*bootloader_esp32s3.*(.rodata .rodata.*) + *libarch.a:*bootloader_flash.*(.rodata .rodata.*) + *libarch.a:*bootloader_flash_config_esp32s3.*(.rodata .rodata.*) + *libarch.a:*bootloader_clock_init.*(.rodata .rodata.*) + *libarch.a:*bootloader_clock_loader.*(.rodata .rodata.*) + *libarch.a:*bootloader_efuse.*(.rodata .rodata.*) + *libarch.a:*bootloader_panic.*(.rodata .rodata.*) + *libarch.a:*bootloader_mem.*(.rodata .rodata.*) + *libarch.a:*bootloader_random.*(.rodata .rodata.*) + *libarch.a:*bootloader_random_esp32s3.*(.rodata .rodata.*) + *libarch.a:*esp_image_format.*(.rodata .rodata.*) + *libarch.a:*bootloader_soc.*(.rodata .rodata.*) + *libarch.a:*bootloader_sha.*(.rodata .rodata.*) + *libarch.a:*flash_encrypt.*(.rodata .rodata.*) + *libarch.a:*cache_hal.*(.rodata .rodata.*) + *libarch.a:*uart_hal.*(.rodata .rodata.*) + *libarch.a:*mpu_hal.*(.rodata .rodata.*) + *libarch.a:*mmu_hal.*(.rodata .rodata.*) + *libarch.a:*uart_periph.*(.rodata .rodata.*) + *libarch.a:*esp_rom_uart.*(.rodata .rodata.*) + *libarch.a:*esp_rom_sys.*(.rodata .rodata.*) + *libarch.a:*esp_rom_spiflash.*(.rodata .rodata.*) + *libarch.a:*esp_rom_cache_esp32s2_esp32s3.*(.rodata .rodata.*) + *libarch.a:*esp_rom_wdt.*(.rodata .rodata.*) + *libarch.a:*esp_efuse_fields.*(.rodata .rodata.*) + *libarch.a:*esp_efuse_api_key.*(.rodata .rodata.*) + *libarch.a:*log.*(.rodata .rodata.*) + *libarch.a:*log_noos.*(.rodata .rodata.*) + *libarch.a:*cpu_region_protect.*(.rodata .rodata.*) + *libarch.a:*mspi_timing_tuning.*(.rodata .rodata.*) +#ifdef CONFIG_ESP32S3_SPIRAM_MODE_QUAD + *libarch.a:esp32s3_psram_quad.*(.rodata .rodata.*) +#endif +#ifdef CONFIG_ESP32S3_SPIRAM_MODE_OCT + *libarch.a:esp32s3_psram_octal.*(.rodata .rodata.*) +#endif + + . = ALIGN(4); + _edata = ABSOLUTE(.); + _data_end = ABSOLUTE(.); + + /* Heap starts at the end of .data */ + + _sheap = ABSOLUTE(.); + } >dram0_0_seg AT>ROM + + _image_drom_vma = ADDR(.flash.rodata); + _image_drom_lma = LOADADDR(.flash.rodata); + _image_drom_size = LOADADDR(.flash.rodata) + SIZEOF(.flash.rodata) - _image_drom_lma; + + /* The alignment of the ".flash.rodata" output section is forced to + * 0x00010000 (64KB) to ensure that it will be allocated at the beginning + * of the next available Flash block. + * This is required to meet the following constraint from the external + * flash MMU: + * VMA % 64KB == LMA % 64KB + * i.e. the lower 16 bits of both the virtual address (address seen by the + * CPU) and the load address (physical address of the external flash) must + * be equal. + */ + + .flash.rodata_dummy (NOLOAD) : + { + . = ALIGN(0x10000); + } > ROM + + .flash.rodata : + { + _rodata_reserved_start = ABSOLUTE(.); + + _srodata = ABSOLUTE(.); + *(EXCLUDE_FILE (esp32s3_start.*) .rodata) + *(EXCLUDE_FILE (esp32s3_start.*) .rodata.*) + + *(.rodata) + *(.rodata.*) +#ifdef CONFIG_ESP32S3_WIRELESS + *(.rodata_wlog_verbose.*) + *(.rodata_wlog_debug.*) + *(.rodata_wlog_info.*) + *(.rodata_wlog_warning.*) + *(.rodata_wlog_error.*) +#endif + *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */ + *(.gnu.linkonce.r.*) + *(.rodata1) + __XT_EXCEPTION_TABLE_ = ABSOLUTE(.); + *(.xt_except_table) + *(.gcc_except_table) + *(.gcc_except_table.*) + *(.gnu.linkonce.e.*) + *(.gnu.version_r) + *(.eh_frame) + + . = ALIGN(4); + + /* C++ constructor and destructor tables, properly ordered: */ + + _sinit = ABSOLUTE(.); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + _einit = ABSOLUTE(.); + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + + /* C++ exception handlers table: */ + + __XT_EXCEPTION_DESCS_ = ABSOLUTE(.); + *(.xt_except_desc) + *(.gnu.linkonce.h.*) + __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); + *(.xt_except_desc_end) + *(.dynamic) + *(.gnu.version_d) + _erodata = ABSOLUTE(.); + + /* Literals are also RO data. */ + + _lit4_start = ABSOLUTE(.); + *(*.lit4) + *(.lit4.*) + *(.gnu.linkonce.lit4.*) + _lit4_end = ABSOLUTE(.); + . = ALIGN(4); + } >drom0_0_seg AT>ROM + + .flash.rodata_noload (NOLOAD) : + { + /* + This is a symbol marking the flash.rodata end, this can be + used for mmu driver to maintain virtual address + We don't need to include the noload rodata in this section + */ + _rodata_reserved_end = ABSOLUTE(.); + . = ALIGN (4); + mapping[rodata_noload] + } >drom0_0_seg + + _image_irom_vma = ADDR(.flash.text); + _image_irom_lma = LOADADDR(.flash.text); + _image_irom_size = LOADADDR(.flash.text) + SIZEOF(.flash.text) - _image_irom_lma; + + .flash.text_dummy (NOLOAD) : + { + . += SIZEOF(.flash.rodata); + . = ALIGN(0x10000); + } >default_code_seg AT> ROM + + .flash.text : + { + _stext = .; + _instruction_reserved_start = ABSOLUTE(.); + + *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) + *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */ + *(.fini.literal) + *(.fini) + *(.gnu.version) + + /* CPU will try to prefetch up to 16 bytes of instructions. + * This means that any configuration (e.g. MMU, PMS) must allow + * safe access to up to 16 bytes after the last real instruction, add + * dummy bytes to ensure this + */ + + . += 16; + + _instruction_reserved_end = ABSOLUTE(.); + _etext = .; + } >irom0_0_seg AT>ROM + + /* Marks the end of IRAM code segment */ + + .iram0.text_end (NOLOAD) : + { + /* ESP32-S3 memprot requires 16B padding for possible CPU prefetch and + * 256B alignment for PMS split lines. + */ + + . += 16; + . = ALIGN(256); + _iram_end = ABSOLUTE(.); + } >iram0_0_seg + + .iram0.data : + { + . = ALIGN(4); + + *(.iram.data) + *(.iram.data.*) + } >iram0_0_seg + + .iram0.bss (NOLOAD) : + { + . = ALIGN(4); + + *(.iram.bss) + *(.iram.bss.*) + + . = ALIGN(4); + _iram_end = ABSOLUTE(.); + } >iram0_0_seg + + .rtc.text : + { + . = ALIGN(4); + *(.rtc.literal .rtc.text) + } >rtc_iram_seg AT>ROM + + /* RTC BSS section. */ + + .rtc.bss (NOLOAD) : + { + *(.rtc.bss) + } >rtc_slow_seg + + .rtc.data : + { + . = ALIGN(4); + *(.rtc.data) + *(.rtc.data.*) + *(.rtc.rodata) + *(.rtc.rodata.*) + + /* Whatever is left from the RTC memory is used as a special heap. */ + + . = ALIGN (4); + _srtcheap = ABSOLUTE(.); + } >rtc_slow_seg + + /* + * This section holds RTC data that should have fixed addresses. + * The data are not initialized at power-up and are retained during deep sleep. + */ + .rtc_reserved (NOLOAD): + { + . = ALIGN(4); + _rtc_reserved_start = ABSOLUTE(.); + /* New data can only be added here to ensure existing data are not moved. + Because data have adhered to the end of the segment and code is relied on it. + >> put new data here << */ + + *(.rtc_timer_data_in_rtc_mem .rtc_timer_data_in_rtc_mem.*) + KEEP(*(.bootloader_data_rtc_mem .bootloader_data_rtc_mem.*)) + _rtc_reserved_end = ABSOLUTE(.); + } > rtc_reserved_seg + +} diff --git a/boards/xtensa/esp32s3/common/src/esp32s3_lan9250.c b/boards/xtensa/esp32s3/common/src/esp32s3_lan9250.c index fe7120077619a..707e712a58e8e 100644 --- a/boards/xtensa/esp32s3/common/src/esp32s3_lan9250.c +++ b/boards/xtensa/esp32s3/common/src/esp32s3_lan9250.c @@ -35,14 +35,13 @@ #include #include "xtensa.h" +#include "esp32s3_efuse.h" #include "esp32s3_gpio.h" #ifdef CONFIG_LAN9250_SPI #include "esp32s3_spi.h" #else #include "esp32s3_qspi.h" #endif -#include "hardware/esp32s3_efuse.h" -#include "hardware/esp32s3_gpio_sigmap.h" /**************************************************************************** * Pre-processor Definitions @@ -175,8 +174,8 @@ static void lan9250_getmac(const struct lan9250_lower_s *lower, uint8_t *mac) uint32_t regval[2]; uint8_t *data = (uint8_t *)regval; - regval[0] = getreg32(EFUSE_RD_MAC_SPI_SYS_0_REG); - regval[1] = getreg32(EFUSE_RD_MAC_SPI_SYS_1_REG); + regval[0] = esp32s3_efuse_read_reg(EFUSE_BLK1, 0); + regval[1] = esp32s3_efuse_read_reg(EFUSE_BLK1, 1); for (int i = 0; i < 6; i++) { diff --git a/boards/xtensa/esp32s3/esp32s3-box/scripts/Make.defs b/boards/xtensa/esp32s3/esp32s3-box/scripts/Make.defs index 1f4857cd1753a..9fb14d9885791 100644 --- a/boards/xtensa/esp32s3/esp32s3-box/scripts/Make.defs +++ b/boards/xtensa/esp32s3/esp32s3-box/scripts/Make.defs @@ -38,6 +38,8 @@ else ARCHSCRIPT += $(call FINDSCRIPT,flat_memory.ld) ifeq ($(CONFIG_ESP32S3_APP_FORMAT_MCUBOOT),y) ARCHSCRIPT += $(call FINDSCRIPT,mcuboot_sections.ld) + else ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y) + ARCHSCRIPT += $(call FINDSCRIPT,simple_boot_sections.ld) else ARCHSCRIPT += $(call FINDSCRIPT,legacy_sections.ld) endif diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/eth_lan9250/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/eth_lan9250/defconfig index 798c4c7d4e625..53e3bad04dcf5 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/eth_lan9250/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/eth_lan9250/defconfig @@ -25,6 +25,7 @@ CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y CONFIG_DEFAULT_TASK_STACKSIZE=4096 +CONFIG_ESP32S3_EFUSE=y CONFIG_ESP32S3_GPIO_IRQ=y CONFIG_ESP32S3_SPI2=y CONFIG_ESP32S3_SPI_SWCS=y diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/scripts/Make.defs b/boards/xtensa/esp32s3/esp32s3-devkit/scripts/Make.defs index 5bca3415a06d5..9d7ea3f173e11 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/scripts/Make.defs +++ b/boards/xtensa/esp32s3/esp32s3-devkit/scripts/Make.defs @@ -38,6 +38,8 @@ else ARCHSCRIPT += $(call FINDSCRIPT,flat_memory.ld) ifeq ($(CONFIG_ESP32S3_APP_FORMAT_MCUBOOT),y) ARCHSCRIPT += $(call FINDSCRIPT,mcuboot_sections.ld) + else ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y) + ARCHSCRIPT += $(call FINDSCRIPT,simple_boot_sections.ld) else ARCHSCRIPT += $(call FINDSCRIPT,legacy_sections.ld) endif diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_ledc.c b/boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_ledc.c index 04ab0439120ec..deb6728dfd083 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_ledc.c +++ b/boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_ledc.c @@ -33,7 +33,6 @@ #include -#include "chip.h" #include "esp32s3_ledc.h" /**************************************************************************** diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_twai.c b/boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_twai.c index 998a49c2e228c..d6b98e28efc19 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_twai.c +++ b/boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_twai.c @@ -30,8 +30,6 @@ #include #include -#include "chip.h" - #include "esp32s3_twai.h" #include "esp32s3-devkit.h" diff --git a/boards/xtensa/esp32s3/esp32s3-eye/scripts/Make.defs b/boards/xtensa/esp32s3/esp32s3-eye/scripts/Make.defs index 001d639323c96..48aebb5325366 100644 --- a/boards/xtensa/esp32s3/esp32s3-eye/scripts/Make.defs +++ b/boards/xtensa/esp32s3/esp32s3-eye/scripts/Make.defs @@ -36,7 +36,13 @@ ifeq ($(CONFIG_BUILD_PROTECTED),y) ARCHSCRIPT += $(call FINDSCRIPT,kernel-space.ld) else ARCHSCRIPT += $(call FINDSCRIPT,flat_memory.ld) - ARCHSCRIPT += $(call FINDSCRIPT,legacy_sections.ld) + ifeq ($(CONFIG_ESP32S3_APP_FORMAT_MCUBOOT),y) + ARCHSCRIPT += $(call FINDSCRIPT,mcuboot_sections.ld) + else ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y) + ARCHSCRIPT += $(call FINDSCRIPT,simple_boot_sections.ld) + else + ARCHSCRIPT += $(call FINDSCRIPT,legacy_sections.ld) + endif endif ifneq ($(CONFIG_DEBUG_NOOPT),y) diff --git a/boards/xtensa/esp32s3/esp32s3-lcd-ev/scripts/Make.defs b/boards/xtensa/esp32s3/esp32s3-lcd-ev/scripts/Make.defs index e35a09b999617..4ac4c5647167d 100644 --- a/boards/xtensa/esp32s3/esp32s3-lcd-ev/scripts/Make.defs +++ b/boards/xtensa/esp32s3/esp32s3-lcd-ev/scripts/Make.defs @@ -38,6 +38,8 @@ else ARCHSCRIPT += $(call FINDSCRIPT,flat_memory.ld) ifeq ($(CONFIG_ESP32S3_APP_FORMAT_MCUBOOT),y) ARCHSCRIPT += $(call FINDSCRIPT,mcuboot_sections.ld) + else ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y) + ARCHSCRIPT += $(call FINDSCRIPT,simple_boot_sections.ld) else ARCHSCRIPT += $(call FINDSCRIPT,legacy_sections.ld) endif diff --git a/boards/xtensa/esp32s3/esp32s3-meadow/scripts/Make.defs b/boards/xtensa/esp32s3/esp32s3-meadow/scripts/Make.defs index 28863294b13d7..b3d65c6cb8988 100644 --- a/boards/xtensa/esp32s3/esp32s3-meadow/scripts/Make.defs +++ b/boards/xtensa/esp32s3/esp32s3-meadow/scripts/Make.defs @@ -36,7 +36,13 @@ ifeq ($(CONFIG_BUILD_PROTECTED),y) ARCHSCRIPT += $(call FINDSCRIPT,kernel-space.ld) else ARCHSCRIPT += $(call FINDSCRIPT,flat_memory.ld) - ARCHSCRIPT += $(call FINDSCRIPT,legacy_sections.ld) + ifeq ($(CONFIG_ESP32S3_APP_FORMAT_MCUBOOT),y) + ARCHSCRIPT += $(call FINDSCRIPT,mcuboot_sections.ld) + else ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y) + ARCHSCRIPT += $(call FINDSCRIPT,simple_boot_sections.ld) + else + ARCHSCRIPT += $(call FINDSCRIPT,legacy_sections.ld) + endif endif ifneq ($(CONFIG_DEBUG_NOOPT),y) diff --git a/tools/esp32s3/Config.mk b/tools/esp32s3/Config.mk index 039f1e7c54cee..b44c081a0aca3 100644 --- a/tools/esp32s3/Config.mk +++ b/tools/esp32s3/Config.mk @@ -98,6 +98,13 @@ else ifeq ($(CONFIG_ESP32S3_APP_FORMAT_MCUBOOT),y) IMGTOOL_SIGN_ARGS := --pad $(VERIFIED) $(IMGTOOL_ALIGN_ARGS) -v 0 -s auto \ -H $(CONFIG_ESP32S3_APP_MCUBOOT_HEADER_SIZE) --pad-header \ -S $(CONFIG_ESP32S3_OTA_SLOT_SIZE) +else +# CONFIG_ESPRESSIF_SIMPLE_BOOT + + APP_OFFSET := 0x0000 + APP_IMAGE := nuttx.bin + FLASH_APP := $(APP_OFFSET) $(APP_IMAGE) + ESPTOOL_BINDIR := . endif ESPTOOL_BINS += $(FLASH_APP) @@ -157,6 +164,25 @@ define MKIMAGE $(Q) echo nuttx.bin >> nuttx.manifest $(Q) echo "Generated: nuttx.bin (MCUboot compatible)" endef +else +define MKIMAGE + $(Q) echo "MKIMAGE: ESP32-S3 binary" + $(Q) if ! esptool.py version 1>/dev/null 2>&1; then \ + echo ""; \ + echo "esptool.py not found. Please run: \"pip install esptool\""; \ + echo ""; \ + echo "Run make again to create the nuttx.bin image."; \ + exit 1; \ + fi + $(Q) if [ -z $(FLASH_SIZE) ]; then \ + echo "Missing Flash memory size configuration."; \ + exit 1; \ + fi + $(eval ELF2IMAGE_OPTS := $(if $(CONFIG_ESPRESSIF_SIMPLE_BOOT),--ram-only-header) -fs $(FLASH_SIZE) -fm $(FLASH_MODE) -ff $(FLASH_FREQ)) + esptool.py -c esp32s3 elf2image $(ELF2IMAGE_OPTS) -o nuttx.bin nuttx + $(Q) echo nuttx.bin >> nuttx.manifest + $(Q) echo "Generated: nuttx.bin" +endef endif # PREBUILD -- Perform pre build operations