From cb14874c19817ae0f169aa8c8c1977491128ae9d Mon Sep 17 00:00:00 2001 From: Almir Okato Date: Thu, 14 Dec 2023 09:23:46 -0300 Subject: [PATCH] esp32c3-generic: add simple boot support The Simple Boot feature for Espressif chips is a method of booting that doesn't depend on a 2nd stage bootloader. Its not the intention to replace a 2nd stage bootloader such as MCUboot and ESP-IDF bootloader, but to have a minimal and straight-forward way of booting, and also simplify the building. This commit also makes this bootloader configuration as default for esp32c3-generic target and removes the need for running 'make bootloader' command for it. Signed-off-by: Almir Okato --- arch/risc-v/src/espressif/Bootloader.mk | 5 + arch/risc-v/src/espressif/Kconfig | 28 +- arch/risc-v/src/espressif/Make.defs | 2 +- arch/risc-v/src/espressif/esp_start.c | 267 +++++++++--- arch/risc-v/src/espressif/hal_esp32c3.mk | 43 ++ .../common/scripts/esp32c3_flat_memory.ld | 3 + .../scripts/esp32c3_mcuboot_sections.ld | 6 + .../scripts/esp32c3_simple_boot_sections.ld | 399 ++++++++++++++++++ .../esp32c3-generic/scripts/Make.defs | 2 + tools/espressif/Config.mk | 9 +- 10 files changed, 693 insertions(+), 71 deletions(-) create mode 100644 boards/risc-v/espressif/common/scripts/esp32c3_simple_boot_sections.ld diff --git a/arch/risc-v/src/espressif/Bootloader.mk b/arch/risc-v/src/espressif/Bootloader.mk index 15621de18f26c..82b3bff914057 100644 --- a/arch/risc-v/src/espressif/Bootloader.mk +++ b/arch/risc-v/src/espressif/Bootloader.mk @@ -86,6 +86,10 @@ else } >> $(BOOTLOADER_CONFIG) endif +ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y) +bootloader: + $(Q) echo "Using direct bootloader to boot NuttX." +else ifeq ($(CONFIG_ESPRESSIF_BOOTLOADER_MCUBOOT),y) BOOTLOADER_BIN = $(TOPDIR)/mcuboot-$(CHIP_SERIES).bin @@ -123,3 +127,4 @@ clean_bootloader: $(call DELFILE,$(TOPDIR)/partition-table-$(CHIP_SERIES).bin) endif +endif diff --git a/arch/risc-v/src/espressif/Kconfig b/arch/risc-v/src/espressif/Kconfig index 9f2c060b4df1c..31f7fcb1cef55 100644 --- a/arch/risc-v/src/espressif/Kconfig +++ b/arch/risc-v/src/espressif/Kconfig @@ -15,7 +15,7 @@ config ESPRESSIF_ESP32C3 select ARCH_RV_ISA_M select ARCH_RV_ISA_C select ARCH_VECNOTIRQ - select ARCH_HAVE_BOOTLOADER + select ARCH_HAVE_BOOTLOADER if !ESPRESSIF_SIMPLE_BOOT select ARCH_HAVE_MPU select ARCH_HAVE_RESET select ARCH_HAVE_RNG @@ -121,6 +121,10 @@ config ESPRESSIF_FLASH_DETECT ---help--- Auto detect flash size when flashing. +config ESPRESSIF_NUM_CPUS + int + default 1 if ESPRESSIF_ESP32C3 || ESPRESSIF_ESP32C6 || ESPRESSIF_ESP32H2 + choice ESPRESSIF_CPU_FREQ prompt "CPU frequency" default ESPRESSIF_CPU_FREQ_160 if ESPRESSIF_ESP32C3 || ESPRESSIF_ESP32C6 @@ -213,14 +217,32 @@ config ESPRESSIF_SOC_RTC_MEM_SUPPORTED menu "Bootloader and Image Configuration" +choice + prompt "Bootloader type" + default ESPRESSIF_SIMPLE_BOOT + depends on ESPRESSIF_ESP32C3 + ---help--- + Bootloader type + config ESPRESSIF_BOOTLOADER_MCUBOOT bool "Enable Native MCUboot" select ESPRESSIF_HAVE_OTA_PARTITION depends on ESPRESSIF_ESP32C3 - default n ---help--- Enables the Espressif port of MCUboot bootloader. +config ESPRESSIF_SIMPLE_BOOT + bool "Enable Simple Boot mode" + depends on ESPRESSIF_ESP32C3 + ---help--- + Enables the Simple Boot, a method of booting that doesn't depend on a + 2nd stage bootloader. Please note that some of the ESP-IDF bootloader + features are not available using direct boot, such as partition tables + and OTA. However, most of these features are implemented in NuttX and + MCUboot. + +endchoice + config ESPRESSIF_MCUBOOT_VERSION string "MCUboot version" depends on ESPRESSIF_BOOTLOADER_MCUBOOT @@ -259,7 +281,7 @@ config ESPRESSIF_APP_MCUBOOT_HEADER_SIZE config ESPRESSIF_PARTITION_TABLE_OFFSET hex "Partition Table offset" default 0x8000 - depends on !ESPRESSIF_BOOTLOADER_MCUBOOT + depends on !ESPRESSIF_BOOTLOADER_MCUBOOT && !ESPRESSIF_SIMPLE_BOOT config ESPRESSIF_HAVE_OTA_PARTITION bool diff --git a/arch/risc-v/src/espressif/Make.defs b/arch/risc-v/src/espressif/Make.defs index f0bcfc8f90062..224a0e3270e1e 100644 --- a/arch/risc-v/src/espressif/Make.defs +++ b/arch/risc-v/src/espressif/Make.defs @@ -83,7 +83,7 @@ endif ESP_HAL_3RDPARTY_REPO = esp-hal-3rdparty ifndef ESP_HAL_3RDPARTY_VERSION - ESP_HAL_3RDPARTY_VERSION = 22804823777dbbb7f43925b7729b3a32331aa7cd + ESP_HAL_3RDPARTY_VERSION = b6a943764f5e5a12d12edd8a6d71bdecc505428c endif ifndef ESP_HAL_3RDPARTY_URL diff --git a/arch/risc-v/src/espressif/esp_start.c b/arch/risc-v/src/espressif/esp_start.c index 8265f4cb6d9db..a0c9d51134b1d 100644 --- a/arch/risc-v/src/espressif/esp_start.c +++ b/arch/risc-v/src/espressif/esp_start.c @@ -40,10 +40,24 @@ #include "esp_cpu.h" #include "esp_private/brownout.h" #include "hal/wdt_hal.h" +#include "hal/mmu_hal.h" +#include "hal/mmu_types.h" +#include "hal/cache_types.h" +#include "hal/cache_ll.h" +#include "hal/cache_hal.h" #include "soc/ext_mem_defs.h" #include "soc/extmem_reg.h" #include "soc/mmu.h" #include "soc/reg_base.h" +#include "rom/cache.h" + +#ifdef CONFIG_ESPRESSIF_SIMPLE_BOOT +#include "bootloader_init.h" +#include "bootloader_flash_priv.h" +#include "esp_rom_uart.h" +#include "esp_rom_sys.h" +#include "esp_app_format.h" +#endif /**************************************************************************** * Pre-processor Definitions @@ -55,24 +69,46 @@ # define showprogress(c) #endif +#if defined(CONFIG_ESPRESSIF_BOOTLOADER_MCUBOOT) || \ + defined (CONFIG_ESPRESSIF_SIMPLE_BOOT) #ifdef CONFIG_ESPRESSIF_BOOTLOADER_MCUBOOT # define PRIMARY_SLOT_OFFSET CONFIG_ESPRESSIF_OTA_PRIMARY_SLOT_OFFSET +# define MMU_FLASH_MASK (~(MMU_BLOCK_SIZE - 1)) +#else +/* Force offset to the beginning of the whole image + */ + +# define PRIMARY_SLOT_OFFSET 0 +#endif # define HDR_ATTR __attribute__((section(".entry_addr"))) \ __attribute__((used)) # define FLASH_MMU_TABLE ((volatile uint32_t*) DR_REG_MMU_TABLE) # define FLASH_MMU_TABLE_SIZE (ICACHE_MMU_SIZE/sizeof(uint32_t)) # define MMU_BLOCK_SIZE 0x00010000 /* 64 KB */ -# define MMU_FLASH_MASK (~(MMU_BLOCK_SIZE - 1)) # define CACHE_REG EXTMEM_ICACHE_CTRL1_REG # define CACHE_MASK (EXTMEM_ICACHE_SHUT_IBUS_M | \ EXTMEM_ICACHE_SHUT_DBUS_M) + +# define CHECKSUM_ALIGN 16 +# define IS_PADD(addr) (addr == 0) +# define IS_DRAM(addr) (addr >= SOC_DRAM_LOW && addr < SOC_DRAM_HIGH) +# define IS_IRAM(addr) (addr >= SOC_IRAM_LOW && addr < SOC_IRAM_HIGH) +# define IS_IROM(addr) (addr >= SOC_IROM_LOW && addr < SOC_IROM_HIGH) +# define IS_DROM(addr) (addr >= SOC_DROM_LOW && addr < SOC_DROM_HIGH) +# define IS_SRAM(addr) (IS_IRAM(addr) || IS_DRAM(addr)) +# define IS_MMAP(addr) (IS_IROM(addr) || IS_DROM(addr)) +# define IS_NONE(addr) (!IS_IROM(addr) && !IS_DROM(addr) \ + && !IS_IRAM(addr) && !IS_DRAM(addr) && !IS_PADD(addr)) + +# define IS_MAPPING(addr) IS_IROM(addr) || IS_DROM(addr) #endif /**************************************************************************** * Private Types ****************************************************************************/ -#ifdef CONFIG_ESPRESSIF_BOOTLOADER_MCUBOOT +#if defined(CONFIG_ESPRESSIF_BOOTLOADER_MCUBOOT) || \ + defined (CONFIG_ESPRESSIF_SIMPLE_BOOT) extern uint8_t _image_irom_vma[]; extern uint8_t _image_irom_lma[]; extern uint8_t _image_irom_size[]; @@ -86,33 +122,17 @@ extern uint8_t _image_drom_size[]; * ROM Function Prototypes ****************************************************************************/ -#ifdef CONFIG_ESPRESSIF_BOOTLOADER_MCUBOOT +#if defined(CONFIG_ESPRESSIF_BOOTLOADER_MCUBOOT) || \ + defined (CONFIG_ESPRESSIF_SIMPLE_BOOT) extern int ets_printf(const char *fmt, ...) printf_like(1, 2); -extern uint32_t cache_suspend_icache(void); -extern void cache_resume_icache(uint32_t val); -extern void cache_invalidate_icache_all(void); - -#ifdef CONFIG_ESPRESSIF_ESP32C3 -extern int cache_dbus_mmu_set(uint32_t ext_ram, uint32_t vaddr, - uint32_t paddr, uint32_t psize, uint32_t num, - uint32_t fixed); -extern int cache_ibus_mmu_set(uint32_t ext_ram, uint32_t vaddr, - uint32_t paddr, uint32_t psize, uint32_t num, - uint32_t fixed); -#elif defined(CONFIG_ESPRESSIF_ESP32C6) -extern bool ets_efuse_cache_encryption_enabled(void); -extern int cache_mspi_mmu_set(uint32_t sensitive, uint32_t ext_ram, - uint32_t vaddr, uint32_t paddr, uint32_t psize, - uint32_t num, uint32_t fixed); -#endif - #endif /**************************************************************************** * Private Function Prototypes ****************************************************************************/ -#ifdef CONFIG_ESPRESSIF_BOOTLOADER_MCUBOOT +#if defined(CONFIG_ESPRESSIF_BOOTLOADER_MCUBOOT) || \ + defined (CONFIG_ESPRESSIF_SIMPLE_BOOT) IRAM_ATTR noreturn_function void __start(void); #endif @@ -120,7 +140,8 @@ IRAM_ATTR noreturn_function void __start(void); * Private Data ****************************************************************************/ -#ifdef CONFIG_ESPRESSIF_BOOTLOADER_MCUBOOT +#if defined(CONFIG_ESPRESSIF_BOOTLOADER_MCUBOOT) || \ + defined (CONFIG_ESPRESSIF_SIMPLE_BOOT) HDR_ATTR static void (*_entry_point)(void) = __start; #endif @@ -153,7 +174,8 @@ uintptr_t g_idle_topstack = ESP_IDLESTACK_TOP; * ****************************************************************************/ -#ifdef CONFIG_ESPRESSIF_BOOTLOADER_MCUBOOT +#if defined(CONFIG_ESPRESSIF_BOOTLOADER_MCUBOOT) || \ + defined (CONFIG_ESPRESSIF_SIMPLE_BOOT) static inline uint32_t calc_mmu_pages(uint32_t size, uint32_t vaddr) { return (size + (vaddr - (vaddr & MMU_FLASH_MASK)) + MMU_BLOCK_SIZE - 1) / @@ -175,55 +197,151 @@ static inline uint32_t calc_mmu_pages(uint32_t size, uint32_t vaddr) * ****************************************************************************/ -#ifdef CONFIG_ESPRESSIF_BOOTLOADER_MCUBOOT -static int map_rom_segments(void) +#if defined(CONFIG_ESPRESSIF_BOOTLOADER_MCUBOOT) || \ + defined(CONFIG_ESPRESSIF_SIMPLE_BOOT) +static int map_rom_segments(uint32_t app_drom_start, uint32_t app_drom_vaddr, + uint32_t app_drom_size, uint32_t app_irom_start, + uint32_t app_irom_vaddr, uint32_t app_irom_size) { uint32_t rc = 0; - uint32_t regval; - uint32_t drom_lma_aligned; - uint32_t drom_vma_aligned; - uint32_t drom_page_count; - uint32_t irom_lma_aligned; - uint32_t irom_vma_aligned; - uint32_t irom_page_count; + uint32_t actual_mapped_len = 0; + uint32_t app_irom_start_aligned = app_irom_start & MMU_FLASH_MASK; + uint32_t app_irom_vaddr_aligned = app_irom_vaddr & MMU_FLASH_MASK; + uint32_t app_drom_start_aligned = app_drom_start & MMU_FLASH_MASK; + uint32_t app_drom_vaddr_aligned = app_drom_vaddr & MMU_FLASH_MASK; +#ifdef CONFIG_ESPRESSIF_SIMPLE_BOOT + esp_image_header_t image_header; /* Header for entire image */ + esp_image_segment_header_t WORD_ALIGNED_ATTR segment_hdr; + bool padding_checksum = false; + unsigned int segments = 0; + unsigned int ram_segments = 0; + size_t offset = CONFIG_BOOTLOADER_OFFSET_IN_FLASH; +#endif - size_t partition_offset = PRIMARY_SLOT_OFFSET; - uint32_t app_irom_lma = partition_offset + (uint32_t)_image_irom_lma; - uint32_t app_irom_size = (uint32_t)_image_irom_size; - uint32_t app_irom_vma = (uint32_t)_image_irom_vma; - uint32_t app_drom_lma = partition_offset + (uint32_t)_image_drom_lma; - uint32_t app_drom_size = (uint32_t)_image_drom_size; - uint32_t app_drom_vma = (uint32_t)_image_drom_vma; - - uint32_t autoload = cache_suspend_icache(); - cache_invalidate_icache_all(); - - /* Clear the MMU entries that are already set up, so the new app only has - * the mappings it creates. - */ + ets_printf("\nIROM lma: 0x%lx vma: 0x%lx size: 0x%lx\n", + (uint32_t)_image_irom_lma, + (uint32_t)_image_irom_vma, + (uint32_t)_image_irom_size); + ets_printf("DROM lma: 0x%lx vma: 0x%lx size: 0x%lx\n", + (uint32_t)_image_drom_lma, + (uint32_t)_image_drom_vma, + (uint32_t)_image_drom_size); - for (size_t i = 0; i < FLASH_MMU_TABLE_SIZE; i++) +#ifdef CONFIG_ESPRESSIF_SIMPLE_BOOT + + /* Read image header */ + + if (bootloader_flash_read(offset, &image_header, + sizeof(esp_image_header_t), + true) != ESP_OK) { - FLASH_MMU_TABLE[i] = MMU_INVALID; + ets_printf("Failed to load image header!\n"); + abort(); } - drom_lma_aligned = app_drom_lma & MMU_FLASH_MASK; - drom_vma_aligned = app_drom_vma & MMU_FLASH_MASK; - drom_page_count = calc_mmu_pages(app_drom_size, app_drom_vma); - rc = cache_dbus_mmu_set(MMU_ACCESS_FLASH, drom_vma_aligned, - drom_lma_aligned, 64, (int)drom_page_count, 0); + offset += sizeof(esp_image_header_t); - irom_lma_aligned = app_irom_lma & MMU_FLASH_MASK; - irom_vma_aligned = app_irom_vma & MMU_FLASH_MASK; - irom_page_count = calc_mmu_pages(app_irom_size, app_irom_vma); - rc |= cache_ibus_mmu_set(MMU_ACCESS_FLASH, irom_vma_aligned, - irom_lma_aligned, 64, (int)irom_page_count, 0); + /* Iterate for segment information parsing */ - regval = getreg32(CACHE_REG); - regval &= ~(CACHE_MASK); - putreg32(regval, CACHE_REG); + while (segments++ < 16) + { + /* Read segment header */ + + if (bootloader_flash_read(offset, &segment_hdr, + sizeof(esp_image_segment_header_t), + true) != ESP_OK) + { + ets_printf("failed to read segment header at %x\n", offset); + abort(); + } + + if (IS_NONE(segment_hdr.load_addr)) + { + /* Total segment count = (segments - 1) */ + + break; + } + + ets_printf("%s: lma 0x%08x vma 0x%08lx len 0x%-6lx (%lu)\n", + IS_NONE(segment_hdr.load_addr) ? "???" : + IS_MMAP(segment_hdr.load_addr) ? + IS_IROM(segment_hdr.load_addr) ? "imap" : "dmap" : + IS_PADD(segment_hdr.load_addr) ? "padd" : + IS_DRAM(segment_hdr.load_addr) ? "dram" : "iram", + offset + sizeof(esp_image_segment_header_t), + segment_hdr.load_addr, segment_hdr.data_len, + segment_hdr.data_len); + + /* Fix drom and irom produced be the linker, as this + * is later invalidated by the elf2image command. + */ + + if (IS_DROM(segment_hdr.load_addr)) + { + app_drom_start = offset + sizeof(esp_image_segment_header_t); + app_drom_start_aligned = app_drom_start & MMU_FLASH_MASK; + } + + if (IS_IROM(segment_hdr.load_addr)) + { + app_irom_start = offset + sizeof(esp_image_segment_header_t); + app_irom_start_aligned = app_irom_start & MMU_FLASH_MASK; + } + + if (IS_SRAM(segment_hdr.load_addr)) + { + ram_segments++; + } + + offset += sizeof(esp_image_segment_header_t) + segment_hdr.data_len; + if (ram_segments == image_header.segment_count && !padding_checksum) + { + offset += (CHECKSUM_ALIGN - 1) - (offset % CHECKSUM_ALIGN) + 1; + padding_checksum = true; + } + } - cache_resume_icache(autoload); + if (segments == 0 || segments == 16) + { + ets_printf("Error parsing segments\n"); + } + + ets_printf("total segments stored %d\n", segments - 1); +#endif + + cache_hal_disable(CACHE_TYPE_ALL); + + /* Clear the MMU entries that are already set up, + * so the new app only has the mappings it creates. + */ + + mmu_hal_unmap_all(); + + mmu_hal_map_region(0, MMU_TARGET_FLASH0, + app_drom_vaddr_aligned, app_drom_start_aligned, + app_drom_size, &actual_mapped_len); + + mmu_hal_map_region(0, MMU_TARGET_FLASH0, + app_irom_vaddr_aligned, app_irom_start_aligned, + app_irom_size, &actual_mapped_len); + + /* ------------------Enable corresponding buses--------------------- */ + + cache_bus_mask_t bus_mask = cache_ll_l1_get_bus(0, app_drom_vaddr_aligned, + app_drom_size); + cache_ll_l1_enable_bus(0, bus_mask); + bus_mask = cache_ll_l1_get_bus(0, app_irom_vaddr_aligned, app_irom_size); + cache_ll_l1_enable_bus(0, bus_mask); +#if CONFIG_ESPRESSIF_NUM_CPUS > 1 + bus_mask = cache_ll_l1_get_bus(1, app_drom_vaddr_aligned, app_drom_size); + cache_ll_l1_enable_bus(1, bus_mask); + bus_mask = cache_ll_l1_get_bus(1, app_irom_vaddr_aligned, app_irom_size); + cache_ll_l1_enable_bus(1, bus_mask); +#endif + + /* ------------------Enable Cache----------------------------------- */ + + cache_hal_enable(CACHE_TYPE_ALL); return (int)rc; } @@ -239,13 +357,30 @@ static int map_rom_segments(void) void __esp_start(void) { -#ifdef CONFIG_ESPRESSIF_BOOTLOADER_MCUBOOT - if (map_rom_segments() != 0) +#ifdef CONFIG_ESPRESSIF_SIMPLE_BOOT + if (bootloader_init() != 0) { - ets_printf("Failed to setup XIP, aborting\n"); + ets_printf("Hardware init failed, aborting\n"); while (true); } +#endif +#if defined(CONFIG_ESPRESSIF_BOOTLOADER_MCUBOOT) || \ + defined(CONFIG_ESPRESSIF_SIMPLE_BOOT) + size_t partition_offset = PRIMARY_SLOT_OFFSET; + uint32_t app_irom_start = partition_offset + (uint32_t)_image_irom_lma; + uint32_t app_irom_size = (uint32_t)_image_irom_size; + uint32_t app_irom_vaddr = (uint32_t)_image_irom_vma; + uint32_t app_drom_start = partition_offset + (uint32_t)_image_drom_lma; + uint32_t app_drom_size = (uint32_t)_image_drom_size; + uint32_t app_drom_vaddr = (uint32_t)_image_drom_vma; + + if (map_rom_segments(app_drom_start, app_drom_vaddr, app_drom_size, + app_irom_start, app_irom_vaddr, app_irom_size) != 0) + { + ets_printf("Failed to setup XIP, aborting\n"); + while (true); + } #endif #ifdef CONFIG_ESPRESSIF_REGION_PROTECTION diff --git a/arch/risc-v/src/espressif/hal_esp32c3.mk b/arch/risc-v/src/espressif/hal_esp32c3.mk index e0ac44ba84615..aaa774e1aa17d 100644 --- a/arch/risc-v/src/espressif/hal_esp32c3.mk +++ b/arch/risc-v/src/espressif/hal_esp32c3.mk @@ -50,6 +50,15 @@ INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/compone INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/soc/include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/soc/$(CHIP_SERIES)/include +ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y) + INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/include + INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/private_include + INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/bootloader_flash/include + INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/spi_flash/include + INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/spi_flash/include/spi_flash + INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_app_format/include +endif + # Linker scripts ARCHSCRIPT += $(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_rom/$(CHIP_SERIES)/ld/$(CHIP_SERIES).rom.ld @@ -76,6 +85,7 @@ CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/esp_c CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/$(CHIP_SERIES)/esp_clk_tree.c CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/$(CHIP_SERIES)/cpu_region_protect.c CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/$(CHIP_SERIES)/rtc_clk.c +CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/$(CHIP_SERIES)/rtc_clk_init.c CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/$(CHIP_SERIES)/rtc_init.c CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/$(CHIP_SERIES)/rtc_sleep.c CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/$(CHIP_SERIES)/rtc_time.c @@ -92,6 +102,9 @@ CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/ledc_hal_iram.c CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/systimer_hal.c CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/timer_hal.c CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/timer_hal_iram.c +CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/cache_hal.c +CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/mpu_hal.c +CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/mmu_hal.c CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/uart_hal.c CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/uart_hal_iram.c CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/wdt_hal_iram.c @@ -102,3 +115,33 @@ CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/log/log_noos.c CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/riscv/interrupt.c CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/soc/$(CHIP_SERIES)/gpio_periph.c CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/soc/$(CHIP_SERIES)/ledc_periph.c + +ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y) + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/nuttx/src/bootloader_banner_wrap.c + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/src/bootloader_console.c + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/src/bootloader_console_loader.c + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/src/${CHIP_SERIES}/bootloader_${CHIP_SERIES}.c + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/src/bootloader_init.c + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/src/bootloader_common.c + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/src/bootloader_common_loader.c + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/bootloader_flash/src/bootloader_flash.c + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_${CHIP_SERIES}.c + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/src/bootloader_clock_init.c + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/src/bootloader_clock_loader.c + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/src/bootloader_efuse.c + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/src/bootloader_mem.c + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/src/bootloader_random.c + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/src/bootloader_random_${CHIP_SERIES}.c + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/src/esp_image_format.c + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/src/${CHIP_SERIES}/bootloader_soc.c + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/src/${CHIP_SERIES}/bootloader_sha.c + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/src/flash_encrypt.c + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/soc/${CHIP_SERIES}/uart_periph.c + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_rom/patches/esp_rom_uart.c + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_rom/patches/esp_rom_sys.c + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_rom/patches/esp_rom_spiflash.c + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/efuse/src/esp_efuse_fields.c + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/efuse/src/efuse_controller/keys/with_key_purposes/esp_efuse_api_key.c + + LDFLAGS += --wrap=bootloader_print_banner +endif diff --git a/boards/risc-v/espressif/common/scripts/esp32c3_flat_memory.ld b/boards/risc-v/espressif/common/scripts/esp32c3_flat_memory.ld index a9fc160421417..6df79d39cb1a7 100644 --- a/boards/risc-v/espressif/common/scripts/esp32c3_flat_memory.ld +++ b/boards/risc-v/espressif/common/scripts/esp32c3_flat_memory.ld @@ -73,6 +73,9 @@ MEMORY metadata (RX) : org = CONFIG_ESPRESSIF_APP_MCUBOOT_HEADER_SIZE, len = 0x20 ROM (RX) : org = ORIGIN(metadata) + LENGTH(metadata), len = FLASH_SIZE - ORIGIN(ROM) +#elif defined (CONFIG_ESPRESSIF_SIMPLE_BOOT) + ROM (RX) : org = ORIGIN(ROM), + len = FLASH_SIZE - ORIGIN(ROM) #endif /* Below values assume the flash cache is on, and have the blocks this diff --git a/boards/risc-v/espressif/common/scripts/esp32c3_mcuboot_sections.ld b/boards/risc-v/espressif/common/scripts/esp32c3_mcuboot_sections.ld index 960df6ebac234..bce770697db09 100644 --- a/boards/risc-v/espressif/common/scripts/esp32c3_mcuboot_sections.ld +++ b/boards/risc-v/espressif/common/scripts/esp32c3_mcuboot_sections.ld @@ -126,6 +126,9 @@ SECTIONS *(.iram1) *(.iram1.*) + *libarch.a:*cache_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*mpu_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*mmu_hal.*(.text .text.* .literal .literal.*) *libarch.a:esp_spiflash.*(.literal .text .literal.* .text.*) esp_head.*(.literal .text .literal.* .text.*) esp_start.*(.literal .text .literal.* .text.*) @@ -200,6 +203,9 @@ SECTIONS KEEP (*(.gnu.linkonce.s2.*)) KEEP (*(.jcr)) *(.dram1 .dram1.*) + *libarch.a:*cache_hal.*(.rodata .rodata.*) + *libarch.a:*mpu_hal.*(.rodata .rodata.*) + *libarch.a:*mmu_hal.*(.rodata .rodata.*) *libarch.a:esp_spiflash.*(.rodata .rodata.*) esp_head.*(.rodata .rodata.*) esp_start.*(.rodata .rodata.*) diff --git a/boards/risc-v/espressif/common/scripts/esp32c3_simple_boot_sections.ld b/boards/risc-v/espressif/common/scripts/esp32c3_simple_boot_sections.ld new file mode 100644 index 0000000000000..b1db1cb4cbf02 --- /dev/null +++ b/boards/risc-v/espressif/common/scripts/esp32c3_simple_boot_sections.ld @@ -0,0 +1,399 @@ +/**************************************************************************** + * boards/risc-v/espressif/common/scripts/esp32c3_simple_boot_sections.ld + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* Default entry point: */ + +ENTRY(__start); + +SECTIONS +{ + .iram0.text : + { + _iram_start = ABSOLUTE(.); + + /* Vectors go to start of IRAM */ + + KEEP(*(.exception_vectors.text)); + . = ALIGN(4); + + *(.iram1) + *(.iram1.*) + *libsched.a:irq_dispatch.*(.text .text.* .literal .literal.*) + + *libarch.a:*brownout.*(.text .text.* .literal .literal.*) + *libarch.a:*cpu.*(.text .text.* .literal .literal.*) + *libarch.a:*gpio_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*periph_ctrl.*(.text .text.* .literal .literal.*) + *libarch.a:*clk.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_clk.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_clk_tree.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_clk_tree_common.*(.text .text.* .literal .literal.*) + *libarch.a:*clk_tree_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*rtc_init.*(.text .text.* .literal .literal.*) + *libarch.a:*rtc_clk.*(.text .text.* .literal .literal.*) + *libarch.a:*rtc_clk_init.*(.text .text.* .literal .literal.*) + *libarch.a:*rtc_sleep.*(.text .text.* .literal .literal.*) + *libarch.a:*rtc_time.*(.text .text.* .literal .literal.*) + *libarch.a:*systimer.*(.text .text.* .literal .literal.*) + *libarch.a:*systimer_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*uart_hal_iram.*(.text .text.* .literal .literal.*) + *libarch.a:*wdt_hal_iram.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_banner_wrap.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_init.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_common.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_common_loader.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_console.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_console_loader.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_esp32c3.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_flash.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_flash_config_esp32c3.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_clock_init.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_clock_loader.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_efuse.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_panic.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_mem.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_random.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_random_esp32c3.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_image_format.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_soc.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_sha.*(.text .text.* .literal .literal.*) + *libarch.a:*flash_encrypt.*(.text .text.* .literal .literal.*) + *libarch.a:*cache_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*uart_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*mpu_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*mmu_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*uart_periph.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_rom_uart.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_rom_sys.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_rom_spiflash.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_efuse_fields.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_efuse_api_key.*(.text .text.* .literal .literal.*) + *libarch.a:*log.*(.text .text.* .literal .literal.*) + *libarch.a:*log_noos.*(.text .text.* .literal .literal.*) + *libarch.a:esp_spiflash.*(.literal .text .literal.* .text.*) + + esp_head.*(.literal .text .literal.* .text.*) + esp_start.*(.literal .text .literal.* .text.*) + + } >iram0_0_seg AT > ROM + + /* This section is required to skip .iram0.text area because iram0_0_seg + * and dram0_0_seg reflect the same address space on different buses. + */ + + .dram0.dummy (NOLOAD): + { + . = ORIGIN(dram0_0_seg) + _iram_end - _iram_start; + } >dram0_0_seg + + /* Shared RAM */ + + .dram0.bss (NOLOAD) : + { + . = ALIGN (8); + _bss_start = ABSOLUTE(.); + _sbss = ABSOLUTE(.); + *(.dynsbss) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + *(.dynbss) + *(.bss) + *(.bss.*) + *(.share.mem) + *(.gnu.linkonce.b.*) + *(COMMON) + + . = ALIGN (8); + _ebss = ABSOLUTE(.); + _bss_end = ABSOLUTE(.); + } >dram0_0_seg + + .noinit (NOLOAD): + { + /* This section contains data that is not initialized during load, + * or during the application's initialization sequence. + */ + + *(.noinit) + *(.noinit.*) + } >dram0_0_seg + + .dram0.data : + { + . = ALIGN (16); + _data_start = ABSOLUTE(.); + _sdata = ABSOLUTE(.); + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + *(.data1) + __global_pointer$ = . + 0x800; + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + *(.jcr) + *(.dram1) + *(.dram1.*) + *libsched.a:irq_dispatch.*(.rodata .rodata.*) + + *libarch.a:*brownout.*(.rodata .rodata.*) + *libarch.a:*cpu.*(.rodata .rodata.*) + *libarch.a:*gpio_hal.*(.rodata .rodata.*) + *libarch.a:*periph_ctrl.*(.rodata .rodata.*) + *libarch.a:*clk.*(.rodata .rodata.*) + *libarch.a:*esp_clk.*(.rodata .rodata.*) + *libarch.a:*esp_clk_tree.*(.rodata .rodata.*) + *libarch.a:*esp_clk_tree_common.*(.rodata .rodata.*) + *libarch.a:*clk_tree_hal.*(.rodata .rodata.*) + *libarch.a:*rtc_init.*(.rodata .rodata.*) + *libarch.a:*rtc_clk.*(.rodata .rodata.*) + *libarch.a:*rtc_clk_init.*(.rodata .rodata.*) + *libarch.a:*rtc_sleep.*(.rodata .rodata.*) + *libarch.a:*rtc_time.*(.rodata .rodata.*) + *libarch.a:*systimer.*(.rodata .rodata.*) + *libarch.a:*systimer_hal.*(.rodata .rodata.*) + *libarch.a:*uart_hal_iram.*(.rodata .rodata.*) + *libarch.a:*wdt_hal_iram.*(.rodata .rodata.*) + *libarch.a:*bootloader_banner_wrap.*(.rodata .rodata.*) + *libarch.a:*bootloader_init.*(.rodata .rodata.*) + *libarch.a:*bootloader_common.*(.rodata .rodata.*) + *libarch.a:*bootloader_common_loader.*(.rodata .rodata.*) + *libarch.a:*bootloader_console.*(.rodata .rodata.*) + *libarch.a:*bootloader_console_loader.*(.rodata .rodata.*) + *libarch.a:*bootloader_esp32c3.*(.rodata .rodata.*) + *libarch.a:*bootloader_flash.*(.rodata .rodata.*) + *libarch.a:*bootloader_flash_config_esp32c3.*(.rodata .rodata.*) + *libarch.a:*bootloader_clock_init.*(.rodata .rodata.*) + *libarch.a:*bootloader_clock_loader.*(.rodata .rodata.*) + *libarch.a:*bootloader_efuse.*(.rodata .rodata.*) + *libarch.a:*bootloader_panic.*(.rodata .rodata.*) + *libarch.a:*bootloader_mem.*(.rodata .rodata.*) + *libarch.a:*bootloader_random.*(.rodata .rodata.*) + *libarch.a:*bootloader_random_esp32c3.*(.rodata .rodata.*) + *libarch.a:*esp_image_format.*(.rodata .rodata.*) + *libarch.a:*bootloader_soc.*(.rodata .rodata.*) + *libarch.a:*bootloader_sha.*(.rodata .rodata.*) + *libarch.a:*flash_encrypt.*(.rodata .rodata.*) + *libarch.a:*cache_hal.*(.rodata .rodata.*) + *libarch.a:*uart_hal.*(.rodata .rodata.*) + *libarch.a:*mpu_hal.*(.rodata .rodata.*) + *libarch.a:*mmu_hal.*(.rodata .rodata.*) + *libarch.a:*uart_periph.*(.rodata .rodata.*) + *libarch.a:*esp_rom_uart.*(.rodata .rodata.*) + *libarch.a:*esp_rom_sys.*(.rodata .rodata.*) + *libarch.a:*esp_rom_spiflash.*(.rodata .rodata.*) + *libarch.a:*esp_efuse_fields.*(.rodata .rodata.*) + *libarch.a:*esp_efuse_api_key.*(.rodata .rodata.*) + *libarch.a:*log.*(.rodata .rodata.*) + *libarch.a:*log_noos.*(.rodata .rodata.*) + *libarch.a:esp_spiflash.*(.rodata .rodata.*) + + esp_head.*(.rodata .rodata.*) + esp_start.*(.rodata .rodata.*) + + . = ALIGN(4); + _edata = ABSOLUTE(.); + _data_end = ABSOLUTE(.); + + /* Heap starts at the end of .data */ + + _sheap = ABSOLUTE(.); + } >dram0_0_seg AT > ROM + + _image_irom_vma = ADDR(.flash.text); + _image_irom_lma = LOADADDR(.flash.text); + _image_irom_size = LOADADDR(.flash.text) + SIZEOF(.flash.text) - _image_irom_lma; + + .flash.text : ALIGN(0xFFFF) + { + _stext = .; + + *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) + *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */ + *(.fini.literal) + *(.fini) + *(.gnu.version) + _etext = .; + + /* Similar to _iram_start, this symbol goes here so it is + * resolved by addr2line in preference to the first symbol in + * the flash.text segment. + */ + + _flash_cache_start = ABSOLUTE(0); + } >default_code_seg AT > ROM + + .flash_rodata_dummy (NOLOAD) : ALIGN(0xFFFF) + { + /* Start at the same alignment constraint than .flash.text */ + + /* . = ALIGN(ALIGNOF(.flash.text)); */ + + /* Create an empty gap as big as .flash.text section */ + + . = . + SIZEOF(.flash.text); + + /* Prepare the alignment of the section above. Few bytes (0x20) must be + * added for the mapping header. + */ + + /*. = ALIGN(0x10000) + 0x20; */ + } >default_rodata_seg + + _image_drom_vma = ADDR(.flash.rodata); + _image_drom_lma = LOADADDR(.flash.rodata); + _image_drom_size = LOADADDR(.flash.rodata) + SIZEOF(.flash.rodata) - _image_drom_lma; + + .flash.rodata : ALIGN(0xFFFF) + { + _srodata = ABSOLUTE(.); + *(EXCLUDE_FILE (*libarch.a:esp_spiflash.* esp_head.* esp_start.*) .rodata) + *(EXCLUDE_FILE (*libarch.a:esp_spiflash.* esp_head.* esp_start.*) .rodata.*) + + *(.rodata) + *(.rodata.*) + + *(.srodata.*) + + *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */ + *(.gnu.linkonce.r.*) + *(.rodata1) + __XT_EXCEPTION_TABLE_ = ABSOLUTE(.); + *(.xt_except_table) + *(.gcc_except_table .gcc_except_table.*) + *(.gnu.linkonce.e.*) + *(.gnu.version_r) + . = (. + 3) & ~ 3; + __eh_frame = ABSOLUTE(.); + KEEP(*(.eh_frame)) + . = (. + 7) & ~ 3; + + /* C++ constructor and destructor tables: + * RISC-V GCC is configured with --enable-initfini-array so it emits an + * .init_array section instead. + */ + + _sinit = ABSOLUTE(.); + KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array.*)) + KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array)) + _einit = ABSOLUTE(.); + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + + /* C++ exception handlers table: */ + + __XT_EXCEPTION_DESCS_ = ABSOLUTE(.); + *(.xt_except_desc) + *(.gnu.linkonce.h.*) + __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); + *(.xt_except_desc_end) + *(.dynamic) + *(.gnu.version_d) + _erodata = ABSOLUTE(.); + + /* Literals are also RO data. */ + + _lit4_start = ABSOLUTE(.); + *(*.lit4) + *(.lit4.*) + *(.gnu.linkonce.lit4.*) + _lit4_end = ABSOLUTE(.); + . = ALIGN(4); + } >default_rodata_seg AT > ROM + + /* Marks the end of IRAM code segment */ + + .iram0.text_end (NOLOAD) : + { + . = ALIGN (16); + } >iram0_0_seg + + .iram0.data : + { + . = ALIGN(16); + *(.iram.data) + *(.iram.data*) + } >iram0_0_seg + + .iram0.bss (NOLOAD) : + { + . = ALIGN(16); + *(.iram.bss) + *(.iram.bss*) + + . = ALIGN(16); + _iram_end = ABSOLUTE(.); + } >iram0_0_seg + + /* RTC fast memory holds RTC wake stub code !*/ + + .rtc.text : + { + . = ALIGN(4); + *(.rtc.literal .rtc.text) + } >rtc_iram_seg + + /* RTC BSS section. */ + + .rtc.bss (NOLOAD) : + { + *(.rtc.bss) + } >rtc_iram_seg + + /* RTC data section holds RTC wake stub data/rodata. */ + + .rtc.data : + { + *(.rtc.data) + *(.rtc.rodata) + } >rtc_iram_seg + + /* This section holds RTC data that should have fixed addresses. + * The data are not initialized at power-up and are retained during deep sleep. + */ + .rtc_reserved (NOLOAD): + { + . = ALIGN(4); + _rtc_reserved_start = ABSOLUTE(.); + /* New data can only be added here to ensure existing data are not moved. + Because data have adhered to the end of the segment and code is relied on it. + >> put new data here << */ + + *(.rtc_timer_data_in_rtc_mem .rtc_timer_data_in_rtc_mem.*) + KEEP(*(.bootloader_data_rtc_mem .bootloader_data_rtc_mem.*)) + _rtc_reserved_end = ABSOLUTE(.); + } > rtc_reserved_seg + + _rtc_reserved_length = _rtc_reserved_end - _rtc_reserved_start; + ASSERT((_rtc_reserved_length <= LENGTH(rtc_reserved_seg)), + "RTC reserved segment data does not fit.") + +} + diff --git a/boards/risc-v/espressif/esp32c3-generic/scripts/Make.defs b/boards/risc-v/espressif/esp32c3-generic/scripts/Make.defs index 9236ebb6fc4b5..ffd7e0220d8a4 100644 --- a/boards/risc-v/espressif/esp32c3-generic/scripts/Make.defs +++ b/boards/risc-v/espressif/esp32c3-generic/scripts/Make.defs @@ -35,6 +35,8 @@ ARCHSCRIPT += $(call FINDSCRIPT,$(CHIP_SERIES)_flat_memory.ld) ifeq ($(CONFIG_ESPRESSIF_BOOTLOADER_MCUBOOT),y) ARCHSCRIPT += $(call FINDSCRIPT,$(CHIP_SERIES)_mcuboot_sections.ld) +else ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y) + ARCHSCRIPT += $(call FINDSCRIPT,$(CHIP_SERIES)_simple_boot_sections.ld) else ARCHSCRIPT += $(call FINDSCRIPT,$(CHIP_SERIES)_legacy_sections.ld) endif diff --git a/tools/espressif/Config.mk b/tools/espressif/Config.mk index d95b594b1b570..e2d9b4cb8d503 100644 --- a/tools/espressif/Config.mk +++ b/tools/espressif/Config.mk @@ -72,6 +72,8 @@ ifdef ESPTOOL_BINDIR BOOTLOADER := $(ESPTOOL_BINDIR)/mcuboot-$(CHIP_SERIES).bin FLASH_BL := $(BL_OFFSET) $(BOOTLOADER) ESPTOOL_BINS := $(FLASH_BL) + else ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y) + else BL_OFFSET := 0x0 PT_OFFSET := $(CONFIG_ESPRESSIF_PARTITION_TABLE_OFFSET) @@ -98,6 +100,11 @@ ifeq ($(CONFIG_ESPRESSIF_BOOTLOADER_MCUBOOT),y) IMGTOOL_SIGN_ARGS := --pad $(VERIFIED) $(IMGTOOL_ALIGN_ARGS) -v 0 -s auto \ -H $(CONFIG_ESPRESSIF_APP_MCUBOOT_HEADER_SIZE) --pad-header \ -S $(CONFIG_ESPRESSIF_OTA_SLOT_SIZE) +else ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y) + APP_OFFSET := 0x0000 + APP_IMAGE := nuttx.bin + FLASH_APP := $(APP_OFFSET) $(APP_IMAGE) + ESPTOOL_BINDIR := . else APP_OFFSET := 0x10000 APP_IMAGE := nuttx.bin @@ -157,7 +164,7 @@ define MKIMAGE echo "Missing Flash memory size configuration."; \ exit 1; \ fi - $(eval ELF2IMAGE_OPTS := -fs $(FLASH_SIZE) -fm $(FLASH_MODE) -ff $(FLASH_FREQ)) + $(eval ELF2IMAGE_OPTS := $(if $(CONFIG_ESPRESSIF_SIMPLE_BOOT),--ram-only-header) -fs $(FLASH_SIZE) -fm $(FLASH_MODE) -ff $(FLASH_FREQ)) esptool.py -c $(CHIP_SERIES) elf2image $(ELF2IMAGE_OPTS) -o nuttx.bin nuttx $(Q) echo nuttx.bin >> nuttx.manifest $(Q) echo "Generated: nuttx.bin"