diff --git a/Examples/MAX32657/Hello_World/.cproject b/Examples/MAX32657/Hello_World/.cproject new file mode 100644 index 00000000000..3a8a4199e81 --- /dev/null +++ b/Examples/MAX32657/Hello_World/.cproject @@ -0,0 +1,81 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Examples/MAX32657/Hello_World/.project b/Examples/MAX32657/Hello_World/.project new file mode 100644 index 00000000000..d21c0a970b7 --- /dev/null +++ b/Examples/MAX32657/Hello_World/.project @@ -0,0 +1,26 @@ + + + Hello_World + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/Examples/MAX32657/Hello_World/.settings/language.settings.xml b/Examples/MAX32657/Hello_World/.settings/language.settings.xml new file mode 100644 index 00000000000..d32717b6f37 --- /dev/null +++ b/Examples/MAX32657/Hello_World/.settings/language.settings.xml @@ -0,0 +1,15 @@ + + + + + + + + + + + + + + + diff --git a/Examples/MAX32657/Hello_World/.settings/org.eclipse.cdt.codan.core.prefs b/Examples/MAX32657/Hello_World/.settings/org.eclipse.cdt.codan.core.prefs new file mode 100644 index 00000000000..59c0b37ba75 --- /dev/null +++ b/Examples/MAX32657/Hello_World/.settings/org.eclipse.cdt.codan.core.prefs @@ -0,0 +1,93 @@ +eclipse.preferences.version=1 +org.eclipse.cdt.codan.checkers.errnoreturn=Warning +org.eclipse.cdt.codan.checkers.errnoreturn.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"No return\\")",implicit\=>false} +org.eclipse.cdt.codan.checkers.errreturnvalue=Error +org.eclipse.cdt.codan.checkers.errreturnvalue.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused return value\\")"} +org.eclipse.cdt.codan.checkers.nocommentinside=-Error +org.eclipse.cdt.codan.checkers.nocommentinside.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Nesting comments\\")"} +org.eclipse.cdt.codan.checkers.nolinecomment=-Error +org.eclipse.cdt.codan.checkers.nolinecomment.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Line comments\\")"} +org.eclipse.cdt.codan.checkers.noreturn=Error +org.eclipse.cdt.codan.checkers.noreturn.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"No return value\\")",implicit\=>false} +org.eclipse.cdt.codan.internal.checkers.AbstractClassCreation=Error +org.eclipse.cdt.codan.internal.checkers.AbstractClassCreation.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Abstract class cannot be instantiated\\")"} +org.eclipse.cdt.codan.internal.checkers.AmbiguousProblem=Error +org.eclipse.cdt.codan.internal.checkers.AmbiguousProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Ambiguous problem\\")"} +org.eclipse.cdt.codan.internal.checkers.AssignmentInConditionProblem=Warning +org.eclipse.cdt.codan.internal.checkers.AssignmentInConditionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Assignment in condition\\")"} +org.eclipse.cdt.codan.internal.checkers.AssignmentToItselfProblem=Error +org.eclipse.cdt.codan.internal.checkers.AssignmentToItselfProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Assignment to itself\\")"} +org.eclipse.cdt.codan.internal.checkers.CStyleCastProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.CStyleCastProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"C-Style cast instead of C++ cast\\")"} +org.eclipse.cdt.codan.internal.checkers.CaseBreakProblem=Warning +org.eclipse.cdt.codan.internal.checkers.CaseBreakProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"No break at end of case\\")",no_break_comment\=>"no break",last_case_param\=>false,empty_case_param\=>false,enable_fallthrough_quickfix_param\=>false} +org.eclipse.cdt.codan.internal.checkers.CatchByReference=Warning +org.eclipse.cdt.codan.internal.checkers.CatchByReference.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Catching by reference is recommended\\")",unknown\=>false,exceptions\=>()} +org.eclipse.cdt.codan.internal.checkers.CircularReferenceProblem=Error +org.eclipse.cdt.codan.internal.checkers.CircularReferenceProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Circular inheritance\\")"} +org.eclipse.cdt.codan.internal.checkers.ClassMembersInitialization=Warning +org.eclipse.cdt.codan.internal.checkers.ClassMembersInitialization.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Class members should be properly initialized\\")",skip\=>true} +org.eclipse.cdt.codan.internal.checkers.CopyrightProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.CopyrightProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Lack of copyright information\\")",regex\=>".*Copyright.*"} +org.eclipse.cdt.codan.internal.checkers.DecltypeAutoProblem=Error +org.eclipse.cdt.codan.internal.checkers.DecltypeAutoProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid 'decltype(auto)' specifier\\")"} +org.eclipse.cdt.codan.internal.checkers.FieldResolutionProblem=Error +org.eclipse.cdt.codan.internal.checkers.FieldResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Field cannot be resolved\\")"} +org.eclipse.cdt.codan.internal.checkers.FunctionResolutionProblem=Error +org.eclipse.cdt.codan.internal.checkers.FunctionResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Function cannot be resolved\\")"} +org.eclipse.cdt.codan.internal.checkers.GotoStatementProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.GotoStatementProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Goto statement used\\")"} +org.eclipse.cdt.codan.internal.checkers.InvalidArguments=Error +org.eclipse.cdt.codan.internal.checkers.InvalidArguments.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid arguments\\")"} +org.eclipse.cdt.codan.internal.checkers.InvalidTemplateArgumentsProblem=Error +org.eclipse.cdt.codan.internal.checkers.InvalidTemplateArgumentsProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid template argument\\")"} +org.eclipse.cdt.codan.internal.checkers.LabelStatementNotFoundProblem=Error +org.eclipse.cdt.codan.internal.checkers.LabelStatementNotFoundProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Label statement not found\\")"} +org.eclipse.cdt.codan.internal.checkers.MemberDeclarationNotFoundProblem=Error +org.eclipse.cdt.codan.internal.checkers.MemberDeclarationNotFoundProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Member declaration not found\\")"} +org.eclipse.cdt.codan.internal.checkers.MethodResolutionProblem=Error +org.eclipse.cdt.codan.internal.checkers.MethodResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Method cannot be resolved\\")"} +org.eclipse.cdt.codan.internal.checkers.MissCaseProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.MissCaseProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Missing cases in switch\\")"} +org.eclipse.cdt.codan.internal.checkers.MissDefaultProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.MissDefaultProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Missing default in switch\\")",defaultWithAllEnums\=>false} +org.eclipse.cdt.codan.internal.checkers.MissReferenceProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.MissReferenceProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Missing reference return value in assignment operator\\")"} +org.eclipse.cdt.codan.internal.checkers.MissSelfCheckProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.MissSelfCheckProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Missing self check in assignment operator\\")"} +org.eclipse.cdt.codan.internal.checkers.NamingConventionFunctionChecker=-Info +org.eclipse.cdt.codan.internal.checkers.NamingConventionFunctionChecker.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Name convention for function\\")",pattern\=>"^[a-z]",macro\=>true,exceptions\=>()} +org.eclipse.cdt.codan.internal.checkers.NonVirtualDestructorProblem=Warning +org.eclipse.cdt.codan.internal.checkers.NonVirtualDestructorProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Class has a virtual method and non-virtual destructor\\")"} +org.eclipse.cdt.codan.internal.checkers.OverloadProblem=Error +org.eclipse.cdt.codan.internal.checkers.OverloadProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid overload\\")"} +org.eclipse.cdt.codan.internal.checkers.RedeclarationProblem=Error +org.eclipse.cdt.codan.internal.checkers.RedeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid redeclaration\\")"} +org.eclipse.cdt.codan.internal.checkers.RedefinitionProblem=Error +org.eclipse.cdt.codan.internal.checkers.RedefinitionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid redefinition\\")"} +org.eclipse.cdt.codan.internal.checkers.ReturnStyleProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.ReturnStyleProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Return with parenthesis\\")"} +org.eclipse.cdt.codan.internal.checkers.ScanfFormatStringSecurityProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.ScanfFormatStringSecurityProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Format String Vulnerability\\")"} +org.eclipse.cdt.codan.internal.checkers.StatementHasNoEffectProblem=Warning +org.eclipse.cdt.codan.internal.checkers.StatementHasNoEffectProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Statement has no effect\\")",macro\=>true,exceptions\=>()} +org.eclipse.cdt.codan.internal.checkers.SuggestedParenthesisProblem=Warning +org.eclipse.cdt.codan.internal.checkers.SuggestedParenthesisProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Suggested parenthesis around expression\\")",paramNot\=>false} +org.eclipse.cdt.codan.internal.checkers.SuspiciousSemicolonProblem=Warning +org.eclipse.cdt.codan.internal.checkers.SuspiciousSemicolonProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Suspicious semicolon\\")",else\=>false,afterelse\=>false} +org.eclipse.cdt.codan.internal.checkers.TypeResolutionProblem=Error +org.eclipse.cdt.codan.internal.checkers.TypeResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Type cannot be resolved\\")"} +org.eclipse.cdt.codan.internal.checkers.UnusedFunctionDeclarationProblem=Warning +org.eclipse.cdt.codan.internal.checkers.UnusedFunctionDeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused function declaration\\")",macro\=>true} +org.eclipse.cdt.codan.internal.checkers.UnusedStaticFunctionProblem=Warning +org.eclipse.cdt.codan.internal.checkers.UnusedStaticFunctionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused static function\\")",macro\=>true} +org.eclipse.cdt.codan.internal.checkers.UnusedVariableDeclarationProblem=Warning +org.eclipse.cdt.codan.internal.checkers.UnusedVariableDeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused variable declaration in file scope\\")",macro\=>true,exceptions\=>("@(\#)","$Id")} +org.eclipse.cdt.codan.internal.checkers.UsingInHeaderProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.UsingInHeaderProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Using directive in header\\")"} +org.eclipse.cdt.codan.internal.checkers.VariableResolutionProblem=Error +org.eclipse.cdt.codan.internal.checkers.VariableResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Symbol is not resolved\\")"} +org.eclipse.cdt.codan.internal.checkers.VirtualMethodCallProblem=-Error +org.eclipse.cdt.codan.internal.checkers.VirtualMethodCallProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Virtual method call in constructor/destructor\\")"} +org.eclipse.cdt.qt.core.qtproblem=Warning +org.eclipse.cdt.qt.core.qtproblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>false,RUN_ON_INC_BUILD\=>false,RUN_ON_FILE_OPEN\=>true,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>null} diff --git a/Examples/MAX32657/Hello_World/.settings/org.eclipse.cdt.core.prefs b/Examples/MAX32657/Hello_World/.settings/org.eclipse.cdt.core.prefs new file mode 100644 index 00000000000..7634acd5b10 --- /dev/null +++ b/Examples/MAX32657/Hello_World/.settings/org.eclipse.cdt.core.prefs @@ -0,0 +1,15 @@ +eclipse.preferences.version=1 +environment/project/cdt.managedbuild.toolchain.gnu.cross.base.1028364529/BOARD/delimiter=; +environment/project/cdt.managedbuild.toolchain.gnu.cross.base.1028364529/BOARD/operation=append +environment/project/cdt.managedbuild.toolchain.gnu.cross.base.1028364529/BOARD/value=EvKit_V1 +environment/project/cdt.managedbuild.toolchain.gnu.cross.base.1028364529/GCC_PREFIX/delimiter=; +environment/project/cdt.managedbuild.toolchain.gnu.cross.base.1028364529/GCC_PREFIX/operation=replace +environment/project/cdt.managedbuild.toolchain.gnu.cross.base.1028364529/GCC_PREFIX/value=arm-none-eabi- +environment/project/cdt.managedbuild.toolchain.gnu.cross.base.1028364529/PROJECT/delimiter=; +environment/project/cdt.managedbuild.toolchain.gnu.cross.base.1028364529/PROJECT/operation=append +environment/project/cdt.managedbuild.toolchain.gnu.cross.base.1028364529/PROJECT/value=Hello_World +environment/project/cdt.managedbuild.toolchain.gnu.cross.base.1028364529/TARGET/delimiter=; +environment/project/cdt.managedbuild.toolchain.gnu.cross.base.1028364529/TARGET/operation=append +environment/project/cdt.managedbuild.toolchain.gnu.cross.base.1028364529/TARGET/value=MAX32657 +environment/project/cdt.managedbuild.toolchain.gnu.cross.base.1028364529/append=true +environment/project/cdt.managedbuild.toolchain.gnu.cross.base.1028364529/appendContributed=true diff --git a/Examples/MAX32657/Hello_World/.vscode/README.md b/Examples/MAX32657/Hello_World/.vscode/README.md new file mode 100755 index 00000000000..5b355bd51c9 --- /dev/null +++ b/Examples/MAX32657/Hello_World/.vscode/README.md @@ -0,0 +1,47 @@ +# VSCode-Maxim + +_(If you're viewing this document from within Visual Studio Code you can press `CTRL+SHIFT+V` to open a Markdown preview window.)_ + +## Quick Links + +* [MSDK User Guide](https://analogdevicesinc.github.io/msdk/USERGUIDE/) +* [VSCode-Maxim Github](https://github.com/analogdevicesinc/VSCode-Maxim) + +## Introduction + +VSCode-Maxim is a set of [Visual Studio Code](https://code.visualstudio.com/) project configurations and utilities for enabling embedded development for [Analog Device's MSDK](https://github.com/analogdevicesinc/msdk) and the [MAX32xxx/MAX78xxx microcontrollers](https://www.analog.com/en/product-category/microcontrollers.html). + +The following features are supported: + +* Code editing with intellisense down to the register level +* Code compilation with the ability to easily re-target a project for different microcontrollers and boards +* Flashing programs +* GUI and command-line debugging + +## Dependencies + +* [Visual Studio Code](https://code.visualstudio.com/) + * [C/C++ VSCode Extension](https://marketplace.visualstudio.com/items?itemName=ms-vscode.cpptools) + * [Cortex-Debug Extension](https://marketplace.visualstudio.com/items?itemName=marus25.cortex-debug) +* [Analog Devices MSDK](https://analogdevicesinc.github.io/msdk/) + +## Installation + +Install the MSDK, then set `"MAXIM_PATH"` in your _user_ VS Code settings. + +See [Getting Started with Visual Studio Code](https://analogdevicesinc.github.io/msdk/USERGUIDE/#getting-started-with-visual-studio-code) in the MSDK User Guide for detailed instructions. + +## Usage + +See the [MSDK User Guide](https://analogdevicesinc.github.io/msdk/USERGUIDE/#visual-studio-code) for detailed usage info. + +## Issue Tracker + +Bug reports, feature requests, and contributions are welcome via the [issues](https://github.com/analogdevicesinc/VSCode-Maxim/issues) tracker on Github. + +New issues should contain _at minimum_ the following information: + +* Visual Studio Code version #s (see `Help -> About`) +* C/C++ Extension version # +* Target microcontroller and evaluation platform +* The projects `.vscode` folder and `Makefile` (where applicable). Standard compression formats such as `.zip`, `.rar`, `.tar.gz`, etc. are all acceptable. diff --git a/Examples/MAX32657/Hello_World/.vscode/c_cpp_properties.json b/Examples/MAX32657/Hello_World/.vscode/c_cpp_properties.json new file mode 100755 index 00000000000..dfbed47b581 --- /dev/null +++ b/Examples/MAX32657/Hello_World/.vscode/c_cpp_properties.json @@ -0,0 +1,53 @@ +{ + "configurations": [ + { + "name": "Win32", + "includePath": [ + "${default}" + ], + "defines": [ + "${default}" + ], + "intelliSenseMode": "gcc-arm", + "compilerPath": "${config:ARM_GCC_path}/bin/arm-none-eabi-gcc.exe", + "browse": { + "path": [ + "${default}" + ] + } + }, + { + "name": "Linux", + "includePath": [ + "${default}" + ], + "defines": [ + "${default}" + ], + "intelliSenseMode": "gcc-arm", + "compilerPath": "${config:ARM_GCC_path}/bin/arm-none-eabi-gcc", + "browse": { + "path": [ + "${default}" + ] + } + }, + { + "name": "Mac", + "includePath": [ + "${default}" + ], + "defines": [ + "${default}" + ], + "intelliSenseMode": "gcc-arm", + "compilerPath": "${config:ARM_GCC_path}/bin/arm-none-eabi-gcc", + "browse": { + "path": [ + "${default}" + ] + } + } + ], + "version": 4 +} \ No newline at end of file diff --git a/Examples/MAX32657/Hello_World/.vscode/flash.gdb b/Examples/MAX32657/Hello_World/.vscode/flash.gdb new file mode 100755 index 00000000000..8f22801a47d --- /dev/null +++ b/Examples/MAX32657/Hello_World/.vscode/flash.gdb @@ -0,0 +1,17 @@ +define flash_m4 + set architecture armv7e-m + set remotetimeout 10 + target remote | openocd -c "gdb_port pipe;log_output flash.log" -s $arg0/scripts -f interface/$arg1 -f target/$arg2 -c "init; reset halt" + load + compare-sections + monitor reset halt +end + +define flash_m4_run + set architecture armv7e-m + set remotetimeout 10 + target remote | openocd -c "gdb_port pipe;log_output flash.log" -s $arg0/scripts -f interface/$arg1 -f target/$arg2 -c "init; reset halt" + load + compare-sections + monitor resume +end diff --git a/Examples/MAX32657/Hello_World/.vscode/launch.json b/Examples/MAX32657/Hello_World/.vscode/launch.json new file mode 100755 index 00000000000..01fe5199048 --- /dev/null +++ b/Examples/MAX32657/Hello_World/.vscode/launch.json @@ -0,0 +1,133 @@ +{ + "configurations": [ + { + "name": "Debug Arm (Cortex-debug)", + "cwd":"${workspaceRoot}", + "executable": "${workspaceFolder}/build/${config:program_file}", + "loadFiles": ["${workspaceFolder}/build/${config:program_file}"], + "symbolFiles": [{ + "file": "${workspaceFolder}/build/${config:symbol_file}" + }], + "request": "launch", + "type": "cortex-debug", + "servertype": "openocd", + "linux": { + "gdbPath": "${config:ARM_GCC_path}/bin/arm-none-eabi-gdb", + "serverpath": "${config:OCD_path}/openocd", + }, + "windows": { + "gdbPath": "${config:ARM_GCC_path}/bin/arm-none-eabi-gdb.exe", + "serverpath": "${config:OCD_path}/openocd.exe", + }, + "osx": { + "gdbPath": "${config:ARM_GCC_path}/bin/arm-none-eabi-gdb", + "serverpath": "${config:OCD_path}/openocd", + }, + "searchDir": ["${config:OCD_path}/scripts"], + "configFiles": ["interface/${config:M4_OCD_interface_file}", "target/${config:M4_OCD_target_file}"], + "interface": "swd", + "runToEntryPoint": "main", + "svdFile": "${config:MAXIM_PATH}/Libraries/CMSIS/Device/Maxim/${config:target}/Include/${config:target}.svd" + }, + { + "name": "GDB (Arm M4)", + "type": "cppdbg", + "request": "launch", + "program": "${workspaceFolder}/build/${config:program_file}", + "args": [], + "stopAtEntry": true, + "cwd": "${workspaceFolder}", + "environment": [], + "externalConsole": false, + "MIMode": "gdb", + "linux": { + "miDebuggerPath": "${config:ARM_GCC_path}/bin/arm-none-eabi-gdb", + "debugServerPath": "${config:OCD_path}/openocd", + }, + "windows": { + "miDebuggerPath": "${config:ARM_GCC_path}/bin/arm-none-eabi-gdb.exe", + "debugServerPath": "${config:OCD_path}/openocd.exe", + }, + "osx": { + "miDebuggerPath": "${config:ARM_GCC_path}/bin/arm-none-eabi-gdb", + "debugServerPath": "${config:OCD_path}/bin/openocd", + }, + "logging": { + "exceptions": true, + "trace": false, + "traceResponse": false, + "engineLogging": false + }, + "miDebuggerServerAddress": "localhost:3333", + "debugServerArgs": "-s ${config:OCD_path}/scripts -f interface/${config:M4_OCD_interface_file} -f target/${config:M4_OCD_target_file} -c \"init; reset halt\"", + "serverStarted": "Info : Listening on port 3333 for gdb connections", + "filterStderr": true, + "targetArchitecture": "arm", + "customLaunchSetupCommands": [ + {"text":"-list-features"} + ], + "setupCommands": [ + { "text":"set logging overwrite on"}, + { "text":"set logging file debug-arm.log"}, + { "text":"set logging on"}, + { "text":"cd ${workspaceFolder}" }, + { "text":"exec-file build/${config:program_file}" }, + { "text":"symbol-file build/${config:symbol_file}" }, + { "text":"target remote localhost:3333" }, + { "text":"monitor reset halt" }, + { "text":"set $pc=Reset_Handler"}, + { "text":"b main" } + ] + }, + { + "name": "GDB (RISC-V)", + "type": "cppdbg", + "request": "launch", + "program": "${workspaceFolder}/buildrv/${config:program_file}", + "args": [], + "stopAtEntry": false, + "cwd": "${workspaceFolder}", + "environment": [], + "externalConsole": false, + "MIMode": "gdb", + "linux": { + "miDebuggerPath": "${config:xPack_GCC_path}/bin/riscv-none-elf-gdb", + "debugServerPath": "${config:OCD_path}/openocd", + }, + "windows": { + "miDebuggerPath": "${config:xPack_GCC_path}/bin/riscv-none-elf-gdb.exe", + "debugServerPath": "${config:OCD_path}/openocd.exe", + }, + "osx": { + "miDebuggerPath": "${config:xPack_GCC_path}/bin/riscv-none-elf-gdb", + "debugServerPath": "${config:OCD_path}/bin/openocd", + }, + "logging": { + "exceptions": true, + "trace": false, + "traceResponse": false, + "engineLogging": false + }, + "miDebuggerServerAddress": "localhost:3334", + "debugServerArgs": "-c \"gdb_port 3334\" -s ${config:OCD_path}/scripts -f interface/${config:RV_OCD_interface_file} -f target/${config:RV_OCD_target_file}", + "serverStarted": "Info : Listening on port 3334 for gdb connections", + "filterStderr": true, + "customLaunchSetupCommands": [ + {"text":"-list-features"} + ], + "targetArchitecture": "arm", + "setupCommands": [ + { "text":"set logging overwrite on"}, + { "text":"set logging file debug-riscv.log"}, + { "text":"set logging on"}, + { "text":"cd ${workspaceFolder}" }, + { "text": "set architecture riscv:rv32", "ignoreFailures": false }, + { "text":"exec-file build/${config:program_file}", "ignoreFailures": false }, + { "text":"symbol-file buildrv/${config:symbol_file}", "ignoreFailures": false }, + { "text":"target remote localhost:3334" }, + { "text":"b main" }, + { "text": "set $pc=Reset_Handler","ignoreFailures": false } + ] + } + ] +} diff --git a/Examples/MAX32657/Hello_World/.vscode/settings.json b/Examples/MAX32657/Hello_World/.vscode/settings.json new file mode 100755 index 00000000000..66194c6a77c --- /dev/null +++ b/Examples/MAX32657/Hello_World/.vscode/settings.json @@ -0,0 +1,80 @@ +{ + "terminal.integrated.env.windows": { + "Path":"${config:OCD_path};${config:ARM_GCC_path}/bin;${config:xPack_GCC_path}/bin;${config:MSYS_path}/usr/bin;${config:Make_path};${env:PATH}", + "MAXIM_PATH":"${config:MAXIM_PATH}" + }, + "terminal.integrated.defaultProfile.windows": "Command Prompt", + + "terminal.integrated.env.linux": { + "PATH":"${config:OCD_path}:${config:ARM_GCC_path}/bin:${config:xPack_GCC_path}/bin:${config:Make_path}:${env:PATH}", + "MAXIM_PATH":"${config:MAXIM_PATH}" + }, + "terminal.integrated.env.osx": { + "PATH":"${config:OCD_path}/bin:${config:ARM_GCC_path}/bin:${config:xPack_GCC_path}/bin:${config:Make_path}:${env:PATH}", + "MAXIM_PATH":"${config:MAXIM_PATH}" + }, + + "target":"MAX32657", + "board":"EvKit_V1", + + "project_name":"${workspaceFolderBasename}", + + "program_file":"${config:project_name}.elf", + "symbol_file":"${config:program_file}", + + "M4_OCD_interface_file":"cmsis-dap.cfg", + "M4_OCD_target_file":"max32657.cfg", + "RV_OCD_interface_file":"ftdi/olimex-arm-usb-ocd-h.cfg", + "RV_OCD_target_file":"${config:target}_riscv.cfg", + + "v_Arm_GCC":"10.3", + "v_xPack_GCC":"12.2.0-3.1", + + "OCD_path":"${config:MAXIM_PATH}/Tools/OpenOCD", + "ARM_GCC_path":"${config:MAXIM_PATH}/Tools/GNUTools/${config:v_Arm_GCC}", + "xPack_GCC_path":"${config:MAXIM_PATH}/Tools/xPack/riscv-none-elf-gcc/${config:v_xPack_GCC}", + "Make_path":"${config:MAXIM_PATH}/Tools/GNUTools/Make", + "MSYS_path":"${config:MAXIM_PATH}/Tools/MSYS2", + + "C_Cpp.default.includePath": [ + "${workspaceFolder}", + "${workspaceFolder}/**", + "${config:MAXIM_PATH}/Libraries/Boards/${config:target}/Include", + "${config:MAXIM_PATH}/Libraries/Boards/${config:target}/${config:board}/Include", + "${config:MAXIM_PATH}/Libraries/CMSIS/Device/Maxim/${config:target}/Include", + "${config:MAXIM_PATH}/Libraries/CMSIS/5.9.0/Core/Include", + "${config:MAXIM_PATH}/Libraries/CMSIS/Include", + "${config:ARM_GCC_path}/arm-none-eabi/include", + "${config:ARM_GCC_path}/lib/gcc/arm-none-eabi/${config:v_Arm_GCC}/include", + "${config:MAXIM_PATH}/Libraries/PeriphDrivers/Include/${config:target}", + "${config:MAXIM_PATH}/Libraries/MiscDrivers/Camera", + "${config:MAXIM_PATH}/Libraries/MiscDrivers/Display", + "${config:MAXIM_PATH}/Libraries/MiscDrivers/Display/fonts", + "${config:MAXIM_PATH}/Libraries/MiscDrivers/ExtMemory", + "${config:MAXIM_PATH}/Libraries/MiscDrivers/LED", + "${config:MAXIM_PATH}/Libraries/MiscDrivers/PMIC", + "${config:MAXIM_PATH}/Libraries/MiscDrivers/PushButton", + "${config:MAXIM_PATH}/Libraries/MiscDrivers/Touchscreen" + ], + "C_Cpp.default.browse.path": [ + "${workspaceFolder}", + "${config:MAXIM_PATH}/Libraries/Boards/${config:target}/Source", + "${config:MAXIM_PATH}/Libraries/Boards/${config:target}/${config:board}/Source", + "${config:MAXIM_PATH}/Libraries/PeriphDrivers/Source", + "${config:MAXIM_PATH}/Libraries/MiscDrivers/Camera", + "${config:MAXIM_PATH}/Libraries/MiscDrivers/Display", + "${config:MAXIM_PATH}/Libraries/MiscDrivers/Display/fonts", + "${config:MAXIM_PATH}/Libraries/MiscDrivers/LED", + "${config:MAXIM_PATH}/Libraries/MiscDrivers/PMIC", + "${config:MAXIM_PATH}/Libraries/MiscDrivers/PushButton", + "${config:MAXIM_PATH}/Libraries/MiscDrivers/Touchscreen", + "${config:MAXIM_PATH}/Libraries/MiscDrivers" + ], + "C_Cpp.default.defines": [ + + ], + "C_Cpp.default.forcedInclude": [ + "${workspaceFolder}/build/project_defines.h" + ] +} + diff --git a/Examples/MAX32657/Hello_World/.vscode/tasks.json b/Examples/MAX32657/Hello_World/.vscode/tasks.json new file mode 100755 index 00000000000..e95445e2b3e --- /dev/null +++ b/Examples/MAX32657/Hello_World/.vscode/tasks.json @@ -0,0 +1,115 @@ +{ + "version": "2.0.0", + "tasks": [ + { + "label": "build", + "type": "shell", + "command": "make -r -j 8 --output-sync=target --no-print-directory TARGET=${config:target} BOARD=${config:board} MAXIM_PATH=${config:MAXIM_PATH} MAKE=make PROJECT=${config:project_name}", + "osx":{ + "command": "source ~/.zshrc && make -r -j 8 --output-sync=target --no-print-directory TARGET=${config:target} BOARD=${config:board} MAXIM_PATH=${config:MAXIM_PATH} MAKE=make PROJECT=${config:project_name}" + }, + "group": "build", + "problemMatcher": [] + }, + { + "label": "clean", + "type": "shell", + "command": "make -j 8 clean --output-sync=target --no-print-directory TARGET=${config:target} BOARD=${config:board} MAXIM_PATH=${config:MAXIM_PATH} MAKE=make PROJECT=${config:project_name}", + "osx":{ + "command": "source ~/.zshrc && make -j 8 clean --output-sync=target --no-print-directory TARGET=${config:target} BOARD=${config:board} MAXIM_PATH=${config:MAXIM_PATH} MAKE=make PROJECT=${config:project_name}" + }, + "group": "build", + "problemMatcher": [] + }, + { + "label": "clean-periph", + "type": "shell", + "command": "make -j 8 distclean --output-sync=target --no-print-directory TARGET=${config:target} BOARD=${config:board} MAXIM_PATH=${config:MAXIM_PATH} MAKE=make PROJECT=${config:project_name}", + "osx":{ + "command": "source ~/.zshrc && make -j 8 distclean --output-sync=target --no-print-directory TARGET=${config:target} BOARD=${config:board} MAXIM_PATH=${config:MAXIM_PATH} MAKE=make PROJECT=${config:project_name}" + }, + "group": "build", + "problemMatcher": [] + }, + { + "label": "flash", + "type": "shell", + "command": "arm-none-eabi-gdb", + "args": [ + "--cd=\"${workspaceFolder}\"", + "--se=\"build/${config:program_file}\"", + "--symbols=build/${config:symbol_file}", + "-x=\"${workspaceFolder}/.vscode/flash.gdb\"", + "--ex=\"flash_m4 ${config:OCD_path} ${config:M4_OCD_interface_file} ${config:M4_OCD_target_file}\"", + "--batch" + ], + "group": "build", + "problemMatcher": [], + "dependsOn":["build"] + }, + { + "label": "flash & run", + "type": "shell", + "command": "arm-none-eabi-gdb", + "args": [ + "--cd=\"${workspaceFolder}\"", + "--se=\"build/${config:program_file}\"", + "--symbols=build/${config:symbol_file}", + "-x=\"${workspaceFolder}/.vscode/flash.gdb\"", + "--ex=\"flash_m4_run ${config:OCD_path} ${config:M4_OCD_interface_file} ${config:M4_OCD_target_file}\"", + "--batch" + ], + "group": "build", + "problemMatcher": [], + "dependsOn":["build"] + }, + { + "label": "erase flash", + "type": "shell", + "command": "openocd", + "args": [ + "-s", "${config:OCD_path}/scripts", + "-f", "interface/${config:M4_OCD_interface_file}", + "-f", "target/${config:M4_OCD_target_file}", + "-c", "\"init; reset halt; max32xxx mass_erase 0;\"", + "-c", "exit" + ], + "group":"build", + "problemMatcher": [], + "dependsOn":[] + }, + { + "label": "openocd (m4)", + "type": "shell", + "command": "openocd", + "args": [ + "-s", + "${config:OCD_path}/scripts", + "-f", + "interface/${config:M4_OCD_interface_file}", + "-f", + "target/${config:M4_OCD_target_file}", + "-c", + "\"init; reset halt\"" + ], + "problemMatcher": [], + "dependsOn":[] + }, + { + "label": "gdb (m4)", + "type": "shell", + "command": "arm-none-eabi-gdb", + "args": [ + "--ex=\"cd ${workspaceFolder}\"", + "--se=\"build/${config:program_file}\"", + "--symbols=build/${config:symbol_file}", + "--ex=\"target remote localhost:3333\"", + "--ex=\"monitor reset halt\"", + "--ex=\"b main\"", + "--ex=\"c\"" + ], + "problemMatcher": [], + "dependsOn":[] + }, + ] +} \ No newline at end of file diff --git a/Examples/MAX32657/Hello_World/Hello_World.launch b/Examples/MAX32657/Hello_World/Hello_World.launch new file mode 100644 index 00000000000..208feecdd1f --- /dev/null +++ b/Examples/MAX32657/Hello_World/Hello_World.launch @@ -0,0 +1,62 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Examples/MAX32657/Hello_World/Makefile b/Examples/MAX32657/Hello_World/Makefile new file mode 100644 index 00000000000..6c2b40a794a --- /dev/null +++ b/Examples/MAX32657/Hello_World/Makefile @@ -0,0 +1,382 @@ +############################################################################### + # + # Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + # Analog Devices, Inc.), + # Copyright (C) 2023-2024 Analog Devices, Inc. + # + # Licensed under the Apache License, Version 2.0 (the "License"); + # you may not use this file except in compliance with the License. + # You may obtain a copy of the License at + # + # http://www.apache.org/licenses/LICENSE-2.0 + # + # Unless required by applicable law or agreed to in writing, software + # distributed under the License is distributed on an "AS IS" BASIS, + # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + # See the License for the specific language governing permissions and + # limitations under the License. + # + ############################################################################## + +# ** Readme! ** +# Don't edit this file! This is the core Makefile for a MaximSDK +# project. The available configuration options can be overridden +# in "project.mk", on the command-line, or with system environment +# variables. + +# See https://analogdevicesinc.github.io/msdk/USERGUIDE/#build-system +# for more detailed instructions on how to use this system. + +# The detailed instructions mentioned above are easier to read than +# this file, but the comments found in this file also outline the +# available configuration variables. This file is organized into +# sub-sections, some of which expose config variables. + + +# ******************************************************************************* +# Set the target microcontroller and board to compile for. + +# Every TARGET microcontroller has some Board Support Packages (BSPs) that are +# available for it under the MaximSDK/Libraries/Boards/TARGET folder. The BSP +# that gets selected is MaximSDK/Libraries/Boards/TARGET/BOARD. + +# Configuration Variables: +# - TARGET : Override the default target microcontroller. Ex: TARGET=MAX78000 +# - BOARD : Override the default BSP (case sensitive). Ex: BOARD=EvKit_V1, BOARD=FTHR_RevA + + +ifeq "$(TARGET)" "" +# Default target microcontroller +TARGET := MAX32657 +TARGET_UC := MAX32657 +TARGET_LC := max32657 +else +# "TARGET" has been overridden in the environment or on the command-line. +# We need to calculate an upper and lowercase version of the part number, +# because paths on Linux and MacOS are case-sensitive. +TARGET_UC := $(subst m,M,$(subst a,A,$(subst x,X,$(TARGET)))) +TARGET_LC := $(subst M,m,$(subst A,a,$(subst X,x,$(TARGET)))) +endif + +# Default board. +BOARD ?= EvKit_V1 + +# ******************************************************************************* +# Locate the MaximSDK + +# This Makefile needs to know where to find the MaximSDK, and the MAXIM_PATH variable +# should point to the root directory of the MaximSDK installation. Setting this manually +# is usually only required if you're working on the command-line. + +# If MAXIM_PATH is not specified, we assume the project still lives inside of the MaximSDK +# and move up from this project's original location. + +# Configuration Variables: +# - MAXIM_PATH : Tell this Makefile where to find the MaximSDK. Ex: MAXIM_PATH=C:/MaximSDK + + +ifneq "$(MAXIM_PATH)" "" +# Sanitize MAXIM_PATH for backslashes +MAXIM_PATH := $(subst \,/,$(MAXIM_PATH)) +# Locate some other useful paths... +LIBS_DIR := $(abspath $(MAXIM_PATH)/Libraries) +CMSIS_ROOT := $(LIBS_DIR)/CMSIS +endif + +# ******************************************************************************* +# Include project Makefile. We do this after formulating TARGET, BOARD, and MAXIM_PATH +# in case project.mk needs to reference those values. However, we also include +# this as early as possible in the Makefile so that it can append to or override +# the variables below. + + +PROJECTMK ?= $(abspath ./project.mk) +include $(PROJECTMK) +$(info Loaded project.mk) +# PROJECTMK is also used by implicit rules and other libraries to add project.mk as a watch file + +# ******************************************************************************* +# Final path sanitization and re-calculation. No options here. + +ifeq "$(MAXIM_PATH)" "" +# MAXIM_PATH is still not defined... +DEPTH := ../../../ +MAXIM_PATH := $(abspath $(DEPTH)) +$(warning Warning: MAXIM_PATH is not set! Set MAXIM_PATH in your environment or in project.mk to clear this warning.) +$(warning Warning: Attempting to use $(MAXIM_PATH) calculated from relative path) +else +# Sanitize MAXIM_PATH for backslashes +MAXIM_PATH := $(subst \,/,$(MAXIM_PATH)) +endif + +# Final recalculation of LIBS_DIR/CMSIS_ROOT +LIBS_DIR := $(abspath $(MAXIM_PATH)/Libraries) +CMSIS_ROOT := $(LIBS_DIR)/CMSIS + +# One final UC/LC check in case user set TARGET in project.mk +TARGET_UC := $(subst m,M,$(subst a,A,$(subst x,X,$(TARGET)))) +TARGET_LC := $(subst M,m,$(subst A,a,$(subst X,x,$(TARGET)))) + +export TARGET +export TARGET_UC +export TARGET_LC +export CMSIS_ROOT +# TODO: Remove dependency on exports for these variables. + +# ******************************************************************************* +# Set up search paths, and auto-detect all source code on those paths. + +# The following paths are searched by default, where "./" is the project directory. +# ./ +# |- *.h +# |- *.c +# |-include (optional) +# |- *.h +# |-src (optional) +# |- *.c + +# Configuration Variables: +# - VPATH : Tell this Makefile to search additional locations for source (.c) files. +# You should use the "+=" operator with this option. +# Ex: VPATH += your/new/path +# - IPATH : Tell this Makefile to search additional locations for header (.h) files. +# You should use the "+=" operator with this option. +# Ex: VPATH += your/new/path +# - SRCS : Tell this Makefile to explicitly add a source (.c) file to the build. +# This is really only useful if you want to add a source file that isn't +# on any VPATH, in which case you can add the full path to the file here. +# You should use the "+=" operator with this option. +# Ex: SRCS += your/specific/source/file.c +# - AUTOSEARCH : Set whether this Makefile should automatically detect .c files on +# VPATH and add them to the build. This is enabled by default. Set +# to 0 to disable. If autosearch is disabled, source files must be +# manually added to SRCS. +# Ex: AUTOSEARCH = 0 + + +# Where to find source files for this project. +VPATH += . +VPATH += src +VPATH := $(VPATH) + +# Where to find header files for this project +IPATH += . +IPATH += include +IPATH := $(IPATH) + +AUTOSEARCH ?= 1 +ifeq ($(AUTOSEARCH), 1) +# Auto-detect all C/C++ source files on VPATH +SRCS += $(wildcard $(addsuffix /*.c, $(VPATH))) +SRCS += $(wildcard $(addsuffix /*.cpp, $(VPATH))) +endif + +# Collapse SRCS before passing them on to the next stage +SRCS := $(SRCS) + +# ******************************************************************************* +# Set the output filename + +# Configuration Variables: +# - PROJECT : Override the default output filename. Ex: PROJECT=MyProject + + +# The default value creates a file named after the target micro. Ex: MAX78000.elf +PROJECT ?= $(TARGET_LC) + +# ******************************************************************************* +# Compiler options + +# Configuration Variables: +# - DEBUG : Set DEBUG=1 to build explicitly for debugging. This adds some additional +# symbols and sets -Og as the default optimization level. +# - MXC_OPTIMIZE_CFLAGS : Override the default compiler optimization level. +# Ex: MXC_OPTIMIZE_CFLAGS = -O2 +# - PROJ_CFLAGS : Add additional compiler flags to the build. +# You should use the "+=" operator with this option. +# Ex: PROJ_CFLAGS += -Wextra +# - MFLOAT_ABI : Set the floating point acceleration level. +# The only options are "hard", "soft", or "softfp". +# Ex: MFLOAT_ABI = hard +# - LINKERFILE : Override the default linkerfile. +# Ex: LINKERFILE = customlinkerfile.ld +# - LINKERPATH : Override the default search location for $(LINKERFILE) +# The default search location is $(CMSIS_ROOT)/Device/Maxim/$(TARGET_UC)/Source/GCC +# If $(LINKERFILE) cannot be found at this path, then the root project +# directory will be used as a fallback. + +# Select 'GCC' or 'IAR' compiler +ifeq "$(COMPILER)" "" +COMPILER := GCC +endif + +# Set default compiler optimization levels +ifeq "$(MAKECMDGOALS)" "release" +# Default optimization level for "release" builds (make release) +MXC_OPTIMIZE_CFLAGS ?= -O2 +DEBUG = 0 +endif + +ifeq ($(DEBUG),1) +# Optimizes for debugging as recommended +# by GNU for code-edit-debug cycles +# https://gcc.gnu.org/onlinedocs/gcc/Optimize-Options.html#Optimize-Options +MXC_OPTIMIZE_CFLAGS := -Og +endif + +# Default level if not building for release or explicitly for debug +MXC_OPTIMIZE_CFLAGS ?= -Og + +# Set compiler flags +PROJ_CFLAGS += -Wall # Enable warnings +PROJ_CFLAGS += -DMXC_ASSERT_ENABLE + +# Set hardware floating point acceleration. +# Options are: +# - hard +# - soft +# - softfp (default if MFLOAT_ABI is not set) +MFLOAT_ABI ?= softfp +# MFLOAT_ABI must be exported to other Makefiles +export MFLOAT_ABI + +# This path contains system-level intialization files for the target micro. Add to the build. +VPATH += $(CMSIS_ROOT)/Device/Maxim/$(TARGET_UC)/Source + +# ******************************************************************************* +# Secure Boot Tools (SBT) + +# This section integrates the Secure Boot Tools. It's intended for use with +# microcontrollers that have a secure bootloader. + +# Enabling SBT integration will add some special rules, such as "make sla", "make scpa", etc. + +# Configuration variables: +# SBT : Toggle SBT integration. Set to 1 to enable, or 0 +# to disable +# MAXIM_SBT_DIR : Specify the location of the SBT tool binaries. This defaults to +# Tools/SBT in the MaximSDK. The standalone SBT installer will override +# this via an environment variable. +# TARGET_SEC : Specify the part number to be passed into the SBT. This should match +# the secure variant part #. The default value will depend on TARGET. +# For example, TARGET=MAX32650 will result in TARGET_SEC=MAX32651, and +# the default selection happens in Tools/SBT/SBT-config. +# However, if there are multiple secure part #s for the target +# microcontroller this variable may need to be changed. + +SBT ?= 0 +ifeq ($(SBT), 1) +MAXIM_SBT_DIR ?= $(MAXIM_PATH)/Tools/SBT +MAXIM_SBT_DIR := $(subst \,/,$(MAXIM_SBT_DIR)) +# ^ Must sanitize path for \ on Windows, since this may come from an environment +# variable. + +export MAXIM_SBT_DIR # SBTs must have this environment variable defined to work + +# SBT-config.mk and SBT-rules.mk are included further down this Makefile. + +endif # SBT + +# ******************************************************************************* +# Default goal selection. This section allows you to override the default goal +# that will run if no targets are specified on the command-line. +# (ie. just running 'make' instead of 'make all') + +# Configuration variables: +# .DEFAULT_GOAL : Set the default goal if no targets were specified on the +# command-line +# ** "override" must be used with this variable. ** +# Ex: "override .DEFAULT_GOAL = mygoal" + +ifeq "$(.DEFAULT_GOAL)" "" +ifeq ($(SBT),1) +override .DEFAULT_GOAL := sla +else +override .DEFAULT_GOAL := all +endif +endif + +# Developer note: 'override' is used above for legacy Makefile compatibility. +# gcc.mk/gcc_riscv.mk need to hard-set 'all' internally, so this new system +# uses 'override' to come in over the top without breaking old projects. + +# It's also necessary to explicitly set MAKECMDGOALS... +ifeq "$(MAKECMDGOALS)" "" +MAKECMDGOALS:=$(.DEFAULT_GOAL) +endif + +# Enable colors when --sync-output is used. +# See https://www.gnu.org/software/make/manual/make.html#Terminal-Output (section 13.2) +ifneq ($(MAKE_TERMOUT),) +PROJ_CFLAGS += -fdiagnostics-color=always +endif + +ifneq ($(FORCE_COLOR),) +PROJ_CFLAGS += -fdiagnostics-color=always +endif + +# ******************************************************************************* +# Include SBT config. We need to do this here because it needs to know +# the current MAKECMDGOAL. +ifeq ($(SBT),1) +include $(MAXIM_PATH)/Tools/SBT/SBT-config.mk +endif + +# ******************************************************************************* +# Libraries + +# This section offers "toggle switches" to include or exclude the libraries that +# are available in the MaximSDK. Set a configuration variable to 1 to include the +# library in the build, or 0 to exclude. + +# Each library may also have its own library specific configuration variables. See +# Libraries/libs.mk for more details. + +# Configuration variables: +# - LIB_BOARD : Include the Board-Support Package (BSP) library. (Enabled by default) +# - LIB_PERIPHDRIVERS : Include the peripheral driver library. (Enabled by default) +# - LIB_CMSIS_DSP : Include the CMSIS-DSP library. +# - LIB_CORDIO : Include the Cordio BLE library +# - LIB_FCL : Include the Free Cryptographic Library (FCL) +# - LIB_FREERTOS : Include the FreeRTOS and FreeRTOS-Plus-CLI libraries +# - LIB_LC3 : Include the Low Complexity Communication Codec (LC3) library +# - LIB_LITTLEFS : Include the "little file system" (littleFS) library +# - LIB_LWIP : Include the lwIP library +# - LIB_MAXUSB : Include the MAXUSB library +# - LIB_SDHC : Include the SDHC library + +include $(LIBS_DIR)/libs.mk + + +# ******************************************************************************* +# Rules + +# Include the rules for building for this target. All other makefiles should be +# included before this one. +include $(CMSIS_ROOT)/Device/Maxim/$(TARGET_UC)/Source/$(COMPILER)/$(TARGET_LC).mk + +# Include the rules that integrate the SBTs. SBTs are a special case that must be +# include after the core gcc rules to extend them. +ifeq ($(SBT), 1) +include $(MAXIM_PATH)/Tools/SBT/SBT-rules.mk +endif + + +# Get .DEFAULT_GOAL working. +ifeq "$(MAKECMDGOALS)" "" +MAKECMDGOALS:=$(.DEFAULT_GOAL) +endif + + +all: +# Extend the functionality of the "all" recipe here + arm-none-eabi-size --format=berkeley $(BUILD_DIR)/$(PROJECT).elf + +libclean: + $(MAKE) -f ${PERIPH_DRIVER_DIR}/periphdriver.mk clean.periph + +clean: +# Extend the functionality of the "clean" recipe here + +# The rule to clean out all the build products. +distclean: clean libclean diff --git a/Examples/MAX32657/Hello_World/README.md b/Examples/MAX32657/Hello_World/README.md new file mode 100644 index 00000000000..c64b76a6473 --- /dev/null +++ b/Examples/MAX32657/Hello_World/README.md @@ -0,0 +1,32 @@ +## Description + +A basic getting started program. + +This version of Hello_World prints an incrementing count to the console UART and toggles a LED0 every 500 ms. + + +## Software + +### Project Usage + +Universal instructions on building, flashing, and debugging this project can be found in the **[MSDK User Guide](https://analogdevicesinc.github.io/msdk/USERGUIDE/)**. + +### Project-Specific Build Notes + +* This project comes pre-configured for the MAX32657EVKIT. See [Board Support Packages](https://analogdevicesinc.github.io/msdk/USERGUIDE/#board-support-packages) in the MSDK User Guide for instructions on changing the target board. + +## Required Connections + +## Expected Output + +The Console UART of the device will output these messages: + +``` +Hello World! +count : 0 +count : 1 +count : 2 +count : 3 +``` + +You will also observe LED0 blinking at a rate of 2Hz. diff --git a/Examples/MAX32657/Hello_World/main.c b/Examples/MAX32657/Hello_World/main.c new file mode 100644 index 00000000000..5a4ce99ba9d --- /dev/null +++ b/Examples/MAX32657/Hello_World/main.c @@ -0,0 +1,56 @@ +/****************************************************************************** + * + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +/** + * @file main.c + * @brief Hello World! + * @details This example uses the UART to print to a terminal and flashes an LED. + */ + +/***** Includes *****/ +#include +#include +#include "mxc_device.h" +#include "led.h" +#include "pb.h" +#include "board.h" +#include "mxc_delay.h" + +/***** Definitions *****/ + +/***** Globals *****/ + +/***** Functions *****/ + +// ***************************************************************************** +int main(void) +{ + int count = 0; + + printf("Hello World!\n"); + + while (1) { + LED_On(LED_RED); + MXC_Delay(500000); + LED_Off(LED_RED); + MXC_Delay(500000); + printf("count = %d\n", count++); + } +} diff --git a/Examples/MAX32657/Hello_World/project.mk b/Examples/MAX32657/Hello_World/project.mk new file mode 100644 index 00000000000..c5bb8a2183b --- /dev/null +++ b/Examples/MAX32657/Hello_World/project.mk @@ -0,0 +1,10 @@ +# This file can be used to set build configuration +# variables. These variables are defined in a file called +# "Makefile" that is located next to this one. + +# For instructions on how to use this system, see +# https://analogdevicesinc.github.io/msdk/USERGUIDE/#build-system + +# ********************************************************** + +# Add your config here! diff --git a/Libraries/Boards/MAX32657/EvKit_V1/Source/board.c b/Libraries/Boards/MAX32657/EvKit_V1/Source/board.c index 4d02252ff00..f0bdcddf5e0 100644 --- a/Libraries/Boards/MAX32657/EvKit_V1/Source/board.c +++ b/Libraries/Boards/MAX32657/EvKit_V1/Source/board.c @@ -92,7 +92,7 @@ int Console_Init(void) { int err; - if ((err = MXC_UART_Init(ConsoleUart, CONSOLE_BAUD, MXC_UART_APB_CLK)) != E_NO_ERROR) { + if ((err = MXC_UART_Init(ConsoleUart, CONSOLE_BAUD)) != E_NO_ERROR) { return err; } diff --git a/Libraries/CMSIS/Device/Maxim/GCC/gcc.mk b/Libraries/CMSIS/Device/Maxim/GCC/gcc.mk index d16eae97c2c..873d657f568 100644 --- a/Libraries/CMSIS/Device/Maxim/GCC/gcc.mk +++ b/Libraries/CMSIS/Device/Maxim/GCC/gcc.mk @@ -255,6 +255,37 @@ endif # - cortex-m33 MCPU ?= cortex-m4 +ifeq "$(MCPU)" "cortex-m33" +# Security mode for the target processor. +# Acceptable values are +# - SECURE +# - NONSECURE +# +# When "SECURE" is selected, the build system will link the program binary into the secure +# memory sections and map peripheral instances onto their corresponding secure +# address aliases. "MSECURITY_MODE_SECURE" will be defined at compile time. +# +# When "NONSCURE" is selected, the program binary will be linked into the non-secure memory +# sections and peripherals will be mapped onto the non-secure address aliases. +# It should be noted that the M33 will boot into secure mode by default, which has access to +# both the secure and non-secure addresses and aliases. "MSECURITY_MODE_NONSECURE" will be defined +# at compile time. +MSECURITY_MODE ?= SECURE + +ifeq "$(MSECURITY_MODE)" "SECURE" +# Tell the compiler we are building a secure project. This is required to satisfy the requirements +# defined in "Armv8-M Security Extension: Requirements on Developments Tools" +# https://developer.arm.com/documentation/ecm0359818/latest +PROJ_CFLAGS += -mcmse + +PROJ_AFLAGS += -DIS_SECURE_ENVRIONMENT + +# Tell the linker we are building a secure project. This defines the "SECURE_LINK" symbol which the +# linker uses to set the secure FLASH/SRAM memory address ranges. +PROJ_LDFLAGS += -Xlinker --defsym=SECURE_LINK=1 +endif +endif + # Float ABI options: # See https://gcc.gnu.org/onlinedocs/gcc/ARM-Options.html (-mfloat-abi) # Specifies which floating-point ABI to use. Permissible values are: ‘soft’, ‘softfp’ and ‘hard’. diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h index 396c9128ffb..24a89242cdd 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h @@ -31,6 +31,7 @@ #define MXC_NUMCORES 1 #include +#include "system_max32657.h" #ifndef FALSE #define FALSE (0) @@ -95,10 +96,10 @@ typedef enum { DMA0_CH1_IRQn, /* 0x21 0x0084 33: DMA0 Channel 1 */ DMA0_CH2_IRQn, /* 0x22 0x0088 34: DMA0 Channel 2 */ DMA0_CH3_IRQn, /* 0x23 0x008C 35: DMA0 Channel 3 */ - DMA1_CH0_IRQn, /* 0x24 0x0090 36: DMA1 Channel 0 */ - DMA1_CH1_IRQn, /* 0x25 0x0094 37: DMA1 Channel 1 */ - DMA1_CH2_IRQn, /* 0x26 0x0098 38: DMA1 CHannel 2 */ - DMA1_CH3_IRQn, /* 0x27 0x009C 39: DMA1 Channel 3 */ + DMA1_CH0_IRQn, /* 0x24 0x0090 36: DMA1 Channel 0 (Secure) */ + DMA1_CH1_IRQn, /* 0x25 0x0094 37: DMA1 Channel 1 (Secure) */ + DMA1_CH2_IRQn, /* 0x26 0x0098 38: DMA1 CHannel 2 (Secure) */ + DMA1_CH3_IRQn, /* 0x27 0x009C 39: DMA1 Channel 3 (Secure) */ WUT0_IRQn, /* 0x28 0x00A0 40: Wakeup Timer 0 */ WUT1_IRQn, /* 0x29 0x00A4 41: Wakeup TImer 1 */ GPIOWAKE_IRQn, /* 0x2A 0x00A8 42: GPIO Wakeup */ @@ -149,6 +150,10 @@ typedef enum { #define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ #define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ +#include +#include +#define IS_SECURE_ENVIRONMENT (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)) + /* ================================================================================ */ /* ================== Device Specific Memory Section ================== */ /* ================================================================================ */ @@ -167,19 +172,28 @@ typedef enum { #define MXC_FLASH_S_MEM_BASE 0x11000000UL #define MXC_FLASH_S_PAGE_SIZE 0x00002000UL #define MXC_FLASH_S_MEM_SIZE 0x00100000UL +/* Flash info is always in secure region */ #define MXC_INFO_S_MEM_BASE 0x12000000UL #define MXC_INFO_S_MEM_SIZE 0x00004000UL #define MXC_SRAM_S_MEM_BASE 0x30000000UL #define MXC_SRAM_S_MEM_SIZE 0x00040000UL -/* Secure Region name redefinitions for explicit use */ +#define MXC_INFO_MEM_BASE MXC_INFO_S_MEM_BASE +#define MXC_INFO_MEM_SIZE MXC_INFO_S_MEM_SIZE + +#if IS_SECURE_ENVIRONMENT #define MXC_FLASH_MEM_BASE MXC_FLASH_S_MEM_BASE #define MXC_FLASH_PAGE_SIZE MXC_FLASH_S_PAGE_SIZE #define MXC_FLASH_MEM_SIZE MXC_FLASH_S_MEM_SIZE -#define MXC_INFO_MEM_BASE MXC_INFO_S_MEM_BASE -#define MXC_INFO_MEM_SIZE MXC_INFO_S_MEM_SIZE #define MXC_SRAM_MEM_BASE MXC_SRAM_S_MEM_BASE #define MXC_SRAM_MEM_SIZE MXC_SRAM_S_MEM_SIZE +#else +#define MXC_FLASH_MEM_BASE MXC_FLASH_NS_MEM_BASE +#define MXC_FLASH_PAGE_SIZE MXC_FLASH_NS_PAGE_SIZE +#define MXC_FLASH_MEM_SIZE MXC_FLASH_NS_MEM_SIZE +#define MXC_SRAM_MEM_BASE MXC_SRAM_NS_MEM_BASE +#define MXC_SRAM_MEM_SIZE MXC_SRAM_NS_MEM_SIZE +#endif /* ================================================================================ */ /* ================ Device Specific Peripheral Section ================ */ @@ -200,8 +214,11 @@ typedef enum { #define MXC_BASE_GCR_S ((uint32_t)0x50000000UL) #define MXC_GCR_S ((mxc_gcr_regs_t *)MXC_BASE_GCR_S) -#define MXC_BASE_GCR MXC_BASE_GCR_S +#if IS_SECURE_ENVIRONMENT #define MXC_GCR MXC_GCR_S +#else +#define MXC_GCR MXC_GCR_NS +#endif /******************************************************************************/ /* Non-battery backed SI Registers */ @@ -214,8 +231,13 @@ typedef enum { #define MXC_BASE_SIR_S ((uint32_t)0x50000400UL) #define MXC_SIR_S ((mxc_sir_regs_t *)MXC_BASE_SIR_S) +#if IS_SECURE_ENVIRONMENT #define MXC_BASE_SIR MXC_BASE_SIR_S #define MXC_SIR MXC_SIR_S +#else +#define MXC_BASE_SIR MXC_BASE_SIR_NS +#define MXC_SIR MXC_SIR_NS +#endif /******************************************************************************/ /* Non-Battery Backed Function Control */ @@ -228,6 +250,14 @@ typedef enum { #define MXC_BASE_FCR_S ((uint32_t)0x50000800UL) #define MXC_FCR_S ((mxc_fcr_regs_t *)MXC_BASE_FCR_S) +#if IS_SECURE_ENVIRONMENT +#define MXC_BASE_FCR MXC_BASE_FCR_S +#define MXC_FCR MXC_FCR_S +#else +#define MXC_BASE_FCR MXC_BASE_FCR_NS +#define MXC_FCR MXC_FCR_NS +#endif + /******************************************************************************/ /* Windowed Watchdog Timer */ #define MXC_CFG_WDT_INSTANCES (1) @@ -240,36 +270,51 @@ typedef enum { #define MXC_BASE_WDT_S ((uint32_t)0x50003000UL) #define MXC_WDT_S ((mxc_wdt_regs_t *)MXC_BASE_WDT_S) +#if IS_SECURE_ENVIRONMENT #define MXC_BASE_WDT MXC_BASE_WDT_S #define MXC_WDT MXC_WDT_S +#else +#define MXC_BASE_WDT MXC_BASE_WDT_NS +#define MXC_WDT MXC_WDT_NS +#endif /******************************************************************************/ /* SVM Controller */ /* Non-secure Mapping */ #define MXC_BASE_SVM_NS ((uint32_t)0x40004800UL) -#define MXC_SVM_NS //TODO(ME30): Add SVM controller registers. +#define MXC_SVM_NS 0 //TODO(ME30): Add SVM controller registers. /* Secure Mapping */ #define MXC_BASE_SVM_S ((uint32_t)0x50004800UL) -#define MXC_SVM_S //TODO(ME30): Add SVM controller registers. +#define MXC_SVM_S 0 //TODO(ME30): Add SVM controller registers. +#if IS_SECURE_ENVIRONMENT #define MXC_BASE_SVM MXC_BASE_SVM_S -#define MXC_SVM //TODO(ME30): Add SVM controller registers. +#define MXC_SVM MXC_SVM_S //TODO(ME30): Add SVM controller registers +#else +#define MXC_BASE_SVM MXC_BASE_SVM_NS +#define MXC_SVM MXC_SVM_NS +#endif /******************************************************************************/ /* Boost Controller */ /* Non-secure Mapping */ #define MXC_BASE_BOOST_NS ((uint32_t)0x40004C00UL) -#define MXC_BOOST_NS //TODO(ME30): Add Boost controller registers. +#define MXC_BOOST_NS 0 //TODO(ME30): Add Boost controller registers. /* Secure Mapping */ #define MXC_BASE_BOOST_S ((uint32_t)0x50004C00UL) -#define MXC_BOOST_S //TODO(ME30): Add Boost controller registers. +#define MXC_BOOST_S 0 //TODO(ME30): Add Boost controller registers. +#if IS_SECURE_ENVIRONMENT #define MXC_BASE_BOOST MXC_BASE_BOOST_S -#define MXC_BOOST //TODO(ME30): Add Boost controller registers. +#define MXC_BOOST MXC_BOOST_S +#else +#define MXC_BASE_BOOST MXC_BASE_BOOST_NS +#define MXC_BOOST MXC_BOOST_NS +#endif /******************************************************************************/ /* Trim System Initalization Register */ @@ -282,8 +327,13 @@ typedef enum { #define MXC_BASE_TRIMSIR_S ((uint32_t)0x50005400UL) #define MXC_TRIMSIR_S ((mxc_trimsir_regs_t *)MXC_BASE_TRIMSIR_S) +#if IS_SECURE_ENVIRONMENT #define MXC_BASE_TRIMSIR MXC_BASE_TRIMSIR_S #define MXC_TRIMSIR MXC_TRIMSIR_S +#else +#define MXC_BASE_TRIMSIR MXC_BASE_TRIMSIR_NS +#define MXC_TRIMSIR MXC_TRIMSIR_NS +#endif /******************************************************************************/ /* Real Time Clock */ @@ -296,8 +346,13 @@ typedef enum { #define MXC_BASE_RTC_S ((uint32_t)0x50006000UL) #define MXC_RTC_S ((mxc_rtc_regs_t *)MXC_BASE_RTC_S) +#if IS_SECURE_ENVIRONMENT #define MXC_BASE_RTC MXC_BASE_RTC_S #define MXC_RTC MXC_RTC_S +#else +#define MXC_BASE_RTC MXC_BASE_RTC_NS +#define MXC_RTC MXC_RTC_NS +#endif /******************************************************************************/ /* Wake-Up Timer (WUT) */ @@ -315,10 +370,17 @@ typedef enum { #define MXC_BASE_WUT1_S ((uint32_t)0x50006600UL) #define MXC_WUT1_S ((mxc_wut_regs_t *)MXC_BASE_WUT1_S) +#if IS_SECURE_ENVIRONMENT #define MXC_BASE_WUT0 MXC_BASE_WUT0_S #define MXC_WUT0 MXC_WUT0_S #define MXC_BASE_WUT1 MXC_BASE_WUT1_S #define MXC_WUT1 MXC_WUT1_S +#else +#define MXC_BASE_WUT0 MXC_BASE_WUT0_NS +#define MXC_WUT0 MXC_WUT0_NS +#define MXC_BASE_WUT1 MXC_BASE_WUT1_NS +#define MXC_WUT1 MXC_WUT1_NS +#endif /******************************************************************************/ /* Power Sequencer */ @@ -331,8 +393,13 @@ typedef enum { #define MXC_BASE_PWRSEQ_S ((uint32_t)0x50006800UL) #define MXC_PWRSEQ_S ((mxc_pwrseq_regs_t *)MXC_BASE_PWRSEQ_S) +#if IS_SECURE_ENVIRONMENT #define MXC_BASE_PWRSEQ MXC_BASE_PWRSEQ_S #define MXC_PWRSEQ MXC_PWRSEQ_S +#else +#define MXC_BASE_PWRSEQ MXC_BASE_PWRSEQ_NS +#define MXC_PWRSEQ MXC_PWRSEQ_NS +#endif /******************************************************************************/ /* Misc Control */ @@ -345,8 +412,13 @@ typedef enum { #define MXC_BASE_MCR_S ((uint32_t)0x50006C00UL) #define MXC_MCR_S ((mxc_mcr_regs_t *)MXC_BASE_MCR_S) +#if IS_SECURE_ENVIRONMENT #define MXC_BASE_MCR MXC_BASE_MCR_S #define MXC_MCR MXC_MCR_S +#else +#define MXC_BASE_MCR MXC_BASE_MCR_NS +#define MXC_MCR MXC_MCR_NS +#endif /******************************************************************************/ /* AES */ @@ -359,8 +431,13 @@ typedef enum { #define MXC_BASE_AES_S ((uint32_t)0x50007400UL) #define MXC_AES_S ((mxc_aes_regs_t *)MXC_BASE_AES_NS) +#if IS_SECURE_ENVIRONMENT #define MXC_BASE_AES MXC_BASE_AES_S #define MXC_AES MXC_AES_S +#else +#define MXC_BASE_AES MXC_BASE_AES_NS +#define MXC_AES MXC_AES_NS +#endif /******************************************************************************/ /* AES Keys */ @@ -373,8 +450,13 @@ typedef enum { #define MXC_BASE_AESKEYS_S ((uint32_t)0x50007800UL) #define MXC_AESKEYS_S ((mxc_aeskeys_regs_t *)MXC_BASE_AESKEYS_S) +#if IS_SECURE_ENVIRONMENT #define MXC_BASE_AESKEYS MXC_BASE_AESKEYS_S #define MXC_AESKEYS MXC_AESKEYS_S +#else +#define MXC_BASE_AESKEYS MXC_BASE_AESKEYS_NS +#define MXC_AESKEYS MXC_AESKEYS_NS +#endif /******************************************************************************/ /* GPIO */ @@ -392,8 +474,24 @@ typedef enum { #define MXC_BASE_GPIO0_S ((uint32_t)0x50008000UL) #define MXC_GPIO0_S ((mxc_gpio_regs_t *)MXC_BASE_GPIO0_S) +#if IS_SECURE_ENVIRONMENT #define MXC_BASE_GPIO0 MXC_BASE_GPIO0_S #define MXC_GPIO0 MXC_GPIO0_S +#else +#define MXC_BASE_GPIO0 MXC_BASE_GPIO0_NS +#define MXC_GPIO0 MXC_GPIO0_NS +#endif + +/* +Note(JC): There is only 1 GPIO instance, but for driver compatibility these must be +implemented. + +For GET_IRQ we follow precedent and return the base 0 IRQn, which is the ICE unlock. +We may want to handle GET_IRQ better... +*/ +#define MXC_GPIO_GET_IDX(p) ((p) == MXC_GPIO0 ? 0 : 0) +#define MXC_GPIO_GET_GPIO(i) ((i) == 0 ? MXC_GPIO0 : 0) +#define MXC_GPIO_GET_IRQ(i) ((i) == 0 ? GPIO0_IRQn : (IRQn_Type)0) /******************************************************************************/ /* CRC */ @@ -406,8 +504,13 @@ typedef enum { #define MXC_BASE_CRC_S ((uint32_t)0x5000F000UL) #define MXC_CRC_S ((mxc_crc_regs_t *)MXC_BASE_CRC_S) +#if IS_SECURE_ENVIRONMENT #define MXC_BASE_CRC MXC_BASE_CRC_S #define MXC_CRC MXC_CRC_S +#else +#define MXC_BASE_CRC MXC_BASE_CRC_NS +#define MXC_CRC MXC_CRC_NS +#endif /******************************************************************************/ /* Timer */ @@ -431,24 +534,6 @@ typedef enum { #define MXC_BASE_TMR5_NS ((uint32_t)0x40081000UL) #define MXC_TMR5_NS ((mxc_tmr_regs_t *)MXC_BASE_TMR5_NS) -#define MXC_TMR_NS_GET_BASE(i) \ - ((i) == 0 ? MXC_BASE_TMR0_NS : \ - (i) == 1 ? MXC_BASE_TMR1_NS : \ - (i) == 2 ? MXC_BASE_TMR2_NS : \ - (i) == 3 ? MXC_BASE_TMR3_NS : \ - (i) == 4 ? MXC_BASE_TMR4_NS : \ - (i) == 5 ? MXC_BASE_TMR5_NS : \ - 0) - -#define MXC_TMR_NS_GET_TMR(i) \ - ((i) == 0 ? MXC_TMR0_NS : \ - (i) == 1 ? MXC_TMR1_NS : \ - (i) == 2 ? MXC_TMR2_NS : \ - (i) == 3 ? MXC_TMR3_NS : \ - (i) == 4 ? MXC_TMR4_NS : \ - (i) == 5 ? MXC_TMR5_NS : \ - 0) - /* Secure Mapping */ #define MXC_BASE_TMR0_S ((uint32_t)0x50010000UL) #define MXC_TMR0_S ((mxc_tmr_regs_t *)MXC_BASE_TMR0_S) @@ -463,35 +548,38 @@ typedef enum { #define MXC_BASE_TMR5_S ((uint32_t)0x50081000UL) #define MXC_TMR5_S ((mxc_tmr_regs_t *)MXC_BASE_TMR5_S) -#define MXC_BASE_TMR0 MXC_BASE_TMR0_S +#if IS_SECURE_ENVIRONMENT #define MXC_TMR0 MXC_TMR0_S -#define MXC_BASE_TMR1 MXC_BASE_TMR1_S #define MXC_TMR1 MXC_TMR1_S -#define MXC_BASE_TMR2 MXC_BASE_TMR2_S #define MXC_TMR2 MXC_TMR2_S -#define MXC_BASE_TMR3 MXC_BASE_TMR3_S #define MXC_TMR3 MXC_TMR3_S -#define MXC_BASE_TMR4 MXC_BASE_TMR4_S #define MXC_TMR4 MXC_TMR4_S -#define MXC_BASE_TMR5 MXC_BASE_TMR5_S #define MXC_TMR5 MXC_TMR5_S +#else +#define MXC_TMR0 MXC_TMR0_NS +#define MXC_TMR1 MXC_TMR1_NS +#define MXC_TMR2 MXC_TMR2_NS +#define MXC_TMR3 MXC_TMR3_NS +#define MXC_TMR4 MXC_TMR4_NS +#define MXC_TMR5 MXC_TMR5_NS +#endif -#define MXC_TMR_S_GET_BASE(i) \ - ((i) == 0 ? MXC_BASE_TMR0_S : \ - (i) == 1 ? MXC_BASE_TMR1_S : \ - (i) == 2 ? MXC_BASE_TMR2_S : \ - (i) == 3 ? MXC_BASE_TMR3_S : \ - (i) == 4 ? MXC_BASE_TMR4_S : \ - (i) == 5 ? MXC_BASE_TMR5_S : \ +#define MXC_TMR_GET_BASE(i) \ + ((i) == 0 ? MXC_BASE_TMR0 : \ + (i) == 1 ? MXC_BASE_TMR1 : \ + (i) == 2 ? MXC_BASE_TMR2 : \ + (i) == 3 ? MXC_BASE_TMR3 : \ + (i) == 4 ? MXC_BASE_TMR4 : \ + (i) == 5 ? MXC_BASE_TMR5 : \ 0) -#define MXC_TMR_S_GET_TMR(i) \ - ((i) == 0 ? MXC_TMR0_S : \ - (i) == 1 ? MXC_TMR1_S : \ - (i) == 2 ? MXC_TMR2_S : \ - (i) == 3 ? MXC_TMR3_S : \ - (i) == 4 ? MXC_TMR4_S : \ - (i) == 5 ? MXC_TMR5_S : \ +#define MXC_TMR_GET_TMR(i) \ + ((i) == 0 ? MXC_TMR0 : \ + (i) == 1 ? MXC_TMR1 : \ + (i) == 2 ? MXC_TMR2 : \ + (i) == 3 ? MXC_TMR3 : \ + (i) == 4 ? MXC_TMR4 : \ + (i) == 5 ? MXC_TMR5 : \ 0) #define MXC_TMR_GET_IRQ(i) \ @@ -504,22 +592,18 @@ typedef enum { 0) #define MXC_TMR_GET_IDX(p) \ - ((p) == MXC_TMR0_NS ? 0 : \ - (p) == MXC_TMR1_NS ? 1 : \ - (p) == MXC_TMR2_NS ? 2 : \ - (p) == MXC_TMR3_NS ? 3 : \ - (p) == MXC_TMR4_NS ? 4 : \ - (p) == MXC_TMR5_NS ? 5 : \ - (p) == MXC_TMR0_S ? 0 : \ - (p) == MXC_TMR1_S ? 1 : \ - (p) == MXC_TMR2_S ? 2 : \ - (p) == MXC_TMR3_S ? 3 : \ - (p) == MXC_TMR4_S ? 4 : \ - (p) == MXC_TMR5_S ? 5 : \ - -1) + ((p) == MXC_TMR0 ? 0 : \ + (p) == MXC_TMR1 ? 1 : \ + (p) == MXC_TMR2 ? 2 : \ + (p) == MXC_TMR3 ? 3 : \ + (p) == MXC_TMR4 ? 4 : \ + (p) == MXC_TMR5 ? 5 : \ + -1) /******************************************************************************/ /* I3C */ +#define MXC_I3C_FIFO_DEPTH (8) // TODO(ME30): Confirm this is correct. + /* Non-secure Mapping */ #define MXC_BASE_I3C_NS ((uint32_t)0x4001D000UL) #define MXC_I3C_NS ((mxc_i2c_regs_t *)MXC_BASE_I3C_NS) @@ -528,38 +612,79 @@ typedef enum { #define MXC_BASE_I3C_S ((uint32_t)0x5001D000UL) #define MXC_I3C_S ((mxc_i2c_regs_t *)MXC_BASE_I3C_S) -#define MXC_BASE_I3C MXC_BASE_I2C_S +#if IS_SECURE_ENVIRONMENT +#define MXC_BASE_I3C MXC_BASE_I3C_S #define MXC_I3C MXC_I3C_S - -#define MXC_I3C_FIFO_DEPTH (8) // TODO(ME30): Confirm this is correct. +#else +#define MXC_BASE_I3C MXC_BASE_I3C_NS +#define MXC_I3C MXC_I3C_NS +#endif /******************************************************************************/ /* DMA */ #define MXC_DMA_CHANNELS (4) +#if IS_SECURE_ENVIRONMENT #define MXC_DMA_INSTANCES (2) +#else +#define MXC_DMA_INSTANCES (1) +#endif /* Non-secure Mapping */ #define MXC_BASE_DMA0_NS ((uint32_t)0x40028000UL) #define MXC_DMA0_NS ((mxc_dma_regs_t *)MXC_BASE_DMA0_NS) -/* DMA1 instance only for secure mode. */ /* Secure Mapping */ +// TODO(ME30): Is there actuall a secure mapping for DMA0? +// -Yes, DMA0 can be accessed from secure mode. Realizing this, I think +// we would still have to define two DMA instances. +// DMA0 can only access the non-secure mappings of the peripherals, +// but DMA0 can be accessed in both Non-secure and Secure code. +// DMA1 can access both secure and non-secure addresses of the peripherals, +// but DMA1 can Only be accessed in Secure code. #define MXC_BASE_DMA0_S ((uint32_t)0x50028000UL) #define MXC_DMA0_S ((mxc_dma_regs_t *)MXC_BASE_DMA0_S) #define MXC_BASE_DMA1_S ((uint32_t)0x50035000UL) #define MXC_DMA1_S ((mxc_dma_regs_t *)MXC_BASE_DMA1_S) +#if IS_SECURE_ENVIRONMENT #define MXC_BASE_DMA0 MXC_BASE_DMA0_S #define MXC_DMA0 MXC_DMA0_S #define MXC_BASE_DMA1 MXC_BASE_DMA1_S #define MXC_DMA1 MXC_DMA1_S -#define MXC_DMA_CH_GET_IRQ(i) \ - ((IRQn_Type)(((i) == 0) ? DMA0_IRQn : \ - ((i) == 1) ? DMA1_IRQn : \ - ((i) == 2) ? DMA2_IRQn : \ - ((i) == 3) ? DMA3_IRQn : \ +#define MXC_DMA_CH_GET_IRQ(p, i) \ + ((IRQn_Type)(((p) == MXC_DMA0 && (i) == 0) ? DMA0_CH0_IRQn : \ + ((p) == MXC_DMA0 && (i) == 1) ? DMA0_CH1_IRQn : \ + ((p) == MXC_DMA0 && (i) == 2) ? DMA0_CH2_IRQn : \ + ((p) == MXC_DMA0 && (i) == 3) ? DMA0_CH3_IRQn : \ + ((p) == MXC_DMA1 && (i) == 0) ? DMA1_CH0_IRQn : \ + ((p) == MXC_DMA1 && (i) == 1) ? DMA1_CH1_IRQn : \ + ((p) == MXC_DMA1 && (i) == 2) ? DMA1_CH2_IRQn : \ + ((p) == MXC_DMA1 && (i) == 3) ? DMA1_CH3_IRQn : \ + 0)) + +#else +#define MXC_BASE_DMA0 MXC_BASE_DMA0_NS +#define MXC_DMA0 MXC_DMA0_NS +// TODO(DMA1): Not entirely show how to handle access to MXC_DMA1 in non-secure mode. +// A secure fault should be generated when non-secure code accesses +// a secure peripheral mapping, so it'd be best if a build time warning +// or error was thrown when using MXCX_DMA1. +#define MXC_BASE_DMA1 0 +#define MXC_DMA1 0 + +/* DMA1 IRQs not usable in Non-Secure state. */ +#define MXC_DMA_CH_GET_IRQ(p, i) \ + ((IRQn_Type)(((p) == MXC_DMA0 && (i) == 0) ? DMA0_CH0_IRQn : \ + ((p) == MXC_DMA0 && (i) == 1) ? DMA0_CH1_IRQn : \ + ((p) == MXC_DMA0 && (i) == 2) ? DMA0_CH2_IRQn : \ + ((p) == MXC_DMA0 && (i) == 3) ? DMA0_CH3_IRQn : \ 0)) +#endif // IS_SECURE_ENVIRONMENT + +#define MXC_DMA_GET_BASE(i) ((i) == MXC_BASE_DMA0 ? 0 : (p) == MXC_BASE_DMA1 ? 1 : -1) + +#define MXC_DMA_GET_IDX(p) ((p) == MXC_DMA0 ? 0 : (p) == MXC_DMA1 ? 1 : -1) /******************************************************************************/ /* Flash Controller */ @@ -573,6 +698,12 @@ typedef enum { #define MXC_BASE_FLC_S MXC_BASE_FLC #define MXC_FLC_S MXC_FLC +/** + * There is only one flash instance, but some bottom-level RevX implementations + * depend on MXC_FLC_GET_FLC + */ +#define MXC_FLC_GET_FLC(i) ((i) == 0 ? MXC_FLC : 0) + /******************************************************************************/ /* Internal Cache Controller */ #define MXC_ICC_INSTANCES (1) @@ -588,25 +719,26 @@ typedef enum { /******************************************************************************/ /* UART / Serial Port Interface */ #define MXC_UART_INSTANCES (1) -#define MXC_UART_FIFO_DEPTH (8) // TOD(ME30): Check this is correct. +#define MXC_UART_FIFO_DEPTH (8) // TODO(ME30): Check this is correct. /* Non-secure Mapping */ #define MXC_BASE_UART_NS ((uint32_t)0x40042000UL) #define MXC_UART_NS ((mxc_uart_regs_t *)MXC_BASE_UART_NS) -#define MXC_UART_NS_GET_BASE(i) ((i) == 0 ? MXC_BASE_UART0_NS : 0) -#define MXC_UART_NS_GET_UART(i) ((i) == 0 ? MXC_UART_NS : 0) - /* Secure Mapping */ #define MXC_BASE_UART_S ((uint32_t)0x50042000UL) #define MXC_UART_S ((mxc_uart_regs_t *)MXC_BASE_UART_S) +#if IS_SECURE_ENVIRONMENT #define MXC_BASE_UART MXC_BASE_UART_S #define MXC_UART MXC_UART_S +#else +#define MXC_BASE_UART MXC_BASE_UART_NS +#define MXC_UART MXC_UART_NS +#endif -#define MXC_UART_S_GET_UART(i) ((i) == 0 ? MXC_UART_S : 0) -#define MXC_UART_S_GET_BASE(i) ((i) == 0 ? MXC_BASE_UART0_S : 0) - +#define MXC_UART_GET_BASE(i) ((i) == 0 ? MXC_BASE_UART : 0) +#define MXC_UART_GET_UART(i) ((i) == 0 ? MXC_UART : 0) #define MXC_UART_GET_IRQ(i) (IRQn_Type)((i) == 0 ? UART0_IRQn : 0) #define MXC_UART_GET_IDX(p) ((p) == MXC_UART_NS ? 0 : (p) == MXC_UART_S ? 0 : -1) @@ -620,19 +752,20 @@ typedef enum { #define MXC_BASE_SPI_NS ((uint32_t)0x40046000UL) #define MXC_SPI_NS ((mxc_spi_regs_t *)MXC_BASE_SPI_NS) -#define MXC_SPI_NS_GET_BASE(i) ((i) == 0 ? MXC_BASE_SPI_NS : 0) -#define MXC_SPI_NS_GET_SPI(i) ((i) == 0 ? MXC_SPI_NS : 0) - /* Secure Mapping */ #define MXC_BASE_SPI_S ((uint32_t)0x50046000UL) #define MXC_SPI_S ((mxc_spi_regs_t *)MXC_BASE_SPI_S) +#if IS_SECURE_ENVIRONMENT #define MXC_BASE_SPI MXC_BASE_SPI_S #define MXC_SPI MXC_SPI_S +#else +#define MXC_BASE_SPI MXC_BASE_SPI_S +#define MXC_SPI MXC_SPI_NS +#endif -#define MXC_SPI_S_GET_BASE(i) ((i) == 0 ? MXC_BASE_SPI_S : 0) -#define MXC_SPI_S_GET_SPI(i) ((i) == 0 ? MXC_SPI_S : 0) - +#define MXC_SPI_GET_BASE(i) ((i) == 0 ? MXC_BASE_SPI : 0) +#define MXC_SPI_GET_SPI(i) ((i) == 0 ? MXC_SPI : 0) #define MXC_SPI_GET_IRQ(i) (IRQn_Type)((i) == 0 ? SPI_IRQn : 0) #define MXC_SPI_GET_IDX(p) ((p) == MXC_SPI_NS ? 0 : (p) == MXC_SPI_S ? 0 : -1) @@ -647,8 +780,13 @@ typedef enum { #define MXC_BASE_TRNG_S ((uint32_t)0x5004D000UL) #define MXC_TRNG_S ((mxc_trng_regs_t *)MXC_BASE_TRNG_S) +#if IS_SECURE_ENVIRONMENT #define MXC_BASE_TRNG MXC_BASE_TRNG_S #define MXC_TRNG MXC_TRNG_S +#else +#define MXC_BASE_TRNG MXC_BASE_TRNG_NS +#define MXC_TRNG MXC_TRNG_NS +#endif /******************************************************************************/ /* BTLE */ @@ -662,8 +800,14 @@ typedef enum { #define MXC_BASE_BTLE_S ((uint32_t)0x50050000UL) #define MXC_BTLE_S // TODO(ME30): Add BTLE related registers? This section doesn't exist for ME17. +#if IS_SECURE_ENVIRONMENT +// TODO(ME30): Does this have registers? #define MXC_BASE_BTLE MXC_BASE_BTLE_S -#define MXC_BTLE // TODO(ME30): Does this have registers? +#define MXC_BTLE MXC_BTLE_S +#else +#define MXC_BASE_BTLE MXC_BASE_BTLE_NS +#define MXC_BTLE MXC_BTLE_NS +#endif /******************************************************************************/ /* Secure Privilege Control (SPC TZ) */ @@ -671,8 +815,6 @@ typedef enum { /* Secure Mapping Only */ #define MXC_BASE_SPC ((uint32_t)0x50090000UL) #define MXC_SPC // TODO(ME30): Does this have registers? - -#define MXC_BASE_SPC_S MXC_BASE_SPC #define MXC_SPC_S // TODO(ME30): Does this have registers? /******************************************************************************/ @@ -753,4 +895,12 @@ typedef enum { #define MXC_SETFIELD(reg, mask, setting) ((reg) = ((reg) & ~(mask)) | ((setting) & (mask))) +/******************************************************************************/ +/* CPACR Definitions */ +/* Note: Added by Maxim Integrated, as these are missing from CMSIS/Core/Include/core_cm33.h */ +#define SCB_CPACR_CP10_Pos 20 /*!< SCB CPACR: Coprocessor 10 Position */ +#define SCB_CPACR_CP10_Msk (0x3UL << SCB_CPACR_CP10_Pos) /*!< SCB CPACR: Coprocessor 10 Mask */ +#define SCB_CPACR_CP11_Pos 22 /*!< SCB CPACR: Coprocessor 11 Position */ +#define SCB_CPACR_CP11_Msk (0x3UL << SCB_CPACR_CP11_Pos) /*!< SCB CPACR: Coprocessor 11 Mask */ + #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX326657_INCLUDE_MAX32657_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/partition_max32657.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/partition_max32657.h new file mode 100644 index 00000000000..5b9fed2bedf --- /dev/null +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/partition_max32657.h @@ -0,0 +1,1285 @@ +/*************************************************************************//** + * @file partition_max32657.h + * @brief CMSIS-Core(M) Device Initial Setup for Secure/Non-Secure Zones for + * MAX32657 + * @version V1.0.0 + * @date 20. January 2021 + *****************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * Portions Copyright (C) 2024 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_SOURCE_GCC_PARTITION_MAX32657_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_SOURCE_GCC_PARTITION_MAX32657_H_ + +#include "max32657.h" + +#if IS_SECURE_ENVIRONMENT + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +*/ + +/* +// Enable SAU +// Value for SAU->CTRL register bit ENABLE +*/ +#define SAU_INIT_CTRL_ENABLE 1 + +/* +// When SAU is disabled +// <0=> All Memory is Secure +// <1=> All Memory is Non-Secure +// Value for SAU->CTRL register bit ALLNS +// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. +*/ +#define SAU_INIT_CTRL_ALLNS 0 + +/* +// +*/ + +/* +// Initialize Security Attribution Unit (SAU) Address Regions +// SAU configuration specifies regions to be one of: +// - Secure and Non-Secure Callable +// - Non-Secure +// Note: All memory regions not configured by SAU are Secure +*/ +/** + * Analog Devices, Inc. + * 4 Regions in the MAX32657. + * 1. Non-Secure Flash + * 2. Secure Flash + * 3. Non-Secure SRAM + * 4. Secure SRAM + * + * Finer grain control can be achieved depending on the application + * requirements by updating the regions of this file. + * + * Non-Secure Flash (1MB) 0x0100.0000 - 0x010F.FFFF + * Non-Secure SRAM0 (32kB) 0x2000.0000 - 0x2000.7FFF + * Non-Secure SRAM1 (32kB) 0x2000.8000 - 0x2000.FFFF + * Non-Secure SRAM2 (64kB) 0x2001.0000 - 0x2001.FFFF + * Non-Secure SRAM3 (64kB) 0x2002.0000 - 0x2002.FFFF + * Non-Secure SRAM4 (64kB) 0x2003.0000 - 0x2003.FFFF + * + * Secure Flash (1MB) 0x1100.0000 - 0x110F.FFFF + * Secure SRAM0 (32kB) 0x3000.0000 - 0x3000.7FFF + * Secure SRAM1 (32kB) 0x3000.8000 - 0x3000.FFFF + * Secure SRAM2 (64kB) 0x3001.0000 - 0x3001.FFFF + * Secure SRAM3 (64kB) 0x3002.0000 - 0x3002.FFFF + * Secure SRAM4 (64kB) 0x3003.0000 - 0x3003.FFFF + */ +#define SAU_REGIONS_MAX 4 /* Max. number of SAU regions */ + +/* +// Initialize SAU Region 0 (Secure Flash) +// Setup SAU Region 0 memory attributes +*/ +#define SAU_INIT_REGION0 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START0 0x11000000 /* start address of SAU region 0 (ROM) */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END0 0x110FFFFF /* end address of SAU region 0 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC0 1 +/* +// +*/ + +/* +// Initialize SAU Region 1 (Non-Secure Flash) +// Setup SAU Region 1 memory attributes +*/ +#define SAU_INIT_REGION1 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START1 0x01000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END1 0x010FFFFF + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC1 0 +/* +// +*/ + +/* +// Initialize SAU Region 2 (Secure SRAM) +// Setup SAU Region 2 memory attributes +*/ +#define SAU_INIT_REGION2 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START2 0x30000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END2 0x3003FFFF + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC2 1 +/* +// +*/ + +/* +// Initialize SAU Region 3 (Non-Secure SRAM) +// Setup SAU Region 3 memory attributes +*/ +#define SAU_INIT_REGION3 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START3 0x20000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END3 0x2003FFFF + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC3 0 +/* +// +*/ + +/* +// Initialize SAU Region 4 +// Setup SAU Region 4 memory attributes +*/ +#define SAU_INIT_REGION4 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC4 0 +/* +// +*/ + +/* +// Initialize SAU Region 5 +// Setup SAU Region 5 memory attributes +*/ +#define SAU_INIT_REGION5 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START5 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END5 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC5 0 +/* +// +*/ + +/* +// Initialize SAU Region 6 +// Setup SAU Region 6 memory attributes +*/ +#define SAU_INIT_REGION6 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START6 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END6 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC6 0 +/* +// +*/ + +/* +// Initialize SAU Region 7 +// Setup SAU Region 7 memory attributes +*/ +#define SAU_INIT_REGION7 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START7 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END7 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC7 0 +/* +// +*/ + +/* +// +*/ + +/* +// Setup behaviour of Sleep and Exception Handling +*/ +#define SCB_CSR_AIRCR_INIT 1 + +/* +// Deep Sleep can be enabled by +// <0=>Secure and Non-Secure state +// <1=>Secure state only +// Value for SCB->CSR register bit DEEPSLEEPS +*/ +#define SCB_CSR_DEEPSLEEPS_VAL 1 + +/* +// System reset request accessible from +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for SCB->AIRCR register bit SYSRESETREQS +*/ +#define SCB_AIRCR_SYSRESETREQS_VAL 1 + +/* +// Priority of Non-Secure exceptions is +// <0=> Not altered +// <1=> Lowered to 0x80-0xFF +// Value for SCB->AIRCR register bit PRIS +*/ +#define SCB_AIRCR_PRIS_VAL 1 + +/* +// BusFault, HardFault, and NMI target +// <0=> Secure state +// <1=> Non-Secure state +// Value for SCB->AIRCR register bit BFHFNMINS +*/ +#define SCB_AIRCR_BFHFNMINS_VAL 0 + +/* +// +*/ + +/* +// Setup behaviour of Floating Point and Vector Unit (FPU/MVE) +*/ +#define TZ_FPU_NS_USAGE 1 + +/* +// Floating Point and Vector Unit usage +// <0=> Secure state only +// <3=> Secure and Non-Secure state +// Value for SCB->NSACR register bits CP10, CP11 +*/ +#define SCB_NSACR_CP10_11_VAL 3 + +/* +// Treat floating-point registers as Secure +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit TS +*/ +#define FPU_FPCCR_TS_VAL 0 + +/* +// Clear on return (CLRONRET) accessibility +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for FPU->FPCCR register bit CLRONRETS +*/ +#define FPU_FPCCR_CLRONRETS_VAL 0 + +/* +// Clear floating-point caller saved registers on exception return +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit CLRONRET +*/ +#define FPU_FPCCR_CLRONRET_VAL 1 + +/* +// +*/ + +/* +// Setup Interrupt Target +*/ + +/* +// Initialize ITNS 0 (Interrupts 0..31) +*/ +#define NVIC_INIT_ITNS0 1 + +/* +// Interrupts 0..31 +// ICE Unlock <0=> Secure state <1=> Non-Secure state +// Watchdog Timer <0=> Secure state <1=> Non-Secure state +// Real Time Clock <0=> Secure state <1=> Non-Secure state +// True Random Number Generator <0=> Secure state <1=> Non-Secure state +// Timer 0 <0=> Secure state <1=> Non-Secure state +// Timer 1 <0=> Secure state <1=> Non-Secure state +// Timer 2 <0=> Secure state <1=> Non-Secure state +// Timer 3 <0=> Secure state <1=> Non-Secure state +// Timer 4 <0=> Secure state <1=> Non-Secure state +// Timer 5 <0=> Secure state <1=> Non-Secure state +// I3C <0=> Secure state <1=> Non-Secure state +// UART <0=> Secure state <1=> Non-Secure state +// SPI <0=> Secure state <1=> Non-Secure state +// Flash Controller <0=> Secure state <1=> Non-Secure state +// GPIO0 <0=> Secure state <1=> Non-Secure state +// Reserved (15) <0=> Secure state <1=> Non-Secure state +// DMA0 Channel 0 <0=> Secure state <1=> Non-Secure state +// DMA0 Channel 1 <0=> Secure state <1=> Non-Secure state +// DMA0 Channel 2 <0=> Secure state <1=> Non-Secure state +// DMA0 Channel 3 <0=> Secure state <1=> Non-Secure state +// DMA1 Channel 0 <0=> Secure state <1=> Non-Secure state +// DMA1 Channel 1 <0=> Secure state <1=> Non-Secure state +// DMA1 Channel 2 <0=> Secure state <1=> Non-Secure state +// DMA1 Channel 3 <0=> Secure state <1=> Non-Secure state +// Wakeup Timer 0 <0=> Secure state <1=> Non-Secure state +// Wakeup Timer 1 <0=> Secure state <1=> Non-Secure state +// GPIO Wake <0=> Secure state <1=> Non-Secure state +// CRC <0=> Secure state <1=> Non-Secure state +// AES <0=> Secure state <1=> Non-Secure state +// ERFO Ready <0=> Secure state <1=> Non-Secure state +// Boost Controller <0=> Secure state <1=> Non-Secure state +// ECC <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS0_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 1 (Interrupts 32..63) +*/ +#define NVIC_INIT_ITNS1 1 + +/* +// Interrupts 32..63 +// BTLE XXXX0 <0=> Secure state <1=> Non-Secure state +// BTLE XXXX1 <0=> Secure state <1=> Non-Secure state +// BTLE XXXX2 <0=> Secure state <1=> Non-Secure state +// BTLE XXXX3 <0=> Secure state <1=> Non-Secure state +// BTLE XXXX4 <0=> Secure state <1=> Non-Secure state +// BTLE XXXX5 <0=> Secure state <1=> Non-Secure state +// BTLE XXXX6 <0=> Secure state <1=> Non-Secure state +// BTLE XXXX7 <0=> Secure state <1=> Non-Secure state +// BTLE XXXX8 <0=> Secure state <1=> Non-Secure state +// BTLE XXXX9 <0=> Secure state <1=> Non-Secure state +// BTLE XXXXA <0=> Secure state <1=> Non-Secure state +// BTLE XXXXB <0=> Secure state <1=> Non-Secure state +// BTLE XXXXC <0=> Secure state <1=> Non-Secure state +// BTLE XXXXD <0=> Secure state <1=> Non-Secure state +// BTLE XXXXE <0=> Secure state <1=> Non-Secure state +// Reserved (47) <0=> Secure state <1=> Non-Secure state +// MPC Combined (Secure) <0=> Secure state <1=> Non-Secure state +// PPC Combined (Secure) <0=> Secure state <1=> Non-Secure state +// Reserved (50) <0=> Secure state <1=> Non-Secure state +// Reserved (51) <0=> Secure state <1=> Non-Secure state +// Reserved (52) <0=> Secure state <1=> Non-Secure state +// Reserved (53) <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS1_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 2 (Interrupts 64..95) +*/ +#define NVIC_INIT_ITNS2 0 + +/* +// Interrupts 64..95 +// Interrupt 64 <0=> Secure state <1=> Non-Secure state +// Interrupt 65 <0=> Secure state <1=> Non-Secure state +// Interrupt 66 <0=> Secure state <1=> Non-Secure state +// Interrupt 67 <0=> Secure state <1=> Non-Secure state +// Interrupt 68 <0=> Secure state <1=> Non-Secure state +// Interrupt 69 <0=> Secure state <1=> Non-Secure state +// Interrupt 70 <0=> Secure state <1=> Non-Secure state +// Interrupt 71 <0=> Secure state <1=> Non-Secure state +// Interrupt 72 <0=> Secure state <1=> Non-Secure state +// Interrupt 73 <0=> Secure state <1=> Non-Secure state +// Interrupt 74 <0=> Secure state <1=> Non-Secure state +// Interrupt 75 <0=> Secure state <1=> Non-Secure state +// Interrupt 76 <0=> Secure state <1=> Non-Secure state +// Interrupt 77 <0=> Secure state <1=> Non-Secure state +// Interrupt 78 <0=> Secure state <1=> Non-Secure state +// Interrupt 79 <0=> Secure state <1=> Non-Secure state +// Interrupt 80 <0=> Secure state <1=> Non-Secure state +// Interrupt 81 <0=> Secure state <1=> Non-Secure state +// Interrupt 82 <0=> Secure state <1=> Non-Secure state +// Interrupt 83 <0=> Secure state <1=> Non-Secure state +// Interrupt 84 <0=> Secure state <1=> Non-Secure state +// Interrupt 85 <0=> Secure state <1=> Non-Secure state +// Interrupt 86 <0=> Secure state <1=> Non-Secure state +// Interrupt 87 <0=> Secure state <1=> Non-Secure state +// Interrupt 88 <0=> Secure state <1=> Non-Secure state +// Interrupt 89 <0=> Secure state <1=> Non-Secure state +// Interrupt 90 <0=> Secure state <1=> Non-Secure state +// Interrupt 91 <0=> Secure state <1=> Non-Secure state +// Interrupt 92 <0=> Secure state <1=> Non-Secure state +// Interrupt 93 <0=> Secure state <1=> Non-Secure state +// Interrupt 94 <0=> Secure state <1=> Non-Secure state +// Interrupt 95 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS2_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 3 (Interrupts 96..127) +*/ +#define NVIC_INIT_ITNS3 0 + +/* +// Interrupts 96..127 +// Interrupt 96 <0=> Secure state <1=> Non-Secure state +// Interrupt 97 <0=> Secure state <1=> Non-Secure state +// Interrupt 98 <0=> Secure state <1=> Non-Secure state +// Interrupt 99 <0=> Secure state <1=> Non-Secure state +// Interrupt 100 <0=> Secure state <1=> Non-Secure state +// Interrupt 101 <0=> Secure state <1=> Non-Secure state +// Interrupt 102 <0=> Secure state <1=> Non-Secure state +// Interrupt 103 <0=> Secure state <1=> Non-Secure state +// Interrupt 104 <0=> Secure state <1=> Non-Secure state +// Interrupt 105 <0=> Secure state <1=> Non-Secure state +// Interrupt 106 <0=> Secure state <1=> Non-Secure state +// Interrupt 107 <0=> Secure state <1=> Non-Secure state +// Interrupt 108 <0=> Secure state <1=> Non-Secure state +// Interrupt 109 <0=> Secure state <1=> Non-Secure state +// Interrupt 110 <0=> Secure state <1=> Non-Secure state +// Interrupt 111 <0=> Secure state <1=> Non-Secure state +// Interrupt 112 <0=> Secure state <1=> Non-Secure state +// Interrupt 113 <0=> Secure state <1=> Non-Secure state +// Interrupt 114 <0=> Secure state <1=> Non-Secure state +// Interrupt 115 <0=> Secure state <1=> Non-Secure state +// Interrupt 116 <0=> Secure state <1=> Non-Secure state +// Interrupt 117 <0=> Secure state <1=> Non-Secure state +// Interrupt 118 <0=> Secure state <1=> Non-Secure state +// Interrupt 119 <0=> Secure state <1=> Non-Secure state +// Interrupt 120 <0=> Secure state <1=> Non-Secure state +// Interrupt 121 <0=> Secure state <1=> Non-Secure state +// Interrupt 122 <0=> Secure state <1=> Non-Secure state +// Interrupt 123 <0=> Secure state <1=> Non-Secure state +// Interrupt 124 <0=> Secure state <1=> Non-Secure state +// Interrupt 125 <0=> Secure state <1=> Non-Secure state +// Interrupt 126 <0=> Secure state <1=> Non-Secure state +// Interrupt 127 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS3_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 4 (Interrupts 128..159) +*/ +#define NVIC_INIT_ITNS4 0 + +/* +// Interrupts 128..159 +// Interrupt 128 <0=> Secure state <1=> Non-Secure state +// Interrupt 129 <0=> Secure state <1=> Non-Secure state +// Interrupt 130 <0=> Secure state <1=> Non-Secure state +// Interrupt 131 <0=> Secure state <1=> Non-Secure state +// Interrupt 132 <0=> Secure state <1=> Non-Secure state +// Interrupt 133 <0=> Secure state <1=> Non-Secure state +// Interrupt 134 <0=> Secure state <1=> Non-Secure state +// Interrupt 135 <0=> Secure state <1=> Non-Secure state +// Interrupt 136 <0=> Secure state <1=> Non-Secure state +// Interrupt 137 <0=> Secure state <1=> Non-Secure state +// Interrupt 138 <0=> Secure state <1=> Non-Secure state +// Interrupt 139 <0=> Secure state <1=> Non-Secure state +// Interrupt 140 <0=> Secure state <1=> Non-Secure state +// Interrupt 141 <0=> Secure state <1=> Non-Secure state +// Interrupt 142 <0=> Secure state <1=> Non-Secure state +// Interrupt 143 <0=> Secure state <1=> Non-Secure state +// Interrupt 144 <0=> Secure state <1=> Non-Secure state +// Interrupt 145 <0=> Secure state <1=> Non-Secure state +// Interrupt 146 <0=> Secure state <1=> Non-Secure state +// Interrupt 147 <0=> Secure state <1=> Non-Secure state +// Interrupt 148 <0=> Secure state <1=> Non-Secure state +// Interrupt 149 <0=> Secure state <1=> Non-Secure state +// Interrupt 150 <0=> Secure state <1=> Non-Secure state +// Interrupt 151 <0=> Secure state <1=> Non-Secure state +// Interrupt 152 <0=> Secure state <1=> Non-Secure state +// Interrupt 153 <0=> Secure state <1=> Non-Secure state +// Interrupt 154 <0=> Secure state <1=> Non-Secure state +// Interrupt 155 <0=> Secure state <1=> Non-Secure state +// Interrupt 156 <0=> Secure state <1=> Non-Secure state +// Interrupt 157 <0=> Secure state <1=> Non-Secure state +// Interrupt 158 <0=> Secure state <1=> Non-Secure state +// Interrupt 159 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS4_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 5 (Interrupts 160..191) +*/ +#define NVIC_INIT_ITNS5 0 + +/* +// Interrupts 160..191 +// Interrupt 160 <0=> Secure state <1=> Non-Secure state +// Interrupt 161 <0=> Secure state <1=> Non-Secure state +// Interrupt 162 <0=> Secure state <1=> Non-Secure state +// Interrupt 163 <0=> Secure state <1=> Non-Secure state +// Interrupt 164 <0=> Secure state <1=> Non-Secure state +// Interrupt 165 <0=> Secure state <1=> Non-Secure state +// Interrupt 166 <0=> Secure state <1=> Non-Secure state +// Interrupt 167 <0=> Secure state <1=> Non-Secure state +// Interrupt 168 <0=> Secure state <1=> Non-Secure state +// Interrupt 169 <0=> Secure state <1=> Non-Secure state +// Interrupt 170 <0=> Secure state <1=> Non-Secure state +// Interrupt 171 <0=> Secure state <1=> Non-Secure state +// Interrupt 172 <0=> Secure state <1=> Non-Secure state +// Interrupt 173 <0=> Secure state <1=> Non-Secure state +// Interrupt 174 <0=> Secure state <1=> Non-Secure state +// Interrupt 175 <0=> Secure state <1=> Non-Secure state +// Interrupt 176 <0=> Secure state <1=> Non-Secure state +// Interrupt 177 <0=> Secure state <1=> Non-Secure state +// Interrupt 178 <0=> Secure state <1=> Non-Secure state +// Interrupt 179 <0=> Secure state <1=> Non-Secure state +// Interrupt 180 <0=> Secure state <1=> Non-Secure state +// Interrupt 181 <0=> Secure state <1=> Non-Secure state +// Interrupt 182 <0=> Secure state <1=> Non-Secure state +// Interrupt 183 <0=> Secure state <1=> Non-Secure state +// Interrupt 184 <0=> Secure state <1=> Non-Secure state +// Interrupt 185 <0=> Secure state <1=> Non-Secure state +// Interrupt 186 <0=> Secure state <1=> Non-Secure state +// Interrupt 187 <0=> Secure state <1=> Non-Secure state +// Interrupt 188 <0=> Secure state <1=> Non-Secure state +// Interrupt 189 <0=> Secure state <1=> Non-Secure state +// Interrupt 190 <0=> Secure state <1=> Non-Secure state +// Interrupt 191 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS5_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 6 (Interrupts 192..223) +*/ +#define NVIC_INIT_ITNS6 0 + +/* +// Interrupts 192..223 +// Interrupt 192 <0=> Secure state <1=> Non-Secure state +// Interrupt 193 <0=> Secure state <1=> Non-Secure state +// Interrupt 194 <0=> Secure state <1=> Non-Secure state +// Interrupt 195 <0=> Secure state <1=> Non-Secure state +// Interrupt 196 <0=> Secure state <1=> Non-Secure state +// Interrupt 197 <0=> Secure state <1=> Non-Secure state +// Interrupt 198 <0=> Secure state <1=> Non-Secure state +// Interrupt 199 <0=> Secure state <1=> Non-Secure state +// Interrupt 200 <0=> Secure state <1=> Non-Secure state +// Interrupt 201 <0=> Secure state <1=> Non-Secure state +// Interrupt 202 <0=> Secure state <1=> Non-Secure state +// Interrupt 203 <0=> Secure state <1=> Non-Secure state +// Interrupt 204 <0=> Secure state <1=> Non-Secure state +// Interrupt 205 <0=> Secure state <1=> Non-Secure state +// Interrupt 206 <0=> Secure state <1=> Non-Secure state +// Interrupt 207 <0=> Secure state <1=> Non-Secure state +// Interrupt 208 <0=> Secure state <1=> Non-Secure state +// Interrupt 209 <0=> Secure state <1=> Non-Secure state +// Interrupt 210 <0=> Secure state <1=> Non-Secure state +// Interrupt 211 <0=> Secure state <1=> Non-Secure state +// Interrupt 212 <0=> Secure state <1=> Non-Secure state +// Interrupt 213 <0=> Secure state <1=> Non-Secure state +// Interrupt 214 <0=> Secure state <1=> Non-Secure state +// Interrupt 215 <0=> Secure state <1=> Non-Secure state +// Interrupt 216 <0=> Secure state <1=> Non-Secure state +// Interrupt 217 <0=> Secure state <1=> Non-Secure state +// Interrupt 218 <0=> Secure state <1=> Non-Secure state +// Interrupt 219 <0=> Secure state <1=> Non-Secure state +// Interrupt 220 <0=> Secure state <1=> Non-Secure state +// Interrupt 221 <0=> Secure state <1=> Non-Secure state +// Interrupt 222 <0=> Secure state <1=> Non-Secure state +// Interrupt 223 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS6_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 7 (Interrupts 224..255) +*/ +#define NVIC_INIT_ITNS7 0 + +/* +// Interrupts 224..255 +// Interrupt 224 <0=> Secure state <1=> Non-Secure state +// Interrupt 225 <0=> Secure state <1=> Non-Secure state +// Interrupt 226 <0=> Secure state <1=> Non-Secure state +// Interrupt 227 <0=> Secure state <1=> Non-Secure state +// Interrupt 228 <0=> Secure state <1=> Non-Secure state +// Interrupt 229 <0=> Secure state <1=> Non-Secure state +// Interrupt 230 <0=> Secure state <1=> Non-Secure state +// Interrupt 231 <0=> Secure state <1=> Non-Secure state +// Interrupt 232 <0=> Secure state <1=> Non-Secure state +// Interrupt 233 <0=> Secure state <1=> Non-Secure state +// Interrupt 234 <0=> Secure state <1=> Non-Secure state +// Interrupt 235 <0=> Secure state <1=> Non-Secure state +// Interrupt 236 <0=> Secure state <1=> Non-Secure state +// Interrupt 237 <0=> Secure state <1=> Non-Secure state +// Interrupt 238 <0=> Secure state <1=> Non-Secure state +// Interrupt 239 <0=> Secure state <1=> Non-Secure state +// Interrupt 240 <0=> Secure state <1=> Non-Secure state +// Interrupt 241 <0=> Secure state <1=> Non-Secure state +// Interrupt 242 <0=> Secure state <1=> Non-Secure state +// Interrupt 243 <0=> Secure state <1=> Non-Secure state +// Interrupt 244 <0=> Secure state <1=> Non-Secure state +// Interrupt 245 <0=> Secure state <1=> Non-Secure state +// Interrupt 246 <0=> Secure state <1=> Non-Secure state +// Interrupt 247 <0=> Secure state <1=> Non-Secure state +// Interrupt 248 <0=> Secure state <1=> Non-Secure state +// Interrupt 249 <0=> Secure state <1=> Non-Secure state +// Interrupt 250 <0=> Secure state <1=> Non-Secure state +// Interrupt 251 <0=> Secure state <1=> Non-Secure state +// Interrupt 252 <0=> Secure state <1=> Non-Secure state +// Interrupt 253 <0=> Secure state <1=> Non-Secure state +// Interrupt 254 <0=> Secure state <1=> Non-Secure state +// Interrupt 255 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS7_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 8 (Interrupts 256..287) +*/ +#define NVIC_INIT_ITNS8 0 + +/* +// Interrupts 256..287 +// Interrupt 256 <0=> Secure state <1=> Non-Secure state +// Interrupt 257 <0=> Secure state <1=> Non-Secure state +// Interrupt 258 <0=> Secure state <1=> Non-Secure state +// Interrupt 259 <0=> Secure state <1=> Non-Secure state +// Interrupt 260 <0=> Secure state <1=> Non-Secure state +// Interrupt 261 <0=> Secure state <1=> Non-Secure state +// Interrupt 262 <0=> Secure state <1=> Non-Secure state +// Interrupt 263 <0=> Secure state <1=> Non-Secure state +// Interrupt 264 <0=> Secure state <1=> Non-Secure state +// Interrupt 265 <0=> Secure state <1=> Non-Secure state +// Interrupt 266 <0=> Secure state <1=> Non-Secure state +// Interrupt 267 <0=> Secure state <1=> Non-Secure state +// Interrupt 268 <0=> Secure state <1=> Non-Secure state +// Interrupt 269 <0=> Secure state <1=> Non-Secure state +// Interrupt 270 <0=> Secure state <1=> Non-Secure state +// Interrupt 271 <0=> Secure state <1=> Non-Secure state +// Interrupt 272 <0=> Secure state <1=> Non-Secure state +// Interrupt 273 <0=> Secure state <1=> Non-Secure state +// Interrupt 274 <0=> Secure state <1=> Non-Secure state +// Interrupt 275 <0=> Secure state <1=> Non-Secure state +// Interrupt 276 <0=> Secure state <1=> Non-Secure state +// Interrupt 277 <0=> Secure state <1=> Non-Secure state +// Interrupt 278 <0=> Secure state <1=> Non-Secure state +// Interrupt 279 <0=> Secure state <1=> Non-Secure state +// Interrupt 280 <0=> Secure state <1=> Non-Secure state +// Interrupt 281 <0=> Secure state <1=> Non-Secure state +// Interrupt 282 <0=> Secure state <1=> Non-Secure state +// Interrupt 283 <0=> Secure state <1=> Non-Secure state +// Interrupt 284 <0=> Secure state <1=> Non-Secure state +// Interrupt 285 <0=> Secure state <1=> Non-Secure state +// Interrupt 286 <0=> Secure state <1=> Non-Secure state +// Interrupt 287 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS8_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 9 (Interrupts 288..319) +*/ +#define NVIC_INIT_ITNS9 0 + +/* +// Interrupts 288..319 +// Interrupt 288 <0=> Secure state <1=> Non-Secure state +// Interrupt 289 <0=> Secure state <1=> Non-Secure state +// Interrupt 290 <0=> Secure state <1=> Non-Secure state +// Interrupt 291 <0=> Secure state <1=> Non-Secure state +// Interrupt 292 <0=> Secure state <1=> Non-Secure state +// Interrupt 293 <0=> Secure state <1=> Non-Secure state +// Interrupt 294 <0=> Secure state <1=> Non-Secure state +// Interrupt 295 <0=> Secure state <1=> Non-Secure state +// Interrupt 296 <0=> Secure state <1=> Non-Secure state +// Interrupt 297 <0=> Secure state <1=> Non-Secure state +// Interrupt 298 <0=> Secure state <1=> Non-Secure state +// Interrupt 299 <0=> Secure state <1=> Non-Secure state +// Interrupt 300 <0=> Secure state <1=> Non-Secure state +// Interrupt 301 <0=> Secure state <1=> Non-Secure state +// Interrupt 302 <0=> Secure state <1=> Non-Secure state +// Interrupt 303 <0=> Secure state <1=> Non-Secure state +// Interrupt 304 <0=> Secure state <1=> Non-Secure state +// Interrupt 305 <0=> Secure state <1=> Non-Secure state +// Interrupt 306 <0=> Secure state <1=> Non-Secure state +// Interrupt 307 <0=> Secure state <1=> Non-Secure state +// Interrupt 308 <0=> Secure state <1=> Non-Secure state +// Interrupt 309 <0=> Secure state <1=> Non-Secure state +// Interrupt 310 <0=> Secure state <1=> Non-Secure state +// Interrupt 311 <0=> Secure state <1=> Non-Secure state +// Interrupt 312 <0=> Secure state <1=> Non-Secure state +// Interrupt 313 <0=> Secure state <1=> Non-Secure state +// Interrupt 314 <0=> Secure state <1=> Non-Secure state +// Interrupt 315 <0=> Secure state <1=> Non-Secure state +// Interrupt 316 <0=> Secure state <1=> Non-Secure state +// Interrupt 317 <0=> Secure state <1=> Non-Secure state +// Interrupt 318 <0=> Secure state <1=> Non-Secure state +// Interrupt 319 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS9_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 10 (Interrupts 320..351) +*/ +#define NVIC_INIT_ITNS10 0 + +/* +// Interrupts 320..351 +// Interrupt 320 <0=> Secure state <1=> Non-Secure state +// Interrupt 321 <0=> Secure state <1=> Non-Secure state +// Interrupt 322 <0=> Secure state <1=> Non-Secure state +// Interrupt 323 <0=> Secure state <1=> Non-Secure state +// Interrupt 324 <0=> Secure state <1=> Non-Secure state +// Interrupt 325 <0=> Secure state <1=> Non-Secure state +// Interrupt 326 <0=> Secure state <1=> Non-Secure state +// Interrupt 327 <0=> Secure state <1=> Non-Secure state +// Interrupt 328 <0=> Secure state <1=> Non-Secure state +// Interrupt 329 <0=> Secure state <1=> Non-Secure state +// Interrupt 330 <0=> Secure state <1=> Non-Secure state +// Interrupt 331 <0=> Secure state <1=> Non-Secure state +// Interrupt 332 <0=> Secure state <1=> Non-Secure state +// Interrupt 333 <0=> Secure state <1=> Non-Secure state +// Interrupt 334 <0=> Secure state <1=> Non-Secure state +// Interrupt 335 <0=> Secure state <1=> Non-Secure state +// Interrupt 336 <0=> Secure state <1=> Non-Secure state +// Interrupt 337 <0=> Secure state <1=> Non-Secure state +// Interrupt 338 <0=> Secure state <1=> Non-Secure state +// Interrupt 339 <0=> Secure state <1=> Non-Secure state +// Interrupt 340 <0=> Secure state <1=> Non-Secure state +// Interrupt 341 <0=> Secure state <1=> Non-Secure state +// Interrupt 342 <0=> Secure state <1=> Non-Secure state +// Interrupt 343 <0=> Secure state <1=> Non-Secure state +// Interrupt 344 <0=> Secure state <1=> Non-Secure state +// Interrupt 345 <0=> Secure state <1=> Non-Secure state +// Interrupt 346 <0=> Secure state <1=> Non-Secure state +// Interrupt 347 <0=> Secure state <1=> Non-Secure state +// Interrupt 348 <0=> Secure state <1=> Non-Secure state +// Interrupt 349 <0=> Secure state <1=> Non-Secure state +// Interrupt 350 <0=> Secure state <1=> Non-Secure state +// Interrupt 351 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS10_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 11 (Interrupts 352..383) +*/ +#define NVIC_INIT_ITNS11 0 + +/* +// Interrupts 352..383 +// Interrupt 352 <0=> Secure state <1=> Non-Secure state +// Interrupt 353 <0=> Secure state <1=> Non-Secure state +// Interrupt 354 <0=> Secure state <1=> Non-Secure state +// Interrupt 355 <0=> Secure state <1=> Non-Secure state +// Interrupt 356 <0=> Secure state <1=> Non-Secure state +// Interrupt 357 <0=> Secure state <1=> Non-Secure state +// Interrupt 358 <0=> Secure state <1=> Non-Secure state +// Interrupt 359 <0=> Secure state <1=> Non-Secure state +// Interrupt 360 <0=> Secure state <1=> Non-Secure state +// Interrupt 361 <0=> Secure state <1=> Non-Secure state +// Interrupt 362 <0=> Secure state <1=> Non-Secure state +// Interrupt 363 <0=> Secure state <1=> Non-Secure state +// Interrupt 364 <0=> Secure state <1=> Non-Secure state +// Interrupt 365 <0=> Secure state <1=> Non-Secure state +// Interrupt 366 <0=> Secure state <1=> Non-Secure state +// Interrupt 367 <0=> Secure state <1=> Non-Secure state +// Interrupt 368 <0=> Secure state <1=> Non-Secure state +// Interrupt 369 <0=> Secure state <1=> Non-Secure state +// Interrupt 370 <0=> Secure state <1=> Non-Secure state +// Interrupt 371 <0=> Secure state <1=> Non-Secure state +// Interrupt 372 <0=> Secure state <1=> Non-Secure state +// Interrupt 373 <0=> Secure state <1=> Non-Secure state +// Interrupt 374 <0=> Secure state <1=> Non-Secure state +// Interrupt 375 <0=> Secure state <1=> Non-Secure state +// Interrupt 376 <0=> Secure state <1=> Non-Secure state +// Interrupt 377 <0=> Secure state <1=> Non-Secure state +// Interrupt 378 <0=> Secure state <1=> Non-Secure state +// Interrupt 379 <0=> Secure state <1=> Non-Secure state +// Interrupt 380 <0=> Secure state <1=> Non-Secure state +// Interrupt 381 <0=> Secure state <1=> Non-Secure state +// Interrupt 382 <0=> Secure state <1=> Non-Secure state +// Interrupt 383 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS11_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 12 (Interrupts 384..415) +*/ +#define NVIC_INIT_ITNS12 0 + +/* +// Interrupts 384..415 +// Interrupt 384 <0=> Secure state <1=> Non-Secure state +// Interrupt 385 <0=> Secure state <1=> Non-Secure state +// Interrupt 386 <0=> Secure state <1=> Non-Secure state +// Interrupt 387 <0=> Secure state <1=> Non-Secure state +// Interrupt 388 <0=> Secure state <1=> Non-Secure state +// Interrupt 389 <0=> Secure state <1=> Non-Secure state +// Interrupt 390 <0=> Secure state <1=> Non-Secure state +// Interrupt 391 <0=> Secure state <1=> Non-Secure state +// Interrupt 392 <0=> Secure state <1=> Non-Secure state +// Interrupt 393 <0=> Secure state <1=> Non-Secure state +// Interrupt 394 <0=> Secure state <1=> Non-Secure state +// Interrupt 395 <0=> Secure state <1=> Non-Secure state +// Interrupt 396 <0=> Secure state <1=> Non-Secure state +// Interrupt 397 <0=> Secure state <1=> Non-Secure state +// Interrupt 398 <0=> Secure state <1=> Non-Secure state +// Interrupt 399 <0=> Secure state <1=> Non-Secure state +// Interrupt 400 <0=> Secure state <1=> Non-Secure state +// Interrupt 401 <0=> Secure state <1=> Non-Secure state +// Interrupt 402 <0=> Secure state <1=> Non-Secure state +// Interrupt 403 <0=> Secure state <1=> Non-Secure state +// Interrupt 404 <0=> Secure state <1=> Non-Secure state +// Interrupt 405 <0=> Secure state <1=> Non-Secure state +// Interrupt 406 <0=> Secure state <1=> Non-Secure state +// Interrupt 407 <0=> Secure state <1=> Non-Secure state +// Interrupt 408 <0=> Secure state <1=> Non-Secure state +// Interrupt 409 <0=> Secure state <1=> Non-Secure state +// Interrupt 410 <0=> Secure state <1=> Non-Secure state +// Interrupt 411 <0=> Secure state <1=> Non-Secure state +// Interrupt 412 <0=> Secure state <1=> Non-Secure state +// Interrupt 413 <0=> Secure state <1=> Non-Secure state +// Interrupt 414 <0=> Secure state <1=> Non-Secure state +// Interrupt 415 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS12_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 13 (Interrupts 416..447) +*/ +#define NVIC_INIT_ITNS13 0 + +/* +// Interrupts 416..447 +// Interrupt 416 <0=> Secure state <1=> Non-Secure state +// Interrupt 417 <0=> Secure state <1=> Non-Secure state +// Interrupt 418 <0=> Secure state <1=> Non-Secure state +// Interrupt 419 <0=> Secure state <1=> Non-Secure state +// Interrupt 420 <0=> Secure state <1=> Non-Secure state +// Interrupt 421 <0=> Secure state <1=> Non-Secure state +// Interrupt 422 <0=> Secure state <1=> Non-Secure state +// Interrupt 423 <0=> Secure state <1=> Non-Secure state +// Interrupt 424 <0=> Secure state <1=> Non-Secure state +// Interrupt 425 <0=> Secure state <1=> Non-Secure state +// Interrupt 426 <0=> Secure state <1=> Non-Secure state +// Interrupt 427 <0=> Secure state <1=> Non-Secure state +// Interrupt 428 <0=> Secure state <1=> Non-Secure state +// Interrupt 429 <0=> Secure state <1=> Non-Secure state +// Interrupt 430 <0=> Secure state <1=> Non-Secure state +// Interrupt 431 <0=> Secure state <1=> Non-Secure state +// Interrupt 432 <0=> Secure state <1=> Non-Secure state +// Interrupt 433 <0=> Secure state <1=> Non-Secure state +// Interrupt 434 <0=> Secure state <1=> Non-Secure state +// Interrupt 435 <0=> Secure state <1=> Non-Secure state +// Interrupt 436 <0=> Secure state <1=> Non-Secure state +// Interrupt 437 <0=> Secure state <1=> Non-Secure state +// Interrupt 438 <0=> Secure state <1=> Non-Secure state +// Interrupt 439 <0=> Secure state <1=> Non-Secure state +// Interrupt 440 <0=> Secure state <1=> Non-Secure state +// Interrupt 441 <0=> Secure state <1=> Non-Secure state +// Interrupt 442 <0=> Secure state <1=> Non-Secure state +// Interrupt 443 <0=> Secure state <1=> Non-Secure state +// Interrupt 444 <0=> Secure state <1=> Non-Secure state +// Interrupt 445 <0=> Secure state <1=> Non-Secure state +// Interrupt 446 <0=> Secure state <1=> Non-Secure state +// Interrupt 447 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS13_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 14 (Interrupts 448..479) +*/ +#define NVIC_INIT_ITNS14 0 + +/* +// Interrupts 448..479 +// Interrupt 448 <0=> Secure state <1=> Non-Secure state +// Interrupt 449 <0=> Secure state <1=> Non-Secure state +// Interrupt 450 <0=> Secure state <1=> Non-Secure state +// Interrupt 451 <0=> Secure state <1=> Non-Secure state +// Interrupt 452 <0=> Secure state <1=> Non-Secure state +// Interrupt 453 <0=> Secure state <1=> Non-Secure state +// Interrupt 454 <0=> Secure state <1=> Non-Secure state +// Interrupt 455 <0=> Secure state <1=> Non-Secure state +// Interrupt 456 <0=> Secure state <1=> Non-Secure state +// Interrupt 457 <0=> Secure state <1=> Non-Secure state +// Interrupt 458 <0=> Secure state <1=> Non-Secure state +// Interrupt 459 <0=> Secure state <1=> Non-Secure state +// Interrupt 460 <0=> Secure state <1=> Non-Secure state +// Interrupt 461 <0=> Secure state <1=> Non-Secure state +// Interrupt 462 <0=> Secure state <1=> Non-Secure state +// Interrupt 463 <0=> Secure state <1=> Non-Secure state +// Interrupt 464 <0=> Secure state <1=> Non-Secure state +// Interrupt 465 <0=> Secure state <1=> Non-Secure state +// Interrupt 466 <0=> Secure state <1=> Non-Secure state +// Interrupt 467 <0=> Secure state <1=> Non-Secure state +// Interrupt 468 <0=> Secure state <1=> Non-Secure state +// Interrupt 469 <0=> Secure state <1=> Non-Secure state +// Interrupt 470 <0=> Secure state <1=> Non-Secure state +// Interrupt 471 <0=> Secure state <1=> Non-Secure state +// Interrupt 472 <0=> Secure state <1=> Non-Secure state +// Interrupt 473 <0=> Secure state <1=> Non-Secure state +// Interrupt 474 <0=> Secure state <1=> Non-Secure state +// Interrupt 475 <0=> Secure state <1=> Non-Secure state +// Interrupt 476 <0=> Secure state <1=> Non-Secure state +// Interrupt 477 <0=> Secure state <1=> Non-Secure state +// Interrupt 478 <0=> Secure state <1=> Non-Secure state +// Interrupt 479 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS14_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 15 (Interrupts 480..511) +*/ +#define NVIC_INIT_ITNS15 0 + +/* +// Interrupts 480..511 +// Interrupt 480 <0=> Secure state <1=> Non-Secure state +// Interrupt 481 <0=> Secure state <1=> Non-Secure state +// Interrupt 482 <0=> Secure state <1=> Non-Secure state +// Interrupt 483 <0=> Secure state <1=> Non-Secure state +// Interrupt 484 <0=> Secure state <1=> Non-Secure state +// Interrupt 485 <0=> Secure state <1=> Non-Secure state +// Interrupt 486 <0=> Secure state <1=> Non-Secure state +// Interrupt 487 <0=> Secure state <1=> Non-Secure state +// Interrupt 488 <0=> Secure state <1=> Non-Secure state +// Interrupt 489 <0=> Secure state <1=> Non-Secure state +// Interrupt 490 <0=> Secure state <1=> Non-Secure state +// Interrupt 491 <0=> Secure state <1=> Non-Secure state +// Interrupt 492 <0=> Secure state <1=> Non-Secure state +// Interrupt 493 <0=> Secure state <1=> Non-Secure state +// Interrupt 494 <0=> Secure state <1=> Non-Secure state +// Interrupt 495 <0=> Secure state <1=> Non-Secure state +// Interrupt 496 <0=> Secure state <1=> Non-Secure state +// Interrupt 497 <0=> Secure state <1=> Non-Secure state +// Interrupt 498 <0=> Secure state <1=> Non-Secure state +// Interrupt 499 <0=> Secure state <1=> Non-Secure state +// Interrupt 500 <0=> Secure state <1=> Non-Secure state +// Interrupt 501 <0=> Secure state <1=> Non-Secure state +// Interrupt 502 <0=> Secure state <1=> Non-Secure state +// Interrupt 503 <0=> Secure state <1=> Non-Secure state +// Interrupt 504 <0=> Secure state <1=> Non-Secure state +// Interrupt 505 <0=> Secure state <1=> Non-Secure state +// Interrupt 506 <0=> Secure state <1=> Non-Secure state +// Interrupt 507 <0=> Secure state <1=> Non-Secure state +// Interrupt 508 <0=> Secure state <1=> Non-Secure state +// Interrupt 509 <0=> Secure state <1=> Non-Secure state +// Interrupt 510 <0=> Secure state <1=> Non-Secure state +// Interrupt 511 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS15_VAL 0x00000000 + +/* +// +*/ + +/* +// +*/ + + + +/* + max 128 SAU regions. + SAU regions are defined in partition.h + */ + +#define SAU_INIT_REGION(n) \ + SAU->RNR = (n & SAU_RNR_REGION_Msk); \ + SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ + SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ + ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U + +/** + \brief Setup a SAU Region + \details Writes the region information contained in SAU_Region to the + registers SAU_RNR, SAU_RBAR, and SAU_RLAR + */ +__STATIC_INLINE void TZ_SAU_Setup (void) +{ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + + #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) + SAU_INIT_REGION(0); + #endif + + #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) + SAU_INIT_REGION(1); + #endif + + #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) + SAU_INIT_REGION(2); + #endif + + #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) + SAU_INIT_REGION(3); + #endif + + #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) + SAU_INIT_REGION(4); + #endif + + #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) + SAU_INIT_REGION(5); + #endif + + #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) + SAU_INIT_REGION(6); + #endif + + #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) + SAU_INIT_REGION(7); + #endif + + /* repeat this for all possible SAU regions */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + + + #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) + SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | + ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; + #endif + + #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) + SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | + ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); + + SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | + SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk )) | + ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | + ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | + ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | + ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); + #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ + + #if (((defined (__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0))) && \ + (defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U))) + + SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | + ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); + + FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | + ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | + ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | + ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); + #endif + + #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) + NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; + #endif + + #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) + NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; + #endif + + #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) + NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; + #endif + + #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) + NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; + #endif + + #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) + NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; + #endif + + #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U) + NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL; + #endif + + #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U) + NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL; + #endif + + #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U) + NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL; + #endif + + #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U) + NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL; + #endif + + #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U) + NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL; + #endif + + #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U) + NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL; + #endif + + #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U) + NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL; + #endif + + #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U) + NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL; + #endif + + #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U) + NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL; + #endif + + #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U) + NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL; + #endif + + #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U) + NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL; + #endif + + /* repeat this for all possible ITNS elements */ + +} + +#endif // IS_SECURE_EVIRONMENT + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_SOURCE_PARTITION_MAX32657_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/max32657.ld b/Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/max32657.ld index 695e2f01d09..7a02a14948e 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/max32657.ld +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/max32657.ld @@ -1,8 +1,6 @@ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by - * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. + * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -19,23 +17,30 @@ ******************************************************************************/ MEMORY { - ROM (rx) : ORIGIN = 0x00000000, LENGTH = 0x00010000 /* 64kB ROM */ - FLASH (rx) : ORIGIN = 0x10000000, LENGTH = 0x00080000 /* 512KB Flash */ - SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00020000 /* 128kB SRAM */ + ROM_S (rx) : ORIGIN = 0x00000000, LENGTH = 0x00010000 /* 64kB secure ROM (ROM always secure) */ + FLASH (rx) : ORIGIN = DEFINED(SECURE_LINK) ? 0x11000000 : 0x01000000, LENGTH = 0x00100000 /* 1MB Flash */ + FLASH_INFO_S (rx) : ORIGIN = 0x12000000, LENGTH = 0x00010000 /* 16KB secure Flash Info */ + SRAM (rwx) : ORIGIN = DEFINED(SECURE_LINK) ? 0x30000000 : 0x20000000, LENGTH = 0x00040000 /* 256KB SRAM */ } +/* Note(JC): "SECURE_LINK" is a symbol defined at link-time by Libraries/CMSIS/Device/Maxim/GCC/gcc.mk + * It's only defined for when building secure binaries (which is the default). + * When it's defined, the FLASH and SRAM memory addresses will use the secure ranges. Otherwise, the + * non-secure ranges will be used. This mechanism allows secure and non-secure binaries to be linked + * without having to maintain a separate copy of the linkerfile. + */ SECTIONS { .rom : { KEEP(*(.rom_vector)) *(.rom_handlers*) - } > ROM + } > ROM_S .text : { _text = .; KEEP(*(.isr_vector)) - EXCLUDE_FILE (*riscv.o) *(.text*) /* Program code (exclude RISCV code) */ + *(.text*) /* Program code */ *(.rodata*) /* read-only data: "const" */ KEEP(*(.init)) @@ -60,19 +65,21 @@ SECTIONS { _etext = .; } > FLASH - .ARM.extab : + + /* + * Secure Gatway (SG) veneers. + * All SG veneers are placed in the special output section .gnu.sgstubs. + */ + .gnu.sgstubs : { - *(.ARM.extab* .gnu.linkonce.armextab.*) + _sg_veneers = .; + *(.gnu.sgstubs*) + _esg_veneers = .; } > FLASH - /* Binary import */ - .bin_storage : + .ARM.extab : { - FILL(0xFF) - _bin_start_ = .; - KEEP(*(.bin_storage_img)) - _bin_end_ = .; - . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) } > FLASH .rom_code : @@ -81,7 +88,7 @@ SECTIONS { _sran_code = .; *(.rom_code_section) _esran_code = .; - } > ROM + } > ROM_S .flash_code : { @@ -145,32 +152,37 @@ SECTIONS { . = ALIGN(4); _bss = .; *(.bss*) /*read-write zero initialized data: uninitialzed global variable*/ - *(COMMON) _ebss = ALIGN(., 4); } > SRAM - .shared : + /** + * Stack Seal section is required for secure builds. Stack sealing protects + * secure stack from illegal access by non-secure code. + */ + .stackseal (COPY): { - . = ALIGN(4); - _shared = .; - *(.mailbox*) - . = ALIGN(4); - *(.shared*) /*read-write zero initialized data: uninitialzed global variable*/ - _eshared = ALIGN(., 4); - } > SRAM AT>FLASH - __shared_data = LOADADDR(.shared); + . = ALIGN(8); + __StackSeal = .; + . = . + 8; + . = ALIGN(8); + } > SRAM - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ + /** + * Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section. + */ __StackTop = ORIGIN(SRAM) + LENGTH(SRAM); __StackLimit = __StackTop - SIZEOF(.stack_dummy); - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ + /** + * .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later. + */ .stack_dummy (COPY): { - *(.stack*) + KEEP(*(.stack*)) + *(.stackseal*) } > SRAM .heap (COPY): @@ -184,14 +196,4 @@ SECTIONS { /* Check if data + heap + stack exceeds RAM limit */ ASSERT(__StackLimit >= _ebss, "region RAM overflowed with stack") - - /* Section used by RISCV loader projects. See RISCV_LOAD documentation in the build system. */ - .riscv_flash : - { - /* Align address to mod 256 with a small offset. This is required to match the flash page size.*/ - . = ALIGN(256); /* ALIGN operatator is used here. Note that (. & 0x1FFFFF00) was used in the past, but a strange bug was seen on Windows where the & did not behave as expected.*/ - . += 0x100; - _riscv_boot = .; - KEEP(*riscv.o (.text*)) - } > FLASH } diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/startup_max32657.S b/Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/startup_max32657.S index 4bad29772e9..2a4348f73c2 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/startup_max32657.S +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/startup_max32657.S @@ -19,31 +19,36 @@ ******************************************************************************/ .syntax unified - .arch armv8-m + .arch armv8-m.main .section .stack .align 3 #ifdef __STACK_SIZE - .equ Stack_Size, __STACK_SIZE + .equ Stack_Size, __STACK_SIZE #else - // TODO: Update max stack size - .equ Stack_Size, 0x00001000 + // Default stack size (192KB) + .equ Stack_Size, 0x00030000 #endif .globl __StackTop .globl __StackLimit +#if IS_SECURE_ENVIRONMENT + // __StackSeal defined in linker script + .equ __STACK_SEAL, __StackSeal + .globl __StackSeal +#endif __StackLimit: .space Stack_Size - .size __StackLimit, . - __StackLimit + .size __StackLimit, . - __StackLimit __StackTop: - .size __StackTop, . - __StackTop + .size __StackTop, . - __StackTop .section .heap .align 3 #ifdef __HEAP_SIZE - .equ Heap_Size, __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE #else - // TODO: Update max heap size - .equ Heap_Size, 0x00000C00 + // Default heap size (64KB) + .equ Heap_Size, 0x00010000 #endif .globl __HeapBase .globl __HeapLimit @@ -60,26 +65,84 @@ __HeapLimit: .align 9 /* must be aligned to 512 byte boundary. VTOR requirement */ .globl __isr_vector __isr_vector: - .long __StackTop /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* NMI Handler */ - .long HardFault_Handler /* Hard Fault Handler */ - .long MemManage_Handler /* MPU Fault Handler */ - .long BusFault_Handler /* Bus Fault Handler */ - .long UsageFault_Handler /* Usage Fault Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long SVC_Handler /* SVCall Handler */ - .long DebugMon_Handler /* Debug Monitor Handler */ - .long 0 /* Reserved */ - .long PendSV_Handler /* PendSV Handler */ - .long SysTick_Handler /* SysTick Handler */ - - // TODO: Add device-specific interrupt table - /* Device-specific Interrupts */ - .long RSVXX_IRQHandler /* 0xXX 0xXXXX XX: Reserved */ + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* Device-specific Interrupts */ + /* CMSIS Interrupt Number */ + /* |||| || */ + /* |||| Offset || */ + /* vvvv vvvvvv vv */ + + .long ICE_IRQHandler /* 0x10 0x0040 16: ICE Unlock */ + .long WDT_IRQHandler /* 0x11 0x0044 17: Watchdog Timer */ + .long RTC_IRQHandler /* 0x12 0x0048 18: RTC */ + .long TRNG_IRQHandler /* 0x13 0x004C 19: True Random Number Generator */ + .long TMR0_IRQHandler /* 0x14 0x0050 20: Timer 0 */ + .long TMR1_IRQHandler /* 0x15 0x0054 21: Timer 1 */ + .long TMR2_IRQHandler /* 0x16 0x0058 22: Timer 2 */ + .long TMR3_IRQHandler /* 0x17 0x005C 23: Timer 3 */ + .long TMR4_IRQHandler /* 0x18 0x0060 24: Timer 4 */ + .long TMR5_IRQHandler /* 0x19 0x0064 25: Timer 5 */ + .long I3C_IRQHandler /* 0x1A 0x0068 26: I3C */ + .long UART_IRQHandler /* 0x1B 0x006C 27: UART */ + .long SPI_IRQHandler /* 0x1C 0x0070 28: SPI */ + .long FLC_IRQHandler /* 0x1D 0x0074 29: FLC */ + .long GPIO0_IRQHandler /* 0x1E 0x0078 30: GPIO0 */ + .long RSV15_IRQHandler /* 0x1F 0x007C 31: Reserved */ + .long DMA0_CH0_IRQHandler /* 0x20 0x0080 32: DMA0 Channel 0 */ + .long DMA0_CH1_IRQHandler /* 0x21 0x0084 33: DMA0 Channel 1 */ + .long DMA0_CH2_IRQHandler /* 0x22 0x0088 34: DMA0 Channel 2 */ + .long DMA0_CH3_IRQHandler /* 0x23 0x008C 35: DMA0 Channel 3 */ + .long DMA1_CH0_IRQHandler /* 0x24 0x0090 36: DMA1 Channel 0 */ + .long DMA1_CH1_IRQHandler /* 0x25 0x0094 37: DMA1 Channel 1 */ + .long DMA1_CH2_IRQHandler /* 0x26 0x0098 38: DMA1 Channel 2 */ + .long DMA1_CH3_IRQHandler /* 0x27 0x009C 39: DMA1 Channel 3 */ + .long WUT0_IRQHandler /* 0x28 0x00A0 40: Wakeup Timer 0 */ + .long WUT1_IRQHandler /* 0x29 0x00A4 41: Wakeup Timer 1 */ + .long GPIOWAKE_IRQHandler /* 0x2A 0x00A8 42: GPIO Wakeup */ + .long CRC_IRQHandler /* 0x2B 0x00AC 43: CRC */ + .long AES_IRQHandler /* 0x2C 0x00B0 44: AES */ + .long ERFO_IRQHandler /* 0x2D 0x00B4 45: ERFO Ready */ + .long BOOST_IRQHandler /* 0x2E 0x00B8 46: Boost Controller */ + .long ECC_IRQHandler /* 0x2F 0x00BC 47: ECC */ +/* TODO(Bluetooth): Confirm BTLE IRQ Handler Names */ + .long BTLE_XXXX0_IRQHandler /* 0x30 0x00C0 48: BTLE XXXX0 */ + .long BTLE_XXXX1_IRQHandler /* 0x31 0x00C4 49: BTLE XXXX1 */ + .long BTLE_XXXX2_IRQHandler /* 0x32 0x00C8 50: BTLE XXXX2 */ + .long BTLE_XXXX3_IRQHandler /* 0x33 0x00CC 51: BTLE XXXX3 */ + .long BTLE_XXXX4_IRQHandler /* 0x34 0x00D0 52: BTLE XXXX4 */ + .long BTLE_XXXX5_IRQHandler /* 0x35 0x00D4 53: BTLE XXXX5 */ + .long BTLE_XXXX6_IRQHandler /* 0x36 0x00D8 54: BTLE XXXX6 */ + .long BTLE_XXXX7_IRQHandler /* 0x37 0x00DC 55: BTLE XXXX7 */ + .long BTLE_XXXX8_IRQHandler /* 0x38 0x00E0 56: BTLE XXXX8 */ + .long BTLE_XXXX9_IRQHandler /* 0x39 0x00E4 57: BTLE XXXX9 */ + .long BTLE_XXXXA_IRQHandler /* 0x3A 0x00E8 58: BTLE XXXXA */ + .long BTLE_XXXXB_IRQHandler /* 0x3B 0x00EC 59: BTLE XXXXB */ + .long BTLE_XXXXC_IRQHandler /* 0x3C 0x00F0 60: BTLE XXXXC */ + .long BTLE_XXXXD_IRQHandler /* 0x3D 0x00F4 61: BTLE XXXXD */ + .long BTLE_XXXXE_IRQHandler /* 0x3E 0x00F8 62: BTLE XXXXE */ + .long RSV47_IRQHandler /* 0x3F 0x00FC 63: Reserved */ + .long MPC_IRQHandler /* 0x40 0x0100 64: MPC Combined (Secure) */ + .long PPC_IRQHandler /* 0x44 0x0104 65: PPC Combined (Secure) */ + .long RSV50_IRQHandler /* 0x48 0x0108 66: Reserved */ + .long RSV51_IRQHandler /* 0x49 0x010C 67: Reserved */ + .long RSV52_IRQHandler /* 0x4A 0x0110 68: Reserved */ + .long RSV53_IRQHandler /* 0x4B 0x0114 69: Reserved */ .text .thumb @@ -91,6 +154,19 @@ Reset_Handler: ldr r0, =__StackTop mov sp, r0 +#if IS_SECURE_ENVIRONMENT + /* Set limit on Main and Process SP */ + ldr r0, =__STACK_LIMIT + msr msplim, r0 + msr psplim, r0 + + /* Set up Stack Sealing - using predefined stack seal value */ + ldr r0, =__STACK_SEAL + ldr r1, =0xFEF5EDA5U + /* Store seal value twice as a double word for redundancy */ + strd r1, r1, [r0, #0] +#endif + /* PreInit runs before any RAM initialization. Example usage: DDR setup, etc. */ ldr r0, =PreInit blx r0 @@ -177,7 +253,6 @@ Reset_Handler: .size \handler_name, . - \handler_name .endm - // TODO: Update to match arch-specific handlers above def_irq_handler NMI_Handler def_irq_handler HardFault_Handler def_irq_handler MemManage_Handler @@ -189,7 +264,65 @@ Reset_Handler: def_irq_handler SysTick_Handler def_irq_handler Default_Handler - // TODO: Add default device-specific handlers to match above - /* Device-specific Interrupts */ - def_irq_handler RSVXX_IRQHandler /* 0xXX 0xXXXX XX: Reserved */ + /* Device-specific Interrupts */ + /* CMSIS Interrupt Number */ + /* |||| || */ + /* |||| Offset || */ + /* vvvv vvvvvv vv */ + + def_irq_handler ICE_IRQHandler /* 0x10 0x0040 16: ICE Unlock */ + def_irq_handler WDT_IRQHandler /* 0x11 0x0044 17: Watchdog Timer */ + def_irq_handler RTC_IRQHandler /* 0x12 0x0048 18: RTC */ + def_irq_handler TRNG_IRQHandler /* 0x13 0x004C 19: True Random Number Generator */ + def_irq_handler TMR0_IRQHandler /* 0x14 0x0050 20: Timer 0 */ + def_irq_handler TMR1_IRQHandler /* 0x15 0x0054 21: Timer 1 */ + def_irq_handler TMR2_IRQHandler /* 0x16 0x0058 22: Timer 2 */ + def_irq_handler TMR3_IRQHandler /* 0x17 0x005C 23: Timer 3 */ + def_irq_handler TMR4_IRQHandler /* 0x18 0x0060 24: Timer 4 */ + def_irq_handler TMR5_IRQHandler /* 0x19 0x0064 25: Timer 5 */ + def_irq_handler I3C_IRQHandler /* 0x1A 0x0068 26: I3C */ + def_irq_handler UART_IRQHandler /* 0x1B 0x006C 27: UART */ + def_irq_handler SPI_IRQHandler /* 0x1C 0x0070 28: SPI */ + def_irq_handler FLC_IRQHandler /* 0x1D 0x0074 29: FLC */ + def_irq_handler GPIO0_IRQHandler /* 0x1E 0x0078 30: GPIO0 */ + def_irq_handler RSV15_IRQHandler /* 0x1F 0x007C 31: Reserved */ + def_irq_handler DMA0_CH0_IRQHandler /* 0x20 0x0080 32: DMA0 Channel 0 */ + def_irq_handler DMA0_CH1_IRQHandler /* 0x21 0x0084 33: DMA0 Channel 1 */ + def_irq_handler DMA0_CH2_IRQHandler /* 0x22 0x0088 34: DMA0 Channel 2 */ + def_irq_handler DMA0_CH3_IRQHandler /* 0x23 0x008C 35: DMA0 Channel 3 */ + def_irq_handler DMA1_CH0_IRQHandler /* 0x24 0x0090 36: DMA1 Channel 0 */ + def_irq_handler DMA1_CH1_IRQHandler /* 0x25 0x0094 37: DMA1 Channel 1 */ + def_irq_handler DMA1_CH2_IRQHandler /* 0x26 0x0098 38: DMA1 Channel 2 */ + def_irq_handler DMA1_CH3_IRQHandler /* 0x27 0x009C 39: DMA1 Channel 3 */ + def_irq_handler WUT0_IRQHandler /* 0x28 0x00A0 40: Wakeup Timer 0 */ + def_irq_handler WUT1_IRQHandler /* 0x29 0x00A4 41: Wakeup Timer 1 */ + def_irq_handler GPIOWAKE_IRQHandler /* 0x2A 0x00A8 42: GPIO Wakeup */ + def_irq_handler CRC_IRQHandler /* 0x2B 0x00AC 43: CRC */ + def_irq_handler AES_IRQHandler /* 0x2C 0x00B0 44: AES */ + def_irq_handler ERFO_IRQHandler /* 0x2D 0x00B4 45: ERFO Ready */ + def_irq_handler BOOST_IRQHandler /* 0x2E 0x00B8 46: Boost Controller */ + def_irq_handler ECC_IRQHandler /* 0x2F 0x00BC 47: ECC */ +/* TODO(Bluetooth): Confirm BTLE IRQ Handler Names */ + def_irq_handler BTLE_XXXX0_IRQHandler /* 0x30 0x00C0 48: BTLE XXXX0 */ + def_irq_handler BTLE_XXXX1_IRQHandler /* 0x31 0x00C4 49: BTLE XXXX1 */ + def_irq_handler BTLE_XXXX2_IRQHandler /* 0x32 0x00C8 50: BTLE XXXX2 */ + def_irq_handler BTLE_XXXX3_IRQHandler /* 0x33 0x00CC 51: BTLE XXXX3 */ + def_irq_handler BTLE_XXXX4_IRQHandler /* 0x34 0x00D0 52: BTLE XXXX4 */ + def_irq_handler BTLE_XXXX5_IRQHandler /* 0x35 0x00D4 53: BTLE XXXX5 */ + def_irq_handler BTLE_XXXX6_IRQHandler /* 0x36 0x00D8 54: BTLE XXXX6 */ + def_irq_handler BTLE_XXXX7_IRQHandler /* 0x37 0x00DC 55: BTLE XXXX7 */ + def_irq_handler BTLE_XXXX8_IRQHandler /* 0x38 0x00E0 56: BTLE XXXX8 */ + def_irq_handler BTLE_XXXX9_IRQHandler /* 0x39 0x00E4 57: BTLE XXXX9 */ + def_irq_handler BTLE_XXXXA_IRQHandler /* 0x3A 0x00E8 58: BTLE XXXXA */ + def_irq_handler BTLE_XXXXB_IRQHandler /* 0x3B 0x00EC 59: BTLE XXXXB */ + def_irq_handler BTLE_XXXXC_IRQHandler /* 0x3C 0x00F0 60: BTLE XXXXC */ + def_irq_handler BTLE_XXXXD_IRQHandler /* 0x3D 0x00F4 61: BTLE XXXXD */ + def_irq_handler BTLE_XXXXE_IRQHandler /* 0x3E 0x00F8 62: BTLE XXXXE */ + def_irq_handler RSV47_IRQHandler /* 0x3F 0x00FC 63: Reserved */ + def_irq_handler MPC_IRQHandler /* 0x40 0x0100 64: MPC Combined (Secure) */ + def_irq_handler PPC_IRQHandler /* 0x44 0x0104 65: PPC Combined (Secure) */ + def_irq_handler RSV50_IRQHandler /* 0x48 0x0108 66: Reserved */ + def_irq_handler RSV51_IRQHandler /* 0x49 0x010C 67: Reserved */ + def_irq_handler RSV52_IRQHandler /* 0x4A 0x0110 68: Reserved */ + def_irq_handler RSV53_IRQHandler /* 0x4B 0x0114 69: Reserved */ .end diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Source/system_max32657.c b/Libraries/CMSIS/Device/Maxim/MAX32657/Source/system_max32657.c index 5b3c0874344..417f887b2ab 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Source/system_max32657.c +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Source/system_max32657.c @@ -16,4 +16,155 @@ * ******************************************************************************/ -// TODO(ME30): System implementation +#include +#include +#include +#include +#include "mxc_sys.h" +#include "max32657.h" +#include "system_max32657.h" +#include "partition_max32657.h" +#include "gcr_regs.h" + +extern void (*const __isr_vector[])(void); + +uint32_t SystemCoreClock = IPO_FREQ; // Part defaults to IPO on startup + +/* + The libc implementation from GCC 11+ depends on _getpid and _kill in some places. + There is no concept of processes/PIDs in the baremetal PeriphDrivers, therefore + we implement stub functions that return an error code to resolve linker warnings. +*/ +int _getpid(void) +{ + return E_NOT_SUPPORTED; +} + +int _kill(void) +{ + return E_NOT_SUPPORTED; +} + +__weak void SystemCoreClockUpdate(void) +{ + uint32_t base_freq, div, clk_src; + + // Get the clock source and frequency + clk_src = (MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_SYSCLK_SEL); + switch (clk_src) { + case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IPO: + base_freq = IPO_FREQ; + break; + case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERFO: + base_freq = ERFO_FREQ; + break; + case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_INRO: + base_freq = INRO_FREQ; + break; + case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IBRO: + base_freq = IBRO_FREQ; + break; + case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERTCO: + base_freq = ERTCO_FREQ; + break; + // case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK: + // base_freq = EXTCLK_FREQ; + // break; + // TODO(JC): ^^^ Uncomment when EXTCLK register definition is added + default: + // Codes 001 and 111 are reserved. + // This code should never execute, however, initialize to safe value. + base_freq = HIRC_FREQ; + break; + } + + // Get the clock divider + div = (MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_SYSCLK_DIV) >> MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS; + + SystemCoreClock = base_freq >> div; +} + +/* This function is called before C runtime initialization and can be + * implemented by the application for early initializations. If a value other + * than '0' is returned, the C runtime initialization will be skipped. + * + * You may over-ride this function in your program by defining a custom + * PreInit(), but care should be taken to reproduce the initialization steps + * or a non-functional system may result. + */ +__weak int PreInit(void) +{ + /* Do nothing */ + // TODO(JC): No SIMO on this device, confirm nothing needs to be done here. + // (SW): Correct, different power HW. + return 0; +} + +/* This function is called before the Board_Init function. This weak + * implementation does nothing, but you may over-ride this function in your + * program if you want to configure the state of all pins prior to the + * application running. This is useful when using external tools (like a + * Pin Mux configuration tool) that generate code to initialize the pins. + */ +__weak void PinInit(void) +{ + /* Do nothing */ +} + +/* This function can be implemented by the application to initialize the board */ +__weak int Board_Init(void) +{ + /* Do nothing */ + return 0; +} + +/* This function is called just before control is transferred to main(). + * + * You may over-ride this function in your program by defining a custom + * SystemInit(), but care should be taken to reproduce the initialization + * steps or a non-functional system may result. + */ +__weak void SystemInit(void) +{ +#if defined(__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t)__isr_vector; +#endif /* __VTOR_PRESENT check */ + +#if (__FPU_PRESENT == 1U) + /* Enable FPU - coprocessor slots 10 & 11 full access */ + SCB->CPACR |= SCB_CPACR_CP10_Msk | SCB_CPACR_CP11_Msk; +#endif /* __FPU_PRESENT check */ + + /* + Enable Unaligned Access Trapping to throw an exception when there is an + unaligned memory access while unaligned access support is disabled. + + Note: ARMv8-M without the Main Extension disables unaligned access by default. + */ +#if defined(UNALIGNED_SUPPORT_DISABLE) || defined(__ARM_FEATURE_UNALIGNED) + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + /* Security Extension Features */ +#if IS_SECURE_ENVIRONMENT + /* Settings for TrustZone SAU setup are defined in partitions_max32657.h */ + TZ_SAU_Setup(); +#endif /* TrustZone */ + + __DSB(); + __ISB(); + + /* Enable interrupts */ + __enable_irq(); + + // TODO(ICC): Enable the internal cache controller after testing. + // MXC_ICC_Enable(); + + /* Change system clock source to the main high-speed clock */ + MXC_SYS_Clock_Select(MXC_SYS_CLOCK_IPO); + MXC_SYS_SetClockDiv(MXC_SYS_CLOCK_DIV_1); + SystemCoreClockUpdate(); + + PinInit(); + Board_Init(); +} diff --git a/Libraries/PeriphDrivers/Include/MAX32657/aes.h b/Libraries/PeriphDrivers/Include/MAX32657/aes.h index 7f51f371c1b..806df3abbbc 100644 --- a/Libraries/PeriphDrivers/Include/MAX32657/aes.h +++ b/Libraries/PeriphDrivers/Include/MAX32657/aes.h @@ -27,6 +27,7 @@ /***** Includes *****/ #include "aes_regs.h" #include "aeskeys_regs.h" +#include "dma_regs.h" #ifdef __cplusplus extern "C" { @@ -89,9 +90,10 @@ typedef struct _mxc_aes_cipher_req_t { /** * @brief Enable portions of the AES * + * @param dma DMA instance used for AES * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_AES_Init(void); +int MXC_AES_Init(mxc_dma_regs_t *dma); /** * @brief Enable AES Interrupts @@ -213,18 +215,20 @@ int MXC_AES_Decrypt(mxc_aes_req_t *req); * * @param src_addr source address * @param len number of words of data + * @param dma DMA instance to configue for AES * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_AES_TXDMAConfig(void *src_addr, int len); +int MXC_AES_TXDMAConfig(void *src_addr, int len, mxc_dma_regs_t *dma); /** * @brief Perform AES RX using DMA. Configures DMA request and receives data from AES FIFO. * * @param dest_addr destination address * @param len number of words of data + * @param dma DMA instance to configure for AES * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_AES_RXDMAConfig(void *dest_addr, int len); +int MXC_AES_RXDMAConfig(void *dest_addr, int len, mxc_dma_regs_t *dma); /** * @brief Perform encryption or decryption using DMA diff --git a/Libraries/PeriphDrivers/Include/MAX32657/crc.h b/Libraries/PeriphDrivers/Include/MAX32657/crc.h index 35218bf1f23..f80ed216122 100644 --- a/Libraries/PeriphDrivers/Include/MAX32657/crc.h +++ b/Libraries/PeriphDrivers/Include/MAX32657/crc.h @@ -26,6 +26,7 @@ /***** Includes *****/ #include "crc_regs.h" +#include "dma_regs.h" #ifdef __cplusplus extern "C" { @@ -63,10 +64,10 @@ typedef enum { CRC_LSB_FIRST, CRC_MSB_FIRST } mxc_crc_bitorder_t; /** * @brief Enable portions of the CRC * - * + * @param dma DMA Instance used for CRC calculation * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_CRC_Init(void); +int MXC_CRC_Init(mxc_dma_regs_t *dma); /** * @brief Disable and reset portions of the CRC diff --git a/Libraries/PeriphDrivers/Include/MAX32657/dma.h b/Libraries/PeriphDrivers/Include/MAX32657/dma.h index 747e5702681..44fd184aeb7 100644 --- a/Libraries/PeriphDrivers/Include/MAX32657/dma.h +++ b/Libraries/PeriphDrivers/Include/MAX32657/dma.h @@ -53,6 +53,7 @@ typedef enum { } mxc_dma_priority_t; /** @brief DMA request select */ +// TODO(ME30): Updated DMA reqsel typedef enum { MXC_DMA_REQUEST_MEMTOMEM = MXC_S_DMA_CTRL_REQUEST_MEMTOMEM, ///< Memory to Memory DMA Request Selection @@ -192,25 +193,30 @@ typedef mxc_dma_srcdst_t (*mxc_dma_trans_chain_t)(mxc_dma_srcdst_t dest); * if you wish to manage clock and gpio related things in upper level instead of here. * Define MSDK_NO_GPIO_CLK_INIT flag in project.mk file. * By this flag this function will remove clock and gpio related codes from file. + * @param dma Pointer to selected DMA instance's registers. + * * @return #E_NO_ERROR if successful */ -int MXC_DMA_Init(void); +int MXC_DMA_Init(mxc_dma_regs_t *dma); /** * @brief De-Initialize DMA resources. + * + * @param dma Pointer to selected DMA instance's registers. */ -void MXC_DMA_DeInit(void); +void MXC_DMA_DeInit(mxc_dma_regs_t *dma); /** * @brief Request DMA channel * @details Returns a handle to the first free DMA channel, which can be used via API calls * or direct access to channel registers using the MXC_DMA_GetCHRegs(int ch) function. + * @param dma Pointer to selected DMA instance's registers. * @return Non-negative channel handle (inclusive of zero). * @return #E_NONE_AVAIL All channels in use. * @return #E_BAD_STATE DMA is not initialized, call MXC_DMA_Init() first. * @return #E_BUSY DMA is currently busy (locked), try again later. */ -int MXC_DMA_AcquireChannel(void); +int MXC_DMA_AcquireChannel(mxc_dma_regs_t *dma); /** * @brief Release DMA channel @@ -359,19 +365,21 @@ int MXC_DMA_ChannelClearFlags(int ch, int flags); * @brief Enable channel interrupt * @note Each channel has two interrupts (complete, and count to zero) which must also be enabled with MXC_DMA_SetChannelInterruptEn() + * @param dma DMA instance used for the DMA channel registers. * @param ch DMA channel to enable interrupts for. * @return #E_BAD_PARAM if an unused or invalid channel handle, * #E_NO_ERROR otherwise, \ref MXC_Error_Codes */ -int MXC_DMA_EnableInt(int ch); +int MXC_DMA_EnableInt(mxc_dma_regs_t *dma, int ch); /** * @brief Disable channel interrupt + * @param dma DMA instance used for the DMA channel registers. * @param ch DMA channel to disable interrupts for. * @return #E_BAD_PARAM if an unused or invalid channel handle, * #E_NO_ERROR otherwise, \ref MXC_Error_Codes */ -int MXC_DMA_DisableInt(int ch); +int MXC_DMA_DisableInt(mxc_dma_regs_t *dma, int ch); /** * @brief Start transfer @@ -401,10 +409,11 @@ mxc_dma_ch_regs_t *MXC_DMA_GetCHRegs(int ch); /** * @brief Interrupt handler function + * @param dma Pointer to DMA registers. * @details Call this function as the ISR for each DMA channel under driver control. * Interrupt flags for channel ch will be automatically cleared before return. */ -void MXC_DMA_Handler(void); +void MXC_DMA_Handler(mxc_dma_regs_t *dma); /*************************/ /* High Level Functions */ @@ -415,6 +424,7 @@ void MXC_DMA_Handler(void); * @note The user must have the DMA interrupt enabled and call * MXC_DMA_Handler() from the ISR. * + * @param dma Pointer to DMA registers. * @param dest pointer to destination memory * @param src pointer to source memory * @param len number of bytes to copy @@ -422,20 +432,22 @@ void MXC_DMA_Handler(void); * * @return see \ref MXC_Error_Codes */ -int MXC_DMA_MemCpy(void *dest, void *src, int len, mxc_dma_complete_cb_t callback); +int MXC_DMA_MemCpy(mxc_dma_regs_t *dma, void *dest, void *src, int len, + mxc_dma_complete_cb_t callback); /** * @brief Performs a memcpy, using DMA, optionally asynchronous * @note The user must have the DMA interrupt enabled and call * MXC_DMA_Handler() from the ISR. * + * @param dma Pointer to DMA registers. * @param config The channel config struct * @param firstSrcDst The source, destination, and count for the first transfer * @param callback function is called when transfer is complete * * @return see \ref MXC_Error_Codes */ -int MXC_DMA_DoTransfer(mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, +int MXC_DMA_DoTransfer(mxc_dma_regs_t *dma, mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, mxc_dma_trans_chain_t callback); /** * For other functional uses of DMA (UART, SPI, etc) see the appropriate peripheral driver diff --git a/Libraries/PeriphDrivers/Include/MAX32657/mxc_sys.h b/Libraries/PeriphDrivers/Include/MAX32657/mxc_sys.h index 2bb366ac654..4d0d93621d3 100644 --- a/Libraries/PeriphDrivers/Include/MAX32657/mxc_sys.h +++ b/Libraries/PeriphDrivers/Include/MAX32657/mxc_sys.h @@ -26,7 +26,6 @@ #include "mxc_device.h" #include "gcr_regs.h" -#include "lpgcr_regs.h" #ifdef __cplusplus extern "C" { @@ -41,123 +40,73 @@ extern "C" { /** @brief System reset0 and reset1 enumeration. Used in MXC_SYS_PeriphReset0 function */ typedef enum { - MXC_SYS_RESET0_DMA = MXC_F_GCR_RST0_DMA_POS, /**< Reset DMA */ - MXC_SYS_RESET0_WDT0 = MXC_F_GCR_RST0_WDT0_POS, /**< Reset WDT */ + MXC_SYS_RESET0_DMA0 = MXC_F_GCR_RST0_DMA0_POS, /**< Reset DMA0 */ + MXC_SYS_RESET0_WDT = MXC_F_GCR_RST0_WDT_POS, /**< Reset WDT */ MXC_SYS_RESET0_GPIO0 = MXC_F_GCR_RST0_GPIO0_POS, /**< Reset GPIO0 */ - MXC_SYS_RESET0_GPIO1 = MXC_F_GCR_RST0_GPIO1_POS, /**< Reset GPIO1 */ MXC_SYS_RESET0_TMR0 = MXC_F_GCR_RST0_TMR0_POS, /**< Reset TMR0 */ MXC_SYS_RESET0_TMR1 = MXC_F_GCR_RST0_TMR1_POS, /**< Reset TMR1 */ MXC_SYS_RESET0_TMR2 = MXC_F_GCR_RST0_TMR2_POS, /**< Reset TMR2 */ MXC_SYS_RESET0_TMR3 = MXC_F_GCR_RST0_TMR3_POS, /**< Reset TMR3 */ - MXC_SYS_RESET0_UART0 = MXC_F_GCR_RST0_UART0_POS, /**< Reset UART0 */ - MXC_SYS_RESET0_UART1 = MXC_F_GCR_RST0_UART1_POS, /**< Reset UART1 */ - MXC_SYS_RESET0_SPI1 = MXC_F_GCR_RST0_SPI1_POS, /**< Reset SPI1 */ - MXC_SYS_RESET0_I2C0 = MXC_F_GCR_RST0_I2C0_POS, /**< Reset I2C0 */ + MXC_SYS_RESET0_TMR4 = MXC_F_GCR_RST0_TMR4_POS, /**< Reset TMR4 */ + MXC_SYS_RESET0_TMR5 = MXC_F_GCR_RST0_TMR5_POS, /**< Reset TMR5 */ + MXC_SYS_RESET0_UART = MXC_F_GCR_RST0_UART_POS, /**< Reset UART0 */ + MXC_SYS_RESET0_SPI = MXC_F_GCR_RST0_SPI_POS, /**< Reset SPI */ + MXC_SYS_RESET0_I3C = MXC_F_GCR_RST0_I3C, /**< Reset I2C/I3C */ MXC_SYS_RESET0_RTC = MXC_F_GCR_RST0_RTC_POS, /**< Reset RTC */ - MXC_SYS_RESET0_SMPHR = MXC_F_GCR_RST0_SMPHR_POS, /**< Reset SMPHR */ + // MXC_SYS_RESET0_SMPHR = MXC_F_GCR_RST0_SMPHR_POS, /**< Reset SMPHR */ MXC_SYS_RESET0_TRNG = MXC_F_GCR_RST0_TRNG_POS, /**< Reset TRNG */ - MXC_SYS_RESET0_CNN = MXC_F_GCR_RST0_CNN_POS, /**< Reset CNN */ - MXC_SYS_RESET0_ADC = MXC_F_GCR_RST0_ADC_POS, /**< Reset ADC */ - MXC_SYS_RESET0_UART2 = MXC_F_GCR_RST0_UART2_POS, /**< Reset UART2 */ + MXC_SYS_RESET0_DMA1 = MXC_F_GCR_RST0_DMA1_POS, /**< Reset DMA0 */ MXC_SYS_RESET0_SOFT = MXC_F_GCR_RST0_SOFT_POS, /**< Soft reset */ MXC_SYS_RESET0_PERIPH = MXC_F_GCR_RST0_PERIPH_POS, /**< Peripheral reset */ MXC_SYS_RESET0_SYS = MXC_F_GCR_RST0_SYS_POS, /**< System reset */ /* RESET1 Below this line we add 32 to separate RESET0 and RESET1 */ - MXC_SYS_RESET1_I2C1 = (MXC_F_GCR_RST1_I2C1_POS + 32), /**< Reset I2C1 */ - MXC_SYS_RESET1_PT = (MXC_F_GCR_RST1_PT_POS + 32), /**< Reset PT */ - MXC_SYS_RESET1_OWM = (MXC_F_GCR_RST1_OWM_POS + 32), /**< Reset OWM */ MXC_SYS_RESET1_CRC = (MXC_F_GCR_RST1_CRC_POS + 32), /**< Reset CRC */ MXC_SYS_RESET1_AES = (MXC_F_GCR_RST1_AES_POS + 32), /**< Reset AES */ - MXC_SYS_RESET1_SMPHR = (MXC_F_GCR_RST1_SMPHR_POS + 32), /**< Reset SMPHR */ - MXC_SYS_RESET1_I2C2 = (MXC_F_GCR_RST1_I2C2_POS + 32), /**< Reset I2C2 */ - MXC_SYS_RESET1_I2S = (MXC_F_GCR_RST1_I2S_POS + 32), /**< Reset I2S*/ - // MXC_SYS_RESET1_BTLE = (MXC_F_GCR_RST1_BTLE_POS + 32), /**< Reset BTLE*/ - MXC_SYS_RESET1_DVS = (MXC_F_GCR_RST1_DVS_POS + 32), /**< Reset DVS */ - MXC_SYS_RESET1_SIMO = (MXC_F_GCR_RST1_SIMO_POS + 32), /**< Reset SIMO */ - MXC_SYS_RESET1_SPI0 = (MXC_F_GCR_RST1_SPI0_POS + 32), /**< Reset SPI0 */ - MXC_SYS_RESET1_CPU1 = (MXC_F_GCR_RST1_CPU1_POS + 32), /**< Reset CPU1 */ - /* LPGCR RESET Below this line we add 64 to separate LPGCR and GCR */ - MXC_SYS_RESET_GPIO2 = (MXC_F_LPGCR_RST_GPIO2_POS + 64), /**< Reset GPIO2 */ - MXC_SYS_RESET_WDT1 = (MXC_F_LPGCR_RST_WDT1_POS + 64), /**< Reset WDT1 */ - MXC_SYS_RESET_TMR4 = (MXC_F_LPGCR_RST_TMR4_POS + 64), /**< Reset TMR4 */ - MXC_SYS_RESET_TMR5 = (MXC_F_LPGCR_RST_TMR5_POS + 64), /**< Reset TMR5 */ - MXC_SYS_RESET_UART3 = (MXC_F_LPGCR_RST_UART3_POS + 64), /**< Reset UART3 */ - MXC_SYS_RESET_LPCOMP = (MXC_F_LPGCR_RST_LPCOMP_POS + 64), /**< Reset LPCOMP */ } mxc_sys_reset_t; /** @brief System clock disable enumeration. Used in MXC_SYS_ClockDisable and MXC_SYS_ClockEnable functions */ typedef enum { MXC_SYS_PERIPH_CLOCK_GPIO0 = - MXC_F_GCR_PCLKDIS0_GPIO0_POS, /**< Disable MXC_F_GCR_PCLKDIS0_GPIO0 clock */ - MXC_SYS_PERIPH_CLOCK_GPIO1 = - MXC_F_GCR_PCLKDIS0_GPIO1_POS, /**< Disable MXC_F_GCR_PCLKDIS0_GPIO1 clock */ - MXC_SYS_PERIPH_CLOCK_DMA = - MXC_F_GCR_PCLKDIS0_DMA_POS, /**< Disable MXC_F_GCR_PCLKDIS0_DMA clock */ - MXC_SYS_PERIPH_CLOCK_SPI1 = - MXC_F_GCR_PCLKDIS0_SPI1_POS, /**< Disable MXC_F_GCR_PCLKDIS0_SPI1 clock */ - MXC_SYS_PERIPH_CLOCK_UART0 = - MXC_F_GCR_PCLKDIS0_UART0_POS, /**< Disable MXC_F_GCR_PCLKDIS0_UART0 clock */ - MXC_SYS_PERIPH_CLOCK_UART1 = - MXC_F_GCR_PCLKDIS0_UART1_POS, /**< Disable MXC_F_GCR_PCLKDIS0_UART1 clock */ - MXC_SYS_PERIPH_CLOCK_I2C0 = - MXC_F_GCR_PCLKDIS0_I2C0_POS, /**< Disable MXC_F_GCR_PCLKDIS0_I2C0 clock */ + MXC_F_GCR_PCLKDIS0_GPIO0_POS, /**< Disable GPIO0 clock */ + MXC_SYS_PERIPH_CLOCK_DMA0 = + MXC_F_GCR_PCLKDIS0_DMA0_POS, /**< Disable DMA0 clock */ + MXC_SYS_PERIPH_CLOCK_SPI = + MXC_F_GCR_PCLKDIS0_SPI_POS, /**< Disable SPI clock */ + MXC_SYS_PERIPH_CLOCK_UART = + MXC_F_GCR_PCLKDIS0_UART_POS, /**< Disable UART0 clock */ + MXC_SYS_PERIPH_CLOCK_I3C = + MXC_F_GCR_PCLKDIS0_I3C_POS, /**< Disable I2C/I3C clock */ MXC_SYS_PERIPH_CLOCK_TMR0 = - MXC_F_GCR_PCLKDIS0_TMR0_POS, /**< Disable MXC_F_GCR_PCLKDIS0_TMR0 clock */ + MXC_F_GCR_PCLKDIS0_TMR0_POS, /**< Disable TMR0 clock */ MXC_SYS_PERIPH_CLOCK_TMR1 = - MXC_F_GCR_PCLKDIS0_TMR1_POS, /**< Disable MXC_F_GCR_PCLKDIS0_TMR1 clock */ + MXC_F_GCR_PCLKDIS0_TMR1_POS, /**< Disable TMR1 clock */ MXC_SYS_PERIPH_CLOCK_TMR2 = - MXC_F_GCR_PCLKDIS0_TMR2_POS, /**< Disable MXC_F_GCR_PCLKDIS0_TMR2 clock */ + MXC_F_GCR_PCLKDIS0_TMR2_POS, /**< Disable TMR2 clock */ MXC_SYS_PERIPH_CLOCK_TMR3 = - MXC_F_GCR_PCLKDIS0_TMR3_POS, /**< Disable MXC_F_GCR_PCLKDIS0_T3 clock */ - MXC_SYS_PERIPH_CLOCK_ADC = - MXC_F_GCR_PCLKDIS0_ADC_POS, /**< Disable MXC_F_GCR_PCLKDIS0_ADC clock */ - MXC_SYS_PERIPH_CLOCK_CNN = - MXC_F_GCR_PCLKDIS0_CNN_POS, /**< Disable MXC_F_GCR_PCLKDIS0_CNN clock */ - MXC_SYS_PERIPH_CLOCK_I2C1 = - MXC_F_GCR_PCLKDIS0_I2C1_POS, /**< Disable MXC_F_GCR_PCLKDIS0_I2C1 clock */ - MXC_SYS_PERIPH_CLOCK_PT = MXC_F_GCR_PCLKDIS0_PT_POS, /**< Disable MXC_F_GCR_PCLKDIS0_PT clock */ + MXC_F_GCR_PCLKDIS0_TMR3_POS, /**< Disable TMR3 clock */ + MXC_SYS_PERIPH_CLOCK_TMR4 = + MXC_F_GCR_PCLKDIS0_TMR4_POS, /**< Disable TMR4 clock */ + MXC_SYS_PERIPH_CLOCK_TMR5 = + MXC_F_GCR_PCLKDIS0_TMR5_POS, /**< Disable TMR4 clock */ /* PCLKDIS1 Below this line we add 32 to separate PCLKDIS0 and PCLKDIS1 */ - MXC_SYS_PERIPH_CLOCK_UART2 = - (MXC_F_GCR_PCLKDIS1_UART2_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_UART2 clock */ MXC_SYS_PERIPH_CLOCK_TRNG = - (MXC_F_GCR_PCLKDIS1_TRNG_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_TRNG clock */ - MXC_SYS_PERIPH_CLOCK_SMPHR = - (MXC_F_GCR_PCLKDIS1_SMPHR_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_SMPHR clock */ - MXC_SYS_PERIPH_CLOCK_OWIRE = - (MXC_F_GCR_PCLKDIS1_OWM_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_OWM clock */ + (MXC_F_GCR_PCLKDIS1_TRNG_POS + 32), /**< Disable TRNG clock */ + // MXC_SYS_PERIPH_CLOCK_SMPHR = + // (MXC_F_GCR_PCLKDIS1_SMPHR_POS + 32), /**< Disable SMPHR clock */ MXC_SYS_PERIPH_CLOCK_CRC = - (MXC_F_GCR_PCLKDIS1_CRC_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_CRC clock */ + (MXC_F_GCR_PCLKDIS1_CRC_POS + 32), /**< Disable CRC clock */ MXC_SYS_PERIPH_CLOCK_AES = - (MXC_F_GCR_PCLKDIS1_AES_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_AES clock */ - MXC_SYS_PERIPH_CLOCK_I2S = - (MXC_F_GCR_PCLKDIS1_I2S_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_I2S clock */ - MXC_SYS_PERIPH_CLOCK_SPI0 = - (MXC_F_GCR_PCLKDIS1_SPI0_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_SPI0 clock */ - MXC_SYS_PERIPH_CLOCK_I2C2 = - (MXC_F_GCR_PCLKDIS1_I2C2_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_I2C2 clock */ - MXC_SYS_PERIPH_CLOCK_WDT0 = - (MXC_F_GCR_PCLKDIS1_WDT0_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_WDT0 clock */ - MXC_SYS_PERIPH_CLOCK_CPU1 = - (MXC_F_GCR_PCLKDIS1_CPU1_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_CPU1 clock */ - /* LPGCR PCLKDIS Below this line we add 64 to seperate GCR and LPGCR registers */ - MXC_SYS_PERIPH_CLOCK_GPIO2 = - (MXC_F_LPGCR_PCLKDIS_GPIO2_POS + 64), /**< Disable MXC_F_LPGCR_PCLKDIS_GPIO2 clock */ - MXC_SYS_PERIPH_CLOCK_WDT1 = - (MXC_F_LPGCR_PCLKDIS_WDT1_POS + 64), /**< Disable MXC_F_LPGCR_PCLKDIS_WDT1 clock */ - MXC_SYS_PERIPH_CLOCK_TMR4 = - (MXC_F_LPGCR_PCLKDIS_TMR4_POS + 64), /**< Disable MXC_F_LPGCR_PCLKDIS_TMR4 clock */ - MXC_SYS_PERIPH_CLOCK_TMR5 = - (MXC_F_LPGCR_PCLKDIS_TMR5_POS + 64), /**< Disable MXC_F_LPGCR_PCLKDIS_TMR5 clock */ - MXC_SYS_PERIPH_CLOCK_UART3 = - (MXC_F_LPGCR_PCLKDIS_UART3_POS + 64), /**< Disable MXC_F_LPGCR_PCLKDIS_UART3 clock */ - MXC_SYS_PERIPH_CLOCK_LPCOMP = - (MXC_F_LPGCR_PCLKDIS_LPCOMP_POS + 64), /**< Disable MXC_F_LPGCR_PCLKDIS_LPCOMP clock */ + (MXC_F_GCR_PCLKDIS1_AES_POS + 32), /**< Disable AES clock */ + // MXC_SYS_PERIPH_CLOCK_SPI = + // (MXC_F_GCR_PCLKDIS1_SPI_POS + 32), /**< Disable SPI clock */ + // TODO(JC): The SPI clock disable is defined in both PCLKDIS0 and PCLKDIS1 + MXC_SYS_PERIPH_CLOCK_WDT = + (MXC_F_GCR_PCLKDIS1_WDT_POS), /**< Disable WDT clock */ } mxc_sys_periph_clock_t; /** @brief Enumeration to select System Clock source */ +// TODO(ME30): CLKCTRL sysclk_sel values seem incorrect. typedef enum { - MXC_SYS_CLOCK_ISO = - MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ISO, /**< Select the Internal Secondary Oscillator (ISO) */ MXC_SYS_CLOCK_IPO = MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IPO, /**< Select the Internal Primary Oscillator (IPO) */ MXC_SYS_CLOCK_IBRO = @@ -168,8 +117,9 @@ typedef enum { MXC_V_GCR_CLKCTRL_SYSCLK_SEL_INRO, /**< Select the Internal Nanoring Oscillator (INRO) */ MXC_SYS_CLOCK_ERTCO = MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERTCO, /**< Select the External RTC Crystal Oscillator */ - MXC_SYS_CLOCK_EXTCLK = - MXC_V_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK /**< Use the external system clock input */ + // MXC_SYS_CLOCK_EXTCLK = + // MXC_V_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK /**< Use the external system clock input */ + // TODO(JC): ^^^ EXTCLK select is missing from gcr_regs.h (should be 0x7) } mxc_sys_system_clock_t; /** @brief Enumeration to set the System Clock divider */ diff --git a/Libraries/PeriphDrivers/Include/MAX32657/rtc.h b/Libraries/PeriphDrivers/Include/MAX32657/rtc.h index ad8c192a5f9..187e70ec417 100644 --- a/Libraries/PeriphDrivers/Include/MAX32657/rtc.h +++ b/Libraries/PeriphDrivers/Include/MAX32657/rtc.h @@ -70,8 +70,8 @@ typedef enum { * @brief Bitmasks for each of the RTC's interrupt flags. */ typedef enum { - MXC_RTC_INT_FL_LONG = MXC_F_RTC_CTRL_TOD_ALARM, /**< Long-interval alarm interrupt flag */ - MXC_RTC_INT_FL_SHORT = MXC_F_RTC_CTRL_SSEC_ALARM, /**< Short-interval alarm interrupt flag */ + MXC_RTC_INT_FL_LONG = MXC_F_RTC_CTRL_TOD_ALARM_IF, /**< Long-interval alarm interrupt flag */ + MXC_RTC_INT_FL_SHORT = MXC_F_RTC_CTRL_SSEC_ALARM_IF, /**< Short-interval alarm interrupt flag */ MXC_RTC_INT_FL_READY = MXC_F_RTC_CTRL_RDY, /**< Timer ready interrupt flag */ } mxc_rtc_int_fl_t; diff --git a/Libraries/PeriphDrivers/Include/MAX32657/spi.h b/Libraries/PeriphDrivers/Include/MAX32657/spi.h index de855f2cb0e..7ddde948670 100644 --- a/Libraries/PeriphDrivers/Include/MAX32657/spi.h +++ b/Libraries/PeriphDrivers/Include/MAX32657/spi.h @@ -32,6 +32,7 @@ #include "gpio.h" #include "mxc_pins.h" #include "mxc_lock.h" +#include "dma_regs.h" #ifdef __cplusplus extern "C" { @@ -595,11 +596,12 @@ int MXC_SPI_MasterTransactionAsync(mxc_spi_req_t *req); * possible. The channel will be reset and returned to the system at the end of * the transaction. * - * @param req Pointer to details of the transaction + * @param req Pointer to details of the transaction + * @param dma DMA instance to use for SPI DMA * * @return See \ref MXC_Error_Codes for the list of error return codes. */ -int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t *req); +int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t *req, mxc_dma_regs_t *dma); /** * @brief Performs a blocking SPI transaction. @@ -642,10 +644,11 @@ int MXC_SPI_SlaveTransactionAsync(mxc_spi_req_t *req); * the transaction. * * @param req Pointer to details of the transaction + * @param dma DMA instance to use for SPI DMA * * @return See \ref MXC_Error_Codes for the list of error return codes. */ -int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t *req); +int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t *req, mxc_dma_regs_t *dma); /** * @brief Sets the TX data to transmit as a 'dummy' byte diff --git a/Libraries/PeriphDrivers/Include/MAX32657/tmr.h b/Libraries/PeriphDrivers/Include/MAX32657/tmr.h index 89e3feb3760..9fd2c7d96ad 100644 --- a/Libraries/PeriphDrivers/Include/MAX32657/tmr.h +++ b/Libraries/PeriphDrivers/Include/MAX32657/tmr.h @@ -137,10 +137,10 @@ typedef enum { /** * @brief Peripheral Clock settings */ +// TODO(ME30): TMR clock sources typedef enum { MXC_TMR_APB_CLK = 0, /**< PCLK */ MXC_TMR_EXT_CLK = 1, /**< External Clock */ - MXC_TMR_ISO_CLK = 2, /**< 60MHz Clock */ MXC_TMR_IBRO_CLK = 3, /**< 7.3728MHz Clock */ MXC_TMR_ERTCO_CLK = 4, /**< 32.768KHz Clock */ MXC_TMR_INRO_CLK = 5, /**< 8-30KHz Clock */ diff --git a/Libraries/PeriphDrivers/Include/MAX32657/uart.h b/Libraries/PeriphDrivers/Include/MAX32657/uart.h index 8acc38bb9b5..523b80f8e0b 100644 --- a/Libraries/PeriphDrivers/Include/MAX32657/uart.h +++ b/Libraries/PeriphDrivers/Include/MAX32657/uart.h @@ -1,11 +1,13 @@ /** * @file uart.h - * @brief Serial Peripheral Interface (UART) communications driver. + * @brief (UART) communications driver. */ /****************************************************************************** * - * Copyright (C) 2024 Analog Devices, Inc. + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -22,20 +24,19 @@ ******************************************************************************/ /* Define to prevent redundant inclusion */ -#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_UART_H_ -#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_UART_H_ +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32570_UART_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32570_UART_H_ /***** Definitions *****/ #include #include "uart_regs.h" #include "mxc_sys.h" +#include "dma_regs.h" #ifdef __cplusplus extern "C" { #endif -#define UART_EXTCLK_FREQ E_BAD_PARAM - /** * @defgroup uart UART * @ingroup periphlibs @@ -45,7 +46,7 @@ extern "C" { typedef struct _mxc_uart_req_t mxc_uart_req_t; /** * @brief The list of UART stop bit lengths supported - * + * */ typedef enum { MXC_UART_STOP_1, ///< UART Stop 1 clock cycle @@ -54,69 +55,67 @@ typedef enum { /** * @brief The list of UART Parity options supported - * + * */ typedef enum { MXC_UART_PARITY_DISABLE, ///< UART Parity Disabled + MXC_UART_PARITY_EVEN, ///< UART Parity Even + MXC_UART_PARITY_ODD, ///< UART Parity Odd + MXC_UART_PARITY_MARK, ///< UART Parity Mark + MXC_UART_PARITY_SPACE, ///< UART Parity Space MXC_UART_PARITY_EVEN_0, ///< UART Parity Even, 0 based MXC_UART_PARITY_EVEN_1, ///< UART Parity Even, 1 based MXC_UART_PARITY_ODD_0, ///< UART Parity Odd, 0 based MXC_UART_PARITY_ODD_1, ///< UART Parity Odd, 1 based + MXC_UART_PARITY_MARK_0, ///< UART Parity Mark, 0 based + MXC_UART_PARITY_MARK_1, ///< UART Parity Mark, 1 based + MXC_UART_PARITY_SPACE_0, ///< UART Parity Space, 0 based + MXC_UART_PARITY_SPACE_1, ///< UART Parity Space, 1 based } mxc_uart_parity_t; /** * @brief The list of UART flow control options supported - * + * */ typedef enum { MXC_UART_FLOW_DIS, ///< UART Flow Control Disabled - MXC_UART_FLOW_EN, ///< UART Flow Control Enabled + MXC_UART_FLOW_EN_LOW, ///< UART Flow Control Enabled, Active Low + MXC_UART_FLOW_EN_HIGH, ///< UART Flow Control Enabled, Active High } mxc_uart_flow_t; -/** - * @brief Clock settings */ -typedef enum { - /*Only available for UARTS 0-2*/ - MXC_UART_APB_CLK = 0, - /*Available for all UARTs*/ - MXC_UART_IBRO_CLK = 2, - /*ERTCO clock can only be used for UART3*/ - MXC_UART_ERTCO_CLK = 4, -} mxc_uart_clock_t; - /** * @brief The callback routine used to indicate the transaction has terminated. * - * @param req The details of the transaction. - * @param result See \ref MXC_Error_Codes for the list of error codes. + * @param req The details of the transaction. + * @param result See \ref MXC_Error_Codes for the list of error codes. */ typedef void (*mxc_uart_complete_cb_t)(mxc_uart_req_t *req, int result); /** * @brief The callback routine used to indicate the transaction has terminated. * - * @param req The details of the transaction. - * @param num The number of characters actually copied - * @param result See \ref MXC_Error_Codes for the list of error codes. + * @param req The details of the transaction. + * @param num The number of characters actually copied + * @param result See \ref MXC_Error_Codes for the list of error codes. */ typedef void (*mxc_uart_dma_complete_cb_t)(mxc_uart_req_t *req, int num, int result); /** - * @brief The information required to perform a complete UART transaction + * @brief The information required to perform a complete UART transaction. * - * @note This structure is used by blocking, async, and DMA based transactions. - * @note "callback" only needs to be initialized for interrupt driven (Async) and DMA transactions. + * This structure is used by blocking, async, and DMA based transactions. + * @note "callback" is only needed for interrupt driven (Async) and DMA transactions. */ struct _mxc_uart_req_t { mxc_uart_regs_t *uart; /// 8 bits, use two bytes per character - ///< and pad the MSB of the upper byte with zeros + uint8_t *txData; ///< Buffer containing transmit data. For character sizes + ///< < 8 bits, pad the MSB of each byte with zeros. For + ///< character sizes > 8 bits, use two bytes per character + ///< and pad the MSB of the upper byte with zeros uint8_t *rxData; ///< Buffer to store received data For character sizes - ///< < 8 bits, pad the MSB of each byte with zeros. For - ///< character sizes > 8 bits, use two bytes per character - ///< and pad the MSB of the upper byte with zeros + ///< < 8 bits, pad the MSB of each byte with zeros. For + ///< character sizes > 8 bits, use two bytes per character + ///< and pad the MSB of the upper byte with zeros uint32_t txLen; ///< Number of bytes to be sent from txData uint32_t rxLen; ///< Number of bytes to be stored in rxData volatile uint32_t txCnt; ///< Number of bytes actually transmitted from txData @@ -133,29 +132,25 @@ struct _mxc_uart_req_t { /** * @brief Initialize and enable UART peripheral. - * + * * This function initializes everything necessary to call a UART transaction function. * Some parameters are set to defaults as follows: * UART Data Size - 8 bits * UART Stop Bits - 1 bit * UART Parity - None * UART Flow Control - None - * + * UART Clock - 7.37MHz Clock (for baud > 7372800, PCLK is used) + * * These parameters can be modified after initialization using low level functions - * - * @note On default this function enables UART peripheral clock. - * if you wish to manage clock and gpio related things in upper level instead of here. - * Define MSDK_NO_GPIO_CLK_INIT flag in project.mk file. - * By this flag this function will remove clock and gpio related codes from file. - * - * @param uart Pointer to UART registers (selects the UART block used.) - * @param baud The requested clock frequency. The actual clock frequency - * will be returned by the function if successful. - * @param clock Clock source * - * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + * @param uart Pointer to UART registers (selects the UART block used.) + * @param baud The requested clock frequency. The actual clock frequency + * will be returned by the function if successful. + * + * @return If successful, the actual clock frequency is returned. Otherwise, see + * \ref MXC_Error_Codes for a list of return codes. */ -int MXC_UART_Init(mxc_uart_regs_t *uart, unsigned int baud, mxc_uart_clock_t clock); +int MXC_UART_Init(mxc_uart_regs_t *uart, unsigned int baud); /** * @brief Disable and shutdown UART peripheral. @@ -183,14 +178,15 @@ int MXC_UART_ReadyForSleep(mxc_uart_regs_t *uart); /** * @brief Set the frequency of the UART interface. * - * @param uart Pointer to UART registers (selects the UART block used.) - * @param baud The desired baud rate - * @param clock Clock source + * + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param baud The desired baud rate * * @return Negative if error, otherwise actual speed set. See \ref * MXC_Error_Codes for the list of error return codes. */ -int MXC_UART_SetFrequency(mxc_uart_regs_t *uart, unsigned int baud, mxc_uart_clock_t clock); +int MXC_UART_SetFrequency(mxc_uart_regs_t *uart, unsigned int baud); /** * @brief Get the frequency of the UART interface. @@ -205,9 +201,9 @@ int MXC_UART_GetFrequency(mxc_uart_regs_t *uart); /** * @brief Sets the number of bits per character - * - * @param uart Pointer to UART registers (selects the UART block used.) - * @param dataSize The number of bits per character (5-8 bits/character are valid) + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param dataSize The number of bits per character (5-8 bits/character are valid) * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ @@ -215,9 +211,9 @@ int MXC_UART_SetDataSize(mxc_uart_regs_t *uart, int dataSize); /** * @brief Sets the number of stop bits sent at the end of a character - * - * @param uart Pointer to UART registers (selects the UART block used.) - * @param stopBits The number of stop bits used + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param stopBits The number of stop bits used * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ @@ -225,9 +221,9 @@ int MXC_UART_SetStopBits(mxc_uart_regs_t *uart, mxc_uart_stop_t stopBits); /** * @brief Sets the type of parity generation used - * - * @param uart Pointer to UART registers (selects the UART block used.) - * @param parity see \ref UART Parity Types for details + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param parity see \ref mxc_uart_parity_t UART Parity Types for details * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ @@ -235,10 +231,10 @@ int MXC_UART_SetParity(mxc_uart_regs_t *uart, mxc_uart_parity_t parity); /** * @brief Sets the flow control used - * - * @param uart Pointer to UART registers (selects the UART block used.) - * @param flowCtrl see \ref UART Flow Control Types for details - * @param rtsThreshold Number of bytes remaining in the RX FIFO when RTS is asserted + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param flowCtrl see \ref mxc_uart_flow_t UART Flow Control Types for details + * @param rtsThreshold Number of bytes remaining in the RX FIFO when RTS is asserted * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ @@ -246,24 +242,47 @@ int MXC_UART_SetFlowCtrl(mxc_uart_regs_t *uart, mxc_uart_flow_t flowCtrl, int rt /** * @brief Sets the clock source for the baud rate generator - * - * @param uart Pointer to UART registers (selects the UART block used.) - * @param clock Clock source * - * @return Actual baud rate if successful, otherwise see \ref MXC_Error_Codes + * @param uart Pointer to UART registers (selects the UART block used.) + * @param usePCLK Non-zero values will use the PCLK as the bit clock instead + * of the default 7.37MHz clock source. The baud rate generator + * will automatically be reconfigured to the closest possible + * baud rate. + * + * @return Actual baud rate if successful, otherwise see \ref MXC_Error_Codes * for a list of return codes. */ -int MXC_UART_SetClockSource(mxc_uart_regs_t *uart, mxc_uart_clock_t clock); +int MXC_UART_SetClockSource(mxc_uart_regs_t *uart, int usePCLK); + +/** + * @brief Enables or Disables the built-in null modem + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param nullModem Non-zero values will enable the null modem function, + * which swaps TXD/RXD and also swaps RTS/CTS, if used. + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_UART_SetNullModem(mxc_uart_regs_t *uart, int nullModem); /* ************************************************************************* */ /* Low-level functions */ /* ************************************************************************* */ +/** + * @brief Transmits a Break Frame (all bits 0) + * + * @param uart Pointer to UART registers (selects the UART block used.) + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_UART_SendBreak(mxc_uart_regs_t *uart); + /** * @brief Checks the UART Peripheral for an ongoing transmission * * @note This function is applicable in Master mode only - * + * * @param uart Pointer to UART registers (selects the UART block used.) * * @return Active/Inactive, see \ref MXC_Error_Codes for a list of return codes. @@ -280,44 +299,46 @@ int MXC_UART_GetActive(mxc_uart_regs_t *uart); int MXC_UART_AbortTransmission(mxc_uart_regs_t *uart); /** - * @brief Reads the next available character. If no character is available, this function - * will return an error. + * @brief Reads the next available character. This function will block until a character + * is available or a UART error occurs. * * @param uart Pointer to UART registers (selects the UART block used.) * * @return The character read, otherwise see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_UART_ReadCharacterRaw(mxc_uart_regs_t *uart); +int MXC_UART_ReadCharacter(mxc_uart_regs_t *uart); /** - * @brief Writes a character on the UART. If the character cannot be written because the - * transmit FIFO is currently full, this function returns an error. + * @brief Writes a character on the UART. This function will block until the character + * has been placed in the TX FIFO or a UART error occurs. * * @param uart Pointer to UART registers (selects the UART block used.) * @param character The character to write * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_UART_WriteCharacterRaw(mxc_uart_regs_t *uart, uint8_t character); +int MXC_UART_WriteCharacter(mxc_uart_regs_t *uart, uint8_t character); /** - * @brief Reads the next available character + * @brief Reads the next available character. If no character is available, this function + * will return an error. * * @param uart Pointer to UART registers (selects the UART block used.) * * @return The character read, otherwise see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_UART_ReadCharacter(mxc_uart_regs_t *uart); +int MXC_UART_ReadCharacterRaw(mxc_uart_regs_t *uart); /** - * @brief Writes a character on the UART + * @brief Writes a character on the UART. If the character cannot be written because the + * transmit FIFO is currently full, this function returns an error. * * @param uart Pointer to UART registers (selects the UART block used.) - * @param character The character to write + * @param character The character to write * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_UART_WriteCharacter(mxc_uart_regs_t *uart, uint8_t character); +int MXC_UART_WriteCharacterRaw(mxc_uart_regs_t *uart, uint8_t character); /** * @brief Reads the next available character @@ -326,7 +347,7 @@ int MXC_UART_WriteCharacter(mxc_uart_regs_t *uart, uint8_t character); * * @param uart Pointer to UART registers (selects the UART block used.) * @param buffer Buffer to store data in - * @param len Number of characters + * @param len Number of characters * * @return The character read, otherwise see \ref MXC_Error_Codes for a list of return codes. */ @@ -336,19 +357,19 @@ int MXC_UART_Read(mxc_uart_regs_t *uart, uint8_t *buffer, int *len); * @brief Writes a byte on the UART * * @param uart Pointer to UART registers (selects the UART block used.) - * @param byte The buffer of characters to write + * @param byte The buffer of characters to write * @param len The number of characters to write * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_UART_Write(mxc_uart_regs_t *uart, const uint8_t *byte, int *len); +int MXC_UART_Write(mxc_uart_regs_t *uart, uint8_t *byte, int *len); /** * @brief Unloads bytes from the receive FIFO. * * @param uart Pointer to UART registers (selects the UART block used.) - * @param bytes The buffer to read the data into. - * @param len The number of bytes to read. + * @param bytes The buffer to read the data into. + * @param len The number of bytes to read. * * @return The number of bytes actually read. */ @@ -357,14 +378,15 @@ unsigned int MXC_UART_ReadRXFIFO(mxc_uart_regs_t *uart, unsigned char *bytes, un /** * @brief Unloads bytes from the receive FIFO user DMA for longer reads. * - * @param uart Pointer to UART registers (selects the UART block used.) - * @param bytes The buffer to read the data into. - * @param len The number of bytes to read. - * @param callback The function to call when the read is complete + * @param uart Pointer to UART registers (selects the UART block used). + * @param dma Pointer to DMA registers (selects the DMA block used for UART DMA). + * @param bytes The buffer to read the data into. + * @param len The number of bytes to read. + * @param callback The function to call when the read is complete * - * @return See \ref MXC_ERROR_CODES for a list of return values + * @return See \ref MXC_Error_Codes for a list of return values */ -int MXC_UART_ReadRXFIFODMA(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned int len, +int MXC_UART_ReadRXFIFODMA(mxc_uart_regs_t *uart, mxc_dma_regs_t *dma, unsigned char *bytes, unsigned int len, mxc_uart_dma_complete_cb_t callback); /** @@ -380,25 +402,25 @@ unsigned int MXC_UART_GetRXFIFOAvailable(mxc_uart_regs_t *uart); * @brief Loads bytes into the transmit FIFO. * * @param uart Pointer to UART registers (selects the UART block used.) - * @param bytes The buffer containing the bytes to write - * @param len The number of bytes to write. + * @param bytes The buffer containing the bytes to write + * @param len The number of bytes to write. * * @return The number of bytes actually written. */ -unsigned int MXC_UART_WriteTXFIFO(mxc_uart_regs_t *uart, const unsigned char *bytes, - unsigned int len); +unsigned int MXC_UART_WriteTXFIFO(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned int len); /** * @brief Loads bytes into the transmit FIFO using DMA for longer writes * - * @param uart Pointer to UART registers (selects the UART block used.) - * @param bytes The buffer containing the bytes to write - * @param len The number of bytes to write. - * @param callback The function to call when the write is complete + * @param uart Pointer to UART registers (selects the UART block used). + * @param dma Pointer to DMA registers (selects the DMA block used for UART DMA). + * @param bytes The buffer containing the bytes to write + * @param len The number of bytes to write. + * @param callback The function to call when the write is complete * - * @return See \ref MXC_ERROR_CODES for a list of return values + * @return See \ref MXC_Error_Codes for a list of return values */ -int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t *uart, const unsigned char *bytes, unsigned int len, +int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t *uart, mxc_dma_regs_t *dma, unsigned char *bytes, unsigned int len, mxc_uart_dma_complete_cb_t callback); /** @@ -430,18 +452,18 @@ int MXC_UART_ClearTXFIFO(mxc_uart_regs_t *uart); /** * @brief Set the receive threshold level. - * + * * @note RX FIFO Receive threshold. Smaller values will cause * interrupts to occur more often, but reduce the possibility * of losing data because of a FIFO overflow. Larger values - * will reduce the time required by the ISR, but increase the + * will reduce the time required by the ISR, but increase the * possibility of data loss. Passing an invalid value will - * cause the driver to use the value already set in the + * cause the driver to use the value already set in the * appropriate register. * * @param uart Pointer to UART registers (selects the UART block used.) - * @param numBytes The threshold level to set. This value must be - * between 0 and 8 inclusive. + * @param numBytes The threshold level to set. This value must be + * between 0 and 8 inclusive. * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ @@ -449,27 +471,27 @@ int MXC_UART_SetRXThreshold(mxc_uart_regs_t *uart, unsigned int numBytes); /** * @brief Get the current receive threshold level. - * + * * @param uart Pointer to UART registers (selects the UART block used.) - * + * * @return The receive threshold value (in bytes). */ unsigned int MXC_UART_GetRXThreshold(mxc_uart_regs_t *uart); /** * @brief Set the transmit threshold level. - * + * * @note TX FIFO threshold. Smaller values will cause interrupts * to occur more often, but reduce the possibility of terminating * a transaction early in master mode, or transmitting invalid data * in slave mode. Larger values will reduce the time required by - * the ISR, but increase the possibility errors occurring. Passing - * an invalid value will cause the driver to use the value already + * the ISR, but increase the possibility errors occurring. Passing + * an invalid value will cause the driver to use the value already * set in the appropriate register. * * @param uart Pointer to UART registers (selects the UART block used.) - * @param numBytes The threshold level to set. This value must be - * between 0 and 8 inclusive. + * @param numBytes The threshold level to set. This value must be + * between 0 and 8 inclusive. * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ @@ -477,9 +499,9 @@ int MXC_UART_SetTXThreshold(mxc_uart_regs_t *uart, unsigned int numBytes); /** * @brief Get the current transmit threshold level. - * + * * @param uart Pointer to UART registers (selects the UART block used.) - * + * * @return The transmit threshold value (in bytes). */ unsigned int MXC_UART_GetTXThreshold(mxc_uart_regs_t *uart); @@ -487,24 +509,24 @@ unsigned int MXC_UART_GetTXThreshold(mxc_uart_regs_t *uart); /** * @brief Gets the interrupt flags that are currently set * - * @note These functions should not be used while using non-blocking Transaction Level + * @note These functions should not be used while using non-blocking Transaction Level * functions (Async or DMA) * * @param uart Pointer to UART registers (selects the UART block used.) - * - * @return The interrupt flags + * + * @return The interrupt flags */ unsigned int MXC_UART_GetFlags(mxc_uart_regs_t *uart); /** * @brief Clears the interrupt flags that are currently set * - * @note These functions should not be used while using non-blocking Transaction Level + * @note These functions should not be used while using non-blocking Transaction Level * functions (Async or DMA) * * @param uart Pointer to UART registers (selects the UART block used.) * @param flags mask of flags to clear - * + * * @return See \ref MXC_Error_Codes for the list of error return codes. */ int MXC_UART_ClearFlags(mxc_uart_regs_t *uart, unsigned int flags); @@ -512,7 +534,7 @@ int MXC_UART_ClearFlags(mxc_uart_regs_t *uart, unsigned int flags); /** * @brief Enables specific interrupts * - * @note These functions should not be used while using non-blocking Transaction Level + * @note These functions should not be used while using non-blocking Transaction Level * functions (Async or DMA) * * @param uart Pointer to UART registers (selects the UART block used.) @@ -525,7 +547,7 @@ int MXC_UART_EnableInt(mxc_uart_regs_t *uart, unsigned int mask); /** * @brief Disables specific interrupts * - * @note These functions should not be used while using non-blocking Transaction Level + * @note These functions should not be used while using non-blocking Transaction Level * functions (Async or DMA) * * @param uart Pointer to UART registers (selects the UART block used.) @@ -539,7 +561,7 @@ int MXC_UART_DisableInt(mxc_uart_regs_t *uart, unsigned int mask); * @brief Gets the status flags that are currently set * * @param uart Pointer to UART registers (selects the UART block used.) - * + * * @return The status flags */ unsigned int MXC_UART_GetStatus(mxc_uart_regs_t *uart); @@ -549,13 +571,13 @@ unsigned int MXC_UART_GetStatus(mxc_uart_regs_t *uart); /* ************************************************************************* */ /** - * @brief Performs a blocking UART transaction. - * + * @brief Performs a blocking UART transaction. + * * @note Performs a blocking UART transaction as follows. * If tx_len is non-zero, transmit TX data * Once tx_len has been sent, if rx_len is non-zero, receive data * - * @param req Pointer to details of the transaction + * @param req Pointer to details of the transaction * * @return See \ref MXC_Error_Codes for the list of error return codes. */ @@ -563,11 +585,11 @@ int MXC_UART_Transaction(mxc_uart_req_t *req); /** * @brief Setup an interrupt-driven UART transaction - * + * * @note The TX FIFO will be filled with txData if necessary * Relevant interrupts will be enabled * - * @param req Pointer to details of the transaction + * @param req Pointer to details of the transaction * * @return See \ref MXC_Error_Codes for the list of error return codes. */ @@ -575,18 +597,19 @@ int MXC_UART_TransactionAsync(mxc_uart_req_t *req); /** * @brief Setup a DMA driven UART transaction - * + * * @note The TX FIFO will be filled with txData if necessary - * Relevant interrupts will be enabled - * The DMA channel indicated by the request will be set up to load/unload the FIFOs - * with as few interrupt-based events as possible. The channel will be reset and + * Relevant interrupts will be enabled. + * The DMA channel indicated by the request will be set up to load/unload the FIFOs + * with as few interrupt-based events as possible. The channel will be reset and * returned to the system at the end of the transaction. * - * @param req Pointer to details of the transaction + * @param req Pointer to details of the transaction + * @param dma Pointer to DMA registers used for UART DMA * * @return See \ref MXC_Error_Codes for the list of error return codes. */ -int MXC_UART_TransactionDMA(mxc_uart_req_t *req); +int MXC_UART_TransactionDMA(mxc_uart_req_t *req, mxc_dma_regs_t *dma); /** * @brief The processing function for DMA transactions. @@ -600,23 +623,27 @@ int MXC_UART_TransactionDMA(mxc_uart_req_t *req); void MXC_UART_DMACallback(int ch, int error); /** - * @brief Async callback + * @brief Async callback * - * @param uart The uart - * @param retVal The ret value + * @param uart The uart + * @param[in] retVal The ret value * * @return See \ref MXC_Error_Codes for the list of error return codes. */ int MXC_UART_AsyncCallback(mxc_uart_regs_t *uart, int retVal); +int MXC_UART_TxAsyncCallback(mxc_uart_regs_t *uart, int retVal); +int MXC_UART_RxAsyncCallback(mxc_uart_regs_t *uart, int retVal); /** * @brief stop any async callbacks * - * @param uart The uart + * @param uart The uart * * @return See \ref MXC_Error_Codes for the list of error return codes. */ int MXC_UART_AsyncStop(mxc_uart_regs_t *uart); +int MXC_UART_TxAsyncStop(mxc_uart_regs_t *uart); +int MXC_UART_RxAsyncStop(mxc_uart_regs_t *uart); /** * @brief Abort any asynchronous requests in progress. @@ -630,6 +657,8 @@ int MXC_UART_AsyncStop(mxc_uart_regs_t *uart); * @return See \ref MXC_Error_Codes for the list of error return codes. */ int MXC_UART_AbortAsync(mxc_uart_regs_t *uart); +int MXC_UART_TxAbortAsync(mxc_uart_regs_t *uart); +int MXC_UART_RxAbortAsync(mxc_uart_regs_t *uart); /** * @brief The processing function for asynchronous transactions. @@ -642,8 +671,8 @@ int MXC_UART_AbortAsync(mxc_uart_regs_t *uart); * * @return See \ref MXC_Error_Codes for the list of error return codes. */ -int MXC_UART_AsyncHandler(mxc_uart_regs_t *uart); +int MXC_UART_AsyncHandler(mxc_uart_regs_t *uart); /** * @brief Provide TXCount for asynchronous transactions.. * @@ -651,6 +680,7 @@ int MXC_UART_AsyncHandler(mxc_uart_regs_t *uart); * * @return Returns transmit bytes (in FIFO). */ + uint32_t MXC_UART_GetAsyncTXCount(mxc_uart_req_t *req); /** @@ -731,4 +761,4 @@ int MXC_UART_GetRXDMAChannel(mxc_uart_regs_t *uart); } #endif -#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_UART_H_ +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32570_UART_H_ diff --git a/Libraries/PeriphDrivers/Source/AES/aes_ai87.c b/Libraries/PeriphDrivers/Source/AES/aes_ai87.c index 594d86119ce..ba60f951604 100644 --- a/Libraries/PeriphDrivers/Source/AES/aes_ai87.c +++ b/Libraries/PeriphDrivers/Source/AES/aes_ai87.c @@ -138,12 +138,12 @@ int MXC_AES_Decrypt(mxc_aes_req_t *req) int MXC_AES_TXDMAConfig(void *src_addr, int len) { - return MXC_AES_RevB_TXDMAConfig(src_addr, len); + return MXC_AES_RevB_TXDMAConfig(src_addr, len, MXC_DMA); } int MXC_AES_RXDMAConfig(void *dest_addr, int len) { - return MXC_AES_RevB_RXDMAConfig(dest_addr, len); + return MXC_AES_RevB_RXDMAConfig(dest_addr, len, MXC_DMA); } int MXC_AES_GenericAsync(mxc_aes_req_t *req, uint8_t enc) diff --git a/Libraries/PeriphDrivers/Source/AES/aes_me12.c b/Libraries/PeriphDrivers/Source/AES/aes_me12.c index 87e6b35cb25..60c6eaeeb21 100644 --- a/Libraries/PeriphDrivers/Source/AES/aes_me12.c +++ b/Libraries/PeriphDrivers/Source/AES/aes_me12.c @@ -131,12 +131,12 @@ int MXC_AES_Decrypt(mxc_aes_req_t *req) int MXC_AES_TXDMAConfig(void *src_addr, int len) { - return MXC_AES_RevB_TXDMAConfig(src_addr, len); + return MXC_AES_RevB_TXDMAConfig(src_addr, len, MXC_DMA); } int MXC_AES_RXDMAConfig(void *dest_addr, int len) { - return MXC_AES_RevB_RXDMAConfig(dest_addr, len); + return MXC_AES_RevB_RXDMAConfig(dest_addr, len, MXC_DMA); } int MXC_AES_GenericAsync(mxc_aes_req_t *req, uint8_t enc) diff --git a/Libraries/PeriphDrivers/Source/AES/aes_me15.c b/Libraries/PeriphDrivers/Source/AES/aes_me15.c index d35812e0d27..60ecf1ead79 100644 --- a/Libraries/PeriphDrivers/Source/AES/aes_me15.c +++ b/Libraries/PeriphDrivers/Source/AES/aes_me15.c @@ -155,12 +155,12 @@ int MXC_AES_Decrypt(mxc_aes_req_t *req) int MXC_AES_TXDMAConfig(void *src_addr, int len) { - return MXC_AES_RevB_TXDMAConfig(src_addr, len); + return MXC_AES_RevB_TXDMAConfig(src_addr, len, MXC_DMA); } int MXC_AES_RXDMAConfig(void *dest_addr, int len) { - return MXC_AES_RevB_RXDMAConfig(dest_addr, len); + return MXC_AES_RevB_RXDMAConfig(dest_addr, len, MXC_DMA); } int MXC_AES_GenericAsync(mxc_aes_req_t *req, uint8_t enc) diff --git a/Libraries/PeriphDrivers/Source/AES/aes_me17.c b/Libraries/PeriphDrivers/Source/AES/aes_me17.c index 27ac05bc04a..1cbca9635a9 100644 --- a/Libraries/PeriphDrivers/Source/AES/aes_me17.c +++ b/Libraries/PeriphDrivers/Source/AES/aes_me17.c @@ -132,12 +132,12 @@ int MXC_AES_Decrypt(mxc_aes_req_t *req) int MXC_AES_TXDMAConfig(void *src_addr, int len) { - return MXC_AES_RevB_TXDMAConfig(src_addr, len); + return MXC_AES_RevB_TXDMAConfig(src_addr, len, MXC_DMA); } int MXC_AES_RXDMAConfig(void *dest_addr, int len) { - return MXC_AES_RevB_RXDMAConfig(dest_addr, len); + return MXC_AES_RevB_RXDMAConfig(dest_addr, len, MXC_DMA); } int MXC_AES_GenericAsync(mxc_aes_req_t *req, uint8_t enc) diff --git a/Libraries/PeriphDrivers/Source/AES/aes_me21.c b/Libraries/PeriphDrivers/Source/AES/aes_me21.c index 1eaf61ca5e1..cfb340482a9 100644 --- a/Libraries/PeriphDrivers/Source/AES/aes_me21.c +++ b/Libraries/PeriphDrivers/Source/AES/aes_me21.c @@ -126,12 +126,12 @@ int MXC_AES_Decrypt(mxc_aes_req_t *req) int MXC_AES_TXDMAConfig(void *src_addr, int len) { - return MXC_AES_RevB_TXDMAConfig(src_addr, len); + return MXC_AES_RevB_TXDMAConfig(src_addr, len, MXC_DMA); } int MXC_AES_RXDMAConfig(void *dest_addr, int len) { - return MXC_AES_RevB_RXDMAConfig(dest_addr, len); + return MXC_AES_RevB_RXDMAConfig(dest_addr, len, MXC_DMA); } int MXC_AES_GenericAsync(mxc_aes_req_t *req, uint8_t enc) diff --git a/Libraries/PeriphDrivers/Source/AES/aes_me30.c b/Libraries/PeriphDrivers/Source/AES/aes_me30.c index 63603f4cf83..575f8abedf6 100644 --- a/Libraries/PeriphDrivers/Source/AES/aes_me30.c +++ b/Libraries/PeriphDrivers/Source/AES/aes_me30.c @@ -23,19 +23,20 @@ #include "aes_revb.h" #include "trng.h" #include "trng_revb.h" +#include "dma.h" /* ************************************************************************* */ /* Global Control/Configuration functions */ /* ************************************************************************* */ -int MXC_AES_Init(void) +int MXC_AES_Init(mxc_dma_regs_t *dma) { #ifndef MSDK_NO_GPIO_CLK_INIT MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_AES); MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TRNG); #endif - return MXC_AES_RevB_Init((mxc_aes_revb_regs_t *)MXC_AES); + return MXC_AES_RevB_Init((mxc_aes_revb_regs_t *)MXC_AES, dma); } void MXC_AES_EnableInt(uint32_t interrupt) @@ -123,14 +124,14 @@ int MXC_AES_Decrypt(mxc_aes_req_t *req) return MXC_AES_RevB_Decrypt((mxc_aes_revb_regs_t *)MXC_AES, (mxc_aes_revb_req_t *)req); } -int MXC_AES_TXDMAConfig(void *src_addr, int len) +int MXC_AES_TXDMAConfig(void *src_addr, int len, mxc_dma_regs_t *dma) { - return MXC_AES_RevB_TXDMAConfig(src_addr, len); + return MXC_AES_RevB_TXDMAConfig(src_addr, len, dma); } -int MXC_AES_RXDMAConfig(void *dest_addr, int len) +int MXC_AES_RXDMAConfig(void *dest_addr, int len, mxc_dma_regs_t *dma) { - return MXC_AES_RevB_RXDMAConfig(dest_addr, len); + return MXC_AES_RevB_RXDMAConfig(dest_addr, len, dma); } int MXC_AES_GenericAsync(mxc_aes_req_t *req, uint8_t enc) diff --git a/Libraries/PeriphDrivers/Source/AES/aes_revb.c b/Libraries/PeriphDrivers/Source/AES/aes_revb.c index 240b8b6f21a..77ce01370f1 100644 --- a/Libraries/PeriphDrivers/Source/AES/aes_revb.c +++ b/Libraries/PeriphDrivers/Source/AES/aes_revb.c @@ -33,6 +33,7 @@ /* **** Variable Declaration **** */ typedef struct { uint8_t enc; + mxc_dma_regs_t *dma; uint8_t channelRX; uint8_t channelTX; uint32_t remain; @@ -62,7 +63,7 @@ memcpy32r(uint32_t *dst, const uint32_t *src, unsigned int len) } } -int MXC_AES_RevB_Init(mxc_aes_revb_regs_t *aes) +int MXC_AES_RevB_Init(mxc_aes_revb_regs_t *aes, mxc_dma_regs_t *dma) { aes->ctrl = 0x00; @@ -70,6 +71,8 @@ int MXC_AES_RevB_Init(mxc_aes_revb_regs_t *aes) aes->ctrl |= MXC_F_AES_REVB_CTRL_EN; + dma_state.dma = dma; + return E_NO_ERROR; } @@ -226,7 +229,7 @@ int MXC_AES_RevB_Decrypt(mxc_aes_revb_regs_t *aes, mxc_aes_revb_req_t *req) return MXC_AES_RevB_Generic(aes, req); } -int MXC_AES_RevB_TXDMAConfig(void *src_addr, int len) +int MXC_AES_RevB_TXDMAConfig(void *src_addr, int len, mxc_dma_regs_t *dma) { uint8_t channel; mxc_dma_config_t config; @@ -240,9 +243,16 @@ int MXC_AES_RevB_TXDMAConfig(void *src_addr, int len) return E_BAD_PARAM; } +#if (TARGET_NUM == 32657) + MXC_DMA_Init(dma); + + channel = MXC_DMA_AcquireChannel(dma); +#else MXC_DMA_Init(); channel = MXC_DMA_AcquireChannel(); +#endif + dma_state.channelTX = channel; config.reqsel = MXC_DMA_REQUEST_AESTX; @@ -269,7 +279,12 @@ int MXC_AES_RevB_TXDMAConfig(void *src_addr, int len) MXC_DMA_ConfigChannel(config, srcdst); MXC_DMA_SetCallback(channel, MXC_AES_RevB_DMACallback); +#if (TARGET_NUM == 32657) + MXC_DMA_EnableInt(dma, channel); +#else MXC_DMA_EnableInt(channel); +#endif + MXC_DMA_Start(channel); //MXC_DMA->ch[channel].ctrl |= MXC_F_DMA_CTRL_CTZ_IE; MXC_DMA_SetChannelInterruptEn(channel, 0, 1); @@ -277,7 +292,7 @@ int MXC_AES_RevB_TXDMAConfig(void *src_addr, int len) return E_NO_ERROR; } -int MXC_AES_RevB_RXDMAConfig(void *dest_addr, int len) +int MXC_AES_RevB_RXDMAConfig(void *dest_addr, int len, mxc_dma_regs_t *dma) { if (dest_addr == NULL) { return E_NULL_PTR; @@ -291,9 +306,16 @@ int MXC_AES_RevB_RXDMAConfig(void *dest_addr, int len) mxc_dma_config_t config; mxc_dma_srcdst_t srcdst; +#if (TARGET_NUM == 32657) + MXC_DMA_Init(dma); + + channel = MXC_DMA_AcquireChannel(dma); +#else MXC_DMA_Init(); channel = MXC_DMA_AcquireChannel(); +#endif + dma_state.channelRX = channel; config.reqsel = MXC_DMA_REQUEST_AESRX; @@ -320,7 +342,12 @@ int MXC_AES_RevB_RXDMAConfig(void *dest_addr, int len) MXC_DMA_ConfigChannel(config, srcdst); MXC_DMA_SetCallback(channel, MXC_AES_RevB_DMACallback); +#if (TARGET_NUM == 32657) + MXC_DMA_EnableInt(dma, channel); +#else MXC_DMA_EnableInt(channel); +#endif + MXC_DMA_Start(channel); //MXC_DMA->ch[channel].ctrl |= MXC_F_DMA_CTRL_CTZ_IE; MXC_DMA_SetChannelInterruptEn(channel, 0, 1); @@ -359,7 +386,7 @@ int MXC_AES_RevB_GenericAsync(mxc_aes_revb_regs_t *aes, mxc_aes_revb_req_t *req, aes->ctrl |= MXC_F_AES_REVB_CTRL_DMA_RX_EN; //Enable AES DMA aes->ctrl |= MXC_F_AES_REVB_CTRL_DMA_TX_EN; //Enable AES DMA - if (MXC_AES_RevB_TXDMAConfig(dma_state.inputText, dma_state.remain) != E_NO_ERROR) { + if (MXC_AES_RevB_TXDMAConfig(dma_state.inputText, dma_state.remain, dma_state.dma) != E_NO_ERROR) { return E_BAD_PARAM; } @@ -385,7 +412,7 @@ void MXC_AES_RevB_DMACallback(int ch, int error) if (dma_state.remain < 4) { MXC_AES_Start(); } - MXC_AES_RevB_RXDMAConfig(dma_state.outputText, dma_state.remain); + MXC_AES_RevB_RXDMAConfig(dma_state.outputText, dma_state.remain, dma_state.dma); } else if (dma_state.channelRX == ch) { if (dma_state.remain > 4) { dma_state.remain -= 4; @@ -394,7 +421,7 @@ void MXC_AES_RevB_DMACallback(int ch, int error) } MXC_DMA_ReleaseChannel(dma_state.channelRX); if (dma_state.remain > 0) { - MXC_AES_RevB_TXDMAConfig(dma_state.inputText, dma_state.remain); + MXC_AES_RevB_TXDMAConfig(dma_state.inputText, dma_state.remain, dma_state.dma); } } } diff --git a/Libraries/PeriphDrivers/Source/AES/aes_revb.h b/Libraries/PeriphDrivers/Source/AES/aes_revb.h index 3f00bda64c1..0c8b318a7c3 100644 --- a/Libraries/PeriphDrivers/Source/AES/aes_revb.h +++ b/Libraries/PeriphDrivers/Source/AES/aes_revb.h @@ -26,6 +26,7 @@ #include "aes_revb_regs.h" #include "aeskeys_revb_regs.h" #include "trng_revb_regs.h" +#include "dma.h" /** * @brief Enumeration type to select AES key @@ -60,7 +61,7 @@ typedef struct _mxc_aes_revb_cipher_req_t { mxc_aes_complete_t callback; ///< Callback function } mxc_aes_revb_req_t; -int MXC_AES_RevB_Init(mxc_aes_revb_regs_t *aes); +int MXC_AES_RevB_Init(mxc_aes_revb_regs_t *aes, mxc_dma_regs_t *dma); void MXC_AES_RevB_EnableInt(mxc_aes_revb_regs_t *aes, uint32_t interrupt); void MXC_AES_RevB_DisableInt(mxc_aes_revb_regs_t *aes, uint32_t interrupt); int MXC_AES_RevB_IsBusy(mxc_aes_revb_regs_t *aes); @@ -76,8 +77,8 @@ void MXC_AES_RevB_ClearFlags(mxc_aes_revb_regs_t *aes, uint32_t flags); int MXC_AES_RevB_Generic(mxc_aes_revb_regs_t *aes, mxc_aes_revb_req_t *req); int MXC_AES_RevB_Encrypt(mxc_aes_revb_regs_t *aes, mxc_aes_revb_req_t *req); int MXC_AES_RevB_Decrypt(mxc_aes_revb_regs_t *aes, mxc_aes_revb_req_t *req); -int MXC_AES_RevB_TXDMAConfig(void *src_addr, int len); -int MXC_AES_RevB_RXDMAConfig(void *dest_addr, int len); +int MXC_AES_RevB_TXDMAConfig(void *src_addr, int len, mxc_dma_regs_t *dma); +int MXC_AES_RevB_RXDMAConfig(void *dest_addr, int len, mxc_dma_regs_t *dma); int MXC_AES_RevB_GenericAsync(mxc_aes_revb_regs_t *aes, mxc_aes_revb_req_t *req, uint8_t enc); int MXC_AES_RevB_EncryptAsync(mxc_aes_revb_regs_t *aes, mxc_aes_revb_req_t *req); int MXC_AES_RevB_DecryptAsync(mxc_aes_revb_regs_t *aes, mxc_aes_revb_req_t *req); diff --git a/Libraries/PeriphDrivers/Source/CRC/crc_ai87.c b/Libraries/PeriphDrivers/Source/CRC/crc_ai87.c index 8e09e2dc81c..e75000fe5fc 100644 --- a/Libraries/PeriphDrivers/Source/CRC/crc_ai87.c +++ b/Libraries/PeriphDrivers/Source/CRC/crc_ai87.c @@ -36,7 +36,7 @@ int MXC_CRC_Init(void) MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_CRC); #endif - MXC_CRC_RevA_Init((mxc_crc_reva_regs_t *)MXC_CRC); + MXC_CRC_RevA_Init((mxc_crc_reva_regs_t *)MXC_CRC, MXC_DMA); return E_NO_ERROR; } diff --git a/Libraries/PeriphDrivers/Source/CRC/crc_me15.c b/Libraries/PeriphDrivers/Source/CRC/crc_me15.c index 8e09e2dc81c..e75000fe5fc 100644 --- a/Libraries/PeriphDrivers/Source/CRC/crc_me15.c +++ b/Libraries/PeriphDrivers/Source/CRC/crc_me15.c @@ -36,7 +36,7 @@ int MXC_CRC_Init(void) MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_CRC); #endif - MXC_CRC_RevA_Init((mxc_crc_reva_regs_t *)MXC_CRC); + MXC_CRC_RevA_Init((mxc_crc_reva_regs_t *)MXC_CRC, MXC_DMA); return E_NO_ERROR; } diff --git a/Libraries/PeriphDrivers/Source/CRC/crc_me17.c b/Libraries/PeriphDrivers/Source/CRC/crc_me17.c index 8e09e2dc81c..e75000fe5fc 100644 --- a/Libraries/PeriphDrivers/Source/CRC/crc_me17.c +++ b/Libraries/PeriphDrivers/Source/CRC/crc_me17.c @@ -36,7 +36,7 @@ int MXC_CRC_Init(void) MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_CRC); #endif - MXC_CRC_RevA_Init((mxc_crc_reva_regs_t *)MXC_CRC); + MXC_CRC_RevA_Init((mxc_crc_reva_regs_t *)MXC_CRC, MXC_DMA); return E_NO_ERROR; } diff --git a/Libraries/PeriphDrivers/Source/CRC/crc_me30.c b/Libraries/PeriphDrivers/Source/CRC/crc_me30.c index cf4819eb767..1d1bcf41eb9 100644 --- a/Libraries/PeriphDrivers/Source/CRC/crc_me30.c +++ b/Libraries/PeriphDrivers/Source/CRC/crc_me30.c @@ -23,18 +23,19 @@ #include "crc.h" #include "crc_reva.h" +#include "dma.h" /* ************************************************************************* */ /* Global Control/Configuration functions */ /* ************************************************************************* */ -int MXC_CRC_Init(void) +int MXC_CRC_Init(mxc_dma_regs_t *dma) { #ifndef MSDK_NO_GPIO_CLK_INIT MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_CRC); #endif - MXC_CRC_RevA_Init((mxc_crc_reva_regs_t *)MXC_CRC); + MXC_CRC_RevA_Init((mxc_crc_reva_regs_t *)MXC_CRC, dma); return E_NO_ERROR; } diff --git a/Libraries/PeriphDrivers/Source/CRC/crc_reva.c b/Libraries/PeriphDrivers/Source/CRC/crc_reva.c index 4cdb5e5ebb3..a84b553ab89 100644 --- a/Libraries/PeriphDrivers/Source/CRC/crc_reva.c +++ b/Libraries/PeriphDrivers/Source/CRC/crc_reva.c @@ -33,13 +33,16 @@ /***** Global Variables *****/ static mxc_crc_reva_req_t *CRCreq; +static mxc_dma_regs_t *CRCdma; /* ************************************************************************* */ /* Global Control/Configuration functions */ /* ************************************************************************* */ -int MXC_CRC_RevA_Init(mxc_crc_reva_regs_t *crc) +int MXC_CRC_RevA_Init(mxc_crc_reva_regs_t *crc, mxc_dma_regs_t *dma) { + CRCdma = dma; + crc->ctrl = 0x00; crc->val = 0xFFFFFFFF; return E_NO_ERROR; @@ -160,9 +163,15 @@ int MXC_CRC_RevA_ComputeAsync(mxc_crc_reva_regs_t *crc, mxc_crc_reva_req_t *req) CRCreq = req; +#if (TARGET_NUM == 32657) + MXC_DMA_Init(CRCdma); + + channel = MXC_DMA_AcquireChannel(CRCdma); +#else MXC_DMA_Init(); channel = MXC_DMA_AcquireChannel(); +#endif config.reqsel = MXC_DMA_REQUEST_CRCTX; @@ -183,7 +192,13 @@ int MXC_CRC_RevA_ComputeAsync(mxc_crc_reva_regs_t *crc, mxc_crc_reva_req_t *req) MXC_DMA_ConfigChannel(config, srcdst); MXC_DMA_SetCallback(channel, MXC_CRC_Handler); + +#if (TARGET_NUM == 32657) + MXC_DMA_EnableInt(CRCdma, channel); +#else MXC_DMA_EnableInt(channel); +#endif + MXC_DMA_Start(channel); //MXC_DMA->ch[channel].ctrl |= MXC_F_DMA_CTRL_CTZ_IE; MXC_DMA_SetChannelInterruptEn(channel, 0, 1); diff --git a/Libraries/PeriphDrivers/Source/CRC/crc_reva.h b/Libraries/PeriphDrivers/Source/CRC/crc_reva.h index d4a06efee33..8e2c46f9b34 100644 --- a/Libraries/PeriphDrivers/Source/CRC/crc_reva.h +++ b/Libraries/PeriphDrivers/Source/CRC/crc_reva.h @@ -23,6 +23,7 @@ #include "crc.h" #include "crc_reva_regs.h" +#include "dma.h" /***** CRC Definitions *****/ /** @@ -41,7 +42,7 @@ typedef struct _mxc_crc_reva_req_t { */ typedef enum { CRC_REVA_LSB_FIRST, CRC_REVA_MSB_FIRST } mxc_crc_reva_bitorder_t; -int MXC_CRC_RevA_Init(mxc_crc_reva_regs_t *crc); +int MXC_CRC_RevA_Init(mxc_crc_reva_regs_t *crc, mxc_dma_regs_t *dma); int MXC_CRC_RevA_Shutdown(mxc_crc_reva_regs_t *crc); int MXC_CRC_RevA_Handler(int ch, int error); void MXC_CRC_RevA_SetDirection(mxc_crc_reva_regs_t *crc, mxc_crc_reva_bitorder_t bitOrder); diff --git a/Libraries/PeriphDrivers/Source/DMA/dma_me30.c b/Libraries/PeriphDrivers/Source/DMA/dma_me30.c index a0483bd536d..d0359eaa1da 100644 --- a/Libraries/PeriphDrivers/Source/DMA/dma_me30.c +++ b/Libraries/PeriphDrivers/Source/DMA/dma_me30.c @@ -32,26 +32,33 @@ /****** Functions ******/ -int MXC_DMA_Init(void) +int MXC_DMA_Init(mxc_dma_regs_t *dma) { #ifndef MSDK_NO_GPIO_CLK_INIT - if (!MXC_SYS_IsClockEnabled(MXC_SYS_PERIPH_CLOCK_DMA)) { - MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_DMA); - MXC_SYS_Reset_Periph(MXC_SYS_RESET0_DMA); + if (dma == MXC_DMA0 && !MXC_SYS_IsClockEnabled(MXC_SYS_PERIPH_CLOCK_DMA0)) { + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_DMA0); + MXC_SYS_Reset_Periph(MXC_SYS_RESET0_DMA0); } + // TODO(ME30): There is no periph clock enable register for DMA1 atm + // -Added but it's in feat/ME30 branch. + // Uncomment when merged. + // else if (dma == MXC_DMA1 && !MXC_SYS_IsClockEnabled(MXC_SYS_PERIPH_CLOCK_DMA1)) + // MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_DMA1); + // MXC_SYS_Reset_Periph(MXC_SYS_RESET0_DMA1); + // } #endif - return MXC_DMA_RevA_Init((mxc_dma_reva_regs_t *)MXC_DMA); + return MXC_DMA_RevA_Init((mxc_dma_reva_regs_t *)dma); } -void MXC_DMA_DeInit(void) +void MXC_DMA_DeInit(mxc_dma_regs_t *dma) { - return MXC_DMA_RevA_DeInit((mxc_dma_reva_regs_t *)MXC_DMA); + return MXC_DMA_RevA_DeInit((mxc_dma_reva_regs_t *)dma); } -int MXC_DMA_AcquireChannel(void) +int MXC_DMA_AcquireChannel(mxc_dma_regs_t *dma) { - return MXC_DMA_RevA_AcquireChannel((mxc_dma_reva_regs_t *)MXC_DMA); + return MXC_DMA_RevA_AcquireChannel((mxc_dma_reva_regs_t *)dma); } int MXC_DMA_ReleaseChannel(int ch) @@ -119,14 +126,15 @@ int MXC_DMA_ChannelClearFlags(int ch, int flags) return MXC_DMA_RevA_ChannelClearFlags(ch, flags); } -int MXC_DMA_EnableInt(int ch) +// TODO(DMA): Check ME14 becasue you can only get ME14 intrs from MXC_DMA0. +int MXC_DMA_EnableInt(mxc_dma_regs_t *dma, int ch) { - return MXC_DMA_RevA_EnableInt((mxc_dma_reva_regs_t *)MXC_DMA, ch); + return MXC_DMA_RevA_EnableInt((mxc_dma_reva_regs_t *)dma, ch); } -int MXC_DMA_DisableInt(int ch) +int MXC_DMA_DisableInt(mxc_dma_regs_t *dma, int ch) { - return MXC_DMA_RevA_DisableInt((mxc_dma_reva_regs_t *)MXC_DMA, ch); + return MXC_DMA_RevA_DisableInt((mxc_dma_reva_regs_t *)dma, ch); } int MXC_DMA_Start(int ch) @@ -144,18 +152,18 @@ mxc_dma_ch_regs_t *MXC_DMA_GetCHRegs(int ch) return MXC_DMA_RevA_GetCHRegs(ch); } -void MXC_DMA_Handler(void) +void MXC_DMA_Handler(mxc_dma_regs_t *dma) { - MXC_DMA_RevA_Handler((mxc_dma_reva_regs_t *)MXC_DMA); + MXC_DMA_RevA_Handler((mxc_dma_reva_regs_t *)dma); } -int MXC_DMA_MemCpy(void *dest, void *src, int len, mxc_dma_complete_cb_t callback) +int MXC_DMA_MemCpy(mxc_dma_regs_t *dma, void *dest, void *src, int len, mxc_dma_complete_cb_t callback) { - return MXC_DMA_RevA_MemCpy((mxc_dma_reva_regs_t *)MXC_DMA, dest, src, len, callback); + return MXC_DMA_RevA_MemCpy((mxc_dma_reva_regs_t *)dma, dest, src, len, callback); } -int MXC_DMA_DoTransfer(mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, +int MXC_DMA_DoTransfer(mxc_dma_regs_t *dma, mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, mxc_dma_trans_chain_t callback) { - return MXC_DMA_RevA_DoTransfer((mxc_dma_reva_regs_t *)MXC_DMA, config, firstSrcDst, callback); + return MXC_DMA_RevA_DoTransfer((mxc_dma_reva_regs_t *)dma, config, firstSrcDst, callback); } diff --git a/Libraries/PeriphDrivers/Source/DMA/dma_reva.c b/Libraries/PeriphDrivers/Source/DMA/dma_reva.c index 6b8ac9a8436..05ba7bbbf89 100644 --- a/Libraries/PeriphDrivers/Source/DMA/dma_reva.c +++ b/Libraries/PeriphDrivers/Source/DMA/dma_reva.c @@ -470,7 +470,7 @@ int MXC_DMA_RevA_MemCpy(mxc_dma_reva_regs_t *dma, void *dest, void *src, int len mxc_dma_srcdst_t transfer; int channel; -#if TARGET_NUM == 32665 +#if (TARGET_NUM == 32665 || TARGET_NUM == 32657) channel = MXC_DMA_AcquireChannel((mxc_dma_regs_t *)dma); #else channel = MXC_DMA_AcquireChannel(); @@ -500,7 +500,11 @@ int MXC_DMA_RevA_MemCpy(mxc_dma_reva_regs_t *dma, void *dest, void *src, int len return retval; } +#if (TARGET_NUM == 32657) + retval = MXC_DMA_EnableInt((mxc_dma_regs_t *)dma, channel); +#else retval = MXC_DMA_EnableInt(channel); +#endif if (retval != E_NO_ERROR) { return retval; @@ -535,7 +539,7 @@ int MXC_DMA_RevA_DoTransfer(mxc_dma_reva_regs_t *dma, mxc_dma_config_t config, { int retval, channel; -#if TARGET_NUM == 32665 +#if (TARGET_NUM == 32665 || TARGET_NUM == 32657) channel = MXC_DMA_AcquireChannel((mxc_dma_regs_t *)dma); #else channel = MXC_DMA_AcquireChannel(); @@ -553,7 +557,11 @@ int MXC_DMA_RevA_DoTransfer(mxc_dma_reva_regs_t *dma, mxc_dma_config_t config, return retval; } +#if (TARGET_NUM == 32657) + retval = MXC_DMA_EnableInt((mxc_dma_regs_t *)dma, channel); +#else retval = MXC_DMA_EnableInt(channel); +#endif if (retval != E_NO_ERROR) { return retval; diff --git a/Libraries/PeriphDrivers/Source/FLC/flc_me30.c b/Libraries/PeriphDrivers/Source/FLC/flc_me30.c index 961a912434c..fa8f12b072e 100644 --- a/Libraries/PeriphDrivers/Source/FLC/flc_me30.c +++ b/Libraries/PeriphDrivers/Source/FLC/flc_me30.c @@ -27,7 +27,7 @@ #include "mcr_regs.h" // For ECCEN registers. //****************************************************************************** -void MXC_FLC_ME17_Flash_Operation(void) +void MXC_FLC_ME30_Flash_Operation(void) { /* This function should be called after modifying the contents of flash memory. @@ -44,10 +44,10 @@ void MXC_FLC_ME17_Flash_Operation(void) */ /* Flush all instruction caches */ - MXC_GCR->sysctrl |= MXC_F_GCR_SYSCTRL_ICC0_FLUSH; + MXC_GCR->sysctrl |= MXC_F_GCR_SYSCTRL_ICC_FLUSH; /* Wait for flush to complete */ - while (MXC_GCR->sysctrl & MXC_F_GCR_SYSCTRL_ICC0_FLUSH) {} + while (MXC_GCR->sysctrl & MXC_F_GCR_SYSCTRL_ICC_FLUSH) {} // Clear the line fill buffer by reading 2 pages from flash volatile uint32_t *line_addr; @@ -59,21 +59,7 @@ void MXC_FLC_ME17_Flash_Operation(void) } //****************************************************************************** -int MXC_FLC_ME17_GetByAddress(mxc_flc_regs_t **flc, uint32_t addr) -{ - if ((addr >= MXC_FLASH_MEM_BASE) && (addr < (MXC_FLASH_MEM_BASE + MXC_FLASH_MEM_SIZE))) { - *flc = MXC_FLC0; - } else if ((addr >= MXC_INFO_MEM_BASE) && (addr < (MXC_INFO_MEM_BASE + MXC_INFO_MEM_SIZE))) { - *flc = MXC_FLC0; - } else { - return E_BAD_PARAM; - } - - return E_NO_ERROR; -} - -//****************************************************************************** -int MXC_FLC_ME17_GetPhysicalAddress(uint32_t addr, uint32_t *result) +int MXC_FLC_ME30_GetPhysicalAddress(uint32_t addr, uint32_t *result) { if ((addr >= MXC_FLASH_MEM_BASE) && (addr < (MXC_FLASH_MEM_BASE + MXC_FLASH_MEM_SIZE))) { *result = addr & (MXC_FLASH_MEM_SIZE - 1); @@ -113,21 +99,15 @@ int MXC_FLC_PageErase(uint32_t address) { int err; uint32_t addr; - mxc_flc_regs_t *flc = NULL; - // Get FLC Instance - if ((err = MXC_FLC_ME17_GetByAddress(&flc, address)) != E_NO_ERROR) { + if ((err = MXC_FLC_ME30_GetPhysicalAddress(address, &addr)) < E_NO_ERROR) { return err; } - if ((err = MXC_FLC_ME17_GetPhysicalAddress(address, &addr)) < E_NO_ERROR) { - return err; - } - - err = MXC_FLC_RevA_PageErase((mxc_flc_reva_regs_t *)flc, addr); + err = MXC_FLC_RevA_PageErase((mxc_flc_reva_regs_t *)MXC_FLC, addr); // Flush the cache - MXC_FLC_ME17_Flash_Operation(); + MXC_FLC_ME30_Flash_Operation(); return err; } @@ -142,7 +122,6 @@ __attribute__((section(".flashprog"))) int MXC_FLC_Write128(uint32_t address, uint32_t *data) { int err; - mxc_flc_regs_t *flc = NULL; uint32_t addr; // Address checked if it is 128-bit aligned @@ -150,19 +129,14 @@ int MXC_FLC_Write128(uint32_t address, uint32_t *data) return E_BAD_PARAM; } - // Get FLC Instance - if ((err = MXC_FLC_ME17_GetByAddress(&flc, address)) != E_NO_ERROR) { + if ((err = MXC_FLC_ME30_GetPhysicalAddress(address, &addr)) < E_NO_ERROR) { return err; } - if ((err = MXC_FLC_ME17_GetPhysicalAddress(address, &addr)) < E_NO_ERROR) { - return err; - } - - err = MXC_FLC_RevA_Write128((mxc_flc_reva_regs_t *)flc, addr, data); + err = MXC_FLC_RevA_Write128((mxc_flc_reva_regs_t *)MXC_FLC, addr, data); // Flush the cache - MXC_FLC_ME17_Flash_Operation(); + MXC_FLC_ME30_Flash_Operation(); return err; } @@ -172,7 +146,6 @@ int MXC_FLC_Write32(uint32_t address, uint32_t data) { uint32_t addr, aligned; int err; - mxc_flc_regs_t *flc = NULL; // Address checked if it is byte addressable if (address & 0x3) { @@ -182,19 +155,14 @@ int MXC_FLC_Write32(uint32_t address, uint32_t data) // Align address to 128-bit word aligned = address & 0xfffffff0; - // Get FLC Instance - if ((err = MXC_FLC_ME17_GetByAddress(&flc, address)) != E_NO_ERROR) { + if ((err = MXC_FLC_ME30_GetPhysicalAddress(aligned, &addr)) < E_NO_ERROR) { return err; } - if ((err = MXC_FLC_ME17_GetPhysicalAddress(aligned, &addr)) < E_NO_ERROR) { - return err; - } - - err = MXC_FLC_RevA_Write32Using128((mxc_flc_reva_regs_t *)flc, address, data, addr); + err = MXC_FLC_RevA_Write32Using128((mxc_flc_reva_regs_t *)MXC_FLC, address, data, addr); // Flush the cache - MXC_FLC_ME17_Flash_Operation(); + MXC_FLC_ME30_Flash_Operation(); return err; } @@ -202,49 +170,26 @@ int MXC_FLC_Write32(uint32_t address, uint32_t data) //****************************************************************************** int MXC_FLC_MassErase(void) { - int err, i; - mxc_flc_regs_t *flc; - - for (i = 0; i < MXC_FLC_INSTANCES; i++) { - flc = MXC_FLC_GET_FLC(i); - - err = MXC_FLC_RevA_MassErase((mxc_flc_reva_regs_t *)flc); + int err; - // Flush the cache - MXC_FLC_ME17_Flash_Operation(); + err = MXC_FLC_RevA_MassErase((mxc_flc_reva_regs_t *)MXC_FLC); - if (err != E_NO_ERROR) { - return err; - } - } + // Flush the cache + MXC_FLC_ME30_Flash_Operation(); - return E_NO_ERROR; + return err; } //****************************************************************************** int MXC_FLC_UnlockInfoBlock(uint32_t address) { - int err; - mxc_flc_regs_t *flc; - - if ((err = MXC_FLC_ME17_GetByAddress(&flc, address)) != E_NO_ERROR) { - return err; - } - - return MXC_FLC_RevA_UnlockInfoBlock((mxc_flc_reva_regs_t *)flc, address); + return MXC_FLC_RevA_UnlockInfoBlock((mxc_flc_reva_regs_t *)MXC_FLC, address); } //****************************************************************************** int MXC_FLC_LockInfoBlock(uint32_t address) { - int err; - mxc_flc_regs_t *flc; - - if ((err = MXC_FLC_ME17_GetByAddress(&flc, address)) != E_NO_ERROR) { - return err; - } - - return MXC_FLC_RevA_LockInfoBlock((mxc_flc_reva_regs_t *)flc, address); + return MXC_FLC_RevA_LockInfoBlock((mxc_flc_reva_regs_t *)MXC_FLC, address); } //****************************************************************************** diff --git a/Libraries/PeriphDrivers/Source/GPIO/gpio_me30.c b/Libraries/PeriphDrivers/Source/GPIO/gpio_me30.c index 5b3312315d7..bddc113d0b0 100644 --- a/Libraries/PeriphDrivers/Source/GPIO/gpio_me30.c +++ b/Libraries/PeriphDrivers/Source/GPIO/gpio_me30.c @@ -24,7 +24,6 @@ #include "gpio_reva.h" #include "gpio_common.h" #include "mxc_sys.h" -#include "lpgcr_regs.h" #include "mcr_regs.h" #include "pwrseq_regs.h" @@ -53,14 +52,6 @@ int MXC_GPIO_Init(uint32_t portmask) MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_GPIO0); } - if (portmask & 0x2) { - MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_GPIO1); - } - - if (portmask & 0x4) { - MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_GPIO2); - } - return MXC_GPIO_Common_Init(portmask); } @@ -70,14 +61,6 @@ int MXC_GPIO_Shutdown(uint32_t portmask) MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_GPIO0); } - if (portmask & 0x2) { - MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_GPIO1); - } - - if (portmask & 0x4) { - MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_GPIO2); - } - return E_NO_ERROR; } @@ -87,14 +70,6 @@ int MXC_GPIO_Reset(uint32_t portmask) MXC_SYS_Reset_Periph(MXC_SYS_RESET0_GPIO0); } - if (portmask & 0x2) { - MXC_SYS_Reset_Periph(MXC_SYS_RESET0_GPIO1); - } - - if (portmask & 0x4) { - MXC_SYS_Reset_Periph(MXC_SYS_RESET_GPIO2); - } - return E_NO_ERROR; } @@ -118,88 +93,46 @@ int MXC_GPIO_Config(const mxc_gpio_cfg_t *cfg) return error; } - if (cfg->port == MXC_GPIO3) { - switch (cfg->func) { - case MXC_GPIO_FUNC_IN: - MXC_MCR->gpio3_ctrl &= ~(P30_OUT_EN(cfg->mask) | P31_OUT_EN(cfg->mask)); - MXC_MCR->outen &= ~(SQWAVE_OUT_EN(cfg->mask) | PDOWN_OUT_EN(cfg->mask)); - break; - - case MXC_GPIO_FUNC_OUT: - MXC_MCR->gpio3_ctrl |= P30_OUT_EN(cfg->mask) | P31_OUT_EN(cfg->mask); - MXC_MCR->outen &= ~(SQWAVE_OUT_EN(cfg->mask) | PDOWN_OUT_EN(cfg->mask)); - break; - - case MXC_GPIO_FUNC_ALT1: - MXC_MCR->gpio3_ctrl |= P30_OUT_EN(cfg->mask) | P31_OUT_EN(cfg->mask); - MXC_MCR->outen |= SQWAVE_OUT_EN(cfg->mask) | PDOWN_OUT_EN(cfg->mask); - break; - - default: - return E_NOT_SUPPORTED; - } - - switch (cfg->pad) { - case MXC_GPIO_PAD_NONE: - MXC_MCR->gpio3_ctrl |= P30_PULL_DIS(cfg->mask) | P31_PULL_DIS(cfg->mask); - break; - - case MXC_GPIO_PAD_PULL_UP: - case MXC_GPIO_PAD_WEAK_PULL_UP: - MXC_MCR->gpio3_ctrl |= P30_DATA_OUT(cfg->mask) | P31_DATA_OUT(cfg->mask); - MXC_MCR->gpio3_ctrl &= ~(P30_PULL_DIS(cfg->mask) | P31_PULL_DIS(cfg->mask)); - break; - - case MXC_GPIO_PAD_PULL_DOWN: - case MXC_GPIO_PAD_WEAK_PULL_DOWN: - MXC_MCR->gpio3_ctrl &= ~(P30_DATA_OUT(cfg->mask) | P31_DATA_OUT(cfg->mask)); - MXC_MCR->gpio3_ctrl &= ~(P30_PULL_DIS(cfg->mask) | P31_PULL_DIS(cfg->mask)); - break; - - default: - return E_NOT_SUPPORTED; - } - } else { - // Configure alternate function - error = MXC_GPIO_RevA_SetAF((mxc_gpio_reva_regs_t *)gpio, cfg->func, cfg->mask); - if (error != E_NO_ERROR) { - return error; - } - - // Configure the pad - switch (cfg->pad) { - case MXC_GPIO_PAD_NONE: - gpio->padctrl0 &= ~cfg->mask; - gpio->padctrl1 &= ~cfg->mask; - break; - - case MXC_GPIO_PAD_WEAK_PULL_UP: - gpio->padctrl0 |= cfg->mask; - gpio->padctrl1 &= ~cfg->mask; - gpio->ps &= ~cfg->mask; - break; - - case MXC_GPIO_PAD_PULL_UP: - gpio->padctrl0 |= cfg->mask; - gpio->padctrl1 &= ~cfg->mask; - gpio->ps |= cfg->mask; - break; - - case MXC_GPIO_PAD_WEAK_PULL_DOWN: - gpio->padctrl0 &= ~cfg->mask; - gpio->padctrl1 |= cfg->mask; - gpio->ps &= ~cfg->mask; - break; - - case MXC_GPIO_PAD_PULL_DOWN: - gpio->padctrl0 &= ~cfg->mask; - gpio->padctrl1 |= cfg->mask; - gpio->ps |= cfg->mask; - break; - - default: - return E_BAD_PARAM; - } + // Configure alternate function + error = MXC_GPIO_RevA_SetAF((mxc_gpio_reva_regs_t *)gpio, cfg->func, cfg->mask); + if (error != E_NO_ERROR) { + return error; + } + + // Configure the pad + // TODO(ME30): "ps" (weak vs strong pull-up/down select) register field missing + switch (cfg->pad) { + case MXC_GPIO_PAD_NONE: + gpio->padctrl0 &= ~cfg->mask; + gpio->padctrl1 &= ~cfg->mask; + break; + + case MXC_GPIO_PAD_WEAK_PULL_UP: + gpio->padctrl0 |= cfg->mask; + gpio->padctrl1 &= ~cfg->mask; + // gpio->ps &= ~cfg->mask; + break; + + case MXC_GPIO_PAD_PULL_UP: + gpio->padctrl0 |= cfg->mask; + gpio->padctrl1 &= ~cfg->mask; + // gpio->ps |= cfg->mask; + break; + + case MXC_GPIO_PAD_WEAK_PULL_DOWN: + gpio->padctrl0 &= ~cfg->mask; + gpio->padctrl1 |= cfg->mask; + // gpio->ps &= ~cfg->mask; + break; + + case MXC_GPIO_PAD_PULL_DOWN: + gpio->padctrl0 &= ~cfg->mask; + gpio->padctrl1 |= cfg->mask; + // gpio->ps |= cfg->mask; + break; + + default: + return E_BAD_PARAM; } // Configure the drive strength @@ -213,122 +146,54 @@ int MXC_GPIO_Config(const mxc_gpio_cfg_t *cfg) /* ************************************************************************** */ uint32_t MXC_GPIO_InGet(mxc_gpio_regs_t *port, uint32_t mask) { - uint32_t in = 0; - - if (port == MXC_GPIO3) { - if (MXC_MCR->gpio3_ctrl & P30_DATA_IN(mask)) { - in |= MXC_GPIO_PIN_0; - } - - if (MXC_MCR->gpio3_ctrl & P31_DATA_IN(mask)) { - in |= MXC_GPIO_PIN_1; - } - - return in; - } - return MXC_GPIO_RevA_InGet((mxc_gpio_reva_regs_t *)port, mask); } /* ************************************************************************** */ void MXC_GPIO_OutSet(mxc_gpio_regs_t *port, uint32_t mask) { - if (port == MXC_GPIO3) { - MXC_MCR->gpio3_ctrl |= P30_DATA_OUT(mask) | P31_DATA_OUT(mask); - return; - } - MXC_GPIO_RevA_OutSet((mxc_gpio_reva_regs_t *)port, mask); } /* ************************************************************************** */ void MXC_GPIO_OutClr(mxc_gpio_regs_t *port, uint32_t mask) { - if (port == MXC_GPIO3) { - MXC_MCR->gpio3_ctrl &= ~(P30_DATA_OUT(mask) | P31_DATA_OUT(mask)); - return; - } - MXC_GPIO_RevA_OutClr((mxc_gpio_reva_regs_t *)port, mask); } /* ************************************************************************** */ uint32_t MXC_GPIO_OutGet(mxc_gpio_regs_t *port, uint32_t mask) { - uint32_t out = 0; - - if (port == MXC_GPIO3) { - if (MXC_MCR->gpio3_ctrl & P30_DATA_OUT(mask)) { - out |= MXC_GPIO_PIN_0; - } - - if (MXC_MCR->gpio3_ctrl & P31_DATA_OUT(mask)) { - out |= MXC_GPIO_PIN_1; - } - - return out; - } - return MXC_GPIO_RevA_OutGet((mxc_gpio_reva_regs_t *)port, mask); } /* ************************************************************************** */ void MXC_GPIO_OutPut(mxc_gpio_regs_t *port, uint32_t mask, uint32_t val) { - if (port == MXC_GPIO3) { - uint32_t gpio3_cp = MXC_MCR->gpio3_ctrl & ~(P30_DATA_OUT(mask) | P31_DATA_OUT(mask)); - - MXC_MCR->gpio3_ctrl = gpio3_cp | P30_DATA_OUT((mask & val)) | P31_DATA_OUT((mask & val)); - return; - } - MXC_GPIO_RevA_OutPut((mxc_gpio_reva_regs_t *)port, mask, val); } /* ************************************************************************** */ void MXC_GPIO_OutToggle(mxc_gpio_regs_t *port, uint32_t mask) { - if (port == MXC_GPIO3) { - MXC_MCR->gpio3_ctrl ^= P30_DATA_OUT(mask) | P31_DATA_OUT(mask); - return; - } - MXC_GPIO_RevA_OutToggle((mxc_gpio_reva_regs_t *)port, mask); } /* ************************************************************************** */ int MXC_GPIO_IntConfig(const mxc_gpio_cfg_t *cfg, mxc_gpio_int_pol_t pol) { - if (cfg->port == MXC_GPIO3) { - if (pol != MXC_GPIO_INT_BOTH) { - return E_NOT_SUPPORTED; - } - - return E_NO_ERROR; - } - return MXC_GPIO_RevA_IntConfig(cfg, pol); } /* ************************************************************************** */ void MXC_GPIO_EnableInt(mxc_gpio_regs_t *port, uint32_t mask) { - if (port == MXC_GPIO3) { - MXC_PWRSEQ->lpwken3 |= mask; - return; - } - MXC_GPIO_RevA_EnableInt((mxc_gpio_reva_regs_t *)port, mask); } /* ************************************************************************** */ void MXC_GPIO_DisableInt(mxc_gpio_regs_t *port, uint32_t mask) { - if (port == MXC_GPIO3) { - MXC_PWRSEQ->lpwken3 &= ~mask; - return; - } - MXC_GPIO_RevA_DisableInt((mxc_gpio_reva_regs_t *)port, mask); } @@ -347,67 +212,36 @@ void MXC_GPIO_Handler(unsigned int port) /* ************************************************************************** */ void MXC_GPIO_ClearFlags(mxc_gpio_regs_t *port, uint32_t flags) { - if (port == MXC_GPIO3) { - MXC_PWRSEQ->lpwkst3 = flags; - return; - } - MXC_GPIO_RevA_ClearFlags((mxc_gpio_reva_regs_t *)port, flags); } /* ************************************************************************** */ uint32_t MXC_GPIO_GetFlags(mxc_gpio_regs_t *port) { - if (port == MXC_GPIO3) { - return MXC_PWRSEQ->lpwkst3; - } - return MXC_GPIO_RevA_GetFlags((mxc_gpio_reva_regs_t *)port); } /* ************************************************************************** */ int MXC_GPIO_SetVSSEL(mxc_gpio_regs_t *port, mxc_gpio_vssel_t vssel, uint32_t mask) { - if (port == MXC_GPIO3) { - if (vssel == MXC_GPIO_VSSEL_VDDIO) { - return E_NOT_SUPPORTED; - } - - return E_NO_ERROR; - } - return MXC_GPIO_RevA_SetVSSEL((mxc_gpio_reva_regs_t *)port, vssel, mask); } /* ************************************************************************** */ void MXC_GPIO_SetWakeEn(mxc_gpio_regs_t *port, uint32_t mask) { - if (port == MXC_GPIO3) { - MXC_PWRSEQ->lpwken3 |= mask; - return; - } - MXC_GPIO_RevA_SetWakeEn((mxc_gpio_reva_regs_t *)port, mask); } /* ************************************************************************** */ void MXC_GPIO_ClearWakeEn(mxc_gpio_regs_t *port, uint32_t mask) { - if (port == MXC_GPIO3) { - MXC_PWRSEQ->lpwken3 &= ~mask; - return; - } - MXC_GPIO_RevA_ClearWakeEn((mxc_gpio_reva_regs_t *)port, mask); } /* ************************************************************************** */ uint32_t MXC_GPIO_GetWakeEn(mxc_gpio_regs_t *port) { - if (port == MXC_GPIO3) { - return MXC_PWRSEQ->lpwken3; - } - return MXC_GPIO_RevA_GetWakeEn((mxc_gpio_reva_regs_t *)port); } diff --git a/Libraries/PeriphDrivers/Source/RTC/rtc_me30.c b/Libraries/PeriphDrivers/Source/RTC/rtc_me30.c index 6d6eefe2757..df0dac1d216 100644 --- a/Libraries/PeriphDrivers/Source/RTC/rtc_me30.c +++ b/Libraries/PeriphDrivers/Source/RTC/rtc_me30.c @@ -222,13 +222,13 @@ int MXC_RTC_TrimCrystal(void) /* Wait for an RTC edge */ MXC_RTC_ClearFlags(MXC_RTC_GetFlags()); - while (!(MXC_RTC->ctrl & MXC_F_RTC_CTRL_SSEC_ALARM)) {} + while (!(MXC_RTC->ctrl & MXC_F_RTC_CTRL_SSEC_ALARM_IF)) {} MXC_TMR_Start(MXC_TMR3); /* Wait for an RTC edge */ MXC_RTC_ClearFlags(MXC_RTC_GetFlags()); - while (!(MXC_RTC->ctrl & MXC_F_RTC_CTRL_SSEC_ALARM)) {} + while (!(MXC_RTC->ctrl & MXC_F_RTC_CTRL_SSEC_ALARM_IF)) {} /* Capture the TMR count and adjust for processing delay */ elapsed = MXC_TMR_GetCount(MXC_TMR3); diff --git a/Libraries/PeriphDrivers/Source/SPI/spi_me30.c b/Libraries/PeriphDrivers/Source/SPI/spi_me30.c index da6225abb7b..3d75b2bcd37 100644 --- a/Libraries/PeriphDrivers/Source/SPI/spi_me30.c +++ b/Libraries/PeriphDrivers/Source/SPI/spi_me30.c @@ -66,9 +66,8 @@ int MXC_SPI_Init(mxc_spi_regs_t *spi, int masterMode, int quadModeUsed, int numS } // Configure GPIO for spi - if (spi == MXC_SPI1) { - MXC_SYS_Reset_Periph(MXC_SYS_RESET0_SPI1); - MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_SPI1); + MXC_SYS_Reset_Periph(MXC_SYS_RESET0_SPI); + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_SPI); #if (TARGET != MAX78000 || TARGET_NUM == 32655) @@ -86,87 +85,37 @@ int MXC_SPI_Init(mxc_spi_regs_t *spi, int masterMode, int quadModeUsed, int numS } #endif - //clear mask - gpio_cfg_spi.mask = 0; + //clear mask + gpio_cfg_spi.mask = 0; - // check rest of the pins - if (pins.clock) { - gpio_cfg_spi.mask |= MXC_GPIO_PIN_23; - } - - if (pins.miso) { - gpio_cfg_spi.mask |= MXC_GPIO_PIN_22; - } - - if (pins.mosi) { - gpio_cfg_spi.mask |= MXC_GPIO_PIN_21; - } - - if (pins.sdio2) { - gpio_cfg_spi.mask |= MXC_GPIO_PIN_24; - } - - if (pins.sdio3) { - gpio_cfg_spi.mask |= MXC_GPIO_PIN_25; - } - - if (pins.ss0) { - gpio_cfg_spi.mask |= MXC_GPIO_PIN_20; - } - - gpio_cfg_spi.func = MXC_GPIO_FUNC_ALT1; -#ifdef MXC_SPI0 - } else if (spi == MXC_SPI0) { - MXC_SYS_Reset_Periph(MXC_SYS_RESET1_SPI0); - MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_SPI0); - - //Define pins - if (pins.ss1) { - gpio_cfg_spi.mask = MXC_GPIO_PIN_11; - gpio_cfg_spi.func = MXC_GPIO_FUNC_ALT2; - MXC_GPIO_Config(&gpio_cfg_spi); - } - - if (pins.ss2) { - gpio_cfg_spi.func = MXC_GPIO_FUNC_ALT2; - gpio_cfg_spi.mask = MXC_GPIO_PIN_10; - MXC_GPIO_Config(&gpio_cfg_spi); - } - - //clear mask - gpio_cfg_spi.mask = 0; - - // check rest of the pins - if (pins.clock) { - gpio_cfg_spi.mask |= MXC_GPIO_PIN_7; - } - - if (pins.miso) { - gpio_cfg_spi.mask |= MXC_GPIO_PIN_6; - } + // TODO(ME30): Validate pin assignments + // check rest of the pins + if (pins.clock) { + gpio_cfg_spi.mask |= MXC_GPIO_PIN_23; + } - if (pins.mosi) { - gpio_cfg_spi.mask |= MXC_GPIO_PIN_5; - } + if (pins.miso) { + gpio_cfg_spi.mask |= MXC_GPIO_PIN_22; + } - if (pins.sdio2) { - gpio_cfg_spi.mask |= MXC_GPIO_PIN_8; - } + if (pins.mosi) { + gpio_cfg_spi.mask |= MXC_GPIO_PIN_21; + } - if (pins.sdio3) { - gpio_cfg_spi.mask |= MXC_GPIO_PIN_9; - } + if (pins.sdio2) { + gpio_cfg_spi.mask |= MXC_GPIO_PIN_24; + } - if (pins.ss0) { - gpio_cfg_spi.mask |= MXC_GPIO_PIN_4; - } + if (pins.sdio3) { + gpio_cfg_spi.mask |= MXC_GPIO_PIN_25; + } - gpio_cfg_spi.func = MXC_GPIO_FUNC_ALT1; -#endif - } else { - return E_NO_DEVICE; + if (pins.ss0) { + gpio_cfg_spi.mask |= MXC_GPIO_PIN_20; } + gpio_cfg_spi.func = MXC_GPIO_FUNC_ALT1; + MXC_GPIO_Config(&gpio_cfg_spi); #else (void)pins; @@ -185,15 +134,7 @@ int MXC_SPI_Shutdown(mxc_spi_regs_t *spi) MXC_SPI_RevA1_Shutdown((mxc_spi_reva_regs_t *)spi); - if (spi == MXC_SPI1) { - MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_SPI1); -#ifdef MXC_SPI0 - } else if (spi == MXC_SPI0) { - MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_SPI0); -#endif - } else { - return E_NO_DEVICE; - } + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_SPI); return E_NO_ERROR; } @@ -207,42 +148,33 @@ int MXC_SPI_GetPeripheralClock(mxc_spi_regs_t *spi) { int retval; - if (spi == MXC_SPI1) { - retval = PeripheralClock; -#ifdef MXC_SPI0 // SPI0 is not accessible from the RISC core. - } else if (spi == MXC_SPI0) { - int sys_clk = (MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_SYSCLK_SEL) >> - MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS; - switch (sys_clk) { - case MXC_SYS_CLOCK_IPO: - retval = IPO_FREQ; - break; - case MXC_SYS_CLOCK_IBRO: - retval = IBRO_FREQ; - break; - case MXC_SYS_CLOCK_ISO: - retval = ISO_FREQ; - break; - case MXC_SYS_CLOCK_INRO: - retval = INRO_FREQ; - break; - case MXC_SYS_CLOCK_ERTCO: - retval = ERTCO_FREQ; - break; - case MXC_SYS_CLOCK_EXTCLK: - retval = EXTCLK_FREQ; - break; + // TODO(ME30): Validate this logic + int sys_clk = (MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_SYSCLK_SEL) >> + MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS; + switch (sys_clk) { + case MXC_SYS_CLOCK_IPO: + retval = IPO_FREQ; + break; + case MXC_SYS_CLOCK_IBRO: + retval = IBRO_FREQ; + break; + case MXC_SYS_CLOCK_INRO: + retval = INRO_FREQ; + break; + case MXC_SYS_CLOCK_ERTCO: + retval = ERTCO_FREQ; + break; + // TODO(ME30): EXTCLK definition is missing from registers + // case MXC_SYS_CLOCK_EXTCLK: + // retval = EXTCLK_FREQ; + // break; #if TARGET_NUM == 32655 || TARGET_NUM == 32680 case MXC_SYS_CLOCK_ERFO: retval = ERFO_FREQ; break; #endif - default: - return E_BAD_STATE; - } -#endif // MXC_SPI0 - } else { - return E_BAD_PARAM; + default: + return E_BAD_STATE; } retval /= 2; @@ -405,7 +337,7 @@ int MXC_SPI_MasterTransactionAsync(mxc_spi_req_t *req) return MXC_SPI_RevA1_MasterTransactionAsync((mxc_spi_reva_req_t *)req); } -int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t *req) +int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t *req, mxc_dma_regs_t *dma) { int reqselTx = -1; int reqselRx = -1; @@ -445,8 +377,7 @@ int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t *req) } } - return MXC_SPI_RevA1_MasterTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx, - MXC_DMA); + return MXC_SPI_RevA1_MasterTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx, dma); } int MXC_SPI_SlaveTransaction(mxc_spi_req_t *req) @@ -459,7 +390,7 @@ int MXC_SPI_SlaveTransactionAsync(mxc_spi_req_t *req) return MXC_SPI_RevA1_SlaveTransactionAsync((mxc_spi_reva_req_t *)req); } -int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t *req) +int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t *req, mxc_dma_regs_t *dma) { int reqselTx = -1; int reqselRx = -1; @@ -501,8 +432,7 @@ int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t *req) } } - return MXC_SPI_RevA1_SlaveTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx, - MXC_DMA); + return MXC_SPI_RevA1_SlaveTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx, dma); } int MXC_SPI_SetDefaultTXData(mxc_spi_regs_t *spi, unsigned int defaultTXData) diff --git a/Libraries/PeriphDrivers/Source/SPI/spi_reva1.c b/Libraries/PeriphDrivers/Source/SPI/spi_reva1.c index 4c7fd64e6dc..74b8871e5f3 100644 --- a/Libraries/PeriphDrivers/Source/SPI/spi_reva1.c +++ b/Libraries/PeriphDrivers/Source/SPI/spi_reva1.c @@ -952,7 +952,7 @@ int MXC_SPI_RevA1_MasterTransactionDMA(mxc_spi_reva_req_t *req, int reqselTx, in // for non-MT mode do this setup every time, for MT mode only first time if ((states[spi_num].mtMode == 0) || ((states[spi_num].mtMode == 1) && (states[spi_num].mtFirstTrans == 1))) { -#if TARGET_NUM == 32665 +#if (TARGET_NUM == 32665 || TARGET_NUM == 32657) MXC_DMA_Init(dma); states[spi_num].channelTx = MXC_DMA_AcquireChannel(dma); states[spi_num].channelRx = MXC_DMA_AcquireChannel(dma); @@ -1009,7 +1009,13 @@ int MXC_SPI_RevA1_MasterTransactionDMA(mxc_spi_reva_req_t *req, int reqselTx, in //tx if (req->txData != NULL && !tx_is_complete) { MXC_DMA_SetCallback(states[spi_num].channelTx, MXC_SPI_RevA1_DMACallback); + +#if (TARGET_NUM == 32657) + MXC_DMA_EnableInt(dma, states[spi_num].channelTx); +#else MXC_DMA_EnableInt(states[spi_num].channelTx); +#endif + config.reqsel = (mxc_dma_reqsel_t)reqselTx; config.ch = states[spi_num].channelTx; advConfig.ch = states[spi_num].channelTx; @@ -1049,7 +1055,13 @@ int MXC_SPI_RevA1_MasterTransactionDMA(mxc_spi_reva_req_t *req, int reqselTx, in // rx if (req->rxData != NULL && !rx_is_complete) { MXC_DMA_SetCallback(states[spi_num].channelRx, MXC_SPI_RevA1_DMACallback); + +#if (TARGET_NUM == 32657) + MXC_DMA_EnableInt(dma, states[spi_num].channelRx); +#else MXC_DMA_EnableInt(states[spi_num].channelRx); +#endif + config.reqsel = (mxc_dma_reqsel_t)reqselRx; config.ch = states[spi_num].channelRx; config.srcinc_en = 0; @@ -1160,7 +1172,7 @@ int MXC_SPI_RevA1_SlaveTransactionDMA(mxc_spi_reva_req_t *req, int reqselTx, int // for non-MT mode do this setup every time, for MT mode only first time if ((states[spi_num].mtMode == 0) || ((states[spi_num].mtMode == 1) && (states[spi_num].mtFirstTrans == 1))) { -#if TARGET_NUM == 32665 +#if (TARGET_NUM == 32665 || TARGET_NUM == 32657) MXC_DMA_Init(dma); states[spi_num].channelTx = MXC_DMA_AcquireChannel(dma); states[spi_num].channelRx = MXC_DMA_AcquireChannel(dma); @@ -1180,8 +1192,14 @@ int MXC_SPI_RevA1_SlaveTransactionDMA(mxc_spi_reva_req_t *req, int reqselTx, int MXC_DMA_SetCallback(states[spi_num].channelTx, MXC_SPI_RevA1_DMACallback); MXC_DMA_SetCallback(states[spi_num].channelRx, MXC_SPI_RevA1_DMACallback); + +#if (TARGET_NUM == 32657) + MXC_DMA_EnableInt(dma, states[spi_num].channelTx); + MXC_DMA_EnableInt(dma, states[spi_num].channelRx); +#else MXC_DMA_EnableInt(states[spi_num].channelTx); MXC_DMA_EnableInt(states[spi_num].channelRx); +#endif } bits = MXC_SPI_GetDataSize((mxc_spi_regs_t *)req->spi); diff --git a/Libraries/PeriphDrivers/Source/SYS/pins_me30.c b/Libraries/PeriphDrivers/Source/SYS/pins_me30.c index 79c0d33bc52..8b8e6b4afda 100644 --- a/Libraries/PeriphDrivers/Source/SYS/pins_me30.c +++ b/Libraries/PeriphDrivers/Source/SYS/pins_me30.c @@ -40,98 +40,31 @@ const mxc_gpio_cfg_t gpio_cfg_uart0_flow = { MXC_GPIO0, (MXC_GPIO_PIN_2 | MXC_GP MXC_GPIO_PAD_WEAK_PULL_UP, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; const mxc_gpio_cfg_t gpio_cfg_uart0_flow_disable = { MXC_GPIO0, (MXC_GPIO_PIN_2 | MXC_GPIO_PIN_3), MXC_GPIO_FUNC_IN, MXC_GPIO_PAD_WEAK_PULL_UP, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_uart1 = { MXC_GPIO0, (MXC_GPIO_PIN_12 | MXC_GPIO_PIN_13), MXC_GPIO_FUNC_ALT1, - MXC_GPIO_PAD_WEAK_PULL_UP, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_uart1_flow = { MXC_GPIO0, (MXC_GPIO_PIN_14 | MXC_GPIO_PIN_15), MXC_GPIO_FUNC_ALT2, - MXC_GPIO_PAD_WEAK_PULL_UP, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_uart1_flow_disable = { MXC_GPIO0, (MXC_GPIO_PIN_14 | MXC_GPIO_PIN_15), MXC_GPIO_FUNC_IN, - MXC_GPIO_PAD_WEAK_PULL_UP, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_uart2 = { MXC_GPIO1, (MXC_GPIO_PIN_0 | MXC_GPIO_PIN_1), MXC_GPIO_FUNC_ALT1, - MXC_GPIO_PAD_WEAK_PULL_UP, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_uart2_flow = { MXC_GPIO0, (MXC_GPIO_PIN_30 | MXC_GPIO_PIN_31), MXC_GPIO_FUNC_ALT2, - MXC_GPIO_PAD_WEAK_PULL_UP, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_uart2_flow_disable = { MXC_GPIO0, (MXC_GPIO_PIN_30 | MXC_GPIO_PIN_31), MXC_GPIO_FUNC_IN, - MXC_GPIO_PAD_WEAK_PULL_UP, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_uart3 = { MXC_GPIO2, (MXC_GPIO_PIN_6 | MXC_GPIO_PIN_7), MXC_GPIO_FUNC_ALT2, - MXC_GPIO_PAD_WEAK_PULL_UP, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; - -const mxc_gpio_cfg_t antenna_ctrl0 = { MXC_GPIO1, (MXC_GPIO_PIN_8 | MXC_GPIO_PIN_9), MXC_GPIO_FUNC_ALT1, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t antenna_ctrl1 = { MXC_GPIO1, (MXC_GPIO_PIN_6 | MXC_GPIO_PIN_7), MXC_GPIO_FUNC_ALT2, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +// const mxc_gpio_cfg_t antenna_ctrl0 = { MXC_GPIO1, (MXC_GPIO_PIN_8 | MXC_GPIO_PIN_9), MXC_GPIO_FUNC_ALT1, +// MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +// const mxc_gpio_cfg_t antenna_ctrl1 = { MXC_GPIO1, (MXC_GPIO_PIN_6 | MXC_GPIO_PIN_7), MXC_GPIO_FUNC_ALT2, +// MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +// TODO(ME30): TMR pins // Timers are only defined once, depending on package, each timer could be mapped to other pins -const mxc_gpio_cfg_t gpio_cfg_tmr0 = { MXC_GPIO0, (MXC_GPIO_PIN_2), MXC_GPIO_FUNC_ALT1, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_tmr0b = { MXC_GPIO0, (MXC_GPIO_PIN_3), MXC_GPIO_FUNC_ALT1, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_tmr1 = { MXC_GPIO0, (MXC_GPIO_PIN_14), MXC_GPIO_FUNC_ALT1, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_tmr1b = { MXC_GPIO0, (MXC_GPIO_PIN_15), MXC_GPIO_FUNC_ALT1, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_tmr1_MapB = { MXC_GPIO0, (MXC_GPIO_PIN_20), MXC_GPIO_FUNC_ALT2, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_tmr2 = { MXC_GPIO0, (MXC_GPIO_PIN_26), MXC_GPIO_FUNC_ALT1, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_tmr2b = { MXC_GPIO0, (MXC_GPIO_PIN_27), MXC_GPIO_FUNC_ALT1, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_tmr3 = { MXC_GPIO1, (MXC_GPIO_PIN_6), MXC_GPIO_FUNC_ALT1, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_tmr3b = { MXC_GPIO1, (MXC_GPIO_PIN_7), MXC_GPIO_FUNC_ALT1, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; - -const mxc_gpio_cfg_t gpio_cfg_i2s0 = { MXC_GPIO1, (MXC_GPIO_PIN_2 | MXC_GPIO_PIN_3 | MXC_GPIO_PIN_4 | MXC_GPIO_PIN_5), - MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; - -const mxc_gpio_cfg_t gpio_cfg_i2s0_clkext = { MXC_GPIO0, MXC_GPIO_PIN_14, MXC_GPIO_FUNC_ALT2, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; - -const mxc_gpio_cfg_t gpio_cfg_rtcsqw = { MXC_GPIO3, MXC_GPIO_PIN_1, MXC_GPIO_FUNC_ALT1, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIOH, MXC_GPIO_DRVSTR_0}; - -const mxc_gpio_cfg_t gpio_cfg_pt0 = { MXC_GPIO0, MXC_GPIO_PIN_18, MXC_GPIO_FUNC_ALT1, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_pt1 = { MXC_GPIO0, MXC_GPIO_PIN_19, MXC_GPIO_FUNC_ALT1, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_pt2 = { MXC_GPIO0, MXC_GPIO_PIN_16, MXC_GPIO_FUNC_ALT2, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_pt3 = { MXC_GPIO0, MXC_GPIO_PIN_17, MXC_GPIO_FUNC_ALT2, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; - -// 1-Wire pins need to be at 3.3V so that MXC_GPIO_VSSEL_VDDIOH is selected. -const mxc_gpio_cfg_t gpio_cfg_owm = { MXC_GPIO0, (MXC_GPIO_PIN_6 | MXC_GPIO_PIN_7), MXC_GPIO_FUNC_ALT2, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIOH, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_owmb = { MXC_GPIO0, (MXC_GPIO_PIN_18 | MXC_GPIO_PIN_19), MXC_GPIO_FUNC_ALT2, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIOH, MXC_GPIO_DRVSTR_0 }; - -const mxc_gpio_cfg_t gpio_cfg_adc_ain0 = { MXC_GPIO2, MXC_GPIO_PIN_0, MXC_GPIO_FUNC_ALT1, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_adc_ain1 = { MXC_GPIO2, MXC_GPIO_PIN_1, MXC_GPIO_FUNC_ALT1, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_adc_ain2 = { MXC_GPIO2, MXC_GPIO_PIN_2, MXC_GPIO_FUNC_ALT1, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_adc_ain3 = { MXC_GPIO2, MXC_GPIO_PIN_3, MXC_GPIO_FUNC_ALT1, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_adc_ain4 = { MXC_GPIO2, MXC_GPIO_PIN_4, MXC_GPIO_FUNC_ALT1, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_adc_ain5 = { MXC_GPIO2, MXC_GPIO_PIN_5, MXC_GPIO_FUNC_ALT1, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_adc_ain6 = { MXC_GPIO2, MXC_GPIO_PIN_6, MXC_GPIO_FUNC_ALT1, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_adc_ain7 = { MXC_GPIO2, MXC_GPIO_PIN_7, MXC_GPIO_FUNC_ALT1, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; - -const mxc_gpio_cfg_t gpio_cfg_rv_jtag = { MXC_GPIO1, (MXC_GPIO_PIN_0 | MXC_GPIO_PIN_1 | MXC_GPIO_PIN_2 | MXC_GPIO_PIN_3), - MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; - -const mxc_gpio_cfg_t gpio_cfg_cmp0 = { MXC_GPIO2, (MXC_GPIO_PIN_0 | MXC_GPIO_PIN_1), MXC_GPIO_FUNC_ALT1, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_cmp1 = { MXC_GPIO2, (MXC_GPIO_PIN_2 | MXC_GPIO_PIN_3), MXC_GPIO_FUNC_ALT1, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_cmp2 = { MXC_GPIO2, (MXC_GPIO_PIN_4 | MXC_GPIO_PIN_5), MXC_GPIO_FUNC_ALT1, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_cmp3 = { MXC_GPIO2, (MXC_GPIO_PIN_6 | MXC_GPIO_PIN_7), MXC_GPIO_FUNC_ALT1, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +// const mxc_gpio_cfg_t gpio_cfg_tmr0 = { MXC_GPIO0, (MXC_GPIO_PIN_2), MXC_GPIO_FUNC_ALT1, +// MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +// const mxc_gpio_cfg_t gpio_cfg_tmr0b = { MXC_GPIO0, (MXC_GPIO_PIN_3), MXC_GPIO_FUNC_ALT1, +// MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +// const mxc_gpio_cfg_t gpio_cfg_tmr1 = { MXC_GPIO0, (MXC_GPIO_PIN_14), MXC_GPIO_FUNC_ALT1, +// MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +// const mxc_gpio_cfg_t gpio_cfg_tmr1b = { MXC_GPIO0, (MXC_GPIO_PIN_15), MXC_GPIO_FUNC_ALT1, +// MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +// const mxc_gpio_cfg_t gpio_cfg_tmr1_MapB = { MXC_GPIO0, (MXC_GPIO_PIN_20), MXC_GPIO_FUNC_ALT2, +// MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +// const mxc_gpio_cfg_t gpio_cfg_tmr2 = { MXC_GPIO0, (MXC_GPIO_PIN_26), MXC_GPIO_FUNC_ALT1, +// MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +// const mxc_gpio_cfg_t gpio_cfg_tmr2b = { MXC_GPIO0, (MXC_GPIO_PIN_27), MXC_GPIO_FUNC_ALT1, +// MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +// const mxc_gpio_cfg_t gpio_cfg_tmr3 = { MXC_GPIO1, (MXC_GPIO_PIN_6), MXC_GPIO_FUNC_ALT1, +// MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +// const mxc_gpio_cfg_t gpio_cfg_tmr3b = { MXC_GPIO1, (MXC_GPIO_PIN_7), MXC_GPIO_FUNC_ALT1, +// MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; // SPI v2 Pin Definitions const mxc_gpio_cfg_t gpio_cfg_spi0_standard = { MXC_GPIO0, (MXC_GPIO_PIN_5 | MXC_GPIO_PIN_6 | MXC_GPIO_PIN_7), @@ -143,21 +76,10 @@ const mxc_gpio_cfg_t gpio_cfg_spi0_dual = { MXC_GPIO0, (MXC_GPIO_PIN_5 | MXC_GPI const mxc_gpio_cfg_t gpio_cfg_spi0_quad = { MXC_GPIO0, (MXC_GPIO_PIN_5 | MXC_GPIO_PIN_6 | MXC_GPIO_PIN_7 | MXC_GPIO_PIN_8 | MXC_GPIO_PIN_9), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_spi1_standard = { MXC_GPIO0, (MXC_GPIO_PIN_21 | MXC_GPIO_PIN_22 | MXC_GPIO_PIN_23), MXC_GPIO_FUNC_ALT1, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_spi1_3wire = { MXC_GPIO0, (MXC_GPIO_PIN_21 | MXC_GPIO_PIN_23), MXC_GPIO_FUNC_ALT1, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_spi1_dual = { MXC_GPIO0, (MXC_GPIO_PIN_21 | MXC_GPIO_PIN_22 | MXC_GPIO_PIN_23), - MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_spi1_quad = { MXC_GPIO0, (MXC_GPIO_PIN_21 | MXC_GPIO_PIN_22 | MXC_GPIO_PIN_23 | MXC_GPIO_PIN_24 | MXC_GPIO_PIN_25), - MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; - // SPI v2 Target Selects Pin Definitions const mxc_gpio_cfg_t gpio_cfg_spi0_ts0 = { MXC_GPIO0, MXC_GPIO_PIN_4, MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; const mxc_gpio_cfg_t gpio_cfg_spi0_ts1 = { MXC_GPIO0, MXC_GPIO_PIN_26, MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; const mxc_gpio_cfg_t gpio_cfg_spi0_ts2 = { MXC_GPIO0, MXC_GPIO_PIN_27, MXC_GPIO_FUNC_ALT2, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_spi1_ts0 = { MXC_GPIO0, MXC_GPIO_PIN_20, MXC_GPIO_FUNC_ALT1, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; \ No newline at end of file diff --git a/Libraries/PeriphDrivers/Source/SYS/sys_me30.c b/Libraries/PeriphDrivers/Source/SYS/sys_me30.c index 4ad2ab85b67..78e09ee40bc 100644 --- a/Libraries/PeriphDrivers/Source/SYS/sys_me30.c +++ b/Libraries/PeriphDrivers/Source/SYS/sys_me30.c @@ -29,7 +29,6 @@ #include "mxc_assert.h" #include "mxc_sys.h" #include "mxc_delay.h" -#include "lpgcr_regs.h" #include "gcr_regs.h" #include "fcr_regs.h" #include "mcr_regs.h" @@ -61,14 +60,14 @@ extern uint32_t _binary_riscv_bin_start; int MXC_SYS_GetUSN(uint8_t *usn, uint8_t *checksum) { int err = E_NO_ERROR; - uint32_t *infoblock = (uint32_t *)MXC_INFO0_MEM_BASE; + uint32_t *infoblock = (uint32_t *)MXC_INFO_MEM_BASE; if (usn == NULL) { return E_NULL_PTR; } /* Read the USN from the info block */ - MXC_FLC_UnlockInfoBlock(MXC_INFO0_MEM_BASE); + MXC_FLC_UnlockInfoBlock(MXC_INFO_MEM_BASE); memset(usn, 0, MXC_SYS_USN_CHECKSUM_LEN); @@ -94,9 +93,12 @@ int MXC_SYS_GetUSN(uint8_t *usn, uint8_t *checksum) checksum[0] = ((infoblock[3] & 0x7F800000) >> 23); checksum[1] = ((infoblock[4] & 0x007F8000) >> 15); - err = MXC_AES_Init(); + // Info block only accessible for secure code. + // Use Secure DMA1. + // TODO(DMA): Figure out access to "secure" functions when in non-secure code. + err = MXC_AES_Init(MXC_DMA1); if (err) { - MXC_FLC_LockInfoBlock(MXC_INFO0_MEM_BASE); + MXC_FLC_LockInfoBlock(MXC_INFO_MEM_BASE); return err; } @@ -114,7 +116,7 @@ int MXC_SYS_GetUSN(uint8_t *usn, uint8_t *checksum) err = MXC_AES_Generic(&aes_req); if (err) { - MXC_FLC_LockInfoBlock(MXC_INFO0_MEM_BASE); + MXC_FLC_LockInfoBlock(MXC_INFO_MEM_BASE); return err; } @@ -122,7 +124,7 @@ int MXC_SYS_GetUSN(uint8_t *usn, uint8_t *checksum) // Verify Checksum if (check_csum[0] != checksum[1] || check_csum[1] != checksum[0]) { - MXC_FLC_LockInfoBlock(MXC_INFO0_MEM_BASE); + MXC_FLC_LockInfoBlock(MXC_INFO_MEM_BASE); return E_INVALID; } } @@ -131,7 +133,7 @@ int MXC_SYS_GetUSN(uint8_t *usn, uint8_t *checksum) usn[11] = ((infoblock[3] & 0x7F800000) >> 23); usn[12] = ((infoblock[4] & 0x007F8000) >> 15); - MXC_FLC_LockInfoBlock(MXC_INFO0_MEM_BASE); + MXC_FLC_LockInfoBlock(MXC_INFO_MEM_BASE); return err; } @@ -146,10 +148,7 @@ int MXC_SYS_GetRevision(void) int MXC_SYS_IsClockEnabled(mxc_sys_periph_clock_t clock) { /* The mxc_sys_periph_clock_t enum uses enum values that are the offset by 32 and 64 for the perckcn1 register. */ - if (clock > 63) { - clock -= 64; - return !(MXC_LPGCR->pclkdis & (0x1 << clock)); - } else if (clock > 31) { + if (clock > 31) { clock -= 32; return !(MXC_GCR->pclkdis1 & (0x1 << clock)); } else { @@ -161,10 +160,7 @@ int MXC_SYS_IsClockEnabled(mxc_sys_periph_clock_t clock) void MXC_SYS_ClockDisable(mxc_sys_periph_clock_t clock) { /* The mxc_sys_periph_clock_t enum uses enum values that are the offset by 32 and 64 for the perckcn1 register. */ - if (clock > 63) { - clock -= 64; - MXC_LPGCR->pclkdis |= (0x1 << clock); - } else if (clock > 31) { + if (clock > 31) { clock -= 32; MXC_GCR->pclkdis1 |= (0x1 << clock); } else { @@ -176,10 +172,7 @@ void MXC_SYS_ClockDisable(mxc_sys_periph_clock_t clock) void MXC_SYS_ClockEnable(mxc_sys_periph_clock_t clock) { /* The mxc_sys_periph_clock_t enum uses enum values that are the offset by 32 and 64 for the perckcn1 register. */ - if (clock > 63) { - clock -= 64; - MXC_LPGCR->pclkdis &= ~(0x1 << clock); - } else if (clock > 31) { + if (clock > 31) { clock -= 32; MXC_GCR->pclkdis1 &= ~(0x1 << clock); } else { @@ -232,10 +225,11 @@ int MXC_SYS_ClockSourceEnable(mxc_sys_system_clock_t clock) return MXC_SYS_Clock_Timeout(MXC_F_GCR_CLKCTRL_IBRO_RDY); break; - case MXC_SYS_CLOCK_EXTCLK: - // No "RDY" bit to monitor, so just configure the GPIO - return MXC_GPIO_Config(&gpio_cfg_extclk); - break; + // TODO(ME30): EXTCLK is missing from register definitions + // case MXC_SYS_CLOCK_EXTCLK: + // // No "RDY" bit to monitor, so just configure the GPIO + // return MXC_GPIO_Config(&gpio_cfg_extclk); + // break; case MXC_SYS_CLOCK_INRO: // The 80k clock is always enabled @@ -243,20 +237,21 @@ int MXC_SYS_ClockSourceEnable(mxc_sys_system_clock_t clock) break; case MXC_SYS_CLOCK_ERFO: - MXC_GCR->btleldoctrl |= MXC_F_GCR_BTLELDOCTRL_LDOTXEN | MXC_F_GCR_BTLELDOCTRL_LDORXEN; + MXC_GCR->btleldoctrl |= MXC_F_GCR_BTLELDOCTRL_TX_EN | MXC_F_GCR_BTLELDOCTRL_RX_EN; /* Initialize kickstart circuit Select Kick start circuit clock source- IPO/ISO */ - MXC_FCR->erfoks = ((MXC_S_FCR_ERFOKS_KSCLKSEL_ISO) - /* Set Drive strengh - 0x1,0x2,0x3 */ - | ((0x1) << MXC_F_FCR_ERFOKS_KSERFODRIVER_POS) - /* Set kick count 1-127 */ - | (0x8) - /* Set double pulse length On/Off*/ - | (0 & MXC_F_FCR_ERFOKS_KSERFO2X) - /* Enable On/Off */ - | (MXC_F_FCR_ERFOKS_KSERFO_EN)); + // TODO(ME30): MXC_FCR missing ERFOKS definition + // MXC_FCR->erfoks = ((MXC_S_FCR_ERFOKS_KSCLKSEL_ISO) + // /* Set Drive strengh - 0x1,0x2,0x3 */ + // | ((0x1) << MXC_F_FCR_ERFOKS_KSERFODRIVER_POS) + // /* Set kick count 1-127 */ + // | (0x8) + // /* Set double pulse length On/Off*/ + // | (0 & MXC_F_FCR_ERFOKS_KSERFO2X) + // /* Enable On/Off */ + // | (MXC_F_FCR_ERFOKS_KSERFO_EN)); /* Enable ERFO */ MXC_GCR->clkctrl |= MXC_F_GCR_CLKCTRL_ERFO_EN; @@ -295,15 +290,16 @@ int MXC_SYS_ClockSourceDisable(mxc_sys_system_clock_t clock) MXC_GCR->clkctrl &= ~MXC_F_GCR_CLKCTRL_IBRO_EN; break; - case MXC_SYS_CLOCK_EXTCLK: - /* - There's not a great way to disable the external clock. - Deinitializing the GPIO here may have unintended consequences - for application code. - Selecting a different system clock source is sufficient - to "disable" the EXT_CLK source. - */ - break; + // TODO(ME30): Missing EXTCLK register definition + // case MXC_SYS_CLOCK_EXTCLK: + // /* + // There's not a great way to disable the external clock. + // Deinitializing the GPIO here may have unintended consequences + // for application code. + // Selecting a different system clock source is sufficient + // to "disable" the EXT_CLK source. + // */ + // break; case MXC_SYS_CLOCK_INRO: // The 80k clock is always enabled @@ -356,29 +352,11 @@ int MXC_SYS_Clock_Timeout(uint32_t ready) int MXC_SYS_Clock_Select(mxc_sys_system_clock_t clock) { uint32_t current_clock; - int err = E_NO_ERROR; // Save the current system clock current_clock = MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_SYSCLK_SEL; switch (clock) { - case MXC_SYS_CLOCK_ISO: - - // Enable ISO clock - if (!(MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_ISO_EN)) { - MXC_GCR->clkctrl |= MXC_F_GCR_CLKCTRL_ISO_EN; - - // Check if ISO clock is ready - if (MXC_SYS_Clock_Timeout(MXC_F_GCR_CLKCTRL_ISO_RDY) != E_NO_ERROR) { - return E_TIME_OUT; - } - } - - // Set ISO clock as System Clock - MXC_SETFIELD(MXC_GCR->clkctrl, MXC_F_GCR_CLKCTRL_SYSCLK_SEL, - MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ISO); - - break; case MXC_SYS_CLOCK_IPO: // Enable IPO clock @@ -415,20 +393,21 @@ int MXC_SYS_Clock_Select(mxc_sys_system_clock_t clock) break; - case MXC_SYS_CLOCK_EXTCLK: - /* - There's not "EXT_CLK RDY" bit for the ME17, so we'll - blindly enable (configure GPIO) the external clock every time. - */ - err = MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_EXTCLK); - if (err) - return err; + // TODO(ME30): Missing EXTCLK register definition + // case MXC_SYS_CLOCK_EXTCLK: + // /* + // There's not "EXT_CLK RDY" bit for the ME17, so we'll + // blindly enable (configure GPIO) the external clock every time. + // */ + // err = MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_EXTCLK); + // if (err) + // return err; - // Set EXT clock as System Clock - MXC_SETFIELD(MXC_GCR->clkctrl, MXC_F_GCR_CLKCTRL_SYSCLK_SEL, - MXC_S_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK); + // // Set EXT clock as System Clock + // MXC_SETFIELD(MXC_GCR->clkctrl, MXC_F_GCR_CLKCTRL_SYSCLK_SEL, + // MXC_S_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK); - break; + // break; case MXC_SYS_CLOCK_ERFO: @@ -514,11 +493,7 @@ mxc_sys_system_clock_div_t MXC_SYS_GetClockDiv(void) void MXC_SYS_Reset_Periph(mxc_sys_reset_t reset) { /* The mxc_sys_reset_t enum uses enum values that are the offset by 32 and 64 for the rst register. */ - if (reset > 63) { - reset -= 64; - MXC_LPGCR->rst = (0x1 << reset); - while (MXC_LPGCR->rst & (0x1 << reset)) {} - } else if (reset > 31) { + if (reset > 31) { reset -= 32; MXC_GCR->rst1 = (0x1 << reset); while (MXC_GCR->rst1 & (0x1 << reset)) {} @@ -528,41 +503,6 @@ void MXC_SYS_Reset_Periph(mxc_sys_reset_t reset) } } -/* ************************************************************************** */ -void MXC_SYS_RISCVRun(void) -{ - /* Disable the the RSCV */ - MXC_GCR->pclkdis1 |= MXC_F_GCR_PCLKDIS1_CPU1; - - /* Set the interrupt vector base address */ - MXC_FCR->urvbootaddr = (uint32_t)&_binary_riscv_bin_start; - - /* Power up the RSCV */ - MXC_GCR->pclkdis1 &= ~(MXC_F_GCR_PCLKDIS1_CPU1); - - /* CPU1 reset */ - MXC_GCR->rst1 |= MXC_F_GCR_RST1_CPU1; -} - -/* ************************************************************************** */ -void MXC_SYS_RISCVShutdown(void) -{ - /* Disable the the RSCV */ - MXC_GCR->pclkdis1 |= MXC_F_GCR_PCLKDIS1_CPU1; -} - -/* ************************************************************************** */ -uint32_t MXC_SYS_RiscVClockRate(void) -{ - // If in LPM mode and the PCLK is selected as the RV32 clock source, - if (((MXC_GCR->pm & MXC_F_GCR_PM_MODE) == MXC_S_GCR_PM_MODE_LPM) && - (MXC_PWRSEQ->lpcn & MXC_F_PWRSEQ_LPCN_LPMCLKSEL)) { - return ISO_FREQ; - } else { - return PeripheralClock; - } -} - /* ************************************************************************** */ int MXC_SYS_LockDAP_Permanent(void) { diff --git a/Libraries/PeriphDrivers/Source/TMR/tmr_me30.c b/Libraries/PeriphDrivers/Source/TMR/tmr_me30.c index 8c4404d6b6a..868caf34d47 100644 --- a/Libraries/PeriphDrivers/Source/TMR/tmr_me30.c +++ b/Libraries/PeriphDrivers/Source/TMR/tmr_me30.c @@ -19,7 +19,6 @@ #include "tmr.h" #include "tmr_revb.h" #include "tmr_common.h" -#include "lpgcr_regs.h" #include "stdbool.h" int MXC_TMR_Init(mxc_tmr_regs_t *tmr, mxc_tmr_cfg_t *cfg, bool init_pins) @@ -34,16 +33,6 @@ int MXC_TMR_Init(mxc_tmr_regs_t *tmr, mxc_tmr_cfg_t *cfg, bool init_pins) MXC_ASSERT(tmr_id >= 0); switch (cfg->clock) { - case MXC_TMR_ISO_CLK: - if (tmr_id > 3) { // Timers 4-5 do not support this clock source - return E_NOT_SUPPORTED; - } - - clockSource = MXC_TMR_CLK1; - MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_ISO); - MXC_TMR_RevB_SetClockSourceFreq((mxc_tmr_revb_regs_t *)tmr, ISO_FREQ); - break; - case MXC_TMR_IBRO_CLK: if (tmr_id > 3) { // Timers 4-5 do not support this clock source return E_NOT_SUPPORTED; @@ -64,7 +53,6 @@ int MXC_TMR_Init(mxc_tmr_regs_t *tmr, mxc_tmr_cfg_t *cfg, bool init_pins) MXC_TMR_RevB_SetClockSourceFreq((mxc_tmr_revb_regs_t *)tmr, (IBRO_FREQ / 8)); break; -#if (TARGET_NUM != 32680) case MXC_TMR_ERTCO_CLK: if (tmr_id == 4) { clockSource = MXC_TMR_CLK1; @@ -77,7 +65,6 @@ int MXC_TMR_Init(mxc_tmr_regs_t *tmr, mxc_tmr_cfg_t *cfg, bool init_pins) MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_ERTCO); MXC_TMR_RevB_SetClockSourceFreq((mxc_tmr_revb_regs_t *)tmr, ERTCO_FREQ); break; -#endif case MXC_TMR_INRO_CLK: if (tmr_id < 4) { // Timers 0-3 do not support this clock source @@ -154,12 +141,12 @@ int MXC_TMR_Init(mxc_tmr_regs_t *tmr, mxc_tmr_cfg_t *cfg, bool init_pins) break; case 4: - MXC_SYS_Reset_Periph(MXC_SYS_RESET_TMR4); + MXC_SYS_Reset_Periph(MXC_SYS_RESET0_TMR4); MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TMR4); break; case 5: - MXC_SYS_Reset_Periph(MXC_SYS_RESET_TMR5); + MXC_SYS_Reset_Periph(MXC_SYS_RESET0_TMR5); MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TMR5); break; } @@ -265,19 +252,13 @@ uint32_t MXC_TMR_GetPeriod(mxc_tmr_regs_t *tmr, mxc_tmr_clock_t clock, uint32_t clockFrequency = PeripheralClock; break; - case MXC_TMR_ISO_CLK: - clockFrequency = ISO_FREQ; - break; - case MXC_TMR_IBRO_CLK: clockFrequency = IBRO_FREQ; break; -#if (TARGET_NUM != 32680) case MXC_TMR_ERTCO_CLK: clockFrequency = ERTCO_FREQ; break; -#endif default: break; diff --git a/Libraries/PeriphDrivers/Source/TRNG/trng_me30.c b/Libraries/PeriphDrivers/Source/TRNG/trng_me30.c index 0875de46e2d..9d9725e5616 100644 --- a/Libraries/PeriphDrivers/Source/TRNG/trng_me30.c +++ b/Libraries/PeriphDrivers/Source/TRNG/trng_me30.c @@ -85,9 +85,5 @@ void MXC_TRNG_RandomAsync(uint8_t *data, uint32_t len, mxc_trng_complete_t callb int MXC_TRNG_HealthTest(void) { - if ((MXC_SYS_GetRevision() & 0xF0) == 0xA0) { // ME17 Rev. A does not support health tests. - return E_NOT_SUPPORTED; - } - return MXC_TRNG_RevB_HealthTest((mxc_trng_revb_regs_t *)MXC_TRNG); } diff --git a/Libraries/PeriphDrivers/Source/UART/uart_me30.c b/Libraries/PeriphDrivers/Source/UART/uart_me30.c index 32b722c786c..303d21c973a 100644 --- a/Libraries/PeriphDrivers/Source/UART/uart_me30.c +++ b/Libraries/PeriphDrivers/Source/UART/uart_me30.c @@ -1,6 +1,8 @@ /****************************************************************************** * - * Copyright (C) 2024 Analog Devices, Inc. + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -20,29 +22,47 @@ #include "mxc_device.h" #include "mxc_pins.h" #include "mxc_assert.h" -#include "uart_revb.h" +#include "uart_reva.h" #include "uart_common.h" -#include "lpgcr_regs.h" #include "dma.h" void MXC_UART_DMACallback(int ch, int error) { - MXC_UART_RevB_DMACallback(ch, error); + MXC_UART_RevA_DMACallback(ch, error); } int MXC_UART_AsyncCallback(mxc_uart_regs_t *uart, int retVal) { - return MXC_UART_RevB_AsyncCallback((mxc_uart_revb_regs_t *)uart, retVal); + return MXC_UART_RevA_AsyncCallback((mxc_uart_reva_regs_t *)uart, retVal); +} + +int MXC_UART_TxAsyncCallback(mxc_uart_regs_t *uart, int retVal) +{ + return MXC_UART_RevA_TxAsyncCallback((mxc_uart_reva_regs_t *)uart, retVal); +} + +int MXC_UART_RxAsyncCallback(mxc_uart_regs_t *uart, int retVal) +{ + return MXC_UART_RevA_RxAsyncCallback((mxc_uart_reva_regs_t *)uart, retVal); } int MXC_UART_AsyncStop(mxc_uart_regs_t *uart) { - return MXC_UART_RevB_AsyncStop((mxc_uart_revb_regs_t *)uart); + return MXC_UART_RevA_AsyncStop((mxc_uart_reva_regs_t *)uart); } -int MXC_UART_Init(mxc_uart_regs_t *uart, unsigned int baud, mxc_uart_clock_t clock) +int MXC_UART_TxAsyncStop(mxc_uart_regs_t *uart) +{ + return MXC_UART_RevA_TxAsyncStop((mxc_uart_reva_regs_t *)uart); +} + +int MXC_UART_RxAsyncStop(mxc_uart_regs_t *uart) +{ + return MXC_UART_RevA_RxAsyncStop((mxc_uart_reva_regs_t *)uart); +} + +int MXC_UART_Init(mxc_uart_regs_t *uart, unsigned int baud) { -#ifndef MSDK_NO_GPIO_CLK_INIT int retval; retval = MXC_UART_Shutdown(uart); @@ -51,261 +71,90 @@ int MXC_UART_Init(mxc_uart_regs_t *uart, unsigned int baud, mxc_uart_clock_t clo return retval; } - switch (clock) { -#if TARGET_NUM != 32680 - case MXC_UART_ERTCO_CLK: - MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_ERTCO); - break; -#endif - - case MXC_UART_IBRO_CLK: - MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_IBRO); - break; - - default: - break; - } - - switch (MXC_UART_GET_IDX(uart)) { - case 0: - MXC_GPIO_Config(&gpio_cfg_uart0); - MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_UART0); - break; - - case 1: - MXC_GPIO_Config(&gpio_cfg_uart1); - MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_UART1); - break; - - case 2: - MXC_GPIO_Config(&gpio_cfg_uart2); - MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_UART2); - break; - - case 3: - MXC_GPIO_Config(&gpio_cfg_uart3); - MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_UART3); - break; - - default: - return E_BAD_PARAM; - } -#endif // MSDK_NO_GPIO_CLK_INIT + MXC_GPIO_Config(&gpio_cfg_uart0); + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_UART); - return MXC_UART_RevB_Init((mxc_uart_revb_regs_t *)uart, baud, clock); + return MXC_UART_RevA_Init((mxc_uart_reva_regs_t *)uart, baud); } int MXC_UART_Shutdown(mxc_uart_regs_t *uart) { - switch (MXC_UART_GET_IDX(uart)) { - case 0: - MXC_SYS_Reset_Periph(MXC_SYS_RESET0_UART0); - MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_UART0); - break; - - case 1: - MXC_SYS_Reset_Periph(MXC_SYS_RESET0_UART1); - MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_UART1); - break; - - case 2: - MXC_SYS_Reset_Periph(MXC_SYS_RESET0_UART2); - MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_UART2); - break; - - case 3: - MXC_SYS_Reset_Periph(MXC_SYS_RESET_UART3); - MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_UART3); - break; - - default: - return E_BAD_PARAM; - } + MXC_SYS_Reset_Periph(MXC_SYS_RESET0_UART); + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_UART); return E_NO_ERROR; } int MXC_UART_ReadyForSleep(mxc_uart_regs_t *uart) { - return MXC_UART_RevB_ReadyForSleep((mxc_uart_revb_regs_t *)uart); + return MXC_UART_RevA_ReadyForSleep((mxc_uart_reva_regs_t *)uart); } -int MXC_UART_SetFrequency(mxc_uart_regs_t *uart, unsigned int baud, mxc_uart_clock_t clock) +int MXC_UART_SetFrequency(mxc_uart_regs_t *uart, unsigned int baud) { - int freq; - unsigned mod = 0; - unsigned clkDiv = 0; - - if (MXC_UART_GET_IDX(uart) < 0) { - return E_BAD_PARAM; - } - - // check if the uart is LPUART - if (uart == MXC_UART3) { - // OSR default value - uart->osr = 5; - - switch (clock) { - case MXC_UART_IBRO_CLK: - uart->ctrl |= MXC_S_UART_CTRL_BCLKSRC_PERIPHERAL_CLOCK; - clkDiv = ((IBRO_FREQ) / baud); - mod = ((IBRO_FREQ) % baud); - break; - - case MXC_UART_ERTCO_CLK: - // Only supports up to 9600 baud with ERTCO clock. - if (baud > 9600) { - return E_NOT_SUPPORTED; - } - - uart->ctrl |= MXC_S_UART_CTRL_BCLKSRC_EXTERNAL_CLOCK; - uart->ctrl |= MXC_F_UART_CTRL_FDM; - if (baud == 9600) { - clkDiv = 7; - mod = 0; - } else { - clkDiv = ((ERTCO_FREQ * 2) / baud); - mod = ((ERTCO_FREQ * 2) % baud); - } - - if (baud > 2400) { - uart->osr = 0; - } else { - uart->osr = 1; - } - break; - - default: - return E_BAD_PARAM; - } - - if (!clkDiv || mod > (baud / 2)) { - clkDiv++; - } - uart->clkdiv = clkDiv; - - freq = MXC_UART_GetFrequency(uart); - } else { - if (clock == MXC_UART_ERTCO_CLK) { - return E_BAD_PARAM; - } - - freq = MXC_UART_RevB_SetFrequency((mxc_uart_revb_regs_t *)uart, baud, clock); - } - - if (freq > 0) { - // Enable baud clock and wait for it to become ready. - uart->ctrl |= MXC_F_UART_CTRL_BCLKEN; - while (((uart->ctrl & MXC_F_UART_CTRL_BCLKRDY) >> MXC_F_UART_CTRL_BCLKRDY_POS) == 0) {} - } - - return freq; + return MXC_UART_RevA_SetFrequency((mxc_uart_reva_regs_t *)uart, baud); } int MXC_UART_GetFrequency(mxc_uart_regs_t *uart) { - int periphClock = 0; - - if (MXC_UART_GET_IDX(uart) < 0) { - return E_BAD_PARAM; - } - - // check if UART is LP UART - if (uart == MXC_UART3) { - if ((uart->ctrl & MXC_F_UART_CTRL_BCLKSRC) == - MXC_S_UART_REVB_CTRL_BCLKSRC_PERIPHERAL_CLOCK) { - periphClock = IBRO_FREQ; - } else if ((uart->ctrl & MXC_F_UART_CTRL_BCLKSRC) == - MXC_S_UART_REVB_CTRL_BCLKSRC_EXTERNAL_CLOCK) { - periphClock = ERTCO_FREQ * 2; - } else { - return E_NOT_SUPPORTED; - } - return (periphClock / uart->clkdiv); - } else { - return MXC_UART_RevB_GetFrequency((mxc_uart_revb_regs_t *)uart); - } + return MXC_UART_RevA_GetFrequency((mxc_uart_reva_regs_t *)uart); } int MXC_UART_SetDataSize(mxc_uart_regs_t *uart, int dataSize) { - return MXC_UART_RevB_SetDataSize((mxc_uart_revb_regs_t *)uart, dataSize); + return MXC_UART_RevA_SetDataSize((mxc_uart_reva_regs_t *)uart, dataSize); } int MXC_UART_SetStopBits(mxc_uart_regs_t *uart, mxc_uart_stop_t stopBits) { - return MXC_UART_RevB_SetStopBits((mxc_uart_revb_regs_t *)uart, stopBits); + return MXC_UART_RevA_SetStopBits((mxc_uart_reva_regs_t *)uart, stopBits); } int MXC_UART_SetParity(mxc_uart_regs_t *uart, mxc_uart_parity_t parity) { - return MXC_UART_RevB_SetParity((mxc_uart_revb_regs_t *)uart, parity); + return MXC_UART_RevA_SetParity((mxc_uart_reva_regs_t *)uart, parity); } int MXC_UART_SetFlowCtrl(mxc_uart_regs_t *uart, mxc_uart_flow_t flowCtrl, int rtsThreshold) { - if (flowCtrl == MXC_UART_FLOW_EN) { - switch (MXC_UART_GET_IDX(uart)) { - case 0: - MXC_GPIO_Config(&gpio_cfg_uart0_flow); - break; - - case 1: - MXC_GPIO_Config(&gpio_cfg_uart1_flow); - break; - - case 2: - MXC_GPIO_Config(&gpio_cfg_uart2_flow); - break; - - default: - return E_BAD_PARAM; - } - } else { - switch (MXC_UART_GET_IDX(uart)) { - case 0: - MXC_GPIO_Config(&gpio_cfg_uart0_flow_disable); - break; - - case 1: - MXC_GPIO_Config(&gpio_cfg_uart1_flow_disable); - break; - - case 2: - MXC_GPIO_Config(&gpio_cfg_uart2_flow_disable); - break; - - default: - return E_BAD_PARAM; - } - } + MXC_GPIO_Config(&gpio_cfg_uart0_flow); - return MXC_UART_RevB_SetFlowCtrl((mxc_uart_revb_regs_t *)uart, flowCtrl, rtsThreshold); + return MXC_UART_RevA_SetFlowCtrl((mxc_uart_reva_regs_t *)uart, flowCtrl, rtsThreshold); } -int MXC_UART_SetClockSource(mxc_uart_regs_t *uart, mxc_uart_clock_t clock) +int MXC_UART_SetClockSource(mxc_uart_regs_t *uart, int usePCLK) { - return MXC_UART_RevB_SetClockSource((mxc_uart_revb_regs_t *)uart, clock); + return MXC_UART_RevA_SetClockSource((mxc_uart_reva_regs_t *)uart, usePCLK); +} + +int MXC_UART_SetNullModem(mxc_uart_regs_t *uart, int nullModem) +{ + return MXC_UART_RevA_SetNullModem((mxc_uart_reva_regs_t *)uart, nullModem); +} + +int MXC_UART_SendBreak(mxc_uart_regs_t *uart) +{ + return MXC_UART_RevA_SendBreak((mxc_uart_reva_regs_t *)uart); } int MXC_UART_GetActive(mxc_uart_regs_t *uart) { - return MXC_UART_RevB_GetActive((mxc_uart_revb_regs_t *)uart); + return MXC_UART_RevA_GetActive((mxc_uart_reva_regs_t *)uart); } int MXC_UART_AbortTransmission(mxc_uart_regs_t *uart) { - return MXC_UART_RevB_AbortTransmission((mxc_uart_revb_regs_t *)uart); + return MXC_UART_RevA_AbortTransmission((mxc_uart_reva_regs_t *)uart); } int MXC_UART_ReadCharacterRaw(mxc_uart_regs_t *uart) { - return MXC_UART_RevB_ReadCharacterRaw((mxc_uart_revb_regs_t *)uart); + return MXC_UART_RevA_ReadCharacterRaw((mxc_uart_reva_regs_t *)uart); } int MXC_UART_WriteCharacterRaw(mxc_uart_regs_t *uart, uint8_t character) { - return MXC_UART_RevB_WriteCharacterRaw((mxc_uart_revb_regs_t *)uart, character); + return MXC_UART_RevA_WriteCharacterRaw((mxc_uart_reva_regs_t *)uart, character); } int MXC_UART_ReadCharacter(mxc_uart_regs_t *uart) @@ -320,176 +169,142 @@ int MXC_UART_WriteCharacter(mxc_uart_regs_t *uart, uint8_t character) int MXC_UART_Read(mxc_uart_regs_t *uart, uint8_t *buffer, int *len) { - return MXC_UART_RevB_Read((mxc_uart_revb_regs_t *)uart, buffer, len); + return MXC_UART_RevA_Read((mxc_uart_reva_regs_t *)uart, buffer, len); } -int MXC_UART_Write(mxc_uart_regs_t *uart, const uint8_t *byte, int *len) +int MXC_UART_Write(mxc_uart_regs_t *uart, uint8_t *byte, int *len) { - return MXC_UART_RevB_Write((mxc_uart_revb_regs_t *)uart, byte, len); + return MXC_UART_RevA_Write((mxc_uart_reva_regs_t *)uart, byte, len); } unsigned int MXC_UART_ReadRXFIFO(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned int len) { - return MXC_UART_RevB_ReadRXFIFO((mxc_uart_revb_regs_t *)uart, bytes, len); + return MXC_UART_RevA_ReadRXFIFO((mxc_uart_reva_regs_t *)uart, bytes, len); } -int MXC_UART_ReadRXFIFODMA(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned int len, +int MXC_UART_ReadRXFIFODMA(mxc_uart_regs_t *uart, mxc_dma_regs_t *dma, unsigned char *bytes, unsigned int len, mxc_uart_dma_complete_cb_t callback) { mxc_dma_config_t config; + config.reqsel = MXC_DMA_REQUEST_UART0RX; // TODO(ME30): Updated DMA reqsel - int uart_num = MXC_UART_GET_IDX(uart); - - switch (uart_num) { - case 0: - config.reqsel = MXC_DMA_REQUEST_UART0RX; - break; - - case 1: - config.reqsel = MXC_DMA_REQUEST_UART1RX; - break; - - case 2: - config.reqsel = MXC_DMA_REQUEST_UART2RX; - break; - - case 3: - config.reqsel = MXC_DMA_REQUEST_UART3RX; - break; - - default: - return E_BAD_PARAM; - break; - } - - return MXC_UART_RevB_ReadRXFIFODMA((mxc_uart_revb_regs_t *)uart, bytes, len, callback, config); + return MXC_UART_RevA_ReadRXFIFODMA((mxc_uart_reva_regs_t *)uart, dma, bytes, len, callback, + config); } unsigned int MXC_UART_GetRXFIFOAvailable(mxc_uart_regs_t *uart) { - return MXC_UART_RevB_GetRXFIFOAvailable((mxc_uart_revb_regs_t *)uart); + return MXC_UART_RevA_GetRXFIFOAvailable((mxc_uart_reva_regs_t *)uart); } -unsigned int MXC_UART_WriteTXFIFO(mxc_uart_regs_t *uart, const unsigned char *bytes, - unsigned int len) +unsigned int MXC_UART_WriteTXFIFO(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned int len) { - return MXC_UART_RevB_WriteTXFIFO((mxc_uart_revb_regs_t *)uart, bytes, len); + return MXC_UART_RevA_WriteTXFIFO((mxc_uart_reva_regs_t *)uart, bytes, len); } -int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t *uart, const unsigned char *bytes, unsigned int len, +int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t *uart, mxc_dma_regs_t *dma, unsigned char *bytes, unsigned int len, mxc_uart_dma_complete_cb_t callback) { mxc_dma_config_t config; + config.reqsel = MXC_DMA_REQUEST_UART0TX; // TODO(ME30): Updated DMA reqsel - int uart_num = MXC_UART_GET_IDX(uart); - switch (uart_num) { - case 0: - config.reqsel = MXC_DMA_REQUEST_UART0TX; - break; - - case 1: - config.reqsel = MXC_DMA_REQUEST_UART1TX; - break; - - case 2: - config.reqsel = MXC_DMA_REQUEST_UART2TX; - break; - - case 3: - config.reqsel = MXC_DMA_REQUEST_UART3TX; - break; - - default: - return E_BAD_PARAM; - break; - } - - return MXC_UART_RevB_WriteTXFIFODMA((mxc_uart_revb_regs_t *)uart, bytes, len, callback, config); + return MXC_UART_RevA_WriteTXFIFODMA((mxc_uart_reva_regs_t *)uart, dma, bytes, len, callback, + config); } unsigned int MXC_UART_GetTXFIFOAvailable(mxc_uart_regs_t *uart) { - return MXC_UART_RevB_GetTXFIFOAvailable((mxc_uart_revb_regs_t *)uart); + return MXC_UART_RevA_GetTXFIFOAvailable((mxc_uart_reva_regs_t *)uart); } int MXC_UART_ClearRXFIFO(mxc_uart_regs_t *uart) { - return MXC_UART_RevB_ClearRXFIFO((mxc_uart_revb_regs_t *)uart); + return MXC_UART_RevA_ClearRXFIFO((mxc_uart_reva_regs_t *)uart); } int MXC_UART_ClearTXFIFO(mxc_uart_regs_t *uart) { - return MXC_UART_RevB_ClearTXFIFO((mxc_uart_revb_regs_t *)uart); + return MXC_UART_RevA_ClearTXFIFO((mxc_uart_reva_regs_t *)uart); } int MXC_UART_SetRXThreshold(mxc_uart_regs_t *uart, unsigned int numBytes) { - return MXC_UART_RevB_SetRXThreshold((mxc_uart_revb_regs_t *)uart, numBytes); + return MXC_UART_RevA_SetRXThreshold((mxc_uart_reva_regs_t *)uart, numBytes); } unsigned int MXC_UART_GetRXThreshold(mxc_uart_regs_t *uart) { - return MXC_UART_RevB_GetRXThreshold((mxc_uart_revb_regs_t *)uart); + return MXC_UART_RevA_GetRXThreshold((mxc_uart_reva_regs_t *)uart); } int MXC_UART_SetTXThreshold(mxc_uart_regs_t *uart, unsigned int numBytes) { - return E_NOT_SUPPORTED; + return MXC_UART_RevA_SetTXThreshold((mxc_uart_reva_regs_t *)uart, numBytes); } unsigned int MXC_UART_GetTXThreshold(mxc_uart_regs_t *uart) { - return E_NOT_SUPPORTED; + return MXC_UART_RevA_GetTXThreshold((mxc_uart_reva_regs_t *)uart); } unsigned int MXC_UART_GetFlags(mxc_uart_regs_t *uart) { - return MXC_UART_RevB_GetFlags((mxc_uart_revb_regs_t *)uart); + return MXC_UART_RevA_GetFlags((mxc_uart_reva_regs_t *)uart); } int MXC_UART_ClearFlags(mxc_uart_regs_t *uart, unsigned int flags) { - return MXC_UART_RevB_ClearFlags((mxc_uart_revb_regs_t *)uart, flags); + return MXC_UART_RevA_ClearFlags((mxc_uart_reva_regs_t *)uart, flags); } -int MXC_UART_EnableInt(mxc_uart_regs_t *uart, unsigned int intEn) +int MXC_UART_EnableInt(mxc_uart_regs_t *uart, unsigned int mask) { - return MXC_UART_RevB_EnableInt((mxc_uart_revb_regs_t *)uart, intEn); + return MXC_UART_RevA_EnableInt((mxc_uart_reva_regs_t *)uart, mask); } -int MXC_UART_DisableInt(mxc_uart_regs_t *uart, unsigned int intDis) +int MXC_UART_DisableInt(mxc_uart_regs_t *uart, unsigned int mask) { - return MXC_UART_RevB_DisableInt((mxc_uart_revb_regs_t *)uart, intDis); + return MXC_UART_RevA_DisableInt((mxc_uart_reva_regs_t *)uart, mask); } unsigned int MXC_UART_GetStatus(mxc_uart_regs_t *uart) { - return MXC_UART_RevB_GetStatus((mxc_uart_revb_regs_t *)uart); + return MXC_UART_RevA_GetStatus((mxc_uart_reva_regs_t *)uart); } int MXC_UART_Transaction(mxc_uart_req_t *req) { - return MXC_UART_RevB_Transaction((mxc_uart_revb_req_t *)req); + return MXC_UART_RevA_Transaction((mxc_uart_reva_req_t *)req); } int MXC_UART_TransactionAsync(mxc_uart_req_t *req) { - return MXC_UART_RevB_TransactionAsync((mxc_uart_revb_req_t *)req); + return MXC_UART_RevA_TransactionAsync((mxc_uart_reva_req_t *)req); } -int MXC_UART_TransactionDMA(mxc_uart_req_t *req) +int MXC_UART_TransactionDMA(mxc_uart_req_t *req, mxc_dma_regs_t *dma) { - return MXC_UART_RevB_TransactionDMA((mxc_uart_revb_req_t *)req); + return MXC_UART_RevA_TransactionDMA((mxc_uart_reva_req_t *)req, dma); } int MXC_UART_AbortAsync(mxc_uart_regs_t *uart) { - return MXC_UART_RevB_AbortAsync((mxc_uart_revb_regs_t *)uart); + return MXC_UART_RevA_AbortAsync((mxc_uart_reva_regs_t *)uart); +} + +int MXC_UART_TxAbortAsync(mxc_uart_regs_t *uart) +{ + return MXC_UART_RevA_TxAbortAsync((mxc_uart_reva_regs_t *)uart); +} + +int MXC_UART_RxAbortAsync(mxc_uart_regs_t *uart) +{ + return MXC_UART_RevA_RxAbortAsync((mxc_uart_reva_regs_t *)uart); } int MXC_UART_AsyncHandler(mxc_uart_regs_t *uart) { - return MXC_UART_RevB_AsyncHandler((mxc_uart_revb_regs_t *)uart); + return MXC_UART_RevA_AsyncHandler((mxc_uart_reva_regs_t *)uart); } uint32_t MXC_UART_GetAsyncTXCount(mxc_uart_req_t *req) @@ -504,25 +319,21 @@ uint32_t MXC_UART_GetAsyncRXCount(mxc_uart_req_t *req) int MXC_UART_SetAutoDMAHandlers(mxc_uart_regs_t *uart, bool enable) { - return MXC_UART_RevB_SetAutoDMAHandlers((mxc_uart_revb_regs_t *)uart, enable); + return MXC_UART_RevA_SetAutoDMAHandlers((mxc_uart_reva_regs_t *)uart, enable); } - int MXC_UART_SetTXDMAChannel(mxc_uart_regs_t *uart, unsigned int channel) { - return MXC_UART_RevB_SetTXDMAChannel((mxc_uart_revb_regs_t *)uart, channel); + return MXC_UART_RevA_SetTXDMAChannel((mxc_uart_reva_regs_t *)uart, channel); } - int MXC_UART_GetTXDMAChannel(mxc_uart_regs_t *uart) { - return MXC_UART_RevB_GetTXDMAChannel((mxc_uart_revb_regs_t *)uart); + return MXC_UART_RevA_GetTXDMAChannel((mxc_uart_reva_regs_t *)uart); } - int MXC_UART_SetRXDMAChannel(mxc_uart_regs_t *uart, unsigned int channel) { - return MXC_UART_RevB_SetRXDMAChannel((mxc_uart_revb_regs_t *)uart, channel); + return MXC_UART_RevA_SetRXDMAChannel((mxc_uart_reva_regs_t *)uart, channel); } - int MXC_UART_GetRXDMAChannel(mxc_uart_regs_t *uart) { - return MXC_UART_RevB_GetTXDMAChannel((mxc_uart_revb_regs_t *)uart); + return MXC_UART_RevA_GetRXDMAChannel((mxc_uart_reva_regs_t *)uart); } diff --git a/Libraries/PeriphDrivers/Source/UART/uart_reva.c b/Libraries/PeriphDrivers/Source/UART/uart_reva.c index 2256afe35a1..5ba07b5c3e4 100644 --- a/Libraries/PeriphDrivers/Source/UART/uart_reva.c +++ b/Libraries/PeriphDrivers/Source/UART/uart_reva.c @@ -48,6 +48,7 @@ typedef struct { int channelTx; int channelRx; bool auto_dma_handlers; + mxc_dma_regs_t *dma; } uart_reva_req_state_t; uart_reva_req_state_t states[MXC_UART_INSTANCES]; @@ -99,6 +100,7 @@ int MXC_UART_RevA_Init(mxc_uart_reva_regs_t *uart, unsigned int baud) states[i].tx_req = NULL; states[i].rx_req = NULL; states[i].auto_dma_handlers = false; + states[i].dma = NULL; return E_NO_ERROR; } @@ -502,7 +504,13 @@ unsigned int MXC_UART_RevA_ReadRXFIFO(mxc_uart_reva_regs_t *uart, unsigned char return read; } -#if MXC_DMA_INSTANCES > 1 + +// TODO(DMA): Replaced the DMA instance number check to the only +// parts affected by this. Our DMA drivers probably +// needs a rework to handle multiple instances because +// the ME14's DMA drivers are very limited with +// the DMA instance selection. +#if (TARGET_NUM == 32665 || TARGET_NUM == 32657) void MXC_UART_RevA_DMA0_Handler(void) { @@ -522,19 +530,21 @@ DMA instance. void MXC_UART_RevA_DMA_SetupAutoHandlers(mxc_dma_regs_t *dma_instance, unsigned int channel) { #ifdef __arm__ - NVIC_EnableIRQ(MXC_DMA_CH_GET_IRQ(channel)); +#if (TARGET_NUM == 32665 || TARGET_NUM == 32657) + NVIC_EnableIRQ(MXC_DMA_CH_GET_IRQ(dma_instance, channel)); -#if MXC_DMA_INSTANCES > 1 /* (JC): This is not the cleanest or most scalable way to do this, but I tried defining default handler's in the system file. Some complications make this the most attractive short-term option. We could handle multiple DMA instances better in the DMA API (See the mismatch between the size of "dma_resource" array and the number of channels per instance, to start)*/ if (dma_instance == MXC_DMA0) { - MXC_NVIC_SetVector(MXC_DMA_CH_GET_IRQ(channel), MXC_UART_RevA_DMA0_Handler); + MXC_NVIC_SetVector(MXC_DMA_CH_GET_IRQ(dma_instance, channel), MXC_UART_RevA_DMA0_Handler); } else if (dma_instance == MXC_DMA1) { - MXC_NVIC_SetVector(MXC_DMA_CH_GET_IRQ(channel), MXC_UART_RevA_DMA1_Handler); + MXC_NVIC_SetVector(MXC_DMA_CH_GET_IRQ(dma_instance, channel), MXC_UART_RevA_DMA1_Handler); } #else + NVIC_EnableIRQ(MXC_DMA_CH_GET_IRQ(channel)); + // Only one DMA instance, we can point direct to MXC_DMA_Handler MXC_NVIC_SetVector(MXC_DMA_CH_GET_IRQ(channel), MXC_DMA_Handler); #endif // MXC_DMA_INSTANCES > 1 @@ -560,7 +570,7 @@ int MXC_UART_RevA_ReadRXFIFODMA(mxc_uart_reva_regs_t *uart, mxc_dma_regs_t *dma, if (states[uart_num].auto_dma_handlers && states[uart_num].channelRx < 0) { /* Acquire channel if we don't have one already */ -#if MXC_DMA_INSTANCES > 1 +#if MXC_DMA_INSTANCES > 1 || TARGET_NUM == 32657 channel = MXC_DMA_AcquireChannel(dma); #else channel = MXC_DMA_AcquireChannel(); @@ -591,7 +601,13 @@ int MXC_UART_RevA_ReadRXFIFODMA(mxc_uart_reva_regs_t *uart, mxc_dma_regs_t *dma, MXC_DMA_ConfigChannel(config, srcdst); MXC_DMA_SetCallback(channel, MXC_UART_DMACallback); + +#if (TARGET_NUM == 32657) + MXC_DMA_EnableInt(dma, channel); +#else MXC_DMA_EnableInt(channel); +#endif + MXC_DMA_Start(channel); //MXC_DMA->ch[channel].ctrl |= MXC_F_DMA_CTRL_CTZ_IE; MXC_DMA_SetChannelInterruptEn(channel, 0, 1); @@ -679,7 +695,7 @@ unsigned int MXC_UART_RevA_WriteTXFIFODMA(mxc_uart_reva_regs_t *uart, mxc_dma_re if (states[uart_num].auto_dma_handlers && states[uart_num].channelTx < 0) { /* Acquire channel if we don't have one already */ -#if TARGET_NUM == 32665 +#if (TARGET_NUM == 32665 || TARGET_NUM == 32657) channel = MXC_DMA_AcquireChannel(dma); #else channel = MXC_DMA_AcquireChannel(); @@ -708,7 +724,13 @@ unsigned int MXC_UART_RevA_WriteTXFIFODMA(mxc_uart_reva_regs_t *uart, mxc_dma_re MXC_DMA_ConfigChannel(config, srcdst); MXC_DMA_SetCallback(channel, MXC_UART_DMACallback); + +#if (TARGET_NUM == 32657) + MXC_DMA_EnableInt(dma, channel); +#else MXC_DMA_EnableInt(channel); +#endif + MXC_DMA_Start(channel); //MXC_DMA->ch[channel].ctrl |= MXC_F_DMA_CTRL_CTZ_IE; MXC_DMA_SetChannelInterruptEn(channel, 0, 1); @@ -951,6 +973,9 @@ int MXC_UART_RevA_TransactionDMA(mxc_uart_reva_req_t *req, mxc_dma_regs_t *dma) { int uart_num = MXC_UART_GET_IDX((mxc_uart_regs_t *)(req->uart)); + // Save DMA instance for DMA Callback. + states[uart_num].dma = dma; + if (req->txLen) { if (req->txData == NULL) { return E_BAD_PARAM; @@ -976,7 +1001,7 @@ int MXC_UART_RevA_TransactionDMA(mxc_uart_reva_req_t *req, mxc_dma_regs_t *dma) (req->uart)->dma |= (2 << MXC_F_UART_REVA_DMA_TXDMA_LEVEL_POS); // Set TX DMA threshold to 2 bytes -#if TARGET_NUM == 32665 +#if (TARGET_NUM == 32665 || TARGET_NUM == 32657) MXC_DMA_Init(dma); #else MXC_DMA_Init(); @@ -990,7 +1015,7 @@ int MXC_UART_RevA_TransactionDMA(mxc_uart_reva_req_t *req, mxc_dma_regs_t *dma) if ((req->txData != NULL) && (req->txLen)) { /* Save TX req, the DMA handler will use this later. */ states[uart_num].tx_req = req; -#if TARGET_NUM == 32665 +#if (TARGET_NUM == 32665 || TARGET_NUM == 32657) if (MXC_UART_WriteTXFIFODMA((mxc_uart_regs_t *)(req->uart), dma, req->txData, req->txLen, NULL) != E_NO_ERROR) { return E_BAD_PARAM; @@ -1005,7 +1030,7 @@ int MXC_UART_RevA_TransactionDMA(mxc_uart_reva_req_t *req, mxc_dma_regs_t *dma) if ((req->rxData != NULL) && (req->rxLen)) { states[uart_num].rx_req = req; -#if TARGET_NUM == 32665 +#if (TARGET_NUM == 32665 || TARGET_NUM == 32657) if (MXC_UART_ReadRXFIFODMA((mxc_uart_regs_t *)(req->uart), dma, req->rxData, req->rxLen, NULL) != E_NO_ERROR) { return E_BAD_PARAM; @@ -1029,7 +1054,7 @@ void MXC_UART_RevA_DMACallback(int ch, int error) if (states[i].channelTx == ch) { /* Populate txLen. The number of "remainder" bytes is what's left on the DMA channel's count register. */ - states[i].tx_req->txCnt = states[i].tx_req->txLen - MXC_DMA->ch[ch].cnt; + states[i].tx_req->txCnt = states[i].tx_req->txLen - states[i].dma->ch[ch].cnt; temp_req = states[i].tx_req; @@ -1051,7 +1076,7 @@ void MXC_UART_RevA_DMACallback(int ch, int error) break; } else if (states[i].channelRx == ch) { /* Same as above, but for RX */ - states[i].rx_req->rxCnt = states[i].rx_req->rxLen - MXC_DMA->ch[ch].cnt; + states[i].rx_req->rxCnt = states[i].rx_req->rxLen - states[i].dma->ch[ch].cnt; temp_req = states[i].rx_req; if (states[i].auto_dma_handlers) { MXC_DMA_ReleaseChannel(ch); diff --git a/Libraries/PeriphDrivers/Source/WDT/wdt_me30.c b/Libraries/PeriphDrivers/Source/WDT/wdt_me30.c index 0c761e70c7e..8c1af1514bf 100644 --- a/Libraries/PeriphDrivers/Source/WDT/wdt_me30.c +++ b/Libraries/PeriphDrivers/Source/WDT/wdt_me30.c @@ -29,27 +29,22 @@ int MXC_WDT_Init(mxc_wdt_regs_t *wdt, mxc_wdt_cfg_t *cfg) { #ifndef MSDK_NO_GPIO_CLK_INIT - if (wdt == MXC_WDT0) { - MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_WDT0); - } else if (wdt == MXC_WDT1) { - MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_WDT1); + if (wdt == MXC_WDT) { + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_WDT); } else { return E_BAD_PARAM; } #endif - MXC_WDT_RevB_Init((mxc_wdt_revb_regs_t *)wdt, (mxc_wdt_revb_cfg_t *)cfg); - - return E_NO_ERROR; + return MXC_WDT_RevB_Init((mxc_wdt_revb_regs_t *)wdt, (mxc_wdt_revb_cfg_t *)cfg); } int MXC_WDT_Shutdown(mxc_wdt_regs_t *wdt) { - if (wdt == MXC_WDT0) { - MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_WDT0); - } else if (wdt == MXC_WDT1) { - MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_WDT1); - } else { + if (wdt == MXC_WDT) { + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_WDT); + } + else { return E_BAD_PARAM; } @@ -127,24 +122,12 @@ int MXC_WDT_SetClockSource(mxc_wdt_regs_t *wdt, mxc_wdt_clock_t clock_source) uint8_t idx = 0; uint8_t instance = 0; -#if TARGET_NUM == 32655 || TARGET_NUM == 78000 - mxc_wdt_clock_t clock_sources[2][8] = { + mxc_wdt_clock_t clock_sources[1][8] = { { MXC_WDT_PCLK, MXC_WDT_IBRO_CLK, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, - { MXC_WDT_IBRO_CLK, MXC_WDT_INRO_CLK, MXC_WDT_ERTCO_CLK, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF } }; -#elif TARGET_NUM == 32680 - mxc_wdt_clock_t clock_sources[2][8] = { - { MXC_WDT_PCLK, MXC_WDT_IBRO_CLK, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, - { MXC_WDT_IBRO_CLK, 0xFF, MXC_WDT_INRO_CLK, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF } - }; -#else -#error ME17 WDT driver does not support given target number. -#endif - if (wdt == MXC_WDT0) { + if (wdt == MXC_WDT) { instance = 0; - } else if (wdt == MXC_WDT1) { - instance = 1; } else { return E_BAD_PARAM; } diff --git a/Libraries/PeriphDrivers/max32657_files.mk b/Libraries/PeriphDrivers/max32657_files.mk index afaccda46e3..c8ed1baecaf 100644 --- a/Libraries/PeriphDrivers/max32657_files.mk +++ b/Libraries/PeriphDrivers/max32657_files.mk @@ -50,4 +50,67 @@ PERIPH_DRIVER_INCLUDE_DIR += $(INCLUDE_DIR)/$(TARGET_UC)/ PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/mxc_assert.c PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/mxc_delay.c PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/mxc_lock.c +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/sys_me30.c +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/pins_me30.c + +PERIPH_DRIVER_INCLUDE_DIR += $(SOURCE_DIR)/AES +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/AES/aes_me30.c +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/AES/aes_revb.c + +PERIPH_DRIVER_INCLUDE_DIR += $(SOURCE_DIR)/CRC +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/CRC/crc_me30.c +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/CRC/crc_reva.c + +PERIPH_DRIVER_INCLUDE_DIR += $(SOURCE_DIR)/DMA +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/DMA/dma_me30.c +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/DMA/dma_reva.c + +PERIPH_DRIVER_INCLUDE_DIR += $(SOURCE_DIR)/FLC +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/FLC/flc_common.c +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/FLC/flc_me30.c +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/FLC/flc_reva.c + +PERIPH_DRIVER_INCLUDE_DIR += $(SOURCE_DIR)/GPIO +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/GPIO/gpio_common.c +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/GPIO/gpio_me30.c +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/GPIO/gpio_reva.c + +PERIPH_DRIVER_INCLUDE_DIR += $(SOURCE_DIR)/ICC +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/ICC/icc_me30.c +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/ICC/icc_reva.c + +# TODO(ME30): Add LP drivers back in when register files are provided +# PERIPH_DRIVER_INCLUDE_DIR += $(SOURCE_DIR)/LP +# PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/LP/lp_me30.c + +PERIPH_DRIVER_INCLUDE_DIR += $(SOURCE_DIR)/RTC +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/RTC/rtc_me30.c +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/RTC/rtc_reva.c + +PERIPH_DRIVER_INCLUDE_DIR += $(SOURCE_DIR)/SPI +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SPI/spi_me30.c +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SPI/spi_reva1.c + +PERIPH_DRIVER_INCLUDE_DIR += $(SOURCE_DIR)/TMR +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/TMR/tmr_common.c +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/TMR/tmr_me30.c +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/TMR/tmr_revb.c + +PERIPH_DRIVER_INCLUDE_DIR += $(SOURCE_DIR)/TRNG +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/TRNG/trng_me30.c +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/TRNG/trng_revb.c + +PERIPH_DRIVER_INCLUDE_DIR += $(SOURCE_DIR)/UART +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/UART/uart_common.c +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/UART/uart_me30.c +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/UART/uart_reva.c + +PERIPH_DRIVER_INCLUDE_DIR += $(SOURCE_DIR)/WDT +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/WDT/wdt_common.c +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/WDT/wdt_me30.c +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/WDT/wdt_reva.c + +PERIPH_DRIVER_INCLUDE_DIR += $(SOURCE_DIR)/WUT +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/WUT/wut_me30.c +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/WUT/wut_reva.c