diff --git a/Libraries/CMSIS/Device/Maxim/GCC/gcc.mk b/Libraries/CMSIS/Device/Maxim/GCC/gcc.mk index 8b434adada0..873d657f568 100644 --- a/Libraries/CMSIS/Device/Maxim/GCC/gcc.mk +++ b/Libraries/CMSIS/Device/Maxim/GCC/gcc.mk @@ -278,6 +278,8 @@ ifeq "$(MSECURITY_MODE)" "SECURE" # https://developer.arm.com/documentation/ecm0359818/latest PROJ_CFLAGS += -mcmse +PROJ_AFLAGS += -DIS_SECURE_ENVRIONMENT + # Tell the linker we are building a secure project. This defines the "SECURE_LINK" symbol which the # linker uses to set the secure FLASH/SRAM memory address ranges. PROJ_LDFLAGS += -Xlinker --defsym=SECURE_LINK=1 diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h index 065c785951e..24a89242cdd 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h @@ -59,7 +59,6 @@ /* ================================================================================ */ // clang-format off -// TODO(ME30): Secure vs non-secure interrupt vectors typedef enum { NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, @@ -97,10 +96,10 @@ typedef enum { DMA0_CH1_IRQn, /* 0x21 0x0084 33: DMA0 Channel 1 */ DMA0_CH2_IRQn, /* 0x22 0x0088 34: DMA0 Channel 2 */ DMA0_CH3_IRQn, /* 0x23 0x008C 35: DMA0 Channel 3 */ - DMA1_CH0_IRQn, /* 0x24 0x0090 36: DMA1 Channel 0 */ - DMA1_CH1_IRQn, /* 0x25 0x0094 37: DMA1 Channel 1 */ - DMA1_CH2_IRQn, /* 0x26 0x0098 38: DMA1 CHannel 2 */ - DMA1_CH3_IRQn, /* 0x27 0x009C 39: DMA1 Channel 3 */ + DMA1_CH0_IRQn, /* 0x24 0x0090 36: DMA1 Channel 0 (Secure) */ + DMA1_CH1_IRQn, /* 0x25 0x0094 37: DMA1 Channel 1 (Secure) */ + DMA1_CH2_IRQn, /* 0x26 0x0098 38: DMA1 CHannel 2 (Secure) */ + DMA1_CH3_IRQn, /* 0x27 0x009C 39: DMA1 Channel 3 (Secure) */ WUT0_IRQn, /* 0x28 0x00A0 40: Wakeup Timer 0 */ WUT1_IRQn, /* 0x29 0x00A4 41: Wakeup TImer 1 */ GPIOWAKE_IRQn, /* 0x2A 0x00A8 42: GPIO Wakeup */ @@ -233,8 +232,10 @@ typedef enum { #define MXC_SIR_S ((mxc_sir_regs_t *)MXC_BASE_SIR_S) #if IS_SECURE_ENVIRONMENT +#define MXC_BASE_SIR MXC_BASE_SIR_S #define MXC_SIR MXC_SIR_S #else +#define MXC_BASE_SIR MXC_BASE_SIR_NS #define MXC_SIR MXC_SIR_NS #endif @@ -250,8 +251,10 @@ typedef enum { #define MXC_FCR_S ((mxc_fcr_regs_t *)MXC_BASE_FCR_S) #if IS_SECURE_ENVIRONMENT +#define MXC_BASE_FCR MXC_BASE_FCR_S #define MXC_FCR MXC_FCR_S #else +#define MXC_BASE_FCR MXC_BASE_FCR_NS #define MXC_FCR MXC_FCR_NS #endif @@ -268,8 +271,10 @@ typedef enum { #define MXC_WDT_S ((mxc_wdt_regs_t *)MXC_BASE_WDT_S) #if IS_SECURE_ENVIRONMENT +#define MXC_BASE_WDT MXC_BASE_WDT_S #define MXC_WDT MXC_WDT_S #else +#define MXC_BASE_WDT MXC_BASE_WDT_NS #define MXC_WDT MXC_WDT_NS #endif @@ -278,15 +283,17 @@ typedef enum { /* Non-secure Mapping */ #define MXC_BASE_SVM_NS ((uint32_t)0x40004800UL) -#define MXC_SVM_NS //TODO(ME30): Add SVM controller registers. +#define MXC_SVM_NS 0 //TODO(ME30): Add SVM controller registers. /* Secure Mapping */ #define MXC_BASE_SVM_S ((uint32_t)0x50004800UL) -#define MXC_SVM_S //TODO(ME30): Add SVM controller registers. +#define MXC_SVM_S 0 //TODO(ME30): Add SVM controller registers. #if IS_SECURE_ENVIRONMENT +#define MXC_BASE_SVM MXC_BASE_SVM_S #define MXC_SVM MXC_SVM_S //TODO(ME30): Add SVM controller registers #else +#define MXC_BASE_SVM MXC_BASE_SVM_NS #define MXC_SVM MXC_SVM_NS #endif @@ -295,15 +302,17 @@ typedef enum { /* Non-secure Mapping */ #define MXC_BASE_BOOST_NS ((uint32_t)0x40004C00UL) -#define MXC_BOOST_NS //TODO(ME30): Add Boost controller registers. +#define MXC_BOOST_NS 0 //TODO(ME30): Add Boost controller registers. /* Secure Mapping */ #define MXC_BASE_BOOST_S ((uint32_t)0x50004C00UL) -#define MXC_BOOST_S //TODO(ME30): Add Boost controller registers. +#define MXC_BOOST_S 0 //TODO(ME30): Add Boost controller registers. #if IS_SECURE_ENVIRONMENT +#define MXC_BASE_BOOST MXC_BASE_BOOST_S #define MXC_BOOST MXC_BOOST_S #else +#define MXC_BASE_BOOST MXC_BASE_BOOST_NS #define MXC_BOOST MXC_BOOST_NS #endif @@ -319,8 +328,10 @@ typedef enum { #define MXC_TRIMSIR_S ((mxc_trimsir_regs_t *)MXC_BASE_TRIMSIR_S) #if IS_SECURE_ENVIRONMENT +#define MXC_BASE_TRIMSIR MXC_BASE_TRIMSIR_S #define MXC_TRIMSIR MXC_TRIMSIR_S #else +#define MXC_BASE_TRIMSIR MXC_BASE_TRIMSIR_NS #define MXC_TRIMSIR MXC_TRIMSIR_NS #endif @@ -336,8 +347,10 @@ typedef enum { #define MXC_RTC_S ((mxc_rtc_regs_t *)MXC_BASE_RTC_S) #if IS_SECURE_ENVIRONMENT +#define MXC_BASE_RTC MXC_BASE_RTC_S #define MXC_RTC MXC_RTC_S #else +#define MXC_BASE_RTC MXC_BASE_RTC_NS #define MXC_RTC MXC_RTC_NS #endif @@ -358,10 +371,14 @@ typedef enum { #define MXC_WUT1_S ((mxc_wut_regs_t *)MXC_BASE_WUT1_S) #if IS_SECURE_ENVIRONMENT +#define MXC_BASE_WUT0 MXC_BASE_WUT0_S #define MXC_WUT0 MXC_WUT0_S +#define MXC_BASE_WUT1 MXC_BASE_WUT1_S #define MXC_WUT1 MXC_WUT1_S #else +#define MXC_BASE_WUT0 MXC_BASE_WUT0_NS #define MXC_WUT0 MXC_WUT0_NS +#define MXC_BASE_WUT1 MXC_BASE_WUT1_NS #define MXC_WUT1 MXC_WUT1_NS #endif @@ -377,8 +394,10 @@ typedef enum { #define MXC_PWRSEQ_S ((mxc_pwrseq_regs_t *)MXC_BASE_PWRSEQ_S) #if IS_SECURE_ENVIRONMENT +#define MXC_BASE_PWRSEQ MXC_BASE_PWRSEQ_S #define MXC_PWRSEQ MXC_PWRSEQ_S #else +#define MXC_BASE_PWRSEQ MXC_BASE_PWRSEQ_NS #define MXC_PWRSEQ MXC_PWRSEQ_NS #endif @@ -394,9 +413,11 @@ typedef enum { #define MXC_MCR_S ((mxc_mcr_regs_t *)MXC_BASE_MCR_S) #if IS_SECURE_ENVIRONMENT +#define MXC_BASE_MCR MXC_BASE_MCR_S #define MXC_MCR MXC_MCR_S #else -#define MXC_MCR MXC_MCR_S +#define MXC_BASE_MCR MXC_BASE_MCR_NS +#define MXC_MCR MXC_MCR_NS #endif /******************************************************************************/ @@ -411,8 +432,10 @@ typedef enum { #define MXC_AES_S ((mxc_aes_regs_t *)MXC_BASE_AES_NS) #if IS_SECURE_ENVIRONMENT +#define MXC_BASE_AES MXC_BASE_AES_S #define MXC_AES MXC_AES_S #else +#define MXC_BASE_AES MXC_BASE_AES_NS #define MXC_AES MXC_AES_NS #endif @@ -428,8 +451,10 @@ typedef enum { #define MXC_AESKEYS_S ((mxc_aeskeys_regs_t *)MXC_BASE_AESKEYS_S) #if IS_SECURE_ENVIRONMENT +#define MXC_BASE_AESKEYS MXC_BASE_AESKEYS_S #define MXC_AESKEYS MXC_AESKEYS_S #else +#define MXC_BASE_AESKEYS MXC_BASE_AESKEYS_NS #define MXC_AESKEYS MXC_AESKEYS_NS #endif @@ -449,11 +474,11 @@ typedef enum { #define MXC_BASE_GPIO0_S ((uint32_t)0x50008000UL) #define MXC_GPIO0_S ((mxc_gpio_regs_t *)MXC_BASE_GPIO0_S) -#define MXC_BASE_GPIO0 MXC_BASE_GPIO0_S - #if IS_SECURE_ENVIRONMENT +#define MXC_BASE_GPIO0 MXC_BASE_GPIO0_S #define MXC_GPIO0 MXC_GPIO0_S #else +#define MXC_BASE_GPIO0 MXC_BASE_GPIO0_NS #define MXC_GPIO0 MXC_GPIO0_NS #endif @@ -480,8 +505,10 @@ We may want to handle GET_IRQ better... #define MXC_CRC_S ((mxc_crc_regs_t *)MXC_BASE_CRC_S) #if IS_SECURE_ENVIRONMENT +#define MXC_BASE_CRC MXC_BASE_CRC_S #define MXC_CRC MXC_CRC_S #else +#define MXC_BASE_CRC MXC_BASE_CRC_NS #define MXC_CRC MXC_CRC_NS #endif @@ -507,24 +534,6 @@ We may want to handle GET_IRQ better... #define MXC_BASE_TMR5_NS ((uint32_t)0x40081000UL) #define MXC_TMR5_NS ((mxc_tmr_regs_t *)MXC_BASE_TMR5_NS) -#define MXC_TMR_NS_GET_BASE(i) \ - ((i) == 0 ? MXC_BASE_TMR0_NS : \ - (i) == 1 ? MXC_BASE_TMR1_NS : \ - (i) == 2 ? MXC_BASE_TMR2_NS : \ - (i) == 3 ? MXC_BASE_TMR3_NS : \ - (i) == 4 ? MXC_BASE_TMR4_NS : \ - (i) == 5 ? MXC_BASE_TMR5_NS : \ - 0) - -#define MXC_TMR_NS_GET_TMR(i) \ - ((i) == 0 ? MXC_TMR0_NS : \ - (i) == 1 ? MXC_TMR1_NS : \ - (i) == 2 ? MXC_TMR2_NS : \ - (i) == 3 ? MXC_TMR3_NS : \ - (i) == 4 ? MXC_TMR4_NS : \ - (i) == 5 ? MXC_TMR5_NS : \ - 0) - /* Secure Mapping */ #define MXC_BASE_TMR0_S ((uint32_t)0x50010000UL) #define MXC_TMR0_S ((mxc_tmr_regs_t *)MXC_BASE_TMR0_S) @@ -555,7 +564,16 @@ We may want to handle GET_IRQ better... #define MXC_TMR5 MXC_TMR5_NS #endif -#define MXC_TMR_S_GET_TMR(i) \ +#define MXC_TMR_GET_BASE(i) \ + ((i) == 0 ? MXC_BASE_TMR0 : \ + (i) == 1 ? MXC_BASE_TMR1 : \ + (i) == 2 ? MXC_BASE_TMR2 : \ + (i) == 3 ? MXC_BASE_TMR3 : \ + (i) == 4 ? MXC_BASE_TMR4 : \ + (i) == 5 ? MXC_BASE_TMR5 : \ + 0) + +#define MXC_TMR_GET_TMR(i) \ ((i) == 0 ? MXC_TMR0 : \ (i) == 1 ? MXC_TMR1 : \ (i) == 2 ? MXC_TMR2 : \ @@ -574,19 +592,13 @@ We may want to handle GET_IRQ better... 0) #define MXC_TMR_GET_IDX(p) \ - ((p) == MXC_TMR0_NS ? 0 : \ - (p) == MXC_TMR1_NS ? 1 : \ - (p) == MXC_TMR2_NS ? 2 : \ - (p) == MXC_TMR3_NS ? 3 : \ - (p) == MXC_TMR4_NS ? 4 : \ - (p) == MXC_TMR5_NS ? 5 : \ - (p) == MXC_TMR0_S ? 0 : \ - (p) == MXC_TMR1_S ? 1 : \ - (p) == MXC_TMR2_S ? 2 : \ - (p) == MXC_TMR3_S ? 3 : \ - (p) == MXC_TMR4_S ? 4 : \ - (p) == MXC_TMR5_S ? 5 : \ - -1) + ((p) == MXC_TMR0 ? 0 : \ + (p) == MXC_TMR1 ? 1 : \ + (p) == MXC_TMR2 ? 2 : \ + (p) == MXC_TMR3 ? 3 : \ + (p) == MXC_TMR4 ? 4 : \ + (p) == MXC_TMR5 ? 5 : \ + -1) /******************************************************************************/ /* I3C */ @@ -601,52 +613,76 @@ We may want to handle GET_IRQ better... #define MXC_I3C_S ((mxc_i2c_regs_t *)MXC_BASE_I3C_S) #if IS_SECURE_ENVIRONMENT +#define MXC_BASE_I3C MXC_BASE_I3C_S #define MXC_I3C MXC_I3C_S #else +#define MXC_BASE_I3C MXC_BASE_I3C_NS #define MXC_I3C MXC_I3C_NS #endif /******************************************************************************/ /* DMA */ #define MXC_DMA_CHANNELS (4) +#if IS_SECURE_ENVIRONMENT +#define MXC_DMA_INSTANCES (2) +#else #define MXC_DMA_INSTANCES (1) -// ^ Note: We have 2 DMA instances in hardware, but they are secure vs non-secure -// instances. Therefore we treat the part as if there is only 1. +#endif /* Non-secure Mapping */ #define MXC_BASE_DMA0_NS ((uint32_t)0x40028000UL) #define MXC_DMA0_NS ((mxc_dma_regs_t *)MXC_BASE_DMA0_NS) -/* DMA0 instance only for secure mode. */ /* Secure Mapping */ // TODO(ME30): Is there actuall a secure mapping for DMA0? +// -Yes, DMA0 can be accessed from secure mode. Realizing this, I think +// we would still have to define two DMA instances. +// DMA0 can only access the non-secure mappings of the peripherals, +// but DMA0 can be accessed in both Non-secure and Secure code. +// DMA1 can access both secure and non-secure addresses of the peripherals, +// but DMA1 can Only be accessed in Secure code. #define MXC_BASE_DMA0_S ((uint32_t)0x50028000UL) #define MXC_DMA0_S ((mxc_dma_regs_t *)MXC_BASE_DMA0_S) #define MXC_BASE_DMA1_S ((uint32_t)0x50035000UL) #define MXC_DMA1_S ((mxc_dma_regs_t *)MXC_BASE_DMA1_S) +#if IS_SECURE_ENVIRONMENT #define MXC_BASE_DMA0 MXC_BASE_DMA0_S -#define MXC_DMA0 MXC_DMA0_NS +#define MXC_DMA0 MXC_DMA0_S #define MXC_BASE_DMA1 MXC_BASE_DMA1_S #define MXC_DMA1 MXC_DMA1_S -#if IS_SECURE_ENVIRONMENT -#define MXC_DMA MXC_DMA1_S -#define MXC_DMA_CH_GET_IRQ(i) \ - ((IRQn_Type)(((i) == 0) ? DMA1_CH0_IRQn : \ - ((i) == 1) ? DMA1_CH1_IRQn : \ - ((i) == 2) ? DMA1_CH2_IRQn : \ - ((i) == 3) ? DMA1_CH3_IRQn : \ +#define MXC_DMA_CH_GET_IRQ(p, i) \ + ((IRQn_Type)(((p) == MXC_DMA0 && (i) == 0) ? DMA0_CH0_IRQn : \ + ((p) == MXC_DMA0 && (i) == 1) ? DMA0_CH1_IRQn : \ + ((p) == MXC_DMA0 && (i) == 2) ? DMA0_CH2_IRQn : \ + ((p) == MXC_DMA0 && (i) == 3) ? DMA0_CH3_IRQn : \ + ((p) == MXC_DMA1 && (i) == 0) ? DMA1_CH0_IRQn : \ + ((p) == MXC_DMA1 && (i) == 1) ? DMA1_CH1_IRQn : \ + ((p) == MXC_DMA1 && (i) == 2) ? DMA1_CH2_IRQn : \ + ((p) == MXC_DMA1 && (i) == 3) ? DMA1_CH3_IRQn : \ 0)) + #else -#define MXC_DMA MXC_DMA0_NS -#define MXC_DMA_CH_GET_IRQ(i) \ - ((IRQn_Type)(((i) == 0) ? DMA0_CH0_IRQn : \ - ((i) == 1) ? DMA0_CH1_IRQn : \ - ((i) == 2) ? DMA0_CH2_IRQn : \ - ((i) == 3) ? DMA0_CH3_IRQn : \ +#define MXC_BASE_DMA0 MXC_BASE_DMA0_NS +#define MXC_DMA0 MXC_DMA0_NS +// TODO(DMA1): Not entirely show how to handle access to MXC_DMA1 in non-secure mode. +// A secure fault should be generated when non-secure code accesses +// a secure peripheral mapping, so it'd be best if a build time warning +// or error was thrown when using MXCX_DMA1. +#define MXC_BASE_DMA1 0 +#define MXC_DMA1 0 + +/* DMA1 IRQs not usable in Non-Secure state. */ +#define MXC_DMA_CH_GET_IRQ(p, i) \ + ((IRQn_Type)(((p) == MXC_DMA0 && (i) == 0) ? DMA0_CH0_IRQn : \ + ((p) == MXC_DMA0 && (i) == 1) ? DMA0_CH1_IRQn : \ + ((p) == MXC_DMA0 && (i) == 2) ? DMA0_CH2_IRQn : \ + ((p) == MXC_DMA0 && (i) == 3) ? DMA0_CH3_IRQn : \ 0)) -#endif +#endif // IS_SECURE_ENVIRONMENT + +#define MXC_DMA_GET_BASE(i) ((i) == MXC_BASE_DMA0 ? 0 : (p) == MXC_BASE_DMA1 ? 1 : -1) #define MXC_DMA_GET_IDX(p) ((p) == MXC_DMA0 ? 0 : (p) == MXC_DMA1 ? 1 : -1) @@ -662,19 +698,22 @@ We may want to handle GET_IRQ better... #define MXC_BASE_FLC_S MXC_BASE_FLC #define MXC_FLC_S MXC_FLC -// Note(JC): There is only one flash instance, but some bottom-level RevX implementations -// depend on MXC_FLC_GET_FLC -#define MXC_FLC_GET_FLC(i) MXC_FLC +/** + * There is only one flash instance, but some bottom-level RevX implementations + * depend on MXC_FLC_GET_FLC + */ +#define MXC_FLC_GET_FLC(i) ((i) == 0 ? MXC_FLC : 0) /******************************************************************************/ /* Internal Cache Controller */ #define MXC_ICC_INSTANCES (1) /* Secure Mapping Only */ -#define MXC_BASE_ICC_S ((uint32_t)0x5002A000UL) +#define MXC_BASE_ICC ((uint32_t)0x5002A000UL) #define MXC_ICC ((mxc_icc_regs_t *)MXC_BASE_ICC_S) /* Added for consistency and explicitness */ +#define MXC_BASE_ICC_S MXC_BASE_ICC #define MXC_ICC_S MXC_ICC /******************************************************************************/ @@ -691,11 +730,14 @@ We may want to handle GET_IRQ better... #define MXC_UART_S ((mxc_uart_regs_t *)MXC_BASE_UART_S) #if IS_SECURE_ENVIRONMENT +#define MXC_BASE_UART MXC_BASE_UART_S #define MXC_UART MXC_UART_S #else +#define MXC_BASE_UART MXC_BASE_UART_NS #define MXC_UART MXC_UART_NS #endif +#define MXC_UART_GET_BASE(i) ((i) == 0 ? MXC_BASE_UART : 0) #define MXC_UART_GET_UART(i) ((i) == 0 ? MXC_UART : 0) #define MXC_UART_GET_IRQ(i) (IRQn_Type)((i) == 0 ? UART0_IRQn : 0) #define MXC_UART_GET_IDX(p) ((p) == MXC_UART_NS ? 0 : (p) == MXC_UART_S ? 0 : -1) @@ -710,19 +752,19 @@ We may want to handle GET_IRQ better... #define MXC_BASE_SPI_NS ((uint32_t)0x40046000UL) #define MXC_SPI_NS ((mxc_spi_regs_t *)MXC_BASE_SPI_NS) -#define MXC_SPI_NS_GET_BASE(i) ((i) == 0 ? MXC_BASE_SPI_NS : 0) -#define MXC_SPI_NS_GET_SPI(i) ((i) == 0 ? MXC_SPI_NS : 0) - /* Secure Mapping */ #define MXC_BASE_SPI_S ((uint32_t)0x50046000UL) #define MXC_SPI_S ((mxc_spi_regs_t *)MXC_BASE_SPI_S) #if IS_SECURE_ENVIRONMENT +#define MXC_BASE_SPI MXC_BASE_SPI_S #define MXC_SPI MXC_SPI_S #else +#define MXC_BASE_SPI MXC_BASE_SPI_S #define MXC_SPI MXC_SPI_NS #endif +#define MXC_SPI_GET_BASE(i) ((i) == 0 ? MXC_BASE_SPI : 0) #define MXC_SPI_GET_SPI(i) ((i) == 0 ? MXC_SPI : 0) #define MXC_SPI_GET_IRQ(i) (IRQn_Type)((i) == 0 ? SPI_IRQn : 0) #define MXC_SPI_GET_IDX(p) ((p) == MXC_SPI_NS ? 0 : (p) == MXC_SPI_S ? 0 : -1) @@ -739,8 +781,10 @@ We may want to handle GET_IRQ better... #define MXC_TRNG_S ((mxc_trng_regs_t *)MXC_BASE_TRNG_S) #if IS_SECURE_ENVIRONMENT +#define MXC_BASE_TRNG MXC_BASE_TRNG_S #define MXC_TRNG MXC_TRNG_S #else +#define MXC_BASE_TRNG MXC_BASE_TRNG_NS #define MXC_TRNG MXC_TRNG_NS #endif @@ -758,8 +802,10 @@ We may want to handle GET_IRQ better... #if IS_SECURE_ENVIRONMENT // TODO(ME30): Does this have registers? +#define MXC_BASE_BTLE MXC_BASE_BTLE_S #define MXC_BTLE MXC_BTLE_S #else +#define MXC_BASE_BTLE MXC_BASE_BTLE_NS #define MXC_BTLE MXC_BTLE_NS #endif diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/partition_max32657.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/partition_max32657.h new file mode 100644 index 00000000000..5b9fed2bedf --- /dev/null +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/partition_max32657.h @@ -0,0 +1,1285 @@ +/*************************************************************************//** + * @file partition_max32657.h + * @brief CMSIS-Core(M) Device Initial Setup for Secure/Non-Secure Zones for + * MAX32657 + * @version V1.0.0 + * @date 20. January 2021 + *****************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * Portions Copyright (C) 2024 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_SOURCE_GCC_PARTITION_MAX32657_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_SOURCE_GCC_PARTITION_MAX32657_H_ + +#include "max32657.h" + +#if IS_SECURE_ENVIRONMENT + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +*/ + +/* +// Enable SAU +// Value for SAU->CTRL register bit ENABLE +*/ +#define SAU_INIT_CTRL_ENABLE 1 + +/* +// When SAU is disabled +// <0=> All Memory is Secure +// <1=> All Memory is Non-Secure +// Value for SAU->CTRL register bit ALLNS +// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. +*/ +#define SAU_INIT_CTRL_ALLNS 0 + +/* +// +*/ + +/* +// Initialize Security Attribution Unit (SAU) Address Regions +// SAU configuration specifies regions to be one of: +// - Secure and Non-Secure Callable +// - Non-Secure +// Note: All memory regions not configured by SAU are Secure +*/ +/** + * Analog Devices, Inc. + * 4 Regions in the MAX32657. + * 1. Non-Secure Flash + * 2. Secure Flash + * 3. Non-Secure SRAM + * 4. Secure SRAM + * + * Finer grain control can be achieved depending on the application + * requirements by updating the regions of this file. + * + * Non-Secure Flash (1MB) 0x0100.0000 - 0x010F.FFFF + * Non-Secure SRAM0 (32kB) 0x2000.0000 - 0x2000.7FFF + * Non-Secure SRAM1 (32kB) 0x2000.8000 - 0x2000.FFFF + * Non-Secure SRAM2 (64kB) 0x2001.0000 - 0x2001.FFFF + * Non-Secure SRAM3 (64kB) 0x2002.0000 - 0x2002.FFFF + * Non-Secure SRAM4 (64kB) 0x2003.0000 - 0x2003.FFFF + * + * Secure Flash (1MB) 0x1100.0000 - 0x110F.FFFF + * Secure SRAM0 (32kB) 0x3000.0000 - 0x3000.7FFF + * Secure SRAM1 (32kB) 0x3000.8000 - 0x3000.FFFF + * Secure SRAM2 (64kB) 0x3001.0000 - 0x3001.FFFF + * Secure SRAM3 (64kB) 0x3002.0000 - 0x3002.FFFF + * Secure SRAM4 (64kB) 0x3003.0000 - 0x3003.FFFF + */ +#define SAU_REGIONS_MAX 4 /* Max. number of SAU regions */ + +/* +// Initialize SAU Region 0 (Secure Flash) +// Setup SAU Region 0 memory attributes +*/ +#define SAU_INIT_REGION0 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START0 0x11000000 /* start address of SAU region 0 (ROM) */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END0 0x110FFFFF /* end address of SAU region 0 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC0 1 +/* +// +*/ + +/* +// Initialize SAU Region 1 (Non-Secure Flash) +// Setup SAU Region 1 memory attributes +*/ +#define SAU_INIT_REGION1 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START1 0x01000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END1 0x010FFFFF + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC1 0 +/* +// +*/ + +/* +// Initialize SAU Region 2 (Secure SRAM) +// Setup SAU Region 2 memory attributes +*/ +#define SAU_INIT_REGION2 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START2 0x30000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END2 0x3003FFFF + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC2 1 +/* +// +*/ + +/* +// Initialize SAU Region 3 (Non-Secure SRAM) +// Setup SAU Region 3 memory attributes +*/ +#define SAU_INIT_REGION3 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START3 0x20000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END3 0x2003FFFF + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC3 0 +/* +// +*/ + +/* +// Initialize SAU Region 4 +// Setup SAU Region 4 memory attributes +*/ +#define SAU_INIT_REGION4 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC4 0 +/* +// +*/ + +/* +// Initialize SAU Region 5 +// Setup SAU Region 5 memory attributes +*/ +#define SAU_INIT_REGION5 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START5 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END5 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC5 0 +/* +// +*/ + +/* +// Initialize SAU Region 6 +// Setup SAU Region 6 memory attributes +*/ +#define SAU_INIT_REGION6 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START6 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END6 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC6 0 +/* +// +*/ + +/* +// Initialize SAU Region 7 +// Setup SAU Region 7 memory attributes +*/ +#define SAU_INIT_REGION7 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START7 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END7 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC7 0 +/* +// +*/ + +/* +// +*/ + +/* +// Setup behaviour of Sleep and Exception Handling +*/ +#define SCB_CSR_AIRCR_INIT 1 + +/* +// Deep Sleep can be enabled by +// <0=>Secure and Non-Secure state +// <1=>Secure state only +// Value for SCB->CSR register bit DEEPSLEEPS +*/ +#define SCB_CSR_DEEPSLEEPS_VAL 1 + +/* +// System reset request accessible from +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for SCB->AIRCR register bit SYSRESETREQS +*/ +#define SCB_AIRCR_SYSRESETREQS_VAL 1 + +/* +// Priority of Non-Secure exceptions is +// <0=> Not altered +// <1=> Lowered to 0x80-0xFF +// Value for SCB->AIRCR register bit PRIS +*/ +#define SCB_AIRCR_PRIS_VAL 1 + +/* +// BusFault, HardFault, and NMI target +// <0=> Secure state +// <1=> Non-Secure state +// Value for SCB->AIRCR register bit BFHFNMINS +*/ +#define SCB_AIRCR_BFHFNMINS_VAL 0 + +/* +// +*/ + +/* +// Setup behaviour of Floating Point and Vector Unit (FPU/MVE) +*/ +#define TZ_FPU_NS_USAGE 1 + +/* +// Floating Point and Vector Unit usage +// <0=> Secure state only +// <3=> Secure and Non-Secure state +// Value for SCB->NSACR register bits CP10, CP11 +*/ +#define SCB_NSACR_CP10_11_VAL 3 + +/* +// Treat floating-point registers as Secure +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit TS +*/ +#define FPU_FPCCR_TS_VAL 0 + +/* +// Clear on return (CLRONRET) accessibility +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for FPU->FPCCR register bit CLRONRETS +*/ +#define FPU_FPCCR_CLRONRETS_VAL 0 + +/* +// Clear floating-point caller saved registers on exception return +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit CLRONRET +*/ +#define FPU_FPCCR_CLRONRET_VAL 1 + +/* +// +*/ + +/* +// Setup Interrupt Target +*/ + +/* +// Initialize ITNS 0 (Interrupts 0..31) +*/ +#define NVIC_INIT_ITNS0 1 + +/* +// Interrupts 0..31 +// ICE Unlock <0=> Secure state <1=> Non-Secure state +// Watchdog Timer <0=> Secure state <1=> Non-Secure state +// Real Time Clock <0=> Secure state <1=> Non-Secure state +// True Random Number Generator <0=> Secure state <1=> Non-Secure state +// Timer 0 <0=> Secure state <1=> Non-Secure state +// Timer 1 <0=> Secure state <1=> Non-Secure state +// Timer 2 <0=> Secure state <1=> Non-Secure state +// Timer 3 <0=> Secure state <1=> Non-Secure state +// Timer 4 <0=> Secure state <1=> Non-Secure state +// Timer 5 <0=> Secure state <1=> Non-Secure state +// I3C <0=> Secure state <1=> Non-Secure state +// UART <0=> Secure state <1=> Non-Secure state +// SPI <0=> Secure state <1=> Non-Secure state +// Flash Controller <0=> Secure state <1=> Non-Secure state +// GPIO0 <0=> Secure state <1=> Non-Secure state +// Reserved (15) <0=> Secure state <1=> Non-Secure state +// DMA0 Channel 0 <0=> Secure state <1=> Non-Secure state +// DMA0 Channel 1 <0=> Secure state <1=> Non-Secure state +// DMA0 Channel 2 <0=> Secure state <1=> Non-Secure state +// DMA0 Channel 3 <0=> Secure state <1=> Non-Secure state +// DMA1 Channel 0 <0=> Secure state <1=> Non-Secure state +// DMA1 Channel 1 <0=> Secure state <1=> Non-Secure state +// DMA1 Channel 2 <0=> Secure state <1=> Non-Secure state +// DMA1 Channel 3 <0=> Secure state <1=> Non-Secure state +// Wakeup Timer 0 <0=> Secure state <1=> Non-Secure state +// Wakeup Timer 1 <0=> Secure state <1=> Non-Secure state +// GPIO Wake <0=> Secure state <1=> Non-Secure state +// CRC <0=> Secure state <1=> Non-Secure state +// AES <0=> Secure state <1=> Non-Secure state +// ERFO Ready <0=> Secure state <1=> Non-Secure state +// Boost Controller <0=> Secure state <1=> Non-Secure state +// ECC <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS0_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 1 (Interrupts 32..63) +*/ +#define NVIC_INIT_ITNS1 1 + +/* +// Interrupts 32..63 +// BTLE XXXX0 <0=> Secure state <1=> Non-Secure state +// BTLE XXXX1 <0=> Secure state <1=> Non-Secure state +// BTLE XXXX2 <0=> Secure state <1=> Non-Secure state +// BTLE XXXX3 <0=> Secure state <1=> Non-Secure state +// BTLE XXXX4 <0=> Secure state <1=> Non-Secure state +// BTLE XXXX5 <0=> Secure state <1=> Non-Secure state +// BTLE XXXX6 <0=> Secure state <1=> Non-Secure state +// BTLE XXXX7 <0=> Secure state <1=> Non-Secure state +// BTLE XXXX8 <0=> Secure state <1=> Non-Secure state +// BTLE XXXX9 <0=> Secure state <1=> Non-Secure state +// BTLE XXXXA <0=> Secure state <1=> Non-Secure state +// BTLE XXXXB <0=> Secure state <1=> Non-Secure state +// BTLE XXXXC <0=> Secure state <1=> Non-Secure state +// BTLE XXXXD <0=> Secure state <1=> Non-Secure state +// BTLE XXXXE <0=> Secure state <1=> Non-Secure state +// Reserved (47) <0=> Secure state <1=> Non-Secure state +// MPC Combined (Secure) <0=> Secure state <1=> Non-Secure state +// PPC Combined (Secure) <0=> Secure state <1=> Non-Secure state +// Reserved (50) <0=> Secure state <1=> Non-Secure state +// Reserved (51) <0=> Secure state <1=> Non-Secure state +// Reserved (52) <0=> Secure state <1=> Non-Secure state +// Reserved (53) <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS1_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 2 (Interrupts 64..95) +*/ +#define NVIC_INIT_ITNS2 0 + +/* +// Interrupts 64..95 +// Interrupt 64 <0=> Secure state <1=> Non-Secure state +// Interrupt 65 <0=> Secure state <1=> Non-Secure state +// Interrupt 66 <0=> Secure state <1=> Non-Secure state +// Interrupt 67 <0=> Secure state <1=> Non-Secure state +// Interrupt 68 <0=> Secure state <1=> Non-Secure state +// Interrupt 69 <0=> Secure state <1=> Non-Secure state +// Interrupt 70 <0=> Secure state <1=> Non-Secure state +// Interrupt 71 <0=> Secure state <1=> Non-Secure state +// Interrupt 72 <0=> Secure state <1=> Non-Secure state +// Interrupt 73 <0=> Secure state <1=> Non-Secure state +// Interrupt 74 <0=> Secure state <1=> Non-Secure state +// Interrupt 75 <0=> Secure state <1=> Non-Secure state +// Interrupt 76 <0=> Secure state <1=> Non-Secure state +// Interrupt 77 <0=> Secure state <1=> Non-Secure state +// Interrupt 78 <0=> Secure state <1=> Non-Secure state +// Interrupt 79 <0=> Secure state <1=> Non-Secure state +// Interrupt 80 <0=> Secure state <1=> Non-Secure state +// Interrupt 81 <0=> Secure state <1=> Non-Secure state +// Interrupt 82 <0=> Secure state <1=> Non-Secure state +// Interrupt 83 <0=> Secure state <1=> Non-Secure state +// Interrupt 84 <0=> Secure state <1=> Non-Secure state +// Interrupt 85 <0=> Secure state <1=> Non-Secure state +// Interrupt 86 <0=> Secure state <1=> Non-Secure state +// Interrupt 87 <0=> Secure state <1=> Non-Secure state +// Interrupt 88 <0=> Secure state <1=> Non-Secure state +// Interrupt 89 <0=> Secure state <1=> Non-Secure state +// Interrupt 90 <0=> Secure state <1=> Non-Secure state +// Interrupt 91 <0=> Secure state <1=> Non-Secure state +// Interrupt 92 <0=> Secure state <1=> Non-Secure state +// Interrupt 93 <0=> Secure state <1=> Non-Secure state +// Interrupt 94 <0=> Secure state <1=> Non-Secure state +// Interrupt 95 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS2_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 3 (Interrupts 96..127) +*/ +#define NVIC_INIT_ITNS3 0 + +/* +// Interrupts 96..127 +// Interrupt 96 <0=> Secure state <1=> Non-Secure state +// Interrupt 97 <0=> Secure state <1=> Non-Secure state +// Interrupt 98 <0=> Secure state <1=> Non-Secure state +// Interrupt 99 <0=> Secure state <1=> Non-Secure state +// Interrupt 100 <0=> Secure state <1=> Non-Secure state +// Interrupt 101 <0=> Secure state <1=> Non-Secure state +// Interrupt 102 <0=> Secure state <1=> Non-Secure state +// Interrupt 103 <0=> Secure state <1=> Non-Secure state +// Interrupt 104 <0=> Secure state <1=> Non-Secure state +// Interrupt 105 <0=> Secure state <1=> Non-Secure state +// Interrupt 106 <0=> Secure state <1=> Non-Secure state +// Interrupt 107 <0=> Secure state <1=> Non-Secure state +// Interrupt 108 <0=> Secure state <1=> Non-Secure state +// Interrupt 109 <0=> Secure state <1=> Non-Secure state +// Interrupt 110 <0=> Secure state <1=> Non-Secure state +// Interrupt 111 <0=> Secure state <1=> Non-Secure state +// Interrupt 112 <0=> Secure state <1=> Non-Secure state +// Interrupt 113 <0=> Secure state <1=> Non-Secure state +// Interrupt 114 <0=> Secure state <1=> Non-Secure state +// Interrupt 115 <0=> Secure state <1=> Non-Secure state +// Interrupt 116 <0=> Secure state <1=> Non-Secure state +// Interrupt 117 <0=> Secure state <1=> Non-Secure state +// Interrupt 118 <0=> Secure state <1=> Non-Secure state +// Interrupt 119 <0=> Secure state <1=> Non-Secure state +// Interrupt 120 <0=> Secure state <1=> Non-Secure state +// Interrupt 121 <0=> Secure state <1=> Non-Secure state +// Interrupt 122 <0=> Secure state <1=> Non-Secure state +// Interrupt 123 <0=> Secure state <1=> Non-Secure state +// Interrupt 124 <0=> Secure state <1=> Non-Secure state +// Interrupt 125 <0=> Secure state <1=> Non-Secure state +// Interrupt 126 <0=> Secure state <1=> Non-Secure state +// Interrupt 127 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS3_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 4 (Interrupts 128..159) +*/ +#define NVIC_INIT_ITNS4 0 + +/* +// Interrupts 128..159 +// Interrupt 128 <0=> Secure state <1=> Non-Secure state +// Interrupt 129 <0=> Secure state <1=> Non-Secure state +// Interrupt 130 <0=> Secure state <1=> Non-Secure state +// Interrupt 131 <0=> Secure state <1=> Non-Secure state +// Interrupt 132 <0=> Secure state <1=> Non-Secure state +// Interrupt 133 <0=> Secure state <1=> Non-Secure state +// Interrupt 134 <0=> Secure state <1=> Non-Secure state +// Interrupt 135 <0=> Secure state <1=> Non-Secure state +// Interrupt 136 <0=> Secure state <1=> Non-Secure state +// Interrupt 137 <0=> Secure state <1=> Non-Secure state +// Interrupt 138 <0=> Secure state <1=> Non-Secure state +// Interrupt 139 <0=> Secure state <1=> Non-Secure state +// Interrupt 140 <0=> Secure state <1=> Non-Secure state +// Interrupt 141 <0=> Secure state <1=> Non-Secure state +// Interrupt 142 <0=> Secure state <1=> Non-Secure state +// Interrupt 143 <0=> Secure state <1=> Non-Secure state +// Interrupt 144 <0=> Secure state <1=> Non-Secure state +// Interrupt 145 <0=> Secure state <1=> Non-Secure state +// Interrupt 146 <0=> Secure state <1=> Non-Secure state +// Interrupt 147 <0=> Secure state <1=> Non-Secure state +// Interrupt 148 <0=> Secure state <1=> Non-Secure state +// Interrupt 149 <0=> Secure state <1=> Non-Secure state +// Interrupt 150 <0=> Secure state <1=> Non-Secure state +// Interrupt 151 <0=> Secure state <1=> Non-Secure state +// Interrupt 152 <0=> Secure state <1=> Non-Secure state +// Interrupt 153 <0=> Secure state <1=> Non-Secure state +// Interrupt 154 <0=> Secure state <1=> Non-Secure state +// Interrupt 155 <0=> Secure state <1=> Non-Secure state +// Interrupt 156 <0=> Secure state <1=> Non-Secure state +// Interrupt 157 <0=> Secure state <1=> Non-Secure state +// Interrupt 158 <0=> Secure state <1=> Non-Secure state +// Interrupt 159 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS4_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 5 (Interrupts 160..191) +*/ +#define NVIC_INIT_ITNS5 0 + +/* +// Interrupts 160..191 +// Interrupt 160 <0=> Secure state <1=> Non-Secure state +// Interrupt 161 <0=> Secure state <1=> Non-Secure state +// Interrupt 162 <0=> Secure state <1=> Non-Secure state +// Interrupt 163 <0=> Secure state <1=> Non-Secure state +// Interrupt 164 <0=> Secure state <1=> Non-Secure state +// Interrupt 165 <0=> Secure state <1=> Non-Secure state +// Interrupt 166 <0=> Secure state <1=> Non-Secure state +// Interrupt 167 <0=> Secure state <1=> Non-Secure state +// Interrupt 168 <0=> Secure state <1=> Non-Secure state +// Interrupt 169 <0=> Secure state <1=> Non-Secure state +// Interrupt 170 <0=> Secure state <1=> Non-Secure state +// Interrupt 171 <0=> Secure state <1=> Non-Secure state +// Interrupt 172 <0=> Secure state <1=> Non-Secure state +// Interrupt 173 <0=> Secure state <1=> Non-Secure state +// Interrupt 174 <0=> Secure state <1=> Non-Secure state +// Interrupt 175 <0=> Secure state <1=> Non-Secure state +// Interrupt 176 <0=> Secure state <1=> Non-Secure state +// Interrupt 177 <0=> Secure state <1=> Non-Secure state +// Interrupt 178 <0=> Secure state <1=> Non-Secure state +// Interrupt 179 <0=> Secure state <1=> Non-Secure state +// Interrupt 180 <0=> Secure state <1=> Non-Secure state +// Interrupt 181 <0=> Secure state <1=> Non-Secure state +// Interrupt 182 <0=> Secure state <1=> Non-Secure state +// Interrupt 183 <0=> Secure state <1=> Non-Secure state +// Interrupt 184 <0=> Secure state <1=> Non-Secure state +// Interrupt 185 <0=> Secure state <1=> Non-Secure state +// Interrupt 186 <0=> Secure state <1=> Non-Secure state +// Interrupt 187 <0=> Secure state <1=> Non-Secure state +// Interrupt 188 <0=> Secure state <1=> Non-Secure state +// Interrupt 189 <0=> Secure state <1=> Non-Secure state +// Interrupt 190 <0=> Secure state <1=> Non-Secure state +// Interrupt 191 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS5_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 6 (Interrupts 192..223) +*/ +#define NVIC_INIT_ITNS6 0 + +/* +// Interrupts 192..223 +// Interrupt 192 <0=> Secure state <1=> Non-Secure state +// Interrupt 193 <0=> Secure state <1=> Non-Secure state +// Interrupt 194 <0=> Secure state <1=> Non-Secure state +// Interrupt 195 <0=> Secure state <1=> Non-Secure state +// Interrupt 196 <0=> Secure state <1=> Non-Secure state +// Interrupt 197 <0=> Secure state <1=> Non-Secure state +// Interrupt 198 <0=> Secure state <1=> Non-Secure state +// Interrupt 199 <0=> Secure state <1=> Non-Secure state +// Interrupt 200 <0=> Secure state <1=> Non-Secure state +// Interrupt 201 <0=> Secure state <1=> Non-Secure state +// Interrupt 202 <0=> Secure state <1=> Non-Secure state +// Interrupt 203 <0=> Secure state <1=> Non-Secure state +// Interrupt 204 <0=> Secure state <1=> Non-Secure state +// Interrupt 205 <0=> Secure state <1=> Non-Secure state +// Interrupt 206 <0=> Secure state <1=> Non-Secure state +// Interrupt 207 <0=> Secure state <1=> Non-Secure state +// Interrupt 208 <0=> Secure state <1=> Non-Secure state +// Interrupt 209 <0=> Secure state <1=> Non-Secure state +// Interrupt 210 <0=> Secure state <1=> Non-Secure state +// Interrupt 211 <0=> Secure state <1=> Non-Secure state +// Interrupt 212 <0=> Secure state <1=> Non-Secure state +// Interrupt 213 <0=> Secure state <1=> Non-Secure state +// Interrupt 214 <0=> Secure state <1=> Non-Secure state +// Interrupt 215 <0=> Secure state <1=> Non-Secure state +// Interrupt 216 <0=> Secure state <1=> Non-Secure state +// Interrupt 217 <0=> Secure state <1=> Non-Secure state +// Interrupt 218 <0=> Secure state <1=> Non-Secure state +// Interrupt 219 <0=> Secure state <1=> Non-Secure state +// Interrupt 220 <0=> Secure state <1=> Non-Secure state +// Interrupt 221 <0=> Secure state <1=> Non-Secure state +// Interrupt 222 <0=> Secure state <1=> Non-Secure state +// Interrupt 223 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS6_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 7 (Interrupts 224..255) +*/ +#define NVIC_INIT_ITNS7 0 + +/* +// Interrupts 224..255 +// Interrupt 224 <0=> Secure state <1=> Non-Secure state +// Interrupt 225 <0=> Secure state <1=> Non-Secure state +// Interrupt 226 <0=> Secure state <1=> Non-Secure state +// Interrupt 227 <0=> Secure state <1=> Non-Secure state +// Interrupt 228 <0=> Secure state <1=> Non-Secure state +// Interrupt 229 <0=> Secure state <1=> Non-Secure state +// Interrupt 230 <0=> Secure state <1=> Non-Secure state +// Interrupt 231 <0=> Secure state <1=> Non-Secure state +// Interrupt 232 <0=> Secure state <1=> Non-Secure state +// Interrupt 233 <0=> Secure state <1=> Non-Secure state +// Interrupt 234 <0=> Secure state <1=> Non-Secure state +// Interrupt 235 <0=> Secure state <1=> Non-Secure state +// Interrupt 236 <0=> Secure state <1=> Non-Secure state +// Interrupt 237 <0=> Secure state <1=> Non-Secure state +// Interrupt 238 <0=> Secure state <1=> Non-Secure state +// Interrupt 239 <0=> Secure state <1=> Non-Secure state +// Interrupt 240 <0=> Secure state <1=> Non-Secure state +// Interrupt 241 <0=> Secure state <1=> Non-Secure state +// Interrupt 242 <0=> Secure state <1=> Non-Secure state +// Interrupt 243 <0=> Secure state <1=> Non-Secure state +// Interrupt 244 <0=> Secure state <1=> Non-Secure state +// Interrupt 245 <0=> Secure state <1=> Non-Secure state +// Interrupt 246 <0=> Secure state <1=> Non-Secure state +// Interrupt 247 <0=> Secure state <1=> Non-Secure state +// Interrupt 248 <0=> Secure state <1=> Non-Secure state +// Interrupt 249 <0=> Secure state <1=> Non-Secure state +// Interrupt 250 <0=> Secure state <1=> Non-Secure state +// Interrupt 251 <0=> Secure state <1=> Non-Secure state +// Interrupt 252 <0=> Secure state <1=> Non-Secure state +// Interrupt 253 <0=> Secure state <1=> Non-Secure state +// Interrupt 254 <0=> Secure state <1=> Non-Secure state +// Interrupt 255 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS7_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 8 (Interrupts 256..287) +*/ +#define NVIC_INIT_ITNS8 0 + +/* +// Interrupts 256..287 +// Interrupt 256 <0=> Secure state <1=> Non-Secure state +// Interrupt 257 <0=> Secure state <1=> Non-Secure state +// Interrupt 258 <0=> Secure state <1=> Non-Secure state +// Interrupt 259 <0=> Secure state <1=> Non-Secure state +// Interrupt 260 <0=> Secure state <1=> Non-Secure state +// Interrupt 261 <0=> Secure state <1=> Non-Secure state +// Interrupt 262 <0=> Secure state <1=> Non-Secure state +// Interrupt 263 <0=> Secure state <1=> Non-Secure state +// Interrupt 264 <0=> Secure state <1=> Non-Secure state +// Interrupt 265 <0=> Secure state <1=> Non-Secure state +// Interrupt 266 <0=> Secure state <1=> Non-Secure state +// Interrupt 267 <0=> Secure state <1=> Non-Secure state +// Interrupt 268 <0=> Secure state <1=> Non-Secure state +// Interrupt 269 <0=> Secure state <1=> Non-Secure state +// Interrupt 270 <0=> Secure state <1=> Non-Secure state +// Interrupt 271 <0=> Secure state <1=> Non-Secure state +// Interrupt 272 <0=> Secure state <1=> Non-Secure state +// Interrupt 273 <0=> Secure state <1=> Non-Secure state +// Interrupt 274 <0=> Secure state <1=> Non-Secure state +// Interrupt 275 <0=> Secure state <1=> Non-Secure state +// Interrupt 276 <0=> Secure state <1=> Non-Secure state +// Interrupt 277 <0=> Secure state <1=> Non-Secure state +// Interrupt 278 <0=> Secure state <1=> Non-Secure state +// Interrupt 279 <0=> Secure state <1=> Non-Secure state +// Interrupt 280 <0=> Secure state <1=> Non-Secure state +// Interrupt 281 <0=> Secure state <1=> Non-Secure state +// Interrupt 282 <0=> Secure state <1=> Non-Secure state +// Interrupt 283 <0=> Secure state <1=> Non-Secure state +// Interrupt 284 <0=> Secure state <1=> Non-Secure state +// Interrupt 285 <0=> Secure state <1=> Non-Secure state +// Interrupt 286 <0=> Secure state <1=> Non-Secure state +// Interrupt 287 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS8_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 9 (Interrupts 288..319) +*/ +#define NVIC_INIT_ITNS9 0 + +/* +// Interrupts 288..319 +// Interrupt 288 <0=> Secure state <1=> Non-Secure state +// Interrupt 289 <0=> Secure state <1=> Non-Secure state +// Interrupt 290 <0=> Secure state <1=> Non-Secure state +// Interrupt 291 <0=> Secure state <1=> Non-Secure state +// Interrupt 292 <0=> Secure state <1=> Non-Secure state +// Interrupt 293 <0=> Secure state <1=> Non-Secure state +// Interrupt 294 <0=> Secure state <1=> Non-Secure state +// Interrupt 295 <0=> Secure state <1=> Non-Secure state +// Interrupt 296 <0=> Secure state <1=> Non-Secure state +// Interrupt 297 <0=> Secure state <1=> Non-Secure state +// Interrupt 298 <0=> Secure state <1=> Non-Secure state +// Interrupt 299 <0=> Secure state <1=> Non-Secure state +// Interrupt 300 <0=> Secure state <1=> Non-Secure state +// Interrupt 301 <0=> Secure state <1=> Non-Secure state +// Interrupt 302 <0=> Secure state <1=> Non-Secure state +// Interrupt 303 <0=> Secure state <1=> Non-Secure state +// Interrupt 304 <0=> Secure state <1=> Non-Secure state +// Interrupt 305 <0=> Secure state <1=> Non-Secure state +// Interrupt 306 <0=> Secure state <1=> Non-Secure state +// Interrupt 307 <0=> Secure state <1=> Non-Secure state +// Interrupt 308 <0=> Secure state <1=> Non-Secure state +// Interrupt 309 <0=> Secure state <1=> Non-Secure state +// Interrupt 310 <0=> Secure state <1=> Non-Secure state +// Interrupt 311 <0=> Secure state <1=> Non-Secure state +// Interrupt 312 <0=> Secure state <1=> Non-Secure state +// Interrupt 313 <0=> Secure state <1=> Non-Secure state +// Interrupt 314 <0=> Secure state <1=> Non-Secure state +// Interrupt 315 <0=> Secure state <1=> Non-Secure state +// Interrupt 316 <0=> Secure state <1=> Non-Secure state +// Interrupt 317 <0=> Secure state <1=> Non-Secure state +// Interrupt 318 <0=> Secure state <1=> Non-Secure state +// Interrupt 319 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS9_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 10 (Interrupts 320..351) +*/ +#define NVIC_INIT_ITNS10 0 + +/* +// Interrupts 320..351 +// Interrupt 320 <0=> Secure state <1=> Non-Secure state +// Interrupt 321 <0=> Secure state <1=> Non-Secure state +// Interrupt 322 <0=> Secure state <1=> Non-Secure state +// Interrupt 323 <0=> Secure state <1=> Non-Secure state +// Interrupt 324 <0=> Secure state <1=> Non-Secure state +// Interrupt 325 <0=> Secure state <1=> Non-Secure state +// Interrupt 326 <0=> Secure state <1=> Non-Secure state +// Interrupt 327 <0=> Secure state <1=> Non-Secure state +// Interrupt 328 <0=> Secure state <1=> Non-Secure state +// Interrupt 329 <0=> Secure state <1=> Non-Secure state +// Interrupt 330 <0=> Secure state <1=> Non-Secure state +// Interrupt 331 <0=> Secure state <1=> Non-Secure state +// Interrupt 332 <0=> Secure state <1=> Non-Secure state +// Interrupt 333 <0=> Secure state <1=> Non-Secure state +// Interrupt 334 <0=> Secure state <1=> Non-Secure state +// Interrupt 335 <0=> Secure state <1=> Non-Secure state +// Interrupt 336 <0=> Secure state <1=> Non-Secure state +// Interrupt 337 <0=> Secure state <1=> Non-Secure state +// Interrupt 338 <0=> Secure state <1=> Non-Secure state +// Interrupt 339 <0=> Secure state <1=> Non-Secure state +// Interrupt 340 <0=> Secure state <1=> Non-Secure state +// Interrupt 341 <0=> Secure state <1=> Non-Secure state +// Interrupt 342 <0=> Secure state <1=> Non-Secure state +// Interrupt 343 <0=> Secure state <1=> Non-Secure state +// Interrupt 344 <0=> Secure state <1=> Non-Secure state +// Interrupt 345 <0=> Secure state <1=> Non-Secure state +// Interrupt 346 <0=> Secure state <1=> Non-Secure state +// Interrupt 347 <0=> Secure state <1=> Non-Secure state +// Interrupt 348 <0=> Secure state <1=> Non-Secure state +// Interrupt 349 <0=> Secure state <1=> Non-Secure state +// Interrupt 350 <0=> Secure state <1=> Non-Secure state +// Interrupt 351 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS10_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 11 (Interrupts 352..383) +*/ +#define NVIC_INIT_ITNS11 0 + +/* +// Interrupts 352..383 +// Interrupt 352 <0=> Secure state <1=> Non-Secure state +// Interrupt 353 <0=> Secure state <1=> Non-Secure state +// Interrupt 354 <0=> Secure state <1=> Non-Secure state +// Interrupt 355 <0=> Secure state <1=> Non-Secure state +// Interrupt 356 <0=> Secure state <1=> Non-Secure state +// Interrupt 357 <0=> Secure state <1=> Non-Secure state +// Interrupt 358 <0=> Secure state <1=> Non-Secure state +// Interrupt 359 <0=> Secure state <1=> Non-Secure state +// Interrupt 360 <0=> Secure state <1=> Non-Secure state +// Interrupt 361 <0=> Secure state <1=> Non-Secure state +// Interrupt 362 <0=> Secure state <1=> Non-Secure state +// Interrupt 363 <0=> Secure state <1=> Non-Secure state +// Interrupt 364 <0=> Secure state <1=> Non-Secure state +// Interrupt 365 <0=> Secure state <1=> Non-Secure state +// Interrupt 366 <0=> Secure state <1=> Non-Secure state +// Interrupt 367 <0=> Secure state <1=> Non-Secure state +// Interrupt 368 <0=> Secure state <1=> Non-Secure state +// Interrupt 369 <0=> Secure state <1=> Non-Secure state +// Interrupt 370 <0=> Secure state <1=> Non-Secure state +// Interrupt 371 <0=> Secure state <1=> Non-Secure state +// Interrupt 372 <0=> Secure state <1=> Non-Secure state +// Interrupt 373 <0=> Secure state <1=> Non-Secure state +// Interrupt 374 <0=> Secure state <1=> Non-Secure state +// Interrupt 375 <0=> Secure state <1=> Non-Secure state +// Interrupt 376 <0=> Secure state <1=> Non-Secure state +// Interrupt 377 <0=> Secure state <1=> Non-Secure state +// Interrupt 378 <0=> Secure state <1=> Non-Secure state +// Interrupt 379 <0=> Secure state <1=> Non-Secure state +// Interrupt 380 <0=> Secure state <1=> Non-Secure state +// Interrupt 381 <0=> Secure state <1=> Non-Secure state +// Interrupt 382 <0=> Secure state <1=> Non-Secure state +// Interrupt 383 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS11_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 12 (Interrupts 384..415) +*/ +#define NVIC_INIT_ITNS12 0 + +/* +// Interrupts 384..415 +// Interrupt 384 <0=> Secure state <1=> Non-Secure state +// Interrupt 385 <0=> Secure state <1=> Non-Secure state +// Interrupt 386 <0=> Secure state <1=> Non-Secure state +// Interrupt 387 <0=> Secure state <1=> Non-Secure state +// Interrupt 388 <0=> Secure state <1=> Non-Secure state +// Interrupt 389 <0=> Secure state <1=> Non-Secure state +// Interrupt 390 <0=> Secure state <1=> Non-Secure state +// Interrupt 391 <0=> Secure state <1=> Non-Secure state +// Interrupt 392 <0=> Secure state <1=> Non-Secure state +// Interrupt 393 <0=> Secure state <1=> Non-Secure state +// Interrupt 394 <0=> Secure state <1=> Non-Secure state +// Interrupt 395 <0=> Secure state <1=> Non-Secure state +// Interrupt 396 <0=> Secure state <1=> Non-Secure state +// Interrupt 397 <0=> Secure state <1=> Non-Secure state +// Interrupt 398 <0=> Secure state <1=> Non-Secure state +// Interrupt 399 <0=> Secure state <1=> Non-Secure state +// Interrupt 400 <0=> Secure state <1=> Non-Secure state +// Interrupt 401 <0=> Secure state <1=> Non-Secure state +// Interrupt 402 <0=> Secure state <1=> Non-Secure state +// Interrupt 403 <0=> Secure state <1=> Non-Secure state +// Interrupt 404 <0=> Secure state <1=> Non-Secure state +// Interrupt 405 <0=> Secure state <1=> Non-Secure state +// Interrupt 406 <0=> Secure state <1=> Non-Secure state +// Interrupt 407 <0=> Secure state <1=> Non-Secure state +// Interrupt 408 <0=> Secure state <1=> Non-Secure state +// Interrupt 409 <0=> Secure state <1=> Non-Secure state +// Interrupt 410 <0=> Secure state <1=> Non-Secure state +// Interrupt 411 <0=> Secure state <1=> Non-Secure state +// Interrupt 412 <0=> Secure state <1=> Non-Secure state +// Interrupt 413 <0=> Secure state <1=> Non-Secure state +// Interrupt 414 <0=> Secure state <1=> Non-Secure state +// Interrupt 415 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS12_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 13 (Interrupts 416..447) +*/ +#define NVIC_INIT_ITNS13 0 + +/* +// Interrupts 416..447 +// Interrupt 416 <0=> Secure state <1=> Non-Secure state +// Interrupt 417 <0=> Secure state <1=> Non-Secure state +// Interrupt 418 <0=> Secure state <1=> Non-Secure state +// Interrupt 419 <0=> Secure state <1=> Non-Secure state +// Interrupt 420 <0=> Secure state <1=> Non-Secure state +// Interrupt 421 <0=> Secure state <1=> Non-Secure state +// Interrupt 422 <0=> Secure state <1=> Non-Secure state +// Interrupt 423 <0=> Secure state <1=> Non-Secure state +// Interrupt 424 <0=> Secure state <1=> Non-Secure state +// Interrupt 425 <0=> Secure state <1=> Non-Secure state +// Interrupt 426 <0=> Secure state <1=> Non-Secure state +// Interrupt 427 <0=> Secure state <1=> Non-Secure state +// Interrupt 428 <0=> Secure state <1=> Non-Secure state +// Interrupt 429 <0=> Secure state <1=> Non-Secure state +// Interrupt 430 <0=> Secure state <1=> Non-Secure state +// Interrupt 431 <0=> Secure state <1=> Non-Secure state +// Interrupt 432 <0=> Secure state <1=> Non-Secure state +// Interrupt 433 <0=> Secure state <1=> Non-Secure state +// Interrupt 434 <0=> Secure state <1=> Non-Secure state +// Interrupt 435 <0=> Secure state <1=> Non-Secure state +// Interrupt 436 <0=> Secure state <1=> Non-Secure state +// Interrupt 437 <0=> Secure state <1=> Non-Secure state +// Interrupt 438 <0=> Secure state <1=> Non-Secure state +// Interrupt 439 <0=> Secure state <1=> Non-Secure state +// Interrupt 440 <0=> Secure state <1=> Non-Secure state +// Interrupt 441 <0=> Secure state <1=> Non-Secure state +// Interrupt 442 <0=> Secure state <1=> Non-Secure state +// Interrupt 443 <0=> Secure state <1=> Non-Secure state +// Interrupt 444 <0=> Secure state <1=> Non-Secure state +// Interrupt 445 <0=> Secure state <1=> Non-Secure state +// Interrupt 446 <0=> Secure state <1=> Non-Secure state +// Interrupt 447 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS13_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 14 (Interrupts 448..479) +*/ +#define NVIC_INIT_ITNS14 0 + +/* +// Interrupts 448..479 +// Interrupt 448 <0=> Secure state <1=> Non-Secure state +// Interrupt 449 <0=> Secure state <1=> Non-Secure state +// Interrupt 450 <0=> Secure state <1=> Non-Secure state +// Interrupt 451 <0=> Secure state <1=> Non-Secure state +// Interrupt 452 <0=> Secure state <1=> Non-Secure state +// Interrupt 453 <0=> Secure state <1=> Non-Secure state +// Interrupt 454 <0=> Secure state <1=> Non-Secure state +// Interrupt 455 <0=> Secure state <1=> Non-Secure state +// Interrupt 456 <0=> Secure state <1=> Non-Secure state +// Interrupt 457 <0=> Secure state <1=> Non-Secure state +// Interrupt 458 <0=> Secure state <1=> Non-Secure state +// Interrupt 459 <0=> Secure state <1=> Non-Secure state +// Interrupt 460 <0=> Secure state <1=> Non-Secure state +// Interrupt 461 <0=> Secure state <1=> Non-Secure state +// Interrupt 462 <0=> Secure state <1=> Non-Secure state +// Interrupt 463 <0=> Secure state <1=> Non-Secure state +// Interrupt 464 <0=> Secure state <1=> Non-Secure state +// Interrupt 465 <0=> Secure state <1=> Non-Secure state +// Interrupt 466 <0=> Secure state <1=> Non-Secure state +// Interrupt 467 <0=> Secure state <1=> Non-Secure state +// Interrupt 468 <0=> Secure state <1=> Non-Secure state +// Interrupt 469 <0=> Secure state <1=> Non-Secure state +// Interrupt 470 <0=> Secure state <1=> Non-Secure state +// Interrupt 471 <0=> Secure state <1=> Non-Secure state +// Interrupt 472 <0=> Secure state <1=> Non-Secure state +// Interrupt 473 <0=> Secure state <1=> Non-Secure state +// Interrupt 474 <0=> Secure state <1=> Non-Secure state +// Interrupt 475 <0=> Secure state <1=> Non-Secure state +// Interrupt 476 <0=> Secure state <1=> Non-Secure state +// Interrupt 477 <0=> Secure state <1=> Non-Secure state +// Interrupt 478 <0=> Secure state <1=> Non-Secure state +// Interrupt 479 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS14_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 15 (Interrupts 480..511) +*/ +#define NVIC_INIT_ITNS15 0 + +/* +// Interrupts 480..511 +// Interrupt 480 <0=> Secure state <1=> Non-Secure state +// Interrupt 481 <0=> Secure state <1=> Non-Secure state +// Interrupt 482 <0=> Secure state <1=> Non-Secure state +// Interrupt 483 <0=> Secure state <1=> Non-Secure state +// Interrupt 484 <0=> Secure state <1=> Non-Secure state +// Interrupt 485 <0=> Secure state <1=> Non-Secure state +// Interrupt 486 <0=> Secure state <1=> Non-Secure state +// Interrupt 487 <0=> Secure state <1=> Non-Secure state +// Interrupt 488 <0=> Secure state <1=> Non-Secure state +// Interrupt 489 <0=> Secure state <1=> Non-Secure state +// Interrupt 490 <0=> Secure state <1=> Non-Secure state +// Interrupt 491 <0=> Secure state <1=> Non-Secure state +// Interrupt 492 <0=> Secure state <1=> Non-Secure state +// Interrupt 493 <0=> Secure state <1=> Non-Secure state +// Interrupt 494 <0=> Secure state <1=> Non-Secure state +// Interrupt 495 <0=> Secure state <1=> Non-Secure state +// Interrupt 496 <0=> Secure state <1=> Non-Secure state +// Interrupt 497 <0=> Secure state <1=> Non-Secure state +// Interrupt 498 <0=> Secure state <1=> Non-Secure state +// Interrupt 499 <0=> Secure state <1=> Non-Secure state +// Interrupt 500 <0=> Secure state <1=> Non-Secure state +// Interrupt 501 <0=> Secure state <1=> Non-Secure state +// Interrupt 502 <0=> Secure state <1=> Non-Secure state +// Interrupt 503 <0=> Secure state <1=> Non-Secure state +// Interrupt 504 <0=> Secure state <1=> Non-Secure state +// Interrupt 505 <0=> Secure state <1=> Non-Secure state +// Interrupt 506 <0=> Secure state <1=> Non-Secure state +// Interrupt 507 <0=> Secure state <1=> Non-Secure state +// Interrupt 508 <0=> Secure state <1=> Non-Secure state +// Interrupt 509 <0=> Secure state <1=> Non-Secure state +// Interrupt 510 <0=> Secure state <1=> Non-Secure state +// Interrupt 511 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS15_VAL 0x00000000 + +/* +// +*/ + +/* +// +*/ + + + +/* + max 128 SAU regions. + SAU regions are defined in partition.h + */ + +#define SAU_INIT_REGION(n) \ + SAU->RNR = (n & SAU_RNR_REGION_Msk); \ + SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ + SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ + ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U + +/** + \brief Setup a SAU Region + \details Writes the region information contained in SAU_Region to the + registers SAU_RNR, SAU_RBAR, and SAU_RLAR + */ +__STATIC_INLINE void TZ_SAU_Setup (void) +{ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + + #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) + SAU_INIT_REGION(0); + #endif + + #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) + SAU_INIT_REGION(1); + #endif + + #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) + SAU_INIT_REGION(2); + #endif + + #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) + SAU_INIT_REGION(3); + #endif + + #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) + SAU_INIT_REGION(4); + #endif + + #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) + SAU_INIT_REGION(5); + #endif + + #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) + SAU_INIT_REGION(6); + #endif + + #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) + SAU_INIT_REGION(7); + #endif + + /* repeat this for all possible SAU regions */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + + + #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) + SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | + ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; + #endif + + #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) + SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | + ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); + + SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | + SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk )) | + ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | + ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | + ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | + ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); + #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ + + #if (((defined (__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0))) && \ + (defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U))) + + SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | + ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); + + FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | + ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | + ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | + ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); + #endif + + #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) + NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; + #endif + + #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) + NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; + #endif + + #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) + NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; + #endif + + #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) + NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; + #endif + + #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) + NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; + #endif + + #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U) + NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL; + #endif + + #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U) + NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL; + #endif + + #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U) + NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL; + #endif + + #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U) + NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL; + #endif + + #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U) + NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL; + #endif + + #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U) + NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL; + #endif + + #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U) + NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL; + #endif + + #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U) + NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL; + #endif + + #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U) + NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL; + #endif + + #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U) + NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL; + #endif + + #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U) + NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL; + #endif + + /* repeat this for all possible ITNS elements */ + +} + +#endif // IS_SECURE_EVIRONMENT + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_SOURCE_PARTITION_MAX32657_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/max32657.ld b/Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/max32657.ld index 6455e14f967..7a02a14948e 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/max32657.ld +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/max32657.ld @@ -40,7 +40,7 @@ SECTIONS { { _text = .; KEEP(*(.isr_vector)) - EXCLUDE_FILE (*riscv.o) *(.text*) /* Program code (exclude RISCV code) */ + *(.text*) /* Program code */ *(.rodata*) /* read-only data: "const" */ KEEP(*(.init)) @@ -65,19 +65,21 @@ SECTIONS { _etext = .; } > FLASH - .ARM.extab : + + /* + * Secure Gatway (SG) veneers. + * All SG veneers are placed in the special output section .gnu.sgstubs. + */ + .gnu.sgstubs : { - *(.ARM.extab* .gnu.linkonce.armextab.*) + _sg_veneers = .; + *(.gnu.sgstubs*) + _esg_veneers = .; } > FLASH - /* Binary import */ - .bin_storage : + .ARM.extab : { - FILL(0xFF) - _bin_start_ = .; - KEEP(*(.bin_storage_img)) - _bin_end_ = .; - . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) } > FLASH .rom_code : @@ -153,17 +155,34 @@ SECTIONS { _ebss = ALIGN(., 4); } > SRAM - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ + /** + * Stack Seal section is required for secure builds. Stack sealing protects + * secure stack from illegal access by non-secure code. + */ + .stackseal (COPY): + { + . = ALIGN(8); + __StackSeal = .; + . = . + 8; + . = ALIGN(8); + } > SRAM + + /** + * Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section. + */ __StackTop = ORIGIN(SRAM) + LENGTH(SRAM); __StackLimit = __StackTop - SIZEOF(.stack_dummy); - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ + /** + * .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later. + */ .stack_dummy (COPY): { - *(.stack*) + KEEP(*(.stack*)) + *(.stackseal*) } > SRAM .heap (COPY): @@ -177,5 +196,4 @@ SECTIONS { /* Check if data + heap + stack exceeds RAM limit */ ASSERT(__StackLimit >= _ebss, "region RAM overflowed with stack") - } diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/startup_max32657.S b/Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/startup_max32657.S index 6d472f73a13..2a4348f73c2 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/startup_max32657.S +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/startup_max32657.S @@ -24,26 +24,31 @@ .section .stack .align 3 #ifdef __STACK_SIZE - .equ Stack_Size, __STACK_SIZE + .equ Stack_Size, __STACK_SIZE #else // Default stack size (192KB) - .equ Stack_Size, 0x00030000 + .equ Stack_Size, 0x00030000 #endif .globl __StackTop .globl __StackLimit +#if IS_SECURE_ENVIRONMENT + // __StackSeal defined in linker script + .equ __STACK_SEAL, __StackSeal + .globl __StackSeal +#endif __StackLimit: .space Stack_Size - .size __StackLimit, . - __StackLimit + .size __StackLimit, . - __StackLimit __StackTop: - .size __StackTop, . - __StackTop + .size __StackTop, . - __StackTop .section .heap .align 3 #ifdef __HEAP_SIZE - .equ Heap_Size, __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE #else // Default heap size (64KB) - .equ Heap_Size, 0x00010000 + .equ Heap_Size, 0x00010000 #endif .globl __HeapBase .globl __HeapLimit @@ -60,26 +65,84 @@ __HeapLimit: .align 9 /* must be aligned to 512 byte boundary. VTOR requirement */ .globl __isr_vector __isr_vector: - .long __StackTop /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* NMI Handler */ - .long HardFault_Handler /* Hard Fault Handler */ - .long MemManage_Handler /* MPU Fault Handler */ - .long BusFault_Handler /* Bus Fault Handler */ - .long UsageFault_Handler /* Usage Fault Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long SVC_Handler /* SVCall Handler */ - .long DebugMon_Handler /* Debug Monitor Handler */ - .long 0 /* Reserved */ - .long PendSV_Handler /* PendSV Handler */ - .long SysTick_Handler /* SysTick Handler */ - - // TODO: Add device-specific interrupt table - /* Device-specific Interrupts */ - .long RSVXX_IRQHandler /* 0xXX 0xXXXX XX: Reserved */ + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* Device-specific Interrupts */ + /* CMSIS Interrupt Number */ + /* |||| || */ + /* |||| Offset || */ + /* vvvv vvvvvv vv */ + + .long ICE_IRQHandler /* 0x10 0x0040 16: ICE Unlock */ + .long WDT_IRQHandler /* 0x11 0x0044 17: Watchdog Timer */ + .long RTC_IRQHandler /* 0x12 0x0048 18: RTC */ + .long TRNG_IRQHandler /* 0x13 0x004C 19: True Random Number Generator */ + .long TMR0_IRQHandler /* 0x14 0x0050 20: Timer 0 */ + .long TMR1_IRQHandler /* 0x15 0x0054 21: Timer 1 */ + .long TMR2_IRQHandler /* 0x16 0x0058 22: Timer 2 */ + .long TMR3_IRQHandler /* 0x17 0x005C 23: Timer 3 */ + .long TMR4_IRQHandler /* 0x18 0x0060 24: Timer 4 */ + .long TMR5_IRQHandler /* 0x19 0x0064 25: Timer 5 */ + .long I3C_IRQHandler /* 0x1A 0x0068 26: I3C */ + .long UART_IRQHandler /* 0x1B 0x006C 27: UART */ + .long SPI_IRQHandler /* 0x1C 0x0070 28: SPI */ + .long FLC_IRQHandler /* 0x1D 0x0074 29: FLC */ + .long GPIO0_IRQHandler /* 0x1E 0x0078 30: GPIO0 */ + .long RSV15_IRQHandler /* 0x1F 0x007C 31: Reserved */ + .long DMA0_CH0_IRQHandler /* 0x20 0x0080 32: DMA0 Channel 0 */ + .long DMA0_CH1_IRQHandler /* 0x21 0x0084 33: DMA0 Channel 1 */ + .long DMA0_CH2_IRQHandler /* 0x22 0x0088 34: DMA0 Channel 2 */ + .long DMA0_CH3_IRQHandler /* 0x23 0x008C 35: DMA0 Channel 3 */ + .long DMA1_CH0_IRQHandler /* 0x24 0x0090 36: DMA1 Channel 0 */ + .long DMA1_CH1_IRQHandler /* 0x25 0x0094 37: DMA1 Channel 1 */ + .long DMA1_CH2_IRQHandler /* 0x26 0x0098 38: DMA1 Channel 2 */ + .long DMA1_CH3_IRQHandler /* 0x27 0x009C 39: DMA1 Channel 3 */ + .long WUT0_IRQHandler /* 0x28 0x00A0 40: Wakeup Timer 0 */ + .long WUT1_IRQHandler /* 0x29 0x00A4 41: Wakeup Timer 1 */ + .long GPIOWAKE_IRQHandler /* 0x2A 0x00A8 42: GPIO Wakeup */ + .long CRC_IRQHandler /* 0x2B 0x00AC 43: CRC */ + .long AES_IRQHandler /* 0x2C 0x00B0 44: AES */ + .long ERFO_IRQHandler /* 0x2D 0x00B4 45: ERFO Ready */ + .long BOOST_IRQHandler /* 0x2E 0x00B8 46: Boost Controller */ + .long ECC_IRQHandler /* 0x2F 0x00BC 47: ECC */ +/* TODO(Bluetooth): Confirm BTLE IRQ Handler Names */ + .long BTLE_XXXX0_IRQHandler /* 0x30 0x00C0 48: BTLE XXXX0 */ + .long BTLE_XXXX1_IRQHandler /* 0x31 0x00C4 49: BTLE XXXX1 */ + .long BTLE_XXXX2_IRQHandler /* 0x32 0x00C8 50: BTLE XXXX2 */ + .long BTLE_XXXX3_IRQHandler /* 0x33 0x00CC 51: BTLE XXXX3 */ + .long BTLE_XXXX4_IRQHandler /* 0x34 0x00D0 52: BTLE XXXX4 */ + .long BTLE_XXXX5_IRQHandler /* 0x35 0x00D4 53: BTLE XXXX5 */ + .long BTLE_XXXX6_IRQHandler /* 0x36 0x00D8 54: BTLE XXXX6 */ + .long BTLE_XXXX7_IRQHandler /* 0x37 0x00DC 55: BTLE XXXX7 */ + .long BTLE_XXXX8_IRQHandler /* 0x38 0x00E0 56: BTLE XXXX8 */ + .long BTLE_XXXX9_IRQHandler /* 0x39 0x00E4 57: BTLE XXXX9 */ + .long BTLE_XXXXA_IRQHandler /* 0x3A 0x00E8 58: BTLE XXXXA */ + .long BTLE_XXXXB_IRQHandler /* 0x3B 0x00EC 59: BTLE XXXXB */ + .long BTLE_XXXXC_IRQHandler /* 0x3C 0x00F0 60: BTLE XXXXC */ + .long BTLE_XXXXD_IRQHandler /* 0x3D 0x00F4 61: BTLE XXXXD */ + .long BTLE_XXXXE_IRQHandler /* 0x3E 0x00F8 62: BTLE XXXXE */ + .long RSV47_IRQHandler /* 0x3F 0x00FC 63: Reserved */ + .long MPC_IRQHandler /* 0x40 0x0100 64: MPC Combined (Secure) */ + .long PPC_IRQHandler /* 0x44 0x0104 65: PPC Combined (Secure) */ + .long RSV50_IRQHandler /* 0x48 0x0108 66: Reserved */ + .long RSV51_IRQHandler /* 0x49 0x010C 67: Reserved */ + .long RSV52_IRQHandler /* 0x4A 0x0110 68: Reserved */ + .long RSV53_IRQHandler /* 0x4B 0x0114 69: Reserved */ .text .thumb @@ -91,6 +154,19 @@ Reset_Handler: ldr r0, =__StackTop mov sp, r0 +#if IS_SECURE_ENVIRONMENT + /* Set limit on Main and Process SP */ + ldr r0, =__STACK_LIMIT + msr msplim, r0 + msr psplim, r0 + + /* Set up Stack Sealing - using predefined stack seal value */ + ldr r0, =__STACK_SEAL + ldr r1, =0xFEF5EDA5U + /* Store seal value twice as a double word for redundancy */ + strd r1, r1, [r0, #0] +#endif + /* PreInit runs before any RAM initialization. Example usage: DDR setup, etc. */ ldr r0, =PreInit blx r0 @@ -177,7 +253,6 @@ Reset_Handler: .size \handler_name, . - \handler_name .endm - // TODO: Update to match arch-specific handlers above def_irq_handler NMI_Handler def_irq_handler HardFault_Handler def_irq_handler MemManage_Handler @@ -189,7 +264,65 @@ Reset_Handler: def_irq_handler SysTick_Handler def_irq_handler Default_Handler - // TODO: Add default device-specific handlers to match above - /* Device-specific Interrupts */ - def_irq_handler RSVXX_IRQHandler /* 0xXX 0xXXXX XX: Reserved */ + /* Device-specific Interrupts */ + /* CMSIS Interrupt Number */ + /* |||| || */ + /* |||| Offset || */ + /* vvvv vvvvvv vv */ + + def_irq_handler ICE_IRQHandler /* 0x10 0x0040 16: ICE Unlock */ + def_irq_handler WDT_IRQHandler /* 0x11 0x0044 17: Watchdog Timer */ + def_irq_handler RTC_IRQHandler /* 0x12 0x0048 18: RTC */ + def_irq_handler TRNG_IRQHandler /* 0x13 0x004C 19: True Random Number Generator */ + def_irq_handler TMR0_IRQHandler /* 0x14 0x0050 20: Timer 0 */ + def_irq_handler TMR1_IRQHandler /* 0x15 0x0054 21: Timer 1 */ + def_irq_handler TMR2_IRQHandler /* 0x16 0x0058 22: Timer 2 */ + def_irq_handler TMR3_IRQHandler /* 0x17 0x005C 23: Timer 3 */ + def_irq_handler TMR4_IRQHandler /* 0x18 0x0060 24: Timer 4 */ + def_irq_handler TMR5_IRQHandler /* 0x19 0x0064 25: Timer 5 */ + def_irq_handler I3C_IRQHandler /* 0x1A 0x0068 26: I3C */ + def_irq_handler UART_IRQHandler /* 0x1B 0x006C 27: UART */ + def_irq_handler SPI_IRQHandler /* 0x1C 0x0070 28: SPI */ + def_irq_handler FLC_IRQHandler /* 0x1D 0x0074 29: FLC */ + def_irq_handler GPIO0_IRQHandler /* 0x1E 0x0078 30: GPIO0 */ + def_irq_handler RSV15_IRQHandler /* 0x1F 0x007C 31: Reserved */ + def_irq_handler DMA0_CH0_IRQHandler /* 0x20 0x0080 32: DMA0 Channel 0 */ + def_irq_handler DMA0_CH1_IRQHandler /* 0x21 0x0084 33: DMA0 Channel 1 */ + def_irq_handler DMA0_CH2_IRQHandler /* 0x22 0x0088 34: DMA0 Channel 2 */ + def_irq_handler DMA0_CH3_IRQHandler /* 0x23 0x008C 35: DMA0 Channel 3 */ + def_irq_handler DMA1_CH0_IRQHandler /* 0x24 0x0090 36: DMA1 Channel 0 */ + def_irq_handler DMA1_CH1_IRQHandler /* 0x25 0x0094 37: DMA1 Channel 1 */ + def_irq_handler DMA1_CH2_IRQHandler /* 0x26 0x0098 38: DMA1 Channel 2 */ + def_irq_handler DMA1_CH3_IRQHandler /* 0x27 0x009C 39: DMA1 Channel 3 */ + def_irq_handler WUT0_IRQHandler /* 0x28 0x00A0 40: Wakeup Timer 0 */ + def_irq_handler WUT1_IRQHandler /* 0x29 0x00A4 41: Wakeup Timer 1 */ + def_irq_handler GPIOWAKE_IRQHandler /* 0x2A 0x00A8 42: GPIO Wakeup */ + def_irq_handler CRC_IRQHandler /* 0x2B 0x00AC 43: CRC */ + def_irq_handler AES_IRQHandler /* 0x2C 0x00B0 44: AES */ + def_irq_handler ERFO_IRQHandler /* 0x2D 0x00B4 45: ERFO Ready */ + def_irq_handler BOOST_IRQHandler /* 0x2E 0x00B8 46: Boost Controller */ + def_irq_handler ECC_IRQHandler /* 0x2F 0x00BC 47: ECC */ +/* TODO(Bluetooth): Confirm BTLE IRQ Handler Names */ + def_irq_handler BTLE_XXXX0_IRQHandler /* 0x30 0x00C0 48: BTLE XXXX0 */ + def_irq_handler BTLE_XXXX1_IRQHandler /* 0x31 0x00C4 49: BTLE XXXX1 */ + def_irq_handler BTLE_XXXX2_IRQHandler /* 0x32 0x00C8 50: BTLE XXXX2 */ + def_irq_handler BTLE_XXXX3_IRQHandler /* 0x33 0x00CC 51: BTLE XXXX3 */ + def_irq_handler BTLE_XXXX4_IRQHandler /* 0x34 0x00D0 52: BTLE XXXX4 */ + def_irq_handler BTLE_XXXX5_IRQHandler /* 0x35 0x00D4 53: BTLE XXXX5 */ + def_irq_handler BTLE_XXXX6_IRQHandler /* 0x36 0x00D8 54: BTLE XXXX6 */ + def_irq_handler BTLE_XXXX7_IRQHandler /* 0x37 0x00DC 55: BTLE XXXX7 */ + def_irq_handler BTLE_XXXX8_IRQHandler /* 0x38 0x00E0 56: BTLE XXXX8 */ + def_irq_handler BTLE_XXXX9_IRQHandler /* 0x39 0x00E4 57: BTLE XXXX9 */ + def_irq_handler BTLE_XXXXA_IRQHandler /* 0x3A 0x00E8 58: BTLE XXXXA */ + def_irq_handler BTLE_XXXXB_IRQHandler /* 0x3B 0x00EC 59: BTLE XXXXB */ + def_irq_handler BTLE_XXXXC_IRQHandler /* 0x3C 0x00F0 60: BTLE XXXXC */ + def_irq_handler BTLE_XXXXD_IRQHandler /* 0x3D 0x00F4 61: BTLE XXXXD */ + def_irq_handler BTLE_XXXXE_IRQHandler /* 0x3E 0x00F8 62: BTLE XXXXE */ + def_irq_handler RSV47_IRQHandler /* 0x3F 0x00FC 63: Reserved */ + def_irq_handler MPC_IRQHandler /* 0x40 0x0100 64: MPC Combined (Secure) */ + def_irq_handler PPC_IRQHandler /* 0x44 0x0104 65: PPC Combined (Secure) */ + def_irq_handler RSV50_IRQHandler /* 0x48 0x0108 66: Reserved */ + def_irq_handler RSV51_IRQHandler /* 0x49 0x010C 67: Reserved */ + def_irq_handler RSV52_IRQHandler /* 0x4A 0x0110 68: Reserved */ + def_irq_handler RSV53_IRQHandler /* 0x4B 0x0114 69: Reserved */ .end diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Source/system_max32657.c b/Libraries/CMSIS/Device/Maxim/MAX32657/Source/system_max32657.c index 51078ce7a50..417f887b2ab 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Source/system_max32657.c +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Source/system_max32657.c @@ -16,20 +16,24 @@ * ******************************************************************************/ -// TODO(ME30): System implementation - -#include "system_max32657.h" -#include "max32657.h" +#include +#include +#include +#include #include "mxc_sys.h" -#include "icc.h" +#include "max32657.h" +#include "system_max32657.h" +#include "partition_max32657.h" +#include "gcr_regs.h" extern void (*const __isr_vector[])(void); + uint32_t SystemCoreClock = IPO_FREQ; // Part defaults to IPO on startup /* -The libc implementation from GCC 11+ depends on _getpid and _kill in some places. -There is no concept of processes/PIDs in the baremetal PeriphDrivers, therefore -we implement stub functions that return an error code to resolve linker warnings. + The libc implementation from GCC 11+ depends on _getpid and _kill in some places. + There is no concept of processes/PIDs in the baremetal PeriphDrivers, therefore + we implement stub functions that return an error code to resolve linker warnings. */ int _getpid(void) { @@ -47,7 +51,7 @@ __weak void SystemCoreClockUpdate(void) // Get the clock source and frequency clk_src = (MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_SYSCLK_SEL); - switch (clk_src) { + switch (clk_src) { case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IPO: base_freq = IPO_FREQ; break; @@ -56,7 +60,7 @@ __weak void SystemCoreClockUpdate(void) break; case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_INRO: base_freq = INRO_FREQ; - break; + break; case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IBRO: base_freq = IBRO_FREQ; break; @@ -90,8 +94,9 @@ __weak void SystemCoreClockUpdate(void) */ __weak int PreInit(void) { - // TODO(JC): No SIMO on this device, confirm nothing needs to be done here. - + /* Do nothing */ + // TODO(JC): No SIMO on this device, confirm nothing needs to be done here. + // (SW): Correct, different power HW. return 0; } @@ -121,26 +126,40 @@ __weak int Board_Init(void) */ __weak void SystemInit(void) { - /* Configure the interrupt controller to use the application vector table in */ - /* the application space */ -#if defined(__CC_ARM) || defined(__GNUC__) - /* IAR sets the VTOR pointer incorrectly and causes stack corruption */ +#if defined(__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) SCB->VTOR = (uint32_t)__isr_vector; -#endif /* __CC_ARM || __GNUC__ */ +#endif /* __VTOR_PRESENT check */ - /* Make sure interrupts are enabled. */ - __enable_irq(); +#if (__FPU_PRESENT == 1U) + /* Enable FPU - coprocessor slots 10 & 11 full access */ + SCB->CPACR |= SCB_CPACR_CP10_Msk | SCB_CPACR_CP11_Msk; +#endif /* __FPU_PRESENT check */ - /* Enable instruction cache */ - MXC_ICC_Enable(MXC_ICC); + /* + Enable Unaligned Access Trapping to throw an exception when there is an + unaligned memory access while unaligned access support is disabled. + + Note: ARMv8-M without the Main Extension disables unaligned access by default. + */ +#if defined(UNALIGNED_SUPPORT_DISABLE) || defined(__ARM_FEATURE_UNALIGNED) + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + /* Security Extension Features */ +#if IS_SECURE_ENVIRONMENT + /* Settings for TrustZone SAU setup are defined in partitions_max32657.h */ + TZ_SAU_Setup(); +#endif /* TrustZone */ - /* Enable FPU on Cortex-M4, which occupies coprocessor slots 10 & 11 */ - /* Grant full access, per "Table B3-24 CPACR bit assignments". */ - /* DDI0403D "ARMv7-M Architecture Reference Manual" */ - SCB->CPACR |= SCB_CPACR_CP10_Msk | SCB_CPACR_CP11_Msk; __DSB(); __ISB(); + /* Enable interrupts */ + __enable_irq(); + + // TODO(ICC): Enable the internal cache controller after testing. + // MXC_ICC_Enable(); + /* Change system clock source to the main high-speed clock */ MXC_SYS_Clock_Select(MXC_SYS_CLOCK_IPO); MXC_SYS_SetClockDiv(MXC_SYS_CLOCK_DIV_1); @@ -148,4 +167,4 @@ __weak void SystemInit(void) PinInit(); Board_Init(); -} \ No newline at end of file +} diff --git a/Libraries/PeriphDrivers/Include/MAX32657/aes.h b/Libraries/PeriphDrivers/Include/MAX32657/aes.h index 7f51f371c1b..806df3abbbc 100644 --- a/Libraries/PeriphDrivers/Include/MAX32657/aes.h +++ b/Libraries/PeriphDrivers/Include/MAX32657/aes.h @@ -27,6 +27,7 @@ /***** Includes *****/ #include "aes_regs.h" #include "aeskeys_regs.h" +#include "dma_regs.h" #ifdef __cplusplus extern "C" { @@ -89,9 +90,10 @@ typedef struct _mxc_aes_cipher_req_t { /** * @brief Enable portions of the AES * + * @param dma DMA instance used for AES * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_AES_Init(void); +int MXC_AES_Init(mxc_dma_regs_t *dma); /** * @brief Enable AES Interrupts @@ -213,18 +215,20 @@ int MXC_AES_Decrypt(mxc_aes_req_t *req); * * @param src_addr source address * @param len number of words of data + * @param dma DMA instance to configue for AES * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_AES_TXDMAConfig(void *src_addr, int len); +int MXC_AES_TXDMAConfig(void *src_addr, int len, mxc_dma_regs_t *dma); /** * @brief Perform AES RX using DMA. Configures DMA request and receives data from AES FIFO. * * @param dest_addr destination address * @param len number of words of data + * @param dma DMA instance to configure for AES * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_AES_RXDMAConfig(void *dest_addr, int len); +int MXC_AES_RXDMAConfig(void *dest_addr, int len, mxc_dma_regs_t *dma); /** * @brief Perform encryption or decryption using DMA diff --git a/Libraries/PeriphDrivers/Include/MAX32657/crc.h b/Libraries/PeriphDrivers/Include/MAX32657/crc.h index 35218bf1f23..f80ed216122 100644 --- a/Libraries/PeriphDrivers/Include/MAX32657/crc.h +++ b/Libraries/PeriphDrivers/Include/MAX32657/crc.h @@ -26,6 +26,7 @@ /***** Includes *****/ #include "crc_regs.h" +#include "dma_regs.h" #ifdef __cplusplus extern "C" { @@ -63,10 +64,10 @@ typedef enum { CRC_LSB_FIRST, CRC_MSB_FIRST } mxc_crc_bitorder_t; /** * @brief Enable portions of the CRC * - * + * @param dma DMA Instance used for CRC calculation * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_CRC_Init(void); +int MXC_CRC_Init(mxc_dma_regs_t *dma); /** * @brief Disable and reset portions of the CRC diff --git a/Libraries/PeriphDrivers/Include/MAX32657/dma.h b/Libraries/PeriphDrivers/Include/MAX32657/dma.h index ef471bb2ce4..44fd184aeb7 100644 --- a/Libraries/PeriphDrivers/Include/MAX32657/dma.h +++ b/Libraries/PeriphDrivers/Include/MAX32657/dma.h @@ -193,25 +193,30 @@ typedef mxc_dma_srcdst_t (*mxc_dma_trans_chain_t)(mxc_dma_srcdst_t dest); * if you wish to manage clock and gpio related things in upper level instead of here. * Define MSDK_NO_GPIO_CLK_INIT flag in project.mk file. * By this flag this function will remove clock and gpio related codes from file. + * @param dma Pointer to selected DMA instance's registers. + * * @return #E_NO_ERROR if successful */ -int MXC_DMA_Init(void); +int MXC_DMA_Init(mxc_dma_regs_t *dma); /** * @brief De-Initialize DMA resources. + * + * @param dma Pointer to selected DMA instance's registers. */ -void MXC_DMA_DeInit(void); +void MXC_DMA_DeInit(mxc_dma_regs_t *dma); /** * @brief Request DMA channel * @details Returns a handle to the first free DMA channel, which can be used via API calls * or direct access to channel registers using the MXC_DMA_GetCHRegs(int ch) function. + * @param dma Pointer to selected DMA instance's registers. * @return Non-negative channel handle (inclusive of zero). * @return #E_NONE_AVAIL All channels in use. * @return #E_BAD_STATE DMA is not initialized, call MXC_DMA_Init() first. * @return #E_BUSY DMA is currently busy (locked), try again later. */ -int MXC_DMA_AcquireChannel(void); +int MXC_DMA_AcquireChannel(mxc_dma_regs_t *dma); /** * @brief Release DMA channel @@ -360,19 +365,21 @@ int MXC_DMA_ChannelClearFlags(int ch, int flags); * @brief Enable channel interrupt * @note Each channel has two interrupts (complete, and count to zero) which must also be enabled with MXC_DMA_SetChannelInterruptEn() + * @param dma DMA instance used for the DMA channel registers. * @param ch DMA channel to enable interrupts for. * @return #E_BAD_PARAM if an unused or invalid channel handle, * #E_NO_ERROR otherwise, \ref MXC_Error_Codes */ -int MXC_DMA_EnableInt(int ch); +int MXC_DMA_EnableInt(mxc_dma_regs_t *dma, int ch); /** * @brief Disable channel interrupt + * @param dma DMA instance used for the DMA channel registers. * @param ch DMA channel to disable interrupts for. * @return #E_BAD_PARAM if an unused or invalid channel handle, * #E_NO_ERROR otherwise, \ref MXC_Error_Codes */ -int MXC_DMA_DisableInt(int ch); +int MXC_DMA_DisableInt(mxc_dma_regs_t *dma, int ch); /** * @brief Start transfer @@ -402,10 +409,11 @@ mxc_dma_ch_regs_t *MXC_DMA_GetCHRegs(int ch); /** * @brief Interrupt handler function + * @param dma Pointer to DMA registers. * @details Call this function as the ISR for each DMA channel under driver control. * Interrupt flags for channel ch will be automatically cleared before return. */ -void MXC_DMA_Handler(void); +void MXC_DMA_Handler(mxc_dma_regs_t *dma); /*************************/ /* High Level Functions */ @@ -416,6 +424,7 @@ void MXC_DMA_Handler(void); * @note The user must have the DMA interrupt enabled and call * MXC_DMA_Handler() from the ISR. * + * @param dma Pointer to DMA registers. * @param dest pointer to destination memory * @param src pointer to source memory * @param len number of bytes to copy @@ -423,20 +432,22 @@ void MXC_DMA_Handler(void); * * @return see \ref MXC_Error_Codes */ -int MXC_DMA_MemCpy(void *dest, void *src, int len, mxc_dma_complete_cb_t callback); +int MXC_DMA_MemCpy(mxc_dma_regs_t *dma, void *dest, void *src, int len, + mxc_dma_complete_cb_t callback); /** * @brief Performs a memcpy, using DMA, optionally asynchronous * @note The user must have the DMA interrupt enabled and call * MXC_DMA_Handler() from the ISR. * + * @param dma Pointer to DMA registers. * @param config The channel config struct * @param firstSrcDst The source, destination, and count for the first transfer * @param callback function is called when transfer is complete * * @return see \ref MXC_Error_Codes */ -int MXC_DMA_DoTransfer(mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, +int MXC_DMA_DoTransfer(mxc_dma_regs_t *dma, mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, mxc_dma_trans_chain_t callback); /** * For other functional uses of DMA (UART, SPI, etc) see the appropriate peripheral driver diff --git a/Libraries/PeriphDrivers/Include/MAX32657/spi.h b/Libraries/PeriphDrivers/Include/MAX32657/spi.h index de855f2cb0e..7ddde948670 100644 --- a/Libraries/PeriphDrivers/Include/MAX32657/spi.h +++ b/Libraries/PeriphDrivers/Include/MAX32657/spi.h @@ -32,6 +32,7 @@ #include "gpio.h" #include "mxc_pins.h" #include "mxc_lock.h" +#include "dma_regs.h" #ifdef __cplusplus extern "C" { @@ -595,11 +596,12 @@ int MXC_SPI_MasterTransactionAsync(mxc_spi_req_t *req); * possible. The channel will be reset and returned to the system at the end of * the transaction. * - * @param req Pointer to details of the transaction + * @param req Pointer to details of the transaction + * @param dma DMA instance to use for SPI DMA * * @return See \ref MXC_Error_Codes for the list of error return codes. */ -int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t *req); +int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t *req, mxc_dma_regs_t *dma); /** * @brief Performs a blocking SPI transaction. @@ -642,10 +644,11 @@ int MXC_SPI_SlaveTransactionAsync(mxc_spi_req_t *req); * the transaction. * * @param req Pointer to details of the transaction + * @param dma DMA instance to use for SPI DMA * * @return See \ref MXC_Error_Codes for the list of error return codes. */ -int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t *req); +int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t *req, mxc_dma_regs_t *dma); /** * @brief Sets the TX data to transmit as a 'dummy' byte diff --git a/Libraries/PeriphDrivers/Include/MAX32657/uart.h b/Libraries/PeriphDrivers/Include/MAX32657/uart.h index 40e90877866..523b80f8e0b 100644 --- a/Libraries/PeriphDrivers/Include/MAX32657/uart.h +++ b/Libraries/PeriphDrivers/Include/MAX32657/uart.h @@ -31,6 +31,7 @@ #include #include "uart_regs.h" #include "mxc_sys.h" +#include "dma_regs.h" #ifdef __cplusplus extern "C" { @@ -377,14 +378,15 @@ unsigned int MXC_UART_ReadRXFIFO(mxc_uart_regs_t *uart, unsigned char *bytes, un /** * @brief Unloads bytes from the receive FIFO user DMA for longer reads. * - * @param uart Pointer to UART registers (selects the UART block used.) + * @param uart Pointer to UART registers (selects the UART block used). + * @param dma Pointer to DMA registers (selects the DMA block used for UART DMA). * @param bytes The buffer to read the data into. * @param len The number of bytes to read. * @param callback The function to call when the read is complete * * @return See \ref MXC_Error_Codes for a list of return values */ -int MXC_UART_ReadRXFIFODMA(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned int len, +int MXC_UART_ReadRXFIFODMA(mxc_uart_regs_t *uart, mxc_dma_regs_t *dma, unsigned char *bytes, unsigned int len, mxc_uart_dma_complete_cb_t callback); /** @@ -410,14 +412,15 @@ unsigned int MXC_UART_WriteTXFIFO(mxc_uart_regs_t *uart, unsigned char *bytes, u /** * @brief Loads bytes into the transmit FIFO using DMA for longer writes * - * @param uart Pointer to UART registers (selects the UART block used.) + * @param uart Pointer to UART registers (selects the UART block used). + * @param dma Pointer to DMA registers (selects the DMA block used for UART DMA). * @param bytes The buffer containing the bytes to write * @param len The number of bytes to write. * @param callback The function to call when the write is complete * * @return See \ref MXC_Error_Codes for a list of return values */ -int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned int len, +int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t *uart, mxc_dma_regs_t *dma, unsigned char *bytes, unsigned int len, mxc_uart_dma_complete_cb_t callback); /** @@ -602,10 +605,11 @@ int MXC_UART_TransactionAsync(mxc_uart_req_t *req); * returned to the system at the end of the transaction. * * @param req Pointer to details of the transaction + * @param dma Pointer to DMA registers used for UART DMA * * @return See \ref MXC_Error_Codes for the list of error return codes. */ -int MXC_UART_TransactionDMA(mxc_uart_req_t *req); +int MXC_UART_TransactionDMA(mxc_uart_req_t *req, mxc_dma_regs_t *dma); /** * @brief The processing function for DMA transactions. diff --git a/Libraries/PeriphDrivers/Source/AES/aes_ai87.c b/Libraries/PeriphDrivers/Source/AES/aes_ai87.c index 594d86119ce..ba60f951604 100644 --- a/Libraries/PeriphDrivers/Source/AES/aes_ai87.c +++ b/Libraries/PeriphDrivers/Source/AES/aes_ai87.c @@ -138,12 +138,12 @@ int MXC_AES_Decrypt(mxc_aes_req_t *req) int MXC_AES_TXDMAConfig(void *src_addr, int len) { - return MXC_AES_RevB_TXDMAConfig(src_addr, len); + return MXC_AES_RevB_TXDMAConfig(src_addr, len, MXC_DMA); } int MXC_AES_RXDMAConfig(void *dest_addr, int len) { - return MXC_AES_RevB_RXDMAConfig(dest_addr, len); + return MXC_AES_RevB_RXDMAConfig(dest_addr, len, MXC_DMA); } int MXC_AES_GenericAsync(mxc_aes_req_t *req, uint8_t enc) diff --git a/Libraries/PeriphDrivers/Source/AES/aes_me12.c b/Libraries/PeriphDrivers/Source/AES/aes_me12.c index 87e6b35cb25..60c6eaeeb21 100644 --- a/Libraries/PeriphDrivers/Source/AES/aes_me12.c +++ b/Libraries/PeriphDrivers/Source/AES/aes_me12.c @@ -131,12 +131,12 @@ int MXC_AES_Decrypt(mxc_aes_req_t *req) int MXC_AES_TXDMAConfig(void *src_addr, int len) { - return MXC_AES_RevB_TXDMAConfig(src_addr, len); + return MXC_AES_RevB_TXDMAConfig(src_addr, len, MXC_DMA); } int MXC_AES_RXDMAConfig(void *dest_addr, int len) { - return MXC_AES_RevB_RXDMAConfig(dest_addr, len); + return MXC_AES_RevB_RXDMAConfig(dest_addr, len, MXC_DMA); } int MXC_AES_GenericAsync(mxc_aes_req_t *req, uint8_t enc) diff --git a/Libraries/PeriphDrivers/Source/AES/aes_me15.c b/Libraries/PeriphDrivers/Source/AES/aes_me15.c index d35812e0d27..60ecf1ead79 100644 --- a/Libraries/PeriphDrivers/Source/AES/aes_me15.c +++ b/Libraries/PeriphDrivers/Source/AES/aes_me15.c @@ -155,12 +155,12 @@ int MXC_AES_Decrypt(mxc_aes_req_t *req) int MXC_AES_TXDMAConfig(void *src_addr, int len) { - return MXC_AES_RevB_TXDMAConfig(src_addr, len); + return MXC_AES_RevB_TXDMAConfig(src_addr, len, MXC_DMA); } int MXC_AES_RXDMAConfig(void *dest_addr, int len) { - return MXC_AES_RevB_RXDMAConfig(dest_addr, len); + return MXC_AES_RevB_RXDMAConfig(dest_addr, len, MXC_DMA); } int MXC_AES_GenericAsync(mxc_aes_req_t *req, uint8_t enc) diff --git a/Libraries/PeriphDrivers/Source/AES/aes_me17.c b/Libraries/PeriphDrivers/Source/AES/aes_me17.c index 27ac05bc04a..1cbca9635a9 100644 --- a/Libraries/PeriphDrivers/Source/AES/aes_me17.c +++ b/Libraries/PeriphDrivers/Source/AES/aes_me17.c @@ -132,12 +132,12 @@ int MXC_AES_Decrypt(mxc_aes_req_t *req) int MXC_AES_TXDMAConfig(void *src_addr, int len) { - return MXC_AES_RevB_TXDMAConfig(src_addr, len); + return MXC_AES_RevB_TXDMAConfig(src_addr, len, MXC_DMA); } int MXC_AES_RXDMAConfig(void *dest_addr, int len) { - return MXC_AES_RevB_RXDMAConfig(dest_addr, len); + return MXC_AES_RevB_RXDMAConfig(dest_addr, len, MXC_DMA); } int MXC_AES_GenericAsync(mxc_aes_req_t *req, uint8_t enc) diff --git a/Libraries/PeriphDrivers/Source/AES/aes_me21.c b/Libraries/PeriphDrivers/Source/AES/aes_me21.c index 1eaf61ca5e1..cfb340482a9 100644 --- a/Libraries/PeriphDrivers/Source/AES/aes_me21.c +++ b/Libraries/PeriphDrivers/Source/AES/aes_me21.c @@ -126,12 +126,12 @@ int MXC_AES_Decrypt(mxc_aes_req_t *req) int MXC_AES_TXDMAConfig(void *src_addr, int len) { - return MXC_AES_RevB_TXDMAConfig(src_addr, len); + return MXC_AES_RevB_TXDMAConfig(src_addr, len, MXC_DMA); } int MXC_AES_RXDMAConfig(void *dest_addr, int len) { - return MXC_AES_RevB_RXDMAConfig(dest_addr, len); + return MXC_AES_RevB_RXDMAConfig(dest_addr, len, MXC_DMA); } int MXC_AES_GenericAsync(mxc_aes_req_t *req, uint8_t enc) diff --git a/Libraries/PeriphDrivers/Source/AES/aes_me30.c b/Libraries/PeriphDrivers/Source/AES/aes_me30.c index 63603f4cf83..575f8abedf6 100644 --- a/Libraries/PeriphDrivers/Source/AES/aes_me30.c +++ b/Libraries/PeriphDrivers/Source/AES/aes_me30.c @@ -23,19 +23,20 @@ #include "aes_revb.h" #include "trng.h" #include "trng_revb.h" +#include "dma.h" /* ************************************************************************* */ /* Global Control/Configuration functions */ /* ************************************************************************* */ -int MXC_AES_Init(void) +int MXC_AES_Init(mxc_dma_regs_t *dma) { #ifndef MSDK_NO_GPIO_CLK_INIT MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_AES); MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TRNG); #endif - return MXC_AES_RevB_Init((mxc_aes_revb_regs_t *)MXC_AES); + return MXC_AES_RevB_Init((mxc_aes_revb_regs_t *)MXC_AES, dma); } void MXC_AES_EnableInt(uint32_t interrupt) @@ -123,14 +124,14 @@ int MXC_AES_Decrypt(mxc_aes_req_t *req) return MXC_AES_RevB_Decrypt((mxc_aes_revb_regs_t *)MXC_AES, (mxc_aes_revb_req_t *)req); } -int MXC_AES_TXDMAConfig(void *src_addr, int len) +int MXC_AES_TXDMAConfig(void *src_addr, int len, mxc_dma_regs_t *dma) { - return MXC_AES_RevB_TXDMAConfig(src_addr, len); + return MXC_AES_RevB_TXDMAConfig(src_addr, len, dma); } -int MXC_AES_RXDMAConfig(void *dest_addr, int len) +int MXC_AES_RXDMAConfig(void *dest_addr, int len, mxc_dma_regs_t *dma) { - return MXC_AES_RevB_RXDMAConfig(dest_addr, len); + return MXC_AES_RevB_RXDMAConfig(dest_addr, len, dma); } int MXC_AES_GenericAsync(mxc_aes_req_t *req, uint8_t enc) diff --git a/Libraries/PeriphDrivers/Source/AES/aes_revb.c b/Libraries/PeriphDrivers/Source/AES/aes_revb.c index 240b8b6f21a..77ce01370f1 100644 --- a/Libraries/PeriphDrivers/Source/AES/aes_revb.c +++ b/Libraries/PeriphDrivers/Source/AES/aes_revb.c @@ -33,6 +33,7 @@ /* **** Variable Declaration **** */ typedef struct { uint8_t enc; + mxc_dma_regs_t *dma; uint8_t channelRX; uint8_t channelTX; uint32_t remain; @@ -62,7 +63,7 @@ memcpy32r(uint32_t *dst, const uint32_t *src, unsigned int len) } } -int MXC_AES_RevB_Init(mxc_aes_revb_regs_t *aes) +int MXC_AES_RevB_Init(mxc_aes_revb_regs_t *aes, mxc_dma_regs_t *dma) { aes->ctrl = 0x00; @@ -70,6 +71,8 @@ int MXC_AES_RevB_Init(mxc_aes_revb_regs_t *aes) aes->ctrl |= MXC_F_AES_REVB_CTRL_EN; + dma_state.dma = dma; + return E_NO_ERROR; } @@ -226,7 +229,7 @@ int MXC_AES_RevB_Decrypt(mxc_aes_revb_regs_t *aes, mxc_aes_revb_req_t *req) return MXC_AES_RevB_Generic(aes, req); } -int MXC_AES_RevB_TXDMAConfig(void *src_addr, int len) +int MXC_AES_RevB_TXDMAConfig(void *src_addr, int len, mxc_dma_regs_t *dma) { uint8_t channel; mxc_dma_config_t config; @@ -240,9 +243,16 @@ int MXC_AES_RevB_TXDMAConfig(void *src_addr, int len) return E_BAD_PARAM; } +#if (TARGET_NUM == 32657) + MXC_DMA_Init(dma); + + channel = MXC_DMA_AcquireChannel(dma); +#else MXC_DMA_Init(); channel = MXC_DMA_AcquireChannel(); +#endif + dma_state.channelTX = channel; config.reqsel = MXC_DMA_REQUEST_AESTX; @@ -269,7 +279,12 @@ int MXC_AES_RevB_TXDMAConfig(void *src_addr, int len) MXC_DMA_ConfigChannel(config, srcdst); MXC_DMA_SetCallback(channel, MXC_AES_RevB_DMACallback); +#if (TARGET_NUM == 32657) + MXC_DMA_EnableInt(dma, channel); +#else MXC_DMA_EnableInt(channel); +#endif + MXC_DMA_Start(channel); //MXC_DMA->ch[channel].ctrl |= MXC_F_DMA_CTRL_CTZ_IE; MXC_DMA_SetChannelInterruptEn(channel, 0, 1); @@ -277,7 +292,7 @@ int MXC_AES_RevB_TXDMAConfig(void *src_addr, int len) return E_NO_ERROR; } -int MXC_AES_RevB_RXDMAConfig(void *dest_addr, int len) +int MXC_AES_RevB_RXDMAConfig(void *dest_addr, int len, mxc_dma_regs_t *dma) { if (dest_addr == NULL) { return E_NULL_PTR; @@ -291,9 +306,16 @@ int MXC_AES_RevB_RXDMAConfig(void *dest_addr, int len) mxc_dma_config_t config; mxc_dma_srcdst_t srcdst; +#if (TARGET_NUM == 32657) + MXC_DMA_Init(dma); + + channel = MXC_DMA_AcquireChannel(dma); +#else MXC_DMA_Init(); channel = MXC_DMA_AcquireChannel(); +#endif + dma_state.channelRX = channel; config.reqsel = MXC_DMA_REQUEST_AESRX; @@ -320,7 +342,12 @@ int MXC_AES_RevB_RXDMAConfig(void *dest_addr, int len) MXC_DMA_ConfigChannel(config, srcdst); MXC_DMA_SetCallback(channel, MXC_AES_RevB_DMACallback); +#if (TARGET_NUM == 32657) + MXC_DMA_EnableInt(dma, channel); +#else MXC_DMA_EnableInt(channel); +#endif + MXC_DMA_Start(channel); //MXC_DMA->ch[channel].ctrl |= MXC_F_DMA_CTRL_CTZ_IE; MXC_DMA_SetChannelInterruptEn(channel, 0, 1); @@ -359,7 +386,7 @@ int MXC_AES_RevB_GenericAsync(mxc_aes_revb_regs_t *aes, mxc_aes_revb_req_t *req, aes->ctrl |= MXC_F_AES_REVB_CTRL_DMA_RX_EN; //Enable AES DMA aes->ctrl |= MXC_F_AES_REVB_CTRL_DMA_TX_EN; //Enable AES DMA - if (MXC_AES_RevB_TXDMAConfig(dma_state.inputText, dma_state.remain) != E_NO_ERROR) { + if (MXC_AES_RevB_TXDMAConfig(dma_state.inputText, dma_state.remain, dma_state.dma) != E_NO_ERROR) { return E_BAD_PARAM; } @@ -385,7 +412,7 @@ void MXC_AES_RevB_DMACallback(int ch, int error) if (dma_state.remain < 4) { MXC_AES_Start(); } - MXC_AES_RevB_RXDMAConfig(dma_state.outputText, dma_state.remain); + MXC_AES_RevB_RXDMAConfig(dma_state.outputText, dma_state.remain, dma_state.dma); } else if (dma_state.channelRX == ch) { if (dma_state.remain > 4) { dma_state.remain -= 4; @@ -394,7 +421,7 @@ void MXC_AES_RevB_DMACallback(int ch, int error) } MXC_DMA_ReleaseChannel(dma_state.channelRX); if (dma_state.remain > 0) { - MXC_AES_RevB_TXDMAConfig(dma_state.inputText, dma_state.remain); + MXC_AES_RevB_TXDMAConfig(dma_state.inputText, dma_state.remain, dma_state.dma); } } } diff --git a/Libraries/PeriphDrivers/Source/AES/aes_revb.h b/Libraries/PeriphDrivers/Source/AES/aes_revb.h index 3f00bda64c1..0c8b318a7c3 100644 --- a/Libraries/PeriphDrivers/Source/AES/aes_revb.h +++ b/Libraries/PeriphDrivers/Source/AES/aes_revb.h @@ -26,6 +26,7 @@ #include "aes_revb_regs.h" #include "aeskeys_revb_regs.h" #include "trng_revb_regs.h" +#include "dma.h" /** * @brief Enumeration type to select AES key @@ -60,7 +61,7 @@ typedef struct _mxc_aes_revb_cipher_req_t { mxc_aes_complete_t callback; ///< Callback function } mxc_aes_revb_req_t; -int MXC_AES_RevB_Init(mxc_aes_revb_regs_t *aes); +int MXC_AES_RevB_Init(mxc_aes_revb_regs_t *aes, mxc_dma_regs_t *dma); void MXC_AES_RevB_EnableInt(mxc_aes_revb_regs_t *aes, uint32_t interrupt); void MXC_AES_RevB_DisableInt(mxc_aes_revb_regs_t *aes, uint32_t interrupt); int MXC_AES_RevB_IsBusy(mxc_aes_revb_regs_t *aes); @@ -76,8 +77,8 @@ void MXC_AES_RevB_ClearFlags(mxc_aes_revb_regs_t *aes, uint32_t flags); int MXC_AES_RevB_Generic(mxc_aes_revb_regs_t *aes, mxc_aes_revb_req_t *req); int MXC_AES_RevB_Encrypt(mxc_aes_revb_regs_t *aes, mxc_aes_revb_req_t *req); int MXC_AES_RevB_Decrypt(mxc_aes_revb_regs_t *aes, mxc_aes_revb_req_t *req); -int MXC_AES_RevB_TXDMAConfig(void *src_addr, int len); -int MXC_AES_RevB_RXDMAConfig(void *dest_addr, int len); +int MXC_AES_RevB_TXDMAConfig(void *src_addr, int len, mxc_dma_regs_t *dma); +int MXC_AES_RevB_RXDMAConfig(void *dest_addr, int len, mxc_dma_regs_t *dma); int MXC_AES_RevB_GenericAsync(mxc_aes_revb_regs_t *aes, mxc_aes_revb_req_t *req, uint8_t enc); int MXC_AES_RevB_EncryptAsync(mxc_aes_revb_regs_t *aes, mxc_aes_revb_req_t *req); int MXC_AES_RevB_DecryptAsync(mxc_aes_revb_regs_t *aes, mxc_aes_revb_req_t *req); diff --git a/Libraries/PeriphDrivers/Source/CRC/crc_ai87.c b/Libraries/PeriphDrivers/Source/CRC/crc_ai87.c index 8e09e2dc81c..e75000fe5fc 100644 --- a/Libraries/PeriphDrivers/Source/CRC/crc_ai87.c +++ b/Libraries/PeriphDrivers/Source/CRC/crc_ai87.c @@ -36,7 +36,7 @@ int MXC_CRC_Init(void) MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_CRC); #endif - MXC_CRC_RevA_Init((mxc_crc_reva_regs_t *)MXC_CRC); + MXC_CRC_RevA_Init((mxc_crc_reva_regs_t *)MXC_CRC, MXC_DMA); return E_NO_ERROR; } diff --git a/Libraries/PeriphDrivers/Source/CRC/crc_me15.c b/Libraries/PeriphDrivers/Source/CRC/crc_me15.c index 8e09e2dc81c..e75000fe5fc 100644 --- a/Libraries/PeriphDrivers/Source/CRC/crc_me15.c +++ b/Libraries/PeriphDrivers/Source/CRC/crc_me15.c @@ -36,7 +36,7 @@ int MXC_CRC_Init(void) MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_CRC); #endif - MXC_CRC_RevA_Init((mxc_crc_reva_regs_t *)MXC_CRC); + MXC_CRC_RevA_Init((mxc_crc_reva_regs_t *)MXC_CRC, MXC_DMA); return E_NO_ERROR; } diff --git a/Libraries/PeriphDrivers/Source/CRC/crc_me17.c b/Libraries/PeriphDrivers/Source/CRC/crc_me17.c index 8e09e2dc81c..e75000fe5fc 100644 --- a/Libraries/PeriphDrivers/Source/CRC/crc_me17.c +++ b/Libraries/PeriphDrivers/Source/CRC/crc_me17.c @@ -36,7 +36,7 @@ int MXC_CRC_Init(void) MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_CRC); #endif - MXC_CRC_RevA_Init((mxc_crc_reva_regs_t *)MXC_CRC); + MXC_CRC_RevA_Init((mxc_crc_reva_regs_t *)MXC_CRC, MXC_DMA); return E_NO_ERROR; } diff --git a/Libraries/PeriphDrivers/Source/CRC/crc_me30.c b/Libraries/PeriphDrivers/Source/CRC/crc_me30.c index cf4819eb767..1d1bcf41eb9 100644 --- a/Libraries/PeriphDrivers/Source/CRC/crc_me30.c +++ b/Libraries/PeriphDrivers/Source/CRC/crc_me30.c @@ -23,18 +23,19 @@ #include "crc.h" #include "crc_reva.h" +#include "dma.h" /* ************************************************************************* */ /* Global Control/Configuration functions */ /* ************************************************************************* */ -int MXC_CRC_Init(void) +int MXC_CRC_Init(mxc_dma_regs_t *dma) { #ifndef MSDK_NO_GPIO_CLK_INIT MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_CRC); #endif - MXC_CRC_RevA_Init((mxc_crc_reva_regs_t *)MXC_CRC); + MXC_CRC_RevA_Init((mxc_crc_reva_regs_t *)MXC_CRC, dma); return E_NO_ERROR; } diff --git a/Libraries/PeriphDrivers/Source/CRC/crc_reva.c b/Libraries/PeriphDrivers/Source/CRC/crc_reva.c index 4cdb5e5ebb3..a84b553ab89 100644 --- a/Libraries/PeriphDrivers/Source/CRC/crc_reva.c +++ b/Libraries/PeriphDrivers/Source/CRC/crc_reva.c @@ -33,13 +33,16 @@ /***** Global Variables *****/ static mxc_crc_reva_req_t *CRCreq; +static mxc_dma_regs_t *CRCdma; /* ************************************************************************* */ /* Global Control/Configuration functions */ /* ************************************************************************* */ -int MXC_CRC_RevA_Init(mxc_crc_reva_regs_t *crc) +int MXC_CRC_RevA_Init(mxc_crc_reva_regs_t *crc, mxc_dma_regs_t *dma) { + CRCdma = dma; + crc->ctrl = 0x00; crc->val = 0xFFFFFFFF; return E_NO_ERROR; @@ -160,9 +163,15 @@ int MXC_CRC_RevA_ComputeAsync(mxc_crc_reva_regs_t *crc, mxc_crc_reva_req_t *req) CRCreq = req; +#if (TARGET_NUM == 32657) + MXC_DMA_Init(CRCdma); + + channel = MXC_DMA_AcquireChannel(CRCdma); +#else MXC_DMA_Init(); channel = MXC_DMA_AcquireChannel(); +#endif config.reqsel = MXC_DMA_REQUEST_CRCTX; @@ -183,7 +192,13 @@ int MXC_CRC_RevA_ComputeAsync(mxc_crc_reva_regs_t *crc, mxc_crc_reva_req_t *req) MXC_DMA_ConfigChannel(config, srcdst); MXC_DMA_SetCallback(channel, MXC_CRC_Handler); + +#if (TARGET_NUM == 32657) + MXC_DMA_EnableInt(CRCdma, channel); +#else MXC_DMA_EnableInt(channel); +#endif + MXC_DMA_Start(channel); //MXC_DMA->ch[channel].ctrl |= MXC_F_DMA_CTRL_CTZ_IE; MXC_DMA_SetChannelInterruptEn(channel, 0, 1); diff --git a/Libraries/PeriphDrivers/Source/CRC/crc_reva.h b/Libraries/PeriphDrivers/Source/CRC/crc_reva.h index d4a06efee33..8e2c46f9b34 100644 --- a/Libraries/PeriphDrivers/Source/CRC/crc_reva.h +++ b/Libraries/PeriphDrivers/Source/CRC/crc_reva.h @@ -23,6 +23,7 @@ #include "crc.h" #include "crc_reva_regs.h" +#include "dma.h" /***** CRC Definitions *****/ /** @@ -41,7 +42,7 @@ typedef struct _mxc_crc_reva_req_t { */ typedef enum { CRC_REVA_LSB_FIRST, CRC_REVA_MSB_FIRST } mxc_crc_reva_bitorder_t; -int MXC_CRC_RevA_Init(mxc_crc_reva_regs_t *crc); +int MXC_CRC_RevA_Init(mxc_crc_reva_regs_t *crc, mxc_dma_regs_t *dma); int MXC_CRC_RevA_Shutdown(mxc_crc_reva_regs_t *crc); int MXC_CRC_RevA_Handler(int ch, int error); void MXC_CRC_RevA_SetDirection(mxc_crc_reva_regs_t *crc, mxc_crc_reva_bitorder_t bitOrder); diff --git a/Libraries/PeriphDrivers/Source/DMA/dma_me30.c b/Libraries/PeriphDrivers/Source/DMA/dma_me30.c index bab48e3c5e9..d0359eaa1da 100644 --- a/Libraries/PeriphDrivers/Source/DMA/dma_me30.c +++ b/Libraries/PeriphDrivers/Source/DMA/dma_me30.c @@ -32,31 +32,33 @@ /****** Functions ******/ -int MXC_DMA_Init(void) +int MXC_DMA_Init(mxc_dma_regs_t *dma) { #ifndef MSDK_NO_GPIO_CLK_INIT - if (MXC_DMA == MXC_DMA0 && !MXC_SYS_IsClockEnabled(MXC_SYS_PERIPH_CLOCK_DMA0)) { + if (dma == MXC_DMA0 && !MXC_SYS_IsClockEnabled(MXC_SYS_PERIPH_CLOCK_DMA0)) { MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_DMA0); MXC_SYS_Reset_Periph(MXC_SYS_RESET0_DMA0); } // TODO(ME30): There is no periph clock enable register for DMA1 atm - // else if (MXC_DMA == MXC_DMA1 && !MXC_SYS_IsClockEnabled(MXC_SYS_PERIPH_CLOCK_DMA1)) + // -Added but it's in feat/ME30 branch. + // Uncomment when merged. + // else if (dma == MXC_DMA1 && !MXC_SYS_IsClockEnabled(MXC_SYS_PERIPH_CLOCK_DMA1)) // MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_DMA1); // MXC_SYS_Reset_Periph(MXC_SYS_RESET0_DMA1); // } #endif - return MXC_DMA_RevA_Init((mxc_dma_reva_regs_t *)MXC_DMA); + return MXC_DMA_RevA_Init((mxc_dma_reva_regs_t *)dma); } -void MXC_DMA_DeInit(void) +void MXC_DMA_DeInit(mxc_dma_regs_t *dma) { - return MXC_DMA_RevA_DeInit((mxc_dma_reva_regs_t *)MXC_DMA); + return MXC_DMA_RevA_DeInit((mxc_dma_reva_regs_t *)dma); } -int MXC_DMA_AcquireChannel(void) +int MXC_DMA_AcquireChannel(mxc_dma_regs_t *dma) { - return MXC_DMA_RevA_AcquireChannel((mxc_dma_reva_regs_t *)MXC_DMA); + return MXC_DMA_RevA_AcquireChannel((mxc_dma_reva_regs_t *)dma); } int MXC_DMA_ReleaseChannel(int ch) @@ -124,14 +126,15 @@ int MXC_DMA_ChannelClearFlags(int ch, int flags) return MXC_DMA_RevA_ChannelClearFlags(ch, flags); } -int MXC_DMA_EnableInt(int ch) +// TODO(DMA): Check ME14 becasue you can only get ME14 intrs from MXC_DMA0. +int MXC_DMA_EnableInt(mxc_dma_regs_t *dma, int ch) { - return MXC_DMA_RevA_EnableInt((mxc_dma_reva_regs_t *)MXC_DMA, ch); + return MXC_DMA_RevA_EnableInt((mxc_dma_reva_regs_t *)dma, ch); } -int MXC_DMA_DisableInt(int ch) +int MXC_DMA_DisableInt(mxc_dma_regs_t *dma, int ch) { - return MXC_DMA_RevA_DisableInt((mxc_dma_reva_regs_t *)MXC_DMA, ch); + return MXC_DMA_RevA_DisableInt((mxc_dma_reva_regs_t *)dma, ch); } int MXC_DMA_Start(int ch) @@ -149,18 +152,18 @@ mxc_dma_ch_regs_t *MXC_DMA_GetCHRegs(int ch) return MXC_DMA_RevA_GetCHRegs(ch); } -void MXC_DMA_Handler(void) +void MXC_DMA_Handler(mxc_dma_regs_t *dma) { - MXC_DMA_RevA_Handler((mxc_dma_reva_regs_t *)MXC_DMA); + MXC_DMA_RevA_Handler((mxc_dma_reva_regs_t *)dma); } -int MXC_DMA_MemCpy(void *dest, void *src, int len, mxc_dma_complete_cb_t callback) +int MXC_DMA_MemCpy(mxc_dma_regs_t *dma, void *dest, void *src, int len, mxc_dma_complete_cb_t callback) { - return MXC_DMA_RevA_MemCpy((mxc_dma_reva_regs_t *)MXC_DMA, dest, src, len, callback); + return MXC_DMA_RevA_MemCpy((mxc_dma_reva_regs_t *)dma, dest, src, len, callback); } -int MXC_DMA_DoTransfer(mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, +int MXC_DMA_DoTransfer(mxc_dma_regs_t *dma, mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, mxc_dma_trans_chain_t callback) { - return MXC_DMA_RevA_DoTransfer((mxc_dma_reva_regs_t *)MXC_DMA, config, firstSrcDst, callback); + return MXC_DMA_RevA_DoTransfer((mxc_dma_reva_regs_t *)dma, config, firstSrcDst, callback); } diff --git a/Libraries/PeriphDrivers/Source/DMA/dma_reva.c b/Libraries/PeriphDrivers/Source/DMA/dma_reva.c index 6b8ac9a8436..05ba7bbbf89 100644 --- a/Libraries/PeriphDrivers/Source/DMA/dma_reva.c +++ b/Libraries/PeriphDrivers/Source/DMA/dma_reva.c @@ -470,7 +470,7 @@ int MXC_DMA_RevA_MemCpy(mxc_dma_reva_regs_t *dma, void *dest, void *src, int len mxc_dma_srcdst_t transfer; int channel; -#if TARGET_NUM == 32665 +#if (TARGET_NUM == 32665 || TARGET_NUM == 32657) channel = MXC_DMA_AcquireChannel((mxc_dma_regs_t *)dma); #else channel = MXC_DMA_AcquireChannel(); @@ -500,7 +500,11 @@ int MXC_DMA_RevA_MemCpy(mxc_dma_reva_regs_t *dma, void *dest, void *src, int len return retval; } +#if (TARGET_NUM == 32657) + retval = MXC_DMA_EnableInt((mxc_dma_regs_t *)dma, channel); +#else retval = MXC_DMA_EnableInt(channel); +#endif if (retval != E_NO_ERROR) { return retval; @@ -535,7 +539,7 @@ int MXC_DMA_RevA_DoTransfer(mxc_dma_reva_regs_t *dma, mxc_dma_config_t config, { int retval, channel; -#if TARGET_NUM == 32665 +#if (TARGET_NUM == 32665 || TARGET_NUM == 32657) channel = MXC_DMA_AcquireChannel((mxc_dma_regs_t *)dma); #else channel = MXC_DMA_AcquireChannel(); @@ -553,7 +557,11 @@ int MXC_DMA_RevA_DoTransfer(mxc_dma_reva_regs_t *dma, mxc_dma_config_t config, return retval; } +#if (TARGET_NUM == 32657) + retval = MXC_DMA_EnableInt((mxc_dma_regs_t *)dma, channel); +#else retval = MXC_DMA_EnableInt(channel); +#endif if (retval != E_NO_ERROR) { return retval; diff --git a/Libraries/PeriphDrivers/Source/SPI/spi_me30.c b/Libraries/PeriphDrivers/Source/SPI/spi_me30.c index b2e419561d2..3d75b2bcd37 100644 --- a/Libraries/PeriphDrivers/Source/SPI/spi_me30.c +++ b/Libraries/PeriphDrivers/Source/SPI/spi_me30.c @@ -337,7 +337,7 @@ int MXC_SPI_MasterTransactionAsync(mxc_spi_req_t *req) return MXC_SPI_RevA1_MasterTransactionAsync((mxc_spi_reva_req_t *)req); } -int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t *req) +int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t *req, mxc_dma_regs_t *dma) { int reqselTx = -1; int reqselRx = -1; @@ -377,8 +377,7 @@ int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t *req) } } - return MXC_SPI_RevA1_MasterTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx, - MXC_DMA); + return MXC_SPI_RevA1_MasterTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx, dma); } int MXC_SPI_SlaveTransaction(mxc_spi_req_t *req) @@ -391,7 +390,7 @@ int MXC_SPI_SlaveTransactionAsync(mxc_spi_req_t *req) return MXC_SPI_RevA1_SlaveTransactionAsync((mxc_spi_reva_req_t *)req); } -int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t *req) +int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t *req, mxc_dma_regs_t *dma) { int reqselTx = -1; int reqselRx = -1; @@ -433,8 +432,7 @@ int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t *req) } } - return MXC_SPI_RevA1_SlaveTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx, - MXC_DMA); + return MXC_SPI_RevA1_SlaveTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx, dma); } int MXC_SPI_SetDefaultTXData(mxc_spi_regs_t *spi, unsigned int defaultTXData) diff --git a/Libraries/PeriphDrivers/Source/SPI/spi_reva1.c b/Libraries/PeriphDrivers/Source/SPI/spi_reva1.c index 4c7fd64e6dc..74b8871e5f3 100644 --- a/Libraries/PeriphDrivers/Source/SPI/spi_reva1.c +++ b/Libraries/PeriphDrivers/Source/SPI/spi_reva1.c @@ -952,7 +952,7 @@ int MXC_SPI_RevA1_MasterTransactionDMA(mxc_spi_reva_req_t *req, int reqselTx, in // for non-MT mode do this setup every time, for MT mode only first time if ((states[spi_num].mtMode == 0) || ((states[spi_num].mtMode == 1) && (states[spi_num].mtFirstTrans == 1))) { -#if TARGET_NUM == 32665 +#if (TARGET_NUM == 32665 || TARGET_NUM == 32657) MXC_DMA_Init(dma); states[spi_num].channelTx = MXC_DMA_AcquireChannel(dma); states[spi_num].channelRx = MXC_DMA_AcquireChannel(dma); @@ -1009,7 +1009,13 @@ int MXC_SPI_RevA1_MasterTransactionDMA(mxc_spi_reva_req_t *req, int reqselTx, in //tx if (req->txData != NULL && !tx_is_complete) { MXC_DMA_SetCallback(states[spi_num].channelTx, MXC_SPI_RevA1_DMACallback); + +#if (TARGET_NUM == 32657) + MXC_DMA_EnableInt(dma, states[spi_num].channelTx); +#else MXC_DMA_EnableInt(states[spi_num].channelTx); +#endif + config.reqsel = (mxc_dma_reqsel_t)reqselTx; config.ch = states[spi_num].channelTx; advConfig.ch = states[spi_num].channelTx; @@ -1049,7 +1055,13 @@ int MXC_SPI_RevA1_MasterTransactionDMA(mxc_spi_reva_req_t *req, int reqselTx, in // rx if (req->rxData != NULL && !rx_is_complete) { MXC_DMA_SetCallback(states[spi_num].channelRx, MXC_SPI_RevA1_DMACallback); + +#if (TARGET_NUM == 32657) + MXC_DMA_EnableInt(dma, states[spi_num].channelRx); +#else MXC_DMA_EnableInt(states[spi_num].channelRx); +#endif + config.reqsel = (mxc_dma_reqsel_t)reqselRx; config.ch = states[spi_num].channelRx; config.srcinc_en = 0; @@ -1160,7 +1172,7 @@ int MXC_SPI_RevA1_SlaveTransactionDMA(mxc_spi_reva_req_t *req, int reqselTx, int // for non-MT mode do this setup every time, for MT mode only first time if ((states[spi_num].mtMode == 0) || ((states[spi_num].mtMode == 1) && (states[spi_num].mtFirstTrans == 1))) { -#if TARGET_NUM == 32665 +#if (TARGET_NUM == 32665 || TARGET_NUM == 32657) MXC_DMA_Init(dma); states[spi_num].channelTx = MXC_DMA_AcquireChannel(dma); states[spi_num].channelRx = MXC_DMA_AcquireChannel(dma); @@ -1180,8 +1192,14 @@ int MXC_SPI_RevA1_SlaveTransactionDMA(mxc_spi_reva_req_t *req, int reqselTx, int MXC_DMA_SetCallback(states[spi_num].channelTx, MXC_SPI_RevA1_DMACallback); MXC_DMA_SetCallback(states[spi_num].channelRx, MXC_SPI_RevA1_DMACallback); + +#if (TARGET_NUM == 32657) + MXC_DMA_EnableInt(dma, states[spi_num].channelTx); + MXC_DMA_EnableInt(dma, states[spi_num].channelRx); +#else MXC_DMA_EnableInt(states[spi_num].channelTx); MXC_DMA_EnableInt(states[spi_num].channelRx); +#endif } bits = MXC_SPI_GetDataSize((mxc_spi_regs_t *)req->spi); diff --git a/Libraries/PeriphDrivers/Source/SYS/sys_me30.c b/Libraries/PeriphDrivers/Source/SYS/sys_me30.c index e03cd7c5cfd..78e09ee40bc 100644 --- a/Libraries/PeriphDrivers/Source/SYS/sys_me30.c +++ b/Libraries/PeriphDrivers/Source/SYS/sys_me30.c @@ -93,7 +93,10 @@ int MXC_SYS_GetUSN(uint8_t *usn, uint8_t *checksum) checksum[0] = ((infoblock[3] & 0x7F800000) >> 23); checksum[1] = ((infoblock[4] & 0x007F8000) >> 15); - err = MXC_AES_Init(); + // Info block only accessible for secure code. + // Use Secure DMA1. + // TODO(DMA): Figure out access to "secure" functions when in non-secure code. + err = MXC_AES_Init(MXC_DMA1); if (err) { MXC_FLC_LockInfoBlock(MXC_INFO_MEM_BASE); return err; diff --git a/Libraries/PeriphDrivers/Source/UART/uart_me30.c b/Libraries/PeriphDrivers/Source/UART/uart_me30.c index 83eb8202790..303d21c973a 100644 --- a/Libraries/PeriphDrivers/Source/UART/uart_me30.c +++ b/Libraries/PeriphDrivers/Source/UART/uart_me30.c @@ -182,13 +182,13 @@ unsigned int MXC_UART_ReadRXFIFO(mxc_uart_regs_t *uart, unsigned char *bytes, un return MXC_UART_RevA_ReadRXFIFO((mxc_uart_reva_regs_t *)uart, bytes, len); } -int MXC_UART_ReadRXFIFODMA(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned int len, +int MXC_UART_ReadRXFIFODMA(mxc_uart_regs_t *uart, mxc_dma_regs_t *dma, unsigned char *bytes, unsigned int len, mxc_uart_dma_complete_cb_t callback) { mxc_dma_config_t config; config.reqsel = MXC_DMA_REQUEST_UART0RX; // TODO(ME30): Updated DMA reqsel - return MXC_UART_RevA_ReadRXFIFODMA((mxc_uart_reva_regs_t *)uart, MXC_DMA, bytes, len, callback, + return MXC_UART_RevA_ReadRXFIFODMA((mxc_uart_reva_regs_t *)uart, dma, bytes, len, callback, config); } @@ -202,13 +202,13 @@ unsigned int MXC_UART_WriteTXFIFO(mxc_uart_regs_t *uart, unsigned char *bytes, u return MXC_UART_RevA_WriteTXFIFO((mxc_uart_reva_regs_t *)uart, bytes, len); } -int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned int len, +int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t *uart, mxc_dma_regs_t *dma, unsigned char *bytes, unsigned int len, mxc_uart_dma_complete_cb_t callback) { mxc_dma_config_t config; config.reqsel = MXC_DMA_REQUEST_UART0TX; // TODO(ME30): Updated DMA reqsel - return MXC_UART_RevA_WriteTXFIFODMA((mxc_uart_reva_regs_t *)uart, MXC_DMA, bytes, len, callback, + return MXC_UART_RevA_WriteTXFIFODMA((mxc_uart_reva_regs_t *)uart, dma, bytes, len, callback, config); } @@ -282,9 +282,9 @@ int MXC_UART_TransactionAsync(mxc_uart_req_t *req) return MXC_UART_RevA_TransactionAsync((mxc_uart_reva_req_t *)req); } -int MXC_UART_TransactionDMA(mxc_uart_req_t *req) +int MXC_UART_TransactionDMA(mxc_uart_req_t *req, mxc_dma_regs_t *dma) { - return MXC_UART_RevA_TransactionDMA((mxc_uart_reva_req_t *)req, MXC_DMA); + return MXC_UART_RevA_TransactionDMA((mxc_uart_reva_req_t *)req, dma); } int MXC_UART_AbortAsync(mxc_uart_regs_t *uart) diff --git a/Libraries/PeriphDrivers/Source/UART/uart_reva.c b/Libraries/PeriphDrivers/Source/UART/uart_reva.c index 2256afe35a1..5ba07b5c3e4 100644 --- a/Libraries/PeriphDrivers/Source/UART/uart_reva.c +++ b/Libraries/PeriphDrivers/Source/UART/uart_reva.c @@ -48,6 +48,7 @@ typedef struct { int channelTx; int channelRx; bool auto_dma_handlers; + mxc_dma_regs_t *dma; } uart_reva_req_state_t; uart_reva_req_state_t states[MXC_UART_INSTANCES]; @@ -99,6 +100,7 @@ int MXC_UART_RevA_Init(mxc_uart_reva_regs_t *uart, unsigned int baud) states[i].tx_req = NULL; states[i].rx_req = NULL; states[i].auto_dma_handlers = false; + states[i].dma = NULL; return E_NO_ERROR; } @@ -502,7 +504,13 @@ unsigned int MXC_UART_RevA_ReadRXFIFO(mxc_uart_reva_regs_t *uart, unsigned char return read; } -#if MXC_DMA_INSTANCES > 1 + +// TODO(DMA): Replaced the DMA instance number check to the only +// parts affected by this. Our DMA drivers probably +// needs a rework to handle multiple instances because +// the ME14's DMA drivers are very limited with +// the DMA instance selection. +#if (TARGET_NUM == 32665 || TARGET_NUM == 32657) void MXC_UART_RevA_DMA0_Handler(void) { @@ -522,19 +530,21 @@ DMA instance. void MXC_UART_RevA_DMA_SetupAutoHandlers(mxc_dma_regs_t *dma_instance, unsigned int channel) { #ifdef __arm__ - NVIC_EnableIRQ(MXC_DMA_CH_GET_IRQ(channel)); +#if (TARGET_NUM == 32665 || TARGET_NUM == 32657) + NVIC_EnableIRQ(MXC_DMA_CH_GET_IRQ(dma_instance, channel)); -#if MXC_DMA_INSTANCES > 1 /* (JC): This is not the cleanest or most scalable way to do this, but I tried defining default handler's in the system file. Some complications make this the most attractive short-term option. We could handle multiple DMA instances better in the DMA API (See the mismatch between the size of "dma_resource" array and the number of channels per instance, to start)*/ if (dma_instance == MXC_DMA0) { - MXC_NVIC_SetVector(MXC_DMA_CH_GET_IRQ(channel), MXC_UART_RevA_DMA0_Handler); + MXC_NVIC_SetVector(MXC_DMA_CH_GET_IRQ(dma_instance, channel), MXC_UART_RevA_DMA0_Handler); } else if (dma_instance == MXC_DMA1) { - MXC_NVIC_SetVector(MXC_DMA_CH_GET_IRQ(channel), MXC_UART_RevA_DMA1_Handler); + MXC_NVIC_SetVector(MXC_DMA_CH_GET_IRQ(dma_instance, channel), MXC_UART_RevA_DMA1_Handler); } #else + NVIC_EnableIRQ(MXC_DMA_CH_GET_IRQ(channel)); + // Only one DMA instance, we can point direct to MXC_DMA_Handler MXC_NVIC_SetVector(MXC_DMA_CH_GET_IRQ(channel), MXC_DMA_Handler); #endif // MXC_DMA_INSTANCES > 1 @@ -560,7 +570,7 @@ int MXC_UART_RevA_ReadRXFIFODMA(mxc_uart_reva_regs_t *uart, mxc_dma_regs_t *dma, if (states[uart_num].auto_dma_handlers && states[uart_num].channelRx < 0) { /* Acquire channel if we don't have one already */ -#if MXC_DMA_INSTANCES > 1 +#if MXC_DMA_INSTANCES > 1 || TARGET_NUM == 32657 channel = MXC_DMA_AcquireChannel(dma); #else channel = MXC_DMA_AcquireChannel(); @@ -591,7 +601,13 @@ int MXC_UART_RevA_ReadRXFIFODMA(mxc_uart_reva_regs_t *uart, mxc_dma_regs_t *dma, MXC_DMA_ConfigChannel(config, srcdst); MXC_DMA_SetCallback(channel, MXC_UART_DMACallback); + +#if (TARGET_NUM == 32657) + MXC_DMA_EnableInt(dma, channel); +#else MXC_DMA_EnableInt(channel); +#endif + MXC_DMA_Start(channel); //MXC_DMA->ch[channel].ctrl |= MXC_F_DMA_CTRL_CTZ_IE; MXC_DMA_SetChannelInterruptEn(channel, 0, 1); @@ -679,7 +695,7 @@ unsigned int MXC_UART_RevA_WriteTXFIFODMA(mxc_uart_reva_regs_t *uart, mxc_dma_re if (states[uart_num].auto_dma_handlers && states[uart_num].channelTx < 0) { /* Acquire channel if we don't have one already */ -#if TARGET_NUM == 32665 +#if (TARGET_NUM == 32665 || TARGET_NUM == 32657) channel = MXC_DMA_AcquireChannel(dma); #else channel = MXC_DMA_AcquireChannel(); @@ -708,7 +724,13 @@ unsigned int MXC_UART_RevA_WriteTXFIFODMA(mxc_uart_reva_regs_t *uart, mxc_dma_re MXC_DMA_ConfigChannel(config, srcdst); MXC_DMA_SetCallback(channel, MXC_UART_DMACallback); + +#if (TARGET_NUM == 32657) + MXC_DMA_EnableInt(dma, channel); +#else MXC_DMA_EnableInt(channel); +#endif + MXC_DMA_Start(channel); //MXC_DMA->ch[channel].ctrl |= MXC_F_DMA_CTRL_CTZ_IE; MXC_DMA_SetChannelInterruptEn(channel, 0, 1); @@ -951,6 +973,9 @@ int MXC_UART_RevA_TransactionDMA(mxc_uart_reva_req_t *req, mxc_dma_regs_t *dma) { int uart_num = MXC_UART_GET_IDX((mxc_uart_regs_t *)(req->uart)); + // Save DMA instance for DMA Callback. + states[uart_num].dma = dma; + if (req->txLen) { if (req->txData == NULL) { return E_BAD_PARAM; @@ -976,7 +1001,7 @@ int MXC_UART_RevA_TransactionDMA(mxc_uart_reva_req_t *req, mxc_dma_regs_t *dma) (req->uart)->dma |= (2 << MXC_F_UART_REVA_DMA_TXDMA_LEVEL_POS); // Set TX DMA threshold to 2 bytes -#if TARGET_NUM == 32665 +#if (TARGET_NUM == 32665 || TARGET_NUM == 32657) MXC_DMA_Init(dma); #else MXC_DMA_Init(); @@ -990,7 +1015,7 @@ int MXC_UART_RevA_TransactionDMA(mxc_uart_reva_req_t *req, mxc_dma_regs_t *dma) if ((req->txData != NULL) && (req->txLen)) { /* Save TX req, the DMA handler will use this later. */ states[uart_num].tx_req = req; -#if TARGET_NUM == 32665 +#if (TARGET_NUM == 32665 || TARGET_NUM == 32657) if (MXC_UART_WriteTXFIFODMA((mxc_uart_regs_t *)(req->uart), dma, req->txData, req->txLen, NULL) != E_NO_ERROR) { return E_BAD_PARAM; @@ -1005,7 +1030,7 @@ int MXC_UART_RevA_TransactionDMA(mxc_uart_reva_req_t *req, mxc_dma_regs_t *dma) if ((req->rxData != NULL) && (req->rxLen)) { states[uart_num].rx_req = req; -#if TARGET_NUM == 32665 +#if (TARGET_NUM == 32665 || TARGET_NUM == 32657) if (MXC_UART_ReadRXFIFODMA((mxc_uart_regs_t *)(req->uart), dma, req->rxData, req->rxLen, NULL) != E_NO_ERROR) { return E_BAD_PARAM; @@ -1029,7 +1054,7 @@ void MXC_UART_RevA_DMACallback(int ch, int error) if (states[i].channelTx == ch) { /* Populate txLen. The number of "remainder" bytes is what's left on the DMA channel's count register. */ - states[i].tx_req->txCnt = states[i].tx_req->txLen - MXC_DMA->ch[ch].cnt; + states[i].tx_req->txCnt = states[i].tx_req->txLen - states[i].dma->ch[ch].cnt; temp_req = states[i].tx_req; @@ -1051,7 +1076,7 @@ void MXC_UART_RevA_DMACallback(int ch, int error) break; } else if (states[i].channelRx == ch) { /* Same as above, but for RX */ - states[i].rx_req->rxCnt = states[i].rx_req->rxLen - MXC_DMA->ch[ch].cnt; + states[i].rx_req->rxCnt = states[i].rx_req->rxLen - states[i].dma->ch[ch].cnt; temp_req = states[i].rx_req; if (states[i].auto_dma_handlers) { MXC_DMA_ReleaseChannel(ch);